1//===-- VEMCCodeEmitter.cpp - Convert VE code to machine code -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the VEMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/VEFixupKinds.h"
14#include "VE.h"
15#include "VEMCAsmInfo.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCCodeEmitter.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCFixup.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/MC/MCSymbol.h"
27#include "llvm/Support/EndianStream.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "mccodeemitter"
35
36STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
37
38namespace {
39
40class VEMCCodeEmitter : public MCCodeEmitter {
41 MCContext &Ctx;
42
43public:
44 VEMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
45 : Ctx(ctx) {}
46 VEMCCodeEmitter(const VEMCCodeEmitter &) = delete;
47 VEMCCodeEmitter &operator=(const VEMCCodeEmitter &) = delete;
48 ~VEMCCodeEmitter() override = default;
49
50 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
51 SmallVectorImpl<MCFixup> &Fixups,
52 const MCSubtargetInfo &STI) const override;
53
54 // getBinaryCodeForInstr - TableGen'erated function for getting the
55 // binary encoding for an instruction.
56 uint64_t getBinaryCodeForInstr(const MCInst &MI,
57 SmallVectorImpl<MCFixup> &Fixups,
58 const MCSubtargetInfo &STI) const;
59
60 /// getMachineOpValue - Return binary encoding of operand. If the machine
61 /// operand requires relocation, record the relocation and return zero.
62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
65
66 uint64_t getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
69 uint64_t getCCOpValue(const MCInst &MI, unsigned OpNo,
70 SmallVectorImpl<MCFixup> &Fixups,
71 const MCSubtargetInfo &STI) const;
72 uint64_t getRDOpValue(const MCInst &MI, unsigned OpNo,
73 SmallVectorImpl<MCFixup> &Fixups,
74 const MCSubtargetInfo &STI) const;
75};
76
77} // end anonymous namespace
78
79void VEMCCodeEmitter::encodeInstruction(const MCInst &MI,
80 SmallVectorImpl<char> &CB,
81 SmallVectorImpl<MCFixup> &Fixups,
82 const MCSubtargetInfo &STI) const {
83 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
84 support::endian::write<uint64_t>(Out&: CB, V: Bits, E: llvm::endianness::little);
85
86 ++MCNumEmitted; // Keep track of the # of mi's emitted.
87}
88
89unsigned VEMCCodeEmitter::getMachineOpValue(const MCInst &MI,
90 const MCOperand &MO,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const {
93 if (MO.isReg())
94 return Ctx.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
95 if (MO.isImm())
96 return static_cast<unsigned>(MO.getImm());
97
98 assert(MO.isExpr());
99
100 const MCExpr *Expr = MO.getExpr();
101 if (const auto *SExpr = dyn_cast<MCSpecifierExpr>(Val: Expr)) {
102 auto Kind = VE::getFixupKind(S: SExpr->getSpecifier());
103 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind));
104 return 0;
105 }
106
107 int64_t Res;
108 if (Expr->evaluateAsAbsolute(Res))
109 return Res;
110
111 llvm_unreachable("Unhandled expression!");
112 return 0;
113}
114
115uint64_t
116VEMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
117 SmallVectorImpl<MCFixup> &Fixups,
118 const MCSubtargetInfo &STI) const {
119 const MCOperand &MO = MI.getOperand(i: OpNo);
120 if (MO.isReg() || MO.isImm())
121 return getMachineOpValue(MI, MO, Fixups, STI);
122
123 Fixups.push_back(
124 Elt: MCFixup::create(Offset: 0, Value: MO.getExpr(), Kind: (MCFixupKind)VE::fixup_ve_srel32));
125 return 0;
126}
127
128uint64_t VEMCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned OpNo,
129 SmallVectorImpl<MCFixup> &Fixups,
130 const MCSubtargetInfo &STI) const {
131 const MCOperand &MO = MI.getOperand(i: OpNo);
132 if (MO.isImm())
133 return VECondCodeToVal(
134 CC: static_cast<VECC::CondCode>(getMachineOpValue(MI, MO, Fixups, STI)));
135 return 0;
136}
137
138uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
139 SmallVectorImpl<MCFixup> &Fixups,
140 const MCSubtargetInfo &STI) const {
141 const MCOperand &MO = MI.getOperand(i: OpNo);
142 if (MO.isImm())
143 return VERDToVal(R: static_cast<VERD::RoundingMode>(
144 getMachineOpValue(MI, MO, Fixups, STI)));
145 return 0;
146}
147
148#include "VEGenMCCodeEmitter.inc"
149
150MCCodeEmitter *llvm::createVEMCCodeEmitter(const MCInstrInfo &MCII,
151 MCContext &Ctx) {
152 return new VEMCCodeEmitter(MCII, Ctx);
153}
154