| 1 | //===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax ----===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This class prints an XCore MCInst to a .s file. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #include "XCoreInstPrinter.h" |
| 14 | #include "llvm/ADT/StringRef.h" |
| 15 | #include "llvm/MC/MCExpr.h" |
| 16 | #include "llvm/MC/MCInst.h" |
| 17 | #include "llvm/MC/MCRegister.h" |
| 18 | #include "llvm/MC/MCSymbol.h" |
| 19 | #include "llvm/Support/Casting.h" |
| 20 | #include "llvm/Support/ErrorHandling.h" |
| 21 | #include "llvm/Support/raw_ostream.h" |
| 22 | #include <cassert> |
| 23 | |
| 24 | using namespace llvm; |
| 25 | |
| 26 | #define DEBUG_TYPE "asm-printer" |
| 27 | |
| 28 | #include "XCoreGenAsmWriter.inc" |
| 29 | |
| 30 | void XCoreInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { |
| 31 | OS << StringRef(getRegisterName(Reg)).lower(); |
| 32 | } |
| 33 | |
| 34 | void XCoreInstPrinter::printInst(const MCInst *MI, uint64_t Address, |
| 35 | StringRef Annot, const MCSubtargetInfo &STI, |
| 36 | raw_ostream &O) { |
| 37 | printInstruction(MI, Address, O); |
| 38 | printAnnotation(OS&: O, Annot); |
| 39 | } |
| 40 | |
| 41 | void XCoreInstPrinter:: |
| 42 | printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) { |
| 43 | report_fatal_error(reason: "can't handle InlineJT" ); |
| 44 | } |
| 45 | |
| 46 | void XCoreInstPrinter:: |
| 47 | printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) { |
| 48 | report_fatal_error(reason: "can't handle InlineJT32" ); |
| 49 | } |
| 50 | |
| 51 | static void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI, |
| 52 | raw_ostream &OS) { |
| 53 | int Offset = 0; |
| 54 | const MCSymbolRefExpr *SRE; |
| 55 | |
| 56 | if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Val: Expr)) { |
| 57 | SRE = dyn_cast<MCSymbolRefExpr>(Val: BE->getLHS()); |
| 58 | const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val: BE->getRHS()); |
| 59 | assert(SRE && CE && "Binary expression must be sym+const." ); |
| 60 | Offset = CE->getValue(); |
| 61 | } else { |
| 62 | SRE = dyn_cast<MCSymbolRefExpr>(Val: Expr); |
| 63 | assert(SRE && "Unexpected MCExpr type." ); |
| 64 | } |
| 65 | assert(SRE->getSpecifier() == 0); |
| 66 | |
| 67 | SRE->getSymbol().print(OS, MAI); |
| 68 | |
| 69 | if (Offset) { |
| 70 | if (Offset > 0) |
| 71 | OS << '+'; |
| 72 | OS << Offset; |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | void XCoreInstPrinter:: |
| 77 | printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { |
| 78 | const MCOperand &Op = MI->getOperand(i: OpNo); |
| 79 | if (Op.isReg()) { |
| 80 | printRegName(OS&: O, Reg: Op.getReg()); |
| 81 | return; |
| 82 | } |
| 83 | |
| 84 | if (Op.isImm()) { |
| 85 | O << Op.getImm(); |
| 86 | return; |
| 87 | } |
| 88 | |
| 89 | assert(Op.isExpr() && "unknown operand kind in printOperand" ); |
| 90 | printExpr(Expr: Op.getExpr(), MAI: &MAI, OS&: O); |
| 91 | } |
| 92 | |