1//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise ARM hardware features
10// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/TargetParser/ARMTargetParser.h"
15#include "llvm/ADT/StringSwitch.h"
16#include "llvm/Support/Format.h"
17#include "llvm/Support/raw_ostream.h"
18#include "llvm/TargetParser/ARMTargetParserCommon.h"
19#include "llvm/TargetParser/Triple.h"
20#include <cctype>
21
22using namespace llvm;
23
24static StringRef getHWDivSynonym(StringRef HWDiv) {
25 return StringSwitch<StringRef>(HWDiv)
26 .Case(S: "thumb,arm", Value: "arm,thumb")
27 .Default(Value: HWDiv);
28}
29
30// Allows partial match, ex. "v7a" matches "armv7a".
31ARM::ArchKind ARM::parseArch(StringRef Arch) {
32 Arch = getCanonicalArchName(Arch);
33 StringRef Syn = getArchSynonym(Arch);
34 for (const auto &A : ARMArchNames) {
35 if (A.Name.ends_with(Suffix: Syn))
36 return A.ID;
37 }
38 return ArchKind::INVALID;
39}
40
41// Version number (ex. v7 = 7).
42unsigned ARM::parseArchVersion(StringRef Arch) {
43 Arch = getCanonicalArchName(Arch);
44 switch (parseArch(Arch)) {
45 case ArchKind::ARMV4:
46 case ArchKind::ARMV4T:
47 return 4;
48 case ArchKind::ARMV5T:
49 case ArchKind::ARMV5TE:
50 case ArchKind::IWMMXT:
51 case ArchKind::IWMMXT2:
52 case ArchKind::XSCALE:
53 case ArchKind::ARMV5TEJ:
54 return 5;
55 case ArchKind::ARMV6:
56 case ArchKind::ARMV6K:
57 case ArchKind::ARMV6T2:
58 case ArchKind::ARMV6KZ:
59 case ArchKind::ARMV6M:
60 return 6;
61 case ArchKind::ARMV7A:
62 case ArchKind::ARMV7VE:
63 case ArchKind::ARMV7R:
64 case ArchKind::ARMV7M:
65 case ArchKind::ARMV7S:
66 case ArchKind::ARMV7EM:
67 case ArchKind::ARMV7K:
68 return 7;
69 case ArchKind::ARMV8A:
70 case ArchKind::ARMV8_1A:
71 case ArchKind::ARMV8_2A:
72 case ArchKind::ARMV8_3A:
73 case ArchKind::ARMV8_4A:
74 case ArchKind::ARMV8_5A:
75 case ArchKind::ARMV8_6A:
76 case ArchKind::ARMV8_7A:
77 case ArchKind::ARMV8_8A:
78 case ArchKind::ARMV8_9A:
79 case ArchKind::ARMV8R:
80 case ArchKind::ARMV8MBaseline:
81 case ArchKind::ARMV8MMainline:
82 case ArchKind::ARMV8_1MMainline:
83 return 8;
84 case ArchKind::ARMV9A:
85 case ArchKind::ARMV9_1A:
86 case ArchKind::ARMV9_2A:
87 case ArchKind::ARMV9_3A:
88 case ArchKind::ARMV9_4A:
89 case ArchKind::ARMV9_5A:
90 case ArchKind::ARMV9_6A:
91 return 9;
92 case ArchKind::INVALID:
93 return 0;
94 }
95 llvm_unreachable("Unhandled architecture");
96}
97
98static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) {
99 switch (AK) {
100 case ARM::ArchKind::ARMV6M:
101 case ARM::ArchKind::ARMV7M:
102 case ARM::ArchKind::ARMV7EM:
103 case ARM::ArchKind::ARMV8MMainline:
104 case ARM::ArchKind::ARMV8MBaseline:
105 case ARM::ArchKind::ARMV8_1MMainline:
106 return ARM::ProfileKind::M;
107 case ARM::ArchKind::ARMV7R:
108 case ARM::ArchKind::ARMV8R:
109 return ARM::ProfileKind::R;
110 case ARM::ArchKind::ARMV7A:
111 case ARM::ArchKind::ARMV7VE:
112 case ARM::ArchKind::ARMV7K:
113 case ARM::ArchKind::ARMV8A:
114 case ARM::ArchKind::ARMV8_1A:
115 case ARM::ArchKind::ARMV8_2A:
116 case ARM::ArchKind::ARMV8_3A:
117 case ARM::ArchKind::ARMV8_4A:
118 case ARM::ArchKind::ARMV8_5A:
119 case ARM::ArchKind::ARMV8_6A:
120 case ARM::ArchKind::ARMV8_7A:
121 case ARM::ArchKind::ARMV8_8A:
122 case ARM::ArchKind::ARMV8_9A:
123 case ARM::ArchKind::ARMV9A:
124 case ARM::ArchKind::ARMV9_1A:
125 case ARM::ArchKind::ARMV9_2A:
126 case ARM::ArchKind::ARMV9_3A:
127 case ARM::ArchKind::ARMV9_4A:
128 case ARM::ArchKind::ARMV9_5A:
129 case ARM::ArchKind::ARMV9_6A:
130 return ARM::ProfileKind::A;
131 case ARM::ArchKind::ARMV4:
132 case ARM::ArchKind::ARMV4T:
133 case ARM::ArchKind::ARMV5T:
134 case ARM::ArchKind::ARMV5TE:
135 case ARM::ArchKind::ARMV5TEJ:
136 case ARM::ArchKind::ARMV6:
137 case ARM::ArchKind::ARMV6K:
138 case ARM::ArchKind::ARMV6T2:
139 case ARM::ArchKind::ARMV6KZ:
140 case ARM::ArchKind::ARMV7S:
141 case ARM::ArchKind::IWMMXT:
142 case ARM::ArchKind::IWMMXT2:
143 case ARM::ArchKind::XSCALE:
144 case ARM::ArchKind::INVALID:
145 return ARM::ProfileKind::INVALID;
146 }
147 llvm_unreachable("Unhandled architecture");
148}
149
150// Profile A/R/M
151ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
152 Arch = getCanonicalArchName(Arch);
153 return getProfileKind(AK: parseArch(Arch));
154}
155
156bool ARM::getFPUFeatures(ARM::FPUKind FPUKind,
157 std::vector<StringRef> &Features) {
158
159 if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
160 return false;
161
162 static const struct FPUFeatureNameInfo {
163 const char *PlusName, *MinusName;
164 FPUVersion MinVersion;
165 FPURestriction MaxRestriction;
166 } FPUFeatureInfoList[] = {
167 // We have to specify the + and - versions of the name in full so
168 // that we can return them as static StringRefs.
169 //
170 // Also, the SubtargetFeatures ending in just "sp" are listed here
171 // under FPURestriction::None, which is the only FPURestriction in
172 // which they would be valid (since FPURestriction::SP doesn't
173 // exist).
174 {.PlusName: "+vfp2", .MinusName: "-vfp2", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::D16},
175 {.PlusName: "+vfp2sp", .MinusName: "-vfp2sp", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::SP_D16},
176 {.PlusName: "+vfp3", .MinusName: "-vfp3", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
177 {.PlusName: "+vfp3d16", .MinusName: "-vfp3d16", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::D16},
178 {.PlusName: "+vfp3d16sp", .MinusName: "-vfp3d16sp", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::SP_D16},
179 {.PlusName: "+vfp3sp", .MinusName: "-vfp3sp", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
180 {.PlusName: "+fp16", .MinusName: "-fp16", .MinVersion: FPUVersion::VFPV3_FP16, .MaxRestriction: FPURestriction::SP_D16},
181 {.PlusName: "+vfp4", .MinusName: "-vfp4", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::None},
182 {.PlusName: "+vfp4d16", .MinusName: "-vfp4d16", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::D16},
183 {.PlusName: "+vfp4d16sp", .MinusName: "-vfp4d16sp", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::SP_D16},
184 {.PlusName: "+vfp4sp", .MinusName: "-vfp4sp", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::None},
185 {.PlusName: "+fp-armv8", .MinusName: "-fp-armv8", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::None},
186 {.PlusName: "+fp-armv8d16", .MinusName: "-fp-armv8d16", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::D16},
187 {.PlusName: "+fp-armv8d16sp", .MinusName: "-fp-armv8d16sp", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::SP_D16},
188 {.PlusName: "+fp-armv8sp", .MinusName: "-fp-armv8sp", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::None},
189 {.PlusName: "+fullfp16", .MinusName: "-fullfp16", .MinVersion: FPUVersion::VFPV5_FULLFP16, .MaxRestriction: FPURestriction::SP_D16},
190 {.PlusName: "+fp64", .MinusName: "-fp64", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::D16},
191 {.PlusName: "+d32", .MinusName: "-d32", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
192 };
193
194 for (const auto &Info: FPUFeatureInfoList) {
195 if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
196 FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
197 Features.push_back(x: Info.PlusName);
198 else
199 Features.push_back(x: Info.MinusName);
200 }
201
202 static const struct NeonFeatureNameInfo {
203 const char *PlusName, *MinusName;
204 NeonSupportLevel MinSupportLevel;
205 } NeonFeatureInfoList[] = {
206 {.PlusName: "+neon", .MinusName: "-neon", .MinSupportLevel: NeonSupportLevel::Neon},
207 {.PlusName: "+sha2", .MinusName: "-sha2", .MinSupportLevel: NeonSupportLevel::Crypto},
208 {.PlusName: "+aes", .MinusName: "-aes", .MinSupportLevel: NeonSupportLevel::Crypto},
209 };
210
211 for (const auto &Info: NeonFeatureInfoList) {
212 if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
213 Features.push_back(x: Info.PlusName);
214 else
215 Features.push_back(x: Info.MinusName);
216 }
217
218 return true;
219}
220
221ARM::FPUKind ARM::parseFPU(StringRef FPU) {
222 StringRef Syn = getFPUSynonym(FPU);
223 for (const auto &F : FPUNames) {
224 if (Syn == F.Name)
225 return F.ID;
226 }
227 return FK_INVALID;
228}
229
230ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(ARM::FPUKind FPUKind) {
231 if (FPUKind >= FK_LAST)
232 return NeonSupportLevel::None;
233 return FPUNames[FPUKind].NeonSupport;
234}
235
236StringRef ARM::getFPUSynonym(StringRef FPU) {
237 return StringSwitch<StringRef>(FPU)
238 .Cases(S0: "fpa", S1: "fpe2", S2: "fpe3", S3: "maverick", Value: "invalid") // Unsupported
239 .Case(S: "vfp2", Value: "vfpv2")
240 .Case(S: "vfp3", Value: "vfpv3")
241 .Case(S: "vfp4", Value: "vfpv4")
242 .Case(S: "vfp3-d16", Value: "vfpv3-d16")
243 .Case(S: "vfp4-d16", Value: "vfpv4-d16")
244 .Cases(S0: "fp4-sp-d16", S1: "vfpv4-sp-d16", Value: "fpv4-sp-d16")
245 .Cases(S0: "fp4-dp-d16", S1: "fpv4-dp-d16", Value: "vfpv4-d16")
246 .Case(S: "fp5-sp-d16", Value: "fpv5-sp-d16")
247 .Cases(S0: "fp5-dp-d16", S1: "fpv5-dp-d16", Value: "fpv5-d16")
248 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
249 .Case(S: "neon-vfpv3", Value: "neon")
250 .Default(Value: FPU);
251}
252
253StringRef ARM::getFPUName(ARM::FPUKind FPUKind) {
254 if (FPUKind >= FK_LAST)
255 return StringRef();
256 return FPUNames[FPUKind].Name;
257}
258
259ARM::FPUVersion ARM::getFPUVersion(ARM::FPUKind FPUKind) {
260 if (FPUKind >= FK_LAST)
261 return FPUVersion::NONE;
262 return FPUNames[FPUKind].FPUVer;
263}
264
265ARM::FPURestriction ARM::getFPURestriction(ARM::FPUKind FPUKind) {
266 if (FPUKind >= FK_LAST)
267 return FPURestriction::None;
268 return FPUNames[FPUKind].Restriction;
269}
270
271ARM::FPUKind ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
272 if (CPU == "generic")
273 return ARM::ARMArchNames[static_cast<unsigned>(AK)].DefaultFPU;
274
275 return StringSwitch<ARM::FPUKind>(CPU)
276#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
277 .Case(NAME, DEFAULT_FPU)
278#include "llvm/TargetParser/ARMTargetParser.def"
279 .Default(Value: ARM::FK_INVALID);
280}
281
282uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
283 if (CPU == "generic")
284 return ARM::ARMArchNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
285
286 return StringSwitch<uint64_t>(CPU)
287#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
288 .Case(NAME, \
289 ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
290 DEFAULT_EXT)
291#include "llvm/TargetParser/ARMTargetParser.def"
292 .Default(Value: ARM::AEK_INVALID);
293}
294
295bool ARM::getHWDivFeatures(uint64_t HWDivKind,
296 std::vector<StringRef> &Features) {
297
298 if (HWDivKind == AEK_INVALID)
299 return false;
300
301 if (HWDivKind & AEK_HWDIVARM)
302 Features.push_back(x: "+hwdiv-arm");
303 else
304 Features.push_back(x: "-hwdiv-arm");
305
306 if (HWDivKind & AEK_HWDIVTHUMB)
307 Features.push_back(x: "+hwdiv");
308 else
309 Features.push_back(x: "-hwdiv");
310
311 return true;
312}
313
314bool ARM::getExtensionFeatures(uint64_t Extensions,
315 std::vector<StringRef> &Features) {
316
317 if (Extensions == AEK_INVALID)
318 return false;
319
320 for (const auto &AE : ARCHExtNames) {
321 if ((Extensions & AE.ID) == AE.ID && !AE.Feature.empty())
322 Features.push_back(x: AE.Feature);
323 else if (!AE.NegFeature.empty())
324 Features.push_back(x: AE.NegFeature);
325 }
326
327 return getHWDivFeatures(HWDivKind: Extensions, Features);
328}
329
330StringRef ARM::getArchName(ARM::ArchKind AK) {
331 return ARMArchNames[static_cast<unsigned>(AK)].Name;
332}
333
334StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
335 return ARMArchNames[static_cast<unsigned>(AK)].CPUAttr;
336}
337
338StringRef ARM::getSubArch(ARM::ArchKind AK) {
339 return ARMArchNames[static_cast<unsigned>(AK)].getSubArch();
340}
341
342unsigned ARM::getArchAttr(ARM::ArchKind AK) {
343 return ARMArchNames[static_cast<unsigned>(AK)].ArchAttr;
344}
345
346StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
347 for (const auto &AE : ARCHExtNames) {
348 if (ArchExtKind == AE.ID)
349 return AE.Name;
350 }
351 return StringRef();
352}
353
354static bool stripNegationPrefix(StringRef &Name) {
355 return Name.consume_front(Prefix: "no");
356}
357
358StringRef ARM::getArchExtFeature(StringRef ArchExt) {
359 bool Negated = stripNegationPrefix(Name&: ArchExt);
360 for (const auto &AE : ARCHExtNames) {
361 if (!AE.Feature.empty() && ArchExt == AE.Name)
362 return StringRef(Negated ? AE.NegFeature : AE.Feature);
363 }
364
365 return StringRef();
366}
367
368static ARM::FPUKind findDoublePrecisionFPU(ARM::FPUKind InputFPUKind) {
369 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
370 return ARM::FK_INVALID;
371
372 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
373
374 // If the input FPU already supports double-precision, then there
375 // isn't any different FPU we can return here.
376 if (ARM::isDoublePrecision(restriction: InputFPU.Restriction))
377 return InputFPUKind;
378
379 // Otherwise, look for an FPU entry with all the same fields, except
380 // that it supports double precision.
381 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
382 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
383 CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
384 ARM::has32Regs(restriction: CandidateFPU.Restriction) ==
385 ARM::has32Regs(restriction: InputFPU.Restriction) &&
386 ARM::isDoublePrecision(restriction: CandidateFPU.Restriction)) {
387 return CandidateFPU.ID;
388 }
389 }
390
391 // nothing found
392 return ARM::FK_INVALID;
393}
394
395static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind InputFPUKind) {
396 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
397 return ARM::FK_INVALID;
398
399 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
400
401 // If the input FPU already is single-precision only, then there
402 // isn't any different FPU we can return here.
403 if (!ARM::isDoublePrecision(restriction: InputFPU.Restriction))
404 return InputFPUKind;
405
406 // Otherwise, look for an FPU entry that has the same FPUVer
407 // and is not Double Precision. We want to allow for changing of
408 // NEON Support and Restrictions so CPU's such as Cortex-R52 can
409 // select between SP Only and Full DP modes.
410 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
411 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
412 !ARM::isDoublePrecision(restriction: CandidateFPU.Restriction)) {
413 return CandidateFPU.ID;
414 }
415 }
416
417 // nothing found
418 return ARM::FK_INVALID;
419}
420
421bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
422 StringRef ArchExt,
423 std::vector<StringRef> &Features,
424 ARM::FPUKind &ArgFPUKind) {
425
426 size_t StartingNumFeatures = Features.size();
427 const bool Negated = stripNegationPrefix(Name&: ArchExt);
428 uint64_t ID = parseArchExt(ArchExt);
429
430 if (ID == AEK_INVALID)
431 return false;
432
433 for (const auto &AE : ARCHExtNames) {
434 if (Negated) {
435 if ((AE.ID & ID) == ID && !AE.NegFeature.empty())
436 Features.push_back(x: AE.NegFeature);
437 } else {
438 if ((AE.ID & ID) == AE.ID && !AE.Feature.empty())
439 Features.push_back(x: AE.Feature);
440 }
441 }
442
443 if (CPU == "")
444 CPU = "generic";
445
446 if (ArchExt == "fp" || ArchExt == "fp.dp") {
447 const ARM::FPUKind DefaultFPU = getDefaultFPU(CPU, AK);
448 ARM::FPUKind FPUKind;
449 if (ArchExt == "fp.dp") {
450 const bool IsDP = ArgFPUKind != ARM::FK_INVALID &&
451 ArgFPUKind != ARM::FK_NONE &&
452 isDoublePrecision(restriction: getFPURestriction(FPUKind: ArgFPUKind));
453 if (Negated) {
454 /* If there is no FPU selected yet, we still need to set ArgFPUKind, as
455 * leaving it as FK_INVALID, would cause default FPU to be selected
456 * later and that could be double precision one. */
457 if (ArgFPUKind != ARM::FK_INVALID && !IsDP)
458 return true;
459 FPUKind = findSinglePrecisionFPU(InputFPUKind: DefaultFPU);
460 if (FPUKind == ARM::FK_INVALID)
461 FPUKind = ARM::FK_NONE;
462 } else {
463 if (IsDP)
464 return true;
465 FPUKind = findDoublePrecisionFPU(InputFPUKind: DefaultFPU);
466 if (FPUKind == ARM::FK_INVALID)
467 return false;
468 }
469 } else if (Negated) {
470 FPUKind = ARM::FK_NONE;
471 } else {
472 FPUKind = DefaultFPU;
473 }
474 ArgFPUKind = FPUKind;
475 return true;
476 }
477 return StartingNumFeatures != Features.size();
478}
479
480ARM::ArchKind ARM::convertV9toV8(ARM::ArchKind AK) {
481 if (getProfileKind(AK) != ProfileKind::A)
482 return ARM::ArchKind::INVALID;
483 if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
484 return ARM::ArchKind::INVALID;
485 unsigned AK_v8 = static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
486 AK_v8 += static_cast<unsigned>(AK) -
487 static_cast<unsigned>(ARM::ArchKind::ARMV9A);
488 return static_cast<ARM::ArchKind>(AK_v8);
489}
490
491StringRef ARM::getDefaultCPU(StringRef Arch) {
492 ArchKind AK = parseArch(Arch);
493 if (AK == ArchKind::INVALID)
494 return StringRef();
495
496 // Look for multiple AKs to find the default for pair AK+Name.
497 for (const auto &CPU : CPUNames) {
498 if (CPU.ArchID == AK && CPU.Default)
499 return CPU.Name;
500 }
501
502 // If we can't find a default then target the architecture instead
503 return "generic";
504}
505
506uint64_t ARM::parseHWDiv(StringRef HWDiv) {
507 StringRef Syn = getHWDivSynonym(HWDiv);
508 for (const auto &D : HWDivNames) {
509 if (Syn == D.Name)
510 return D.ID;
511 }
512 return AEK_INVALID;
513}
514
515uint64_t ARM::parseArchExt(StringRef ArchExt) {
516 for (const auto &A : ARCHExtNames) {
517 if (ArchExt == A.Name)
518 return A.ID;
519 }
520 return AEK_INVALID;
521}
522
523ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
524 for (const auto &C : CPUNames) {
525 if (CPU == C.Name)
526 return C.ArchID;
527 }
528 return ArchKind::INVALID;
529}
530
531void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
532 for (const auto &Arch : CPUNames) {
533 if (Arch.ArchID != ArchKind::INVALID)
534 Values.push_back(Elt: Arch.Name);
535 }
536}
537
538StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
539 StringRef ArchName =
540 CPU.empty() ? TT.getArchName() : getArchName(AK: parseCPUArch(CPU));
541
542 if (TT.isOSBinFormatMachO()) {
543 if (TT.getEnvironment() == Triple::EABI ||
544 TT.getOS() == Triple::UnknownOS ||
545 parseArchProfile(Arch: ArchName) == ProfileKind::M)
546 return "aapcs";
547 if (TT.isWatchABI())
548 return "aapcs16";
549 return "apcs-gnu";
550 } else if (TT.isOSWindows())
551 // FIXME: this is invalid for WindowsCE.
552 return "aapcs";
553
554 // Select the default based on the platform.
555 switch (TT.getEnvironment()) {
556 case Triple::Android:
557 case Triple::GNUEABI:
558 case Triple::GNUEABIT64:
559 case Triple::GNUEABIHF:
560 case Triple::GNUEABIHFT64:
561 case Triple::MuslEABI:
562 case Triple::MuslEABIHF:
563 case Triple::OpenHOS:
564 return "aapcs-linux";
565 case Triple::EABIHF:
566 case Triple::EABI:
567 return "aapcs";
568 default:
569 if (TT.isOSNetBSD())
570 return "apcs-gnu";
571 if (TT.isOSFreeBSD() || TT.isOSOpenBSD() || TT.isOSHaiku() ||
572 TT.isOHOSFamily())
573 return "aapcs-linux";
574 return "aapcs";
575 }
576}
577
578ARM::ARMABI ARM::computeTargetABI(const Triple &TT, StringRef CPU,
579 StringRef ABIName) {
580 if (ABIName.empty())
581 ABIName = ARM::computeDefaultTargetABI(TT, CPU);
582
583 if (ABIName == "aapcs16")
584 return ARM_ABI_AAPCS16;
585
586 if (ABIName.starts_with(Prefix: "aapcs"))
587 return ARM_ABI_AAPCS;
588
589 if (ABIName.starts_with(Prefix: "apcs"))
590 return ARM_ABI_APCS;
591
592 return ARM_ABI_UNKNOWN;
593}
594
595StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
596 if (MArch.empty())
597 MArch = Triple.getArchName();
598 MArch = llvm::ARM::getCanonicalArchName(Arch: MArch);
599
600 // Some defaults are forced.
601 switch (Triple.getOS()) {
602 case llvm::Triple::FreeBSD:
603 case llvm::Triple::NetBSD:
604 case llvm::Triple::OpenBSD:
605 case llvm::Triple::Haiku:
606 if (!MArch.empty() && MArch == "v6")
607 return "arm1176jzf-s";
608 if (!MArch.empty() && MArch == "v7")
609 return "cortex-a8";
610 break;
611 case llvm::Triple::Win32:
612 // FIXME: this is invalid for WindowsCE
613 if (llvm::ARM::parseArchVersion(Arch: MArch) <= 7)
614 return "cortex-a9";
615 break;
616 case llvm::Triple::IOS:
617 case llvm::Triple::MacOSX:
618 case llvm::Triple::TvOS:
619 case llvm::Triple::WatchOS:
620 case llvm::Triple::DriverKit:
621 case llvm::Triple::XROS:
622 if (MArch == "v7k")
623 return "cortex-a7";
624 break;
625 default:
626 break;
627 }
628
629 if (MArch.empty())
630 return StringRef();
631
632 StringRef CPU = llvm::ARM::getDefaultCPU(Arch: MArch);
633 if (!CPU.empty() && CPU != "invalid")
634 return CPU;
635
636 // If no specific architecture version is requested, return the minimum CPU
637 // required by the OS and environment.
638 switch (Triple.getOS()) {
639 case llvm::Triple::Haiku:
640 return "arm1176jzf-s";
641 case llvm::Triple::NetBSD:
642 switch (Triple.getEnvironment()) {
643 case llvm::Triple::EABI:
644 case llvm::Triple::EABIHF:
645 case llvm::Triple::GNUEABI:
646 case llvm::Triple::GNUEABIHF:
647 return "arm926ej-s";
648 default:
649 return "strongarm";
650 }
651 case llvm::Triple::NaCl:
652 case llvm::Triple::OpenBSD:
653 return "cortex-a8";
654 default:
655 switch (Triple.getEnvironment()) {
656 case llvm::Triple::EABIHF:
657 case llvm::Triple::GNUEABIHF:
658 case llvm::Triple::GNUEABIHFT64:
659 case llvm::Triple::MuslEABIHF:
660 return "arm1176jzf-s";
661 default:
662 return "arm7tdmi";
663 }
664 }
665
666 llvm_unreachable("invalid arch name");
667}
668
669void ARM::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
670 outs() << "All available -march extensions for ARM\n\n"
671 << " " << left_justify(Str: "Name", Width: 20)
672 << (DescMap.empty() ? "\n" : "Description\n");
673 for (const auto &Ext : ARCHExtNames) {
674 // Extensions without a feature cannot be used with -march.
675 if (!Ext.Feature.empty()) {
676 std::string Description = DescMap[Ext.Name].str();
677 // With SIMD, this links to the NEON feature, so the description should be
678 // taken from here, as SIMD does not exist in TableGen.
679 if (Ext.Name == "simd")
680 Description = DescMap["neon"].str();
681 outs() << " "
682 << format(Fmt: Description.empty() ? "%s\n" : "%-20s%s\n",
683 Vals: Ext.Name.str().c_str(), Vals: Description.c_str());
684 }
685 }
686}
687