| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Assembly Writer Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: AArch64.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | /// getMnemonic - This method is automatically generated by tablegen |
| 11 | /// from the instruction set description. |
| 12 | std::pair<const char *, uint64_t> AArch64AppleInstPrinter::getMnemonic(const MCInst *MI) { |
| 13 | |
| 14 | #ifdef __GNUC__ |
| 15 | #pragma GCC diagnostic push |
| 16 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 17 | #endif |
| 18 | static const char AsmStrs[] = { |
| 19 | /* 0 */ "st64bv0\t\0" |
| 20 | /* 9 */ "ld1\t\0" |
| 21 | /* 14 */ "stl1\t\0" |
| 22 | /* 20 */ "trn1\t\0" |
| 23 | /* 26 */ "ldap1\t\0" |
| 24 | /* 33 */ "zip1\t\0" |
| 25 | /* 39 */ "uzp1\t\0" |
| 26 | /* 45 */ "zipq1\t\0" |
| 27 | /* 52 */ "uzpq1\t\0" |
| 28 | /* 59 */ "dcps1\t\0" |
| 29 | /* 66 */ "gcsss1\t\0" |
| 30 | /* 74 */ "st1\t\0" |
| 31 | /* 79 */ "rax1\t\0" |
| 32 | /* 85 */ "rev32\t\0" |
| 33 | /* 92 */ "ld2\t\0" |
| 34 | /* 97 */ "luti2\t\0" |
| 35 | /* 104 */ "fmlal2\t\0" |
| 36 | /* 112 */ "fmlsl2\t\0" |
| 37 | /* 120 */ "fcvtl2\t\0" |
| 38 | /* 128 */ "trn2\t\0" |
| 39 | /* 134 */ "fcvtn2\t\0" |
| 40 | /* 142 */ "fcvtxn2\t\0" |
| 41 | /* 151 */ "zip2\t\0" |
| 42 | /* 157 */ "uzp2\t\0" |
| 43 | /* 163 */ "zipq2\t\0" |
| 44 | /* 170 */ "uzpq2\t\0" |
| 45 | /* 177 */ "dcps2\t\0" |
| 46 | /* 184 */ "gcsss2\t\0" |
| 47 | /* 192 */ "st2\t\0" |
| 48 | /* 197 */ "ld3\t\0" |
| 49 | /* 202 */ "eor3\t\0" |
| 50 | /* 208 */ "dcps3\t\0" |
| 51 | /* 215 */ "st3\t\0" |
| 52 | /* 220 */ "ld4\t\0" |
| 53 | /* 225 */ "luti4\t\0" |
| 54 | /* 232 */ "st4\t\0" |
| 55 | /* 237 */ "rev16\t\0" |
| 56 | /* 244 */ "braa\t\0" |
| 57 | /* 250 */ "ldraa\t\0" |
| 58 | /* 257 */ "blraa\t\0" |
| 59 | /* 264 */ "saba\t\0" |
| 60 | /* 270 */ "uaba\t\0" |
| 61 | /* 276 */ "pacda\t\0" |
| 62 | /* 283 */ "ldadda\t\0" |
| 63 | /* 291 */ "fadda\t\0" |
| 64 | /* 298 */ "autda\t\0" |
| 65 | /* 305 */ "pacga\t\0" |
| 66 | /* 312 */ "addha\t\0" |
| 67 | /* 319 */ "pacia\t\0" |
| 68 | /* 326 */ "autia\t\0" |
| 69 | /* 333 */ "brka\t\0" |
| 70 | /* 339 */ "fcmla\t\0" |
| 71 | /* 346 */ "bfmla\t\0" |
| 72 | /* 353 */ "bfmmla\t\0" |
| 73 | /* 361 */ "usmmla\t\0" |
| 74 | /* 369 */ "ummla\t\0" |
| 75 | /* 376 */ "fnmla\t\0" |
| 76 | /* 383 */ "ldsmina\t\0" |
| 77 | /* 392 */ "ldumina\t\0" |
| 78 | /* 401 */ "brkpa\t\0" |
| 79 | /* 408 */ "bmopa\t\0" |
| 80 | /* 415 */ "bfmopa\t\0" |
| 81 | /* 423 */ "usmopa\t\0" |
| 82 | /* 431 */ "sumopa\t\0" |
| 83 | /* 439 */ "rcwsswppa\t\0" |
| 84 | /* 450 */ "rcwswppa\t\0" |
| 85 | /* 460 */ "ldclrpa\t\0" |
| 86 | /* 469 */ "rcwsclrpa\t\0" |
| 87 | /* 480 */ "rcwclrpa\t\0" |
| 88 | /* 490 */ "rcwscaspa\t\0" |
| 89 | /* 501 */ "rcwcaspa\t\0" |
| 90 | /* 511 */ "ldsetpa\t\0" |
| 91 | /* 520 */ "rcwssetpa\t\0" |
| 92 | /* 531 */ "rcwsetpa\t\0" |
| 93 | /* 541 */ "rcwsswpa\t\0" |
| 94 | /* 551 */ "rcwswpa\t\0" |
| 95 | /* 560 */ "fexpa\t\0" |
| 96 | /* 567 */ "ldclra\t\0" |
| 97 | /* 575 */ "rcwsclra\t\0" |
| 98 | /* 585 */ "rcwclra\t\0" |
| 99 | /* 594 */ "ldeora\t\0" |
| 100 | /* 602 */ "srsra\t\0" |
| 101 | /* 609 */ "ursra\t\0" |
| 102 | /* 616 */ "ssra\t\0" |
| 103 | /* 622 */ "usra\t\0" |
| 104 | /* 628 */ "rcwscasa\t\0" |
| 105 | /* 638 */ "rcwcasa\t\0" |
| 106 | /* 647 */ "ldseta\t\0" |
| 107 | /* 655 */ "rcwsseta\t\0" |
| 108 | /* 665 */ "rcwseta\t\0" |
| 109 | /* 674 */ "frinta\t\0" |
| 110 | /* 682 */ "clasta\t\0" |
| 111 | /* 690 */ "addva\t\0" |
| 112 | /* 697 */ "mova\t\0" |
| 113 | /* 703 */ "ldsmaxa\t\0" |
| 114 | /* 712 */ "ldumaxa\t\0" |
| 115 | /* 721 */ "pacdza\t\0" |
| 116 | /* 729 */ "autdza\t\0" |
| 117 | /* 737 */ "paciza\t\0" |
| 118 | /* 745 */ "autiza\t\0" |
| 119 | /* 753 */ "ins.b\t\0" |
| 120 | /* 760 */ "smov.b\t\0" |
| 121 | /* 768 */ "umov.b\t\0" |
| 122 | /* 776 */ "ld1b\t\0" |
| 123 | /* 782 */ "ldff1b\t\0" |
| 124 | /* 790 */ "ldnf1b\t\0" |
| 125 | /* 798 */ "ldnt1b\t\0" |
| 126 | /* 806 */ "stnt1b\t\0" |
| 127 | /* 814 */ "st1b\t\0" |
| 128 | /* 820 */ "crc32b\t\0" |
| 129 | /* 828 */ "ld2b\t\0" |
| 130 | /* 834 */ "st2b\t\0" |
| 131 | /* 840 */ "ld3b\t\0" |
| 132 | /* 846 */ "st3b\t\0" |
| 133 | /* 852 */ "ld64b\t\0" |
| 134 | /* 859 */ "st64b\t\0" |
| 135 | /* 866 */ "ld4b\t\0" |
| 136 | /* 872 */ "st4b\t\0" |
| 137 | /* 878 */ "trn1.16b\t\0" |
| 138 | /* 888 */ "zip1.16b\t\0" |
| 139 | /* 898 */ "uzp1.16b\t\0" |
| 140 | /* 908 */ "rev32.16b\t\0" |
| 141 | /* 919 */ "rsubhn2.16b\t\0" |
| 142 | /* 932 */ "raddhn2.16b\t\0" |
| 143 | /* 945 */ "sqshrn2.16b\t\0" |
| 144 | /* 958 */ "uqshrn2.16b\t\0" |
| 145 | /* 971 */ "sqrshrn2.16b\t\0" |
| 146 | /* 985 */ "uqrshrn2.16b\t\0" |
| 147 | /* 999 */ "trn2.16b\t\0" |
| 148 | /* 1009 */ "sqxtn2.16b\t\0" |
| 149 | /* 1021 */ "uqxtn2.16b\t\0" |
| 150 | /* 1033 */ "sqshrun2.16b\t\0" |
| 151 | /* 1047 */ "sqrshrun2.16b\t\0" |
| 152 | /* 1062 */ "sqxtun2.16b\t\0" |
| 153 | /* 1075 */ "zip2.16b\t\0" |
| 154 | /* 1085 */ "uzp2.16b\t\0" |
| 155 | /* 1095 */ "eor3.16b\t\0" |
| 156 | /* 1105 */ "rev64.16b\t\0" |
| 157 | /* 1116 */ "rev16.16b\t\0" |
| 158 | /* 1127 */ "saba.16b\t\0" |
| 159 | /* 1137 */ "uaba.16b\t\0" |
| 160 | /* 1147 */ "mla.16b\t\0" |
| 161 | /* 1156 */ "srsra.16b\t\0" |
| 162 | /* 1167 */ "ursra.16b\t\0" |
| 163 | /* 1178 */ "ssra.16b\t\0" |
| 164 | /* 1188 */ "usra.16b\t\0" |
| 165 | /* 1198 */ "shsub.16b\t\0" |
| 166 | /* 1209 */ "uhsub.16b\t\0" |
| 167 | /* 1220 */ "sqsub.16b\t\0" |
| 168 | /* 1231 */ "uqsub.16b\t\0" |
| 169 | /* 1242 */ "bic.16b\t\0" |
| 170 | /* 1251 */ "aesimc.16b\t\0" |
| 171 | /* 1263 */ "aesmc.16b\t\0" |
| 172 | /* 1274 */ "sabd.16b\t\0" |
| 173 | /* 1284 */ "uabd.16b\t\0" |
| 174 | /* 1294 */ "srhadd.16b\t\0" |
| 175 | /* 1306 */ "urhadd.16b\t\0" |
| 176 | /* 1318 */ "shadd.16b\t\0" |
| 177 | /* 1329 */ "uhadd.16b\t\0" |
| 178 | /* 1340 */ "usqadd.16b\t\0" |
| 179 | /* 1352 */ "suqadd.16b\t\0" |
| 180 | /* 1364 */ "and.16b\t\0" |
| 181 | /* 1373 */ "aesd.16b\t\0" |
| 182 | /* 1383 */ "cmge.16b\t\0" |
| 183 | /* 1393 */ "cmle.16b\t\0" |
| 184 | /* 1403 */ "aese.16b\t\0" |
| 185 | /* 1413 */ "bif.16b\t\0" |
| 186 | /* 1422 */ "sqneg.16b\t\0" |
| 187 | /* 1433 */ "cmhi.16b\t\0" |
| 188 | /* 1443 */ "sli.16b\t\0" |
| 189 | /* 1452 */ "sri.16b\t\0" |
| 190 | /* 1461 */ "movi.16b\t\0" |
| 191 | /* 1471 */ "sqshl.16b\t\0" |
| 192 | /* 1482 */ "uqshl.16b\t\0" |
| 193 | /* 1493 */ "sqrshl.16b\t\0" |
| 194 | /* 1505 */ "uqrshl.16b\t\0" |
| 195 | /* 1517 */ "srshl.16b\t\0" |
| 196 | /* 1528 */ "urshl.16b\t\0" |
| 197 | /* 1539 */ "sshl.16b\t\0" |
| 198 | /* 1549 */ "ushl.16b\t\0" |
| 199 | /* 1559 */ "bsl.16b\t\0" |
| 200 | /* 1568 */ "pmul.16b\t\0" |
| 201 | /* 1578 */ "smin.16b\t\0" |
| 202 | /* 1588 */ "umin.16b\t\0" |
| 203 | /* 1598 */ "orn.16b\t\0" |
| 204 | /* 1607 */ "addp.16b\t\0" |
| 205 | /* 1617 */ "sminp.16b\t\0" |
| 206 | /* 1628 */ "uminp.16b\t\0" |
| 207 | /* 1639 */ "dup.16b\t\0" |
| 208 | /* 1648 */ "smaxp.16b\t\0" |
| 209 | /* 1659 */ "umaxp.16b\t\0" |
| 210 | /* 1670 */ "cmeq.16b\t\0" |
| 211 | /* 1680 */ "srshr.16b\t\0" |
| 212 | /* 1691 */ "urshr.16b\t\0" |
| 213 | /* 1702 */ "sshr.16b\t\0" |
| 214 | /* 1712 */ "ushr.16b\t\0" |
| 215 | /* 1722 */ "eor.16b\t\0" |
| 216 | /* 1731 */ "orr.16b\t\0" |
| 217 | /* 1740 */ "sqabs.16b\t\0" |
| 218 | /* 1751 */ "cmhs.16b\t\0" |
| 219 | /* 1761 */ "cls.16b\t\0" |
| 220 | /* 1770 */ "mls.16b\t\0" |
| 221 | /* 1779 */ "cmgt.16b\t\0" |
| 222 | /* 1789 */ "rbit.16b\t\0" |
| 223 | /* 1799 */ "cmlt.16b\t\0" |
| 224 | /* 1809 */ "cnt.16b\t\0" |
| 225 | /* 1818 */ "not.16b\t\0" |
| 226 | /* 1827 */ "cmtst.16b\t\0" |
| 227 | /* 1838 */ "ext.16b\t\0" |
| 228 | /* 1847 */ "sqshlu.16b\t\0" |
| 229 | /* 1859 */ "addv.16b\t\0" |
| 230 | /* 1869 */ "saddlv.16b\t\0" |
| 231 | /* 1881 */ "uaddlv.16b\t\0" |
| 232 | /* 1893 */ "sminv.16b\t\0" |
| 233 | /* 1904 */ "uminv.16b\t\0" |
| 234 | /* 1915 */ "smaxv.16b\t\0" |
| 235 | /* 1926 */ "umaxv.16b\t\0" |
| 236 | /* 1937 */ "bcax.16b\t\0" |
| 237 | /* 1947 */ "smax.16b\t\0" |
| 238 | /* 1957 */ "umax.16b\t\0" |
| 239 | /* 1967 */ "clz.16b\t\0" |
| 240 | /* 1976 */ "trn1.8b\t\0" |
| 241 | /* 1985 */ "zip1.8b\t\0" |
| 242 | /* 1994 */ "uzp1.8b\t\0" |
| 243 | /* 2003 */ "rev32.8b\t\0" |
| 244 | /* 2013 */ "trn2.8b\t\0" |
| 245 | /* 2022 */ "zip2.8b\t\0" |
| 246 | /* 2031 */ "uzp2.8b\t\0" |
| 247 | /* 2040 */ "rev64.8b\t\0" |
| 248 | /* 2050 */ "rev16.8b\t\0" |
| 249 | /* 2060 */ "saba.8b\t\0" |
| 250 | /* 2069 */ "uaba.8b\t\0" |
| 251 | /* 2078 */ "mla.8b\t\0" |
| 252 | /* 2086 */ "srsra.8b\t\0" |
| 253 | /* 2096 */ "ursra.8b\t\0" |
| 254 | /* 2106 */ "ssra.8b\t\0" |
| 255 | /* 2115 */ "usra.8b\t\0" |
| 256 | /* 2124 */ "shsub.8b\t\0" |
| 257 | /* 2134 */ "uhsub.8b\t\0" |
| 258 | /* 2144 */ "sqsub.8b\t\0" |
| 259 | /* 2154 */ "uqsub.8b\t\0" |
| 260 | /* 2164 */ "bic.8b\t\0" |
| 261 | /* 2172 */ "sabd.8b\t\0" |
| 262 | /* 2181 */ "uabd.8b\t\0" |
| 263 | /* 2190 */ "srhadd.8b\t\0" |
| 264 | /* 2201 */ "urhadd.8b\t\0" |
| 265 | /* 2212 */ "shadd.8b\t\0" |
| 266 | /* 2222 */ "uhadd.8b\t\0" |
| 267 | /* 2232 */ "usqadd.8b\t\0" |
| 268 | /* 2243 */ "suqadd.8b\t\0" |
| 269 | /* 2254 */ "and.8b\t\0" |
| 270 | /* 2262 */ "cmge.8b\t\0" |
| 271 | /* 2271 */ "cmle.8b\t\0" |
| 272 | /* 2280 */ "bif.8b\t\0" |
| 273 | /* 2288 */ "sqneg.8b\t\0" |
| 274 | /* 2298 */ "cmhi.8b\t\0" |
| 275 | /* 2307 */ "sli.8b\t\0" |
| 276 | /* 2315 */ "sri.8b\t\0" |
| 277 | /* 2323 */ "movi.8b\t\0" |
| 278 | /* 2332 */ "sqshl.8b\t\0" |
| 279 | /* 2342 */ "uqshl.8b\t\0" |
| 280 | /* 2352 */ "sqrshl.8b\t\0" |
| 281 | /* 2363 */ "uqrshl.8b\t\0" |
| 282 | /* 2374 */ "srshl.8b\t\0" |
| 283 | /* 2384 */ "urshl.8b\t\0" |
| 284 | /* 2394 */ "sshl.8b\t\0" |
| 285 | /* 2403 */ "ushl.8b\t\0" |
| 286 | /* 2412 */ "bsl.8b\t\0" |
| 287 | /* 2420 */ "pmul.8b\t\0" |
| 288 | /* 2429 */ "rsubhn.8b\t\0" |
| 289 | /* 2440 */ "raddhn.8b\t\0" |
| 290 | /* 2451 */ "smin.8b\t\0" |
| 291 | /* 2460 */ "umin.8b\t\0" |
| 292 | /* 2469 */ "sqshrn.8b\t\0" |
| 293 | /* 2480 */ "uqshrn.8b\t\0" |
| 294 | /* 2491 */ "sqrshrn.8b\t\0" |
| 295 | /* 2503 */ "uqrshrn.8b\t\0" |
| 296 | /* 2515 */ "orn.8b\t\0" |
| 297 | /* 2523 */ "sqxtn.8b\t\0" |
| 298 | /* 2533 */ "uqxtn.8b\t\0" |
| 299 | /* 2543 */ "sqshrun.8b\t\0" |
| 300 | /* 2555 */ "sqrshrun.8b\t\0" |
| 301 | /* 2568 */ "sqxtun.8b\t\0" |
| 302 | /* 2579 */ "addp.8b\t\0" |
| 303 | /* 2588 */ "sminp.8b\t\0" |
| 304 | /* 2598 */ "uminp.8b\t\0" |
| 305 | /* 2608 */ "dup.8b\t\0" |
| 306 | /* 2616 */ "smaxp.8b\t\0" |
| 307 | /* 2626 */ "umaxp.8b\t\0" |
| 308 | /* 2636 */ "cmeq.8b\t\0" |
| 309 | /* 2645 */ "srshr.8b\t\0" |
| 310 | /* 2655 */ "urshr.8b\t\0" |
| 311 | /* 2665 */ "sshr.8b\t\0" |
| 312 | /* 2674 */ "ushr.8b\t\0" |
| 313 | /* 2683 */ "eor.8b\t\0" |
| 314 | /* 2691 */ "orr.8b\t\0" |
| 315 | /* 2699 */ "sqabs.8b\t\0" |
| 316 | /* 2709 */ "cmhs.8b\t\0" |
| 317 | /* 2718 */ "cls.8b\t\0" |
| 318 | /* 2726 */ "mls.8b\t\0" |
| 319 | /* 2734 */ "cmgt.8b\t\0" |
| 320 | /* 2743 */ "rbit.8b\t\0" |
| 321 | /* 2752 */ "cmlt.8b\t\0" |
| 322 | /* 2761 */ "cnt.8b\t\0" |
| 323 | /* 2769 */ "not.8b\t\0" |
| 324 | /* 2777 */ "cmtst.8b\t\0" |
| 325 | /* 2787 */ "ext.8b\t\0" |
| 326 | /* 2795 */ "sqshlu.8b\t\0" |
| 327 | /* 2806 */ "addv.8b\t\0" |
| 328 | /* 2815 */ "saddlv.8b\t\0" |
| 329 | /* 2826 */ "uaddlv.8b\t\0" |
| 330 | /* 2837 */ "sminv.8b\t\0" |
| 331 | /* 2847 */ "uminv.8b\t\0" |
| 332 | /* 2857 */ "smaxv.8b\t\0" |
| 333 | /* 2867 */ "umaxv.8b\t\0" |
| 334 | /* 2877 */ "smax.8b\t\0" |
| 335 | /* 2886 */ "umax.8b\t\0" |
| 336 | /* 2895 */ "clz.8b\t\0" |
| 337 | /* 2903 */ "ldaddab\t\0" |
| 338 | /* 2912 */ "ldsminab\t\0" |
| 339 | /* 2922 */ "lduminab\t\0" |
| 340 | /* 2932 */ "swpab\t\0" |
| 341 | /* 2939 */ "brab\t\0" |
| 342 | /* 2945 */ "ldrab\t\0" |
| 343 | /* 2952 */ "blrab\t\0" |
| 344 | /* 2959 */ "ldclrab\t\0" |
| 345 | /* 2968 */ "ldeorab\t\0" |
| 346 | /* 2977 */ "casab\t\0" |
| 347 | /* 2984 */ "ldsetab\t\0" |
| 348 | /* 2993 */ "ldsmaxab\t\0" |
| 349 | /* 3003 */ "ldumaxab\t\0" |
| 350 | /* 3013 */ "fmlallbb\t\0" |
| 351 | /* 3023 */ "crc32cb\t\0" |
| 352 | /* 3032 */ "sqdecb\t\0" |
| 353 | /* 3040 */ "uqdecb\t\0" |
| 354 | /* 3048 */ "sqincb\t\0" |
| 355 | /* 3056 */ "uqincb\t\0" |
| 356 | /* 3064 */ "pacdb\t\0" |
| 357 | /* 3071 */ "ldaddb\t\0" |
| 358 | /* 3079 */ "autdb\t\0" |
| 359 | /* 3086 */ "prfb\t\0" |
| 360 | /* 3092 */ "flogb\t\0" |
| 361 | /* 3099 */ "pacib\t\0" |
| 362 | /* 3106 */ "autib\t\0" |
| 363 | /* 3113 */ "brkb\t\0" |
| 364 | /* 3119 */ "sabalb\t\0" |
| 365 | /* 3127 */ "uabalb\t\0" |
| 366 | /* 3135 */ "ldaddalb\t\0" |
| 367 | /* 3145 */ "sqdmlalb\t\0" |
| 368 | /* 3155 */ "bfmlalb\t\0" |
| 369 | /* 3164 */ "smlalb\t\0" |
| 370 | /* 3172 */ "umlalb\t\0" |
| 371 | /* 3180 */ "ldsminalb\t\0" |
| 372 | /* 3191 */ "lduminalb\t\0" |
| 373 | /* 3202 */ "swpalb\t\0" |
| 374 | /* 3210 */ "ldclralb\t\0" |
| 375 | /* 3220 */ "ldeoralb\t\0" |
| 376 | /* 3230 */ "casalb\t\0" |
| 377 | /* 3238 */ "ldsetalb\t\0" |
| 378 | /* 3248 */ "ldsmaxalb\t\0" |
| 379 | /* 3259 */ "ldumaxalb\t\0" |
| 380 | /* 3270 */ "ssublb\t\0" |
| 381 | /* 3278 */ "usublb\t\0" |
| 382 | /* 3286 */ "sbclb\t\0" |
| 383 | /* 3293 */ "adclb\t\0" |
| 384 | /* 3300 */ "sabdlb\t\0" |
| 385 | /* 3308 */ "uabdlb\t\0" |
| 386 | /* 3316 */ "ldaddlb\t\0" |
| 387 | /* 3325 */ "saddlb\t\0" |
| 388 | /* 3333 */ "uaddlb\t\0" |
| 389 | /* 3341 */ "sshllb\t\0" |
| 390 | /* 3349 */ "ushllb\t\0" |
| 391 | /* 3357 */ "sqdmullb\t\0" |
| 392 | /* 3367 */ "pmullb\t\0" |
| 393 | /* 3375 */ "smullb\t\0" |
| 394 | /* 3383 */ "umullb\t\0" |
| 395 | /* 3391 */ "ldsminlb\t\0" |
| 396 | /* 3401 */ "lduminlb\t\0" |
| 397 | /* 3411 */ "swplb\t\0" |
| 398 | /* 3418 */ "ldclrlb\t\0" |
| 399 | /* 3427 */ "ldeorlb\t\0" |
| 400 | /* 3436 */ "caslb\t\0" |
| 401 | /* 3443 */ "sqdmlslb\t\0" |
| 402 | /* 3453 */ "bfmlslb\t\0" |
| 403 | /* 3462 */ "smlslb\t\0" |
| 404 | /* 3470 */ "umlslb\t\0" |
| 405 | /* 3478 */ "ldsetlb\t\0" |
| 406 | /* 3487 */ "ldsmaxlb\t\0" |
| 407 | /* 3497 */ "ldumaxlb\t\0" |
| 408 | /* 3507 */ "dmb\t\0" |
| 409 | /* 3512 */ "rsubhnb\t\0" |
| 410 | /* 3521 */ "raddhnb\t\0" |
| 411 | /* 3530 */ "ldsminb\t\0" |
| 412 | /* 3539 */ "lduminb\t\0" |
| 413 | /* 3548 */ "sqshrnb\t\0" |
| 414 | /* 3557 */ "uqshrnb\t\0" |
| 415 | /* 3566 */ "sqrshrnb\t\0" |
| 416 | /* 3576 */ "uqrshrnb\t\0" |
| 417 | /* 3586 */ "fcvtnb\t\0" |
| 418 | /* 3594 */ "sqxtnb\t\0" |
| 419 | /* 3602 */ "uqxtnb\t\0" |
| 420 | /* 3610 */ "sqshrunb\t\0" |
| 421 | /* 3620 */ "sqrshrunb\t\0" |
| 422 | /* 3631 */ "sqxtunb\t\0" |
| 423 | /* 3640 */ "ld1rob\t\0" |
| 424 | /* 3648 */ "brkpb\t\0" |
| 425 | /* 3655 */ "swpb\t\0" |
| 426 | /* 3661 */ "ld1rqb\t\0" |
| 427 | /* 3669 */ "ld1rb\t\0" |
| 428 | /* 3676 */ "ldarb\t\0" |
| 429 | /* 3683 */ "ldlarb\t\0" |
| 430 | /* 3691 */ "ldrb\t\0" |
| 431 | /* 3697 */ "ldclrb\t\0" |
| 432 | /* 3705 */ "stllrb\t\0" |
| 433 | /* 3713 */ "stlrb\t\0" |
| 434 | /* 3720 */ "ldeorb\t\0" |
| 435 | /* 3728 */ "ldaprb\t\0" |
| 436 | /* 3736 */ "ldtrb\t\0" |
| 437 | /* 3743 */ "strb\t\0" |
| 438 | /* 3749 */ "sttrb\t\0" |
| 439 | /* 3756 */ "ldurb\t\0" |
| 440 | /* 3763 */ "stlurb\t\0" |
| 441 | /* 3771 */ "ldapurb\t\0" |
| 442 | /* 3780 */ "sturb\t\0" |
| 443 | /* 3787 */ "ldaxrb\t\0" |
| 444 | /* 3795 */ "ldxrb\t\0" |
| 445 | /* 3802 */ "stlxrb\t\0" |
| 446 | /* 3810 */ "stxrb\t\0" |
| 447 | /* 3817 */ "ld1sb\t\0" |
| 448 | /* 3824 */ "ldff1sb\t\0" |
| 449 | /* 3833 */ "ldnf1sb\t\0" |
| 450 | /* 3842 */ "ldnt1sb\t\0" |
| 451 | /* 3851 */ "casb\t\0" |
| 452 | /* 3857 */ "dsb\t\0" |
| 453 | /* 3862 */ "isb\t\0" |
| 454 | /* 3867 */ "fmsb\t\0" |
| 455 | /* 3873 */ "fnmsb\t\0" |
| 456 | /* 3880 */ "ld1rsb\t\0" |
| 457 | /* 3888 */ "ldrsb\t\0" |
| 458 | /* 3895 */ "ldtrsb\t\0" |
| 459 | /* 3903 */ "ldursb\t\0" |
| 460 | /* 3911 */ "ldapursb\t\0" |
| 461 | /* 3921 */ "tsb\t\0" |
| 462 | /* 3926 */ "ldsetb\t\0" |
| 463 | /* 3934 */ "ssubltb\t\0" |
| 464 | /* 3943 */ "fmlalltb\t\0" |
| 465 | /* 3953 */ "cntb\t\0" |
| 466 | /* 3959 */ "eortb\t\0" |
| 467 | /* 3966 */ "clastb\t\0" |
| 468 | /* 3974 */ "sxtb\t\0" |
| 469 | /* 3980 */ "uxtb\t\0" |
| 470 | /* 3986 */ "bfsub\t\0" |
| 471 | /* 3993 */ "shsub\t\0" |
| 472 | /* 4000 */ "uhsub\t\0" |
| 473 | /* 4007 */ "fmsub\t\0" |
| 474 | /* 4014 */ "fnmsub\t\0" |
| 475 | /* 4022 */ "sqsub\t\0" |
| 476 | /* 4029 */ "uqsub\t\0" |
| 477 | /* 4036 */ "revb\t\0" |
| 478 | /* 4042 */ "ssubwb\t\0" |
| 479 | /* 4050 */ "usubwb\t\0" |
| 480 | /* 4058 */ "saddwb\t\0" |
| 481 | /* 4066 */ "uaddwb\t\0" |
| 482 | /* 4074 */ "ldsmaxb\t\0" |
| 483 | /* 4083 */ "ldumaxb\t\0" |
| 484 | /* 4092 */ "pacdzb\t\0" |
| 485 | /* 4100 */ "autdzb\t\0" |
| 486 | /* 4108 */ "pacizb\t\0" |
| 487 | /* 4116 */ "autizb\t\0" |
| 488 | /* 4124 */ "sbc\t\0" |
| 489 | /* 4129 */ "adc\t\0" |
| 490 | /* 4134 */ "bic\t\0" |
| 491 | /* 4139 */ "aesimc\t\0" |
| 492 | /* 4147 */ "aesmc\t\0" |
| 493 | /* 4154 */ "csinc\t\0" |
| 494 | /* 4161 */ "retaasppc\t\0" |
| 495 | /* 4172 */ "autiasppc\t\0" |
| 496 | /* 4183 */ "retabsppc\t\0" |
| 497 | /* 4194 */ "autibsppc\t\0" |
| 498 | /* 4205 */ "hvc\t\0" |
| 499 | /* 4210 */ "svc\t\0" |
| 500 | /* 4215 */ "fmla.d\t\0" |
| 501 | /* 4223 */ "fmul.d\t\0" |
| 502 | /* 4231 */ "fmls.d\t\0" |
| 503 | /* 4239 */ "ins.d\t\0" |
| 504 | /* 4246 */ "fmov.d\t\0" |
| 505 | /* 4254 */ "umov.d\t\0" |
| 506 | /* 4262 */ "fmulx.d\t\0" |
| 507 | /* 4271 */ "sadalp.1d\t\0" |
| 508 | /* 4282 */ "uadalp.1d\t\0" |
| 509 | /* 4293 */ "saddlp.1d\t\0" |
| 510 | /* 4304 */ "uaddlp.1d\t\0" |
| 511 | /* 4315 */ "ld1d\t\0" |
| 512 | /* 4321 */ "ldff1d\t\0" |
| 513 | /* 4329 */ "ldnf1d\t\0" |
| 514 | /* 4337 */ "ldnt1d\t\0" |
| 515 | /* 4345 */ "stnt1d\t\0" |
| 516 | /* 4353 */ "st1d\t\0" |
| 517 | /* 4359 */ "sha512su0.2d\t\0" |
| 518 | /* 4373 */ "trn1.2d\t\0" |
| 519 | /* 4382 */ "zip1.2d\t\0" |
| 520 | /* 4391 */ "uzp1.2d\t\0" |
| 521 | /* 4400 */ "sha512su1.2d\t\0" |
| 522 | /* 4414 */ "rax1.2d\t\0" |
| 523 | /* 4423 */ "sha512h2.2d\t\0" |
| 524 | /* 4436 */ "sabal2.2d\t\0" |
| 525 | /* 4447 */ "uabal2.2d\t\0" |
| 526 | /* 4458 */ "sqdmlal2.2d\t\0" |
| 527 | /* 4471 */ "smlal2.2d\t\0" |
| 528 | /* 4482 */ "umlal2.2d\t\0" |
| 529 | /* 4493 */ "ssubl2.2d\t\0" |
| 530 | /* 4504 */ "usubl2.2d\t\0" |
| 531 | /* 4515 */ "sabdl2.2d\t\0" |
| 532 | /* 4526 */ "uabdl2.2d\t\0" |
| 533 | /* 4537 */ "saddl2.2d\t\0" |
| 534 | /* 4548 */ "uaddl2.2d\t\0" |
| 535 | /* 4559 */ "sshll2.2d\t\0" |
| 536 | /* 4570 */ "ushll2.2d\t\0" |
| 537 | /* 4581 */ "sqdmull2.2d\t\0" |
| 538 | /* 4594 */ "smull2.2d\t\0" |
| 539 | /* 4605 */ "umull2.2d\t\0" |
| 540 | /* 4616 */ "sqdmlsl2.2d\t\0" |
| 541 | /* 4629 */ "smlsl2.2d\t\0" |
| 542 | /* 4640 */ "umlsl2.2d\t\0" |
| 543 | /* 4651 */ "trn2.2d\t\0" |
| 544 | /* 4660 */ "zip2.2d\t\0" |
| 545 | /* 4669 */ "uzp2.2d\t\0" |
| 546 | /* 4678 */ "ssubw2.2d\t\0" |
| 547 | /* 4689 */ "usubw2.2d\t\0" |
| 548 | /* 4700 */ "saddw2.2d\t\0" |
| 549 | /* 4711 */ "uaddw2.2d\t\0" |
| 550 | /* 4722 */ "fcmla.2d\t\0" |
| 551 | /* 4732 */ "fmla.2d\t\0" |
| 552 | /* 4741 */ "srsra.2d\t\0" |
| 553 | /* 4751 */ "ursra.2d\t\0" |
| 554 | /* 4761 */ "ssra.2d\t\0" |
| 555 | /* 4770 */ "usra.2d\t\0" |
| 556 | /* 4779 */ "frinta.2d\t\0" |
| 557 | /* 4790 */ "fsub.2d\t\0" |
| 558 | /* 4799 */ "sqsub.2d\t\0" |
| 559 | /* 4809 */ "uqsub.2d\t\0" |
| 560 | /* 4819 */ "fabd.2d\t\0" |
| 561 | /* 4828 */ "fcadd.2d\t\0" |
| 562 | /* 4838 */ "fadd.2d\t\0" |
| 563 | /* 4847 */ "usqadd.2d\t\0" |
| 564 | /* 4858 */ "suqadd.2d\t\0" |
| 565 | /* 4869 */ "facge.2d\t\0" |
| 566 | /* 4879 */ "fcmge.2d\t\0" |
| 567 | /* 4889 */ "fscale.2d\t\0" |
| 568 | /* 4900 */ "fcmle.2d\t\0" |
| 569 | /* 4910 */ "frecpe.2d\t\0" |
| 570 | /* 4921 */ "frsqrte.2d\t\0" |
| 571 | /* 4933 */ "scvtf.2d\t\0" |
| 572 | /* 4943 */ "ucvtf.2d\t\0" |
| 573 | /* 4953 */ "fneg.2d\t\0" |
| 574 | /* 4962 */ "sqneg.2d\t\0" |
| 575 | /* 4972 */ "sha512h.2d\t\0" |
| 576 | /* 4984 */ "cmhi.2d\t\0" |
| 577 | /* 4993 */ "sli.2d\t\0" |
| 578 | /* 5001 */ "sri.2d\t\0" |
| 579 | /* 5009 */ "frinti.2d\t\0" |
| 580 | /* 5020 */ "movi.2d\t\0" |
| 581 | /* 5029 */ "sabal.2d\t\0" |
| 582 | /* 5039 */ "uabal.2d\t\0" |
| 583 | /* 5049 */ "sqdmlal.2d\t\0" |
| 584 | /* 5061 */ "smlal.2d\t\0" |
| 585 | /* 5071 */ "umlal.2d\t\0" |
| 586 | /* 5081 */ "ssubl.2d\t\0" |
| 587 | /* 5091 */ "usubl.2d\t\0" |
| 588 | /* 5101 */ "sabdl.2d\t\0" |
| 589 | /* 5111 */ "uabdl.2d\t\0" |
| 590 | /* 5121 */ "saddl.2d\t\0" |
| 591 | /* 5131 */ "uaddl.2d\t\0" |
| 592 | /* 5141 */ "sqshl.2d\t\0" |
| 593 | /* 5151 */ "uqshl.2d\t\0" |
| 594 | /* 5161 */ "sqrshl.2d\t\0" |
| 595 | /* 5172 */ "uqrshl.2d\t\0" |
| 596 | /* 5183 */ "srshl.2d\t\0" |
| 597 | /* 5193 */ "urshl.2d\t\0" |
| 598 | /* 5203 */ "sshl.2d\t\0" |
| 599 | /* 5212 */ "ushl.2d\t\0" |
| 600 | /* 5221 */ "sshll.2d\t\0" |
| 601 | /* 5231 */ "ushll.2d\t\0" |
| 602 | /* 5241 */ "sqdmull.2d\t\0" |
| 603 | /* 5253 */ "smull.2d\t\0" |
| 604 | /* 5263 */ "umull.2d\t\0" |
| 605 | /* 5273 */ "sqdmlsl.2d\t\0" |
| 606 | /* 5285 */ "smlsl.2d\t\0" |
| 607 | /* 5295 */ "umlsl.2d\t\0" |
| 608 | /* 5305 */ "fmul.2d\t\0" |
| 609 | /* 5314 */ "fminnm.2d\t\0" |
| 610 | /* 5325 */ "fmaxnm.2d\t\0" |
| 611 | /* 5336 */ "frintm.2d\t\0" |
| 612 | /* 5347 */ "famin.2d\t\0" |
| 613 | /* 5357 */ "fmin.2d\t\0" |
| 614 | /* 5366 */ "frintn.2d\t\0" |
| 615 | /* 5377 */ "faddp.2d\t\0" |
| 616 | /* 5387 */ "sadalp.2d\t\0" |
| 617 | /* 5398 */ "uadalp.2d\t\0" |
| 618 | /* 5409 */ "saddlp.2d\t\0" |
| 619 | /* 5420 */ "uaddlp.2d\t\0" |
| 620 | /* 5431 */ "fminnmp.2d\t\0" |
| 621 | /* 5443 */ "fmaxnmp.2d\t\0" |
| 622 | /* 5455 */ "fminp.2d\t\0" |
| 623 | /* 5465 */ "frintp.2d\t\0" |
| 624 | /* 5476 */ "dup.2d\t\0" |
| 625 | /* 5484 */ "fmaxp.2d\t\0" |
| 626 | /* 5494 */ "fcmeq.2d\t\0" |
| 627 | /* 5504 */ "xar.2d\t\0" |
| 628 | /* 5512 */ "srshr.2d\t\0" |
| 629 | /* 5522 */ "urshr.2d\t\0" |
| 630 | /* 5532 */ "sshr.2d\t\0" |
| 631 | /* 5541 */ "ushr.2d\t\0" |
| 632 | /* 5550 */ "fcvtas.2d\t\0" |
| 633 | /* 5561 */ "fabs.2d\t\0" |
| 634 | /* 5570 */ "sqabs.2d\t\0" |
| 635 | /* 5580 */ "cmhs.2d\t\0" |
| 636 | /* 5589 */ "fmls.2d\t\0" |
| 637 | /* 5598 */ "fcvtms.2d\t\0" |
| 638 | /* 5609 */ "fcvtns.2d\t\0" |
| 639 | /* 5620 */ "frecps.2d\t\0" |
| 640 | /* 5631 */ "fcvtps.2d\t\0" |
| 641 | /* 5642 */ "frsqrts.2d\t\0" |
| 642 | /* 5654 */ "fcvtzs.2d\t\0" |
| 643 | /* 5665 */ "facgt.2d\t\0" |
| 644 | /* 5675 */ "fcmgt.2d\t\0" |
| 645 | /* 5685 */ "fcmlt.2d\t\0" |
| 646 | /* 5695 */ "fsqrt.2d\t\0" |
| 647 | /* 5705 */ "cmtst.2d\t\0" |
| 648 | /* 5715 */ "fcvtau.2d\t\0" |
| 649 | /* 5726 */ "sqshlu.2d\t\0" |
| 650 | /* 5737 */ "fcvtmu.2d\t\0" |
| 651 | /* 5748 */ "fcvtnu.2d\t\0" |
| 652 | /* 5759 */ "fcvtpu.2d\t\0" |
| 653 | /* 5770 */ "fcvtzu.2d\t\0" |
| 654 | /* 5781 */ "fdiv.2d\t\0" |
| 655 | /* 5790 */ "fmov.2d\t\0" |
| 656 | /* 5799 */ "ssubw.2d\t\0" |
| 657 | /* 5809 */ "usubw.2d\t\0" |
| 658 | /* 5819 */ "saddw.2d\t\0" |
| 659 | /* 5829 */ "uaddw.2d\t\0" |
| 660 | /* 5839 */ "frint32x.2d\t\0" |
| 661 | /* 5852 */ "frint64x.2d\t\0" |
| 662 | /* 5865 */ "famax.2d\t\0" |
| 663 | /* 5875 */ "fmax.2d\t\0" |
| 664 | /* 5884 */ "fmulx.2d\t\0" |
| 665 | /* 5894 */ "frintx.2d\t\0" |
| 666 | /* 5905 */ "frint32z.2d\t\0" |
| 667 | /* 5918 */ "frint64z.2d\t\0" |
| 668 | /* 5931 */ "frintz.2d\t\0" |
| 669 | /* 5942 */ "ld2d\t\0" |
| 670 | /* 5948 */ "st2d\t\0" |
| 671 | /* 5954 */ "ld3d\t\0" |
| 672 | /* 5960 */ "st3d\t\0" |
| 673 | /* 5966 */ "ld4d\t\0" |
| 674 | /* 5972 */ "st4d\t\0" |
| 675 | /* 5978 */ "fmad\t\0" |
| 676 | /* 5984 */ "fnmad\t\0" |
| 677 | /* 5991 */ "ftmad\t\0" |
| 678 | /* 5998 */ "fabd\t\0" |
| 679 | /* 6004 */ "sabd\t\0" |
| 680 | /* 6010 */ "uabd\t\0" |
| 681 | /* 6016 */ "xpacd\t\0" |
| 682 | /* 6023 */ "sqdecd\t\0" |
| 683 | /* 6031 */ "uqdecd\t\0" |
| 684 | /* 6039 */ "sqincd\t\0" |
| 685 | /* 6047 */ "uqincd\t\0" |
| 686 | /* 6055 */ "fcadd\t\0" |
| 687 | /* 6062 */ "sqcadd\t\0" |
| 688 | /* 6070 */ "ldadd\t\0" |
| 689 | /* 6077 */ "bfadd\t\0" |
| 690 | /* 6084 */ "srhadd\t\0" |
| 691 | /* 6092 */ "urhadd\t\0" |
| 692 | /* 6100 */ "shadd\t\0" |
| 693 | /* 6107 */ "uhadd\t\0" |
| 694 | /* 6114 */ "fmadd\t\0" |
| 695 | /* 6121 */ "fnmadd\t\0" |
| 696 | /* 6129 */ "usqadd\t\0" |
| 697 | /* 6137 */ "suqadd\t\0" |
| 698 | /* 6145 */ "prfd\t\0" |
| 699 | /* 6151 */ "nand\t\0" |
| 700 | /* 6157 */ "ld1rod\t\0" |
| 701 | /* 6165 */ "ld1rqd\t\0" |
| 702 | /* 6173 */ "ld1rd\t\0" |
| 703 | /* 6180 */ "asrd\t\0" |
| 704 | /* 6186 */ "aesd\t\0" |
| 705 | /* 6192 */ "cntd\t\0" |
| 706 | /* 6198 */ "revd\t\0" |
| 707 | /* 6204 */ "sm4e\t\0" |
| 708 | /* 6210 */ "splice\t\0" |
| 709 | /* 6218 */ "facge\t\0" |
| 710 | /* 6225 */ "whilege\t\0" |
| 711 | /* 6234 */ "fcmge\t\0" |
| 712 | /* 6241 */ "cmpge\t\0" |
| 713 | /* 6248 */ "fscale\t\0" |
| 714 | /* 6256 */ "whilele\t\0" |
| 715 | /* 6265 */ "fcmle\t\0" |
| 716 | /* 6272 */ "cmple\t\0" |
| 717 | /* 6279 */ "fcmne\t\0" |
| 718 | /* 6286 */ "ctermne\t\0" |
| 719 | /* 6295 */ "cmpne\t\0" |
| 720 | /* 6302 */ "frecpe\t\0" |
| 721 | /* 6310 */ "urecpe\t\0" |
| 722 | /* 6318 */ "fccmpe\t\0" |
| 723 | /* 6326 */ "fcmpe\t\0" |
| 724 | /* 6333 */ "aese\t\0" |
| 725 | /* 6339 */ "pfalse\t\0" |
| 726 | /* 6347 */ "frsqrte\t\0" |
| 727 | /* 6356 */ "ursqrte\t\0" |
| 728 | /* 6365 */ "ptrue\t\0" |
| 729 | /* 6372 */ "udf\t\0" |
| 730 | /* 6377 */ "scvtf\t\0" |
| 731 | /* 6384 */ "ucvtf\t\0" |
| 732 | /* 6391 */ "st2g\t\0" |
| 733 | /* 6397 */ "stz2g\t\0" |
| 734 | /* 6404 */ "subg\t\0" |
| 735 | /* 6410 */ "addg\t\0" |
| 736 | /* 6416 */ "ldg\t\0" |
| 737 | /* 6421 */ "fneg\t\0" |
| 738 | /* 6427 */ "sqneg\t\0" |
| 739 | /* 6434 */ "csneg\t\0" |
| 740 | /* 6441 */ "histseg\t\0" |
| 741 | /* 6450 */ "irg\t\0" |
| 742 | /* 6455 */ "stg\t\0" |
| 743 | /* 6460 */ "stzg\t\0" |
| 744 | /* 6466 */ "fmla.h\t\0" |
| 745 | /* 6474 */ "sqrdmlah.h\t\0" |
| 746 | /* 6486 */ "sqdmulh.h\t\0" |
| 747 | /* 6497 */ "sqrdmulh.h\t\0" |
| 748 | /* 6509 */ "sqrdmlsh.h\t\0" |
| 749 | /* 6521 */ "sqdmlal.h\t\0" |
| 750 | /* 6532 */ "sqdmull.h\t\0" |
| 751 | /* 6543 */ "sqdmlsl.h\t\0" |
| 752 | /* 6554 */ "fmul.h\t\0" |
| 753 | /* 6562 */ "fmls.h\t\0" |
| 754 | /* 6570 */ "ins.h\t\0" |
| 755 | /* 6577 */ "smov.h\t\0" |
| 756 | /* 6585 */ "umov.h\t\0" |
| 757 | /* 6593 */ "fmulx.h\t\0" |
| 758 | /* 6602 */ "sha1h\t\0" |
| 759 | /* 6609 */ "ld1h\t\0" |
| 760 | /* 6615 */ "ldff1h\t\0" |
| 761 | /* 6623 */ "ldnf1h\t\0" |
| 762 | /* 6631 */ "ldnt1h\t\0" |
| 763 | /* 6639 */ "stnt1h\t\0" |
| 764 | /* 6647 */ "st1h\t\0" |
| 765 | /* 6653 */ "faddp.2h\t\0" |
| 766 | /* 6663 */ "fminnmp.2h\t\0" |
| 767 | /* 6675 */ "fmaxnmp.2h\t\0" |
| 768 | /* 6687 */ "fminp.2h\t\0" |
| 769 | /* 6697 */ "fmaxp.2h\t\0" |
| 770 | /* 6707 */ "crc32h\t\0" |
| 771 | /* 6715 */ "ld2h\t\0" |
| 772 | /* 6721 */ "st2h\t\0" |
| 773 | /* 6727 */ "ld3h\t\0" |
| 774 | /* 6733 */ "st3h\t\0" |
| 775 | /* 6739 */ "trn1.4h\t\0" |
| 776 | /* 6748 */ "zip1.4h\t\0" |
| 777 | /* 6757 */ "uzp1.4h\t\0" |
| 778 | /* 6766 */ "rev32.4h\t\0" |
| 779 | /* 6776 */ "trn2.4h\t\0" |
| 780 | /* 6785 */ "zip2.4h\t\0" |
| 781 | /* 6794 */ "uzp2.4h\t\0" |
| 782 | /* 6803 */ "rev64.4h\t\0" |
| 783 | /* 6813 */ "saba.4h\t\0" |
| 784 | /* 6822 */ "uaba.4h\t\0" |
| 785 | /* 6831 */ "fcmla.4h\t\0" |
| 786 | /* 6841 */ "fmla.4h\t\0" |
| 787 | /* 6850 */ "srsra.4h\t\0" |
| 788 | /* 6860 */ "ursra.4h\t\0" |
| 789 | /* 6870 */ "ssra.4h\t\0" |
| 790 | /* 6879 */ "usra.4h\t\0" |
| 791 | /* 6888 */ "frinta.4h\t\0" |
| 792 | /* 6899 */ "fsub.4h\t\0" |
| 793 | /* 6908 */ "shsub.4h\t\0" |
| 794 | /* 6918 */ "uhsub.4h\t\0" |
| 795 | /* 6928 */ "sqsub.4h\t\0" |
| 796 | /* 6938 */ "uqsub.4h\t\0" |
| 797 | /* 6948 */ "bic.4h\t\0" |
| 798 | /* 6956 */ "fabd.4h\t\0" |
| 799 | /* 6965 */ "sabd.4h\t\0" |
| 800 | /* 6974 */ "uabd.4h\t\0" |
| 801 | /* 6983 */ "fcadd.4h\t\0" |
| 802 | /* 6993 */ "fadd.4h\t\0" |
| 803 | /* 7002 */ "srhadd.4h\t\0" |
| 804 | /* 7013 */ "urhadd.4h\t\0" |
| 805 | /* 7024 */ "shadd.4h\t\0" |
| 806 | /* 7034 */ "uhadd.4h\t\0" |
| 807 | /* 7044 */ "usqadd.4h\t\0" |
| 808 | /* 7055 */ "suqadd.4h\t\0" |
| 809 | /* 7066 */ "facge.4h\t\0" |
| 810 | /* 7076 */ "fcmge.4h\t\0" |
| 811 | /* 7086 */ "fscale.4h\t\0" |
| 812 | /* 7097 */ "fcmle.4h\t\0" |
| 813 | /* 7107 */ "frecpe.4h\t\0" |
| 814 | /* 7118 */ "frsqrte.4h\t\0" |
| 815 | /* 7130 */ "scvtf.4h\t\0" |
| 816 | /* 7140 */ "ucvtf.4h\t\0" |
| 817 | /* 7150 */ "fneg.4h\t\0" |
| 818 | /* 7159 */ "sqneg.4h\t\0" |
| 819 | /* 7169 */ "sqrdmlah.4h\t\0" |
| 820 | /* 7182 */ "sqdmulh.4h\t\0" |
| 821 | /* 7194 */ "sqrdmulh.4h\t\0" |
| 822 | /* 7207 */ "sqrdmlsh.4h\t\0" |
| 823 | /* 7220 */ "cmhi.4h\t\0" |
| 824 | /* 7229 */ "sli.4h\t\0" |
| 825 | /* 7237 */ "mvni.4h\t\0" |
| 826 | /* 7246 */ "sri.4h\t\0" |
| 827 | /* 7254 */ "frinti.4h\t\0" |
| 828 | /* 7265 */ "movi.4h\t\0" |
| 829 | /* 7274 */ "sqshl.4h\t\0" |
| 830 | /* 7284 */ "uqshl.4h\t\0" |
| 831 | /* 7294 */ "sqrshl.4h\t\0" |
| 832 | /* 7305 */ "uqrshl.4h\t\0" |
| 833 | /* 7316 */ "srshl.4h\t\0" |
| 834 | /* 7326 */ "urshl.4h\t\0" |
| 835 | /* 7336 */ "sshl.4h\t\0" |
| 836 | /* 7345 */ "ushl.4h\t\0" |
| 837 | /* 7354 */ "fmul.4h\t\0" |
| 838 | /* 7363 */ "fminnm.4h\t\0" |
| 839 | /* 7374 */ "fmaxnm.4h\t\0" |
| 840 | /* 7385 */ "frintm.4h\t\0" |
| 841 | /* 7396 */ "rsubhn.4h\t\0" |
| 842 | /* 7407 */ "raddhn.4h\t\0" |
| 843 | /* 7418 */ "famin.4h\t\0" |
| 844 | /* 7428 */ "fmin.4h\t\0" |
| 845 | /* 7437 */ "smin.4h\t\0" |
| 846 | /* 7446 */ "umin.4h\t\0" |
| 847 | /* 7455 */ "sqshrn.4h\t\0" |
| 848 | /* 7466 */ "uqshrn.4h\t\0" |
| 849 | /* 7477 */ "sqrshrn.4h\t\0" |
| 850 | /* 7489 */ "uqrshrn.4h\t\0" |
| 851 | /* 7501 */ "frintn.4h\t\0" |
| 852 | /* 7512 */ "bfcvtn.4h\t\0" |
| 853 | /* 7523 */ "sqxtn.4h\t\0" |
| 854 | /* 7533 */ "uqxtn.4h\t\0" |
| 855 | /* 7543 */ "sqshrun.4h\t\0" |
| 856 | /* 7555 */ "sqrshrun.4h\t\0" |
| 857 | /* 7568 */ "sqxtun.4h\t\0" |
| 858 | /* 7579 */ "faddp.4h\t\0" |
| 859 | /* 7589 */ "sadalp.4h\t\0" |
| 860 | /* 7600 */ "uadalp.4h\t\0" |
| 861 | /* 7611 */ "saddlp.4h\t\0" |
| 862 | /* 7622 */ "uaddlp.4h\t\0" |
| 863 | /* 7633 */ "fminnmp.4h\t\0" |
| 864 | /* 7645 */ "fmaxnmp.4h\t\0" |
| 865 | /* 7657 */ "fminp.4h\t\0" |
| 866 | /* 7667 */ "sminp.4h\t\0" |
| 867 | /* 7677 */ "uminp.4h\t\0" |
| 868 | /* 7687 */ "frintp.4h\t\0" |
| 869 | /* 7698 */ "dup.4h\t\0" |
| 870 | /* 7706 */ "fmaxp.4h\t\0" |
| 871 | /* 7716 */ "smaxp.4h\t\0" |
| 872 | /* 7726 */ "umaxp.4h\t\0" |
| 873 | /* 7736 */ "fcmeq.4h\t\0" |
| 874 | /* 7746 */ "srshr.4h\t\0" |
| 875 | /* 7756 */ "urshr.4h\t\0" |
| 876 | /* 7766 */ "sshr.4h\t\0" |
| 877 | /* 7775 */ "ushr.4h\t\0" |
| 878 | /* 7784 */ "orr.4h\t\0" |
| 879 | /* 7792 */ "fcvtas.4h\t\0" |
| 880 | /* 7803 */ "fabs.4h\t\0" |
| 881 | /* 7812 */ "sqabs.4h\t\0" |
| 882 | /* 7822 */ "cmhs.4h\t\0" |
| 883 | /* 7831 */ "cls.4h\t\0" |
| 884 | /* 7839 */ "fmls.4h\t\0" |
| 885 | /* 7848 */ "fcvtms.4h\t\0" |
| 886 | /* 7859 */ "fcvtns.4h\t\0" |
| 887 | /* 7870 */ "frecps.4h\t\0" |
| 888 | /* 7881 */ "fcvtps.4h\t\0" |
| 889 | /* 7892 */ "frsqrts.4h\t\0" |
| 890 | /* 7904 */ "fcvtzs.4h\t\0" |
| 891 | /* 7915 */ "facgt.4h\t\0" |
| 892 | /* 7925 */ "fcmgt.4h\t\0" |
| 893 | /* 7935 */ "fcmlt.4h\t\0" |
| 894 | /* 7945 */ "fsqrt.4h\t\0" |
| 895 | /* 7955 */ "cmtst.4h\t\0" |
| 896 | /* 7965 */ "fcvtau.4h\t\0" |
| 897 | /* 7976 */ "sqshlu.4h\t\0" |
| 898 | /* 7987 */ "fcvtmu.4h\t\0" |
| 899 | /* 7998 */ "fcvtnu.4h\t\0" |
| 900 | /* 8009 */ "fcvtpu.4h\t\0" |
| 901 | /* 8020 */ "fcvtzu.4h\t\0" |
| 902 | /* 8031 */ "addv.4h\t\0" |
| 903 | /* 8040 */ "fdiv.4h\t\0" |
| 904 | /* 8049 */ "saddlv.4h\t\0" |
| 905 | /* 8060 */ "uaddlv.4h\t\0" |
| 906 | /* 8071 */ "fminnmv.4h\t\0" |
| 907 | /* 8083 */ "fmaxnmv.4h\t\0" |
| 908 | /* 8095 */ "fminv.4h\t\0" |
| 909 | /* 8105 */ "sminv.4h\t\0" |
| 910 | /* 8115 */ "uminv.4h\t\0" |
| 911 | /* 8125 */ "fmov.4h\t\0" |
| 912 | /* 8134 */ "fmaxv.4h\t\0" |
| 913 | /* 8144 */ "smaxv.4h\t\0" |
| 914 | /* 8154 */ "umaxv.4h\t\0" |
| 915 | /* 8164 */ "famax.4h\t\0" |
| 916 | /* 8174 */ "fmax.4h\t\0" |
| 917 | /* 8183 */ "smax.4h\t\0" |
| 918 | /* 8192 */ "umax.4h\t\0" |
| 919 | /* 8201 */ "fmulx.4h\t\0" |
| 920 | /* 8211 */ "frintx.4h\t\0" |
| 921 | /* 8222 */ "clz.4h\t\0" |
| 922 | /* 8230 */ "frintz.4h\t\0" |
| 923 | /* 8241 */ "ld4h\t\0" |
| 924 | /* 8247 */ "st4h\t\0" |
| 925 | /* 8253 */ "trn1.8h\t\0" |
| 926 | /* 8262 */ "zip1.8h\t\0" |
| 927 | /* 8271 */ "uzp1.8h\t\0" |
| 928 | /* 8280 */ "rev32.8h\t\0" |
| 929 | /* 8290 */ "sabal2.8h\t\0" |
| 930 | /* 8301 */ "uabal2.8h\t\0" |
| 931 | /* 8312 */ "smlal2.8h\t\0" |
| 932 | /* 8323 */ "umlal2.8h\t\0" |
| 933 | /* 8334 */ "ssubl2.8h\t\0" |
| 934 | /* 8345 */ "usubl2.8h\t\0" |
| 935 | /* 8356 */ "sabdl2.8h\t\0" |
| 936 | /* 8367 */ "uabdl2.8h\t\0" |
| 937 | /* 8378 */ "saddl2.8h\t\0" |
| 938 | /* 8389 */ "uaddl2.8h\t\0" |
| 939 | /* 8400 */ "sshll2.8h\t\0" |
| 940 | /* 8411 */ "ushll2.8h\t\0" |
| 941 | /* 8422 */ "pmull2.8h\t\0" |
| 942 | /* 8433 */ "smull2.8h\t\0" |
| 943 | /* 8444 */ "umull2.8h\t\0" |
| 944 | /* 8455 */ "smlsl2.8h\t\0" |
| 945 | /* 8466 */ "umlsl2.8h\t\0" |
| 946 | /* 8477 */ "bf1cvtl2.8h\t\0" |
| 947 | /* 8490 */ "bf2cvtl2.8h\t\0" |
| 948 | /* 8503 */ "rsubhn2.8h\t\0" |
| 949 | /* 8515 */ "raddhn2.8h\t\0" |
| 950 | /* 8527 */ "sqshrn2.8h\t\0" |
| 951 | /* 8539 */ "uqshrn2.8h\t\0" |
| 952 | /* 8551 */ "sqrshrn2.8h\t\0" |
| 953 | /* 8564 */ "uqrshrn2.8h\t\0" |
| 954 | /* 8577 */ "trn2.8h\t\0" |
| 955 | /* 8586 */ "bfcvtn2.8h\t\0" |
| 956 | /* 8598 */ "sqxtn2.8h\t\0" |
| 957 | /* 8609 */ "uqxtn2.8h\t\0" |
| 958 | /* 8620 */ "sqshrun2.8h\t\0" |
| 959 | /* 8633 */ "sqrshrun2.8h\t\0" |
| 960 | /* 8647 */ "sqxtun2.8h\t\0" |
| 961 | /* 8659 */ "zip2.8h\t\0" |
| 962 | /* 8668 */ "uzp2.8h\t\0" |
| 963 | /* 8677 */ "ssubw2.8h\t\0" |
| 964 | /* 8688 */ "usubw2.8h\t\0" |
| 965 | /* 8699 */ "saddw2.8h\t\0" |
| 966 | /* 8710 */ "uaddw2.8h\t\0" |
| 967 | /* 8721 */ "rev64.8h\t\0" |
| 968 | /* 8731 */ "saba.8h\t\0" |
| 969 | /* 8740 */ "uaba.8h\t\0" |
| 970 | /* 8749 */ "fcmla.8h\t\0" |
| 971 | /* 8759 */ "fmla.8h\t\0" |
| 972 | /* 8768 */ "srsra.8h\t\0" |
| 973 | /* 8778 */ "ursra.8h\t\0" |
| 974 | /* 8788 */ "ssra.8h\t\0" |
| 975 | /* 8797 */ "usra.8h\t\0" |
| 976 | /* 8806 */ "frinta.8h\t\0" |
| 977 | /* 8817 */ "fsub.8h\t\0" |
| 978 | /* 8826 */ "shsub.8h\t\0" |
| 979 | /* 8836 */ "uhsub.8h\t\0" |
| 980 | /* 8846 */ "sqsub.8h\t\0" |
| 981 | /* 8856 */ "uqsub.8h\t\0" |
| 982 | /* 8866 */ "bic.8h\t\0" |
| 983 | /* 8874 */ "fabd.8h\t\0" |
| 984 | /* 8883 */ "sabd.8h\t\0" |
| 985 | /* 8892 */ "uabd.8h\t\0" |
| 986 | /* 8901 */ "fcadd.8h\t\0" |
| 987 | /* 8911 */ "fadd.8h\t\0" |
| 988 | /* 8920 */ "srhadd.8h\t\0" |
| 989 | /* 8931 */ "urhadd.8h\t\0" |
| 990 | /* 8942 */ "shadd.8h\t\0" |
| 991 | /* 8952 */ "uhadd.8h\t\0" |
| 992 | /* 8962 */ "usqadd.8h\t\0" |
| 993 | /* 8973 */ "suqadd.8h\t\0" |
| 994 | /* 8984 */ "facge.8h\t\0" |
| 995 | /* 8994 */ "fcmge.8h\t\0" |
| 996 | /* 9004 */ "fscale.8h\t\0" |
| 997 | /* 9015 */ "fcmle.8h\t\0" |
| 998 | /* 9025 */ "frecpe.8h\t\0" |
| 999 | /* 9036 */ "frsqrte.8h\t\0" |
| 1000 | /* 9048 */ "scvtf.8h\t\0" |
| 1001 | /* 9058 */ "ucvtf.8h\t\0" |
| 1002 | /* 9068 */ "fneg.8h\t\0" |
| 1003 | /* 9077 */ "sqneg.8h\t\0" |
| 1004 | /* 9087 */ "sqrdmlah.8h\t\0" |
| 1005 | /* 9100 */ "sqdmulh.8h\t\0" |
| 1006 | /* 9112 */ "sqrdmulh.8h\t\0" |
| 1007 | /* 9125 */ "sqrdmlsh.8h\t\0" |
| 1008 | /* 9138 */ "cmhi.8h\t\0" |
| 1009 | /* 9147 */ "sli.8h\t\0" |
| 1010 | /* 9155 */ "mvni.8h\t\0" |
| 1011 | /* 9164 */ "sri.8h\t\0" |
| 1012 | /* 9172 */ "frinti.8h\t\0" |
| 1013 | /* 9183 */ "movi.8h\t\0" |
| 1014 | /* 9192 */ "sabal.8h\t\0" |
| 1015 | /* 9202 */ "uabal.8h\t\0" |
| 1016 | /* 9212 */ "smlal.8h\t\0" |
| 1017 | /* 9222 */ "umlal.8h\t\0" |
| 1018 | /* 9232 */ "ssubl.8h\t\0" |
| 1019 | /* 9242 */ "usubl.8h\t\0" |
| 1020 | /* 9252 */ "sabdl.8h\t\0" |
| 1021 | /* 9262 */ "uabdl.8h\t\0" |
| 1022 | /* 9272 */ "saddl.8h\t\0" |
| 1023 | /* 9282 */ "uaddl.8h\t\0" |
| 1024 | /* 9292 */ "sqshl.8h\t\0" |
| 1025 | /* 9302 */ "uqshl.8h\t\0" |
| 1026 | /* 9312 */ "sqrshl.8h\t\0" |
| 1027 | /* 9323 */ "uqrshl.8h\t\0" |
| 1028 | /* 9334 */ "srshl.8h\t\0" |
| 1029 | /* 9344 */ "urshl.8h\t\0" |
| 1030 | /* 9354 */ "sshl.8h\t\0" |
| 1031 | /* 9363 */ "ushl.8h\t\0" |
| 1032 | /* 9372 */ "sshll.8h\t\0" |
| 1033 | /* 9382 */ "ushll.8h\t\0" |
| 1034 | /* 9392 */ "pmull.8h\t\0" |
| 1035 | /* 9402 */ "smull.8h\t\0" |
| 1036 | /* 9412 */ "umull.8h\t\0" |
| 1037 | /* 9422 */ "smlsl.8h\t\0" |
| 1038 | /* 9432 */ "umlsl.8h\t\0" |
| 1039 | /* 9442 */ "bf1cvtl.8h\t\0" |
| 1040 | /* 9454 */ "bf2cvtl.8h\t\0" |
| 1041 | /* 9466 */ "fmul.8h\t\0" |
| 1042 | /* 9475 */ "fminnm.8h\t\0" |
| 1043 | /* 9486 */ "fmaxnm.8h\t\0" |
| 1044 | /* 9497 */ "frintm.8h\t\0" |
| 1045 | /* 9508 */ "famin.8h\t\0" |
| 1046 | /* 9518 */ "fmin.8h\t\0" |
| 1047 | /* 9527 */ "smin.8h\t\0" |
| 1048 | /* 9536 */ "umin.8h\t\0" |
| 1049 | /* 9545 */ "frintn.8h\t\0" |
| 1050 | /* 9556 */ "faddp.8h\t\0" |
| 1051 | /* 9566 */ "sadalp.8h\t\0" |
| 1052 | /* 9577 */ "uadalp.8h\t\0" |
| 1053 | /* 9588 */ "saddlp.8h\t\0" |
| 1054 | /* 9599 */ "uaddlp.8h\t\0" |
| 1055 | /* 9610 */ "fminnmp.8h\t\0" |
| 1056 | /* 9622 */ "fmaxnmp.8h\t\0" |
| 1057 | /* 9634 */ "fminp.8h\t\0" |
| 1058 | /* 9644 */ "sminp.8h\t\0" |
| 1059 | /* 9654 */ "uminp.8h\t\0" |
| 1060 | /* 9664 */ "frintp.8h\t\0" |
| 1061 | /* 9675 */ "dup.8h\t\0" |
| 1062 | /* 9683 */ "fmaxp.8h\t\0" |
| 1063 | /* 9693 */ "smaxp.8h\t\0" |
| 1064 | /* 9703 */ "umaxp.8h\t\0" |
| 1065 | /* 9713 */ "fcmeq.8h\t\0" |
| 1066 | /* 9723 */ "srshr.8h\t\0" |
| 1067 | /* 9733 */ "urshr.8h\t\0" |
| 1068 | /* 9743 */ "sshr.8h\t\0" |
| 1069 | /* 9752 */ "ushr.8h\t\0" |
| 1070 | /* 9761 */ "orr.8h\t\0" |
| 1071 | /* 9769 */ "fcvtas.8h\t\0" |
| 1072 | /* 9780 */ "fabs.8h\t\0" |
| 1073 | /* 9789 */ "sqabs.8h\t\0" |
| 1074 | /* 9799 */ "cmhs.8h\t\0" |
| 1075 | /* 9808 */ "cls.8h\t\0" |
| 1076 | /* 9816 */ "fmls.8h\t\0" |
| 1077 | /* 9825 */ "fcvtms.8h\t\0" |
| 1078 | /* 9836 */ "fcvtns.8h\t\0" |
| 1079 | /* 9847 */ "frecps.8h\t\0" |
| 1080 | /* 9858 */ "fcvtps.8h\t\0" |
| 1081 | /* 9869 */ "frsqrts.8h\t\0" |
| 1082 | /* 9881 */ "fcvtzs.8h\t\0" |
| 1083 | /* 9892 */ "facgt.8h\t\0" |
| 1084 | /* 9902 */ "fcmgt.8h\t\0" |
| 1085 | /* 9912 */ "fcmlt.8h\t\0" |
| 1086 | /* 9922 */ "fsqrt.8h\t\0" |
| 1087 | /* 9932 */ "cmtst.8h\t\0" |
| 1088 | /* 9942 */ "fcvtau.8h\t\0" |
| 1089 | /* 9953 */ "sqshlu.8h\t\0" |
| 1090 | /* 9964 */ "fcvtmu.8h\t\0" |
| 1091 | /* 9975 */ "fcvtnu.8h\t\0" |
| 1092 | /* 9986 */ "fcvtpu.8h\t\0" |
| 1093 | /* 9997 */ "fcvtzu.8h\t\0" |
| 1094 | /* 10008 */ "addv.8h\t\0" |
| 1095 | /* 10017 */ "fdiv.8h\t\0" |
| 1096 | /* 10026 */ "saddlv.8h\t\0" |
| 1097 | /* 10037 */ "uaddlv.8h\t\0" |
| 1098 | /* 10048 */ "fminnmv.8h\t\0" |
| 1099 | /* 10060 */ "fmaxnmv.8h\t\0" |
| 1100 | /* 10072 */ "fminv.8h\t\0" |
| 1101 | /* 10082 */ "sminv.8h\t\0" |
| 1102 | /* 10092 */ "uminv.8h\t\0" |
| 1103 | /* 10102 */ "fmov.8h\t\0" |
| 1104 | /* 10111 */ "fmaxv.8h\t\0" |
| 1105 | /* 10121 */ "smaxv.8h\t\0" |
| 1106 | /* 10131 */ "umaxv.8h\t\0" |
| 1107 | /* 10141 */ "ssubw.8h\t\0" |
| 1108 | /* 10151 */ "usubw.8h\t\0" |
| 1109 | /* 10161 */ "saddw.8h\t\0" |
| 1110 | /* 10171 */ "uaddw.8h\t\0" |
| 1111 | /* 10181 */ "famax.8h\t\0" |
| 1112 | /* 10191 */ "fmax.8h\t\0" |
| 1113 | /* 10200 */ "smax.8h\t\0" |
| 1114 | /* 10209 */ "umax.8h\t\0" |
| 1115 | /* 10218 */ "fmulx.8h\t\0" |
| 1116 | /* 10228 */ "frintx.8h\t\0" |
| 1117 | /* 10239 */ "clz.8h\t\0" |
| 1118 | /* 10247 */ "frintz.8h\t\0" |
| 1119 | /* 10258 */ "ldaddah\t\0" |
| 1120 | /* 10267 */ "sqrdcmlah\t\0" |
| 1121 | /* 10278 */ "sqrdmlah\t\0" |
| 1122 | /* 10288 */ "ldsminah\t\0" |
| 1123 | /* 10298 */ "lduminah\t\0" |
| 1124 | /* 10308 */ "swpah\t\0" |
| 1125 | /* 10315 */ "ldclrah\t\0" |
| 1126 | /* 10324 */ "ldeorah\t\0" |
| 1127 | /* 10333 */ "casah\t\0" |
| 1128 | /* 10340 */ "ldsetah\t\0" |
| 1129 | /* 10349 */ "ldsmaxah\t\0" |
| 1130 | /* 10359 */ "ldumaxah\t\0" |
| 1131 | /* 10369 */ "crc32ch\t\0" |
| 1132 | /* 10378 */ "sqdech\t\0" |
| 1133 | /* 10386 */ "uqdech\t\0" |
| 1134 | /* 10394 */ "sqinch\t\0" |
| 1135 | /* 10402 */ "uqinch\t\0" |
| 1136 | /* 10410 */ "nmatch\t\0" |
| 1137 | /* 10418 */ "ldaddh\t\0" |
| 1138 | /* 10426 */ "prfh\t\0" |
| 1139 | /* 10432 */ "ldaddalh\t\0" |
| 1140 | /* 10442 */ "ldsminalh\t\0" |
| 1141 | /* 10453 */ "lduminalh\t\0" |
| 1142 | /* 10464 */ "swpalh\t\0" |
| 1143 | /* 10472 */ "ldclralh\t\0" |
| 1144 | /* 10482 */ "ldeoralh\t\0" |
| 1145 | /* 10492 */ "casalh\t\0" |
| 1146 | /* 10500 */ "ldsetalh\t\0" |
| 1147 | /* 10510 */ "ldsmaxalh\t\0" |
| 1148 | /* 10521 */ "ldumaxalh\t\0" |
| 1149 | /* 10532 */ "ldaddlh\t\0" |
| 1150 | /* 10541 */ "ldsminlh\t\0" |
| 1151 | /* 10551 */ "lduminlh\t\0" |
| 1152 | /* 10561 */ "swplh\t\0" |
| 1153 | /* 10568 */ "ldclrlh\t\0" |
| 1154 | /* 10577 */ "ldeorlh\t\0" |
| 1155 | /* 10586 */ "caslh\t\0" |
| 1156 | /* 10593 */ "ldsetlh\t\0" |
| 1157 | /* 10602 */ "sqdmulh\t\0" |
| 1158 | /* 10611 */ "sqrdmulh\t\0" |
| 1159 | /* 10621 */ "smulh\t\0" |
| 1160 | /* 10628 */ "umulh\t\0" |
| 1161 | /* 10635 */ "ldsmaxlh\t\0" |
| 1162 | /* 10645 */ "ldumaxlh\t\0" |
| 1163 | /* 10655 */ "ldsminh\t\0" |
| 1164 | /* 10664 */ "lduminh\t\0" |
| 1165 | /* 10673 */ "ld1roh\t\0" |
| 1166 | /* 10681 */ "swph\t\0" |
| 1167 | /* 10687 */ "ld1rqh\t\0" |
| 1168 | /* 10695 */ "ld1rh\t\0" |
| 1169 | /* 10702 */ "ldarh\t\0" |
| 1170 | /* 10709 */ "ldlarh\t\0" |
| 1171 | /* 10717 */ "ldrh\t\0" |
| 1172 | /* 10723 */ "ldclrh\t\0" |
| 1173 | /* 10731 */ "stllrh\t\0" |
| 1174 | /* 10739 */ "stlrh\t\0" |
| 1175 | /* 10746 */ "ldeorh\t\0" |
| 1176 | /* 10754 */ "ldaprh\t\0" |
| 1177 | /* 10762 */ "ldtrh\t\0" |
| 1178 | /* 10769 */ "strh\t\0" |
| 1179 | /* 10775 */ "sttrh\t\0" |
| 1180 | /* 10782 */ "ldurh\t\0" |
| 1181 | /* 10789 */ "stlurh\t\0" |
| 1182 | /* 10797 */ "ldapurh\t\0" |
| 1183 | /* 10806 */ "sturh\t\0" |
| 1184 | /* 10813 */ "ldaxrh\t\0" |
| 1185 | /* 10821 */ "ldxrh\t\0" |
| 1186 | /* 10828 */ "stlxrh\t\0" |
| 1187 | /* 10836 */ "stxrh\t\0" |
| 1188 | /* 10843 */ "ld1sh\t\0" |
| 1189 | /* 10850 */ "ldff1sh\t\0" |
| 1190 | /* 10859 */ "ldnf1sh\t\0" |
| 1191 | /* 10868 */ "ldnt1sh\t\0" |
| 1192 | /* 10877 */ "cash\t\0" |
| 1193 | /* 10883 */ "sqrdmlsh\t\0" |
| 1194 | /* 10893 */ "ld1rsh\t\0" |
| 1195 | /* 10901 */ "ldrsh\t\0" |
| 1196 | /* 10908 */ "ldtrsh\t\0" |
| 1197 | /* 10916 */ "ldursh\t\0" |
| 1198 | /* 10924 */ "ldapursh\t\0" |
| 1199 | /* 10934 */ "ldseth\t\0" |
| 1200 | /* 10942 */ "cnth\t\0" |
| 1201 | /* 10948 */ "sxth\t\0" |
| 1202 | /* 10954 */ "uxth\t\0" |
| 1203 | /* 10960 */ "revh\t\0" |
| 1204 | /* 10966 */ "ldsmaxh\t\0" |
| 1205 | /* 10975 */ "ldumaxh\t\0" |
| 1206 | /* 10984 */ "xpaci\t\0" |
| 1207 | /* 10991 */ "whilehi\t\0" |
| 1208 | /* 11000 */ "punpkhi\t\0" |
| 1209 | /* 11009 */ "sunpkhi\t\0" |
| 1210 | /* 11018 */ "uunpkhi\t\0" |
| 1211 | /* 11027 */ "cmhi\t\0" |
| 1212 | /* 11033 */ "cmphi\t\0" |
| 1213 | /* 11040 */ "sli\t\0" |
| 1214 | /* 11045 */ "gmi\t\0" |
| 1215 | /* 11050 */ "sri\t\0" |
| 1216 | /* 11055 */ "frinti\t\0" |
| 1217 | /* 11063 */ "movi\t\0" |
| 1218 | /* 11069 */ "sunpk\t\0" |
| 1219 | /* 11076 */ "uunpk\t\0" |
| 1220 | /* 11083 */ "brk\t\0" |
| 1221 | /* 11088 */ "movk\t\0" |
| 1222 | /* 11094 */ "ldaddal\t\0" |
| 1223 | /* 11103 */ "sqdmlal\t\0" |
| 1224 | /* 11112 */ "bfmlal\t\0" |
| 1225 | /* 11120 */ "smlal\t\0" |
| 1226 | /* 11127 */ "umlal\t\0" |
| 1227 | /* 11134 */ "ldsminal\t\0" |
| 1228 | /* 11144 */ "lduminal\t\0" |
| 1229 | /* 11154 */ "rcwsswppal\t\0" |
| 1230 | /* 11166 */ "rcwswppal\t\0" |
| 1231 | /* 11177 */ "ldclrpal\t\0" |
| 1232 | /* 11187 */ "rcwsclrpal\t\0" |
| 1233 | /* 11199 */ "rcwclrpal\t\0" |
| 1234 | /* 11210 */ "rcwscaspal\t\0" |
| 1235 | /* 11222 */ "rcwcaspal\t\0" |
| 1236 | /* 11233 */ "ldsetpal\t\0" |
| 1237 | /* 11243 */ "rcwssetpal\t\0" |
| 1238 | /* 11255 */ "rcwsetpal\t\0" |
| 1239 | /* 11266 */ "rcwsswpal\t\0" |
| 1240 | /* 11277 */ "rcwswpal\t\0" |
| 1241 | /* 11287 */ "ldclral\t\0" |
| 1242 | /* 11296 */ "rcwsclral\t\0" |
| 1243 | /* 11307 */ "rcwclral\t\0" |
| 1244 | /* 11317 */ "ldeoral\t\0" |
| 1245 | /* 11326 */ "rcwscasal\t\0" |
| 1246 | /* 11337 */ "rcwcasal\t\0" |
| 1247 | /* 11347 */ "ldsetal\t\0" |
| 1248 | /* 11356 */ "rcwssetal\t\0" |
| 1249 | /* 11367 */ "rcwsetal\t\0" |
| 1250 | /* 11377 */ "ldsmaxal\t\0" |
| 1251 | /* 11387 */ "ldumaxal\t\0" |
| 1252 | /* 11397 */ "tbl\t\0" |
| 1253 | /* 11402 */ "smsubl\t\0" |
| 1254 | /* 11410 */ "umsubl\t\0" |
| 1255 | /* 11418 */ "ldaddl\t\0" |
| 1256 | /* 11426 */ "smaddl\t\0" |
| 1257 | /* 11434 */ "umaddl\t\0" |
| 1258 | /* 11442 */ "tcancel\t\0" |
| 1259 | /* 11451 */ "fcsel\t\0" |
| 1260 | /* 11458 */ "psel\t\0" |
| 1261 | /* 11464 */ "ftssel\t\0" |
| 1262 | /* 11472 */ "sqshl\t\0" |
| 1263 | /* 11479 */ "uqshl\t\0" |
| 1264 | /* 11486 */ "sqrshl\t\0" |
| 1265 | /* 11494 */ "uqrshl\t\0" |
| 1266 | /* 11502 */ "srshl\t\0" |
| 1267 | /* 11509 */ "urshl\t\0" |
| 1268 | /* 11516 */ "sshl\t\0" |
| 1269 | /* 11522 */ "ushl\t\0" |
| 1270 | /* 11528 */ "fmlall\t\0" |
| 1271 | /* 11536 */ "usmlall\t\0" |
| 1272 | /* 11545 */ "sumlall\t\0" |
| 1273 | /* 11554 */ "smlsll\t\0" |
| 1274 | /* 11562 */ "umlsll\t\0" |
| 1275 | /* 11570 */ "sqdmull\t\0" |
| 1276 | /* 11579 */ "ldsminl\t\0" |
| 1277 | /* 11588 */ "lduminl\t\0" |
| 1278 | /* 11597 */ "addpl\t\0" |
| 1279 | /* 11604 */ "rcwsswppl\t\0" |
| 1280 | /* 11615 */ "rcwswppl\t\0" |
| 1281 | /* 11625 */ "ldclrpl\t\0" |
| 1282 | /* 11634 */ "rcwsclrpl\t\0" |
| 1283 | /* 11645 */ "rcwclrpl\t\0" |
| 1284 | /* 11655 */ "rcwscaspl\t\0" |
| 1285 | /* 11666 */ "rcwcaspl\t\0" |
| 1286 | /* 11676 */ "addspl\t\0" |
| 1287 | /* 11684 */ "ldsetpl\t\0" |
| 1288 | /* 11693 */ "rcwssetpl\t\0" |
| 1289 | /* 11704 */ "rcwsetpl\t\0" |
| 1290 | /* 11714 */ "rcwsswpl\t\0" |
| 1291 | /* 11724 */ "rcwswpl\t\0" |
| 1292 | /* 11733 */ "ldclrl\t\0" |
| 1293 | /* 11741 */ "rcwsclrl\t\0" |
| 1294 | /* 11751 */ "rcwclrl\t\0" |
| 1295 | /* 11760 */ "ldeorl\t\0" |
| 1296 | /* 11768 */ "rcwscasl\t\0" |
| 1297 | /* 11778 */ "rcwcasl\t\0" |
| 1298 | /* 11787 */ "nbsl\t\0" |
| 1299 | /* 11793 */ "sqdmlsl\t\0" |
| 1300 | /* 11802 */ "bfmlsl\t\0" |
| 1301 | /* 11810 */ "smlsl\t\0" |
| 1302 | /* 11817 */ "umlsl\t\0" |
| 1303 | /* 11824 */ "sysl\t\0" |
| 1304 | /* 11830 */ "ldsetl\t\0" |
| 1305 | /* 11838 */ "rcwssetl\t\0" |
| 1306 | /* 11848 */ "rcwsetl\t\0" |
| 1307 | /* 11857 */ "bf1cvtl\t\0" |
| 1308 | /* 11866 */ "bf2cvtl\t\0" |
| 1309 | /* 11875 */ "fcvtl\t\0" |
| 1310 | /* 11882 */ "bfmul\t\0" |
| 1311 | /* 11889 */ "fnmul\t\0" |
| 1312 | /* 11896 */ "pmul\t\0" |
| 1313 | /* 11902 */ "ftsmul\t\0" |
| 1314 | /* 11910 */ "addvl\t\0" |
| 1315 | /* 11917 */ "rdvl\t\0" |
| 1316 | /* 11923 */ "addsvl\t\0" |
| 1317 | /* 11931 */ "rdsvl\t\0" |
| 1318 | /* 11938 */ "ldsmaxl\t\0" |
| 1319 | /* 11947 */ "ldumaxl\t\0" |
| 1320 | /* 11956 */ "sbfm\t\0" |
| 1321 | /* 11962 */ "ubfm\t\0" |
| 1322 | /* 11968 */ "rprfm\t\0" |
| 1323 | /* 11975 */ "ldgm\t\0" |
| 1324 | /* 11981 */ "stgm\t\0" |
| 1325 | /* 11987 */ "stzgm\t\0" |
| 1326 | /* 11994 */ "gcspushm\t\0" |
| 1327 | /* 12004 */ "bfminnm\t\0" |
| 1328 | /* 12013 */ "bfmaxnm\t\0" |
| 1329 | /* 12022 */ "gcspopm\t\0" |
| 1330 | /* 12031 */ "dupm\t\0" |
| 1331 | /* 12037 */ "frintm\t\0" |
| 1332 | /* 12045 */ "prfum\t\0" |
| 1333 | /* 12052 */ "bsl1n\t\0" |
| 1334 | /* 12059 */ "bsl2n\t\0" |
| 1335 | /* 12066 */ "famin\t\0" |
| 1336 | /* 12073 */ "bfmin\t\0" |
| 1337 | /* 12080 */ "ldsmin\t\0" |
| 1338 | /* 12088 */ "ldumin\t\0" |
| 1339 | /* 12096 */ "brkn\t\0" |
| 1340 | /* 12102 */ "ccmn\t\0" |
| 1341 | /* 12108 */ "eon\t\0" |
| 1342 | /* 12113 */ "sqshrn\t\0" |
| 1343 | /* 12121 */ "uqshrn\t\0" |
| 1344 | /* 12129 */ "sqrshrn\t\0" |
| 1345 | /* 12138 */ "uqrshrn\t\0" |
| 1346 | /* 12147 */ "orn\t\0" |
| 1347 | /* 12152 */ "frintn\t\0" |
| 1348 | /* 12160 */ "bfcvtn\t\0" |
| 1349 | /* 12168 */ "sqcvtn\t\0" |
| 1350 | /* 12176 */ "uqcvtn\t\0" |
| 1351 | /* 12184 */ "sqxtn\t\0" |
| 1352 | /* 12191 */ "uqxtn\t\0" |
| 1353 | /* 12198 */ "sqshrun\t\0" |
| 1354 | /* 12207 */ "sqrshrun\t\0" |
| 1355 | /* 12217 */ "sqcvtun\t\0" |
| 1356 | /* 12226 */ "sqxtun\t\0" |
| 1357 | /* 12234 */ "movn\t\0" |
| 1358 | /* 12240 */ "fcvtxn\t\0" |
| 1359 | /* 12248 */ "whilelo\t\0" |
| 1360 | /* 12257 */ "punpklo\t\0" |
| 1361 | /* 12266 */ "sunpklo\t\0" |
| 1362 | /* 12275 */ "uunpklo\t\0" |
| 1363 | /* 12284 */ "cmplo\t\0" |
| 1364 | /* 12291 */ "zero\t\0" |
| 1365 | /* 12297 */ "fcmuo\t\0" |
| 1366 | /* 12304 */ "subp\t\0" |
| 1367 | /* 12310 */ "sqdecp\t\0" |
| 1368 | /* 12318 */ "uqdecp\t\0" |
| 1369 | /* 12326 */ "sqincp\t\0" |
| 1370 | /* 12334 */ "uqincp\t\0" |
| 1371 | /* 12342 */ "faddp\t\0" |
| 1372 | /* 12349 */ "ldp\t\0" |
| 1373 | /* 12354 */ "bdep\t\0" |
| 1374 | /* 12360 */ "stgp\t\0" |
| 1375 | /* 12366 */ "zip\t\0" |
| 1376 | /* 12371 */ "sadalp\t\0" |
| 1377 | /* 12379 */ "uadalp\t\0" |
| 1378 | /* 12387 */ "stilp\t\0" |
| 1379 | /* 12394 */ "bfclamp\t\0" |
| 1380 | /* 12403 */ "sclamp\t\0" |
| 1381 | /* 12411 */ "uclamp\t\0" |
| 1382 | /* 12419 */ "fccmp\t\0" |
| 1383 | /* 12426 */ "fcmp\t\0" |
| 1384 | /* 12432 */ "fminnmp\t\0" |
| 1385 | /* 12441 */ "fmaxnmp\t\0" |
| 1386 | /* 12450 */ "ldnp\t\0" |
| 1387 | /* 12456 */ "fminp\t\0" |
| 1388 | /* 12463 */ "sminp\t\0" |
| 1389 | /* 12470 */ "uminp\t\0" |
| 1390 | /* 12477 */ "stnp\t\0" |
| 1391 | /* 12483 */ "ldiapp\t\0" |
| 1392 | /* 12491 */ "rcwsswpp\t\0" |
| 1393 | /* 12501 */ "rcwswpp\t\0" |
| 1394 | /* 12510 */ "adrp\t\0" |
| 1395 | /* 12516 */ "bgrp\t\0" |
| 1396 | /* 12522 */ "ldclrp\t\0" |
| 1397 | /* 12530 */ "rcwsclrp\t\0" |
| 1398 | /* 12540 */ "rcwclrp\t\0" |
| 1399 | /* 12549 */ "rcwscasp\t\0" |
| 1400 | /* 12559 */ "rcwcasp\t\0" |
| 1401 | /* 12568 */ "sysp\t\0" |
| 1402 | /* 12574 */ "ldsetp\t\0" |
| 1403 | /* 12582 */ "rcwssetp\t\0" |
| 1404 | /* 12592 */ "rcwsetp\t\0" |
| 1405 | /* 12601 */ "cntp\t\0" |
| 1406 | /* 12607 */ "frintp\t\0" |
| 1407 | /* 12615 */ "stp\t\0" |
| 1408 | /* 12620 */ "fdup\t\0" |
| 1409 | /* 12626 */ "rcwsswp\t\0" |
| 1410 | /* 12635 */ "rcwswp\t\0" |
| 1411 | /* 12643 */ "ldaxp\t\0" |
| 1412 | /* 12650 */ "fmaxp\t\0" |
| 1413 | /* 12657 */ "smaxp\t\0" |
| 1414 | /* 12664 */ "umaxp\t\0" |
| 1415 | /* 12671 */ "ldxp\t\0" |
| 1416 | /* 12677 */ "stlxp\t\0" |
| 1417 | /* 12684 */ "stxp\t\0" |
| 1418 | /* 12690 */ "uzp\t\0" |
| 1419 | /* 12695 */ "pmull2.1q\t\0" |
| 1420 | /* 12706 */ "pmull.1q\t\0" |
| 1421 | /* 12716 */ "ld1q\t\0" |
| 1422 | /* 12722 */ "st1q\t\0" |
| 1423 | /* 12728 */ "ld2q\t\0" |
| 1424 | /* 12734 */ "st2q\t\0" |
| 1425 | /* 12740 */ "ld3q\t\0" |
| 1426 | /* 12746 */ "st3q\t\0" |
| 1427 | /* 12752 */ "ld4q\t\0" |
| 1428 | /* 12758 */ "st4q\t\0" |
| 1429 | /* 12764 */ "fcmeq\t\0" |
| 1430 | /* 12771 */ "ctermeq\t\0" |
| 1431 | /* 12780 */ "cmpeq\t\0" |
| 1432 | /* 12787 */ "tblq\t\0" |
| 1433 | /* 12793 */ "dupq\t\0" |
| 1434 | /* 12799 */ "extq\t\0" |
| 1435 | /* 12805 */ "tbxq\t\0" |
| 1436 | /* 12811 */ "ld1r\t\0" |
| 1437 | /* 12817 */ "ld2r\t\0" |
| 1438 | /* 12823 */ "ld3r\t\0" |
| 1439 | /* 12829 */ "ld4r\t\0" |
| 1440 | /* 12835 */ "ldar\t\0" |
| 1441 | /* 12841 */ "ldlar\t\0" |
| 1442 | /* 12848 */ "xar\t\0" |
| 1443 | /* 12853 */ "fsubr\t\0" |
| 1444 | /* 12860 */ "shsubr\t\0" |
| 1445 | /* 12868 */ "uhsubr\t\0" |
| 1446 | /* 12876 */ "sqsubr\t\0" |
| 1447 | /* 12884 */ "uqsubr\t\0" |
| 1448 | /* 12892 */ "retaasppcr\t\0" |
| 1449 | /* 12904 */ "autiasppcr\t\0" |
| 1450 | /* 12916 */ "retabsppcr\t\0" |
| 1451 | /* 12928 */ "autibsppcr\t\0" |
| 1452 | /* 12940 */ "adr\t\0" |
| 1453 | /* 12945 */ "ldr\t\0" |
| 1454 | /* 12950 */ "rdffr\t\0" |
| 1455 | /* 12957 */ "wrffr\t\0" |
| 1456 | /* 12964 */ "sqrshr\t\0" |
| 1457 | /* 12972 */ "uqrshr\t\0" |
| 1458 | /* 12980 */ "srshr\t\0" |
| 1459 | /* 12987 */ "urshr\t\0" |
| 1460 | /* 12994 */ "sshr\t\0" |
| 1461 | /* 13000 */ "ushr\t\0" |
| 1462 | /* 13006 */ "blr\t\0" |
| 1463 | /* 13011 */ "ldclr\t\0" |
| 1464 | /* 13018 */ "rcwsclr\t\0" |
| 1465 | /* 13027 */ "rcwclr\t\0" |
| 1466 | /* 13035 */ "sqshlr\t\0" |
| 1467 | /* 13043 */ "uqshlr\t\0" |
| 1468 | /* 13051 */ "sqrshlr\t\0" |
| 1469 | /* 13060 */ "uqrshlr\t\0" |
| 1470 | /* 13069 */ "srshlr\t\0" |
| 1471 | /* 13077 */ "urshlr\t\0" |
| 1472 | /* 13085 */ "stllr\t\0" |
| 1473 | /* 13092 */ "lslr\t\0" |
| 1474 | /* 13098 */ "stlr\t\0" |
| 1475 | /* 13104 */ "ldeor\t\0" |
| 1476 | /* 13111 */ "nor\t\0" |
| 1477 | /* 13116 */ "ror\t\0" |
| 1478 | /* 13121 */ "ldapr\t\0" |
| 1479 | /* 13128 */ "orr\t\0" |
| 1480 | /* 13133 */ "asrr\t\0" |
| 1481 | /* 13139 */ "lsrr\t\0" |
| 1482 | /* 13145 */ "msrr\t\0" |
| 1483 | /* 13151 */ "asr\t\0" |
| 1484 | /* 13156 */ "lsr\t\0" |
| 1485 | /* 13161 */ "msr\t\0" |
| 1486 | /* 13166 */ "insr\t\0" |
| 1487 | /* 13172 */ "ldtr\t\0" |
| 1488 | /* 13178 */ "gcsstr\t\0" |
| 1489 | /* 13186 */ "gcssttr\t\0" |
| 1490 | /* 13195 */ "extr\t\0" |
| 1491 | /* 13201 */ "ldur\t\0" |
| 1492 | /* 13207 */ "stlur\t\0" |
| 1493 | /* 13214 */ "ldapur\t\0" |
| 1494 | /* 13222 */ "stur\t\0" |
| 1495 | /* 13228 */ "fdivr\t\0" |
| 1496 | /* 13235 */ "sdivr\t\0" |
| 1497 | /* 13242 */ "udivr\t\0" |
| 1498 | /* 13249 */ "whilewr\t\0" |
| 1499 | /* 13258 */ "ldaxr\t\0" |
| 1500 | /* 13265 */ "ldxr\t\0" |
| 1501 | /* 13271 */ "stlxr\t\0" |
| 1502 | /* 13278 */ "stxr\t\0" |
| 1503 | /* 13284 */ "fmla.s\t\0" |
| 1504 | /* 13292 */ "sqrdmlah.s\t\0" |
| 1505 | /* 13304 */ "sqdmulh.s\t\0" |
| 1506 | /* 13315 */ "sqrdmulh.s\t\0" |
| 1507 | /* 13327 */ "sqrdmlsh.s\t\0" |
| 1508 | /* 13339 */ "sqdmlal.s\t\0" |
| 1509 | /* 13350 */ "sqdmull.s\t\0" |
| 1510 | /* 13361 */ "sqdmlsl.s\t\0" |
| 1511 | /* 13372 */ "fmul.s\t\0" |
| 1512 | /* 13380 */ "fmls.s\t\0" |
| 1513 | /* 13388 */ "ins.s\t\0" |
| 1514 | /* 13395 */ "smov.s\t\0" |
| 1515 | /* 13403 */ "umov.s\t\0" |
| 1516 | /* 13411 */ "fmulx.s\t\0" |
| 1517 | /* 13420 */ "trn1.2s\t\0" |
| 1518 | /* 13429 */ "zip1.2s\t\0" |
| 1519 | /* 13438 */ "uzp1.2s\t\0" |
| 1520 | /* 13447 */ "trn2.2s\t\0" |
| 1521 | /* 13456 */ "zip2.2s\t\0" |
| 1522 | /* 13465 */ "uzp2.2s\t\0" |
| 1523 | /* 13474 */ "rev64.2s\t\0" |
| 1524 | /* 13484 */ "saba.2s\t\0" |
| 1525 | /* 13493 */ "uaba.2s\t\0" |
| 1526 | /* 13502 */ "fcmla.2s\t\0" |
| 1527 | /* 13512 */ "fmla.2s\t\0" |
| 1528 | /* 13521 */ "srsra.2s\t\0" |
| 1529 | /* 13531 */ "ursra.2s\t\0" |
| 1530 | /* 13541 */ "ssra.2s\t\0" |
| 1531 | /* 13550 */ "usra.2s\t\0" |
| 1532 | /* 13559 */ "frinta.2s\t\0" |
| 1533 | /* 13570 */ "fsub.2s\t\0" |
| 1534 | /* 13579 */ "shsub.2s\t\0" |
| 1535 | /* 13589 */ "uhsub.2s\t\0" |
| 1536 | /* 13599 */ "sqsub.2s\t\0" |
| 1537 | /* 13609 */ "uqsub.2s\t\0" |
| 1538 | /* 13619 */ "bic.2s\t\0" |
| 1539 | /* 13627 */ "fabd.2s\t\0" |
| 1540 | /* 13636 */ "sabd.2s\t\0" |
| 1541 | /* 13645 */ "uabd.2s\t\0" |
| 1542 | /* 13654 */ "fcadd.2s\t\0" |
| 1543 | /* 13664 */ "fadd.2s\t\0" |
| 1544 | /* 13673 */ "srhadd.2s\t\0" |
| 1545 | /* 13684 */ "urhadd.2s\t\0" |
| 1546 | /* 13695 */ "shadd.2s\t\0" |
| 1547 | /* 13705 */ "uhadd.2s\t\0" |
| 1548 | /* 13715 */ "usqadd.2s\t\0" |
| 1549 | /* 13726 */ "suqadd.2s\t\0" |
| 1550 | /* 13737 */ "facge.2s\t\0" |
| 1551 | /* 13747 */ "fcmge.2s\t\0" |
| 1552 | /* 13757 */ "fscale.2s\t\0" |
| 1553 | /* 13768 */ "fcmle.2s\t\0" |
| 1554 | /* 13778 */ "frecpe.2s\t\0" |
| 1555 | /* 13789 */ "urecpe.2s\t\0" |
| 1556 | /* 13800 */ "frsqrte.2s\t\0" |
| 1557 | /* 13812 */ "ursqrte.2s\t\0" |
| 1558 | /* 13824 */ "scvtf.2s\t\0" |
| 1559 | /* 13834 */ "ucvtf.2s\t\0" |
| 1560 | /* 13844 */ "fneg.2s\t\0" |
| 1561 | /* 13853 */ "sqneg.2s\t\0" |
| 1562 | /* 13863 */ "sqrdmlah.2s\t\0" |
| 1563 | /* 13876 */ "sqdmulh.2s\t\0" |
| 1564 | /* 13888 */ "sqrdmulh.2s\t\0" |
| 1565 | /* 13901 */ "sqrdmlsh.2s\t\0" |
| 1566 | /* 13914 */ "cmhi.2s\t\0" |
| 1567 | /* 13923 */ "sli.2s\t\0" |
| 1568 | /* 13931 */ "mvni.2s\t\0" |
| 1569 | /* 13940 */ "sri.2s\t\0" |
| 1570 | /* 13948 */ "frinti.2s\t\0" |
| 1571 | /* 13959 */ "movi.2s\t\0" |
| 1572 | /* 13968 */ "sqshl.2s\t\0" |
| 1573 | /* 13978 */ "uqshl.2s\t\0" |
| 1574 | /* 13988 */ "sqrshl.2s\t\0" |
| 1575 | /* 13999 */ "uqrshl.2s\t\0" |
| 1576 | /* 14010 */ "srshl.2s\t\0" |
| 1577 | /* 14020 */ "urshl.2s\t\0" |
| 1578 | /* 14030 */ "sshl.2s\t\0" |
| 1579 | /* 14039 */ "ushl.2s\t\0" |
| 1580 | /* 14048 */ "fmul.2s\t\0" |
| 1581 | /* 14057 */ "fminnm.2s\t\0" |
| 1582 | /* 14068 */ "fmaxnm.2s\t\0" |
| 1583 | /* 14079 */ "frintm.2s\t\0" |
| 1584 | /* 14090 */ "rsubhn.2s\t\0" |
| 1585 | /* 14101 */ "raddhn.2s\t\0" |
| 1586 | /* 14112 */ "famin.2s\t\0" |
| 1587 | /* 14122 */ "fmin.2s\t\0" |
| 1588 | /* 14131 */ "smin.2s\t\0" |
| 1589 | /* 14140 */ "umin.2s\t\0" |
| 1590 | /* 14149 */ "sqshrn.2s\t\0" |
| 1591 | /* 14160 */ "uqshrn.2s\t\0" |
| 1592 | /* 14171 */ "sqrshrn.2s\t\0" |
| 1593 | /* 14183 */ "uqrshrn.2s\t\0" |
| 1594 | /* 14195 */ "frintn.2s\t\0" |
| 1595 | /* 14206 */ "sqxtn.2s\t\0" |
| 1596 | /* 14216 */ "uqxtn.2s\t\0" |
| 1597 | /* 14226 */ "sqshrun.2s\t\0" |
| 1598 | /* 14238 */ "sqrshrun.2s\t\0" |
| 1599 | /* 14251 */ "sqxtun.2s\t\0" |
| 1600 | /* 14262 */ "faddp.2s\t\0" |
| 1601 | /* 14272 */ "sadalp.2s\t\0" |
| 1602 | /* 14283 */ "uadalp.2s\t\0" |
| 1603 | /* 14294 */ "saddlp.2s\t\0" |
| 1604 | /* 14305 */ "uaddlp.2s\t\0" |
| 1605 | /* 14316 */ "fminnmp.2s\t\0" |
| 1606 | /* 14328 */ "fmaxnmp.2s\t\0" |
| 1607 | /* 14340 */ "fminp.2s\t\0" |
| 1608 | /* 14350 */ "sminp.2s\t\0" |
| 1609 | /* 14360 */ "uminp.2s\t\0" |
| 1610 | /* 14370 */ "frintp.2s\t\0" |
| 1611 | /* 14381 */ "dup.2s\t\0" |
| 1612 | /* 14389 */ "fmaxp.2s\t\0" |
| 1613 | /* 14399 */ "smaxp.2s\t\0" |
| 1614 | /* 14409 */ "umaxp.2s\t\0" |
| 1615 | /* 14419 */ "fcmeq.2s\t\0" |
| 1616 | /* 14429 */ "srshr.2s\t\0" |
| 1617 | /* 14439 */ "urshr.2s\t\0" |
| 1618 | /* 14449 */ "sshr.2s\t\0" |
| 1619 | /* 14458 */ "ushr.2s\t\0" |
| 1620 | /* 14467 */ "orr.2s\t\0" |
| 1621 | /* 14475 */ "fcvtas.2s\t\0" |
| 1622 | /* 14486 */ "fabs.2s\t\0" |
| 1623 | /* 14495 */ "sqabs.2s\t\0" |
| 1624 | /* 14505 */ "cmhs.2s\t\0" |
| 1625 | /* 14514 */ "cls.2s\t\0" |
| 1626 | /* 14522 */ "fmls.2s\t\0" |
| 1627 | /* 14531 */ "fcvtms.2s\t\0" |
| 1628 | /* 14542 */ "fcvtns.2s\t\0" |
| 1629 | /* 14553 */ "frecps.2s\t\0" |
| 1630 | /* 14564 */ "fcvtps.2s\t\0" |
| 1631 | /* 14575 */ "frsqrts.2s\t\0" |
| 1632 | /* 14587 */ "fcvtzs.2s\t\0" |
| 1633 | /* 14598 */ "facgt.2s\t\0" |
| 1634 | /* 14608 */ "fcmgt.2s\t\0" |
| 1635 | /* 14618 */ "fcmlt.2s\t\0" |
| 1636 | /* 14628 */ "fsqrt.2s\t\0" |
| 1637 | /* 14638 */ "cmtst.2s\t\0" |
| 1638 | /* 14648 */ "fcvtau.2s\t\0" |
| 1639 | /* 14659 */ "sqshlu.2s\t\0" |
| 1640 | /* 14670 */ "fcvtmu.2s\t\0" |
| 1641 | /* 14681 */ "fcvtnu.2s\t\0" |
| 1642 | /* 14692 */ "fcvtpu.2s\t\0" |
| 1643 | /* 14703 */ "fcvtzu.2s\t\0" |
| 1644 | /* 14714 */ "fdiv.2s\t\0" |
| 1645 | /* 14723 */ "fmov.2s\t\0" |
| 1646 | /* 14732 */ "frint32x.2s\t\0" |
| 1647 | /* 14745 */ "frint64x.2s\t\0" |
| 1648 | /* 14758 */ "famax.2s\t\0" |
| 1649 | /* 14768 */ "fmax.2s\t\0" |
| 1650 | /* 14777 */ "smax.2s\t\0" |
| 1651 | /* 14786 */ "umax.2s\t\0" |
| 1652 | /* 14795 */ "fmulx.2s\t\0" |
| 1653 | /* 14805 */ "frintx.2s\t\0" |
| 1654 | /* 14816 */ "frint32z.2s\t\0" |
| 1655 | /* 14829 */ "frint64z.2s\t\0" |
| 1656 | /* 14842 */ "clz.2s\t\0" |
| 1657 | /* 14850 */ "frintz.2s\t\0" |
| 1658 | /* 14861 */ "sha1su0.4s\t\0" |
| 1659 | /* 14873 */ "sha256su0.4s\t\0" |
| 1660 | /* 14887 */ "trn1.4s\t\0" |
| 1661 | /* 14896 */ "zip1.4s\t\0" |
| 1662 | /* 14905 */ "uzp1.4s\t\0" |
| 1663 | /* 14914 */ "sm3ss1.4s\t\0" |
| 1664 | /* 14925 */ "sha1su1.4s\t\0" |
| 1665 | /* 14937 */ "sha256su1.4s\t\0" |
| 1666 | /* 14951 */ "sm3partw1.4s\t\0" |
| 1667 | /* 14965 */ "sha256h2.4s\t\0" |
| 1668 | /* 14978 */ "sabal2.4s\t\0" |
| 1669 | /* 14989 */ "uabal2.4s\t\0" |
| 1670 | /* 15000 */ "sqdmlal2.4s\t\0" |
| 1671 | /* 15013 */ "smlal2.4s\t\0" |
| 1672 | /* 15024 */ "umlal2.4s\t\0" |
| 1673 | /* 15035 */ "ssubl2.4s\t\0" |
| 1674 | /* 15046 */ "usubl2.4s\t\0" |
| 1675 | /* 15057 */ "sabdl2.4s\t\0" |
| 1676 | /* 15068 */ "uabdl2.4s\t\0" |
| 1677 | /* 15079 */ "saddl2.4s\t\0" |
| 1678 | /* 15090 */ "uaddl2.4s\t\0" |
| 1679 | /* 15101 */ "sshll2.4s\t\0" |
| 1680 | /* 15112 */ "ushll2.4s\t\0" |
| 1681 | /* 15123 */ "sqdmull2.4s\t\0" |
| 1682 | /* 15136 */ "smull2.4s\t\0" |
| 1683 | /* 15147 */ "umull2.4s\t\0" |
| 1684 | /* 15158 */ "sqdmlsl2.4s\t\0" |
| 1685 | /* 15171 */ "smlsl2.4s\t\0" |
| 1686 | /* 15182 */ "umlsl2.4s\t\0" |
| 1687 | /* 15193 */ "rsubhn2.4s\t\0" |
| 1688 | /* 15205 */ "raddhn2.4s\t\0" |
| 1689 | /* 15217 */ "sqshrn2.4s\t\0" |
| 1690 | /* 15229 */ "uqshrn2.4s\t\0" |
| 1691 | /* 15241 */ "sqrshrn2.4s\t\0" |
| 1692 | /* 15254 */ "uqrshrn2.4s\t\0" |
| 1693 | /* 15267 */ "trn2.4s\t\0" |
| 1694 | /* 15276 */ "sqxtn2.4s\t\0" |
| 1695 | /* 15287 */ "uqxtn2.4s\t\0" |
| 1696 | /* 15298 */ "sqshrun2.4s\t\0" |
| 1697 | /* 15311 */ "sqrshrun2.4s\t\0" |
| 1698 | /* 15325 */ "sqxtun2.4s\t\0" |
| 1699 | /* 15337 */ "zip2.4s\t\0" |
| 1700 | /* 15346 */ "uzp2.4s\t\0" |
| 1701 | /* 15355 */ "ssubw2.4s\t\0" |
| 1702 | /* 15366 */ "usubw2.4s\t\0" |
| 1703 | /* 15377 */ "saddw2.4s\t\0" |
| 1704 | /* 15388 */ "uaddw2.4s\t\0" |
| 1705 | /* 15399 */ "sm3partw2.4s\t\0" |
| 1706 | /* 15413 */ "rev64.4s\t\0" |
| 1707 | /* 15423 */ "sm3tt1a.4s\t\0" |
| 1708 | /* 15435 */ "sm3tt2a.4s\t\0" |
| 1709 | /* 15447 */ "saba.4s\t\0" |
| 1710 | /* 15456 */ "uaba.4s\t\0" |
| 1711 | /* 15465 */ "fcmla.4s\t\0" |
| 1712 | /* 15475 */ "fmla.4s\t\0" |
| 1713 | /* 15484 */ "srsra.4s\t\0" |
| 1714 | /* 15494 */ "ursra.4s\t\0" |
| 1715 | /* 15504 */ "ssra.4s\t\0" |
| 1716 | /* 15513 */ "usra.4s\t\0" |
| 1717 | /* 15522 */ "frinta.4s\t\0" |
| 1718 | /* 15533 */ "sm3tt1b.4s\t\0" |
| 1719 | /* 15545 */ "sm3tt2b.4s\t\0" |
| 1720 | /* 15557 */ "fsub.4s\t\0" |
| 1721 | /* 15566 */ "shsub.4s\t\0" |
| 1722 | /* 15576 */ "uhsub.4s\t\0" |
| 1723 | /* 15586 */ "sqsub.4s\t\0" |
| 1724 | /* 15596 */ "uqsub.4s\t\0" |
| 1725 | /* 15606 */ "sha1c.4s\t\0" |
| 1726 | /* 15616 */ "bic.4s\t\0" |
| 1727 | /* 15624 */ "fabd.4s\t\0" |
| 1728 | /* 15633 */ "sabd.4s\t\0" |
| 1729 | /* 15642 */ "uabd.4s\t\0" |
| 1730 | /* 15651 */ "fcadd.4s\t\0" |
| 1731 | /* 15661 */ "fadd.4s\t\0" |
| 1732 | /* 15670 */ "srhadd.4s\t\0" |
| 1733 | /* 15681 */ "urhadd.4s\t\0" |
| 1734 | /* 15692 */ "shadd.4s\t\0" |
| 1735 | /* 15702 */ "uhadd.4s\t\0" |
| 1736 | /* 15712 */ "usqadd.4s\t\0" |
| 1737 | /* 15723 */ "suqadd.4s\t\0" |
| 1738 | /* 15734 */ "sm4e.4s\t\0" |
| 1739 | /* 15743 */ "facge.4s\t\0" |
| 1740 | /* 15753 */ "fcmge.4s\t\0" |
| 1741 | /* 15763 */ "fscale.4s\t\0" |
| 1742 | /* 15774 */ "fcmle.4s\t\0" |
| 1743 | /* 15784 */ "frecpe.4s\t\0" |
| 1744 | /* 15795 */ "urecpe.4s\t\0" |
| 1745 | /* 15806 */ "frsqrte.4s\t\0" |
| 1746 | /* 15818 */ "ursqrte.4s\t\0" |
| 1747 | /* 15830 */ "scvtf.4s\t\0" |
| 1748 | /* 15840 */ "ucvtf.4s\t\0" |
| 1749 | /* 15850 */ "fneg.4s\t\0" |
| 1750 | /* 15859 */ "sqneg.4s\t\0" |
| 1751 | /* 15869 */ "sha256h.4s\t\0" |
| 1752 | /* 15881 */ "sqrdmlah.4s\t\0" |
| 1753 | /* 15894 */ "sqdmulh.4s\t\0" |
| 1754 | /* 15906 */ "sqrdmulh.4s\t\0" |
| 1755 | /* 15919 */ "sqrdmlsh.4s\t\0" |
| 1756 | /* 15932 */ "cmhi.4s\t\0" |
| 1757 | /* 15941 */ "sli.4s\t\0" |
| 1758 | /* 15949 */ "mvni.4s\t\0" |
| 1759 | /* 15958 */ "sri.4s\t\0" |
| 1760 | /* 15966 */ "frinti.4s\t\0" |
| 1761 | /* 15977 */ "movi.4s\t\0" |
| 1762 | /* 15986 */ "sabal.4s\t\0" |
| 1763 | /* 15996 */ "uabal.4s\t\0" |
| 1764 | /* 16006 */ "sqdmlal.4s\t\0" |
| 1765 | /* 16018 */ "smlal.4s\t\0" |
| 1766 | /* 16028 */ "umlal.4s\t\0" |
| 1767 | /* 16038 */ "ssubl.4s\t\0" |
| 1768 | /* 16048 */ "usubl.4s\t\0" |
| 1769 | /* 16058 */ "sabdl.4s\t\0" |
| 1770 | /* 16068 */ "uabdl.4s\t\0" |
| 1771 | /* 16078 */ "saddl.4s\t\0" |
| 1772 | /* 16088 */ "uaddl.4s\t\0" |
| 1773 | /* 16098 */ "sqshl.4s\t\0" |
| 1774 | /* 16108 */ "uqshl.4s\t\0" |
| 1775 | /* 16118 */ "sqrshl.4s\t\0" |
| 1776 | /* 16129 */ "uqrshl.4s\t\0" |
| 1777 | /* 16140 */ "srshl.4s\t\0" |
| 1778 | /* 16150 */ "urshl.4s\t\0" |
| 1779 | /* 16160 */ "sshl.4s\t\0" |
| 1780 | /* 16169 */ "ushl.4s\t\0" |
| 1781 | /* 16178 */ "sshll.4s\t\0" |
| 1782 | /* 16188 */ "ushll.4s\t\0" |
| 1783 | /* 16198 */ "sqdmull.4s\t\0" |
| 1784 | /* 16210 */ "smull.4s\t\0" |
| 1785 | /* 16220 */ "umull.4s\t\0" |
| 1786 | /* 16230 */ "sqdmlsl.4s\t\0" |
| 1787 | /* 16242 */ "smlsl.4s\t\0" |
| 1788 | /* 16252 */ "umlsl.4s\t\0" |
| 1789 | /* 16262 */ "fmul.4s\t\0" |
| 1790 | /* 16271 */ "sha1m.4s\t\0" |
| 1791 | /* 16281 */ "fminnm.4s\t\0" |
| 1792 | /* 16292 */ "fmaxnm.4s\t\0" |
| 1793 | /* 16303 */ "frintm.4s\t\0" |
| 1794 | /* 16314 */ "famin.4s\t\0" |
| 1795 | /* 16324 */ "fmin.4s\t\0" |
| 1796 | /* 16333 */ "smin.4s\t\0" |
| 1797 | /* 16342 */ "umin.4s\t\0" |
| 1798 | /* 16351 */ "frintn.4s\t\0" |
| 1799 | /* 16362 */ "sha1p.4s\t\0" |
| 1800 | /* 16372 */ "faddp.4s\t\0" |
| 1801 | /* 16382 */ "sadalp.4s\t\0" |
| 1802 | /* 16393 */ "uadalp.4s\t\0" |
| 1803 | /* 16404 */ "saddlp.4s\t\0" |
| 1804 | /* 16415 */ "uaddlp.4s\t\0" |
| 1805 | /* 16426 */ "fminnmp.4s\t\0" |
| 1806 | /* 16438 */ "fmaxnmp.4s\t\0" |
| 1807 | /* 16450 */ "fminp.4s\t\0" |
| 1808 | /* 16460 */ "sminp.4s\t\0" |
| 1809 | /* 16470 */ "uminp.4s\t\0" |
| 1810 | /* 16480 */ "frintp.4s\t\0" |
| 1811 | /* 16491 */ "dup.4s\t\0" |
| 1812 | /* 16499 */ "fmaxp.4s\t\0" |
| 1813 | /* 16509 */ "smaxp.4s\t\0" |
| 1814 | /* 16519 */ "umaxp.4s\t\0" |
| 1815 | /* 16529 */ "fcmeq.4s\t\0" |
| 1816 | /* 16539 */ "srshr.4s\t\0" |
| 1817 | /* 16549 */ "urshr.4s\t\0" |
| 1818 | /* 16559 */ "sshr.4s\t\0" |
| 1819 | /* 16568 */ "ushr.4s\t\0" |
| 1820 | /* 16577 */ "orr.4s\t\0" |
| 1821 | /* 16585 */ "fcvtas.4s\t\0" |
| 1822 | /* 16596 */ "fabs.4s\t\0" |
| 1823 | /* 16605 */ "sqabs.4s\t\0" |
| 1824 | /* 16615 */ "cmhs.4s\t\0" |
| 1825 | /* 16624 */ "cls.4s\t\0" |
| 1826 | /* 16632 */ "fmls.4s\t\0" |
| 1827 | /* 16641 */ "fcvtms.4s\t\0" |
| 1828 | /* 16652 */ "fcvtns.4s\t\0" |
| 1829 | /* 16663 */ "frecps.4s\t\0" |
| 1830 | /* 16674 */ "fcvtps.4s\t\0" |
| 1831 | /* 16685 */ "frsqrts.4s\t\0" |
| 1832 | /* 16697 */ "fcvtzs.4s\t\0" |
| 1833 | /* 16708 */ "facgt.4s\t\0" |
| 1834 | /* 16718 */ "fcmgt.4s\t\0" |
| 1835 | /* 16728 */ "fcmlt.4s\t\0" |
| 1836 | /* 16738 */ "fsqrt.4s\t\0" |
| 1837 | /* 16748 */ "cmtst.4s\t\0" |
| 1838 | /* 16758 */ "fcvtau.4s\t\0" |
| 1839 | /* 16769 */ "sqshlu.4s\t\0" |
| 1840 | /* 16780 */ "fcvtmu.4s\t\0" |
| 1841 | /* 16791 */ "fcvtnu.4s\t\0" |
| 1842 | /* 16802 */ "fcvtpu.4s\t\0" |
| 1843 | /* 16813 */ "fcvtzu.4s\t\0" |
| 1844 | /* 16824 */ "addv.4s\t\0" |
| 1845 | /* 16833 */ "fdiv.4s\t\0" |
| 1846 | /* 16842 */ "saddlv.4s\t\0" |
| 1847 | /* 16853 */ "uaddlv.4s\t\0" |
| 1848 | /* 16864 */ "fminnmv.4s\t\0" |
| 1849 | /* 16876 */ "fmaxnmv.4s\t\0" |
| 1850 | /* 16888 */ "fminv.4s\t\0" |
| 1851 | /* 16898 */ "sminv.4s\t\0" |
| 1852 | /* 16908 */ "uminv.4s\t\0" |
| 1853 | /* 16918 */ "fmov.4s\t\0" |
| 1854 | /* 16927 */ "fmaxv.4s\t\0" |
| 1855 | /* 16937 */ "smaxv.4s\t\0" |
| 1856 | /* 16947 */ "umaxv.4s\t\0" |
| 1857 | /* 16957 */ "ssubw.4s\t\0" |
| 1858 | /* 16967 */ "usubw.4s\t\0" |
| 1859 | /* 16977 */ "saddw.4s\t\0" |
| 1860 | /* 16987 */ "uaddw.4s\t\0" |
| 1861 | /* 16997 */ "frint32x.4s\t\0" |
| 1862 | /* 17010 */ "frint64x.4s\t\0" |
| 1863 | /* 17023 */ "famax.4s\t\0" |
| 1864 | /* 17033 */ "fmax.4s\t\0" |
| 1865 | /* 17042 */ "smax.4s\t\0" |
| 1866 | /* 17051 */ "umax.4s\t\0" |
| 1867 | /* 17060 */ "fmulx.4s\t\0" |
| 1868 | /* 17070 */ "frintx.4s\t\0" |
| 1869 | /* 17081 */ "sm4ekey.4s\t\0" |
| 1870 | /* 17093 */ "frint32z.4s\t\0" |
| 1871 | /* 17106 */ "frint64z.4s\t\0" |
| 1872 | /* 17119 */ "clz.4s\t\0" |
| 1873 | /* 17127 */ "frintz.4s\t\0" |
| 1874 | /* 17138 */ "rcwscas\t\0" |
| 1875 | /* 17147 */ "rcwcas\t\0" |
| 1876 | /* 17155 */ "brkas\t\0" |
| 1877 | /* 17162 */ "brkpas\t\0" |
| 1878 | /* 17170 */ "fcvtas\t\0" |
| 1879 | /* 17178 */ "fabs\t\0" |
| 1880 | /* 17184 */ "sqabs\t\0" |
| 1881 | /* 17191 */ "brkbs\t\0" |
| 1882 | /* 17198 */ "brkpbs\t\0" |
| 1883 | /* 17206 */ "subs\t\0" |
| 1884 | /* 17212 */ "sbcs\t\0" |
| 1885 | /* 17218 */ "adcs\t\0" |
| 1886 | /* 17224 */ "bics\t\0" |
| 1887 | /* 17230 */ "adds\t\0" |
| 1888 | /* 17236 */ "nands\t\0" |
| 1889 | /* 17243 */ "ptrues\t\0" |
| 1890 | /* 17251 */ "whilehs\t\0" |
| 1891 | /* 17260 */ "cmhs\t\0" |
| 1892 | /* 17266 */ "cmphs\t\0" |
| 1893 | /* 17273 */ "cls\t\0" |
| 1894 | /* 17278 */ "whilels\t\0" |
| 1895 | /* 17287 */ "bfmls\t\0" |
| 1896 | /* 17294 */ "fnmls\t\0" |
| 1897 | /* 17301 */ "cmpls\t\0" |
| 1898 | /* 17308 */ "fcvtms\t\0" |
| 1899 | /* 17316 */ "brkns\t\0" |
| 1900 | /* 17323 */ "orns\t\0" |
| 1901 | /* 17329 */ "fcvtns\t\0" |
| 1902 | /* 17337 */ "subps\t\0" |
| 1903 | /* 17344 */ "frecps\t\0" |
| 1904 | /* 17352 */ "bmops\t\0" |
| 1905 | /* 17359 */ "bfmops\t\0" |
| 1906 | /* 17367 */ "usmops\t\0" |
| 1907 | /* 17375 */ "sumops\t\0" |
| 1908 | /* 17383 */ "fcvtps\t\0" |
| 1909 | /* 17391 */ "rdffrs\t\0" |
| 1910 | /* 17399 */ "mrs\t\0" |
| 1911 | /* 17404 */ "eors\t\0" |
| 1912 | /* 17410 */ "nors\t\0" |
| 1913 | /* 17416 */ "mrrs\t\0" |
| 1914 | /* 17422 */ "orrs\t\0" |
| 1915 | /* 17428 */ "frsqrts\t\0" |
| 1916 | /* 17437 */ "sys\t\0" |
| 1917 | /* 17442 */ "fcvtzs\t\0" |
| 1918 | /* 17450 */ "fjcvtzs\t\0" |
| 1919 | /* 17459 */ "sqdmlalbt\t\0" |
| 1920 | /* 17470 */ "ssublbt\t\0" |
| 1921 | /* 17479 */ "saddlbt\t\0" |
| 1922 | /* 17488 */ "fmlallbt\t\0" |
| 1923 | /* 17498 */ "sqdmlslbt\t\0" |
| 1924 | /* 17509 */ "eorbt\t\0" |
| 1925 | /* 17516 */ "compact\t\0" |
| 1926 | /* 17525 */ "wfet\t\0" |
| 1927 | /* 17531 */ "ret\t\0" |
| 1928 | /* 17536 */ "ldset\t\0" |
| 1929 | /* 17543 */ "rcwsset\t\0" |
| 1930 | /* 17552 */ "rcwset\t\0" |
| 1931 | /* 17560 */ "facgt\t\0" |
| 1932 | /* 17567 */ "whilegt\t\0" |
| 1933 | /* 17576 */ "fcmgt\t\0" |
| 1934 | /* 17583 */ "cmpgt\t\0" |
| 1935 | /* 17590 */ "rbit\t\0" |
| 1936 | /* 17596 */ "trcit\t\0" |
| 1937 | /* 17603 */ "wfit\t\0" |
| 1938 | /* 17609 */ "sabalt\t\0" |
| 1939 | /* 17617 */ "uabalt\t\0" |
| 1940 | /* 17625 */ "sqdmlalt\t\0" |
| 1941 | /* 17635 */ "bfmlalt\t\0" |
| 1942 | /* 17644 */ "smlalt\t\0" |
| 1943 | /* 17652 */ "umlalt\t\0" |
| 1944 | /* 17660 */ "ssublt\t\0" |
| 1945 | /* 17668 */ "usublt\t\0" |
| 1946 | /* 17676 */ "sbclt\t\0" |
| 1947 | /* 17683 */ "adclt\t\0" |
| 1948 | /* 17690 */ "sabdlt\t\0" |
| 1949 | /* 17698 */ "uabdlt\t\0" |
| 1950 | /* 17706 */ "saddlt\t\0" |
| 1951 | /* 17714 */ "uaddlt\t\0" |
| 1952 | /* 17722 */ "whilelt\t\0" |
| 1953 | /* 17731 */ "hlt\t\0" |
| 1954 | /* 17736 */ "sshllt\t\0" |
| 1955 | /* 17744 */ "ushllt\t\0" |
| 1956 | /* 17752 */ "sqdmullt\t\0" |
| 1957 | /* 17762 */ "pmullt\t\0" |
| 1958 | /* 17770 */ "smullt\t\0" |
| 1959 | /* 17778 */ "umullt\t\0" |
| 1960 | /* 17786 */ "fcmlt\t\0" |
| 1961 | /* 17793 */ "cmplt\t\0" |
| 1962 | /* 17800 */ "sqdmlslt\t\0" |
| 1963 | /* 17810 */ "bfmlslt\t\0" |
| 1964 | /* 17819 */ "smlslt\t\0" |
| 1965 | /* 17827 */ "umlslt\t\0" |
| 1966 | /* 17835 */ "bf1cvtlt\t\0" |
| 1967 | /* 17845 */ "bf2cvtlt\t\0" |
| 1968 | /* 17855 */ "fcvtlt\t\0" |
| 1969 | /* 17863 */ "histcnt\t\0" |
| 1970 | /* 17872 */ "rsubhnt\t\0" |
| 1971 | /* 17881 */ "raddhnt\t\0" |
| 1972 | /* 17890 */ "hint\t\0" |
| 1973 | /* 17896 */ "sqshrnt\t\0" |
| 1974 | /* 17905 */ "uqshrnt\t\0" |
| 1975 | /* 17914 */ "sqrshrnt\t\0" |
| 1976 | /* 17924 */ "uqrshrnt\t\0" |
| 1977 | /* 17934 */ "bfcvtnt\t\0" |
| 1978 | /* 17943 */ "sqxtnt\t\0" |
| 1979 | /* 17951 */ "uqxtnt\t\0" |
| 1980 | /* 17959 */ "sqshrunt\t\0" |
| 1981 | /* 17969 */ "sqrshrunt\t\0" |
| 1982 | /* 17980 */ "sqxtunt\t\0" |
| 1983 | /* 17989 */ "fcvtxnt\t\0" |
| 1984 | /* 17998 */ "cdot\t\0" |
| 1985 | /* 18004 */ "bfdot\t\0" |
| 1986 | /* 18011 */ "usdot\t\0" |
| 1987 | /* 18018 */ "sudot\t\0" |
| 1988 | /* 18025 */ "bfvdot\t\0" |
| 1989 | /* 18033 */ "usvdot\t\0" |
| 1990 | /* 18041 */ "suvdot\t\0" |
| 1991 | /* 18049 */ "cnot\t\0" |
| 1992 | /* 18055 */ "mlapt\t\0" |
| 1993 | /* 18062 */ "msubpt\t\0" |
| 1994 | /* 18070 */ "madpt\t\0" |
| 1995 | /* 18077 */ "maddpt\t\0" |
| 1996 | /* 18085 */ "tstart\t\0" |
| 1997 | /* 18093 */ "fsqrt\t\0" |
| 1998 | /* 18100 */ "ptest\t\0" |
| 1999 | /* 18107 */ "ttest\t\0" |
| 2000 | /* 18114 */ "pfirst\t\0" |
| 2001 | /* 18122 */ "cmtst\t\0" |
| 2002 | /* 18129 */ "fmlalltt\t\0" |
| 2003 | /* 18139 */ "bf1cvt\t\0" |
| 2004 | /* 18147 */ "bf2cvt\t\0" |
| 2005 | /* 18155 */ "bfcvt\t\0" |
| 2006 | /* 18162 */ "sqcvt\t\0" |
| 2007 | /* 18169 */ "uqcvt\t\0" |
| 2008 | /* 18176 */ "movt\t\0" |
| 2009 | /* 18182 */ "ssubwt\t\0" |
| 2010 | /* 18190 */ "usubwt\t\0" |
| 2011 | /* 18198 */ "saddwt\t\0" |
| 2012 | /* 18206 */ "uaddwt\t\0" |
| 2013 | /* 18214 */ "bext\t\0" |
| 2014 | /* 18220 */ "pnext\t\0" |
| 2015 | /* 18227 */ "pext\t\0" |
| 2016 | /* 18233 */ "fcvtau\t\0" |
| 2017 | /* 18241 */ "sqshlu\t\0" |
| 2018 | /* 18249 */ "fcvtmu\t\0" |
| 2019 | /* 18257 */ "fcvtnu\t\0" |
| 2020 | /* 18265 */ "fcvtpu\t\0" |
| 2021 | /* 18273 */ "sqrshru\t\0" |
| 2022 | /* 18282 */ "sqcvtu\t\0" |
| 2023 | /* 18290 */ "fcvtzu\t\0" |
| 2024 | /* 18298 */ "st64bv\t\0" |
| 2025 | /* 18306 */ "faddv\t\0" |
| 2026 | /* 18313 */ "saddv\t\0" |
| 2027 | /* 18320 */ "uaddv\t\0" |
| 2028 | /* 18327 */ "andv\t\0" |
| 2029 | /* 18333 */ "rev\t\0" |
| 2030 | /* 18338 */ "fdiv\t\0" |
| 2031 | /* 18344 */ "sdiv\t\0" |
| 2032 | /* 18350 */ "udiv\t\0" |
| 2033 | /* 18356 */ "fminnmv\t\0" |
| 2034 | /* 18365 */ "fmaxnmv\t\0" |
| 2035 | /* 18374 */ "fminv\t\0" |
| 2036 | /* 18381 */ "sminv\t\0" |
| 2037 | /* 18388 */ "uminv\t\0" |
| 2038 | /* 18395 */ "csinv\t\0" |
| 2039 | /* 18402 */ "fmov\t\0" |
| 2040 | /* 18408 */ "pmov\t\0" |
| 2041 | /* 18414 */ "faddqv\t\0" |
| 2042 | /* 18422 */ "andqv\t\0" |
| 2043 | /* 18429 */ "fminnmqv\t\0" |
| 2044 | /* 18439 */ "fmaxnmqv\t\0" |
| 2045 | /* 18449 */ "fminqv\t\0" |
| 2046 | /* 18457 */ "sminqv\t\0" |
| 2047 | /* 18465 */ "uminqv\t\0" |
| 2048 | /* 18473 */ "eorqv\t\0" |
| 2049 | /* 18480 */ "fmaxqv\t\0" |
| 2050 | /* 18488 */ "smaxqv\t\0" |
| 2051 | /* 18496 */ "umaxqv\t\0" |
| 2052 | /* 18504 */ "eorv\t\0" |
| 2053 | /* 18510 */ "fmaxv\t\0" |
| 2054 | /* 18517 */ "smaxv\t\0" |
| 2055 | /* 18524 */ "umaxv\t\0" |
| 2056 | /* 18531 */ "ld1w\t\0" |
| 2057 | /* 18537 */ "ldff1w\t\0" |
| 2058 | /* 18545 */ "ldnf1w\t\0" |
| 2059 | /* 18553 */ "ldnt1w\t\0" |
| 2060 | /* 18561 */ "stnt1w\t\0" |
| 2061 | /* 18569 */ "st1w\t\0" |
| 2062 | /* 18575 */ "crc32w\t\0" |
| 2063 | /* 18583 */ "ld2w\t\0" |
| 2064 | /* 18589 */ "st2w\t\0" |
| 2065 | /* 18595 */ "ld3w\t\0" |
| 2066 | /* 18601 */ "st3w\t\0" |
| 2067 | /* 18607 */ "ld4w\t\0" |
| 2068 | /* 18613 */ "st4w\t\0" |
| 2069 | /* 18619 */ "crc32cw\t\0" |
| 2070 | /* 18628 */ "sqdecw\t\0" |
| 2071 | /* 18636 */ "uqdecw\t\0" |
| 2072 | /* 18644 */ "sqincw\t\0" |
| 2073 | /* 18652 */ "uqincw\t\0" |
| 2074 | /* 18660 */ "prfw\t\0" |
| 2075 | /* 18666 */ "ld1row\t\0" |
| 2076 | /* 18674 */ "ld1rqw\t\0" |
| 2077 | /* 18682 */ "ld1rw\t\0" |
| 2078 | /* 18689 */ "whilerw\t\0" |
| 2079 | /* 18698 */ "ld1sw\t\0" |
| 2080 | /* 18705 */ "ldff1sw\t\0" |
| 2081 | /* 18714 */ "ldnf1sw\t\0" |
| 2082 | /* 18723 */ "ldnt1sw\t\0" |
| 2083 | /* 18732 */ "ldpsw\t\0" |
| 2084 | /* 18739 */ "ld1rsw\t\0" |
| 2085 | /* 18747 */ "ldrsw\t\0" |
| 2086 | /* 18754 */ "ldtrsw\t\0" |
| 2087 | /* 18762 */ "ldursw\t\0" |
| 2088 | /* 18770 */ "ldapursw\t\0" |
| 2089 | /* 18780 */ "cntw\t\0" |
| 2090 | /* 18786 */ "sxtw\t\0" |
| 2091 | /* 18792 */ "uxtw\t\0" |
| 2092 | /* 18798 */ "revw\t\0" |
| 2093 | /* 18804 */ "crc32x\t\0" |
| 2094 | /* 18812 */ "frint32x\t\0" |
| 2095 | /* 18822 */ "frint64x\t\0" |
| 2096 | /* 18832 */ "bcax\t\0" |
| 2097 | /* 18838 */ "famax\t\0" |
| 2098 | /* 18845 */ "bfmax\t\0" |
| 2099 | /* 18852 */ "ldsmax\t\0" |
| 2100 | /* 18860 */ "ldumax\t\0" |
| 2101 | /* 18868 */ "tbx\t\0" |
| 2102 | /* 18873 */ "crc32cx\t\0" |
| 2103 | /* 18882 */ "index\t\0" |
| 2104 | /* 18889 */ "clrex\t\0" |
| 2105 | /* 18896 */ "movprfx\t\0" |
| 2106 | /* 18905 */ "fmulx\t\0" |
| 2107 | /* 18912 */ "frecpx\t\0" |
| 2108 | /* 18920 */ "frintx\t\0" |
| 2109 | /* 18928 */ "fcvtx\t\0" |
| 2110 | /* 18935 */ "sm4ekey\t\0" |
| 2111 | /* 18944 */ "fcpy\t\0" |
| 2112 | /* 18950 */ "frint32z\t\0" |
| 2113 | /* 18960 */ "frint64z\t\0" |
| 2114 | /* 18970 */ "braaz\t\0" |
| 2115 | /* 18977 */ "blraaz\t\0" |
| 2116 | /* 18985 */ "movaz\t\0" |
| 2117 | /* 18992 */ "brabz\t\0" |
| 2118 | /* 18999 */ "blrabz\t\0" |
| 2119 | /* 19007 */ "cbz\t\0" |
| 2120 | /* 19012 */ "tbz\t\0" |
| 2121 | /* 19017 */ "clz\t\0" |
| 2122 | /* 19022 */ "cbnz\t\0" |
| 2123 | /* 19028 */ "tbnz\t\0" |
| 2124 | /* 19034 */ "ctz\t\0" |
| 2125 | /* 19039 */ "frintz\t\0" |
| 2126 | /* 19047 */ "movz\t\0" |
| 2127 | /* 19053 */ ".tlsdesccall \0" |
| 2128 | /* 19067 */ "zero\t{ \0" |
| 2129 | /* 19075 */ "# XRay Function Patchable RET.\0" |
| 2130 | /* 19106 */ "b.\0" |
| 2131 | /* 19109 */ "bc.\0" |
| 2132 | /* 19113 */ "# XRay Typed Event Log.\0" |
| 2133 | /* 19137 */ "# XRay Custom Event Log.\0" |
| 2134 | /* 19162 */ "# XRay Function Enter.\0" |
| 2135 | /* 19185 */ "# XRay Tail Call Exit.\0" |
| 2136 | /* 19208 */ "# XRay Function Exit.\0" |
| 2137 | /* 19230 */ "hint\t#10\0" |
| 2138 | /* 19239 */ "hint\t#30\0" |
| 2139 | /* 19248 */ "hint\t#40\0" |
| 2140 | /* 19257 */ "hint\t#31\0" |
| 2141 | /* 19266 */ "hint\t#12\0" |
| 2142 | /* 19275 */ "fmlal2\0" |
| 2143 | /* 19282 */ "fmlsl2\0" |
| 2144 | /* 19289 */ "fcvtn2\0" |
| 2145 | /* 19296 */ "hint\t#14\0" |
| 2146 | /* 19305 */ "hint\t#24\0" |
| 2147 | /* 19314 */ "pacia171615\0" |
| 2148 | /* 19326 */ "autia171615\0" |
| 2149 | /* 19338 */ "pacib171615\0" |
| 2150 | /* 19350 */ "autib171615\0" |
| 2151 | /* 19362 */ "hint\t#25\0" |
| 2152 | /* 19371 */ "setf16\0" |
| 2153 | /* 19378 */ "hint\t#26\0" |
| 2154 | /* 19387 */ "hint\t#7\0" |
| 2155 | /* 19395 */ "hint\t#27\0" |
| 2156 | /* 19404 */ "hint\t#8\0" |
| 2157 | /* 19412 */ "hint\t#28\0" |
| 2158 | /* 19421 */ "setf8\0" |
| 2159 | /* 19427 */ "hint\t#29\0" |
| 2160 | /* 19436 */ "hint\t#39\0" |
| 2161 | /* 19445 */ "LIFETIME_END\0" |
| 2162 | /* 19458 */ "PSEUDO_PROBE\0" |
| 2163 | /* 19471 */ "BUNDLE\0" |
| 2164 | /* 19478 */ "DBG_VALUE\0" |
| 2165 | /* 19488 */ "DBG_INSTR_REF\0" |
| 2166 | /* 19502 */ "DBG_PHI\0" |
| 2167 | /* 19510 */ "DBG_LABEL\0" |
| 2168 | /* 19520 */ "LIFETIME_START\0" |
| 2169 | /* 19535 */ "DBG_VALUE_LIST\0" |
| 2170 | /* 19550 */ "cpyfe\t[\0" |
| 2171 | /* 19558 */ "setge\t[\0" |
| 2172 | /* 19566 */ "sete\t[\0" |
| 2173 | /* 19573 */ "cpye\t[\0" |
| 2174 | /* 19580 */ "cpyfm\t[\0" |
| 2175 | /* 19588 */ "setgm\t[\0" |
| 2176 | /* 19596 */ "setm\t[\0" |
| 2177 | /* 19603 */ "cpym\t[\0" |
| 2178 | /* 19610 */ "cpyfen\t[\0" |
| 2179 | /* 19619 */ "setgen\t[\0" |
| 2180 | /* 19628 */ "seten\t[\0" |
| 2181 | /* 19636 */ "cpyen\t[\0" |
| 2182 | /* 19644 */ "cpyfmn\t[\0" |
| 2183 | /* 19653 */ "setgmn\t[\0" |
| 2184 | /* 19662 */ "setmn\t[\0" |
| 2185 | /* 19670 */ "cpymn\t[\0" |
| 2186 | /* 19678 */ "cpyfpn\t[\0" |
| 2187 | /* 19687 */ "setgpn\t[\0" |
| 2188 | /* 19696 */ "setpn\t[\0" |
| 2189 | /* 19704 */ "cpypn\t[\0" |
| 2190 | /* 19712 */ "cpyfern\t[\0" |
| 2191 | /* 19722 */ "cpyern\t[\0" |
| 2192 | /* 19731 */ "cpyfmrn\t[\0" |
| 2193 | /* 19741 */ "cpymrn\t[\0" |
| 2194 | /* 19750 */ "cpyfprn\t[\0" |
| 2195 | /* 19760 */ "cpyprn\t[\0" |
| 2196 | /* 19769 */ "cpyfetrn\t[\0" |
| 2197 | /* 19780 */ "cpyetrn\t[\0" |
| 2198 | /* 19790 */ "cpyfmtrn\t[\0" |
| 2199 | /* 19801 */ "cpymtrn\t[\0" |
| 2200 | /* 19811 */ "cpyfptrn\t[\0" |
| 2201 | /* 19822 */ "cpyptrn\t[\0" |
| 2202 | /* 19832 */ "cpyfertrn\t[\0" |
| 2203 | /* 19844 */ "cpyertrn\t[\0" |
| 2204 | /* 19855 */ "cpyfmrtrn\t[\0" |
| 2205 | /* 19867 */ "cpymrtrn\t[\0" |
| 2206 | /* 19878 */ "cpyfprtrn\t[\0" |
| 2207 | /* 19890 */ "cpyprtrn\t[\0" |
| 2208 | /* 19901 */ "cpyfewtrn\t[\0" |
| 2209 | /* 19913 */ "cpyewtrn\t[\0" |
| 2210 | /* 19924 */ "cpyfmwtrn\t[\0" |
| 2211 | /* 19936 */ "cpymwtrn\t[\0" |
| 2212 | /* 19947 */ "cpyfpwtrn\t[\0" |
| 2213 | /* 19959 */ "cpypwtrn\t[\0" |
| 2214 | /* 19970 */ "cpyfetn\t[\0" |
| 2215 | /* 19980 */ "setgetn\t[\0" |
| 2216 | /* 19990 */ "setetn\t[\0" |
| 2217 | /* 19999 */ "cpyetn\t[\0" |
| 2218 | /* 20008 */ "cpyfmtn\t[\0" |
| 2219 | /* 20018 */ "setgmtn\t[\0" |
| 2220 | /* 20028 */ "setmtn\t[\0" |
| 2221 | /* 20037 */ "cpymtn\t[\0" |
| 2222 | /* 20046 */ "cpyfptn\t[\0" |
| 2223 | /* 20056 */ "setgptn\t[\0" |
| 2224 | /* 20066 */ "setptn\t[\0" |
| 2225 | /* 20075 */ "cpyptn\t[\0" |
| 2226 | /* 20084 */ "cpyfertn\t[\0" |
| 2227 | /* 20095 */ "cpyertn\t[\0" |
| 2228 | /* 20105 */ "cpyfmrtn\t[\0" |
| 2229 | /* 20116 */ "cpymrtn\t[\0" |
| 2230 | /* 20126 */ "cpyfprtn\t[\0" |
| 2231 | /* 20137 */ "cpyprtn\t[\0" |
| 2232 | /* 20147 */ "cpyfewtn\t[\0" |
| 2233 | /* 20158 */ "cpyewtn\t[\0" |
| 2234 | /* 20168 */ "cpyfmwtn\t[\0" |
| 2235 | /* 20179 */ "cpymwtn\t[\0" |
| 2236 | /* 20189 */ "cpyfpwtn\t[\0" |
| 2237 | /* 20200 */ "cpypwtn\t[\0" |
| 2238 | /* 20210 */ "cpyfewn\t[\0" |
| 2239 | /* 20220 */ "cpyewn\t[\0" |
| 2240 | /* 20229 */ "cpyfmwn\t[\0" |
| 2241 | /* 20239 */ "cpymwn\t[\0" |
| 2242 | /* 20248 */ "cpyfpwn\t[\0" |
| 2243 | /* 20258 */ "cpypwn\t[\0" |
| 2244 | /* 20267 */ "cpyfetwn\t[\0" |
| 2245 | /* 20278 */ "cpyetwn\t[\0" |
| 2246 | /* 20288 */ "cpyfmtwn\t[\0" |
| 2247 | /* 20299 */ "cpymtwn\t[\0" |
| 2248 | /* 20309 */ "cpyfptwn\t[\0" |
| 2249 | /* 20320 */ "cpyptwn\t[\0" |
| 2250 | /* 20330 */ "cpyfertwn\t[\0" |
| 2251 | /* 20342 */ "cpyertwn\t[\0" |
| 2252 | /* 20353 */ "cpyfmrtwn\t[\0" |
| 2253 | /* 20365 */ "cpymrtwn\t[\0" |
| 2254 | /* 20376 */ "cpyfprtwn\t[\0" |
| 2255 | /* 20388 */ "cpyprtwn\t[\0" |
| 2256 | /* 20399 */ "cpyfewtwn\t[\0" |
| 2257 | /* 20411 */ "cpyewtwn\t[\0" |
| 2258 | /* 20422 */ "cpyfmwtwn\t[\0" |
| 2259 | /* 20434 */ "cpymwtwn\t[\0" |
| 2260 | /* 20445 */ "cpyfpwtwn\t[\0" |
| 2261 | /* 20457 */ "cpypwtwn\t[\0" |
| 2262 | /* 20468 */ "cpyfp\t[\0" |
| 2263 | /* 20476 */ "setgp\t[\0" |
| 2264 | /* 20484 */ "setp\t[\0" |
| 2265 | /* 20491 */ "cpyp\t[\0" |
| 2266 | /* 20498 */ "cpyfet\t[\0" |
| 2267 | /* 20507 */ "setget\t[\0" |
| 2268 | /* 20516 */ "setet\t[\0" |
| 2269 | /* 20524 */ "cpyet\t[\0" |
| 2270 | /* 20532 */ "cpyfmt\t[\0" |
| 2271 | /* 20541 */ "setgmt\t[\0" |
| 2272 | /* 20550 */ "setmt\t[\0" |
| 2273 | /* 20558 */ "cpymt\t[\0" |
| 2274 | /* 20566 */ "cpyfpt\t[\0" |
| 2275 | /* 20575 */ "setgpt\t[\0" |
| 2276 | /* 20584 */ "setpt\t[\0" |
| 2277 | /* 20592 */ "cpypt\t[\0" |
| 2278 | /* 20600 */ "cpyfert\t[\0" |
| 2279 | /* 20610 */ "cpyert\t[\0" |
| 2280 | /* 20619 */ "cpyfmrt\t[\0" |
| 2281 | /* 20629 */ "cpymrt\t[\0" |
| 2282 | /* 20638 */ "cpyfprt\t[\0" |
| 2283 | /* 20648 */ "cpyprt\t[\0" |
| 2284 | /* 20657 */ "cpyfewt\t[\0" |
| 2285 | /* 20667 */ "cpyewt\t[\0" |
| 2286 | /* 20676 */ "cpyfmwt\t[\0" |
| 2287 | /* 20686 */ "cpymwt\t[\0" |
| 2288 | /* 20695 */ "cpyfpwt\t[\0" |
| 2289 | /* 20705 */ "cpypwt\t[\0" |
| 2290 | /* 20714 */ "eretaa\0" |
| 2291 | /* 20721 */ "bfmmla\0" |
| 2292 | /* 20728 */ "usmmla\0" |
| 2293 | /* 20735 */ "ummla\0" |
| 2294 | /* 20741 */ "eretab\0" |
| 2295 | /* 20748 */ "fmlallbb\0" |
| 2296 | /* 20757 */ "bfmlalb\0" |
| 2297 | /* 20765 */ "sb\0" |
| 2298 | /* 20768 */ "fmlalltb\0" |
| 2299 | /* 20777 */ "fvdotb\0" |
| 2300 | /* 20784 */ "pacnbiasppc\0" |
| 2301 | /* 20796 */ "paciasppc\0" |
| 2302 | /* 20806 */ "pacnbibsppc\0" |
| 2303 | /* 20818 */ "pacibsppc\0" |
| 2304 | /* 20828 */ "rmif\0" |
| 2305 | /* 20833 */ "xaflag\0" |
| 2306 | /* 20840 */ "axflag\0" |
| 2307 | /* 20847 */ "brb\tinj\0" |
| 2308 | /* 20855 */ "fmlal\0" |
| 2309 | /* 20861 */ "# FEntry call\0" |
| 2310 | /* 20875 */ "brb\tiall\0" |
| 2311 | /* 20884 */ "fmlsl\0" |
| 2312 | /* 20890 */ "setffr\0" |
| 2313 | /* 20897 */ "drps\0" |
| 2314 | /* 20902 */ "fmlallbt\0" |
| 2315 | /* 20911 */ "eret\0" |
| 2316 | /* 20916 */ "tcommit\0" |
| 2317 | /* 20924 */ "bfmlalt\0" |
| 2318 | /* 20932 */ "bfdot\0" |
| 2319 | /* 20938 */ "usdot\0" |
| 2320 | /* 20944 */ "udot\0" |
| 2321 | /* 20949 */ "fmlalltt\0" |
| 2322 | /* 20958 */ "fvdott\0" |
| 2323 | /* 20965 */ "cfinv\0" |
| 2324 | /* 20971 */ "gcspopcx\0" |
| 2325 | /* 20980 */ "gcspushx\0" |
| 2326 | /* 20989 */ "gcspopx\0" |
| 2327 | /* 20997 */ "ld1b\t{\0" |
| 2328 | /* 21004 */ "st1b\t{\0" |
| 2329 | /* 21011 */ "ld1d\t{\0" |
| 2330 | /* 21018 */ "st1d\t{\0" |
| 2331 | /* 21025 */ "ld1h\t{\0" |
| 2332 | /* 21032 */ "st1h\t{\0" |
| 2333 | /* 21039 */ "ld1q\t{\0" |
| 2334 | /* 21046 */ "st1q\t{\0" |
| 2335 | /* 21053 */ "ld1w\t{\0" |
| 2336 | /* 21060 */ "st1w\t{\0" |
| 2337 | }; |
| 2338 | #ifdef __GNUC__ |
| 2339 | #pragma GCC diagnostic pop |
| 2340 | #endif |
| 2341 | |
| 2342 | static const uint32_t OpInfo0[] = { |
| 2343 | 0U, // PHI |
| 2344 | 0U, // INLINEASM |
| 2345 | 0U, // INLINEASM_BR |
| 2346 | 0U, // CFI_INSTRUCTION |
| 2347 | 0U, // EH_LABEL |
| 2348 | 0U, // GC_LABEL |
| 2349 | 0U, // ANNOTATION_LABEL |
| 2350 | 0U, // KILL |
| 2351 | 0U, // EXTRACT_SUBREG |
| 2352 | 0U, // INSERT_SUBREG |
| 2353 | 0U, // IMPLICIT_DEF |
| 2354 | 0U, // SUBREG_TO_REG |
| 2355 | 0U, // COPY_TO_REGCLASS |
| 2356 | 19479U, // DBG_VALUE |
| 2357 | 19536U, // DBG_VALUE_LIST |
| 2358 | 19489U, // DBG_INSTR_REF |
| 2359 | 19503U, // DBG_PHI |
| 2360 | 19511U, // DBG_LABEL |
| 2361 | 0U, // REG_SEQUENCE |
| 2362 | 0U, // COPY |
| 2363 | 19472U, // BUNDLE |
| 2364 | 19521U, // LIFETIME_START |
| 2365 | 19446U, // LIFETIME_END |
| 2366 | 19459U, // PSEUDO_PROBE |
| 2367 | 0U, // ARITH_FENCE |
| 2368 | 0U, // STACKMAP |
| 2369 | 20862U, // FENTRY_CALL |
| 2370 | 0U, // PATCHPOINT |
| 2371 | 0U, // LOAD_STACK_GUARD |
| 2372 | 0U, // PREALLOCATED_SETUP |
| 2373 | 0U, // PREALLOCATED_ARG |
| 2374 | 0U, // STATEPOINT |
| 2375 | 0U, // LOCAL_ESCAPE |
| 2376 | 0U, // FAULTING_OP |
| 2377 | 0U, // PATCHABLE_OP |
| 2378 | 19163U, // PATCHABLE_FUNCTION_ENTER |
| 2379 | 19076U, // PATCHABLE_RET |
| 2380 | 19209U, // PATCHABLE_FUNCTION_EXIT |
| 2381 | 19186U, // PATCHABLE_TAIL_CALL |
| 2382 | 19138U, // PATCHABLE_EVENT_CALL |
| 2383 | 19114U, // PATCHABLE_TYPED_EVENT_CALL |
| 2384 | 0U, // ICALL_BRANCH_FUNNEL |
| 2385 | 0U, // MEMBARRIER |
| 2386 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 2387 | 0U, // CONVERGENCECTRL_ENTRY |
| 2388 | 0U, // CONVERGENCECTRL_ANCHOR |
| 2389 | 0U, // CONVERGENCECTRL_LOOP |
| 2390 | 0U, // CONVERGENCECTRL_GLUE |
| 2391 | 0U, // G_ASSERT_SEXT |
| 2392 | 0U, // G_ASSERT_ZEXT |
| 2393 | 0U, // G_ASSERT_ALIGN |
| 2394 | 0U, // G_ADD |
| 2395 | 0U, // G_SUB |
| 2396 | 0U, // G_MUL |
| 2397 | 0U, // G_SDIV |
| 2398 | 0U, // G_UDIV |
| 2399 | 0U, // G_SREM |
| 2400 | 0U, // G_UREM |
| 2401 | 0U, // G_SDIVREM |
| 2402 | 0U, // G_UDIVREM |
| 2403 | 0U, // G_AND |
| 2404 | 0U, // G_OR |
| 2405 | 0U, // G_XOR |
| 2406 | 0U, // G_IMPLICIT_DEF |
| 2407 | 0U, // G_PHI |
| 2408 | 0U, // G_FRAME_INDEX |
| 2409 | 0U, // G_GLOBAL_VALUE |
| 2410 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 2411 | 0U, // G_CONSTANT_POOL |
| 2412 | 0U, // G_EXTRACT |
| 2413 | 0U, // G_UNMERGE_VALUES |
| 2414 | 0U, // G_INSERT |
| 2415 | 0U, // G_MERGE_VALUES |
| 2416 | 0U, // G_BUILD_VECTOR |
| 2417 | 0U, // G_BUILD_VECTOR_TRUNC |
| 2418 | 0U, // G_CONCAT_VECTORS |
| 2419 | 0U, // G_PTRTOINT |
| 2420 | 0U, // G_INTTOPTR |
| 2421 | 0U, // G_BITCAST |
| 2422 | 0U, // G_FREEZE |
| 2423 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 2424 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 2425 | 0U, // G_INTRINSIC_TRUNC |
| 2426 | 0U, // G_INTRINSIC_ROUND |
| 2427 | 0U, // G_INTRINSIC_LRINT |
| 2428 | 0U, // G_INTRINSIC_LLRINT |
| 2429 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 2430 | 0U, // G_READCYCLECOUNTER |
| 2431 | 0U, // G_READSTEADYCOUNTER |
| 2432 | 0U, // G_LOAD |
| 2433 | 0U, // G_SEXTLOAD |
| 2434 | 0U, // G_ZEXTLOAD |
| 2435 | 0U, // G_INDEXED_LOAD |
| 2436 | 0U, // G_INDEXED_SEXTLOAD |
| 2437 | 0U, // G_INDEXED_ZEXTLOAD |
| 2438 | 0U, // G_STORE |
| 2439 | 0U, // G_INDEXED_STORE |
| 2440 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 2441 | 0U, // G_ATOMIC_CMPXCHG |
| 2442 | 0U, // G_ATOMICRMW_XCHG |
| 2443 | 0U, // G_ATOMICRMW_ADD |
| 2444 | 0U, // G_ATOMICRMW_SUB |
| 2445 | 0U, // G_ATOMICRMW_AND |
| 2446 | 0U, // G_ATOMICRMW_NAND |
| 2447 | 0U, // G_ATOMICRMW_OR |
| 2448 | 0U, // G_ATOMICRMW_XOR |
| 2449 | 0U, // G_ATOMICRMW_MAX |
| 2450 | 0U, // G_ATOMICRMW_MIN |
| 2451 | 0U, // G_ATOMICRMW_UMAX |
| 2452 | 0U, // G_ATOMICRMW_UMIN |
| 2453 | 0U, // G_ATOMICRMW_FADD |
| 2454 | 0U, // G_ATOMICRMW_FSUB |
| 2455 | 0U, // G_ATOMICRMW_FMAX |
| 2456 | 0U, // G_ATOMICRMW_FMIN |
| 2457 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 2458 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 2459 | 0U, // G_FENCE |
| 2460 | 0U, // G_PREFETCH |
| 2461 | 0U, // G_BRCOND |
| 2462 | 0U, // G_BRINDIRECT |
| 2463 | 0U, // G_INVOKE_REGION_START |
| 2464 | 0U, // G_INTRINSIC |
| 2465 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 2466 | 0U, // G_INTRINSIC_CONVERGENT |
| 2467 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 2468 | 0U, // G_ANYEXT |
| 2469 | 0U, // G_TRUNC |
| 2470 | 0U, // G_CONSTANT |
| 2471 | 0U, // G_FCONSTANT |
| 2472 | 0U, // G_VASTART |
| 2473 | 0U, // G_VAARG |
| 2474 | 0U, // G_SEXT |
| 2475 | 0U, // G_SEXT_INREG |
| 2476 | 0U, // G_ZEXT |
| 2477 | 0U, // G_SHL |
| 2478 | 0U, // G_LSHR |
| 2479 | 0U, // G_ASHR |
| 2480 | 0U, // G_FSHL |
| 2481 | 0U, // G_FSHR |
| 2482 | 0U, // G_ROTR |
| 2483 | 0U, // G_ROTL |
| 2484 | 0U, // G_ICMP |
| 2485 | 0U, // G_FCMP |
| 2486 | 0U, // G_SCMP |
| 2487 | 0U, // G_UCMP |
| 2488 | 0U, // G_SELECT |
| 2489 | 0U, // G_UADDO |
| 2490 | 0U, // G_UADDE |
| 2491 | 0U, // G_USUBO |
| 2492 | 0U, // G_USUBE |
| 2493 | 0U, // G_SADDO |
| 2494 | 0U, // G_SADDE |
| 2495 | 0U, // G_SSUBO |
| 2496 | 0U, // G_SSUBE |
| 2497 | 0U, // G_UMULO |
| 2498 | 0U, // G_SMULO |
| 2499 | 0U, // G_UMULH |
| 2500 | 0U, // G_SMULH |
| 2501 | 0U, // G_UADDSAT |
| 2502 | 0U, // G_SADDSAT |
| 2503 | 0U, // G_USUBSAT |
| 2504 | 0U, // G_SSUBSAT |
| 2505 | 0U, // G_USHLSAT |
| 2506 | 0U, // G_SSHLSAT |
| 2507 | 0U, // G_SMULFIX |
| 2508 | 0U, // G_UMULFIX |
| 2509 | 0U, // G_SMULFIXSAT |
| 2510 | 0U, // G_UMULFIXSAT |
| 2511 | 0U, // G_SDIVFIX |
| 2512 | 0U, // G_UDIVFIX |
| 2513 | 0U, // G_SDIVFIXSAT |
| 2514 | 0U, // G_UDIVFIXSAT |
| 2515 | 0U, // G_FADD |
| 2516 | 0U, // G_FSUB |
| 2517 | 0U, // G_FMUL |
| 2518 | 0U, // G_FMA |
| 2519 | 0U, // G_FMAD |
| 2520 | 0U, // G_FDIV |
| 2521 | 0U, // G_FREM |
| 2522 | 0U, // G_FPOW |
| 2523 | 0U, // G_FPOWI |
| 2524 | 0U, // G_FEXP |
| 2525 | 0U, // G_FEXP2 |
| 2526 | 0U, // G_FEXP10 |
| 2527 | 0U, // G_FLOG |
| 2528 | 0U, // G_FLOG2 |
| 2529 | 0U, // G_FLOG10 |
| 2530 | 0U, // G_FLDEXP |
| 2531 | 0U, // G_FFREXP |
| 2532 | 0U, // G_FNEG |
| 2533 | 0U, // G_FPEXT |
| 2534 | 0U, // G_FPTRUNC |
| 2535 | 0U, // G_FPTOSI |
| 2536 | 0U, // G_FPTOUI |
| 2537 | 0U, // G_SITOFP |
| 2538 | 0U, // G_UITOFP |
| 2539 | 0U, // G_FABS |
| 2540 | 0U, // G_FCOPYSIGN |
| 2541 | 0U, // G_IS_FPCLASS |
| 2542 | 0U, // G_FCANONICALIZE |
| 2543 | 0U, // G_FMINNUM |
| 2544 | 0U, // G_FMAXNUM |
| 2545 | 0U, // G_FMINNUM_IEEE |
| 2546 | 0U, // G_FMAXNUM_IEEE |
| 2547 | 0U, // G_FMINIMUM |
| 2548 | 0U, // G_FMAXIMUM |
| 2549 | 0U, // G_GET_FPENV |
| 2550 | 0U, // G_SET_FPENV |
| 2551 | 0U, // G_RESET_FPENV |
| 2552 | 0U, // G_GET_FPMODE |
| 2553 | 0U, // G_SET_FPMODE |
| 2554 | 0U, // G_RESET_FPMODE |
| 2555 | 0U, // G_PTR_ADD |
| 2556 | 0U, // G_PTRMASK |
| 2557 | 0U, // G_SMIN |
| 2558 | 0U, // G_SMAX |
| 2559 | 0U, // G_UMIN |
| 2560 | 0U, // G_UMAX |
| 2561 | 0U, // G_ABS |
| 2562 | 0U, // G_LROUND |
| 2563 | 0U, // G_LLROUND |
| 2564 | 0U, // G_BR |
| 2565 | 0U, // G_BRJT |
| 2566 | 0U, // G_VSCALE |
| 2567 | 0U, // G_INSERT_SUBVECTOR |
| 2568 | 0U, // G_EXTRACT_SUBVECTOR |
| 2569 | 0U, // G_INSERT_VECTOR_ELT |
| 2570 | 0U, // G_EXTRACT_VECTOR_ELT |
| 2571 | 0U, // G_SHUFFLE_VECTOR |
| 2572 | 0U, // G_SPLAT_VECTOR |
| 2573 | 0U, // G_VECTOR_COMPRESS |
| 2574 | 0U, // G_CTTZ |
| 2575 | 0U, // G_CTTZ_ZERO_UNDEF |
| 2576 | 0U, // G_CTLZ |
| 2577 | 0U, // G_CTLZ_ZERO_UNDEF |
| 2578 | 0U, // G_CTPOP |
| 2579 | 0U, // G_BSWAP |
| 2580 | 0U, // G_BITREVERSE |
| 2581 | 0U, // G_FCEIL |
| 2582 | 0U, // G_FCOS |
| 2583 | 0U, // G_FSIN |
| 2584 | 0U, // G_FTAN |
| 2585 | 0U, // G_FACOS |
| 2586 | 0U, // G_FASIN |
| 2587 | 0U, // G_FATAN |
| 2588 | 0U, // G_FCOSH |
| 2589 | 0U, // G_FSINH |
| 2590 | 0U, // G_FTANH |
| 2591 | 0U, // G_FSQRT |
| 2592 | 0U, // G_FFLOOR |
| 2593 | 0U, // G_FRINT |
| 2594 | 0U, // G_FNEARBYINT |
| 2595 | 0U, // G_ADDRSPACE_CAST |
| 2596 | 0U, // G_BLOCK_ADDR |
| 2597 | 0U, // G_JUMP_TABLE |
| 2598 | 0U, // G_DYN_STACKALLOC |
| 2599 | 0U, // G_STACKSAVE |
| 2600 | 0U, // G_STACKRESTORE |
| 2601 | 0U, // G_STRICT_FADD |
| 2602 | 0U, // G_STRICT_FSUB |
| 2603 | 0U, // G_STRICT_FMUL |
| 2604 | 0U, // G_STRICT_FDIV |
| 2605 | 0U, // G_STRICT_FREM |
| 2606 | 0U, // G_STRICT_FMA |
| 2607 | 0U, // G_STRICT_FSQRT |
| 2608 | 0U, // G_STRICT_FLDEXP |
| 2609 | 0U, // G_READ_REGISTER |
| 2610 | 0U, // G_WRITE_REGISTER |
| 2611 | 0U, // G_MEMCPY |
| 2612 | 0U, // G_MEMCPY_INLINE |
| 2613 | 0U, // G_MEMMOVE |
| 2614 | 0U, // G_MEMSET |
| 2615 | 0U, // G_BZERO |
| 2616 | 0U, // G_TRAP |
| 2617 | 0U, // G_DEBUGTRAP |
| 2618 | 0U, // G_UBSANTRAP |
| 2619 | 0U, // G_VECREDUCE_SEQ_FADD |
| 2620 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 2621 | 0U, // G_VECREDUCE_FADD |
| 2622 | 0U, // G_VECREDUCE_FMUL |
| 2623 | 0U, // G_VECREDUCE_FMAX |
| 2624 | 0U, // G_VECREDUCE_FMIN |
| 2625 | 0U, // G_VECREDUCE_FMAXIMUM |
| 2626 | 0U, // G_VECREDUCE_FMINIMUM |
| 2627 | 0U, // G_VECREDUCE_ADD |
| 2628 | 0U, // G_VECREDUCE_MUL |
| 2629 | 0U, // G_VECREDUCE_AND |
| 2630 | 0U, // G_VECREDUCE_OR |
| 2631 | 0U, // G_VECREDUCE_XOR |
| 2632 | 0U, // G_VECREDUCE_SMAX |
| 2633 | 0U, // G_VECREDUCE_SMIN |
| 2634 | 0U, // G_VECREDUCE_UMAX |
| 2635 | 0U, // G_VECREDUCE_UMIN |
| 2636 | 0U, // G_SBFX |
| 2637 | 0U, // G_UBFX |
| 2638 | 0U, // ABS_ZPmZ_B_UNDEF |
| 2639 | 0U, // ABS_ZPmZ_D_UNDEF |
| 2640 | 0U, // ABS_ZPmZ_H_UNDEF |
| 2641 | 0U, // ABS_ZPmZ_S_UNDEF |
| 2642 | 0U, // ADDHA_MPPZ_D_PSEUDO_D |
| 2643 | 0U, // ADDHA_MPPZ_S_PSEUDO_S |
| 2644 | 0U, // ADDSWrr |
| 2645 | 0U, // ADDSXrr |
| 2646 | 0U, // ADDVA_MPPZ_D_PSEUDO_D |
| 2647 | 0U, // ADDVA_MPPZ_S_PSEUDO_S |
| 2648 | 0U, // ADDWrr |
| 2649 | 0U, // ADDXrr |
| 2650 | 0U, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 2651 | 0U, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 2652 | 0U, // ADD_VG2_M2ZZ_D_PSEUDO |
| 2653 | 0U, // ADD_VG2_M2ZZ_S_PSEUDO |
| 2654 | 0U, // ADD_VG2_M2Z_D_PSEUDO |
| 2655 | 0U, // ADD_VG2_M2Z_S_PSEUDO |
| 2656 | 0U, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 2657 | 0U, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 2658 | 0U, // ADD_VG4_M4ZZ_D_PSEUDO |
| 2659 | 0U, // ADD_VG4_M4ZZ_S_PSEUDO |
| 2660 | 0U, // ADD_VG4_M4Z_D_PSEUDO |
| 2661 | 0U, // ADD_VG4_M4Z_S_PSEUDO |
| 2662 | 0U, // ADD_ZPZZ_B_ZERO |
| 2663 | 0U, // ADD_ZPZZ_D_ZERO |
| 2664 | 0U, // ADD_ZPZZ_H_ZERO |
| 2665 | 0U, // ADD_ZPZZ_S_ZERO |
| 2666 | 0U, // ADDlowTLS |
| 2667 | 0U, // ADJCALLSTACKDOWN |
| 2668 | 0U, // ADJCALLSTACKUP |
| 2669 | 0U, // AESIMCrrTied |
| 2670 | 0U, // AESMCrrTied |
| 2671 | 0U, // ANDSWrr |
| 2672 | 0U, // ANDSXrr |
| 2673 | 0U, // ANDWrr |
| 2674 | 0U, // ANDXrr |
| 2675 | 0U, // AND_ZPZZ_B_ZERO |
| 2676 | 0U, // AND_ZPZZ_D_ZERO |
| 2677 | 0U, // AND_ZPZZ_H_ZERO |
| 2678 | 0U, // AND_ZPZZ_S_ZERO |
| 2679 | 0U, // ASRD_ZPZI_B_ZERO |
| 2680 | 0U, // ASRD_ZPZI_D_ZERO |
| 2681 | 0U, // ASRD_ZPZI_H_ZERO |
| 2682 | 0U, // ASRD_ZPZI_S_ZERO |
| 2683 | 0U, // ASR_ZPZI_B_UNDEF |
| 2684 | 0U, // ASR_ZPZI_B_ZERO |
| 2685 | 0U, // ASR_ZPZI_D_UNDEF |
| 2686 | 0U, // ASR_ZPZI_D_ZERO |
| 2687 | 0U, // ASR_ZPZI_H_UNDEF |
| 2688 | 0U, // ASR_ZPZI_H_ZERO |
| 2689 | 0U, // ASR_ZPZI_S_UNDEF |
| 2690 | 0U, // ASR_ZPZI_S_ZERO |
| 2691 | 0U, // ASR_ZPZZ_B_UNDEF |
| 2692 | 0U, // ASR_ZPZZ_B_ZERO |
| 2693 | 0U, // ASR_ZPZZ_D_UNDEF |
| 2694 | 0U, // ASR_ZPZZ_D_ZERO |
| 2695 | 0U, // ASR_ZPZZ_H_UNDEF |
| 2696 | 0U, // ASR_ZPZZ_H_ZERO |
| 2697 | 0U, // ASR_ZPZZ_S_UNDEF |
| 2698 | 0U, // ASR_ZPZZ_S_ZERO |
| 2699 | 0U, // AUT |
| 2700 | 0U, // AUTH_TCRETURN |
| 2701 | 0U, // AUTH_TCRETURN_BTI |
| 2702 | 0U, // AUTPAC |
| 2703 | 0U, // AllocateZABuffer |
| 2704 | 0U, // BFADD_VG2_M2Z_H_PSEUDO |
| 2705 | 0U, // BFADD_VG4_M4Z_H_PSEUDO |
| 2706 | 0U, // BFADD_ZPZZ_UNDEF |
| 2707 | 0U, // BFADD_ZPZZ_ZERO |
| 2708 | 0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2709 | 0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2710 | 0U, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2711 | 0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2712 | 0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 2713 | 0U, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2714 | 0U, // BFMAXNM_ZPZZ_UNDEF |
| 2715 | 0U, // BFMAXNM_ZPZZ_ZERO |
| 2716 | 0U, // BFMAX_ZPZZ_UNDEF |
| 2717 | 0U, // BFMAX_ZPZZ_ZERO |
| 2718 | 0U, // BFMINNM_ZPZZ_UNDEF |
| 2719 | 0U, // BFMINNM_ZPZZ_ZERO |
| 2720 | 0U, // BFMIN_ZPZZ_UNDEF |
| 2721 | 0U, // BFMIN_ZPZZ_ZERO |
| 2722 | 0U, // BFMLAL_MZZI_HtoS_PSEUDO |
| 2723 | 0U, // BFMLAL_MZZ_HtoS_PSEUDO |
| 2724 | 0U, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2725 | 0U, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 2726 | 0U, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2727 | 0U, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2728 | 0U, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2729 | 0U, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2730 | 0U, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 2731 | 0U, // BFMLA_VG2_M2ZZI_PSEUDO |
| 2732 | 0U, // BFMLA_VG2_M2ZZ_PSEUDO |
| 2733 | 0U, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 2734 | 0U, // BFMLA_VG4_M4ZZI_PSEUDO |
| 2735 | 0U, // BFMLA_VG4_M4ZZ_PSEUDO |
| 2736 | 0U, // BFMLA_ZPZZZ_UNDEF |
| 2737 | 0U, // BFMLSL_MZZI_HtoS_PSEUDO |
| 2738 | 0U, // BFMLSL_MZZ_HtoS_PSEUDO |
| 2739 | 0U, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2740 | 0U, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 2741 | 0U, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 2742 | 0U, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2743 | 0U, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 2744 | 0U, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 2745 | 0U, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 2746 | 0U, // BFMLS_VG2_M2ZZI_PSEUDO |
| 2747 | 0U, // BFMLS_VG2_M2ZZ_PSEUDO |
| 2748 | 0U, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 2749 | 0U, // BFMLS_VG4_M4ZZI_PSEUDO |
| 2750 | 0U, // BFMLS_VG4_M4ZZ_PSEUDO |
| 2751 | 0U, // BFMLS_ZPZZZ_UNDEF |
| 2752 | 0U, // BFMOPA_MPPZZ_H_PSEUDO |
| 2753 | 0U, // BFMOPA_MPPZZ_PSEUDO |
| 2754 | 0U, // BFMOPS_MPPZZ_H_PSEUDO |
| 2755 | 0U, // BFMOPS_MPPZZ_PSEUDO |
| 2756 | 0U, // BFMUL_ZPZZ_UNDEF |
| 2757 | 0U, // BFMUL_ZPZZ_ZERO |
| 2758 | 0U, // BFSUB_VG2_M2Z_H_PSEUDO |
| 2759 | 0U, // BFSUB_VG4_M4Z_H_PSEUDO |
| 2760 | 0U, // BFSUB_ZPZZ_UNDEF |
| 2761 | 0U, // BFSUB_ZPZZ_ZERO |
| 2762 | 0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2763 | 0U, // BICSWrr |
| 2764 | 0U, // BICSXrr |
| 2765 | 0U, // BICWrr |
| 2766 | 0U, // BICXrr |
| 2767 | 0U, // BIC_ZPZZ_B_ZERO |
| 2768 | 0U, // BIC_ZPZZ_D_ZERO |
| 2769 | 0U, // BIC_ZPZZ_H_ZERO |
| 2770 | 0U, // BIC_ZPZZ_S_ZERO |
| 2771 | 0U, // BLRA |
| 2772 | 0U, // BLRA_RVMARKER |
| 2773 | 0U, // BLRNoIP |
| 2774 | 0U, // BLR_BTI |
| 2775 | 0U, // BLR_RVMARKER |
| 2776 | 0U, // BLR_X16 |
| 2777 | 0U, // BMOPA_MPPZZ_S_PSEUDO |
| 2778 | 0U, // BMOPS_MPPZZ_S_PSEUDO |
| 2779 | 0U, // BRA |
| 2780 | 0U, // BR_JumpTable |
| 2781 | 0U, // BSPv16i8 |
| 2782 | 0U, // BSPv8i8 |
| 2783 | 0U, // CATCHRET |
| 2784 | 0U, // CLEANUPRET |
| 2785 | 0U, // CLS_ZPmZ_B_UNDEF |
| 2786 | 0U, // CLS_ZPmZ_D_UNDEF |
| 2787 | 0U, // CLS_ZPmZ_H_UNDEF |
| 2788 | 0U, // CLS_ZPmZ_S_UNDEF |
| 2789 | 0U, // CLZ_ZPmZ_B_UNDEF |
| 2790 | 0U, // CLZ_ZPmZ_D_UNDEF |
| 2791 | 0U, // CLZ_ZPmZ_H_UNDEF |
| 2792 | 0U, // CLZ_ZPmZ_S_UNDEF |
| 2793 | 0U, // CMP_SWAP_128 |
| 2794 | 0U, // CMP_SWAP_128_ACQUIRE |
| 2795 | 0U, // CMP_SWAP_128_MONOTONIC |
| 2796 | 0U, // CMP_SWAP_128_RELEASE |
| 2797 | 0U, // CMP_SWAP_16 |
| 2798 | 0U, // CMP_SWAP_32 |
| 2799 | 0U, // CMP_SWAP_64 |
| 2800 | 0U, // CMP_SWAP_8 |
| 2801 | 0U, // CNOT_ZPmZ_B_UNDEF |
| 2802 | 0U, // CNOT_ZPmZ_D_UNDEF |
| 2803 | 0U, // CNOT_ZPmZ_H_UNDEF |
| 2804 | 0U, // CNOT_ZPmZ_S_UNDEF |
| 2805 | 0U, // CNT_ZPmZ_B_UNDEF |
| 2806 | 0U, // CNT_ZPmZ_D_UNDEF |
| 2807 | 0U, // CNT_ZPmZ_H_UNDEF |
| 2808 | 0U, // CNT_ZPmZ_S_UNDEF |
| 2809 | 0U, // COALESCER_BARRIER_FPR128 |
| 2810 | 0U, // COALESCER_BARRIER_FPR16 |
| 2811 | 0U, // COALESCER_BARRIER_FPR32 |
| 2812 | 0U, // COALESCER_BARRIER_FPR64 |
| 2813 | 0U, // EMITBKEY |
| 2814 | 0U, // EMITMTETAGGED |
| 2815 | 0U, // EONWrr |
| 2816 | 0U, // EONXrr |
| 2817 | 0U, // EORWrr |
| 2818 | 0U, // EORXrr |
| 2819 | 0U, // EOR_ZPZZ_B_ZERO |
| 2820 | 0U, // EOR_ZPZZ_D_ZERO |
| 2821 | 0U, // EOR_ZPZZ_H_ZERO |
| 2822 | 0U, // EOR_ZPZZ_S_ZERO |
| 2823 | 0U, // F128CSEL |
| 2824 | 0U, // FABD_ZPZZ_D_UNDEF |
| 2825 | 0U, // FABD_ZPZZ_D_ZERO |
| 2826 | 0U, // FABD_ZPZZ_H_UNDEF |
| 2827 | 0U, // FABD_ZPZZ_H_ZERO |
| 2828 | 0U, // FABD_ZPZZ_S_UNDEF |
| 2829 | 0U, // FABD_ZPZZ_S_ZERO |
| 2830 | 0U, // FABS_ZPmZ_D_UNDEF |
| 2831 | 0U, // FABS_ZPmZ_H_UNDEF |
| 2832 | 0U, // FABS_ZPmZ_S_UNDEF |
| 2833 | 0U, // FADD_VG2_M2Z_D_PSEUDO |
| 2834 | 0U, // FADD_VG2_M2Z_H_PSEUDO |
| 2835 | 0U, // FADD_VG2_M2Z_S_PSEUDO |
| 2836 | 0U, // FADD_VG4_M4Z_D_PSEUDO |
| 2837 | 0U, // FADD_VG4_M4Z_H_PSEUDO |
| 2838 | 0U, // FADD_VG4_M4Z_S_PSEUDO |
| 2839 | 0U, // FADD_ZPZI_D_UNDEF |
| 2840 | 0U, // FADD_ZPZI_D_ZERO |
| 2841 | 0U, // FADD_ZPZI_H_UNDEF |
| 2842 | 0U, // FADD_ZPZI_H_ZERO |
| 2843 | 0U, // FADD_ZPZI_S_UNDEF |
| 2844 | 0U, // FADD_ZPZI_S_ZERO |
| 2845 | 0U, // FADD_ZPZZ_D_UNDEF |
| 2846 | 0U, // FADD_ZPZZ_D_ZERO |
| 2847 | 0U, // FADD_ZPZZ_H_UNDEF |
| 2848 | 0U, // FADD_ZPZZ_H_ZERO |
| 2849 | 0U, // FADD_ZPZZ_S_UNDEF |
| 2850 | 0U, // FADD_ZPZZ_S_ZERO |
| 2851 | 0U, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 2852 | 0U, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 2853 | 0U, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 2854 | 0U, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 2855 | 0U, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 2856 | 0U, // FCVTZS_ZPmZ_StoD_UNDEF |
| 2857 | 0U, // FCVTZS_ZPmZ_StoS_UNDEF |
| 2858 | 0U, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 2859 | 0U, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 2860 | 0U, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 2861 | 0U, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 2862 | 0U, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 2863 | 0U, // FCVTZU_ZPmZ_StoD_UNDEF |
| 2864 | 0U, // FCVTZU_ZPmZ_StoS_UNDEF |
| 2865 | 0U, // FCVT_ZPmZ_DtoH_UNDEF |
| 2866 | 0U, // FCVT_ZPmZ_DtoS_UNDEF |
| 2867 | 0U, // FCVT_ZPmZ_HtoD_UNDEF |
| 2868 | 0U, // FCVT_ZPmZ_HtoS_UNDEF |
| 2869 | 0U, // FCVT_ZPmZ_StoD_UNDEF |
| 2870 | 0U, // FCVT_ZPmZ_StoH_UNDEF |
| 2871 | 0U, // FDIVR_ZPZZ_D_ZERO |
| 2872 | 0U, // FDIVR_ZPZZ_H_ZERO |
| 2873 | 0U, // FDIVR_ZPZZ_S_ZERO |
| 2874 | 0U, // FDIV_ZPZZ_D_UNDEF |
| 2875 | 0U, // FDIV_ZPZZ_D_ZERO |
| 2876 | 0U, // FDIV_ZPZZ_H_UNDEF |
| 2877 | 0U, // FDIV_ZPZZ_H_ZERO |
| 2878 | 0U, // FDIV_ZPZZ_S_UNDEF |
| 2879 | 0U, // FDIV_ZPZZ_S_ZERO |
| 2880 | 0U, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO |
| 2881 | 0U, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 2882 | 0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2883 | 0U, // FDOT_VG2_M2ZZI_BtoS_PSEUDO |
| 2884 | 0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2885 | 0U, // FDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2886 | 0U, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO |
| 2887 | 0U, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 2888 | 0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2889 | 0U, // FDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 2890 | 0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 2891 | 0U, // FDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2892 | 0U, // FLOGB_ZPZZ_D_ZERO |
| 2893 | 0U, // FLOGB_ZPZZ_H_ZERO |
| 2894 | 0U, // FLOGB_ZPZZ_S_ZERO |
| 2895 | 0U, // FMAXNM_ZPZI_D_UNDEF |
| 2896 | 0U, // FMAXNM_ZPZI_D_ZERO |
| 2897 | 0U, // FMAXNM_ZPZI_H_UNDEF |
| 2898 | 0U, // FMAXNM_ZPZI_H_ZERO |
| 2899 | 0U, // FMAXNM_ZPZI_S_UNDEF |
| 2900 | 0U, // FMAXNM_ZPZI_S_ZERO |
| 2901 | 0U, // FMAXNM_ZPZZ_D_UNDEF |
| 2902 | 0U, // FMAXNM_ZPZZ_D_ZERO |
| 2903 | 0U, // FMAXNM_ZPZZ_H_UNDEF |
| 2904 | 0U, // FMAXNM_ZPZZ_H_ZERO |
| 2905 | 0U, // FMAXNM_ZPZZ_S_UNDEF |
| 2906 | 0U, // FMAXNM_ZPZZ_S_ZERO |
| 2907 | 0U, // FMAX_ZPZI_D_UNDEF |
| 2908 | 0U, // FMAX_ZPZI_D_ZERO |
| 2909 | 0U, // FMAX_ZPZI_H_UNDEF |
| 2910 | 0U, // FMAX_ZPZI_H_ZERO |
| 2911 | 0U, // FMAX_ZPZI_S_UNDEF |
| 2912 | 0U, // FMAX_ZPZI_S_ZERO |
| 2913 | 0U, // FMAX_ZPZZ_D_UNDEF |
| 2914 | 0U, // FMAX_ZPZZ_D_ZERO |
| 2915 | 0U, // FMAX_ZPZZ_H_UNDEF |
| 2916 | 0U, // FMAX_ZPZZ_H_ZERO |
| 2917 | 0U, // FMAX_ZPZZ_S_UNDEF |
| 2918 | 0U, // FMAX_ZPZZ_S_ZERO |
| 2919 | 0U, // FMINNM_ZPZI_D_UNDEF |
| 2920 | 0U, // FMINNM_ZPZI_D_ZERO |
| 2921 | 0U, // FMINNM_ZPZI_H_UNDEF |
| 2922 | 0U, // FMINNM_ZPZI_H_ZERO |
| 2923 | 0U, // FMINNM_ZPZI_S_UNDEF |
| 2924 | 0U, // FMINNM_ZPZI_S_ZERO |
| 2925 | 0U, // FMINNM_ZPZZ_D_UNDEF |
| 2926 | 0U, // FMINNM_ZPZZ_D_ZERO |
| 2927 | 0U, // FMINNM_ZPZZ_H_UNDEF |
| 2928 | 0U, // FMINNM_ZPZZ_H_ZERO |
| 2929 | 0U, // FMINNM_ZPZZ_S_UNDEF |
| 2930 | 0U, // FMINNM_ZPZZ_S_ZERO |
| 2931 | 0U, // FMIN_ZPZI_D_UNDEF |
| 2932 | 0U, // FMIN_ZPZI_D_ZERO |
| 2933 | 0U, // FMIN_ZPZI_H_UNDEF |
| 2934 | 0U, // FMIN_ZPZI_H_ZERO |
| 2935 | 0U, // FMIN_ZPZI_S_UNDEF |
| 2936 | 0U, // FMIN_ZPZI_S_ZERO |
| 2937 | 0U, // FMIN_ZPZZ_D_UNDEF |
| 2938 | 0U, // FMIN_ZPZZ_D_ZERO |
| 2939 | 0U, // FMIN_ZPZZ_H_UNDEF |
| 2940 | 0U, // FMIN_ZPZZ_H_ZERO |
| 2941 | 0U, // FMIN_ZPZZ_S_UNDEF |
| 2942 | 0U, // FMIN_ZPZZ_S_ZERO |
| 2943 | 0U, // FMLALL_MZZI_BtoS_PSEUDO |
| 2944 | 0U, // FMLALL_MZZ_BtoS_PSEUDO |
| 2945 | 0U, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2946 | 0U, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2947 | 0U, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2948 | 0U, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2949 | 0U, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2950 | 0U, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2951 | 0U, // FMLAL_MZZI_HtoS_PSEUDO |
| 2952 | 0U, // FMLAL_MZZ_HtoS_PSEUDO |
| 2953 | 0U, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO |
| 2954 | 0U, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2955 | 0U, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 2956 | 0U, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO |
| 2957 | 0U, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2958 | 0U, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO |
| 2959 | 0U, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2960 | 0U, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2961 | 0U, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO |
| 2962 | 0U, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2963 | 0U, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 2964 | 0U, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 2965 | 0U, // FMLA_VG2_M2Z4Z_H_PSEUDO |
| 2966 | 0U, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 2967 | 0U, // FMLA_VG2_M2ZZI_H_PSEUDO |
| 2968 | 0U, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 2969 | 0U, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 2970 | 0U, // FMLA_VG2_M2ZZ_H_PSEUDO |
| 2971 | 0U, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 2972 | 0U, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 2973 | 0U, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 2974 | 0U, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 2975 | 0U, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 2976 | 0U, // FMLA_VG4_M4ZZI_H_PSEUDO |
| 2977 | 0U, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 2978 | 0U, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 2979 | 0U, // FMLA_VG4_M4ZZ_H_PSEUDO |
| 2980 | 0U, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 2981 | 0U, // FMLA_ZPZZZ_D_UNDEF |
| 2982 | 0U, // FMLA_ZPZZZ_H_UNDEF |
| 2983 | 0U, // FMLA_ZPZZZ_S_UNDEF |
| 2984 | 0U, // FMLSL_MZZI_HtoS_PSEUDO |
| 2985 | 0U, // FMLSL_MZZ_HtoS_PSEUDO |
| 2986 | 0U, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2987 | 0U, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 2988 | 0U, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 2989 | 0U, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2990 | 0U, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 2991 | 0U, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 2992 | 0U, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 2993 | 0U, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 2994 | 0U, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 2995 | 0U, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 2996 | 0U, // FMLS_VG2_M2ZZI_H_PSEUDO |
| 2997 | 0U, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 2998 | 0U, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 2999 | 0U, // FMLS_VG2_M2ZZ_H_PSEUDO |
| 3000 | 0U, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 3001 | 0U, // FMLS_VG4_M4Z2Z_H_PSEUDO |
| 3002 | 0U, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 3003 | 0U, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 3004 | 0U, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 3005 | 0U, // FMLS_VG4_M4ZZI_H_PSEUDO |
| 3006 | 0U, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 3007 | 0U, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 3008 | 0U, // FMLS_VG4_M4ZZ_H_PSEUDO |
| 3009 | 0U, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 3010 | 0U, // FMLS_ZPZZZ_D_UNDEF |
| 3011 | 0U, // FMLS_ZPZZZ_H_UNDEF |
| 3012 | 0U, // FMLS_ZPZZZ_S_UNDEF |
| 3013 | 0U, // FMOPAL_MPPZZ_PSEUDO |
| 3014 | 0U, // FMOPA_MPPZZ_BtoS_PSEUDO |
| 3015 | 0U, // FMOPA_MPPZZ_D_PSEUDO |
| 3016 | 0U, // FMOPA_MPPZZ_H_PSEUDO |
| 3017 | 0U, // FMOPA_MPPZZ_S_PSEUDO |
| 3018 | 0U, // FMOPSL_MPPZZ_PSEUDO |
| 3019 | 0U, // FMOPS_MPPZZ_D_PSEUDO |
| 3020 | 0U, // FMOPS_MPPZZ_H_PSEUDO |
| 3021 | 0U, // FMOPS_MPPZZ_S_PSEUDO |
| 3022 | 0U, // FMOVD0 |
| 3023 | 0U, // FMOVH0 |
| 3024 | 0U, // FMOVS0 |
| 3025 | 0U, // FMULX_ZPZZ_D_UNDEF |
| 3026 | 0U, // FMULX_ZPZZ_D_ZERO |
| 3027 | 0U, // FMULX_ZPZZ_H_UNDEF |
| 3028 | 0U, // FMULX_ZPZZ_H_ZERO |
| 3029 | 0U, // FMULX_ZPZZ_S_UNDEF |
| 3030 | 0U, // FMULX_ZPZZ_S_ZERO |
| 3031 | 0U, // FMUL_ZPZI_D_UNDEF |
| 3032 | 0U, // FMUL_ZPZI_D_ZERO |
| 3033 | 0U, // FMUL_ZPZI_H_UNDEF |
| 3034 | 0U, // FMUL_ZPZI_H_ZERO |
| 3035 | 0U, // FMUL_ZPZI_S_UNDEF |
| 3036 | 0U, // FMUL_ZPZI_S_ZERO |
| 3037 | 0U, // FMUL_ZPZZ_D_UNDEF |
| 3038 | 0U, // FMUL_ZPZZ_D_ZERO |
| 3039 | 0U, // FMUL_ZPZZ_H_UNDEF |
| 3040 | 0U, // FMUL_ZPZZ_H_ZERO |
| 3041 | 0U, // FMUL_ZPZZ_S_UNDEF |
| 3042 | 0U, // FMUL_ZPZZ_S_ZERO |
| 3043 | 0U, // FNEG_ZPmZ_D_UNDEF |
| 3044 | 0U, // FNEG_ZPmZ_H_UNDEF |
| 3045 | 0U, // FNEG_ZPmZ_S_UNDEF |
| 3046 | 0U, // FNMLA_ZPZZZ_D_UNDEF |
| 3047 | 0U, // FNMLA_ZPZZZ_H_UNDEF |
| 3048 | 0U, // FNMLA_ZPZZZ_S_UNDEF |
| 3049 | 0U, // FNMLS_ZPZZZ_D_UNDEF |
| 3050 | 0U, // FNMLS_ZPZZZ_H_UNDEF |
| 3051 | 0U, // FNMLS_ZPZZZ_S_UNDEF |
| 3052 | 0U, // FRECPX_ZPmZ_D_UNDEF |
| 3053 | 0U, // FRECPX_ZPmZ_H_UNDEF |
| 3054 | 0U, // FRECPX_ZPmZ_S_UNDEF |
| 3055 | 0U, // FRINTA_ZPmZ_D_UNDEF |
| 3056 | 0U, // FRINTA_ZPmZ_H_UNDEF |
| 3057 | 0U, // FRINTA_ZPmZ_S_UNDEF |
| 3058 | 0U, // FRINTI_ZPmZ_D_UNDEF |
| 3059 | 0U, // FRINTI_ZPmZ_H_UNDEF |
| 3060 | 0U, // FRINTI_ZPmZ_S_UNDEF |
| 3061 | 0U, // FRINTM_ZPmZ_D_UNDEF |
| 3062 | 0U, // FRINTM_ZPmZ_H_UNDEF |
| 3063 | 0U, // FRINTM_ZPmZ_S_UNDEF |
| 3064 | 0U, // FRINTN_ZPmZ_D_UNDEF |
| 3065 | 0U, // FRINTN_ZPmZ_H_UNDEF |
| 3066 | 0U, // FRINTN_ZPmZ_S_UNDEF |
| 3067 | 0U, // FRINTP_ZPmZ_D_UNDEF |
| 3068 | 0U, // FRINTP_ZPmZ_H_UNDEF |
| 3069 | 0U, // FRINTP_ZPmZ_S_UNDEF |
| 3070 | 0U, // FRINTX_ZPmZ_D_UNDEF |
| 3071 | 0U, // FRINTX_ZPmZ_H_UNDEF |
| 3072 | 0U, // FRINTX_ZPmZ_S_UNDEF |
| 3073 | 0U, // FRINTZ_ZPmZ_D_UNDEF |
| 3074 | 0U, // FRINTZ_ZPmZ_H_UNDEF |
| 3075 | 0U, // FRINTZ_ZPmZ_S_UNDEF |
| 3076 | 0U, // FSQRT_ZPmZ_D_UNDEF |
| 3077 | 0U, // FSQRT_ZPmZ_H_UNDEF |
| 3078 | 0U, // FSQRT_ZPmZ_S_UNDEF |
| 3079 | 0U, // FSUBR_ZPZI_D_UNDEF |
| 3080 | 0U, // FSUBR_ZPZI_D_ZERO |
| 3081 | 0U, // FSUBR_ZPZI_H_UNDEF |
| 3082 | 0U, // FSUBR_ZPZI_H_ZERO |
| 3083 | 0U, // FSUBR_ZPZI_S_UNDEF |
| 3084 | 0U, // FSUBR_ZPZI_S_ZERO |
| 3085 | 0U, // FSUBR_ZPZZ_D_ZERO |
| 3086 | 0U, // FSUBR_ZPZZ_H_ZERO |
| 3087 | 0U, // FSUBR_ZPZZ_S_ZERO |
| 3088 | 0U, // FSUB_VG2_M2Z_D_PSEUDO |
| 3089 | 0U, // FSUB_VG2_M2Z_H_PSEUDO |
| 3090 | 0U, // FSUB_VG2_M2Z_S_PSEUDO |
| 3091 | 0U, // FSUB_VG4_M4Z_D_PSEUDO |
| 3092 | 0U, // FSUB_VG4_M4Z_H_PSEUDO |
| 3093 | 0U, // FSUB_VG4_M4Z_S_PSEUDO |
| 3094 | 0U, // FSUB_ZPZI_D_UNDEF |
| 3095 | 0U, // FSUB_ZPZI_D_ZERO |
| 3096 | 0U, // FSUB_ZPZI_H_UNDEF |
| 3097 | 0U, // FSUB_ZPZI_H_ZERO |
| 3098 | 0U, // FSUB_ZPZI_S_UNDEF |
| 3099 | 0U, // FSUB_ZPZI_S_ZERO |
| 3100 | 0U, // FSUB_ZPZZ_D_UNDEF |
| 3101 | 0U, // FSUB_ZPZZ_D_ZERO |
| 3102 | 0U, // FSUB_ZPZZ_H_UNDEF |
| 3103 | 0U, // FSUB_ZPZZ_H_ZERO |
| 3104 | 0U, // FSUB_ZPZZ_S_UNDEF |
| 3105 | 0U, // FSUB_ZPZZ_S_ZERO |
| 3106 | 0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 3107 | 0U, // G_AARCH64_PREFETCH |
| 3108 | 0U, // G_ADD_LOW |
| 3109 | 0U, // G_BSP |
| 3110 | 0U, // G_DUP |
| 3111 | 0U, // G_DUPLANE16 |
| 3112 | 0U, // G_DUPLANE32 |
| 3113 | 0U, // G_DUPLANE64 |
| 3114 | 0U, // G_DUPLANE8 |
| 3115 | 0U, // G_EXT |
| 3116 | 0U, // G_FCMEQ |
| 3117 | 0U, // G_FCMEQZ |
| 3118 | 0U, // G_FCMGE |
| 3119 | 0U, // G_FCMGEZ |
| 3120 | 0U, // G_FCMGT |
| 3121 | 0U, // G_FCMGTZ |
| 3122 | 0U, // G_FCMLEZ |
| 3123 | 0U, // G_FCMLTZ |
| 3124 | 0U, // G_REV16 |
| 3125 | 0U, // G_REV32 |
| 3126 | 0U, // G_REV64 |
| 3127 | 0U, // G_SADDLP |
| 3128 | 0U, // G_SADDLV |
| 3129 | 0U, // G_SDOT |
| 3130 | 0U, // G_SITOF |
| 3131 | 0U, // G_SMULL |
| 3132 | 0U, // G_TRN1 |
| 3133 | 0U, // G_TRN2 |
| 3134 | 0U, // G_UADDLP |
| 3135 | 0U, // G_UADDLV |
| 3136 | 0U, // G_UDOT |
| 3137 | 0U, // G_UITOF |
| 3138 | 0U, // G_UMULL |
| 3139 | 0U, // G_UZP1 |
| 3140 | 0U, // G_UZP2 |
| 3141 | 0U, // G_VASHR |
| 3142 | 0U, // G_VLSHR |
| 3143 | 0U, // G_ZIP1 |
| 3144 | 0U, // G_ZIP2 |
| 3145 | 0U, // HOM_Epilog |
| 3146 | 0U, // HOM_Prolog |
| 3147 | 0U, // HWASAN_CHECK_MEMACCESS |
| 3148 | 0U, // HWASAN_CHECK_MEMACCESS_FIXEDSHADOW |
| 3149 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 3150 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW |
| 3151 | 0U, // INSERT_MXIPZ_H_PSEUDO_B |
| 3152 | 0U, // INSERT_MXIPZ_H_PSEUDO_D |
| 3153 | 0U, // INSERT_MXIPZ_H_PSEUDO_H |
| 3154 | 0U, // INSERT_MXIPZ_H_PSEUDO_Q |
| 3155 | 0U, // INSERT_MXIPZ_H_PSEUDO_S |
| 3156 | 0U, // INSERT_MXIPZ_V_PSEUDO_B |
| 3157 | 0U, // INSERT_MXIPZ_V_PSEUDO_D |
| 3158 | 0U, // INSERT_MXIPZ_V_PSEUDO_H |
| 3159 | 0U, // INSERT_MXIPZ_V_PSEUDO_Q |
| 3160 | 0U, // INSERT_MXIPZ_V_PSEUDO_S |
| 3161 | 0U, // IRGstack |
| 3162 | 0U, // InitTPIDR2Obj |
| 3163 | 0U, // JumpTableDest16 |
| 3164 | 0U, // JumpTableDest32 |
| 3165 | 0U, // JumpTableDest8 |
| 3166 | 0U, // KCFI_CHECK |
| 3167 | 0U, // LD1B_2Z_IMM_PSEUDO |
| 3168 | 0U, // LD1B_2Z_PSEUDO |
| 3169 | 0U, // LD1B_4Z_IMM_PSEUDO |
| 3170 | 0U, // LD1B_4Z_PSEUDO |
| 3171 | 0U, // LD1D_2Z_IMM_PSEUDO |
| 3172 | 0U, // LD1D_2Z_PSEUDO |
| 3173 | 0U, // LD1D_4Z_IMM_PSEUDO |
| 3174 | 0U, // LD1D_4Z_PSEUDO |
| 3175 | 0U, // LD1H_2Z_IMM_PSEUDO |
| 3176 | 0U, // LD1H_2Z_PSEUDO |
| 3177 | 0U, // LD1H_4Z_IMM_PSEUDO |
| 3178 | 0U, // LD1H_4Z_PSEUDO |
| 3179 | 0U, // LD1W_2Z_IMM_PSEUDO |
| 3180 | 0U, // LD1W_2Z_PSEUDO |
| 3181 | 0U, // LD1W_4Z_IMM_PSEUDO |
| 3182 | 0U, // LD1W_4Z_PSEUDO |
| 3183 | 0U, // LD1_MXIPXX_H_PSEUDO_B |
| 3184 | 0U, // LD1_MXIPXX_H_PSEUDO_D |
| 3185 | 0U, // LD1_MXIPXX_H_PSEUDO_H |
| 3186 | 0U, // LD1_MXIPXX_H_PSEUDO_Q |
| 3187 | 0U, // LD1_MXIPXX_H_PSEUDO_S |
| 3188 | 0U, // LD1_MXIPXX_V_PSEUDO_B |
| 3189 | 0U, // LD1_MXIPXX_V_PSEUDO_D |
| 3190 | 0U, // LD1_MXIPXX_V_PSEUDO_H |
| 3191 | 0U, // LD1_MXIPXX_V_PSEUDO_Q |
| 3192 | 0U, // LD1_MXIPXX_V_PSEUDO_S |
| 3193 | 0U, // LDNT1B_2Z_IMM_PSEUDO |
| 3194 | 0U, // LDNT1B_2Z_PSEUDO |
| 3195 | 0U, // LDNT1B_4Z_IMM_PSEUDO |
| 3196 | 0U, // LDNT1B_4Z_PSEUDO |
| 3197 | 0U, // LDNT1D_2Z_IMM_PSEUDO |
| 3198 | 0U, // LDNT1D_2Z_PSEUDO |
| 3199 | 0U, // LDNT1D_4Z_IMM_PSEUDO |
| 3200 | 0U, // LDNT1D_4Z_PSEUDO |
| 3201 | 0U, // LDNT1H_2Z_IMM_PSEUDO |
| 3202 | 0U, // LDNT1H_2Z_PSEUDO |
| 3203 | 0U, // LDNT1H_4Z_IMM_PSEUDO |
| 3204 | 0U, // LDNT1H_4Z_PSEUDO |
| 3205 | 0U, // LDNT1W_2Z_IMM_PSEUDO |
| 3206 | 0U, // LDNT1W_2Z_PSEUDO |
| 3207 | 0U, // LDNT1W_4Z_IMM_PSEUDO |
| 3208 | 0U, // LDNT1W_4Z_PSEUDO |
| 3209 | 0U, // LDR_PPXI |
| 3210 | 0U, // LDR_TX_PSEUDO |
| 3211 | 0U, // LDR_ZA_PSEUDO |
| 3212 | 0U, // LDR_ZZXI |
| 3213 | 0U, // LDR_ZZZXI |
| 3214 | 0U, // LDR_ZZZZXI |
| 3215 | 0U, // LOADauthptrstatic |
| 3216 | 0U, // LOADgot |
| 3217 | 0U, // LOADgotPAC |
| 3218 | 0U, // LSL_ZPZI_B_UNDEF |
| 3219 | 0U, // LSL_ZPZI_B_ZERO |
| 3220 | 0U, // LSL_ZPZI_D_UNDEF |
| 3221 | 0U, // LSL_ZPZI_D_ZERO |
| 3222 | 0U, // LSL_ZPZI_H_UNDEF |
| 3223 | 0U, // LSL_ZPZI_H_ZERO |
| 3224 | 0U, // LSL_ZPZI_S_UNDEF |
| 3225 | 0U, // LSL_ZPZI_S_ZERO |
| 3226 | 0U, // LSL_ZPZZ_B_UNDEF |
| 3227 | 0U, // LSL_ZPZZ_B_ZERO |
| 3228 | 0U, // LSL_ZPZZ_D_UNDEF |
| 3229 | 0U, // LSL_ZPZZ_D_ZERO |
| 3230 | 0U, // LSL_ZPZZ_H_UNDEF |
| 3231 | 0U, // LSL_ZPZZ_H_ZERO |
| 3232 | 0U, // LSL_ZPZZ_S_UNDEF |
| 3233 | 0U, // LSL_ZPZZ_S_ZERO |
| 3234 | 0U, // LSR_ZPZI_B_UNDEF |
| 3235 | 0U, // LSR_ZPZI_B_ZERO |
| 3236 | 0U, // LSR_ZPZI_D_UNDEF |
| 3237 | 0U, // LSR_ZPZI_D_ZERO |
| 3238 | 0U, // LSR_ZPZI_H_UNDEF |
| 3239 | 0U, // LSR_ZPZI_H_ZERO |
| 3240 | 0U, // LSR_ZPZI_S_UNDEF |
| 3241 | 0U, // LSR_ZPZI_S_ZERO |
| 3242 | 0U, // LSR_ZPZZ_B_UNDEF |
| 3243 | 0U, // LSR_ZPZZ_B_ZERO |
| 3244 | 0U, // LSR_ZPZZ_D_UNDEF |
| 3245 | 0U, // LSR_ZPZZ_D_ZERO |
| 3246 | 0U, // LSR_ZPZZ_H_UNDEF |
| 3247 | 0U, // LSR_ZPZZ_H_ZERO |
| 3248 | 0U, // LSR_ZPZZ_S_UNDEF |
| 3249 | 0U, // LSR_ZPZZ_S_ZERO |
| 3250 | 0U, // MLA_ZPZZZ_B_UNDEF |
| 3251 | 0U, // MLA_ZPZZZ_D_UNDEF |
| 3252 | 0U, // MLA_ZPZZZ_H_UNDEF |
| 3253 | 0U, // MLA_ZPZZZ_S_UNDEF |
| 3254 | 0U, // MLS_ZPZZZ_B_UNDEF |
| 3255 | 0U, // MLS_ZPZZZ_D_UNDEF |
| 3256 | 0U, // MLS_ZPZZZ_H_UNDEF |
| 3257 | 0U, // MLS_ZPZZZ_S_UNDEF |
| 3258 | 0U, // MOPSMemoryCopyPseudo |
| 3259 | 0U, // MOPSMemoryMovePseudo |
| 3260 | 0U, // MOPSMemorySetPseudo |
| 3261 | 0U, // MOPSMemorySetTaggingPseudo |
| 3262 | 0U, // MOVAZ_2ZMI_H_B_PSEUDO |
| 3263 | 0U, // MOVAZ_2ZMI_H_D_PSEUDO |
| 3264 | 0U, // MOVAZ_2ZMI_H_H_PSEUDO |
| 3265 | 0U, // MOVAZ_2ZMI_H_S_PSEUDO |
| 3266 | 0U, // MOVAZ_2ZMI_V_B_PSEUDO |
| 3267 | 0U, // MOVAZ_2ZMI_V_D_PSEUDO |
| 3268 | 0U, // MOVAZ_2ZMI_V_H_PSEUDO |
| 3269 | 0U, // MOVAZ_2ZMI_V_S_PSEUDO |
| 3270 | 0U, // MOVAZ_4ZMI_H_B_PSEUDO |
| 3271 | 0U, // MOVAZ_4ZMI_H_D_PSEUDO |
| 3272 | 0U, // MOVAZ_4ZMI_H_H_PSEUDO |
| 3273 | 0U, // MOVAZ_4ZMI_H_S_PSEUDO |
| 3274 | 0U, // MOVAZ_4ZMI_V_B_PSEUDO |
| 3275 | 0U, // MOVAZ_4ZMI_V_D_PSEUDO |
| 3276 | 0U, // MOVAZ_4ZMI_V_H_PSEUDO |
| 3277 | 0U, // MOVAZ_4ZMI_V_S_PSEUDO |
| 3278 | 0U, // MOVAZ_VG2_2ZMXI_PSEUDO |
| 3279 | 0U, // MOVAZ_VG4_4ZMXI_PSEUDO |
| 3280 | 0U, // MOVAZ_ZMI_H_B_PSEUDO |
| 3281 | 0U, // MOVAZ_ZMI_H_D_PSEUDO |
| 3282 | 0U, // MOVAZ_ZMI_H_H_PSEUDO |
| 3283 | 0U, // MOVAZ_ZMI_H_Q_PSEUDO |
| 3284 | 0U, // MOVAZ_ZMI_H_S_PSEUDO |
| 3285 | 0U, // MOVAZ_ZMI_V_B_PSEUDO |
| 3286 | 0U, // MOVAZ_ZMI_V_D_PSEUDO |
| 3287 | 0U, // MOVAZ_ZMI_V_H_PSEUDO |
| 3288 | 0U, // MOVAZ_ZMI_V_Q_PSEUDO |
| 3289 | 0U, // MOVAZ_ZMI_V_S_PSEUDO |
| 3290 | 0U, // MOVA_MXI2Z_H_B_PSEUDO |
| 3291 | 0U, // MOVA_MXI2Z_H_D_PSEUDO |
| 3292 | 0U, // MOVA_MXI2Z_H_H_PSEUDO |
| 3293 | 0U, // MOVA_MXI2Z_H_S_PSEUDO |
| 3294 | 0U, // MOVA_MXI2Z_V_B_PSEUDO |
| 3295 | 0U, // MOVA_MXI2Z_V_D_PSEUDO |
| 3296 | 0U, // MOVA_MXI2Z_V_H_PSEUDO |
| 3297 | 0U, // MOVA_MXI2Z_V_S_PSEUDO |
| 3298 | 0U, // MOVA_MXI4Z_H_B_PSEUDO |
| 3299 | 0U, // MOVA_MXI4Z_H_D_PSEUDO |
| 3300 | 0U, // MOVA_MXI4Z_H_H_PSEUDO |
| 3301 | 0U, // MOVA_MXI4Z_H_S_PSEUDO |
| 3302 | 0U, // MOVA_MXI4Z_V_B_PSEUDO |
| 3303 | 0U, // MOVA_MXI4Z_V_D_PSEUDO |
| 3304 | 0U, // MOVA_MXI4Z_V_H_PSEUDO |
| 3305 | 0U, // MOVA_MXI4Z_V_S_PSEUDO |
| 3306 | 0U, // MOVA_VG2_MXI2Z_PSEUDO |
| 3307 | 0U, // MOVA_VG4_MXI4Z_PSEUDO |
| 3308 | 0U, // MOVMCSym |
| 3309 | 0U, // MOVaddr |
| 3310 | 0U, // MOVaddrBA |
| 3311 | 0U, // MOVaddrCP |
| 3312 | 0U, // MOVaddrEXT |
| 3313 | 0U, // MOVaddrJT |
| 3314 | 0U, // MOVaddrPAC |
| 3315 | 0U, // MOVaddrTLS |
| 3316 | 0U, // MOVbaseTLS |
| 3317 | 0U, // MOVi32imm |
| 3318 | 0U, // MOVi64imm |
| 3319 | 0U, // MRS_FPCR |
| 3320 | 0U, // MRS_FPSR |
| 3321 | 0U, // MSR_FPCR |
| 3322 | 0U, // MSR_FPSR |
| 3323 | 0U, // MSRpstatePseudo |
| 3324 | 0U, // MUL_ZPZZ_B_UNDEF |
| 3325 | 0U, // MUL_ZPZZ_D_UNDEF |
| 3326 | 0U, // MUL_ZPZZ_H_UNDEF |
| 3327 | 0U, // MUL_ZPZZ_S_UNDEF |
| 3328 | 0U, // NEG_ZPmZ_B_UNDEF |
| 3329 | 0U, // NEG_ZPmZ_D_UNDEF |
| 3330 | 0U, // NEG_ZPmZ_H_UNDEF |
| 3331 | 0U, // NEG_ZPmZ_S_UNDEF |
| 3332 | 0U, // NOT_ZPmZ_B_UNDEF |
| 3333 | 0U, // NOT_ZPmZ_D_UNDEF |
| 3334 | 0U, // NOT_ZPmZ_H_UNDEF |
| 3335 | 0U, // NOT_ZPmZ_S_UNDEF |
| 3336 | 0U, // ORNWrr |
| 3337 | 0U, // ORNXrr |
| 3338 | 0U, // ORRWrr |
| 3339 | 0U, // ORRXrr |
| 3340 | 0U, // ORR_ZPZZ_B_ZERO |
| 3341 | 0U, // ORR_ZPZZ_D_ZERO |
| 3342 | 0U, // ORR_ZPZZ_H_ZERO |
| 3343 | 0U, // ORR_ZPZZ_S_ZERO |
| 3344 | 0U, // PAUTH_BLEND |
| 3345 | 0U, // PAUTH_EPILOGUE |
| 3346 | 0U, // PAUTH_PROLOGUE |
| 3347 | 0U, // PROBED_STACKALLOC |
| 3348 | 0U, // PROBED_STACKALLOC_DYN |
| 3349 | 0U, // PROBED_STACKALLOC_VAR |
| 3350 | 0U, // PTEST_PP_ANY |
| 3351 | 0U, // RET_ReallyLR |
| 3352 | 0U, // RestoreZAPseudo |
| 3353 | 0U, // SABD_ZPZZ_B_UNDEF |
| 3354 | 0U, // SABD_ZPZZ_D_UNDEF |
| 3355 | 0U, // SABD_ZPZZ_H_UNDEF |
| 3356 | 0U, // SABD_ZPZZ_S_UNDEF |
| 3357 | 0U, // SCVTF_ZPmZ_DtoD_UNDEF |
| 3358 | 0U, // SCVTF_ZPmZ_DtoH_UNDEF |
| 3359 | 0U, // SCVTF_ZPmZ_DtoS_UNDEF |
| 3360 | 0U, // SCVTF_ZPmZ_HtoH_UNDEF |
| 3361 | 0U, // SCVTF_ZPmZ_StoD_UNDEF |
| 3362 | 0U, // SCVTF_ZPmZ_StoH_UNDEF |
| 3363 | 0U, // SCVTF_ZPmZ_StoS_UNDEF |
| 3364 | 0U, // SDIV_ZPZZ_D_UNDEF |
| 3365 | 0U, // SDIV_ZPZZ_S_UNDEF |
| 3366 | 0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 3367 | 0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 3368 | 0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 3369 | 0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3370 | 0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 3371 | 0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 3372 | 0U, // SDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 3373 | 0U, // SDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 3374 | 0U, // SDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 3375 | 0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 3376 | 0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 3377 | 0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 3378 | 0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3379 | 0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 3380 | 0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3381 | 0U, // SDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 3382 | 0U, // SDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 3383 | 0U, // SDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 3384 | 0U, // SEH_AddFP |
| 3385 | 0U, // SEH_EpilogEnd |
| 3386 | 0U, // SEH_EpilogStart |
| 3387 | 0U, // SEH_Nop |
| 3388 | 0U, // SEH_PACSignLR |
| 3389 | 0U, // SEH_PrologEnd |
| 3390 | 0U, // SEH_SaveAnyRegQP |
| 3391 | 0U, // SEH_SaveAnyRegQPX |
| 3392 | 0U, // SEH_SaveFPLR |
| 3393 | 0U, // SEH_SaveFPLR_X |
| 3394 | 0U, // SEH_SaveFReg |
| 3395 | 0U, // SEH_SaveFRegP |
| 3396 | 0U, // SEH_SaveFRegP_X |
| 3397 | 0U, // SEH_SaveFReg_X |
| 3398 | 0U, // SEH_SaveReg |
| 3399 | 0U, // SEH_SaveRegP |
| 3400 | 0U, // SEH_SaveRegP_X |
| 3401 | 0U, // SEH_SaveReg_X |
| 3402 | 0U, // SEH_SetFP |
| 3403 | 0U, // SEH_StackAlloc |
| 3404 | 0U, // SMAX_ZPZZ_B_UNDEF |
| 3405 | 0U, // SMAX_ZPZZ_D_UNDEF |
| 3406 | 0U, // SMAX_ZPZZ_H_UNDEF |
| 3407 | 0U, // SMAX_ZPZZ_S_UNDEF |
| 3408 | 0U, // SMIN_ZPZZ_B_UNDEF |
| 3409 | 0U, // SMIN_ZPZZ_D_UNDEF |
| 3410 | 0U, // SMIN_ZPZZ_H_UNDEF |
| 3411 | 0U, // SMIN_ZPZZ_S_UNDEF |
| 3412 | 0U, // SMLALL_MZZI_BtoS_PSEUDO |
| 3413 | 0U, // SMLALL_MZZI_HtoD_PSEUDO |
| 3414 | 0U, // SMLALL_MZZ_BtoS_PSEUDO |
| 3415 | 0U, // SMLALL_MZZ_HtoD_PSEUDO |
| 3416 | 0U, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3417 | 0U, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 3418 | 0U, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3419 | 0U, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 3420 | 0U, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3421 | 0U, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 3422 | 0U, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3423 | 0U, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3424 | 0U, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3425 | 0U, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 3426 | 0U, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3427 | 0U, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 3428 | 0U, // SMLAL_MZZI_HtoS_PSEUDO |
| 3429 | 0U, // SMLAL_MZZ_HtoS_PSEUDO |
| 3430 | 0U, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3431 | 0U, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 3432 | 0U, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 3433 | 0U, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3434 | 0U, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 3435 | 0U, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 3436 | 0U, // SMLSLL_MZZI_BtoS_PSEUDO |
| 3437 | 0U, // SMLSLL_MZZI_HtoD_PSEUDO |
| 3438 | 0U, // SMLSLL_MZZ_BtoS_PSEUDO |
| 3439 | 0U, // SMLSLL_MZZ_HtoD_PSEUDO |
| 3440 | 0U, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3441 | 0U, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 3442 | 0U, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 3443 | 0U, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 3444 | 0U, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 3445 | 0U, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 3446 | 0U, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3447 | 0U, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3448 | 0U, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 3449 | 0U, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 3450 | 0U, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 3451 | 0U, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 3452 | 0U, // SMLSL_MZZI_HtoS_PSEUDO |
| 3453 | 0U, // SMLSL_MZZ_HtoS_PSEUDO |
| 3454 | 0U, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3455 | 0U, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 3456 | 0U, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 3457 | 0U, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3458 | 0U, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 3459 | 0U, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 3460 | 0U, // SMOPA_MPPZZ_D_PSEUDO |
| 3461 | 0U, // SMOPA_MPPZZ_HtoS_PSEUDO |
| 3462 | 0U, // SMOPA_MPPZZ_S_PSEUDO |
| 3463 | 0U, // SMOPS_MPPZZ_D_PSEUDO |
| 3464 | 0U, // SMOPS_MPPZZ_HtoS_PSEUDO |
| 3465 | 0U, // SMOPS_MPPZZ_S_PSEUDO |
| 3466 | 0U, // SMULH_ZPZZ_B_UNDEF |
| 3467 | 0U, // SMULH_ZPZZ_D_UNDEF |
| 3468 | 0U, // SMULH_ZPZZ_H_UNDEF |
| 3469 | 0U, // SMULH_ZPZZ_S_UNDEF |
| 3470 | 0U, // SPACE |
| 3471 | 0U, // SQABS_ZPmZ_B_UNDEF |
| 3472 | 0U, // SQABS_ZPmZ_D_UNDEF |
| 3473 | 0U, // SQABS_ZPmZ_H_UNDEF |
| 3474 | 0U, // SQABS_ZPmZ_S_UNDEF |
| 3475 | 0U, // SQNEG_ZPmZ_B_UNDEF |
| 3476 | 0U, // SQNEG_ZPmZ_D_UNDEF |
| 3477 | 0U, // SQNEG_ZPmZ_H_UNDEF |
| 3478 | 0U, // SQNEG_ZPmZ_S_UNDEF |
| 3479 | 0U, // SQRSHL_ZPZZ_B_UNDEF |
| 3480 | 0U, // SQRSHL_ZPZZ_D_UNDEF |
| 3481 | 0U, // SQRSHL_ZPZZ_H_UNDEF |
| 3482 | 0U, // SQRSHL_ZPZZ_S_UNDEF |
| 3483 | 0U, // SQSHLU_ZPZI_B_ZERO |
| 3484 | 0U, // SQSHLU_ZPZI_D_ZERO |
| 3485 | 0U, // SQSHLU_ZPZI_H_ZERO |
| 3486 | 0U, // SQSHLU_ZPZI_S_ZERO |
| 3487 | 0U, // SQSHL_ZPZI_B_ZERO |
| 3488 | 0U, // SQSHL_ZPZI_D_ZERO |
| 3489 | 0U, // SQSHL_ZPZI_H_ZERO |
| 3490 | 0U, // SQSHL_ZPZI_S_ZERO |
| 3491 | 0U, // SQSHL_ZPZZ_B_UNDEF |
| 3492 | 0U, // SQSHL_ZPZZ_D_UNDEF |
| 3493 | 0U, // SQSHL_ZPZZ_H_UNDEF |
| 3494 | 0U, // SQSHL_ZPZZ_S_UNDEF |
| 3495 | 0U, // SRSHL_ZPZZ_B_UNDEF |
| 3496 | 0U, // SRSHL_ZPZZ_D_UNDEF |
| 3497 | 0U, // SRSHL_ZPZZ_H_UNDEF |
| 3498 | 0U, // SRSHL_ZPZZ_S_UNDEF |
| 3499 | 0U, // SRSHR_ZPZI_B_ZERO |
| 3500 | 0U, // SRSHR_ZPZI_D_ZERO |
| 3501 | 0U, // SRSHR_ZPZI_H_ZERO |
| 3502 | 0U, // SRSHR_ZPZI_S_ZERO |
| 3503 | 0U, // STGloop |
| 3504 | 0U, // STGloop_wback |
| 3505 | 0U, // STR_PPXI |
| 3506 | 0U, // STR_TX_PSEUDO |
| 3507 | 0U, // STR_ZZXI |
| 3508 | 0U, // STR_ZZZXI |
| 3509 | 0U, // STR_ZZZZXI |
| 3510 | 0U, // STZGloop |
| 3511 | 0U, // STZGloop_wback |
| 3512 | 0U, // SUBR_ZPZZ_B_ZERO |
| 3513 | 0U, // SUBR_ZPZZ_D_ZERO |
| 3514 | 0U, // SUBR_ZPZZ_H_ZERO |
| 3515 | 0U, // SUBR_ZPZZ_S_ZERO |
| 3516 | 0U, // SUBSWrr |
| 3517 | 0U, // SUBSXrr |
| 3518 | 0U, // SUBWrr |
| 3519 | 0U, // SUBXrr |
| 3520 | 0U, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 3521 | 0U, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 3522 | 0U, // SUB_VG2_M2ZZ_D_PSEUDO |
| 3523 | 0U, // SUB_VG2_M2ZZ_S_PSEUDO |
| 3524 | 0U, // SUB_VG2_M2Z_D_PSEUDO |
| 3525 | 0U, // SUB_VG2_M2Z_S_PSEUDO |
| 3526 | 0U, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 3527 | 0U, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 3528 | 0U, // SUB_VG4_M4ZZ_D_PSEUDO |
| 3529 | 0U, // SUB_VG4_M4ZZ_S_PSEUDO |
| 3530 | 0U, // SUB_VG4_M4Z_D_PSEUDO |
| 3531 | 0U, // SUB_VG4_M4Z_S_PSEUDO |
| 3532 | 0U, // SUB_ZPZZ_B_ZERO |
| 3533 | 0U, // SUB_ZPZZ_D_ZERO |
| 3534 | 0U, // SUB_ZPZZ_H_ZERO |
| 3535 | 0U, // SUB_ZPZZ_S_ZERO |
| 3536 | 0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3537 | 0U, // SUDOT_VG2_M2ZZ_BToS_PSEUDO |
| 3538 | 0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3539 | 0U, // SUDOT_VG4_M4ZZ_BToS_PSEUDO |
| 3540 | 0U, // SUMLALL_MZZI_BtoS_PSEUDO |
| 3541 | 0U, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3542 | 0U, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3543 | 0U, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3544 | 0U, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3545 | 0U, // SUMOPA_MPPZZ_D_PSEUDO |
| 3546 | 0U, // SUMOPA_MPPZZ_S_PSEUDO |
| 3547 | 0U, // SUMOPS_MPPZZ_D_PSEUDO |
| 3548 | 0U, // SUMOPS_MPPZZ_S_PSEUDO |
| 3549 | 0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3550 | 0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 3551 | 0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 3552 | 0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3553 | 0U, // SXTB_ZPmZ_D_UNDEF |
| 3554 | 0U, // SXTB_ZPmZ_H_UNDEF |
| 3555 | 0U, // SXTB_ZPmZ_S_UNDEF |
| 3556 | 0U, // SXTH_ZPmZ_D_UNDEF |
| 3557 | 0U, // SXTH_ZPmZ_S_UNDEF |
| 3558 | 0U, // SXTW_ZPmZ_D_UNDEF |
| 3559 | 0U, // SpeculationBarrierISBDSBEndBB |
| 3560 | 0U, // SpeculationBarrierSBEndBB |
| 3561 | 0U, // SpeculationSafeValueW |
| 3562 | 0U, // SpeculationSafeValueX |
| 3563 | 0U, // StoreSwiftAsyncContext |
| 3564 | 0U, // TAGPstack |
| 3565 | 0U, // TCRETURNdi |
| 3566 | 0U, // TCRETURNri |
| 3567 | 0U, // TCRETURNriALL |
| 3568 | 0U, // TCRETURNrinotx16 |
| 3569 | 0U, // TCRETURNrix16x17 |
| 3570 | 0U, // TCRETURNrix17 |
| 3571 | 51822U, // TLSDESCCALL |
| 3572 | 0U, // TLSDESC_CALLSEQ |
| 3573 | 0U, // UABD_ZPZZ_B_UNDEF |
| 3574 | 0U, // UABD_ZPZZ_D_UNDEF |
| 3575 | 0U, // UABD_ZPZZ_H_UNDEF |
| 3576 | 0U, // UABD_ZPZZ_S_UNDEF |
| 3577 | 0U, // UCVTF_ZPmZ_DtoD_UNDEF |
| 3578 | 0U, // UCVTF_ZPmZ_DtoH_UNDEF |
| 3579 | 0U, // UCVTF_ZPmZ_DtoS_UNDEF |
| 3580 | 0U, // UCVTF_ZPmZ_HtoH_UNDEF |
| 3581 | 0U, // UCVTF_ZPmZ_StoD_UNDEF |
| 3582 | 0U, // UCVTF_ZPmZ_StoH_UNDEF |
| 3583 | 0U, // UCVTF_ZPmZ_StoS_UNDEF |
| 3584 | 0U, // UDIV_ZPZZ_D_UNDEF |
| 3585 | 0U, // UDIV_ZPZZ_S_UNDEF |
| 3586 | 0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 3587 | 0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 3588 | 0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 3589 | 0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3590 | 0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 3591 | 0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 3592 | 0U, // UDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 3593 | 0U, // UDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 3594 | 0U, // UDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 3595 | 0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 3596 | 0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 3597 | 0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 3598 | 0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 3599 | 0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 3600 | 0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3601 | 0U, // UDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 3602 | 0U, // UDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 3603 | 0U, // UDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 3604 | 0U, // UMAX_ZPZZ_B_UNDEF |
| 3605 | 0U, // UMAX_ZPZZ_D_UNDEF |
| 3606 | 0U, // UMAX_ZPZZ_H_UNDEF |
| 3607 | 0U, // UMAX_ZPZZ_S_UNDEF |
| 3608 | 0U, // UMIN_ZPZZ_B_UNDEF |
| 3609 | 0U, // UMIN_ZPZZ_D_UNDEF |
| 3610 | 0U, // UMIN_ZPZZ_H_UNDEF |
| 3611 | 0U, // UMIN_ZPZZ_S_UNDEF |
| 3612 | 0U, // UMLALL_MZZI_BtoS_PSEUDO |
| 3613 | 0U, // UMLALL_MZZI_HtoD_PSEUDO |
| 3614 | 0U, // UMLALL_MZZ_BtoS_PSEUDO |
| 3615 | 0U, // UMLALL_MZZ_HtoD_PSEUDO |
| 3616 | 0U, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3617 | 0U, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 3618 | 0U, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3619 | 0U, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 3620 | 0U, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3621 | 0U, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 3622 | 0U, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3623 | 0U, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3624 | 0U, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3625 | 0U, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 3626 | 0U, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3627 | 0U, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 3628 | 0U, // UMLAL_MZZI_HtoS_PSEUDO |
| 3629 | 0U, // UMLAL_MZZ_HtoS_PSEUDO |
| 3630 | 0U, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3631 | 0U, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 3632 | 0U, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 3633 | 0U, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3634 | 0U, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 3635 | 0U, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 3636 | 0U, // UMLSLL_MZZI_BtoS_PSEUDO |
| 3637 | 0U, // UMLSLL_MZZI_HtoD_PSEUDO |
| 3638 | 0U, // UMLSLL_MZZ_BtoS_PSEUDO |
| 3639 | 0U, // UMLSLL_MZZ_HtoD_PSEUDO |
| 3640 | 0U, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3641 | 0U, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 3642 | 0U, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 3643 | 0U, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 3644 | 0U, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 3645 | 0U, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 3646 | 0U, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3647 | 0U, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3648 | 0U, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 3649 | 0U, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 3650 | 0U, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 3651 | 0U, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 3652 | 0U, // UMLSL_MZZI_HtoS_PSEUDO |
| 3653 | 0U, // UMLSL_MZZ_HtoS_PSEUDO |
| 3654 | 0U, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3655 | 0U, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 3656 | 0U, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 3657 | 0U, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3658 | 0U, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 3659 | 0U, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 3660 | 0U, // UMOPA_MPPZZ_D_PSEUDO |
| 3661 | 0U, // UMOPA_MPPZZ_HtoS_PSEUDO |
| 3662 | 0U, // UMOPA_MPPZZ_S_PSEUDO |
| 3663 | 0U, // UMOPS_MPPZZ_D_PSEUDO |
| 3664 | 0U, // UMOPS_MPPZZ_HtoS_PSEUDO |
| 3665 | 0U, // UMOPS_MPPZZ_S_PSEUDO |
| 3666 | 0U, // UMULH_ZPZZ_B_UNDEF |
| 3667 | 0U, // UMULH_ZPZZ_D_UNDEF |
| 3668 | 0U, // UMULH_ZPZZ_H_UNDEF |
| 3669 | 0U, // UMULH_ZPZZ_S_UNDEF |
| 3670 | 0U, // UQRSHL_ZPZZ_B_UNDEF |
| 3671 | 0U, // UQRSHL_ZPZZ_D_UNDEF |
| 3672 | 0U, // UQRSHL_ZPZZ_H_UNDEF |
| 3673 | 0U, // UQRSHL_ZPZZ_S_UNDEF |
| 3674 | 0U, // UQSHL_ZPZI_B_ZERO |
| 3675 | 0U, // UQSHL_ZPZI_D_ZERO |
| 3676 | 0U, // UQSHL_ZPZI_H_ZERO |
| 3677 | 0U, // UQSHL_ZPZI_S_ZERO |
| 3678 | 0U, // UQSHL_ZPZZ_B_UNDEF |
| 3679 | 0U, // UQSHL_ZPZZ_D_UNDEF |
| 3680 | 0U, // UQSHL_ZPZZ_H_UNDEF |
| 3681 | 0U, // UQSHL_ZPZZ_S_UNDEF |
| 3682 | 0U, // URECPE_ZPmZ_S_UNDEF |
| 3683 | 0U, // URSHL_ZPZZ_B_UNDEF |
| 3684 | 0U, // URSHL_ZPZZ_D_UNDEF |
| 3685 | 0U, // URSHL_ZPZZ_H_UNDEF |
| 3686 | 0U, // URSHL_ZPZZ_S_UNDEF |
| 3687 | 0U, // URSHR_ZPZI_B_ZERO |
| 3688 | 0U, // URSHR_ZPZI_D_ZERO |
| 3689 | 0U, // URSHR_ZPZI_H_ZERO |
| 3690 | 0U, // URSHR_ZPZI_S_ZERO |
| 3691 | 0U, // URSQRTE_ZPmZ_S_UNDEF |
| 3692 | 0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 3693 | 0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3694 | 0U, // USDOT_VG2_M2ZZ_BToS_PSEUDO |
| 3695 | 0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 3696 | 0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3697 | 0U, // USDOT_VG4_M4ZZ_BToS_PSEUDO |
| 3698 | 0U, // USMLALL_MZZI_BtoS_PSEUDO |
| 3699 | 0U, // USMLALL_MZZ_BtoS_PSEUDO |
| 3700 | 0U, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3701 | 0U, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3702 | 0U, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3703 | 0U, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3704 | 0U, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3705 | 0U, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3706 | 0U, // USMOPA_MPPZZ_D_PSEUDO |
| 3707 | 0U, // USMOPA_MPPZZ_S_PSEUDO |
| 3708 | 0U, // USMOPS_MPPZZ_D_PSEUDO |
| 3709 | 0U, // USMOPS_MPPZZ_S_PSEUDO |
| 3710 | 0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3711 | 0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 3712 | 0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 3713 | 0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3714 | 0U, // UXTB_ZPmZ_D_UNDEF |
| 3715 | 0U, // UXTB_ZPmZ_H_UNDEF |
| 3716 | 0U, // UXTB_ZPmZ_S_UNDEF |
| 3717 | 0U, // UXTH_ZPmZ_D_UNDEF |
| 3718 | 0U, // UXTH_ZPmZ_S_UNDEF |
| 3719 | 0U, // UXTW_ZPmZ_D_UNDEF |
| 3720 | 0U, // VGRestorePseudo |
| 3721 | 0U, // VGSavePseudo |
| 3722 | 0U, // ZERO_MXI_2Z_PSEUDO |
| 3723 | 0U, // ZERO_MXI_4Z_PSEUDO |
| 3724 | 0U, // ZERO_MXI_VG2_2Z_PSEUDO |
| 3725 | 0U, // ZERO_MXI_VG2_4Z_PSEUDO |
| 3726 | 0U, // ZERO_MXI_VG2_Z_PSEUDO |
| 3727 | 0U, // ZERO_MXI_VG4_2Z_PSEUDO |
| 3728 | 0U, // ZERO_MXI_VG4_4Z_PSEUDO |
| 3729 | 0U, // ZERO_MXI_VG4_Z_PSEUDO |
| 3730 | 0U, // ZERO_M_PSEUDO |
| 3731 | 0U, // ZERO_T_PSEUDO |
| 3732 | 4244252U, // ABSWr |
| 3733 | 4244252U, // ABSXr |
| 3734 | 541147932U, // ABS_ZPmZ_B |
| 3735 | 541180700U, // ABS_ZPmZ_D |
| 3736 | 1082278684U, // ABS_ZPmZ_H |
| 3737 | 541246236U, // ABS_ZPmZ_S |
| 3738 | 1615005391U, // ABSv16i8 |
| 3739 | 4244252U, // ABSv1i64 |
| 3740 | 1615018136U, // ABSv2i32 |
| 3741 | 1615009211U, // ABSv2i64 |
| 3742 | 1615011453U, // ABSv4i16 |
| 3743 | 1615020246U, // ABSv4i32 |
| 3744 | 1615013430U, // ABSv8i16 |
| 3745 | 1615006350U, // ABSv8i8 |
| 3746 | 2151779550U, // ADCLB_ZZZ_D |
| 3747 | 2688715998U, // ADCLB_ZZZ_S |
| 3748 | 2151793940U, // ADCLT_ZZZ_D |
| 3749 | 2688730388U, // ADCLT_ZZZ_S |
| 3750 | 4244291U, // ADCSWr |
| 3751 | 4244291U, // ADCSXr |
| 3752 | 4231202U, // ADCWr |
| 3753 | 4231202U, // ADCXr |
| 3754 | 4233483U, // ADDG |
| 3755 | 3234038073U, // ADDHA_MPPZ_D |
| 3756 | 3238232377U, // ADDHA_MPPZ_S |
| 3757 | 3762359747U, // ADDHNB_ZZZ_B |
| 3758 | 21106115U, // ADDHNB_ZZZ_H |
| 3759 | 541232579U, // ADDHNB_ZZZ_S |
| 3760 | 1078019547U, // ADDHNT_ZZZ_B |
| 3761 | 25314779U, // ADDHNT_ZZZ_H |
| 3762 | 2151859675U, // ADDHNT_ZZZ_S |
| 3763 | 1615017751U, // ADDHNv2i64_v2i32 |
| 3764 | 1615084391U, // ADDHNv2i64_v4i32 |
| 3765 | 1615011057U, // ADDHNv4i32_v4i16 |
| 3766 | 1615077701U, // ADDHNv4i32_v8i16 |
| 3767 | 1615070118U, // ADDHNv8i16_v16i8 |
| 3768 | 1615006090U, // ADDHNv8i16_v8i8 |
| 3769 | 4238670U, // ADDPL_XXI |
| 3770 | 4245151U, // ADDPT_shift |
| 3771 | 2151755832U, // ADDP_ZPmZ_B |
| 3772 | 2151788600U, // ADDP_ZPmZ_D |
| 3773 | 2713858104U, // ADDP_ZPmZ_H |
| 3774 | 2151854136U, // ADDP_ZPmZ_S |
| 3775 | 1615005256U, // ADDPv16i8 |
| 3776 | 1615017912U, // ADDPv2i32 |
| 3777 | 1615009027U, // ADDPv2i64 |
| 3778 | 1614845187U, // ADDPv2i64p |
| 3779 | 1615011229U, // ADDPv4i16 |
| 3780 | 1615020022U, // ADDPv4i32 |
| 3781 | 1615013206U, // ADDPv8i16 |
| 3782 | 1615006228U, // ADDPv8i8 |
| 3783 | 2181253104U, // ADDQV_VPZ_B |
| 3784 | 2185447408U, // ADDQV_VPZ_D |
| 3785 | 2189641712U, // ADDQV_VPZ_H |
| 3786 | 2193836016U, // ADDQV_VPZ_S |
| 3787 | 4238749U, // ADDSPL_XXI |
| 3788 | 4238996U, // ADDSVL_XXI |
| 3789 | 4244303U, // ADDSWri |
| 3790 | 4244303U, // ADDSWrs |
| 3791 | 4244303U, // ADDSWrx |
| 3792 | 4244303U, // ADDSXri |
| 3793 | 4244303U, // ADDSXrs |
| 3794 | 4244303U, // ADDSXrx |
| 3795 | 4244303U, // ADDSXrx64 |
| 3796 | 3234038451U, // ADDVA_MPPZ_D |
| 3797 | 3238232755U, // ADDVA_MPPZ_S |
| 3798 | 4238983U, // ADDVL_XXI |
| 3799 | 1614841668U, // ADDVv16i8v |
| 3800 | 1614847840U, // ADDVv4i16v |
| 3801 | 1614856633U, // ADDVv4i32v |
| 3802 | 1614849817U, // ADDVv8i16v |
| 3803 | 1614842615U, // ADDVv8i8v |
| 3804 | 4233130U, // ADDWri |
| 3805 | 4233130U, // ADDWrs |
| 3806 | 4233130U, // ADDWrx |
| 3807 | 4233130U, // ADDXri |
| 3808 | 4233130U, // ADDXrs |
| 3809 | 4233130U, // ADDXrx |
| 3810 | 4233130U, // ADDXrx64 |
| 3811 | 50632618U, // ADD_VG2_2ZZ_B |
| 3812 | 54859690U, // ADD_VG2_2ZZ_D |
| 3813 | 59086762U, // ADD_VG2_2ZZ_H |
| 3814 | 63313834U, // ADD_VG2_2ZZ_S |
| 3815 | 3288766378U, // ADD_VG2_M2Z2Z_D |
| 3816 | 3288799146U, // ADD_VG2_M2Z2Z_S |
| 3817 | 3288766378U, // ADD_VG2_M2ZZ_D |
| 3818 | 3288799146U, // ADD_VG2_M2ZZ_S |
| 3819 | 3288766378U, // ADD_VG2_M2Z_D |
| 3820 | 3288799146U, // ADD_VG2_M2Z_S |
| 3821 | 50632618U, // ADD_VG4_4ZZ_B |
| 3822 | 54859690U, // ADD_VG4_4ZZ_D |
| 3823 | 59086762U, // ADD_VG4_4ZZ_H |
| 3824 | 63313834U, // ADD_VG4_4ZZ_S |
| 3825 | 3825637290U, // ADD_VG4_M4Z4Z_D |
| 3826 | 3825670058U, // ADD_VG4_M4Z4Z_S |
| 3827 | 3825637290U, // ADD_VG4_M4ZZ_D |
| 3828 | 3825670058U, // ADD_VG4_M4ZZ_S |
| 3829 | 3825637290U, // ADD_VG4_M4Z_D |
| 3830 | 3825670058U, // ADD_VG4_M4Z_S |
| 3831 | 4265898U, // ADD_ZI_B |
| 3832 | 541169578U, // ADD_ZI_D |
| 3833 | 71440298U, // ADD_ZI_H |
| 3834 | 541235114U, // ADD_ZI_S |
| 3835 | 2151749546U, // ADD_ZPmZ_B |
| 3836 | 2151794335U, // ADD_ZPmZ_CPA |
| 3837 | 2151782314U, // ADD_ZPmZ_D |
| 3838 | 2713851818U, // ADD_ZPmZ_H |
| 3839 | 2151847850U, // ADD_ZPmZ_S |
| 3840 | 4265898U, // ADD_ZZZ_B |
| 3841 | 541181599U, // ADD_ZZZ_CPA |
| 3842 | 541169578U, // ADD_ZZZ_D |
| 3843 | 71440298U, // ADD_ZZZ_H |
| 3844 | 541235114U, // ADD_ZZZ_S |
| 3845 | 1615004946U, // ADDv16i8 |
| 3846 | 4233130U, // ADDv1i64 |
| 3847 | 1615017305U, // ADDv2i32 |
| 3848 | 1615008479U, // ADDv2i64 |
| 3849 | 1615010634U, // ADDv4i16 |
| 3850 | 1615019302U, // ADDv4i32 |
| 3851 | 1615012552U, // ADDv8i16 |
| 3852 | 1615005842U, // ADDv8i8 |
| 3853 | 1077981837U, // ADR |
| 3854 | 1077981407U, // ADRP |
| 3855 | 612479629U, // ADR_LSL_ZZZ_D_0 |
| 3856 | 612479629U, // ADR_LSL_ZZZ_D_1 |
| 3857 | 612479629U, // ADR_LSL_ZZZ_D_2 |
| 3858 | 612479629U, // ADR_LSL_ZZZ_D_3 |
| 3859 | 612545165U, // ADR_LSL_ZZZ_S_0 |
| 3860 | 612545165U, // ADR_LSL_ZZZ_S_1 |
| 3861 | 612545165U, // ADR_LSL_ZZZ_S_2 |
| 3862 | 612545165U, // ADR_LSL_ZZZ_S_3 |
| 3863 | 612479629U, // ADR_SXTW_ZZZ_D_0 |
| 3864 | 612479629U, // ADR_SXTW_ZZZ_D_1 |
| 3865 | 612479629U, // ADR_SXTW_ZZZ_D_2 |
| 3866 | 612479629U, // ADR_SXTW_ZZZ_D_3 |
| 3867 | 612479629U, // ADR_UXTW_ZZZ_D_0 |
| 3868 | 612479629U, // ADR_UXTW_ZZZ_D_1 |
| 3869 | 612479629U, // ADR_UXTW_ZZZ_D_2 |
| 3870 | 612479629U, // ADR_UXTW_ZZZ_D_3 |
| 3871 | 4266027U, // AESD_ZZZ_B |
| 3872 | 1615070558U, // AESDrr |
| 3873 | 4266174U, // AESE_ZZZ_B |
| 3874 | 1615070588U, // AESErr |
| 3875 | 4263980U, // AESIMC_ZZ_B |
| 3876 | 1615004900U, // AESIMCrr |
| 3877 | 4263988U, // AESMC_ZZ_B |
| 3878 | 1615004912U, // AESMCrr |
| 3879 | 2181253111U, // ANDQV_VPZ_B |
| 3880 | 2185447415U, // ANDQV_VPZ_D |
| 3881 | 2189641719U, // ANDQV_VPZ_H |
| 3882 | 2193836023U, // ANDQV_VPZ_S |
| 3883 | 4244310U, // ANDSWri |
| 3884 | 4244310U, // ANDSWrs |
| 3885 | 4244310U, // ANDSXri |
| 3886 | 4244310U, // ANDSXrs |
| 3887 | 2151760726U, // ANDS_PPzPP |
| 3888 | 509848U, // ANDV_VPZ_B |
| 3889 | 3301459864U, // ANDV_VPZ_D |
| 3890 | 3305686936U, // ANDV_VPZ_H |
| 3891 | 3246999448U, // ANDV_VPZ_S |
| 3892 | 4233225U, // ANDWri |
| 3893 | 4233225U, // ANDWrs |
| 3894 | 4233225U, // ANDXri |
| 3895 | 4233225U, // ANDXrs |
| 3896 | 2151749641U, // AND_PPzPP |
| 3897 | 541169673U, // AND_ZI |
| 3898 | 2151749641U, // AND_ZPmZ_B |
| 3899 | 2151782409U, // AND_ZPmZ_D |
| 3900 | 2713851913U, // AND_ZPmZ_H |
| 3901 | 2151847945U, // AND_ZPmZ_S |
| 3902 | 541169673U, // AND_ZZZ |
| 3903 | 1615005013U, // ANDv16i8 |
| 3904 | 1615005903U, // ANDv8i8 |
| 3905 | 2151749669U, // ASRD_ZPmI_B |
| 3906 | 2151782437U, // ASRD_ZPmI_D |
| 3907 | 2713851941U, // ASRD_ZPmI_H |
| 3908 | 2151847973U, // ASRD_ZPmI_S |
| 3909 | 2151756622U, // ASRR_ZPmZ_B |
| 3910 | 2151789390U, // ASRR_ZPmZ_D |
| 3911 | 2713858894U, // ASRR_ZPmZ_H |
| 3912 | 2151854926U, // ASRR_ZPmZ_S |
| 3913 | 4240224U, // ASRVWr |
| 3914 | 4240224U, // ASRVXr |
| 3915 | 2151756640U, // ASR_WIDE_ZPmZ_B |
| 3916 | 2713858912U, // ASR_WIDE_ZPmZ_H |
| 3917 | 2151854944U, // ASR_WIDE_ZPmZ_S |
| 3918 | 4272992U, // ASR_WIDE_ZZZ_B |
| 3919 | 71447392U, // ASR_WIDE_ZZZ_H |
| 3920 | 541242208U, // ASR_WIDE_ZZZ_S |
| 3921 | 2151756640U, // ASR_ZPmI_B |
| 3922 | 2151789408U, // ASR_ZPmI_D |
| 3923 | 2713858912U, // ASR_ZPmI_H |
| 3924 | 2151854944U, // ASR_ZPmI_S |
| 3925 | 2151756640U, // ASR_ZPmZ_B |
| 3926 | 2151789408U, // ASR_ZPmZ_D |
| 3927 | 2713858912U, // ASR_ZPmZ_H |
| 3928 | 2151854944U, // ASR_ZPmZ_S |
| 3929 | 4272992U, // ASR_ZZI_B |
| 3930 | 541176672U, // ASR_ZZI_D |
| 3931 | 71447392U, // ASR_ZZI_H |
| 3932 | 541242208U, // ASR_ZZI_S |
| 3933 | 1615429931U, // AUTDA |
| 3934 | 1615432712U, // AUTDB |
| 3935 | 623322U, // AUTDZA |
| 3936 | 626693U, // AUTDZB |
| 3937 | 1615429959U, // AUTIA |
| 3938 | 19267U, // AUTIA1716 |
| 3939 | 19327U, // AUTIA171615 |
| 3940 | 19428U, // AUTIASP |
| 3941 | 659533U, // AUTIASPPCi |
| 3942 | 45673U, // AUTIASPPCr |
| 3943 | 19413U, // AUTIAZ |
| 3944 | 1615432739U, // AUTIB |
| 3945 | 19297U, // AUTIB1716 |
| 3946 | 19351U, // AUTIB171615 |
| 3947 | 19258U, // AUTIBSP |
| 3948 | 659555U, // AUTIBSPPCi |
| 3949 | 45697U, // AUTIBSPPCr |
| 3950 | 19240U, // AUTIBZ |
| 3951 | 623338U, // AUTIZA |
| 3952 | 626709U, // AUTIZB |
| 3953 | 20841U, // AXFLAG |
| 3954 | 656118U, // B |
| 3955 | 1615005586U, // BCAX |
| 3956 | 541182353U, // BCAX_ZZZZ |
| 3957 | 707238U, // BCcc |
| 3958 | 4272195U, // BDEP_ZZZ_B |
| 3959 | 541175875U, // BDEP_ZZZ_D |
| 3960 | 71446595U, // BDEP_ZZZ_H |
| 3961 | 541241411U, // BDEP_ZZZ_S |
| 3962 | 4278055U, // BEXT_ZZZ_B |
| 3963 | 541181735U, // BEXT_ZZZ_D |
| 3964 | 71452455U, // BEXT_ZZZ_H |
| 3965 | 541247271U, // BEXT_ZZZ_S |
| 3966 | 1615087189U, // BF16DOTlanev4bf16 |
| 3967 | 1615087189U, // BF16DOTlanev8bf16 |
| 3968 | 1615012126U, // BF1CVTL2v8f16 |
| 3969 | 3309454764U, // BF1CVTLT_ZZ_BtoH |
| 3970 | 3309678162U, // BF1CVTL_2ZZ_BtoH_NAME |
| 3971 | 1615013091U, // BF1CVTLv8f16 |
| 3972 | 3309684444U, // BF1CVT_2ZZ_BtoH_NAME |
| 3973 | 3309455068U, // BF1CVT_ZZ_BtoH |
| 3974 | 1615012139U, // BF2CVTL2v8f16 |
| 3975 | 3309454774U, // BF2CVTLT_ZZ_BtoH |
| 3976 | 3309678171U, // BF2CVTL_2ZZ_BtoH_NAME |
| 3977 | 1615013103U, // BF2CVTLv8f16 |
| 3978 | 3309684452U, // BF2CVT_2ZZ_BtoH_NAME |
| 3979 | 3309455076U, // BF2CVT_ZZ_BtoH |
| 3980 | 3289061310U, // BFADD_VG2_M2Z_H |
| 3981 | 3825932222U, // BFADD_VG4_M4Z_H |
| 3982 | 2713851838U, // BFADD_ZPmZZ |
| 3983 | 71440318U, // BFADD_ZZZ |
| 3984 | 84258923U, // BFCLAMP_VG2_2ZZZ_H |
| 3985 | 84258923U, // BFCLAMP_VG4_4ZZZ_H |
| 3986 | 84029547U, // BFCLAMP_ZZZ |
| 3987 | 4245228U, // BFCVT |
| 3988 | 1615011161U, // BFCVTN |
| 3989 | 1615077771U, // BFCVTN2 |
| 3990 | 2156021263U, // BFCVTNT_ZPmZ |
| 3991 | 2688626561U, // BFCVTN_Z2Z_HtoB |
| 3992 | 3284283265U, // BFCVTN_Z2Z_StoH |
| 3993 | 2688632556U, // BFCVT_Z2Z_HtoB |
| 3994 | 3284289260U, // BFCVT_Z2Z_StoH |
| 3995 | 2156021484U, // BFCVT_ZPmZ |
| 3996 | 3288811093U, // BFDOT_VG2_M2Z2Z_HtoS |
| 3997 | 3288811093U, // BFDOT_VG2_M2ZZI_HtoS |
| 3998 | 3288811093U, // BFDOT_VG2_M2ZZ_HtoS |
| 3999 | 3825682005U, // BFDOT_VG4_M4Z4Z_HtoS |
| 4000 | 3825682005U, // BFDOT_VG4_M4ZZI_HtoS |
| 4001 | 3825682005U, // BFDOT_VG4_M4ZZ_HtoS |
| 4002 | 1078117973U, // BFDOT_ZZI |
| 4003 | 1078117973U, // BFDOT_ZZZ |
| 4004 | 20933U, // BFDOTv4bf16 |
| 4005 | 20933U, // BFDOTv8bf16 |
| 4006 | 59092718U, // BFMAXNM_VG2_2Z2Z_H |
| 4007 | 59092718U, // BFMAXNM_VG2_2ZZ_H |
| 4008 | 59092718U, // BFMAXNM_VG4_4Z2Z_H |
| 4009 | 59092718U, // BFMAXNM_VG4_4ZZ_H |
| 4010 | 2713857774U, // BFMAXNM_ZPmZZ |
| 4011 | 59099550U, // BFMAX_VG2_2Z2Z_H |
| 4012 | 59099550U, // BFMAX_VG2_2ZZ_H |
| 4013 | 59099550U, // BFMAX_VG4_4Z2Z_H |
| 4014 | 59099550U, // BFMAX_VG4_4ZZ_H |
| 4015 | 2713864606U, // BFMAX_ZPmZZ |
| 4016 | 59092709U, // BFMINNM_VG2_2Z2Z_H |
| 4017 | 59092709U, // BFMINNM_VG2_2ZZ_H |
| 4018 | 59092709U, // BFMINNM_VG4_4Z2Z_H |
| 4019 | 59092709U, // BFMINNM_VG4_4ZZ_H |
| 4020 | 2713857765U, // BFMINNM_ZPmZZ |
| 4021 | 59092778U, // BFMIN_VG2_2Z2Z_H |
| 4022 | 59092778U, // BFMIN_VG2_2ZZ_H |
| 4023 | 59092778U, // BFMIN_VG4_4Z2Z_H |
| 4024 | 59092778U, // BFMIN_VG4_4ZZ_H |
| 4025 | 2713857834U, // BFMIN_ZPmZZ |
| 4026 | 20758U, // BFMLALB |
| 4027 | 20758U, // BFMLALBIdx |
| 4028 | 1078103124U, // BFMLALB_ZZZ |
| 4029 | 1078103124U, // BFMLALB_ZZZI |
| 4030 | 20925U, // BFMLALT |
| 4031 | 20925U, // BFMLALTIdx |
| 4032 | 1078117604U, // BFMLALT_ZZZ |
| 4033 | 1078117604U, // BFMLALT_ZZZI |
| 4034 | 3313970025U, // BFMLAL_MZZI_HtoS |
| 4035 | 3313970025U, // BFMLAL_MZZ_HtoS |
| 4036 | 3313970025U, // BFMLAL_VG2_M2Z2Z_HtoS |
| 4037 | 3313970025U, // BFMLAL_VG2_M2ZZI_HtoS |
| 4038 | 3313970025U, // BFMLAL_VG2_M2ZZ_HtoS |
| 4039 | 3850840937U, // BFMLAL_VG4_M4Z4Z_HtoS |
| 4040 | 3850840937U, // BFMLAL_VG4_M4ZZI_HtoS |
| 4041 | 3850840937U, // BFMLAL_VG4_M4ZZ_HtoS |
| 4042 | 3289055579U, // BFMLA_VG2_M2Z2Z |
| 4043 | 3289055579U, // BFMLA_VG2_M2ZZ |
| 4044 | 3289055579U, // BFMLA_VG2_M2ZZI |
| 4045 | 3825926491U, // BFMLA_VG4_M4Z4Z |
| 4046 | 3825926491U, // BFMLA_VG4_M4ZZ |
| 4047 | 3825926491U, // BFMLA_VG4_M4ZZI |
| 4048 | 2713846107U, // BFMLA_ZPmZZ |
| 4049 | 84017499U, // BFMLA_ZZZI |
| 4050 | 1078103422U, // BFMLSLB_ZZZI_S |
| 4051 | 1078103422U, // BFMLSLB_ZZZ_S |
| 4052 | 1078117779U, // BFMLSLT_ZZZI_S |
| 4053 | 1078117779U, // BFMLSLT_ZZZ_S |
| 4054 | 3313970715U, // BFMLSL_MZZI_HtoS |
| 4055 | 3313970715U, // BFMLSL_MZZ_HtoS |
| 4056 | 3313970715U, // BFMLSL_VG2_M2Z2Z_HtoS |
| 4057 | 3313970715U, // BFMLSL_VG2_M2ZZI_HtoS |
| 4058 | 3313970715U, // BFMLSL_VG2_M2ZZ_HtoS |
| 4059 | 3850841627U, // BFMLSL_VG4_M4Z4Z_HtoS |
| 4060 | 3850841627U, // BFMLSL_VG4_M4ZZI_HtoS |
| 4061 | 3850841627U, // BFMLSL_VG4_M4ZZ_HtoS |
| 4062 | 3289072520U, // BFMLS_VG2_M2Z2Z |
| 4063 | 3289072520U, // BFMLS_VG2_M2ZZ |
| 4064 | 3289072520U, // BFMLS_VG2_M2ZZI |
| 4065 | 3825943432U, // BFMLS_VG4_M4Z4Z |
| 4066 | 3825943432U, // BFMLS_VG4_M4ZZ |
| 4067 | 3825943432U, // BFMLS_VG4_M4ZZI |
| 4068 | 2713863048U, // BFMLS_ZPmZZ |
| 4069 | 84034440U, // BFMLS_ZZZI |
| 4070 | 20722U, // BFMMLA |
| 4071 | 1078100322U, // BFMMLA_ZZZ |
| 4072 | 96698784U, // BFMOPA_MPPZZ |
| 4073 | 96698784U, // BFMOPA_MPPZZ_H |
| 4074 | 96715728U, // BFMOPS_MPPZZ |
| 4075 | 96715728U, // BFMOPS_MPPZZ_H |
| 4076 | 2713857643U, // BFMUL_ZPmZZ |
| 4077 | 71446123U, // BFMUL_ZZZ |
| 4078 | 71446123U, // BFMUL_ZZZI |
| 4079 | 1614851766U, // BFMWri |
| 4080 | 1614851766U, // BFMXri |
| 4081 | 3289059219U, // BFSUB_VG2_M2Z_H |
| 4082 | 3825930131U, // BFSUB_VG4_M4Z_H |
| 4083 | 2713849747U, // BFSUB_ZPmZZ |
| 4084 | 71438227U, // BFSUB_ZZZ |
| 4085 | 3288811114U, // BFVDOT_VG2_M2ZZI_HtoS |
| 4086 | 4272357U, // BGRP_ZZZ_B |
| 4087 | 541176037U, // BGRP_ZZZ_D |
| 4088 | 71446757U, // BGRP_ZZZ_H |
| 4089 | 541241573U, // BGRP_ZZZ_S |
| 4090 | 4244297U, // BICSWrs |
| 4091 | 4244297U, // BICSXrs |
| 4092 | 2151760713U, // BICS_PPzPP |
| 4093 | 4231207U, // BICWrs |
| 4094 | 4231207U, // BICXrs |
| 4095 | 2151747623U, // BIC_PPzPP |
| 4096 | 2151747623U, // BIC_ZPmZ_B |
| 4097 | 2151780391U, // BIC_ZPmZ_D |
| 4098 | 2713849895U, // BIC_ZPmZ_H |
| 4099 | 2151845927U, // BIC_ZPmZ_S |
| 4100 | 541167655U, // BIC_ZZZ |
| 4101 | 1615004891U, // BICv16i8 |
| 4102 | 3762566452U, // BICv2i32 |
| 4103 | 3762559781U, // BICv4i16 |
| 4104 | 3762568449U, // BICv4i32 |
| 4105 | 3762561699U, // BICv8i16 |
| 4106 | 1615005813U, // BICv8i8 |
| 4107 | 1615070598U, // BIFv16i8 |
| 4108 | 1615071465U, // BIFv8i8 |
| 4109 | 1615070975U, // BITv16i8 |
| 4110 | 1615071929U, // BITv8i8 |
| 4111 | 666759U, // BL |
| 4112 | 45775U, // BLR |
| 4113 | 4227330U, // BLRAA |
| 4114 | 51746U, // BLRAAZ |
| 4115 | 4230025U, // BLRAB |
| 4116 | 51768U, // BLRABZ |
| 4117 | 17007001U, // BMOPA_MPPZZ_S |
| 4118 | 17023945U, // BMOPS_MPPZZ_S |
| 4119 | 45625U, // BR |
| 4120 | 4227317U, // BRAA |
| 4121 | 51739U, // BRAAZ |
| 4122 | 4230012U, // BRAB |
| 4123 | 51761U, // BRABZ |
| 4124 | 20876U, // BRB_IALL |
| 4125 | 20848U, // BRB_INJ |
| 4126 | 764748U, // BRK |
| 4127 | 2151760644U, // BRKAS_PPzP |
| 4128 | 541131086U, // BRKA_PPmP |
| 4129 | 2151743822U, // BRKA_PPzP |
| 4130 | 2151760680U, // BRKBS_PPzP |
| 4131 | 541133866U, // BRKB_PPmP |
| 4132 | 2151746602U, // BRKB_PPzP |
| 4133 | 2151760805U, // BRKNS_PPzP |
| 4134 | 2151755585U, // BRKN_PPzP |
| 4135 | 2151760651U, // BRKPAS_PPzPP |
| 4136 | 2151743890U, // BRKPA_PPzPP |
| 4137 | 2151760687U, // BRKPBS_PPzPP |
| 4138 | 2151747137U, // BRKPB_PPzPP |
| 4139 | 541175573U, // BSL1N_ZZZZ |
| 4140 | 541175580U, // BSL2N_ZZZZ |
| 4141 | 541175309U, // BSL_ZZZZ |
| 4142 | 1615070744U, // BSLv16i8 |
| 4143 | 1615071597U, // BSLv8i8 |
| 4144 | 707235U, // Bcc |
| 4145 | 4265897U, // CADD_ZZI_B |
| 4146 | 541169577U, // CADD_ZZI_D |
| 4147 | 71440297U, // CADD_ZZI_H |
| 4148 | 541235113U, // CADD_ZZI_S |
| 4149 | 1615432610U, // CASAB |
| 4150 | 1615439966U, // CASAH |
| 4151 | 1615432863U, // CASALB |
| 4152 | 1615440125U, // CASALH |
| 4153 | 1615440963U, // CASALW |
| 4154 | 1615440963U, // CASALX |
| 4155 | 1615430265U, // CASAW |
| 4156 | 1615430265U, // CASAX |
| 4157 | 1615433484U, // CASB |
| 4158 | 1615440510U, // CASH |
| 4159 | 1615433069U, // CASLB |
| 4160 | 1615440219U, // CASLH |
| 4161 | 1615441405U, // CASLW |
| 4162 | 1615441405U, // CASLX |
| 4163 | 797647U, // CASPALW |
| 4164 | 830415U, // CASPALX |
| 4165 | 786927U, // CASPAW |
| 4166 | 819695U, // CASPAX |
| 4167 | 798092U, // CASPLW |
| 4168 | 830860U, // CASPLX |
| 4169 | 798986U, // CASPW |
| 4170 | 831754U, // CASPX |
| 4171 | 1615446775U, // CASW |
| 4172 | 1615446775U, // CASX |
| 4173 | 4246095U, // CBNZW |
| 4174 | 4246095U, // CBNZX |
| 4175 | 4246080U, // CBZW |
| 4176 | 4246080U, // CBZX |
| 4177 | 4239175U, // CCMNWi |
| 4178 | 4239175U, // CCMNWr |
| 4179 | 4239175U, // CCMNXi |
| 4180 | 4239175U, // CCMNXr |
| 4181 | 4239493U, // CCMPWi |
| 4182 | 4239493U, // CCMPWr |
| 4183 | 4239493U, // CCMPXi |
| 4184 | 4239493U, // CCMPXr |
| 4185 | 1078052431U, // CDOT_ZZZI_D |
| 4186 | 541247055U, // CDOT_ZZZI_S |
| 4187 | 1078052431U, // CDOT_ZZZ_D |
| 4188 | 541247055U, // CDOT_ZZZ_S |
| 4189 | 20966U, // CFINV |
| 4190 | 19249U, // CHKFEAT |
| 4191 | 2151711403U, // CLASTA_RPZ_B |
| 4192 | 2151711403U, // CLASTA_RPZ_D |
| 4193 | 2151711403U, // CLASTA_RPZ_H |
| 4194 | 2151711403U, // CLASTA_RPZ_S |
| 4195 | 2151711403U, // CLASTA_VPZ_B |
| 4196 | 2151711403U, // CLASTA_VPZ_D |
| 4197 | 2151711403U, // CLASTA_VPZ_H |
| 4198 | 2151711403U, // CLASTA_VPZ_S |
| 4199 | 2151744171U, // CLASTA_ZPZ_B |
| 4200 | 2151776939U, // CLASTA_ZPZ_D |
| 4201 | 29491883U, // CLASTA_ZPZ_H |
| 4202 | 2151842475U, // CLASTA_ZPZ_S |
| 4203 | 2151714687U, // CLASTB_RPZ_B |
| 4204 | 2151714687U, // CLASTB_RPZ_D |
| 4205 | 2151714687U, // CLASTB_RPZ_H |
| 4206 | 2151714687U, // CLASTB_RPZ_S |
| 4207 | 2151714687U, // CLASTB_VPZ_B |
| 4208 | 2151714687U, // CLASTB_VPZ_D |
| 4209 | 2151714687U, // CLASTB_VPZ_H |
| 4210 | 2151714687U, // CLASTB_VPZ_S |
| 4211 | 2151747455U, // CLASTB_ZPZ_B |
| 4212 | 2151780223U, // CLASTB_ZPZ_D |
| 4213 | 29495167U, // CLASTB_ZPZ_H |
| 4214 | 2151845759U, // CLASTB_ZPZ_S |
| 4215 | 51658U, // CLREX |
| 4216 | 4244346U, // CLSWr |
| 4217 | 4244346U, // CLSXr |
| 4218 | 541148026U, // CLS_ZPmZ_B |
| 4219 | 541180794U, // CLS_ZPmZ_D |
| 4220 | 1082278778U, // CLS_ZPmZ_H |
| 4221 | 541246330U, // CLS_ZPmZ_S |
| 4222 | 1615005410U, // CLSv16i8 |
| 4223 | 1615018163U, // CLSv2i32 |
| 4224 | 1615011480U, // CLSv4i16 |
| 4225 | 1615020273U, // CLSv4i32 |
| 4226 | 1615013457U, // CLSv8i16 |
| 4227 | 1615006367U, // CLSv8i8 |
| 4228 | 4246090U, // CLZWr |
| 4229 | 4246090U, // CLZXr |
| 4230 | 541149770U, // CLZ_ZPmZ_B |
| 4231 | 541182538U, // CLZ_ZPmZ_D |
| 4232 | 1082280522U, // CLZ_ZPmZ_H |
| 4233 | 541248074U, // CLZ_ZPmZ_S |
| 4234 | 1615005616U, // CLZv16i8 |
| 4235 | 1615018491U, // CLZv2i32 |
| 4236 | 1615011871U, // CLZv4i16 |
| 4237 | 1615020768U, // CLZv4i32 |
| 4238 | 1615013888U, // CLZv8i16 |
| 4239 | 1615006544U, // CLZv8i8 |
| 4240 | 1615005319U, // CMEQv16i8 |
| 4241 | 1615005319U, // CMEQv16i8rz |
| 4242 | 4239838U, // CMEQv1i64 |
| 4243 | 4239838U, // CMEQv1i64rz |
| 4244 | 1615018069U, // CMEQv2i32 |
| 4245 | 1615018069U, // CMEQv2i32rz |
| 4246 | 1615009144U, // CMEQv2i64 |
| 4247 | 1615009144U, // CMEQv2i64rz |
| 4248 | 1615011386U, // CMEQv4i16 |
| 4249 | 1615011386U, // CMEQv4i16rz |
| 4250 | 1615020179U, // CMEQv4i32 |
| 4251 | 1615020179U, // CMEQv4i32rz |
| 4252 | 1615013363U, // CMEQv8i16 |
| 4253 | 1615013363U, // CMEQv8i16rz |
| 4254 | 1615006285U, // CMEQv8i8 |
| 4255 | 1615006285U, // CMEQv8i8rz |
| 4256 | 1615005032U, // CMGEv16i8 |
| 4257 | 1615005032U, // CMGEv16i8rz |
| 4258 | 4233308U, // CMGEv1i64 |
| 4259 | 4233308U, // CMGEv1i64rz |
| 4260 | 1615017397U, // CMGEv2i32 |
| 4261 | 1615017397U, // CMGEv2i32rz |
| 4262 | 1615008529U, // CMGEv2i64 |
| 4263 | 1615008529U, // CMGEv2i64rz |
| 4264 | 1615010726U, // CMGEv4i16 |
| 4265 | 1615010726U, // CMGEv4i16rz |
| 4266 | 1615019403U, // CMGEv4i32 |
| 4267 | 1615019403U, // CMGEv4i32rz |
| 4268 | 1615012644U, // CMGEv8i16 |
| 4269 | 1615012644U, // CMGEv8i16rz |
| 4270 | 1615005911U, // CMGEv8i8 |
| 4271 | 1615005911U, // CMGEv8i8rz |
| 4272 | 1615005428U, // CMGTv16i8 |
| 4273 | 1615005428U, // CMGTv16i8rz |
| 4274 | 4244650U, // CMGTv1i64 |
| 4275 | 4244650U, // CMGTv1i64rz |
| 4276 | 1615018258U, // CMGTv2i32 |
| 4277 | 1615018258U, // CMGTv2i32rz |
| 4278 | 1615009325U, // CMGTv2i64 |
| 4279 | 1615009325U, // CMGTv2i64rz |
| 4280 | 1615011575U, // CMGTv4i16 |
| 4281 | 1615011575U, // CMGTv4i16rz |
| 4282 | 1615020368U, // CMGTv4i32 |
| 4283 | 1615020368U, // CMGTv4i32rz |
| 4284 | 1615013552U, // CMGTv8i16 |
| 4285 | 1615013552U, // CMGTv8i16rz |
| 4286 | 1615006383U, // CMGTv8i8 |
| 4287 | 1615006383U, // CMGTv8i8rz |
| 4288 | 1615005082U, // CMHIv16i8 |
| 4289 | 4238100U, // CMHIv1i64 |
| 4290 | 1615017563U, // CMHIv2i32 |
| 4291 | 1615008633U, // CMHIv2i64 |
| 4292 | 1615010869U, // CMHIv4i16 |
| 4293 | 1615019581U, // CMHIv4i32 |
| 4294 | 1615012787U, // CMHIv8i16 |
| 4295 | 1615005947U, // CMHIv8i8 |
| 4296 | 1615005400U, // CMHSv16i8 |
| 4297 | 4244333U, // CMHSv1i64 |
| 4298 | 1615018154U, // CMHSv2i32 |
| 4299 | 1615009229U, // CMHSv2i64 |
| 4300 | 1615011471U, // CMHSv4i16 |
| 4301 | 1615020264U, // CMHSv4i32 |
| 4302 | 1615013448U, // CMHSv8i16 |
| 4303 | 1615006358U, // CMHSv8i8 |
| 4304 | 84017493U, // CMLA_ZZZI_H |
| 4305 | 2688713045U, // CMLA_ZZZI_S |
| 4306 | 541131093U, // CMLA_ZZZ_B |
| 4307 | 2151776597U, // CMLA_ZZZ_D |
| 4308 | 84017493U, // CMLA_ZZZ_H |
| 4309 | 2688713045U, // CMLA_ZZZ_S |
| 4310 | 1615005042U, // CMLEv16i8rz |
| 4311 | 4233339U, // CMLEv1i64rz |
| 4312 | 1615017418U, // CMLEv2i32rz |
| 4313 | 1615008550U, // CMLEv2i64rz |
| 4314 | 1615010747U, // CMLEv4i16rz |
| 4315 | 1615019424U, // CMLEv4i32rz |
| 4316 | 1615012665U, // CMLEv8i16rz |
| 4317 | 1615005920U, // CMLEv8i8rz |
| 4318 | 1615005448U, // CMLTv16i8rz |
| 4319 | 4244860U, // CMLTv1i64rz |
| 4320 | 1615018268U, // CMLTv2i32rz |
| 4321 | 1615009335U, // CMLTv2i64rz |
| 4322 | 1615011585U, // CMLTv4i16rz |
| 4323 | 1615020378U, // CMLTv4i32rz |
| 4324 | 1615013562U, // CMLTv8i16rz |
| 4325 | 1615006401U, // CMLTv8i8rz |
| 4326 | 2151756269U, // CMPEQ_PPzZI_B |
| 4327 | 2151789037U, // CMPEQ_PPzZI_D |
| 4328 | 1103245805U, // CMPEQ_PPzZI_H |
| 4329 | 2151854573U, // CMPEQ_PPzZI_S |
| 4330 | 2151756269U, // CMPEQ_PPzZZ_B |
| 4331 | 2151789037U, // CMPEQ_PPzZZ_D |
| 4332 | 1103245805U, // CMPEQ_PPzZZ_H |
| 4333 | 2151854573U, // CMPEQ_PPzZZ_S |
| 4334 | 2151756269U, // CMPEQ_WIDE_PPzZZ_B |
| 4335 | 1103245805U, // CMPEQ_WIDE_PPzZZ_H |
| 4336 | 2151854573U, // CMPEQ_WIDE_PPzZZ_S |
| 4337 | 2151749730U, // CMPGE_PPzZI_B |
| 4338 | 2151782498U, // CMPGE_PPzZI_D |
| 4339 | 1103239266U, // CMPGE_PPzZI_H |
| 4340 | 2151848034U, // CMPGE_PPzZI_S |
| 4341 | 2151749730U, // CMPGE_PPzZZ_B |
| 4342 | 2151782498U, // CMPGE_PPzZZ_D |
| 4343 | 1103239266U, // CMPGE_PPzZZ_H |
| 4344 | 2151848034U, // CMPGE_PPzZZ_S |
| 4345 | 2151749730U, // CMPGE_WIDE_PPzZZ_B |
| 4346 | 1103239266U, // CMPGE_WIDE_PPzZZ_H |
| 4347 | 2151848034U, // CMPGE_WIDE_PPzZZ_S |
| 4348 | 2151761072U, // CMPGT_PPzZI_B |
| 4349 | 2151793840U, // CMPGT_PPzZI_D |
| 4350 | 1103250608U, // CMPGT_PPzZI_H |
| 4351 | 2151859376U, // CMPGT_PPzZI_S |
| 4352 | 2151761072U, // CMPGT_PPzZZ_B |
| 4353 | 2151793840U, // CMPGT_PPzZZ_D |
| 4354 | 1103250608U, // CMPGT_PPzZZ_H |
| 4355 | 2151859376U, // CMPGT_PPzZZ_S |
| 4356 | 2151761072U, // CMPGT_WIDE_PPzZZ_B |
| 4357 | 1103250608U, // CMPGT_WIDE_PPzZZ_H |
| 4358 | 2151859376U, // CMPGT_WIDE_PPzZZ_S |
| 4359 | 2151754522U, // CMPHI_PPzZI_B |
| 4360 | 2151787290U, // CMPHI_PPzZI_D |
| 4361 | 1103244058U, // CMPHI_PPzZI_H |
| 4362 | 2151852826U, // CMPHI_PPzZI_S |
| 4363 | 2151754522U, // CMPHI_PPzZZ_B |
| 4364 | 2151787290U, // CMPHI_PPzZZ_D |
| 4365 | 1103244058U, // CMPHI_PPzZZ_H |
| 4366 | 2151852826U, // CMPHI_PPzZZ_S |
| 4367 | 2151754522U, // CMPHI_WIDE_PPzZZ_B |
| 4368 | 1103244058U, // CMPHI_WIDE_PPzZZ_H |
| 4369 | 2151852826U, // CMPHI_WIDE_PPzZZ_S |
| 4370 | 2151760755U, // CMPHS_PPzZI_B |
| 4371 | 2151793523U, // CMPHS_PPzZI_D |
| 4372 | 1103250291U, // CMPHS_PPzZI_H |
| 4373 | 2151859059U, // CMPHS_PPzZI_S |
| 4374 | 2151760755U, // CMPHS_PPzZZ_B |
| 4375 | 2151793523U, // CMPHS_PPzZZ_D |
| 4376 | 1103250291U, // CMPHS_PPzZZ_H |
| 4377 | 2151859059U, // CMPHS_PPzZZ_S |
| 4378 | 2151760755U, // CMPHS_WIDE_PPzZZ_B |
| 4379 | 1103250291U, // CMPHS_WIDE_PPzZZ_H |
| 4380 | 2151859059U, // CMPHS_WIDE_PPzZZ_S |
| 4381 | 2151749761U, // CMPLE_PPzZI_B |
| 4382 | 2151782529U, // CMPLE_PPzZI_D |
| 4383 | 1103239297U, // CMPLE_PPzZI_H |
| 4384 | 2151848065U, // CMPLE_PPzZI_S |
| 4385 | 2151749761U, // CMPLE_WIDE_PPzZZ_B |
| 4386 | 1103239297U, // CMPLE_WIDE_PPzZZ_H |
| 4387 | 2151848065U, // CMPLE_WIDE_PPzZZ_S |
| 4388 | 2151755773U, // CMPLO_PPzZI_B |
| 4389 | 2151788541U, // CMPLO_PPzZI_D |
| 4390 | 1103245309U, // CMPLO_PPzZI_H |
| 4391 | 2151854077U, // CMPLO_PPzZI_S |
| 4392 | 2151755773U, // CMPLO_WIDE_PPzZZ_B |
| 4393 | 1103245309U, // CMPLO_WIDE_PPzZZ_H |
| 4394 | 2151854077U, // CMPLO_WIDE_PPzZZ_S |
| 4395 | 2151760790U, // CMPLS_PPzZI_B |
| 4396 | 2151793558U, // CMPLS_PPzZI_D |
| 4397 | 1103250326U, // CMPLS_PPzZI_H |
| 4398 | 2151859094U, // CMPLS_PPzZI_S |
| 4399 | 2151760790U, // CMPLS_WIDE_PPzZZ_B |
| 4400 | 1103250326U, // CMPLS_WIDE_PPzZZ_H |
| 4401 | 2151859094U, // CMPLS_WIDE_PPzZZ_S |
| 4402 | 2151761282U, // CMPLT_PPzZI_B |
| 4403 | 2151794050U, // CMPLT_PPzZI_D |
| 4404 | 1103250818U, // CMPLT_PPzZI_H |
| 4405 | 2151859586U, // CMPLT_PPzZI_S |
| 4406 | 2151761282U, // CMPLT_WIDE_PPzZZ_B |
| 4407 | 1103250818U, // CMPLT_WIDE_PPzZZ_H |
| 4408 | 2151859586U, // CMPLT_WIDE_PPzZZ_S |
| 4409 | 2151749784U, // CMPNE_PPzZI_B |
| 4410 | 2151782552U, // CMPNE_PPzZI_D |
| 4411 | 1103239320U, // CMPNE_PPzZI_H |
| 4412 | 2151848088U, // CMPNE_PPzZI_S |
| 4413 | 2151749784U, // CMPNE_PPzZZ_B |
| 4414 | 2151782552U, // CMPNE_PPzZZ_D |
| 4415 | 1103239320U, // CMPNE_PPzZZ_H |
| 4416 | 2151848088U, // CMPNE_PPzZZ_S |
| 4417 | 2151749784U, // CMPNE_WIDE_PPzZZ_B |
| 4418 | 1103239320U, // CMPNE_WIDE_PPzZZ_H |
| 4419 | 2151848088U, // CMPNE_WIDE_PPzZZ_S |
| 4420 | 1615005476U, // CMTSTv16i8 |
| 4421 | 4245195U, // CMTSTv1i64 |
| 4422 | 1615018287U, // CMTSTv2i32 |
| 4423 | 1615009354U, // CMTSTv2i64 |
| 4424 | 1615011604U, // CMTSTv4i16 |
| 4425 | 1615020397U, // CMTSTv4i32 |
| 4426 | 1615013581U, // CMTSTv8i16 |
| 4427 | 1615006426U, // CMTSTv8i8 |
| 4428 | 541148802U, // CNOT_ZPmZ_B |
| 4429 | 541181570U, // CNOT_ZPmZ_D |
| 4430 | 1082279554U, // CNOT_ZPmZ_H |
| 4431 | 541247106U, // CNOT_ZPmZ_S |
| 4432 | 1614843762U, // CNTB_XPiI |
| 4433 | 1614846001U, // CNTD_XPiI |
| 4434 | 1614850751U, // CNTH_XPiI |
| 4435 | 2151723322U, // CNTP_XCI_B |
| 4436 | 2688594234U, // CNTP_XCI_D |
| 4437 | 3225465146U, // CNTP_XCI_H |
| 4438 | 3762336058U, // CNTP_XCI_S |
| 4439 | 2151723322U, // CNTP_XPP_B |
| 4440 | 2151723322U, // CNTP_XPP_D |
| 4441 | 2151723322U, // CNTP_XPP_H |
| 4442 | 2151723322U, // CNTP_XPP_S |
| 4443 | 1614858589U, // CNTW_XPiI |
| 4444 | 4244940U, // CNTWr |
| 4445 | 4244940U, // CNTXr |
| 4446 | 541148620U, // CNT_ZPmZ_B |
| 4447 | 541181388U, // CNT_ZPmZ_D |
| 4448 | 1082279372U, // CNT_ZPmZ_H |
| 4449 | 541246924U, // CNT_ZPmZ_S |
| 4450 | 1615005458U, // CNTv16i8 |
| 4451 | 1615006410U, // CNTv8i8 |
| 4452 | 2151793773U, // COMPACT_ZPZ_D |
| 4453 | 2151859309U, // COMPACT_ZPZ_S |
| 4454 | 871542U, // CPYE |
| 4455 | 871605U, // CPYEN |
| 4456 | 871691U, // CPYERN |
| 4457 | 872579U, // CPYERT |
| 4458 | 872064U, // CPYERTN |
| 4459 | 871813U, // CPYERTRN |
| 4460 | 872311U, // CPYERTWN |
| 4461 | 872493U, // CPYET |
| 4462 | 871968U, // CPYETN |
| 4463 | 871749U, // CPYETRN |
| 4464 | 872247U, // CPYETWN |
| 4465 | 872189U, // CPYEWN |
| 4466 | 872636U, // CPYEWT |
| 4467 | 872127U, // CPYEWTN |
| 4468 | 871882U, // CPYEWTRN |
| 4469 | 872380U, // CPYEWTWN |
| 4470 | 871519U, // CPYFE |
| 4471 | 871579U, // CPYFEN |
| 4472 | 871681U, // CPYFERN |
| 4473 | 872569U, // CPYFERT |
| 4474 | 872053U, // CPYFERTN |
| 4475 | 871801U, // CPYFERTRN |
| 4476 | 872299U, // CPYFERTWN |
| 4477 | 872467U, // CPYFET |
| 4478 | 871939U, // CPYFETN |
| 4479 | 871738U, // CPYFETRN |
| 4480 | 872236U, // CPYFETWN |
| 4481 | 872179U, // CPYFEWN |
| 4482 | 872626U, // CPYFEWT |
| 4483 | 872116U, // CPYFEWTN |
| 4484 | 871870U, // CPYFEWTRN |
| 4485 | 872368U, // CPYFEWTWN |
| 4486 | 871549U, // CPYFM |
| 4487 | 871613U, // CPYFMN |
| 4488 | 871700U, // CPYFMRN |
| 4489 | 872588U, // CPYFMRT |
| 4490 | 872074U, // CPYFMRTN |
| 4491 | 871824U, // CPYFMRTRN |
| 4492 | 872322U, // CPYFMRTWN |
| 4493 | 872501U, // CPYFMT |
| 4494 | 871977U, // CPYFMTN |
| 4495 | 871759U, // CPYFMTRN |
| 4496 | 872257U, // CPYFMTWN |
| 4497 | 872198U, // CPYFMWN |
| 4498 | 872645U, // CPYFMWT |
| 4499 | 872137U, // CPYFMWTN |
| 4500 | 871893U, // CPYFMWTRN |
| 4501 | 872391U, // CPYFMWTWN |
| 4502 | 872437U, // CPYFP |
| 4503 | 871647U, // CPYFPN |
| 4504 | 871719U, // CPYFPRN |
| 4505 | 872607U, // CPYFPRT |
| 4506 | 872095U, // CPYFPRTN |
| 4507 | 871847U, // CPYFPRTRN |
| 4508 | 872345U, // CPYFPRTWN |
| 4509 | 872535U, // CPYFPT |
| 4510 | 872015U, // CPYFPTN |
| 4511 | 871780U, // CPYFPTRN |
| 4512 | 872278U, // CPYFPTWN |
| 4513 | 872217U, // CPYFPWN |
| 4514 | 872664U, // CPYFPWT |
| 4515 | 872158U, // CPYFPWTN |
| 4516 | 871916U, // CPYFPWTRN |
| 4517 | 872414U, // CPYFPWTWN |
| 4518 | 871572U, // CPYM |
| 4519 | 871639U, // CPYMN |
| 4520 | 871710U, // CPYMRN |
| 4521 | 872598U, // CPYMRT |
| 4522 | 872085U, // CPYMRTN |
| 4523 | 871836U, // CPYMRTRN |
| 4524 | 872334U, // CPYMRTWN |
| 4525 | 872527U, // CPYMT |
| 4526 | 872006U, // CPYMTN |
| 4527 | 871770U, // CPYMTRN |
| 4528 | 872268U, // CPYMTWN |
| 4529 | 872208U, // CPYMWN |
| 4530 | 872655U, // CPYMWT |
| 4531 | 872148U, // CPYMWTN |
| 4532 | 871905U, // CPYMWTRN |
| 4533 | 872403U, // CPYMWTWN |
| 4534 | 872460U, // CPYP |
| 4535 | 871673U, // CPYPN |
| 4536 | 871729U, // CPYPRN |
| 4537 | 872617U, // CPYPRT |
| 4538 | 872106U, // CPYPRTN |
| 4539 | 871859U, // CPYPRTRN |
| 4540 | 872357U, // CPYPRTWN |
| 4541 | 872561U, // CPYPT |
| 4542 | 872044U, // CPYPTN |
| 4543 | 871791U, // CPYPTRN |
| 4544 | 872289U, // CPYPTWN |
| 4545 | 872227U, // CPYPWN |
| 4546 | 872674U, // CPYPWT |
| 4547 | 872169U, // CPYPWTN |
| 4548 | 871928U, // CPYPWTRN |
| 4549 | 872426U, // CPYPWTWN |
| 4550 | 541149698U, // CPY_ZPmI_B |
| 4551 | 541182466U, // CPY_ZPmI_D |
| 4552 | 8538626U, // CPY_ZPmI_H |
| 4553 | 541248002U, // CPY_ZPmI_S |
| 4554 | 541149698U, // CPY_ZPmR_B |
| 4555 | 541182466U, // CPY_ZPmR_D |
| 4556 | 545409538U, // CPY_ZPmR_H |
| 4557 | 541248002U, // CPY_ZPmR_S |
| 4558 | 541149698U, // CPY_ZPmV_B |
| 4559 | 541182466U, // CPY_ZPmV_D |
| 4560 | 545409538U, // CPY_ZPmV_H |
| 4561 | 541248002U, // CPY_ZPmV_S |
| 4562 | 2151762434U, // CPY_ZPzI_B |
| 4563 | 2151795202U, // CPY_ZPzI_D |
| 4564 | 1103251970U, // CPY_ZPzI_H |
| 4565 | 2151860738U, // CPY_ZPzI_S |
| 4566 | 4227893U, // CRC32Brr |
| 4567 | 4230096U, // CRC32CBrr |
| 4568 | 4237442U, // CRC32CHrr |
| 4569 | 4245692U, // CRC32CWrr |
| 4570 | 4245946U, // CRC32CXrr |
| 4571 | 4233780U, // CRC32Hrr |
| 4572 | 4245648U, // CRC32Wrr |
| 4573 | 4245877U, // CRC32Xrr |
| 4574 | 4238525U, // CSELWr |
| 4575 | 4238525U, // CSELXr |
| 4576 | 4231227U, // CSINCWr |
| 4577 | 4231227U, // CSINCXr |
| 4578 | 4245468U, // CSINVWr |
| 4579 | 4245468U, // CSINVXr |
| 4580 | 4233507U, // CSNEGWr |
| 4581 | 4233507U, // CSNEGXr |
| 4582 | 4239844U, // CTERMEQ_WW |
| 4583 | 4239844U, // CTERMEQ_XX |
| 4584 | 4233359U, // CTERMNE_WW |
| 4585 | 4233359U, // CTERMNE_XX |
| 4586 | 4246107U, // CTZWr |
| 4587 | 4246107U, // CTZXr |
| 4588 | 753724U, // DCPS1 |
| 4589 | 753842U, // DCPS2 |
| 4590 | 753873U, // DCPS3 |
| 4591 | 1077971931U, // DECB_XPiI |
| 4592 | 1077974922U, // DECD_XPiI |
| 4593 | 1078040458U, // DECD_ZPiI |
| 4594 | 1077979277U, // DECH_XPiI |
| 4595 | 100804749U, // DECH_ZPiI |
| 4596 | 4239385U, // DECP_XP_B |
| 4597 | 541110297U, // DECP_XP_D |
| 4598 | 3762335769U, // DECP_XP_H |
| 4599 | 541110297U, // DECP_XP_S |
| 4600 | 2151788569U, // DECP_ZP_D |
| 4601 | 3305254937U, // DECP_ZP_H |
| 4602 | 2688725017U, // DECP_ZP_S |
| 4603 | 1077987527U, // DECW_XPiI |
| 4604 | 1078118599U, // DECW_ZPiI |
| 4605 | 888244U, // DMB |
| 4606 | 20898U, // DRPS |
| 4607 | 888594U, // DSB |
| 4608 | 921362U, // DSBnXS |
| 4609 | 1614917376U, // DUPM_ZI |
| 4610 | 4272634U, // DUPQ_ZZI_B |
| 4611 | 541176314U, // DUPQ_ZZI_D |
| 4612 | 2218930682U, // DUPQ_ZZI_H |
| 4613 | 541241850U, // DUPQ_ZZI_S |
| 4614 | 2688627022U, // DUP_ZI_B |
| 4615 | 3225530702U, // DUP_ZI_D |
| 4616 | 105001294U, // DUP_ZI_H |
| 4617 | 3762467150U, // DUP_ZI_S |
| 4618 | 4272462U, // DUP_ZR_B |
| 4619 | 4305230U, // DUP_ZR_D |
| 4620 | 3330421070U, // DUP_ZR_H |
| 4621 | 4370766U, // DUP_ZR_S |
| 4622 | 4272462U, // DUP_ZZI_B |
| 4623 | 541176142U, // DUP_ZZI_D |
| 4624 | 2218930510U, // DUP_ZZI_H |
| 4625 | 2261692750U, // DUP_ZZI_Q |
| 4626 | 541241678U, // DUP_ZZI_S |
| 4627 | 1614858212U, // DUPi16 |
| 4628 | 1614858212U, // DUPi32 |
| 4629 | 1614858212U, // DUPi64 |
| 4630 | 1614858212U, // DUPi8 |
| 4631 | 4392552U, // DUPv16i8gpr |
| 4632 | 1615005288U, // DUPv16i8lane |
| 4633 | 4405294U, // DUPv2i32gpr |
| 4634 | 1615018030U, // DUPv2i32lane |
| 4635 | 4396389U, // DUPv2i64gpr |
| 4636 | 1615009125U, // DUPv2i64lane |
| 4637 | 4398611U, // DUPv4i16gpr |
| 4638 | 1615011347U, // DUPv4i16lane |
| 4639 | 4407404U, // DUPv4i32gpr |
| 4640 | 1615020140U, // DUPv4i32lane |
| 4641 | 4400588U, // DUPv8i16gpr |
| 4642 | 1615013324U, // DUPv8i16lane |
| 4643 | 4393521U, // DUPv8i8gpr |
| 4644 | 1615006257U, // DUPv8i8lane |
| 4645 | 4239181U, // EONWrs |
| 4646 | 4239181U, // EONXrs |
| 4647 | 1615004744U, // EOR3 |
| 4648 | 541163723U, // EOR3_ZZZZ |
| 4649 | 541148262U, // EORBT_ZZZ_B |
| 4650 | 2151793766U, // EORBT_ZZZ_D |
| 4651 | 84034662U, // EORBT_ZZZ_H |
| 4652 | 2688730214U, // EORBT_ZZZ_S |
| 4653 | 2181253162U, // EORQV_VPZ_B |
| 4654 | 2185447466U, // EORQV_VPZ_D |
| 4655 | 2189641770U, // EORQV_VPZ_H |
| 4656 | 2193836074U, // EORQV_VPZ_S |
| 4657 | 2151760893U, // EORS_PPzPP |
| 4658 | 541134712U, // EORTB_ZZZ_B |
| 4659 | 2151780216U, // EORTB_ZZZ_D |
| 4660 | 84021112U, // EORTB_ZZZ_H |
| 4661 | 2688716664U, // EORTB_ZZZ_S |
| 4662 | 510025U, // EORV_VPZ_B |
| 4663 | 3301460041U, // EORV_VPZ_D |
| 4664 | 3305687113U, // EORV_VPZ_H |
| 4665 | 3246999625U, // EORV_VPZ_S |
| 4666 | 4240179U, // EORWri |
| 4667 | 4240179U, // EORWrs |
| 4668 | 4240179U, // EORXri |
| 4669 | 4240179U, // EORXrs |
| 4670 | 2151756595U, // EOR_PPzPP |
| 4671 | 541176627U, // EOR_ZI |
| 4672 | 2151756595U, // EOR_ZPmZ_B |
| 4673 | 2151789363U, // EOR_ZPmZ_D |
| 4674 | 2713858867U, // EOR_ZPmZ_H |
| 4675 | 2151854899U, // EOR_ZPmZ_S |
| 4676 | 541176627U, // EOR_ZZZ |
| 4677 | 1615005371U, // EORv16i8 |
| 4678 | 1615006332U, // EORv8i8 |
| 4679 | 20912U, // ERET |
| 4680 | 20715U, // ERETAA |
| 4681 | 20742U, // ERETAB |
| 4682 | 4272640U, // EXTQ_ZZI |
| 4683 | 541131450U, // EXTRACT_ZPMXI_H_B |
| 4684 | 541164218U, // EXTRACT_ZPMXI_H_D |
| 4685 | 8520378U, // EXTRACT_ZPMXI_H_H |
| 4686 | 9339578U, // EXTRACT_ZPMXI_H_Q |
| 4687 | 541229754U, // EXTRACT_ZPMXI_H_S |
| 4688 | 541131450U, // EXTRACT_ZPMXI_V_B |
| 4689 | 541164218U, // EXTRACT_ZPMXI_V_D |
| 4690 | 545391290U, // EXTRACT_ZPMXI_V_H |
| 4691 | 546210490U, // EXTRACT_ZPMXI_V_Q |
| 4692 | 541229754U, // EXTRACT_ZPMXI_V_S |
| 4693 | 4240268U, // EXTRWrri |
| 4694 | 4240268U, // EXTRXrri |
| 4695 | 4278056U, // EXT_ZZI |
| 4696 | 1078019880U, // EXT_ZZI_B |
| 4697 | 1615005487U, // EXTv16i8 |
| 4698 | 1615006436U, // EXTv8i8 |
| 4699 | 1615012127U, // F1CVTL2v8f16 |
| 4700 | 3309454765U, // F1CVTLT_ZZ_BtoH |
| 4701 | 3309678163U, // F1CVTL_2ZZ_BtoH_NAME |
| 4702 | 1615013092U, // F1CVTLv8f16 |
| 4703 | 3309684445U, // F1CVT_2ZZ_BtoH_NAME |
| 4704 | 3309455069U, // F1CVT_ZZ_BtoH |
| 4705 | 1615012140U, // F2CVTL2v8f16 |
| 4706 | 3309454775U, // F2CVTLT_ZZ_BtoH |
| 4707 | 3309678172U, // F2CVTL_2ZZ_BtoH_NAME |
| 4708 | 1615013104U, // F2CVTLv8f16 |
| 4709 | 3309684453U, // F2CVT_2ZZ_BtoH_NAME |
| 4710 | 3309455077U, // F2CVT_ZZ_BtoH |
| 4711 | 4233071U, // FABD16 |
| 4712 | 4233071U, // FABD32 |
| 4713 | 4233071U, // FABD64 |
| 4714 | 2151782255U, // FABD_ZPmZ_D |
| 4715 | 2713851759U, // FABD_ZPmZ_H |
| 4716 | 2151847791U, // FABD_ZPmZ_S |
| 4717 | 1615017276U, // FABDv2f32 |
| 4718 | 1615008468U, // FABDv2f64 |
| 4719 | 1615010605U, // FABDv4f16 |
| 4720 | 1615019273U, // FABDv4f32 |
| 4721 | 1615012523U, // FABDv8f16 |
| 4722 | 4244251U, // FABSDr |
| 4723 | 4244251U, // FABSHr |
| 4724 | 4244251U, // FABSSr |
| 4725 | 541180699U, // FABS_ZPmZ_D |
| 4726 | 1082278683U, // FABS_ZPmZ_H |
| 4727 | 541246235U, // FABS_ZPmZ_S |
| 4728 | 1615018135U, // FABSv2f32 |
| 4729 | 1615009210U, // FABSv2f64 |
| 4730 | 1615011452U, // FABSv4f16 |
| 4731 | 1615020245U, // FABSv4f32 |
| 4732 | 1615013429U, // FABSv8f16 |
| 4733 | 4233291U, // FACGE16 |
| 4734 | 4233291U, // FACGE32 |
| 4735 | 4233291U, // FACGE64 |
| 4736 | 2151782475U, // FACGE_PPzZZ_D |
| 4737 | 1103239243U, // FACGE_PPzZZ_H |
| 4738 | 2151848011U, // FACGE_PPzZZ_S |
| 4739 | 1615017386U, // FACGEv2f32 |
| 4740 | 1615008518U, // FACGEv2f64 |
| 4741 | 1615010715U, // FACGEv4f16 |
| 4742 | 1615019392U, // FACGEv4f32 |
| 4743 | 1615012633U, // FACGEv8f16 |
| 4744 | 4244633U, // FACGT16 |
| 4745 | 4244633U, // FACGT32 |
| 4746 | 4244633U, // FACGT64 |
| 4747 | 2151793817U, // FACGT_PPzZZ_D |
| 4748 | 1103250585U, // FACGT_PPzZZ_H |
| 4749 | 2151859353U, // FACGT_PPzZZ_S |
| 4750 | 1615018247U, // FACGTv2f32 |
| 4751 | 1615009314U, // FACGTv2f64 |
| 4752 | 1615011564U, // FACGTv4f16 |
| 4753 | 1615020357U, // FACGTv4f32 |
| 4754 | 1615013541U, // FACGTv8f16 |
| 4755 | 117965092U, // FADDA_VPZ_D |
| 4756 | 122192164U, // FADDA_VPZ_H |
| 4757 | 126419236U, // FADDA_VPZ_S |
| 4758 | 4233151U, // FADDDrr |
| 4759 | 4233151U, // FADDHrr |
| 4760 | 2151788599U, // FADDP_ZPmZZ_D |
| 4761 | 2713858103U, // FADDP_ZPmZZ_H |
| 4762 | 2151854135U, // FADDP_ZPmZZ_S |
| 4763 | 1615017911U, // FADDPv2f32 |
| 4764 | 1615009026U, // FADDPv2f64 |
| 4765 | 1614846462U, // FADDPv2i16p |
| 4766 | 1614854071U, // FADDPv2i32p |
| 4767 | 1614845186U, // FADDPv2i64p |
| 4768 | 1615011228U, // FADDPv4f16 |
| 4769 | 1615020021U, // FADDPv4f32 |
| 4770 | 1615013205U, // FADDPv8f16 |
| 4771 | 2185447407U, // FADDQV_D |
| 4772 | 2189641711U, // FADDQV_H |
| 4773 | 2193836015U, // FADDQV_S |
| 4774 | 4233151U, // FADDSrr |
| 4775 | 3301459843U, // FADDV_VPZ_D |
| 4776 | 3305686915U, // FADDV_VPZ_H |
| 4777 | 3246999427U, // FADDV_VPZ_S |
| 4778 | 3288766399U, // FADD_VG2_M2Z_D |
| 4779 | 3289061311U, // FADD_VG2_M2Z_H |
| 4780 | 3288799167U, // FADD_VG2_M2Z_S |
| 4781 | 3825637311U, // FADD_VG4_M4Z_D |
| 4782 | 3825932223U, // FADD_VG4_M4Z_H |
| 4783 | 3825670079U, // FADD_VG4_M4Z_S |
| 4784 | 2151782335U, // FADD_ZPmI_D |
| 4785 | 2713851839U, // FADD_ZPmI_H |
| 4786 | 2151847871U, // FADD_ZPmI_S |
| 4787 | 2151782335U, // FADD_ZPmZ_D |
| 4788 | 2713851839U, // FADD_ZPmZ_H |
| 4789 | 2151847871U, // FADD_ZPmZ_S |
| 4790 | 541169599U, // FADD_ZZZ_D |
| 4791 | 71440319U, // FADD_ZZZ_H |
| 4792 | 541235135U, // FADD_ZZZ_S |
| 4793 | 1615017313U, // FADDv2f32 |
| 4794 | 1615008487U, // FADDv2f64 |
| 4795 | 1615010642U, // FADDv4f16 |
| 4796 | 1615019310U, // FADDv4f32 |
| 4797 | 1615012560U, // FADDv8f16 |
| 4798 | 54872471U, // FAMAX_2Z2Z_D |
| 4799 | 59099543U, // FAMAX_2Z2Z_H |
| 4800 | 63326615U, // FAMAX_2Z2Z_S |
| 4801 | 54872471U, // FAMAX_4Z4Z_D |
| 4802 | 59099543U, // FAMAX_4Z4Z_H |
| 4803 | 63326615U, // FAMAX_4Z4Z_S |
| 4804 | 2151795095U, // FAMAX_ZPmZ_D |
| 4805 | 2713864599U, // FAMAX_ZPmZ_H |
| 4806 | 2151860631U, // FAMAX_ZPmZ_S |
| 4807 | 1615018407U, // FAMAXv2f32 |
| 4808 | 1615009514U, // FAMAXv2f64 |
| 4809 | 1615011813U, // FAMAXv4f16 |
| 4810 | 1615020672U, // FAMAXv4f32 |
| 4811 | 1615013830U, // FAMAXv8f16 |
| 4812 | 54865699U, // FAMIN_2Z2Z_D |
| 4813 | 59092771U, // FAMIN_2Z2Z_H |
| 4814 | 63319843U, // FAMIN_2Z2Z_S |
| 4815 | 54865699U, // FAMIN_4Z4Z_D |
| 4816 | 59092771U, // FAMIN_4Z4Z_H |
| 4817 | 63319843U, // FAMIN_4Z4Z_S |
| 4818 | 2151788323U, // FAMIN_ZPmZ_D |
| 4819 | 2713857827U, // FAMIN_ZPmZ_H |
| 4820 | 2151853859U, // FAMIN_ZPmZ_S |
| 4821 | 1615017761U, // FAMINv2f32 |
| 4822 | 1615008996U, // FAMINv2f64 |
| 4823 | 1615011067U, // FAMINv4f16 |
| 4824 | 1615019963U, // FAMINv4f32 |
| 4825 | 1615013157U, // FAMINv8f16 |
| 4826 | 2151782312U, // FCADD_ZPmZ_D |
| 4827 | 2713851816U, // FCADD_ZPmZ_H |
| 4828 | 2151847848U, // FCADD_ZPmZ_S |
| 4829 | 1615017303U, // FCADDv2f32 |
| 4830 | 1615008477U, // FCADDv2f64 |
| 4831 | 1615010632U, // FCADDv4f16 |
| 4832 | 1615019300U, // FCADDv4f32 |
| 4833 | 1615012550U, // FCADDv8f16 |
| 4834 | 4239492U, // FCCMPDrr |
| 4835 | 4233391U, // FCCMPEDrr |
| 4836 | 4233391U, // FCCMPEHrr |
| 4837 | 4233391U, // FCCMPESrr |
| 4838 | 4239492U, // FCCMPHrr |
| 4839 | 4239492U, // FCCMPSrr |
| 4840 | 80031852U, // FCLAMP_VG2_2Z2Z_D |
| 4841 | 84258924U, // FCLAMP_VG2_2Z2Z_H |
| 4842 | 25571436U, // FCLAMP_VG2_2Z2Z_S |
| 4843 | 80031852U, // FCLAMP_VG4_4Z4Z_D |
| 4844 | 84258924U, // FCLAMP_VG4_4Z4Z_H |
| 4845 | 25571436U, // FCLAMP_VG4_4Z4Z_S |
| 4846 | 2151788652U, // FCLAMP_ZZZ_D |
| 4847 | 84029548U, // FCLAMP_ZZZ_H |
| 4848 | 2688725100U, // FCLAMP_ZZZ_S |
| 4849 | 4239837U, // FCMEQ16 |
| 4850 | 4239837U, // FCMEQ32 |
| 4851 | 4239837U, // FCMEQ64 |
| 4852 | 2151789021U, // FCMEQ_PPzZ0_D |
| 4853 | 1103245789U, // FCMEQ_PPzZ0_H |
| 4854 | 2151854557U, // FCMEQ_PPzZ0_S |
| 4855 | 2151789021U, // FCMEQ_PPzZZ_D |
| 4856 | 1103245789U, // FCMEQ_PPzZZ_H |
| 4857 | 2151854557U, // FCMEQ_PPzZZ_S |
| 4858 | 4239837U, // FCMEQv1i16rz |
| 4859 | 4239837U, // FCMEQv1i32rz |
| 4860 | 4239837U, // FCMEQv1i64rz |
| 4861 | 1615018068U, // FCMEQv2f32 |
| 4862 | 1615009143U, // FCMEQv2f64 |
| 4863 | 1615018068U, // FCMEQv2i32rz |
| 4864 | 1615009143U, // FCMEQv2i64rz |
| 4865 | 1615011385U, // FCMEQv4f16 |
| 4866 | 1615020178U, // FCMEQv4f32 |
| 4867 | 1615011385U, // FCMEQv4i16rz |
| 4868 | 1615020178U, // FCMEQv4i32rz |
| 4869 | 1615013362U, // FCMEQv8f16 |
| 4870 | 1615013362U, // FCMEQv8i16rz |
| 4871 | 4233307U, // FCMGE16 |
| 4872 | 4233307U, // FCMGE32 |
| 4873 | 4233307U, // FCMGE64 |
| 4874 | 2151782491U, // FCMGE_PPzZ0_D |
| 4875 | 1103239259U, // FCMGE_PPzZ0_H |
| 4876 | 2151848027U, // FCMGE_PPzZ0_S |
| 4877 | 2151782491U, // FCMGE_PPzZZ_D |
| 4878 | 1103239259U, // FCMGE_PPzZZ_H |
| 4879 | 2151848027U, // FCMGE_PPzZZ_S |
| 4880 | 4233307U, // FCMGEv1i16rz |
| 4881 | 4233307U, // FCMGEv1i32rz |
| 4882 | 4233307U, // FCMGEv1i64rz |
| 4883 | 1615017396U, // FCMGEv2f32 |
| 4884 | 1615008528U, // FCMGEv2f64 |
| 4885 | 1615017396U, // FCMGEv2i32rz |
| 4886 | 1615008528U, // FCMGEv2i64rz |
| 4887 | 1615010725U, // FCMGEv4f16 |
| 4888 | 1615019402U, // FCMGEv4f32 |
| 4889 | 1615010725U, // FCMGEv4i16rz |
| 4890 | 1615019402U, // FCMGEv4i32rz |
| 4891 | 1615012643U, // FCMGEv8f16 |
| 4892 | 1615012643U, // FCMGEv8i16rz |
| 4893 | 4244649U, // FCMGT16 |
| 4894 | 4244649U, // FCMGT32 |
| 4895 | 4244649U, // FCMGT64 |
| 4896 | 2151793833U, // FCMGT_PPzZ0_D |
| 4897 | 1103250601U, // FCMGT_PPzZ0_H |
| 4898 | 2151859369U, // FCMGT_PPzZ0_S |
| 4899 | 2151793833U, // FCMGT_PPzZZ_D |
| 4900 | 1103250601U, // FCMGT_PPzZZ_H |
| 4901 | 2151859369U, // FCMGT_PPzZZ_S |
| 4902 | 4244649U, // FCMGTv1i16rz |
| 4903 | 4244649U, // FCMGTv1i32rz |
| 4904 | 4244649U, // FCMGTv1i64rz |
| 4905 | 1615018257U, // FCMGTv2f32 |
| 4906 | 1615009324U, // FCMGTv2f64 |
| 4907 | 1615018257U, // FCMGTv2i32rz |
| 4908 | 1615009324U, // FCMGTv2i64rz |
| 4909 | 1615011574U, // FCMGTv4f16 |
| 4910 | 1615020367U, // FCMGTv4f32 |
| 4911 | 1615011574U, // FCMGTv4i16rz |
| 4912 | 1615020367U, // FCMGTv4i32rz |
| 4913 | 1615013551U, // FCMGTv8f16 |
| 4914 | 1615013551U, // FCMGTv8i16rz |
| 4915 | 2151776596U, // FCMLA_ZPmZZ_D |
| 4916 | 2713846100U, // FCMLA_ZPmZZ_H |
| 4917 | 2151842132U, // FCMLA_ZPmZZ_S |
| 4918 | 84017492U, // FCMLA_ZZZI_H |
| 4919 | 2688713044U, // FCMLA_ZZZI_S |
| 4920 | 1615082687U, // FCMLAv2f32 |
| 4921 | 1615073907U, // FCMLAv2f64 |
| 4922 | 1615076016U, // FCMLAv4f16 |
| 4923 | 1615076016U, // FCMLAv4f16_indexed |
| 4924 | 1615084650U, // FCMLAv4f32 |
| 4925 | 1615084650U, // FCMLAv4f32_indexed |
| 4926 | 1615077934U, // FCMLAv8f16 |
| 4927 | 1615077934U, // FCMLAv8f16_indexed |
| 4928 | 2151782522U, // FCMLE_PPzZ0_D |
| 4929 | 1103239290U, // FCMLE_PPzZ0_H |
| 4930 | 2151848058U, // FCMLE_PPzZ0_S |
| 4931 | 4233338U, // FCMLEv1i16rz |
| 4932 | 4233338U, // FCMLEv1i32rz |
| 4933 | 4233338U, // FCMLEv1i64rz |
| 4934 | 1615017417U, // FCMLEv2i32rz |
| 4935 | 1615008549U, // FCMLEv2i64rz |
| 4936 | 1615010746U, // FCMLEv4i16rz |
| 4937 | 1615019423U, // FCMLEv4i32rz |
| 4938 | 1615012664U, // FCMLEv8i16rz |
| 4939 | 2151794043U, // FCMLT_PPzZ0_D |
| 4940 | 1103250811U, // FCMLT_PPzZ0_H |
| 4941 | 2151859579U, // FCMLT_PPzZ0_S |
| 4942 | 4244859U, // FCMLTv1i16rz |
| 4943 | 4244859U, // FCMLTv1i32rz |
| 4944 | 4244859U, // FCMLTv1i64rz |
| 4945 | 1615018267U, // FCMLTv2i32rz |
| 4946 | 1615009334U, // FCMLTv2i64rz |
| 4947 | 1615011584U, // FCMLTv4i16rz |
| 4948 | 1615020377U, // FCMLTv4i32rz |
| 4949 | 1615013561U, // FCMLTv8i16rz |
| 4950 | 2151782536U, // FCMNE_PPzZ0_D |
| 4951 | 1103239304U, // FCMNE_PPzZ0_H |
| 4952 | 2151848072U, // FCMNE_PPzZ0_S |
| 4953 | 2151782536U, // FCMNE_PPzZZ_D |
| 4954 | 1103239304U, // FCMNE_PPzZZ_H |
| 4955 | 2151848072U, // FCMNE_PPzZZ_S |
| 4956 | 130068619U, // FCMPDri |
| 4957 | 4239499U, // FCMPDrr |
| 4958 | 130062519U, // FCMPEDri |
| 4959 | 4233399U, // FCMPEDrr |
| 4960 | 130062519U, // FCMPEHri |
| 4961 | 4233399U, // FCMPEHrr |
| 4962 | 130062519U, // FCMPESri |
| 4963 | 4233399U, // FCMPESrr |
| 4964 | 130068619U, // FCMPHri |
| 4965 | 4239499U, // FCMPHrr |
| 4966 | 130068619U, // FCMPSri |
| 4967 | 4239499U, // FCMPSrr |
| 4968 | 2151788554U, // FCMUO_PPzZZ_D |
| 4969 | 1103245322U, // FCMUO_PPzZZ_H |
| 4970 | 2151854090U, // FCMUO_PPzZZ_S |
| 4971 | 541182465U, // FCPY_ZPmI_D |
| 4972 | 1619151361U, // FCPY_ZPmI_H |
| 4973 | 541248001U, // FCPY_ZPmI_S |
| 4974 | 4238524U, // FCSELDrrr |
| 4975 | 4238524U, // FCSELHrrr |
| 4976 | 4238524U, // FCSELSrrr |
| 4977 | 4244243U, // FCVTASUWDr |
| 4978 | 4244243U, // FCVTASUWHr |
| 4979 | 4244243U, // FCVTASUWSr |
| 4980 | 4244243U, // FCVTASUXDr |
| 4981 | 4244243U, // FCVTASUXHr |
| 4982 | 4244243U, // FCVTASUXSr |
| 4983 | 4244243U, // FCVTASv1f16 |
| 4984 | 4244243U, // FCVTASv1i32 |
| 4985 | 4244243U, // FCVTASv1i64 |
| 4986 | 1615018124U, // FCVTASv2f32 |
| 4987 | 1615009199U, // FCVTASv2f64 |
| 4988 | 1615011441U, // FCVTASv4f16 |
| 4989 | 1615020234U, // FCVTASv4f32 |
| 4990 | 1615013418U, // FCVTASv8f16 |
| 4991 | 4245306U, // FCVTAUUWDr |
| 4992 | 4245306U, // FCVTAUUWHr |
| 4993 | 4245306U, // FCVTAUUWSr |
| 4994 | 4245306U, // FCVTAUUXDr |
| 4995 | 4245306U, // FCVTAUUXHr |
| 4996 | 4245306U, // FCVTAUUXSr |
| 4997 | 4245306U, // FCVTAUv1f16 |
| 4998 | 4245306U, // FCVTAUv1i32 |
| 4999 | 4245306U, // FCVTAUv1i64 |
| 5000 | 1615018297U, // FCVTAUv2f32 |
| 5001 | 1615009364U, // FCVTAUv2f64 |
| 5002 | 1615011614U, // FCVTAUv4f16 |
| 5003 | 1615020407U, // FCVTAUv4f32 |
| 5004 | 1615013591U, // FCVTAUv8f16 |
| 5005 | 4245229U, // FCVTDHr |
| 5006 | 4245229U, // FCVTDSr |
| 5007 | 4245229U, // FCVTHDr |
| 5008 | 4245229U, // FCVTHSr |
| 5009 | 541246912U, // FCVTLT_ZPmZ_HtoS |
| 5010 | 541181376U, // FCVTLT_ZPmZ_StoD |
| 5011 | 3292933732U, // FCVTL_2ZZ_H_S |
| 5012 | 1648569956U, // FCVTLv2i32 |
| 5013 | 1656958564U, // FCVTLv4i16 |
| 5014 | 1648558201U, // FCVTLv4i32 |
| 5015 | 1656946809U, // FCVTLv8i16 |
| 5016 | 4244381U, // FCVTMSUWDr |
| 5017 | 4244381U, // FCVTMSUWHr |
| 5018 | 4244381U, // FCVTMSUWSr |
| 5019 | 4244381U, // FCVTMSUXDr |
| 5020 | 4244381U, // FCVTMSUXHr |
| 5021 | 4244381U, // FCVTMSUXSr |
| 5022 | 4244381U, // FCVTMSv1f16 |
| 5023 | 4244381U, // FCVTMSv1i32 |
| 5024 | 4244381U, // FCVTMSv1i64 |
| 5025 | 1615018180U, // FCVTMSv2f32 |
| 5026 | 1615009247U, // FCVTMSv2f64 |
| 5027 | 1615011497U, // FCVTMSv4f16 |
| 5028 | 1615020290U, // FCVTMSv4f32 |
| 5029 | 1615013474U, // FCVTMSv8f16 |
| 5030 | 4245322U, // FCVTMUUWDr |
| 5031 | 4245322U, // FCVTMUUWHr |
| 5032 | 4245322U, // FCVTMUUWSr |
| 5033 | 4245322U, // FCVTMUUXDr |
| 5034 | 4245322U, // FCVTMUUXHr |
| 5035 | 4245322U, // FCVTMUUXSr |
| 5036 | 4245322U, // FCVTMUv1f16 |
| 5037 | 4245322U, // FCVTMUv1i32 |
| 5038 | 4245322U, // FCVTMUv1i64 |
| 5039 | 1615018319U, // FCVTMUv2f32 |
| 5040 | 1615009386U, // FCVTMUv2f64 |
| 5041 | 1615011636U, // FCVTMUv4f16 |
| 5042 | 1615020429U, // FCVTMUv4f32 |
| 5043 | 1615013613U, // FCVTMUv8f16 |
| 5044 | 2151747075U, // FCVTNB_Z2Z_StoB |
| 5045 | 4244402U, // FCVTNSUWDr |
| 5046 | 4244402U, // FCVTNSUWHr |
| 5047 | 4244402U, // FCVTNSUWSr |
| 5048 | 4244402U, // FCVTNSUXDr |
| 5049 | 4244402U, // FCVTNSUXHr |
| 5050 | 4244402U, // FCVTNSUXSr |
| 5051 | 4244402U, // FCVTNSv1f16 |
| 5052 | 4244402U, // FCVTNSv1i32 |
| 5053 | 4244402U, // FCVTNSv1i64 |
| 5054 | 1615018191U, // FCVTNSv2f32 |
| 5055 | 1615009258U, // FCVTNSv2f64 |
| 5056 | 1615011508U, // FCVTNSv4f16 |
| 5057 | 1615020301U, // FCVTNSv4f32 |
| 5058 | 1615013485U, // FCVTNSv8f16 |
| 5059 | 2151761424U, // FCVTNT_Z2Z_StoB |
| 5060 | 541246992U, // FCVTNT_ZPmZ_DtoS |
| 5061 | 2156021264U, // FCVTNT_ZPmZ_StoH |
| 5062 | 4245330U, // FCVTNUUWDr |
| 5063 | 4245330U, // FCVTNUUWHr |
| 5064 | 4245330U, // FCVTNUUWSr |
| 5065 | 4245330U, // FCVTNUUXDr |
| 5066 | 4245330U, // FCVTNUUXHr |
| 5067 | 4245330U, // FCVTNUUXSr |
| 5068 | 4245330U, // FCVTNUv1f16 |
| 5069 | 4245330U, // FCVTNUv1i32 |
| 5070 | 4245330U, // FCVTNUv1i64 |
| 5071 | 1615018330U, // FCVTNUv2f32 |
| 5072 | 1615009397U, // FCVTNUv2f64 |
| 5073 | 1615011647U, // FCVTNUv4f16 |
| 5074 | 1615020440U, // FCVTNUv4f32 |
| 5075 | 1615013624U, // FCVTNUv8f16 |
| 5076 | 1644375938U, // FCVTN_F16_F8v16f8 |
| 5077 | 1745039234U, // FCVTN_F16_F8v8f8 |
| 5078 | 19290U, // FCVTN_F32_F82v16f8 |
| 5079 | 1745039234U, // FCVTN_F32_F8v8f8 |
| 5080 | 2688626562U, // FCVTN_Z2Z_HtoB |
| 5081 | 3284283266U, // FCVTN_Z2Z_StoH |
| 5082 | 2151755650U, // FCVTN_Z4Z_StoB_NAME |
| 5083 | 138620802U, // FCVTNv2i32 |
| 5084 | 142815106U, // FCVTNv4i16 |
| 5085 | 1657012359U, // FCVTNv4i32 |
| 5086 | 1652818055U, // FCVTNv8i16 |
| 5087 | 4244456U, // FCVTPSUWDr |
| 5088 | 4244456U, // FCVTPSUWHr |
| 5089 | 4244456U, // FCVTPSUWSr |
| 5090 | 4244456U, // FCVTPSUXDr |
| 5091 | 4244456U, // FCVTPSUXHr |
| 5092 | 4244456U, // FCVTPSUXSr |
| 5093 | 4244456U, // FCVTPSv1f16 |
| 5094 | 4244456U, // FCVTPSv1i32 |
| 5095 | 4244456U, // FCVTPSv1i64 |
| 5096 | 1615018213U, // FCVTPSv2f32 |
| 5097 | 1615009280U, // FCVTPSv2f64 |
| 5098 | 1615011530U, // FCVTPSv4f16 |
| 5099 | 1615020323U, // FCVTPSv4f32 |
| 5100 | 1615013507U, // FCVTPSv8f16 |
| 5101 | 4245338U, // FCVTPUUWDr |
| 5102 | 4245338U, // FCVTPUUWHr |
| 5103 | 4245338U, // FCVTPUUWSr |
| 5104 | 4245338U, // FCVTPUUXDr |
| 5105 | 4245338U, // FCVTPUUXHr |
| 5106 | 4245338U, // FCVTPUUXSr |
| 5107 | 4245338U, // FCVTPUv1f16 |
| 5108 | 4245338U, // FCVTPUv1i32 |
| 5109 | 4245338U, // FCVTPUv1i64 |
| 5110 | 1615018341U, // FCVTPUv2f32 |
| 5111 | 1615009408U, // FCVTPUv2f64 |
| 5112 | 1615011658U, // FCVTPUv4f16 |
| 5113 | 1615020451U, // FCVTPUv4f32 |
| 5114 | 1615013635U, // FCVTPUv8f16 |
| 5115 | 4245229U, // FCVTSDr |
| 5116 | 4245229U, // FCVTSHr |
| 5117 | 541247046U, // FCVTXNT_ZPmZ_DtoS |
| 5118 | 4239313U, // FCVTXNv1i64 |
| 5119 | 138620881U, // FCVTXNv2f32 |
| 5120 | 1657012367U, // FCVTXNv4f32 |
| 5121 | 541247985U, // FCVTX_ZPmZ_DtoS |
| 5122 | 4244515U, // FCVTZSSWDri |
| 5123 | 4244515U, // FCVTZSSWHri |
| 5124 | 4244515U, // FCVTZSSWSri |
| 5125 | 4244515U, // FCVTZSSXDri |
| 5126 | 4244515U, // FCVTZSSXHri |
| 5127 | 4244515U, // FCVTZSSXSri |
| 5128 | 4244515U, // FCVTZSUWDr |
| 5129 | 4244515U, // FCVTZSUWHr |
| 5130 | 4244515U, // FCVTZSUWSr |
| 5131 | 4244515U, // FCVTZSUXDr |
| 5132 | 4244515U, // FCVTZSUXHr |
| 5133 | 4244515U, // FCVTZSUXSr |
| 5134 | 3284550691U, // FCVTZS_2Z2Z_StoS |
| 5135 | 3284550691U, // FCVTZS_4Z4Z_StoS |
| 5136 | 541180963U, // FCVTZS_ZPmZ_DtoD |
| 5137 | 541246499U, // FCVTZS_ZPmZ_DtoS |
| 5138 | 541180963U, // FCVTZS_ZPmZ_HtoD |
| 5139 | 1082278947U, // FCVTZS_ZPmZ_HtoH |
| 5140 | 541246499U, // FCVTZS_ZPmZ_HtoS |
| 5141 | 541180963U, // FCVTZS_ZPmZ_StoD |
| 5142 | 541246499U, // FCVTZS_ZPmZ_StoS |
| 5143 | 4244515U, // FCVTZSd |
| 5144 | 4244515U, // FCVTZSh |
| 5145 | 4244515U, // FCVTZSs |
| 5146 | 4244515U, // FCVTZSv1f16 |
| 5147 | 4244515U, // FCVTZSv1i32 |
| 5148 | 4244515U, // FCVTZSv1i64 |
| 5149 | 1615018236U, // FCVTZSv2f32 |
| 5150 | 1615009303U, // FCVTZSv2f64 |
| 5151 | 1615018236U, // FCVTZSv2i32_shift |
| 5152 | 1615009303U, // FCVTZSv2i64_shift |
| 5153 | 1615011553U, // FCVTZSv4f16 |
| 5154 | 1615020346U, // FCVTZSv4f32 |
| 5155 | 1615011553U, // FCVTZSv4i16_shift |
| 5156 | 1615020346U, // FCVTZSv4i32_shift |
| 5157 | 1615013530U, // FCVTZSv8f16 |
| 5158 | 1615013530U, // FCVTZSv8i16_shift |
| 5159 | 4245363U, // FCVTZUSWDri |
| 5160 | 4245363U, // FCVTZUSWHri |
| 5161 | 4245363U, // FCVTZUSWSri |
| 5162 | 4245363U, // FCVTZUSXDri |
| 5163 | 4245363U, // FCVTZUSXHri |
| 5164 | 4245363U, // FCVTZUSXSri |
| 5165 | 4245363U, // FCVTZUUWDr |
| 5166 | 4245363U, // FCVTZUUWHr |
| 5167 | 4245363U, // FCVTZUUWSr |
| 5168 | 4245363U, // FCVTZUUXDr |
| 5169 | 4245363U, // FCVTZUUXHr |
| 5170 | 4245363U, // FCVTZUUXSr |
| 5171 | 3284551539U, // FCVTZU_2Z2Z_StoS |
| 5172 | 3284551539U, // FCVTZU_4Z4Z_StoS |
| 5173 | 541181811U, // FCVTZU_ZPmZ_DtoD |
| 5174 | 541247347U, // FCVTZU_ZPmZ_DtoS |
| 5175 | 541181811U, // FCVTZU_ZPmZ_HtoD |
| 5176 | 1082279795U, // FCVTZU_ZPmZ_HtoH |
| 5177 | 541247347U, // FCVTZU_ZPmZ_HtoS |
| 5178 | 541181811U, // FCVTZU_ZPmZ_StoD |
| 5179 | 541247347U, // FCVTZU_ZPmZ_StoS |
| 5180 | 4245363U, // FCVTZUd |
| 5181 | 4245363U, // FCVTZUh |
| 5182 | 4245363U, // FCVTZUs |
| 5183 | 4245363U, // FCVTZUv1f16 |
| 5184 | 4245363U, // FCVTZUv1i32 |
| 5185 | 4245363U, // FCVTZUv1i64 |
| 5186 | 1615018352U, // FCVTZUv2f32 |
| 5187 | 1615009419U, // FCVTZUv2f64 |
| 5188 | 1615018352U, // FCVTZUv2i32_shift |
| 5189 | 1615009419U, // FCVTZUv2i64_shift |
| 5190 | 1615011669U, // FCVTZUv4f16 |
| 5191 | 1615020462U, // FCVTZUv4f32 |
| 5192 | 1615011669U, // FCVTZUv4i16_shift |
| 5193 | 1615020462U, // FCVTZUv4i32_shift |
| 5194 | 1615013646U, // FCVTZUv8f16 |
| 5195 | 1615013646U, // FCVTZUv8i16_shift |
| 5196 | 3292940013U, // FCVT_2ZZ_H_S |
| 5197 | 2688632557U, // FCVT_Z2Z_HtoB |
| 5198 | 3284289261U, // FCVT_Z2Z_StoH |
| 5199 | 2151761645U, // FCVT_Z4Z_StoB_NAME |
| 5200 | 2692892397U, // FCVT_ZPmZ_DtoH |
| 5201 | 541247213U, // FCVT_ZPmZ_DtoS |
| 5202 | 541181677U, // FCVT_ZPmZ_HtoD |
| 5203 | 541247213U, // FCVT_ZPmZ_HtoS |
| 5204 | 541181677U, // FCVT_ZPmZ_StoD |
| 5205 | 2156021485U, // FCVT_ZPmZ_StoH |
| 5206 | 4245411U, // FDIVDrr |
| 5207 | 4245411U, // FDIVHrr |
| 5208 | 2151789485U, // FDIVR_ZPmZ_D |
| 5209 | 2713858989U, // FDIVR_ZPmZ_H |
| 5210 | 2151855021U, // FDIVR_ZPmZ_S |
| 5211 | 4245411U, // FDIVSrr |
| 5212 | 2151794595U, // FDIV_ZPmZ_D |
| 5213 | 2713864099U, // FDIV_ZPmZ_H |
| 5214 | 2151860131U, // FDIV_ZPmZ_S |
| 5215 | 1615018363U, // FDIVv2f32 |
| 5216 | 1615009430U, // FDIVv2f64 |
| 5217 | 1615011689U, // FDIVv4f16 |
| 5218 | 1615020482U, // FDIVv4f32 |
| 5219 | 1615013666U, // FDIVv8f16 |
| 5220 | 3289073238U, // FDOT_VG2_M2Z2Z_BtoH |
| 5221 | 3288811094U, // FDOT_VG2_M2Z2Z_BtoS |
| 5222 | 3288811094U, // FDOT_VG2_M2Z2Z_HtoS |
| 5223 | 3289073238U, // FDOT_VG2_M2ZZI_BtoH |
| 5224 | 3288811094U, // FDOT_VG2_M2ZZI_BtoS |
| 5225 | 3288811094U, // FDOT_VG2_M2ZZI_HtoS |
| 5226 | 3289073238U, // FDOT_VG2_M2ZZ_BtoH |
| 5227 | 3288811094U, // FDOT_VG2_M2ZZ_BtoS |
| 5228 | 3288811094U, // FDOT_VG2_M2ZZ_HtoS |
| 5229 | 3825944150U, // FDOT_VG4_M4Z4Z_BtoH |
| 5230 | 3825682006U, // FDOT_VG4_M4Z4Z_BtoS |
| 5231 | 3825682006U, // FDOT_VG4_M4Z4Z_HtoS |
| 5232 | 3825944150U, // FDOT_VG4_M4ZZI_BtoH |
| 5233 | 3825682006U, // FDOT_VG4_M4ZZI_BtoS |
| 5234 | 3825682006U, // FDOT_VG4_M4ZZI_HtoS |
| 5235 | 3825944150U, // FDOT_VG4_M4ZZ_BtoH |
| 5236 | 3825682006U, // FDOT_VG4_M4ZZ_BtoS |
| 5237 | 3825682006U, // FDOT_VG4_M4ZZ_HtoS |
| 5238 | 146949718U, // FDOT_ZZZI_BtoH |
| 5239 | 541247062U, // FDOT_ZZZI_BtoS |
| 5240 | 1078117974U, // FDOT_ZZZI_S |
| 5241 | 146949718U, // FDOT_ZZZ_BtoH |
| 5242 | 541247062U, // FDOT_ZZZ_BtoS |
| 5243 | 1078117974U, // FDOT_ZZZ_S |
| 5244 | 1615087190U, // FDOTlanev16f8 |
| 5245 | 1615087190U, // FDOTlanev4f16 |
| 5246 | 1615087190U, // FDOTlanev8f16 |
| 5247 | 1615087190U, // FDOTlanev8f8 |
| 5248 | 20934U, // FDOTv2f32 |
| 5249 | 20934U, // FDOTv4f16 |
| 5250 | 20934U, // FDOTv4f32 |
| 5251 | 20934U, // FDOTv8f16 |
| 5252 | 3225530701U, // FDUP_ZI_D |
| 5253 | 151138637U, // FDUP_ZI_H |
| 5254 | 3225596237U, // FDUP_ZI_S |
| 5255 | 541164081U, // FEXPA_ZZ_D |
| 5256 | 3292660273U, // FEXPA_ZZ_H |
| 5257 | 541229617U, // FEXPA_ZZ_S |
| 5258 | 4244523U, // FJCVTZS |
| 5259 | 541166613U, // FLOGB_ZPmZ_D |
| 5260 | 1082264597U, // FLOGB_ZPmZ_H |
| 5261 | 541232149U, // FLOGB_ZPmZ_S |
| 5262 | 4233187U, // FMADDDrrr |
| 5263 | 4233187U, // FMADDHrrr |
| 5264 | 4233187U, // FMADDSrrr |
| 5265 | 2151782235U, // FMAD_ZPmZZ_D |
| 5266 | 2713851739U, // FMAD_ZPmZZ_H |
| 5267 | 2151847771U, // FMAD_ZPmZZ_S |
| 5268 | 4245919U, // FMAXDrr |
| 5269 | 4245919U, // FMAXHrr |
| 5270 | 4239087U, // FMAXNMDrr |
| 5271 | 4239087U, // FMAXNMHrr |
| 5272 | 2151788698U, // FMAXNMP_ZPmZZ_D |
| 5273 | 2713858202U, // FMAXNMP_ZPmZZ_H |
| 5274 | 2151854234U, // FMAXNMP_ZPmZZ_S |
| 5275 | 1615017977U, // FMAXNMPv2f32 |
| 5276 | 1615009092U, // FMAXNMPv2f64 |
| 5277 | 1614846484U, // FMAXNMPv2i16p |
| 5278 | 1614854137U, // FMAXNMPv2i32p |
| 5279 | 1614845252U, // FMAXNMPv2i64p |
| 5280 | 1615011294U, // FMAXNMPv4f16 |
| 5281 | 1615020087U, // FMAXNMPv4f32 |
| 5282 | 1615013271U, // FMAXNMPv8f16 |
| 5283 | 2185447432U, // FMAXNMQV_D |
| 5284 | 2189641736U, // FMAXNMQV_H |
| 5285 | 2193836040U, // FMAXNMQV_S |
| 5286 | 4239087U, // FMAXNMSrr |
| 5287 | 3301459902U, // FMAXNMV_VPZ_D |
| 5288 | 3305686974U, // FMAXNMV_VPZ_H |
| 5289 | 3246999486U, // FMAXNMV_VPZ_S |
| 5290 | 1614847892U, // FMAXNMVv4i16v |
| 5291 | 1614856685U, // FMAXNMVv4i32v |
| 5292 | 1614849869U, // FMAXNMVv8i16v |
| 5293 | 54865647U, // FMAXNM_VG2_2Z2Z_D |
| 5294 | 59092719U, // FMAXNM_VG2_2Z2Z_H |
| 5295 | 63319791U, // FMAXNM_VG2_2Z2Z_S |
| 5296 | 54865647U, // FMAXNM_VG2_2ZZ_D |
| 5297 | 59092719U, // FMAXNM_VG2_2ZZ_H |
| 5298 | 63319791U, // FMAXNM_VG2_2ZZ_S |
| 5299 | 54865647U, // FMAXNM_VG4_4Z4Z_D |
| 5300 | 59092719U, // FMAXNM_VG4_4Z4Z_H |
| 5301 | 63319791U, // FMAXNM_VG4_4Z4Z_S |
| 5302 | 54865647U, // FMAXNM_VG4_4ZZ_D |
| 5303 | 59092719U, // FMAXNM_VG4_4ZZ_H |
| 5304 | 63319791U, // FMAXNM_VG4_4ZZ_S |
| 5305 | 2151788271U, // FMAXNM_ZPmI_D |
| 5306 | 2713857775U, // FMAXNM_ZPmI_H |
| 5307 | 2151853807U, // FMAXNM_ZPmI_S |
| 5308 | 2151788271U, // FMAXNM_ZPmZ_D |
| 5309 | 2713857775U, // FMAXNM_ZPmZ_H |
| 5310 | 2151853807U, // FMAXNM_ZPmZ_S |
| 5311 | 1615017717U, // FMAXNMv2f32 |
| 5312 | 1615008974U, // FMAXNMv2f64 |
| 5313 | 1615011023U, // FMAXNMv4f16 |
| 5314 | 1615019941U, // FMAXNMv4f32 |
| 5315 | 1615013135U, // FMAXNMv8f16 |
| 5316 | 2151788907U, // FMAXP_ZPmZZ_D |
| 5317 | 2713858411U, // FMAXP_ZPmZZ_H |
| 5318 | 2151854443U, // FMAXP_ZPmZZ_S |
| 5319 | 1615018038U, // FMAXPv2f32 |
| 5320 | 1615009133U, // FMAXPv2f64 |
| 5321 | 1614846506U, // FMAXPv2i16p |
| 5322 | 1614854198U, // FMAXPv2i32p |
| 5323 | 1614845293U, // FMAXPv2i64p |
| 5324 | 1615011355U, // FMAXPv4f16 |
| 5325 | 1615020148U, // FMAXPv4f32 |
| 5326 | 1615013332U, // FMAXPv8f16 |
| 5327 | 2185447473U, // FMAXQV_D |
| 5328 | 2189641777U, // FMAXQV_H |
| 5329 | 2193836081U, // FMAXQV_S |
| 5330 | 4245919U, // FMAXSrr |
| 5331 | 3301460047U, // FMAXV_VPZ_D |
| 5332 | 3305687119U, // FMAXV_VPZ_H |
| 5333 | 3246999631U, // FMAXV_VPZ_S |
| 5334 | 1614847943U, // FMAXVv4i16v |
| 5335 | 1614856736U, // FMAXVv4i32v |
| 5336 | 1614849920U, // FMAXVv8i16v |
| 5337 | 54872479U, // FMAX_VG2_2Z2Z_D |
| 5338 | 59099551U, // FMAX_VG2_2Z2Z_H |
| 5339 | 63326623U, // FMAX_VG2_2Z2Z_S |
| 5340 | 54872479U, // FMAX_VG2_2ZZ_D |
| 5341 | 59099551U, // FMAX_VG2_2ZZ_H |
| 5342 | 63326623U, // FMAX_VG2_2ZZ_S |
| 5343 | 54872479U, // FMAX_VG4_4Z4Z_D |
| 5344 | 59099551U, // FMAX_VG4_4Z4Z_H |
| 5345 | 63326623U, // FMAX_VG4_4Z4Z_S |
| 5346 | 54872479U, // FMAX_VG4_4ZZ_D |
| 5347 | 59099551U, // FMAX_VG4_4ZZ_H |
| 5348 | 63326623U, // FMAX_VG4_4ZZ_S |
| 5349 | 2151795103U, // FMAX_ZPmI_D |
| 5350 | 2713864607U, // FMAX_ZPmI_H |
| 5351 | 2151860639U, // FMAX_ZPmI_S |
| 5352 | 2151795103U, // FMAX_ZPmZ_D |
| 5353 | 2713864607U, // FMAX_ZPmZ_H |
| 5354 | 2151860639U, // FMAX_ZPmZ_S |
| 5355 | 1615018417U, // FMAXv2f32 |
| 5356 | 1615009524U, // FMAXv2f64 |
| 5357 | 1615011823U, // FMAXv4f16 |
| 5358 | 1615020682U, // FMAXv4f32 |
| 5359 | 1615013840U, // FMAXv8f16 |
| 5360 | 4239147U, // FMINDrr |
| 5361 | 4239147U, // FMINHrr |
| 5362 | 4239078U, // FMINNMDrr |
| 5363 | 4239078U, // FMINNMHrr |
| 5364 | 2151788689U, // FMINNMP_ZPmZZ_D |
| 5365 | 2713858193U, // FMINNMP_ZPmZZ_H |
| 5366 | 2151854225U, // FMINNMP_ZPmZZ_S |
| 5367 | 1615017965U, // FMINNMPv2f32 |
| 5368 | 1615009080U, // FMINNMPv2f64 |
| 5369 | 1614846472U, // FMINNMPv2i16p |
| 5370 | 1614854125U, // FMINNMPv2i32p |
| 5371 | 1614845240U, // FMINNMPv2i64p |
| 5372 | 1615011282U, // FMINNMPv4f16 |
| 5373 | 1615020075U, // FMINNMPv4f32 |
| 5374 | 1615013259U, // FMINNMPv8f16 |
| 5375 | 2185447422U, // FMINNMQV_D |
| 5376 | 2189641726U, // FMINNMQV_H |
| 5377 | 2193836030U, // FMINNMQV_S |
| 5378 | 4239078U, // FMINNMSrr |
| 5379 | 3301459893U, // FMINNMV_VPZ_D |
| 5380 | 3305686965U, // FMINNMV_VPZ_H |
| 5381 | 3246999477U, // FMINNMV_VPZ_S |
| 5382 | 1614847880U, // FMINNMVv4i16v |
| 5383 | 1614856673U, // FMINNMVv4i32v |
| 5384 | 1614849857U, // FMINNMVv8i16v |
| 5385 | 54865638U, // FMINNM_VG2_2Z2Z_D |
| 5386 | 59092710U, // FMINNM_VG2_2Z2Z_H |
| 5387 | 63319782U, // FMINNM_VG2_2Z2Z_S |
| 5388 | 54865638U, // FMINNM_VG2_2ZZ_D |
| 5389 | 59092710U, // FMINNM_VG2_2ZZ_H |
| 5390 | 63319782U, // FMINNM_VG2_2ZZ_S |
| 5391 | 54865638U, // FMINNM_VG4_4Z4Z_D |
| 5392 | 59092710U, // FMINNM_VG4_4Z4Z_H |
| 5393 | 63319782U, // FMINNM_VG4_4Z4Z_S |
| 5394 | 54865638U, // FMINNM_VG4_4ZZ_D |
| 5395 | 59092710U, // FMINNM_VG4_4ZZ_H |
| 5396 | 63319782U, // FMINNM_VG4_4ZZ_S |
| 5397 | 2151788262U, // FMINNM_ZPmI_D |
| 5398 | 2713857766U, // FMINNM_ZPmI_H |
| 5399 | 2151853798U, // FMINNM_ZPmI_S |
| 5400 | 2151788262U, // FMINNM_ZPmZ_D |
| 5401 | 2713857766U, // FMINNM_ZPmZ_H |
| 5402 | 2151853798U, // FMINNM_ZPmZ_S |
| 5403 | 1615017706U, // FMINNMv2f32 |
| 5404 | 1615008963U, // FMINNMv2f64 |
| 5405 | 1615011012U, // FMINNMv4f16 |
| 5406 | 1615019930U, // FMINNMv4f32 |
| 5407 | 1615013124U, // FMINNMv8f16 |
| 5408 | 2151788713U, // FMINP_ZPmZZ_D |
| 5409 | 2713858217U, // FMINP_ZPmZZ_H |
| 5410 | 2151854249U, // FMINP_ZPmZZ_S |
| 5411 | 1615017989U, // FMINPv2f32 |
| 5412 | 1615009104U, // FMINPv2f64 |
| 5413 | 1614846496U, // FMINPv2i16p |
| 5414 | 1614854149U, // FMINPv2i32p |
| 5415 | 1614845264U, // FMINPv2i64p |
| 5416 | 1615011306U, // FMINPv4f16 |
| 5417 | 1615020099U, // FMINPv4f32 |
| 5418 | 1615013283U, // FMINPv8f16 |
| 5419 | 2185447442U, // FMINQV_D |
| 5420 | 2189641746U, // FMINQV_H |
| 5421 | 2193836050U, // FMINQV_S |
| 5422 | 4239147U, // FMINSrr |
| 5423 | 3301459911U, // FMINV_VPZ_D |
| 5424 | 3305686983U, // FMINV_VPZ_H |
| 5425 | 3246999495U, // FMINV_VPZ_S |
| 5426 | 1614847904U, // FMINVv4i16v |
| 5427 | 1614856697U, // FMINVv4i32v |
| 5428 | 1614849881U, // FMINVv8i16v |
| 5429 | 54865707U, // FMIN_VG2_2Z2Z_D |
| 5430 | 59092779U, // FMIN_VG2_2Z2Z_H |
| 5431 | 63319851U, // FMIN_VG2_2Z2Z_S |
| 5432 | 54865707U, // FMIN_VG2_2ZZ_D |
| 5433 | 59092779U, // FMIN_VG2_2ZZ_H |
| 5434 | 63319851U, // FMIN_VG2_2ZZ_S |
| 5435 | 54865707U, // FMIN_VG4_4Z4Z_D |
| 5436 | 59092779U, // FMIN_VG4_4Z4Z_H |
| 5437 | 63319851U, // FMIN_VG4_4Z4Z_S |
| 5438 | 54865707U, // FMIN_VG4_4ZZ_D |
| 5439 | 59092779U, // FMIN_VG4_4ZZ_H |
| 5440 | 63319851U, // FMIN_VG4_4ZZ_S |
| 5441 | 2151788331U, // FMIN_ZPmI_D |
| 5442 | 2713857835U, // FMIN_ZPmI_H |
| 5443 | 2151853867U, // FMIN_ZPmI_S |
| 5444 | 2151788331U, // FMIN_ZPmZ_D |
| 5445 | 2713857835U, // FMIN_ZPmZ_H |
| 5446 | 2151853867U, // FMIN_ZPmZ_S |
| 5447 | 1615017771U, // FMINv2f32 |
| 5448 | 1615009006U, // FMINv2f64 |
| 5449 | 1615011077U, // FMINv4f16 |
| 5450 | 1615019973U, // FMINv4f32 |
| 5451 | 1615013167U, // FMINv8f16 |
| 5452 | 1615069289U, // FMLAL2lanev4f16 |
| 5453 | 1615069289U, // FMLAL2lanev8f16 |
| 5454 | 19276U, // FMLAL2v4f16 |
| 5455 | 19276U, // FMLAL2v8f16 |
| 5456 | 146934869U, // FMLALB_ZZZ |
| 5457 | 146934869U, // FMLALB_ZZZI |
| 5458 | 1078103125U, // FMLALB_ZZZI_SHH |
| 5459 | 1078103125U, // FMLALB_ZZZ_SHH |
| 5460 | 1615072341U, // FMLALBlanev8f16 |
| 5461 | 20759U, // FMLALBv8f16 |
| 5462 | 541232070U, // FMLALLBB_ZZZ |
| 5463 | 541232070U, // FMLALLBB_ZZZI |
| 5464 | 1615072198U, // FMLALLBBlanev4f32 |
| 5465 | 20749U, // FMLALLBBv4f32 |
| 5466 | 541246545U, // FMLALLBT_ZZZ |
| 5467 | 541246545U, // FMLALLBT_ZZZI |
| 5468 | 1615086673U, // FMLALLBTlanev4f32 |
| 5469 | 20903U, // FMLALLBTv4f32 |
| 5470 | 541233000U, // FMLALLTB_ZZZ |
| 5471 | 541233000U, // FMLALLTB_ZZZI |
| 5472 | 1615073128U, // FMLALLTBlanev4f32 |
| 5473 | 20769U, // FMLALLTBv4f32 |
| 5474 | 541247186U, // FMLALLTT_ZZZ |
| 5475 | 541247186U, // FMLALLTT_ZZZI |
| 5476 | 1615087314U, // FMLALLTTlanev4f32 |
| 5477 | 20950U, // FMLALLTTv4f32 |
| 5478 | 3376885001U, // FMLALL_MZZI_BtoS |
| 5479 | 3376885001U, // FMLALL_MZZ_BtoS |
| 5480 | 3376885001U, // FMLALL_VG2_M2Z2Z_BtoS |
| 5481 | 3376885001U, // FMLALL_VG2_M2ZZI_BtoS |
| 5482 | 3913755913U, // FMLALL_VG2_M2ZZ_BtoS |
| 5483 | 3913755913U, // FMLALL_VG4_M4Z4Z_BtoS |
| 5484 | 3913755913U, // FMLALL_VG4_M4ZZI_BtoS |
| 5485 | 155659529U, // FMLALL_VG4_M4ZZ_BtoS |
| 5486 | 146949349U, // FMLALT_ZZZ |
| 5487 | 146949349U, // FMLALT_ZZZI |
| 5488 | 1078117605U, // FMLALT_ZZZI_SHH |
| 5489 | 1078117605U, // FMLALT_ZZZ_SHH |
| 5490 | 1615086821U, // FMLALTlanev8f16 |
| 5491 | 20926U, // FMLALTv8f16 |
| 5492 | 3314232170U, // FMLAL_MZZI_BtoH |
| 5493 | 3313970026U, // FMLAL_MZZI_HtoS |
| 5494 | 3313970026U, // FMLAL_MZZ_HtoS |
| 5495 | 3314232170U, // FMLAL_VG2_M2Z2Z_BtoH |
| 5496 | 3313970026U, // FMLAL_VG2_M2Z2Z_HtoS |
| 5497 | 3314232170U, // FMLAL_VG2_M2ZZI_BtoH |
| 5498 | 3313970026U, // FMLAL_VG2_M2ZZI_HtoS |
| 5499 | 3314232170U, // FMLAL_VG2_M2ZZ_BtoH |
| 5500 | 3313970026U, // FMLAL_VG2_M2ZZ_HtoS |
| 5501 | 3314232170U, // FMLAL_VG2_MZZ_BtoH |
| 5502 | 3851103082U, // FMLAL_VG4_M4Z4Z_BtoH |
| 5503 | 3850840938U, // FMLAL_VG4_M4Z4Z_HtoS |
| 5504 | 3851103082U, // FMLAL_VG4_M4ZZI_BtoH |
| 5505 | 3850840938U, // FMLAL_VG4_M4ZZI_HtoS |
| 5506 | 3851103082U, // FMLAL_VG4_M4ZZ_BtoH |
| 5507 | 3850840938U, // FMLAL_VG4_M4ZZ_HtoS |
| 5508 | 1615080298U, // FMLALlanev4f16 |
| 5509 | 1615080298U, // FMLALlanev8f16 |
| 5510 | 20856U, // FMLALv4f16 |
| 5511 | 20856U, // FMLALv8f16 |
| 5512 | 3288760668U, // FMLA_VG2_M2Z2Z_D |
| 5513 | 3288793436U, // FMLA_VG2_M2Z2Z_S |
| 5514 | 3289055580U, // FMLA_VG2_M2Z4Z_H |
| 5515 | 3288760668U, // FMLA_VG2_M2ZZI_D |
| 5516 | 3289055580U, // FMLA_VG2_M2ZZI_H |
| 5517 | 3288793436U, // FMLA_VG2_M2ZZI_S |
| 5518 | 3288760668U, // FMLA_VG2_M2ZZ_D |
| 5519 | 3289055580U, // FMLA_VG2_M2ZZ_H |
| 5520 | 3288793436U, // FMLA_VG2_M2ZZ_S |
| 5521 | 3825631580U, // FMLA_VG4_M4Z4Z_D |
| 5522 | 3825926492U, // FMLA_VG4_M4Z4Z_H |
| 5523 | 3825664348U, // FMLA_VG4_M4Z4Z_S |
| 5524 | 3825631580U, // FMLA_VG4_M4ZZI_D |
| 5525 | 3825926492U, // FMLA_VG4_M4ZZI_H |
| 5526 | 3825664348U, // FMLA_VG4_M4ZZI_S |
| 5527 | 3825631580U, // FMLA_VG4_M4ZZ_D |
| 5528 | 3825926492U, // FMLA_VG4_M4ZZ_H |
| 5529 | 3825664348U, // FMLA_VG4_M4ZZ_S |
| 5530 | 2151776604U, // FMLA_ZPmZZ_D |
| 5531 | 2713846108U, // FMLA_ZPmZZ_H |
| 5532 | 2151842140U, // FMLA_ZPmZZ_S |
| 5533 | 2151776604U, // FMLA_ZZZI_D |
| 5534 | 84017500U, // FMLA_ZZZI_H |
| 5535 | 2688713052U, // FMLA_ZZZI_S |
| 5536 | 1615436099U, // FMLAv1i16_indexed |
| 5537 | 1615442917U, // FMLAv1i32_indexed |
| 5538 | 1615433848U, // FMLAv1i64_indexed |
| 5539 | 1615082697U, // FMLAv2f32 |
| 5540 | 1615073917U, // FMLAv2f64 |
| 5541 | 1615082697U, // FMLAv2i32_indexed |
| 5542 | 1615073917U, // FMLAv2i64_indexed |
| 5543 | 1615076026U, // FMLAv4f16 |
| 5544 | 1615084660U, // FMLAv4f32 |
| 5545 | 1615076026U, // FMLAv4i16_indexed |
| 5546 | 1615084660U, // FMLAv4i32_indexed |
| 5547 | 1615077944U, // FMLAv8f16 |
| 5548 | 1615077944U, // FMLAv8i16_indexed |
| 5549 | 1615069297U, // FMLSL2lanev4f16 |
| 5550 | 1615069297U, // FMLSL2lanev8f16 |
| 5551 | 19283U, // FMLSL2v4f16 |
| 5552 | 19283U, // FMLSL2v8f16 |
| 5553 | 1078103423U, // FMLSLB_ZZZI_SHH |
| 5554 | 1078103423U, // FMLSLB_ZZZ_SHH |
| 5555 | 1078117780U, // FMLSLT_ZZZI_SHH |
| 5556 | 1078117780U, // FMLSLT_ZZZ_SHH |
| 5557 | 3313970716U, // FMLSL_MZZI_HtoS |
| 5558 | 3313970716U, // FMLSL_MZZ_HtoS |
| 5559 | 3313970716U, // FMLSL_VG2_M2Z2Z_HtoS |
| 5560 | 3313970716U, // FMLSL_VG2_M2ZZI_HtoS |
| 5561 | 3313970716U, // FMLSL_VG2_M2ZZ_HtoS |
| 5562 | 3850841628U, // FMLSL_VG4_M4Z4Z_HtoS |
| 5563 | 3850841628U, // FMLSL_VG4_M4ZZI_HtoS |
| 5564 | 3850841628U, // FMLSL_VG4_M4ZZ_HtoS |
| 5565 | 1615080988U, // FMLSLlanev4f16 |
| 5566 | 1615080988U, // FMLSLlanev8f16 |
| 5567 | 20885U, // FMLSLv4f16 |
| 5568 | 20885U, // FMLSLv8f16 |
| 5569 | 3288777609U, // FMLS_VG2_M2Z2Z_D |
| 5570 | 3289072521U, // FMLS_VG2_M2Z2Z_H |
| 5571 | 3288810377U, // FMLS_VG2_M2Z2Z_S |
| 5572 | 3288777609U, // FMLS_VG2_M2ZZI_D |
| 5573 | 3289072521U, // FMLS_VG2_M2ZZI_H |
| 5574 | 3288810377U, // FMLS_VG2_M2ZZI_S |
| 5575 | 3288777609U, // FMLS_VG2_M2ZZ_D |
| 5576 | 3289072521U, // FMLS_VG2_M2ZZ_H |
| 5577 | 3288810377U, // FMLS_VG2_M2ZZ_S |
| 5578 | 3825943433U, // FMLS_VG4_M4Z2Z_H |
| 5579 | 3825648521U, // FMLS_VG4_M4Z4Z_D |
| 5580 | 3825681289U, // FMLS_VG4_M4Z4Z_S |
| 5581 | 3825648521U, // FMLS_VG4_M4ZZI_D |
| 5582 | 3825943433U, // FMLS_VG4_M4ZZI_H |
| 5583 | 3825681289U, // FMLS_VG4_M4ZZI_S |
| 5584 | 3825648521U, // FMLS_VG4_M4ZZ_D |
| 5585 | 3825943433U, // FMLS_VG4_M4ZZ_H |
| 5586 | 3825681289U, // FMLS_VG4_M4ZZ_S |
| 5587 | 2151793545U, // FMLS_ZPmZZ_D |
| 5588 | 2713863049U, // FMLS_ZPmZZ_H |
| 5589 | 2151859081U, // FMLS_ZPmZZ_S |
| 5590 | 2151793545U, // FMLS_ZZZI_D |
| 5591 | 84034441U, // FMLS_ZZZI_H |
| 5592 | 2688729993U, // FMLS_ZZZI_S |
| 5593 | 1615436195U, // FMLSv1i16_indexed |
| 5594 | 1615443013U, // FMLSv1i32_indexed |
| 5595 | 1615433864U, // FMLSv1i64_indexed |
| 5596 | 1615083707U, // FMLSv2f32 |
| 5597 | 1615074774U, // FMLSv2f64 |
| 5598 | 1615083707U, // FMLSv2i32_indexed |
| 5599 | 1615074774U, // FMLSv2i64_indexed |
| 5600 | 1615077024U, // FMLSv4f16 |
| 5601 | 1615085817U, // FMLSv4f32 |
| 5602 | 1615077024U, // FMLSv4i16_indexed |
| 5603 | 1615085817U, // FMLSv4i32_indexed |
| 5604 | 1615079001U, // FMLSv8f16 |
| 5605 | 1615079001U, // FMLSv8i16_indexed |
| 5606 | 2151776611U, // FMMLA_ZZZ_D |
| 5607 | 2688713059U, // FMMLA_ZZZ_S |
| 5608 | 96698785U, // FMOPAL_MPPZZ |
| 5609 | 159613345U, // FMOPA_MPPZZ_BtoH |
| 5610 | 159613345U, // FMOPA_MPPZZ_BtoS |
| 5611 | 12812705U, // FMOPA_MPPZZ_D |
| 5612 | 96698785U, // FMOPA_MPPZZ_H |
| 5613 | 17007009U, // FMOPA_MPPZZ_S |
| 5614 | 96715729U, // FMOPSL_MPPZZ |
| 5615 | 12829649U, // FMOPS_MPPZZ_D |
| 5616 | 96715729U, // FMOPS_MPPZZ_H |
| 5617 | 17023953U, // FMOPS_MPPZZ_S |
| 5618 | 1614844055U, // FMOVDXHighr |
| 5619 | 4245475U, // FMOVDXr |
| 5620 | 3225470947U, // FMOVDi |
| 5621 | 4245475U, // FMOVDr |
| 5622 | 4245475U, // FMOVHWr |
| 5623 | 4245475U, // FMOVHXr |
| 5624 | 3225470947U, // FMOVHi |
| 5625 | 4245475U, // FMOVHr |
| 5626 | 4245475U, // FMOVSWr |
| 5627 | 3225470947U, // FMOVSi |
| 5628 | 4245475U, // FMOVSr |
| 5629 | 4245475U, // FMOVWHr |
| 5630 | 4245475U, // FMOVWSr |
| 5631 | 163778711U, // FMOVXDHighr |
| 5632 | 4245475U, // FMOVXDr |
| 5633 | 4245475U, // FMOVXHr |
| 5634 | 3225631108U, // FMOVv2f32_ns |
| 5635 | 3225622175U, // FMOVv2f64_ns |
| 5636 | 3225624510U, // FMOVv4f16_ns |
| 5637 | 3225633303U, // FMOVv4f32_ns |
| 5638 | 3225626487U, // FMOVv8f16_ns |
| 5639 | 2151780124U, // FMSB_ZPmZZ_D |
| 5640 | 2713849628U, // FMSB_ZPmZZ_H |
| 5641 | 2151845660U, // FMSB_ZPmZZ_S |
| 5642 | 4231080U, // FMSUBDrrr |
| 5643 | 4231080U, // FMSUBHrrr |
| 5644 | 4231080U, // FMSUBSrrr |
| 5645 | 4238956U, // FMULDrr |
| 5646 | 4238956U, // FMULHrr |
| 5647 | 4238956U, // FMULSrr |
| 5648 | 4245978U, // FMULX16 |
| 5649 | 4245978U, // FMULX32 |
| 5650 | 4245978U, // FMULX64 |
| 5651 | 2151795162U, // FMULX_ZPmZ_D |
| 5652 | 2713864666U, // FMULX_ZPmZ_H |
| 5653 | 2151860698U, // FMULX_ZPmZ_S |
| 5654 | 4233666U, // FMULXv1i16_indexed |
| 5655 | 4240484U, // FMULXv1i32_indexed |
| 5656 | 4231335U, // FMULXv1i64_indexed |
| 5657 | 1615018444U, // FMULXv2f32 |
| 5658 | 1615009533U, // FMULXv2f64 |
| 5659 | 1615018444U, // FMULXv2i32_indexed |
| 5660 | 1615009533U, // FMULXv2i64_indexed |
| 5661 | 1615011850U, // FMULXv4f16 |
| 5662 | 1615020709U, // FMULXv4f32 |
| 5663 | 1615011850U, // FMULXv4i16_indexed |
| 5664 | 1615020709U, // FMULXv4i32_indexed |
| 5665 | 1615013867U, // FMULXv8f16 |
| 5666 | 1615013867U, // FMULXv8i16_indexed |
| 5667 | 2151788140U, // FMUL_ZPmI_D |
| 5668 | 2713857644U, // FMUL_ZPmI_H |
| 5669 | 2151853676U, // FMUL_ZPmI_S |
| 5670 | 2151788140U, // FMUL_ZPmZ_D |
| 5671 | 2713857644U, // FMUL_ZPmZ_H |
| 5672 | 2151853676U, // FMUL_ZPmZ_S |
| 5673 | 541175404U, // FMUL_ZZZI_D |
| 5674 | 71446124U, // FMUL_ZZZI_H |
| 5675 | 541240940U, // FMUL_ZZZI_S |
| 5676 | 541175404U, // FMUL_ZZZ_D |
| 5677 | 71446124U, // FMUL_ZZZ_H |
| 5678 | 541240940U, // FMUL_ZZZ_S |
| 5679 | 4233627U, // FMULv1i16_indexed |
| 5680 | 4240445U, // FMULv1i32_indexed |
| 5681 | 4231296U, // FMULv1i64_indexed |
| 5682 | 1615017697U, // FMULv2f32 |
| 5683 | 1615008954U, // FMULv2f64 |
| 5684 | 1615017697U, // FMULv2i32_indexed |
| 5685 | 1615008954U, // FMULv2i64_indexed |
| 5686 | 1615011003U, // FMULv4f16 |
| 5687 | 1615019911U, // FMULv4f32 |
| 5688 | 1615011003U, // FMULv4i16_indexed |
| 5689 | 1615019911U, // FMULv4i32_indexed |
| 5690 | 1615013115U, // FMULv8f16 |
| 5691 | 1615013115U, // FMULv8i16_indexed |
| 5692 | 4233494U, // FNEGDr |
| 5693 | 4233494U, // FNEGHr |
| 5694 | 4233494U, // FNEGSr |
| 5695 | 541169942U, // FNEG_ZPmZ_D |
| 5696 | 1082267926U, // FNEG_ZPmZ_H |
| 5697 | 541235478U, // FNEG_ZPmZ_S |
| 5698 | 1615017493U, // FNEGv2f32 |
| 5699 | 1615008602U, // FNEGv2f64 |
| 5700 | 1615010799U, // FNEGv4f16 |
| 5701 | 1615019499U, // FNEGv4f32 |
| 5702 | 1615012717U, // FNEGv8f16 |
| 5703 | 4233194U, // FNMADDDrrr |
| 5704 | 4233194U, // FNMADDHrrr |
| 5705 | 4233194U, // FNMADDSrrr |
| 5706 | 2151782241U, // FNMAD_ZPmZZ_D |
| 5707 | 2713851745U, // FNMAD_ZPmZZ_H |
| 5708 | 2151847777U, // FNMAD_ZPmZZ_S |
| 5709 | 2151776633U, // FNMLA_ZPmZZ_D |
| 5710 | 2713846137U, // FNMLA_ZPmZZ_H |
| 5711 | 2151842169U, // FNMLA_ZPmZZ_S |
| 5712 | 2151793551U, // FNMLS_ZPmZZ_D |
| 5713 | 2713863055U, // FNMLS_ZPmZZ_H |
| 5714 | 2151859087U, // FNMLS_ZPmZZ_S |
| 5715 | 2151780130U, // FNMSB_ZPmZZ_D |
| 5716 | 2713849634U, // FNMSB_ZPmZZ_H |
| 5717 | 2151845666U, // FNMSB_ZPmZZ_S |
| 5718 | 4231087U, // FNMSUBDrrr |
| 5719 | 4231087U, // FNMSUBHrrr |
| 5720 | 4231087U, // FNMSUBSrrr |
| 5721 | 4238962U, // FNMULDrr |
| 5722 | 4238962U, // FNMULHrr |
| 5723 | 4238962U, // FNMULSrr |
| 5724 | 541169823U, // FRECPE_ZZ_D |
| 5725 | 3292666015U, // FRECPE_ZZ_H |
| 5726 | 541235359U, // FRECPE_ZZ_S |
| 5727 | 4233375U, // FRECPEv1f16 |
| 5728 | 4233375U, // FRECPEv1i32 |
| 5729 | 4233375U, // FRECPEv1i64 |
| 5730 | 1615017427U, // FRECPEv2f32 |
| 5731 | 1615008559U, // FRECPEv2f64 |
| 5732 | 1615010756U, // FRECPEv4f16 |
| 5733 | 1615019433U, // FRECPEv4f32 |
| 5734 | 1615012674U, // FRECPEv8f16 |
| 5735 | 4244417U, // FRECPS16 |
| 5736 | 4244417U, // FRECPS32 |
| 5737 | 4244417U, // FRECPS64 |
| 5738 | 541180865U, // FRECPS_ZZZ_D |
| 5739 | 71451585U, // FRECPS_ZZZ_H |
| 5740 | 541246401U, // FRECPS_ZZZ_S |
| 5741 | 1615018202U, // FRECPSv2f32 |
| 5742 | 1615009269U, // FRECPSv2f64 |
| 5743 | 1615011519U, // FRECPSv4f16 |
| 5744 | 1615020312U, // FRECPSv4f32 |
| 5745 | 1615013496U, // FRECPSv8f16 |
| 5746 | 541182433U, // FRECPX_ZPmZ_D |
| 5747 | 1082280417U, // FRECPX_ZPmZ_H |
| 5748 | 541247969U, // FRECPX_ZPmZ_S |
| 5749 | 4245985U, // FRECPXv1f16 |
| 5750 | 4245985U, // FRECPXv1i32 |
| 5751 | 4245985U, // FRECPXv1i64 |
| 5752 | 4245885U, // FRINT32XDr |
| 5753 | 4245885U, // FRINT32XSr |
| 5754 | 1615018381U, // FRINT32Xv2f32 |
| 5755 | 1615009488U, // FRINT32Xv2f64 |
| 5756 | 1615020646U, // FRINT32Xv4f32 |
| 5757 | 4246023U, // FRINT32ZDr |
| 5758 | 4246023U, // FRINT32ZSr |
| 5759 | 1615018465U, // FRINT32Zv2f32 |
| 5760 | 1615009554U, // FRINT32Zv2f64 |
| 5761 | 1615020742U, // FRINT32Zv4f32 |
| 5762 | 4245895U, // FRINT64XDr |
| 5763 | 4245895U, // FRINT64XSr |
| 5764 | 1615018394U, // FRINT64Xv2f32 |
| 5765 | 1615009501U, // FRINT64Xv2f64 |
| 5766 | 1615020659U, // FRINT64Xv4f32 |
| 5767 | 4246033U, // FRINT64ZDr |
| 5768 | 4246033U, // FRINT64ZSr |
| 5769 | 1615018478U, // FRINT64Zv2f32 |
| 5770 | 1615009567U, // FRINT64Zv2f64 |
| 5771 | 1615020755U, // FRINT64Zv4f32 |
| 5772 | 4227747U, // FRINTADr |
| 5773 | 4227747U, // FRINTAHr |
| 5774 | 4227747U, // FRINTASr |
| 5775 | 3284533923U, // FRINTA_2Z2Z_S |
| 5776 | 3284533923U, // FRINTA_4Z4Z_S |
| 5777 | 541164195U, // FRINTA_ZPmZ_D |
| 5778 | 1082262179U, // FRINTA_ZPmZ_H |
| 5779 | 541229731U, // FRINTA_ZPmZ_S |
| 5780 | 1615017208U, // FRINTAv2f32 |
| 5781 | 1615008428U, // FRINTAv2f64 |
| 5782 | 1615010537U, // FRINTAv4f16 |
| 5783 | 1615019171U, // FRINTAv4f32 |
| 5784 | 1615012455U, // FRINTAv8f16 |
| 5785 | 4238128U, // FRINTIDr |
| 5786 | 4238128U, // FRINTIHr |
| 5787 | 4238128U, // FRINTISr |
| 5788 | 541174576U, // FRINTI_ZPmZ_D |
| 5789 | 1082272560U, // FRINTI_ZPmZ_H |
| 5790 | 541240112U, // FRINTI_ZPmZ_S |
| 5791 | 1615017597U, // FRINTIv2f32 |
| 5792 | 1615008658U, // FRINTIv2f64 |
| 5793 | 1615010903U, // FRINTIv4f16 |
| 5794 | 1615019615U, // FRINTIv4f32 |
| 5795 | 1615012821U, // FRINTIv8f16 |
| 5796 | 4239110U, // FRINTMDr |
| 5797 | 4239110U, // FRINTMHr |
| 5798 | 4239110U, // FRINTMSr |
| 5799 | 3284545286U, // FRINTM_2Z2Z_S |
| 5800 | 3284545286U, // FRINTM_4Z4Z_S |
| 5801 | 541175558U, // FRINTM_ZPmZ_D |
| 5802 | 1082273542U, // FRINTM_ZPmZ_H |
| 5803 | 541241094U, // FRINTM_ZPmZ_S |
| 5804 | 1615017728U, // FRINTMv2f32 |
| 5805 | 1615008985U, // FRINTMv2f64 |
| 5806 | 1615011034U, // FRINTMv4f16 |
| 5807 | 1615019952U, // FRINTMv4f32 |
| 5808 | 1615013146U, // FRINTMv8f16 |
| 5809 | 4239225U, // FRINTNDr |
| 5810 | 4239225U, // FRINTNHr |
| 5811 | 4239225U, // FRINTNSr |
| 5812 | 3284545401U, // FRINTN_2Z2Z_S |
| 5813 | 3284545401U, // FRINTN_4Z4Z_S |
| 5814 | 541175673U, // FRINTN_ZPmZ_D |
| 5815 | 1082273657U, // FRINTN_ZPmZ_H |
| 5816 | 541241209U, // FRINTN_ZPmZ_S |
| 5817 | 1615017844U, // FRINTNv2f32 |
| 5818 | 1615009015U, // FRINTNv2f64 |
| 5819 | 1615011150U, // FRINTNv4f16 |
| 5820 | 1615020000U, // FRINTNv4f32 |
| 5821 | 1615013194U, // FRINTNv8f16 |
| 5822 | 4239680U, // FRINTPDr |
| 5823 | 4239680U, // FRINTPHr |
| 5824 | 4239680U, // FRINTPSr |
| 5825 | 3284545856U, // FRINTP_2Z2Z_S |
| 5826 | 3284545856U, // FRINTP_4Z4Z_S |
| 5827 | 541176128U, // FRINTP_ZPmZ_D |
| 5828 | 1082274112U, // FRINTP_ZPmZ_H |
| 5829 | 541241664U, // FRINTP_ZPmZ_S |
| 5830 | 1615018019U, // FRINTPv2f32 |
| 5831 | 1615009114U, // FRINTPv2f64 |
| 5832 | 1615011336U, // FRINTPv4f16 |
| 5833 | 1615020129U, // FRINTPv4f32 |
| 5834 | 1615013313U, // FRINTPv8f16 |
| 5835 | 4245993U, // FRINTXDr |
| 5836 | 4245993U, // FRINTXHr |
| 5837 | 4245993U, // FRINTXSr |
| 5838 | 541182441U, // FRINTX_ZPmZ_D |
| 5839 | 1082280425U, // FRINTX_ZPmZ_H |
| 5840 | 541247977U, // FRINTX_ZPmZ_S |
| 5841 | 1615018454U, // FRINTXv2f32 |
| 5842 | 1615009543U, // FRINTXv2f64 |
| 5843 | 1615011860U, // FRINTXv4f16 |
| 5844 | 1615020719U, // FRINTXv4f32 |
| 5845 | 1615013877U, // FRINTXv8f16 |
| 5846 | 4246112U, // FRINTZDr |
| 5847 | 4246112U, // FRINTZHr |
| 5848 | 4246112U, // FRINTZSr |
| 5849 | 541182560U, // FRINTZ_ZPmZ_D |
| 5850 | 1082280544U, // FRINTZ_ZPmZ_H |
| 5851 | 541248096U, // FRINTZ_ZPmZ_S |
| 5852 | 1615018499U, // FRINTZv2f32 |
| 5853 | 1615009580U, // FRINTZv2f64 |
| 5854 | 1615011879U, // FRINTZv4f16 |
| 5855 | 1615020776U, // FRINTZv4f32 |
| 5856 | 1615013896U, // FRINTZv8f16 |
| 5857 | 541169868U, // FRSQRTE_ZZ_D |
| 5858 | 3292666060U, // FRSQRTE_ZZ_H |
| 5859 | 541235404U, // FRSQRTE_ZZ_S |
| 5860 | 4233420U, // FRSQRTEv1f16 |
| 5861 | 4233420U, // FRSQRTEv1i32 |
| 5862 | 4233420U, // FRSQRTEv1i64 |
| 5863 | 1615017449U, // FRSQRTEv2f32 |
| 5864 | 1615008570U, // FRSQRTEv2f64 |
| 5865 | 1615010767U, // FRSQRTEv4f16 |
| 5866 | 1615019455U, // FRSQRTEv4f32 |
| 5867 | 1615012685U, // FRSQRTEv8f16 |
| 5868 | 4244501U, // FRSQRTS16 |
| 5869 | 4244501U, // FRSQRTS32 |
| 5870 | 4244501U, // FRSQRTS64 |
| 5871 | 541180949U, // FRSQRTS_ZZZ_D |
| 5872 | 71451669U, // FRSQRTS_ZZZ_H |
| 5873 | 541246485U, // FRSQRTS_ZZZ_S |
| 5874 | 1615018224U, // FRSQRTSv2f32 |
| 5875 | 1615009291U, // FRSQRTSv2f64 |
| 5876 | 1615011541U, // FRSQRTSv4f16 |
| 5877 | 1615020334U, // FRSQRTSv4f32 |
| 5878 | 1615013518U, // FRSQRTSv8f16 |
| 5879 | 54859881U, // FSCALE_2Z2Z_D |
| 5880 | 59086953U, // FSCALE_2Z2Z_H |
| 5881 | 63314025U, // FSCALE_2Z2Z_S |
| 5882 | 54859881U, // FSCALE_2ZZ_D |
| 5883 | 59086953U, // FSCALE_2ZZ_H |
| 5884 | 63314025U, // FSCALE_2ZZ_S |
| 5885 | 54859881U, // FSCALE_4Z4Z_D |
| 5886 | 59086953U, // FSCALE_4Z4Z_H |
| 5887 | 63314025U, // FSCALE_4Z4Z_S |
| 5888 | 54859881U, // FSCALE_4ZZ_D |
| 5889 | 59086953U, // FSCALE_4ZZ_H |
| 5890 | 63314025U, // FSCALE_4ZZ_S |
| 5891 | 2151782505U, // FSCALE_ZPmZ_D |
| 5892 | 2713852009U, // FSCALE_ZPmZ_H |
| 5893 | 2151848041U, // FSCALE_ZPmZ_S |
| 5894 | 1615017406U, // FSCALEv2f32 |
| 5895 | 1615008538U, // FSCALEv2f64 |
| 5896 | 1615010735U, // FSCALEv4f16 |
| 5897 | 1615019412U, // FSCALEv4f32 |
| 5898 | 1615012653U, // FSCALEv8f16 |
| 5899 | 4245166U, // FSQRTDr |
| 5900 | 4245166U, // FSQRTHr |
| 5901 | 4245166U, // FSQRTSr |
| 5902 | 541181614U, // FSQRT_ZPmZ_D |
| 5903 | 1082279598U, // FSQRT_ZPmZ_H |
| 5904 | 541247150U, // FSQRT_ZPmZ_S |
| 5905 | 1615018277U, // FSQRTv2f32 |
| 5906 | 1615009344U, // FSQRTv2f64 |
| 5907 | 1615011594U, // FSQRTv4f16 |
| 5908 | 1615020387U, // FSQRTv4f32 |
| 5909 | 1615013571U, // FSQRTv8f16 |
| 5910 | 4231060U, // FSUBDrr |
| 5911 | 4231060U, // FSUBHrr |
| 5912 | 2151789110U, // FSUBR_ZPmI_D |
| 5913 | 2713858614U, // FSUBR_ZPmI_H |
| 5914 | 2151854646U, // FSUBR_ZPmI_S |
| 5915 | 2151789110U, // FSUBR_ZPmZ_D |
| 5916 | 2713858614U, // FSUBR_ZPmZ_H |
| 5917 | 2151854646U, // FSUBR_ZPmZ_S |
| 5918 | 4231060U, // FSUBSrr |
| 5919 | 3288764308U, // FSUB_VG2_M2Z_D |
| 5920 | 3289059220U, // FSUB_VG2_M2Z_H |
| 5921 | 3288797076U, // FSUB_VG2_M2Z_S |
| 5922 | 3825635220U, // FSUB_VG4_M4Z_D |
| 5923 | 3825930132U, // FSUB_VG4_M4Z_H |
| 5924 | 3825667988U, // FSUB_VG4_M4Z_S |
| 5925 | 2151780244U, // FSUB_ZPmI_D |
| 5926 | 2713849748U, // FSUB_ZPmI_H |
| 5927 | 2151845780U, // FSUB_ZPmI_S |
| 5928 | 2151780244U, // FSUB_ZPmZ_D |
| 5929 | 2713849748U, // FSUB_ZPmZ_H |
| 5930 | 2151845780U, // FSUB_ZPmZ_S |
| 5931 | 541167508U, // FSUB_ZZZ_D |
| 5932 | 71438228U, // FSUB_ZZZ_H |
| 5933 | 541233044U, // FSUB_ZZZ_S |
| 5934 | 1615017219U, // FSUBv2f32 |
| 5935 | 1615008439U, // FSUBv2f64 |
| 5936 | 1615010548U, // FSUBv4f16 |
| 5937 | 1615019206U, // FSUBv4f32 |
| 5938 | 1615012466U, // FSUBv8f16 |
| 5939 | 541169512U, // FTMAD_ZZI_D |
| 5940 | 71440232U, // FTMAD_ZZI_H |
| 5941 | 541235048U, // FTMAD_ZZI_S |
| 5942 | 541175423U, // FTSMUL_ZZZ_D |
| 5943 | 71446143U, // FTSMUL_ZZZ_H |
| 5944 | 541240959U, // FTSMUL_ZZZ_S |
| 5945 | 541174985U, // FTSSEL_ZZZ_D |
| 5946 | 71445705U, // FTSSEL_ZZZ_H |
| 5947 | 541240521U, // FTSSEL_ZZZ_S |
| 5948 | 20778U, // FVDOTB_VG4_M2ZZI_BtoS |
| 5949 | 20959U, // FVDOTT_VG4_M2ZZI_BtoS |
| 5950 | 3289073259U, // FVDOT_VG2_M2ZZI_BtoH |
| 5951 | 3288811115U, // FVDOT_VG2_M2ZZI_HtoS |
| 5952 | 20972U, // GCSPOPCX |
| 5953 | 44791U, // GCSPOPM |
| 5954 | 20990U, // GCSPOPX |
| 5955 | 44763U, // GCSPUSHM |
| 5956 | 20981U, // GCSPUSHX |
| 5957 | 32835U, // GCSSS1 |
| 5958 | 32953U, // GCSSS2 |
| 5959 | 75543419U, // GCSSTR |
| 5960 | 75543427U, // GCSSTTR |
| 5961 | 566559497U, // GLD1B_D |
| 5962 | 566559497U, // GLD1B_D_IMM |
| 5963 | 566559497U, // GLD1B_D_SXTW |
| 5964 | 566559497U, // GLD1B_D_UXTW |
| 5965 | 566625033U, // GLD1B_S_IMM |
| 5966 | 566625033U, // GLD1B_S_SXTW |
| 5967 | 566625033U, // GLD1B_S_UXTW |
| 5968 | 566563036U, // GLD1D |
| 5969 | 566563036U, // GLD1D_IMM |
| 5970 | 566563036U, // GLD1D_SCALED |
| 5971 | 566563036U, // GLD1D_SXTW |
| 5972 | 566563036U, // GLD1D_SXTW_SCALED |
| 5973 | 566563036U, // GLD1D_UXTW |
| 5974 | 566563036U, // GLD1D_UXTW_SCALED |
| 5975 | 566565330U, // GLD1H_D |
| 5976 | 566565330U, // GLD1H_D_IMM |
| 5977 | 566565330U, // GLD1H_D_SCALED |
| 5978 | 566565330U, // GLD1H_D_SXTW |
| 5979 | 566565330U, // GLD1H_D_SXTW_SCALED |
| 5980 | 566565330U, // GLD1H_D_UXTW |
| 5981 | 566565330U, // GLD1H_D_UXTW_SCALED |
| 5982 | 566630866U, // GLD1H_S_IMM |
| 5983 | 566630866U, // GLD1H_S_SXTW |
| 5984 | 566630866U, // GLD1H_S_SXTW_SCALED |
| 5985 | 566630866U, // GLD1H_S_UXTW |
| 5986 | 566630866U, // GLD1H_S_UXTW_SCALED |
| 5987 | 567226797U, // GLD1Q |
| 5988 | 566562538U, // GLD1SB_D |
| 5989 | 566562538U, // GLD1SB_D_IMM |
| 5990 | 566562538U, // GLD1SB_D_SXTW |
| 5991 | 566562538U, // GLD1SB_D_UXTW |
| 5992 | 566628074U, // GLD1SB_S_IMM |
| 5993 | 566628074U, // GLD1SB_S_SXTW |
| 5994 | 566628074U, // GLD1SB_S_UXTW |
| 5995 | 566569564U, // GLD1SH_D |
| 5996 | 566569564U, // GLD1SH_D_IMM |
| 5997 | 566569564U, // GLD1SH_D_SCALED |
| 5998 | 566569564U, // GLD1SH_D_SXTW |
| 5999 | 566569564U, // GLD1SH_D_SXTW_SCALED |
| 6000 | 566569564U, // GLD1SH_D_UXTW |
| 6001 | 566569564U, // GLD1SH_D_UXTW_SCALED |
| 6002 | 566635100U, // GLD1SH_S_IMM |
| 6003 | 566635100U, // GLD1SH_S_SXTW |
| 6004 | 566635100U, // GLD1SH_S_SXTW_SCALED |
| 6005 | 566635100U, // GLD1SH_S_UXTW |
| 6006 | 566635100U, // GLD1SH_S_UXTW_SCALED |
| 6007 | 566577419U, // GLD1SW_D |
| 6008 | 566577419U, // GLD1SW_D_IMM |
| 6009 | 566577419U, // GLD1SW_D_SCALED |
| 6010 | 566577419U, // GLD1SW_D_SXTW |
| 6011 | 566577419U, // GLD1SW_D_SXTW_SCALED |
| 6012 | 566577419U, // GLD1SW_D_UXTW |
| 6013 | 566577419U, // GLD1SW_D_UXTW_SCALED |
| 6014 | 566577252U, // GLD1W_D |
| 6015 | 566577252U, // GLD1W_D_IMM |
| 6016 | 566577252U, // GLD1W_D_SCALED |
| 6017 | 566577252U, // GLD1W_D_SXTW |
| 6018 | 566577252U, // GLD1W_D_SXTW_SCALED |
| 6019 | 566577252U, // GLD1W_D_UXTW |
| 6020 | 566577252U, // GLD1W_D_UXTW_SCALED |
| 6021 | 566642788U, // GLD1W_IMM |
| 6022 | 566642788U, // GLD1W_SXTW |
| 6023 | 566642788U, // GLD1W_SXTW_SCALED |
| 6024 | 566642788U, // GLD1W_UXTW |
| 6025 | 566642788U, // GLD1W_UXTW_SCALED |
| 6026 | 566559503U, // GLDFF1B_D |
| 6027 | 566559503U, // GLDFF1B_D_IMM |
| 6028 | 566559503U, // GLDFF1B_D_SXTW |
| 6029 | 566559503U, // GLDFF1B_D_UXTW |
| 6030 | 566625039U, // GLDFF1B_S_IMM |
| 6031 | 566625039U, // GLDFF1B_S_SXTW |
| 6032 | 566625039U, // GLDFF1B_S_UXTW |
| 6033 | 566563042U, // GLDFF1D |
| 6034 | 566563042U, // GLDFF1D_IMM |
| 6035 | 566563042U, // GLDFF1D_SCALED |
| 6036 | 566563042U, // GLDFF1D_SXTW |
| 6037 | 566563042U, // GLDFF1D_SXTW_SCALED |
| 6038 | 566563042U, // GLDFF1D_UXTW |
| 6039 | 566563042U, // GLDFF1D_UXTW_SCALED |
| 6040 | 566565336U, // GLDFF1H_D |
| 6041 | 566565336U, // GLDFF1H_D_IMM |
| 6042 | 566565336U, // GLDFF1H_D_SCALED |
| 6043 | 566565336U, // GLDFF1H_D_SXTW |
| 6044 | 566565336U, // GLDFF1H_D_SXTW_SCALED |
| 6045 | 566565336U, // GLDFF1H_D_UXTW |
| 6046 | 566565336U, // GLDFF1H_D_UXTW_SCALED |
| 6047 | 566630872U, // GLDFF1H_S_IMM |
| 6048 | 566630872U, // GLDFF1H_S_SXTW |
| 6049 | 566630872U, // GLDFF1H_S_SXTW_SCALED |
| 6050 | 566630872U, // GLDFF1H_S_UXTW |
| 6051 | 566630872U, // GLDFF1H_S_UXTW_SCALED |
| 6052 | 566562545U, // GLDFF1SB_D |
| 6053 | 566562545U, // GLDFF1SB_D_IMM |
| 6054 | 566562545U, // GLDFF1SB_D_SXTW |
| 6055 | 566562545U, // GLDFF1SB_D_UXTW |
| 6056 | 566628081U, // GLDFF1SB_S_IMM |
| 6057 | 566628081U, // GLDFF1SB_S_SXTW |
| 6058 | 566628081U, // GLDFF1SB_S_UXTW |
| 6059 | 566569571U, // GLDFF1SH_D |
| 6060 | 566569571U, // GLDFF1SH_D_IMM |
| 6061 | 566569571U, // GLDFF1SH_D_SCALED |
| 6062 | 566569571U, // GLDFF1SH_D_SXTW |
| 6063 | 566569571U, // GLDFF1SH_D_SXTW_SCALED |
| 6064 | 566569571U, // GLDFF1SH_D_UXTW |
| 6065 | 566569571U, // GLDFF1SH_D_UXTW_SCALED |
| 6066 | 566635107U, // GLDFF1SH_S_IMM |
| 6067 | 566635107U, // GLDFF1SH_S_SXTW |
| 6068 | 566635107U, // GLDFF1SH_S_SXTW_SCALED |
| 6069 | 566635107U, // GLDFF1SH_S_UXTW |
| 6070 | 566635107U, // GLDFF1SH_S_UXTW_SCALED |
| 6071 | 566577426U, // GLDFF1SW_D |
| 6072 | 566577426U, // GLDFF1SW_D_IMM |
| 6073 | 566577426U, // GLDFF1SW_D_SCALED |
| 6074 | 566577426U, // GLDFF1SW_D_SXTW |
| 6075 | 566577426U, // GLDFF1SW_D_SXTW_SCALED |
| 6076 | 566577426U, // GLDFF1SW_D_UXTW |
| 6077 | 566577426U, // GLDFF1SW_D_UXTW_SCALED |
| 6078 | 566577258U, // GLDFF1W_D |
| 6079 | 566577258U, // GLDFF1W_D_IMM |
| 6080 | 566577258U, // GLDFF1W_D_SCALED |
| 6081 | 566577258U, // GLDFF1W_D_SXTW |
| 6082 | 566577258U, // GLDFF1W_D_SXTW_SCALED |
| 6083 | 566577258U, // GLDFF1W_D_UXTW |
| 6084 | 566577258U, // GLDFF1W_D_UXTW_SCALED |
| 6085 | 566642794U, // GLDFF1W_IMM |
| 6086 | 566642794U, // GLDFF1W_SXTW |
| 6087 | 566642794U, // GLDFF1W_SXTW_SCALED |
| 6088 | 566642794U, // GLDFF1W_UXTW |
| 6089 | 566642794U, // GLDFF1W_UXTW_SCALED |
| 6090 | 4238118U, // GMI |
| 6091 | 1033699U, // HINT |
| 6092 | 2151794120U, // HISTCNT_ZPzZZ_D |
| 6093 | 2151859656U, // HISTCNT_ZPzZZ_S |
| 6094 | 4266282U, // HISTSEG_ZZZ |
| 6095 | 771396U, // HLT |
| 6096 | 757870U, // HVC |
| 6097 | 1077971947U, // INCB_XPiI |
| 6098 | 1077974938U, // INCD_XPiI |
| 6099 | 1078040474U, // INCD_ZPiI |
| 6100 | 1077979293U, // INCH_XPiI |
| 6101 | 100804765U, // INCH_ZPiI |
| 6102 | 4239401U, // INCP_XP_B |
| 6103 | 541110313U, // INCP_XP_D |
| 6104 | 3762335785U, // INCP_XP_H |
| 6105 | 541110313U, // INCP_XP_S |
| 6106 | 2151788585U, // INCP_ZP_D |
| 6107 | 3305254953U, // INCP_ZP_H |
| 6108 | 2688725033U, // INCP_ZP_S |
| 6109 | 1077987543U, // INCW_XPiI |
| 6110 | 1078118615U, // INCW_ZPiI |
| 6111 | 1078020547U, // INDEX_II_B |
| 6112 | 4311491U, // INDEX_II_D |
| 6113 | 1778534851U, // INDEX_II_H |
| 6114 | 4377027U, // INDEX_II_S |
| 6115 | 1078020547U, // INDEX_IR_B |
| 6116 | 4311491U, // INDEX_IR_D |
| 6117 | 1778534851U, // INDEX_IR_H |
| 6118 | 4377027U, // INDEX_IR_S |
| 6119 | 4278723U, // INDEX_RI_B |
| 6120 | 4311491U, // INDEX_RI_D |
| 6121 | 109201859U, // INDEX_RI_H |
| 6122 | 4377027U, // INDEX_RI_S |
| 6123 | 4278723U, // INDEX_RR_B |
| 6124 | 4311491U, // INDEX_RR_D |
| 6125 | 109201859U, // INDEX_RR_H |
| 6126 | 4377027U, // INDEX_RR_S |
| 6127 | 173015738U, // INSERT_MXIPZ_H_B |
| 6128 | 173015738U, // INSERT_MXIPZ_H_D |
| 6129 | 173015738U, // INSERT_MXIPZ_H_H |
| 6130 | 173015738U, // INSERT_MXIPZ_H_Q |
| 6131 | 173015738U, // INSERT_MXIPZ_H_S |
| 6132 | 173048506U, // INSERT_MXIPZ_V_B |
| 6133 | 173048506U, // INSERT_MXIPZ_V_D |
| 6134 | 173048506U, // INSERT_MXIPZ_V_H |
| 6135 | 173048506U, // INSERT_MXIPZ_V_Q |
| 6136 | 173048506U, // INSERT_MXIPZ_V_S |
| 6137 | 1614885743U, // INSR_ZR_B |
| 6138 | 1614918511U, // INSR_ZR_D |
| 6139 | 3393336175U, // INSR_ZR_H |
| 6140 | 1614984047U, // INSR_ZR_S |
| 6141 | 2151756655U, // INSR_ZV_B |
| 6142 | 2688660335U, // INSR_ZV_D |
| 6143 | 3343004527U, // INSR_ZV_H |
| 6144 | 3225596783U, // INSR_ZV_S |
| 6145 | 700717483U, // INSvi16gpr |
| 6146 | 3921942955U, // INSvi16lane |
| 6147 | 700724301U, // INSvi32gpr |
| 6148 | 3921949773U, // INSvi32lane |
| 6149 | 700715152U, // INSvi64gpr |
| 6150 | 3921940624U, // INSvi64lane |
| 6151 | 700711666U, // INSvi8gpr |
| 6152 | 3921937138U, // INSvi8lane |
| 6153 | 4233523U, // IRG |
| 6154 | 888599U, // ISB |
| 6155 | 2151711404U, // LASTA_RPZ_B |
| 6156 | 2151711404U, // LASTA_RPZ_D |
| 6157 | 2151711404U, // LASTA_RPZ_H |
| 6158 | 2151711404U, // LASTA_RPZ_S |
| 6159 | 2151711404U, // LASTA_VPZ_B |
| 6160 | 2151711404U, // LASTA_VPZ_D |
| 6161 | 2151711404U, // LASTA_VPZ_H |
| 6162 | 2151711404U, // LASTA_VPZ_S |
| 6163 | 2151714688U, // LASTB_RPZ_B |
| 6164 | 2151714688U, // LASTB_RPZ_D |
| 6165 | 2151714688U, // LASTB_RPZ_H |
| 6166 | 2151714688U, // LASTB_RPZ_S |
| 6167 | 2151714688U, // LASTB_VPZ_B |
| 6168 | 2151714688U, // LASTB_VPZ_D |
| 6169 | 2151714688U, // LASTB_VPZ_H |
| 6170 | 2151714688U, // LASTB_VPZ_S |
| 6171 | 566526729U, // LD1B |
| 6172 | 713327369U, // LD1B_2Z |
| 6173 | 713327369U, // LD1B_2Z_IMM |
| 6174 | 5309193U, // LD1B_2Z_STRIDED |
| 6175 | 5309193U, // LD1B_2Z_STRIDED_IMM |
| 6176 | 713327369U, // LD1B_4Z |
| 6177 | 713327369U, // LD1B_4Z_IMM |
| 6178 | 713327369U, // LD1B_4Z_STRIDED |
| 6179 | 713327369U, // LD1B_4Z_STRIDED_IMM |
| 6180 | 566559497U, // LD1B_D |
| 6181 | 566559497U, // LD1B_D_IMM |
| 6182 | 566592265U, // LD1B_H |
| 6183 | 566592265U, // LD1B_H_IMM |
| 6184 | 566526729U, // LD1B_IMM |
| 6185 | 566625033U, // LD1B_S |
| 6186 | 566625033U, // LD1B_S_IMM |
| 6187 | 566563036U, // LD1D |
| 6188 | 713363676U, // LD1D_2Z |
| 6189 | 713363676U, // LD1D_2Z_IMM |
| 6190 | 713363676U, // LD1D_2Z_STRIDED |
| 6191 | 713363676U, // LD1D_2Z_STRIDED_IMM |
| 6192 | 713363676U, // LD1D_4Z |
| 6193 | 713363676U, // LD1D_4Z_IMM |
| 6194 | 713363676U, // LD1D_4Z_STRIDED |
| 6195 | 713363676U, // LD1D_4Z_STRIDED_IMM |
| 6196 | 566563036U, // LD1D_IMM |
| 6197 | 567218396U, // LD1D_Q |
| 6198 | 567218396U, // LD1D_Q_IMM |
| 6199 | 1146890U, // LD1Fourv16b |
| 6200 | 181534730U, // LD1Fourv16b_POST |
| 6201 | 1212426U, // LD1Fourv1d |
| 6202 | 185794570U, // LD1Fourv1d_POST |
| 6203 | 1277962U, // LD1Fourv2d |
| 6204 | 181665802U, // LD1Fourv2d_POST |
| 6205 | 1343498U, // LD1Fourv2s |
| 6206 | 185925642U, // LD1Fourv2s_POST |
| 6207 | 1409034U, // LD1Fourv4h |
| 6208 | 185991178U, // LD1Fourv4h_POST |
| 6209 | 1474570U, // LD1Fourv4s |
| 6210 | 181862410U, // LD1Fourv4s_POST |
| 6211 | 1540106U, // LD1Fourv8b |
| 6212 | 186122250U, // LD1Fourv8b_POST |
| 6213 | 1605642U, // LD1Fourv8h |
| 6214 | 181993482U, // LD1Fourv8h_POST |
| 6215 | 566598098U, // LD1H |
| 6216 | 713398738U, // LD1H_2Z |
| 6217 | 713398738U, // LD1H_2Z_IMM |
| 6218 | 5872082U, // LD1H_2Z_STRIDED |
| 6219 | 5872082U, // LD1H_2Z_STRIDED_IMM |
| 6220 | 713398738U, // LD1H_4Z |
| 6221 | 713398738U, // LD1H_4Z_IMM |
| 6222 | 713398738U, // LD1H_4Z_STRIDED |
| 6223 | 713398738U, // LD1H_4Z_STRIDED_IMM |
| 6224 | 566565330U, // LD1H_D |
| 6225 | 566565330U, // LD1H_D_IMM |
| 6226 | 566598098U, // LD1H_IMM |
| 6227 | 566630866U, // LD1H_S |
| 6228 | 566630866U, // LD1H_S_IMM |
| 6229 | 1146890U, // LD1Onev16b |
| 6230 | 189923338U, // LD1Onev16b_POST |
| 6231 | 1212426U, // LD1Onev1d |
| 6232 | 194183178U, // LD1Onev1d_POST |
| 6233 | 1277962U, // LD1Onev2d |
| 6234 | 190054410U, // LD1Onev2d_POST |
| 6235 | 1343498U, // LD1Onev2s |
| 6236 | 194314250U, // LD1Onev2s_POST |
| 6237 | 1409034U, // LD1Onev4h |
| 6238 | 194379786U, // LD1Onev4h_POST |
| 6239 | 1474570U, // LD1Onev4s |
| 6240 | 190251018U, // LD1Onev4s_POST |
| 6241 | 1540106U, // LD1Onev8b |
| 6242 | 194510858U, // LD1Onev8b_POST |
| 6243 | 1605642U, // LD1Onev8h |
| 6244 | 190382090U, // LD1Onev8h_POST |
| 6245 | 566562390U, // LD1RB_D_IMM |
| 6246 | 566595158U, // LD1RB_H_IMM |
| 6247 | 566529622U, // LD1RB_IMM |
| 6248 | 566627926U, // LD1RB_S_IMM |
| 6249 | 566564894U, // LD1RD_IMM |
| 6250 | 566569416U, // LD1RH_D_IMM |
| 6251 | 566602184U, // LD1RH_IMM |
| 6252 | 566634952U, // LD1RH_S_IMM |
| 6253 | 566529593U, // LD1RO_B |
| 6254 | 566529593U, // LD1RO_B_IMM |
| 6255 | 566564878U, // LD1RO_D |
| 6256 | 566564878U, // LD1RO_D_IMM |
| 6257 | 566602162U, // LD1RO_H |
| 6258 | 566602162U, // LD1RO_H_IMM |
| 6259 | 566642923U, // LD1RO_W |
| 6260 | 566642923U, // LD1RO_W_IMM |
| 6261 | 566529614U, // LD1RQ_B |
| 6262 | 566529614U, // LD1RQ_B_IMM |
| 6263 | 566564886U, // LD1RQ_D |
| 6264 | 566564886U, // LD1RQ_D_IMM |
| 6265 | 566602176U, // LD1RQ_H |
| 6266 | 566602176U, // LD1RQ_H_IMM |
| 6267 | 566642931U, // LD1RQ_W |
| 6268 | 566642931U, // LD1RQ_W_IMM |
| 6269 | 566562601U, // LD1RSB_D_IMM |
| 6270 | 566595369U, // LD1RSB_H_IMM |
| 6271 | 566628137U, // LD1RSB_S_IMM |
| 6272 | 566569614U, // LD1RSH_D_IMM |
| 6273 | 566635150U, // LD1RSH_S_IMM |
| 6274 | 566577460U, // LD1RSW_IMM |
| 6275 | 566577403U, // LD1RW_D_IMM |
| 6276 | 566642939U, // LD1RW_IMM |
| 6277 | 1159692U, // LD1Rv16b |
| 6278 | 198324748U, // LD1Rv16b_POST |
| 6279 | 1225228U, // LD1Rv1d |
| 6280 | 194195980U, // LD1Rv1d_POST |
| 6281 | 1290764U, // LD1Rv2d |
| 6282 | 194261516U, // LD1Rv2d_POST |
| 6283 | 1356300U, // LD1Rv2s |
| 6284 | 202715660U, // LD1Rv2s_POST |
| 6285 | 1421836U, // LD1Rv4h |
| 6286 | 206975500U, // LD1Rv4h_POST |
| 6287 | 1487372U, // LD1Rv4s |
| 6288 | 202846732U, // LD1Rv4s_POST |
| 6289 | 1552908U, // LD1Rv8b |
| 6290 | 198717964U, // LD1Rv8b_POST |
| 6291 | 1618444U, // LD1Rv8h |
| 6292 | 207172108U, // LD1Rv8h_POST |
| 6293 | 566562538U, // LD1SB_D |
| 6294 | 566562538U, // LD1SB_D_IMM |
| 6295 | 566595306U, // LD1SB_H |
| 6296 | 566595306U, // LD1SB_H_IMM |
| 6297 | 566628074U, // LD1SB_S |
| 6298 | 566628074U, // LD1SB_S_IMM |
| 6299 | 566569564U, // LD1SH_D |
| 6300 | 566569564U, // LD1SH_D_IMM |
| 6301 | 566635100U, // LD1SH_S |
| 6302 | 566635100U, // LD1SH_S_IMM |
| 6303 | 566577419U, // LD1SW_D |
| 6304 | 566577419U, // LD1SW_D_IMM |
| 6305 | 1146890U, // LD1Threev16b |
| 6306 | 210894858U, // LD1Threev16b_POST |
| 6307 | 1212426U, // LD1Threev1d |
| 6308 | 215154698U, // LD1Threev1d_POST |
| 6309 | 1277962U, // LD1Threev2d |
| 6310 | 211025930U, // LD1Threev2d_POST |
| 6311 | 1343498U, // LD1Threev2s |
| 6312 | 215285770U, // LD1Threev2s_POST |
| 6313 | 1409034U, // LD1Threev4h |
| 6314 | 215351306U, // LD1Threev4h_POST |
| 6315 | 1474570U, // LD1Threev4s |
| 6316 | 211222538U, // LD1Threev4s_POST |
| 6317 | 1540106U, // LD1Threev8b |
| 6318 | 215482378U, // LD1Threev8b_POST |
| 6319 | 1605642U, // LD1Threev8h |
| 6320 | 211353610U, // LD1Threev8h_POST |
| 6321 | 1146890U, // LD1Twov16b |
| 6322 | 185729034U, // LD1Twov16b_POST |
| 6323 | 1212426U, // LD1Twov1d |
| 6324 | 189988874U, // LD1Twov1d_POST |
| 6325 | 1277962U, // LD1Twov2d |
| 6326 | 185860106U, // LD1Twov2d_POST |
| 6327 | 1343498U, // LD1Twov2s |
| 6328 | 190119946U, // LD1Twov2s_POST |
| 6329 | 1409034U, // LD1Twov4h |
| 6330 | 190185482U, // LD1Twov4h_POST |
| 6331 | 1474570U, // LD1Twov4s |
| 6332 | 186056714U, // LD1Twov4s_POST |
| 6333 | 1540106U, // LD1Twov8b |
| 6334 | 190316554U, // LD1Twov8b_POST |
| 6335 | 1605642U, // LD1Twov8h |
| 6336 | 186187786U, // LD1Twov8h_POST |
| 6337 | 566642788U, // LD1W |
| 6338 | 713443428U, // LD1W_2Z |
| 6339 | 713443428U, // LD1W_2Z_IMM |
| 6340 | 713443428U, // LD1W_2Z_STRIDED |
| 6341 | 713443428U, // LD1W_2Z_STRIDED_IMM |
| 6342 | 713443428U, // LD1W_4Z |
| 6343 | 713443428U, // LD1W_4Z_IMM |
| 6344 | 713443428U, // LD1W_4Z_STRIDED |
| 6345 | 713443428U, // LD1W_4Z_STRIDED_IMM |
| 6346 | 566577252U, // LD1W_D |
| 6347 | 566577252U, // LD1W_D_IMM |
| 6348 | 566642788U, // LD1W_IMM |
| 6349 | 567232612U, // LD1W_Q |
| 6350 | 567232612U, // LD1W_Q_IMM |
| 6351 | 110121478U, // LD1_MXIPXX_H_B |
| 6352 | 110121492U, // LD1_MXIPXX_H_D |
| 6353 | 110121506U, // LD1_MXIPXX_H_H |
| 6354 | 110121520U, // LD1_MXIPXX_H_Q |
| 6355 | 110121534U, // LD1_MXIPXX_H_S |
| 6356 | 110154246U, // LD1_MXIPXX_V_B |
| 6357 | 110154260U, // LD1_MXIPXX_V_D |
| 6358 | 110154274U, // LD1_MXIPXX_V_H |
| 6359 | 110154288U, // LD1_MXIPXX_V_Q |
| 6360 | 110154302U, // LD1_MXIPXX_V_S |
| 6361 | 219807754U, // LD1i16 |
| 6362 | 224034826U, // LD1i16_POST |
| 6363 | 219873290U, // LD1i32 |
| 6364 | 228294666U, // LD1i32_POST |
| 6365 | 219938826U, // LD1i64 |
| 6366 | 232554506U, // LD1i64_POST |
| 6367 | 220004362U, // LD1i8 |
| 6368 | 236814346U, // LD1i8_POST |
| 6369 | 566526781U, // LD2B |
| 6370 | 566526781U, // LD2B_IMM |
| 6371 | 566564663U, // LD2D |
| 6372 | 566564663U, // LD2D_IMM |
| 6373 | 566598204U, // LD2H |
| 6374 | 566598204U, // LD2H_IMM |
| 6375 | 567226809U, // LD2Q |
| 6376 | 567226809U, // LD2Q_IMM |
| 6377 | 1159698U, // LD2Rv16b |
| 6378 | 206713362U, // LD2Rv16b_POST |
| 6379 | 1225234U, // LD2Rv1d |
| 6380 | 190001682U, // LD2Rv1d_POST |
| 6381 | 1290770U, // LD2Rv2d |
| 6382 | 190067218U, // LD2Rv2d_POST |
| 6383 | 1356306U, // LD2Rv2s |
| 6384 | 194327058U, // LD2Rv2s_POST |
| 6385 | 1421842U, // LD2Rv4h |
| 6386 | 202781202U, // LD2Rv4h_POST |
| 6387 | 1487378U, // LD2Rv4s |
| 6388 | 194458130U, // LD2Rv4s_POST |
| 6389 | 1552914U, // LD2Rv8b |
| 6390 | 207106578U, // LD2Rv8b_POST |
| 6391 | 1618450U, // LD2Rv8h |
| 6392 | 202977810U, // LD2Rv8h_POST |
| 6393 | 1146973U, // LD2Twov16b |
| 6394 | 185729117U, // LD2Twov16b_POST |
| 6395 | 1278045U, // LD2Twov2d |
| 6396 | 185860189U, // LD2Twov2d_POST |
| 6397 | 1343581U, // LD2Twov2s |
| 6398 | 190120029U, // LD2Twov2s_POST |
| 6399 | 1409117U, // LD2Twov4h |
| 6400 | 190185565U, // LD2Twov4h_POST |
| 6401 | 1474653U, // LD2Twov4s |
| 6402 | 186056797U, // LD2Twov4s_POST |
| 6403 | 1540189U, // LD2Twov8b |
| 6404 | 190316637U, // LD2Twov8b_POST |
| 6405 | 1605725U, // LD2Twov8h |
| 6406 | 186187869U, // LD2Twov8h_POST |
| 6407 | 566642840U, // LD2W |
| 6408 | 566642840U, // LD2W_IMM |
| 6409 | 219807837U, // LD2i16 |
| 6410 | 228229213U, // LD2i16_POST |
| 6411 | 219873373U, // LD2i32 |
| 6412 | 232489053U, // LD2i32_POST |
| 6413 | 219938909U, // LD2i64 |
| 6414 | 240943197U, // LD2i64_POST |
| 6415 | 220004445U, // LD2i8 |
| 6416 | 224231517U, // LD2i8_POST |
| 6417 | 566526793U, // LD3B |
| 6418 | 566526793U, // LD3B_IMM |
| 6419 | 566564675U, // LD3D |
| 6420 | 566564675U, // LD3D_IMM |
| 6421 | 566598216U, // LD3H |
| 6422 | 566598216U, // LD3H_IMM |
| 6423 | 567226821U, // LD3Q |
| 6424 | 567226821U, // LD3Q_IMM |
| 6425 | 1159704U, // LD3Rv16b |
| 6426 | 244462104U, // LD3Rv16b_POST |
| 6427 | 1225240U, // LD3Rv1d |
| 6428 | 215167512U, // LD3Rv1d_POST |
| 6429 | 1290776U, // LD3Rv2d |
| 6430 | 215233048U, // LD3Rv2d_POST |
| 6431 | 1356312U, // LD3Rv2s |
| 6432 | 248853016U, // LD3Rv2s_POST |
| 6433 | 1421848U, // LD3Rv4h |
| 6434 | 253112856U, // LD3Rv4h_POST |
| 6435 | 1487384U, // LD3Rv4s |
| 6436 | 248984088U, // LD3Rv4s_POST |
| 6437 | 1552920U, // LD3Rv8b |
| 6438 | 244855320U, // LD3Rv8b_POST |
| 6439 | 1618456U, // LD3Rv8h |
| 6440 | 253309464U, // LD3Rv8h_POST |
| 6441 | 1147078U, // LD3Threev16b |
| 6442 | 210895046U, // LD3Threev16b_POST |
| 6443 | 1278150U, // LD3Threev2d |
| 6444 | 211026118U, // LD3Threev2d_POST |
| 6445 | 1343686U, // LD3Threev2s |
| 6446 | 215285958U, // LD3Threev2s_POST |
| 6447 | 1409222U, // LD3Threev4h |
| 6448 | 215351494U, // LD3Threev4h_POST |
| 6449 | 1474758U, // LD3Threev4s |
| 6450 | 211222726U, // LD3Threev4s_POST |
| 6451 | 1540294U, // LD3Threev8b |
| 6452 | 215482566U, // LD3Threev8b_POST |
| 6453 | 1605830U, // LD3Threev8h |
| 6454 | 211353798U, // LD3Threev8h_POST |
| 6455 | 566642852U, // LD3W |
| 6456 | 566642852U, // LD3W_IMM |
| 6457 | 219807942U, // LD3i16 |
| 6458 | 257589446U, // LD3i16_POST |
| 6459 | 219873478U, // LD3i32 |
| 6460 | 261849286U, // LD3i32_POST |
| 6461 | 219939014U, // LD3i64 |
| 6462 | 266109126U, // LD3i64_POST |
| 6463 | 220004550U, // LD3i8 |
| 6464 | 270368966U, // LD3i8_POST |
| 6465 | 566526819U, // LD4B |
| 6466 | 566526819U, // LD4B_IMM |
| 6467 | 566564687U, // LD4D |
| 6468 | 566564687U, // LD4D_IMM |
| 6469 | 1147101U, // LD4Fourv16b |
| 6470 | 181534941U, // LD4Fourv16b_POST |
| 6471 | 1278173U, // LD4Fourv2d |
| 6472 | 181666013U, // LD4Fourv2d_POST |
| 6473 | 1343709U, // LD4Fourv2s |
| 6474 | 185925853U, // LD4Fourv2s_POST |
| 6475 | 1409245U, // LD4Fourv4h |
| 6476 | 185991389U, // LD4Fourv4h_POST |
| 6477 | 1474781U, // LD4Fourv4s |
| 6478 | 181862621U, // LD4Fourv4s_POST |
| 6479 | 1540317U, // LD4Fourv8b |
| 6480 | 186122461U, // LD4Fourv8b_POST |
| 6481 | 1605853U, // LD4Fourv8h |
| 6482 | 181993693U, // LD4Fourv8h_POST |
| 6483 | 566599730U, // LD4H |
| 6484 | 566599730U, // LD4H_IMM |
| 6485 | 567226833U, // LD4Q |
| 6486 | 567226833U, // LD4Q_IMM |
| 6487 | 1159710U, // LD4Rv16b |
| 6488 | 202519070U, // LD4Rv16b_POST |
| 6489 | 1225246U, // LD4Rv1d |
| 6490 | 185807390U, // LD4Rv1d_POST |
| 6491 | 1290782U, // LD4Rv2d |
| 6492 | 185872926U, // LD4Rv2d_POST |
| 6493 | 1356318U, // LD4Rv2s |
| 6494 | 190132766U, // LD4Rv2s_POST |
| 6495 | 1421854U, // LD4Rv4h |
| 6496 | 194392606U, // LD4Rv4h_POST |
| 6497 | 1487390U, // LD4Rv4s |
| 6498 | 190263838U, // LD4Rv4s_POST |
| 6499 | 1552926U, // LD4Rv8b |
| 6500 | 202912286U, // LD4Rv8b_POST |
| 6501 | 1618462U, // LD4Rv8h |
| 6502 | 194589214U, // LD4Rv8h_POST |
| 6503 | 566642864U, // LD4W |
| 6504 | 566642864U, // LD4W_IMM |
| 6505 | 219807965U, // LD4i16 |
| 6506 | 232423645U, // LD4i16_POST |
| 6507 | 219873501U, // LD4i32 |
| 6508 | 240877789U, // LD4i32_POST |
| 6509 | 219939037U, // LD4i64 |
| 6510 | 274497757U, // LD4i64_POST |
| 6511 | 220004573U, // LD4i8 |
| 6512 | 228425949U, // LD4i8_POST |
| 6513 | 1966933U, // LD64B |
| 6514 | 541690712U, // LDADDAB |
| 6515 | 541698067U, // LDADDAH |
| 6516 | 541690944U, // LDADDALB |
| 6517 | 541698241U, // LDADDALH |
| 6518 | 541698903U, // LDADDALW |
| 6519 | 541698903U, // LDADDALX |
| 6520 | 541688092U, // LDADDAW |
| 6521 | 541688092U, // LDADDAX |
| 6522 | 541690880U, // LDADDB |
| 6523 | 541698227U, // LDADDH |
| 6524 | 541691125U, // LDADDLB |
| 6525 | 541698341U, // LDADDLH |
| 6526 | 541699227U, // LDADDLW |
| 6527 | 541699227U, // LDADDLX |
| 6528 | 541693879U, // LDADDW |
| 6529 | 541693879U, // LDADDX |
| 6530 | 219938843U, // LDAP1 |
| 6531 | 75533969U, // LDAPRB |
| 6532 | 75540995U, // LDAPRH |
| 6533 | 75543362U, // LDAPRW |
| 6534 | 1686745922U, // LDAPRWpost |
| 6535 | 75543362U, // LDAPRX |
| 6536 | 1686745922U, // LDAPRXpost |
| 6537 | 75534012U, // LDAPURBi |
| 6538 | 75541038U, // LDAPURHi |
| 6539 | 75534152U, // LDAPURSBWi |
| 6540 | 75534152U, // LDAPURSBXi |
| 6541 | 75541165U, // LDAPURSHWi |
| 6542 | 75541165U, // LDAPURSHXi |
| 6543 | 75549011U, // LDAPURSWi |
| 6544 | 75543455U, // LDAPURXi |
| 6545 | 75543455U, // LDAPURbi |
| 6546 | 75543455U, // LDAPURdi |
| 6547 | 75543455U, // LDAPURhi |
| 6548 | 75543455U, // LDAPURi |
| 6549 | 75543455U, // LDAPURqi |
| 6550 | 75543455U, // LDAPURsi |
| 6551 | 75533917U, // LDARB |
| 6552 | 75540943U, // LDARH |
| 6553 | 75543076U, // LDARW |
| 6554 | 75543076U, // LDARX |
| 6555 | 4239716U, // LDAXPW |
| 6556 | 4239716U, // LDAXPX |
| 6557 | 75534028U, // LDAXRB |
| 6558 | 75541054U, // LDAXRH |
| 6559 | 75543499U, // LDAXRW |
| 6560 | 75543499U, // LDAXRX |
| 6561 | 541690768U, // LDCLRAB |
| 6562 | 541698124U, // LDCLRAH |
| 6563 | 541691019U, // LDCLRALB |
| 6564 | 541698281U, // LDCLRALH |
| 6565 | 541699096U, // LDCLRALW |
| 6566 | 541699096U, // LDCLRALX |
| 6567 | 541688376U, // LDCLRAW |
| 6568 | 541688376U, // LDCLRAX |
| 6569 | 541691506U, // LDCLRB |
| 6570 | 541698532U, // LDCLRH |
| 6571 | 541691227U, // LDCLRLB |
| 6572 | 541698377U, // LDCLRLH |
| 6573 | 541699542U, // LDCLRLW |
| 6574 | 541699542U, // LDCLRLX |
| 6575 | 543076587U, // LDCLRP |
| 6576 | 543064525U, // LDCLRPA |
| 6577 | 543075242U, // LDCLRPAL |
| 6578 | 543075690U, // LDCLRPL |
| 6579 | 541700820U, // LDCLRW |
| 6580 | 541700820U, // LDCLRX |
| 6581 | 541690777U, // LDEORAB |
| 6582 | 541698133U, // LDEORAH |
| 6583 | 541691029U, // LDEORALB |
| 6584 | 541698291U, // LDEORALH |
| 6585 | 541699126U, // LDEORALW |
| 6586 | 541699126U, // LDEORALX |
| 6587 | 541688403U, // LDEORAW |
| 6588 | 541688403U, // LDEORAX |
| 6589 | 541691529U, // LDEORB |
| 6590 | 541698555U, // LDEORH |
| 6591 | 541691236U, // LDEORLB |
| 6592 | 541698386U, // LDEORLH |
| 6593 | 541699569U, // LDEORLW |
| 6594 | 541699569U, // LDEORLX |
| 6595 | 541700913U, // LDEORW |
| 6596 | 541700913U, // LDEORX |
| 6597 | 566526735U, // LDFF1B |
| 6598 | 566559503U, // LDFF1B_D |
| 6599 | 566592271U, // LDFF1B_H |
| 6600 | 566625039U, // LDFF1B_S |
| 6601 | 566563042U, // LDFF1D |
| 6602 | 566598104U, // LDFF1H |
| 6603 | 566565336U, // LDFF1H_D |
| 6604 | 566630872U, // LDFF1H_S |
| 6605 | 566562545U, // LDFF1SB_D |
| 6606 | 566595313U, // LDFF1SB_H |
| 6607 | 566628081U, // LDFF1SB_S |
| 6608 | 566569571U, // LDFF1SH_D |
| 6609 | 566635107U, // LDFF1SH_S |
| 6610 | 566577426U, // LDFF1SW_D |
| 6611 | 566642794U, // LDFF1W |
| 6612 | 566577258U, // LDFF1W_D |
| 6613 | 1686739217U, // LDG |
| 6614 | 75542216U, // LDGM |
| 6615 | 4239556U, // LDIAPPW |
| 6616 | 1615442116U, // LDIAPPWpost |
| 6617 | 4239556U, // LDIAPPX |
| 6618 | 1615442116U, // LDIAPPXpost |
| 6619 | 75533924U, // LDLARB |
| 6620 | 75540950U, // LDLARH |
| 6621 | 75543082U, // LDLARW |
| 6622 | 75543082U, // LDLARX |
| 6623 | 566559511U, // LDNF1B_D_IMM |
| 6624 | 566592279U, // LDNF1B_H_IMM |
| 6625 | 566526743U, // LDNF1B_IMM |
| 6626 | 566625047U, // LDNF1B_S_IMM |
| 6627 | 566563050U, // LDNF1D_IMM |
| 6628 | 566565344U, // LDNF1H_D_IMM |
| 6629 | 566598112U, // LDNF1H_IMM |
| 6630 | 566630880U, // LDNF1H_S_IMM |
| 6631 | 566562554U, // LDNF1SB_D_IMM |
| 6632 | 566595322U, // LDNF1SB_H_IMM |
| 6633 | 566628090U, // LDNF1SB_S_IMM |
| 6634 | 566569580U, // LDNF1SH_D_IMM |
| 6635 | 566635116U, // LDNF1SH_S_IMM |
| 6636 | 566577435U, // LDNF1SW_D_IMM |
| 6637 | 566577266U, // LDNF1W_D_IMM |
| 6638 | 566642802U, // LDNF1W_IMM |
| 6639 | 4239523U, // LDNPDi |
| 6640 | 4239523U, // LDNPQi |
| 6641 | 4239523U, // LDNPSi |
| 6642 | 4239523U, // LDNPWi |
| 6643 | 4239523U, // LDNPXi |
| 6644 | 713327391U, // LDNT1B_2Z |
| 6645 | 713327391U, // LDNT1B_2Z_IMM |
| 6646 | 5309215U, // LDNT1B_2Z_STRIDED |
| 6647 | 5309215U, // LDNT1B_2Z_STRIDED_IMM |
| 6648 | 713327391U, // LDNT1B_4Z |
| 6649 | 713327391U, // LDNT1B_4Z_IMM |
| 6650 | 713327391U, // LDNT1B_4Z_STRIDED |
| 6651 | 713327391U, // LDNT1B_4Z_STRIDED_IMM |
| 6652 | 566526751U, // LDNT1B_ZRI |
| 6653 | 566526751U, // LDNT1B_ZRR |
| 6654 | 566559519U, // LDNT1B_ZZR_D |
| 6655 | 566625055U, // LDNT1B_ZZR_S |
| 6656 | 713363698U, // LDNT1D_2Z |
| 6657 | 713363698U, // LDNT1D_2Z_IMM |
| 6658 | 713363698U, // LDNT1D_2Z_STRIDED |
| 6659 | 713363698U, // LDNT1D_2Z_STRIDED_IMM |
| 6660 | 713363698U, // LDNT1D_4Z |
| 6661 | 713363698U, // LDNT1D_4Z_IMM |
| 6662 | 713363698U, // LDNT1D_4Z_STRIDED |
| 6663 | 713363698U, // LDNT1D_4Z_STRIDED_IMM |
| 6664 | 566563058U, // LDNT1D_ZRI |
| 6665 | 566563058U, // LDNT1D_ZRR |
| 6666 | 566563058U, // LDNT1D_ZZR_D |
| 6667 | 713398760U, // LDNT1H_2Z |
| 6668 | 713398760U, // LDNT1H_2Z_IMM |
| 6669 | 5872104U, // LDNT1H_2Z_STRIDED |
| 6670 | 5872104U, // LDNT1H_2Z_STRIDED_IMM |
| 6671 | 713398760U, // LDNT1H_4Z |
| 6672 | 713398760U, // LDNT1H_4Z_IMM |
| 6673 | 713398760U, // LDNT1H_4Z_STRIDED |
| 6674 | 713398760U, // LDNT1H_4Z_STRIDED_IMM |
| 6675 | 566598120U, // LDNT1H_ZRI |
| 6676 | 566598120U, // LDNT1H_ZRR |
| 6677 | 566565352U, // LDNT1H_ZZR_D |
| 6678 | 566630888U, // LDNT1H_ZZR_S |
| 6679 | 566562563U, // LDNT1SB_ZZR_D |
| 6680 | 566628099U, // LDNT1SB_ZZR_S |
| 6681 | 566569589U, // LDNT1SH_ZZR_D |
| 6682 | 566635125U, // LDNT1SH_ZZR_S |
| 6683 | 566577444U, // LDNT1SW_ZZR_D |
| 6684 | 713443450U, // LDNT1W_2Z |
| 6685 | 713443450U, // LDNT1W_2Z_IMM |
| 6686 | 713443450U, // LDNT1W_2Z_STRIDED |
| 6687 | 713443450U, // LDNT1W_2Z_STRIDED_IMM |
| 6688 | 713443450U, // LDNT1W_4Z |
| 6689 | 713443450U, // LDNT1W_4Z_IMM |
| 6690 | 713443450U, // LDNT1W_4Z_STRIDED |
| 6691 | 713443450U, // LDNT1W_4Z_STRIDED_IMM |
| 6692 | 566642810U, // LDNT1W_ZRI |
| 6693 | 566642810U, // LDNT1W_ZRR |
| 6694 | 566577274U, // LDNT1W_ZZR_D |
| 6695 | 566642810U, // LDNT1W_ZZR_S |
| 6696 | 4239422U, // LDPDi |
| 6697 | 1615441982U, // LDPDpost |
| 6698 | 1615441982U, // LDPDpre |
| 6699 | 4239422U, // LDPQi |
| 6700 | 1615441982U, // LDPQpost |
| 6701 | 1615441982U, // LDPQpre |
| 6702 | 4245805U, // LDPSWi |
| 6703 | 1615448365U, // LDPSWpost |
| 6704 | 1615448365U, // LDPSWpre |
| 6705 | 4239422U, // LDPSi |
| 6706 | 1615441982U, // LDPSpost |
| 6707 | 1615441982U, // LDPSpre |
| 6708 | 4239422U, // LDPWi |
| 6709 | 1615441982U, // LDPWpost |
| 6710 | 1615441982U, // LDPWpre |
| 6711 | 4239422U, // LDPXi |
| 6712 | 1615441982U, // LDPXpost |
| 6713 | 1615441982U, // LDPXpre |
| 6714 | 75530491U, // LDRAAindexed |
| 6715 | 1686733051U, // LDRAAwriteback |
| 6716 | 75533186U, // LDRABindexed |
| 6717 | 1686735746U, // LDRABwriteback |
| 6718 | 1686736492U, // LDRBBpost |
| 6719 | 1686736492U, // LDRBBpre |
| 6720 | 75533932U, // LDRBBroW |
| 6721 | 75533932U, // LDRBBroX |
| 6722 | 75533932U, // LDRBBui |
| 6723 | 1686745746U, // LDRBpost |
| 6724 | 1686745746U, // LDRBpre |
| 6725 | 75543186U, // LDRBroW |
| 6726 | 75543186U, // LDRBroX |
| 6727 | 75543186U, // LDRBui |
| 6728 | 4240018U, // LDRDl |
| 6729 | 1686745746U, // LDRDpost |
| 6730 | 1686745746U, // LDRDpre |
| 6731 | 75543186U, // LDRDroW |
| 6732 | 75543186U, // LDRDroX |
| 6733 | 75543186U, // LDRDui |
| 6734 | 1686743518U, // LDRHHpost |
| 6735 | 1686743518U, // LDRHHpre |
| 6736 | 75540958U, // LDRHHroW |
| 6737 | 75540958U, // LDRHHroX |
| 6738 | 75540958U, // LDRHHui |
| 6739 | 1686745746U, // LDRHpost |
| 6740 | 1686745746U, // LDRHpre |
| 6741 | 75543186U, // LDRHroW |
| 6742 | 75543186U, // LDRHroX |
| 6743 | 75543186U, // LDRHui |
| 6744 | 4240018U, // LDRQl |
| 6745 | 1686745746U, // LDRQpost |
| 6746 | 1686745746U, // LDRQpre |
| 6747 | 75543186U, // LDRQroW |
| 6748 | 75543186U, // LDRQroX |
| 6749 | 75543186U, // LDRQui |
| 6750 | 1686736689U, // LDRSBWpost |
| 6751 | 1686736689U, // LDRSBWpre |
| 6752 | 75534129U, // LDRSBWroW |
| 6753 | 75534129U, // LDRSBWroX |
| 6754 | 75534129U, // LDRSBWui |
| 6755 | 1686736689U, // LDRSBXpost |
| 6756 | 1686736689U, // LDRSBXpre |
| 6757 | 75534129U, // LDRSBXroW |
| 6758 | 75534129U, // LDRSBXroX |
| 6759 | 75534129U, // LDRSBXui |
| 6760 | 1686743702U, // LDRSHWpost |
| 6761 | 1686743702U, // LDRSHWpre |
| 6762 | 75541142U, // LDRSHWroW |
| 6763 | 75541142U, // LDRSHWroX |
| 6764 | 75541142U, // LDRSHWui |
| 6765 | 1686743702U, // LDRSHXpost |
| 6766 | 1686743702U, // LDRSHXpre |
| 6767 | 75541142U, // LDRSHXroW |
| 6768 | 75541142U, // LDRSHXroX |
| 6769 | 75541142U, // LDRSHXui |
| 6770 | 4245820U, // LDRSWl |
| 6771 | 1686751548U, // LDRSWpost |
| 6772 | 1686751548U, // LDRSWpre |
| 6773 | 75548988U, // LDRSWroW |
| 6774 | 75548988U, // LDRSWroX |
| 6775 | 75548988U, // LDRSWui |
| 6776 | 4240018U, // LDRSl |
| 6777 | 1686745746U, // LDRSpost |
| 6778 | 1686745746U, // LDRSpre |
| 6779 | 75543186U, // LDRSroW |
| 6780 | 75543186U, // LDRSroX |
| 6781 | 75543186U, // LDRSui |
| 6782 | 4240018U, // LDRWl |
| 6783 | 1686745746U, // LDRWpost |
| 6784 | 1686745746U, // LDRWpre |
| 6785 | 75543186U, // LDRWroW |
| 6786 | 75543186U, // LDRWroX |
| 6787 | 75543186U, // LDRWui |
| 6788 | 4240018U, // LDRXl |
| 6789 | 1686745746U, // LDRXpost |
| 6790 | 1686745746U, // LDRXpre |
| 6791 | 75543186U, // LDRXroW |
| 6792 | 75543186U, // LDRXroX |
| 6793 | 75543186U, // LDRXui |
| 6794 | 77542034U, // LDR_PXI |
| 6795 | 75543186U, // LDR_TX |
| 6796 | 2077330U, // LDR_ZA |
| 6797 | 77542034U, // LDR_ZXI |
| 6798 | 541690793U, // LDSETAB |
| 6799 | 541698149U, // LDSETAH |
| 6800 | 541691047U, // LDSETALB |
| 6801 | 541698309U, // LDSETALH |
| 6802 | 541699156U, // LDSETALW |
| 6803 | 541699156U, // LDSETALX |
| 6804 | 541688456U, // LDSETAW |
| 6805 | 541688456U, // LDSETAX |
| 6806 | 541691735U, // LDSETB |
| 6807 | 541698743U, // LDSETH |
| 6808 | 541691287U, // LDSETLB |
| 6809 | 541698402U, // LDSETLH |
| 6810 | 541699639U, // LDSETLW |
| 6811 | 541699639U, // LDSETLX |
| 6812 | 543076639U, // LDSETP |
| 6813 | 543064576U, // LDSETPA |
| 6814 | 543075298U, // LDSETPAL |
| 6815 | 543075749U, // LDSETPL |
| 6816 | 541705345U, // LDSETW |
| 6817 | 541705345U, // LDSETX |
| 6818 | 541690802U, // LDSMAXAB |
| 6819 | 541698158U, // LDSMAXAH |
| 6820 | 541691057U, // LDSMAXALB |
| 6821 | 541698319U, // LDSMAXALH |
| 6822 | 541699186U, // LDSMAXALW |
| 6823 | 541699186U, // LDSMAXALX |
| 6824 | 541688512U, // LDSMAXAW |
| 6825 | 541688512U, // LDSMAXAX |
| 6826 | 541691883U, // LDSMAXB |
| 6827 | 541698775U, // LDSMAXH |
| 6828 | 541691296U, // LDSMAXLB |
| 6829 | 541698444U, // LDSMAXLH |
| 6830 | 541699747U, // LDSMAXLW |
| 6831 | 541699747U, // LDSMAXLX |
| 6832 | 541706661U, // LDSMAXW |
| 6833 | 541706661U, // LDSMAXX |
| 6834 | 541690721U, // LDSMINAB |
| 6835 | 541698097U, // LDSMINAH |
| 6836 | 541690989U, // LDSMINALB |
| 6837 | 541698251U, // LDSMINALH |
| 6838 | 541698943U, // LDSMINALW |
| 6839 | 541698943U, // LDSMINALX |
| 6840 | 541688192U, // LDSMINAW |
| 6841 | 541688192U, // LDSMINAX |
| 6842 | 541691339U, // LDSMINB |
| 6843 | 541698464U, // LDSMINH |
| 6844 | 541691200U, // LDSMINLB |
| 6845 | 541698350U, // LDSMINLH |
| 6846 | 541699388U, // LDSMINLW |
| 6847 | 541699388U, // LDSMINLX |
| 6848 | 541699889U, // LDSMINW |
| 6849 | 541699889U, // LDSMINX |
| 6850 | 75533977U, // LDTRBi |
| 6851 | 75541003U, // LDTRHi |
| 6852 | 75534136U, // LDTRSBWi |
| 6853 | 75534136U, // LDTRSBXi |
| 6854 | 75541149U, // LDTRSHWi |
| 6855 | 75541149U, // LDTRSHXi |
| 6856 | 75548995U, // LDTRSWi |
| 6857 | 75543413U, // LDTRWi |
| 6858 | 75543413U, // LDTRXi |
| 6859 | 541690812U, // LDUMAXAB |
| 6860 | 541698168U, // LDUMAXAH |
| 6861 | 541691068U, // LDUMAXALB |
| 6862 | 541698330U, // LDUMAXALH |
| 6863 | 541699196U, // LDUMAXALW |
| 6864 | 541699196U, // LDUMAXALX |
| 6865 | 541688521U, // LDUMAXAW |
| 6866 | 541688521U, // LDUMAXAX |
| 6867 | 541691892U, // LDUMAXB |
| 6868 | 541698784U, // LDUMAXH |
| 6869 | 541691306U, // LDUMAXLB |
| 6870 | 541698454U, // LDUMAXLH |
| 6871 | 541699756U, // LDUMAXLW |
| 6872 | 541699756U, // LDUMAXLX |
| 6873 | 541706669U, // LDUMAXW |
| 6874 | 541706669U, // LDUMAXX |
| 6875 | 541690731U, // LDUMINAB |
| 6876 | 541698107U, // LDUMINAH |
| 6877 | 541691000U, // LDUMINALB |
| 6878 | 541698262U, // LDUMINALH |
| 6879 | 541698953U, // LDUMINALW |
| 6880 | 541698953U, // LDUMINALX |
| 6881 | 541688201U, // LDUMINAW |
| 6882 | 541688201U, // LDUMINAX |
| 6883 | 541691348U, // LDUMINB |
| 6884 | 541698473U, // LDUMINH |
| 6885 | 541691210U, // LDUMINLB |
| 6886 | 541698360U, // LDUMINLH |
| 6887 | 541699397U, // LDUMINLW |
| 6888 | 541699397U, // LDUMINLX |
| 6889 | 541699897U, // LDUMINW |
| 6890 | 541699897U, // LDUMINX |
| 6891 | 75533997U, // LDURBBi |
| 6892 | 75543442U, // LDURBi |
| 6893 | 75543442U, // LDURDi |
| 6894 | 75541023U, // LDURHHi |
| 6895 | 75543442U, // LDURHi |
| 6896 | 75543442U, // LDURQi |
| 6897 | 75534144U, // LDURSBWi |
| 6898 | 75534144U, // LDURSBXi |
| 6899 | 75541157U, // LDURSHWi |
| 6900 | 75541157U, // LDURSHXi |
| 6901 | 75549003U, // LDURSWi |
| 6902 | 75543442U, // LDURSi |
| 6903 | 75543442U, // LDURWi |
| 6904 | 75543442U, // LDURXi |
| 6905 | 4239744U, // LDXPW |
| 6906 | 4239744U, // LDXPX |
| 6907 | 75534036U, // LDXRB |
| 6908 | 75541062U, // LDXRH |
| 6909 | 75543506U, // LDXRW |
| 6910 | 75543506U, // LDXRX |
| 6911 | 2151756581U, // LSLR_ZPmZ_B |
| 6912 | 2151789349U, // LSLR_ZPmZ_D |
| 6913 | 2713858853U, // LSLR_ZPmZ_H |
| 6914 | 2151854885U, // LSLR_ZPmZ_S |
| 6915 | 4238870U, // LSLVWr |
| 6916 | 4238870U, // LSLVXr |
| 6917 | 2151755286U, // LSL_WIDE_ZPmZ_B |
| 6918 | 2713857558U, // LSL_WIDE_ZPmZ_H |
| 6919 | 2151853590U, // LSL_WIDE_ZPmZ_S |
| 6920 | 4271638U, // LSL_WIDE_ZZZ_B |
| 6921 | 71446038U, // LSL_WIDE_ZZZ_H |
| 6922 | 541240854U, // LSL_WIDE_ZZZ_S |
| 6923 | 2151755286U, // LSL_ZPmI_B |
| 6924 | 2151788054U, // LSL_ZPmI_D |
| 6925 | 2713857558U, // LSL_ZPmI_H |
| 6926 | 2151853590U, // LSL_ZPmI_S |
| 6927 | 2151755286U, // LSL_ZPmZ_B |
| 6928 | 2151788054U, // LSL_ZPmZ_D |
| 6929 | 2713857558U, // LSL_ZPmZ_H |
| 6930 | 2151853590U, // LSL_ZPmZ_S |
| 6931 | 4271638U, // LSL_ZZI_B |
| 6932 | 541175318U, // LSL_ZZI_D |
| 6933 | 71446038U, // LSL_ZZI_H |
| 6934 | 541240854U, // LSL_ZZI_S |
| 6935 | 2151756628U, // LSRR_ZPmZ_B |
| 6936 | 2151789396U, // LSRR_ZPmZ_D |
| 6937 | 2713858900U, // LSRR_ZPmZ_H |
| 6938 | 2151854932U, // LSRR_ZPmZ_S |
| 6939 | 4240229U, // LSRVWr |
| 6940 | 4240229U, // LSRVXr |
| 6941 | 2151756645U, // LSR_WIDE_ZPmZ_B |
| 6942 | 2713858917U, // LSR_WIDE_ZPmZ_H |
| 6943 | 2151854949U, // LSR_WIDE_ZPmZ_S |
| 6944 | 4272997U, // LSR_WIDE_ZZZ_B |
| 6945 | 71447397U, // LSR_WIDE_ZZZ_H |
| 6946 | 541242213U, // LSR_WIDE_ZZZ_S |
| 6947 | 2151756645U, // LSR_ZPmI_B |
| 6948 | 2151789413U, // LSR_ZPmI_D |
| 6949 | 2713858917U, // LSR_ZPmI_H |
| 6950 | 2151854949U, // LSR_ZPmI_S |
| 6951 | 2151756645U, // LSR_ZPmZ_B |
| 6952 | 2151789413U, // LSR_ZPmZ_D |
| 6953 | 2713858917U, // LSR_ZPmZ_H |
| 6954 | 2151854949U, // LSR_ZPmZ_S |
| 6955 | 4272997U, // LSR_ZZI_B |
| 6956 | 541176677U, // LSR_ZZI_D |
| 6957 | 71447397U, // LSR_ZZI_H |
| 6958 | 541242213U, // LSR_ZZI_S |
| 6959 | 1107492962U, // LUT2v16f8 |
| 6960 | 1652752482U, // LUT2v8f16 |
| 6961 | 1107493090U, // LUT4v16f8 |
| 6962 | 1652752610U, // LUT4v8f16 |
| 6963 | 109346914U, // LUTI2_2ZTZI_B |
| 6964 | 109412450U, // LUTI2_2ZTZI_H |
| 6965 | 109445218U, // LUTI2_2ZTZI_S |
| 6966 | 109346914U, // LUTI2_4ZTZI_B |
| 6967 | 109412450U, // LUTI2_4ZTZI_H |
| 6968 | 109445218U, // LUTI2_4ZTZI_S |
| 6969 | 5308514U, // LUTI2_S_2ZTZI_B |
| 6970 | 5865570U, // LUTI2_S_2ZTZI_H |
| 6971 | 109346914U, // LUTI2_S_4ZTZI_B |
| 6972 | 109412450U, // LUTI2_S_4ZTZI_H |
| 6973 | 4259938U, // LUTI2_ZTZI_B |
| 6974 | 109183074U, // LUTI2_ZTZI_H |
| 6975 | 4358242U, // LUTI2_ZTZI_S |
| 6976 | 1078001762U, // LUTI2_ZZZI_B |
| 6977 | 58851426U, // LUTI2_ZZZI_H |
| 6978 | 109347042U, // LUTI4_2ZTZI_B |
| 6979 | 109412578U, // LUTI4_2ZTZI_H |
| 6980 | 109445346U, // LUTI4_2ZTZI_S |
| 6981 | 109412578U, // LUTI4_4ZTZI_H |
| 6982 | 109445346U, // LUTI4_4ZTZI_S |
| 6983 | 109347042U, // LUTI4_4ZZT2Z |
| 6984 | 5308642U, // LUTI4_S_2ZTZI_B |
| 6985 | 5865698U, // LUTI4_S_2ZTZI_H |
| 6986 | 109412578U, // LUTI4_S_4ZTZI_H |
| 6987 | 109347042U, // LUTI4_S_4ZZT2Z |
| 6988 | 58851554U, // LUTI4_Z2ZZI_H |
| 6989 | 4260066U, // LUTI4_ZTZI_B |
| 6990 | 109183202U, // LUTI4_ZTZI_H |
| 6991 | 4358370U, // LUTI4_ZTZI_S |
| 6992 | 1078001890U, // LUTI4_ZZZI_B |
| 6993 | 58851554U, // LUTI4_ZZZI_H |
| 6994 | 4245150U, // MADDPT |
| 6995 | 4233188U, // MADDWrrr |
| 6996 | 4233188U, // MADDXrrr |
| 6997 | 2151794327U, // MAD_CPA |
| 6998 | 2151749468U, // MAD_ZPmZZ_B |
| 6999 | 2151782236U, // MAD_ZPmZZ_D |
| 7000 | 2713851740U, // MAD_ZPmZZ_H |
| 7001 | 2151847772U, // MAD_ZPmZZ_S |
| 7002 | 2151753900U, // MATCH_PPzZZ_B |
| 7003 | 1103243436U, // MATCH_PPzZZ_H |
| 7004 | 2151794312U, // MLA_CPA |
| 7005 | 2151743830U, // MLA_ZPmZZ_B |
| 7006 | 2151776598U, // MLA_ZPmZZ_D |
| 7007 | 2713846102U, // MLA_ZPmZZ_H |
| 7008 | 2151842134U, // MLA_ZPmZZ_S |
| 7009 | 2151776598U, // MLA_ZZZI_D |
| 7010 | 84017494U, // MLA_ZZZI_H |
| 7011 | 2688713046U, // MLA_ZZZI_S |
| 7012 | 1615070332U, // MLAv16i8 |
| 7013 | 1615082689U, // MLAv2i32 |
| 7014 | 1615082689U, // MLAv2i32_indexed |
| 7015 | 1615076018U, // MLAv4i16 |
| 7016 | 1615076018U, // MLAv4i16_indexed |
| 7017 | 1615084652U, // MLAv4i32 |
| 7018 | 1615084652U, // MLAv4i32_indexed |
| 7019 | 1615077936U, // MLAv8i16 |
| 7020 | 1615077936U, // MLAv8i16_indexed |
| 7021 | 1615071263U, // MLAv8i8 |
| 7022 | 2151760778U, // MLS_ZPmZZ_B |
| 7023 | 2151793546U, // MLS_ZPmZZ_D |
| 7024 | 2713863050U, // MLS_ZPmZZ_H |
| 7025 | 2151859082U, // MLS_ZPmZZ_S |
| 7026 | 2151793546U, // MLS_ZZZI_D |
| 7027 | 84034442U, // MLS_ZZZI_H |
| 7028 | 2688729994U, // MLS_ZZZI_S |
| 7029 | 1615070955U, // MLSv16i8 |
| 7030 | 1615083708U, // MLSv2i32 |
| 7031 | 1615083708U, // MLSv2i32_indexed |
| 7032 | 1615077025U, // MLSv4i16 |
| 7033 | 1615077025U, // MLSv4i16_indexed |
| 7034 | 1615085818U, // MLSv4i32 |
| 7035 | 1615085818U, // MLSv4i32_indexed |
| 7036 | 1615079002U, // MLSv8i16 |
| 7037 | 1615079002U, // MLSv8i16_indexed |
| 7038 | 1615071911U, // MLSv8i8 |
| 7039 | 278842471U, // MOPSSETGE |
| 7040 | 278842532U, // MOPSSETGEN |
| 7041 | 278843420U, // MOPSSETGET |
| 7042 | 278842893U, // MOPSSETGETN |
| 7043 | 2428815914U, // MOVAZ_2ZMI_H_B |
| 7044 | 2428848682U, // MOVAZ_2ZMI_H_D |
| 7045 | 2428881450U, // MOVAZ_2ZMI_H_H |
| 7046 | 2428914218U, // MOVAZ_2ZMI_H_S |
| 7047 | 2433010218U, // MOVAZ_2ZMI_V_B |
| 7048 | 2433042986U, // MOVAZ_2ZMI_V_D |
| 7049 | 2433075754U, // MOVAZ_2ZMI_V_H |
| 7050 | 2433108522U, // MOVAZ_2ZMI_V_S |
| 7051 | 2965686826U, // MOVAZ_4ZMI_H_B |
| 7052 | 2965719594U, // MOVAZ_4ZMI_H_D |
| 7053 | 2965752362U, // MOVAZ_4ZMI_H_H |
| 7054 | 2965785130U, // MOVAZ_4ZMI_H_S |
| 7055 | 2969881130U, // MOVAZ_4ZMI_V_B |
| 7056 | 2969913898U, // MOVAZ_4ZMI_V_D |
| 7057 | 2969946666U, // MOVAZ_4ZMI_V_H |
| 7058 | 2969979434U, // MOVAZ_4ZMI_V_S |
| 7059 | 3510979114U, // MOVAZ_VG2_2ZMXI |
| 7060 | 4047850026U, // MOVAZ_VG4_4ZMXI |
| 7061 | 4278826U, // MOVAZ_ZMI_H_B |
| 7062 | 4311594U, // MOVAZ_ZMI_H_D |
| 7063 | 830622250U, // MOVAZ_ZMI_H_H |
| 7064 | 831441450U, // MOVAZ_ZMI_H_Q |
| 7065 | 4377130U, // MOVAZ_ZMI_H_S |
| 7066 | 541149738U, // MOVAZ_ZMI_V_B |
| 7067 | 541182506U, // MOVAZ_ZMI_V_D |
| 7068 | 834816554U, // MOVAZ_ZMI_V_H |
| 7069 | 835635754U, // MOVAZ_ZMI_V_Q |
| 7070 | 541248042U, // MOVAZ_ZMI_V_S |
| 7071 | 1904509626U, // MOVA_2ZMXI_H_B |
| 7072 | 1904542394U, // MOVA_2ZMXI_H_D |
| 7073 | 1904575162U, // MOVA_2ZMXI_H_H |
| 7074 | 1904607930U, // MOVA_2ZMXI_H_S |
| 7075 | 1908703930U, // MOVA_2ZMXI_V_B |
| 7076 | 1908736698U, // MOVA_2ZMXI_V_D |
| 7077 | 1908769466U, // MOVA_2ZMXI_V_H |
| 7078 | 1908802234U, // MOVA_2ZMXI_V_S |
| 7079 | 1904509626U, // MOVA_4ZMXI_H_B |
| 7080 | 1904542394U, // MOVA_4ZMXI_H_D |
| 7081 | 1904575162U, // MOVA_4ZMXI_H_H |
| 7082 | 1904607930U, // MOVA_4ZMXI_H_S |
| 7083 | 1908703930U, // MOVA_4ZMXI_V_B |
| 7084 | 1908736698U, // MOVA_4ZMXI_V_D |
| 7085 | 1908769466U, // MOVA_4ZMXI_V_H |
| 7086 | 1908802234U, // MOVA_4ZMXI_V_S |
| 7087 | 173015738U, // MOVA_MXI2Z_H_B |
| 7088 | 173015738U, // MOVA_MXI2Z_H_D |
| 7089 | 173015738U, // MOVA_MXI2Z_H_H |
| 7090 | 173015738U, // MOVA_MXI2Z_H_S |
| 7091 | 173048506U, // MOVA_MXI2Z_V_B |
| 7092 | 173048506U, // MOVA_MXI2Z_V_D |
| 7093 | 173048506U, // MOVA_MXI2Z_V_H |
| 7094 | 173048506U, // MOVA_MXI2Z_V_S |
| 7095 | 173015738U, // MOVA_MXI4Z_H_B |
| 7096 | 173015738U, // MOVA_MXI4Z_H_D |
| 7097 | 173015738U, // MOVA_MXI4Z_H_H |
| 7098 | 173015738U, // MOVA_MXI4Z_H_S |
| 7099 | 173048506U, // MOVA_MXI4Z_V_B |
| 7100 | 173048506U, // MOVA_MXI4Z_V_D |
| 7101 | 173048506U, // MOVA_MXI4Z_V_H |
| 7102 | 173048506U, // MOVA_MXI4Z_V_S |
| 7103 | 3523543738U, // MOVA_VG2_2ZMXI |
| 7104 | 3288761018U, // MOVA_VG2_MXI2Z |
| 7105 | 4060414650U, // MOVA_VG4_4ZMXI |
| 7106 | 3825631930U, // MOVA_VG4_MXI4Z |
| 7107 | 1077979960U, // MOVID |
| 7108 | 1615005110U, // MOVIv16b_ns |
| 7109 | 1078137757U, // MOVIv2d_ns |
| 7110 | 1615017608U, // MOVIv2i32 |
| 7111 | 1615017608U, // MOVIv2s_msl |
| 7112 | 1615010914U, // MOVIv4i16 |
| 7113 | 1615019626U, // MOVIv4i32 |
| 7114 | 1615019626U, // MOVIv4s_msl |
| 7115 | 1615005972U, // MOVIv8b_ns |
| 7116 | 1615012832U, // MOVIv8i16 |
| 7117 | 3762334545U, // MOVKWi |
| 7118 | 3762334545U, // MOVKXi |
| 7119 | 1614852043U, // MOVNWi |
| 7120 | 1614852043U, // MOVNXi |
| 7121 | 541149649U, // MOVPRFX_ZPmZ_B |
| 7122 | 541182417U, // MOVPRFX_ZPmZ_D |
| 7123 | 1082280401U, // MOVPRFX_ZPmZ_H |
| 7124 | 541247953U, // MOVPRFX_ZPmZ_S |
| 7125 | 2151762385U, // MOVPRFX_ZPzZ_B |
| 7126 | 2151795153U, // MOVPRFX_ZPzZ_D |
| 7127 | 1103251921U, // MOVPRFX_ZPzZ_H |
| 7128 | 2151860689U, // MOVPRFX_ZPzZ_S |
| 7129 | 2153728465U, // MOVPRFX_ZZ |
| 7130 | 2453718785U, // MOVT |
| 7131 | 2990589697U, // MOVT_TIX |
| 7132 | 4245249U, // MOVT_XTI |
| 7133 | 1614858856U, // MOVZWi |
| 7134 | 1614858856U, // MOVZXi |
| 7135 | 2114569U, // MRRS |
| 7136 | 3225469944U, // MRS |
| 7137 | 2151747357U, // MSB_ZPmZZ_B |
| 7138 | 2151780125U, // MSB_ZPmZZ_D |
| 7139 | 2713849629U, // MSB_ZPmZZ_H |
| 7140 | 2151845661U, // MSB_ZPmZZ_S |
| 7141 | 3332420458U, // MSR |
| 7142 | 312521562U, // MSRR |
| 7143 | 2175850U, // MSRpstateImm1 |
| 7144 | 2175850U, // MSRpstateImm4 |
| 7145 | 2208618U, // MSRpstatesvcrImm1 |
| 7146 | 4245135U, // MSUBPT |
| 7147 | 4231081U, // MSUBWrrr |
| 7148 | 4231081U, // MSUBXrrr |
| 7149 | 4271725U, // MUL_ZI_B |
| 7150 | 541175405U, // MUL_ZI_D |
| 7151 | 71446125U, // MUL_ZI_H |
| 7152 | 541240941U, // MUL_ZI_S |
| 7153 | 2151755373U, // MUL_ZPmZ_B |
| 7154 | 2151788141U, // MUL_ZPmZ_D |
| 7155 | 2713857645U, // MUL_ZPmZ_H |
| 7156 | 2151853677U, // MUL_ZPmZ_S |
| 7157 | 541175405U, // MUL_ZZZI_D |
| 7158 | 71446125U, // MUL_ZZZI_H |
| 7159 | 541240941U, // MUL_ZZZI_S |
| 7160 | 4271725U, // MUL_ZZZ_B |
| 7161 | 541175405U, // MUL_ZZZ_D |
| 7162 | 71446125U, // MUL_ZZZ_H |
| 7163 | 541240941U, // MUL_ZZZ_S |
| 7164 | 1615005218U, // MULv16i8 |
| 7165 | 1615017698U, // MULv2i32 |
| 7166 | 1615017698U, // MULv2i32_indexed |
| 7167 | 1615011004U, // MULv4i16 |
| 7168 | 1615011004U, // MULv4i16_indexed |
| 7169 | 1615019912U, // MULv4i32 |
| 7170 | 1615019912U, // MULv4i32_indexed |
| 7171 | 1615013116U, // MULv8i16 |
| 7172 | 1615013116U, // MULv8i16_indexed |
| 7173 | 1615006070U, // MULv8i8 |
| 7174 | 1615017580U, // MVNIv2i32 |
| 7175 | 1615017580U, // MVNIv2s_msl |
| 7176 | 1615010886U, // MVNIv4i16 |
| 7177 | 1615019598U, // MVNIv4i32 |
| 7178 | 1615019598U, // MVNIv4s_msl |
| 7179 | 1615012804U, // MVNIv8i16 |
| 7180 | 2151760725U, // NANDS_PPzPP |
| 7181 | 2151749640U, // NAND_PPzPP |
| 7182 | 541175308U, // NBSL_ZZZZ |
| 7183 | 541137175U, // NEG_ZPmZ_B |
| 7184 | 541169943U, // NEG_ZPmZ_D |
| 7185 | 1082267927U, // NEG_ZPmZ_H |
| 7186 | 541235479U, // NEG_ZPmZ_S |
| 7187 | 1615005073U, // NEGv16i8 |
| 7188 | 4233495U, // NEGv1i64 |
| 7189 | 1615017494U, // NEGv2i32 |
| 7190 | 1615008603U, // NEGv2i64 |
| 7191 | 1615010800U, // NEGv4i16 |
| 7192 | 1615019500U, // NEGv4i32 |
| 7193 | 1615012718U, // NEGv8i16 |
| 7194 | 1615005939U, // NEGv8i8 |
| 7195 | 2151753899U, // NMATCH_PPzZZ_B |
| 7196 | 1103243435U, // NMATCH_PPzZZ_H |
| 7197 | 2151760899U, // NORS_PPzPP |
| 7198 | 2151756600U, // NOR_PPzPP |
| 7199 | 541148803U, // NOT_ZPmZ_B |
| 7200 | 541181571U, // NOT_ZPmZ_D |
| 7201 | 1082279555U, // NOT_ZPmZ_H |
| 7202 | 541247107U, // NOT_ZPmZ_S |
| 7203 | 1615005467U, // NOTv16i8 |
| 7204 | 1615006418U, // NOTv8i8 |
| 7205 | 2151760812U, // ORNS_PPzPP |
| 7206 | 4239220U, // ORNWrs |
| 7207 | 4239220U, // ORNXrs |
| 7208 | 2151755636U, // ORN_PPzPP |
| 7209 | 1615005247U, // ORNv16i8 |
| 7210 | 1615006164U, // ORNv8i8 |
| 7211 | 2181253163U, // ORQV_VPZ_B |
| 7212 | 2185447467U, // ORQV_VPZ_D |
| 7213 | 2189641771U, // ORQV_VPZ_H |
| 7214 | 2193836075U, // ORQV_VPZ_S |
| 7215 | 2151760911U, // ORRS_PPzPP |
| 7216 | 4240201U, // ORRWri |
| 7217 | 4240201U, // ORRWrs |
| 7218 | 4240201U, // ORRXri |
| 7219 | 4240201U, // ORRXrs |
| 7220 | 2151756617U, // ORR_PPzPP |
| 7221 | 541176649U, // ORR_ZI |
| 7222 | 2151756617U, // ORR_ZPmZ_B |
| 7223 | 2151789385U, // ORR_ZPmZ_D |
| 7224 | 2713858889U, // ORR_ZPmZ_H |
| 7225 | 2151854921U, // ORR_ZPmZ_S |
| 7226 | 541176649U, // ORR_ZZZ |
| 7227 | 1615005380U, // ORRv16i8 |
| 7228 | 3762567300U, // ORRv2i32 |
| 7229 | 3762560617U, // ORRv4i16 |
| 7230 | 3762569410U, // ORRv4i32 |
| 7231 | 3762562594U, // ORRv8i16 |
| 7232 | 1615006340U, // ORRv8i8 |
| 7233 | 510026U, // ORV_VPZ_B |
| 7234 | 3301460042U, // ORV_VPZ_D |
| 7235 | 3305687114U, // ORV_VPZ_H |
| 7236 | 3246999626U, // ORV_VPZ_S |
| 7237 | 1615429909U, // PACDA |
| 7238 | 1615432697U, // PACDB |
| 7239 | 623314U, // PACDZA |
| 7240 | 626685U, // PACDZB |
| 7241 | 4227378U, // PACGA |
| 7242 | 1615429952U, // PACIA |
| 7243 | 19405U, // PACIA1716 |
| 7244 | 19315U, // PACIA171615 |
| 7245 | 19363U, // PACIASP |
| 7246 | 20797U, // PACIASPPC |
| 7247 | 19306U, // PACIAZ |
| 7248 | 1615432732U, // PACIB |
| 7249 | 19231U, // PACIB1716 |
| 7250 | 19339U, // PACIB171615 |
| 7251 | 19396U, // PACIBSP |
| 7252 | 20819U, // PACIBSPPC |
| 7253 | 19379U, // PACIBZ |
| 7254 | 623330U, // PACIZA |
| 7255 | 626701U, // PACIZB |
| 7256 | 19437U, // PACM |
| 7257 | 20785U, // PACNBIASPPC |
| 7258 | 20807U, // PACNBIBSPPC |
| 7259 | 2323957556U, // PEXT_2PCI_B |
| 7260 | 2323990324U, // PEXT_2PCI_D |
| 7261 | 2324023092U, // PEXT_2PCI_H |
| 7262 | 2324055860U, // PEXT_2PCI_S |
| 7263 | 4278068U, // PEXT_PCI_B |
| 7264 | 4310836U, // PEXT_PCI_D |
| 7265 | 2323793716U, // PEXT_PCI_H |
| 7266 | 4376372U, // PEXT_PCI_S |
| 7267 | 71876U, // PFALSE |
| 7268 | 2151761603U, // PFIRST_B |
| 7269 | 2151761897U, // PMOV_PZI_B |
| 7270 | 2151794665U, // PMOV_PZI_D |
| 7271 | 2176993257U, // PMOV_PZI_H |
| 7272 | 2151860201U, // PMOV_PZI_S |
| 7273 | 3923724265U, // PMOV_ZIP_B |
| 7274 | 2849982441U, // PMOV_ZIP_D |
| 7275 | 1239369705U, // PMOV_ZIP_H |
| 7276 | 2313111529U, // PMOV_ZIP_S |
| 7277 | 541166888U, // PMULLB_ZZZ_D |
| 7278 | 88214824U, // PMULLB_ZZZ_H |
| 7279 | 315526440U, // PMULLB_ZZZ_Q |
| 7280 | 541181283U, // PMULLT_ZZZ_D |
| 7281 | 88229219U, // PMULLT_ZZZ_H |
| 7282 | 315540835U, // PMULLT_ZZZ_Q |
| 7283 | 1615012071U, // PMULLv16i8 |
| 7284 | 1615016355U, // PMULLv1i64 |
| 7285 | 1615016344U, // PMULLv2i64 |
| 7286 | 1615013041U, // PMULLv8i8 |
| 7287 | 4271737U, // PMUL_ZZZ_B |
| 7288 | 1615005217U, // PMULv16i8 |
| 7289 | 1615006069U, // PMULv8i8 |
| 7290 | 2151761709U, // PNEXT_B |
| 7291 | 2151794477U, // PNEXT_D |
| 7292 | 29509421U, // PNEXT_H |
| 7293 | 2151860013U, // PNEXT_S |
| 7294 | 81923087U, // PRFB_D_PZI |
| 7295 | 174197775U, // PRFB_D_SCALED |
| 7296 | 174197775U, // PRFB_D_SXTW_SCALED |
| 7297 | 174197775U, // PRFB_D_UXTW_SCALED |
| 7298 | 174197775U, // PRFB_PRI |
| 7299 | 174197775U, // PRFB_PRR |
| 7300 | 27397135U, // PRFB_S_PZI |
| 7301 | 174197775U, // PRFB_S_SXTW_SCALED |
| 7302 | 174197775U, // PRFB_S_UXTW_SCALED |
| 7303 | 81926146U, // PRFD_D_PZI |
| 7304 | 174200834U, // PRFD_D_SCALED |
| 7305 | 174200834U, // PRFD_D_SXTW_SCALED |
| 7306 | 174200834U, // PRFD_D_UXTW_SCALED |
| 7307 | 174200834U, // PRFD_PRI |
| 7308 | 174200834U, // PRFD_PRR |
| 7309 | 27400194U, // PRFD_S_PZI |
| 7310 | 174200834U, // PRFD_S_SXTW_SCALED |
| 7311 | 174200834U, // PRFD_S_UXTW_SCALED |
| 7312 | 81930427U, // PRFH_D_PZI |
| 7313 | 174205115U, // PRFH_D_SCALED |
| 7314 | 174205115U, // PRFH_D_SXTW_SCALED |
| 7315 | 174205115U, // PRFH_D_UXTW_SCALED |
| 7316 | 174205115U, // PRFH_PRI |
| 7317 | 174205115U, // PRFH_PRR |
| 7318 | 27404475U, // PRFH_S_PZI |
| 7319 | 174205115U, // PRFH_S_SXTW_SCALED |
| 7320 | 174205115U, // PRFH_S_UXTW_SCALED |
| 7321 | 6467266U, // PRFMl |
| 7322 | 77770434U, // PRFMroW |
| 7323 | 77770434U, // PRFMroX |
| 7324 | 77770434U, // PRFMui |
| 7325 | 77770510U, // PRFUMi |
| 7326 | 81938661U, // PRFW_D_PZI |
| 7327 | 174213349U, // PRFW_D_SCALED |
| 7328 | 174213349U, // PRFW_D_SXTW_SCALED |
| 7329 | 174213349U, // PRFW_D_UXTW_SCALED |
| 7330 | 174213349U, // PRFW_PRI |
| 7331 | 174213349U, // PRFW_PRR |
| 7332 | 27412709U, // PRFW_S_PZI |
| 7333 | 174213349U, // PRFW_S_SXTW_SCALED |
| 7334 | 174213349U, // PRFW_S_UXTW_SCALED |
| 7335 | 2153721027U, // PSEL_PPPRI_B |
| 7336 | 2153721027U, // PSEL_PPPRI_D |
| 7337 | 2153721027U, // PSEL_PPPRI_H |
| 7338 | 2153721027U, // PSEL_PPPRI_S |
| 7339 | 6244021U, // PTEST_PP |
| 7340 | 1614889820U, // PTRUES_B |
| 7341 | 1614922588U, // PTRUES_D |
| 7342 | 318915420U, // PTRUES_H |
| 7343 | 1614988124U, // PTRUES_S |
| 7344 | 1614878942U, // PTRUE_B |
| 7345 | 2300126U, // PTRUE_C_B |
| 7346 | 2332894U, // PTRUE_C_D |
| 7347 | 2365662U, // PTRUE_C_H |
| 7348 | 2398430U, // PTRUE_C_S |
| 7349 | 1614911710U, // PTRUE_D |
| 7350 | 318904542U, // PTRUE_H |
| 7351 | 1614977246U, // PTRUE_S |
| 7352 | 3309447929U, // PUNPKHI_PP |
| 7353 | 3309449186U, // PUNPKLO_PP |
| 7354 | 3762359746U, // RADDHNB_ZZZ_B |
| 7355 | 21106114U, // RADDHNB_ZZZ_H |
| 7356 | 541232578U, // RADDHNB_ZZZ_S |
| 7357 | 1078019546U, // RADDHNT_ZZZ_B |
| 7358 | 25314778U, // RADDHNT_ZZZ_H |
| 7359 | 2151859674U, // RADDHNT_ZZZ_S |
| 7360 | 1615017750U, // RADDHNv2i64_v2i32 |
| 7361 | 1615084390U, // RADDHNv2i64_v4i32 |
| 7362 | 1615011056U, // RADDHNv4i32_v4i16 |
| 7363 | 1615077700U, // RADDHNv4i32_v8i16 |
| 7364 | 1615070117U, // RADDHNv8i16_v16i8 |
| 7365 | 1615006089U, // RADDHNv8i16_v8i8 |
| 7366 | 1615008063U, // RAX1 |
| 7367 | 541163600U, // RAX1_ZZZ_D |
| 7368 | 4244663U, // RBITWr |
| 7369 | 4244663U, // RBITXr |
| 7370 | 541148343U, // RBIT_ZPmZ_B |
| 7371 | 541181111U, // RBIT_ZPmZ_D |
| 7372 | 1082279095U, // RBIT_ZPmZ_H |
| 7373 | 541246647U, // RBIT_ZPmZ_S |
| 7374 | 1615005438U, // RBITv16i8 |
| 7375 | 1615006392U, // RBITv8i8 |
| 7376 | 1615446780U, // RCWCAS |
| 7377 | 1615430271U, // RCWCASA |
| 7378 | 1615440970U, // RCWCASAL |
| 7379 | 1615441411U, // RCWCASL |
| 7380 | 831760U, // RCWCASP |
| 7381 | 819702U, // RCWCASPA |
| 7382 | 830423U, // RCWCASPAL |
| 7383 | 830867U, // RCWCASPL |
| 7384 | 541700836U, // RCWCLR |
| 7385 | 541688394U, // RCWCLRA |
| 7386 | 541699116U, // RCWCLRAL |
| 7387 | 541699560U, // RCWCLRL |
| 7388 | 543076605U, // RCWCLRP |
| 7389 | 543064545U, // RCWCLRPA |
| 7390 | 543075264U, // RCWCLRPAL |
| 7391 | 543075710U, // RCWCLRPL |
| 7392 | 541700827U, // RCWCLRS |
| 7393 | 541688384U, // RCWCLRSA |
| 7394 | 541699105U, // RCWCLRSAL |
| 7395 | 541699550U, // RCWCLRSL |
| 7396 | 543076595U, // RCWCLRSP |
| 7397 | 543064534U, // RCWCLRSPA |
| 7398 | 543075252U, // RCWCLRSPAL |
| 7399 | 543075699U, // RCWCLRSPL |
| 7400 | 1615446771U, // RCWSCAS |
| 7401 | 1615430261U, // RCWSCASA |
| 7402 | 1615440959U, // RCWSCASAL |
| 7403 | 1615441401U, // RCWSCASL |
| 7404 | 831750U, // RCWSCASP |
| 7405 | 819691U, // RCWSCASPA |
| 7406 | 830411U, // RCWSCASPAL |
| 7407 | 830856U, // RCWSCASPL |
| 7408 | 541705361U, // RCWSET |
| 7409 | 541688474U, // RCWSETA |
| 7410 | 541699176U, // RCWSETAL |
| 7411 | 541699657U, // RCWSETL |
| 7412 | 543076657U, // RCWSETP |
| 7413 | 543064596U, // RCWSETPA |
| 7414 | 543075320U, // RCWSETPAL |
| 7415 | 543075769U, // RCWSETPL |
| 7416 | 541705352U, // RCWSETS |
| 7417 | 541688464U, // RCWSETSA |
| 7418 | 541699165U, // RCWSETSAL |
| 7419 | 541699647U, // RCWSETSL |
| 7420 | 543076647U, // RCWSETSP |
| 7421 | 543064585U, // RCWSETSPA |
| 7422 | 543075308U, // RCWSETSPAL |
| 7423 | 543075758U, // RCWSETSPL |
| 7424 | 541700444U, // RCWSWP |
| 7425 | 541688360U, // RCWSWPA |
| 7426 | 541699086U, // RCWSWPAL |
| 7427 | 541699533U, // RCWSWPL |
| 7428 | 543076566U, // RCWSWPP |
| 7429 | 543064515U, // RCWSWPPA |
| 7430 | 543075231U, // RCWSWPPAL |
| 7431 | 543075680U, // RCWSWPPL |
| 7432 | 541700435U, // RCWSWPS |
| 7433 | 541688350U, // RCWSWPSA |
| 7434 | 541699075U, // RCWSWPSAL |
| 7435 | 541699523U, // RCWSWPSL |
| 7436 | 543076556U, // RCWSWPSP |
| 7437 | 543064504U, // RCWSWPSPA |
| 7438 | 543075219U, // RCWSWPSPAL |
| 7439 | 543075669U, // RCWSWPSPL |
| 7440 | 2151760880U, // RDFFRS_PPz |
| 7441 | 78487U, // RDFFR_P |
| 7442 | 2151756439U, // RDFFR_PPz |
| 7443 | 4239004U, // RDSVLI_XI |
| 7444 | 4238990U, // RDVLI_XI |
| 7445 | 50300U, // RET |
| 7446 | 20716U, // RETAA |
| 7447 | 659522U, // RETAASPPCi |
| 7448 | 45661U, // RETAASPPCr |
| 7449 | 20743U, // RETAB |
| 7450 | 659544U, // RETABSPPCi |
| 7451 | 45685U, // RETABSPPCr |
| 7452 | 4227310U, // REV16Wr |
| 7453 | 4227310U, // REV16Xr |
| 7454 | 1615004765U, // REV16v16i8 |
| 7455 | 1615005699U, // REV16v8i8 |
| 7456 | 4227158U, // REV32Xr |
| 7457 | 1615004557U, // REV32v16i8 |
| 7458 | 1615010415U, // REV32v4i16 |
| 7459 | 1615011929U, // REV32v8i16 |
| 7460 | 1615005652U, // REV32v8i8 |
| 7461 | 1615004754U, // REV64v16i8 |
| 7462 | 1615017123U, // REV64v2i32 |
| 7463 | 1615010452U, // REV64v4i16 |
| 7464 | 1615019062U, // REV64v4i32 |
| 7465 | 1615012370U, // REV64v8i16 |
| 7466 | 1615005689U, // REV64v8i8 |
| 7467 | 541167557U, // REVB_ZPmZ_D |
| 7468 | 1082265541U, // REVB_ZPmZ_H |
| 7469 | 541233093U, // REVB_ZPmZ_S |
| 7470 | 9345079U, // REVD_ZPmZ |
| 7471 | 541174481U, // REVH_ZPmZ_D |
| 7472 | 541240017U, // REVH_ZPmZ_S |
| 7473 | 541182319U, // REVW_ZPmZ_D |
| 7474 | 4245406U, // REVWr |
| 7475 | 4245406U, // REVXr |
| 7476 | 4278174U, // REV_PP_B |
| 7477 | 541181854U, // REV_PP_D |
| 7478 | 3292678046U, // REV_PP_H |
| 7479 | 541247390U, // REV_PP_S |
| 7480 | 4278174U, // REV_ZZ_B |
| 7481 | 541181854U, // REV_ZZ_D |
| 7482 | 3292678046U, // REV_ZZ_H |
| 7483 | 541247390U, // REV_ZZ_S |
| 7484 | 20829U, // RMIF |
| 7485 | 4240189U, // RORVWr |
| 7486 | 4240189U, // RORVXr |
| 7487 | 2436801U, // RPRFM |
| 7488 | 3762359793U, // RSHRNB_ZZI_B |
| 7489 | 21106161U, // RSHRNB_ZZI_H |
| 7490 | 541232625U, // RSHRNB_ZZI_S |
| 7491 | 1078019581U, // RSHRNT_ZZI_B |
| 7492 | 25314813U, // RSHRNT_ZZI_H |
| 7493 | 2151859709U, // RSHRNT_ZZI_S |
| 7494 | 1615070158U, // RSHRNv16i8_shift |
| 7495 | 1615017822U, // RSHRNv2i32_shift |
| 7496 | 1615011128U, // RSHRNv4i16_shift |
| 7497 | 1615084428U, // RSHRNv4i32_shift |
| 7498 | 1615077738U, // RSHRNv8i16_shift |
| 7499 | 1615006142U, // RSHRNv8i8_shift |
| 7500 | 3762359737U, // RSUBHNB_ZZZ_B |
| 7501 | 21106105U, // RSUBHNB_ZZZ_H |
| 7502 | 541232569U, // RSUBHNB_ZZZ_S |
| 7503 | 1078019537U, // RSUBHNT_ZZZ_B |
| 7504 | 25314769U, // RSUBHNT_ZZZ_H |
| 7505 | 2151859665U, // RSUBHNT_ZZZ_S |
| 7506 | 1615017739U, // RSUBHNv2i64_v2i32 |
| 7507 | 1615084378U, // RSUBHNv2i64_v4i32 |
| 7508 | 1615011045U, // RSUBHNv4i32_v4i16 |
| 7509 | 1615077688U, // RSUBHNv4i32_v8i16 |
| 7510 | 1615070104U, // RSUBHNv8i16_v16i8 |
| 7511 | 1615006078U, // RSUBHNv8i16_v8i8 |
| 7512 | 2688650288U, // SABALB_ZZZ_D |
| 7513 | 146934832U, // SABALB_ZZZ_H |
| 7514 | 1078103088U, // SABALB_ZZZ_S |
| 7515 | 2688664778U, // SABALT_ZZZ_D |
| 7516 | 146949322U, // SABALT_ZZZ_H |
| 7517 | 1078117578U, // SABALT_ZZZ_S |
| 7518 | 1615077475U, // SABALv16i8_v8i16 |
| 7519 | 1615074214U, // SABALv2i32_v2i64 |
| 7520 | 1615085171U, // SABALv4i16_v4i32 |
| 7521 | 1615073621U, // SABALv4i32_v2i64 |
| 7522 | 1615084163U, // SABALv8i16_v4i32 |
| 7523 | 1615078377U, // SABALv8i8_v8i16 |
| 7524 | 541131017U, // SABA_ZZZ_B |
| 7525 | 2151776521U, // SABA_ZZZ_D |
| 7526 | 84017417U, // SABA_ZZZ_H |
| 7527 | 2688712969U, // SABA_ZZZ_S |
| 7528 | 1615070312U, // SABAv16i8 |
| 7529 | 1615082669U, // SABAv2i32 |
| 7530 | 1615075998U, // SABAv4i16 |
| 7531 | 1615084632U, // SABAv4i32 |
| 7532 | 1615077916U, // SABAv8i16 |
| 7533 | 1615071245U, // SABAv8i8 |
| 7534 | 541166821U, // SABDLB_ZZZ_D |
| 7535 | 88214757U, // SABDLB_ZZZ_H |
| 7536 | 3762457829U, // SABDLB_ZZZ_S |
| 7537 | 541181211U, // SABDLT_ZZZ_D |
| 7538 | 88229147U, // SABDLT_ZZZ_H |
| 7539 | 3762472219U, // SABDLT_ZZZ_S |
| 7540 | 1615012005U, // SABDLv16i8_v8i16 |
| 7541 | 1615008750U, // SABDLv2i32_v2i64 |
| 7542 | 1615019707U, // SABDLv4i16_v4i32 |
| 7543 | 1615008164U, // SABDLv4i32_v2i64 |
| 7544 | 1615018706U, // SABDLv8i16_v4i32 |
| 7545 | 1615012901U, // SABDLv8i8_v8i16 |
| 7546 | 2151749493U, // SABD_ZPmZ_B |
| 7547 | 2151782261U, // SABD_ZPmZ_D |
| 7548 | 2713851765U, // SABD_ZPmZ_H |
| 7549 | 2151847797U, // SABD_ZPmZ_S |
| 7550 | 1615004923U, // SABDv16i8 |
| 7551 | 1615017285U, // SABDv2i32 |
| 7552 | 1615010614U, // SABDv4i16 |
| 7553 | 1615019282U, // SABDv4i32 |
| 7554 | 1615012532U, // SABDv8i16 |
| 7555 | 1615005821U, // SABDv8i8 |
| 7556 | 2151788628U, // SADALP_ZPmZ_D |
| 7557 | 2713858132U, // SADALP_ZPmZ_H |
| 7558 | 2151854164U, // SADALP_ZPmZ_S |
| 7559 | 1615078751U, // SADALPv16i8_v8i16 |
| 7560 | 1615073456U, // SADALPv2i32_v1i64 |
| 7561 | 1615083457U, // SADALPv4i16_v2i32 |
| 7562 | 1615074572U, // SADALPv4i32_v2i64 |
| 7563 | 1615085567U, // SADALPv8i16_v4i32 |
| 7564 | 1615076774U, // SADALPv8i8_v4i16 |
| 7565 | 541181000U, // SADDLBT_ZZZ_D |
| 7566 | 88228936U, // SADDLBT_ZZZ_H |
| 7567 | 3762472008U, // SADDLBT_ZZZ_S |
| 7568 | 541166846U, // SADDLB_ZZZ_D |
| 7569 | 88214782U, // SADDLB_ZZZ_H |
| 7570 | 3762457854U, // SADDLB_ZZZ_S |
| 7571 | 1615013237U, // SADDLPv16i8_v8i16 |
| 7572 | 1615007942U, // SADDLPv2i32_v1i64 |
| 7573 | 1615017943U, // SADDLPv4i16_v2i32 |
| 7574 | 1615009058U, // SADDLPv4i32_v2i64 |
| 7575 | 1615020053U, // SADDLPv8i16_v4i32 |
| 7576 | 1615011260U, // SADDLPv8i8_v4i16 |
| 7577 | 541181227U, // SADDLT_ZZZ_D |
| 7578 | 88229163U, // SADDLT_ZZZ_H |
| 7579 | 3762472235U, // SADDLT_ZZZ_S |
| 7580 | 1614841678U, // SADDLVv16i8v |
| 7581 | 1614847858U, // SADDLVv4i16v |
| 7582 | 1614856651U, // SADDLVv4i32v |
| 7583 | 1614849835U, // SADDLVv8i16v |
| 7584 | 1614842624U, // SADDLVv8i8v |
| 7585 | 1615012027U, // SADDLv16i8_v8i16 |
| 7586 | 1615008770U, // SADDLv2i32_v2i64 |
| 7587 | 1615019727U, // SADDLv4i16_v4i32 |
| 7588 | 1615008186U, // SADDLv4i32_v2i64 |
| 7589 | 1615018728U, // SADDLv8i16_v4i32 |
| 7590 | 1615012921U, // SADDLv8i8_v8i16 |
| 7591 | 3368568714U, // SADDV_VPZ_B |
| 7592 | 3305654154U, // SADDV_VPZ_H |
| 7593 | 3246933898U, // SADDV_VPZ_S |
| 7594 | 541167579U, // SADDWB_ZZZ_D |
| 7595 | 71438299U, // SADDWB_ZZZ_H |
| 7596 | 541233115U, // SADDWB_ZZZ_S |
| 7597 | 541181719U, // SADDWT_ZZZ_D |
| 7598 | 71452439U, // SADDWT_ZZZ_H |
| 7599 | 541247255U, // SADDWT_ZZZ_S |
| 7600 | 1615012348U, // SADDWv16i8_v8i16 |
| 7601 | 1615009468U, // SADDWv2i32_v2i64 |
| 7602 | 1615020626U, // SADDWv4i16_v4i32 |
| 7603 | 1615008349U, // SADDWv4i32_v2i64 |
| 7604 | 1615019026U, // SADDWv8i16_v4i32 |
| 7605 | 1615013810U, // SADDWv8i8_v8i16 |
| 7606 | 20766U, // SB |
| 7607 | 2151779543U, // SBCLB_ZZZ_D |
| 7608 | 2688715991U, // SBCLB_ZZZ_S |
| 7609 | 2151793933U, // SBCLT_ZZZ_D |
| 7610 | 2688730381U, // SBCLT_ZZZ_S |
| 7611 | 4244285U, // SBCSWr |
| 7612 | 4244285U, // SBCSXr |
| 7613 | 4231197U, // SBCWr |
| 7614 | 4231197U, // SBCXr |
| 7615 | 4239029U, // SBFMWri |
| 7616 | 4239029U, // SBFMXri |
| 7617 | 147107956U, // SCLAMP_VG2_2Z2Z_B |
| 7618 | 80031860U, // SCLAMP_VG2_2Z2Z_D |
| 7619 | 84258932U, // SCLAMP_VG2_2Z2Z_H |
| 7620 | 25571444U, // SCLAMP_VG2_2Z2Z_S |
| 7621 | 147107956U, // SCLAMP_VG4_4Z4Z_B |
| 7622 | 80031860U, // SCLAMP_VG4_4Z4Z_D |
| 7623 | 84258932U, // SCLAMP_VG4_4Z4Z_H |
| 7624 | 25571444U, // SCLAMP_VG4_4Z4Z_S |
| 7625 | 541143156U, // SCLAMP_ZZZ_B |
| 7626 | 2151788660U, // SCLAMP_ZZZ_D |
| 7627 | 84029556U, // SCLAMP_ZZZ_H |
| 7628 | 2688725108U, // SCLAMP_ZZZ_S |
| 7629 | 4233450U, // SCVTFSWDri |
| 7630 | 4233450U, // SCVTFSWHri |
| 7631 | 4233450U, // SCVTFSWSri |
| 7632 | 4233450U, // SCVTFSXDri |
| 7633 | 4233450U, // SCVTFSXHri |
| 7634 | 4233450U, // SCVTFSXSri |
| 7635 | 4233450U, // SCVTFUWDri |
| 7636 | 4233450U, // SCVTFUWHri |
| 7637 | 4233450U, // SCVTFUWSri |
| 7638 | 4233450U, // SCVTFUXDri |
| 7639 | 4233450U, // SCVTFUXHri |
| 7640 | 4233450U, // SCVTFUXSri |
| 7641 | 3284539626U, // SCVTF_2Z2Z_StoS |
| 7642 | 3284539626U, // SCVTF_4Z4Z_StoS |
| 7643 | 541169898U, // SCVTF_ZPmZ_DtoD |
| 7644 | 2692880618U, // SCVTF_ZPmZ_DtoH |
| 7645 | 541235434U, // SCVTF_ZPmZ_DtoS |
| 7646 | 1082267882U, // SCVTF_ZPmZ_HtoH |
| 7647 | 541169898U, // SCVTF_ZPmZ_StoD |
| 7648 | 2156009706U, // SCVTF_ZPmZ_StoH |
| 7649 | 541235434U, // SCVTF_ZPmZ_StoS |
| 7650 | 4233450U, // SCVTFd |
| 7651 | 4233450U, // SCVTFh |
| 7652 | 4233450U, // SCVTFs |
| 7653 | 4233450U, // SCVTFv1i16 |
| 7654 | 4233450U, // SCVTFv1i32 |
| 7655 | 4233450U, // SCVTFv1i64 |
| 7656 | 1615017473U, // SCVTFv2f32 |
| 7657 | 1615008582U, // SCVTFv2f64 |
| 7658 | 1615017473U, // SCVTFv2i32_shift |
| 7659 | 1615008582U, // SCVTFv2i64_shift |
| 7660 | 1615010779U, // SCVTFv4f16 |
| 7661 | 1615019479U, // SCVTFv4f32 |
| 7662 | 1615010779U, // SCVTFv4i16_shift |
| 7663 | 1615019479U, // SCVTFv4i32_shift |
| 7664 | 1615012697U, // SCVTFv8f16 |
| 7665 | 1615012697U, // SCVTFv8i16_shift |
| 7666 | 2151789492U, // SDIVR_ZPmZ_D |
| 7667 | 2151855028U, // SDIVR_ZPmZ_S |
| 7668 | 4245417U, // SDIVWr |
| 7669 | 4245417U, // SDIVXr |
| 7670 | 2151794601U, // SDIV_ZPmZ_D |
| 7671 | 2151860137U, // SDIV_ZPmZ_S |
| 7672 | 3288811101U, // SDOT_VG2_M2Z2Z_BtoS |
| 7673 | 3288778333U, // SDOT_VG2_M2Z2Z_HtoD |
| 7674 | 3288811101U, // SDOT_VG2_M2Z2Z_HtoS |
| 7675 | 3288811101U, // SDOT_VG2_M2ZZI_BToS |
| 7676 | 3288811101U, // SDOT_VG2_M2ZZI_HToS |
| 7677 | 3288778333U, // SDOT_VG2_M2ZZI_HtoD |
| 7678 | 3288811101U, // SDOT_VG2_M2ZZ_BtoS |
| 7679 | 3288778333U, // SDOT_VG2_M2ZZ_HtoD |
| 7680 | 3288811101U, // SDOT_VG2_M2ZZ_HtoS |
| 7681 | 3825682013U, // SDOT_VG4_M4Z4Z_BtoS |
| 7682 | 3825649245U, // SDOT_VG4_M4Z4Z_HtoD |
| 7683 | 3825682013U, // SDOT_VG4_M4Z4Z_HtoS |
| 7684 | 3825682013U, // SDOT_VG4_M4ZZI_BToS |
| 7685 | 3825682013U, // SDOT_VG4_M4ZZI_HToS |
| 7686 | 3825649245U, // SDOT_VG4_M4ZZI_HtoD |
| 7687 | 3825682013U, // SDOT_VG4_M4ZZ_BtoS |
| 7688 | 3825649245U, // SDOT_VG4_M4ZZ_HtoD |
| 7689 | 3825682013U, // SDOT_VG4_M4ZZ_HtoS |
| 7690 | 1078052445U, // SDOT_ZZZI_D |
| 7691 | 1078117981U, // SDOT_ZZZI_HtoS |
| 7692 | 541247069U, // SDOT_ZZZI_S |
| 7693 | 1078052445U, // SDOT_ZZZ_D |
| 7694 | 1078117981U, // SDOT_ZZZ_HtoS |
| 7695 | 541247069U, // SDOT_ZZZ_S |
| 7696 | 1615087197U, // SDOTlanev16i8 |
| 7697 | 1615087197U, // SDOTlanev8i8 |
| 7698 | 20940U, // SDOTv16i8 |
| 7699 | 20940U, // SDOTv8i8 |
| 7700 | 2151754942U, // SEL_PPPP |
| 7701 | 176467134U, // SEL_VG2_2ZC2Z2Z_B |
| 7702 | 176499902U, // SEL_VG2_2ZC2Z2Z_D |
| 7703 | 176532670U, // SEL_VG2_2ZC2Z2Z_H |
| 7704 | 176565438U, // SEL_VG2_2ZC2Z2Z_S |
| 7705 | 176467134U, // SEL_VG4_4ZC4Z4Z_B |
| 7706 | 176499902U, // SEL_VG4_4ZC4Z4Z_D |
| 7707 | 176532670U, // SEL_VG4_4ZC4Z4Z_H |
| 7708 | 176565438U, // SEL_VG4_4ZC4Z4Z_S |
| 7709 | 2151754942U, // SEL_ZPZZ_B |
| 7710 | 2151787710U, // SEL_ZPZZ_D |
| 7711 | 29502654U, // SEL_ZPZZ_H |
| 7712 | 2151853246U, // SEL_ZPZZ_S |
| 7713 | 278842479U, // SETE |
| 7714 | 278842541U, // SETEN |
| 7715 | 278843429U, // SETET |
| 7716 | 278842903U, // SETETN |
| 7717 | 19372U, // SETF16 |
| 7718 | 19422U, // SETF8 |
| 7719 | 20891U, // SETFFR |
| 7720 | 278842501U, // SETGM |
| 7721 | 278842566U, // SETGMN |
| 7722 | 278843454U, // SETGMT |
| 7723 | 278842931U, // SETGMTN |
| 7724 | 278843389U, // SETGP |
| 7725 | 278842600U, // SETGPN |
| 7726 | 278843488U, // SETGPT |
| 7727 | 278842969U, // SETGPTN |
| 7728 | 278842509U, // SETM |
| 7729 | 278842575U, // SETMN |
| 7730 | 278843463U, // SETMT |
| 7731 | 278842941U, // SETMTN |
| 7732 | 278843397U, // SETP |
| 7733 | 278842609U, // SETPN |
| 7734 | 278843497U, // SETPT |
| 7735 | 278842979U, // SETPTN |
| 7736 | 1615445239U, // SHA1Crrr |
| 7737 | 4233675U, // SHA1Hrr |
| 7738 | 1615445904U, // SHA1Mrrr |
| 7739 | 1615445995U, // SHA1Prrr |
| 7740 | 1615084046U, // SHA1SU0rrr |
| 7741 | 1615084110U, // SHA1SU1rr |
| 7742 | 1615444598U, // SHA256H2rrr |
| 7743 | 1615445502U, // SHA256Hrrr |
| 7744 | 1615084058U, // SHA256SU0rr |
| 7745 | 1615084122U, // SHA256SU1rrr |
| 7746 | 1615434605U, // SHA512H |
| 7747 | 1615434056U, // SHA512H2 |
| 7748 | 1615073544U, // SHA512SU0 |
| 7749 | 1615073585U, // SHA512SU1 |
| 7750 | 2151749589U, // SHADD_ZPmZ_B |
| 7751 | 2151782357U, // SHADD_ZPmZ_D |
| 7752 | 2713851861U, // SHADD_ZPmZ_H |
| 7753 | 2151847893U, // SHADD_ZPmZ_S |
| 7754 | 1615004967U, // SHADDv16i8 |
| 7755 | 1615017344U, // SHADDv2i32 |
| 7756 | 1615010673U, // SHADDv4i16 |
| 7757 | 1615019341U, // SHADDv4i32 |
| 7758 | 1615012591U, // SHADDv8i16 |
| 7759 | 1615005861U, // SHADDv8i8 |
| 7760 | 1615012050U, // SHLLv16i8 |
| 7761 | 1615008871U, // SHLLv2i32 |
| 7762 | 1615019828U, // SHLLv4i16 |
| 7763 | 1615008209U, // SHLLv4i32 |
| 7764 | 1615018751U, // SHLLv8i16 |
| 7765 | 1615013022U, // SHLLv8i8 |
| 7766 | 4238547U, // SHLd |
| 7767 | 1615005122U, // SHLv16i8_shift |
| 7768 | 1615017619U, // SHLv2i32_shift |
| 7769 | 1615008792U, // SHLv2i64_shift |
| 7770 | 1615010925U, // SHLv4i16_shift |
| 7771 | 1615019749U, // SHLv4i32_shift |
| 7772 | 1615012943U, // SHLv8i16_shift |
| 7773 | 1615005983U, // SHLv8i8_shift |
| 7774 | 3762359775U, // SHRNB_ZZI_B |
| 7775 | 21106143U, // SHRNB_ZZI_H |
| 7776 | 541232607U, // SHRNB_ZZI_S |
| 7777 | 1078019563U, // SHRNT_ZZI_B |
| 7778 | 25314795U, // SHRNT_ZZI_H |
| 7779 | 2151859691U, // SHRNT_ZZI_S |
| 7780 | 1615070132U, // SHRNv16i8_shift |
| 7781 | 1615017800U, // SHRNv2i32_shift |
| 7782 | 1615011106U, // SHRNv4i16_shift |
| 7783 | 1615084404U, // SHRNv4i32_shift |
| 7784 | 1615077714U, // SHRNv8i16_shift |
| 7785 | 1615006120U, // SHRNv8i8_shift |
| 7786 | 2151756349U, // SHSUBR_ZPmZ_B |
| 7787 | 2151789117U, // SHSUBR_ZPmZ_D |
| 7788 | 2713858621U, // SHSUBR_ZPmZ_H |
| 7789 | 2151854653U, // SHSUBR_ZPmZ_S |
| 7790 | 2151747482U, // SHSUB_ZPmZ_B |
| 7791 | 2151780250U, // SHSUB_ZPmZ_D |
| 7792 | 2713849754U, // SHSUB_ZPmZ_H |
| 7793 | 2151845786U, // SHSUB_ZPmZ_S |
| 7794 | 1615004847U, // SHSUBv16i8 |
| 7795 | 1615017228U, // SHSUBv2i32 |
| 7796 | 1615010557U, // SHSUBv4i16 |
| 7797 | 1615019215U, // SHSUBv4i32 |
| 7798 | 1615012475U, // SHSUBv8i16 |
| 7799 | 1615005773U, // SHSUBv8i8 |
| 7800 | 541141793U, // SLI_ZZI_B |
| 7801 | 2151787297U, // SLI_ZZI_D |
| 7802 | 84028193U, // SLI_ZZI_H |
| 7803 | 2688723745U, // SLI_ZZI_S |
| 7804 | 1615440673U, // SLId |
| 7805 | 1615070628U, // SLIv16i8_shift |
| 7806 | 1615083108U, // SLIv2i32_shift |
| 7807 | 1615074178U, // SLIv2i64_shift |
| 7808 | 1615076414U, // SLIv4i16_shift |
| 7809 | 1615085126U, // SLIv4i32_shift |
| 7810 | 1615078332U, // SLIv8i16_shift |
| 7811 | 1615071492U, // SLIv8i8_shift |
| 7812 | 1615084136U, // SM3PARTW1 |
| 7813 | 1615084584U, // SM3PARTW2 |
| 7814 | 1615018563U, // SM3SS1 |
| 7815 | 1615084608U, // SM3TT1A |
| 7816 | 1615084718U, // SM3TT1B |
| 7817 | 1615084620U, // SM3TT2A |
| 7818 | 1615084730U, // SM3TT2B |
| 7819 | 1615084919U, // SM4E |
| 7820 | 541247992U, // SM4EKEY_ZZZ_S |
| 7821 | 1615020730U, // SM4ENCKEY |
| 7822 | 541235261U, // SM4E_ZZZ_S |
| 7823 | 4238499U, // SMADDLrrr |
| 7824 | 2151756146U, // SMAXP_ZPmZ_B |
| 7825 | 2151788914U, // SMAXP_ZPmZ_D |
| 7826 | 2713858418U, // SMAXP_ZPmZ_H |
| 7827 | 2151854450U, // SMAXP_ZPmZ_S |
| 7828 | 1615005297U, // SMAXPv16i8 |
| 7829 | 1615018048U, // SMAXPv2i32 |
| 7830 | 1615011365U, // SMAXPv4i16 |
| 7831 | 1615020158U, // SMAXPv4i32 |
| 7832 | 1615013342U, // SMAXPv8i16 |
| 7833 | 1615006265U, // SMAXPv8i8 |
| 7834 | 2181253177U, // SMAXQV_VPZ_B |
| 7835 | 2185447481U, // SMAXQV_VPZ_D |
| 7836 | 2189641785U, // SMAXQV_VPZ_H |
| 7837 | 2193836089U, // SMAXQV_VPZ_S |
| 7838 | 510038U, // SMAXV_VPZ_B |
| 7839 | 3301460054U, // SMAXV_VPZ_D |
| 7840 | 3305687126U, // SMAXV_VPZ_H |
| 7841 | 3246999638U, // SMAXV_VPZ_S |
| 7842 | 1614841724U, // SMAXVv16i8v |
| 7843 | 1614847953U, // SMAXVv4i16v |
| 7844 | 1614856746U, // SMAXVv4i32v |
| 7845 | 1614849930U, // SMAXVv8i16v |
| 7846 | 1614842666U, // SMAXVv8i8v |
| 7847 | 4245927U, // SMAXWri |
| 7848 | 4245927U, // SMAXWrr |
| 7849 | 4245927U, // SMAXXri |
| 7850 | 4245927U, // SMAXXrr |
| 7851 | 50645415U, // SMAX_VG2_2Z2Z_B |
| 7852 | 54872487U, // SMAX_VG2_2Z2Z_D |
| 7853 | 59099559U, // SMAX_VG2_2Z2Z_H |
| 7854 | 63326631U, // SMAX_VG2_2Z2Z_S |
| 7855 | 50645415U, // SMAX_VG2_2ZZ_B |
| 7856 | 54872487U, // SMAX_VG2_2ZZ_D |
| 7857 | 59099559U, // SMAX_VG2_2ZZ_H |
| 7858 | 63326631U, // SMAX_VG2_2ZZ_S |
| 7859 | 50645415U, // SMAX_VG4_4Z4Z_B |
| 7860 | 54872487U, // SMAX_VG4_4Z4Z_D |
| 7861 | 59099559U, // SMAX_VG4_4Z4Z_H |
| 7862 | 63326631U, // SMAX_VG4_4Z4Z_S |
| 7863 | 50645415U, // SMAX_VG4_4ZZ_B |
| 7864 | 54872487U, // SMAX_VG4_4ZZ_D |
| 7865 | 59099559U, // SMAX_VG4_4ZZ_H |
| 7866 | 63326631U, // SMAX_VG4_4ZZ_S |
| 7867 | 4278695U, // SMAX_ZI_B |
| 7868 | 541182375U, // SMAX_ZI_D |
| 7869 | 71453095U, // SMAX_ZI_H |
| 7870 | 541247911U, // SMAX_ZI_S |
| 7871 | 2151762343U, // SMAX_ZPmZ_B |
| 7872 | 2151795111U, // SMAX_ZPmZ_D |
| 7873 | 2713864615U, // SMAX_ZPmZ_H |
| 7874 | 2151860647U, // SMAX_ZPmZ_S |
| 7875 | 1615005596U, // SMAXv16i8 |
| 7876 | 1615018426U, // SMAXv2i32 |
| 7877 | 1615011832U, // SMAXv4i16 |
| 7878 | 1615020691U, // SMAXv4i32 |
| 7879 | 1615013849U, // SMAXv8i16 |
| 7880 | 1615006526U, // SMAXv8i8 |
| 7881 | 757814U, // SMC |
| 7882 | 2151755952U, // SMINP_ZPmZ_B |
| 7883 | 2151788720U, // SMINP_ZPmZ_D |
| 7884 | 2713858224U, // SMINP_ZPmZ_H |
| 7885 | 2151854256U, // SMINP_ZPmZ_S |
| 7886 | 1615005266U, // SMINPv16i8 |
| 7887 | 1615017999U, // SMINPv2i32 |
| 7888 | 1615011316U, // SMINPv4i16 |
| 7889 | 1615020109U, // SMINPv4i32 |
| 7890 | 1615013293U, // SMINPv8i16 |
| 7891 | 1615006237U, // SMINPv8i8 |
| 7892 | 2181253146U, // SMINQV_VPZ_B |
| 7893 | 2185447450U, // SMINQV_VPZ_D |
| 7894 | 2189641754U, // SMINQV_VPZ_H |
| 7895 | 2193836058U, // SMINQV_VPZ_S |
| 7896 | 509902U, // SMINV_VPZ_B |
| 7897 | 3301459918U, // SMINV_VPZ_D |
| 7898 | 3305686990U, // SMINV_VPZ_H |
| 7899 | 3246999502U, // SMINV_VPZ_S |
| 7900 | 1614841702U, // SMINVv16i8v |
| 7901 | 1614847914U, // SMINVv4i16v |
| 7902 | 1614856707U, // SMINVv4i32v |
| 7903 | 1614849891U, // SMINVv8i16v |
| 7904 | 1614842646U, // SMINVv8i8v |
| 7905 | 4239155U, // SMINWri |
| 7906 | 4239155U, // SMINWrr |
| 7907 | 4239155U, // SMINXri |
| 7908 | 4239155U, // SMINXrr |
| 7909 | 50638643U, // SMIN_VG2_2Z2Z_B |
| 7910 | 54865715U, // SMIN_VG2_2Z2Z_D |
| 7911 | 59092787U, // SMIN_VG2_2Z2Z_H |
| 7912 | 63319859U, // SMIN_VG2_2Z2Z_S |
| 7913 | 50638643U, // SMIN_VG2_2ZZ_B |
| 7914 | 54865715U, // SMIN_VG2_2ZZ_D |
| 7915 | 59092787U, // SMIN_VG2_2ZZ_H |
| 7916 | 63319859U, // SMIN_VG2_2ZZ_S |
| 7917 | 50638643U, // SMIN_VG4_4Z4Z_B |
| 7918 | 54865715U, // SMIN_VG4_4Z4Z_D |
| 7919 | 59092787U, // SMIN_VG4_4Z4Z_H |
| 7920 | 63319859U, // SMIN_VG4_4Z4Z_S |
| 7921 | 50638643U, // SMIN_VG4_4ZZ_B |
| 7922 | 54865715U, // SMIN_VG4_4ZZ_D |
| 7923 | 59092787U, // SMIN_VG4_4ZZ_H |
| 7924 | 63319859U, // SMIN_VG4_4ZZ_S |
| 7925 | 4271923U, // SMIN_ZI_B |
| 7926 | 541175603U, // SMIN_ZI_D |
| 7927 | 71446323U, // SMIN_ZI_H |
| 7928 | 541241139U, // SMIN_ZI_S |
| 7929 | 2151755571U, // SMIN_ZPmZ_B |
| 7930 | 2151788339U, // SMIN_ZPmZ_D |
| 7931 | 2713857843U, // SMIN_ZPmZ_H |
| 7932 | 2151853875U, // SMIN_ZPmZ_S |
| 7933 | 1615005227U, // SMINv16i8 |
| 7934 | 1615017780U, // SMINv2i32 |
| 7935 | 1615011086U, // SMINv4i16 |
| 7936 | 1615019982U, // SMINv4i32 |
| 7937 | 1615013176U, // SMINv8i16 |
| 7938 | 1615006100U, // SMINv8i8 |
| 7939 | 2688650333U, // SMLALB_ZZZI_D |
| 7940 | 1078103133U, // SMLALB_ZZZI_S |
| 7941 | 2688650333U, // SMLALB_ZZZ_D |
| 7942 | 146934877U, // SMLALB_ZZZ_H |
| 7943 | 1078103133U, // SMLALB_ZZZ_S |
| 7944 | 3376885010U, // SMLALL_MZZI_BtoS |
| 7945 | 3376852242U, // SMLALL_MZZI_HtoD |
| 7946 | 3376885010U, // SMLALL_MZZ_BtoS |
| 7947 | 3376852242U, // SMLALL_MZZ_HtoD |
| 7948 | 3376885010U, // SMLALL_VG2_M2Z2Z_BtoS |
| 7949 | 3376852242U, // SMLALL_VG2_M2Z2Z_HtoD |
| 7950 | 3376885010U, // SMLALL_VG2_M2ZZI_BtoS |
| 7951 | 3376852242U, // SMLALL_VG2_M2ZZI_HtoD |
| 7952 | 3913755922U, // SMLALL_VG2_M2ZZ_BtoS |
| 7953 | 3913723154U, // SMLALL_VG2_M2ZZ_HtoD |
| 7954 | 3913755922U, // SMLALL_VG4_M4Z4Z_BtoS |
| 7955 | 3913723154U, // SMLALL_VG4_M4Z4Z_HtoD |
| 7956 | 3913755922U, // SMLALL_VG4_M4ZZI_BtoS |
| 7957 | 3913723154U, // SMLALL_VG4_M4ZZI_HtoD |
| 7958 | 155659538U, // SMLALL_VG4_M4ZZ_BtoS |
| 7959 | 155626770U, // SMLALL_VG4_M4ZZ_HtoD |
| 7960 | 2688664813U, // SMLALT_ZZZI_D |
| 7961 | 1078117613U, // SMLALT_ZZZI_S |
| 7962 | 2688664813U, // SMLALT_ZZZ_D |
| 7963 | 146949357U, // SMLALT_ZZZ_H |
| 7964 | 1078117613U, // SMLALT_ZZZ_S |
| 7965 | 3313970033U, // SMLAL_MZZI_HtoS |
| 7966 | 3313970033U, // SMLAL_MZZ_HtoS |
| 7967 | 3313970033U, // SMLAL_VG2_M2Z2Z_HtoS |
| 7968 | 3313970033U, // SMLAL_VG2_M2ZZI_S |
| 7969 | 3313970033U, // SMLAL_VG2_M2ZZ_HtoS |
| 7970 | 3850840945U, // SMLAL_VG4_M4Z4Z_HtoS |
| 7971 | 3850840945U, // SMLAL_VG4_M4ZZI_HtoS |
| 7972 | 3850840945U, // SMLAL_VG4_M4ZZ_HtoS |
| 7973 | 1615077497U, // SMLALv16i8_v8i16 |
| 7974 | 1615074246U, // SMLALv2i32_indexed |
| 7975 | 1615074246U, // SMLALv2i32_v2i64 |
| 7976 | 1615085203U, // SMLALv4i16_indexed |
| 7977 | 1615085203U, // SMLALv4i16_v4i32 |
| 7978 | 1615073656U, // SMLALv4i32_indexed |
| 7979 | 1615073656U, // SMLALv4i32_v2i64 |
| 7980 | 1615084198U, // SMLALv8i16_indexed |
| 7981 | 1615084198U, // SMLALv8i16_v4i32 |
| 7982 | 1615078397U, // SMLALv8i8_v8i16 |
| 7983 | 2688650631U, // SMLSLB_ZZZI_D |
| 7984 | 1078103431U, // SMLSLB_ZZZI_S |
| 7985 | 2688650631U, // SMLSLB_ZZZ_D |
| 7986 | 146935175U, // SMLSLB_ZZZ_H |
| 7987 | 1078103431U, // SMLSLB_ZZZ_S |
| 7988 | 3376885027U, // SMLSLL_MZZI_BtoS |
| 7989 | 3376852259U, // SMLSLL_MZZI_HtoD |
| 7990 | 3376885027U, // SMLSLL_MZZ_BtoS |
| 7991 | 3376852259U, // SMLSLL_MZZ_HtoD |
| 7992 | 3376885027U, // SMLSLL_VG2_M2Z2Z_BtoS |
| 7993 | 3376852259U, // SMLSLL_VG2_M2Z2Z_HtoD |
| 7994 | 3376885027U, // SMLSLL_VG2_M2ZZI_BtoS |
| 7995 | 3376852259U, // SMLSLL_VG2_M2ZZI_HtoD |
| 7996 | 3913755939U, // SMLSLL_VG2_M2ZZ_BtoS |
| 7997 | 3913723171U, // SMLSLL_VG2_M2ZZ_HtoD |
| 7998 | 3913755939U, // SMLSLL_VG4_M4Z4Z_BtoS |
| 7999 | 3913723171U, // SMLSLL_VG4_M4Z4Z_HtoD |
| 8000 | 3913755939U, // SMLSLL_VG4_M4ZZI_BtoS |
| 8001 | 3913723171U, // SMLSLL_VG4_M4ZZI_HtoD |
| 8002 | 155659555U, // SMLSLL_VG4_M4ZZ_BtoS |
| 8003 | 155626787U, // SMLSLL_VG4_M4ZZ_HtoD |
| 8004 | 2688664988U, // SMLSLT_ZZZI_D |
| 8005 | 1078117788U, // SMLSLT_ZZZI_S |
| 8006 | 2688664988U, // SMLSLT_ZZZ_D |
| 8007 | 146949532U, // SMLSLT_ZZZ_H |
| 8008 | 1078117788U, // SMLSLT_ZZZ_S |
| 8009 | 3313970723U, // SMLSL_MZZI_HtoS |
| 8010 | 3313970723U, // SMLSL_MZZ_HtoS |
| 8011 | 3313970723U, // SMLSL_VG2_M2Z2Z_HtoS |
| 8012 | 3313970723U, // SMLSL_VG2_M2ZZI_S |
| 8013 | 3313970723U, // SMLSL_VG2_M2ZZ_HtoS |
| 8014 | 3850841635U, // SMLSL_VG4_M4Z4Z_HtoS |
| 8015 | 3850841635U, // SMLSL_VG4_M4ZZI_HtoS |
| 8016 | 3850841635U, // SMLSL_VG4_M4ZZ_HtoS |
| 8017 | 1615077640U, // SMLSLv16i8_v8i16 |
| 8018 | 1615074470U, // SMLSLv2i32_indexed |
| 8019 | 1615074470U, // SMLSLv2i32_v2i64 |
| 8020 | 1615085427U, // SMLSLv4i16_indexed |
| 8021 | 1615085427U, // SMLSLv4i16_v4i32 |
| 8022 | 1615073814U, // SMLSLv4i32_indexed |
| 8023 | 1615073814U, // SMLSLv4i32_v2i64 |
| 8024 | 1615084356U, // SMLSLv8i16_indexed |
| 8025 | 1615084356U, // SMLSLv8i16_v4i32 |
| 8026 | 1615078607U, // SMLSLv8i8_v8i16 |
| 8027 | 20730U, // SMMLA |
| 8028 | 541229419U, // SMMLA_ZZZ |
| 8029 | 96698793U, // SMOPA_MPPZZ_D |
| 8030 | 96698793U, // SMOPA_MPPZZ_HtoS |
| 8031 | 159613353U, // SMOPA_MPPZZ_S |
| 8032 | 96715737U, // SMOPS_MPPZZ_D |
| 8033 | 96715737U, // SMOPS_MPPZZ_HtoS |
| 8034 | 159630297U, // SMOPS_MPPZZ_S |
| 8035 | 1614846386U, // SMOVvi16to32 |
| 8036 | 1614846386U, // SMOVvi16to32_idx0 |
| 8037 | 1614846386U, // SMOVvi16to64 |
| 8038 | 1614846386U, // SMOVvi16to64_idx0 |
| 8039 | 1614853204U, // SMOVvi32to64 |
| 8040 | 1614853204U, // SMOVvi32to64_idx0 |
| 8041 | 1614840569U, // SMOVvi8to32 |
| 8042 | 1614840569U, // SMOVvi8to32_idx0 |
| 8043 | 1614840569U, // SMOVvi8to64 |
| 8044 | 1614840569U, // SMOVvi8to64_idx0 |
| 8045 | 4238475U, // SMSUBLrrr |
| 8046 | 2151754110U, // SMULH_ZPmZ_B |
| 8047 | 2151786878U, // SMULH_ZPmZ_D |
| 8048 | 2713856382U, // SMULH_ZPmZ_H |
| 8049 | 2151852414U, // SMULH_ZPmZ_S |
| 8050 | 4270462U, // SMULH_ZZZ_B |
| 8051 | 541174142U, // SMULH_ZZZ_D |
| 8052 | 71444862U, // SMULH_ZZZ_H |
| 8053 | 541239678U, // SMULH_ZZZ_S |
| 8054 | 4237694U, // SMULHrr |
| 8055 | 541166896U, // SMULLB_ZZZI_D |
| 8056 | 3762457904U, // SMULLB_ZZZI_S |
| 8057 | 541166896U, // SMULLB_ZZZ_D |
| 8058 | 88214832U, // SMULLB_ZZZ_H |
| 8059 | 3762457904U, // SMULLB_ZZZ_S |
| 8060 | 541181291U, // SMULLT_ZZZI_D |
| 8061 | 3762472299U, // SMULLT_ZZZI_S |
| 8062 | 541181291U, // SMULLT_ZZZ_D |
| 8063 | 88229227U, // SMULLT_ZZZ_H |
| 8064 | 3762472299U, // SMULLT_ZZZ_S |
| 8065 | 1615012082U, // SMULLv16i8_v8i16 |
| 8066 | 1615008902U, // SMULLv2i32_indexed |
| 8067 | 1615008902U, // SMULLv2i32_v2i64 |
| 8068 | 1615019859U, // SMULLv4i16_indexed |
| 8069 | 1615019859U, // SMULLv4i16_v4i32 |
| 8070 | 1615008243U, // SMULLv4i32_indexed |
| 8071 | 1615008243U, // SMULLv4i32_v2i64 |
| 8072 | 1615018785U, // SMULLv8i16_indexed |
| 8073 | 1615018785U, // SMULLv8i16_v4i32 |
| 8074 | 1615013051U, // SMULLv8i8_v8i16 |
| 8075 | 2151749699U, // SPLICE_ZPZZ_B |
| 8076 | 2151782467U, // SPLICE_ZPZZ_D |
| 8077 | 29497411U, // SPLICE_ZPZZ_H |
| 8078 | 2151848003U, // SPLICE_ZPZZ_S |
| 8079 | 2151749699U, // SPLICE_ZPZ_B |
| 8080 | 2151782467U, // SPLICE_ZPZ_D |
| 8081 | 29497411U, // SPLICE_ZPZ_H |
| 8082 | 2151848003U, // SPLICE_ZPZ_S |
| 8083 | 541147937U, // SQABS_ZPmZ_B |
| 8084 | 541180705U, // SQABS_ZPmZ_D |
| 8085 | 1082278689U, // SQABS_ZPmZ_H |
| 8086 | 541246241U, // SQABS_ZPmZ_S |
| 8087 | 1615005389U, // SQABSv16i8 |
| 8088 | 4244257U, // SQABSv1i16 |
| 8089 | 4244257U, // SQABSv1i32 |
| 8090 | 4244257U, // SQABSv1i64 |
| 8091 | 4244257U, // SQABSv1i8 |
| 8092 | 1615018144U, // SQABSv2i32 |
| 8093 | 1615009219U, // SQABSv2i64 |
| 8094 | 1615011461U, // SQABSv4i16 |
| 8095 | 1615020254U, // SQABSv4i32 |
| 8096 | 1615013438U, // SQABSv8i16 |
| 8097 | 1615006348U, // SQABSv8i8 |
| 8098 | 4265971U, // SQADD_ZI_B |
| 8099 | 541169651U, // SQADD_ZI_D |
| 8100 | 71440371U, // SQADD_ZI_H |
| 8101 | 541235187U, // SQADD_ZI_S |
| 8102 | 2151749619U, // SQADD_ZPmZ_B |
| 8103 | 2151782387U, // SQADD_ZPmZ_D |
| 8104 | 2713851891U, // SQADD_ZPmZ_H |
| 8105 | 2151847923U, // SQADD_ZPmZ_S |
| 8106 | 4265971U, // SQADD_ZZZ_B |
| 8107 | 541169651U, // SQADD_ZZZ_D |
| 8108 | 71440371U, // SQADD_ZZZ_H |
| 8109 | 541235187U, // SQADD_ZZZ_S |
| 8110 | 1615004990U, // SQADDv16i8 |
| 8111 | 4233203U, // SQADDv1i16 |
| 8112 | 4233203U, // SQADDv1i32 |
| 8113 | 4233203U, // SQADDv1i64 |
| 8114 | 4233203U, // SQADDv1i8 |
| 8115 | 1615017365U, // SQADDv2i32 |
| 8116 | 1615008497U, // SQADDv2i64 |
| 8117 | 1615010694U, // SQADDv4i16 |
| 8118 | 1615019362U, // SQADDv4i32 |
| 8119 | 1615012612U, // SQADDv8i16 |
| 8120 | 1615005882U, // SQADDv8i8 |
| 8121 | 4265903U, // SQCADD_ZZI_B |
| 8122 | 541169583U, // SQCADD_ZZI_D |
| 8123 | 71440303U, // SQCADD_ZZI_H |
| 8124 | 541235119U, // SQCADD_ZZI_S |
| 8125 | 3284283273U, // SQCVTN_Z2Z_StoH |
| 8126 | 3275894665U, // SQCVTN_Z4Z_DtoH |
| 8127 | 2151755657U, // SQCVTN_Z4Z_StoB |
| 8128 | 3284283322U, // SQCVTUN_Z2Z_StoH |
| 8129 | 3275894714U, // SQCVTUN_Z4Z_DtoH |
| 8130 | 2151755706U, // SQCVTUN_Z4Z_StoB |
| 8131 | 3284289387U, // SQCVTU_Z2Z_StoH |
| 8132 | 3275900779U, // SQCVTU_Z4Z_DtoH |
| 8133 | 2151761771U, // SQCVTU_Z4Z_StoB |
| 8134 | 3284289267U, // SQCVT_Z2Z_StoH |
| 8135 | 3275900659U, // SQCVT_Z4Z_DtoH |
| 8136 | 2151761651U, // SQCVT_Z4Z_StoB |
| 8137 | 1077971929U, // SQDECB_XPiI |
| 8138 | 541101017U, // SQDECB_XPiWdI |
| 8139 | 1077974920U, // SQDECD_XPiI |
| 8140 | 541104008U, // SQDECD_XPiWdI |
| 8141 | 1078040456U, // SQDECD_ZPiI |
| 8142 | 1077979275U, // SQDECH_XPiI |
| 8143 | 541108363U, // SQDECH_XPiWdI |
| 8144 | 100804747U, // SQDECH_ZPiI |
| 8145 | 4239383U, // SQDECP_XPWd_B |
| 8146 | 541110295U, // SQDECP_XPWd_D |
| 8147 | 3762335767U, // SQDECP_XPWd_H |
| 8148 | 541110295U, // SQDECP_XPWd_S |
| 8149 | 4239383U, // SQDECP_XP_B |
| 8150 | 541110295U, // SQDECP_XP_D |
| 8151 | 3762335767U, // SQDECP_XP_H |
| 8152 | 541110295U, // SQDECP_XP_S |
| 8153 | 2151788567U, // SQDECP_ZP_D |
| 8154 | 3305254935U, // SQDECP_ZP_H |
| 8155 | 2688725015U, // SQDECP_ZP_S |
| 8156 | 1077987525U, // SQDECW_XPiI |
| 8157 | 541116613U, // SQDECW_XPiWdI |
| 8158 | 1078118597U, // SQDECW_ZPiI |
| 8159 | 2688664628U, // SQDMLALBT_ZZZ_D |
| 8160 | 146949172U, // SQDMLALBT_ZZZ_H |
| 8161 | 1078117428U, // SQDMLALBT_ZZZ_S |
| 8162 | 2688650314U, // SQDMLALB_ZZZI_D |
| 8163 | 1078103114U, // SQDMLALB_ZZZI_S |
| 8164 | 2688650314U, // SQDMLALB_ZZZ_D |
| 8165 | 146934858U, // SQDMLALB_ZZZ_H |
| 8166 | 1078103114U, // SQDMLALB_ZZZ_S |
| 8167 | 2688664794U, // SQDMLALT_ZZZI_D |
| 8168 | 1078117594U, // SQDMLALT_ZZZI_S |
| 8169 | 2688664794U, // SQDMLALT_ZZZ_D |
| 8170 | 146949338U, // SQDMLALT_ZZZ_H |
| 8171 | 1078117594U, // SQDMLALT_ZZZ_S |
| 8172 | 1615440736U, // SQDMLALi16 |
| 8173 | 1615440736U, // SQDMLALi32 |
| 8174 | 1615436154U, // SQDMLALv1i32_indexed |
| 8175 | 1615442972U, // SQDMLALv1i64_indexed |
| 8176 | 1615074234U, // SQDMLALv2i32_indexed |
| 8177 | 1615074234U, // SQDMLALv2i32_v2i64 |
| 8178 | 1615085191U, // SQDMLALv4i16_indexed |
| 8179 | 1615085191U, // SQDMLALv4i16_v4i32 |
| 8180 | 1615073643U, // SQDMLALv4i32_indexed |
| 8181 | 1615073643U, // SQDMLALv4i32_v2i64 |
| 8182 | 1615084185U, // SQDMLALv8i16_indexed |
| 8183 | 1615084185U, // SQDMLALv8i16_v4i32 |
| 8184 | 2688664667U, // SQDMLSLBT_ZZZ_D |
| 8185 | 146949211U, // SQDMLSLBT_ZZZ_H |
| 8186 | 1078117467U, // SQDMLSLBT_ZZZ_S |
| 8187 | 2688650612U, // SQDMLSLB_ZZZI_D |
| 8188 | 1078103412U, // SQDMLSLB_ZZZI_S |
| 8189 | 2688650612U, // SQDMLSLB_ZZZ_D |
| 8190 | 146935156U, // SQDMLSLB_ZZZ_H |
| 8191 | 1078103412U, // SQDMLSLB_ZZZ_S |
| 8192 | 2688664969U, // SQDMLSLT_ZZZI_D |
| 8193 | 1078117769U, // SQDMLSLT_ZZZI_S |
| 8194 | 2688664969U, // SQDMLSLT_ZZZ_D |
| 8195 | 146949513U, // SQDMLSLT_ZZZ_H |
| 8196 | 1078117769U, // SQDMLSLT_ZZZ_S |
| 8197 | 1615441426U, // SQDMLSLi16 |
| 8198 | 1615441426U, // SQDMLSLi32 |
| 8199 | 1615436176U, // SQDMLSLv1i32_indexed |
| 8200 | 1615442994U, // SQDMLSLv1i64_indexed |
| 8201 | 1615074458U, // SQDMLSLv2i32_indexed |
| 8202 | 1615074458U, // SQDMLSLv2i32_v2i64 |
| 8203 | 1615085415U, // SQDMLSLv4i16_indexed |
| 8204 | 1615085415U, // SQDMLSLv4i16_v4i32 |
| 8205 | 1615073801U, // SQDMLSLv4i32_indexed |
| 8206 | 1615073801U, // SQDMLSLv4i32_v2i64 |
| 8207 | 1615084343U, // SQDMLSLv8i16_indexed |
| 8208 | 1615084343U, // SQDMLSLv8i16_v4i32 |
| 8209 | 50637163U, // SQDMULH_VG2_2Z2Z_B |
| 8210 | 54864235U, // SQDMULH_VG2_2Z2Z_D |
| 8211 | 59091307U, // SQDMULH_VG2_2Z2Z_H |
| 8212 | 63318379U, // SQDMULH_VG2_2Z2Z_S |
| 8213 | 50637163U, // SQDMULH_VG2_2ZZ_B |
| 8214 | 54864235U, // SQDMULH_VG2_2ZZ_D |
| 8215 | 59091307U, // SQDMULH_VG2_2ZZ_H |
| 8216 | 63318379U, // SQDMULH_VG2_2ZZ_S |
| 8217 | 50637163U, // SQDMULH_VG4_4Z4Z_B |
| 8218 | 54864235U, // SQDMULH_VG4_4Z4Z_D |
| 8219 | 59091307U, // SQDMULH_VG4_4Z4Z_H |
| 8220 | 63318379U, // SQDMULH_VG4_4Z4Z_S |
| 8221 | 50637163U, // SQDMULH_VG4_4ZZ_B |
| 8222 | 54864235U, // SQDMULH_VG4_4ZZ_D |
| 8223 | 59091307U, // SQDMULH_VG4_4ZZ_H |
| 8224 | 63318379U, // SQDMULH_VG4_4ZZ_S |
| 8225 | 541174123U, // SQDMULH_ZZZI_D |
| 8226 | 71444843U, // SQDMULH_ZZZI_H |
| 8227 | 541239659U, // SQDMULH_ZZZI_S |
| 8228 | 4270443U, // SQDMULH_ZZZ_B |
| 8229 | 541174123U, // SQDMULH_ZZZ_D |
| 8230 | 71444843U, // SQDMULH_ZZZ_H |
| 8231 | 541239659U, // SQDMULH_ZZZ_S |
| 8232 | 4237675U, // SQDMULHv1i16 |
| 8233 | 4233559U, // SQDMULHv1i16_indexed |
| 8234 | 4237675U, // SQDMULHv1i32 |
| 8235 | 4240377U, // SQDMULHv1i32_indexed |
| 8236 | 1615017525U, // SQDMULHv2i32 |
| 8237 | 1615017525U, // SQDMULHv2i32_indexed |
| 8238 | 1615010831U, // SQDMULHv4i16 |
| 8239 | 1615010831U, // SQDMULHv4i16_indexed |
| 8240 | 1615019543U, // SQDMULHv4i32 |
| 8241 | 1615019543U, // SQDMULHv4i32_indexed |
| 8242 | 1615012749U, // SQDMULHv8i16 |
| 8243 | 1615012749U, // SQDMULHv8i16_indexed |
| 8244 | 541166878U, // SQDMULLB_ZZZI_D |
| 8245 | 3762457886U, // SQDMULLB_ZZZI_S |
| 8246 | 541166878U, // SQDMULLB_ZZZ_D |
| 8247 | 88214814U, // SQDMULLB_ZZZ_H |
| 8248 | 3762457886U, // SQDMULLB_ZZZ_S |
| 8249 | 541181273U, // SQDMULLT_ZZZI_D |
| 8250 | 3762472281U, // SQDMULLT_ZZZI_S |
| 8251 | 541181273U, // SQDMULLT_ZZZ_D |
| 8252 | 88229209U, // SQDMULLT_ZZZ_H |
| 8253 | 3762472281U, // SQDMULLT_ZZZ_S |
| 8254 | 4238643U, // SQDMULLi16 |
| 8255 | 4238643U, // SQDMULLi32 |
| 8256 | 4233605U, // SQDMULLv1i32_indexed |
| 8257 | 4240423U, // SQDMULLv1i64_indexed |
| 8258 | 1615008890U, // SQDMULLv2i32_indexed |
| 8259 | 1615008890U, // SQDMULLv2i32_v2i64 |
| 8260 | 1615019847U, // SQDMULLv4i16_indexed |
| 8261 | 1615019847U, // SQDMULLv4i16_v4i32 |
| 8262 | 1615008230U, // SQDMULLv4i32_indexed |
| 8263 | 1615008230U, // SQDMULLv4i32_v2i64 |
| 8264 | 1615018772U, // SQDMULLv8i16_indexed |
| 8265 | 1615018772U, // SQDMULLv8i16_v4i32 |
| 8266 | 1077971945U, // SQINCB_XPiI |
| 8267 | 541101033U, // SQINCB_XPiWdI |
| 8268 | 1077974936U, // SQINCD_XPiI |
| 8269 | 541104024U, // SQINCD_XPiWdI |
| 8270 | 1078040472U, // SQINCD_ZPiI |
| 8271 | 1077979291U, // SQINCH_XPiI |
| 8272 | 541108379U, // SQINCH_XPiWdI |
| 8273 | 100804763U, // SQINCH_ZPiI |
| 8274 | 4239399U, // SQINCP_XPWd_B |
| 8275 | 541110311U, // SQINCP_XPWd_D |
| 8276 | 3762335783U, // SQINCP_XPWd_H |
| 8277 | 541110311U, // SQINCP_XPWd_S |
| 8278 | 4239399U, // SQINCP_XP_B |
| 8279 | 541110311U, // SQINCP_XP_D |
| 8280 | 3762335783U, // SQINCP_XP_H |
| 8281 | 541110311U, // SQINCP_XP_S |
| 8282 | 2151788583U, // SQINCP_ZP_D |
| 8283 | 3305254951U, // SQINCP_ZP_H |
| 8284 | 2688725031U, // SQINCP_ZP_S |
| 8285 | 1077987541U, // SQINCW_XPiI |
| 8286 | 541116629U, // SQINCW_XPiWdI |
| 8287 | 1078118613U, // SQINCW_ZPiI |
| 8288 | 541137180U, // SQNEG_ZPmZ_B |
| 8289 | 541169948U, // SQNEG_ZPmZ_D |
| 8290 | 1082267932U, // SQNEG_ZPmZ_H |
| 8291 | 541235484U, // SQNEG_ZPmZ_S |
| 8292 | 1615005071U, // SQNEGv16i8 |
| 8293 | 4233500U, // SQNEGv1i16 |
| 8294 | 4233500U, // SQNEGv1i32 |
| 8295 | 4233500U, // SQNEGv1i64 |
| 8296 | 4233500U, // SQNEGv1i8 |
| 8297 | 1615017502U, // SQNEGv2i32 |
| 8298 | 1615008611U, // SQNEGv2i64 |
| 8299 | 1615010808U, // SQNEGv4i16 |
| 8300 | 1615019508U, // SQNEGv4i32 |
| 8301 | 1615012726U, // SQNEGv8i16 |
| 8302 | 1615005937U, // SQNEGv8i8 |
| 8303 | 84027420U, // SQRDCMLAH_ZZZI_H |
| 8304 | 2688722972U, // SQRDCMLAH_ZZZI_S |
| 8305 | 541141020U, // SQRDCMLAH_ZZZ_B |
| 8306 | 2151786524U, // SQRDCMLAH_ZZZ_D |
| 8307 | 84027420U, // SQRDCMLAH_ZZZ_H |
| 8308 | 2688722972U, // SQRDCMLAH_ZZZ_S |
| 8309 | 2151786535U, // SQRDMLAH_ZZZI_D |
| 8310 | 84027431U, // SQRDMLAH_ZZZI_H |
| 8311 | 2688722983U, // SQRDMLAH_ZZZI_S |
| 8312 | 541141031U, // SQRDMLAH_ZZZ_B |
| 8313 | 2151786535U, // SQRDMLAH_ZZZ_D |
| 8314 | 84027431U, // SQRDMLAH_ZZZ_H |
| 8315 | 2688722983U, // SQRDMLAH_ZZZ_S |
| 8316 | 1615439911U, // SQRDMLAHv1i16 |
| 8317 | 1615436107U, // SQRDMLAHv1i16_indexed |
| 8318 | 1615439911U, // SQRDMLAHv1i32 |
| 8319 | 1615442925U, // SQRDMLAHv1i32_indexed |
| 8320 | 1615083048U, // SQRDMLAHv2i32 |
| 8321 | 1615083048U, // SQRDMLAHv2i32_indexed |
| 8322 | 1615076354U, // SQRDMLAHv4i16 |
| 8323 | 1615076354U, // SQRDMLAHv4i16_indexed |
| 8324 | 1615085066U, // SQRDMLAHv4i32 |
| 8325 | 1615085066U, // SQRDMLAHv4i32_indexed |
| 8326 | 1615078272U, // SQRDMLAHv8i16 |
| 8327 | 1615078272U, // SQRDMLAHv8i16_indexed |
| 8328 | 2151787140U, // SQRDMLSH_ZZZI_D |
| 8329 | 84028036U, // SQRDMLSH_ZZZI_H |
| 8330 | 2688723588U, // SQRDMLSH_ZZZI_S |
| 8331 | 541141636U, // SQRDMLSH_ZZZ_B |
| 8332 | 2151787140U, // SQRDMLSH_ZZZ_D |
| 8333 | 84028036U, // SQRDMLSH_ZZZ_H |
| 8334 | 2688723588U, // SQRDMLSH_ZZZ_S |
| 8335 | 1615440516U, // SQRDMLSHv1i16 |
| 8336 | 1615436142U, // SQRDMLSHv1i16_indexed |
| 8337 | 1615440516U, // SQRDMLSHv1i32 |
| 8338 | 1615442960U, // SQRDMLSHv1i32_indexed |
| 8339 | 1615083086U, // SQRDMLSHv2i32 |
| 8340 | 1615083086U, // SQRDMLSHv2i32_indexed |
| 8341 | 1615076392U, // SQRDMLSHv4i16 |
| 8342 | 1615076392U, // SQRDMLSHv4i16_indexed |
| 8343 | 1615085104U, // SQRDMLSHv4i32 |
| 8344 | 1615085104U, // SQRDMLSHv4i32_indexed |
| 8345 | 1615078310U, // SQRDMLSHv8i16 |
| 8346 | 1615078310U, // SQRDMLSHv8i16_indexed |
| 8347 | 541174132U, // SQRDMULH_ZZZI_D |
| 8348 | 71444852U, // SQRDMULH_ZZZI_H |
| 8349 | 541239668U, // SQRDMULH_ZZZI_S |
| 8350 | 4270452U, // SQRDMULH_ZZZ_B |
| 8351 | 541174132U, // SQRDMULH_ZZZ_D |
| 8352 | 71444852U, // SQRDMULH_ZZZ_H |
| 8353 | 541239668U, // SQRDMULH_ZZZ_S |
| 8354 | 4237684U, // SQRDMULHv1i16 |
| 8355 | 4233570U, // SQRDMULHv1i16_indexed |
| 8356 | 4237684U, // SQRDMULHv1i32 |
| 8357 | 4240388U, // SQRDMULHv1i32_indexed |
| 8358 | 1615017537U, // SQRDMULHv2i32 |
| 8359 | 1615017537U, // SQRDMULHv2i32_indexed |
| 8360 | 1615010843U, // SQRDMULHv4i16 |
| 8361 | 1615010843U, // SQRDMULHv4i16_indexed |
| 8362 | 1615019555U, // SQRDMULHv4i32 |
| 8363 | 1615019555U, // SQRDMULHv4i32_indexed |
| 8364 | 1615012761U, // SQRDMULHv8i16 |
| 8365 | 1615012761U, // SQRDMULHv8i16_indexed |
| 8366 | 2151756540U, // SQRSHLR_ZPmZ_B |
| 8367 | 2151789308U, // SQRSHLR_ZPmZ_D |
| 8368 | 2713858812U, // SQRSHLR_ZPmZ_H |
| 8369 | 2151854844U, // SQRSHLR_ZPmZ_S |
| 8370 | 2151754975U, // SQRSHL_ZPmZ_B |
| 8371 | 2151787743U, // SQRSHL_ZPmZ_D |
| 8372 | 2713857247U, // SQRSHL_ZPmZ_H |
| 8373 | 2151853279U, // SQRSHL_ZPmZ_S |
| 8374 | 1615005142U, // SQRSHLv16i8 |
| 8375 | 4238559U, // SQRSHLv1i16 |
| 8376 | 4238559U, // SQRSHLv1i32 |
| 8377 | 4238559U, // SQRSHLv1i64 |
| 8378 | 4238559U, // SQRSHLv1i8 |
| 8379 | 1615017637U, // SQRSHLv2i32 |
| 8380 | 1615008810U, // SQRSHLv2i64 |
| 8381 | 1615010943U, // SQRSHLv4i16 |
| 8382 | 1615019767U, // SQRSHLv4i32 |
| 8383 | 1615012961U, // SQRSHLv8i16 |
| 8384 | 1615006001U, // SQRSHLv8i8 |
| 8385 | 3762359791U, // SQRSHRNB_ZZI_B |
| 8386 | 21106159U, // SQRSHRNB_ZZI_H |
| 8387 | 541232623U, // SQRSHRNB_ZZI_S |
| 8388 | 1078019579U, // SQRSHRNT_ZZI_B |
| 8389 | 25314811U, // SQRSHRNT_ZZI_H |
| 8390 | 2151859707U, // SQRSHRNT_ZZI_S |
| 8391 | 2151755618U, // SQRSHRN_VG4_Z4ZI_B |
| 8392 | 54669154U, // SQRSHRN_VG4_Z4ZI_H |
| 8393 | 63057762U, // SQRSHRN_Z2ZI_StoH |
| 8394 | 4239202U, // SQRSHRNb |
| 8395 | 4239202U, // SQRSHRNh |
| 8396 | 4239202U, // SQRSHRNs |
| 8397 | 1615070156U, // SQRSHRNv16i8_shift |
| 8398 | 1615017820U, // SQRSHRNv2i32_shift |
| 8399 | 1615011126U, // SQRSHRNv4i16_shift |
| 8400 | 1615084426U, // SQRSHRNv4i32_shift |
| 8401 | 1615077736U, // SQRSHRNv8i16_shift |
| 8402 | 1615006140U, // SQRSHRNv8i8_shift |
| 8403 | 3762359845U, // SQRSHRUNB_ZZI_B |
| 8404 | 21106213U, // SQRSHRUNB_ZZI_H |
| 8405 | 541232677U, // SQRSHRUNB_ZZI_S |
| 8406 | 1078019634U, // SQRSHRUNT_ZZI_B |
| 8407 | 25314866U, // SQRSHRUNT_ZZI_H |
| 8408 | 2151859762U, // SQRSHRUNT_ZZI_S |
| 8409 | 2151755696U, // SQRSHRUN_VG4_Z4ZI_B |
| 8410 | 54669232U, // SQRSHRUN_VG4_Z4ZI_H |
| 8411 | 63057840U, // SQRSHRUN_Z2ZI_StoH |
| 8412 | 4239280U, // SQRSHRUNb |
| 8413 | 4239280U, // SQRSHRUNh |
| 8414 | 4239280U, // SQRSHRUNs |
| 8415 | 1615070232U, // SQRSHRUNv16i8_shift |
| 8416 | 1615017887U, // SQRSHRUNv2i32_shift |
| 8417 | 1615011204U, // SQRSHRUNv4i16_shift |
| 8418 | 1615084496U, // SQRSHRUNv4i32_shift |
| 8419 | 1615077818U, // SQRSHRUNv8i16_shift |
| 8420 | 1615006204U, // SQRSHRUNv8i8_shift |
| 8421 | 63063906U, // SQRSHRU_VG2_Z2ZI_H |
| 8422 | 2151761762U, // SQRSHRU_VG4_Z4ZI_B |
| 8423 | 54675298U, // SQRSHRU_VG4_Z4ZI_H |
| 8424 | 63058597U, // SQRSHR_VG2_Z2ZI_H |
| 8425 | 2151756453U, // SQRSHR_VG4_Z4ZI_B |
| 8426 | 54669989U, // SQRSHR_VG4_Z4ZI_H |
| 8427 | 2151756524U, // SQSHLR_ZPmZ_B |
| 8428 | 2151789292U, // SQSHLR_ZPmZ_D |
| 8429 | 2713858796U, // SQSHLR_ZPmZ_H |
| 8430 | 2151854828U, // SQSHLR_ZPmZ_S |
| 8431 | 2151761730U, // SQSHLU_ZPmI_B |
| 8432 | 2151794498U, // SQSHLU_ZPmI_D |
| 8433 | 2713864002U, // SQSHLU_ZPmI_H |
| 8434 | 2151860034U, // SQSHLU_ZPmI_S |
| 8435 | 4245314U, // SQSHLUb |
| 8436 | 4245314U, // SQSHLUd |
| 8437 | 4245314U, // SQSHLUh |
| 8438 | 4245314U, // SQSHLUs |
| 8439 | 1615005496U, // SQSHLUv16i8_shift |
| 8440 | 1615018308U, // SQSHLUv2i32_shift |
| 8441 | 1615009375U, // SQSHLUv2i64_shift |
| 8442 | 1615011625U, // SQSHLUv4i16_shift |
| 8443 | 1615020418U, // SQSHLUv4i32_shift |
| 8444 | 1615013602U, // SQSHLUv8i16_shift |
| 8445 | 1615006444U, // SQSHLUv8i8_shift |
| 8446 | 2151754961U, // SQSHL_ZPmI_B |
| 8447 | 2151787729U, // SQSHL_ZPmI_D |
| 8448 | 2713857233U, // SQSHL_ZPmI_H |
| 8449 | 2151853265U, // SQSHL_ZPmI_S |
| 8450 | 2151754961U, // SQSHL_ZPmZ_B |
| 8451 | 2151787729U, // SQSHL_ZPmZ_D |
| 8452 | 2713857233U, // SQSHL_ZPmZ_H |
| 8453 | 2151853265U, // SQSHL_ZPmZ_S |
| 8454 | 4238545U, // SQSHLb |
| 8455 | 4238545U, // SQSHLd |
| 8456 | 4238545U, // SQSHLh |
| 8457 | 4238545U, // SQSHLs |
| 8458 | 1615005120U, // SQSHLv16i8 |
| 8459 | 1615005120U, // SQSHLv16i8_shift |
| 8460 | 4238545U, // SQSHLv1i16 |
| 8461 | 4238545U, // SQSHLv1i32 |
| 8462 | 4238545U, // SQSHLv1i64 |
| 8463 | 4238545U, // SQSHLv1i8 |
| 8464 | 1615017617U, // SQSHLv2i32 |
| 8465 | 1615017617U, // SQSHLv2i32_shift |
| 8466 | 1615008790U, // SQSHLv2i64 |
| 8467 | 1615008790U, // SQSHLv2i64_shift |
| 8468 | 1615010923U, // SQSHLv4i16 |
| 8469 | 1615010923U, // SQSHLv4i16_shift |
| 8470 | 1615019747U, // SQSHLv4i32 |
| 8471 | 1615019747U, // SQSHLv4i32_shift |
| 8472 | 1615012941U, // SQSHLv8i16 |
| 8473 | 1615012941U, // SQSHLv8i16_shift |
| 8474 | 1615005981U, // SQSHLv8i8 |
| 8475 | 1615005981U, // SQSHLv8i8_shift |
| 8476 | 3762359773U, // SQSHRNB_ZZI_B |
| 8477 | 21106141U, // SQSHRNB_ZZI_H |
| 8478 | 541232605U, // SQSHRNB_ZZI_S |
| 8479 | 1078019561U, // SQSHRNT_ZZI_B |
| 8480 | 25314793U, // SQSHRNT_ZZI_H |
| 8481 | 2151859689U, // SQSHRNT_ZZI_S |
| 8482 | 4239186U, // SQSHRNb |
| 8483 | 4239186U, // SQSHRNh |
| 8484 | 4239186U, // SQSHRNs |
| 8485 | 1615070130U, // SQSHRNv16i8_shift |
| 8486 | 1615017798U, // SQSHRNv2i32_shift |
| 8487 | 1615011104U, // SQSHRNv4i16_shift |
| 8488 | 1615084402U, // SQSHRNv4i32_shift |
| 8489 | 1615077712U, // SQSHRNv8i16_shift |
| 8490 | 1615006118U, // SQSHRNv8i8_shift |
| 8491 | 3762359835U, // SQSHRUNB_ZZI_B |
| 8492 | 21106203U, // SQSHRUNB_ZZI_H |
| 8493 | 541232667U, // SQSHRUNB_ZZI_S |
| 8494 | 1078019624U, // SQSHRUNT_ZZI_B |
| 8495 | 25314856U, // SQSHRUNT_ZZI_H |
| 8496 | 2151859752U, // SQSHRUNT_ZZI_S |
| 8497 | 4239271U, // SQSHRUNb |
| 8498 | 4239271U, // SQSHRUNh |
| 8499 | 4239271U, // SQSHRUNs |
| 8500 | 1615070218U, // SQSHRUNv16i8_shift |
| 8501 | 1615017875U, // SQSHRUNv2i32_shift |
| 8502 | 1615011192U, // SQSHRUNv4i16_shift |
| 8503 | 1615084483U, // SQSHRUNv4i32_shift |
| 8504 | 1615077805U, // SQSHRUNv8i16_shift |
| 8505 | 1615006192U, // SQSHRUNv8i8_shift |
| 8506 | 2151756365U, // SQSUBR_ZPmZ_B |
| 8507 | 2151789133U, // SQSUBR_ZPmZ_D |
| 8508 | 2713858637U, // SQSUBR_ZPmZ_H |
| 8509 | 2151854669U, // SQSUBR_ZPmZ_S |
| 8510 | 4263863U, // SQSUB_ZI_B |
| 8511 | 541167543U, // SQSUB_ZI_D |
| 8512 | 71438263U, // SQSUB_ZI_H |
| 8513 | 541233079U, // SQSUB_ZI_S |
| 8514 | 2151747511U, // SQSUB_ZPmZ_B |
| 8515 | 2151780279U, // SQSUB_ZPmZ_D |
| 8516 | 2713849783U, // SQSUB_ZPmZ_H |
| 8517 | 2151845815U, // SQSUB_ZPmZ_S |
| 8518 | 4263863U, // SQSUB_ZZZ_B |
| 8519 | 541167543U, // SQSUB_ZZZ_D |
| 8520 | 71438263U, // SQSUB_ZZZ_H |
| 8521 | 541233079U, // SQSUB_ZZZ_S |
| 8522 | 1615004869U, // SQSUBv16i8 |
| 8523 | 4231095U, // SQSUBv1i16 |
| 8524 | 4231095U, // SQSUBv1i32 |
| 8525 | 4231095U, // SQSUBv1i64 |
| 8526 | 4231095U, // SQSUBv1i8 |
| 8527 | 1615017248U, // SQSUBv2i32 |
| 8528 | 1615008448U, // SQSUBv2i64 |
| 8529 | 1615010577U, // SQSUBv4i16 |
| 8530 | 1615019235U, // SQSUBv4i32 |
| 8531 | 1615012495U, // SQSUBv8i16 |
| 8532 | 1615005793U, // SQSUBv8i8 |
| 8533 | 3762359819U, // SQXTNB_ZZ_B |
| 8534 | 3242331659U, // SQXTNB_ZZ_H |
| 8535 | 541232651U, // SQXTNB_ZZ_S |
| 8536 | 1078019608U, // SQXTNT_ZZ_B |
| 8537 | 3246540312U, // SQXTNT_ZZ_H |
| 8538 | 2151859736U, // SQXTNT_ZZ_S |
| 8539 | 1615070194U, // SQXTNv16i8 |
| 8540 | 4239257U, // SQXTNv1i16 |
| 8541 | 4239257U, // SQXTNv1i32 |
| 8542 | 4239257U, // SQXTNv1i8 |
| 8543 | 1615017855U, // SQXTNv2i32 |
| 8544 | 1615011172U, // SQXTNv4i16 |
| 8545 | 1615084461U, // SQXTNv4i32 |
| 8546 | 1615077783U, // SQXTNv8i16 |
| 8547 | 1615006172U, // SQXTNv8i8 |
| 8548 | 3762359856U, // SQXTUNB_ZZ_B |
| 8549 | 3242331696U, // SQXTUNB_ZZ_H |
| 8550 | 541232688U, // SQXTUNB_ZZ_S |
| 8551 | 1078019645U, // SQXTUNT_ZZ_B |
| 8552 | 3246540349U, // SQXTUNT_ZZ_H |
| 8553 | 2151859773U, // SQXTUNT_ZZ_S |
| 8554 | 1615070247U, // SQXTUNv16i8 |
| 8555 | 4239299U, // SQXTUNv1i16 |
| 8556 | 4239299U, // SQXTUNv1i32 |
| 8557 | 4239299U, // SQXTUNv1i8 |
| 8558 | 1615017900U, // SQXTUNv2i32 |
| 8559 | 1615011217U, // SQXTUNv4i16 |
| 8560 | 1615084510U, // SQXTUNv4i32 |
| 8561 | 1615077832U, // SQXTUNv8i16 |
| 8562 | 1615006217U, // SQXTUNv8i8 |
| 8563 | 2151749573U, // SRHADD_ZPmZ_B |
| 8564 | 2151782341U, // SRHADD_ZPmZ_D |
| 8565 | 2713851845U, // SRHADD_ZPmZ_H |
| 8566 | 2151847877U, // SRHADD_ZPmZ_S |
| 8567 | 1615004943U, // SRHADDv16i8 |
| 8568 | 1615017322U, // SRHADDv2i32 |
| 8569 | 1615010651U, // SRHADDv4i16 |
| 8570 | 1615019319U, // SRHADDv4i32 |
| 8571 | 1615012569U, // SRHADDv8i16 |
| 8572 | 1615005839U, // SRHADDv8i8 |
| 8573 | 541141803U, // SRI_ZZI_B |
| 8574 | 2151787307U, // SRI_ZZI_D |
| 8575 | 84028203U, // SRI_ZZI_H |
| 8576 | 2688723755U, // SRI_ZZI_S |
| 8577 | 1615440683U, // SRId |
| 8578 | 1615070637U, // SRIv16i8_shift |
| 8579 | 1615083125U, // SRIv2i32_shift |
| 8580 | 1615074186U, // SRIv2i64_shift |
| 8581 | 1615076431U, // SRIv4i16_shift |
| 8582 | 1615085143U, // SRIv4i32_shift |
| 8583 | 1615078349U, // SRIv8i16_shift |
| 8584 | 1615071500U, // SRIv8i8_shift |
| 8585 | 2151756558U, // SRSHLR_ZPmZ_B |
| 8586 | 2151789326U, // SRSHLR_ZPmZ_D |
| 8587 | 2713858830U, // SRSHLR_ZPmZ_H |
| 8588 | 2151854862U, // SRSHLR_ZPmZ_S |
| 8589 | 50638063U, // SRSHL_VG2_2Z2Z_B |
| 8590 | 54865135U, // SRSHL_VG2_2Z2Z_D |
| 8591 | 59092207U, // SRSHL_VG2_2Z2Z_H |
| 8592 | 63319279U, // SRSHL_VG2_2Z2Z_S |
| 8593 | 50638063U, // SRSHL_VG2_2ZZ_B |
| 8594 | 54865135U, // SRSHL_VG2_2ZZ_D |
| 8595 | 59092207U, // SRSHL_VG2_2ZZ_H |
| 8596 | 63319279U, // SRSHL_VG2_2ZZ_S |
| 8597 | 50638063U, // SRSHL_VG4_4Z4Z_B |
| 8598 | 54865135U, // SRSHL_VG4_4Z4Z_D |
| 8599 | 59092207U, // SRSHL_VG4_4Z4Z_H |
| 8600 | 63319279U, // SRSHL_VG4_4Z4Z_S |
| 8601 | 50638063U, // SRSHL_VG4_4ZZ_B |
| 8602 | 54865135U, // SRSHL_VG4_4ZZ_D |
| 8603 | 59092207U, // SRSHL_VG4_4ZZ_H |
| 8604 | 63319279U, // SRSHL_VG4_4ZZ_S |
| 8605 | 2151754991U, // SRSHL_ZPmZ_B |
| 8606 | 2151787759U, // SRSHL_ZPmZ_D |
| 8607 | 2713857263U, // SRSHL_ZPmZ_H |
| 8608 | 2151853295U, // SRSHL_ZPmZ_S |
| 8609 | 1615005166U, // SRSHLv16i8 |
| 8610 | 4238575U, // SRSHLv1i64 |
| 8611 | 1615017659U, // SRSHLv2i32 |
| 8612 | 1615008832U, // SRSHLv2i64 |
| 8613 | 1615010965U, // SRSHLv4i16 |
| 8614 | 1615019789U, // SRSHLv4i32 |
| 8615 | 1615012983U, // SRSHLv8i16 |
| 8616 | 1615006023U, // SRSHLv8i8 |
| 8617 | 2151756469U, // SRSHR_ZPmI_B |
| 8618 | 2151789237U, // SRSHR_ZPmI_D |
| 8619 | 2713858741U, // SRSHR_ZPmI_H |
| 8620 | 2151854773U, // SRSHR_ZPmI_S |
| 8621 | 4240053U, // SRSHRd |
| 8622 | 1615005329U, // SRSHRv16i8_shift |
| 8623 | 1615018078U, // SRSHRv2i32_shift |
| 8624 | 1615009161U, // SRSHRv2i64_shift |
| 8625 | 1615011395U, // SRSHRv4i16_shift |
| 8626 | 1615020188U, // SRSHRv4i32_shift |
| 8627 | 1615013372U, // SRSHRv8i16_shift |
| 8628 | 1615006294U, // SRSHRv8i8_shift |
| 8629 | 541131355U, // SRSRA_ZZI_B |
| 8630 | 2151776859U, // SRSRA_ZZI_D |
| 8631 | 84017755U, // SRSRA_ZZI_H |
| 8632 | 2688713307U, // SRSRA_ZZI_S |
| 8633 | 1615430235U, // SRSRAd |
| 8634 | 1615070341U, // SRSRAv16i8_shift |
| 8635 | 1615082706U, // SRSRAv2i32_shift |
| 8636 | 1615073926U, // SRSRAv2i64_shift |
| 8637 | 1615076035U, // SRSRAv4i16_shift |
| 8638 | 1615084669U, // SRSRAv4i32_shift |
| 8639 | 1615077953U, // SRSRAv8i16_shift |
| 8640 | 1615071271U, // SRSRAv8i8_shift |
| 8641 | 541166862U, // SSHLLB_ZZI_D |
| 8642 | 88214798U, // SSHLLB_ZZI_H |
| 8643 | 3762457870U, // SSHLLB_ZZI_S |
| 8644 | 541181257U, // SSHLLT_ZZI_D |
| 8645 | 88229193U, // SSHLLT_ZZI_H |
| 8646 | 3762472265U, // SSHLLT_ZZI_S |
| 8647 | 1615012049U, // SSHLLv16i8_shift |
| 8648 | 1615008870U, // SSHLLv2i32_shift |
| 8649 | 1615019827U, // SSHLLv4i16_shift |
| 8650 | 1615008208U, // SSHLLv4i32_shift |
| 8651 | 1615018750U, // SSHLLv8i16_shift |
| 8652 | 1615013021U, // SSHLLv8i8_shift |
| 8653 | 1615005188U, // SSHLv16i8 |
| 8654 | 4238589U, // SSHLv1i64 |
| 8655 | 1615017679U, // SSHLv2i32 |
| 8656 | 1615008852U, // SSHLv2i64 |
| 8657 | 1615010985U, // SSHLv4i16 |
| 8658 | 1615019809U, // SSHLv4i32 |
| 8659 | 1615013003U, // SSHLv8i16 |
| 8660 | 1615006043U, // SSHLv8i8 |
| 8661 | 4240067U, // SSHRd |
| 8662 | 1615005351U, // SSHRv16i8_shift |
| 8663 | 1615018098U, // SSHRv2i32_shift |
| 8664 | 1615009181U, // SSHRv2i64_shift |
| 8665 | 1615011415U, // SSHRv4i16_shift |
| 8666 | 1615020208U, // SSHRv4i32_shift |
| 8667 | 1615013392U, // SSHRv8i16_shift |
| 8668 | 1615006314U, // SSHRv8i8_shift |
| 8669 | 541131369U, // SSRA_ZZI_B |
| 8670 | 2151776873U, // SSRA_ZZI_D |
| 8671 | 84017769U, // SSRA_ZZI_H |
| 8672 | 2688713321U, // SSRA_ZZI_S |
| 8673 | 1615430249U, // SSRAd |
| 8674 | 1615070363U, // SSRAv16i8_shift |
| 8675 | 1615082726U, // SSRAv2i32_shift |
| 8676 | 1615073946U, // SSRAv2i64_shift |
| 8677 | 1615076055U, // SSRAv4i16_shift |
| 8678 | 1615084689U, // SSRAv4i32_shift |
| 8679 | 1615077973U, // SSRAv8i16_shift |
| 8680 | 1615071291U, // SSRAv8i8_shift |
| 8681 | 1103430447U, // SST1B_D |
| 8682 | 1103430447U, // SST1B_D_IMM |
| 8683 | 1103430447U, // SST1B_D_SXTW |
| 8684 | 1103430447U, // SST1B_D_UXTW |
| 8685 | 1103495983U, // SST1B_S_IMM |
| 8686 | 1103495983U, // SST1B_S_SXTW |
| 8687 | 1103495983U, // SST1B_S_UXTW |
| 8688 | 1103433986U, // SST1D |
| 8689 | 1103433986U, // SST1D_IMM |
| 8690 | 1103433986U, // SST1D_SCALED |
| 8691 | 1103433986U, // SST1D_SXTW |
| 8692 | 1103433986U, // SST1D_SXTW_SCALED |
| 8693 | 1103433986U, // SST1D_UXTW |
| 8694 | 1103433986U, // SST1D_UXTW_SCALED |
| 8695 | 1103436280U, // SST1H_D |
| 8696 | 1103436280U, // SST1H_D_IMM |
| 8697 | 1103436280U, // SST1H_D_SCALED |
| 8698 | 1103436280U, // SST1H_D_SXTW |
| 8699 | 1103436280U, // SST1H_D_SXTW_SCALED |
| 8700 | 1103436280U, // SST1H_D_UXTW |
| 8701 | 1103436280U, // SST1H_D_UXTW_SCALED |
| 8702 | 1103501816U, // SST1H_S_IMM |
| 8703 | 1103501816U, // SST1H_S_SXTW |
| 8704 | 1103501816U, // SST1H_S_SXTW_SCALED |
| 8705 | 1103501816U, // SST1H_S_UXTW |
| 8706 | 1103501816U, // SST1H_S_UXTW_SCALED |
| 8707 | 1104097715U, // SST1Q |
| 8708 | 1103448202U, // SST1W_D |
| 8709 | 1103448202U, // SST1W_D_IMM |
| 8710 | 1103448202U, // SST1W_D_SCALED |
| 8711 | 1103448202U, // SST1W_D_SXTW |
| 8712 | 1103448202U, // SST1W_D_SXTW_SCALED |
| 8713 | 1103448202U, // SST1W_D_UXTW |
| 8714 | 1103448202U, // SST1W_D_UXTW_SCALED |
| 8715 | 1103513738U, // SST1W_IMM |
| 8716 | 1103513738U, // SST1W_SXTW |
| 8717 | 1103513738U, // SST1W_SXTW_SCALED |
| 8718 | 1103513738U, // SST1W_UXTW |
| 8719 | 1103513738U, // SST1W_UXTW_SCALED |
| 8720 | 541180991U, // SSUBLBT_ZZZ_D |
| 8721 | 88228927U, // SSUBLBT_ZZZ_H |
| 8722 | 3762471999U, // SSUBLBT_ZZZ_S |
| 8723 | 541166791U, // SSUBLB_ZZZ_D |
| 8724 | 88214727U, // SSUBLB_ZZZ_H |
| 8725 | 3762457799U, // SSUBLB_ZZZ_S |
| 8726 | 541167455U, // SSUBLTB_ZZZ_D |
| 8727 | 88215391U, // SSUBLTB_ZZZ_H |
| 8728 | 3762458463U, // SSUBLTB_ZZZ_S |
| 8729 | 541181181U, // SSUBLT_ZZZ_D |
| 8730 | 88229117U, // SSUBLT_ZZZ_H |
| 8731 | 3762472189U, // SSUBLT_ZZZ_S |
| 8732 | 1615011983U, // SSUBLv16i8_v8i16 |
| 8733 | 1615008730U, // SSUBLv2i32_v2i64 |
| 8734 | 1615019687U, // SSUBLv4i16_v4i32 |
| 8735 | 1615008142U, // SSUBLv4i32_v2i64 |
| 8736 | 1615018684U, // SSUBLv8i16_v4i32 |
| 8737 | 1615012881U, // SSUBLv8i8_v8i16 |
| 8738 | 541167563U, // SSUBWB_ZZZ_D |
| 8739 | 71438283U, // SSUBWB_ZZZ_H |
| 8740 | 541233099U, // SSUBWB_ZZZ_S |
| 8741 | 541181703U, // SSUBWT_ZZZ_D |
| 8742 | 71452423U, // SSUBWT_ZZZ_H |
| 8743 | 541247239U, // SSUBWT_ZZZ_S |
| 8744 | 1615012326U, // SSUBWv16i8_v8i16 |
| 8745 | 1615009448U, // SSUBWv2i32_v2i64 |
| 8746 | 1615020606U, // SSUBWv4i16_v4i32 |
| 8747 | 1615008327U, // SSUBWv4i32_v2i64 |
| 8748 | 1615019004U, // SSUBWv8i16_v4i32 |
| 8749 | 1615013790U, // SSUBWv8i8_v8i16 |
| 8750 | 1103397679U, // ST1B |
| 8751 | 1250198319U, // ST1B_2Z |
| 8752 | 1250198319U, // ST1B_2Z_IMM |
| 8753 | 5309231U, // ST1B_2Z_STRIDED |
| 8754 | 5309231U, // ST1B_2Z_STRIDED_IMM |
| 8755 | 1250198319U, // ST1B_4Z |
| 8756 | 1250198319U, // ST1B_4Z_IMM |
| 8757 | 1250198319U, // ST1B_4Z_STRIDED |
| 8758 | 1250198319U, // ST1B_4Z_STRIDED_IMM |
| 8759 | 1103430447U, // ST1B_D |
| 8760 | 1103430447U, // ST1B_D_IMM |
| 8761 | 1103463215U, // ST1B_H |
| 8762 | 1103463215U, // ST1B_H_IMM |
| 8763 | 1103397679U, // ST1B_IMM |
| 8764 | 1103495983U, // ST1B_S |
| 8765 | 1103495983U, // ST1B_S_IMM |
| 8766 | 1103433986U, // ST1D |
| 8767 | 1250234626U, // ST1D_2Z |
| 8768 | 1250234626U, // ST1D_2Z_IMM |
| 8769 | 1250234626U, // ST1D_2Z_STRIDED |
| 8770 | 1250234626U, // ST1D_2Z_STRIDED_IMM |
| 8771 | 1250234626U, // ST1D_4Z |
| 8772 | 1250234626U, // ST1D_4Z_IMM |
| 8773 | 1250234626U, // ST1D_4Z_STRIDED |
| 8774 | 1250234626U, // ST1D_4Z_STRIDED_IMM |
| 8775 | 1103433986U, // ST1D_IMM |
| 8776 | 1104089346U, // ST1D_Q |
| 8777 | 1104089346U, // ST1D_Q_IMM |
| 8778 | 1146955U, // ST1Fourv16b |
| 8779 | 181534795U, // ST1Fourv16b_POST |
| 8780 | 1212491U, // ST1Fourv1d |
| 8781 | 185794635U, // ST1Fourv1d_POST |
| 8782 | 1278027U, // ST1Fourv2d |
| 8783 | 181665867U, // ST1Fourv2d_POST |
| 8784 | 1343563U, // ST1Fourv2s |
| 8785 | 185925707U, // ST1Fourv2s_POST |
| 8786 | 1409099U, // ST1Fourv4h |
| 8787 | 185991243U, // ST1Fourv4h_POST |
| 8788 | 1474635U, // ST1Fourv4s |
| 8789 | 181862475U, // ST1Fourv4s_POST |
| 8790 | 1540171U, // ST1Fourv8b |
| 8791 | 186122315U, // ST1Fourv8b_POST |
| 8792 | 1605707U, // ST1Fourv8h |
| 8793 | 181993547U, // ST1Fourv8h_POST |
| 8794 | 1103469048U, // ST1H |
| 8795 | 1250269688U, // ST1H_2Z |
| 8796 | 1250269688U, // ST1H_2Z_IMM |
| 8797 | 5872120U, // ST1H_2Z_STRIDED |
| 8798 | 5872120U, // ST1H_2Z_STRIDED_IMM |
| 8799 | 1250269688U, // ST1H_4Z |
| 8800 | 1250269688U, // ST1H_4Z_IMM |
| 8801 | 1250269688U, // ST1H_4Z_STRIDED |
| 8802 | 1250269688U, // ST1H_4Z_STRIDED_IMM |
| 8803 | 1103436280U, // ST1H_D |
| 8804 | 1103436280U, // ST1H_D_IMM |
| 8805 | 1103469048U, // ST1H_IMM |
| 8806 | 1103501816U, // ST1H_S |
| 8807 | 1103501816U, // ST1H_S_IMM |
| 8808 | 1146955U, // ST1Onev16b |
| 8809 | 189923403U, // ST1Onev16b_POST |
| 8810 | 1212491U, // ST1Onev1d |
| 8811 | 194183243U, // ST1Onev1d_POST |
| 8812 | 1278027U, // ST1Onev2d |
| 8813 | 190054475U, // ST1Onev2d_POST |
| 8814 | 1343563U, // ST1Onev2s |
| 8815 | 194314315U, // ST1Onev2s_POST |
| 8816 | 1409099U, // ST1Onev4h |
| 8817 | 194379851U, // ST1Onev4h_POST |
| 8818 | 1474635U, // ST1Onev4s |
| 8819 | 190251083U, // ST1Onev4s_POST |
| 8820 | 1540171U, // ST1Onev8b |
| 8821 | 194510923U, // ST1Onev8b_POST |
| 8822 | 1605707U, // ST1Onev8h |
| 8823 | 190382155U, // ST1Onev8h_POST |
| 8824 | 1146955U, // ST1Threev16b |
| 8825 | 210894923U, // ST1Threev16b_POST |
| 8826 | 1212491U, // ST1Threev1d |
| 8827 | 215154763U, // ST1Threev1d_POST |
| 8828 | 1278027U, // ST1Threev2d |
| 8829 | 211025995U, // ST1Threev2d_POST |
| 8830 | 1343563U, // ST1Threev2s |
| 8831 | 215285835U, // ST1Threev2s_POST |
| 8832 | 1409099U, // ST1Threev4h |
| 8833 | 215351371U, // ST1Threev4h_POST |
| 8834 | 1474635U, // ST1Threev4s |
| 8835 | 211222603U, // ST1Threev4s_POST |
| 8836 | 1540171U, // ST1Threev8b |
| 8837 | 215482443U, // ST1Threev8b_POST |
| 8838 | 1605707U, // ST1Threev8h |
| 8839 | 211353675U, // ST1Threev8h_POST |
| 8840 | 1146955U, // ST1Twov16b |
| 8841 | 185729099U, // ST1Twov16b_POST |
| 8842 | 1212491U, // ST1Twov1d |
| 8843 | 189988939U, // ST1Twov1d_POST |
| 8844 | 1278027U, // ST1Twov2d |
| 8845 | 185860171U, // ST1Twov2d_POST |
| 8846 | 1343563U, // ST1Twov2s |
| 8847 | 190120011U, // ST1Twov2s_POST |
| 8848 | 1409099U, // ST1Twov4h |
| 8849 | 190185547U, // ST1Twov4h_POST |
| 8850 | 1474635U, // ST1Twov4s |
| 8851 | 186056779U, // ST1Twov4s_POST |
| 8852 | 1540171U, // ST1Twov8b |
| 8853 | 190316619U, // ST1Twov8b_POST |
| 8854 | 1605707U, // ST1Twov8h |
| 8855 | 186187851U, // ST1Twov8h_POST |
| 8856 | 1103513738U, // ST1W |
| 8857 | 1250314378U, // ST1W_2Z |
| 8858 | 1250314378U, // ST1W_2Z_IMM |
| 8859 | 1250314378U, // ST1W_2Z_STRIDED |
| 8860 | 1250314378U, // ST1W_2Z_STRIDED_IMM |
| 8861 | 1250314378U, // ST1W_4Z |
| 8862 | 1250314378U, // ST1W_4Z_IMM |
| 8863 | 1250314378U, // ST1W_4Z_STRIDED |
| 8864 | 1250314378U, // ST1W_4Z_STRIDED_IMM |
| 8865 | 1103448202U, // ST1W_D |
| 8866 | 1103448202U, // ST1W_D_IMM |
| 8867 | 1103513738U, // ST1W_IMM |
| 8868 | 1104103562U, // ST1W_Q |
| 8869 | 1104103562U, // ST1W_Q_IMM |
| 8870 | 110121485U, // ST1_MXIPXX_H_B |
| 8871 | 110121499U, // ST1_MXIPXX_H_D |
| 8872 | 110121513U, // ST1_MXIPXX_H_H |
| 8873 | 110121527U, // ST1_MXIPXX_H_Q |
| 8874 | 110121541U, // ST1_MXIPXX_H_S |
| 8875 | 110154253U, // ST1_MXIPXX_V_B |
| 8876 | 110154267U, // ST1_MXIPXX_V_D |
| 8877 | 110154281U, // ST1_MXIPXX_V_H |
| 8878 | 110154295U, // ST1_MXIPXX_V_Q |
| 8879 | 110154309U, // ST1_MXIPXX_V_S |
| 8880 | 324632651U, // ST1i16 |
| 8881 | 1939472459U, // ST1i16_POST |
| 8882 | 2457675U, // ST1i32 |
| 8883 | 2476408907U, // ST1i32_POST |
| 8884 | 2490443U, // ST1i64 |
| 8885 | 3013345355U, // ST1i64_POST |
| 8886 | 324075595U, // ST1i8 |
| 8887 | 3550281803U, // ST1i8_POST |
| 8888 | 1103397699U, // ST2B |
| 8889 | 1103397699U, // ST2B_IMM |
| 8890 | 1103435581U, // ST2D |
| 8891 | 1103435581U, // ST2D_IMM |
| 8892 | 1686739192U, // ST2GPostIndex |
| 8893 | 1686739192U, // ST2GPreIndex |
| 8894 | 75536632U, // ST2Gi |
| 8895 | 1103469122U, // ST2H |
| 8896 | 1103469122U, // ST2H_IMM |
| 8897 | 1104097727U, // ST2Q |
| 8898 | 1104097727U, // ST2Q_IMM |
| 8899 | 1147073U, // ST2Twov16b |
| 8900 | 185729217U, // ST2Twov16b_POST |
| 8901 | 1278145U, // ST2Twov2d |
| 8902 | 185860289U, // ST2Twov2d_POST |
| 8903 | 1343681U, // ST2Twov2s |
| 8904 | 190120129U, // ST2Twov2s_POST |
| 8905 | 1409217U, // ST2Twov4h |
| 8906 | 190185665U, // ST2Twov4h_POST |
| 8907 | 1474753U, // ST2Twov4s |
| 8908 | 186056897U, // ST2Twov4s_POST |
| 8909 | 1540289U, // ST2Twov8b |
| 8910 | 190316737U, // ST2Twov8b_POST |
| 8911 | 1605825U, // ST2Twov8h |
| 8912 | 186187969U, // ST2Twov8h_POST |
| 8913 | 1103513758U, // ST2W |
| 8914 | 1103513758U, // ST2W_IMM |
| 8915 | 324632769U, // ST2i16 |
| 8916 | 2476343489U, // ST2i16_POST |
| 8917 | 2457793U, // ST2i32 |
| 8918 | 3013279937U, // ST2i32_POST |
| 8919 | 2490561U, // ST2i64 |
| 8920 | 4087087297U, // ST2i64_POST |
| 8921 | 324075713U, // ST2i8 |
| 8922 | 1939669185U, // ST2i8_POST |
| 8923 | 1103397711U, // ST3B |
| 8924 | 1103397711U, // ST3B_IMM |
| 8925 | 1103435593U, // ST3D |
| 8926 | 1103435593U, // ST3D_IMM |
| 8927 | 1103469134U, // ST3H |
| 8928 | 1103469134U, // ST3H_IMM |
| 8929 | 1104097739U, // ST3Q |
| 8930 | 1104097739U, // ST3Q_IMM |
| 8931 | 1147096U, // ST3Threev16b |
| 8932 | 210895064U, // ST3Threev16b_POST |
| 8933 | 1278168U, // ST3Threev2d |
| 8934 | 211026136U, // ST3Threev2d_POST |
| 8935 | 1343704U, // ST3Threev2s |
| 8936 | 215285976U, // ST3Threev2s_POST |
| 8937 | 1409240U, // ST3Threev4h |
| 8938 | 215351512U, // ST3Threev4h_POST |
| 8939 | 1474776U, // ST3Threev4s |
| 8940 | 211222744U, // ST3Threev4s_POST |
| 8941 | 1540312U, // ST3Threev8b |
| 8942 | 215482584U, // ST3Threev8b_POST |
| 8943 | 1605848U, // ST3Threev8h |
| 8944 | 211353816U, // ST3Threev8h_POST |
| 8945 | 1103513770U, // ST3W |
| 8946 | 1103513770U, // ST3W_IMM |
| 8947 | 324632792U, // ST3i16 |
| 8948 | 328859864U, // ST3i16_POST |
| 8949 | 2457816U, // ST3i32 |
| 8950 | 865796312U, // ST3i32_POST |
| 8951 | 2490584U, // ST3i64 |
| 8952 | 1402732760U, // ST3i64_POST |
| 8953 | 324075736U, // ST3i8 |
| 8954 | 1939669208U, // ST3i8_POST |
| 8955 | 1103397737U, // ST4B |
| 8956 | 1103397737U, // ST4B_IMM |
| 8957 | 1103435605U, // ST4D |
| 8958 | 1103435605U, // ST4D_IMM |
| 8959 | 1147113U, // ST4Fourv16b |
| 8960 | 181534953U, // ST4Fourv16b_POST |
| 8961 | 1278185U, // ST4Fourv2d |
| 8962 | 181666025U, // ST4Fourv2d_POST |
| 8963 | 1343721U, // ST4Fourv2s |
| 8964 | 185925865U, // ST4Fourv2s_POST |
| 8965 | 1409257U, // ST4Fourv4h |
| 8966 | 185991401U, // ST4Fourv4h_POST |
| 8967 | 1474793U, // ST4Fourv4s |
| 8968 | 181862633U, // ST4Fourv4s_POST |
| 8969 | 1540329U, // ST4Fourv8b |
| 8970 | 186122473U, // ST4Fourv8b_POST |
| 8971 | 1605865U, // ST4Fourv8h |
| 8972 | 181993705U, // ST4Fourv8h_POST |
| 8973 | 1103470648U, // ST4H |
| 8974 | 1103470648U, // ST4H_IMM |
| 8975 | 1104097751U, // ST4Q |
| 8976 | 1104097751U, // ST4Q_IMM |
| 8977 | 1103513782U, // ST4W |
| 8978 | 1103513782U, // ST4W_IMM |
| 8979 | 324632809U, // ST4i16 |
| 8980 | 3013214441U, // ST4i16_POST |
| 8981 | 2457833U, // ST4i32 |
| 8982 | 4087021801U, // ST4i32_POST |
| 8983 | 2490601U, // ST4i64 |
| 8984 | 2476474601U, // ST4i64_POST |
| 8985 | 324075753U, // ST4i8 |
| 8986 | 2476540137U, // ST4i8_POST |
| 8987 | 1966940U, // ST64B |
| 8988 | 2688599931U, // ST64BV |
| 8989 | 2688581633U, // ST64BV0 |
| 8990 | 75542222U, // STGM |
| 8991 | 4239433U, // STGPi |
| 8992 | 1686739256U, // STGPostIndex |
| 8993 | 1615441993U, // STGPpost |
| 8994 | 1615441993U, // STGPpre |
| 8995 | 1686739256U, // STGPreIndex |
| 8996 | 75536696U, // STGi |
| 8997 | 4239460U, // STILPW |
| 8998 | 1615442020U, // STILPWpre |
| 8999 | 4239460U, // STILPX |
| 9000 | 1615442020U, // STILPXpre |
| 9001 | 2490383U, // STL1 |
| 9002 | 75533946U, // STLLRB |
| 9003 | 75540972U, // STLLRH |
| 9004 | 75543326U, // STLLRW |
| 9005 | 75543326U, // STLLRX |
| 9006 | 75533954U, // STLRB |
| 9007 | 75540980U, // STLRH |
| 9008 | 75543339U, // STLRW |
| 9009 | 1686745899U, // STLRWpre |
| 9010 | 75543339U, // STLRX |
| 9011 | 1686745899U, // STLRXpre |
| 9012 | 75534004U, // STLURBi |
| 9013 | 75541030U, // STLURHi |
| 9014 | 75543448U, // STLURWi |
| 9015 | 75543448U, // STLURXi |
| 9016 | 75543448U, // STLURbi |
| 9017 | 75543448U, // STLURdi |
| 9018 | 75543448U, // STLURhi |
| 9019 | 75543448U, // STLURqi |
| 9020 | 75543448U, // STLURsi |
| 9021 | 4239750U, // STLXPW |
| 9022 | 4239750U, // STLXPX |
| 9023 | 4230875U, // STLXRB |
| 9024 | 4237901U, // STLXRH |
| 9025 | 4240344U, // STLXRW |
| 9026 | 4240344U, // STLXRX |
| 9027 | 4239550U, // STNPDi |
| 9028 | 4239550U, // STNPQi |
| 9029 | 4239550U, // STNPSi |
| 9030 | 4239550U, // STNPWi |
| 9031 | 4239550U, // STNPXi |
| 9032 | 1250198311U, // STNT1B_2Z |
| 9033 | 1250198311U, // STNT1B_2Z_IMM |
| 9034 | 5309223U, // STNT1B_2Z_STRIDED |
| 9035 | 5309223U, // STNT1B_2Z_STRIDED_IMM |
| 9036 | 1250198311U, // STNT1B_4Z |
| 9037 | 1250198311U, // STNT1B_4Z_IMM |
| 9038 | 1250198311U, // STNT1B_4Z_STRIDED |
| 9039 | 1250198311U, // STNT1B_4Z_STRIDED_IMM |
| 9040 | 1103397671U, // STNT1B_ZRI |
| 9041 | 1103397671U, // STNT1B_ZRR |
| 9042 | 1103430439U, // STNT1B_ZZR_D |
| 9043 | 1103495975U, // STNT1B_ZZR_S |
| 9044 | 1250234618U, // STNT1D_2Z |
| 9045 | 1250234618U, // STNT1D_2Z_IMM |
| 9046 | 1250234618U, // STNT1D_2Z_STRIDED |
| 9047 | 1250234618U, // STNT1D_2Z_STRIDED_IMM |
| 9048 | 1250234618U, // STNT1D_4Z |
| 9049 | 1250234618U, // STNT1D_4Z_IMM |
| 9050 | 1250234618U, // STNT1D_4Z_STRIDED |
| 9051 | 1250234618U, // STNT1D_4Z_STRIDED_IMM |
| 9052 | 1103433978U, // STNT1D_ZRI |
| 9053 | 1103433978U, // STNT1D_ZRR |
| 9054 | 1103433978U, // STNT1D_ZZR_D |
| 9055 | 1250269680U, // STNT1H_2Z |
| 9056 | 1250269680U, // STNT1H_2Z_IMM |
| 9057 | 5872112U, // STNT1H_2Z_STRIDED |
| 9058 | 5872112U, // STNT1H_2Z_STRIDED_IMM |
| 9059 | 1250269680U, // STNT1H_4Z |
| 9060 | 1250269680U, // STNT1H_4Z_IMM |
| 9061 | 1250269680U, // STNT1H_4Z_STRIDED |
| 9062 | 1250269680U, // STNT1H_4Z_STRIDED_IMM |
| 9063 | 1103469040U, // STNT1H_ZRI |
| 9064 | 1103469040U, // STNT1H_ZRR |
| 9065 | 1103436272U, // STNT1H_ZZR_D |
| 9066 | 1103501808U, // STNT1H_ZZR_S |
| 9067 | 1250314370U, // STNT1W_2Z |
| 9068 | 1250314370U, // STNT1W_2Z_IMM |
| 9069 | 1250314370U, // STNT1W_2Z_STRIDED |
| 9070 | 1250314370U, // STNT1W_2Z_STRIDED_IMM |
| 9071 | 1250314370U, // STNT1W_4Z |
| 9072 | 1250314370U, // STNT1W_4Z_IMM |
| 9073 | 1250314370U, // STNT1W_4Z_STRIDED |
| 9074 | 1250314370U, // STNT1W_4Z_STRIDED_IMM |
| 9075 | 1103513730U, // STNT1W_ZRI |
| 9076 | 1103513730U, // STNT1W_ZRR |
| 9077 | 1103448194U, // STNT1W_ZZR_D |
| 9078 | 1103513730U, // STNT1W_ZZR_S |
| 9079 | 4239688U, // STPDi |
| 9080 | 1615442248U, // STPDpost |
| 9081 | 1615442248U, // STPDpre |
| 9082 | 4239688U, // STPQi |
| 9083 | 1615442248U, // STPQpost |
| 9084 | 1615442248U, // STPQpre |
| 9085 | 4239688U, // STPSi |
| 9086 | 1615442248U, // STPSpost |
| 9087 | 1615442248U, // STPSpre |
| 9088 | 4239688U, // STPWi |
| 9089 | 1615442248U, // STPWpost |
| 9090 | 1615442248U, // STPWpre |
| 9091 | 4239688U, // STPXi |
| 9092 | 1615442248U, // STPXpost |
| 9093 | 1615442248U, // STPXpre |
| 9094 | 1686736544U, // STRBBpost |
| 9095 | 1686736544U, // STRBBpre |
| 9096 | 75533984U, // STRBBroW |
| 9097 | 75533984U, // STRBBroX |
| 9098 | 75533984U, // STRBBui |
| 9099 | 1686745982U, // STRBpost |
| 9100 | 1686745982U, // STRBpre |
| 9101 | 75543422U, // STRBroW |
| 9102 | 75543422U, // STRBroX |
| 9103 | 75543422U, // STRBui |
| 9104 | 1686745982U, // STRDpost |
| 9105 | 1686745982U, // STRDpre |
| 9106 | 75543422U, // STRDroW |
| 9107 | 75543422U, // STRDroX |
| 9108 | 75543422U, // STRDui |
| 9109 | 1686743570U, // STRHHpost |
| 9110 | 1686743570U, // STRHHpre |
| 9111 | 75541010U, // STRHHroW |
| 9112 | 75541010U, // STRHHroX |
| 9113 | 75541010U, // STRHHui |
| 9114 | 1686745982U, // STRHpost |
| 9115 | 1686745982U, // STRHpre |
| 9116 | 75543422U, // STRHroW |
| 9117 | 75543422U, // STRHroX |
| 9118 | 75543422U, // STRHui |
| 9119 | 1686745982U, // STRQpost |
| 9120 | 1686745982U, // STRQpre |
| 9121 | 75543422U, // STRQroW |
| 9122 | 75543422U, // STRQroX |
| 9123 | 75543422U, // STRQui |
| 9124 | 1686745982U, // STRSpost |
| 9125 | 1686745982U, // STRSpre |
| 9126 | 75543422U, // STRSroW |
| 9127 | 75543422U, // STRSroX |
| 9128 | 75543422U, // STRSui |
| 9129 | 1686745982U, // STRWpost |
| 9130 | 1686745982U, // STRWpre |
| 9131 | 75543422U, // STRWroW |
| 9132 | 75543422U, // STRWroX |
| 9133 | 75543422U, // STRWui |
| 9134 | 1686745982U, // STRXpost |
| 9135 | 1686745982U, // STRXpre |
| 9136 | 75543422U, // STRXroW |
| 9137 | 75543422U, // STRXroX |
| 9138 | 75543422U, // STRXui |
| 9139 | 77542270U, // STR_PXI |
| 9140 | 75543422U, // STR_TX |
| 9141 | 2077566U, // STR_ZA |
| 9142 | 77542270U, // STR_ZXI |
| 9143 | 75533990U, // STTRBi |
| 9144 | 75541016U, // STTRHi |
| 9145 | 75543430U, // STTRWi |
| 9146 | 75543430U, // STTRXi |
| 9147 | 75534021U, // STURBBi |
| 9148 | 75543463U, // STURBi |
| 9149 | 75543463U, // STURDi |
| 9150 | 75541047U, // STURHHi |
| 9151 | 75543463U, // STURHi |
| 9152 | 75543463U, // STURQi |
| 9153 | 75543463U, // STURSi |
| 9154 | 75543463U, // STURWi |
| 9155 | 75543463U, // STURXi |
| 9156 | 4239757U, // STXPW |
| 9157 | 4239757U, // STXPX |
| 9158 | 4230883U, // STXRB |
| 9159 | 4237909U, // STXRH |
| 9160 | 4240351U, // STXRW |
| 9161 | 4240351U, // STXRX |
| 9162 | 1686739198U, // STZ2GPostIndex |
| 9163 | 1686739198U, // STZ2GPreIndex |
| 9164 | 75536638U, // STZ2Gi |
| 9165 | 75542228U, // STZGM |
| 9166 | 1686739261U, // STZGPostIndex |
| 9167 | 1686739261U, // STZGPreIndex |
| 9168 | 75536701U, // STZGi |
| 9169 | 4233477U, // SUBG |
| 9170 | 3762359738U, // SUBHNB_ZZZ_B |
| 9171 | 21106106U, // SUBHNB_ZZZ_H |
| 9172 | 541232570U, // SUBHNB_ZZZ_S |
| 9173 | 1078019538U, // SUBHNT_ZZZ_B |
| 9174 | 25314770U, // SUBHNT_ZZZ_H |
| 9175 | 2151859666U, // SUBHNT_ZZZ_S |
| 9176 | 1615017740U, // SUBHNv2i64_v2i32 |
| 9177 | 1615084379U, // SUBHNv2i64_v4i32 |
| 9178 | 1615011046U, // SUBHNv4i32_v4i16 |
| 9179 | 1615077689U, // SUBHNv4i32_v8i16 |
| 9180 | 1615070105U, // SUBHNv8i16_v16i8 |
| 9181 | 1615006079U, // SUBHNv8i16_v8i8 |
| 9182 | 4239377U, // SUBP |
| 9183 | 4244410U, // SUBPS |
| 9184 | 4245136U, // SUBPT_shift |
| 9185 | 4272695U, // SUBR_ZI_B |
| 9186 | 541176375U, // SUBR_ZI_D |
| 9187 | 71447095U, // SUBR_ZI_H |
| 9188 | 541241911U, // SUBR_ZI_S |
| 9189 | 2151756343U, // SUBR_ZPmZ_B |
| 9190 | 2151789111U, // SUBR_ZPmZ_D |
| 9191 | 2713858615U, // SUBR_ZPmZ_H |
| 9192 | 2151854647U, // SUBR_ZPmZ_S |
| 9193 | 4244279U, // SUBSWri |
| 9194 | 4244279U, // SUBSWrs |
| 9195 | 4244279U, // SUBSWrx |
| 9196 | 4244279U, // SUBSXri |
| 9197 | 4244279U, // SUBSXrs |
| 9198 | 4244279U, // SUBSXrx |
| 9199 | 4244279U, // SUBSXrx64 |
| 9200 | 4231061U, // SUBWri |
| 9201 | 4231061U, // SUBWrs |
| 9202 | 4231061U, // SUBWrx |
| 9203 | 4231061U, // SUBXri |
| 9204 | 4231061U, // SUBXrs |
| 9205 | 4231061U, // SUBXrx |
| 9206 | 4231061U, // SUBXrx64 |
| 9207 | 3288764309U, // SUB_VG2_M2Z2Z_D |
| 9208 | 3288797077U, // SUB_VG2_M2Z2Z_S |
| 9209 | 3288764309U, // SUB_VG2_M2ZZ_D |
| 9210 | 3288797077U, // SUB_VG2_M2ZZ_S |
| 9211 | 3288764309U, // SUB_VG2_M2Z_D |
| 9212 | 3288797077U, // SUB_VG2_M2Z_S |
| 9213 | 3825635221U, // SUB_VG4_M4Z4Z_D |
| 9214 | 3825667989U, // SUB_VG4_M4Z4Z_S |
| 9215 | 3825635221U, // SUB_VG4_M4ZZ_D |
| 9216 | 3825667989U, // SUB_VG4_M4ZZ_S |
| 9217 | 3825635221U, // SUB_VG4_M4Z_D |
| 9218 | 3825667989U, // SUB_VG4_M4Z_S |
| 9219 | 4263829U, // SUB_ZI_B |
| 9220 | 541167509U, // SUB_ZI_D |
| 9221 | 71438229U, // SUB_ZI_H |
| 9222 | 541233045U, // SUB_ZI_S |
| 9223 | 2151747477U, // SUB_ZPmZ_B |
| 9224 | 2151794320U, // SUB_ZPmZ_CPA |
| 9225 | 2151780245U, // SUB_ZPmZ_D |
| 9226 | 2713849749U, // SUB_ZPmZ_H |
| 9227 | 2151845781U, // SUB_ZPmZ_S |
| 9228 | 4263829U, // SUB_ZZZ_B |
| 9229 | 541181584U, // SUB_ZZZ_CPA |
| 9230 | 541167509U, // SUB_ZZZ_D |
| 9231 | 71438229U, // SUB_ZZZ_H |
| 9232 | 541233045U, // SUB_ZZZ_S |
| 9233 | 1615004849U, // SUBv16i8 |
| 9234 | 4231061U, // SUBv1i64 |
| 9235 | 1615017220U, // SUBv2i32 |
| 9236 | 1615008440U, // SUBv2i64 |
| 9237 | 1615010549U, // SUBv4i16 |
| 9238 | 1615019207U, // SUBv4i32 |
| 9239 | 1615012467U, // SUBv8i16 |
| 9240 | 1615005775U, // SUBv8i8 |
| 9241 | 3288811107U, // SUDOT_VG2_M2ZZI_BToS |
| 9242 | 3288811107U, // SUDOT_VG2_M2ZZ_BToS |
| 9243 | 3825682019U, // SUDOT_VG4_M4ZZI_BToS |
| 9244 | 3825682019U, // SUDOT_VG4_M4ZZ_BToS |
| 9245 | 541247075U, // SUDOT_ZZZI |
| 9246 | 1615087203U, // SUDOTlanev16i8 |
| 9247 | 1615087203U, // SUDOTlanev8i8 |
| 9248 | 3376885018U, // SUMLALL_MZZI_BtoS |
| 9249 | 3376885018U, // SUMLALL_VG2_M2ZZI_BtoS |
| 9250 | 3913755930U, // SUMLALL_VG2_M2ZZ_BtoS |
| 9251 | 3913755930U, // SUMLALL_VG4_M4ZZI_BtoS |
| 9252 | 155659546U, // SUMLALL_VG4_M4ZZ_BtoS |
| 9253 | 96698800U, // SUMOPA_MPPZZ_D |
| 9254 | 159613360U, // SUMOPA_MPPZZ_S |
| 9255 | 96715744U, // SUMOPS_MPPZZ_D |
| 9256 | 159630304U, // SUMOPS_MPPZZ_S |
| 9257 | 541174530U, // SUNPKHI_ZZ_D |
| 9258 | 3309447938U, // SUNPKHI_ZZ_H |
| 9259 | 3762465538U, // SUNPKHI_ZZ_S |
| 9260 | 541175787U, // SUNPKLO_ZZ_D |
| 9261 | 3309449195U, // SUNPKLO_ZZ_H |
| 9262 | 3762466795U, // SUNPKLO_ZZ_S |
| 9263 | 3242535742U, // SUNPK_VG2_2ZZ_D |
| 9264 | 3309677374U, // SUNPK_VG2_2ZZ_H |
| 9265 | 3292932926U, // SUNPK_VG2_2ZZ_S |
| 9266 | 3284478782U, // SUNPK_VG4_4Z2Z_D |
| 9267 | 3271928638U, // SUNPK_VG4_4Z2Z_H |
| 9268 | 3280350014U, // SUNPK_VG4_4Z2Z_S |
| 9269 | 2151749626U, // SUQADD_ZPmZ_B |
| 9270 | 2151782394U, // SUQADD_ZPmZ_D |
| 9271 | 2713851898U, // SUQADD_ZPmZ_H |
| 9272 | 2151847930U, // SUQADD_ZPmZ_S |
| 9273 | 1615070537U, // SUQADDv16i8 |
| 9274 | 1615435770U, // SUQADDv1i16 |
| 9275 | 1615435770U, // SUQADDv1i32 |
| 9276 | 1615435770U, // SUQADDv1i64 |
| 9277 | 1615435770U, // SUQADDv1i8 |
| 9278 | 1615082911U, // SUQADDv2i32 |
| 9279 | 1615074043U, // SUQADDv2i64 |
| 9280 | 1615076240U, // SUQADDv4i16 |
| 9281 | 1615084908U, // SUQADDv4i32 |
| 9282 | 1615078158U, // SUQADDv8i16 |
| 9283 | 1615071428U, // SUQADDv8i8 |
| 9284 | 3825682042U, // SUVDOT_VG4_M4ZZI_BToS |
| 9285 | 757875U, // SVC |
| 9286 | 3288811123U, // SVDOT_VG2_M2ZZI_HtoS |
| 9287 | 3825682035U, // SVDOT_VG4_M4ZZI_BtoS |
| 9288 | 3825649267U, // SVDOT_VG4_M4ZZI_HtoD |
| 9289 | 541690741U, // SWPAB |
| 9290 | 541698117U, // SWPAH |
| 9291 | 541691011U, // SWPALB |
| 9292 | 541698273U, // SWPALH |
| 9293 | 541699079U, // SWPALW |
| 9294 | 541699079U, // SWPALX |
| 9295 | 541688354U, // SWPAW |
| 9296 | 541688354U, // SWPAX |
| 9297 | 541691464U, // SWPB |
| 9298 | 541698490U, // SWPH |
| 9299 | 541691220U, // SWPLB |
| 9300 | 541698370U, // SWPLH |
| 9301 | 541699527U, // SWPLW |
| 9302 | 541699527U, // SWPLX |
| 9303 | 543076560U, // SWPP |
| 9304 | 543064508U, // SWPPA |
| 9305 | 543075223U, // SWPPAL |
| 9306 | 543075673U, // SWPPL |
| 9307 | 541700439U, // SWPW |
| 9308 | 541700439U, // SWPX |
| 9309 | 541167495U, // SXTB_ZPmZ_D |
| 9310 | 1082265479U, // SXTB_ZPmZ_H |
| 9311 | 541233031U, // SXTB_ZPmZ_S |
| 9312 | 541174469U, // SXTH_ZPmZ_D |
| 9313 | 541240005U, // SXTH_ZPmZ_S |
| 9314 | 541182307U, // SXTW_ZPmZ_D |
| 9315 | 4238897U, // SYSLxt |
| 9316 | 3225465113U, // SYSPxt |
| 9317 | 3225465113U, // SYSPxt_XZR |
| 9318 | 3225469982U, // SYSxt |
| 9319 | 1078014452U, // TBLQ_ZZZ_B |
| 9320 | 3762401780U, // TBLQ_ZZZ_D |
| 9321 | 58864116U, // TBLQ_ZZZ_H |
| 9322 | 2151854580U, // TBLQ_ZZZ_S |
| 9323 | 1078013062U, // TBL_ZZZZ_B |
| 9324 | 3762400390U, // TBL_ZZZZ_D |
| 9325 | 58862726U, // TBL_ZZZZ_H |
| 9326 | 2151853190U, // TBL_ZZZZ_S |
| 9327 | 1078013062U, // TBL_ZZZ_B |
| 9328 | 3762400390U, // TBL_ZZZ_D |
| 9329 | 58862726U, // TBL_ZZZ_H |
| 9330 | 2151853190U, // TBL_ZZZ_S |
| 9331 | 1107504262U, // TBLv16i8Four |
| 9332 | 1107504262U, // TBLv16i8One |
| 9333 | 1107504262U, // TBLv16i8Three |
| 9334 | 1107504262U, // TBLv16i8Two |
| 9335 | 1208167558U, // TBLv8i8Four |
| 9336 | 1208167558U, // TBLv8i8One |
| 9337 | 1208167558U, // TBLv8i8Three |
| 9338 | 1208167558U, // TBLv8i8Two |
| 9339 | 4246101U, // TBNZW |
| 9340 | 4246101U, // TBNZX |
| 9341 | 541143558U, // TBXQ_ZZZ_B |
| 9342 | 2151789062U, // TBXQ_ZZZ_D |
| 9343 | 84029958U, // TBXQ_ZZZ_H |
| 9344 | 2688725510U, // TBXQ_ZZZ_S |
| 9345 | 541149621U, // TBX_ZZZ_B |
| 9346 | 2151795125U, // TBX_ZZZ_D |
| 9347 | 84036021U, // TBX_ZZZ_H |
| 9348 | 2688731573U, // TBX_ZZZ_S |
| 9349 | 33835445U, // TBXv16i8Four |
| 9350 | 33835445U, // TBXv16i8One |
| 9351 | 33835445U, // TBXv16i8Three |
| 9352 | 33835445U, // TBXv16i8Two |
| 9353 | 134498741U, // TBXv8i8Four |
| 9354 | 134498741U, // TBXv8i8One |
| 9355 | 134498741U, // TBXv8i8Three |
| 9356 | 134498741U, // TBXv8i8Two |
| 9357 | 4246085U, // TBZW |
| 9358 | 4246085U, // TBZX |
| 9359 | 765107U, // TCANCEL |
| 9360 | 20917U, // TCOMMIT |
| 9361 | 50365U, // TRCIT |
| 9362 | 4259861U, // TRN1_PPP_B |
| 9363 | 541163541U, // TRN1_PPP_D |
| 9364 | 71434261U, // TRN1_PPP_H |
| 9365 | 541229077U, // TRN1_PPP_S |
| 9366 | 4259861U, // TRN1_ZZZ_B |
| 9367 | 541163541U, // TRN1_ZZZ_D |
| 9368 | 71434261U, // TRN1_ZZZ_H |
| 9369 | 114196501U, // TRN1_ZZZ_Q |
| 9370 | 541229077U, // TRN1_ZZZ_S |
| 9371 | 1615004527U, // TRN1v16i8 |
| 9372 | 1615017069U, // TRN1v2i32 |
| 9373 | 1615008022U, // TRN1v2i64 |
| 9374 | 1615010388U, // TRN1v4i16 |
| 9375 | 1615018536U, // TRN1v4i32 |
| 9376 | 1615011902U, // TRN1v8i16 |
| 9377 | 1615005625U, // TRN1v8i8 |
| 9378 | 4259969U, // TRN2_PPP_B |
| 9379 | 541163649U, // TRN2_PPP_D |
| 9380 | 71434369U, // TRN2_PPP_H |
| 9381 | 541229185U, // TRN2_PPP_S |
| 9382 | 4259969U, // TRN2_ZZZ_B |
| 9383 | 541163649U, // TRN2_ZZZ_D |
| 9384 | 71434369U, // TRN2_ZZZ_H |
| 9385 | 114196609U, // TRN2_ZZZ_Q |
| 9386 | 541229185U, // TRN2_ZZZ_S |
| 9387 | 1615004648U, // TRN2v16i8 |
| 9388 | 1615017096U, // TRN2v2i32 |
| 9389 | 1615008300U, // TRN2v2i64 |
| 9390 | 1615010425U, // TRN2v4i16 |
| 9391 | 1615018916U, // TRN2v4i32 |
| 9392 | 1615012226U, // TRN2v8i16 |
| 9393 | 1615005662U, // TRN2v8i8 |
| 9394 | 888658U, // TSB |
| 9395 | 50854U, // TSTART |
| 9396 | 50876U, // TTEST |
| 9397 | 2688650296U, // UABALB_ZZZ_D |
| 9398 | 146934840U, // UABALB_ZZZ_H |
| 9399 | 1078103096U, // UABALB_ZZZ_S |
| 9400 | 2688664786U, // UABALT_ZZZ_D |
| 9401 | 146949330U, // UABALT_ZZZ_H |
| 9402 | 1078117586U, // UABALT_ZZZ_S |
| 9403 | 1615077486U, // UABALv16i8_v8i16 |
| 9404 | 1615074224U, // UABALv2i32_v2i64 |
| 9405 | 1615085181U, // UABALv4i16_v4i32 |
| 9406 | 1615073632U, // UABALv4i32_v2i64 |
| 9407 | 1615084174U, // UABALv8i16_v4i32 |
| 9408 | 1615078387U, // UABALv8i8_v8i16 |
| 9409 | 541131023U, // UABA_ZZZ_B |
| 9410 | 2151776527U, // UABA_ZZZ_D |
| 9411 | 84017423U, // UABA_ZZZ_H |
| 9412 | 2688712975U, // UABA_ZZZ_S |
| 9413 | 1615070322U, // UABAv16i8 |
| 9414 | 1615082678U, // UABAv2i32 |
| 9415 | 1615076007U, // UABAv4i16 |
| 9416 | 1615084641U, // UABAv4i32 |
| 9417 | 1615077925U, // UABAv8i16 |
| 9418 | 1615071254U, // UABAv8i8 |
| 9419 | 541166829U, // UABDLB_ZZZ_D |
| 9420 | 88214765U, // UABDLB_ZZZ_H |
| 9421 | 3762457837U, // UABDLB_ZZZ_S |
| 9422 | 541181219U, // UABDLT_ZZZ_D |
| 9423 | 88229155U, // UABDLT_ZZZ_H |
| 9424 | 3762472227U, // UABDLT_ZZZ_S |
| 9425 | 1615012016U, // UABDLv16i8_v8i16 |
| 9426 | 1615008760U, // UABDLv2i32_v2i64 |
| 9427 | 1615019717U, // UABDLv4i16_v4i32 |
| 9428 | 1615008175U, // UABDLv4i32_v2i64 |
| 9429 | 1615018717U, // UABDLv8i16_v4i32 |
| 9430 | 1615012911U, // UABDLv8i8_v8i16 |
| 9431 | 2151749499U, // UABD_ZPmZ_B |
| 9432 | 2151782267U, // UABD_ZPmZ_D |
| 9433 | 2713851771U, // UABD_ZPmZ_H |
| 9434 | 2151847803U, // UABD_ZPmZ_S |
| 9435 | 1615004933U, // UABDv16i8 |
| 9436 | 1615017294U, // UABDv2i32 |
| 9437 | 1615010623U, // UABDv4i16 |
| 9438 | 1615019291U, // UABDv4i32 |
| 9439 | 1615012541U, // UABDv8i16 |
| 9440 | 1615005830U, // UABDv8i8 |
| 9441 | 2151788636U, // UADALP_ZPmZ_D |
| 9442 | 2713858140U, // UADALP_ZPmZ_H |
| 9443 | 2151854172U, // UADALP_ZPmZ_S |
| 9444 | 1615078762U, // UADALPv16i8_v8i16 |
| 9445 | 1615073467U, // UADALPv2i32_v1i64 |
| 9446 | 1615083468U, // UADALPv4i16_v2i32 |
| 9447 | 1615074583U, // UADALPv4i32_v2i64 |
| 9448 | 1615085578U, // UADALPv8i16_v4i32 |
| 9449 | 1615076785U, // UADALPv8i8_v4i16 |
| 9450 | 541166854U, // UADDLB_ZZZ_D |
| 9451 | 88214790U, // UADDLB_ZZZ_H |
| 9452 | 3762457862U, // UADDLB_ZZZ_S |
| 9453 | 1615013248U, // UADDLPv16i8_v8i16 |
| 9454 | 1615007953U, // UADDLPv2i32_v1i64 |
| 9455 | 1615017954U, // UADDLPv4i16_v2i32 |
| 9456 | 1615009069U, // UADDLPv4i32_v2i64 |
| 9457 | 1615020064U, // UADDLPv8i16_v4i32 |
| 9458 | 1615011271U, // UADDLPv8i8_v4i16 |
| 9459 | 541181235U, // UADDLT_ZZZ_D |
| 9460 | 88229171U, // UADDLT_ZZZ_H |
| 9461 | 3762472243U, // UADDLT_ZZZ_S |
| 9462 | 1614841690U, // UADDLVv16i8v |
| 9463 | 1614847869U, // UADDLVv4i16v |
| 9464 | 1614856662U, // UADDLVv4i32v |
| 9465 | 1614849846U, // UADDLVv8i16v |
| 9466 | 1614842635U, // UADDLVv8i8v |
| 9467 | 1615012038U, // UADDLv16i8_v8i16 |
| 9468 | 1615008780U, // UADDLv2i32_v2i64 |
| 9469 | 1615019737U, // UADDLv4i16_v4i32 |
| 9470 | 1615008197U, // UADDLv4i32_v2i64 |
| 9471 | 1615018739U, // UADDLv8i16_v4i32 |
| 9472 | 1615012931U, // UADDLv8i8_v8i16 |
| 9473 | 3368568721U, // UADDV_VPZ_B |
| 9474 | 3301459857U, // UADDV_VPZ_D |
| 9475 | 3305654161U, // UADDV_VPZ_H |
| 9476 | 3246933905U, // UADDV_VPZ_S |
| 9477 | 541167587U, // UADDWB_ZZZ_D |
| 9478 | 71438307U, // UADDWB_ZZZ_H |
| 9479 | 541233123U, // UADDWB_ZZZ_S |
| 9480 | 541181727U, // UADDWT_ZZZ_D |
| 9481 | 71452447U, // UADDWT_ZZZ_H |
| 9482 | 541247263U, // UADDWT_ZZZ_S |
| 9483 | 1615012359U, // UADDWv16i8_v8i16 |
| 9484 | 1615009478U, // UADDWv2i32_v2i64 |
| 9485 | 1615020636U, // UADDWv4i16_v4i32 |
| 9486 | 1615008360U, // UADDWv4i32_v2i64 |
| 9487 | 1615019037U, // UADDWv8i16_v4i32 |
| 9488 | 1615013820U, // UADDWv8i8_v8i16 |
| 9489 | 4239035U, // UBFMWri |
| 9490 | 4239035U, // UBFMXri |
| 9491 | 147107964U, // UCLAMP_VG2_2Z2Z_B |
| 9492 | 80031868U, // UCLAMP_VG2_2Z2Z_D |
| 9493 | 84258940U, // UCLAMP_VG2_2Z2Z_H |
| 9494 | 25571452U, // UCLAMP_VG2_2Z2Z_S |
| 9495 | 147107964U, // UCLAMP_VG4_4Z4Z_B |
| 9496 | 80031868U, // UCLAMP_VG4_4Z4Z_D |
| 9497 | 84258940U, // UCLAMP_VG4_4Z4Z_H |
| 9498 | 25571452U, // UCLAMP_VG4_4Z4Z_S |
| 9499 | 541143164U, // UCLAMP_ZZZ_B |
| 9500 | 2151788668U, // UCLAMP_ZZZ_D |
| 9501 | 84029564U, // UCLAMP_ZZZ_H |
| 9502 | 2688725116U, // UCLAMP_ZZZ_S |
| 9503 | 4233457U, // UCVTFSWDri |
| 9504 | 4233457U, // UCVTFSWHri |
| 9505 | 4233457U, // UCVTFSWSri |
| 9506 | 4233457U, // UCVTFSXDri |
| 9507 | 4233457U, // UCVTFSXHri |
| 9508 | 4233457U, // UCVTFSXSri |
| 9509 | 4233457U, // UCVTFUWDri |
| 9510 | 4233457U, // UCVTFUWHri |
| 9511 | 4233457U, // UCVTFUWSri |
| 9512 | 4233457U, // UCVTFUXDri |
| 9513 | 4233457U, // UCVTFUXHri |
| 9514 | 4233457U, // UCVTFUXSri |
| 9515 | 3284539633U, // UCVTF_2Z2Z_StoS |
| 9516 | 3284539633U, // UCVTF_4Z4Z_StoS |
| 9517 | 541169905U, // UCVTF_ZPmZ_DtoD |
| 9518 | 2692880625U, // UCVTF_ZPmZ_DtoH |
| 9519 | 541235441U, // UCVTF_ZPmZ_DtoS |
| 9520 | 1082267889U, // UCVTF_ZPmZ_HtoH |
| 9521 | 541169905U, // UCVTF_ZPmZ_StoD |
| 9522 | 2156009713U, // UCVTF_ZPmZ_StoH |
| 9523 | 541235441U, // UCVTF_ZPmZ_StoS |
| 9524 | 4233457U, // UCVTFd |
| 9525 | 4233457U, // UCVTFh |
| 9526 | 4233457U, // UCVTFs |
| 9527 | 4233457U, // UCVTFv1i16 |
| 9528 | 4233457U, // UCVTFv1i32 |
| 9529 | 4233457U, // UCVTFv1i64 |
| 9530 | 1615017483U, // UCVTFv2f32 |
| 9531 | 1615008592U, // UCVTFv2f64 |
| 9532 | 1615017483U, // UCVTFv2i32_shift |
| 9533 | 1615008592U, // UCVTFv2i64_shift |
| 9534 | 1615010789U, // UCVTFv4f16 |
| 9535 | 1615019489U, // UCVTFv4f32 |
| 9536 | 1615010789U, // UCVTFv4i16_shift |
| 9537 | 1615019489U, // UCVTFv4i32_shift |
| 9538 | 1615012707U, // UCVTFv8f16 |
| 9539 | 1615012707U, // UCVTFv8i16_shift |
| 9540 | 39141U, // UDF |
| 9541 | 2151789499U, // UDIVR_ZPmZ_D |
| 9542 | 2151855035U, // UDIVR_ZPmZ_S |
| 9543 | 4245423U, // UDIVWr |
| 9544 | 4245423U, // UDIVXr |
| 9545 | 2151794607U, // UDIV_ZPmZ_D |
| 9546 | 2151860143U, // UDIV_ZPmZ_S |
| 9547 | 3288811108U, // UDOT_VG2_M2Z2Z_BtoS |
| 9548 | 3288778340U, // UDOT_VG2_M2Z2Z_HtoD |
| 9549 | 3288811108U, // UDOT_VG2_M2Z2Z_HtoS |
| 9550 | 3288811108U, // UDOT_VG2_M2ZZI_BToS |
| 9551 | 3288811108U, // UDOT_VG2_M2ZZI_HToS |
| 9552 | 3288778340U, // UDOT_VG2_M2ZZI_HtoD |
| 9553 | 3288811108U, // UDOT_VG2_M2ZZ_BtoS |
| 9554 | 3288778340U, // UDOT_VG2_M2ZZ_HtoD |
| 9555 | 3288811108U, // UDOT_VG2_M2ZZ_HtoS |
| 9556 | 3825682020U, // UDOT_VG4_M4Z4Z_BtoS |
| 9557 | 3825649252U, // UDOT_VG4_M4Z4Z_HtoD |
| 9558 | 3825682020U, // UDOT_VG4_M4Z4Z_HtoS |
| 9559 | 3825682020U, // UDOT_VG4_M4ZZI_BtoS |
| 9560 | 3825682020U, // UDOT_VG4_M4ZZI_HToS |
| 9561 | 3825649252U, // UDOT_VG4_M4ZZI_HtoD |
| 9562 | 3825682020U, // UDOT_VG4_M4ZZ_BtoS |
| 9563 | 3825649252U, // UDOT_VG4_M4ZZ_HtoD |
| 9564 | 3825682020U, // UDOT_VG4_M4ZZ_HtoS |
| 9565 | 1078052452U, // UDOT_ZZZI_D |
| 9566 | 1078117988U, // UDOT_ZZZI_HtoS |
| 9567 | 541247076U, // UDOT_ZZZI_S |
| 9568 | 1078052452U, // UDOT_ZZZ_D |
| 9569 | 1078117988U, // UDOT_ZZZ_HtoS |
| 9570 | 541247076U, // UDOT_ZZZ_S |
| 9571 | 1615087204U, // UDOTlanev16i8 |
| 9572 | 1615087204U, // UDOTlanev8i8 |
| 9573 | 20945U, // UDOTv16i8 |
| 9574 | 20945U, // UDOTv8i8 |
| 9575 | 2151749596U, // UHADD_ZPmZ_B |
| 9576 | 2151782364U, // UHADD_ZPmZ_D |
| 9577 | 2713851868U, // UHADD_ZPmZ_H |
| 9578 | 2151847900U, // UHADD_ZPmZ_S |
| 9579 | 1615004978U, // UHADDv16i8 |
| 9580 | 1615017354U, // UHADDv2i32 |
| 9581 | 1615010683U, // UHADDv4i16 |
| 9582 | 1615019351U, // UHADDv4i32 |
| 9583 | 1615012601U, // UHADDv8i16 |
| 9584 | 1615005871U, // UHADDv8i8 |
| 9585 | 2151756357U, // UHSUBR_ZPmZ_B |
| 9586 | 2151789125U, // UHSUBR_ZPmZ_D |
| 9587 | 2713858629U, // UHSUBR_ZPmZ_H |
| 9588 | 2151854661U, // UHSUBR_ZPmZ_S |
| 9589 | 2151747489U, // UHSUB_ZPmZ_B |
| 9590 | 2151780257U, // UHSUB_ZPmZ_D |
| 9591 | 2713849761U, // UHSUB_ZPmZ_H |
| 9592 | 2151845793U, // UHSUB_ZPmZ_S |
| 9593 | 1615004858U, // UHSUBv16i8 |
| 9594 | 1615017238U, // UHSUBv2i32 |
| 9595 | 1615010567U, // UHSUBv4i16 |
| 9596 | 1615019225U, // UHSUBv4i32 |
| 9597 | 1615012485U, // UHSUBv8i16 |
| 9598 | 1615005783U, // UHSUBv8i8 |
| 9599 | 4238507U, // UMADDLrrr |
| 9600 | 2151756153U, // UMAXP_ZPmZ_B |
| 9601 | 2151788921U, // UMAXP_ZPmZ_D |
| 9602 | 2713858425U, // UMAXP_ZPmZ_H |
| 9603 | 2151854457U, // UMAXP_ZPmZ_S |
| 9604 | 1615005308U, // UMAXPv16i8 |
| 9605 | 1615018058U, // UMAXPv2i32 |
| 9606 | 1615011375U, // UMAXPv4i16 |
| 9607 | 1615020168U, // UMAXPv4i32 |
| 9608 | 1615013352U, // UMAXPv8i16 |
| 9609 | 1615006275U, // UMAXPv8i8 |
| 9610 | 2181253185U, // UMAXQV_VPZ_B |
| 9611 | 2185447489U, // UMAXQV_VPZ_D |
| 9612 | 2189641793U, // UMAXQV_VPZ_H |
| 9613 | 2193836097U, // UMAXQV_VPZ_S |
| 9614 | 510045U, // UMAXV_VPZ_B |
| 9615 | 3301460061U, // UMAXV_VPZ_D |
| 9616 | 3305687133U, // UMAXV_VPZ_H |
| 9617 | 3246999645U, // UMAXV_VPZ_S |
| 9618 | 1614841735U, // UMAXVv16i8v |
| 9619 | 1614847963U, // UMAXVv4i16v |
| 9620 | 1614856756U, // UMAXVv4i32v |
| 9621 | 1614849940U, // UMAXVv8i16v |
| 9622 | 1614842676U, // UMAXVv8i8v |
| 9623 | 4245935U, // UMAXWri |
| 9624 | 4245935U, // UMAXWrr |
| 9625 | 4245935U, // UMAXXri |
| 9626 | 4245935U, // UMAXXrr |
| 9627 | 50645423U, // UMAX_VG2_2Z2Z_B |
| 9628 | 54872495U, // UMAX_VG2_2Z2Z_D |
| 9629 | 59099567U, // UMAX_VG2_2Z2Z_H |
| 9630 | 63326639U, // UMAX_VG2_2Z2Z_S |
| 9631 | 50645423U, // UMAX_VG2_2ZZ_B |
| 9632 | 54872495U, // UMAX_VG2_2ZZ_D |
| 9633 | 59099567U, // UMAX_VG2_2ZZ_H |
| 9634 | 63326639U, // UMAX_VG2_2ZZ_S |
| 9635 | 50645423U, // UMAX_VG4_4Z4Z_B |
| 9636 | 54872495U, // UMAX_VG4_4Z4Z_D |
| 9637 | 59099567U, // UMAX_VG4_4Z4Z_H |
| 9638 | 63326639U, // UMAX_VG4_4Z4Z_S |
| 9639 | 50645423U, // UMAX_VG4_4ZZ_B |
| 9640 | 54872495U, // UMAX_VG4_4ZZ_D |
| 9641 | 59099567U, // UMAX_VG4_4ZZ_H |
| 9642 | 63326639U, // UMAX_VG4_4ZZ_S |
| 9643 | 4278703U, // UMAX_ZI_B |
| 9644 | 541182383U, // UMAX_ZI_D |
| 9645 | 71453103U, // UMAX_ZI_H |
| 9646 | 541247919U, // UMAX_ZI_S |
| 9647 | 2151762351U, // UMAX_ZPmZ_B |
| 9648 | 2151795119U, // UMAX_ZPmZ_D |
| 9649 | 2713864623U, // UMAX_ZPmZ_H |
| 9650 | 2151860655U, // UMAX_ZPmZ_S |
| 9651 | 1615005606U, // UMAXv16i8 |
| 9652 | 1615018435U, // UMAXv2i32 |
| 9653 | 1615011841U, // UMAXv4i16 |
| 9654 | 1615020700U, // UMAXv4i32 |
| 9655 | 1615013858U, // UMAXv8i16 |
| 9656 | 1615006535U, // UMAXv8i8 |
| 9657 | 2151755959U, // UMINP_ZPmZ_B |
| 9658 | 2151788727U, // UMINP_ZPmZ_D |
| 9659 | 2713858231U, // UMINP_ZPmZ_H |
| 9660 | 2151854263U, // UMINP_ZPmZ_S |
| 9661 | 1615005277U, // UMINPv16i8 |
| 9662 | 1615018009U, // UMINPv2i32 |
| 9663 | 1615011326U, // UMINPv4i16 |
| 9664 | 1615020119U, // UMINPv4i32 |
| 9665 | 1615013303U, // UMINPv8i16 |
| 9666 | 1615006247U, // UMINPv8i8 |
| 9667 | 2181253154U, // UMINQV_VPZ_B |
| 9668 | 2185447458U, // UMINQV_VPZ_D |
| 9669 | 2189641762U, // UMINQV_VPZ_H |
| 9670 | 2193836066U, // UMINQV_VPZ_S |
| 9671 | 509909U, // UMINV_VPZ_B |
| 9672 | 3301459925U, // UMINV_VPZ_D |
| 9673 | 3305686997U, // UMINV_VPZ_H |
| 9674 | 3246999509U, // UMINV_VPZ_S |
| 9675 | 1614841713U, // UMINVv16i8v |
| 9676 | 1614847924U, // UMINVv4i16v |
| 9677 | 1614856717U, // UMINVv4i32v |
| 9678 | 1614849901U, // UMINVv8i16v |
| 9679 | 1614842656U, // UMINVv8i8v |
| 9680 | 4239163U, // UMINWri |
| 9681 | 4239163U, // UMINWrr |
| 9682 | 4239163U, // UMINXri |
| 9683 | 4239163U, // UMINXrr |
| 9684 | 50638651U, // UMIN_VG2_2Z2Z_B |
| 9685 | 54865723U, // UMIN_VG2_2Z2Z_D |
| 9686 | 59092795U, // UMIN_VG2_2Z2Z_H |
| 9687 | 63319867U, // UMIN_VG2_2Z2Z_S |
| 9688 | 50638651U, // UMIN_VG2_2ZZ_B |
| 9689 | 54865723U, // UMIN_VG2_2ZZ_D |
| 9690 | 59092795U, // UMIN_VG2_2ZZ_H |
| 9691 | 63319867U, // UMIN_VG2_2ZZ_S |
| 9692 | 50638651U, // UMIN_VG4_4Z4Z_B |
| 9693 | 54865723U, // UMIN_VG4_4Z4Z_D |
| 9694 | 59092795U, // UMIN_VG4_4Z4Z_H |
| 9695 | 63319867U, // UMIN_VG4_4Z4Z_S |
| 9696 | 50638651U, // UMIN_VG4_4ZZ_B |
| 9697 | 54865723U, // UMIN_VG4_4ZZ_D |
| 9698 | 59092795U, // UMIN_VG4_4ZZ_H |
| 9699 | 63319867U, // UMIN_VG4_4ZZ_S |
| 9700 | 4271931U, // UMIN_ZI_B |
| 9701 | 541175611U, // UMIN_ZI_D |
| 9702 | 71446331U, // UMIN_ZI_H |
| 9703 | 541241147U, // UMIN_ZI_S |
| 9704 | 2151755579U, // UMIN_ZPmZ_B |
| 9705 | 2151788347U, // UMIN_ZPmZ_D |
| 9706 | 2713857851U, // UMIN_ZPmZ_H |
| 9707 | 2151853883U, // UMIN_ZPmZ_S |
| 9708 | 1615005237U, // UMINv16i8 |
| 9709 | 1615017789U, // UMINv2i32 |
| 9710 | 1615011095U, // UMINv4i16 |
| 9711 | 1615019991U, // UMINv4i32 |
| 9712 | 1615013185U, // UMINv8i16 |
| 9713 | 1615006109U, // UMINv8i8 |
| 9714 | 2688650341U, // UMLALB_ZZZI_D |
| 9715 | 1078103141U, // UMLALB_ZZZI_S |
| 9716 | 2688650341U, // UMLALB_ZZZ_D |
| 9717 | 146934885U, // UMLALB_ZZZ_H |
| 9718 | 1078103141U, // UMLALB_ZZZ_S |
| 9719 | 3376885019U, // UMLALL_MZZI_BtoS |
| 9720 | 3376852251U, // UMLALL_MZZI_HtoD |
| 9721 | 3376885019U, // UMLALL_MZZ_BtoS |
| 9722 | 3376852251U, // UMLALL_MZZ_HtoD |
| 9723 | 3376885019U, // UMLALL_VG2_M2Z2Z_BtoS |
| 9724 | 3376852251U, // UMLALL_VG2_M2Z2Z_HtoD |
| 9725 | 3376885019U, // UMLALL_VG2_M2ZZI_BtoS |
| 9726 | 3376852251U, // UMLALL_VG2_M2ZZI_HtoD |
| 9727 | 3913755931U, // UMLALL_VG2_M2ZZ_BtoS |
| 9728 | 3913723163U, // UMLALL_VG2_M2ZZ_HtoD |
| 9729 | 3913755931U, // UMLALL_VG4_M4Z4Z_BtoS |
| 9730 | 3913723163U, // UMLALL_VG4_M4Z4Z_HtoD |
| 9731 | 3913755931U, // UMLALL_VG4_M4ZZI_BtoS |
| 9732 | 3913723163U, // UMLALL_VG4_M4ZZI_HtoD |
| 9733 | 155659547U, // UMLALL_VG4_M4ZZ_BtoS |
| 9734 | 155626779U, // UMLALL_VG4_M4ZZ_HtoD |
| 9735 | 2688664821U, // UMLALT_ZZZI_D |
| 9736 | 1078117621U, // UMLALT_ZZZI_S |
| 9737 | 2688664821U, // UMLALT_ZZZ_D |
| 9738 | 146949365U, // UMLALT_ZZZ_H |
| 9739 | 1078117621U, // UMLALT_ZZZ_S |
| 9740 | 3313970040U, // UMLAL_MZZI_HtoS |
| 9741 | 3313970040U, // UMLAL_MZZ_HtoS |
| 9742 | 3313970040U, // UMLAL_VG2_M2Z2Z_HtoS |
| 9743 | 3313970040U, // UMLAL_VG2_M2ZZI_S |
| 9744 | 3313970040U, // UMLAL_VG2_M2ZZ_HtoS |
| 9745 | 3850840952U, // UMLAL_VG4_M4Z4Z_HtoS |
| 9746 | 3850840952U, // UMLAL_VG4_M4ZZI_HtoS |
| 9747 | 3850840952U, // UMLAL_VG4_M4ZZ_HtoS |
| 9748 | 1615077508U, // UMLALv16i8_v8i16 |
| 9749 | 1615074256U, // UMLALv2i32_indexed |
| 9750 | 1615074256U, // UMLALv2i32_v2i64 |
| 9751 | 1615085213U, // UMLALv4i16_indexed |
| 9752 | 1615085213U, // UMLALv4i16_v4i32 |
| 9753 | 1615073667U, // UMLALv4i32_indexed |
| 9754 | 1615073667U, // UMLALv4i32_v2i64 |
| 9755 | 1615084209U, // UMLALv8i16_indexed |
| 9756 | 1615084209U, // UMLALv8i16_v4i32 |
| 9757 | 1615078407U, // UMLALv8i8_v8i16 |
| 9758 | 2688650639U, // UMLSLB_ZZZI_D |
| 9759 | 1078103439U, // UMLSLB_ZZZI_S |
| 9760 | 2688650639U, // UMLSLB_ZZZ_D |
| 9761 | 146935183U, // UMLSLB_ZZZ_H |
| 9762 | 1078103439U, // UMLSLB_ZZZ_S |
| 9763 | 3376885035U, // UMLSLL_MZZI_BtoS |
| 9764 | 3376852267U, // UMLSLL_MZZI_HtoD |
| 9765 | 3376885035U, // UMLSLL_MZZ_BtoS |
| 9766 | 3376852267U, // UMLSLL_MZZ_HtoD |
| 9767 | 3376885035U, // UMLSLL_VG2_M2Z2Z_BtoS |
| 9768 | 3376852267U, // UMLSLL_VG2_M2Z2Z_HtoD |
| 9769 | 3376885035U, // UMLSLL_VG2_M2ZZI_BtoS |
| 9770 | 3376852267U, // UMLSLL_VG2_M2ZZI_HtoD |
| 9771 | 3913755947U, // UMLSLL_VG2_M2ZZ_BtoS |
| 9772 | 3913723179U, // UMLSLL_VG2_M2ZZ_HtoD |
| 9773 | 3913755947U, // UMLSLL_VG4_M4Z4Z_BtoS |
| 9774 | 3913723179U, // UMLSLL_VG4_M4Z4Z_HtoD |
| 9775 | 3913755947U, // UMLSLL_VG4_M4ZZI_BtoS |
| 9776 | 3913723179U, // UMLSLL_VG4_M4ZZI_HtoD |
| 9777 | 155659563U, // UMLSLL_VG4_M4ZZ_BtoS |
| 9778 | 155626795U, // UMLSLL_VG4_M4ZZ_HtoD |
| 9779 | 2688664996U, // UMLSLT_ZZZI_D |
| 9780 | 1078117796U, // UMLSLT_ZZZI_S |
| 9781 | 2688664996U, // UMLSLT_ZZZ_D |
| 9782 | 146949540U, // UMLSLT_ZZZ_H |
| 9783 | 1078117796U, // UMLSLT_ZZZ_S |
| 9784 | 3313970730U, // UMLSL_MZZI_HtoS |
| 9785 | 3313970730U, // UMLSL_MZZ_HtoS |
| 9786 | 3313970730U, // UMLSL_VG2_M2Z2Z_HtoS |
| 9787 | 3313970730U, // UMLSL_VG2_M2ZZI_S |
| 9788 | 3313970730U, // UMLSL_VG2_M2ZZ_HtoS |
| 9789 | 3850841642U, // UMLSL_VG4_M4Z4Z_HtoS |
| 9790 | 3850841642U, // UMLSL_VG4_M4ZZI_HtoS |
| 9791 | 3850841642U, // UMLSL_VG4_M4ZZ_HtoS |
| 9792 | 1615077651U, // UMLSLv16i8_v8i16 |
| 9793 | 1615074480U, // UMLSLv2i32_indexed |
| 9794 | 1615074480U, // UMLSLv2i32_v2i64 |
| 9795 | 1615085437U, // UMLSLv4i16_indexed |
| 9796 | 1615085437U, // UMLSLv4i16_v4i32 |
| 9797 | 1615073825U, // UMLSLv4i32_indexed |
| 9798 | 1615073825U, // UMLSLv4i32_v2i64 |
| 9799 | 1615084367U, // UMLSLv8i16_indexed |
| 9800 | 1615084367U, // UMLSLv8i16_v4i32 |
| 9801 | 1615078617U, // UMLSLv8i8_v8i16 |
| 9802 | 20736U, // UMMLA |
| 9803 | 541229426U, // UMMLA_ZZZ |
| 9804 | 96698801U, // UMOPA_MPPZZ_D |
| 9805 | 96698801U, // UMOPA_MPPZZ_HtoS |
| 9806 | 159613361U, // UMOPA_MPPZZ_S |
| 9807 | 96715745U, // UMOPS_MPPZZ_D |
| 9808 | 96715745U, // UMOPS_MPPZZ_HtoS |
| 9809 | 159630305U, // UMOPS_MPPZZ_S |
| 9810 | 1614846394U, // UMOVvi16 |
| 9811 | 1614846394U, // UMOVvi16_idx0 |
| 9812 | 1614853212U, // UMOVvi32 |
| 9813 | 1614853212U, // UMOVvi32_idx0 |
| 9814 | 1614844063U, // UMOVvi64 |
| 9815 | 1614844063U, // UMOVvi64_idx0 |
| 9816 | 1614840577U, // UMOVvi8 |
| 9817 | 1614840577U, // UMOVvi8_idx0 |
| 9818 | 4238483U, // UMSUBLrrr |
| 9819 | 2151754117U, // UMULH_ZPmZ_B |
| 9820 | 2151786885U, // UMULH_ZPmZ_D |
| 9821 | 2713856389U, // UMULH_ZPmZ_H |
| 9822 | 2151852421U, // UMULH_ZPmZ_S |
| 9823 | 4270469U, // UMULH_ZZZ_B |
| 9824 | 541174149U, // UMULH_ZZZ_D |
| 9825 | 71444869U, // UMULH_ZZZ_H |
| 9826 | 541239685U, // UMULH_ZZZ_S |
| 9827 | 4237701U, // UMULHrr |
| 9828 | 541166904U, // UMULLB_ZZZI_D |
| 9829 | 3762457912U, // UMULLB_ZZZI_S |
| 9830 | 541166904U, // UMULLB_ZZZ_D |
| 9831 | 88214840U, // UMULLB_ZZZ_H |
| 9832 | 3762457912U, // UMULLB_ZZZ_S |
| 9833 | 541181299U, // UMULLT_ZZZI_D |
| 9834 | 3762472307U, // UMULLT_ZZZI_S |
| 9835 | 541181299U, // UMULLT_ZZZ_D |
| 9836 | 88229235U, // UMULLT_ZZZ_H |
| 9837 | 3762472307U, // UMULLT_ZZZ_S |
| 9838 | 1615012093U, // UMULLv16i8_v8i16 |
| 9839 | 1615008912U, // UMULLv2i32_indexed |
| 9840 | 1615008912U, // UMULLv2i32_v2i64 |
| 9841 | 1615019869U, // UMULLv4i16_indexed |
| 9842 | 1615019869U, // UMULLv4i16_v4i32 |
| 9843 | 1615008254U, // UMULLv4i32_indexed |
| 9844 | 1615008254U, // UMULLv4i32_v2i64 |
| 9845 | 1615018796U, // UMULLv8i16_indexed |
| 9846 | 1615018796U, // UMULLv8i16_v4i32 |
| 9847 | 1615013061U, // UMULLv8i8_v8i16 |
| 9848 | 4265979U, // UQADD_ZI_B |
| 9849 | 541169659U, // UQADD_ZI_D |
| 9850 | 71440379U, // UQADD_ZI_H |
| 9851 | 541235195U, // UQADD_ZI_S |
| 9852 | 2151749627U, // UQADD_ZPmZ_B |
| 9853 | 2151782395U, // UQADD_ZPmZ_D |
| 9854 | 2713851899U, // UQADD_ZPmZ_H |
| 9855 | 2151847931U, // UQADD_ZPmZ_S |
| 9856 | 4265979U, // UQADD_ZZZ_B |
| 9857 | 541169659U, // UQADD_ZZZ_D |
| 9858 | 71440379U, // UQADD_ZZZ_H |
| 9859 | 541235195U, // UQADD_ZZZ_S |
| 9860 | 1615005002U, // UQADDv16i8 |
| 9861 | 4233211U, // UQADDv1i16 |
| 9862 | 4233211U, // UQADDv1i32 |
| 9863 | 4233211U, // UQADDv1i64 |
| 9864 | 4233211U, // UQADDv1i8 |
| 9865 | 1615017376U, // UQADDv2i32 |
| 9866 | 1615008508U, // UQADDv2i64 |
| 9867 | 1615010705U, // UQADDv4i16 |
| 9868 | 1615019373U, // UQADDv4i32 |
| 9869 | 1615012623U, // UQADDv8i16 |
| 9870 | 1615005893U, // UQADDv8i8 |
| 9871 | 3284283281U, // UQCVTN_Z2Z_StoH |
| 9872 | 3275894673U, // UQCVTN_Z4Z_DtoH |
| 9873 | 2151755665U, // UQCVTN_Z4Z_StoB |
| 9874 | 3284289274U, // UQCVT_Z2Z_StoH |
| 9875 | 3275900666U, // UQCVT_Z4Z_DtoH |
| 9876 | 2151761658U, // UQCVT_Z4Z_StoB |
| 9877 | 1077971937U, // UQDECB_WPiI |
| 9878 | 1077971937U, // UQDECB_XPiI |
| 9879 | 1077974928U, // UQDECD_WPiI |
| 9880 | 1077974928U, // UQDECD_XPiI |
| 9881 | 1078040464U, // UQDECD_ZPiI |
| 9882 | 1077979283U, // UQDECH_WPiI |
| 9883 | 1077979283U, // UQDECH_XPiI |
| 9884 | 100804755U, // UQDECH_ZPiI |
| 9885 | 4239391U, // UQDECP_WP_B |
| 9886 | 541110303U, // UQDECP_WP_D |
| 9887 | 3762335775U, // UQDECP_WP_H |
| 9888 | 541110303U, // UQDECP_WP_S |
| 9889 | 4239391U, // UQDECP_XP_B |
| 9890 | 541110303U, // UQDECP_XP_D |
| 9891 | 3762335775U, // UQDECP_XP_H |
| 9892 | 541110303U, // UQDECP_XP_S |
| 9893 | 2151788575U, // UQDECP_ZP_D |
| 9894 | 3305254943U, // UQDECP_ZP_H |
| 9895 | 2688725023U, // UQDECP_ZP_S |
| 9896 | 1077987533U, // UQDECW_WPiI |
| 9897 | 1077987533U, // UQDECW_XPiI |
| 9898 | 1078118605U, // UQDECW_ZPiI |
| 9899 | 1077971953U, // UQINCB_WPiI |
| 9900 | 1077971953U, // UQINCB_XPiI |
| 9901 | 1077974944U, // UQINCD_WPiI |
| 9902 | 1077974944U, // UQINCD_XPiI |
| 9903 | 1078040480U, // UQINCD_ZPiI |
| 9904 | 1077979299U, // UQINCH_WPiI |
| 9905 | 1077979299U, // UQINCH_XPiI |
| 9906 | 100804771U, // UQINCH_ZPiI |
| 9907 | 4239407U, // UQINCP_WP_B |
| 9908 | 541110319U, // UQINCP_WP_D |
| 9909 | 3762335791U, // UQINCP_WP_H |
| 9910 | 541110319U, // UQINCP_WP_S |
| 9911 | 4239407U, // UQINCP_XP_B |
| 9912 | 541110319U, // UQINCP_XP_D |
| 9913 | 3762335791U, // UQINCP_XP_H |
| 9914 | 541110319U, // UQINCP_XP_S |
| 9915 | 2151788591U, // UQINCP_ZP_D |
| 9916 | 3305254959U, // UQINCP_ZP_H |
| 9917 | 2688725039U, // UQINCP_ZP_S |
| 9918 | 1077987549U, // UQINCW_WPiI |
| 9919 | 1077987549U, // UQINCW_XPiI |
| 9920 | 1078118621U, // UQINCW_ZPiI |
| 9921 | 2151756549U, // UQRSHLR_ZPmZ_B |
| 9922 | 2151789317U, // UQRSHLR_ZPmZ_D |
| 9923 | 2713858821U, // UQRSHLR_ZPmZ_H |
| 9924 | 2151854853U, // UQRSHLR_ZPmZ_S |
| 9925 | 2151754983U, // UQRSHL_ZPmZ_B |
| 9926 | 2151787751U, // UQRSHL_ZPmZ_D |
| 9927 | 2713857255U, // UQRSHL_ZPmZ_H |
| 9928 | 2151853287U, // UQRSHL_ZPmZ_S |
| 9929 | 1615005154U, // UQRSHLv16i8 |
| 9930 | 4238567U, // UQRSHLv1i16 |
| 9931 | 4238567U, // UQRSHLv1i32 |
| 9932 | 4238567U, // UQRSHLv1i64 |
| 9933 | 4238567U, // UQRSHLv1i8 |
| 9934 | 1615017648U, // UQRSHLv2i32 |
| 9935 | 1615008821U, // UQRSHLv2i64 |
| 9936 | 1615010954U, // UQRSHLv4i16 |
| 9937 | 1615019778U, // UQRSHLv4i32 |
| 9938 | 1615012972U, // UQRSHLv8i16 |
| 9939 | 1615006012U, // UQRSHLv8i8 |
| 9940 | 3762359801U, // UQRSHRNB_ZZI_B |
| 9941 | 21106169U, // UQRSHRNB_ZZI_H |
| 9942 | 541232633U, // UQRSHRNB_ZZI_S |
| 9943 | 1078019589U, // UQRSHRNT_ZZI_B |
| 9944 | 25314821U, // UQRSHRNT_ZZI_H |
| 9945 | 2151859717U, // UQRSHRNT_ZZI_S |
| 9946 | 2151755627U, // UQRSHRN_VG4_Z4ZI_B |
| 9947 | 54669163U, // UQRSHRN_VG4_Z4ZI_H |
| 9948 | 63057771U, // UQRSHRN_Z2ZI_StoH |
| 9949 | 4239211U, // UQRSHRNb |
| 9950 | 4239211U, // UQRSHRNh |
| 9951 | 4239211U, // UQRSHRNs |
| 9952 | 1615070170U, // UQRSHRNv16i8_shift |
| 9953 | 1615017832U, // UQRSHRNv2i32_shift |
| 9954 | 1615011138U, // UQRSHRNv4i16_shift |
| 9955 | 1615084439U, // UQRSHRNv4i32_shift |
| 9956 | 1615077749U, // UQRSHRNv8i16_shift |
| 9957 | 1615006152U, // UQRSHRNv8i8_shift |
| 9958 | 63058605U, // UQRSHR_VG2_Z2ZI_H |
| 9959 | 2151756461U, // UQRSHR_VG4_Z4ZI_B |
| 9960 | 54669997U, // UQRSHR_VG4_Z4ZI_H |
| 9961 | 2151756532U, // UQSHLR_ZPmZ_B |
| 9962 | 2151789300U, // UQSHLR_ZPmZ_D |
| 9963 | 2713858804U, // UQSHLR_ZPmZ_H |
| 9964 | 2151854836U, // UQSHLR_ZPmZ_S |
| 9965 | 2151754968U, // UQSHL_ZPmI_B |
| 9966 | 2151787736U, // UQSHL_ZPmI_D |
| 9967 | 2713857240U, // UQSHL_ZPmI_H |
| 9968 | 2151853272U, // UQSHL_ZPmI_S |
| 9969 | 2151754968U, // UQSHL_ZPmZ_B |
| 9970 | 2151787736U, // UQSHL_ZPmZ_D |
| 9971 | 2713857240U, // UQSHL_ZPmZ_H |
| 9972 | 2151853272U, // UQSHL_ZPmZ_S |
| 9973 | 4238552U, // UQSHLb |
| 9974 | 4238552U, // UQSHLd |
| 9975 | 4238552U, // UQSHLh |
| 9976 | 4238552U, // UQSHLs |
| 9977 | 1615005131U, // UQSHLv16i8 |
| 9978 | 1615005131U, // UQSHLv16i8_shift |
| 9979 | 4238552U, // UQSHLv1i16 |
| 9980 | 4238552U, // UQSHLv1i32 |
| 9981 | 4238552U, // UQSHLv1i64 |
| 9982 | 4238552U, // UQSHLv1i8 |
| 9983 | 1615017627U, // UQSHLv2i32 |
| 9984 | 1615017627U, // UQSHLv2i32_shift |
| 9985 | 1615008800U, // UQSHLv2i64 |
| 9986 | 1615008800U, // UQSHLv2i64_shift |
| 9987 | 1615010933U, // UQSHLv4i16 |
| 9988 | 1615010933U, // UQSHLv4i16_shift |
| 9989 | 1615019757U, // UQSHLv4i32 |
| 9990 | 1615019757U, // UQSHLv4i32_shift |
| 9991 | 1615012951U, // UQSHLv8i16 |
| 9992 | 1615012951U, // UQSHLv8i16_shift |
| 9993 | 1615005991U, // UQSHLv8i8 |
| 9994 | 1615005991U, // UQSHLv8i8_shift |
| 9995 | 3762359782U, // UQSHRNB_ZZI_B |
| 9996 | 21106150U, // UQSHRNB_ZZI_H |
| 9997 | 541232614U, // UQSHRNB_ZZI_S |
| 9998 | 1078019570U, // UQSHRNT_ZZI_B |
| 9999 | 25314802U, // UQSHRNT_ZZI_H |
| 10000 | 2151859698U, // UQSHRNT_ZZI_S |
| 10001 | 4239194U, // UQSHRNb |
| 10002 | 4239194U, // UQSHRNh |
| 10003 | 4239194U, // UQSHRNs |
| 10004 | 1615070143U, // UQSHRNv16i8_shift |
| 10005 | 1615017809U, // UQSHRNv2i32_shift |
| 10006 | 1615011115U, // UQSHRNv4i16_shift |
| 10007 | 1615084414U, // UQSHRNv4i32_shift |
| 10008 | 1615077724U, // UQSHRNv8i16_shift |
| 10009 | 1615006129U, // UQSHRNv8i8_shift |
| 10010 | 2151756373U, // UQSUBR_ZPmZ_B |
| 10011 | 2151789141U, // UQSUBR_ZPmZ_D |
| 10012 | 2713858645U, // UQSUBR_ZPmZ_H |
| 10013 | 2151854677U, // UQSUBR_ZPmZ_S |
| 10014 | 4263870U, // UQSUB_ZI_B |
| 10015 | 541167550U, // UQSUB_ZI_D |
| 10016 | 71438270U, // UQSUB_ZI_H |
| 10017 | 541233086U, // UQSUB_ZI_S |
| 10018 | 2151747518U, // UQSUB_ZPmZ_B |
| 10019 | 2151780286U, // UQSUB_ZPmZ_D |
| 10020 | 2713849790U, // UQSUB_ZPmZ_H |
| 10021 | 2151845822U, // UQSUB_ZPmZ_S |
| 10022 | 4263870U, // UQSUB_ZZZ_B |
| 10023 | 541167550U, // UQSUB_ZZZ_D |
| 10024 | 71438270U, // UQSUB_ZZZ_H |
| 10025 | 541233086U, // UQSUB_ZZZ_S |
| 10026 | 1615004880U, // UQSUBv16i8 |
| 10027 | 4231102U, // UQSUBv1i16 |
| 10028 | 4231102U, // UQSUBv1i32 |
| 10029 | 4231102U, // UQSUBv1i64 |
| 10030 | 4231102U, // UQSUBv1i8 |
| 10031 | 1615017258U, // UQSUBv2i32 |
| 10032 | 1615008458U, // UQSUBv2i64 |
| 10033 | 1615010587U, // UQSUBv4i16 |
| 10034 | 1615019245U, // UQSUBv4i32 |
| 10035 | 1615012505U, // UQSUBv8i16 |
| 10036 | 1615005803U, // UQSUBv8i8 |
| 10037 | 3762359827U, // UQXTNB_ZZ_B |
| 10038 | 3242331667U, // UQXTNB_ZZ_H |
| 10039 | 541232659U, // UQXTNB_ZZ_S |
| 10040 | 1078019616U, // UQXTNT_ZZ_B |
| 10041 | 3246540320U, // UQXTNT_ZZ_H |
| 10042 | 2151859744U, // UQXTNT_ZZ_S |
| 10043 | 1615070206U, // UQXTNv16i8 |
| 10044 | 4239264U, // UQXTNv1i16 |
| 10045 | 4239264U, // UQXTNv1i32 |
| 10046 | 4239264U, // UQXTNv1i8 |
| 10047 | 1615017865U, // UQXTNv2i32 |
| 10048 | 1615011182U, // UQXTNv4i16 |
| 10049 | 1615084472U, // UQXTNv4i32 |
| 10050 | 1615077794U, // UQXTNv8i16 |
| 10051 | 1615006182U, // UQXTNv8i8 |
| 10052 | 541235367U, // URECPE_ZPmZ_S |
| 10053 | 1615017438U, // URECPEv2i32 |
| 10054 | 1615019444U, // URECPEv4i32 |
| 10055 | 2151749581U, // URHADD_ZPmZ_B |
| 10056 | 2151782349U, // URHADD_ZPmZ_D |
| 10057 | 2713851853U, // URHADD_ZPmZ_H |
| 10058 | 2151847885U, // URHADD_ZPmZ_S |
| 10059 | 1615004955U, // URHADDv16i8 |
| 10060 | 1615017333U, // URHADDv2i32 |
| 10061 | 1615010662U, // URHADDv4i16 |
| 10062 | 1615019330U, // URHADDv4i32 |
| 10063 | 1615012580U, // URHADDv8i16 |
| 10064 | 1615005850U, // URHADDv8i8 |
| 10065 | 2151756566U, // URSHLR_ZPmZ_B |
| 10066 | 2151789334U, // URSHLR_ZPmZ_D |
| 10067 | 2713858838U, // URSHLR_ZPmZ_H |
| 10068 | 2151854870U, // URSHLR_ZPmZ_S |
| 10069 | 50638070U, // URSHL_VG2_2Z2Z_B |
| 10070 | 54865142U, // URSHL_VG2_2Z2Z_D |
| 10071 | 59092214U, // URSHL_VG2_2Z2Z_H |
| 10072 | 63319286U, // URSHL_VG2_2Z2Z_S |
| 10073 | 50638070U, // URSHL_VG2_2ZZ_B |
| 10074 | 54865142U, // URSHL_VG2_2ZZ_D |
| 10075 | 59092214U, // URSHL_VG2_2ZZ_H |
| 10076 | 63319286U, // URSHL_VG2_2ZZ_S |
| 10077 | 50638070U, // URSHL_VG4_4Z4Z_B |
| 10078 | 54865142U, // URSHL_VG4_4Z4Z_D |
| 10079 | 59092214U, // URSHL_VG4_4Z4Z_H |
| 10080 | 63319286U, // URSHL_VG4_4Z4Z_S |
| 10081 | 50638070U, // URSHL_VG4_4ZZ_B |
| 10082 | 54865142U, // URSHL_VG4_4ZZ_D |
| 10083 | 59092214U, // URSHL_VG4_4ZZ_H |
| 10084 | 63319286U, // URSHL_VG4_4ZZ_S |
| 10085 | 2151754998U, // URSHL_ZPmZ_B |
| 10086 | 2151787766U, // URSHL_ZPmZ_D |
| 10087 | 2713857270U, // URSHL_ZPmZ_H |
| 10088 | 2151853302U, // URSHL_ZPmZ_S |
| 10089 | 1615005177U, // URSHLv16i8 |
| 10090 | 4238582U, // URSHLv1i64 |
| 10091 | 1615017669U, // URSHLv2i32 |
| 10092 | 1615008842U, // URSHLv2i64 |
| 10093 | 1615010975U, // URSHLv4i16 |
| 10094 | 1615019799U, // URSHLv4i32 |
| 10095 | 1615012993U, // URSHLv8i16 |
| 10096 | 1615006033U, // URSHLv8i8 |
| 10097 | 2151756476U, // URSHR_ZPmI_B |
| 10098 | 2151789244U, // URSHR_ZPmI_D |
| 10099 | 2713858748U, // URSHR_ZPmI_H |
| 10100 | 2151854780U, // URSHR_ZPmI_S |
| 10101 | 4240060U, // URSHRd |
| 10102 | 1615005340U, // URSHRv16i8_shift |
| 10103 | 1615018088U, // URSHRv2i32_shift |
| 10104 | 1615009171U, // URSHRv2i64_shift |
| 10105 | 1615011405U, // URSHRv4i16_shift |
| 10106 | 1615020198U, // URSHRv4i32_shift |
| 10107 | 1615013382U, // URSHRv8i16_shift |
| 10108 | 1615006304U, // URSHRv8i8_shift |
| 10109 | 541235413U, // URSQRTE_ZPmZ_S |
| 10110 | 1615017461U, // URSQRTEv2i32 |
| 10111 | 1615019467U, // URSQRTEv4i32 |
| 10112 | 541131362U, // URSRA_ZZI_B |
| 10113 | 2151776866U, // URSRA_ZZI_D |
| 10114 | 84017762U, // URSRA_ZZI_H |
| 10115 | 2688713314U, // URSRA_ZZI_S |
| 10116 | 1615430242U, // URSRAd |
| 10117 | 1615070352U, // URSRAv16i8_shift |
| 10118 | 1615082716U, // URSRAv2i32_shift |
| 10119 | 1615073936U, // URSRAv2i64_shift |
| 10120 | 1615076045U, // URSRAv4i16_shift |
| 10121 | 1615084679U, // URSRAv4i32_shift |
| 10122 | 1615077963U, // URSRAv8i16_shift |
| 10123 | 1615071281U, // URSRAv8i8_shift |
| 10124 | 3288811100U, // USDOT_VG2_M2Z2Z_BToS |
| 10125 | 3288811100U, // USDOT_VG2_M2ZZI_BToS |
| 10126 | 3288811100U, // USDOT_VG2_M2ZZ_BToS |
| 10127 | 3825682012U, // USDOT_VG4_M4Z4Z_BToS |
| 10128 | 3825682012U, // USDOT_VG4_M4ZZI_BToS |
| 10129 | 3825682012U, // USDOT_VG4_M4ZZ_BToS |
| 10130 | 541247068U, // USDOT_ZZZ |
| 10131 | 541247068U, // USDOT_ZZZI |
| 10132 | 1615087196U, // USDOTlanev16i8 |
| 10133 | 1615087196U, // USDOTlanev8i8 |
| 10134 | 20939U, // USDOTv16i8 |
| 10135 | 20939U, // USDOTv8i8 |
| 10136 | 541166870U, // USHLLB_ZZI_D |
| 10137 | 88214806U, // USHLLB_ZZI_H |
| 10138 | 3762457878U, // USHLLB_ZZI_S |
| 10139 | 541181265U, // USHLLT_ZZI_D |
| 10140 | 88229201U, // USHLLT_ZZI_H |
| 10141 | 3762472273U, // USHLLT_ZZI_S |
| 10142 | 1615012060U, // USHLLv16i8_shift |
| 10143 | 1615008880U, // USHLLv2i32_shift |
| 10144 | 1615019837U, // USHLLv4i16_shift |
| 10145 | 1615008219U, // USHLLv4i32_shift |
| 10146 | 1615018761U, // USHLLv8i16_shift |
| 10147 | 1615013031U, // USHLLv8i8_shift |
| 10148 | 1615005198U, // USHLv16i8 |
| 10149 | 4238595U, // USHLv1i64 |
| 10150 | 1615017688U, // USHLv2i32 |
| 10151 | 1615008861U, // USHLv2i64 |
| 10152 | 1615010994U, // USHLv4i16 |
| 10153 | 1615019818U, // USHLv4i32 |
| 10154 | 1615013012U, // USHLv8i16 |
| 10155 | 1615006052U, // USHLv8i8 |
| 10156 | 4240073U, // USHRd |
| 10157 | 1615005361U, // USHRv16i8_shift |
| 10158 | 1615018107U, // USHRv2i32_shift |
| 10159 | 1615009190U, // USHRv2i64_shift |
| 10160 | 1615011424U, // USHRv4i16_shift |
| 10161 | 1615020217U, // USHRv4i32_shift |
| 10162 | 1615013401U, // USHRv8i16_shift |
| 10163 | 1615006323U, // USHRv8i8_shift |
| 10164 | 3376885009U, // USMLALL_MZZI_BtoS |
| 10165 | 3376885009U, // USMLALL_MZZ_BtoS |
| 10166 | 3376885009U, // USMLALL_VG2_M2Z2Z_BtoS |
| 10167 | 3376885009U, // USMLALL_VG2_M2ZZI_BtoS |
| 10168 | 3913755921U, // USMLALL_VG2_M2ZZ_BtoS |
| 10169 | 3913755921U, // USMLALL_VG4_M4Z4Z_BtoS |
| 10170 | 3913755921U, // USMLALL_VG4_M4ZZI_BtoS |
| 10171 | 155659537U, // USMLALL_VG4_M4ZZ_BtoS |
| 10172 | 20729U, // USMMLA |
| 10173 | 541229418U, // USMMLA_ZZZ |
| 10174 | 96698792U, // USMOPA_MPPZZ_D |
| 10175 | 159613352U, // USMOPA_MPPZZ_S |
| 10176 | 96715736U, // USMOPS_MPPZZ_D |
| 10177 | 159630296U, // USMOPS_MPPZZ_S |
| 10178 | 2151749618U, // USQADD_ZPmZ_B |
| 10179 | 2151782386U, // USQADD_ZPmZ_D |
| 10180 | 2713851890U, // USQADD_ZPmZ_H |
| 10181 | 2151847922U, // USQADD_ZPmZ_S |
| 10182 | 1615070525U, // USQADDv16i8 |
| 10183 | 1615435762U, // USQADDv1i16 |
| 10184 | 1615435762U, // USQADDv1i32 |
| 10185 | 1615435762U, // USQADDv1i64 |
| 10186 | 1615435762U, // USQADDv1i8 |
| 10187 | 1615082900U, // USQADDv2i32 |
| 10188 | 1615074032U, // USQADDv2i64 |
| 10189 | 1615076229U, // USQADDv4i16 |
| 10190 | 1615084897U, // USQADDv4i32 |
| 10191 | 1615078147U, // USQADDv8i16 |
| 10192 | 1615071417U, // USQADDv8i8 |
| 10193 | 541131375U, // USRA_ZZI_B |
| 10194 | 2151776879U, // USRA_ZZI_D |
| 10195 | 84017775U, // USRA_ZZI_H |
| 10196 | 2688713327U, // USRA_ZZI_S |
| 10197 | 1615430255U, // USRAd |
| 10198 | 1615070373U, // USRAv16i8_shift |
| 10199 | 1615082735U, // USRAv2i32_shift |
| 10200 | 1615073955U, // USRAv2i64_shift |
| 10201 | 1615076064U, // USRAv4i16_shift |
| 10202 | 1615084698U, // USRAv4i32_shift |
| 10203 | 1615077982U, // USRAv8i16_shift |
| 10204 | 1615071300U, // USRAv8i8_shift |
| 10205 | 541166799U, // USUBLB_ZZZ_D |
| 10206 | 88214735U, // USUBLB_ZZZ_H |
| 10207 | 3762457807U, // USUBLB_ZZZ_S |
| 10208 | 541181189U, // USUBLT_ZZZ_D |
| 10209 | 88229125U, // USUBLT_ZZZ_H |
| 10210 | 3762472197U, // USUBLT_ZZZ_S |
| 10211 | 1615011994U, // USUBLv16i8_v8i16 |
| 10212 | 1615008740U, // USUBLv2i32_v2i64 |
| 10213 | 1615019697U, // USUBLv4i16_v4i32 |
| 10214 | 1615008153U, // USUBLv4i32_v2i64 |
| 10215 | 1615018695U, // USUBLv8i16_v4i32 |
| 10216 | 1615012891U, // USUBLv8i8_v8i16 |
| 10217 | 541167571U, // USUBWB_ZZZ_D |
| 10218 | 71438291U, // USUBWB_ZZZ_H |
| 10219 | 541233107U, // USUBWB_ZZZ_S |
| 10220 | 541181711U, // USUBWT_ZZZ_D |
| 10221 | 71452431U, // USUBWT_ZZZ_H |
| 10222 | 541247247U, // USUBWT_ZZZ_S |
| 10223 | 1615012337U, // USUBWv16i8_v8i16 |
| 10224 | 1615009458U, // USUBWv2i32_v2i64 |
| 10225 | 1615020616U, // USUBWv4i16_v4i32 |
| 10226 | 1615008338U, // USUBWv4i32_v2i64 |
| 10227 | 1615019015U, // USUBWv8i16_v4i32 |
| 10228 | 1615013800U, // USUBWv8i8_v8i16 |
| 10229 | 3825682034U, // USVDOT_VG4_M4ZZI_BToS |
| 10230 | 541174539U, // UUNPKHI_ZZ_D |
| 10231 | 3309447947U, // UUNPKHI_ZZ_H |
| 10232 | 3762465547U, // UUNPKHI_ZZ_S |
| 10233 | 541175796U, // UUNPKLO_ZZ_D |
| 10234 | 3309449204U, // UUNPKLO_ZZ_H |
| 10235 | 3762466804U, // UUNPKLO_ZZ_S |
| 10236 | 3242535749U, // UUNPK_VG2_2ZZ_D |
| 10237 | 3309677381U, // UUNPK_VG2_2ZZ_H |
| 10238 | 3292932933U, // UUNPK_VG2_2ZZ_S |
| 10239 | 3284478789U, // UUNPK_VG4_4Z2Z_D |
| 10240 | 3271928645U, // UUNPK_VG4_4Z2Z_H |
| 10241 | 3280350021U, // UUNPK_VG4_4Z2Z_S |
| 10242 | 3288811131U, // UVDOT_VG2_M2ZZI_HtoS |
| 10243 | 3825682043U, // UVDOT_VG4_M4ZZI_BtoS |
| 10244 | 3825649275U, // UVDOT_VG4_M4ZZI_HtoD |
| 10245 | 541167501U, // UXTB_ZPmZ_D |
| 10246 | 1082265485U, // UXTB_ZPmZ_H |
| 10247 | 541233037U, // UXTB_ZPmZ_S |
| 10248 | 541174475U, // UXTH_ZPmZ_D |
| 10249 | 541240011U, // UXTH_ZPmZ_S |
| 10250 | 541182313U, // UXTW_ZPmZ_D |
| 10251 | 4259880U, // UZP1_PPP_B |
| 10252 | 541163560U, // UZP1_PPP_D |
| 10253 | 71434280U, // UZP1_PPP_H |
| 10254 | 541229096U, // UZP1_PPP_S |
| 10255 | 4259880U, // UZP1_ZZZ_B |
| 10256 | 541163560U, // UZP1_ZZZ_D |
| 10257 | 71434280U, // UZP1_ZZZ_H |
| 10258 | 114196520U, // UZP1_ZZZ_Q |
| 10259 | 541229096U, // UZP1_ZZZ_S |
| 10260 | 1615004547U, // UZP1v16i8 |
| 10261 | 1615017087U, // UZP1v2i32 |
| 10262 | 1615008040U, // UZP1v2i64 |
| 10263 | 1615010406U, // UZP1v4i16 |
| 10264 | 1615018554U, // UZP1v4i32 |
| 10265 | 1615011920U, // UZP1v8i16 |
| 10266 | 1615005643U, // UZP1v8i8 |
| 10267 | 4259998U, // UZP2_PPP_B |
| 10268 | 541163678U, // UZP2_PPP_D |
| 10269 | 71434398U, // UZP2_PPP_H |
| 10270 | 541229214U, // UZP2_PPP_S |
| 10271 | 4259998U, // UZP2_ZZZ_B |
| 10272 | 541163678U, // UZP2_ZZZ_D |
| 10273 | 71434398U, // UZP2_ZZZ_H |
| 10274 | 114196638U, // UZP2_ZZZ_Q |
| 10275 | 541229214U, // UZP2_ZZZ_S |
| 10276 | 1615004734U, // UZP2v16i8 |
| 10277 | 1615017114U, // UZP2v2i32 |
| 10278 | 1615008318U, // UZP2v2i64 |
| 10279 | 1615010443U, // UZP2v4i16 |
| 10280 | 1615018995U, // UZP2v4i32 |
| 10281 | 1615012317U, // UZP2v8i16 |
| 10282 | 1615005680U, // UZP2v8i8 |
| 10283 | 4259893U, // UZPQ1_ZZZ_B |
| 10284 | 541163573U, // UZPQ1_ZZZ_D |
| 10285 | 71434293U, // UZPQ1_ZZZ_H |
| 10286 | 541229109U, // UZPQ1_ZZZ_S |
| 10287 | 4260011U, // UZPQ2_ZZZ_B |
| 10288 | 541163691U, // UZPQ2_ZZZ_D |
| 10289 | 71434411U, // UZPQ2_ZZZ_H |
| 10290 | 541229227U, // UZPQ2_ZZZ_S |
| 10291 | 88387987U, // UZP_VG2_2ZZZ_B |
| 10292 | 314913171U, // UZP_VG2_2ZZZ_D |
| 10293 | 71676307U, // UZP_VG2_2ZZZ_H |
| 10294 | 114241939U, // UZP_VG2_2ZZZ_Q |
| 10295 | 21377427U, // UZP_VG2_2ZZZ_S |
| 10296 | 3271864723U, // UZP_VG4_4Z4Z_B |
| 10297 | 3276091795U, // UZP_VG4_4Z4Z_D |
| 10298 | 3280318867U, // UZP_VG4_4Z4Z_H |
| 10299 | 332345747U, // UZP_VG4_4Z4Z_Q |
| 10300 | 3284545939U, // UZP_VG4_4Z4Z_S |
| 10301 | 50294U, // WFET |
| 10302 | 50372U, // WFIT |
| 10303 | 109353042U, // WHILEGE_2PXX_B |
| 10304 | 109385810U, // WHILEGE_2PXX_D |
| 10305 | 109418578U, // WHILEGE_2PXX_H |
| 10306 | 109451346U, // WHILEGE_2PXX_S |
| 10307 | 6494290U, // WHILEGE_CXX_B |
| 10308 | 6527058U, // WHILEGE_CXX_D |
| 10309 | 6559826U, // WHILEGE_CXX_H |
| 10310 | 6592594U, // WHILEGE_CXX_S |
| 10311 | 4266066U, // WHILEGE_PWW_B |
| 10312 | 4298834U, // WHILEGE_PWW_D |
| 10313 | 109189202U, // WHILEGE_PWW_H |
| 10314 | 4364370U, // WHILEGE_PWW_S |
| 10315 | 4266066U, // WHILEGE_PXX_B |
| 10316 | 4298834U, // WHILEGE_PXX_D |
| 10317 | 109189202U, // WHILEGE_PXX_H |
| 10318 | 4364370U, // WHILEGE_PXX_S |
| 10319 | 109364384U, // WHILEGT_2PXX_B |
| 10320 | 109397152U, // WHILEGT_2PXX_D |
| 10321 | 109429920U, // WHILEGT_2PXX_H |
| 10322 | 109462688U, // WHILEGT_2PXX_S |
| 10323 | 6505632U, // WHILEGT_CXX_B |
| 10324 | 6538400U, // WHILEGT_CXX_D |
| 10325 | 6571168U, // WHILEGT_CXX_H |
| 10326 | 6603936U, // WHILEGT_CXX_S |
| 10327 | 4277408U, // WHILEGT_PWW_B |
| 10328 | 4310176U, // WHILEGT_PWW_D |
| 10329 | 109200544U, // WHILEGT_PWW_H |
| 10330 | 4375712U, // WHILEGT_PWW_S |
| 10331 | 4277408U, // WHILEGT_PXX_B |
| 10332 | 4310176U, // WHILEGT_PXX_D |
| 10333 | 109200544U, // WHILEGT_PXX_H |
| 10334 | 4375712U, // WHILEGT_PXX_S |
| 10335 | 109357808U, // WHILEHI_2PXX_B |
| 10336 | 109390576U, // WHILEHI_2PXX_D |
| 10337 | 109423344U, // WHILEHI_2PXX_H |
| 10338 | 109456112U, // WHILEHI_2PXX_S |
| 10339 | 6499056U, // WHILEHI_CXX_B |
| 10340 | 6531824U, // WHILEHI_CXX_D |
| 10341 | 6564592U, // WHILEHI_CXX_H |
| 10342 | 6597360U, // WHILEHI_CXX_S |
| 10343 | 4270832U, // WHILEHI_PWW_B |
| 10344 | 4303600U, // WHILEHI_PWW_D |
| 10345 | 109193968U, // WHILEHI_PWW_H |
| 10346 | 4369136U, // WHILEHI_PWW_S |
| 10347 | 4270832U, // WHILEHI_PXX_B |
| 10348 | 4303600U, // WHILEHI_PXX_D |
| 10349 | 109193968U, // WHILEHI_PXX_H |
| 10350 | 4369136U, // WHILEHI_PXX_S |
| 10351 | 109364068U, // WHILEHS_2PXX_B |
| 10352 | 109396836U, // WHILEHS_2PXX_D |
| 10353 | 109429604U, // WHILEHS_2PXX_H |
| 10354 | 109462372U, // WHILEHS_2PXX_S |
| 10355 | 6505316U, // WHILEHS_CXX_B |
| 10356 | 6538084U, // WHILEHS_CXX_D |
| 10357 | 6570852U, // WHILEHS_CXX_H |
| 10358 | 6603620U, // WHILEHS_CXX_S |
| 10359 | 4277092U, // WHILEHS_PWW_B |
| 10360 | 4309860U, // WHILEHS_PWW_D |
| 10361 | 109200228U, // WHILEHS_PWW_H |
| 10362 | 4375396U, // WHILEHS_PWW_S |
| 10363 | 4277092U, // WHILEHS_PXX_B |
| 10364 | 4309860U, // WHILEHS_PXX_D |
| 10365 | 109200228U, // WHILEHS_PXX_H |
| 10366 | 4375396U, // WHILEHS_PXX_S |
| 10367 | 109353073U, // WHILELE_2PXX_B |
| 10368 | 109385841U, // WHILELE_2PXX_D |
| 10369 | 109418609U, // WHILELE_2PXX_H |
| 10370 | 109451377U, // WHILELE_2PXX_S |
| 10371 | 6494321U, // WHILELE_CXX_B |
| 10372 | 6527089U, // WHILELE_CXX_D |
| 10373 | 6559857U, // WHILELE_CXX_H |
| 10374 | 6592625U, // WHILELE_CXX_S |
| 10375 | 4266097U, // WHILELE_PWW_B |
| 10376 | 4298865U, // WHILELE_PWW_D |
| 10377 | 109189233U, // WHILELE_PWW_H |
| 10378 | 4364401U, // WHILELE_PWW_S |
| 10379 | 4266097U, // WHILELE_PXX_B |
| 10380 | 4298865U, // WHILELE_PXX_D |
| 10381 | 109189233U, // WHILELE_PXX_H |
| 10382 | 4364401U, // WHILELE_PXX_S |
| 10383 | 109359065U, // WHILELO_2PXX_B |
| 10384 | 109391833U, // WHILELO_2PXX_D |
| 10385 | 109424601U, // WHILELO_2PXX_H |
| 10386 | 109457369U, // WHILELO_2PXX_S |
| 10387 | 6500313U, // WHILELO_CXX_B |
| 10388 | 6533081U, // WHILELO_CXX_D |
| 10389 | 6565849U, // WHILELO_CXX_H |
| 10390 | 6598617U, // WHILELO_CXX_S |
| 10391 | 4272089U, // WHILELO_PWW_B |
| 10392 | 4304857U, // WHILELO_PWW_D |
| 10393 | 109195225U, // WHILELO_PWW_H |
| 10394 | 4370393U, // WHILELO_PWW_S |
| 10395 | 4272089U, // WHILELO_PXX_B |
| 10396 | 4304857U, // WHILELO_PXX_D |
| 10397 | 109195225U, // WHILELO_PXX_H |
| 10398 | 4370393U, // WHILELO_PXX_S |
| 10399 | 109364095U, // WHILELS_2PXX_B |
| 10400 | 109396863U, // WHILELS_2PXX_D |
| 10401 | 109429631U, // WHILELS_2PXX_H |
| 10402 | 109462399U, // WHILELS_2PXX_S |
| 10403 | 6505343U, // WHILELS_CXX_B |
| 10404 | 6538111U, // WHILELS_CXX_D |
| 10405 | 6570879U, // WHILELS_CXX_H |
| 10406 | 6603647U, // WHILELS_CXX_S |
| 10407 | 4277119U, // WHILELS_PWW_B |
| 10408 | 4309887U, // WHILELS_PWW_D |
| 10409 | 109200255U, // WHILELS_PWW_H |
| 10410 | 4375423U, // WHILELS_PWW_S |
| 10411 | 4277119U, // WHILELS_PXX_B |
| 10412 | 4309887U, // WHILELS_PXX_D |
| 10413 | 109200255U, // WHILELS_PXX_H |
| 10414 | 4375423U, // WHILELS_PXX_S |
| 10415 | 109364539U, // WHILELT_2PXX_B |
| 10416 | 109397307U, // WHILELT_2PXX_D |
| 10417 | 109430075U, // WHILELT_2PXX_H |
| 10418 | 109462843U, // WHILELT_2PXX_S |
| 10419 | 6505787U, // WHILELT_CXX_B |
| 10420 | 6538555U, // WHILELT_CXX_D |
| 10421 | 6571323U, // WHILELT_CXX_H |
| 10422 | 6604091U, // WHILELT_CXX_S |
| 10423 | 4277563U, // WHILELT_PWW_B |
| 10424 | 4310331U, // WHILELT_PWW_D |
| 10425 | 109200699U, // WHILELT_PWW_H |
| 10426 | 4375867U, // WHILELT_PWW_S |
| 10427 | 4277563U, // WHILELT_PXX_B |
| 10428 | 4310331U, // WHILELT_PXX_D |
| 10429 | 109200699U, // WHILELT_PXX_H |
| 10430 | 4375867U, // WHILELT_PXX_S |
| 10431 | 4278530U, // WHILERW_PXX_B |
| 10432 | 4311298U, // WHILERW_PXX_D |
| 10433 | 109201666U, // WHILERW_PXX_H |
| 10434 | 4376834U, // WHILERW_PXX_S |
| 10435 | 4273090U, // WHILEWR_PXX_B |
| 10436 | 4305858U, // WHILEWR_PXX_D |
| 10437 | 109196226U, // WHILEWR_PXX_H |
| 10438 | 4371394U, // WHILEWR_PXX_S |
| 10439 | 78494U, // WRFFR |
| 10440 | 20834U, // XAFLAG |
| 10441 | 1615009153U, // XAR |
| 10442 | 4272689U, // XAR_ZZZI_B |
| 10443 | 541176369U, // XAR_ZZZI_D |
| 10444 | 71447089U, // XAR_ZZZI_H |
| 10445 | 541241905U, // XAR_ZZZI_S |
| 10446 | 38785U, // XPACD |
| 10447 | 43753U, // XPACI |
| 10448 | 19388U, // XPACLRI |
| 10449 | 1615070196U, // XTNv16i8 |
| 10450 | 1615017857U, // XTNv2i32 |
| 10451 | 1615011174U, // XTNv4i16 |
| 10452 | 1615084463U, // XTNv4i32 |
| 10453 | 1615077785U, // XTNv8i16 |
| 10454 | 1615006174U, // XTNv8i8 |
| 10455 | 2535428U, // ZERO_M |
| 10456 | 629583876U, // ZERO_MXI_2Z |
| 10457 | 692498436U, // ZERO_MXI_4Z |
| 10458 | 3313938436U, // ZERO_MXI_VG2_2Z |
| 10459 | 3376852996U, // ZERO_MXI_VG2_4Z |
| 10460 | 3288772612U, // ZERO_MXI_VG2_Z |
| 10461 | 3850809348U, // ZERO_MXI_VG4_2Z |
| 10462 | 3913723908U, // ZERO_MXI_VG4_4Z |
| 10463 | 3825643524U, // ZERO_MXI_VG4_Z |
| 10464 | 335596156U, // ZERO_T |
| 10465 | 4259874U, // ZIP1_PPP_B |
| 10466 | 541163554U, // ZIP1_PPP_D |
| 10467 | 71434274U, // ZIP1_PPP_H |
| 10468 | 541229090U, // ZIP1_PPP_S |
| 10469 | 4259874U, // ZIP1_ZZZ_B |
| 10470 | 541163554U, // ZIP1_ZZZ_D |
| 10471 | 71434274U, // ZIP1_ZZZ_H |
| 10472 | 114196514U, // ZIP1_ZZZ_Q |
| 10473 | 541229090U, // ZIP1_ZZZ_S |
| 10474 | 1615004537U, // ZIP1v16i8 |
| 10475 | 1615017078U, // ZIP1v2i32 |
| 10476 | 1615008031U, // ZIP1v2i64 |
| 10477 | 1615010397U, // ZIP1v4i16 |
| 10478 | 1615018545U, // ZIP1v4i32 |
| 10479 | 1615011911U, // ZIP1v8i16 |
| 10480 | 1615005634U, // ZIP1v8i8 |
| 10481 | 4259992U, // ZIP2_PPP_B |
| 10482 | 541163672U, // ZIP2_PPP_D |
| 10483 | 71434392U, // ZIP2_PPP_H |
| 10484 | 541229208U, // ZIP2_PPP_S |
| 10485 | 4259992U, // ZIP2_ZZZ_B |
| 10486 | 541163672U, // ZIP2_ZZZ_D |
| 10487 | 71434392U, // ZIP2_ZZZ_H |
| 10488 | 114196632U, // ZIP2_ZZZ_Q |
| 10489 | 541229208U, // ZIP2_ZZZ_S |
| 10490 | 1615004724U, // ZIP2v16i8 |
| 10491 | 1615017105U, // ZIP2v2i32 |
| 10492 | 1615008309U, // ZIP2v2i64 |
| 10493 | 1615010434U, // ZIP2v4i16 |
| 10494 | 1615018986U, // ZIP2v4i32 |
| 10495 | 1615012308U, // ZIP2v8i16 |
| 10496 | 1615005671U, // ZIP2v8i8 |
| 10497 | 4259886U, // ZIPQ1_ZZZ_B |
| 10498 | 541163566U, // ZIPQ1_ZZZ_D |
| 10499 | 71434286U, // ZIPQ1_ZZZ_H |
| 10500 | 541229102U, // ZIPQ1_ZZZ_S |
| 10501 | 4260004U, // ZIPQ2_ZZZ_B |
| 10502 | 541163684U, // ZIPQ2_ZZZ_D |
| 10503 | 71434404U, // ZIPQ2_ZZZ_H |
| 10504 | 541229220U, // ZIPQ2_ZZZ_S |
| 10505 | 88387663U, // ZIP_VG2_2ZZZ_B |
| 10506 | 314912847U, // ZIP_VG2_2ZZZ_D |
| 10507 | 71675983U, // ZIP_VG2_2ZZZ_H |
| 10508 | 114241615U, // ZIP_VG2_2ZZZ_Q |
| 10509 | 21377103U, // ZIP_VG2_2ZZZ_S |
| 10510 | 3271864399U, // ZIP_VG4_4Z4Z_B |
| 10511 | 3276091471U, // ZIP_VG4_4Z4Z_D |
| 10512 | 3280318543U, // ZIP_VG4_4Z4Z_H |
| 10513 | 332345423U, // ZIP_VG4_4Z4Z_Q |
| 10514 | 3284545615U, // ZIP_VG4_4Z4Z_S |
| 10515 | }; |
| 10516 | |
| 10517 | static const uint32_t OpInfo1[] = { |
| 10518 | 0U, // PHI |
| 10519 | 0U, // INLINEASM |
| 10520 | 0U, // INLINEASM_BR |
| 10521 | 0U, // CFI_INSTRUCTION |
| 10522 | 0U, // EH_LABEL |
| 10523 | 0U, // GC_LABEL |
| 10524 | 0U, // ANNOTATION_LABEL |
| 10525 | 0U, // KILL |
| 10526 | 0U, // EXTRACT_SUBREG |
| 10527 | 0U, // INSERT_SUBREG |
| 10528 | 0U, // IMPLICIT_DEF |
| 10529 | 0U, // SUBREG_TO_REG |
| 10530 | 0U, // COPY_TO_REGCLASS |
| 10531 | 0U, // DBG_VALUE |
| 10532 | 0U, // DBG_VALUE_LIST |
| 10533 | 0U, // DBG_INSTR_REF |
| 10534 | 0U, // DBG_PHI |
| 10535 | 0U, // DBG_LABEL |
| 10536 | 0U, // REG_SEQUENCE |
| 10537 | 0U, // COPY |
| 10538 | 0U, // BUNDLE |
| 10539 | 0U, // LIFETIME_START |
| 10540 | 0U, // LIFETIME_END |
| 10541 | 0U, // PSEUDO_PROBE |
| 10542 | 0U, // ARITH_FENCE |
| 10543 | 0U, // STACKMAP |
| 10544 | 0U, // FENTRY_CALL |
| 10545 | 0U, // PATCHPOINT |
| 10546 | 0U, // LOAD_STACK_GUARD |
| 10547 | 0U, // PREALLOCATED_SETUP |
| 10548 | 0U, // PREALLOCATED_ARG |
| 10549 | 0U, // STATEPOINT |
| 10550 | 0U, // LOCAL_ESCAPE |
| 10551 | 0U, // FAULTING_OP |
| 10552 | 0U, // PATCHABLE_OP |
| 10553 | 0U, // PATCHABLE_FUNCTION_ENTER |
| 10554 | 0U, // PATCHABLE_RET |
| 10555 | 0U, // PATCHABLE_FUNCTION_EXIT |
| 10556 | 0U, // PATCHABLE_TAIL_CALL |
| 10557 | 0U, // PATCHABLE_EVENT_CALL |
| 10558 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 10559 | 0U, // ICALL_BRANCH_FUNNEL |
| 10560 | 0U, // MEMBARRIER |
| 10561 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 10562 | 0U, // CONVERGENCECTRL_ENTRY |
| 10563 | 0U, // CONVERGENCECTRL_ANCHOR |
| 10564 | 0U, // CONVERGENCECTRL_LOOP |
| 10565 | 0U, // CONVERGENCECTRL_GLUE |
| 10566 | 0U, // G_ASSERT_SEXT |
| 10567 | 0U, // G_ASSERT_ZEXT |
| 10568 | 0U, // G_ASSERT_ALIGN |
| 10569 | 0U, // G_ADD |
| 10570 | 0U, // G_SUB |
| 10571 | 0U, // G_MUL |
| 10572 | 0U, // G_SDIV |
| 10573 | 0U, // G_UDIV |
| 10574 | 0U, // G_SREM |
| 10575 | 0U, // G_UREM |
| 10576 | 0U, // G_SDIVREM |
| 10577 | 0U, // G_UDIVREM |
| 10578 | 0U, // G_AND |
| 10579 | 0U, // G_OR |
| 10580 | 0U, // G_XOR |
| 10581 | 0U, // G_IMPLICIT_DEF |
| 10582 | 0U, // G_PHI |
| 10583 | 0U, // G_FRAME_INDEX |
| 10584 | 0U, // G_GLOBAL_VALUE |
| 10585 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 10586 | 0U, // G_CONSTANT_POOL |
| 10587 | 0U, // G_EXTRACT |
| 10588 | 0U, // G_UNMERGE_VALUES |
| 10589 | 0U, // G_INSERT |
| 10590 | 0U, // G_MERGE_VALUES |
| 10591 | 0U, // G_BUILD_VECTOR |
| 10592 | 0U, // G_BUILD_VECTOR_TRUNC |
| 10593 | 0U, // G_CONCAT_VECTORS |
| 10594 | 0U, // G_PTRTOINT |
| 10595 | 0U, // G_INTTOPTR |
| 10596 | 0U, // G_BITCAST |
| 10597 | 0U, // G_FREEZE |
| 10598 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 10599 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 10600 | 0U, // G_INTRINSIC_TRUNC |
| 10601 | 0U, // G_INTRINSIC_ROUND |
| 10602 | 0U, // G_INTRINSIC_LRINT |
| 10603 | 0U, // G_INTRINSIC_LLRINT |
| 10604 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 10605 | 0U, // G_READCYCLECOUNTER |
| 10606 | 0U, // G_READSTEADYCOUNTER |
| 10607 | 0U, // G_LOAD |
| 10608 | 0U, // G_SEXTLOAD |
| 10609 | 0U, // G_ZEXTLOAD |
| 10610 | 0U, // G_INDEXED_LOAD |
| 10611 | 0U, // G_INDEXED_SEXTLOAD |
| 10612 | 0U, // G_INDEXED_ZEXTLOAD |
| 10613 | 0U, // G_STORE |
| 10614 | 0U, // G_INDEXED_STORE |
| 10615 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 10616 | 0U, // G_ATOMIC_CMPXCHG |
| 10617 | 0U, // G_ATOMICRMW_XCHG |
| 10618 | 0U, // G_ATOMICRMW_ADD |
| 10619 | 0U, // G_ATOMICRMW_SUB |
| 10620 | 0U, // G_ATOMICRMW_AND |
| 10621 | 0U, // G_ATOMICRMW_NAND |
| 10622 | 0U, // G_ATOMICRMW_OR |
| 10623 | 0U, // G_ATOMICRMW_XOR |
| 10624 | 0U, // G_ATOMICRMW_MAX |
| 10625 | 0U, // G_ATOMICRMW_MIN |
| 10626 | 0U, // G_ATOMICRMW_UMAX |
| 10627 | 0U, // G_ATOMICRMW_UMIN |
| 10628 | 0U, // G_ATOMICRMW_FADD |
| 10629 | 0U, // G_ATOMICRMW_FSUB |
| 10630 | 0U, // G_ATOMICRMW_FMAX |
| 10631 | 0U, // G_ATOMICRMW_FMIN |
| 10632 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 10633 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 10634 | 0U, // G_FENCE |
| 10635 | 0U, // G_PREFETCH |
| 10636 | 0U, // G_BRCOND |
| 10637 | 0U, // G_BRINDIRECT |
| 10638 | 0U, // G_INVOKE_REGION_START |
| 10639 | 0U, // G_INTRINSIC |
| 10640 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 10641 | 0U, // G_INTRINSIC_CONVERGENT |
| 10642 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 10643 | 0U, // G_ANYEXT |
| 10644 | 0U, // G_TRUNC |
| 10645 | 0U, // G_CONSTANT |
| 10646 | 0U, // G_FCONSTANT |
| 10647 | 0U, // G_VASTART |
| 10648 | 0U, // G_VAARG |
| 10649 | 0U, // G_SEXT |
| 10650 | 0U, // G_SEXT_INREG |
| 10651 | 0U, // G_ZEXT |
| 10652 | 0U, // G_SHL |
| 10653 | 0U, // G_LSHR |
| 10654 | 0U, // G_ASHR |
| 10655 | 0U, // G_FSHL |
| 10656 | 0U, // G_FSHR |
| 10657 | 0U, // G_ROTR |
| 10658 | 0U, // G_ROTL |
| 10659 | 0U, // G_ICMP |
| 10660 | 0U, // G_FCMP |
| 10661 | 0U, // G_SCMP |
| 10662 | 0U, // G_UCMP |
| 10663 | 0U, // G_SELECT |
| 10664 | 0U, // G_UADDO |
| 10665 | 0U, // G_UADDE |
| 10666 | 0U, // G_USUBO |
| 10667 | 0U, // G_USUBE |
| 10668 | 0U, // G_SADDO |
| 10669 | 0U, // G_SADDE |
| 10670 | 0U, // G_SSUBO |
| 10671 | 0U, // G_SSUBE |
| 10672 | 0U, // G_UMULO |
| 10673 | 0U, // G_SMULO |
| 10674 | 0U, // G_UMULH |
| 10675 | 0U, // G_SMULH |
| 10676 | 0U, // G_UADDSAT |
| 10677 | 0U, // G_SADDSAT |
| 10678 | 0U, // G_USUBSAT |
| 10679 | 0U, // G_SSUBSAT |
| 10680 | 0U, // G_USHLSAT |
| 10681 | 0U, // G_SSHLSAT |
| 10682 | 0U, // G_SMULFIX |
| 10683 | 0U, // G_UMULFIX |
| 10684 | 0U, // G_SMULFIXSAT |
| 10685 | 0U, // G_UMULFIXSAT |
| 10686 | 0U, // G_SDIVFIX |
| 10687 | 0U, // G_UDIVFIX |
| 10688 | 0U, // G_SDIVFIXSAT |
| 10689 | 0U, // G_UDIVFIXSAT |
| 10690 | 0U, // G_FADD |
| 10691 | 0U, // G_FSUB |
| 10692 | 0U, // G_FMUL |
| 10693 | 0U, // G_FMA |
| 10694 | 0U, // G_FMAD |
| 10695 | 0U, // G_FDIV |
| 10696 | 0U, // G_FREM |
| 10697 | 0U, // G_FPOW |
| 10698 | 0U, // G_FPOWI |
| 10699 | 0U, // G_FEXP |
| 10700 | 0U, // G_FEXP2 |
| 10701 | 0U, // G_FEXP10 |
| 10702 | 0U, // G_FLOG |
| 10703 | 0U, // G_FLOG2 |
| 10704 | 0U, // G_FLOG10 |
| 10705 | 0U, // G_FLDEXP |
| 10706 | 0U, // G_FFREXP |
| 10707 | 0U, // G_FNEG |
| 10708 | 0U, // G_FPEXT |
| 10709 | 0U, // G_FPTRUNC |
| 10710 | 0U, // G_FPTOSI |
| 10711 | 0U, // G_FPTOUI |
| 10712 | 0U, // G_SITOFP |
| 10713 | 0U, // G_UITOFP |
| 10714 | 0U, // G_FABS |
| 10715 | 0U, // G_FCOPYSIGN |
| 10716 | 0U, // G_IS_FPCLASS |
| 10717 | 0U, // G_FCANONICALIZE |
| 10718 | 0U, // G_FMINNUM |
| 10719 | 0U, // G_FMAXNUM |
| 10720 | 0U, // G_FMINNUM_IEEE |
| 10721 | 0U, // G_FMAXNUM_IEEE |
| 10722 | 0U, // G_FMINIMUM |
| 10723 | 0U, // G_FMAXIMUM |
| 10724 | 0U, // G_GET_FPENV |
| 10725 | 0U, // G_SET_FPENV |
| 10726 | 0U, // G_RESET_FPENV |
| 10727 | 0U, // G_GET_FPMODE |
| 10728 | 0U, // G_SET_FPMODE |
| 10729 | 0U, // G_RESET_FPMODE |
| 10730 | 0U, // G_PTR_ADD |
| 10731 | 0U, // G_PTRMASK |
| 10732 | 0U, // G_SMIN |
| 10733 | 0U, // G_SMAX |
| 10734 | 0U, // G_UMIN |
| 10735 | 0U, // G_UMAX |
| 10736 | 0U, // G_ABS |
| 10737 | 0U, // G_LROUND |
| 10738 | 0U, // G_LLROUND |
| 10739 | 0U, // G_BR |
| 10740 | 0U, // G_BRJT |
| 10741 | 0U, // G_VSCALE |
| 10742 | 0U, // G_INSERT_SUBVECTOR |
| 10743 | 0U, // G_EXTRACT_SUBVECTOR |
| 10744 | 0U, // G_INSERT_VECTOR_ELT |
| 10745 | 0U, // G_EXTRACT_VECTOR_ELT |
| 10746 | 0U, // G_SHUFFLE_VECTOR |
| 10747 | 0U, // G_SPLAT_VECTOR |
| 10748 | 0U, // G_VECTOR_COMPRESS |
| 10749 | 0U, // G_CTTZ |
| 10750 | 0U, // G_CTTZ_ZERO_UNDEF |
| 10751 | 0U, // G_CTLZ |
| 10752 | 0U, // G_CTLZ_ZERO_UNDEF |
| 10753 | 0U, // G_CTPOP |
| 10754 | 0U, // G_BSWAP |
| 10755 | 0U, // G_BITREVERSE |
| 10756 | 0U, // G_FCEIL |
| 10757 | 0U, // G_FCOS |
| 10758 | 0U, // G_FSIN |
| 10759 | 0U, // G_FTAN |
| 10760 | 0U, // G_FACOS |
| 10761 | 0U, // G_FASIN |
| 10762 | 0U, // G_FATAN |
| 10763 | 0U, // G_FCOSH |
| 10764 | 0U, // G_FSINH |
| 10765 | 0U, // G_FTANH |
| 10766 | 0U, // G_FSQRT |
| 10767 | 0U, // G_FFLOOR |
| 10768 | 0U, // G_FRINT |
| 10769 | 0U, // G_FNEARBYINT |
| 10770 | 0U, // G_ADDRSPACE_CAST |
| 10771 | 0U, // G_BLOCK_ADDR |
| 10772 | 0U, // G_JUMP_TABLE |
| 10773 | 0U, // G_DYN_STACKALLOC |
| 10774 | 0U, // G_STACKSAVE |
| 10775 | 0U, // G_STACKRESTORE |
| 10776 | 0U, // G_STRICT_FADD |
| 10777 | 0U, // G_STRICT_FSUB |
| 10778 | 0U, // G_STRICT_FMUL |
| 10779 | 0U, // G_STRICT_FDIV |
| 10780 | 0U, // G_STRICT_FREM |
| 10781 | 0U, // G_STRICT_FMA |
| 10782 | 0U, // G_STRICT_FSQRT |
| 10783 | 0U, // G_STRICT_FLDEXP |
| 10784 | 0U, // G_READ_REGISTER |
| 10785 | 0U, // G_WRITE_REGISTER |
| 10786 | 0U, // G_MEMCPY |
| 10787 | 0U, // G_MEMCPY_INLINE |
| 10788 | 0U, // G_MEMMOVE |
| 10789 | 0U, // G_MEMSET |
| 10790 | 0U, // G_BZERO |
| 10791 | 0U, // G_TRAP |
| 10792 | 0U, // G_DEBUGTRAP |
| 10793 | 0U, // G_UBSANTRAP |
| 10794 | 0U, // G_VECREDUCE_SEQ_FADD |
| 10795 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 10796 | 0U, // G_VECREDUCE_FADD |
| 10797 | 0U, // G_VECREDUCE_FMUL |
| 10798 | 0U, // G_VECREDUCE_FMAX |
| 10799 | 0U, // G_VECREDUCE_FMIN |
| 10800 | 0U, // G_VECREDUCE_FMAXIMUM |
| 10801 | 0U, // G_VECREDUCE_FMINIMUM |
| 10802 | 0U, // G_VECREDUCE_ADD |
| 10803 | 0U, // G_VECREDUCE_MUL |
| 10804 | 0U, // G_VECREDUCE_AND |
| 10805 | 0U, // G_VECREDUCE_OR |
| 10806 | 0U, // G_VECREDUCE_XOR |
| 10807 | 0U, // G_VECREDUCE_SMAX |
| 10808 | 0U, // G_VECREDUCE_SMIN |
| 10809 | 0U, // G_VECREDUCE_UMAX |
| 10810 | 0U, // G_VECREDUCE_UMIN |
| 10811 | 0U, // G_SBFX |
| 10812 | 0U, // G_UBFX |
| 10813 | 0U, // ABS_ZPmZ_B_UNDEF |
| 10814 | 0U, // ABS_ZPmZ_D_UNDEF |
| 10815 | 0U, // ABS_ZPmZ_H_UNDEF |
| 10816 | 0U, // ABS_ZPmZ_S_UNDEF |
| 10817 | 0U, // ADDHA_MPPZ_D_PSEUDO_D |
| 10818 | 0U, // ADDHA_MPPZ_S_PSEUDO_S |
| 10819 | 0U, // ADDSWrr |
| 10820 | 0U, // ADDSXrr |
| 10821 | 0U, // ADDVA_MPPZ_D_PSEUDO_D |
| 10822 | 0U, // ADDVA_MPPZ_S_PSEUDO_S |
| 10823 | 0U, // ADDWrr |
| 10824 | 0U, // ADDXrr |
| 10825 | 0U, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 10826 | 0U, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 10827 | 0U, // ADD_VG2_M2ZZ_D_PSEUDO |
| 10828 | 0U, // ADD_VG2_M2ZZ_S_PSEUDO |
| 10829 | 0U, // ADD_VG2_M2Z_D_PSEUDO |
| 10830 | 0U, // ADD_VG2_M2Z_S_PSEUDO |
| 10831 | 0U, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 10832 | 0U, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 10833 | 0U, // ADD_VG4_M4ZZ_D_PSEUDO |
| 10834 | 0U, // ADD_VG4_M4ZZ_S_PSEUDO |
| 10835 | 0U, // ADD_VG4_M4Z_D_PSEUDO |
| 10836 | 0U, // ADD_VG4_M4Z_S_PSEUDO |
| 10837 | 0U, // ADD_ZPZZ_B_ZERO |
| 10838 | 0U, // ADD_ZPZZ_D_ZERO |
| 10839 | 0U, // ADD_ZPZZ_H_ZERO |
| 10840 | 0U, // ADD_ZPZZ_S_ZERO |
| 10841 | 0U, // ADDlowTLS |
| 10842 | 0U, // ADJCALLSTACKDOWN |
| 10843 | 0U, // ADJCALLSTACKUP |
| 10844 | 0U, // AESIMCrrTied |
| 10845 | 0U, // AESMCrrTied |
| 10846 | 0U, // ANDSWrr |
| 10847 | 0U, // ANDSXrr |
| 10848 | 0U, // ANDWrr |
| 10849 | 0U, // ANDXrr |
| 10850 | 0U, // AND_ZPZZ_B_ZERO |
| 10851 | 0U, // AND_ZPZZ_D_ZERO |
| 10852 | 0U, // AND_ZPZZ_H_ZERO |
| 10853 | 0U, // AND_ZPZZ_S_ZERO |
| 10854 | 0U, // ASRD_ZPZI_B_ZERO |
| 10855 | 0U, // ASRD_ZPZI_D_ZERO |
| 10856 | 0U, // ASRD_ZPZI_H_ZERO |
| 10857 | 0U, // ASRD_ZPZI_S_ZERO |
| 10858 | 0U, // ASR_ZPZI_B_UNDEF |
| 10859 | 0U, // ASR_ZPZI_B_ZERO |
| 10860 | 0U, // ASR_ZPZI_D_UNDEF |
| 10861 | 0U, // ASR_ZPZI_D_ZERO |
| 10862 | 0U, // ASR_ZPZI_H_UNDEF |
| 10863 | 0U, // ASR_ZPZI_H_ZERO |
| 10864 | 0U, // ASR_ZPZI_S_UNDEF |
| 10865 | 0U, // ASR_ZPZI_S_ZERO |
| 10866 | 0U, // ASR_ZPZZ_B_UNDEF |
| 10867 | 0U, // ASR_ZPZZ_B_ZERO |
| 10868 | 0U, // ASR_ZPZZ_D_UNDEF |
| 10869 | 0U, // ASR_ZPZZ_D_ZERO |
| 10870 | 0U, // ASR_ZPZZ_H_UNDEF |
| 10871 | 0U, // ASR_ZPZZ_H_ZERO |
| 10872 | 0U, // ASR_ZPZZ_S_UNDEF |
| 10873 | 0U, // ASR_ZPZZ_S_ZERO |
| 10874 | 0U, // AUT |
| 10875 | 0U, // AUTH_TCRETURN |
| 10876 | 0U, // AUTH_TCRETURN_BTI |
| 10877 | 0U, // AUTPAC |
| 10878 | 0U, // AllocateZABuffer |
| 10879 | 0U, // BFADD_VG2_M2Z_H_PSEUDO |
| 10880 | 0U, // BFADD_VG4_M4Z_H_PSEUDO |
| 10881 | 0U, // BFADD_ZPZZ_UNDEF |
| 10882 | 0U, // BFADD_ZPZZ_ZERO |
| 10883 | 0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 10884 | 0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 10885 | 0U, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 10886 | 0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 10887 | 0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 10888 | 0U, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 10889 | 0U, // BFMAXNM_ZPZZ_UNDEF |
| 10890 | 0U, // BFMAXNM_ZPZZ_ZERO |
| 10891 | 0U, // BFMAX_ZPZZ_UNDEF |
| 10892 | 0U, // BFMAX_ZPZZ_ZERO |
| 10893 | 0U, // BFMINNM_ZPZZ_UNDEF |
| 10894 | 0U, // BFMINNM_ZPZZ_ZERO |
| 10895 | 0U, // BFMIN_ZPZZ_UNDEF |
| 10896 | 0U, // BFMIN_ZPZZ_ZERO |
| 10897 | 0U, // BFMLAL_MZZI_HtoS_PSEUDO |
| 10898 | 0U, // BFMLAL_MZZ_HtoS_PSEUDO |
| 10899 | 0U, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 10900 | 0U, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 10901 | 0U, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 10902 | 0U, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 10903 | 0U, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 10904 | 0U, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 10905 | 0U, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 10906 | 0U, // BFMLA_VG2_M2ZZI_PSEUDO |
| 10907 | 0U, // BFMLA_VG2_M2ZZ_PSEUDO |
| 10908 | 0U, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 10909 | 0U, // BFMLA_VG4_M4ZZI_PSEUDO |
| 10910 | 0U, // BFMLA_VG4_M4ZZ_PSEUDO |
| 10911 | 0U, // BFMLA_ZPZZZ_UNDEF |
| 10912 | 0U, // BFMLSL_MZZI_HtoS_PSEUDO |
| 10913 | 0U, // BFMLSL_MZZ_HtoS_PSEUDO |
| 10914 | 0U, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 10915 | 0U, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 10916 | 0U, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 10917 | 0U, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 10918 | 0U, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 10919 | 0U, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 10920 | 0U, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 10921 | 0U, // BFMLS_VG2_M2ZZI_PSEUDO |
| 10922 | 0U, // BFMLS_VG2_M2ZZ_PSEUDO |
| 10923 | 0U, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 10924 | 0U, // BFMLS_VG4_M4ZZI_PSEUDO |
| 10925 | 0U, // BFMLS_VG4_M4ZZ_PSEUDO |
| 10926 | 0U, // BFMLS_ZPZZZ_UNDEF |
| 10927 | 0U, // BFMOPA_MPPZZ_H_PSEUDO |
| 10928 | 0U, // BFMOPA_MPPZZ_PSEUDO |
| 10929 | 0U, // BFMOPS_MPPZZ_H_PSEUDO |
| 10930 | 0U, // BFMOPS_MPPZZ_PSEUDO |
| 10931 | 0U, // BFMUL_ZPZZ_UNDEF |
| 10932 | 0U, // BFMUL_ZPZZ_ZERO |
| 10933 | 0U, // BFSUB_VG2_M2Z_H_PSEUDO |
| 10934 | 0U, // BFSUB_VG4_M4Z_H_PSEUDO |
| 10935 | 0U, // BFSUB_ZPZZ_UNDEF |
| 10936 | 0U, // BFSUB_ZPZZ_ZERO |
| 10937 | 0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 10938 | 0U, // BICSWrr |
| 10939 | 0U, // BICSXrr |
| 10940 | 0U, // BICWrr |
| 10941 | 0U, // BICXrr |
| 10942 | 0U, // BIC_ZPZZ_B_ZERO |
| 10943 | 0U, // BIC_ZPZZ_D_ZERO |
| 10944 | 0U, // BIC_ZPZZ_H_ZERO |
| 10945 | 0U, // BIC_ZPZZ_S_ZERO |
| 10946 | 0U, // BLRA |
| 10947 | 0U, // BLRA_RVMARKER |
| 10948 | 0U, // BLRNoIP |
| 10949 | 0U, // BLR_BTI |
| 10950 | 0U, // BLR_RVMARKER |
| 10951 | 0U, // BLR_X16 |
| 10952 | 0U, // BMOPA_MPPZZ_S_PSEUDO |
| 10953 | 0U, // BMOPS_MPPZZ_S_PSEUDO |
| 10954 | 0U, // BRA |
| 10955 | 0U, // BR_JumpTable |
| 10956 | 0U, // BSPv16i8 |
| 10957 | 0U, // BSPv8i8 |
| 10958 | 0U, // CATCHRET |
| 10959 | 0U, // CLEANUPRET |
| 10960 | 0U, // CLS_ZPmZ_B_UNDEF |
| 10961 | 0U, // CLS_ZPmZ_D_UNDEF |
| 10962 | 0U, // CLS_ZPmZ_H_UNDEF |
| 10963 | 0U, // CLS_ZPmZ_S_UNDEF |
| 10964 | 0U, // CLZ_ZPmZ_B_UNDEF |
| 10965 | 0U, // CLZ_ZPmZ_D_UNDEF |
| 10966 | 0U, // CLZ_ZPmZ_H_UNDEF |
| 10967 | 0U, // CLZ_ZPmZ_S_UNDEF |
| 10968 | 0U, // CMP_SWAP_128 |
| 10969 | 0U, // CMP_SWAP_128_ACQUIRE |
| 10970 | 0U, // CMP_SWAP_128_MONOTONIC |
| 10971 | 0U, // CMP_SWAP_128_RELEASE |
| 10972 | 0U, // CMP_SWAP_16 |
| 10973 | 0U, // CMP_SWAP_32 |
| 10974 | 0U, // CMP_SWAP_64 |
| 10975 | 0U, // CMP_SWAP_8 |
| 10976 | 0U, // CNOT_ZPmZ_B_UNDEF |
| 10977 | 0U, // CNOT_ZPmZ_D_UNDEF |
| 10978 | 0U, // CNOT_ZPmZ_H_UNDEF |
| 10979 | 0U, // CNOT_ZPmZ_S_UNDEF |
| 10980 | 0U, // CNT_ZPmZ_B_UNDEF |
| 10981 | 0U, // CNT_ZPmZ_D_UNDEF |
| 10982 | 0U, // CNT_ZPmZ_H_UNDEF |
| 10983 | 0U, // CNT_ZPmZ_S_UNDEF |
| 10984 | 0U, // COALESCER_BARRIER_FPR128 |
| 10985 | 0U, // COALESCER_BARRIER_FPR16 |
| 10986 | 0U, // COALESCER_BARRIER_FPR32 |
| 10987 | 0U, // COALESCER_BARRIER_FPR64 |
| 10988 | 0U, // EMITBKEY |
| 10989 | 0U, // EMITMTETAGGED |
| 10990 | 0U, // EONWrr |
| 10991 | 0U, // EONXrr |
| 10992 | 0U, // EORWrr |
| 10993 | 0U, // EORXrr |
| 10994 | 0U, // EOR_ZPZZ_B_ZERO |
| 10995 | 0U, // EOR_ZPZZ_D_ZERO |
| 10996 | 0U, // EOR_ZPZZ_H_ZERO |
| 10997 | 0U, // EOR_ZPZZ_S_ZERO |
| 10998 | 0U, // F128CSEL |
| 10999 | 0U, // FABD_ZPZZ_D_UNDEF |
| 11000 | 0U, // FABD_ZPZZ_D_ZERO |
| 11001 | 0U, // FABD_ZPZZ_H_UNDEF |
| 11002 | 0U, // FABD_ZPZZ_H_ZERO |
| 11003 | 0U, // FABD_ZPZZ_S_UNDEF |
| 11004 | 0U, // FABD_ZPZZ_S_ZERO |
| 11005 | 0U, // FABS_ZPmZ_D_UNDEF |
| 11006 | 0U, // FABS_ZPmZ_H_UNDEF |
| 11007 | 0U, // FABS_ZPmZ_S_UNDEF |
| 11008 | 0U, // FADD_VG2_M2Z_D_PSEUDO |
| 11009 | 0U, // FADD_VG2_M2Z_H_PSEUDO |
| 11010 | 0U, // FADD_VG2_M2Z_S_PSEUDO |
| 11011 | 0U, // FADD_VG4_M4Z_D_PSEUDO |
| 11012 | 0U, // FADD_VG4_M4Z_H_PSEUDO |
| 11013 | 0U, // FADD_VG4_M4Z_S_PSEUDO |
| 11014 | 0U, // FADD_ZPZI_D_UNDEF |
| 11015 | 0U, // FADD_ZPZI_D_ZERO |
| 11016 | 0U, // FADD_ZPZI_H_UNDEF |
| 11017 | 0U, // FADD_ZPZI_H_ZERO |
| 11018 | 0U, // FADD_ZPZI_S_UNDEF |
| 11019 | 0U, // FADD_ZPZI_S_ZERO |
| 11020 | 0U, // FADD_ZPZZ_D_UNDEF |
| 11021 | 0U, // FADD_ZPZZ_D_ZERO |
| 11022 | 0U, // FADD_ZPZZ_H_UNDEF |
| 11023 | 0U, // FADD_ZPZZ_H_ZERO |
| 11024 | 0U, // FADD_ZPZZ_S_UNDEF |
| 11025 | 0U, // FADD_ZPZZ_S_ZERO |
| 11026 | 0U, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 11027 | 0U, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 11028 | 0U, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 11029 | 0U, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 11030 | 0U, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 11031 | 0U, // FCVTZS_ZPmZ_StoD_UNDEF |
| 11032 | 0U, // FCVTZS_ZPmZ_StoS_UNDEF |
| 11033 | 0U, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 11034 | 0U, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 11035 | 0U, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 11036 | 0U, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 11037 | 0U, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 11038 | 0U, // FCVTZU_ZPmZ_StoD_UNDEF |
| 11039 | 0U, // FCVTZU_ZPmZ_StoS_UNDEF |
| 11040 | 0U, // FCVT_ZPmZ_DtoH_UNDEF |
| 11041 | 0U, // FCVT_ZPmZ_DtoS_UNDEF |
| 11042 | 0U, // FCVT_ZPmZ_HtoD_UNDEF |
| 11043 | 0U, // FCVT_ZPmZ_HtoS_UNDEF |
| 11044 | 0U, // FCVT_ZPmZ_StoD_UNDEF |
| 11045 | 0U, // FCVT_ZPmZ_StoH_UNDEF |
| 11046 | 0U, // FDIVR_ZPZZ_D_ZERO |
| 11047 | 0U, // FDIVR_ZPZZ_H_ZERO |
| 11048 | 0U, // FDIVR_ZPZZ_S_ZERO |
| 11049 | 0U, // FDIV_ZPZZ_D_UNDEF |
| 11050 | 0U, // FDIV_ZPZZ_D_ZERO |
| 11051 | 0U, // FDIV_ZPZZ_H_UNDEF |
| 11052 | 0U, // FDIV_ZPZZ_H_ZERO |
| 11053 | 0U, // FDIV_ZPZZ_S_UNDEF |
| 11054 | 0U, // FDIV_ZPZZ_S_ZERO |
| 11055 | 0U, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO |
| 11056 | 0U, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 11057 | 0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 11058 | 0U, // FDOT_VG2_M2ZZI_BtoS_PSEUDO |
| 11059 | 0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11060 | 0U, // FDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 11061 | 0U, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO |
| 11062 | 0U, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 11063 | 0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 11064 | 0U, // FDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 11065 | 0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 11066 | 0U, // FDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 11067 | 0U, // FLOGB_ZPZZ_D_ZERO |
| 11068 | 0U, // FLOGB_ZPZZ_H_ZERO |
| 11069 | 0U, // FLOGB_ZPZZ_S_ZERO |
| 11070 | 0U, // FMAXNM_ZPZI_D_UNDEF |
| 11071 | 0U, // FMAXNM_ZPZI_D_ZERO |
| 11072 | 0U, // FMAXNM_ZPZI_H_UNDEF |
| 11073 | 0U, // FMAXNM_ZPZI_H_ZERO |
| 11074 | 0U, // FMAXNM_ZPZI_S_UNDEF |
| 11075 | 0U, // FMAXNM_ZPZI_S_ZERO |
| 11076 | 0U, // FMAXNM_ZPZZ_D_UNDEF |
| 11077 | 0U, // FMAXNM_ZPZZ_D_ZERO |
| 11078 | 0U, // FMAXNM_ZPZZ_H_UNDEF |
| 11079 | 0U, // FMAXNM_ZPZZ_H_ZERO |
| 11080 | 0U, // FMAXNM_ZPZZ_S_UNDEF |
| 11081 | 0U, // FMAXNM_ZPZZ_S_ZERO |
| 11082 | 0U, // FMAX_ZPZI_D_UNDEF |
| 11083 | 0U, // FMAX_ZPZI_D_ZERO |
| 11084 | 0U, // FMAX_ZPZI_H_UNDEF |
| 11085 | 0U, // FMAX_ZPZI_H_ZERO |
| 11086 | 0U, // FMAX_ZPZI_S_UNDEF |
| 11087 | 0U, // FMAX_ZPZI_S_ZERO |
| 11088 | 0U, // FMAX_ZPZZ_D_UNDEF |
| 11089 | 0U, // FMAX_ZPZZ_D_ZERO |
| 11090 | 0U, // FMAX_ZPZZ_H_UNDEF |
| 11091 | 0U, // FMAX_ZPZZ_H_ZERO |
| 11092 | 0U, // FMAX_ZPZZ_S_UNDEF |
| 11093 | 0U, // FMAX_ZPZZ_S_ZERO |
| 11094 | 0U, // FMINNM_ZPZI_D_UNDEF |
| 11095 | 0U, // FMINNM_ZPZI_D_ZERO |
| 11096 | 0U, // FMINNM_ZPZI_H_UNDEF |
| 11097 | 0U, // FMINNM_ZPZI_H_ZERO |
| 11098 | 0U, // FMINNM_ZPZI_S_UNDEF |
| 11099 | 0U, // FMINNM_ZPZI_S_ZERO |
| 11100 | 0U, // FMINNM_ZPZZ_D_UNDEF |
| 11101 | 0U, // FMINNM_ZPZZ_D_ZERO |
| 11102 | 0U, // FMINNM_ZPZZ_H_UNDEF |
| 11103 | 0U, // FMINNM_ZPZZ_H_ZERO |
| 11104 | 0U, // FMINNM_ZPZZ_S_UNDEF |
| 11105 | 0U, // FMINNM_ZPZZ_S_ZERO |
| 11106 | 0U, // FMIN_ZPZI_D_UNDEF |
| 11107 | 0U, // FMIN_ZPZI_D_ZERO |
| 11108 | 0U, // FMIN_ZPZI_H_UNDEF |
| 11109 | 0U, // FMIN_ZPZI_H_ZERO |
| 11110 | 0U, // FMIN_ZPZI_S_UNDEF |
| 11111 | 0U, // FMIN_ZPZI_S_ZERO |
| 11112 | 0U, // FMIN_ZPZZ_D_UNDEF |
| 11113 | 0U, // FMIN_ZPZZ_D_ZERO |
| 11114 | 0U, // FMIN_ZPZZ_H_UNDEF |
| 11115 | 0U, // FMIN_ZPZZ_H_ZERO |
| 11116 | 0U, // FMIN_ZPZZ_S_UNDEF |
| 11117 | 0U, // FMIN_ZPZZ_S_ZERO |
| 11118 | 0U, // FMLALL_MZZI_BtoS_PSEUDO |
| 11119 | 0U, // FMLALL_MZZ_BtoS_PSEUDO |
| 11120 | 0U, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11121 | 0U, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11122 | 0U, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11123 | 0U, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11124 | 0U, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11125 | 0U, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11126 | 0U, // FMLAL_MZZI_HtoS_PSEUDO |
| 11127 | 0U, // FMLAL_MZZ_HtoS_PSEUDO |
| 11128 | 0U, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO |
| 11129 | 0U, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11130 | 0U, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 11131 | 0U, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO |
| 11132 | 0U, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 11133 | 0U, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO |
| 11134 | 0U, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11135 | 0U, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 11136 | 0U, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO |
| 11137 | 0U, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 11138 | 0U, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 11139 | 0U, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 11140 | 0U, // FMLA_VG2_M2Z4Z_H_PSEUDO |
| 11141 | 0U, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 11142 | 0U, // FMLA_VG2_M2ZZI_H_PSEUDO |
| 11143 | 0U, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 11144 | 0U, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 11145 | 0U, // FMLA_VG2_M2ZZ_H_PSEUDO |
| 11146 | 0U, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 11147 | 0U, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 11148 | 0U, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 11149 | 0U, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 11150 | 0U, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 11151 | 0U, // FMLA_VG4_M4ZZI_H_PSEUDO |
| 11152 | 0U, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 11153 | 0U, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 11154 | 0U, // FMLA_VG4_M4ZZ_H_PSEUDO |
| 11155 | 0U, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 11156 | 0U, // FMLA_ZPZZZ_D_UNDEF |
| 11157 | 0U, // FMLA_ZPZZZ_H_UNDEF |
| 11158 | 0U, // FMLA_ZPZZZ_S_UNDEF |
| 11159 | 0U, // FMLSL_MZZI_HtoS_PSEUDO |
| 11160 | 0U, // FMLSL_MZZ_HtoS_PSEUDO |
| 11161 | 0U, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11162 | 0U, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 11163 | 0U, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 11164 | 0U, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11165 | 0U, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 11166 | 0U, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 11167 | 0U, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 11168 | 0U, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 11169 | 0U, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 11170 | 0U, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 11171 | 0U, // FMLS_VG2_M2ZZI_H_PSEUDO |
| 11172 | 0U, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 11173 | 0U, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 11174 | 0U, // FMLS_VG2_M2ZZ_H_PSEUDO |
| 11175 | 0U, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 11176 | 0U, // FMLS_VG4_M4Z2Z_H_PSEUDO |
| 11177 | 0U, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 11178 | 0U, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 11179 | 0U, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 11180 | 0U, // FMLS_VG4_M4ZZI_H_PSEUDO |
| 11181 | 0U, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 11182 | 0U, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 11183 | 0U, // FMLS_VG4_M4ZZ_H_PSEUDO |
| 11184 | 0U, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 11185 | 0U, // FMLS_ZPZZZ_D_UNDEF |
| 11186 | 0U, // FMLS_ZPZZZ_H_UNDEF |
| 11187 | 0U, // FMLS_ZPZZZ_S_UNDEF |
| 11188 | 0U, // FMOPAL_MPPZZ_PSEUDO |
| 11189 | 0U, // FMOPA_MPPZZ_BtoS_PSEUDO |
| 11190 | 0U, // FMOPA_MPPZZ_D_PSEUDO |
| 11191 | 0U, // FMOPA_MPPZZ_H_PSEUDO |
| 11192 | 0U, // FMOPA_MPPZZ_S_PSEUDO |
| 11193 | 0U, // FMOPSL_MPPZZ_PSEUDO |
| 11194 | 0U, // FMOPS_MPPZZ_D_PSEUDO |
| 11195 | 0U, // FMOPS_MPPZZ_H_PSEUDO |
| 11196 | 0U, // FMOPS_MPPZZ_S_PSEUDO |
| 11197 | 0U, // FMOVD0 |
| 11198 | 0U, // FMOVH0 |
| 11199 | 0U, // FMOVS0 |
| 11200 | 0U, // FMULX_ZPZZ_D_UNDEF |
| 11201 | 0U, // FMULX_ZPZZ_D_ZERO |
| 11202 | 0U, // FMULX_ZPZZ_H_UNDEF |
| 11203 | 0U, // FMULX_ZPZZ_H_ZERO |
| 11204 | 0U, // FMULX_ZPZZ_S_UNDEF |
| 11205 | 0U, // FMULX_ZPZZ_S_ZERO |
| 11206 | 0U, // FMUL_ZPZI_D_UNDEF |
| 11207 | 0U, // FMUL_ZPZI_D_ZERO |
| 11208 | 0U, // FMUL_ZPZI_H_UNDEF |
| 11209 | 0U, // FMUL_ZPZI_H_ZERO |
| 11210 | 0U, // FMUL_ZPZI_S_UNDEF |
| 11211 | 0U, // FMUL_ZPZI_S_ZERO |
| 11212 | 0U, // FMUL_ZPZZ_D_UNDEF |
| 11213 | 0U, // FMUL_ZPZZ_D_ZERO |
| 11214 | 0U, // FMUL_ZPZZ_H_UNDEF |
| 11215 | 0U, // FMUL_ZPZZ_H_ZERO |
| 11216 | 0U, // FMUL_ZPZZ_S_UNDEF |
| 11217 | 0U, // FMUL_ZPZZ_S_ZERO |
| 11218 | 0U, // FNEG_ZPmZ_D_UNDEF |
| 11219 | 0U, // FNEG_ZPmZ_H_UNDEF |
| 11220 | 0U, // FNEG_ZPmZ_S_UNDEF |
| 11221 | 0U, // FNMLA_ZPZZZ_D_UNDEF |
| 11222 | 0U, // FNMLA_ZPZZZ_H_UNDEF |
| 11223 | 0U, // FNMLA_ZPZZZ_S_UNDEF |
| 11224 | 0U, // FNMLS_ZPZZZ_D_UNDEF |
| 11225 | 0U, // FNMLS_ZPZZZ_H_UNDEF |
| 11226 | 0U, // FNMLS_ZPZZZ_S_UNDEF |
| 11227 | 0U, // FRECPX_ZPmZ_D_UNDEF |
| 11228 | 0U, // FRECPX_ZPmZ_H_UNDEF |
| 11229 | 0U, // FRECPX_ZPmZ_S_UNDEF |
| 11230 | 0U, // FRINTA_ZPmZ_D_UNDEF |
| 11231 | 0U, // FRINTA_ZPmZ_H_UNDEF |
| 11232 | 0U, // FRINTA_ZPmZ_S_UNDEF |
| 11233 | 0U, // FRINTI_ZPmZ_D_UNDEF |
| 11234 | 0U, // FRINTI_ZPmZ_H_UNDEF |
| 11235 | 0U, // FRINTI_ZPmZ_S_UNDEF |
| 11236 | 0U, // FRINTM_ZPmZ_D_UNDEF |
| 11237 | 0U, // FRINTM_ZPmZ_H_UNDEF |
| 11238 | 0U, // FRINTM_ZPmZ_S_UNDEF |
| 11239 | 0U, // FRINTN_ZPmZ_D_UNDEF |
| 11240 | 0U, // FRINTN_ZPmZ_H_UNDEF |
| 11241 | 0U, // FRINTN_ZPmZ_S_UNDEF |
| 11242 | 0U, // FRINTP_ZPmZ_D_UNDEF |
| 11243 | 0U, // FRINTP_ZPmZ_H_UNDEF |
| 11244 | 0U, // FRINTP_ZPmZ_S_UNDEF |
| 11245 | 0U, // FRINTX_ZPmZ_D_UNDEF |
| 11246 | 0U, // FRINTX_ZPmZ_H_UNDEF |
| 11247 | 0U, // FRINTX_ZPmZ_S_UNDEF |
| 11248 | 0U, // FRINTZ_ZPmZ_D_UNDEF |
| 11249 | 0U, // FRINTZ_ZPmZ_H_UNDEF |
| 11250 | 0U, // FRINTZ_ZPmZ_S_UNDEF |
| 11251 | 0U, // FSQRT_ZPmZ_D_UNDEF |
| 11252 | 0U, // FSQRT_ZPmZ_H_UNDEF |
| 11253 | 0U, // FSQRT_ZPmZ_S_UNDEF |
| 11254 | 0U, // FSUBR_ZPZI_D_UNDEF |
| 11255 | 0U, // FSUBR_ZPZI_D_ZERO |
| 11256 | 0U, // FSUBR_ZPZI_H_UNDEF |
| 11257 | 0U, // FSUBR_ZPZI_H_ZERO |
| 11258 | 0U, // FSUBR_ZPZI_S_UNDEF |
| 11259 | 0U, // FSUBR_ZPZI_S_ZERO |
| 11260 | 0U, // FSUBR_ZPZZ_D_ZERO |
| 11261 | 0U, // FSUBR_ZPZZ_H_ZERO |
| 11262 | 0U, // FSUBR_ZPZZ_S_ZERO |
| 11263 | 0U, // FSUB_VG2_M2Z_D_PSEUDO |
| 11264 | 0U, // FSUB_VG2_M2Z_H_PSEUDO |
| 11265 | 0U, // FSUB_VG2_M2Z_S_PSEUDO |
| 11266 | 0U, // FSUB_VG4_M4Z_D_PSEUDO |
| 11267 | 0U, // FSUB_VG4_M4Z_H_PSEUDO |
| 11268 | 0U, // FSUB_VG4_M4Z_S_PSEUDO |
| 11269 | 0U, // FSUB_ZPZI_D_UNDEF |
| 11270 | 0U, // FSUB_ZPZI_D_ZERO |
| 11271 | 0U, // FSUB_ZPZI_H_UNDEF |
| 11272 | 0U, // FSUB_ZPZI_H_ZERO |
| 11273 | 0U, // FSUB_ZPZI_S_UNDEF |
| 11274 | 0U, // FSUB_ZPZI_S_ZERO |
| 11275 | 0U, // FSUB_ZPZZ_D_UNDEF |
| 11276 | 0U, // FSUB_ZPZZ_D_ZERO |
| 11277 | 0U, // FSUB_ZPZZ_H_UNDEF |
| 11278 | 0U, // FSUB_ZPZZ_H_ZERO |
| 11279 | 0U, // FSUB_ZPZZ_S_UNDEF |
| 11280 | 0U, // FSUB_ZPZZ_S_ZERO |
| 11281 | 0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11282 | 0U, // G_AARCH64_PREFETCH |
| 11283 | 0U, // G_ADD_LOW |
| 11284 | 0U, // G_BSP |
| 11285 | 0U, // G_DUP |
| 11286 | 0U, // G_DUPLANE16 |
| 11287 | 0U, // G_DUPLANE32 |
| 11288 | 0U, // G_DUPLANE64 |
| 11289 | 0U, // G_DUPLANE8 |
| 11290 | 0U, // G_EXT |
| 11291 | 0U, // G_FCMEQ |
| 11292 | 0U, // G_FCMEQZ |
| 11293 | 0U, // G_FCMGE |
| 11294 | 0U, // G_FCMGEZ |
| 11295 | 0U, // G_FCMGT |
| 11296 | 0U, // G_FCMGTZ |
| 11297 | 0U, // G_FCMLEZ |
| 11298 | 0U, // G_FCMLTZ |
| 11299 | 0U, // G_REV16 |
| 11300 | 0U, // G_REV32 |
| 11301 | 0U, // G_REV64 |
| 11302 | 0U, // G_SADDLP |
| 11303 | 0U, // G_SADDLV |
| 11304 | 0U, // G_SDOT |
| 11305 | 0U, // G_SITOF |
| 11306 | 0U, // G_SMULL |
| 11307 | 0U, // G_TRN1 |
| 11308 | 0U, // G_TRN2 |
| 11309 | 0U, // G_UADDLP |
| 11310 | 0U, // G_UADDLV |
| 11311 | 0U, // G_UDOT |
| 11312 | 0U, // G_UITOF |
| 11313 | 0U, // G_UMULL |
| 11314 | 0U, // G_UZP1 |
| 11315 | 0U, // G_UZP2 |
| 11316 | 0U, // G_VASHR |
| 11317 | 0U, // G_VLSHR |
| 11318 | 0U, // G_ZIP1 |
| 11319 | 0U, // G_ZIP2 |
| 11320 | 0U, // HOM_Epilog |
| 11321 | 0U, // HOM_Prolog |
| 11322 | 0U, // HWASAN_CHECK_MEMACCESS |
| 11323 | 0U, // HWASAN_CHECK_MEMACCESS_FIXEDSHADOW |
| 11324 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 11325 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW |
| 11326 | 0U, // INSERT_MXIPZ_H_PSEUDO_B |
| 11327 | 0U, // INSERT_MXIPZ_H_PSEUDO_D |
| 11328 | 0U, // INSERT_MXIPZ_H_PSEUDO_H |
| 11329 | 0U, // INSERT_MXIPZ_H_PSEUDO_Q |
| 11330 | 0U, // INSERT_MXIPZ_H_PSEUDO_S |
| 11331 | 0U, // INSERT_MXIPZ_V_PSEUDO_B |
| 11332 | 0U, // INSERT_MXIPZ_V_PSEUDO_D |
| 11333 | 0U, // INSERT_MXIPZ_V_PSEUDO_H |
| 11334 | 0U, // INSERT_MXIPZ_V_PSEUDO_Q |
| 11335 | 0U, // INSERT_MXIPZ_V_PSEUDO_S |
| 11336 | 0U, // IRGstack |
| 11337 | 0U, // InitTPIDR2Obj |
| 11338 | 0U, // JumpTableDest16 |
| 11339 | 0U, // JumpTableDest32 |
| 11340 | 0U, // JumpTableDest8 |
| 11341 | 0U, // KCFI_CHECK |
| 11342 | 0U, // LD1B_2Z_IMM_PSEUDO |
| 11343 | 0U, // LD1B_2Z_PSEUDO |
| 11344 | 0U, // LD1B_4Z_IMM_PSEUDO |
| 11345 | 0U, // LD1B_4Z_PSEUDO |
| 11346 | 0U, // LD1D_2Z_IMM_PSEUDO |
| 11347 | 0U, // LD1D_2Z_PSEUDO |
| 11348 | 0U, // LD1D_4Z_IMM_PSEUDO |
| 11349 | 0U, // LD1D_4Z_PSEUDO |
| 11350 | 0U, // LD1H_2Z_IMM_PSEUDO |
| 11351 | 0U, // LD1H_2Z_PSEUDO |
| 11352 | 0U, // LD1H_4Z_IMM_PSEUDO |
| 11353 | 0U, // LD1H_4Z_PSEUDO |
| 11354 | 0U, // LD1W_2Z_IMM_PSEUDO |
| 11355 | 0U, // LD1W_2Z_PSEUDO |
| 11356 | 0U, // LD1W_4Z_IMM_PSEUDO |
| 11357 | 0U, // LD1W_4Z_PSEUDO |
| 11358 | 0U, // LD1_MXIPXX_H_PSEUDO_B |
| 11359 | 0U, // LD1_MXIPXX_H_PSEUDO_D |
| 11360 | 0U, // LD1_MXIPXX_H_PSEUDO_H |
| 11361 | 0U, // LD1_MXIPXX_H_PSEUDO_Q |
| 11362 | 0U, // LD1_MXIPXX_H_PSEUDO_S |
| 11363 | 0U, // LD1_MXIPXX_V_PSEUDO_B |
| 11364 | 0U, // LD1_MXIPXX_V_PSEUDO_D |
| 11365 | 0U, // LD1_MXIPXX_V_PSEUDO_H |
| 11366 | 0U, // LD1_MXIPXX_V_PSEUDO_Q |
| 11367 | 0U, // LD1_MXIPXX_V_PSEUDO_S |
| 11368 | 0U, // LDNT1B_2Z_IMM_PSEUDO |
| 11369 | 0U, // LDNT1B_2Z_PSEUDO |
| 11370 | 0U, // LDNT1B_4Z_IMM_PSEUDO |
| 11371 | 0U, // LDNT1B_4Z_PSEUDO |
| 11372 | 0U, // LDNT1D_2Z_IMM_PSEUDO |
| 11373 | 0U, // LDNT1D_2Z_PSEUDO |
| 11374 | 0U, // LDNT1D_4Z_IMM_PSEUDO |
| 11375 | 0U, // LDNT1D_4Z_PSEUDO |
| 11376 | 0U, // LDNT1H_2Z_IMM_PSEUDO |
| 11377 | 0U, // LDNT1H_2Z_PSEUDO |
| 11378 | 0U, // LDNT1H_4Z_IMM_PSEUDO |
| 11379 | 0U, // LDNT1H_4Z_PSEUDO |
| 11380 | 0U, // LDNT1W_2Z_IMM_PSEUDO |
| 11381 | 0U, // LDNT1W_2Z_PSEUDO |
| 11382 | 0U, // LDNT1W_4Z_IMM_PSEUDO |
| 11383 | 0U, // LDNT1W_4Z_PSEUDO |
| 11384 | 0U, // LDR_PPXI |
| 11385 | 0U, // LDR_TX_PSEUDO |
| 11386 | 0U, // LDR_ZA_PSEUDO |
| 11387 | 0U, // LDR_ZZXI |
| 11388 | 0U, // LDR_ZZZXI |
| 11389 | 0U, // LDR_ZZZZXI |
| 11390 | 0U, // LOADauthptrstatic |
| 11391 | 0U, // LOADgot |
| 11392 | 0U, // LOADgotPAC |
| 11393 | 0U, // LSL_ZPZI_B_UNDEF |
| 11394 | 0U, // LSL_ZPZI_B_ZERO |
| 11395 | 0U, // LSL_ZPZI_D_UNDEF |
| 11396 | 0U, // LSL_ZPZI_D_ZERO |
| 11397 | 0U, // LSL_ZPZI_H_UNDEF |
| 11398 | 0U, // LSL_ZPZI_H_ZERO |
| 11399 | 0U, // LSL_ZPZI_S_UNDEF |
| 11400 | 0U, // LSL_ZPZI_S_ZERO |
| 11401 | 0U, // LSL_ZPZZ_B_UNDEF |
| 11402 | 0U, // LSL_ZPZZ_B_ZERO |
| 11403 | 0U, // LSL_ZPZZ_D_UNDEF |
| 11404 | 0U, // LSL_ZPZZ_D_ZERO |
| 11405 | 0U, // LSL_ZPZZ_H_UNDEF |
| 11406 | 0U, // LSL_ZPZZ_H_ZERO |
| 11407 | 0U, // LSL_ZPZZ_S_UNDEF |
| 11408 | 0U, // LSL_ZPZZ_S_ZERO |
| 11409 | 0U, // LSR_ZPZI_B_UNDEF |
| 11410 | 0U, // LSR_ZPZI_B_ZERO |
| 11411 | 0U, // LSR_ZPZI_D_UNDEF |
| 11412 | 0U, // LSR_ZPZI_D_ZERO |
| 11413 | 0U, // LSR_ZPZI_H_UNDEF |
| 11414 | 0U, // LSR_ZPZI_H_ZERO |
| 11415 | 0U, // LSR_ZPZI_S_UNDEF |
| 11416 | 0U, // LSR_ZPZI_S_ZERO |
| 11417 | 0U, // LSR_ZPZZ_B_UNDEF |
| 11418 | 0U, // LSR_ZPZZ_B_ZERO |
| 11419 | 0U, // LSR_ZPZZ_D_UNDEF |
| 11420 | 0U, // LSR_ZPZZ_D_ZERO |
| 11421 | 0U, // LSR_ZPZZ_H_UNDEF |
| 11422 | 0U, // LSR_ZPZZ_H_ZERO |
| 11423 | 0U, // LSR_ZPZZ_S_UNDEF |
| 11424 | 0U, // LSR_ZPZZ_S_ZERO |
| 11425 | 0U, // MLA_ZPZZZ_B_UNDEF |
| 11426 | 0U, // MLA_ZPZZZ_D_UNDEF |
| 11427 | 0U, // MLA_ZPZZZ_H_UNDEF |
| 11428 | 0U, // MLA_ZPZZZ_S_UNDEF |
| 11429 | 0U, // MLS_ZPZZZ_B_UNDEF |
| 11430 | 0U, // MLS_ZPZZZ_D_UNDEF |
| 11431 | 0U, // MLS_ZPZZZ_H_UNDEF |
| 11432 | 0U, // MLS_ZPZZZ_S_UNDEF |
| 11433 | 0U, // MOPSMemoryCopyPseudo |
| 11434 | 0U, // MOPSMemoryMovePseudo |
| 11435 | 0U, // MOPSMemorySetPseudo |
| 11436 | 0U, // MOPSMemorySetTaggingPseudo |
| 11437 | 0U, // MOVAZ_2ZMI_H_B_PSEUDO |
| 11438 | 0U, // MOVAZ_2ZMI_H_D_PSEUDO |
| 11439 | 0U, // MOVAZ_2ZMI_H_H_PSEUDO |
| 11440 | 0U, // MOVAZ_2ZMI_H_S_PSEUDO |
| 11441 | 0U, // MOVAZ_2ZMI_V_B_PSEUDO |
| 11442 | 0U, // MOVAZ_2ZMI_V_D_PSEUDO |
| 11443 | 0U, // MOVAZ_2ZMI_V_H_PSEUDO |
| 11444 | 0U, // MOVAZ_2ZMI_V_S_PSEUDO |
| 11445 | 0U, // MOVAZ_4ZMI_H_B_PSEUDO |
| 11446 | 0U, // MOVAZ_4ZMI_H_D_PSEUDO |
| 11447 | 0U, // MOVAZ_4ZMI_H_H_PSEUDO |
| 11448 | 0U, // MOVAZ_4ZMI_H_S_PSEUDO |
| 11449 | 0U, // MOVAZ_4ZMI_V_B_PSEUDO |
| 11450 | 0U, // MOVAZ_4ZMI_V_D_PSEUDO |
| 11451 | 0U, // MOVAZ_4ZMI_V_H_PSEUDO |
| 11452 | 0U, // MOVAZ_4ZMI_V_S_PSEUDO |
| 11453 | 0U, // MOVAZ_VG2_2ZMXI_PSEUDO |
| 11454 | 0U, // MOVAZ_VG4_4ZMXI_PSEUDO |
| 11455 | 0U, // MOVAZ_ZMI_H_B_PSEUDO |
| 11456 | 0U, // MOVAZ_ZMI_H_D_PSEUDO |
| 11457 | 0U, // MOVAZ_ZMI_H_H_PSEUDO |
| 11458 | 0U, // MOVAZ_ZMI_H_Q_PSEUDO |
| 11459 | 0U, // MOVAZ_ZMI_H_S_PSEUDO |
| 11460 | 0U, // MOVAZ_ZMI_V_B_PSEUDO |
| 11461 | 0U, // MOVAZ_ZMI_V_D_PSEUDO |
| 11462 | 0U, // MOVAZ_ZMI_V_H_PSEUDO |
| 11463 | 0U, // MOVAZ_ZMI_V_Q_PSEUDO |
| 11464 | 0U, // MOVAZ_ZMI_V_S_PSEUDO |
| 11465 | 0U, // MOVA_MXI2Z_H_B_PSEUDO |
| 11466 | 0U, // MOVA_MXI2Z_H_D_PSEUDO |
| 11467 | 0U, // MOVA_MXI2Z_H_H_PSEUDO |
| 11468 | 0U, // MOVA_MXI2Z_H_S_PSEUDO |
| 11469 | 0U, // MOVA_MXI2Z_V_B_PSEUDO |
| 11470 | 0U, // MOVA_MXI2Z_V_D_PSEUDO |
| 11471 | 0U, // MOVA_MXI2Z_V_H_PSEUDO |
| 11472 | 0U, // MOVA_MXI2Z_V_S_PSEUDO |
| 11473 | 0U, // MOVA_MXI4Z_H_B_PSEUDO |
| 11474 | 0U, // MOVA_MXI4Z_H_D_PSEUDO |
| 11475 | 0U, // MOVA_MXI4Z_H_H_PSEUDO |
| 11476 | 0U, // MOVA_MXI4Z_H_S_PSEUDO |
| 11477 | 0U, // MOVA_MXI4Z_V_B_PSEUDO |
| 11478 | 0U, // MOVA_MXI4Z_V_D_PSEUDO |
| 11479 | 0U, // MOVA_MXI4Z_V_H_PSEUDO |
| 11480 | 0U, // MOVA_MXI4Z_V_S_PSEUDO |
| 11481 | 0U, // MOVA_VG2_MXI2Z_PSEUDO |
| 11482 | 0U, // MOVA_VG4_MXI4Z_PSEUDO |
| 11483 | 0U, // MOVMCSym |
| 11484 | 0U, // MOVaddr |
| 11485 | 0U, // MOVaddrBA |
| 11486 | 0U, // MOVaddrCP |
| 11487 | 0U, // MOVaddrEXT |
| 11488 | 0U, // MOVaddrJT |
| 11489 | 0U, // MOVaddrPAC |
| 11490 | 0U, // MOVaddrTLS |
| 11491 | 0U, // MOVbaseTLS |
| 11492 | 0U, // MOVi32imm |
| 11493 | 0U, // MOVi64imm |
| 11494 | 0U, // MRS_FPCR |
| 11495 | 0U, // MRS_FPSR |
| 11496 | 0U, // MSR_FPCR |
| 11497 | 0U, // MSR_FPSR |
| 11498 | 0U, // MSRpstatePseudo |
| 11499 | 0U, // MUL_ZPZZ_B_UNDEF |
| 11500 | 0U, // MUL_ZPZZ_D_UNDEF |
| 11501 | 0U, // MUL_ZPZZ_H_UNDEF |
| 11502 | 0U, // MUL_ZPZZ_S_UNDEF |
| 11503 | 0U, // NEG_ZPmZ_B_UNDEF |
| 11504 | 0U, // NEG_ZPmZ_D_UNDEF |
| 11505 | 0U, // NEG_ZPmZ_H_UNDEF |
| 11506 | 0U, // NEG_ZPmZ_S_UNDEF |
| 11507 | 0U, // NOT_ZPmZ_B_UNDEF |
| 11508 | 0U, // NOT_ZPmZ_D_UNDEF |
| 11509 | 0U, // NOT_ZPmZ_H_UNDEF |
| 11510 | 0U, // NOT_ZPmZ_S_UNDEF |
| 11511 | 0U, // ORNWrr |
| 11512 | 0U, // ORNXrr |
| 11513 | 0U, // ORRWrr |
| 11514 | 0U, // ORRXrr |
| 11515 | 0U, // ORR_ZPZZ_B_ZERO |
| 11516 | 0U, // ORR_ZPZZ_D_ZERO |
| 11517 | 0U, // ORR_ZPZZ_H_ZERO |
| 11518 | 0U, // ORR_ZPZZ_S_ZERO |
| 11519 | 0U, // PAUTH_BLEND |
| 11520 | 0U, // PAUTH_EPILOGUE |
| 11521 | 0U, // PAUTH_PROLOGUE |
| 11522 | 0U, // PROBED_STACKALLOC |
| 11523 | 0U, // PROBED_STACKALLOC_DYN |
| 11524 | 0U, // PROBED_STACKALLOC_VAR |
| 11525 | 0U, // PTEST_PP_ANY |
| 11526 | 0U, // RET_ReallyLR |
| 11527 | 0U, // RestoreZAPseudo |
| 11528 | 0U, // SABD_ZPZZ_B_UNDEF |
| 11529 | 0U, // SABD_ZPZZ_D_UNDEF |
| 11530 | 0U, // SABD_ZPZZ_H_UNDEF |
| 11531 | 0U, // SABD_ZPZZ_S_UNDEF |
| 11532 | 0U, // SCVTF_ZPmZ_DtoD_UNDEF |
| 11533 | 0U, // SCVTF_ZPmZ_DtoH_UNDEF |
| 11534 | 0U, // SCVTF_ZPmZ_DtoS_UNDEF |
| 11535 | 0U, // SCVTF_ZPmZ_HtoH_UNDEF |
| 11536 | 0U, // SCVTF_ZPmZ_StoD_UNDEF |
| 11537 | 0U, // SCVTF_ZPmZ_StoH_UNDEF |
| 11538 | 0U, // SCVTF_ZPmZ_StoS_UNDEF |
| 11539 | 0U, // SDIV_ZPZZ_D_UNDEF |
| 11540 | 0U, // SDIV_ZPZZ_S_UNDEF |
| 11541 | 0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 11542 | 0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 11543 | 0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 11544 | 0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 11545 | 0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 11546 | 0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 11547 | 0U, // SDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 11548 | 0U, // SDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 11549 | 0U, // SDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 11550 | 0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 11551 | 0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 11552 | 0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 11553 | 0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 11554 | 0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 11555 | 0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 11556 | 0U, // SDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 11557 | 0U, // SDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 11558 | 0U, // SDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 11559 | 0U, // SEH_AddFP |
| 11560 | 0U, // SEH_EpilogEnd |
| 11561 | 0U, // SEH_EpilogStart |
| 11562 | 0U, // SEH_Nop |
| 11563 | 0U, // SEH_PACSignLR |
| 11564 | 0U, // SEH_PrologEnd |
| 11565 | 0U, // SEH_SaveAnyRegQP |
| 11566 | 0U, // SEH_SaveAnyRegQPX |
| 11567 | 0U, // SEH_SaveFPLR |
| 11568 | 0U, // SEH_SaveFPLR_X |
| 11569 | 0U, // SEH_SaveFReg |
| 11570 | 0U, // SEH_SaveFRegP |
| 11571 | 0U, // SEH_SaveFRegP_X |
| 11572 | 0U, // SEH_SaveFReg_X |
| 11573 | 0U, // SEH_SaveReg |
| 11574 | 0U, // SEH_SaveRegP |
| 11575 | 0U, // SEH_SaveRegP_X |
| 11576 | 0U, // SEH_SaveReg_X |
| 11577 | 0U, // SEH_SetFP |
| 11578 | 0U, // SEH_StackAlloc |
| 11579 | 0U, // SMAX_ZPZZ_B_UNDEF |
| 11580 | 0U, // SMAX_ZPZZ_D_UNDEF |
| 11581 | 0U, // SMAX_ZPZZ_H_UNDEF |
| 11582 | 0U, // SMAX_ZPZZ_S_UNDEF |
| 11583 | 0U, // SMIN_ZPZZ_B_UNDEF |
| 11584 | 0U, // SMIN_ZPZZ_D_UNDEF |
| 11585 | 0U, // SMIN_ZPZZ_H_UNDEF |
| 11586 | 0U, // SMIN_ZPZZ_S_UNDEF |
| 11587 | 0U, // SMLALL_MZZI_BtoS_PSEUDO |
| 11588 | 0U, // SMLALL_MZZI_HtoD_PSEUDO |
| 11589 | 0U, // SMLALL_MZZ_BtoS_PSEUDO |
| 11590 | 0U, // SMLALL_MZZ_HtoD_PSEUDO |
| 11591 | 0U, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11592 | 0U, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 11593 | 0U, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11594 | 0U, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 11595 | 0U, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11596 | 0U, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 11597 | 0U, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11598 | 0U, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 11599 | 0U, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11600 | 0U, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 11601 | 0U, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11602 | 0U, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 11603 | 0U, // SMLAL_MZZI_HtoS_PSEUDO |
| 11604 | 0U, // SMLAL_MZZ_HtoS_PSEUDO |
| 11605 | 0U, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11606 | 0U, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 11607 | 0U, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 11608 | 0U, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11609 | 0U, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 11610 | 0U, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 11611 | 0U, // SMLSLL_MZZI_BtoS_PSEUDO |
| 11612 | 0U, // SMLSLL_MZZI_HtoD_PSEUDO |
| 11613 | 0U, // SMLSLL_MZZ_BtoS_PSEUDO |
| 11614 | 0U, // SMLSLL_MZZ_HtoD_PSEUDO |
| 11615 | 0U, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11616 | 0U, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 11617 | 0U, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 11618 | 0U, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 11619 | 0U, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 11620 | 0U, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 11621 | 0U, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11622 | 0U, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 11623 | 0U, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 11624 | 0U, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 11625 | 0U, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 11626 | 0U, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 11627 | 0U, // SMLSL_MZZI_HtoS_PSEUDO |
| 11628 | 0U, // SMLSL_MZZ_HtoS_PSEUDO |
| 11629 | 0U, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11630 | 0U, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 11631 | 0U, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 11632 | 0U, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11633 | 0U, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 11634 | 0U, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 11635 | 0U, // SMOPA_MPPZZ_D_PSEUDO |
| 11636 | 0U, // SMOPA_MPPZZ_HtoS_PSEUDO |
| 11637 | 0U, // SMOPA_MPPZZ_S_PSEUDO |
| 11638 | 0U, // SMOPS_MPPZZ_D_PSEUDO |
| 11639 | 0U, // SMOPS_MPPZZ_HtoS_PSEUDO |
| 11640 | 0U, // SMOPS_MPPZZ_S_PSEUDO |
| 11641 | 0U, // SMULH_ZPZZ_B_UNDEF |
| 11642 | 0U, // SMULH_ZPZZ_D_UNDEF |
| 11643 | 0U, // SMULH_ZPZZ_H_UNDEF |
| 11644 | 0U, // SMULH_ZPZZ_S_UNDEF |
| 11645 | 0U, // SPACE |
| 11646 | 0U, // SQABS_ZPmZ_B_UNDEF |
| 11647 | 0U, // SQABS_ZPmZ_D_UNDEF |
| 11648 | 0U, // SQABS_ZPmZ_H_UNDEF |
| 11649 | 0U, // SQABS_ZPmZ_S_UNDEF |
| 11650 | 0U, // SQNEG_ZPmZ_B_UNDEF |
| 11651 | 0U, // SQNEG_ZPmZ_D_UNDEF |
| 11652 | 0U, // SQNEG_ZPmZ_H_UNDEF |
| 11653 | 0U, // SQNEG_ZPmZ_S_UNDEF |
| 11654 | 0U, // SQRSHL_ZPZZ_B_UNDEF |
| 11655 | 0U, // SQRSHL_ZPZZ_D_UNDEF |
| 11656 | 0U, // SQRSHL_ZPZZ_H_UNDEF |
| 11657 | 0U, // SQRSHL_ZPZZ_S_UNDEF |
| 11658 | 0U, // SQSHLU_ZPZI_B_ZERO |
| 11659 | 0U, // SQSHLU_ZPZI_D_ZERO |
| 11660 | 0U, // SQSHLU_ZPZI_H_ZERO |
| 11661 | 0U, // SQSHLU_ZPZI_S_ZERO |
| 11662 | 0U, // SQSHL_ZPZI_B_ZERO |
| 11663 | 0U, // SQSHL_ZPZI_D_ZERO |
| 11664 | 0U, // SQSHL_ZPZI_H_ZERO |
| 11665 | 0U, // SQSHL_ZPZI_S_ZERO |
| 11666 | 0U, // SQSHL_ZPZZ_B_UNDEF |
| 11667 | 0U, // SQSHL_ZPZZ_D_UNDEF |
| 11668 | 0U, // SQSHL_ZPZZ_H_UNDEF |
| 11669 | 0U, // SQSHL_ZPZZ_S_UNDEF |
| 11670 | 0U, // SRSHL_ZPZZ_B_UNDEF |
| 11671 | 0U, // SRSHL_ZPZZ_D_UNDEF |
| 11672 | 0U, // SRSHL_ZPZZ_H_UNDEF |
| 11673 | 0U, // SRSHL_ZPZZ_S_UNDEF |
| 11674 | 0U, // SRSHR_ZPZI_B_ZERO |
| 11675 | 0U, // SRSHR_ZPZI_D_ZERO |
| 11676 | 0U, // SRSHR_ZPZI_H_ZERO |
| 11677 | 0U, // SRSHR_ZPZI_S_ZERO |
| 11678 | 0U, // STGloop |
| 11679 | 0U, // STGloop_wback |
| 11680 | 0U, // STR_PPXI |
| 11681 | 0U, // STR_TX_PSEUDO |
| 11682 | 0U, // STR_ZZXI |
| 11683 | 0U, // STR_ZZZXI |
| 11684 | 0U, // STR_ZZZZXI |
| 11685 | 0U, // STZGloop |
| 11686 | 0U, // STZGloop_wback |
| 11687 | 0U, // SUBR_ZPZZ_B_ZERO |
| 11688 | 0U, // SUBR_ZPZZ_D_ZERO |
| 11689 | 0U, // SUBR_ZPZZ_H_ZERO |
| 11690 | 0U, // SUBR_ZPZZ_S_ZERO |
| 11691 | 0U, // SUBSWrr |
| 11692 | 0U, // SUBSXrr |
| 11693 | 0U, // SUBWrr |
| 11694 | 0U, // SUBXrr |
| 11695 | 0U, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 11696 | 0U, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 11697 | 0U, // SUB_VG2_M2ZZ_D_PSEUDO |
| 11698 | 0U, // SUB_VG2_M2ZZ_S_PSEUDO |
| 11699 | 0U, // SUB_VG2_M2Z_D_PSEUDO |
| 11700 | 0U, // SUB_VG2_M2Z_S_PSEUDO |
| 11701 | 0U, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 11702 | 0U, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 11703 | 0U, // SUB_VG4_M4ZZ_D_PSEUDO |
| 11704 | 0U, // SUB_VG4_M4ZZ_S_PSEUDO |
| 11705 | 0U, // SUB_VG4_M4Z_D_PSEUDO |
| 11706 | 0U, // SUB_VG4_M4Z_S_PSEUDO |
| 11707 | 0U, // SUB_ZPZZ_B_ZERO |
| 11708 | 0U, // SUB_ZPZZ_D_ZERO |
| 11709 | 0U, // SUB_ZPZZ_H_ZERO |
| 11710 | 0U, // SUB_ZPZZ_S_ZERO |
| 11711 | 0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 11712 | 0U, // SUDOT_VG2_M2ZZ_BToS_PSEUDO |
| 11713 | 0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 11714 | 0U, // SUDOT_VG4_M4ZZ_BToS_PSEUDO |
| 11715 | 0U, // SUMLALL_MZZI_BtoS_PSEUDO |
| 11716 | 0U, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11717 | 0U, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11718 | 0U, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11719 | 0U, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11720 | 0U, // SUMOPA_MPPZZ_D_PSEUDO |
| 11721 | 0U, // SUMOPA_MPPZZ_S_PSEUDO |
| 11722 | 0U, // SUMOPS_MPPZZ_D_PSEUDO |
| 11723 | 0U, // SUMOPS_MPPZZ_S_PSEUDO |
| 11724 | 0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 11725 | 0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11726 | 0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 11727 | 0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 11728 | 0U, // SXTB_ZPmZ_D_UNDEF |
| 11729 | 0U, // SXTB_ZPmZ_H_UNDEF |
| 11730 | 0U, // SXTB_ZPmZ_S_UNDEF |
| 11731 | 0U, // SXTH_ZPmZ_D_UNDEF |
| 11732 | 0U, // SXTH_ZPmZ_S_UNDEF |
| 11733 | 0U, // SXTW_ZPmZ_D_UNDEF |
| 11734 | 0U, // SpeculationBarrierISBDSBEndBB |
| 11735 | 0U, // SpeculationBarrierSBEndBB |
| 11736 | 0U, // SpeculationSafeValueW |
| 11737 | 0U, // SpeculationSafeValueX |
| 11738 | 0U, // StoreSwiftAsyncContext |
| 11739 | 0U, // TAGPstack |
| 11740 | 0U, // TCRETURNdi |
| 11741 | 0U, // TCRETURNri |
| 11742 | 0U, // TCRETURNriALL |
| 11743 | 0U, // TCRETURNrinotx16 |
| 11744 | 0U, // TCRETURNrix16x17 |
| 11745 | 0U, // TCRETURNrix17 |
| 11746 | 0U, // TLSDESCCALL |
| 11747 | 0U, // TLSDESC_CALLSEQ |
| 11748 | 0U, // UABD_ZPZZ_B_UNDEF |
| 11749 | 0U, // UABD_ZPZZ_D_UNDEF |
| 11750 | 0U, // UABD_ZPZZ_H_UNDEF |
| 11751 | 0U, // UABD_ZPZZ_S_UNDEF |
| 11752 | 0U, // UCVTF_ZPmZ_DtoD_UNDEF |
| 11753 | 0U, // UCVTF_ZPmZ_DtoH_UNDEF |
| 11754 | 0U, // UCVTF_ZPmZ_DtoS_UNDEF |
| 11755 | 0U, // UCVTF_ZPmZ_HtoH_UNDEF |
| 11756 | 0U, // UCVTF_ZPmZ_StoD_UNDEF |
| 11757 | 0U, // UCVTF_ZPmZ_StoH_UNDEF |
| 11758 | 0U, // UCVTF_ZPmZ_StoS_UNDEF |
| 11759 | 0U, // UDIV_ZPZZ_D_UNDEF |
| 11760 | 0U, // UDIV_ZPZZ_S_UNDEF |
| 11761 | 0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 11762 | 0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 11763 | 0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 11764 | 0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 11765 | 0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 11766 | 0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 11767 | 0U, // UDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 11768 | 0U, // UDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 11769 | 0U, // UDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 11770 | 0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 11771 | 0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 11772 | 0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 11773 | 0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 11774 | 0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 11775 | 0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 11776 | 0U, // UDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 11777 | 0U, // UDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 11778 | 0U, // UDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 11779 | 0U, // UMAX_ZPZZ_B_UNDEF |
| 11780 | 0U, // UMAX_ZPZZ_D_UNDEF |
| 11781 | 0U, // UMAX_ZPZZ_H_UNDEF |
| 11782 | 0U, // UMAX_ZPZZ_S_UNDEF |
| 11783 | 0U, // UMIN_ZPZZ_B_UNDEF |
| 11784 | 0U, // UMIN_ZPZZ_D_UNDEF |
| 11785 | 0U, // UMIN_ZPZZ_H_UNDEF |
| 11786 | 0U, // UMIN_ZPZZ_S_UNDEF |
| 11787 | 0U, // UMLALL_MZZI_BtoS_PSEUDO |
| 11788 | 0U, // UMLALL_MZZI_HtoD_PSEUDO |
| 11789 | 0U, // UMLALL_MZZ_BtoS_PSEUDO |
| 11790 | 0U, // UMLALL_MZZ_HtoD_PSEUDO |
| 11791 | 0U, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11792 | 0U, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 11793 | 0U, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11794 | 0U, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 11795 | 0U, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11796 | 0U, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 11797 | 0U, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11798 | 0U, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 11799 | 0U, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11800 | 0U, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 11801 | 0U, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11802 | 0U, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 11803 | 0U, // UMLAL_MZZI_HtoS_PSEUDO |
| 11804 | 0U, // UMLAL_MZZ_HtoS_PSEUDO |
| 11805 | 0U, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11806 | 0U, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 11807 | 0U, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 11808 | 0U, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11809 | 0U, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 11810 | 0U, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 11811 | 0U, // UMLSLL_MZZI_BtoS_PSEUDO |
| 11812 | 0U, // UMLSLL_MZZI_HtoD_PSEUDO |
| 11813 | 0U, // UMLSLL_MZZ_BtoS_PSEUDO |
| 11814 | 0U, // UMLSLL_MZZ_HtoD_PSEUDO |
| 11815 | 0U, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11816 | 0U, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 11817 | 0U, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 11818 | 0U, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 11819 | 0U, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 11820 | 0U, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 11821 | 0U, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11822 | 0U, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 11823 | 0U, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 11824 | 0U, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 11825 | 0U, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 11826 | 0U, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 11827 | 0U, // UMLSL_MZZI_HtoS_PSEUDO |
| 11828 | 0U, // UMLSL_MZZ_HtoS_PSEUDO |
| 11829 | 0U, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11830 | 0U, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 11831 | 0U, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 11832 | 0U, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11833 | 0U, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 11834 | 0U, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 11835 | 0U, // UMOPA_MPPZZ_D_PSEUDO |
| 11836 | 0U, // UMOPA_MPPZZ_HtoS_PSEUDO |
| 11837 | 0U, // UMOPA_MPPZZ_S_PSEUDO |
| 11838 | 0U, // UMOPS_MPPZZ_D_PSEUDO |
| 11839 | 0U, // UMOPS_MPPZZ_HtoS_PSEUDO |
| 11840 | 0U, // UMOPS_MPPZZ_S_PSEUDO |
| 11841 | 0U, // UMULH_ZPZZ_B_UNDEF |
| 11842 | 0U, // UMULH_ZPZZ_D_UNDEF |
| 11843 | 0U, // UMULH_ZPZZ_H_UNDEF |
| 11844 | 0U, // UMULH_ZPZZ_S_UNDEF |
| 11845 | 0U, // UQRSHL_ZPZZ_B_UNDEF |
| 11846 | 0U, // UQRSHL_ZPZZ_D_UNDEF |
| 11847 | 0U, // UQRSHL_ZPZZ_H_UNDEF |
| 11848 | 0U, // UQRSHL_ZPZZ_S_UNDEF |
| 11849 | 0U, // UQSHL_ZPZI_B_ZERO |
| 11850 | 0U, // UQSHL_ZPZI_D_ZERO |
| 11851 | 0U, // UQSHL_ZPZI_H_ZERO |
| 11852 | 0U, // UQSHL_ZPZI_S_ZERO |
| 11853 | 0U, // UQSHL_ZPZZ_B_UNDEF |
| 11854 | 0U, // UQSHL_ZPZZ_D_UNDEF |
| 11855 | 0U, // UQSHL_ZPZZ_H_UNDEF |
| 11856 | 0U, // UQSHL_ZPZZ_S_UNDEF |
| 11857 | 0U, // URECPE_ZPmZ_S_UNDEF |
| 11858 | 0U, // URSHL_ZPZZ_B_UNDEF |
| 11859 | 0U, // URSHL_ZPZZ_D_UNDEF |
| 11860 | 0U, // URSHL_ZPZZ_H_UNDEF |
| 11861 | 0U, // URSHL_ZPZZ_S_UNDEF |
| 11862 | 0U, // URSHR_ZPZI_B_ZERO |
| 11863 | 0U, // URSHR_ZPZI_D_ZERO |
| 11864 | 0U, // URSHR_ZPZI_H_ZERO |
| 11865 | 0U, // URSHR_ZPZI_S_ZERO |
| 11866 | 0U, // URSQRTE_ZPmZ_S_UNDEF |
| 11867 | 0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 11868 | 0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 11869 | 0U, // USDOT_VG2_M2ZZ_BToS_PSEUDO |
| 11870 | 0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 11871 | 0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 11872 | 0U, // USDOT_VG4_M4ZZ_BToS_PSEUDO |
| 11873 | 0U, // USMLALL_MZZI_BtoS_PSEUDO |
| 11874 | 0U, // USMLALL_MZZ_BtoS_PSEUDO |
| 11875 | 0U, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11876 | 0U, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11877 | 0U, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11878 | 0U, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11879 | 0U, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11880 | 0U, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11881 | 0U, // USMOPA_MPPZZ_D_PSEUDO |
| 11882 | 0U, // USMOPA_MPPZZ_S_PSEUDO |
| 11883 | 0U, // USMOPS_MPPZZ_D_PSEUDO |
| 11884 | 0U, // USMOPS_MPPZZ_S_PSEUDO |
| 11885 | 0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 11886 | 0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11887 | 0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 11888 | 0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 11889 | 0U, // UXTB_ZPmZ_D_UNDEF |
| 11890 | 0U, // UXTB_ZPmZ_H_UNDEF |
| 11891 | 0U, // UXTB_ZPmZ_S_UNDEF |
| 11892 | 0U, // UXTH_ZPmZ_D_UNDEF |
| 11893 | 0U, // UXTH_ZPmZ_S_UNDEF |
| 11894 | 0U, // UXTW_ZPmZ_D_UNDEF |
| 11895 | 0U, // VGRestorePseudo |
| 11896 | 0U, // VGSavePseudo |
| 11897 | 0U, // ZERO_MXI_2Z_PSEUDO |
| 11898 | 0U, // ZERO_MXI_4Z_PSEUDO |
| 11899 | 0U, // ZERO_MXI_VG2_2Z_PSEUDO |
| 11900 | 0U, // ZERO_MXI_VG2_4Z_PSEUDO |
| 11901 | 0U, // ZERO_MXI_VG2_Z_PSEUDO |
| 11902 | 0U, // ZERO_MXI_VG4_2Z_PSEUDO |
| 11903 | 0U, // ZERO_MXI_VG4_4Z_PSEUDO |
| 11904 | 0U, // ZERO_MXI_VG4_Z_PSEUDO |
| 11905 | 0U, // ZERO_M_PSEUDO |
| 11906 | 0U, // ZERO_T_PSEUDO |
| 11907 | 0U, // ABSWr |
| 11908 | 0U, // ABSXr |
| 11909 | 16U, // ABS_ZPmZ_B |
| 11910 | 32U, // ABS_ZPmZ_D |
| 11911 | 0U, // ABS_ZPmZ_H |
| 11912 | 48U, // ABS_ZPmZ_S |
| 11913 | 0U, // ABSv16i8 |
| 11914 | 0U, // ABSv1i64 |
| 11915 | 0U, // ABSv2i32 |
| 11916 | 0U, // ABSv2i64 |
| 11917 | 0U, // ABSv4i16 |
| 11918 | 0U, // ABSv4i32 |
| 11919 | 0U, // ABSv8i16 |
| 11920 | 0U, // ABSv8i8 |
| 11921 | 2112U, // ADCLB_ZZZ_D |
| 11922 | 4160U, // ADCLB_ZZZ_S |
| 11923 | 2112U, // ADCLT_ZZZ_D |
| 11924 | 4160U, // ADCLT_ZZZ_S |
| 11925 | 6208U, // ADCSWr |
| 11926 | 6208U, // ADCSXr |
| 11927 | 6208U, // ADCWr |
| 11928 | 6208U, // ADCXr |
| 11929 | 270400U, // ADDG |
| 11930 | 0U, // ADDHA_MPPZ_D |
| 11931 | 0U, // ADDHA_MPPZ_S |
| 11932 | 10304U, // ADDHNB_ZZZ_B |
| 11933 | 81U, // ADDHNB_ZZZ_H |
| 11934 | 12353U, // ADDHNB_ZZZ_S |
| 11935 | 14401U, // ADDHNT_ZZZ_B |
| 11936 | 49U, // ADDHNT_ZZZ_H |
| 11937 | 2112U, // ADDHNT_ZZZ_S |
| 11938 | 16448U, // ADDHNv2i64_v2i32 |
| 11939 | 18497U, // ADDHNv2i64_v4i32 |
| 11940 | 16448U, // ADDHNv4i32_v4i16 |
| 11941 | 18497U, // ADDHNv4i32_v8i16 |
| 11942 | 18497U, // ADDHNv8i16_v16i8 |
| 11943 | 16448U, // ADDHNv8i16_v8i8 |
| 11944 | 6208U, // ADDPL_XXI |
| 11945 | 530496U, // ADDPT_shift |
| 11946 | 33837153U, // ADDP_ZPmZ_B |
| 11947 | 67383393U, // ADDP_ZPmZ_D |
| 11948 | 101472369U, // ADDP_ZPmZ_H |
| 11949 | 134504545U, // ADDP_ZPmZ_S |
| 11950 | 16448U, // ADDPv16i8 |
| 11951 | 16448U, // ADDPv2i32 |
| 11952 | 16448U, // ADDPv2i64 |
| 11953 | 0U, // ADDPv2i64p |
| 11954 | 16448U, // ADDPv4i16 |
| 11955 | 16448U, // ADDPv4i32 |
| 11956 | 16448U, // ADDPv8i16 |
| 11957 | 16448U, // ADDPv8i8 |
| 11958 | 20545U, // ADDQV_VPZ_B |
| 11959 | 12353U, // ADDQV_VPZ_D |
| 11960 | 10305U, // ADDQV_VPZ_H |
| 11961 | 24641U, // ADDQV_VPZ_S |
| 11962 | 6208U, // ADDSPL_XXI |
| 11963 | 6208U, // ADDSVL_XXI |
| 11964 | 26688U, // ADDSWri |
| 11965 | 28736U, // ADDSWrs |
| 11966 | 30784U, // ADDSWrx |
| 11967 | 26688U, // ADDSXri |
| 11968 | 28736U, // ADDSXrs |
| 11969 | 30784U, // ADDSXrx |
| 11970 | 1054784U, // ADDSXrx64 |
| 11971 | 0U, // ADDVA_MPPZ_D |
| 11972 | 0U, // ADDVA_MPPZ_S |
| 11973 | 6208U, // ADDVL_XXI |
| 11974 | 0U, // ADDVv16i8v |
| 11975 | 0U, // ADDVv4i16v |
| 11976 | 0U, // ADDVv4i32v |
| 11977 | 0U, // ADDVv8i16v |
| 11978 | 0U, // ADDVv8i8v |
| 11979 | 26688U, // ADDWri |
| 11980 | 28736U, // ADDWrs |
| 11981 | 30784U, // ADDWrx |
| 11982 | 26688U, // ADDXri |
| 11983 | 28736U, // ADDXrs |
| 11984 | 30784U, // ADDXrx |
| 11985 | 1054784U, // ADDXrx64 |
| 11986 | 129U, // ADD_VG2_2ZZ_B |
| 11987 | 145U, // ADD_VG2_2ZZ_D |
| 11988 | 113U, // ADD_VG2_2ZZ_H |
| 11989 | 81U, // ADD_VG2_2ZZ_S |
| 11990 | 1333409U, // ADD_VG2_M2Z2Z_D |
| 11991 | 1595569U, // ADD_VG2_M2Z2Z_S |
| 11992 | 102520993U, // ADD_VG2_M2ZZ_D |
| 11993 | 102783153U, // ADD_VG2_M2ZZ_S |
| 11994 | 161U, // ADD_VG2_M2Z_D |
| 11995 | 177U, // ADD_VG2_M2Z_S |
| 11996 | 129U, // ADD_VG4_4ZZ_B |
| 11997 | 145U, // ADD_VG4_4ZZ_D |
| 11998 | 113U, // ADD_VG4_4ZZ_H |
| 11999 | 81U, // ADD_VG4_4ZZ_S |
| 12000 | 1333409U, // ADD_VG4_M4Z4Z_D |
| 12001 | 1595569U, // ADD_VG4_M4Z4Z_S |
| 12002 | 102520993U, // ADD_VG4_M4ZZ_D |
| 12003 | 102783153U, // ADD_VG4_M4ZZ_S |
| 12004 | 161U, // ADD_VG4_M4Z_D |
| 12005 | 177U, // ADD_VG4_M4Z_S |
| 12006 | 32834U, // ADD_ZI_B |
| 12007 | 34881U, // ADD_ZI_D |
| 12008 | 193U, // ADD_ZI_H |
| 12009 | 36930U, // ADD_ZI_S |
| 12010 | 33837153U, // ADD_ZPmZ_B |
| 12011 | 67383393U, // ADD_ZPmZ_CPA |
| 12012 | 67383393U, // ADD_ZPmZ_D |
| 12013 | 101472369U, // ADD_ZPmZ_H |
| 12014 | 134504545U, // ADD_ZPmZ_S |
| 12015 | 20546U, // ADD_ZZZ_B |
| 12016 | 12353U, // ADD_ZZZ_CPA |
| 12017 | 12353U, // ADD_ZZZ_D |
| 12018 | 113U, // ADD_ZZZ_H |
| 12019 | 24642U, // ADD_ZZZ_S |
| 12020 | 16448U, // ADDv16i8 |
| 12021 | 6208U, // ADDv1i64 |
| 12022 | 16448U, // ADDv2i32 |
| 12023 | 16448U, // ADDv2i64 |
| 12024 | 16448U, // ADDv4i16 |
| 12025 | 16448U, // ADDv4i32 |
| 12026 | 16448U, // ADDv8i16 |
| 12027 | 16448U, // ADDv8i8 |
| 12028 | 2U, // ADR |
| 12029 | 2U, // ADRP |
| 12030 | 38977U, // ADR_LSL_ZZZ_D_0 |
| 12031 | 41025U, // ADR_LSL_ZZZ_D_1 |
| 12032 | 43073U, // ADR_LSL_ZZZ_D_2 |
| 12033 | 45121U, // ADR_LSL_ZZZ_D_3 |
| 12034 | 47170U, // ADR_LSL_ZZZ_S_0 |
| 12035 | 49218U, // ADR_LSL_ZZZ_S_1 |
| 12036 | 51266U, // ADR_LSL_ZZZ_S_2 |
| 12037 | 53314U, // ADR_LSL_ZZZ_S_3 |
| 12038 | 55361U, // ADR_SXTW_ZZZ_D_0 |
| 12039 | 57409U, // ADR_SXTW_ZZZ_D_1 |
| 12040 | 59457U, // ADR_SXTW_ZZZ_D_2 |
| 12041 | 61505U, // ADR_SXTW_ZZZ_D_3 |
| 12042 | 63553U, // ADR_UXTW_ZZZ_D_0 |
| 12043 | 65601U, // ADR_UXTW_ZZZ_D_1 |
| 12044 | 67649U, // ADR_UXTW_ZZZ_D_2 |
| 12045 | 69697U, // ADR_UXTW_ZZZ_D_3 |
| 12046 | 20546U, // AESD_ZZZ_B |
| 12047 | 1U, // AESDrr |
| 12048 | 20546U, // AESE_ZZZ_B |
| 12049 | 1U, // AESErr |
| 12050 | 2U, // AESIMC_ZZ_B |
| 12051 | 0U, // AESIMCrr |
| 12052 | 2U, // AESMC_ZZ_B |
| 12053 | 0U, // AESMCrr |
| 12054 | 20545U, // ANDQV_VPZ_B |
| 12055 | 12353U, // ANDQV_VPZ_D |
| 12056 | 10305U, // ANDQV_VPZ_H |
| 12057 | 24641U, // ANDQV_VPZ_S |
| 12058 | 71744U, // ANDSWri |
| 12059 | 28736U, // ANDSWrs |
| 12060 | 73792U, // ANDSXri |
| 12061 | 28736U, // ANDSXrs |
| 12062 | 33837265U, // ANDS_PPzPP |
| 12063 | 0U, // ANDV_VPZ_B |
| 12064 | 0U, // ANDV_VPZ_D |
| 12065 | 0U, // ANDV_VPZ_H |
| 12066 | 0U, // ANDV_VPZ_S |
| 12067 | 71744U, // ANDWri |
| 12068 | 28736U, // ANDWrs |
| 12069 | 73792U, // ANDXri |
| 12070 | 28736U, // ANDXrs |
| 12071 | 33837265U, // AND_PPzPP |
| 12072 | 73793U, // AND_ZI |
| 12073 | 33837153U, // AND_ZPmZ_B |
| 12074 | 67383393U, // AND_ZPmZ_D |
| 12075 | 101472369U, // AND_ZPmZ_H |
| 12076 | 134504545U, // AND_ZPmZ_S |
| 12077 | 12353U, // AND_ZZZ |
| 12078 | 16448U, // ANDv16i8 |
| 12079 | 16448U, // ANDv8i8 |
| 12080 | 282721U, // ASRD_ZPmI_B |
| 12081 | 274529U, // ASRD_ZPmI_D |
| 12082 | 103045233U, // ASRD_ZPmI_H |
| 12083 | 286817U, // ASRD_ZPmI_S |
| 12084 | 33837153U, // ASRR_ZPmZ_B |
| 12085 | 67383393U, // ASRR_ZPmZ_D |
| 12086 | 101472369U, // ASRR_ZPmZ_H |
| 12087 | 134504545U, // ASRR_ZPmZ_S |
| 12088 | 6208U, // ASRVWr |
| 12089 | 6208U, // ASRVXr |
| 12090 | 67391585U, // ASR_WIDE_ZPmZ_B |
| 12091 | 2644081U, // ASR_WIDE_ZPmZ_H |
| 12092 | 67395681U, // ASR_WIDE_ZPmZ_S |
| 12093 | 12354U, // ASR_WIDE_ZZZ_B |
| 12094 | 145U, // ASR_WIDE_ZZZ_H |
| 12095 | 12354U, // ASR_WIDE_ZZZ_S |
| 12096 | 282721U, // ASR_ZPmI_B |
| 12097 | 274529U, // ASR_ZPmI_D |
| 12098 | 103045233U, // ASR_ZPmI_H |
| 12099 | 286817U, // ASR_ZPmI_S |
| 12100 | 33837153U, // ASR_ZPmZ_B |
| 12101 | 67383393U, // ASR_ZPmZ_D |
| 12102 | 101472369U, // ASR_ZPmZ_H |
| 12103 | 134504545U, // ASR_ZPmZ_S |
| 12104 | 6210U, // ASR_ZZI_B |
| 12105 | 6209U, // ASR_ZZI_D |
| 12106 | 225U, // ASR_ZZI_H |
| 12107 | 6210U, // ASR_ZZI_S |
| 12108 | 2U, // AUTDA |
| 12109 | 2U, // AUTDB |
| 12110 | 0U, // AUTDZA |
| 12111 | 0U, // AUTDZB |
| 12112 | 2U, // AUTIA |
| 12113 | 0U, // AUTIA1716 |
| 12114 | 0U, // AUTIA171615 |
| 12115 | 0U, // AUTIASP |
| 12116 | 0U, // AUTIASPPCi |
| 12117 | 0U, // AUTIASPPCr |
| 12118 | 0U, // AUTIAZ |
| 12119 | 2U, // AUTIB |
| 12120 | 0U, // AUTIB1716 |
| 12121 | 0U, // AUTIB171615 |
| 12122 | 0U, // AUTIBSP |
| 12123 | 0U, // AUTIBSPPCi |
| 12124 | 0U, // AUTIBSPPCr |
| 12125 | 0U, // AUTIBZ |
| 12126 | 0U, // AUTIZA |
| 12127 | 0U, // AUTIZB |
| 12128 | 0U, // AXFLAG |
| 12129 | 0U, // B |
| 12130 | 168050752U, // BCAX |
| 12131 | 67383361U, // BCAX_ZZZZ |
| 12132 | 0U, // BCcc |
| 12133 | 20546U, // BDEP_ZZZ_B |
| 12134 | 12353U, // BDEP_ZZZ_D |
| 12135 | 113U, // BDEP_ZZZ_H |
| 12136 | 24642U, // BDEP_ZZZ_S |
| 12137 | 20546U, // BEXT_ZZZ_B |
| 12138 | 12353U, // BEXT_ZZZ_D |
| 12139 | 113U, // BEXT_ZZZ_H |
| 12140 | 24642U, // BEXT_ZZZ_S |
| 12141 | 103565377U, // BF16DOTlanev4bf16 |
| 12142 | 103565377U, // BF16DOTlanev8bf16 |
| 12143 | 0U, // BF1CVTL2v8f16 |
| 12144 | 0U, // BF1CVTLT_ZZ_BtoH |
| 12145 | 0U, // BF1CVTL_2ZZ_BtoH_NAME |
| 12146 | 0U, // BF1CVTLv8f16 |
| 12147 | 0U, // BF1CVT_2ZZ_BtoH_NAME |
| 12148 | 0U, // BF1CVT_ZZ_BtoH |
| 12149 | 0U, // BF2CVTL2v8f16 |
| 12150 | 0U, // BF2CVTLT_ZZ_BtoH |
| 12151 | 0U, // BF2CVTL_2ZZ_BtoH_NAME |
| 12152 | 0U, // BF2CVTLv8f16 |
| 12153 | 0U, // BF2CVT_2ZZ_BtoH_NAME |
| 12154 | 0U, // BF2CVT_ZZ_BtoH |
| 12155 | 241U, // BFADD_VG2_M2Z_H |
| 12156 | 241U, // BFADD_VG4_M4Z_H |
| 12157 | 101472369U, // BFADD_ZPmZZ |
| 12158 | 113U, // BFADD_ZZZ |
| 12159 | 257U, // BFCLAMP_VG2_2ZZZ_H |
| 12160 | 257U, // BFCLAMP_VG4_4ZZZ_H |
| 12161 | 257U, // BFCLAMP_ZZZ |
| 12162 | 0U, // BFCVT |
| 12163 | 0U, // BFCVTN |
| 12164 | 1U, // BFCVTN2 |
| 12165 | 2U, // BFCVTNT_ZPmZ |
| 12166 | 2U, // BFCVTN_Z2Z_HtoB |
| 12167 | 0U, // BFCVTN_Z2Z_StoH |
| 12168 | 2U, // BFCVT_Z2Z_HtoB |
| 12169 | 0U, // BFCVT_Z2Z_StoH |
| 12170 | 2U, // BFCVT_ZPmZ |
| 12171 | 3168497U, // BFDOT_VG2_M2Z2Z_HtoS |
| 12172 | 204757233U, // BFDOT_VG2_M2ZZI_HtoS |
| 12173 | 104093937U, // BFDOT_VG2_M2ZZ_HtoS |
| 12174 | 3168497U, // BFDOT_VG4_M4Z4Z_HtoS |
| 12175 | 204757233U, // BFDOT_VG4_M4ZZI_HtoS |
| 12176 | 104093937U, // BFDOT_VG4_M4ZZ_HtoS |
| 12177 | 103561281U, // BFDOT_ZZI |
| 12178 | 14401U, // BFDOT_ZZZ |
| 12179 | 0U, // BFDOTv4bf16 |
| 12180 | 0U, // BFDOTv8bf16 |
| 12181 | 273U, // BFMAXNM_VG2_2Z2Z_H |
| 12182 | 113U, // BFMAXNM_VG2_2ZZ_H |
| 12183 | 273U, // BFMAXNM_VG4_4Z2Z_H |
| 12184 | 113U, // BFMAXNM_VG4_4ZZ_H |
| 12185 | 101472369U, // BFMAXNM_ZPmZZ |
| 12186 | 273U, // BFMAX_VG2_2Z2Z_H |
| 12187 | 113U, // BFMAX_VG2_2ZZ_H |
| 12188 | 273U, // BFMAX_VG4_4Z2Z_H |
| 12189 | 113U, // BFMAX_VG4_4ZZ_H |
| 12190 | 101472369U, // BFMAX_ZPmZZ |
| 12191 | 273U, // BFMINNM_VG2_2Z2Z_H |
| 12192 | 113U, // BFMINNM_VG2_2ZZ_H |
| 12193 | 273U, // BFMINNM_VG4_4Z2Z_H |
| 12194 | 113U, // BFMINNM_VG4_4ZZ_H |
| 12195 | 101472369U, // BFMINNM_ZPmZZ |
| 12196 | 273U, // BFMIN_VG2_2Z2Z_H |
| 12197 | 113U, // BFMIN_VG2_2ZZ_H |
| 12198 | 273U, // BFMIN_VG4_4Z2Z_H |
| 12199 | 113U, // BFMIN_VG4_4ZZ_H |
| 12200 | 101472369U, // BFMIN_ZPmZZ |
| 12201 | 0U, // BFMLALB |
| 12202 | 0U, // BFMLALBIdx |
| 12203 | 14401U, // BFMLALB_ZZZ |
| 12204 | 103561281U, // BFMLALB_ZZZI |
| 12205 | 0U, // BFMLALT |
| 12206 | 0U, // BFMLALTIdx |
| 12207 | 14401U, // BFMLALT_ZZZ |
| 12208 | 103561281U, // BFMLALT_ZZZI |
| 12209 | 76066U, // BFMLAL_MZZI_HtoS |
| 12210 | 290U, // BFMLAL_MZZ_HtoS |
| 12211 | 3168497U, // BFMLAL_VG2_M2Z2Z_HtoS |
| 12212 | 204757233U, // BFMLAL_VG2_M2ZZI_HtoS |
| 12213 | 104093937U, // BFMLAL_VG2_M2ZZ_HtoS |
| 12214 | 3168497U, // BFMLAL_VG4_M4Z4Z_HtoS |
| 12215 | 204757233U, // BFMLAL_VG4_M4ZZI_HtoS |
| 12216 | 104093937U, // BFMLAL_VG4_M4ZZ_HtoS |
| 12217 | 3168497U, // BFMLA_VG2_M2Z2Z |
| 12218 | 104093937U, // BFMLA_VG2_M2ZZ |
| 12219 | 204757233U, // BFMLA_VG2_M2ZZI |
| 12220 | 3168497U, // BFMLA_VG4_M4Z4Z |
| 12221 | 104093937U, // BFMLA_VG4_M4ZZ |
| 12222 | 204757233U, // BFMLA_VG4_M4ZZI |
| 12223 | 104356097U, // BFMLA_ZPmZZ |
| 12224 | 78081U, // BFMLA_ZZZI |
| 12225 | 103561281U, // BFMLSLB_ZZZI_S |
| 12226 | 14401U, // BFMLSLB_ZZZ_S |
| 12227 | 103561281U, // BFMLSLT_ZZZI_S |
| 12228 | 14401U, // BFMLSLT_ZZZ_S |
| 12229 | 76066U, // BFMLSL_MZZI_HtoS |
| 12230 | 290U, // BFMLSL_MZZ_HtoS |
| 12231 | 3168497U, // BFMLSL_VG2_M2Z2Z_HtoS |
| 12232 | 204757233U, // BFMLSL_VG2_M2ZZI_HtoS |
| 12233 | 104093937U, // BFMLSL_VG2_M2ZZ_HtoS |
| 12234 | 3168497U, // BFMLSL_VG4_M4Z4Z_HtoS |
| 12235 | 204757233U, // BFMLSL_VG4_M4ZZI_HtoS |
| 12236 | 104093937U, // BFMLSL_VG4_M4ZZ_HtoS |
| 12237 | 3168497U, // BFMLS_VG2_M2Z2Z |
| 12238 | 104093937U, // BFMLS_VG2_M2ZZ |
| 12239 | 204757233U, // BFMLS_VG2_M2ZZI |
| 12240 | 3168497U, // BFMLS_VG4_M4Z4Z |
| 12241 | 104093937U, // BFMLS_VG4_M4ZZ |
| 12242 | 204757233U, // BFMLS_VG4_M4ZZI |
| 12243 | 104356097U, // BFMLS_ZPmZZ |
| 12244 | 78081U, // BFMLS_ZZZI |
| 12245 | 0U, // BFMMLA |
| 12246 | 14401U, // BFMMLA_ZZZ |
| 12247 | 0U, // BFMOPA_MPPZZ |
| 12248 | 0U, // BFMOPA_MPPZZ_H |
| 12249 | 0U, // BFMOPS_MPPZZ |
| 12250 | 0U, // BFMOPS_MPPZZ_H |
| 12251 | 101472369U, // BFMUL_ZPmZZ |
| 12252 | 113U, // BFMUL_ZZZ |
| 12253 | 79985U, // BFMUL_ZZZI |
| 12254 | 235225154U, // BFMWri |
| 12255 | 235225154U, // BFMXri |
| 12256 | 241U, // BFSUB_VG2_M2Z_H |
| 12257 | 241U, // BFSUB_VG4_M4Z_H |
| 12258 | 101472369U, // BFSUB_ZPmZZ |
| 12259 | 113U, // BFSUB_ZZZ |
| 12260 | 204757233U, // BFVDOT_VG2_M2ZZI_HtoS |
| 12261 | 20546U, // BGRP_ZZZ_B |
| 12262 | 12353U, // BGRP_ZZZ_D |
| 12263 | 113U, // BGRP_ZZZ_H |
| 12264 | 24642U, // BGRP_ZZZ_S |
| 12265 | 28736U, // BICSWrs |
| 12266 | 28736U, // BICSXrs |
| 12267 | 33837265U, // BICS_PPzPP |
| 12268 | 28736U, // BICWrs |
| 12269 | 28736U, // BICXrs |
| 12270 | 33837265U, // BIC_PPzPP |
| 12271 | 33837153U, // BIC_ZPmZ_B |
| 12272 | 67383393U, // BIC_ZPmZ_D |
| 12273 | 101472369U, // BIC_ZPmZ_H |
| 12274 | 134504545U, // BIC_ZPmZ_S |
| 12275 | 12353U, // BIC_ZZZ |
| 12276 | 16448U, // BICv16i8 |
| 12277 | 2U, // BICv2i32 |
| 12278 | 2U, // BICv4i16 |
| 12279 | 2U, // BICv4i32 |
| 12280 | 2U, // BICv8i16 |
| 12281 | 16448U, // BICv8i8 |
| 12282 | 18497U, // BIFv16i8 |
| 12283 | 18497U, // BIFv8i8 |
| 12284 | 18497U, // BITv16i8 |
| 12285 | 18497U, // BITv8i8 |
| 12286 | 0U, // BL |
| 12287 | 0U, // BLR |
| 12288 | 0U, // BLRAA |
| 12289 | 0U, // BLRAAZ |
| 12290 | 0U, // BLRAB |
| 12291 | 0U, // BLRABZ |
| 12292 | 305U, // BMOPA_MPPZZ_S |
| 12293 | 305U, // BMOPS_MPPZZ_S |
| 12294 | 0U, // BR |
| 12295 | 0U, // BRAA |
| 12296 | 0U, // BRAAZ |
| 12297 | 0U, // BRAB |
| 12298 | 0U, // BRABZ |
| 12299 | 0U, // BRB_IALL |
| 12300 | 0U, // BRB_INJ |
| 12301 | 0U, // BRK |
| 12302 | 20689U, // BRKAS_PPzP |
| 12303 | 16U, // BRKA_PPmP |
| 12304 | 20689U, // BRKA_PPzP |
| 12305 | 20689U, // BRKBS_PPzP |
| 12306 | 16U, // BRKB_PPmP |
| 12307 | 20689U, // BRKB_PPzP |
| 12308 | 33837265U, // BRKNS_PPzP |
| 12309 | 33837265U, // BRKN_PPzP |
| 12310 | 33837265U, // BRKPAS_PPzPP |
| 12311 | 33837265U, // BRKPA_PPzPP |
| 12312 | 33837265U, // BRKPBS_PPzPP |
| 12313 | 33837265U, // BRKPB_PPzPP |
| 12314 | 67383361U, // BSL1N_ZZZZ |
| 12315 | 67383361U, // BSL2N_ZZZZ |
| 12316 | 67383361U, // BSL_ZZZZ |
| 12317 | 18497U, // BSLv16i8 |
| 12318 | 18497U, // BSLv8i8 |
| 12319 | 0U, // Bcc |
| 12320 | 268718146U, // CADD_ZZI_B |
| 12321 | 268709953U, // CADD_ZZI_D |
| 12322 | 3954801U, // CADD_ZZI_H |
| 12323 | 268722242U, // CADD_ZZI_S |
| 12324 | 4276546U, // CASAB |
| 12325 | 4276546U, // CASAH |
| 12326 | 4276546U, // CASALB |
| 12327 | 4276546U, // CASALH |
| 12328 | 4276546U, // CASALW |
| 12329 | 4276546U, // CASALX |
| 12330 | 4276546U, // CASAW |
| 12331 | 4276546U, // CASAX |
| 12332 | 4276546U, // CASB |
| 12333 | 4276546U, // CASH |
| 12334 | 4276546U, // CASLB |
| 12335 | 4276546U, // CASLH |
| 12336 | 4276546U, // CASLW |
| 12337 | 4276546U, // CASLX |
| 12338 | 0U, // CASPALW |
| 12339 | 0U, // CASPALX |
| 12340 | 0U, // CASPAW |
| 12341 | 0U, // CASPAX |
| 12342 | 0U, // CASPLW |
| 12343 | 0U, // CASPLX |
| 12344 | 0U, // CASPW |
| 12345 | 0U, // CASPX |
| 12346 | 4276546U, // CASW |
| 12347 | 4276546U, // CASX |
| 12348 | 3U, // CBNZW |
| 12349 | 3U, // CBNZX |
| 12350 | 3U, // CBZW |
| 12351 | 3U, // CBZX |
| 12352 | 302258240U, // CCMNWi |
| 12353 | 302258240U, // CCMNWr |
| 12354 | 302258240U, // CCMNXi |
| 12355 | 302258240U, // CCMNXr |
| 12356 | 302258240U, // CCMPWi |
| 12357 | 302258240U, // CCMPWr |
| 12358 | 302258240U, // CCMPXi |
| 12359 | 302258240U, // CCMPXr |
| 12360 | 338442305U, // CDOT_ZZZI_D |
| 12361 | 369438739U, // CDOT_ZZZI_S |
| 12362 | 402929729U, // CDOT_ZZZ_D |
| 12363 | 4478995U, // CDOT_ZZZ_S |
| 12364 | 0U, // CFINV |
| 12365 | 0U, // CHKFEAT |
| 12366 | 33822785U, // CLASTA_RPZ_B |
| 12367 | 67377217U, // CLASTA_RPZ_D |
| 12368 | 436475969U, // CLASTA_RPZ_H |
| 12369 | 134486081U, // CLASTA_RPZ_S |
| 12370 | 33822785U, // CLASTA_VPZ_B |
| 12371 | 67377217U, // CLASTA_VPZ_D |
| 12372 | 436475969U, // CLASTA_VPZ_H |
| 12373 | 134486081U, // CLASTA_VPZ_S |
| 12374 | 33837121U, // CLASTA_ZPZ_B |
| 12375 | 67383361U, // CLASTA_ZPZ_D |
| 12376 | 101472369U, // CLASTA_ZPZ_H |
| 12377 | 134504513U, // CLASTA_ZPZ_S |
| 12378 | 33822785U, // CLASTB_RPZ_B |
| 12379 | 67377217U, // CLASTB_RPZ_D |
| 12380 | 436475969U, // CLASTB_RPZ_H |
| 12381 | 134486081U, // CLASTB_RPZ_S |
| 12382 | 33822785U, // CLASTB_VPZ_B |
| 12383 | 67377217U, // CLASTB_VPZ_D |
| 12384 | 436475969U, // CLASTB_VPZ_H |
| 12385 | 134486081U, // CLASTB_VPZ_S |
| 12386 | 33837121U, // CLASTB_ZPZ_B |
| 12387 | 67383361U, // CLASTB_ZPZ_D |
| 12388 | 101472369U, // CLASTB_ZPZ_H |
| 12389 | 134504513U, // CLASTB_ZPZ_S |
| 12390 | 0U, // CLREX |
| 12391 | 0U, // CLSWr |
| 12392 | 0U, // CLSXr |
| 12393 | 16U, // CLS_ZPmZ_B |
| 12394 | 32U, // CLS_ZPmZ_D |
| 12395 | 0U, // CLS_ZPmZ_H |
| 12396 | 48U, // CLS_ZPmZ_S |
| 12397 | 0U, // CLSv16i8 |
| 12398 | 0U, // CLSv2i32 |
| 12399 | 0U, // CLSv4i16 |
| 12400 | 0U, // CLSv4i32 |
| 12401 | 0U, // CLSv8i16 |
| 12402 | 0U, // CLSv8i8 |
| 12403 | 0U, // CLZWr |
| 12404 | 0U, // CLZXr |
| 12405 | 16U, // CLZ_ZPmZ_B |
| 12406 | 32U, // CLZ_ZPmZ_D |
| 12407 | 0U, // CLZ_ZPmZ_H |
| 12408 | 48U, // CLZ_ZPmZ_S |
| 12409 | 0U, // CLZv16i8 |
| 12410 | 0U, // CLZv2i32 |
| 12411 | 0U, // CLZv4i16 |
| 12412 | 0U, // CLZv4i32 |
| 12413 | 0U, // CLZv8i16 |
| 12414 | 0U, // CLZv8i8 |
| 12415 | 16448U, // CMEQv16i8 |
| 12416 | 336U, // CMEQv16i8rz |
| 12417 | 6208U, // CMEQv1i64 |
| 12418 | 336U, // CMEQv1i64rz |
| 12419 | 16448U, // CMEQv2i32 |
| 12420 | 336U, // CMEQv2i32rz |
| 12421 | 16448U, // CMEQv2i64 |
| 12422 | 336U, // CMEQv2i64rz |
| 12423 | 16448U, // CMEQv4i16 |
| 12424 | 336U, // CMEQv4i16rz |
| 12425 | 16448U, // CMEQv4i32 |
| 12426 | 336U, // CMEQv4i32rz |
| 12427 | 16448U, // CMEQv8i16 |
| 12428 | 336U, // CMEQv8i16rz |
| 12429 | 16448U, // CMEQv8i8 |
| 12430 | 336U, // CMEQv8i8rz |
| 12431 | 16448U, // CMGEv16i8 |
| 12432 | 336U, // CMGEv16i8rz |
| 12433 | 6208U, // CMGEv1i64 |
| 12434 | 336U, // CMGEv1i64rz |
| 12435 | 16448U, // CMGEv2i32 |
| 12436 | 336U, // CMGEv2i32rz |
| 12437 | 16448U, // CMGEv2i64 |
| 12438 | 336U, // CMGEv2i64rz |
| 12439 | 16448U, // CMGEv4i16 |
| 12440 | 336U, // CMGEv4i16rz |
| 12441 | 16448U, // CMGEv4i32 |
| 12442 | 336U, // CMGEv4i32rz |
| 12443 | 16448U, // CMGEv8i16 |
| 12444 | 336U, // CMGEv8i16rz |
| 12445 | 16448U, // CMGEv8i8 |
| 12446 | 336U, // CMGEv8i8rz |
| 12447 | 16448U, // CMGTv16i8 |
| 12448 | 336U, // CMGTv16i8rz |
| 12449 | 6208U, // CMGTv1i64 |
| 12450 | 336U, // CMGTv1i64rz |
| 12451 | 16448U, // CMGTv2i32 |
| 12452 | 336U, // CMGTv2i32rz |
| 12453 | 16448U, // CMGTv2i64 |
| 12454 | 336U, // CMGTv2i64rz |
| 12455 | 16448U, // CMGTv4i16 |
| 12456 | 336U, // CMGTv4i16rz |
| 12457 | 16448U, // CMGTv4i32 |
| 12458 | 336U, // CMGTv4i32rz |
| 12459 | 16448U, // CMGTv8i16 |
| 12460 | 336U, // CMGTv8i16rz |
| 12461 | 16448U, // CMGTv8i8 |
| 12462 | 336U, // CMGTv8i8rz |
| 12463 | 16448U, // CMHIv16i8 |
| 12464 | 6208U, // CMHIv1i64 |
| 12465 | 16448U, // CMHIv2i32 |
| 12466 | 16448U, // CMHIv2i64 |
| 12467 | 16448U, // CMHIv4i16 |
| 12468 | 16448U, // CMHIv4i32 |
| 12469 | 16448U, // CMHIv8i16 |
| 12470 | 16448U, // CMHIv8i8 |
| 12471 | 16448U, // CMHSv16i8 |
| 12472 | 6208U, // CMHSv1i64 |
| 12473 | 16448U, // CMHSv2i32 |
| 12474 | 16448U, // CMHSv2i64 |
| 12475 | 16448U, // CMHSv4i16 |
| 12476 | 16448U, // CMHSv4i32 |
| 12477 | 16448U, // CMHSv8i16 |
| 12478 | 16448U, // CMHSv8i8 |
| 12479 | 369438977U, // CMLA_ZZZI_H |
| 12480 | 338432064U, // CMLA_ZZZI_S |
| 12481 | 4478995U, // CMLA_ZZZ_B |
| 12482 | 402917440U, // CMLA_ZZZ_D |
| 12483 | 4479233U, // CMLA_ZZZ_H |
| 12484 | 402919488U, // CMLA_ZZZ_S |
| 12485 | 336U, // CMLEv16i8rz |
| 12486 | 336U, // CMLEv1i64rz |
| 12487 | 336U, // CMLEv2i32rz |
| 12488 | 336U, // CMLEv2i64rz |
| 12489 | 336U, // CMLEv4i16rz |
| 12490 | 336U, // CMLEv4i32rz |
| 12491 | 336U, // CMLEv8i16rz |
| 12492 | 336U, // CMLEv8i8rz |
| 12493 | 336U, // CMLTv16i8rz |
| 12494 | 336U, // CMLTv1i64rz |
| 12495 | 336U, // CMLTv2i32rz |
| 12496 | 336U, // CMLTv2i64rz |
| 12497 | 336U, // CMLTv4i16rz |
| 12498 | 336U, // CMLTv4i32rz |
| 12499 | 336U, // CMLTv8i16rz |
| 12500 | 336U, // CMLTv8i8rz |
| 12501 | 282833U, // CMPEQ_PPzZI_B |
| 12502 | 274641U, // CMPEQ_PPzZI_D |
| 12503 | 103045235U, // CMPEQ_PPzZI_H |
| 12504 | 286929U, // CMPEQ_PPzZI_S |
| 12505 | 33837265U, // CMPEQ_PPzZZ_B |
| 12506 | 67383505U, // CMPEQ_PPzZZ_D |
| 12507 | 101472371U, // CMPEQ_PPzZZ_H |
| 12508 | 134504657U, // CMPEQ_PPzZZ_S |
| 12509 | 67391697U, // CMPEQ_WIDE_PPzZZ_B |
| 12510 | 2644083U, // CMPEQ_WIDE_PPzZZ_H |
| 12511 | 67395793U, // CMPEQ_WIDE_PPzZZ_S |
| 12512 | 282833U, // CMPGE_PPzZI_B |
| 12513 | 274641U, // CMPGE_PPzZI_D |
| 12514 | 103045235U, // CMPGE_PPzZI_H |
| 12515 | 286929U, // CMPGE_PPzZI_S |
| 12516 | 33837265U, // CMPGE_PPzZZ_B |
| 12517 | 67383505U, // CMPGE_PPzZZ_D |
| 12518 | 101472371U, // CMPGE_PPzZZ_H |
| 12519 | 134504657U, // CMPGE_PPzZZ_S |
| 12520 | 67391697U, // CMPGE_WIDE_PPzZZ_B |
| 12521 | 2644083U, // CMPGE_WIDE_PPzZZ_H |
| 12522 | 67395793U, // CMPGE_WIDE_PPzZZ_S |
| 12523 | 282833U, // CMPGT_PPzZI_B |
| 12524 | 274641U, // CMPGT_PPzZI_D |
| 12525 | 103045235U, // CMPGT_PPzZI_H |
| 12526 | 286929U, // CMPGT_PPzZI_S |
| 12527 | 33837265U, // CMPGT_PPzZZ_B |
| 12528 | 67383505U, // CMPGT_PPzZZ_D |
| 12529 | 101472371U, // CMPGT_PPzZZ_H |
| 12530 | 134504657U, // CMPGT_PPzZZ_S |
| 12531 | 67391697U, // CMPGT_WIDE_PPzZZ_B |
| 12532 | 2644083U, // CMPGT_WIDE_PPzZZ_H |
| 12533 | 67395793U, // CMPGT_WIDE_PPzZZ_S |
| 12534 | 470044881U, // CMPHI_PPzZI_B |
| 12535 | 470036689U, // CMPHI_PPzZI_D |
| 12536 | 4741235U, // CMPHI_PPzZI_H |
| 12537 | 470048977U, // CMPHI_PPzZI_S |
| 12538 | 33837265U, // CMPHI_PPzZZ_B |
| 12539 | 67383505U, // CMPHI_PPzZZ_D |
| 12540 | 101472371U, // CMPHI_PPzZZ_H |
| 12541 | 134504657U, // CMPHI_PPzZZ_S |
| 12542 | 67391697U, // CMPHI_WIDE_PPzZZ_B |
| 12543 | 2644083U, // CMPHI_WIDE_PPzZZ_H |
| 12544 | 67395793U, // CMPHI_WIDE_PPzZZ_S |
| 12545 | 470044881U, // CMPHS_PPzZI_B |
| 12546 | 470036689U, // CMPHS_PPzZI_D |
| 12547 | 4741235U, // CMPHS_PPzZI_H |
| 12548 | 470048977U, // CMPHS_PPzZI_S |
| 12549 | 33837265U, // CMPHS_PPzZZ_B |
| 12550 | 67383505U, // CMPHS_PPzZZ_D |
| 12551 | 101472371U, // CMPHS_PPzZZ_H |
| 12552 | 134504657U, // CMPHS_PPzZZ_S |
| 12553 | 67391697U, // CMPHS_WIDE_PPzZZ_B |
| 12554 | 2644083U, // CMPHS_WIDE_PPzZZ_H |
| 12555 | 67395793U, // CMPHS_WIDE_PPzZZ_S |
| 12556 | 282833U, // CMPLE_PPzZI_B |
| 12557 | 274641U, // CMPLE_PPzZI_D |
| 12558 | 103045235U, // CMPLE_PPzZI_H |
| 12559 | 286929U, // CMPLE_PPzZI_S |
| 12560 | 67391697U, // CMPLE_WIDE_PPzZZ_B |
| 12561 | 2644083U, // CMPLE_WIDE_PPzZZ_H |
| 12562 | 67395793U, // CMPLE_WIDE_PPzZZ_S |
| 12563 | 470044881U, // CMPLO_PPzZI_B |
| 12564 | 470036689U, // CMPLO_PPzZI_D |
| 12565 | 4741235U, // CMPLO_PPzZI_H |
| 12566 | 470048977U, // CMPLO_PPzZI_S |
| 12567 | 67391697U, // CMPLO_WIDE_PPzZZ_B |
| 12568 | 2644083U, // CMPLO_WIDE_PPzZZ_H |
| 12569 | 67395793U, // CMPLO_WIDE_PPzZZ_S |
| 12570 | 470044881U, // CMPLS_PPzZI_B |
| 12571 | 470036689U, // CMPLS_PPzZI_D |
| 12572 | 4741235U, // CMPLS_PPzZI_H |
| 12573 | 470048977U, // CMPLS_PPzZI_S |
| 12574 | 67391697U, // CMPLS_WIDE_PPzZZ_B |
| 12575 | 2644083U, // CMPLS_WIDE_PPzZZ_H |
| 12576 | 67395793U, // CMPLS_WIDE_PPzZZ_S |
| 12577 | 282833U, // CMPLT_PPzZI_B |
| 12578 | 274641U, // CMPLT_PPzZI_D |
| 12579 | 103045235U, // CMPLT_PPzZI_H |
| 12580 | 286929U, // CMPLT_PPzZI_S |
| 12581 | 67391697U, // CMPLT_WIDE_PPzZZ_B |
| 12582 | 2644083U, // CMPLT_WIDE_PPzZZ_H |
| 12583 | 67395793U, // CMPLT_WIDE_PPzZZ_S |
| 12584 | 282833U, // CMPNE_PPzZI_B |
| 12585 | 274641U, // CMPNE_PPzZI_D |
| 12586 | 103045235U, // CMPNE_PPzZI_H |
| 12587 | 286929U, // CMPNE_PPzZI_S |
| 12588 | 33837265U, // CMPNE_PPzZZ_B |
| 12589 | 67383505U, // CMPNE_PPzZZ_D |
| 12590 | 101472371U, // CMPNE_PPzZZ_H |
| 12591 | 134504657U, // CMPNE_PPzZZ_S |
| 12592 | 67391697U, // CMPNE_WIDE_PPzZZ_B |
| 12593 | 2644083U, // CMPNE_WIDE_PPzZZ_H |
| 12594 | 67395793U, // CMPNE_WIDE_PPzZZ_S |
| 12595 | 16448U, // CMTSTv16i8 |
| 12596 | 6208U, // CMTSTv1i64 |
| 12597 | 16448U, // CMTSTv2i32 |
| 12598 | 16448U, // CMTSTv2i64 |
| 12599 | 16448U, // CMTSTv4i16 |
| 12600 | 16448U, // CMTSTv4i32 |
| 12601 | 16448U, // CMTSTv8i16 |
| 12602 | 16448U, // CMTSTv8i8 |
| 12603 | 16U, // CNOT_ZPmZ_B |
| 12604 | 32U, // CNOT_ZPmZ_D |
| 12605 | 0U, // CNOT_ZPmZ_H |
| 12606 | 48U, // CNOT_ZPmZ_S |
| 12607 | 355U, // CNTB_XPiI |
| 12608 | 355U, // CNTD_XPiI |
| 12609 | 355U, // CNTH_XPiI |
| 12610 | 3U, // CNTP_XCI_B |
| 12611 | 3U, // CNTP_XCI_D |
| 12612 | 3U, // CNTP_XCI_H |
| 12613 | 3U, // CNTP_XCI_S |
| 12614 | 20545U, // CNTP_XPP_B |
| 12615 | 12353U, // CNTP_XPP_D |
| 12616 | 10305U, // CNTP_XPP_H |
| 12617 | 24641U, // CNTP_XPP_S |
| 12618 | 355U, // CNTW_XPiI |
| 12619 | 0U, // CNTWr |
| 12620 | 0U, // CNTXr |
| 12621 | 16U, // CNT_ZPmZ_B |
| 12622 | 32U, // CNT_ZPmZ_D |
| 12623 | 0U, // CNT_ZPmZ_H |
| 12624 | 48U, // CNT_ZPmZ_S |
| 12625 | 0U, // CNTv16i8 |
| 12626 | 0U, // CNTv8i8 |
| 12627 | 12353U, // COMPACT_ZPZ_D |
| 12628 | 24641U, // COMPACT_ZPZ_S |
| 12629 | 0U, // CPYE |
| 12630 | 0U, // CPYEN |
| 12631 | 0U, // CPYERN |
| 12632 | 0U, // CPYERT |
| 12633 | 0U, // CPYERTN |
| 12634 | 0U, // CPYERTRN |
| 12635 | 0U, // CPYERTWN |
| 12636 | 0U, // CPYET |
| 12637 | 0U, // CPYETN |
| 12638 | 0U, // CPYETRN |
| 12639 | 0U, // CPYETWN |
| 12640 | 0U, // CPYEWN |
| 12641 | 0U, // CPYEWT |
| 12642 | 0U, // CPYEWTN |
| 12643 | 0U, // CPYEWTRN |
| 12644 | 0U, // CPYEWTWN |
| 12645 | 0U, // CPYFE |
| 12646 | 0U, // CPYFEN |
| 12647 | 0U, // CPYFERN |
| 12648 | 0U, // CPYFERT |
| 12649 | 0U, // CPYFERTN |
| 12650 | 0U, // CPYFERTRN |
| 12651 | 0U, // CPYFERTWN |
| 12652 | 0U, // CPYFET |
| 12653 | 0U, // CPYFETN |
| 12654 | 0U, // CPYFETRN |
| 12655 | 0U, // CPYFETWN |
| 12656 | 0U, // CPYFEWN |
| 12657 | 0U, // CPYFEWT |
| 12658 | 0U, // CPYFEWTN |
| 12659 | 0U, // CPYFEWTRN |
| 12660 | 0U, // CPYFEWTWN |
| 12661 | 0U, // CPYFM |
| 12662 | 0U, // CPYFMN |
| 12663 | 0U, // CPYFMRN |
| 12664 | 0U, // CPYFMRT |
| 12665 | 0U, // CPYFMRTN |
| 12666 | 0U, // CPYFMRTRN |
| 12667 | 0U, // CPYFMRTWN |
| 12668 | 0U, // CPYFMT |
| 12669 | 0U, // CPYFMTN |
| 12670 | 0U, // CPYFMTRN |
| 12671 | 0U, // CPYFMTWN |
| 12672 | 0U, // CPYFMWN |
| 12673 | 0U, // CPYFMWT |
| 12674 | 0U, // CPYFMWTN |
| 12675 | 0U, // CPYFMWTRN |
| 12676 | 0U, // CPYFMWTWN |
| 12677 | 0U, // CPYFP |
| 12678 | 0U, // CPYFPN |
| 12679 | 0U, // CPYFPRN |
| 12680 | 0U, // CPYFPRT |
| 12681 | 0U, // CPYFPRTN |
| 12682 | 0U, // CPYFPRTRN |
| 12683 | 0U, // CPYFPRTWN |
| 12684 | 0U, // CPYFPT |
| 12685 | 0U, // CPYFPTN |
| 12686 | 0U, // CPYFPTRN |
| 12687 | 0U, // CPYFPTWN |
| 12688 | 0U, // CPYFPWN |
| 12689 | 0U, // CPYFPWT |
| 12690 | 0U, // CPYFPWTN |
| 12691 | 0U, // CPYFPWTRN |
| 12692 | 0U, // CPYFPWTWN |
| 12693 | 0U, // CPYM |
| 12694 | 0U, // CPYMN |
| 12695 | 0U, // CPYMRN |
| 12696 | 0U, // CPYMRT |
| 12697 | 0U, // CPYMRTN |
| 12698 | 0U, // CPYMRTRN |
| 12699 | 0U, // CPYMRTWN |
| 12700 | 0U, // CPYMT |
| 12701 | 0U, // CPYMTN |
| 12702 | 0U, // CPYMTRN |
| 12703 | 0U, // CPYMTWN |
| 12704 | 0U, // CPYMWN |
| 12705 | 0U, // CPYMWT |
| 12706 | 0U, // CPYMWTN |
| 12707 | 0U, // CPYMWTRN |
| 12708 | 0U, // CPYMWTWN |
| 12709 | 0U, // CPYP |
| 12710 | 0U, // CPYPN |
| 12711 | 0U, // CPYPRN |
| 12712 | 0U, // CPYPRT |
| 12713 | 0U, // CPYPRTN |
| 12714 | 0U, // CPYPRTRN |
| 12715 | 0U, // CPYPRTWN |
| 12716 | 0U, // CPYPT |
| 12717 | 0U, // CPYPTN |
| 12718 | 0U, // CPYPTRN |
| 12719 | 0U, // CPYPTWN |
| 12720 | 0U, // CPYPWN |
| 12721 | 0U, // CPYPWT |
| 12722 | 0U, // CPYPWTN |
| 12723 | 0U, // CPYPWTRN |
| 12724 | 0U, // CPYPWTWN |
| 12725 | 368U, // CPY_ZPmI_B |
| 12726 | 384U, // CPY_ZPmI_D |
| 12727 | 4U, // CPY_ZPmI_H |
| 12728 | 400U, // CPY_ZPmI_S |
| 12729 | 416U, // CPY_ZPmR_B |
| 12730 | 416U, // CPY_ZPmR_D |
| 12731 | 4U, // CPY_ZPmR_H |
| 12732 | 416U, // CPY_ZPmR_S |
| 12733 | 416U, // CPY_ZPmV_B |
| 12734 | 416U, // CPY_ZPmV_D |
| 12735 | 4U, // CPY_ZPmV_H |
| 12736 | 416U, // CPY_ZPmV_S |
| 12737 | 84177U, // CPY_ZPzI_B |
| 12738 | 86225U, // CPY_ZPzI_D |
| 12739 | 435U, // CPY_ZPzI_H |
| 12740 | 88273U, // CPY_ZPzI_S |
| 12741 | 6208U, // CRC32Brr |
| 12742 | 6208U, // CRC32CBrr |
| 12743 | 6208U, // CRC32CHrr |
| 12744 | 6208U, // CRC32CWrr |
| 12745 | 6208U, // CRC32CXrr |
| 12746 | 6208U, // CRC32Hrr |
| 12747 | 6208U, // CRC32Wrr |
| 12748 | 6208U, // CRC32Xrr |
| 12749 | 302258240U, // CSELWr |
| 12750 | 302258240U, // CSELXr |
| 12751 | 302258240U, // CSINCWr |
| 12752 | 302258240U, // CSINCXr |
| 12753 | 302258240U, // CSINVWr |
| 12754 | 302258240U, // CSINVXr |
| 12755 | 302258240U, // CSNEGWr |
| 12756 | 302258240U, // CSNEGXr |
| 12757 | 0U, // CTERMEQ_WW |
| 12758 | 0U, // CTERMEQ_XX |
| 12759 | 0U, // CTERMNE_WW |
| 12760 | 0U, // CTERMNE_XX |
| 12761 | 0U, // CTZWr |
| 12762 | 0U, // CTZXr |
| 12763 | 0U, // DCPS1 |
| 12764 | 0U, // DCPS2 |
| 12765 | 0U, // DCPS3 |
| 12766 | 4U, // DECB_XPiI |
| 12767 | 4U, // DECD_XPiI |
| 12768 | 4U, // DECD_ZPiI |
| 12769 | 4U, // DECH_XPiI |
| 12770 | 0U, // DECH_ZPiI |
| 12771 | 2U, // DECP_XP_B |
| 12772 | 1U, // DECP_XP_D |
| 12773 | 0U, // DECP_XP_H |
| 12774 | 2U, // DECP_XP_S |
| 12775 | 0U, // DECP_ZP_D |
| 12776 | 0U, // DECP_ZP_H |
| 12777 | 0U, // DECP_ZP_S |
| 12778 | 4U, // DECW_XPiI |
| 12779 | 4U, // DECW_ZPiI |
| 12780 | 0U, // DMB |
| 12781 | 0U, // DRPS |
| 12782 | 0U, // DSB |
| 12783 | 0U, // DSBnXS |
| 12784 | 4U, // DUPM_ZI |
| 12785 | 450U, // DUPQ_ZZI_B |
| 12786 | 449U, // DUPQ_ZZI_D |
| 12787 | 4U, // DUPQ_ZZI_H |
| 12788 | 450U, // DUPQ_ZZI_S |
| 12789 | 4U, // DUP_ZI_B |
| 12790 | 4U, // DUP_ZI_D |
| 12791 | 0U, // DUP_ZI_H |
| 12792 | 4U, // DUP_ZI_S |
| 12793 | 0U, // DUP_ZR_B |
| 12794 | 0U, // DUP_ZR_D |
| 12795 | 0U, // DUP_ZR_H |
| 12796 | 0U, // DUP_ZR_S |
| 12797 | 450U, // DUP_ZZI_B |
| 12798 | 449U, // DUP_ZZI_D |
| 12799 | 4U, // DUP_ZZI_H |
| 12800 | 4U, // DUP_ZZI_Q |
| 12801 | 450U, // DUP_ZZI_S |
| 12802 | 448U, // DUPi16 |
| 12803 | 448U, // DUPi32 |
| 12804 | 448U, // DUPi64 |
| 12805 | 448U, // DUPi8 |
| 12806 | 0U, // DUPv16i8gpr |
| 12807 | 448U, // DUPv16i8lane |
| 12808 | 0U, // DUPv2i32gpr |
| 12809 | 448U, // DUPv2i32lane |
| 12810 | 0U, // DUPv2i64gpr |
| 12811 | 448U, // DUPv2i64lane |
| 12812 | 0U, // DUPv4i16gpr |
| 12813 | 448U, // DUPv4i16lane |
| 12814 | 0U, // DUPv4i32gpr |
| 12815 | 448U, // DUPv4i32lane |
| 12816 | 0U, // DUPv8i16gpr |
| 12817 | 448U, // DUPv8i16lane |
| 12818 | 0U, // DUPv8i8gpr |
| 12819 | 448U, // DUPv8i8lane |
| 12820 | 28736U, // EONWrs |
| 12821 | 28736U, // EONXrs |
| 12822 | 168050752U, // EOR3 |
| 12823 | 67383361U, // EOR3_ZZZZ |
| 12824 | 19U, // EORBT_ZZZ_B |
| 12825 | 2112U, // EORBT_ZZZ_D |
| 12826 | 257U, // EORBT_ZZZ_H |
| 12827 | 4160U, // EORBT_ZZZ_S |
| 12828 | 20545U, // EORQV_VPZ_B |
| 12829 | 12353U, // EORQV_VPZ_D |
| 12830 | 10305U, // EORQV_VPZ_H |
| 12831 | 24641U, // EORQV_VPZ_S |
| 12832 | 33837265U, // EORS_PPzPP |
| 12833 | 19U, // EORTB_ZZZ_B |
| 12834 | 2112U, // EORTB_ZZZ_D |
| 12835 | 257U, // EORTB_ZZZ_H |
| 12836 | 4160U, // EORTB_ZZZ_S |
| 12837 | 0U, // EORV_VPZ_B |
| 12838 | 0U, // EORV_VPZ_D |
| 12839 | 0U, // EORV_VPZ_H |
| 12840 | 0U, // EORV_VPZ_S |
| 12841 | 71744U, // EORWri |
| 12842 | 28736U, // EORWrs |
| 12843 | 73792U, // EORXri |
| 12844 | 28736U, // EORXrs |
| 12845 | 33837265U, // EOR_PPzPP |
| 12846 | 73793U, // EOR_ZI |
| 12847 | 33837153U, // EOR_ZPmZ_B |
| 12848 | 67383393U, // EOR_ZPmZ_D |
| 12849 | 101472369U, // EOR_ZPmZ_H |
| 12850 | 134504545U, // EOR_ZPmZ_S |
| 12851 | 12353U, // EOR_ZZZ |
| 12852 | 16448U, // EORv16i8 |
| 12853 | 16448U, // EORv8i8 |
| 12854 | 0U, // ERET |
| 12855 | 0U, // ERETAA |
| 12856 | 0U, // ERETAB |
| 12857 | 282690U, // EXTQ_ZZI |
| 12858 | 464U, // EXTRACT_ZPMXI_H_B |
| 12859 | 464U, // EXTRACT_ZPMXI_H_D |
| 12860 | 5U, // EXTRACT_ZPMXI_H_H |
| 12861 | 5U, // EXTRACT_ZPMXI_H_Q |
| 12862 | 464U, // EXTRACT_ZPMXI_H_S |
| 12863 | 480U, // EXTRACT_ZPMXI_V_B |
| 12864 | 480U, // EXTRACT_ZPMXI_V_D |
| 12865 | 5U, // EXTRACT_ZPMXI_V_H |
| 12866 | 5U, // EXTRACT_ZPMXI_V_Q |
| 12867 | 480U, // EXTRACT_ZPMXI_V_S |
| 12868 | 268352U, // EXTRWrri |
| 12869 | 268352U, // EXTRXrri |
| 12870 | 470044738U, // EXT_ZZI |
| 12871 | 501U, // EXT_ZZI_B |
| 12872 | 278592U, // EXTv16i8 |
| 12873 | 278592U, // EXTv8i8 |
| 12874 | 0U, // F1CVTL2v8f16 |
| 12875 | 0U, // F1CVTLT_ZZ_BtoH |
| 12876 | 0U, // F1CVTL_2ZZ_BtoH_NAME |
| 12877 | 0U, // F1CVTLv8f16 |
| 12878 | 0U, // F1CVT_2ZZ_BtoH_NAME |
| 12879 | 0U, // F1CVT_ZZ_BtoH |
| 12880 | 0U, // F2CVTL2v8f16 |
| 12881 | 0U, // F2CVTLT_ZZ_BtoH |
| 12882 | 0U, // F2CVTL_2ZZ_BtoH_NAME |
| 12883 | 0U, // F2CVTLv8f16 |
| 12884 | 0U, // F2CVT_2ZZ_BtoH_NAME |
| 12885 | 0U, // F2CVT_ZZ_BtoH |
| 12886 | 6208U, // FABD16 |
| 12887 | 6208U, // FABD32 |
| 12888 | 6208U, // FABD64 |
| 12889 | 67383393U, // FABD_ZPmZ_D |
| 12890 | 101472369U, // FABD_ZPmZ_H |
| 12891 | 134504545U, // FABD_ZPmZ_S |
| 12892 | 16448U, // FABDv2f32 |
| 12893 | 16448U, // FABDv2f64 |
| 12894 | 16448U, // FABDv4f16 |
| 12895 | 16448U, // FABDv4f32 |
| 12896 | 16448U, // FABDv8f16 |
| 12897 | 0U, // FABSDr |
| 12898 | 0U, // FABSHr |
| 12899 | 0U, // FABSSr |
| 12900 | 32U, // FABS_ZPmZ_D |
| 12901 | 0U, // FABS_ZPmZ_H |
| 12902 | 48U, // FABS_ZPmZ_S |
| 12903 | 0U, // FABSv2f32 |
| 12904 | 0U, // FABSv2f64 |
| 12905 | 0U, // FABSv4f16 |
| 12906 | 0U, // FABSv4f32 |
| 12907 | 0U, // FABSv8f16 |
| 12908 | 6208U, // FACGE16 |
| 12909 | 6208U, // FACGE32 |
| 12910 | 6208U, // FACGE64 |
| 12911 | 67383505U, // FACGE_PPzZZ_D |
| 12912 | 101472371U, // FACGE_PPzZZ_H |
| 12913 | 134504657U, // FACGE_PPzZZ_S |
| 12914 | 16448U, // FACGEv2f32 |
| 12915 | 16448U, // FACGEv2f64 |
| 12916 | 16448U, // FACGEv4f16 |
| 12917 | 16448U, // FACGEv4f32 |
| 12918 | 16448U, // FACGEv8f16 |
| 12919 | 6208U, // FACGT16 |
| 12920 | 6208U, // FACGT32 |
| 12921 | 6208U, // FACGT64 |
| 12922 | 67383505U, // FACGT_PPzZZ_D |
| 12923 | 101472371U, // FACGT_PPzZZ_H |
| 12924 | 134504657U, // FACGT_PPzZZ_S |
| 12925 | 16448U, // FACGTv2f32 |
| 12926 | 16448U, // FACGTv2f64 |
| 12927 | 16448U, // FACGTv4f16 |
| 12928 | 16448U, // FACGTv4f32 |
| 12929 | 16448U, // FACGTv8f16 |
| 12930 | 0U, // FADDA_VPZ_D |
| 12931 | 257U, // FADDA_VPZ_H |
| 12932 | 0U, // FADDA_VPZ_S |
| 12933 | 6208U, // FADDDrr |
| 12934 | 6208U, // FADDHrr |
| 12935 | 67383393U, // FADDP_ZPmZZ_D |
| 12936 | 101472369U, // FADDP_ZPmZZ_H |
| 12937 | 134504545U, // FADDP_ZPmZZ_S |
| 12938 | 16448U, // FADDPv2f32 |
| 12939 | 16448U, // FADDPv2f64 |
| 12940 | 0U, // FADDPv2i16p |
| 12941 | 0U, // FADDPv2i32p |
| 12942 | 0U, // FADDPv2i64p |
| 12943 | 16448U, // FADDPv4f16 |
| 12944 | 16448U, // FADDPv4f32 |
| 12945 | 16448U, // FADDPv8f16 |
| 12946 | 12353U, // FADDQV_D |
| 12947 | 10305U, // FADDQV_H |
| 12948 | 24641U, // FADDQV_S |
| 12949 | 6208U, // FADDSrr |
| 12950 | 0U, // FADDV_VPZ_D |
| 12951 | 0U, // FADDV_VPZ_H |
| 12952 | 0U, // FADDV_VPZ_S |
| 12953 | 161U, // FADD_VG2_M2Z_D |
| 12954 | 241U, // FADD_VG2_M2Z_H |
| 12955 | 177U, // FADD_VG2_M2Z_S |
| 12956 | 161U, // FADD_VG4_M4Z_D |
| 12957 | 241U, // FADD_VG4_M4Z_H |
| 12958 | 177U, // FADD_VG4_M4Z_S |
| 12959 | 503591009U, // FADD_ZPmI_D |
| 12960 | 5003377U, // FADD_ZPmI_H |
| 12961 | 503603297U, // FADD_ZPmI_S |
| 12962 | 67383393U, // FADD_ZPmZ_D |
| 12963 | 101472369U, // FADD_ZPmZ_H |
| 12964 | 134504545U, // FADD_ZPmZ_S |
| 12965 | 12353U, // FADD_ZZZ_D |
| 12966 | 113U, // FADD_ZZZ_H |
| 12967 | 24642U, // FADD_ZZZ_S |
| 12968 | 16448U, // FADDv2f32 |
| 12969 | 16448U, // FADDv2f64 |
| 12970 | 16448U, // FADDv4f16 |
| 12971 | 16448U, // FADDv4f32 |
| 12972 | 16448U, // FADDv8f16 |
| 12973 | 513U, // FAMAX_2Z2Z_D |
| 12974 | 273U, // FAMAX_2Z2Z_H |
| 12975 | 529U, // FAMAX_2Z2Z_S |
| 12976 | 513U, // FAMAX_4Z4Z_D |
| 12977 | 273U, // FAMAX_4Z4Z_H |
| 12978 | 529U, // FAMAX_4Z4Z_S |
| 12979 | 67383393U, // FAMAX_ZPmZ_D |
| 12980 | 101472369U, // FAMAX_ZPmZ_H |
| 12981 | 134504545U, // FAMAX_ZPmZ_S |
| 12982 | 16448U, // FAMAXv2f32 |
| 12983 | 16448U, // FAMAXv2f64 |
| 12984 | 16448U, // FAMAXv4f16 |
| 12985 | 16448U, // FAMAXv4f32 |
| 12986 | 16448U, // FAMAXv8f16 |
| 12987 | 513U, // FAMIN_2Z2Z_D |
| 12988 | 273U, // FAMIN_2Z2Z_H |
| 12989 | 529U, // FAMIN_2Z2Z_S |
| 12990 | 513U, // FAMIN_4Z4Z_D |
| 12991 | 273U, // FAMIN_4Z4Z_H |
| 12992 | 529U, // FAMIN_4Z4Z_S |
| 12993 | 67383393U, // FAMIN_ZPmZ_D |
| 12994 | 101472369U, // FAMIN_ZPmZ_H |
| 12995 | 134504545U, // FAMIN_ZPmZ_S |
| 12996 | 16448U, // FAMINv2f32 |
| 12997 | 16448U, // FAMINv2f64 |
| 12998 | 16448U, // FAMINv4f16 |
| 12999 | 16448U, // FAMINv4f32 |
| 13000 | 16448U, // FAMINv8f16 |
| 13001 | 67383393U, // FCADD_ZPmZ_D |
| 13002 | 336353393U, // FCADD_ZPmZ_H |
| 13003 | 134504545U, // FCADD_ZPmZ_S |
| 13004 | 268714048U, // FCADDv2f32 |
| 13005 | 268714048U, // FCADDv2f64 |
| 13006 | 268714048U, // FCADDv4f16 |
| 13007 | 268714048U, // FCADDv4f32 |
| 13008 | 268714048U, // FCADDv8f16 |
| 13009 | 302258240U, // FCCMPDrr |
| 13010 | 302258240U, // FCCMPEDrr |
| 13011 | 302258240U, // FCCMPEHrr |
| 13012 | 302258240U, // FCCMPESrr |
| 13013 | 302258240U, // FCCMPHrr |
| 13014 | 302258240U, // FCCMPSrr |
| 13015 | 33U, // FCLAMP_VG2_2Z2Z_D |
| 13016 | 257U, // FCLAMP_VG2_2Z2Z_H |
| 13017 | 49U, // FCLAMP_VG2_2Z2Z_S |
| 13018 | 33U, // FCLAMP_VG4_4Z4Z_D |
| 13019 | 257U, // FCLAMP_VG4_4Z4Z_H |
| 13020 | 49U, // FCLAMP_VG4_4Z4Z_S |
| 13021 | 2112U, // FCLAMP_ZZZ_D |
| 13022 | 257U, // FCLAMP_ZZZ_H |
| 13023 | 4160U, // FCLAMP_ZZZ_S |
| 13024 | 6208U, // FCMEQ16 |
| 13025 | 6208U, // FCMEQ32 |
| 13026 | 6208U, // FCMEQ64 |
| 13027 | 5255377U, // FCMEQ_PPzZ0_D |
| 13028 | 90227U, // FCMEQ_PPzZ0_H |
| 13029 | 5267665U, // FCMEQ_PPzZ0_S |
| 13030 | 67383505U, // FCMEQ_PPzZZ_D |
| 13031 | 101472371U, // FCMEQ_PPzZZ_H |
| 13032 | 134504657U, // FCMEQ_PPzZZ_S |
| 13033 | 544U, // FCMEQv1i16rz |
| 13034 | 544U, // FCMEQv1i32rz |
| 13035 | 544U, // FCMEQv1i64rz |
| 13036 | 16448U, // FCMEQv2f32 |
| 13037 | 16448U, // FCMEQv2f64 |
| 13038 | 544U, // FCMEQv2i32rz |
| 13039 | 544U, // FCMEQv2i64rz |
| 13040 | 16448U, // FCMEQv4f16 |
| 13041 | 16448U, // FCMEQv4f32 |
| 13042 | 544U, // FCMEQv4i16rz |
| 13043 | 544U, // FCMEQv4i32rz |
| 13044 | 16448U, // FCMEQv8f16 |
| 13045 | 544U, // FCMEQv8i16rz |
| 13046 | 6208U, // FCMGE16 |
| 13047 | 6208U, // FCMGE32 |
| 13048 | 6208U, // FCMGE64 |
| 13049 | 5255377U, // FCMGE_PPzZ0_D |
| 13050 | 90227U, // FCMGE_PPzZ0_H |
| 13051 | 5267665U, // FCMGE_PPzZ0_S |
| 13052 | 67383505U, // FCMGE_PPzZZ_D |
| 13053 | 101472371U, // FCMGE_PPzZZ_H |
| 13054 | 134504657U, // FCMGE_PPzZZ_S |
| 13055 | 544U, // FCMGEv1i16rz |
| 13056 | 544U, // FCMGEv1i32rz |
| 13057 | 544U, // FCMGEv1i64rz |
| 13058 | 16448U, // FCMGEv2f32 |
| 13059 | 16448U, // FCMGEv2f64 |
| 13060 | 544U, // FCMGEv2i32rz |
| 13061 | 544U, // FCMGEv2i64rz |
| 13062 | 16448U, // FCMGEv4f16 |
| 13063 | 16448U, // FCMGEv4f32 |
| 13064 | 544U, // FCMGEv4i16rz |
| 13065 | 544U, // FCMGEv4i32rz |
| 13066 | 16448U, // FCMGEv8f16 |
| 13067 | 544U, // FCMGEv8i16rz |
| 13068 | 6208U, // FCMGT16 |
| 13069 | 6208U, // FCMGT32 |
| 13070 | 6208U, // FCMGT64 |
| 13071 | 5255377U, // FCMGT_PPzZ0_D |
| 13072 | 90227U, // FCMGT_PPzZ0_H |
| 13073 | 5267665U, // FCMGT_PPzZ0_S |
| 13074 | 67383505U, // FCMGT_PPzZZ_D |
| 13075 | 101472371U, // FCMGT_PPzZZ_H |
| 13076 | 134504657U, // FCMGT_PPzZZ_S |
| 13077 | 544U, // FCMGTv1i16rz |
| 13078 | 544U, // FCMGTv1i32rz |
| 13079 | 544U, // FCMGTv1i64rz |
| 13080 | 16448U, // FCMGTv2f32 |
| 13081 | 16448U, // FCMGTv2f64 |
| 13082 | 544U, // FCMGTv2i32rz |
| 13083 | 544U, // FCMGTv2i64rz |
| 13084 | 16448U, // FCMGTv4f16 |
| 13085 | 16448U, // FCMGTv4f32 |
| 13086 | 544U, // FCMGTv4i16rz |
| 13087 | 544U, // FCMGTv4i32rz |
| 13088 | 16448U, // FCMGTv8f16 |
| 13089 | 544U, // FCMGTv8i16rz |
| 13090 | 537135201U, // FCMLA_ZPmZZ_D |
| 13091 | 339237121U, // FCMLA_ZPmZZ_H |
| 13092 | 570691681U, // FCMLA_ZPmZZ_S |
| 13093 | 369438977U, // FCMLA_ZZZI_H |
| 13094 | 338432064U, // FCMLA_ZZZI_S |
| 13095 | 402933825U, // FCMLAv2f32 |
| 13096 | 402933825U, // FCMLAv2f64 |
| 13097 | 402933825U, // FCMLAv4f16 |
| 13098 | 338446401U, // FCMLAv4f16_indexed |
| 13099 | 402933825U, // FCMLAv4f32 |
| 13100 | 338446401U, // FCMLAv4f32_indexed |
| 13101 | 402933825U, // FCMLAv8f16 |
| 13102 | 338446401U, // FCMLAv8f16_indexed |
| 13103 | 5255377U, // FCMLE_PPzZ0_D |
| 13104 | 90227U, // FCMLE_PPzZ0_H |
| 13105 | 5267665U, // FCMLE_PPzZ0_S |
| 13106 | 544U, // FCMLEv1i16rz |
| 13107 | 544U, // FCMLEv1i32rz |
| 13108 | 544U, // FCMLEv1i64rz |
| 13109 | 544U, // FCMLEv2i32rz |
| 13110 | 544U, // FCMLEv2i64rz |
| 13111 | 544U, // FCMLEv4i16rz |
| 13112 | 544U, // FCMLEv4i32rz |
| 13113 | 544U, // FCMLEv8i16rz |
| 13114 | 5255377U, // FCMLT_PPzZ0_D |
| 13115 | 90227U, // FCMLT_PPzZ0_H |
| 13116 | 5267665U, // FCMLT_PPzZ0_S |
| 13117 | 544U, // FCMLTv1i16rz |
| 13118 | 544U, // FCMLTv1i32rz |
| 13119 | 544U, // FCMLTv1i64rz |
| 13120 | 544U, // FCMLTv2i32rz |
| 13121 | 544U, // FCMLTv2i64rz |
| 13122 | 544U, // FCMLTv4i16rz |
| 13123 | 544U, // FCMLTv4i32rz |
| 13124 | 544U, // FCMLTv8i16rz |
| 13125 | 5255377U, // FCMNE_PPzZ0_D |
| 13126 | 90227U, // FCMNE_PPzZ0_H |
| 13127 | 5267665U, // FCMNE_PPzZ0_S |
| 13128 | 67383505U, // FCMNE_PPzZZ_D |
| 13129 | 101472371U, // FCMNE_PPzZZ_H |
| 13130 | 134504657U, // FCMNE_PPzZZ_S |
| 13131 | 0U, // FCMPDri |
| 13132 | 0U, // FCMPDrr |
| 13133 | 0U, // FCMPEDri |
| 13134 | 0U, // FCMPEDrr |
| 13135 | 0U, // FCMPEHri |
| 13136 | 0U, // FCMPEHrr |
| 13137 | 0U, // FCMPESri |
| 13138 | 0U, // FCMPESrr |
| 13139 | 0U, // FCMPHri |
| 13140 | 0U, // FCMPHrr |
| 13141 | 0U, // FCMPSri |
| 13142 | 0U, // FCMPSrr |
| 13143 | 67383505U, // FCMUO_PPzZZ_D |
| 13144 | 101472371U, // FCMUO_PPzZZ_H |
| 13145 | 134504657U, // FCMUO_PPzZZ_S |
| 13146 | 560U, // FCPY_ZPmI_D |
| 13147 | 5U, // FCPY_ZPmI_H |
| 13148 | 560U, // FCPY_ZPmI_S |
| 13149 | 302258240U, // FCSELDrrr |
| 13150 | 302258240U, // FCSELHrrr |
| 13151 | 302258240U, // FCSELSrrr |
| 13152 | 0U, // FCVTASUWDr |
| 13153 | 0U, // FCVTASUWHr |
| 13154 | 0U, // FCVTASUWSr |
| 13155 | 0U, // FCVTASUXDr |
| 13156 | 0U, // FCVTASUXHr |
| 13157 | 0U, // FCVTASUXSr |
| 13158 | 0U, // FCVTASv1f16 |
| 13159 | 0U, // FCVTASv1i32 |
| 13160 | 0U, // FCVTASv1i64 |
| 13161 | 0U, // FCVTASv2f32 |
| 13162 | 0U, // FCVTASv2f64 |
| 13163 | 0U, // FCVTASv4f16 |
| 13164 | 0U, // FCVTASv4f32 |
| 13165 | 0U, // FCVTASv8f16 |
| 13166 | 0U, // FCVTAUUWDr |
| 13167 | 0U, // FCVTAUUWHr |
| 13168 | 0U, // FCVTAUUWSr |
| 13169 | 0U, // FCVTAUUXDr |
| 13170 | 0U, // FCVTAUUXHr |
| 13171 | 0U, // FCVTAUUXSr |
| 13172 | 0U, // FCVTAUv1f16 |
| 13173 | 0U, // FCVTAUv1i32 |
| 13174 | 0U, // FCVTAUv1i64 |
| 13175 | 0U, // FCVTAUv2f32 |
| 13176 | 0U, // FCVTAUv2f64 |
| 13177 | 0U, // FCVTAUv4f16 |
| 13178 | 0U, // FCVTAUv4f32 |
| 13179 | 0U, // FCVTAUv8f16 |
| 13180 | 0U, // FCVTDHr |
| 13181 | 0U, // FCVTDSr |
| 13182 | 0U, // FCVTHDr |
| 13183 | 0U, // FCVTHSr |
| 13184 | 256U, // FCVTLT_ZPmZ_HtoS |
| 13185 | 48U, // FCVTLT_ZPmZ_StoD |
| 13186 | 0U, // FCVTL_2ZZ_H_S |
| 13187 | 576U, // FCVTLv2i32 |
| 13188 | 592U, // FCVTLv4i16 |
| 13189 | 608U, // FCVTLv4i32 |
| 13190 | 624U, // FCVTLv8i16 |
| 13191 | 0U, // FCVTMSUWDr |
| 13192 | 0U, // FCVTMSUWHr |
| 13193 | 0U, // FCVTMSUWSr |
| 13194 | 0U, // FCVTMSUXDr |
| 13195 | 0U, // FCVTMSUXHr |
| 13196 | 0U, // FCVTMSUXSr |
| 13197 | 0U, // FCVTMSv1f16 |
| 13198 | 0U, // FCVTMSv1i32 |
| 13199 | 0U, // FCVTMSv1i64 |
| 13200 | 0U, // FCVTMSv2f32 |
| 13201 | 0U, // FCVTMSv2f64 |
| 13202 | 0U, // FCVTMSv4f16 |
| 13203 | 0U, // FCVTMSv4f32 |
| 13204 | 0U, // FCVTMSv8f16 |
| 13205 | 0U, // FCVTMUUWDr |
| 13206 | 0U, // FCVTMUUWHr |
| 13207 | 0U, // FCVTMUUWSr |
| 13208 | 0U, // FCVTMUUXDr |
| 13209 | 0U, // FCVTMUUXHr |
| 13210 | 0U, // FCVTMUUXSr |
| 13211 | 0U, // FCVTMUv1f16 |
| 13212 | 0U, // FCVTMUv1i32 |
| 13213 | 0U, // FCVTMUv1i64 |
| 13214 | 0U, // FCVTMUv2f32 |
| 13215 | 0U, // FCVTMUv2f64 |
| 13216 | 0U, // FCVTMUv4f16 |
| 13217 | 0U, // FCVTMUv4f32 |
| 13218 | 0U, // FCVTMUv8f16 |
| 13219 | 5U, // FCVTNB_Z2Z_StoB |
| 13220 | 0U, // FCVTNSUWDr |
| 13221 | 0U, // FCVTNSUWHr |
| 13222 | 0U, // FCVTNSUWSr |
| 13223 | 0U, // FCVTNSUXDr |
| 13224 | 0U, // FCVTNSUXHr |
| 13225 | 0U, // FCVTNSUXSr |
| 13226 | 0U, // FCVTNSv1f16 |
| 13227 | 0U, // FCVTNSv1i32 |
| 13228 | 0U, // FCVTNSv1i64 |
| 13229 | 0U, // FCVTNSv2f32 |
| 13230 | 0U, // FCVTNSv2f64 |
| 13231 | 0U, // FCVTNSv4f16 |
| 13232 | 0U, // FCVTNSv4f32 |
| 13233 | 0U, // FCVTNSv8f16 |
| 13234 | 5U, // FCVTNT_Z2Z_StoB |
| 13235 | 32U, // FCVTNT_ZPmZ_DtoS |
| 13236 | 2U, // FCVTNT_ZPmZ_StoH |
| 13237 | 0U, // FCVTNUUWDr |
| 13238 | 0U, // FCVTNUUWHr |
| 13239 | 0U, // FCVTNUUWSr |
| 13240 | 0U, // FCVTNUUXDr |
| 13241 | 0U, // FCVTNUUXHr |
| 13242 | 0U, // FCVTNUUXSr |
| 13243 | 0U, // FCVTNUv1f16 |
| 13244 | 0U, // FCVTNUv1i32 |
| 13245 | 0U, // FCVTNUv1i64 |
| 13246 | 0U, // FCVTNUv2f32 |
| 13247 | 0U, // FCVTNUv2f64 |
| 13248 | 0U, // FCVTNUv4f16 |
| 13249 | 0U, // FCVTNUv4f32 |
| 13250 | 0U, // FCVTNUv8f16 |
| 13251 | 640U, // FCVTN_F16_F8v16f8 |
| 13252 | 656U, // FCVTN_F16_F8v8f8 |
| 13253 | 0U, // FCVTN_F32_F82v16f8 |
| 13254 | 672U, // FCVTN_F32_F8v8f8 |
| 13255 | 2U, // FCVTN_Z2Z_HtoB |
| 13256 | 0U, // FCVTN_Z2Z_StoH |
| 13257 | 5U, // FCVTN_Z4Z_StoB_NAME |
| 13258 | 0U, // FCVTNv2i32 |
| 13259 | 0U, // FCVTNv4i16 |
| 13260 | 689U, // FCVTNv4i32 |
| 13261 | 609U, // FCVTNv8i16 |
| 13262 | 0U, // FCVTPSUWDr |
| 13263 | 0U, // FCVTPSUWHr |
| 13264 | 0U, // FCVTPSUWSr |
| 13265 | 0U, // FCVTPSUXDr |
| 13266 | 0U, // FCVTPSUXHr |
| 13267 | 0U, // FCVTPSUXSr |
| 13268 | 0U, // FCVTPSv1f16 |
| 13269 | 0U, // FCVTPSv1i32 |
| 13270 | 0U, // FCVTPSv1i64 |
| 13271 | 0U, // FCVTPSv2f32 |
| 13272 | 0U, // FCVTPSv2f64 |
| 13273 | 0U, // FCVTPSv4f16 |
| 13274 | 0U, // FCVTPSv4f32 |
| 13275 | 0U, // FCVTPSv8f16 |
| 13276 | 0U, // FCVTPUUWDr |
| 13277 | 0U, // FCVTPUUWHr |
| 13278 | 0U, // FCVTPUUWSr |
| 13279 | 0U, // FCVTPUUXDr |
| 13280 | 0U, // FCVTPUUXHr |
| 13281 | 0U, // FCVTPUUXSr |
| 13282 | 0U, // FCVTPUv1f16 |
| 13283 | 0U, // FCVTPUv1i32 |
| 13284 | 0U, // FCVTPUv1i64 |
| 13285 | 0U, // FCVTPUv2f32 |
| 13286 | 0U, // FCVTPUv2f64 |
| 13287 | 0U, // FCVTPUv4f16 |
| 13288 | 0U, // FCVTPUv4f32 |
| 13289 | 0U, // FCVTPUv8f16 |
| 13290 | 0U, // FCVTSDr |
| 13291 | 0U, // FCVTSHr |
| 13292 | 32U, // FCVTXNT_ZPmZ_DtoS |
| 13293 | 0U, // FCVTXNv1i64 |
| 13294 | 0U, // FCVTXNv2f32 |
| 13295 | 689U, // FCVTXNv4f32 |
| 13296 | 32U, // FCVTX_ZPmZ_DtoS |
| 13297 | 6208U, // FCVTZSSWDri |
| 13298 | 6208U, // FCVTZSSWHri |
| 13299 | 6208U, // FCVTZSSWSri |
| 13300 | 6208U, // FCVTZSSXDri |
| 13301 | 6208U, // FCVTZSSXHri |
| 13302 | 6208U, // FCVTZSSXSri |
| 13303 | 0U, // FCVTZSUWDr |
| 13304 | 0U, // FCVTZSUWHr |
| 13305 | 0U, // FCVTZSUWSr |
| 13306 | 0U, // FCVTZSUXDr |
| 13307 | 0U, // FCVTZSUXHr |
| 13308 | 0U, // FCVTZSUXSr |
| 13309 | 0U, // FCVTZS_2Z2Z_StoS |
| 13310 | 0U, // FCVTZS_4Z4Z_StoS |
| 13311 | 32U, // FCVTZS_ZPmZ_DtoD |
| 13312 | 32U, // FCVTZS_ZPmZ_DtoS |
| 13313 | 256U, // FCVTZS_ZPmZ_HtoD |
| 13314 | 0U, // FCVTZS_ZPmZ_HtoH |
| 13315 | 256U, // FCVTZS_ZPmZ_HtoS |
| 13316 | 48U, // FCVTZS_ZPmZ_StoD |
| 13317 | 48U, // FCVTZS_ZPmZ_StoS |
| 13318 | 6208U, // FCVTZSd |
| 13319 | 6208U, // FCVTZSh |
| 13320 | 6208U, // FCVTZSs |
| 13321 | 0U, // FCVTZSv1f16 |
| 13322 | 0U, // FCVTZSv1i32 |
| 13323 | 0U, // FCVTZSv1i64 |
| 13324 | 0U, // FCVTZSv2f32 |
| 13325 | 0U, // FCVTZSv2f64 |
| 13326 | 6208U, // FCVTZSv2i32_shift |
| 13327 | 6208U, // FCVTZSv2i64_shift |
| 13328 | 0U, // FCVTZSv4f16 |
| 13329 | 0U, // FCVTZSv4f32 |
| 13330 | 6208U, // FCVTZSv4i16_shift |
| 13331 | 6208U, // FCVTZSv4i32_shift |
| 13332 | 0U, // FCVTZSv8f16 |
| 13333 | 6208U, // FCVTZSv8i16_shift |
| 13334 | 6208U, // FCVTZUSWDri |
| 13335 | 6208U, // FCVTZUSWHri |
| 13336 | 6208U, // FCVTZUSWSri |
| 13337 | 6208U, // FCVTZUSXDri |
| 13338 | 6208U, // FCVTZUSXHri |
| 13339 | 6208U, // FCVTZUSXSri |
| 13340 | 0U, // FCVTZUUWDr |
| 13341 | 0U, // FCVTZUUWHr |
| 13342 | 0U, // FCVTZUUWSr |
| 13343 | 0U, // FCVTZUUXDr |
| 13344 | 0U, // FCVTZUUXHr |
| 13345 | 0U, // FCVTZUUXSr |
| 13346 | 0U, // FCVTZU_2Z2Z_StoS |
| 13347 | 0U, // FCVTZU_4Z4Z_StoS |
| 13348 | 32U, // FCVTZU_ZPmZ_DtoD |
| 13349 | 32U, // FCVTZU_ZPmZ_DtoS |
| 13350 | 256U, // FCVTZU_ZPmZ_HtoD |
| 13351 | 0U, // FCVTZU_ZPmZ_HtoH |
| 13352 | 256U, // FCVTZU_ZPmZ_HtoS |
| 13353 | 48U, // FCVTZU_ZPmZ_StoD |
| 13354 | 48U, // FCVTZU_ZPmZ_StoS |
| 13355 | 6208U, // FCVTZUd |
| 13356 | 6208U, // FCVTZUh |
| 13357 | 6208U, // FCVTZUs |
| 13358 | 0U, // FCVTZUv1f16 |
| 13359 | 0U, // FCVTZUv1i32 |
| 13360 | 0U, // FCVTZUv1i64 |
| 13361 | 0U, // FCVTZUv2f32 |
| 13362 | 0U, // FCVTZUv2f64 |
| 13363 | 6208U, // FCVTZUv2i32_shift |
| 13364 | 6208U, // FCVTZUv2i64_shift |
| 13365 | 0U, // FCVTZUv4f16 |
| 13366 | 0U, // FCVTZUv4f32 |
| 13367 | 6208U, // FCVTZUv4i16_shift |
| 13368 | 6208U, // FCVTZUv4i32_shift |
| 13369 | 0U, // FCVTZUv8f16 |
| 13370 | 6208U, // FCVTZUv8i16_shift |
| 13371 | 0U, // FCVT_2ZZ_H_S |
| 13372 | 2U, // FCVT_Z2Z_HtoB |
| 13373 | 0U, // FCVT_Z2Z_StoH |
| 13374 | 5U, // FCVT_Z4Z_StoB_NAME |
| 13375 | 5U, // FCVT_ZPmZ_DtoH |
| 13376 | 32U, // FCVT_ZPmZ_DtoS |
| 13377 | 256U, // FCVT_ZPmZ_HtoD |
| 13378 | 256U, // FCVT_ZPmZ_HtoS |
| 13379 | 48U, // FCVT_ZPmZ_StoD |
| 13380 | 2U, // FCVT_ZPmZ_StoH |
| 13381 | 6208U, // FDIVDrr |
| 13382 | 6208U, // FDIVHrr |
| 13383 | 67383393U, // FDIVR_ZPmZ_D |
| 13384 | 101472369U, // FDIVR_ZPmZ_H |
| 13385 | 134504545U, // FDIVR_ZPmZ_S |
| 13386 | 6208U, // FDIVSrr |
| 13387 | 67383393U, // FDIV_ZPmZ_D |
| 13388 | 101472369U, // FDIV_ZPmZ_H |
| 13389 | 134504545U, // FDIV_ZPmZ_S |
| 13390 | 16448U, // FDIVv2f32 |
| 13391 | 16448U, // FDIVv2f64 |
| 13392 | 16448U, // FDIVv4f16 |
| 13393 | 16448U, // FDIVv4f32 |
| 13394 | 16448U, // FDIVv8f16 |
| 13395 | 92865U, // FDOT_VG2_M2Z2Z_BtoH |
| 13396 | 92865U, // FDOT_VG2_M2Z2Z_BtoS |
| 13397 | 3168497U, // FDOT_VG2_M2Z2Z_HtoS |
| 13398 | 5599937U, // FDOT_VG2_M2ZZI_BtoH |
| 13399 | 5599937U, // FDOT_VG2_M2ZZI_BtoS |
| 13400 | 204757233U, // FDOT_VG2_M2ZZI_HtoS |
| 13401 | 94913U, // FDOT_VG2_M2ZZ_BtoH |
| 13402 | 94913U, // FDOT_VG2_M2ZZ_BtoS |
| 13403 | 104093937U, // FDOT_VG2_M2ZZ_HtoS |
| 13404 | 92865U, // FDOT_VG4_M4Z4Z_BtoH |
| 13405 | 92865U, // FDOT_VG4_M4Z4Z_BtoS |
| 13406 | 3168497U, // FDOT_VG4_M4Z4Z_HtoS |
| 13407 | 5599937U, // FDOT_VG4_M4ZZI_BtoH |
| 13408 | 5599937U, // FDOT_VG4_M4ZZI_BtoS |
| 13409 | 204757233U, // FDOT_VG4_M4ZZI_HtoS |
| 13410 | 94913U, // FDOT_VG4_M4ZZ_BtoH |
| 13411 | 94913U, // FDOT_VG4_M4ZZ_BtoS |
| 13412 | 104093937U, // FDOT_VG4_M4ZZ_HtoS |
| 13413 | 77841U, // FDOT_ZZZI_BtoH |
| 13414 | 77843U, // FDOT_ZZZI_BtoS |
| 13415 | 103561281U, // FDOT_ZZZI_S |
| 13416 | 17U, // FDOT_ZZZ_BtoH |
| 13417 | 19U, // FDOT_ZZZ_BtoS |
| 13418 | 14401U, // FDOT_ZZZ_S |
| 13419 | 103565377U, // FDOTlanev16f8 |
| 13420 | 103565377U, // FDOTlanev4f16 |
| 13421 | 103565377U, // FDOTlanev8f16 |
| 13422 | 103565377U, // FDOTlanev8f8 |
| 13423 | 0U, // FDOTv2f32 |
| 13424 | 0U, // FDOTv4f16 |
| 13425 | 0U, // FDOTv4f32 |
| 13426 | 0U, // FDOTv8f16 |
| 13427 | 5U, // FDUP_ZI_D |
| 13428 | 0U, // FDUP_ZI_H |
| 13429 | 5U, // FDUP_ZI_S |
| 13430 | 1U, // FEXPA_ZZ_D |
| 13431 | 0U, // FEXPA_ZZ_H |
| 13432 | 2U, // FEXPA_ZZ_S |
| 13433 | 0U, // FJCVTZS |
| 13434 | 32U, // FLOGB_ZPmZ_D |
| 13435 | 0U, // FLOGB_ZPmZ_H |
| 13436 | 48U, // FLOGB_ZPmZ_S |
| 13437 | 268352U, // FMADDDrrr |
| 13438 | 268352U, // FMADDHrrr |
| 13439 | 268352U, // FMADDSrrr |
| 13440 | 537135201U, // FMAD_ZPmZZ_D |
| 13441 | 104356097U, // FMAD_ZPmZZ_H |
| 13442 | 570691681U, // FMAD_ZPmZZ_S |
| 13443 | 6208U, // FMAXDrr |
| 13444 | 6208U, // FMAXHrr |
| 13445 | 6208U, // FMAXNMDrr |
| 13446 | 6208U, // FMAXNMHrr |
| 13447 | 67383393U, // FMAXNMP_ZPmZZ_D |
| 13448 | 101472369U, // FMAXNMP_ZPmZZ_H |
| 13449 | 134504545U, // FMAXNMP_ZPmZZ_S |
| 13450 | 16448U, // FMAXNMPv2f32 |
| 13451 | 16448U, // FMAXNMPv2f64 |
| 13452 | 0U, // FMAXNMPv2i16p |
| 13453 | 0U, // FMAXNMPv2i32p |
| 13454 | 0U, // FMAXNMPv2i64p |
| 13455 | 16448U, // FMAXNMPv4f16 |
| 13456 | 16448U, // FMAXNMPv4f32 |
| 13457 | 16448U, // FMAXNMPv8f16 |
| 13458 | 12353U, // FMAXNMQV_D |
| 13459 | 10305U, // FMAXNMQV_H |
| 13460 | 24641U, // FMAXNMQV_S |
| 13461 | 6208U, // FMAXNMSrr |
| 13462 | 0U, // FMAXNMV_VPZ_D |
| 13463 | 0U, // FMAXNMV_VPZ_H |
| 13464 | 0U, // FMAXNMV_VPZ_S |
| 13465 | 0U, // FMAXNMVv4i16v |
| 13466 | 0U, // FMAXNMVv4i32v |
| 13467 | 0U, // FMAXNMVv8i16v |
| 13468 | 513U, // FMAXNM_VG2_2Z2Z_D |
| 13469 | 273U, // FMAXNM_VG2_2Z2Z_H |
| 13470 | 529U, // FMAXNM_VG2_2Z2Z_S |
| 13471 | 145U, // FMAXNM_VG2_2ZZ_D |
| 13472 | 113U, // FMAXNM_VG2_2ZZ_H |
| 13473 | 81U, // FMAXNM_VG2_2ZZ_S |
| 13474 | 513U, // FMAXNM_VG4_4Z4Z_D |
| 13475 | 273U, // FMAXNM_VG4_4Z4Z_H |
| 13476 | 529U, // FMAXNM_VG4_4Z4Z_S |
| 13477 | 145U, // FMAXNM_VG4_4ZZ_D |
| 13478 | 113U, // FMAXNM_VG4_4ZZ_H |
| 13479 | 81U, // FMAXNM_VG4_4ZZ_S |
| 13480 | 604254305U, // FMAXNM_ZPmI_D |
| 13481 | 5789809U, // FMAXNM_ZPmI_H |
| 13482 | 604266593U, // FMAXNM_ZPmI_S |
| 13483 | 67383393U, // FMAXNM_ZPmZ_D |
| 13484 | 101472369U, // FMAXNM_ZPmZ_H |
| 13485 | 134504545U, // FMAXNM_ZPmZ_S |
| 13486 | 16448U, // FMAXNMv2f32 |
| 13487 | 16448U, // FMAXNMv2f64 |
| 13488 | 16448U, // FMAXNMv4f16 |
| 13489 | 16448U, // FMAXNMv4f32 |
| 13490 | 16448U, // FMAXNMv8f16 |
| 13491 | 67383393U, // FMAXP_ZPmZZ_D |
| 13492 | 101472369U, // FMAXP_ZPmZZ_H |
| 13493 | 134504545U, // FMAXP_ZPmZZ_S |
| 13494 | 16448U, // FMAXPv2f32 |
| 13495 | 16448U, // FMAXPv2f64 |
| 13496 | 0U, // FMAXPv2i16p |
| 13497 | 0U, // FMAXPv2i32p |
| 13498 | 0U, // FMAXPv2i64p |
| 13499 | 16448U, // FMAXPv4f16 |
| 13500 | 16448U, // FMAXPv4f32 |
| 13501 | 16448U, // FMAXPv8f16 |
| 13502 | 12353U, // FMAXQV_D |
| 13503 | 10305U, // FMAXQV_H |
| 13504 | 24641U, // FMAXQV_S |
| 13505 | 6208U, // FMAXSrr |
| 13506 | 0U, // FMAXV_VPZ_D |
| 13507 | 0U, // FMAXV_VPZ_H |
| 13508 | 0U, // FMAXV_VPZ_S |
| 13509 | 0U, // FMAXVv4i16v |
| 13510 | 0U, // FMAXVv4i32v |
| 13511 | 0U, // FMAXVv8i16v |
| 13512 | 513U, // FMAX_VG2_2Z2Z_D |
| 13513 | 273U, // FMAX_VG2_2Z2Z_H |
| 13514 | 529U, // FMAX_VG2_2Z2Z_S |
| 13515 | 145U, // FMAX_VG2_2ZZ_D |
| 13516 | 113U, // FMAX_VG2_2ZZ_H |
| 13517 | 81U, // FMAX_VG2_2ZZ_S |
| 13518 | 513U, // FMAX_VG4_4Z4Z_D |
| 13519 | 273U, // FMAX_VG4_4Z4Z_H |
| 13520 | 529U, // FMAX_VG4_4Z4Z_S |
| 13521 | 145U, // FMAX_VG4_4ZZ_D |
| 13522 | 113U, // FMAX_VG4_4ZZ_H |
| 13523 | 81U, // FMAX_VG4_4ZZ_S |
| 13524 | 604254305U, // FMAX_ZPmI_D |
| 13525 | 5789809U, // FMAX_ZPmI_H |
| 13526 | 604266593U, // FMAX_ZPmI_S |
| 13527 | 67383393U, // FMAX_ZPmZ_D |
| 13528 | 101472369U, // FMAX_ZPmZ_H |
| 13529 | 134504545U, // FMAX_ZPmZ_S |
| 13530 | 16448U, // FMAXv2f32 |
| 13531 | 16448U, // FMAXv2f64 |
| 13532 | 16448U, // FMAXv4f16 |
| 13533 | 16448U, // FMAXv4f32 |
| 13534 | 16448U, // FMAXv8f16 |
| 13535 | 6208U, // FMINDrr |
| 13536 | 6208U, // FMINHrr |
| 13537 | 6208U, // FMINNMDrr |
| 13538 | 6208U, // FMINNMHrr |
| 13539 | 67383393U, // FMINNMP_ZPmZZ_D |
| 13540 | 101472369U, // FMINNMP_ZPmZZ_H |
| 13541 | 134504545U, // FMINNMP_ZPmZZ_S |
| 13542 | 16448U, // FMINNMPv2f32 |
| 13543 | 16448U, // FMINNMPv2f64 |
| 13544 | 0U, // FMINNMPv2i16p |
| 13545 | 0U, // FMINNMPv2i32p |
| 13546 | 0U, // FMINNMPv2i64p |
| 13547 | 16448U, // FMINNMPv4f16 |
| 13548 | 16448U, // FMINNMPv4f32 |
| 13549 | 16448U, // FMINNMPv8f16 |
| 13550 | 12353U, // FMINNMQV_D |
| 13551 | 10305U, // FMINNMQV_H |
| 13552 | 24641U, // FMINNMQV_S |
| 13553 | 6208U, // FMINNMSrr |
| 13554 | 0U, // FMINNMV_VPZ_D |
| 13555 | 0U, // FMINNMV_VPZ_H |
| 13556 | 0U, // FMINNMV_VPZ_S |
| 13557 | 0U, // FMINNMVv4i16v |
| 13558 | 0U, // FMINNMVv4i32v |
| 13559 | 0U, // FMINNMVv8i16v |
| 13560 | 513U, // FMINNM_VG2_2Z2Z_D |
| 13561 | 273U, // FMINNM_VG2_2Z2Z_H |
| 13562 | 529U, // FMINNM_VG2_2Z2Z_S |
| 13563 | 145U, // FMINNM_VG2_2ZZ_D |
| 13564 | 113U, // FMINNM_VG2_2ZZ_H |
| 13565 | 81U, // FMINNM_VG2_2ZZ_S |
| 13566 | 513U, // FMINNM_VG4_4Z4Z_D |
| 13567 | 273U, // FMINNM_VG4_4Z4Z_H |
| 13568 | 529U, // FMINNM_VG4_4Z4Z_S |
| 13569 | 145U, // FMINNM_VG4_4ZZ_D |
| 13570 | 113U, // FMINNM_VG4_4ZZ_H |
| 13571 | 81U, // FMINNM_VG4_4ZZ_S |
| 13572 | 604254305U, // FMINNM_ZPmI_D |
| 13573 | 5789809U, // FMINNM_ZPmI_H |
| 13574 | 604266593U, // FMINNM_ZPmI_S |
| 13575 | 67383393U, // FMINNM_ZPmZ_D |
| 13576 | 101472369U, // FMINNM_ZPmZ_H |
| 13577 | 134504545U, // FMINNM_ZPmZ_S |
| 13578 | 16448U, // FMINNMv2f32 |
| 13579 | 16448U, // FMINNMv2f64 |
| 13580 | 16448U, // FMINNMv4f16 |
| 13581 | 16448U, // FMINNMv4f32 |
| 13582 | 16448U, // FMINNMv8f16 |
| 13583 | 67383393U, // FMINP_ZPmZZ_D |
| 13584 | 101472369U, // FMINP_ZPmZZ_H |
| 13585 | 134504545U, // FMINP_ZPmZZ_S |
| 13586 | 16448U, // FMINPv2f32 |
| 13587 | 16448U, // FMINPv2f64 |
| 13588 | 0U, // FMINPv2i16p |
| 13589 | 0U, // FMINPv2i32p |
| 13590 | 0U, // FMINPv2i64p |
| 13591 | 16448U, // FMINPv4f16 |
| 13592 | 16448U, // FMINPv4f32 |
| 13593 | 16448U, // FMINPv8f16 |
| 13594 | 12353U, // FMINQV_D |
| 13595 | 10305U, // FMINQV_H |
| 13596 | 24641U, // FMINQV_S |
| 13597 | 6208U, // FMINSrr |
| 13598 | 0U, // FMINV_VPZ_D |
| 13599 | 0U, // FMINV_VPZ_H |
| 13600 | 0U, // FMINV_VPZ_S |
| 13601 | 0U, // FMINVv4i16v |
| 13602 | 0U, // FMINVv4i32v |
| 13603 | 0U, // FMINVv8i16v |
| 13604 | 513U, // FMIN_VG2_2Z2Z_D |
| 13605 | 273U, // FMIN_VG2_2Z2Z_H |
| 13606 | 529U, // FMIN_VG2_2Z2Z_S |
| 13607 | 145U, // FMIN_VG2_2ZZ_D |
| 13608 | 113U, // FMIN_VG2_2ZZ_H |
| 13609 | 81U, // FMIN_VG2_2ZZ_S |
| 13610 | 513U, // FMIN_VG4_4Z4Z_D |
| 13611 | 273U, // FMIN_VG4_4Z4Z_H |
| 13612 | 529U, // FMIN_VG4_4Z4Z_S |
| 13613 | 145U, // FMIN_VG4_4ZZ_D |
| 13614 | 113U, // FMIN_VG4_4ZZ_H |
| 13615 | 81U, // FMIN_VG4_4ZZ_S |
| 13616 | 604254305U, // FMIN_ZPmI_D |
| 13617 | 5789809U, // FMIN_ZPmI_H |
| 13618 | 604266593U, // FMIN_ZPmI_S |
| 13619 | 67383393U, // FMIN_ZPmZ_D |
| 13620 | 101472369U, // FMIN_ZPmZ_H |
| 13621 | 134504545U, // FMIN_ZPmZ_S |
| 13622 | 16448U, // FMINv2f32 |
| 13623 | 16448U, // FMINv2f64 |
| 13624 | 16448U, // FMINv4f16 |
| 13625 | 16448U, // FMINv4f32 |
| 13626 | 16448U, // FMINv8f16 |
| 13627 | 103565377U, // FMLAL2lanev4f16 |
| 13628 | 103565377U, // FMLAL2lanev8f16 |
| 13629 | 0U, // FMLAL2v4f16 |
| 13630 | 0U, // FMLAL2v8f16 |
| 13631 | 17U, // FMLALB_ZZZ |
| 13632 | 77841U, // FMLALB_ZZZI |
| 13633 | 103561281U, // FMLALB_ZZZI_SHH |
| 13634 | 14401U, // FMLALB_ZZZ_SHH |
| 13635 | 103565377U, // FMLALBlanev8f16 |
| 13636 | 0U, // FMLALBv8f16 |
| 13637 | 19U, // FMLALLBB_ZZZ |
| 13638 | 77843U, // FMLALLBB_ZZZI |
| 13639 | 103565377U, // FMLALLBBlanev4f32 |
| 13640 | 0U, // FMLALLBBv4f32 |
| 13641 | 19U, // FMLALLBT_ZZZ |
| 13642 | 77843U, // FMLALLBT_ZZZI |
| 13643 | 103565377U, // FMLALLBTlanev4f32 |
| 13644 | 0U, // FMLALLBTv4f32 |
| 13645 | 19U, // FMLALLTB_ZZZ |
| 13646 | 77843U, // FMLALLTB_ZZZI |
| 13647 | 103565377U, // FMLALLTBlanev4f32 |
| 13648 | 0U, // FMLALLTBv4f32 |
| 13649 | 19U, // FMLALLTT_ZZZ |
| 13650 | 77843U, // FMLALLTT_ZZZI |
| 13651 | 103565377U, // FMLALLTTlanev4f32 |
| 13652 | 0U, // FMLALLTTv4f32 |
| 13653 | 76498U, // FMLALL_MZZI_BtoS |
| 13654 | 722U, // FMLALL_MZZ_BtoS |
| 13655 | 92865U, // FMLALL_VG2_M2Z2Z_BtoS |
| 13656 | 5599937U, // FMLALL_VG2_M2ZZI_BtoS |
| 13657 | 94917U, // FMLALL_VG2_M2ZZ_BtoS |
| 13658 | 92865U, // FMLALL_VG4_M4Z4Z_BtoS |
| 13659 | 5599937U, // FMLALL_VG4_M4ZZI_BtoS |
| 13660 | 94918U, // FMLALL_VG4_M4ZZ_BtoS |
| 13661 | 17U, // FMLALT_ZZZ |
| 13662 | 77841U, // FMLALT_ZZZI |
| 13663 | 103561281U, // FMLALT_ZZZI_SHH |
| 13664 | 14401U, // FMLALT_ZZZ_SHH |
| 13665 | 103565377U, // FMLALTlanev8f16 |
| 13666 | 0U, // FMLALTv8f16 |
| 13667 | 76498U, // FMLAL_MZZI_BtoH |
| 13668 | 76066U, // FMLAL_MZZI_HtoS |
| 13669 | 290U, // FMLAL_MZZ_HtoS |
| 13670 | 92865U, // FMLAL_VG2_M2Z2Z_BtoH |
| 13671 | 3168497U, // FMLAL_VG2_M2Z2Z_HtoS |
| 13672 | 5599937U, // FMLAL_VG2_M2ZZI_BtoH |
| 13673 | 204757233U, // FMLAL_VG2_M2ZZI_HtoS |
| 13674 | 94913U, // FMLAL_VG2_M2ZZ_BtoH |
| 13675 | 104093937U, // FMLAL_VG2_M2ZZ_HtoS |
| 13676 | 722U, // FMLAL_VG2_MZZ_BtoH |
| 13677 | 92865U, // FMLAL_VG4_M4Z4Z_BtoH |
| 13678 | 3168497U, // FMLAL_VG4_M4Z4Z_HtoS |
| 13679 | 5599937U, // FMLAL_VG4_M4ZZI_BtoH |
| 13680 | 204757233U, // FMLAL_VG4_M4ZZI_HtoS |
| 13681 | 94913U, // FMLAL_VG4_M4ZZ_BtoH |
| 13682 | 104093937U, // FMLAL_VG4_M4ZZ_HtoS |
| 13683 | 103565377U, // FMLALlanev4f16 |
| 13684 | 103565377U, // FMLALlanev8f16 |
| 13685 | 0U, // FMLALv4f16 |
| 13686 | 0U, // FMLALv8f16 |
| 13687 | 1333409U, // FMLA_VG2_M2Z2Z_D |
| 13688 | 1595569U, // FMLA_VG2_M2Z2Z_S |
| 13689 | 3168497U, // FMLA_VG2_M2Z4Z_H |
| 13690 | 203184289U, // FMLA_VG2_M2ZZI_D |
| 13691 | 204757233U, // FMLA_VG2_M2ZZI_H |
| 13692 | 203446449U, // FMLA_VG2_M2ZZI_S |
| 13693 | 102520993U, // FMLA_VG2_M2ZZ_D |
| 13694 | 104093937U, // FMLA_VG2_M2ZZ_H |
| 13695 | 102783153U, // FMLA_VG2_M2ZZ_S |
| 13696 | 1333409U, // FMLA_VG4_M4Z4Z_D |
| 13697 | 3168497U, // FMLA_VG4_M4Z4Z_H |
| 13698 | 1595569U, // FMLA_VG4_M4Z4Z_S |
| 13699 | 203184289U, // FMLA_VG4_M4ZZI_D |
| 13700 | 204757233U, // FMLA_VG4_M4ZZI_H |
| 13701 | 203446449U, // FMLA_VG4_M4ZZI_S |
| 13702 | 102520993U, // FMLA_VG4_M4ZZ_D |
| 13703 | 104093937U, // FMLA_VG4_M4ZZ_H |
| 13704 | 102783153U, // FMLA_VG4_M4ZZ_S |
| 13705 | 537135201U, // FMLA_ZPmZZ_D |
| 13706 | 104356097U, // FMLA_ZPmZZ_H |
| 13707 | 570691681U, // FMLA_ZPmZZ_S |
| 13708 | 103548992U, // FMLA_ZZZI_D |
| 13709 | 78081U, // FMLA_ZZZI_H |
| 13710 | 103551040U, // FMLA_ZZZI_S |
| 13711 | 103565378U, // FMLAv1i16_indexed |
| 13712 | 103565378U, // FMLAv1i32_indexed |
| 13713 | 103565378U, // FMLAv1i64_indexed |
| 13714 | 18497U, // FMLAv2f32 |
| 13715 | 18497U, // FMLAv2f64 |
| 13716 | 103565377U, // FMLAv2i32_indexed |
| 13717 | 103565377U, // FMLAv2i64_indexed |
| 13718 | 18497U, // FMLAv4f16 |
| 13719 | 18497U, // FMLAv4f32 |
| 13720 | 103565377U, // FMLAv4i16_indexed |
| 13721 | 103565377U, // FMLAv4i32_indexed |
| 13722 | 18497U, // FMLAv8f16 |
| 13723 | 103565377U, // FMLAv8i16_indexed |
| 13724 | 103565377U, // FMLSL2lanev4f16 |
| 13725 | 103565377U, // FMLSL2lanev8f16 |
| 13726 | 0U, // FMLSL2v4f16 |
| 13727 | 0U, // FMLSL2v8f16 |
| 13728 | 103561281U, // FMLSLB_ZZZI_SHH |
| 13729 | 14401U, // FMLSLB_ZZZ_SHH |
| 13730 | 103561281U, // FMLSLT_ZZZI_SHH |
| 13731 | 14401U, // FMLSLT_ZZZ_SHH |
| 13732 | 76066U, // FMLSL_MZZI_HtoS |
| 13733 | 290U, // FMLSL_MZZ_HtoS |
| 13734 | 3168497U, // FMLSL_VG2_M2Z2Z_HtoS |
| 13735 | 204757233U, // FMLSL_VG2_M2ZZI_HtoS |
| 13736 | 104093937U, // FMLSL_VG2_M2ZZ_HtoS |
| 13737 | 3168497U, // FMLSL_VG4_M4Z4Z_HtoS |
| 13738 | 204757233U, // FMLSL_VG4_M4ZZI_HtoS |
| 13739 | 104093937U, // FMLSL_VG4_M4ZZ_HtoS |
| 13740 | 103565377U, // FMLSLlanev4f16 |
| 13741 | 103565377U, // FMLSLlanev8f16 |
| 13742 | 0U, // FMLSLv4f16 |
| 13743 | 0U, // FMLSLv8f16 |
| 13744 | 1333409U, // FMLS_VG2_M2Z2Z_D |
| 13745 | 3168497U, // FMLS_VG2_M2Z2Z_H |
| 13746 | 1595569U, // FMLS_VG2_M2Z2Z_S |
| 13747 | 203184289U, // FMLS_VG2_M2ZZI_D |
| 13748 | 204757233U, // FMLS_VG2_M2ZZI_H |
| 13749 | 203446449U, // FMLS_VG2_M2ZZI_S |
| 13750 | 102520993U, // FMLS_VG2_M2ZZ_D |
| 13751 | 104093937U, // FMLS_VG2_M2ZZ_H |
| 13752 | 102783153U, // FMLS_VG2_M2ZZ_S |
| 13753 | 3168497U, // FMLS_VG4_M4Z2Z_H |
| 13754 | 1333409U, // FMLS_VG4_M4Z4Z_D |
| 13755 | 1595569U, // FMLS_VG4_M4Z4Z_S |
| 13756 | 203184289U, // FMLS_VG4_M4ZZI_D |
| 13757 | 204757233U, // FMLS_VG4_M4ZZI_H |
| 13758 | 203446449U, // FMLS_VG4_M4ZZI_S |
| 13759 | 102520993U, // FMLS_VG4_M4ZZ_D |
| 13760 | 104093937U, // FMLS_VG4_M4ZZ_H |
| 13761 | 102783153U, // FMLS_VG4_M4ZZ_S |
| 13762 | 537135201U, // FMLS_ZPmZZ_D |
| 13763 | 104356097U, // FMLS_ZPmZZ_H |
| 13764 | 570691681U, // FMLS_ZPmZZ_S |
| 13765 | 103548992U, // FMLS_ZZZI_D |
| 13766 | 78081U, // FMLS_ZZZI_H |
| 13767 | 103551040U, // FMLS_ZZZI_S |
| 13768 | 103565378U, // FMLSv1i16_indexed |
| 13769 | 103565378U, // FMLSv1i32_indexed |
| 13770 | 103565378U, // FMLSv1i64_indexed |
| 13771 | 18497U, // FMLSv2f32 |
| 13772 | 18497U, // FMLSv2f64 |
| 13773 | 103565377U, // FMLSv2i32_indexed |
| 13774 | 103565377U, // FMLSv2i64_indexed |
| 13775 | 18497U, // FMLSv4f16 |
| 13776 | 18497U, // FMLSv4f32 |
| 13777 | 103565377U, // FMLSv4i16_indexed |
| 13778 | 103565377U, // FMLSv4i32_indexed |
| 13779 | 18497U, // FMLSv8f16 |
| 13780 | 103565377U, // FMLSv8i16_indexed |
| 13781 | 2112U, // FMMLA_ZZZ_D |
| 13782 | 4160U, // FMMLA_ZZZ_S |
| 13783 | 0U, // FMOPAL_MPPZZ |
| 13784 | 0U, // FMOPA_MPPZZ_BtoH |
| 13785 | 0U, // FMOPA_MPPZZ_BtoS |
| 13786 | 737U, // FMOPA_MPPZZ_D |
| 13787 | 0U, // FMOPA_MPPZZ_H |
| 13788 | 305U, // FMOPA_MPPZZ_S |
| 13789 | 0U, // FMOPSL_MPPZZ |
| 13790 | 737U, // FMOPS_MPPZZ_D |
| 13791 | 0U, // FMOPS_MPPZZ_H |
| 13792 | 305U, // FMOPS_MPPZZ_S |
| 13793 | 448U, // FMOVDXHighr |
| 13794 | 0U, // FMOVDXr |
| 13795 | 5U, // FMOVDi |
| 13796 | 0U, // FMOVDr |
| 13797 | 0U, // FMOVHWr |
| 13798 | 0U, // FMOVHXr |
| 13799 | 5U, // FMOVHi |
| 13800 | 0U, // FMOVHr |
| 13801 | 0U, // FMOVSWr |
| 13802 | 5U, // FMOVSi |
| 13803 | 0U, // FMOVSr |
| 13804 | 0U, // FMOVWHr |
| 13805 | 0U, // FMOVWSr |
| 13806 | 0U, // FMOVXDHighr |
| 13807 | 0U, // FMOVXDr |
| 13808 | 0U, // FMOVXHr |
| 13809 | 5U, // FMOVv2f32_ns |
| 13810 | 5U, // FMOVv2f64_ns |
| 13811 | 5U, // FMOVv4f16_ns |
| 13812 | 5U, // FMOVv4f32_ns |
| 13813 | 5U, // FMOVv8f16_ns |
| 13814 | 537135201U, // FMSB_ZPmZZ_D |
| 13815 | 104356097U, // FMSB_ZPmZZ_H |
| 13816 | 570691681U, // FMSB_ZPmZZ_S |
| 13817 | 268352U, // FMSUBDrrr |
| 13818 | 268352U, // FMSUBHrrr |
| 13819 | 268352U, // FMSUBSrrr |
| 13820 | 6208U, // FMULDrr |
| 13821 | 6208U, // FMULHrr |
| 13822 | 6208U, // FMULSrr |
| 13823 | 6208U, // FMULX16 |
| 13824 | 6208U, // FMULX32 |
| 13825 | 6208U, // FMULX64 |
| 13826 | 67383393U, // FMULX_ZPmZ_D |
| 13827 | 101472369U, // FMULX_ZPmZ_H |
| 13828 | 134504545U, // FMULX_ZPmZ_S |
| 13829 | 6045760U, // FMULXv1i16_indexed |
| 13830 | 6045760U, // FMULXv1i32_indexed |
| 13831 | 6045760U, // FMULXv1i64_indexed |
| 13832 | 16448U, // FMULXv2f32 |
| 13833 | 16448U, // FMULXv2f64 |
| 13834 | 6045760U, // FMULXv2i32_indexed |
| 13835 | 6045760U, // FMULXv2i64_indexed |
| 13836 | 16448U, // FMULXv4f16 |
| 13837 | 16448U, // FMULXv4f32 |
| 13838 | 6045760U, // FMULXv4i16_indexed |
| 13839 | 6045760U, // FMULXv4i32_indexed |
| 13840 | 16448U, // FMULXv8f16 |
| 13841 | 6045760U, // FMULXv8i16_indexed |
| 13842 | 637808737U, // FMUL_ZPmI_D |
| 13843 | 6314097U, // FMUL_ZPmI_H |
| 13844 | 637821025U, // FMUL_ZPmI_S |
| 13845 | 67383393U, // FMUL_ZPmZ_D |
| 13846 | 101472369U, // FMUL_ZPmZ_H |
| 13847 | 134504545U, // FMUL_ZPmZ_S |
| 13848 | 6041665U, // FMUL_ZZZI_D |
| 13849 | 79985U, // FMUL_ZZZI_H |
| 13850 | 6053954U, // FMUL_ZZZI_S |
| 13851 | 12353U, // FMUL_ZZZ_D |
| 13852 | 113U, // FMUL_ZZZ_H |
| 13853 | 24642U, // FMUL_ZZZ_S |
| 13854 | 6045760U, // FMULv1i16_indexed |
| 13855 | 6045760U, // FMULv1i32_indexed |
| 13856 | 6045760U, // FMULv1i64_indexed |
| 13857 | 16448U, // FMULv2f32 |
| 13858 | 16448U, // FMULv2f64 |
| 13859 | 6045760U, // FMULv2i32_indexed |
| 13860 | 6045760U, // FMULv2i64_indexed |
| 13861 | 16448U, // FMULv4f16 |
| 13862 | 16448U, // FMULv4f32 |
| 13863 | 6045760U, // FMULv4i16_indexed |
| 13864 | 6045760U, // FMULv4i32_indexed |
| 13865 | 16448U, // FMULv8f16 |
| 13866 | 6045760U, // FMULv8i16_indexed |
| 13867 | 0U, // FNEGDr |
| 13868 | 0U, // FNEGHr |
| 13869 | 0U, // FNEGSr |
| 13870 | 32U, // FNEG_ZPmZ_D |
| 13871 | 0U, // FNEG_ZPmZ_H |
| 13872 | 48U, // FNEG_ZPmZ_S |
| 13873 | 0U, // FNEGv2f32 |
| 13874 | 0U, // FNEGv2f64 |
| 13875 | 0U, // FNEGv4f16 |
| 13876 | 0U, // FNEGv4f32 |
| 13877 | 0U, // FNEGv8f16 |
| 13878 | 268352U, // FNMADDDrrr |
| 13879 | 268352U, // FNMADDHrrr |
| 13880 | 268352U, // FNMADDSrrr |
| 13881 | 537135201U, // FNMAD_ZPmZZ_D |
| 13882 | 104356097U, // FNMAD_ZPmZZ_H |
| 13883 | 570691681U, // FNMAD_ZPmZZ_S |
| 13884 | 537135201U, // FNMLA_ZPmZZ_D |
| 13885 | 104356097U, // FNMLA_ZPmZZ_H |
| 13886 | 570691681U, // FNMLA_ZPmZZ_S |
| 13887 | 537135201U, // FNMLS_ZPmZZ_D |
| 13888 | 104356097U, // FNMLS_ZPmZZ_H |
| 13889 | 570691681U, // FNMLS_ZPmZZ_S |
| 13890 | 537135201U, // FNMSB_ZPmZZ_D |
| 13891 | 104356097U, // FNMSB_ZPmZZ_H |
| 13892 | 570691681U, // FNMSB_ZPmZZ_S |
| 13893 | 268352U, // FNMSUBDrrr |
| 13894 | 268352U, // FNMSUBHrrr |
| 13895 | 268352U, // FNMSUBSrrr |
| 13896 | 6208U, // FNMULDrr |
| 13897 | 6208U, // FNMULHrr |
| 13898 | 6208U, // FNMULSrr |
| 13899 | 1U, // FRECPE_ZZ_D |
| 13900 | 0U, // FRECPE_ZZ_H |
| 13901 | 2U, // FRECPE_ZZ_S |
| 13902 | 0U, // FRECPEv1f16 |
| 13903 | 0U, // FRECPEv1i32 |
| 13904 | 0U, // FRECPEv1i64 |
| 13905 | 0U, // FRECPEv2f32 |
| 13906 | 0U, // FRECPEv2f64 |
| 13907 | 0U, // FRECPEv4f16 |
| 13908 | 0U, // FRECPEv4f32 |
| 13909 | 0U, // FRECPEv8f16 |
| 13910 | 6208U, // FRECPS16 |
| 13911 | 6208U, // FRECPS32 |
| 13912 | 6208U, // FRECPS64 |
| 13913 | 12353U, // FRECPS_ZZZ_D |
| 13914 | 113U, // FRECPS_ZZZ_H |
| 13915 | 24642U, // FRECPS_ZZZ_S |
| 13916 | 16448U, // FRECPSv2f32 |
| 13917 | 16448U, // FRECPSv2f64 |
| 13918 | 16448U, // FRECPSv4f16 |
| 13919 | 16448U, // FRECPSv4f32 |
| 13920 | 16448U, // FRECPSv8f16 |
| 13921 | 32U, // FRECPX_ZPmZ_D |
| 13922 | 0U, // FRECPX_ZPmZ_H |
| 13923 | 48U, // FRECPX_ZPmZ_S |
| 13924 | 0U, // FRECPXv1f16 |
| 13925 | 0U, // FRECPXv1i32 |
| 13926 | 0U, // FRECPXv1i64 |
| 13927 | 0U, // FRINT32XDr |
| 13928 | 0U, // FRINT32XSr |
| 13929 | 0U, // FRINT32Xv2f32 |
| 13930 | 0U, // FRINT32Xv2f64 |
| 13931 | 0U, // FRINT32Xv4f32 |
| 13932 | 0U, // FRINT32ZDr |
| 13933 | 0U, // FRINT32ZSr |
| 13934 | 0U, // FRINT32Zv2f32 |
| 13935 | 0U, // FRINT32Zv2f64 |
| 13936 | 0U, // FRINT32Zv4f32 |
| 13937 | 0U, // FRINT64XDr |
| 13938 | 0U, // FRINT64XSr |
| 13939 | 0U, // FRINT64Xv2f32 |
| 13940 | 0U, // FRINT64Xv2f64 |
| 13941 | 0U, // FRINT64Xv4f32 |
| 13942 | 0U, // FRINT64ZDr |
| 13943 | 0U, // FRINT64ZSr |
| 13944 | 0U, // FRINT64Zv2f32 |
| 13945 | 0U, // FRINT64Zv2f64 |
| 13946 | 0U, // FRINT64Zv4f32 |
| 13947 | 0U, // FRINTADr |
| 13948 | 0U, // FRINTAHr |
| 13949 | 0U, // FRINTASr |
| 13950 | 0U, // FRINTA_2Z2Z_S |
| 13951 | 0U, // FRINTA_4Z4Z_S |
| 13952 | 32U, // FRINTA_ZPmZ_D |
| 13953 | 0U, // FRINTA_ZPmZ_H |
| 13954 | 48U, // FRINTA_ZPmZ_S |
| 13955 | 0U, // FRINTAv2f32 |
| 13956 | 0U, // FRINTAv2f64 |
| 13957 | 0U, // FRINTAv4f16 |
| 13958 | 0U, // FRINTAv4f32 |
| 13959 | 0U, // FRINTAv8f16 |
| 13960 | 0U, // FRINTIDr |
| 13961 | 0U, // FRINTIHr |
| 13962 | 0U, // FRINTISr |
| 13963 | 32U, // FRINTI_ZPmZ_D |
| 13964 | 0U, // FRINTI_ZPmZ_H |
| 13965 | 48U, // FRINTI_ZPmZ_S |
| 13966 | 0U, // FRINTIv2f32 |
| 13967 | 0U, // FRINTIv2f64 |
| 13968 | 0U, // FRINTIv4f16 |
| 13969 | 0U, // FRINTIv4f32 |
| 13970 | 0U, // FRINTIv8f16 |
| 13971 | 0U, // FRINTMDr |
| 13972 | 0U, // FRINTMHr |
| 13973 | 0U, // FRINTMSr |
| 13974 | 0U, // FRINTM_2Z2Z_S |
| 13975 | 0U, // FRINTM_4Z4Z_S |
| 13976 | 32U, // FRINTM_ZPmZ_D |
| 13977 | 0U, // FRINTM_ZPmZ_H |
| 13978 | 48U, // FRINTM_ZPmZ_S |
| 13979 | 0U, // FRINTMv2f32 |
| 13980 | 0U, // FRINTMv2f64 |
| 13981 | 0U, // FRINTMv4f16 |
| 13982 | 0U, // FRINTMv4f32 |
| 13983 | 0U, // FRINTMv8f16 |
| 13984 | 0U, // FRINTNDr |
| 13985 | 0U, // FRINTNHr |
| 13986 | 0U, // FRINTNSr |
| 13987 | 0U, // FRINTN_2Z2Z_S |
| 13988 | 0U, // FRINTN_4Z4Z_S |
| 13989 | 32U, // FRINTN_ZPmZ_D |
| 13990 | 0U, // FRINTN_ZPmZ_H |
| 13991 | 48U, // FRINTN_ZPmZ_S |
| 13992 | 0U, // FRINTNv2f32 |
| 13993 | 0U, // FRINTNv2f64 |
| 13994 | 0U, // FRINTNv4f16 |
| 13995 | 0U, // FRINTNv4f32 |
| 13996 | 0U, // FRINTNv8f16 |
| 13997 | 0U, // FRINTPDr |
| 13998 | 0U, // FRINTPHr |
| 13999 | 0U, // FRINTPSr |
| 14000 | 0U, // FRINTP_2Z2Z_S |
| 14001 | 0U, // FRINTP_4Z4Z_S |
| 14002 | 32U, // FRINTP_ZPmZ_D |
| 14003 | 0U, // FRINTP_ZPmZ_H |
| 14004 | 48U, // FRINTP_ZPmZ_S |
| 14005 | 0U, // FRINTPv2f32 |
| 14006 | 0U, // FRINTPv2f64 |
| 14007 | 0U, // FRINTPv4f16 |
| 14008 | 0U, // FRINTPv4f32 |
| 14009 | 0U, // FRINTPv8f16 |
| 14010 | 0U, // FRINTXDr |
| 14011 | 0U, // FRINTXHr |
| 14012 | 0U, // FRINTXSr |
| 14013 | 32U, // FRINTX_ZPmZ_D |
| 14014 | 0U, // FRINTX_ZPmZ_H |
| 14015 | 48U, // FRINTX_ZPmZ_S |
| 14016 | 0U, // FRINTXv2f32 |
| 14017 | 0U, // FRINTXv2f64 |
| 14018 | 0U, // FRINTXv4f16 |
| 14019 | 0U, // FRINTXv4f32 |
| 14020 | 0U, // FRINTXv8f16 |
| 14021 | 0U, // FRINTZDr |
| 14022 | 0U, // FRINTZHr |
| 14023 | 0U, // FRINTZSr |
| 14024 | 32U, // FRINTZ_ZPmZ_D |
| 14025 | 0U, // FRINTZ_ZPmZ_H |
| 14026 | 48U, // FRINTZ_ZPmZ_S |
| 14027 | 0U, // FRINTZv2f32 |
| 14028 | 0U, // FRINTZv2f64 |
| 14029 | 0U, // FRINTZv4f16 |
| 14030 | 0U, // FRINTZv4f32 |
| 14031 | 0U, // FRINTZv8f16 |
| 14032 | 1U, // FRSQRTE_ZZ_D |
| 14033 | 0U, // FRSQRTE_ZZ_H |
| 14034 | 2U, // FRSQRTE_ZZ_S |
| 14035 | 0U, // FRSQRTEv1f16 |
| 14036 | 0U, // FRSQRTEv1i32 |
| 14037 | 0U, // FRSQRTEv1i64 |
| 14038 | 0U, // FRSQRTEv2f32 |
| 14039 | 0U, // FRSQRTEv2f64 |
| 14040 | 0U, // FRSQRTEv4f16 |
| 14041 | 0U, // FRSQRTEv4f32 |
| 14042 | 0U, // FRSQRTEv8f16 |
| 14043 | 6208U, // FRSQRTS16 |
| 14044 | 6208U, // FRSQRTS32 |
| 14045 | 6208U, // FRSQRTS64 |
| 14046 | 12353U, // FRSQRTS_ZZZ_D |
| 14047 | 113U, // FRSQRTS_ZZZ_H |
| 14048 | 24642U, // FRSQRTS_ZZZ_S |
| 14049 | 16448U, // FRSQRTSv2f32 |
| 14050 | 16448U, // FRSQRTSv2f64 |
| 14051 | 16448U, // FRSQRTSv4f16 |
| 14052 | 16448U, // FRSQRTSv4f32 |
| 14053 | 16448U, // FRSQRTSv8f16 |
| 14054 | 513U, // FSCALE_2Z2Z_D |
| 14055 | 273U, // FSCALE_2Z2Z_H |
| 14056 | 529U, // FSCALE_2Z2Z_S |
| 14057 | 145U, // FSCALE_2ZZ_D |
| 14058 | 113U, // FSCALE_2ZZ_H |
| 14059 | 81U, // FSCALE_2ZZ_S |
| 14060 | 513U, // FSCALE_4Z4Z_D |
| 14061 | 273U, // FSCALE_4Z4Z_H |
| 14062 | 529U, // FSCALE_4Z4Z_S |
| 14063 | 145U, // FSCALE_4ZZ_D |
| 14064 | 113U, // FSCALE_4ZZ_H |
| 14065 | 81U, // FSCALE_4ZZ_S |
| 14066 | 67383393U, // FSCALE_ZPmZ_D |
| 14067 | 101472369U, // FSCALE_ZPmZ_H |
| 14068 | 134504545U, // FSCALE_ZPmZ_S |
| 14069 | 16448U, // FSCALEv2f32 |
| 14070 | 16448U, // FSCALEv2f64 |
| 14071 | 16448U, // FSCALEv4f16 |
| 14072 | 16448U, // FSCALEv4f32 |
| 14073 | 16448U, // FSCALEv8f16 |
| 14074 | 0U, // FSQRTDr |
| 14075 | 0U, // FSQRTHr |
| 14076 | 0U, // FSQRTSr |
| 14077 | 32U, // FSQRT_ZPmZ_D |
| 14078 | 0U, // FSQRT_ZPmZ_H |
| 14079 | 48U, // FSQRT_ZPmZ_S |
| 14080 | 0U, // FSQRTv2f32 |
| 14081 | 0U, // FSQRTv2f64 |
| 14082 | 0U, // FSQRTv4f16 |
| 14083 | 0U, // FSQRTv4f32 |
| 14084 | 0U, // FSQRTv8f16 |
| 14085 | 6208U, // FSUBDrr |
| 14086 | 6208U, // FSUBHrr |
| 14087 | 503591009U, // FSUBR_ZPmI_D |
| 14088 | 5003377U, // FSUBR_ZPmI_H |
| 14089 | 503603297U, // FSUBR_ZPmI_S |
| 14090 | 67383393U, // FSUBR_ZPmZ_D |
| 14091 | 101472369U, // FSUBR_ZPmZ_H |
| 14092 | 134504545U, // FSUBR_ZPmZ_S |
| 14093 | 6208U, // FSUBSrr |
| 14094 | 161U, // FSUB_VG2_M2Z_D |
| 14095 | 241U, // FSUB_VG2_M2Z_H |
| 14096 | 177U, // FSUB_VG2_M2Z_S |
| 14097 | 161U, // FSUB_VG4_M4Z_D |
| 14098 | 241U, // FSUB_VG4_M4Z_H |
| 14099 | 177U, // FSUB_VG4_M4Z_S |
| 14100 | 503591009U, // FSUB_ZPmI_D |
| 14101 | 5003377U, // FSUB_ZPmI_H |
| 14102 | 503603297U, // FSUB_ZPmI_S |
| 14103 | 67383393U, // FSUB_ZPmZ_D |
| 14104 | 101472369U, // FSUB_ZPmZ_H |
| 14105 | 134504545U, // FSUB_ZPmZ_S |
| 14106 | 12353U, // FSUB_ZZZ_D |
| 14107 | 113U, // FSUB_ZZZ_H |
| 14108 | 24642U, // FSUB_ZZZ_S |
| 14109 | 16448U, // FSUBv2f32 |
| 14110 | 16448U, // FSUBv2f64 |
| 14111 | 16448U, // FSUBv4f16 |
| 14112 | 16448U, // FSUBv4f32 |
| 14113 | 16448U, // FSUBv8f16 |
| 14114 | 274497U, // FTMAD_ZZI_D |
| 14115 | 103045233U, // FTMAD_ZZI_H |
| 14116 | 286786U, // FTMAD_ZZI_S |
| 14117 | 12353U, // FTSMUL_ZZZ_D |
| 14118 | 113U, // FTSMUL_ZZZ_H |
| 14119 | 24642U, // FTSMUL_ZZZ_S |
| 14120 | 12353U, // FTSSEL_ZZZ_D |
| 14121 | 113U, // FTSSEL_ZZZ_H |
| 14122 | 24642U, // FTSSEL_ZZZ_S |
| 14123 | 0U, // FVDOTB_VG4_M2ZZI_BtoS |
| 14124 | 0U, // FVDOTT_VG4_M2ZZI_BtoS |
| 14125 | 5599937U, // FVDOT_VG2_M2ZZI_BtoH |
| 14126 | 204757233U, // FVDOT_VG2_M2ZZI_HtoS |
| 14127 | 0U, // GCSPOPCX |
| 14128 | 0U, // GCSPOPM |
| 14129 | 0U, // GCSPOPX |
| 14130 | 0U, // GCSPUSHM |
| 14131 | 0U, // GCSPUSHX |
| 14132 | 0U, // GCSSS1 |
| 14133 | 0U, // GCSSS2 |
| 14134 | 752U, // GCSSTR |
| 14135 | 752U, // GCSSTTR |
| 14136 | 6576358U, // GLD1B_D |
| 14137 | 673470614U, // GLD1B_D_IMM |
| 14138 | 6838502U, // GLD1B_D_SXTW |
| 14139 | 7100646U, // GLD1B_D_UXTW |
| 14140 | 673470550U, // GLD1B_S_IMM |
| 14141 | 7362790U, // GLD1B_S_SXTW |
| 14142 | 7624934U, // GLD1B_S_UXTW |
| 14143 | 6576358U, // GLD1D |
| 14144 | 7886998U, // GLD1D_IMM |
| 14145 | 8149222U, // GLD1D_SCALED |
| 14146 | 6838502U, // GLD1D_SXTW |
| 14147 | 8411366U, // GLD1D_SXTW_SCALED |
| 14148 | 7100646U, // GLD1D_UXTW |
| 14149 | 8673510U, // GLD1D_UXTW_SCALED |
| 14150 | 6576358U, // GLD1H_D |
| 14151 | 680024214U, // GLD1H_D_IMM |
| 14152 | 9197798U, // GLD1H_D_SCALED |
| 14153 | 6838502U, // GLD1H_D_SXTW |
| 14154 | 9459942U, // GLD1H_D_SXTW_SCALED |
| 14155 | 7100646U, // GLD1H_D_UXTW |
| 14156 | 9722086U, // GLD1H_D_UXTW_SCALED |
| 14157 | 680024150U, // GLD1H_S_IMM |
| 14158 | 7362790U, // GLD1H_S_SXTW |
| 14159 | 9984230U, // GLD1H_S_SXTW_SCALED |
| 14160 | 7624934U, // GLD1H_S_UXTW |
| 14161 | 10246374U, // GLD1H_S_UXTW_SCALED |
| 14162 | 673470614U, // GLD1Q |
| 14163 | 6576358U, // GLD1SB_D |
| 14164 | 673470614U, // GLD1SB_D_IMM |
| 14165 | 6838502U, // GLD1SB_D_SXTW |
| 14166 | 7100646U, // GLD1SB_D_UXTW |
| 14167 | 673470550U, // GLD1SB_S_IMM |
| 14168 | 7362790U, // GLD1SB_S_SXTW |
| 14169 | 7624934U, // GLD1SB_S_UXTW |
| 14170 | 6576358U, // GLD1SH_D |
| 14171 | 680024214U, // GLD1SH_D_IMM |
| 14172 | 9197798U, // GLD1SH_D_SCALED |
| 14173 | 6838502U, // GLD1SH_D_SXTW |
| 14174 | 9459942U, // GLD1SH_D_SXTW_SCALED |
| 14175 | 7100646U, // GLD1SH_D_UXTW |
| 14176 | 9722086U, // GLD1SH_D_UXTW_SCALED |
| 14177 | 680024150U, // GLD1SH_S_IMM |
| 14178 | 7362790U, // GLD1SH_S_SXTW |
| 14179 | 9984230U, // GLD1SH_S_SXTW_SCALED |
| 14180 | 7624934U, // GLD1SH_S_UXTW |
| 14181 | 10246374U, // GLD1SH_S_UXTW_SCALED |
| 14182 | 6576358U, // GLD1SW_D |
| 14183 | 681597078U, // GLD1SW_D_IMM |
| 14184 | 10770662U, // GLD1SW_D_SCALED |
| 14185 | 6838502U, // GLD1SW_D_SXTW |
| 14186 | 11032806U, // GLD1SW_D_SXTW_SCALED |
| 14187 | 7100646U, // GLD1SW_D_UXTW |
| 14188 | 11294950U, // GLD1SW_D_UXTW_SCALED |
| 14189 | 6576358U, // GLD1W_D |
| 14190 | 681597078U, // GLD1W_D_IMM |
| 14191 | 10770662U, // GLD1W_D_SCALED |
| 14192 | 6838502U, // GLD1W_D_SXTW |
| 14193 | 11032806U, // GLD1W_D_SXTW_SCALED |
| 14194 | 7100646U, // GLD1W_D_UXTW |
| 14195 | 11294950U, // GLD1W_D_UXTW_SCALED |
| 14196 | 681597014U, // GLD1W_IMM |
| 14197 | 7362790U, // GLD1W_SXTW |
| 14198 | 11557094U, // GLD1W_SXTW_SCALED |
| 14199 | 7624934U, // GLD1W_UXTW |
| 14200 | 11819238U, // GLD1W_UXTW_SCALED |
| 14201 | 6576358U, // GLDFF1B_D |
| 14202 | 673470614U, // GLDFF1B_D_IMM |
| 14203 | 6838502U, // GLDFF1B_D_SXTW |
| 14204 | 7100646U, // GLDFF1B_D_UXTW |
| 14205 | 673470550U, // GLDFF1B_S_IMM |
| 14206 | 7362790U, // GLDFF1B_S_SXTW |
| 14207 | 7624934U, // GLDFF1B_S_UXTW |
| 14208 | 6576358U, // GLDFF1D |
| 14209 | 7886998U, // GLDFF1D_IMM |
| 14210 | 8149222U, // GLDFF1D_SCALED |
| 14211 | 6838502U, // GLDFF1D_SXTW |
| 14212 | 8411366U, // GLDFF1D_SXTW_SCALED |
| 14213 | 7100646U, // GLDFF1D_UXTW |
| 14214 | 8673510U, // GLDFF1D_UXTW_SCALED |
| 14215 | 6576358U, // GLDFF1H_D |
| 14216 | 680024214U, // GLDFF1H_D_IMM |
| 14217 | 9197798U, // GLDFF1H_D_SCALED |
| 14218 | 6838502U, // GLDFF1H_D_SXTW |
| 14219 | 9459942U, // GLDFF1H_D_SXTW_SCALED |
| 14220 | 7100646U, // GLDFF1H_D_UXTW |
| 14221 | 9722086U, // GLDFF1H_D_UXTW_SCALED |
| 14222 | 680024150U, // GLDFF1H_S_IMM |
| 14223 | 7362790U, // GLDFF1H_S_SXTW |
| 14224 | 9984230U, // GLDFF1H_S_SXTW_SCALED |
| 14225 | 7624934U, // GLDFF1H_S_UXTW |
| 14226 | 10246374U, // GLDFF1H_S_UXTW_SCALED |
| 14227 | 6576358U, // GLDFF1SB_D |
| 14228 | 673470614U, // GLDFF1SB_D_IMM |
| 14229 | 6838502U, // GLDFF1SB_D_SXTW |
| 14230 | 7100646U, // GLDFF1SB_D_UXTW |
| 14231 | 673470550U, // GLDFF1SB_S_IMM |
| 14232 | 7362790U, // GLDFF1SB_S_SXTW |
| 14233 | 7624934U, // GLDFF1SB_S_UXTW |
| 14234 | 6576358U, // GLDFF1SH_D |
| 14235 | 680024214U, // GLDFF1SH_D_IMM |
| 14236 | 9197798U, // GLDFF1SH_D_SCALED |
| 14237 | 6838502U, // GLDFF1SH_D_SXTW |
| 14238 | 9459942U, // GLDFF1SH_D_SXTW_SCALED |
| 14239 | 7100646U, // GLDFF1SH_D_UXTW |
| 14240 | 9722086U, // GLDFF1SH_D_UXTW_SCALED |
| 14241 | 680024150U, // GLDFF1SH_S_IMM |
| 14242 | 7362790U, // GLDFF1SH_S_SXTW |
| 14243 | 9984230U, // GLDFF1SH_S_SXTW_SCALED |
| 14244 | 7624934U, // GLDFF1SH_S_UXTW |
| 14245 | 10246374U, // GLDFF1SH_S_UXTW_SCALED |
| 14246 | 6576358U, // GLDFF1SW_D |
| 14247 | 681597078U, // GLDFF1SW_D_IMM |
| 14248 | 10770662U, // GLDFF1SW_D_SCALED |
| 14249 | 6838502U, // GLDFF1SW_D_SXTW |
| 14250 | 11032806U, // GLDFF1SW_D_SXTW_SCALED |
| 14251 | 7100646U, // GLDFF1SW_D_UXTW |
| 14252 | 11294950U, // GLDFF1SW_D_UXTW_SCALED |
| 14253 | 6576358U, // GLDFF1W_D |
| 14254 | 681597078U, // GLDFF1W_D_IMM |
| 14255 | 10770662U, // GLDFF1W_D_SCALED |
| 14256 | 6838502U, // GLDFF1W_D_SXTW |
| 14257 | 11032806U, // GLDFF1W_D_SXTW_SCALED |
| 14258 | 7100646U, // GLDFF1W_D_UXTW |
| 14259 | 11294950U, // GLDFF1W_D_UXTW_SCALED |
| 14260 | 681597014U, // GLDFF1W_IMM |
| 14261 | 7362790U, // GLDFF1W_SXTW |
| 14262 | 11557094U, // GLDFF1W_SXTW_SCALED |
| 14263 | 7624934U, // GLDFF1W_UXTW |
| 14264 | 11819238U, // GLDFF1W_UXTW_SCALED |
| 14265 | 6208U, // GMI |
| 14266 | 0U, // HINT |
| 14267 | 67383505U, // HISTCNT_ZPzZZ_D |
| 14268 | 134504657U, // HISTCNT_ZPzZZ_S |
| 14269 | 20546U, // HISTSEG_ZZZ |
| 14270 | 0U, // HLT |
| 14271 | 0U, // HVC |
| 14272 | 4U, // INCB_XPiI |
| 14273 | 4U, // INCD_XPiI |
| 14274 | 4U, // INCD_ZPiI |
| 14275 | 4U, // INCH_XPiI |
| 14276 | 0U, // INCH_ZPiI |
| 14277 | 2U, // INCP_XP_B |
| 14278 | 1U, // INCP_XP_D |
| 14279 | 0U, // INCP_XP_H |
| 14280 | 2U, // INCP_XP_S |
| 14281 | 0U, // INCP_ZP_D |
| 14282 | 0U, // INCP_ZP_H |
| 14283 | 0U, // INCP_ZP_S |
| 14284 | 4U, // INCW_XPiI |
| 14285 | 4U, // INCW_ZPiI |
| 14286 | 774U, // INDEX_II_B |
| 14287 | 6208U, // INDEX_II_D |
| 14288 | 6U, // INDEX_II_H |
| 14289 | 6208U, // INDEX_II_S |
| 14290 | 230U, // INDEX_IR_B |
| 14291 | 6208U, // INDEX_IR_D |
| 14292 | 2U, // INDEX_IR_H |
| 14293 | 6208U, // INDEX_IR_S |
| 14294 | 96320U, // INDEX_RI_B |
| 14295 | 6208U, // INDEX_RI_D |
| 14296 | 785U, // INDEX_RI_H |
| 14297 | 6208U, // INDEX_RI_S |
| 14298 | 6208U, // INDEX_RR_B |
| 14299 | 6208U, // INDEX_RR_D |
| 14300 | 225U, // INDEX_RR_H |
| 14301 | 6208U, // INDEX_RR_S |
| 14302 | 95009U, // INSERT_MXIPZ_H_B |
| 14303 | 99105U, // INSERT_MXIPZ_H_D |
| 14304 | 101153U, // INSERT_MXIPZ_H_H |
| 14305 | 103201U, // INSERT_MXIPZ_H_Q |
| 14306 | 105249U, // INSERT_MXIPZ_H_S |
| 14307 | 95009U, // INSERT_MXIPZ_V_B |
| 14308 | 99105U, // INSERT_MXIPZ_V_D |
| 14309 | 101153U, // INSERT_MXIPZ_V_H |
| 14310 | 103201U, // INSERT_MXIPZ_V_Q |
| 14311 | 105249U, // INSERT_MXIPZ_V_S |
| 14312 | 2U, // INSR_ZR_B |
| 14313 | 2U, // INSR_ZR_D |
| 14314 | 0U, // INSR_ZR_H |
| 14315 | 2U, // INSR_ZR_S |
| 14316 | 6U, // INSR_ZV_B |
| 14317 | 6U, // INSR_ZV_D |
| 14318 | 0U, // INSR_ZV_H |
| 14319 | 6U, // INSR_ZV_S |
| 14320 | 4U, // INSvi16gpr |
| 14321 | 6U, // INSvi16lane |
| 14322 | 4U, // INSvi32gpr |
| 14323 | 6U, // INSvi32lane |
| 14324 | 4U, // INSvi64gpr |
| 14325 | 6U, // INSvi64lane |
| 14326 | 4U, // INSvi8gpr |
| 14327 | 6U, // INSvi8lane |
| 14328 | 6208U, // IRG |
| 14329 | 0U, // ISB |
| 14330 | 20545U, // LASTA_RPZ_B |
| 14331 | 12353U, // LASTA_RPZ_D |
| 14332 | 10305U, // LASTA_RPZ_H |
| 14333 | 24641U, // LASTA_RPZ_S |
| 14334 | 20545U, // LASTA_VPZ_B |
| 14335 | 12353U, // LASTA_VPZ_D |
| 14336 | 10305U, // LASTA_VPZ_H |
| 14337 | 24641U, // LASTA_VPZ_S |
| 14338 | 20545U, // LASTB_RPZ_B |
| 14339 | 12353U, // LASTB_RPZ_D |
| 14340 | 10305U, // LASTB_RPZ_H |
| 14341 | 24641U, // LASTB_RPZ_S |
| 14342 | 20545U, // LASTB_VPZ_B |
| 14343 | 12353U, // LASTB_VPZ_D |
| 14344 | 10305U, // LASTB_VPZ_H |
| 14345 | 24641U, // LASTB_VPZ_S |
| 14346 | 12081382U, // LD1B |
| 14347 | 12081382U, // LD1B_2Z |
| 14348 | 713578726U, // LD1B_2Z_IMM |
| 14349 | 107319U, // LD1B_2Z_STRIDED |
| 14350 | 109367U, // LD1B_2Z_STRIDED_IMM |
| 14351 | 12081382U, // LD1B_4Z |
| 14352 | 715151590U, // LD1B_4Z_IMM |
| 14353 | 12081382U, // LD1B_4Z_STRIDED |
| 14354 | 715151590U, // LD1B_4Z_STRIDED_IMM |
| 14355 | 12081382U, // LD1B_D |
| 14356 | 707025126U, // LD1B_D_IMM |
| 14357 | 12081382U, // LD1B_H |
| 14358 | 707025126U, // LD1B_H_IMM |
| 14359 | 707025126U, // LD1B_IMM |
| 14360 | 12081382U, // LD1B_S |
| 14361 | 707025126U, // LD1B_S_IMM |
| 14362 | 12343526U, // LD1D |
| 14363 | 12343526U, // LD1D_2Z |
| 14364 | 713578726U, // LD1D_2Z_IMM |
| 14365 | 12343526U, // LD1D_2Z_STRIDED |
| 14366 | 713578726U, // LD1D_2Z_STRIDED_IMM |
| 14367 | 12343526U, // LD1D_4Z |
| 14368 | 715151590U, // LD1D_4Z_IMM |
| 14369 | 12343526U, // LD1D_4Z_STRIDED |
| 14370 | 715151590U, // LD1D_4Z_STRIDED_IMM |
| 14371 | 707025126U, // LD1D_IMM |
| 14372 | 12343526U, // LD1D_Q |
| 14373 | 707025126U, // LD1D_Q_IMM |
| 14374 | 0U, // LD1Fourv16b |
| 14375 | 0U, // LD1Fourv16b_POST |
| 14376 | 0U, // LD1Fourv1d |
| 14377 | 0U, // LD1Fourv1d_POST |
| 14378 | 0U, // LD1Fourv2d |
| 14379 | 0U, // LD1Fourv2d_POST |
| 14380 | 0U, // LD1Fourv2s |
| 14381 | 0U, // LD1Fourv2s_POST |
| 14382 | 0U, // LD1Fourv4h |
| 14383 | 0U, // LD1Fourv4h_POST |
| 14384 | 0U, // LD1Fourv4s |
| 14385 | 0U, // LD1Fourv4s_POST |
| 14386 | 0U, // LD1Fourv8b |
| 14387 | 0U, // LD1Fourv8b_POST |
| 14388 | 0U, // LD1Fourv8h |
| 14389 | 0U, // LD1Fourv8h_POST |
| 14390 | 12605670U, // LD1H |
| 14391 | 12605670U, // LD1H_2Z |
| 14392 | 713578726U, // LD1H_2Z_IMM |
| 14393 | 111415U, // LD1H_2Z_STRIDED |
| 14394 | 109367U, // LD1H_2Z_STRIDED_IMM |
| 14395 | 12605670U, // LD1H_4Z |
| 14396 | 715151590U, // LD1H_4Z_IMM |
| 14397 | 12605670U, // LD1H_4Z_STRIDED |
| 14398 | 715151590U, // LD1H_4Z_STRIDED_IMM |
| 14399 | 12605670U, // LD1H_D |
| 14400 | 707025126U, // LD1H_D_IMM |
| 14401 | 707025126U, // LD1H_IMM |
| 14402 | 12605670U, // LD1H_S |
| 14403 | 707025126U, // LD1H_S_IMM |
| 14404 | 0U, // LD1Onev16b |
| 14405 | 0U, // LD1Onev16b_POST |
| 14406 | 0U, // LD1Onev1d |
| 14407 | 0U, // LD1Onev1d_POST |
| 14408 | 0U, // LD1Onev2d |
| 14409 | 0U, // LD1Onev2d_POST |
| 14410 | 0U, // LD1Onev2s |
| 14411 | 0U, // LD1Onev2s_POST |
| 14412 | 0U, // LD1Onev4h |
| 14413 | 0U, // LD1Onev4h_POST |
| 14414 | 0U, // LD1Onev4s |
| 14415 | 0U, // LD1Onev4s_POST |
| 14416 | 0U, // LD1Onev8b |
| 14417 | 0U, // LD1Onev8b_POST |
| 14418 | 0U, // LD1Onev8h |
| 14419 | 0U, // LD1Onev8h_POST |
| 14420 | 673470694U, // LD1RB_D_IMM |
| 14421 | 673470694U, // LD1RB_H_IMM |
| 14422 | 673470694U, // LD1RB_IMM |
| 14423 | 673470694U, // LD1RB_S_IMM |
| 14424 | 7887078U, // LD1RD_IMM |
| 14425 | 680024294U, // LD1RH_D_IMM |
| 14426 | 680024294U, // LD1RH_IMM |
| 14427 | 680024294U, // LD1RH_S_IMM |
| 14428 | 12081382U, // LD1RO_B |
| 14429 | 12867814U, // LD1RO_B_IMM |
| 14430 | 12343526U, // LD1RO_D |
| 14431 | 12867814U, // LD1RO_D_IMM |
| 14432 | 12605670U, // LD1RO_H |
| 14433 | 12867814U, // LD1RO_H_IMM |
| 14434 | 13129958U, // LD1RO_W |
| 14435 | 12867814U, // LD1RO_W_IMM |
| 14436 | 12081382U, // LD1RQ_B |
| 14437 | 13392102U, // LD1RQ_B_IMM |
| 14438 | 12343526U, // LD1RQ_D |
| 14439 | 13392102U, // LD1RQ_D_IMM |
| 14440 | 12605670U, // LD1RQ_H |
| 14441 | 13392102U, // LD1RQ_H_IMM |
| 14442 | 13129958U, // LD1RQ_W |
| 14443 | 13392102U, // LD1RQ_W_IMM |
| 14444 | 673470694U, // LD1RSB_D_IMM |
| 14445 | 673470694U, // LD1RSB_H_IMM |
| 14446 | 673470694U, // LD1RSB_S_IMM |
| 14447 | 680024294U, // LD1RSH_D_IMM |
| 14448 | 680024294U, // LD1RSH_S_IMM |
| 14449 | 681597158U, // LD1RSW_IMM |
| 14450 | 681597158U, // LD1RW_D_IMM |
| 14451 | 681597158U, // LD1RW_IMM |
| 14452 | 0U, // LD1Rv16b |
| 14453 | 0U, // LD1Rv16b_POST |
| 14454 | 0U, // LD1Rv1d |
| 14455 | 0U, // LD1Rv1d_POST |
| 14456 | 0U, // LD1Rv2d |
| 14457 | 0U, // LD1Rv2d_POST |
| 14458 | 0U, // LD1Rv2s |
| 14459 | 0U, // LD1Rv2s_POST |
| 14460 | 0U, // LD1Rv4h |
| 14461 | 0U, // LD1Rv4h_POST |
| 14462 | 0U, // LD1Rv4s |
| 14463 | 0U, // LD1Rv4s_POST |
| 14464 | 0U, // LD1Rv8b |
| 14465 | 0U, // LD1Rv8b_POST |
| 14466 | 0U, // LD1Rv8h |
| 14467 | 0U, // LD1Rv8h_POST |
| 14468 | 12081382U, // LD1SB_D |
| 14469 | 707025126U, // LD1SB_D_IMM |
| 14470 | 12081382U, // LD1SB_H |
| 14471 | 707025126U, // LD1SB_H_IMM |
| 14472 | 12081382U, // LD1SB_S |
| 14473 | 707025126U, // LD1SB_S_IMM |
| 14474 | 12605670U, // LD1SH_D |
| 14475 | 707025126U, // LD1SH_D_IMM |
| 14476 | 12605670U, // LD1SH_S |
| 14477 | 707025126U, // LD1SH_S_IMM |
| 14478 | 13129958U, // LD1SW_D |
| 14479 | 707025126U, // LD1SW_D_IMM |
| 14480 | 0U, // LD1Threev16b |
| 14481 | 0U, // LD1Threev16b_POST |
| 14482 | 0U, // LD1Threev1d |
| 14483 | 0U, // LD1Threev1d_POST |
| 14484 | 0U, // LD1Threev2d |
| 14485 | 0U, // LD1Threev2d_POST |
| 14486 | 0U, // LD1Threev2s |
| 14487 | 0U, // LD1Threev2s_POST |
| 14488 | 0U, // LD1Threev4h |
| 14489 | 0U, // LD1Threev4h_POST |
| 14490 | 0U, // LD1Threev4s |
| 14491 | 0U, // LD1Threev4s_POST |
| 14492 | 0U, // LD1Threev8b |
| 14493 | 0U, // LD1Threev8b_POST |
| 14494 | 0U, // LD1Threev8h |
| 14495 | 0U, // LD1Threev8h_POST |
| 14496 | 0U, // LD1Twov16b |
| 14497 | 0U, // LD1Twov16b_POST |
| 14498 | 0U, // LD1Twov1d |
| 14499 | 0U, // LD1Twov1d_POST |
| 14500 | 0U, // LD1Twov2d |
| 14501 | 0U, // LD1Twov2d_POST |
| 14502 | 0U, // LD1Twov2s |
| 14503 | 0U, // LD1Twov2s_POST |
| 14504 | 0U, // LD1Twov4h |
| 14505 | 0U, // LD1Twov4h_POST |
| 14506 | 0U, // LD1Twov4s |
| 14507 | 0U, // LD1Twov4s_POST |
| 14508 | 0U, // LD1Twov8b |
| 14509 | 0U, // LD1Twov8b_POST |
| 14510 | 0U, // LD1Twov8h |
| 14511 | 0U, // LD1Twov8h_POST |
| 14512 | 13129958U, // LD1W |
| 14513 | 13129958U, // LD1W_2Z |
| 14514 | 713578726U, // LD1W_2Z_IMM |
| 14515 | 13129958U, // LD1W_2Z_STRIDED |
| 14516 | 713578726U, // LD1W_2Z_STRIDED_IMM |
| 14517 | 13129958U, // LD1W_4Z |
| 14518 | 715151590U, // LD1W_4Z_IMM |
| 14519 | 13129958U, // LD1W_4Z_STRIDED |
| 14520 | 715151590U, // LD1W_4Z_STRIDED_IMM |
| 14521 | 13129958U, // LD1W_D |
| 14522 | 707025126U, // LD1W_D_IMM |
| 14523 | 707025126U, // LD1W_IMM |
| 14524 | 13129958U, // LD1W_Q |
| 14525 | 707025126U, // LD1W_Q_IMM |
| 14526 | 13744961U, // LD1_MXIPXX_H_B |
| 14527 | 14007105U, // LD1_MXIPXX_H_D |
| 14528 | 14269249U, // LD1_MXIPXX_H_H |
| 14529 | 14531393U, // LD1_MXIPXX_H_Q |
| 14530 | 14793537U, // LD1_MXIPXX_H_S |
| 14531 | 13744961U, // LD1_MXIPXX_V_B |
| 14532 | 14007105U, // LD1_MXIPXX_V_D |
| 14533 | 14269249U, // LD1_MXIPXX_V_H |
| 14534 | 14531393U, // LD1_MXIPXX_V_Q |
| 14535 | 14793537U, // LD1_MXIPXX_V_S |
| 14536 | 0U, // LD1i16 |
| 14537 | 0U, // LD1i16_POST |
| 14538 | 0U, // LD1i32 |
| 14539 | 0U, // LD1i32_POST |
| 14540 | 0U, // LD1i64 |
| 14541 | 0U, // LD1i64_POST |
| 14542 | 0U, // LD1i8 |
| 14543 | 0U, // LD1i8_POST |
| 14544 | 12081382U, // LD2B |
| 14545 | 713578726U, // LD2B_IMM |
| 14546 | 12343526U, // LD2D |
| 14547 | 713578726U, // LD2D_IMM |
| 14548 | 12605670U, // LD2H |
| 14549 | 713578726U, // LD2H_IMM |
| 14550 | 14964966U, // LD2Q |
| 14551 | 713578726U, // LD2Q_IMM |
| 14552 | 0U, // LD2Rv16b |
| 14553 | 0U, // LD2Rv16b_POST |
| 14554 | 0U, // LD2Rv1d |
| 14555 | 0U, // LD2Rv1d_POST |
| 14556 | 0U, // LD2Rv2d |
| 14557 | 0U, // LD2Rv2d_POST |
| 14558 | 0U, // LD2Rv2s |
| 14559 | 0U, // LD2Rv2s_POST |
| 14560 | 0U, // LD2Rv4h |
| 14561 | 0U, // LD2Rv4h_POST |
| 14562 | 0U, // LD2Rv4s |
| 14563 | 0U, // LD2Rv4s_POST |
| 14564 | 0U, // LD2Rv8b |
| 14565 | 0U, // LD2Rv8b_POST |
| 14566 | 0U, // LD2Rv8h |
| 14567 | 0U, // LD2Rv8h_POST |
| 14568 | 0U, // LD2Twov16b |
| 14569 | 0U, // LD2Twov16b_POST |
| 14570 | 0U, // LD2Twov2d |
| 14571 | 0U, // LD2Twov2d_POST |
| 14572 | 0U, // LD2Twov2s |
| 14573 | 0U, // LD2Twov2s_POST |
| 14574 | 0U, // LD2Twov4h |
| 14575 | 0U, // LD2Twov4h_POST |
| 14576 | 0U, // LD2Twov4s |
| 14577 | 0U, // LD2Twov4s_POST |
| 14578 | 0U, // LD2Twov8b |
| 14579 | 0U, // LD2Twov8b_POST |
| 14580 | 0U, // LD2Twov8h |
| 14581 | 0U, // LD2Twov8h_POST |
| 14582 | 13129958U, // LD2W |
| 14583 | 713578726U, // LD2W_IMM |
| 14584 | 0U, // LD2i16 |
| 14585 | 0U, // LD2i16_POST |
| 14586 | 0U, // LD2i32 |
| 14587 | 0U, // LD2i32_POST |
| 14588 | 0U, // LD2i64 |
| 14589 | 0U, // LD2i64_POST |
| 14590 | 0U, // LD2i8 |
| 14591 | 0U, // LD2i8_POST |
| 14592 | 12081382U, // LD3B |
| 14593 | 15227110U, // LD3B_IMM |
| 14594 | 12343526U, // LD3D |
| 14595 | 15227110U, // LD3D_IMM |
| 14596 | 12605670U, // LD3H |
| 14597 | 15227110U, // LD3H_IMM |
| 14598 | 14964966U, // LD3Q |
| 14599 | 15227110U, // LD3Q_IMM |
| 14600 | 0U, // LD3Rv16b |
| 14601 | 0U, // LD3Rv16b_POST |
| 14602 | 0U, // LD3Rv1d |
| 14603 | 0U, // LD3Rv1d_POST |
| 14604 | 0U, // LD3Rv2d |
| 14605 | 0U, // LD3Rv2d_POST |
| 14606 | 0U, // LD3Rv2s |
| 14607 | 0U, // LD3Rv2s_POST |
| 14608 | 0U, // LD3Rv4h |
| 14609 | 0U, // LD3Rv4h_POST |
| 14610 | 0U, // LD3Rv4s |
| 14611 | 0U, // LD3Rv4s_POST |
| 14612 | 0U, // LD3Rv8b |
| 14613 | 0U, // LD3Rv8b_POST |
| 14614 | 0U, // LD3Rv8h |
| 14615 | 0U, // LD3Rv8h_POST |
| 14616 | 0U, // LD3Threev16b |
| 14617 | 0U, // LD3Threev16b_POST |
| 14618 | 0U, // LD3Threev2d |
| 14619 | 0U, // LD3Threev2d_POST |
| 14620 | 0U, // LD3Threev2s |
| 14621 | 0U, // LD3Threev2s_POST |
| 14622 | 0U, // LD3Threev4h |
| 14623 | 0U, // LD3Threev4h_POST |
| 14624 | 0U, // LD3Threev4s |
| 14625 | 0U, // LD3Threev4s_POST |
| 14626 | 0U, // LD3Threev8b |
| 14627 | 0U, // LD3Threev8b_POST |
| 14628 | 0U, // LD3Threev8h |
| 14629 | 0U, // LD3Threev8h_POST |
| 14630 | 13129958U, // LD3W |
| 14631 | 15227110U, // LD3W_IMM |
| 14632 | 0U, // LD3i16 |
| 14633 | 0U, // LD3i16_POST |
| 14634 | 0U, // LD3i32 |
| 14635 | 0U, // LD3i32_POST |
| 14636 | 0U, // LD3i64 |
| 14637 | 0U, // LD3i64_POST |
| 14638 | 0U, // LD3i8 |
| 14639 | 0U, // LD3i8_POST |
| 14640 | 12081382U, // LD4B |
| 14641 | 715151590U, // LD4B_IMM |
| 14642 | 12343526U, // LD4D |
| 14643 | 715151590U, // LD4D_IMM |
| 14644 | 0U, // LD4Fourv16b |
| 14645 | 0U, // LD4Fourv16b_POST |
| 14646 | 0U, // LD4Fourv2d |
| 14647 | 0U, // LD4Fourv2d_POST |
| 14648 | 0U, // LD4Fourv2s |
| 14649 | 0U, // LD4Fourv2s_POST |
| 14650 | 0U, // LD4Fourv4h |
| 14651 | 0U, // LD4Fourv4h_POST |
| 14652 | 0U, // LD4Fourv4s |
| 14653 | 0U, // LD4Fourv4s_POST |
| 14654 | 0U, // LD4Fourv8b |
| 14655 | 0U, // LD4Fourv8b_POST |
| 14656 | 0U, // LD4Fourv8h |
| 14657 | 0U, // LD4Fourv8h_POST |
| 14658 | 12605670U, // LD4H |
| 14659 | 715151590U, // LD4H_IMM |
| 14660 | 14964966U, // LD4Q |
| 14661 | 715151590U, // LD4Q_IMM |
| 14662 | 0U, // LD4Rv16b |
| 14663 | 0U, // LD4Rv16b_POST |
| 14664 | 0U, // LD4Rv1d |
| 14665 | 0U, // LD4Rv1d_POST |
| 14666 | 0U, // LD4Rv2d |
| 14667 | 0U, // LD4Rv2d_POST |
| 14668 | 0U, // LD4Rv2s |
| 14669 | 0U, // LD4Rv2s_POST |
| 14670 | 0U, // LD4Rv4h |
| 14671 | 0U, // LD4Rv4h_POST |
| 14672 | 0U, // LD4Rv4s |
| 14673 | 0U, // LD4Rv4s_POST |
| 14674 | 0U, // LD4Rv8b |
| 14675 | 0U, // LD4Rv8b_POST |
| 14676 | 0U, // LD4Rv8h |
| 14677 | 0U, // LD4Rv8h_POST |
| 14678 | 13129958U, // LD4W |
| 14679 | 715151590U, // LD4W_IMM |
| 14680 | 0U, // LD4i16 |
| 14681 | 0U, // LD4i16_POST |
| 14682 | 0U, // LD4i32 |
| 14683 | 0U, // LD4i32_POST |
| 14684 | 0U, // LD4i64 |
| 14685 | 0U, // LD4i64_POST |
| 14686 | 0U, // LD4i8 |
| 14687 | 0U, // LD4i8_POST |
| 14688 | 0U, // LD64B |
| 14689 | 7U, // LDADDAB |
| 14690 | 7U, // LDADDAH |
| 14691 | 7U, // LDADDALB |
| 14692 | 7U, // LDADDALH |
| 14693 | 7U, // LDADDALW |
| 14694 | 7U, // LDADDALX |
| 14695 | 7U, // LDADDAW |
| 14696 | 7U, // LDADDAX |
| 14697 | 7U, // LDADDB |
| 14698 | 7U, // LDADDH |
| 14699 | 7U, // LDADDLB |
| 14700 | 7U, // LDADDLH |
| 14701 | 7U, // LDADDLW |
| 14702 | 7U, // LDADDLX |
| 14703 | 7U, // LDADDW |
| 14704 | 7U, // LDADDX |
| 14705 | 0U, // LDAP1 |
| 14706 | 752U, // LDAPRB |
| 14707 | 752U, // LDAPRH |
| 14708 | 752U, // LDAPRW |
| 14709 | 850U, // LDAPRWpost |
| 14710 | 752U, // LDAPRX |
| 14711 | 866U, // LDAPRXpost |
| 14712 | 4200512U, // LDAPURBi |
| 14713 | 4200512U, // LDAPURHi |
| 14714 | 4200512U, // LDAPURSBWi |
| 14715 | 4200512U, // LDAPURSBXi |
| 14716 | 4200512U, // LDAPURSHWi |
| 14717 | 4200512U, // LDAPURSHXi |
| 14718 | 4200512U, // LDAPURSWi |
| 14719 | 4200512U, // LDAPURXi |
| 14720 | 752U, // LDAPURbi |
| 14721 | 752U, // LDAPURdi |
| 14722 | 752U, // LDAPURhi |
| 14723 | 4200512U, // LDAPURi |
| 14724 | 752U, // LDAPURqi |
| 14725 | 752U, // LDAPURsi |
| 14726 | 752U, // LDARB |
| 14727 | 752U, // LDARH |
| 14728 | 752U, // LDARW |
| 14729 | 752U, // LDARX |
| 14730 | 4200768U, // LDAXPW |
| 14731 | 4200768U, // LDAXPX |
| 14732 | 752U, // LDAXRB |
| 14733 | 752U, // LDAXRH |
| 14734 | 752U, // LDAXRW |
| 14735 | 752U, // LDAXRX |
| 14736 | 7U, // LDCLRAB |
| 14737 | 7U, // LDCLRAH |
| 14738 | 7U, // LDCLRALB |
| 14739 | 7U, // LDCLRALH |
| 14740 | 7U, // LDCLRALW |
| 14741 | 7U, // LDCLRALX |
| 14742 | 7U, // LDCLRAW |
| 14743 | 7U, // LDCLRAX |
| 14744 | 7U, // LDCLRB |
| 14745 | 7U, // LDCLRH |
| 14746 | 7U, // LDCLRLB |
| 14747 | 7U, // LDCLRLH |
| 14748 | 7U, // LDCLRLW |
| 14749 | 7U, // LDCLRLX |
| 14750 | 115012U, // LDCLRP |
| 14751 | 115012U, // LDCLRPA |
| 14752 | 115012U, // LDCLRPAL |
| 14753 | 115012U, // LDCLRPL |
| 14754 | 7U, // LDCLRW |
| 14755 | 7U, // LDCLRX |
| 14756 | 7U, // LDEORAB |
| 14757 | 7U, // LDEORAH |
| 14758 | 7U, // LDEORALB |
| 14759 | 7U, // LDEORALH |
| 14760 | 7U, // LDEORALW |
| 14761 | 7U, // LDEORALX |
| 14762 | 7U, // LDEORAW |
| 14763 | 7U, // LDEORAX |
| 14764 | 7U, // LDEORB |
| 14765 | 7U, // LDEORH |
| 14766 | 7U, // LDEORLB |
| 14767 | 7U, // LDEORLH |
| 14768 | 7U, // LDEORLW |
| 14769 | 7U, // LDEORLX |
| 14770 | 7U, // LDEORW |
| 14771 | 7U, // LDEORX |
| 14772 | 12081382U, // LDFF1B |
| 14773 | 12081382U, // LDFF1B_D |
| 14774 | 12081382U, // LDFF1B_H |
| 14775 | 12081382U, // LDFF1B_S |
| 14776 | 12343526U, // LDFF1D |
| 14777 | 12605670U, // LDFF1H |
| 14778 | 12605670U, // LDFF1H_D |
| 14779 | 12605670U, // LDFF1H_S |
| 14780 | 12081382U, // LDFF1SB_D |
| 14781 | 12081382U, // LDFF1SB_H |
| 14782 | 12081382U, // LDFF1SB_S |
| 14783 | 12605670U, // LDFF1SH_D |
| 14784 | 12605670U, // LDFF1SH_S |
| 14785 | 13129958U, // LDFF1SW_D |
| 14786 | 13129958U, // LDFF1W |
| 14787 | 13129958U, // LDFF1W_D |
| 14788 | 4311106U, // LDG |
| 14789 | 752U, // LDGM |
| 14790 | 4200768U, // LDIAPPW |
| 14791 | 15548738U, // LDIAPPWpost |
| 14792 | 4200768U, // LDIAPPX |
| 14793 | 15810882U, // LDIAPPXpost |
| 14794 | 752U, // LDLARB |
| 14795 | 752U, // LDLARH |
| 14796 | 752U, // LDLARW |
| 14797 | 752U, // LDLARX |
| 14798 | 707025126U, // LDNF1B_D_IMM |
| 14799 | 707025126U, // LDNF1B_H_IMM |
| 14800 | 707025126U, // LDNF1B_IMM |
| 14801 | 707025126U, // LDNF1B_S_IMM |
| 14802 | 707025126U, // LDNF1D_IMM |
| 14803 | 707025126U, // LDNF1H_D_IMM |
| 14804 | 707025126U, // LDNF1H_IMM |
| 14805 | 707025126U, // LDNF1H_S_IMM |
| 14806 | 707025126U, // LDNF1SB_D_IMM |
| 14807 | 707025126U, // LDNF1SB_H_IMM |
| 14808 | 707025126U, // LDNF1SB_S_IMM |
| 14809 | 707025126U, // LDNF1SH_D_IMM |
| 14810 | 707025126U, // LDNF1SH_S_IMM |
| 14811 | 707025126U, // LDNF1SW_D_IMM |
| 14812 | 707025126U, // LDNF1W_D_IMM |
| 14813 | 707025126U, // LDNF1W_IMM |
| 14814 | 738466112U, // LDNPDi |
| 14815 | 772020544U, // LDNPQi |
| 14816 | 805574976U, // LDNPSi |
| 14817 | 805574976U, // LDNPWi |
| 14818 | 738466112U, // LDNPXi |
| 14819 | 12081382U, // LDNT1B_2Z |
| 14820 | 713578726U, // LDNT1B_2Z_IMM |
| 14821 | 107319U, // LDNT1B_2Z_STRIDED |
| 14822 | 109367U, // LDNT1B_2Z_STRIDED_IMM |
| 14823 | 12081382U, // LDNT1B_4Z |
| 14824 | 715151590U, // LDNT1B_4Z_IMM |
| 14825 | 12081382U, // LDNT1B_4Z_STRIDED |
| 14826 | 715151590U, // LDNT1B_4Z_STRIDED_IMM |
| 14827 | 707025126U, // LDNT1B_ZRI |
| 14828 | 12081382U, // LDNT1B_ZRR |
| 14829 | 673470614U, // LDNT1B_ZZR_D |
| 14830 | 673470550U, // LDNT1B_ZZR_S |
| 14831 | 12343526U, // LDNT1D_2Z |
| 14832 | 713578726U, // LDNT1D_2Z_IMM |
| 14833 | 12343526U, // LDNT1D_2Z_STRIDED |
| 14834 | 713578726U, // LDNT1D_2Z_STRIDED_IMM |
| 14835 | 12343526U, // LDNT1D_4Z |
| 14836 | 715151590U, // LDNT1D_4Z_IMM |
| 14837 | 12343526U, // LDNT1D_4Z_STRIDED |
| 14838 | 715151590U, // LDNT1D_4Z_STRIDED_IMM |
| 14839 | 707025126U, // LDNT1D_ZRI |
| 14840 | 12343526U, // LDNT1D_ZRR |
| 14841 | 673470614U, // LDNT1D_ZZR_D |
| 14842 | 12605670U, // LDNT1H_2Z |
| 14843 | 713578726U, // LDNT1H_2Z_IMM |
| 14844 | 111415U, // LDNT1H_2Z_STRIDED |
| 14845 | 109367U, // LDNT1H_2Z_STRIDED_IMM |
| 14846 | 12605670U, // LDNT1H_4Z |
| 14847 | 715151590U, // LDNT1H_4Z_IMM |
| 14848 | 12605670U, // LDNT1H_4Z_STRIDED |
| 14849 | 715151590U, // LDNT1H_4Z_STRIDED_IMM |
| 14850 | 707025126U, // LDNT1H_ZRI |
| 14851 | 12605670U, // LDNT1H_ZRR |
| 14852 | 673470614U, // LDNT1H_ZZR_D |
| 14853 | 673470550U, // LDNT1H_ZZR_S |
| 14854 | 673470614U, // LDNT1SB_ZZR_D |
| 14855 | 673470550U, // LDNT1SB_ZZR_S |
| 14856 | 673470614U, // LDNT1SH_ZZR_D |
| 14857 | 673470550U, // LDNT1SH_ZZR_S |
| 14858 | 673470614U, // LDNT1SW_ZZR_D |
| 14859 | 13129958U, // LDNT1W_2Z |
| 14860 | 713578726U, // LDNT1W_2Z_IMM |
| 14861 | 13129958U, // LDNT1W_2Z_STRIDED |
| 14862 | 713578726U, // LDNT1W_2Z_STRIDED_IMM |
| 14863 | 13129958U, // LDNT1W_4Z |
| 14864 | 715151590U, // LDNT1W_4Z_IMM |
| 14865 | 13129958U, // LDNT1W_4Z_STRIDED |
| 14866 | 715151590U, // LDNT1W_4Z_STRIDED_IMM |
| 14867 | 707025126U, // LDNT1W_ZRI |
| 14868 | 13129958U, // LDNT1W_ZRR |
| 14869 | 673470614U, // LDNT1W_ZZR_D |
| 14870 | 673470550U, // LDNT1W_ZZR_S |
| 14871 | 738466112U, // LDPDi |
| 14872 | 854933826U, // LDPDpost |
| 14873 | 839205186U, // LDPDpre |
| 14874 | 772020544U, // LDPQi |
| 14875 | 888488258U, // LDPQpost |
| 14876 | 872759618U, // LDPQpre |
| 14877 | 805574976U, // LDPSWi |
| 14878 | 922042690U, // LDPSWpost |
| 14879 | 906314050U, // LDPSWpre |
| 14880 | 805574976U, // LDPSi |
| 14881 | 922042690U, // LDPSpost |
| 14882 | 906314050U, // LDPSpre |
| 14883 | 805574976U, // LDPWi |
| 14884 | 922042690U, // LDPWpost |
| 14885 | 906314050U, // LDPWpre |
| 14886 | 738466112U, // LDPXi |
| 14887 | 854933826U, // LDPXpost |
| 14888 | 839205186U, // LDPXpre |
| 14889 | 118848U, // LDRAAindexed |
| 14890 | 120898U, // LDRAAwriteback |
| 14891 | 118848U, // LDRABindexed |
| 14892 | 120898U, // LDRABwriteback |
| 14893 | 82802U, // LDRBBpost |
| 14894 | 16334914U, // LDRBBpre |
| 14895 | 939792448U, // LDRBBroW |
| 14896 | 973346880U, // LDRBBroX |
| 14897 | 122944U, // LDRBBui |
| 14898 | 82802U, // LDRBpost |
| 14899 | 16334914U, // LDRBpre |
| 14900 | 939792448U, // LDRBroW |
| 14901 | 973346880U, // LDRBroX |
| 14902 | 122944U, // LDRBui |
| 14903 | 3U, // LDRDl |
| 14904 | 82802U, // LDRDpost |
| 14905 | 16334914U, // LDRDpre |
| 14906 | 1006901312U, // LDRDroW |
| 14907 | 1040455744U, // LDRDroX |
| 14908 | 124992U, // LDRDui |
| 14909 | 82802U, // LDRHHpost |
| 14910 | 16334914U, // LDRHHpre |
| 14911 | 1074010176U, // LDRHHroW |
| 14912 | 1107564608U, // LDRHHroX |
| 14913 | 127040U, // LDRHHui |
| 14914 | 82802U, // LDRHpost |
| 14915 | 16334914U, // LDRHpre |
| 14916 | 1074010176U, // LDRHroW |
| 14917 | 1107564608U, // LDRHroX |
| 14918 | 127040U, // LDRHui |
| 14919 | 3U, // LDRQl |
| 14920 | 82802U, // LDRQpost |
| 14921 | 16334914U, // LDRQpre |
| 14922 | 1141119040U, // LDRQroW |
| 14923 | 1174673472U, // LDRQroX |
| 14924 | 129088U, // LDRQui |
| 14925 | 82802U, // LDRSBWpost |
| 14926 | 16334914U, // LDRSBWpre |
| 14927 | 939792448U, // LDRSBWroW |
| 14928 | 973346880U, // LDRSBWroX |
| 14929 | 122944U, // LDRSBWui |
| 14930 | 82802U, // LDRSBXpost |
| 14931 | 16334914U, // LDRSBXpre |
| 14932 | 939792448U, // LDRSBXroW |
| 14933 | 973346880U, // LDRSBXroX |
| 14934 | 122944U, // LDRSBXui |
| 14935 | 82802U, // LDRSHWpost |
| 14936 | 16334914U, // LDRSHWpre |
| 14937 | 1074010176U, // LDRSHWroW |
| 14938 | 1107564608U, // LDRSHWroX |
| 14939 | 127040U, // LDRSHWui |
| 14940 | 82802U, // LDRSHXpost |
| 14941 | 16334914U, // LDRSHXpre |
| 14942 | 1074010176U, // LDRSHXroW |
| 14943 | 1107564608U, // LDRSHXroX |
| 14944 | 127040U, // LDRSHXui |
| 14945 | 3U, // LDRSWl |
| 14946 | 82802U, // LDRSWpost |
| 14947 | 16334914U, // LDRSWpre |
| 14948 | 1208227904U, // LDRSWroW |
| 14949 | 1241782336U, // LDRSWroX |
| 14950 | 131136U, // LDRSWui |
| 14951 | 3U, // LDRSl |
| 14952 | 82802U, // LDRSpost |
| 14953 | 16334914U, // LDRSpre |
| 14954 | 1208227904U, // LDRSroW |
| 14955 | 1241782336U, // LDRSroX |
| 14956 | 131136U, // LDRSui |
| 14957 | 3U, // LDRWl |
| 14958 | 82802U, // LDRWpost |
| 14959 | 16334914U, // LDRWpre |
| 14960 | 1208227904U, // LDRWroW |
| 14961 | 1241782336U, // LDRWroX |
| 14962 | 131136U, // LDRWui |
| 14963 | 3U, // LDRXl |
| 14964 | 82802U, // LDRXpost |
| 14965 | 16334914U, // LDRXpre |
| 14966 | 1006901312U, // LDRXroW |
| 14967 | 1040455744U, // LDRXroX |
| 14968 | 124992U, // LDRXui |
| 14969 | 16521280U, // LDR_PXI |
| 14970 | 752U, // LDR_TX |
| 14971 | 0U, // LDR_ZA |
| 14972 | 16521280U, // LDR_ZXI |
| 14973 | 7U, // LDSETAB |
| 14974 | 7U, // LDSETAH |
| 14975 | 7U, // LDSETALB |
| 14976 | 7U, // LDSETALH |
| 14977 | 7U, // LDSETALW |
| 14978 | 7U, // LDSETALX |
| 14979 | 7U, // LDSETAW |
| 14980 | 7U, // LDSETAX |
| 14981 | 7U, // LDSETB |
| 14982 | 7U, // LDSETH |
| 14983 | 7U, // LDSETLB |
| 14984 | 7U, // LDSETLH |
| 14985 | 7U, // LDSETLW |
| 14986 | 7U, // LDSETLX |
| 14987 | 115012U, // LDSETP |
| 14988 | 115012U, // LDSETPA |
| 14989 | 115012U, // LDSETPAL |
| 14990 | 115012U, // LDSETPL |
| 14991 | 7U, // LDSETW |
| 14992 | 7U, // LDSETX |
| 14993 | 7U, // LDSMAXAB |
| 14994 | 7U, // LDSMAXAH |
| 14995 | 7U, // LDSMAXALB |
| 14996 | 7U, // LDSMAXALH |
| 14997 | 7U, // LDSMAXALW |
| 14998 | 7U, // LDSMAXALX |
| 14999 | 7U, // LDSMAXAW |
| 15000 | 7U, // LDSMAXAX |
| 15001 | 7U, // LDSMAXB |
| 15002 | 7U, // LDSMAXH |
| 15003 | 7U, // LDSMAXLB |
| 15004 | 7U, // LDSMAXLH |
| 15005 | 7U, // LDSMAXLW |
| 15006 | 7U, // LDSMAXLX |
| 15007 | 7U, // LDSMAXW |
| 15008 | 7U, // LDSMAXX |
| 15009 | 7U, // LDSMINAB |
| 15010 | 7U, // LDSMINAH |
| 15011 | 7U, // LDSMINALB |
| 15012 | 7U, // LDSMINALH |
| 15013 | 7U, // LDSMINALW |
| 15014 | 7U, // LDSMINALX |
| 15015 | 7U, // LDSMINAW |
| 15016 | 7U, // LDSMINAX |
| 15017 | 7U, // LDSMINB |
| 15018 | 7U, // LDSMINH |
| 15019 | 7U, // LDSMINLB |
| 15020 | 7U, // LDSMINLH |
| 15021 | 7U, // LDSMINLW |
| 15022 | 7U, // LDSMINLX |
| 15023 | 7U, // LDSMINW |
| 15024 | 7U, // LDSMINX |
| 15025 | 4200512U, // LDTRBi |
| 15026 | 4200512U, // LDTRHi |
| 15027 | 4200512U, // LDTRSBWi |
| 15028 | 4200512U, // LDTRSBXi |
| 15029 | 4200512U, // LDTRSHWi |
| 15030 | 4200512U, // LDTRSHXi |
| 15031 | 4200512U, // LDTRSWi |
| 15032 | 4200512U, // LDTRWi |
| 15033 | 4200512U, // LDTRXi |
| 15034 | 7U, // LDUMAXAB |
| 15035 | 7U, // LDUMAXAH |
| 15036 | 7U, // LDUMAXALB |
| 15037 | 7U, // LDUMAXALH |
| 15038 | 7U, // LDUMAXALW |
| 15039 | 7U, // LDUMAXALX |
| 15040 | 7U, // LDUMAXAW |
| 15041 | 7U, // LDUMAXAX |
| 15042 | 7U, // LDUMAXB |
| 15043 | 7U, // LDUMAXH |
| 15044 | 7U, // LDUMAXLB |
| 15045 | 7U, // LDUMAXLH |
| 15046 | 7U, // LDUMAXLW |
| 15047 | 7U, // LDUMAXLX |
| 15048 | 7U, // LDUMAXW |
| 15049 | 7U, // LDUMAXX |
| 15050 | 7U, // LDUMINAB |
| 15051 | 7U, // LDUMINAH |
| 15052 | 7U, // LDUMINALB |
| 15053 | 7U, // LDUMINALH |
| 15054 | 7U, // LDUMINALW |
| 15055 | 7U, // LDUMINALX |
| 15056 | 7U, // LDUMINAW |
| 15057 | 7U, // LDUMINAX |
| 15058 | 7U, // LDUMINB |
| 15059 | 7U, // LDUMINH |
| 15060 | 7U, // LDUMINLB |
| 15061 | 7U, // LDUMINLH |
| 15062 | 7U, // LDUMINLW |
| 15063 | 7U, // LDUMINLX |
| 15064 | 7U, // LDUMINW |
| 15065 | 7U, // LDUMINX |
| 15066 | 4200512U, // LDURBBi |
| 15067 | 4200512U, // LDURBi |
| 15068 | 4200512U, // LDURDi |
| 15069 | 4200512U, // LDURHHi |
| 15070 | 4200512U, // LDURHi |
| 15071 | 4200512U, // LDURQi |
| 15072 | 4200512U, // LDURSBWi |
| 15073 | 4200512U, // LDURSBXi |
| 15074 | 4200512U, // LDURSHWi |
| 15075 | 4200512U, // LDURSHXi |
| 15076 | 4200512U, // LDURSWi |
| 15077 | 4200512U, // LDURSi |
| 15078 | 4200512U, // LDURWi |
| 15079 | 4200512U, // LDURXi |
| 15080 | 4200768U, // LDXPW |
| 15081 | 4200768U, // LDXPX |
| 15082 | 752U, // LDXRB |
| 15083 | 752U, // LDXRH |
| 15084 | 752U, // LDXRW |
| 15085 | 752U, // LDXRX |
| 15086 | 33837153U, // LSLR_ZPmZ_B |
| 15087 | 67383393U, // LSLR_ZPmZ_D |
| 15088 | 101472369U, // LSLR_ZPmZ_H |
| 15089 | 134504545U, // LSLR_ZPmZ_S |
| 15090 | 6208U, // LSLVWr |
| 15091 | 6208U, // LSLVXr |
| 15092 | 67391585U, // LSL_WIDE_ZPmZ_B |
| 15093 | 2644081U, // LSL_WIDE_ZPmZ_H |
| 15094 | 67395681U, // LSL_WIDE_ZPmZ_S |
| 15095 | 12354U, // LSL_WIDE_ZZZ_B |
| 15096 | 145U, // LSL_WIDE_ZZZ_H |
| 15097 | 12354U, // LSL_WIDE_ZZZ_S |
| 15098 | 282721U, // LSL_ZPmI_B |
| 15099 | 274529U, // LSL_ZPmI_D |
| 15100 | 103045233U, // LSL_ZPmI_H |
| 15101 | 286817U, // LSL_ZPmI_S |
| 15102 | 33837153U, // LSL_ZPmZ_B |
| 15103 | 67383393U, // LSL_ZPmZ_D |
| 15104 | 101472369U, // LSL_ZPmZ_H |
| 15105 | 134504545U, // LSL_ZPmZ_S |
| 15106 | 6210U, // LSL_ZZI_B |
| 15107 | 6209U, // LSL_ZZI_D |
| 15108 | 225U, // LSL_ZZI_H |
| 15109 | 6210U, // LSL_ZZI_S |
| 15110 | 33837153U, // LSRR_ZPmZ_B |
| 15111 | 67383393U, // LSRR_ZPmZ_D |
| 15112 | 101472369U, // LSRR_ZPmZ_H |
| 15113 | 134504545U, // LSRR_ZPmZ_S |
| 15114 | 6208U, // LSRVWr |
| 15115 | 6208U, // LSRVXr |
| 15116 | 67391585U, // LSR_WIDE_ZPmZ_B |
| 15117 | 2644081U, // LSR_WIDE_ZPmZ_H |
| 15118 | 67395681U, // LSR_WIDE_ZPmZ_S |
| 15119 | 12354U, // LSR_WIDE_ZZZ_B |
| 15120 | 145U, // LSR_WIDE_ZZZ_H |
| 15121 | 12354U, // LSR_WIDE_ZZZ_S |
| 15122 | 282721U, // LSR_ZPmI_B |
| 15123 | 274529U, // LSR_ZPmI_D |
| 15124 | 103045233U, // LSR_ZPmI_H |
| 15125 | 286817U, // LSR_ZPmI_S |
| 15126 | 33837153U, // LSR_ZPmZ_B |
| 15127 | 67383393U, // LSR_ZPmZ_D |
| 15128 | 101472369U, // LSR_ZPmZ_H |
| 15129 | 134504545U, // LSR_ZPmZ_S |
| 15130 | 6210U, // LSR_ZZI_B |
| 15131 | 6209U, // LSR_ZZI_D |
| 15132 | 225U, // LSR_ZZI_H |
| 15133 | 6210U, // LSR_ZZI_S |
| 15134 | 903U, // LUT2v16f8 |
| 15135 | 7U, // LUT2v8f16 |
| 15136 | 903U, // LUT4v16f8 |
| 15137 | 7U, // LUT4v8f16 |
| 15138 | 913U, // LUTI2_2ZTZI_B |
| 15139 | 913U, // LUTI2_2ZTZI_H |
| 15140 | 913U, // LUTI2_2ZTZI_S |
| 15141 | 913U, // LUTI2_4ZTZI_B |
| 15142 | 913U, // LUTI2_4ZTZI_H |
| 15143 | 913U, // LUTI2_4ZTZI_S |
| 15144 | 133184U, // LUTI2_S_2ZTZI_B |
| 15145 | 133184U, // LUTI2_S_2ZTZI_H |
| 15146 | 913U, // LUTI2_S_4ZTZI_B |
| 15147 | 913U, // LUTI2_S_4ZTZI_H |
| 15148 | 133184U, // LUTI2_ZTZI_B |
| 15149 | 913U, // LUTI2_ZTZI_H |
| 15150 | 133184U, // LUTI2_ZTZI_S |
| 15151 | 917U, // LUTI2_ZZZI_B |
| 15152 | 913U, // LUTI2_ZZZI_H |
| 15153 | 913U, // LUTI4_2ZTZI_B |
| 15154 | 913U, // LUTI4_2ZTZI_H |
| 15155 | 913U, // LUTI4_2ZTZI_S |
| 15156 | 913U, // LUTI4_4ZTZI_H |
| 15157 | 913U, // LUTI4_4ZTZI_S |
| 15158 | 929U, // LUTI4_4ZZT2Z |
| 15159 | 133184U, // LUTI4_S_2ZTZI_B |
| 15160 | 133184U, // LUTI4_S_2ZTZI_H |
| 15161 | 913U, // LUTI4_S_4ZTZI_H |
| 15162 | 929U, // LUTI4_S_4ZZT2Z |
| 15163 | 913U, // LUTI4_Z2ZZI_H |
| 15164 | 133184U, // LUTI4_ZTZI_B |
| 15165 | 913U, // LUTI4_ZTZI_H |
| 15166 | 133184U, // LUTI4_ZTZI_S |
| 15167 | 917U, // LUTI4_ZZZI_B |
| 15168 | 913U, // LUTI4_ZZZI_H |
| 15169 | 268352U, // MADDPT |
| 15170 | 268352U, // MADDWrrr |
| 15171 | 268352U, // MADDXrrr |
| 15172 | 2112U, // MAD_CPA |
| 15173 | 135265U, // MAD_ZPmZZ_B |
| 15174 | 537135201U, // MAD_ZPmZZ_D |
| 15175 | 104356097U, // MAD_ZPmZZ_H |
| 15176 | 570691681U, // MAD_ZPmZZ_S |
| 15177 | 33837265U, // MATCH_PPzZZ_B |
| 15178 | 101472371U, // MATCH_PPzZZ_H |
| 15179 | 2112U, // MLA_CPA |
| 15180 | 135265U, // MLA_ZPmZZ_B |
| 15181 | 537135201U, // MLA_ZPmZZ_D |
| 15182 | 104356097U, // MLA_ZPmZZ_H |
| 15183 | 570691681U, // MLA_ZPmZZ_S |
| 15184 | 103548992U, // MLA_ZZZI_D |
| 15185 | 78081U, // MLA_ZZZI_H |
| 15186 | 103551040U, // MLA_ZZZI_S |
| 15187 | 18497U, // MLAv16i8 |
| 15188 | 18497U, // MLAv2i32 |
| 15189 | 103565377U, // MLAv2i32_indexed |
| 15190 | 18497U, // MLAv4i16 |
| 15191 | 103565377U, // MLAv4i16_indexed |
| 15192 | 18497U, // MLAv4i32 |
| 15193 | 103565377U, // MLAv4i32_indexed |
| 15194 | 18497U, // MLAv8i16 |
| 15195 | 103565377U, // MLAv8i16_indexed |
| 15196 | 18497U, // MLAv8i8 |
| 15197 | 135265U, // MLS_ZPmZZ_B |
| 15198 | 537135201U, // MLS_ZPmZZ_D |
| 15199 | 104356097U, // MLS_ZPmZZ_H |
| 15200 | 570691681U, // MLS_ZPmZZ_S |
| 15201 | 103548992U, // MLS_ZZZI_D |
| 15202 | 78081U, // MLS_ZZZI_H |
| 15203 | 103551040U, // MLS_ZZZI_S |
| 15204 | 18497U, // MLSv16i8 |
| 15205 | 18497U, // MLSv2i32 |
| 15206 | 103565377U, // MLSv2i32_indexed |
| 15207 | 18497U, // MLSv4i16 |
| 15208 | 103565377U, // MLSv4i16_indexed |
| 15209 | 18497U, // MLSv4i32 |
| 15210 | 103565377U, // MLSv4i32_indexed |
| 15211 | 18497U, // MLSv8i16 |
| 15212 | 103565377U, // MLSv8i16_indexed |
| 15213 | 18497U, // MLSv8i8 |
| 15214 | 0U, // MOPSSETGE |
| 15215 | 0U, // MOPSSETGEN |
| 15216 | 0U, // MOPSSETGET |
| 15217 | 0U, // MOPSSETGETN |
| 15218 | 7U, // MOVAZ_2ZMI_H_B |
| 15219 | 7U, // MOVAZ_2ZMI_H_D |
| 15220 | 7U, // MOVAZ_2ZMI_H_H |
| 15221 | 7U, // MOVAZ_2ZMI_H_S |
| 15222 | 7U, // MOVAZ_2ZMI_V_B |
| 15223 | 7U, // MOVAZ_2ZMI_V_D |
| 15224 | 7U, // MOVAZ_2ZMI_V_H |
| 15225 | 7U, // MOVAZ_2ZMI_V_S |
| 15226 | 7U, // MOVAZ_4ZMI_H_B |
| 15227 | 7U, // MOVAZ_4ZMI_H_D |
| 15228 | 7U, // MOVAZ_4ZMI_H_H |
| 15229 | 7U, // MOVAZ_4ZMI_H_S |
| 15230 | 7U, // MOVAZ_4ZMI_V_B |
| 15231 | 7U, // MOVAZ_4ZMI_V_D |
| 15232 | 7U, // MOVAZ_4ZMI_V_H |
| 15233 | 7U, // MOVAZ_4ZMI_V_S |
| 15234 | 7U, // MOVAZ_VG2_2ZMXI |
| 15235 | 7U, // MOVAZ_VG4_4ZMXI |
| 15236 | 8U, // MOVAZ_ZMI_H_B |
| 15237 | 8U, // MOVAZ_ZMI_H_D |
| 15238 | 137284U, // MOVAZ_ZMI_H_H |
| 15239 | 137284U, // MOVAZ_ZMI_H_Q |
| 15240 | 8U, // MOVAZ_ZMI_H_S |
| 15241 | 8U, // MOVAZ_ZMI_V_B |
| 15242 | 8U, // MOVAZ_ZMI_V_D |
| 15243 | 137284U, // MOVAZ_ZMI_V_H |
| 15244 | 137284U, // MOVAZ_ZMI_V_Q |
| 15245 | 8U, // MOVAZ_ZMI_V_S |
| 15246 | 139330U, // MOVA_2ZMXI_H_B |
| 15247 | 139330U, // MOVA_2ZMXI_H_D |
| 15248 | 139330U, // MOVA_2ZMXI_H_H |
| 15249 | 139330U, // MOVA_2ZMXI_H_S |
| 15250 | 139330U, // MOVA_2ZMXI_V_B |
| 15251 | 139330U, // MOVA_2ZMXI_V_D |
| 15252 | 139330U, // MOVA_2ZMXI_V_H |
| 15253 | 139330U, // MOVA_2ZMXI_V_S |
| 15254 | 141378U, // MOVA_4ZMXI_H_B |
| 15255 | 141378U, // MOVA_4ZMXI_H_D |
| 15256 | 141378U, // MOVA_4ZMXI_H_H |
| 15257 | 141378U, // MOVA_4ZMXI_H_S |
| 15258 | 141378U, // MOVA_4ZMXI_V_B |
| 15259 | 141378U, // MOVA_4ZMXI_V_D |
| 15260 | 141378U, // MOVA_4ZMXI_V_H |
| 15261 | 141378U, // MOVA_4ZMXI_V_S |
| 15262 | 144305U, // MOVA_MXI2Z_H_B |
| 15263 | 146353U, // MOVA_MXI2Z_H_D |
| 15264 | 148401U, // MOVA_MXI2Z_H_H |
| 15265 | 150449U, // MOVA_MXI2Z_H_S |
| 15266 | 144305U, // MOVA_MXI2Z_V_B |
| 15267 | 146353U, // MOVA_MXI2Z_V_D |
| 15268 | 148401U, // MOVA_MXI2Z_V_H |
| 15269 | 150449U, // MOVA_MXI2Z_V_S |
| 15270 | 144321U, // MOVA_MXI4Z_H_B |
| 15271 | 146369U, // MOVA_MXI4Z_H_D |
| 15272 | 148417U, // MOVA_MXI4Z_H_H |
| 15273 | 150465U, // MOVA_MXI4Z_H_S |
| 15274 | 144321U, // MOVA_MXI4Z_V_B |
| 15275 | 146369U, // MOVA_MXI4Z_V_D |
| 15276 | 148417U, // MOVA_MXI4Z_V_H |
| 15277 | 150465U, // MOVA_MXI4Z_V_S |
| 15278 | 7U, // MOVA_VG2_2ZMXI |
| 15279 | 161U, // MOVA_VG2_MXI2Z |
| 15280 | 7U, // MOVA_VG4_4ZMXI |
| 15281 | 161U, // MOVA_VG4_MXI4Z |
| 15282 | 8U, // MOVID |
| 15283 | 8U, // MOVIv16b_ns |
| 15284 | 8U, // MOVIv2d_ns |
| 15285 | 984U, // MOVIv2i32 |
| 15286 | 984U, // MOVIv2s_msl |
| 15287 | 984U, // MOVIv4i16 |
| 15288 | 984U, // MOVIv4i32 |
| 15289 | 984U, // MOVIv4s_msl |
| 15290 | 8U, // MOVIv8b_ns |
| 15291 | 984U, // MOVIv8i16 |
| 15292 | 2U, // MOVKWi |
| 15293 | 2U, // MOVKXi |
| 15294 | 984U, // MOVNWi |
| 15295 | 984U, // MOVNXi |
| 15296 | 16U, // MOVPRFX_ZPmZ_B |
| 15297 | 32U, // MOVPRFX_ZPmZ_D |
| 15298 | 0U, // MOVPRFX_ZPmZ_H |
| 15299 | 48U, // MOVPRFX_ZPmZ_S |
| 15300 | 20689U, // MOVPRFX_ZPzZ_B |
| 15301 | 12497U, // MOVPRFX_ZPzZ_D |
| 15302 | 115U, // MOVPRFX_ZPzZ_H |
| 15303 | 24785U, // MOVPRFX_ZPzZ_S |
| 15304 | 1U, // MOVPRFX_ZZ |
| 15305 | 8U, // MOVT |
| 15306 | 8U, // MOVT_TIX |
| 15307 | 992U, // MOVT_XTI |
| 15308 | 984U, // MOVZWi |
| 15309 | 984U, // MOVZXi |
| 15310 | 0U, // MRRS |
| 15311 | 8U, // MRS |
| 15312 | 135265U, // MSB_ZPmZZ_B |
| 15313 | 537135201U, // MSB_ZPmZZ_D |
| 15314 | 104356097U, // MSB_ZPmZZ_H |
| 15315 | 570691681U, // MSB_ZPmZZ_S |
| 15316 | 0U, // MSR |
| 15317 | 0U, // MSRR |
| 15318 | 0U, // MSRpstateImm1 |
| 15319 | 0U, // MSRpstateImm4 |
| 15320 | 0U, // MSRpstatesvcrImm1 |
| 15321 | 268352U, // MSUBPT |
| 15322 | 268352U, // MSUBWrrr |
| 15323 | 268352U, // MSUBXrrr |
| 15324 | 6210U, // MUL_ZI_B |
| 15325 | 6209U, // MUL_ZI_D |
| 15326 | 225U, // MUL_ZI_H |
| 15327 | 6210U, // MUL_ZI_S |
| 15328 | 33837153U, // MUL_ZPmZ_B |
| 15329 | 67383393U, // MUL_ZPmZ_D |
| 15330 | 101472369U, // MUL_ZPmZ_H |
| 15331 | 134504545U, // MUL_ZPmZ_S |
| 15332 | 6041665U, // MUL_ZZZI_D |
| 15333 | 79985U, // MUL_ZZZI_H |
| 15334 | 6053954U, // MUL_ZZZI_S |
| 15335 | 20546U, // MUL_ZZZ_B |
| 15336 | 12353U, // MUL_ZZZ_D |
| 15337 | 113U, // MUL_ZZZ_H |
| 15338 | 24642U, // MUL_ZZZ_S |
| 15339 | 16448U, // MULv16i8 |
| 15340 | 16448U, // MULv2i32 |
| 15341 | 6045760U, // MULv2i32_indexed |
| 15342 | 16448U, // MULv4i16 |
| 15343 | 6045760U, // MULv4i16_indexed |
| 15344 | 16448U, // MULv4i32 |
| 15345 | 6045760U, // MULv4i32_indexed |
| 15346 | 16448U, // MULv8i16 |
| 15347 | 6045760U, // MULv8i16_indexed |
| 15348 | 16448U, // MULv8i8 |
| 15349 | 984U, // MVNIv2i32 |
| 15350 | 984U, // MVNIv2s_msl |
| 15351 | 984U, // MVNIv4i16 |
| 15352 | 984U, // MVNIv4i32 |
| 15353 | 984U, // MVNIv4s_msl |
| 15354 | 984U, // MVNIv8i16 |
| 15355 | 33837265U, // NANDS_PPzPP |
| 15356 | 33837265U, // NAND_PPzPP |
| 15357 | 67383361U, // NBSL_ZZZZ |
| 15358 | 16U, // NEG_ZPmZ_B |
| 15359 | 32U, // NEG_ZPmZ_D |
| 15360 | 0U, // NEG_ZPmZ_H |
| 15361 | 48U, // NEG_ZPmZ_S |
| 15362 | 0U, // NEGv16i8 |
| 15363 | 0U, // NEGv1i64 |
| 15364 | 0U, // NEGv2i32 |
| 15365 | 0U, // NEGv2i64 |
| 15366 | 0U, // NEGv4i16 |
| 15367 | 0U, // NEGv4i32 |
| 15368 | 0U, // NEGv8i16 |
| 15369 | 0U, // NEGv8i8 |
| 15370 | 33837265U, // NMATCH_PPzZZ_B |
| 15371 | 101472371U, // NMATCH_PPzZZ_H |
| 15372 | 33837265U, // NORS_PPzPP |
| 15373 | 33837265U, // NOR_PPzPP |
| 15374 | 16U, // NOT_ZPmZ_B |
| 15375 | 32U, // NOT_ZPmZ_D |
| 15376 | 0U, // NOT_ZPmZ_H |
| 15377 | 48U, // NOT_ZPmZ_S |
| 15378 | 0U, // NOTv16i8 |
| 15379 | 0U, // NOTv8i8 |
| 15380 | 33837265U, // ORNS_PPzPP |
| 15381 | 28736U, // ORNWrs |
| 15382 | 28736U, // ORNXrs |
| 15383 | 33837265U, // ORN_PPzPP |
| 15384 | 16448U, // ORNv16i8 |
| 15385 | 16448U, // ORNv8i8 |
| 15386 | 20545U, // ORQV_VPZ_B |
| 15387 | 12353U, // ORQV_VPZ_D |
| 15388 | 10305U, // ORQV_VPZ_H |
| 15389 | 24641U, // ORQV_VPZ_S |
| 15390 | 33837265U, // ORRS_PPzPP |
| 15391 | 71744U, // ORRWri |
| 15392 | 28736U, // ORRWrs |
| 15393 | 73792U, // ORRXri |
| 15394 | 28736U, // ORRXrs |
| 15395 | 33837265U, // ORR_PPzPP |
| 15396 | 73793U, // ORR_ZI |
| 15397 | 33837153U, // ORR_ZPmZ_B |
| 15398 | 67383393U, // ORR_ZPmZ_D |
| 15399 | 101472369U, // ORR_ZPmZ_H |
| 15400 | 134504545U, // ORR_ZPmZ_S |
| 15401 | 12353U, // ORR_ZZZ |
| 15402 | 16448U, // ORRv16i8 |
| 15403 | 2U, // ORRv2i32 |
| 15404 | 2U, // ORRv4i16 |
| 15405 | 2U, // ORRv4i32 |
| 15406 | 2U, // ORRv8i16 |
| 15407 | 16448U, // ORRv8i8 |
| 15408 | 0U, // ORV_VPZ_B |
| 15409 | 0U, // ORV_VPZ_D |
| 15410 | 0U, // ORV_VPZ_H |
| 15411 | 0U, // ORV_VPZ_S |
| 15412 | 2U, // PACDA |
| 15413 | 2U, // PACDB |
| 15414 | 0U, // PACDZA |
| 15415 | 0U, // PACDZB |
| 15416 | 6208U, // PACGA |
| 15417 | 2U, // PACIA |
| 15418 | 0U, // PACIA1716 |
| 15419 | 0U, // PACIA171615 |
| 15420 | 0U, // PACIASP |
| 15421 | 0U, // PACIASPPC |
| 15422 | 0U, // PACIAZ |
| 15423 | 2U, // PACIB |
| 15424 | 0U, // PACIB1716 |
| 15425 | 0U, // PACIB171615 |
| 15426 | 0U, // PACIBSP |
| 15427 | 0U, // PACIBSPPC |
| 15428 | 0U, // PACIBZ |
| 15429 | 0U, // PACIZA |
| 15430 | 0U, // PACIZB |
| 15431 | 0U, // PACM |
| 15432 | 0U, // PACNBIASPPC |
| 15433 | 0U, // PACNBIBSPPC |
| 15434 | 4U, // PEXT_2PCI_B |
| 15435 | 4U, // PEXT_2PCI_D |
| 15436 | 4U, // PEXT_2PCI_H |
| 15437 | 4U, // PEXT_2PCI_S |
| 15438 | 455U, // PEXT_PCI_B |
| 15439 | 455U, // PEXT_PCI_D |
| 15440 | 4U, // PEXT_PCI_H |
| 15441 | 455U, // PEXT_PCI_S |
| 15442 | 0U, // PFALSE |
| 15443 | 20545U, // PFIRST_B |
| 15444 | 449U, // PMOV_PZI_B |
| 15445 | 449U, // PMOV_PZI_D |
| 15446 | 4U, // PMOV_PZI_H |
| 15447 | 449U, // PMOV_PZI_S |
| 15448 | 8U, // PMOV_ZIP_B |
| 15449 | 5U, // PMOV_ZIP_D |
| 15450 | 0U, // PMOV_ZIP_H |
| 15451 | 2U, // PMOV_ZIP_S |
| 15452 | 24642U, // PMULLB_ZZZ_D |
| 15453 | 129U, // PMULLB_ZZZ_H |
| 15454 | 0U, // PMULLB_ZZZ_Q |
| 15455 | 24642U, // PMULLT_ZZZ_D |
| 15456 | 129U, // PMULLT_ZZZ_H |
| 15457 | 0U, // PMULLT_ZZZ_Q |
| 15458 | 16448U, // PMULLv16i8 |
| 15459 | 16448U, // PMULLv1i64 |
| 15460 | 16448U, // PMULLv2i64 |
| 15461 | 16448U, // PMULLv8i8 |
| 15462 | 20546U, // PMUL_ZZZ_B |
| 15463 | 16448U, // PMULv16i8 |
| 15464 | 16448U, // PMULv8i8 |
| 15465 | 20545U, // PNEXT_B |
| 15466 | 12353U, // PNEXT_D |
| 15467 | 113U, // PNEXT_H |
| 15468 | 24641U, // PNEXT_S |
| 15469 | 151969U, // PRFB_D_PZI |
| 15470 | 1009U, // PRFB_D_SCALED |
| 15471 | 1025U, // PRFB_D_SXTW_SCALED |
| 15472 | 1041U, // PRFB_D_UXTW_SCALED |
| 15473 | 154017U, // PRFB_PRI |
| 15474 | 1057U, // PRFB_PRR |
| 15475 | 151969U, // PRFB_S_PZI |
| 15476 | 1073U, // PRFB_S_SXTW_SCALED |
| 15477 | 1089U, // PRFB_S_UXTW_SCALED |
| 15478 | 1105U, // PRFD_D_PZI |
| 15479 | 1121U, // PRFD_D_SCALED |
| 15480 | 1137U, // PRFD_D_SXTW_SCALED |
| 15481 | 1153U, // PRFD_D_UXTW_SCALED |
| 15482 | 154017U, // PRFD_PRI |
| 15483 | 1169U, // PRFD_PRR |
| 15484 | 1105U, // PRFD_S_PZI |
| 15485 | 1185U, // PRFD_S_SXTW_SCALED |
| 15486 | 1201U, // PRFD_S_UXTW_SCALED |
| 15487 | 1217U, // PRFH_D_PZI |
| 15488 | 1233U, // PRFH_D_SCALED |
| 15489 | 1249U, // PRFH_D_SXTW_SCALED |
| 15490 | 1265U, // PRFH_D_UXTW_SCALED |
| 15491 | 154017U, // PRFH_PRI |
| 15492 | 1281U, // PRFH_PRR |
| 15493 | 1217U, // PRFH_S_PZI |
| 15494 | 1297U, // PRFH_S_SXTW_SCALED |
| 15495 | 1313U, // PRFH_S_UXTW_SCALED |
| 15496 | 3U, // PRFMl |
| 15497 | 1006901312U, // PRFMroW |
| 15498 | 1040455744U, // PRFMroX |
| 15499 | 124992U, // PRFMui |
| 15500 | 4200512U, // PRFUMi |
| 15501 | 1329U, // PRFW_D_PZI |
| 15502 | 1345U, // PRFW_D_SCALED |
| 15503 | 1361U, // PRFW_D_SXTW_SCALED |
| 15504 | 1377U, // PRFW_D_UXTW_SCALED |
| 15505 | 154017U, // PRFW_PRI |
| 15506 | 1393U, // PRFW_PRR |
| 15507 | 1329U, // PRFW_S_PZI |
| 15508 | 1409U, // PRFW_S_SXTW_SCALED |
| 15509 | 1425U, // PRFW_S_UXTW_SCALED |
| 15510 | 16797761U, // PSEL_PPPRI_B |
| 15511 | 16789569U, // PSEL_PPPRI_D |
| 15512 | 16787521U, // PSEL_PPPRI_H |
| 15513 | 16801857U, // PSEL_PPPRI_S |
| 15514 | 2U, // PTEST_PP |
| 15515 | 3U, // PTRUES_B |
| 15516 | 3U, // PTRUES_D |
| 15517 | 0U, // PTRUES_H |
| 15518 | 3U, // PTRUES_S |
| 15519 | 3U, // PTRUE_B |
| 15520 | 0U, // PTRUE_C_B |
| 15521 | 0U, // PTRUE_C_D |
| 15522 | 0U, // PTRUE_C_H |
| 15523 | 0U, // PTRUE_C_S |
| 15524 | 3U, // PTRUE_D |
| 15525 | 0U, // PTRUE_H |
| 15526 | 3U, // PTRUE_S |
| 15527 | 0U, // PUNPKHI_PP |
| 15528 | 0U, // PUNPKLO_PP |
| 15529 | 10304U, // RADDHNB_ZZZ_B |
| 15530 | 81U, // RADDHNB_ZZZ_H |
| 15531 | 12353U, // RADDHNB_ZZZ_S |
| 15532 | 14401U, // RADDHNT_ZZZ_B |
| 15533 | 49U, // RADDHNT_ZZZ_H |
| 15534 | 2112U, // RADDHNT_ZZZ_S |
| 15535 | 16448U, // RADDHNv2i64_v2i32 |
| 15536 | 18497U, // RADDHNv2i64_v4i32 |
| 15537 | 16448U, // RADDHNv4i32_v4i16 |
| 15538 | 18497U, // RADDHNv4i32_v8i16 |
| 15539 | 18497U, // RADDHNv8i16_v16i8 |
| 15540 | 16448U, // RADDHNv8i16_v8i8 |
| 15541 | 16448U, // RAX1 |
| 15542 | 12353U, // RAX1_ZZZ_D |
| 15543 | 0U, // RBITWr |
| 15544 | 0U, // RBITXr |
| 15545 | 16U, // RBIT_ZPmZ_B |
| 15546 | 32U, // RBIT_ZPmZ_D |
| 15547 | 0U, // RBIT_ZPmZ_H |
| 15548 | 48U, // RBIT_ZPmZ_S |
| 15549 | 0U, // RBITv16i8 |
| 15550 | 0U, // RBITv8i8 |
| 15551 | 4276546U, // RCWCAS |
| 15552 | 4276546U, // RCWCASA |
| 15553 | 4276546U, // RCWCASAL |
| 15554 | 4276546U, // RCWCASL |
| 15555 | 0U, // RCWCASP |
| 15556 | 0U, // RCWCASPA |
| 15557 | 0U, // RCWCASPAL |
| 15558 | 0U, // RCWCASPL |
| 15559 | 7U, // RCWCLR |
| 15560 | 7U, // RCWCLRA |
| 15561 | 7U, // RCWCLRAL |
| 15562 | 7U, // RCWCLRL |
| 15563 | 115012U, // RCWCLRP |
| 15564 | 115012U, // RCWCLRPA |
| 15565 | 115012U, // RCWCLRPAL |
| 15566 | 115012U, // RCWCLRPL |
| 15567 | 7U, // RCWCLRS |
| 15568 | 7U, // RCWCLRSA |
| 15569 | 7U, // RCWCLRSAL |
| 15570 | 7U, // RCWCLRSL |
| 15571 | 115012U, // RCWCLRSP |
| 15572 | 115012U, // RCWCLRSPA |
| 15573 | 115012U, // RCWCLRSPAL |
| 15574 | 115012U, // RCWCLRSPL |
| 15575 | 4276546U, // RCWSCAS |
| 15576 | 4276546U, // RCWSCASA |
| 15577 | 4276546U, // RCWSCASAL |
| 15578 | 4276546U, // RCWSCASL |
| 15579 | 0U, // RCWSCASP |
| 15580 | 0U, // RCWSCASPA |
| 15581 | 0U, // RCWSCASPAL |
| 15582 | 0U, // RCWSCASPL |
| 15583 | 7U, // RCWSET |
| 15584 | 7U, // RCWSETA |
| 15585 | 7U, // RCWSETAL |
| 15586 | 7U, // RCWSETL |
| 15587 | 115012U, // RCWSETP |
| 15588 | 115012U, // RCWSETPA |
| 15589 | 115012U, // RCWSETPAL |
| 15590 | 115012U, // RCWSETPL |
| 15591 | 7U, // RCWSETS |
| 15592 | 7U, // RCWSETSA |
| 15593 | 7U, // RCWSETSAL |
| 15594 | 7U, // RCWSETSL |
| 15595 | 115012U, // RCWSETSP |
| 15596 | 115012U, // RCWSETSPA |
| 15597 | 115012U, // RCWSETSPAL |
| 15598 | 115012U, // RCWSETSPL |
| 15599 | 7U, // RCWSWP |
| 15600 | 7U, // RCWSWPA |
| 15601 | 7U, // RCWSWPAL |
| 15602 | 7U, // RCWSWPL |
| 15603 | 115012U, // RCWSWPP |
| 15604 | 115012U, // RCWSWPPA |
| 15605 | 115012U, // RCWSWPPAL |
| 15606 | 115012U, // RCWSWPPL |
| 15607 | 7U, // RCWSWPS |
| 15608 | 7U, // RCWSWPSA |
| 15609 | 7U, // RCWSWPSAL |
| 15610 | 7U, // RCWSWPSL |
| 15611 | 115012U, // RCWSWPSP |
| 15612 | 115012U, // RCWSWPSPA |
| 15613 | 115012U, // RCWSWPSPAL |
| 15614 | 115012U, // RCWSWPSPL |
| 15615 | 1441U, // RDFFRS_PPz |
| 15616 | 0U, // RDFFR_P |
| 15617 | 1441U, // RDFFR_PPz |
| 15618 | 0U, // RDSVLI_XI |
| 15619 | 0U, // RDVLI_XI |
| 15620 | 0U, // RET |
| 15621 | 0U, // RETAA |
| 15622 | 0U, // RETAASPPCi |
| 15623 | 0U, // RETAASPPCr |
| 15624 | 0U, // RETAB |
| 15625 | 0U, // RETABSPPCi |
| 15626 | 0U, // RETABSPPCr |
| 15627 | 0U, // REV16Wr |
| 15628 | 0U, // REV16Xr |
| 15629 | 0U, // REV16v16i8 |
| 15630 | 0U, // REV16v8i8 |
| 15631 | 0U, // REV32Xr |
| 15632 | 0U, // REV32v16i8 |
| 15633 | 0U, // REV32v4i16 |
| 15634 | 0U, // REV32v8i16 |
| 15635 | 0U, // REV32v8i8 |
| 15636 | 0U, // REV64v16i8 |
| 15637 | 0U, // REV64v2i32 |
| 15638 | 0U, // REV64v4i16 |
| 15639 | 0U, // REV64v4i32 |
| 15640 | 0U, // REV64v8i16 |
| 15641 | 0U, // REV64v8i8 |
| 15642 | 32U, // REVB_ZPmZ_D |
| 15643 | 0U, // REVB_ZPmZ_H |
| 15644 | 48U, // REVB_ZPmZ_S |
| 15645 | 9U, // REVD_ZPmZ |
| 15646 | 32U, // REVH_ZPmZ_D |
| 15647 | 48U, // REVH_ZPmZ_S |
| 15648 | 32U, // REVW_ZPmZ_D |
| 15649 | 0U, // REVWr |
| 15650 | 0U, // REVXr |
| 15651 | 2U, // REV_PP_B |
| 15652 | 1U, // REV_PP_D |
| 15653 | 0U, // REV_PP_H |
| 15654 | 2U, // REV_PP_S |
| 15655 | 2U, // REV_ZZ_B |
| 15656 | 1U, // REV_ZZ_D |
| 15657 | 0U, // REV_ZZ_H |
| 15658 | 2U, // REV_ZZ_S |
| 15659 | 0U, // RMIF |
| 15660 | 6208U, // RORVWr |
| 15661 | 6208U, // RORVXr |
| 15662 | 0U, // RPRFM |
| 15663 | 6208U, // RSHRNB_ZZI_B |
| 15664 | 225U, // RSHRNB_ZZI_H |
| 15665 | 6209U, // RSHRNB_ZZI_S |
| 15666 | 81985U, // RSHRNT_ZZI_B |
| 15667 | 417U, // RSHRNT_ZZI_H |
| 15668 | 81984U, // RSHRNT_ZZI_S |
| 15669 | 81985U, // RSHRNv16i8_shift |
| 15670 | 6208U, // RSHRNv2i32_shift |
| 15671 | 6208U, // RSHRNv4i16_shift |
| 15672 | 81985U, // RSHRNv4i32_shift |
| 15673 | 81985U, // RSHRNv8i16_shift |
| 15674 | 6208U, // RSHRNv8i8_shift |
| 15675 | 10304U, // RSUBHNB_ZZZ_B |
| 15676 | 81U, // RSUBHNB_ZZZ_H |
| 15677 | 12353U, // RSUBHNB_ZZZ_S |
| 15678 | 14401U, // RSUBHNT_ZZZ_B |
| 15679 | 49U, // RSUBHNT_ZZZ_H |
| 15680 | 2112U, // RSUBHNT_ZZZ_S |
| 15681 | 16448U, // RSUBHNv2i64_v2i32 |
| 15682 | 18497U, // RSUBHNv2i64_v4i32 |
| 15683 | 16448U, // RSUBHNv4i32_v4i16 |
| 15684 | 18497U, // RSUBHNv4i32_v8i16 |
| 15685 | 18497U, // RSUBHNv8i16_v16i8 |
| 15686 | 16448U, // RSUBHNv8i16_v8i8 |
| 15687 | 4160U, // SABALB_ZZZ_D |
| 15688 | 17U, // SABALB_ZZZ_H |
| 15689 | 14401U, // SABALB_ZZZ_S |
| 15690 | 4160U, // SABALT_ZZZ_D |
| 15691 | 17U, // SABALT_ZZZ_H |
| 15692 | 14401U, // SABALT_ZZZ_S |
| 15693 | 18497U, // SABALv16i8_v8i16 |
| 15694 | 18497U, // SABALv2i32_v2i64 |
| 15695 | 18497U, // SABALv4i16_v4i32 |
| 15696 | 18497U, // SABALv4i32_v2i64 |
| 15697 | 18497U, // SABALv8i16_v4i32 |
| 15698 | 18497U, // SABALv8i8_v8i16 |
| 15699 | 19U, // SABA_ZZZ_B |
| 15700 | 2112U, // SABA_ZZZ_D |
| 15701 | 257U, // SABA_ZZZ_H |
| 15702 | 4160U, // SABA_ZZZ_S |
| 15703 | 18497U, // SABAv16i8 |
| 15704 | 18497U, // SABAv2i32 |
| 15705 | 18497U, // SABAv4i16 |
| 15706 | 18497U, // SABAv4i32 |
| 15707 | 18497U, // SABAv8i16 |
| 15708 | 18497U, // SABAv8i8 |
| 15709 | 24642U, // SABDLB_ZZZ_D |
| 15710 | 129U, // SABDLB_ZZZ_H |
| 15711 | 10304U, // SABDLB_ZZZ_S |
| 15712 | 24642U, // SABDLT_ZZZ_D |
| 15713 | 129U, // SABDLT_ZZZ_H |
| 15714 | 10304U, // SABDLT_ZZZ_S |
| 15715 | 16448U, // SABDLv16i8_v8i16 |
| 15716 | 16448U, // SABDLv2i32_v2i64 |
| 15717 | 16448U, // SABDLv4i16_v4i32 |
| 15718 | 16448U, // SABDLv4i32_v2i64 |
| 15719 | 16448U, // SABDLv8i16_v4i32 |
| 15720 | 16448U, // SABDLv8i8_v8i16 |
| 15721 | 33837153U, // SABD_ZPmZ_B |
| 15722 | 67383393U, // SABD_ZPmZ_D |
| 15723 | 101472369U, // SABD_ZPmZ_H |
| 15724 | 134504545U, // SABD_ZPmZ_S |
| 15725 | 16448U, // SABDv16i8 |
| 15726 | 16448U, // SABDv2i32 |
| 15727 | 16448U, // SABDv4i16 |
| 15728 | 16448U, // SABDv4i32 |
| 15729 | 16448U, // SABDv8i16 |
| 15730 | 16448U, // SABDv8i8 |
| 15731 | 4193U, // SADALP_ZPmZ_D |
| 15732 | 17U, // SADALP_ZPmZ_H |
| 15733 | 14433U, // SADALP_ZPmZ_S |
| 15734 | 1U, // SADALPv16i8_v8i16 |
| 15735 | 1U, // SADALPv2i32_v1i64 |
| 15736 | 1U, // SADALPv4i16_v2i32 |
| 15737 | 1U, // SADALPv4i32_v2i64 |
| 15738 | 1U, // SADALPv8i16_v4i32 |
| 15739 | 1U, // SADALPv8i8_v4i16 |
| 15740 | 24642U, // SADDLBT_ZZZ_D |
| 15741 | 129U, // SADDLBT_ZZZ_H |
| 15742 | 10304U, // SADDLBT_ZZZ_S |
| 15743 | 24642U, // SADDLB_ZZZ_D |
| 15744 | 129U, // SADDLB_ZZZ_H |
| 15745 | 10304U, // SADDLB_ZZZ_S |
| 15746 | 0U, // SADDLPv16i8_v8i16 |
| 15747 | 0U, // SADDLPv2i32_v1i64 |
| 15748 | 0U, // SADDLPv4i16_v2i32 |
| 15749 | 0U, // SADDLPv4i32_v2i64 |
| 15750 | 0U, // SADDLPv8i16_v4i32 |
| 15751 | 0U, // SADDLPv8i8_v4i16 |
| 15752 | 24642U, // SADDLT_ZZZ_D |
| 15753 | 129U, // SADDLT_ZZZ_H |
| 15754 | 10304U, // SADDLT_ZZZ_S |
| 15755 | 0U, // SADDLVv16i8v |
| 15756 | 0U, // SADDLVv4i16v |
| 15757 | 0U, // SADDLVv4i32v |
| 15758 | 0U, // SADDLVv8i16v |
| 15759 | 0U, // SADDLVv8i8v |
| 15760 | 16448U, // SADDLv16i8_v8i16 |
| 15761 | 16448U, // SADDLv2i32_v2i64 |
| 15762 | 16448U, // SADDLv4i16_v4i32 |
| 15763 | 16448U, // SADDLv4i32_v2i64 |
| 15764 | 16448U, // SADDLv8i16_v4i32 |
| 15765 | 16448U, // SADDLv8i8_v8i16 |
| 15766 | 0U, // SADDV_VPZ_B |
| 15767 | 0U, // SADDV_VPZ_H |
| 15768 | 0U, // SADDV_VPZ_S |
| 15769 | 24641U, // SADDWB_ZZZ_D |
| 15770 | 129U, // SADDWB_ZZZ_H |
| 15771 | 10306U, // SADDWB_ZZZ_S |
| 15772 | 24641U, // SADDWT_ZZZ_D |
| 15773 | 129U, // SADDWT_ZZZ_H |
| 15774 | 10306U, // SADDWT_ZZZ_S |
| 15775 | 16448U, // SADDWv16i8_v8i16 |
| 15776 | 16448U, // SADDWv2i32_v2i64 |
| 15777 | 16448U, // SADDWv4i16_v4i32 |
| 15778 | 16448U, // SADDWv4i32_v2i64 |
| 15779 | 16448U, // SADDWv8i16_v4i32 |
| 15780 | 16448U, // SADDWv8i8_v8i16 |
| 15781 | 0U, // SB |
| 15782 | 2112U, // SBCLB_ZZZ_D |
| 15783 | 4160U, // SBCLB_ZZZ_S |
| 15784 | 2112U, // SBCLT_ZZZ_D |
| 15785 | 4160U, // SBCLT_ZZZ_S |
| 15786 | 6208U, // SBCSWr |
| 15787 | 6208U, // SBCSXr |
| 15788 | 6208U, // SBCWr |
| 15789 | 6208U, // SBCXr |
| 15790 | 268352U, // SBFMWri |
| 15791 | 268352U, // SBFMXri |
| 15792 | 17U, // SCLAMP_VG2_2Z2Z_B |
| 15793 | 33U, // SCLAMP_VG2_2Z2Z_D |
| 15794 | 257U, // SCLAMP_VG2_2Z2Z_H |
| 15795 | 49U, // SCLAMP_VG2_2Z2Z_S |
| 15796 | 17U, // SCLAMP_VG4_4Z4Z_B |
| 15797 | 33U, // SCLAMP_VG4_4Z4Z_D |
| 15798 | 257U, // SCLAMP_VG4_4Z4Z_H |
| 15799 | 49U, // SCLAMP_VG4_4Z4Z_S |
| 15800 | 19U, // SCLAMP_ZZZ_B |
| 15801 | 2112U, // SCLAMP_ZZZ_D |
| 15802 | 257U, // SCLAMP_ZZZ_H |
| 15803 | 4160U, // SCLAMP_ZZZ_S |
| 15804 | 6208U, // SCVTFSWDri |
| 15805 | 6208U, // SCVTFSWHri |
| 15806 | 6208U, // SCVTFSWSri |
| 15807 | 6208U, // SCVTFSXDri |
| 15808 | 6208U, // SCVTFSXHri |
| 15809 | 6208U, // SCVTFSXSri |
| 15810 | 0U, // SCVTFUWDri |
| 15811 | 0U, // SCVTFUWHri |
| 15812 | 0U, // SCVTFUWSri |
| 15813 | 0U, // SCVTFUXDri |
| 15814 | 0U, // SCVTFUXHri |
| 15815 | 0U, // SCVTFUXSri |
| 15816 | 0U, // SCVTF_2Z2Z_StoS |
| 15817 | 0U, // SCVTF_4Z4Z_StoS |
| 15818 | 32U, // SCVTF_ZPmZ_DtoD |
| 15819 | 5U, // SCVTF_ZPmZ_DtoH |
| 15820 | 32U, // SCVTF_ZPmZ_DtoS |
| 15821 | 0U, // SCVTF_ZPmZ_HtoH |
| 15822 | 48U, // SCVTF_ZPmZ_StoD |
| 15823 | 2U, // SCVTF_ZPmZ_StoH |
| 15824 | 48U, // SCVTF_ZPmZ_StoS |
| 15825 | 6208U, // SCVTFd |
| 15826 | 6208U, // SCVTFh |
| 15827 | 6208U, // SCVTFs |
| 15828 | 0U, // SCVTFv1i16 |
| 15829 | 0U, // SCVTFv1i32 |
| 15830 | 0U, // SCVTFv1i64 |
| 15831 | 0U, // SCVTFv2f32 |
| 15832 | 0U, // SCVTFv2f64 |
| 15833 | 6208U, // SCVTFv2i32_shift |
| 15834 | 6208U, // SCVTFv2i64_shift |
| 15835 | 0U, // SCVTFv4f16 |
| 15836 | 0U, // SCVTFv4f32 |
| 15837 | 6208U, // SCVTFv4i16_shift |
| 15838 | 6208U, // SCVTFv4i32_shift |
| 15839 | 0U, // SCVTFv8f16 |
| 15840 | 6208U, // SCVTFv8i16_shift |
| 15841 | 67383393U, // SDIVR_ZPmZ_D |
| 15842 | 134504545U, // SDIVR_ZPmZ_S |
| 15843 | 6208U, // SDIVWr |
| 15844 | 6208U, // SDIVXr |
| 15845 | 67383393U, // SDIV_ZPmZ_D |
| 15846 | 134504545U, // SDIV_ZPmZ_S |
| 15847 | 92865U, // SDOT_VG2_M2Z2Z_BtoS |
| 15848 | 3168497U, // SDOT_VG2_M2Z2Z_HtoD |
| 15849 | 3168497U, // SDOT_VG2_M2Z2Z_HtoS |
| 15850 | 5599937U, // SDOT_VG2_M2ZZI_BToS |
| 15851 | 204757233U, // SDOT_VG2_M2ZZI_HToS |
| 15852 | 204757233U, // SDOT_VG2_M2ZZI_HtoD |
| 15853 | 94913U, // SDOT_VG2_M2ZZ_BtoS |
| 15854 | 104093937U, // SDOT_VG2_M2ZZ_HtoD |
| 15855 | 104093937U, // SDOT_VG2_M2ZZ_HtoS |
| 15856 | 92865U, // SDOT_VG4_M4Z4Z_BtoS |
| 15857 | 3168497U, // SDOT_VG4_M4Z4Z_HtoD |
| 15858 | 3168497U, // SDOT_VG4_M4Z4Z_HtoS |
| 15859 | 5599937U, // SDOT_VG4_M4ZZI_BToS |
| 15860 | 204757233U, // SDOT_VG4_M4ZZI_HToS |
| 15861 | 204757233U, // SDOT_VG4_M4ZZI_HtoD |
| 15862 | 94913U, // SDOT_VG4_M4ZZ_BtoS |
| 15863 | 104093937U, // SDOT_VG4_M4ZZ_HtoD |
| 15864 | 104093937U, // SDOT_VG4_M4ZZ_HtoS |
| 15865 | 103561281U, // SDOT_ZZZI_D |
| 15866 | 103561281U, // SDOT_ZZZI_HtoS |
| 15867 | 77843U, // SDOT_ZZZI_S |
| 15868 | 14401U, // SDOT_ZZZ_D |
| 15869 | 14401U, // SDOT_ZZZ_HtoS |
| 15870 | 19U, // SDOT_ZZZ_S |
| 15871 | 103565377U, // SDOTlanev16i8 |
| 15872 | 103565377U, // SDOTlanev8i8 |
| 15873 | 0U, // SDOTv16i8 |
| 15874 | 0U, // SDOTv8i8 |
| 15875 | 33837121U, // SEL_PPPP |
| 15876 | 17063345U, // SEL_VG2_2ZC2Z2Z_B |
| 15877 | 17324545U, // SEL_VG2_2ZC2Z2Z_D |
| 15878 | 17586449U, // SEL_VG2_2ZC2Z2Z_H |
| 15879 | 17848849U, // SEL_VG2_2ZC2Z2Z_S |
| 15880 | 17063345U, // SEL_VG4_4ZC4Z4Z_B |
| 15881 | 17324545U, // SEL_VG4_4ZC4Z4Z_D |
| 15882 | 17586449U, // SEL_VG4_4ZC4Z4Z_H |
| 15883 | 17848849U, // SEL_VG4_4ZC4Z4Z_S |
| 15884 | 33837121U, // SEL_ZPZZ_B |
| 15885 | 67383361U, // SEL_ZPZZ_D |
| 15886 | 101472369U, // SEL_ZPZZ_H |
| 15887 | 134504513U, // SEL_ZPZZ_S |
| 15888 | 0U, // SETE |
| 15889 | 0U, // SETEN |
| 15890 | 0U, // SETET |
| 15891 | 0U, // SETETN |
| 15892 | 0U, // SETF16 |
| 15893 | 0U, // SETF8 |
| 15894 | 0U, // SETFFR |
| 15895 | 0U, // SETGM |
| 15896 | 0U, // SETGMN |
| 15897 | 0U, // SETGMT |
| 15898 | 0U, // SETGMTN |
| 15899 | 0U, // SETGP |
| 15900 | 0U, // SETGPN |
| 15901 | 0U, // SETGPT |
| 15902 | 0U, // SETGPTN |
| 15903 | 0U, // SETM |
| 15904 | 0U, // SETMN |
| 15905 | 0U, // SETMT |
| 15906 | 0U, // SETMTN |
| 15907 | 0U, // SETP |
| 15908 | 0U, // SETPN |
| 15909 | 0U, // SETPT |
| 15910 | 0U, // SETPTN |
| 15911 | 18498U, // SHA1Crrr |
| 15912 | 0U, // SHA1Hrr |
| 15913 | 18498U, // SHA1Mrrr |
| 15914 | 18498U, // SHA1Prrr |
| 15915 | 18497U, // SHA1SU0rrr |
| 15916 | 1U, // SHA1SU1rr |
| 15917 | 18498U, // SHA256H2rrr |
| 15918 | 18498U, // SHA256Hrrr |
| 15919 | 1U, // SHA256SU0rr |
| 15920 | 18497U, // SHA256SU1rrr |
| 15921 | 18498U, // SHA512H |
| 15922 | 18498U, // SHA512H2 |
| 15923 | 1U, // SHA512SU0 |
| 15924 | 18497U, // SHA512SU1 |
| 15925 | 33837153U, // SHADD_ZPmZ_B |
| 15926 | 67383393U, // SHADD_ZPmZ_D |
| 15927 | 101472369U, // SHADD_ZPmZ_H |
| 15928 | 134504545U, // SHADD_ZPmZ_S |
| 15929 | 16448U, // SHADDv16i8 |
| 15930 | 16448U, // SHADDv2i32 |
| 15931 | 16448U, // SHADDv4i16 |
| 15932 | 16448U, // SHADDv4i32 |
| 15933 | 16448U, // SHADDv8i16 |
| 15934 | 16448U, // SHADDv8i8 |
| 15935 | 1472U, // SHLLv16i8 |
| 15936 | 1488U, // SHLLv2i32 |
| 15937 | 1504U, // SHLLv4i16 |
| 15938 | 1488U, // SHLLv4i32 |
| 15939 | 1504U, // SHLLv8i16 |
| 15940 | 1472U, // SHLLv8i8 |
| 15941 | 6208U, // SHLd |
| 15942 | 6208U, // SHLv16i8_shift |
| 15943 | 6208U, // SHLv2i32_shift |
| 15944 | 6208U, // SHLv2i64_shift |
| 15945 | 6208U, // SHLv4i16_shift |
| 15946 | 6208U, // SHLv4i32_shift |
| 15947 | 6208U, // SHLv8i16_shift |
| 15948 | 6208U, // SHLv8i8_shift |
| 15949 | 6208U, // SHRNB_ZZI_B |
| 15950 | 225U, // SHRNB_ZZI_H |
| 15951 | 6209U, // SHRNB_ZZI_S |
| 15952 | 81985U, // SHRNT_ZZI_B |
| 15953 | 417U, // SHRNT_ZZI_H |
| 15954 | 81984U, // SHRNT_ZZI_S |
| 15955 | 81985U, // SHRNv16i8_shift |
| 15956 | 6208U, // SHRNv2i32_shift |
| 15957 | 6208U, // SHRNv4i16_shift |
| 15958 | 81985U, // SHRNv4i32_shift |
| 15959 | 81985U, // SHRNv8i16_shift |
| 15960 | 6208U, // SHRNv8i8_shift |
| 15961 | 33837153U, // SHSUBR_ZPmZ_B |
| 15962 | 67383393U, // SHSUBR_ZPmZ_D |
| 15963 | 101472369U, // SHSUBR_ZPmZ_H |
| 15964 | 134504545U, // SHSUBR_ZPmZ_S |
| 15965 | 33837153U, // SHSUB_ZPmZ_B |
| 15966 | 67383393U, // SHSUB_ZPmZ_D |
| 15967 | 101472369U, // SHSUB_ZPmZ_H |
| 15968 | 134504545U, // SHSUB_ZPmZ_S |
| 15969 | 16448U, // SHSUBv16i8 |
| 15970 | 16448U, // SHSUBv2i32 |
| 15971 | 16448U, // SHSUBv4i16 |
| 15972 | 16448U, // SHSUBv4i32 |
| 15973 | 16448U, // SHSUBv8i16 |
| 15974 | 16448U, // SHSUBv8i8 |
| 15975 | 419U, // SLI_ZZI_B |
| 15976 | 81984U, // SLI_ZZI_D |
| 15977 | 417U, // SLI_ZZI_H |
| 15978 | 81984U, // SLI_ZZI_S |
| 15979 | 81986U, // SLId |
| 15980 | 81985U, // SLIv16i8_shift |
| 15981 | 81985U, // SLIv2i32_shift |
| 15982 | 81985U, // SLIv2i64_shift |
| 15983 | 81985U, // SLIv4i16_shift |
| 15984 | 81985U, // SLIv4i32_shift |
| 15985 | 81985U, // SLIv8i16_shift |
| 15986 | 81985U, // SLIv8i8_shift |
| 15987 | 18497U, // SM3PARTW1 |
| 15988 | 18497U, // SM3PARTW2 |
| 15989 | 168050752U, // SM3SS1 |
| 15990 | 103565377U, // SM3TT1A |
| 15991 | 103565377U, // SM3TT1B |
| 15992 | 103565377U, // SM3TT2A |
| 15993 | 103565377U, // SM3TT2B |
| 15994 | 1U, // SM4E |
| 15995 | 24642U, // SM4EKEY_ZZZ_S |
| 15996 | 16448U, // SM4ENCKEY |
| 15997 | 24642U, // SM4E_ZZZ_S |
| 15998 | 268352U, // SMADDLrrr |
| 15999 | 33837153U, // SMAXP_ZPmZ_B |
| 16000 | 67383393U, // SMAXP_ZPmZ_D |
| 16001 | 101472369U, // SMAXP_ZPmZ_H |
| 16002 | 134504545U, // SMAXP_ZPmZ_S |
| 16003 | 16448U, // SMAXPv16i8 |
| 16004 | 16448U, // SMAXPv2i32 |
| 16005 | 16448U, // SMAXPv4i16 |
| 16006 | 16448U, // SMAXPv4i32 |
| 16007 | 16448U, // SMAXPv8i16 |
| 16008 | 16448U, // SMAXPv8i8 |
| 16009 | 20545U, // SMAXQV_VPZ_B |
| 16010 | 12353U, // SMAXQV_VPZ_D |
| 16011 | 10305U, // SMAXQV_VPZ_H |
| 16012 | 24641U, // SMAXQV_VPZ_S |
| 16013 | 0U, // SMAXV_VPZ_B |
| 16014 | 0U, // SMAXV_VPZ_D |
| 16015 | 0U, // SMAXV_VPZ_H |
| 16016 | 0U, // SMAXV_VPZ_S |
| 16017 | 0U, // SMAXVv16i8v |
| 16018 | 0U, // SMAXVv4i16v |
| 16019 | 0U, // SMAXVv4i32v |
| 16020 | 0U, // SMAXVv8i16v |
| 16021 | 0U, // SMAXVv8i8v |
| 16022 | 6208U, // SMAXWri |
| 16023 | 6208U, // SMAXWrr |
| 16024 | 6208U, // SMAXXri |
| 16025 | 6208U, // SMAXXrr |
| 16026 | 1457U, // SMAX_VG2_2Z2Z_B |
| 16027 | 513U, // SMAX_VG2_2Z2Z_D |
| 16028 | 273U, // SMAX_VG2_2Z2Z_H |
| 16029 | 529U, // SMAX_VG2_2Z2Z_S |
| 16030 | 129U, // SMAX_VG2_2ZZ_B |
| 16031 | 145U, // SMAX_VG2_2ZZ_D |
| 16032 | 113U, // SMAX_VG2_2ZZ_H |
| 16033 | 81U, // SMAX_VG2_2ZZ_S |
| 16034 | 1457U, // SMAX_VG4_4Z4Z_B |
| 16035 | 513U, // SMAX_VG4_4Z4Z_D |
| 16036 | 273U, // SMAX_VG4_4Z4Z_H |
| 16037 | 529U, // SMAX_VG4_4Z4Z_S |
| 16038 | 129U, // SMAX_VG4_4ZZ_B |
| 16039 | 145U, // SMAX_VG4_4ZZ_D |
| 16040 | 113U, // SMAX_VG4_4ZZ_H |
| 16041 | 81U, // SMAX_VG4_4ZZ_S |
| 16042 | 6210U, // SMAX_ZI_B |
| 16043 | 6209U, // SMAX_ZI_D |
| 16044 | 225U, // SMAX_ZI_H |
| 16045 | 6210U, // SMAX_ZI_S |
| 16046 | 33837153U, // SMAX_ZPmZ_B |
| 16047 | 67383393U, // SMAX_ZPmZ_D |
| 16048 | 101472369U, // SMAX_ZPmZ_H |
| 16049 | 134504545U, // SMAX_ZPmZ_S |
| 16050 | 16448U, // SMAXv16i8 |
| 16051 | 16448U, // SMAXv2i32 |
| 16052 | 16448U, // SMAXv4i16 |
| 16053 | 16448U, // SMAXv4i32 |
| 16054 | 16448U, // SMAXv8i16 |
| 16055 | 16448U, // SMAXv8i8 |
| 16056 | 0U, // SMC |
| 16057 | 33837153U, // SMINP_ZPmZ_B |
| 16058 | 67383393U, // SMINP_ZPmZ_D |
| 16059 | 101472369U, // SMINP_ZPmZ_H |
| 16060 | 134504545U, // SMINP_ZPmZ_S |
| 16061 | 16448U, // SMINPv16i8 |
| 16062 | 16448U, // SMINPv2i32 |
| 16063 | 16448U, // SMINPv4i16 |
| 16064 | 16448U, // SMINPv4i32 |
| 16065 | 16448U, // SMINPv8i16 |
| 16066 | 16448U, // SMINPv8i8 |
| 16067 | 20545U, // SMINQV_VPZ_B |
| 16068 | 12353U, // SMINQV_VPZ_D |
| 16069 | 10305U, // SMINQV_VPZ_H |
| 16070 | 24641U, // SMINQV_VPZ_S |
| 16071 | 0U, // SMINV_VPZ_B |
| 16072 | 0U, // SMINV_VPZ_D |
| 16073 | 0U, // SMINV_VPZ_H |
| 16074 | 0U, // SMINV_VPZ_S |
| 16075 | 0U, // SMINVv16i8v |
| 16076 | 0U, // SMINVv4i16v |
| 16077 | 0U, // SMINVv4i32v |
| 16078 | 0U, // SMINVv8i16v |
| 16079 | 0U, // SMINVv8i8v |
| 16080 | 6208U, // SMINWri |
| 16081 | 6208U, // SMINWrr |
| 16082 | 6208U, // SMINXri |
| 16083 | 6208U, // SMINXrr |
| 16084 | 1457U, // SMIN_VG2_2Z2Z_B |
| 16085 | 513U, // SMIN_VG2_2Z2Z_D |
| 16086 | 273U, // SMIN_VG2_2Z2Z_H |
| 16087 | 529U, // SMIN_VG2_2Z2Z_S |
| 16088 | 129U, // SMIN_VG2_2ZZ_B |
| 16089 | 145U, // SMIN_VG2_2ZZ_D |
| 16090 | 113U, // SMIN_VG2_2ZZ_H |
| 16091 | 81U, // SMIN_VG2_2ZZ_S |
| 16092 | 1457U, // SMIN_VG4_4Z4Z_B |
| 16093 | 513U, // SMIN_VG4_4Z4Z_D |
| 16094 | 273U, // SMIN_VG4_4Z4Z_H |
| 16095 | 529U, // SMIN_VG4_4Z4Z_S |
| 16096 | 129U, // SMIN_VG4_4ZZ_B |
| 16097 | 145U, // SMIN_VG4_4ZZ_D |
| 16098 | 113U, // SMIN_VG4_4ZZ_H |
| 16099 | 81U, // SMIN_VG4_4ZZ_S |
| 16100 | 6210U, // SMIN_ZI_B |
| 16101 | 6209U, // SMIN_ZI_D |
| 16102 | 225U, // SMIN_ZI_H |
| 16103 | 6210U, // SMIN_ZI_S |
| 16104 | 33837153U, // SMIN_ZPmZ_B |
| 16105 | 67383393U, // SMIN_ZPmZ_D |
| 16106 | 101472369U, // SMIN_ZPmZ_H |
| 16107 | 134504545U, // SMIN_ZPmZ_S |
| 16108 | 16448U, // SMINv16i8 |
| 16109 | 16448U, // SMINv2i32 |
| 16110 | 16448U, // SMINv4i16 |
| 16111 | 16448U, // SMINv4i32 |
| 16112 | 16448U, // SMINv8i16 |
| 16113 | 16448U, // SMINv8i8 |
| 16114 | 103551040U, // SMLALB_ZZZI_D |
| 16115 | 103561281U, // SMLALB_ZZZI_S |
| 16116 | 4160U, // SMLALB_ZZZ_D |
| 16117 | 17U, // SMLALB_ZZZ_H |
| 16118 | 14401U, // SMLALB_ZZZ_S |
| 16119 | 76498U, // SMLALL_MZZI_BtoS |
| 16120 | 76066U, // SMLALL_MZZI_HtoD |
| 16121 | 722U, // SMLALL_MZZ_BtoS |
| 16122 | 290U, // SMLALL_MZZ_HtoD |
| 16123 | 92865U, // SMLALL_VG2_M2Z2Z_BtoS |
| 16124 | 3168497U, // SMLALL_VG2_M2Z2Z_HtoD |
| 16125 | 5599937U, // SMLALL_VG2_M2ZZI_BtoS |
| 16126 | 204757233U, // SMLALL_VG2_M2ZZI_HtoD |
| 16127 | 94917U, // SMLALL_VG2_M2ZZ_BtoS |
| 16128 | 104093941U, // SMLALL_VG2_M2ZZ_HtoD |
| 16129 | 92865U, // SMLALL_VG4_M4Z4Z_BtoS |
| 16130 | 3168497U, // SMLALL_VG4_M4Z4Z_HtoD |
| 16131 | 5599937U, // SMLALL_VG4_M4ZZI_BtoS |
| 16132 | 204757233U, // SMLALL_VG4_M4ZZI_HtoD |
| 16133 | 94918U, // SMLALL_VG4_M4ZZ_BtoS |
| 16134 | 104093942U, // SMLALL_VG4_M4ZZ_HtoD |
| 16135 | 103551040U, // SMLALT_ZZZI_D |
| 16136 | 103561281U, // SMLALT_ZZZI_S |
| 16137 | 4160U, // SMLALT_ZZZ_D |
| 16138 | 17U, // SMLALT_ZZZ_H |
| 16139 | 14401U, // SMLALT_ZZZ_S |
| 16140 | 76066U, // SMLAL_MZZI_HtoS |
| 16141 | 290U, // SMLAL_MZZ_HtoS |
| 16142 | 3168497U, // SMLAL_VG2_M2Z2Z_HtoS |
| 16143 | 204757233U, // SMLAL_VG2_M2ZZI_S |
| 16144 | 104093937U, // SMLAL_VG2_M2ZZ_HtoS |
| 16145 | 3168497U, // SMLAL_VG4_M4Z4Z_HtoS |
| 16146 | 204757233U, // SMLAL_VG4_M4ZZI_HtoS |
| 16147 | 104093937U, // SMLAL_VG4_M4ZZ_HtoS |
| 16148 | 18497U, // SMLALv16i8_v8i16 |
| 16149 | 103565377U, // SMLALv2i32_indexed |
| 16150 | 18497U, // SMLALv2i32_v2i64 |
| 16151 | 103565377U, // SMLALv4i16_indexed |
| 16152 | 18497U, // SMLALv4i16_v4i32 |
| 16153 | 103565377U, // SMLALv4i32_indexed |
| 16154 | 18497U, // SMLALv4i32_v2i64 |
| 16155 | 103565377U, // SMLALv8i16_indexed |
| 16156 | 18497U, // SMLALv8i16_v4i32 |
| 16157 | 18497U, // SMLALv8i8_v8i16 |
| 16158 | 103551040U, // SMLSLB_ZZZI_D |
| 16159 | 103561281U, // SMLSLB_ZZZI_S |
| 16160 | 4160U, // SMLSLB_ZZZ_D |
| 16161 | 17U, // SMLSLB_ZZZ_H |
| 16162 | 14401U, // SMLSLB_ZZZ_S |
| 16163 | 76498U, // SMLSLL_MZZI_BtoS |
| 16164 | 76066U, // SMLSLL_MZZI_HtoD |
| 16165 | 722U, // SMLSLL_MZZ_BtoS |
| 16166 | 290U, // SMLSLL_MZZ_HtoD |
| 16167 | 92865U, // SMLSLL_VG2_M2Z2Z_BtoS |
| 16168 | 3168497U, // SMLSLL_VG2_M2Z2Z_HtoD |
| 16169 | 5599937U, // SMLSLL_VG2_M2ZZI_BtoS |
| 16170 | 204757233U, // SMLSLL_VG2_M2ZZI_HtoD |
| 16171 | 94917U, // SMLSLL_VG2_M2ZZ_BtoS |
| 16172 | 104093941U, // SMLSLL_VG2_M2ZZ_HtoD |
| 16173 | 92865U, // SMLSLL_VG4_M4Z4Z_BtoS |
| 16174 | 3168497U, // SMLSLL_VG4_M4Z4Z_HtoD |
| 16175 | 5599937U, // SMLSLL_VG4_M4ZZI_BtoS |
| 16176 | 204757233U, // SMLSLL_VG4_M4ZZI_HtoD |
| 16177 | 94918U, // SMLSLL_VG4_M4ZZ_BtoS |
| 16178 | 104093942U, // SMLSLL_VG4_M4ZZ_HtoD |
| 16179 | 103551040U, // SMLSLT_ZZZI_D |
| 16180 | 103561281U, // SMLSLT_ZZZI_S |
| 16181 | 4160U, // SMLSLT_ZZZ_D |
| 16182 | 17U, // SMLSLT_ZZZ_H |
| 16183 | 14401U, // SMLSLT_ZZZ_S |
| 16184 | 76066U, // SMLSL_MZZI_HtoS |
| 16185 | 290U, // SMLSL_MZZ_HtoS |
| 16186 | 3168497U, // SMLSL_VG2_M2Z2Z_HtoS |
| 16187 | 204757233U, // SMLSL_VG2_M2ZZI_S |
| 16188 | 104093937U, // SMLSL_VG2_M2ZZ_HtoS |
| 16189 | 3168497U, // SMLSL_VG4_M4Z4Z_HtoS |
| 16190 | 204757233U, // SMLSL_VG4_M4ZZI_HtoS |
| 16191 | 104093937U, // SMLSL_VG4_M4ZZ_HtoS |
| 16192 | 18497U, // SMLSLv16i8_v8i16 |
| 16193 | 103565377U, // SMLSLv2i32_indexed |
| 16194 | 18497U, // SMLSLv2i32_v2i64 |
| 16195 | 103565377U, // SMLSLv4i16_indexed |
| 16196 | 18497U, // SMLSLv4i16_v4i32 |
| 16197 | 103565377U, // SMLSLv4i32_indexed |
| 16198 | 18497U, // SMLSLv4i32_v2i64 |
| 16199 | 103565377U, // SMLSLv8i16_indexed |
| 16200 | 18497U, // SMLSLv8i16_v4i32 |
| 16201 | 18497U, // SMLSLv8i8_v8i16 |
| 16202 | 0U, // SMMLA |
| 16203 | 19U, // SMMLA_ZZZ |
| 16204 | 0U, // SMOPA_MPPZZ_D |
| 16205 | 0U, // SMOPA_MPPZZ_HtoS |
| 16206 | 0U, // SMOPA_MPPZZ_S |
| 16207 | 0U, // SMOPS_MPPZZ_D |
| 16208 | 0U, // SMOPS_MPPZZ_HtoS |
| 16209 | 0U, // SMOPS_MPPZZ_S |
| 16210 | 448U, // SMOVvi16to32 |
| 16211 | 448U, // SMOVvi16to32_idx0 |
| 16212 | 448U, // SMOVvi16to64 |
| 16213 | 448U, // SMOVvi16to64_idx0 |
| 16214 | 448U, // SMOVvi32to64 |
| 16215 | 448U, // SMOVvi32to64_idx0 |
| 16216 | 448U, // SMOVvi8to32 |
| 16217 | 448U, // SMOVvi8to32_idx0 |
| 16218 | 448U, // SMOVvi8to64 |
| 16219 | 448U, // SMOVvi8to64_idx0 |
| 16220 | 268352U, // SMSUBLrrr |
| 16221 | 33837153U, // SMULH_ZPmZ_B |
| 16222 | 67383393U, // SMULH_ZPmZ_D |
| 16223 | 101472369U, // SMULH_ZPmZ_H |
| 16224 | 134504545U, // SMULH_ZPmZ_S |
| 16225 | 20546U, // SMULH_ZZZ_B |
| 16226 | 12353U, // SMULH_ZZZ_D |
| 16227 | 113U, // SMULH_ZZZ_H |
| 16228 | 24642U, // SMULH_ZZZ_S |
| 16229 | 6208U, // SMULHrr |
| 16230 | 6053954U, // SMULLB_ZZZI_D |
| 16231 | 6039616U, // SMULLB_ZZZI_S |
| 16232 | 24642U, // SMULLB_ZZZ_D |
| 16233 | 129U, // SMULLB_ZZZ_H |
| 16234 | 10304U, // SMULLB_ZZZ_S |
| 16235 | 6053954U, // SMULLT_ZZZI_D |
| 16236 | 6039616U, // SMULLT_ZZZI_S |
| 16237 | 24642U, // SMULLT_ZZZ_D |
| 16238 | 129U, // SMULLT_ZZZ_H |
| 16239 | 10304U, // SMULLT_ZZZ_S |
| 16240 | 16448U, // SMULLv16i8_v8i16 |
| 16241 | 6045760U, // SMULLv2i32_indexed |
| 16242 | 16448U, // SMULLv2i32_v2i64 |
| 16243 | 6045760U, // SMULLv4i16_indexed |
| 16244 | 16448U, // SMULLv4i16_v4i32 |
| 16245 | 6045760U, // SMULLv4i32_indexed |
| 16246 | 16448U, // SMULLv4i32_v2i64 |
| 16247 | 6045760U, // SMULLv8i16_indexed |
| 16248 | 16448U, // SMULLv8i16_v4i32 |
| 16249 | 16448U, // SMULLv8i8_v8i16 |
| 16250 | 155713U, // SPLICE_ZPZZ_B |
| 16251 | 157761U, // SPLICE_ZPZZ_D |
| 16252 | 273U, // SPLICE_ZPZZ_H |
| 16253 | 159809U, // SPLICE_ZPZZ_S |
| 16254 | 33837121U, // SPLICE_ZPZ_B |
| 16255 | 67383361U, // SPLICE_ZPZ_D |
| 16256 | 101472369U, // SPLICE_ZPZ_H |
| 16257 | 134504513U, // SPLICE_ZPZ_S |
| 16258 | 16U, // SQABS_ZPmZ_B |
| 16259 | 32U, // SQABS_ZPmZ_D |
| 16260 | 0U, // SQABS_ZPmZ_H |
| 16261 | 48U, // SQABS_ZPmZ_S |
| 16262 | 0U, // SQABSv16i8 |
| 16263 | 0U, // SQABSv1i16 |
| 16264 | 0U, // SQABSv1i32 |
| 16265 | 0U, // SQABSv1i64 |
| 16266 | 0U, // SQABSv1i8 |
| 16267 | 0U, // SQABSv2i32 |
| 16268 | 0U, // SQABSv2i64 |
| 16269 | 0U, // SQABSv4i16 |
| 16270 | 0U, // SQABSv4i32 |
| 16271 | 0U, // SQABSv8i16 |
| 16272 | 0U, // SQABSv8i8 |
| 16273 | 32834U, // SQADD_ZI_B |
| 16274 | 34881U, // SQADD_ZI_D |
| 16275 | 193U, // SQADD_ZI_H |
| 16276 | 36930U, // SQADD_ZI_S |
| 16277 | 33837153U, // SQADD_ZPmZ_B |
| 16278 | 67383393U, // SQADD_ZPmZ_D |
| 16279 | 101472369U, // SQADD_ZPmZ_H |
| 16280 | 134504545U, // SQADD_ZPmZ_S |
| 16281 | 20546U, // SQADD_ZZZ_B |
| 16282 | 12353U, // SQADD_ZZZ_D |
| 16283 | 113U, // SQADD_ZZZ_H |
| 16284 | 24642U, // SQADD_ZZZ_S |
| 16285 | 16448U, // SQADDv16i8 |
| 16286 | 6208U, // SQADDv1i16 |
| 16287 | 6208U, // SQADDv1i32 |
| 16288 | 6208U, // SQADDv1i64 |
| 16289 | 6208U, // SQADDv1i8 |
| 16290 | 16448U, // SQADDv2i32 |
| 16291 | 16448U, // SQADDv2i64 |
| 16292 | 16448U, // SQADDv4i16 |
| 16293 | 16448U, // SQADDv4i32 |
| 16294 | 16448U, // SQADDv8i16 |
| 16295 | 16448U, // SQADDv8i8 |
| 16296 | 268718146U, // SQCADD_ZZI_B |
| 16297 | 268709953U, // SQCADD_ZZI_D |
| 16298 | 3954801U, // SQCADD_ZZI_H |
| 16299 | 268722242U, // SQCADD_ZZI_S |
| 16300 | 0U, // SQCVTN_Z2Z_StoH |
| 16301 | 0U, // SQCVTN_Z4Z_DtoH |
| 16302 | 5U, // SQCVTN_Z4Z_StoB |
| 16303 | 0U, // SQCVTUN_Z2Z_StoH |
| 16304 | 0U, // SQCVTUN_Z4Z_DtoH |
| 16305 | 5U, // SQCVTUN_Z4Z_StoB |
| 16306 | 0U, // SQCVTU_Z2Z_StoH |
| 16307 | 0U, // SQCVTU_Z4Z_DtoH |
| 16308 | 5U, // SQCVTU_Z4Z_StoB |
| 16309 | 0U, // SQCVT_Z2Z_StoH |
| 16310 | 0U, // SQCVT_Z4Z_DtoH |
| 16311 | 5U, // SQCVT_Z4Z_StoB |
| 16312 | 4U, // SQDECB_XPiI |
| 16313 | 9U, // SQDECB_XPiWdI |
| 16314 | 4U, // SQDECD_XPiI |
| 16315 | 9U, // SQDECD_XPiWdI |
| 16316 | 4U, // SQDECD_ZPiI |
| 16317 | 4U, // SQDECH_XPiI |
| 16318 | 9U, // SQDECH_XPiWdI |
| 16319 | 0U, // SQDECH_ZPiI |
| 16320 | 161858U, // SQDECP_XPWd_B |
| 16321 | 161857U, // SQDECP_XPWd_D |
| 16322 | 161856U, // SQDECP_XPWd_H |
| 16323 | 161858U, // SQDECP_XPWd_S |
| 16324 | 2U, // SQDECP_XP_B |
| 16325 | 1U, // SQDECP_XP_D |
| 16326 | 0U, // SQDECP_XP_H |
| 16327 | 2U, // SQDECP_XP_S |
| 16328 | 0U, // SQDECP_ZP_D |
| 16329 | 0U, // SQDECP_ZP_H |
| 16330 | 0U, // SQDECP_ZP_S |
| 16331 | 4U, // SQDECW_XPiI |
| 16332 | 9U, // SQDECW_XPiWdI |
| 16333 | 4U, // SQDECW_ZPiI |
| 16334 | 4160U, // SQDMLALBT_ZZZ_D |
| 16335 | 17U, // SQDMLALBT_ZZZ_H |
| 16336 | 14401U, // SQDMLALBT_ZZZ_S |
| 16337 | 103551040U, // SQDMLALB_ZZZI_D |
| 16338 | 103561281U, // SQDMLALB_ZZZI_S |
| 16339 | 4160U, // SQDMLALB_ZZZ_D |
| 16340 | 17U, // SQDMLALB_ZZZ_H |
| 16341 | 14401U, // SQDMLALB_ZZZ_S |
| 16342 | 103551040U, // SQDMLALT_ZZZI_D |
| 16343 | 103561281U, // SQDMLALT_ZZZI_S |
| 16344 | 4160U, // SQDMLALT_ZZZ_D |
| 16345 | 17U, // SQDMLALT_ZZZ_H |
| 16346 | 14401U, // SQDMLALT_ZZZ_S |
| 16347 | 81986U, // SQDMLALi16 |
| 16348 | 81986U, // SQDMLALi32 |
| 16349 | 103565378U, // SQDMLALv1i32_indexed |
| 16350 | 103565378U, // SQDMLALv1i64_indexed |
| 16351 | 103565377U, // SQDMLALv2i32_indexed |
| 16352 | 18497U, // SQDMLALv2i32_v2i64 |
| 16353 | 103565377U, // SQDMLALv4i16_indexed |
| 16354 | 18497U, // SQDMLALv4i16_v4i32 |
| 16355 | 103565377U, // SQDMLALv4i32_indexed |
| 16356 | 18497U, // SQDMLALv4i32_v2i64 |
| 16357 | 103565377U, // SQDMLALv8i16_indexed |
| 16358 | 18497U, // SQDMLALv8i16_v4i32 |
| 16359 | 4160U, // SQDMLSLBT_ZZZ_D |
| 16360 | 17U, // SQDMLSLBT_ZZZ_H |
| 16361 | 14401U, // SQDMLSLBT_ZZZ_S |
| 16362 | 103551040U, // SQDMLSLB_ZZZI_D |
| 16363 | 103561281U, // SQDMLSLB_ZZZI_S |
| 16364 | 4160U, // SQDMLSLB_ZZZ_D |
| 16365 | 17U, // SQDMLSLB_ZZZ_H |
| 16366 | 14401U, // SQDMLSLB_ZZZ_S |
| 16367 | 103551040U, // SQDMLSLT_ZZZI_D |
| 16368 | 103561281U, // SQDMLSLT_ZZZI_S |
| 16369 | 4160U, // SQDMLSLT_ZZZ_D |
| 16370 | 17U, // SQDMLSLT_ZZZ_H |
| 16371 | 14401U, // SQDMLSLT_ZZZ_S |
| 16372 | 81986U, // SQDMLSLi16 |
| 16373 | 81986U, // SQDMLSLi32 |
| 16374 | 103565378U, // SQDMLSLv1i32_indexed |
| 16375 | 103565378U, // SQDMLSLv1i64_indexed |
| 16376 | 103565377U, // SQDMLSLv2i32_indexed |
| 16377 | 18497U, // SQDMLSLv2i32_v2i64 |
| 16378 | 103565377U, // SQDMLSLv4i16_indexed |
| 16379 | 18497U, // SQDMLSLv4i16_v4i32 |
| 16380 | 103565377U, // SQDMLSLv4i32_indexed |
| 16381 | 18497U, // SQDMLSLv4i32_v2i64 |
| 16382 | 103565377U, // SQDMLSLv8i16_indexed |
| 16383 | 18497U, // SQDMLSLv8i16_v4i32 |
| 16384 | 1457U, // SQDMULH_VG2_2Z2Z_B |
| 16385 | 513U, // SQDMULH_VG2_2Z2Z_D |
| 16386 | 273U, // SQDMULH_VG2_2Z2Z_H |
| 16387 | 529U, // SQDMULH_VG2_2Z2Z_S |
| 16388 | 129U, // SQDMULH_VG2_2ZZ_B |
| 16389 | 145U, // SQDMULH_VG2_2ZZ_D |
| 16390 | 113U, // SQDMULH_VG2_2ZZ_H |
| 16391 | 81U, // SQDMULH_VG2_2ZZ_S |
| 16392 | 1457U, // SQDMULH_VG4_4Z4Z_B |
| 16393 | 513U, // SQDMULH_VG4_4Z4Z_D |
| 16394 | 273U, // SQDMULH_VG4_4Z4Z_H |
| 16395 | 529U, // SQDMULH_VG4_4Z4Z_S |
| 16396 | 129U, // SQDMULH_VG4_4ZZ_B |
| 16397 | 145U, // SQDMULH_VG4_4ZZ_D |
| 16398 | 113U, // SQDMULH_VG4_4ZZ_H |
| 16399 | 81U, // SQDMULH_VG4_4ZZ_S |
| 16400 | 6041665U, // SQDMULH_ZZZI_D |
| 16401 | 79985U, // SQDMULH_ZZZI_H |
| 16402 | 6053954U, // SQDMULH_ZZZI_S |
| 16403 | 20546U, // SQDMULH_ZZZ_B |
| 16404 | 12353U, // SQDMULH_ZZZ_D |
| 16405 | 113U, // SQDMULH_ZZZ_H |
| 16406 | 24642U, // SQDMULH_ZZZ_S |
| 16407 | 6208U, // SQDMULHv1i16 |
| 16408 | 6045760U, // SQDMULHv1i16_indexed |
| 16409 | 6208U, // SQDMULHv1i32 |
| 16410 | 6045760U, // SQDMULHv1i32_indexed |
| 16411 | 16448U, // SQDMULHv2i32 |
| 16412 | 6045760U, // SQDMULHv2i32_indexed |
| 16413 | 16448U, // SQDMULHv4i16 |
| 16414 | 6045760U, // SQDMULHv4i16_indexed |
| 16415 | 16448U, // SQDMULHv4i32 |
| 16416 | 6045760U, // SQDMULHv4i32_indexed |
| 16417 | 16448U, // SQDMULHv8i16 |
| 16418 | 6045760U, // SQDMULHv8i16_indexed |
| 16419 | 6053954U, // SQDMULLB_ZZZI_D |
| 16420 | 6039616U, // SQDMULLB_ZZZI_S |
| 16421 | 24642U, // SQDMULLB_ZZZ_D |
| 16422 | 129U, // SQDMULLB_ZZZ_H |
| 16423 | 10304U, // SQDMULLB_ZZZ_S |
| 16424 | 6053954U, // SQDMULLT_ZZZI_D |
| 16425 | 6039616U, // SQDMULLT_ZZZI_S |
| 16426 | 24642U, // SQDMULLT_ZZZ_D |
| 16427 | 129U, // SQDMULLT_ZZZ_H |
| 16428 | 10304U, // SQDMULLT_ZZZ_S |
| 16429 | 6208U, // SQDMULLi16 |
| 16430 | 6208U, // SQDMULLi32 |
| 16431 | 6045760U, // SQDMULLv1i32_indexed |
| 16432 | 6045760U, // SQDMULLv1i64_indexed |
| 16433 | 6045760U, // SQDMULLv2i32_indexed |
| 16434 | 16448U, // SQDMULLv2i32_v2i64 |
| 16435 | 6045760U, // SQDMULLv4i16_indexed |
| 16436 | 16448U, // SQDMULLv4i16_v4i32 |
| 16437 | 6045760U, // SQDMULLv4i32_indexed |
| 16438 | 16448U, // SQDMULLv4i32_v2i64 |
| 16439 | 6045760U, // SQDMULLv8i16_indexed |
| 16440 | 16448U, // SQDMULLv8i16_v4i32 |
| 16441 | 4U, // SQINCB_XPiI |
| 16442 | 9U, // SQINCB_XPiWdI |
| 16443 | 4U, // SQINCD_XPiI |
| 16444 | 9U, // SQINCD_XPiWdI |
| 16445 | 4U, // SQINCD_ZPiI |
| 16446 | 4U, // SQINCH_XPiI |
| 16447 | 9U, // SQINCH_XPiWdI |
| 16448 | 0U, // SQINCH_ZPiI |
| 16449 | 161858U, // SQINCP_XPWd_B |
| 16450 | 161857U, // SQINCP_XPWd_D |
| 16451 | 161856U, // SQINCP_XPWd_H |
| 16452 | 161858U, // SQINCP_XPWd_S |
| 16453 | 2U, // SQINCP_XP_B |
| 16454 | 1U, // SQINCP_XP_D |
| 16455 | 0U, // SQINCP_XP_H |
| 16456 | 2U, // SQINCP_XP_S |
| 16457 | 0U, // SQINCP_ZP_D |
| 16458 | 0U, // SQINCP_ZP_H |
| 16459 | 0U, // SQINCP_ZP_S |
| 16460 | 4U, // SQINCW_XPiI |
| 16461 | 9U, // SQINCW_XPiWdI |
| 16462 | 4U, // SQINCW_ZPiI |
| 16463 | 16U, // SQNEG_ZPmZ_B |
| 16464 | 32U, // SQNEG_ZPmZ_D |
| 16465 | 0U, // SQNEG_ZPmZ_H |
| 16466 | 48U, // SQNEG_ZPmZ_S |
| 16467 | 0U, // SQNEGv16i8 |
| 16468 | 0U, // SQNEGv1i16 |
| 16469 | 0U, // SQNEGv1i32 |
| 16470 | 0U, // SQNEGv1i64 |
| 16471 | 0U, // SQNEGv1i8 |
| 16472 | 0U, // SQNEGv2i32 |
| 16473 | 0U, // SQNEGv2i64 |
| 16474 | 0U, // SQNEGv4i16 |
| 16475 | 0U, // SQNEGv4i32 |
| 16476 | 0U, // SQNEGv8i16 |
| 16477 | 0U, // SQNEGv8i8 |
| 16478 | 369438977U, // SQRDCMLAH_ZZZI_H |
| 16479 | 338432064U, // SQRDCMLAH_ZZZI_S |
| 16480 | 4478995U, // SQRDCMLAH_ZZZ_B |
| 16481 | 402917440U, // SQRDCMLAH_ZZZ_D |
| 16482 | 4479233U, // SQRDCMLAH_ZZZ_H |
| 16483 | 402919488U, // SQRDCMLAH_ZZZ_S |
| 16484 | 103548992U, // SQRDMLAH_ZZZI_D |
| 16485 | 78081U, // SQRDMLAH_ZZZI_H |
| 16486 | 103551040U, // SQRDMLAH_ZZZI_S |
| 16487 | 19U, // SQRDMLAH_ZZZ_B |
| 16488 | 2112U, // SQRDMLAH_ZZZ_D |
| 16489 | 257U, // SQRDMLAH_ZZZ_H |
| 16490 | 4160U, // SQRDMLAH_ZZZ_S |
| 16491 | 81986U, // SQRDMLAHv1i16 |
| 16492 | 103565378U, // SQRDMLAHv1i16_indexed |
| 16493 | 81986U, // SQRDMLAHv1i32 |
| 16494 | 103565378U, // SQRDMLAHv1i32_indexed |
| 16495 | 18497U, // SQRDMLAHv2i32 |
| 16496 | 103565377U, // SQRDMLAHv2i32_indexed |
| 16497 | 18497U, // SQRDMLAHv4i16 |
| 16498 | 103565377U, // SQRDMLAHv4i16_indexed |
| 16499 | 18497U, // SQRDMLAHv4i32 |
| 16500 | 103565377U, // SQRDMLAHv4i32_indexed |
| 16501 | 18497U, // SQRDMLAHv8i16 |
| 16502 | 103565377U, // SQRDMLAHv8i16_indexed |
| 16503 | 103548992U, // SQRDMLSH_ZZZI_D |
| 16504 | 78081U, // SQRDMLSH_ZZZI_H |
| 16505 | 103551040U, // SQRDMLSH_ZZZI_S |
| 16506 | 19U, // SQRDMLSH_ZZZ_B |
| 16507 | 2112U, // SQRDMLSH_ZZZ_D |
| 16508 | 257U, // SQRDMLSH_ZZZ_H |
| 16509 | 4160U, // SQRDMLSH_ZZZ_S |
| 16510 | 81986U, // SQRDMLSHv1i16 |
| 16511 | 103565378U, // SQRDMLSHv1i16_indexed |
| 16512 | 81986U, // SQRDMLSHv1i32 |
| 16513 | 103565378U, // SQRDMLSHv1i32_indexed |
| 16514 | 18497U, // SQRDMLSHv2i32 |
| 16515 | 103565377U, // SQRDMLSHv2i32_indexed |
| 16516 | 18497U, // SQRDMLSHv4i16 |
| 16517 | 103565377U, // SQRDMLSHv4i16_indexed |
| 16518 | 18497U, // SQRDMLSHv4i32 |
| 16519 | 103565377U, // SQRDMLSHv4i32_indexed |
| 16520 | 18497U, // SQRDMLSHv8i16 |
| 16521 | 103565377U, // SQRDMLSHv8i16_indexed |
| 16522 | 6041665U, // SQRDMULH_ZZZI_D |
| 16523 | 79985U, // SQRDMULH_ZZZI_H |
| 16524 | 6053954U, // SQRDMULH_ZZZI_S |
| 16525 | 20546U, // SQRDMULH_ZZZ_B |
| 16526 | 12353U, // SQRDMULH_ZZZ_D |
| 16527 | 113U, // SQRDMULH_ZZZ_H |
| 16528 | 24642U, // SQRDMULH_ZZZ_S |
| 16529 | 6208U, // SQRDMULHv1i16 |
| 16530 | 6045760U, // SQRDMULHv1i16_indexed |
| 16531 | 6208U, // SQRDMULHv1i32 |
| 16532 | 6045760U, // SQRDMULHv1i32_indexed |
| 16533 | 16448U, // SQRDMULHv2i32 |
| 16534 | 6045760U, // SQRDMULHv2i32_indexed |
| 16535 | 16448U, // SQRDMULHv4i16 |
| 16536 | 6045760U, // SQRDMULHv4i16_indexed |
| 16537 | 16448U, // SQRDMULHv4i32 |
| 16538 | 6045760U, // SQRDMULHv4i32_indexed |
| 16539 | 16448U, // SQRDMULHv8i16 |
| 16540 | 6045760U, // SQRDMULHv8i16_indexed |
| 16541 | 33837153U, // SQRSHLR_ZPmZ_B |
| 16542 | 67383393U, // SQRSHLR_ZPmZ_D |
| 16543 | 101472369U, // SQRSHLR_ZPmZ_H |
| 16544 | 134504545U, // SQRSHLR_ZPmZ_S |
| 16545 | 33837153U, // SQRSHL_ZPmZ_B |
| 16546 | 67383393U, // SQRSHL_ZPmZ_D |
| 16547 | 101472369U, // SQRSHL_ZPmZ_H |
| 16548 | 134504545U, // SQRSHL_ZPmZ_S |
| 16549 | 16448U, // SQRSHLv16i8 |
| 16550 | 6208U, // SQRSHLv1i16 |
| 16551 | 6208U, // SQRSHLv1i32 |
| 16552 | 6208U, // SQRSHLv1i64 |
| 16553 | 6208U, // SQRSHLv1i8 |
| 16554 | 16448U, // SQRSHLv2i32 |
| 16555 | 16448U, // SQRSHLv2i64 |
| 16556 | 16448U, // SQRSHLv4i16 |
| 16557 | 16448U, // SQRSHLv4i32 |
| 16558 | 16448U, // SQRSHLv8i16 |
| 16559 | 16448U, // SQRSHLv8i8 |
| 16560 | 6208U, // SQRSHRNB_ZZI_B |
| 16561 | 225U, // SQRSHRNB_ZZI_H |
| 16562 | 6209U, // SQRSHRNB_ZZI_S |
| 16563 | 81985U, // SQRSHRNT_ZZI_B |
| 16564 | 417U, // SQRSHRNT_ZZI_H |
| 16565 | 81984U, // SQRSHRNT_ZZI_S |
| 16566 | 6213U, // SQRSHRN_VG4_Z4ZI_B |
| 16567 | 225U, // SQRSHRN_VG4_Z4ZI_H |
| 16568 | 225U, // SQRSHRN_Z2ZI_StoH |
| 16569 | 6208U, // SQRSHRNb |
| 16570 | 6208U, // SQRSHRNh |
| 16571 | 6208U, // SQRSHRNs |
| 16572 | 81985U, // SQRSHRNv16i8_shift |
| 16573 | 6208U, // SQRSHRNv2i32_shift |
| 16574 | 6208U, // SQRSHRNv4i16_shift |
| 16575 | 81985U, // SQRSHRNv4i32_shift |
| 16576 | 81985U, // SQRSHRNv8i16_shift |
| 16577 | 6208U, // SQRSHRNv8i8_shift |
| 16578 | 6208U, // SQRSHRUNB_ZZI_B |
| 16579 | 225U, // SQRSHRUNB_ZZI_H |
| 16580 | 6209U, // SQRSHRUNB_ZZI_S |
| 16581 | 81985U, // SQRSHRUNT_ZZI_B |
| 16582 | 417U, // SQRSHRUNT_ZZI_H |
| 16583 | 81984U, // SQRSHRUNT_ZZI_S |
| 16584 | 6213U, // SQRSHRUN_VG4_Z4ZI_B |
| 16585 | 225U, // SQRSHRUN_VG4_Z4ZI_H |
| 16586 | 225U, // SQRSHRUN_Z2ZI_StoH |
| 16587 | 6208U, // SQRSHRUNb |
| 16588 | 6208U, // SQRSHRUNh |
| 16589 | 6208U, // SQRSHRUNs |
| 16590 | 81985U, // SQRSHRUNv16i8_shift |
| 16591 | 6208U, // SQRSHRUNv2i32_shift |
| 16592 | 6208U, // SQRSHRUNv4i16_shift |
| 16593 | 81985U, // SQRSHRUNv4i32_shift |
| 16594 | 81985U, // SQRSHRUNv8i16_shift |
| 16595 | 6208U, // SQRSHRUNv8i8_shift |
| 16596 | 225U, // SQRSHRU_VG2_Z2ZI_H |
| 16597 | 6213U, // SQRSHRU_VG4_Z4ZI_B |
| 16598 | 225U, // SQRSHRU_VG4_Z4ZI_H |
| 16599 | 225U, // SQRSHR_VG2_Z2ZI_H |
| 16600 | 6213U, // SQRSHR_VG4_Z4ZI_B |
| 16601 | 225U, // SQRSHR_VG4_Z4ZI_H |
| 16602 | 33837153U, // SQSHLR_ZPmZ_B |
| 16603 | 67383393U, // SQSHLR_ZPmZ_D |
| 16604 | 101472369U, // SQSHLR_ZPmZ_H |
| 16605 | 134504545U, // SQSHLR_ZPmZ_S |
| 16606 | 282721U, // SQSHLU_ZPmI_B |
| 16607 | 274529U, // SQSHLU_ZPmI_D |
| 16608 | 103045233U, // SQSHLU_ZPmI_H |
| 16609 | 286817U, // SQSHLU_ZPmI_S |
| 16610 | 6208U, // SQSHLUb |
| 16611 | 6208U, // SQSHLUd |
| 16612 | 6208U, // SQSHLUh |
| 16613 | 6208U, // SQSHLUs |
| 16614 | 6208U, // SQSHLUv16i8_shift |
| 16615 | 6208U, // SQSHLUv2i32_shift |
| 16616 | 6208U, // SQSHLUv2i64_shift |
| 16617 | 6208U, // SQSHLUv4i16_shift |
| 16618 | 6208U, // SQSHLUv4i32_shift |
| 16619 | 6208U, // SQSHLUv8i16_shift |
| 16620 | 6208U, // SQSHLUv8i8_shift |
| 16621 | 282721U, // SQSHL_ZPmI_B |
| 16622 | 274529U, // SQSHL_ZPmI_D |
| 16623 | 103045233U, // SQSHL_ZPmI_H |
| 16624 | 286817U, // SQSHL_ZPmI_S |
| 16625 | 33837153U, // SQSHL_ZPmZ_B |
| 16626 | 67383393U, // SQSHL_ZPmZ_D |
| 16627 | 101472369U, // SQSHL_ZPmZ_H |
| 16628 | 134504545U, // SQSHL_ZPmZ_S |
| 16629 | 6208U, // SQSHLb |
| 16630 | 6208U, // SQSHLd |
| 16631 | 6208U, // SQSHLh |
| 16632 | 6208U, // SQSHLs |
| 16633 | 16448U, // SQSHLv16i8 |
| 16634 | 6208U, // SQSHLv16i8_shift |
| 16635 | 6208U, // SQSHLv1i16 |
| 16636 | 6208U, // SQSHLv1i32 |
| 16637 | 6208U, // SQSHLv1i64 |
| 16638 | 6208U, // SQSHLv1i8 |
| 16639 | 16448U, // SQSHLv2i32 |
| 16640 | 6208U, // SQSHLv2i32_shift |
| 16641 | 16448U, // SQSHLv2i64 |
| 16642 | 6208U, // SQSHLv2i64_shift |
| 16643 | 16448U, // SQSHLv4i16 |
| 16644 | 6208U, // SQSHLv4i16_shift |
| 16645 | 16448U, // SQSHLv4i32 |
| 16646 | 6208U, // SQSHLv4i32_shift |
| 16647 | 16448U, // SQSHLv8i16 |
| 16648 | 6208U, // SQSHLv8i16_shift |
| 16649 | 16448U, // SQSHLv8i8 |
| 16650 | 6208U, // SQSHLv8i8_shift |
| 16651 | 6208U, // SQSHRNB_ZZI_B |
| 16652 | 225U, // SQSHRNB_ZZI_H |
| 16653 | 6209U, // SQSHRNB_ZZI_S |
| 16654 | 81985U, // SQSHRNT_ZZI_B |
| 16655 | 417U, // SQSHRNT_ZZI_H |
| 16656 | 81984U, // SQSHRNT_ZZI_S |
| 16657 | 6208U, // SQSHRNb |
| 16658 | 6208U, // SQSHRNh |
| 16659 | 6208U, // SQSHRNs |
| 16660 | 81985U, // SQSHRNv16i8_shift |
| 16661 | 6208U, // SQSHRNv2i32_shift |
| 16662 | 6208U, // SQSHRNv4i16_shift |
| 16663 | 81985U, // SQSHRNv4i32_shift |
| 16664 | 81985U, // SQSHRNv8i16_shift |
| 16665 | 6208U, // SQSHRNv8i8_shift |
| 16666 | 6208U, // SQSHRUNB_ZZI_B |
| 16667 | 225U, // SQSHRUNB_ZZI_H |
| 16668 | 6209U, // SQSHRUNB_ZZI_S |
| 16669 | 81985U, // SQSHRUNT_ZZI_B |
| 16670 | 417U, // SQSHRUNT_ZZI_H |
| 16671 | 81984U, // SQSHRUNT_ZZI_S |
| 16672 | 6208U, // SQSHRUNb |
| 16673 | 6208U, // SQSHRUNh |
| 16674 | 6208U, // SQSHRUNs |
| 16675 | 81985U, // SQSHRUNv16i8_shift |
| 16676 | 6208U, // SQSHRUNv2i32_shift |
| 16677 | 6208U, // SQSHRUNv4i16_shift |
| 16678 | 81985U, // SQSHRUNv4i32_shift |
| 16679 | 81985U, // SQSHRUNv8i16_shift |
| 16680 | 6208U, // SQSHRUNv8i8_shift |
| 16681 | 33837153U, // SQSUBR_ZPmZ_B |
| 16682 | 67383393U, // SQSUBR_ZPmZ_D |
| 16683 | 101472369U, // SQSUBR_ZPmZ_H |
| 16684 | 134504545U, // SQSUBR_ZPmZ_S |
| 16685 | 32834U, // SQSUB_ZI_B |
| 16686 | 34881U, // SQSUB_ZI_D |
| 16687 | 193U, // SQSUB_ZI_H |
| 16688 | 36930U, // SQSUB_ZI_S |
| 16689 | 33837153U, // SQSUB_ZPmZ_B |
| 16690 | 67383393U, // SQSUB_ZPmZ_D |
| 16691 | 101472369U, // SQSUB_ZPmZ_H |
| 16692 | 134504545U, // SQSUB_ZPmZ_S |
| 16693 | 20546U, // SQSUB_ZZZ_B |
| 16694 | 12353U, // SQSUB_ZZZ_D |
| 16695 | 113U, // SQSUB_ZZZ_H |
| 16696 | 24642U, // SQSUB_ZZZ_S |
| 16697 | 16448U, // SQSUBv16i8 |
| 16698 | 6208U, // SQSUBv1i16 |
| 16699 | 6208U, // SQSUBv1i32 |
| 16700 | 6208U, // SQSUBv1i64 |
| 16701 | 6208U, // SQSUBv1i8 |
| 16702 | 16448U, // SQSUBv2i32 |
| 16703 | 16448U, // SQSUBv2i64 |
| 16704 | 16448U, // SQSUBv4i16 |
| 16705 | 16448U, // SQSUBv4i32 |
| 16706 | 16448U, // SQSUBv8i16 |
| 16707 | 16448U, // SQSUBv8i8 |
| 16708 | 0U, // SQXTNB_ZZ_B |
| 16709 | 0U, // SQXTNB_ZZ_H |
| 16710 | 1U, // SQXTNB_ZZ_S |
| 16711 | 1U, // SQXTNT_ZZ_B |
| 16712 | 0U, // SQXTNT_ZZ_H |
| 16713 | 0U, // SQXTNT_ZZ_S |
| 16714 | 1U, // SQXTNv16i8 |
| 16715 | 0U, // SQXTNv1i16 |
| 16716 | 0U, // SQXTNv1i32 |
| 16717 | 0U, // SQXTNv1i8 |
| 16718 | 0U, // SQXTNv2i32 |
| 16719 | 0U, // SQXTNv4i16 |
| 16720 | 1U, // SQXTNv4i32 |
| 16721 | 1U, // SQXTNv8i16 |
| 16722 | 0U, // SQXTNv8i8 |
| 16723 | 0U, // SQXTUNB_ZZ_B |
| 16724 | 0U, // SQXTUNB_ZZ_H |
| 16725 | 1U, // SQXTUNB_ZZ_S |
| 16726 | 1U, // SQXTUNT_ZZ_B |
| 16727 | 0U, // SQXTUNT_ZZ_H |
| 16728 | 0U, // SQXTUNT_ZZ_S |
| 16729 | 1U, // SQXTUNv16i8 |
| 16730 | 0U, // SQXTUNv1i16 |
| 16731 | 0U, // SQXTUNv1i32 |
| 16732 | 0U, // SQXTUNv1i8 |
| 16733 | 0U, // SQXTUNv2i32 |
| 16734 | 0U, // SQXTUNv4i16 |
| 16735 | 1U, // SQXTUNv4i32 |
| 16736 | 1U, // SQXTUNv8i16 |
| 16737 | 0U, // SQXTUNv8i8 |
| 16738 | 33837153U, // SRHADD_ZPmZ_B |
| 16739 | 67383393U, // SRHADD_ZPmZ_D |
| 16740 | 101472369U, // SRHADD_ZPmZ_H |
| 16741 | 134504545U, // SRHADD_ZPmZ_S |
| 16742 | 16448U, // SRHADDv16i8 |
| 16743 | 16448U, // SRHADDv2i32 |
| 16744 | 16448U, // SRHADDv4i16 |
| 16745 | 16448U, // SRHADDv4i32 |
| 16746 | 16448U, // SRHADDv8i16 |
| 16747 | 16448U, // SRHADDv8i8 |
| 16748 | 419U, // SRI_ZZI_B |
| 16749 | 81984U, // SRI_ZZI_D |
| 16750 | 417U, // SRI_ZZI_H |
| 16751 | 81984U, // SRI_ZZI_S |
| 16752 | 81986U, // SRId |
| 16753 | 81985U, // SRIv16i8_shift |
| 16754 | 81985U, // SRIv2i32_shift |
| 16755 | 81985U, // SRIv2i64_shift |
| 16756 | 81985U, // SRIv4i16_shift |
| 16757 | 81985U, // SRIv4i32_shift |
| 16758 | 81985U, // SRIv8i16_shift |
| 16759 | 81985U, // SRIv8i8_shift |
| 16760 | 33837153U, // SRSHLR_ZPmZ_B |
| 16761 | 67383393U, // SRSHLR_ZPmZ_D |
| 16762 | 101472369U, // SRSHLR_ZPmZ_H |
| 16763 | 134504545U, // SRSHLR_ZPmZ_S |
| 16764 | 1457U, // SRSHL_VG2_2Z2Z_B |
| 16765 | 513U, // SRSHL_VG2_2Z2Z_D |
| 16766 | 273U, // SRSHL_VG2_2Z2Z_H |
| 16767 | 529U, // SRSHL_VG2_2Z2Z_S |
| 16768 | 129U, // SRSHL_VG2_2ZZ_B |
| 16769 | 145U, // SRSHL_VG2_2ZZ_D |
| 16770 | 113U, // SRSHL_VG2_2ZZ_H |
| 16771 | 81U, // SRSHL_VG2_2ZZ_S |
| 16772 | 1457U, // SRSHL_VG4_4Z4Z_B |
| 16773 | 513U, // SRSHL_VG4_4Z4Z_D |
| 16774 | 273U, // SRSHL_VG4_4Z4Z_H |
| 16775 | 529U, // SRSHL_VG4_4Z4Z_S |
| 16776 | 129U, // SRSHL_VG4_4ZZ_B |
| 16777 | 145U, // SRSHL_VG4_4ZZ_D |
| 16778 | 113U, // SRSHL_VG4_4ZZ_H |
| 16779 | 81U, // SRSHL_VG4_4ZZ_S |
| 16780 | 33837153U, // SRSHL_ZPmZ_B |
| 16781 | 67383393U, // SRSHL_ZPmZ_D |
| 16782 | 101472369U, // SRSHL_ZPmZ_H |
| 16783 | 134504545U, // SRSHL_ZPmZ_S |
| 16784 | 16448U, // SRSHLv16i8 |
| 16785 | 6208U, // SRSHLv1i64 |
| 16786 | 16448U, // SRSHLv2i32 |
| 16787 | 16448U, // SRSHLv2i64 |
| 16788 | 16448U, // SRSHLv4i16 |
| 16789 | 16448U, // SRSHLv4i32 |
| 16790 | 16448U, // SRSHLv8i16 |
| 16791 | 16448U, // SRSHLv8i8 |
| 16792 | 282721U, // SRSHR_ZPmI_B |
| 16793 | 274529U, // SRSHR_ZPmI_D |
| 16794 | 103045233U, // SRSHR_ZPmI_H |
| 16795 | 286817U, // SRSHR_ZPmI_S |
| 16796 | 6208U, // SRSHRd |
| 16797 | 6208U, // SRSHRv16i8_shift |
| 16798 | 6208U, // SRSHRv2i32_shift |
| 16799 | 6208U, // SRSHRv2i64_shift |
| 16800 | 6208U, // SRSHRv4i16_shift |
| 16801 | 6208U, // SRSHRv4i32_shift |
| 16802 | 6208U, // SRSHRv8i16_shift |
| 16803 | 6208U, // SRSHRv8i8_shift |
| 16804 | 419U, // SRSRA_ZZI_B |
| 16805 | 81984U, // SRSRA_ZZI_D |
| 16806 | 417U, // SRSRA_ZZI_H |
| 16807 | 81984U, // SRSRA_ZZI_S |
| 16808 | 81986U, // SRSRAd |
| 16809 | 81985U, // SRSRAv16i8_shift |
| 16810 | 81985U, // SRSRAv2i32_shift |
| 16811 | 81985U, // SRSRAv2i64_shift |
| 16812 | 81985U, // SRSRAv4i16_shift |
| 16813 | 81985U, // SRSRAv4i32_shift |
| 16814 | 81985U, // SRSRAv8i16_shift |
| 16815 | 81985U, // SRSRAv8i8_shift |
| 16816 | 6210U, // SSHLLB_ZZI_D |
| 16817 | 225U, // SSHLLB_ZZI_H |
| 16818 | 6208U, // SSHLLB_ZZI_S |
| 16819 | 6210U, // SSHLLT_ZZI_D |
| 16820 | 225U, // SSHLLT_ZZI_H |
| 16821 | 6208U, // SSHLLT_ZZI_S |
| 16822 | 6208U, // SSHLLv16i8_shift |
| 16823 | 6208U, // SSHLLv2i32_shift |
| 16824 | 6208U, // SSHLLv4i16_shift |
| 16825 | 6208U, // SSHLLv4i32_shift |
| 16826 | 6208U, // SSHLLv8i16_shift |
| 16827 | 6208U, // SSHLLv8i8_shift |
| 16828 | 16448U, // SSHLv16i8 |
| 16829 | 6208U, // SSHLv1i64 |
| 16830 | 16448U, // SSHLv2i32 |
| 16831 | 16448U, // SSHLv2i64 |
| 16832 | 16448U, // SSHLv4i16 |
| 16833 | 16448U, // SSHLv4i32 |
| 16834 | 16448U, // SSHLv8i16 |
| 16835 | 16448U, // SSHLv8i8 |
| 16836 | 6208U, // SSHRd |
| 16837 | 6208U, // SSHRv16i8_shift |
| 16838 | 6208U, // SSHRv2i32_shift |
| 16839 | 6208U, // SSHRv2i64_shift |
| 16840 | 6208U, // SSHRv4i16_shift |
| 16841 | 6208U, // SSHRv4i32_shift |
| 16842 | 6208U, // SSHRv8i16_shift |
| 16843 | 6208U, // SSHRv8i8_shift |
| 16844 | 419U, // SSRA_ZZI_B |
| 16845 | 81984U, // SSRA_ZZI_D |
| 16846 | 417U, // SSRA_ZZI_H |
| 16847 | 81984U, // SSRA_ZZI_S |
| 16848 | 81986U, // SSRAd |
| 16849 | 81985U, // SSRAv16i8_shift |
| 16850 | 81985U, // SSRAv2i32_shift |
| 16851 | 81985U, // SSRAv2i64_shift |
| 16852 | 81985U, // SSRAv4i16_shift |
| 16853 | 81985U, // SSRAv4i32_shift |
| 16854 | 81985U, // SSRAv8i16_shift |
| 16855 | 81985U, // SSRAv8i8_shift |
| 16856 | 6576361U, // SST1B_D |
| 16857 | 673470617U, // SST1B_D_IMM |
| 16858 | 6838505U, // SST1B_D_SXTW |
| 16859 | 7100649U, // SST1B_D_UXTW |
| 16860 | 673470553U, // SST1B_S_IMM |
| 16861 | 7362793U, // SST1B_S_SXTW |
| 16862 | 7624937U, // SST1B_S_UXTW |
| 16863 | 6576361U, // SST1D |
| 16864 | 7887001U, // SST1D_IMM |
| 16865 | 8149225U, // SST1D_SCALED |
| 16866 | 6838505U, // SST1D_SXTW |
| 16867 | 8411369U, // SST1D_SXTW_SCALED |
| 16868 | 7100649U, // SST1D_UXTW |
| 16869 | 8673513U, // SST1D_UXTW_SCALED |
| 16870 | 6576361U, // SST1H_D |
| 16871 | 680024217U, // SST1H_D_IMM |
| 16872 | 9197801U, // SST1H_D_SCALED |
| 16873 | 6838505U, // SST1H_D_SXTW |
| 16874 | 9459945U, // SST1H_D_SXTW_SCALED |
| 16875 | 7100649U, // SST1H_D_UXTW |
| 16876 | 9722089U, // SST1H_D_UXTW_SCALED |
| 16877 | 680024153U, // SST1H_S_IMM |
| 16878 | 7362793U, // SST1H_S_SXTW |
| 16879 | 9984233U, // SST1H_S_SXTW_SCALED |
| 16880 | 7624937U, // SST1H_S_UXTW |
| 16881 | 10246377U, // SST1H_S_UXTW_SCALED |
| 16882 | 673470617U, // SST1Q |
| 16883 | 6576361U, // SST1W_D |
| 16884 | 681597081U, // SST1W_D_IMM |
| 16885 | 10770665U, // SST1W_D_SCALED |
| 16886 | 6838505U, // SST1W_D_SXTW |
| 16887 | 11032809U, // SST1W_D_SXTW_SCALED |
| 16888 | 7100649U, // SST1W_D_UXTW |
| 16889 | 11294953U, // SST1W_D_UXTW_SCALED |
| 16890 | 681597017U, // SST1W_IMM |
| 16891 | 7362793U, // SST1W_SXTW |
| 16892 | 11557097U, // SST1W_SXTW_SCALED |
| 16893 | 7624937U, // SST1W_UXTW |
| 16894 | 11819241U, // SST1W_UXTW_SCALED |
| 16895 | 24642U, // SSUBLBT_ZZZ_D |
| 16896 | 129U, // SSUBLBT_ZZZ_H |
| 16897 | 10304U, // SSUBLBT_ZZZ_S |
| 16898 | 24642U, // SSUBLB_ZZZ_D |
| 16899 | 129U, // SSUBLB_ZZZ_H |
| 16900 | 10304U, // SSUBLB_ZZZ_S |
| 16901 | 24642U, // SSUBLTB_ZZZ_D |
| 16902 | 129U, // SSUBLTB_ZZZ_H |
| 16903 | 10304U, // SSUBLTB_ZZZ_S |
| 16904 | 24642U, // SSUBLT_ZZZ_D |
| 16905 | 129U, // SSUBLT_ZZZ_H |
| 16906 | 10304U, // SSUBLT_ZZZ_S |
| 16907 | 16448U, // SSUBLv16i8_v8i16 |
| 16908 | 16448U, // SSUBLv2i32_v2i64 |
| 16909 | 16448U, // SSUBLv4i16_v4i32 |
| 16910 | 16448U, // SSUBLv4i32_v2i64 |
| 16911 | 16448U, // SSUBLv8i16_v4i32 |
| 16912 | 16448U, // SSUBLv8i8_v8i16 |
| 16913 | 24641U, // SSUBWB_ZZZ_D |
| 16914 | 129U, // SSUBWB_ZZZ_H |
| 16915 | 10306U, // SSUBWB_ZZZ_S |
| 16916 | 24641U, // SSUBWT_ZZZ_D |
| 16917 | 129U, // SSUBWT_ZZZ_H |
| 16918 | 10306U, // SSUBWT_ZZZ_S |
| 16919 | 16448U, // SSUBWv16i8_v8i16 |
| 16920 | 16448U, // SSUBWv2i32_v2i64 |
| 16921 | 16448U, // SSUBWv4i16_v4i32 |
| 16922 | 16448U, // SSUBWv4i32_v2i64 |
| 16923 | 16448U, // SSUBWv8i16_v4i32 |
| 16924 | 16448U, // SSUBWv8i8_v8i16 |
| 16925 | 12081385U, // ST1B |
| 16926 | 12081385U, // ST1B_2Z |
| 16927 | 713578729U, // ST1B_2Z_IMM |
| 16928 | 1275337031U, // ST1B_2Z_STRIDED |
| 16929 | 1308891463U, // ST1B_2Z_STRIDED_IMM |
| 16930 | 12081385U, // ST1B_4Z |
| 16931 | 715151593U, // ST1B_4Z_IMM |
| 16932 | 12081385U, // ST1B_4Z_STRIDED |
| 16933 | 715151593U, // ST1B_4Z_STRIDED_IMM |
| 16934 | 12081385U, // ST1B_D |
| 16935 | 707025129U, // ST1B_D_IMM |
| 16936 | 12081385U, // ST1B_H |
| 16937 | 707025129U, // ST1B_H_IMM |
| 16938 | 707025129U, // ST1B_IMM |
| 16939 | 12081385U, // ST1B_S |
| 16940 | 707025129U, // ST1B_S_IMM |
| 16941 | 12343529U, // ST1D |
| 16942 | 12343529U, // ST1D_2Z |
| 16943 | 713578729U, // ST1D_2Z_IMM |
| 16944 | 12343529U, // ST1D_2Z_STRIDED |
| 16945 | 713578729U, // ST1D_2Z_STRIDED_IMM |
| 16946 | 12343529U, // ST1D_4Z |
| 16947 | 715151593U, // ST1D_4Z_IMM |
| 16948 | 12343529U, // ST1D_4Z_STRIDED |
| 16949 | 715151593U, // ST1D_4Z_STRIDED_IMM |
| 16950 | 707025129U, // ST1D_IMM |
| 16951 | 12343529U, // ST1D_Q |
| 16952 | 707025129U, // ST1D_Q_IMM |
| 16953 | 0U, // ST1Fourv16b |
| 16954 | 0U, // ST1Fourv16b_POST |
| 16955 | 0U, // ST1Fourv1d |
| 16956 | 0U, // ST1Fourv1d_POST |
| 16957 | 0U, // ST1Fourv2d |
| 16958 | 0U, // ST1Fourv2d_POST |
| 16959 | 0U, // ST1Fourv2s |
| 16960 | 0U, // ST1Fourv2s_POST |
| 16961 | 0U, // ST1Fourv4h |
| 16962 | 0U, // ST1Fourv4h_POST |
| 16963 | 0U, // ST1Fourv4s |
| 16964 | 0U, // ST1Fourv4s_POST |
| 16965 | 0U, // ST1Fourv8b |
| 16966 | 0U, // ST1Fourv8b_POST |
| 16967 | 0U, // ST1Fourv8h |
| 16968 | 0U, // ST1Fourv8h_POST |
| 16969 | 12605673U, // ST1H |
| 16970 | 12605673U, // ST1H_2Z |
| 16971 | 713578729U, // ST1H_2Z_IMM |
| 16972 | 1342445895U, // ST1H_2Z_STRIDED |
| 16973 | 1308891463U, // ST1H_2Z_STRIDED_IMM |
| 16974 | 12605673U, // ST1H_4Z |
| 16975 | 715151593U, // ST1H_4Z_IMM |
| 16976 | 12605673U, // ST1H_4Z_STRIDED |
| 16977 | 715151593U, // ST1H_4Z_STRIDED_IMM |
| 16978 | 12605673U, // ST1H_D |
| 16979 | 707025129U, // ST1H_D_IMM |
| 16980 | 707025129U, // ST1H_IMM |
| 16981 | 12605673U, // ST1H_S |
| 16982 | 707025129U, // ST1H_S_IMM |
| 16983 | 0U, // ST1Onev16b |
| 16984 | 0U, // ST1Onev16b_POST |
| 16985 | 0U, // ST1Onev1d |
| 16986 | 0U, // ST1Onev1d_POST |
| 16987 | 0U, // ST1Onev2d |
| 16988 | 0U, // ST1Onev2d_POST |
| 16989 | 0U, // ST1Onev2s |
| 16990 | 0U, // ST1Onev2s_POST |
| 16991 | 0U, // ST1Onev4h |
| 16992 | 0U, // ST1Onev4h_POST |
| 16993 | 0U, // ST1Onev4s |
| 16994 | 0U, // ST1Onev4s_POST |
| 16995 | 0U, // ST1Onev8b |
| 16996 | 0U, // ST1Onev8b_POST |
| 16997 | 0U, // ST1Onev8h |
| 16998 | 0U, // ST1Onev8h_POST |
| 16999 | 0U, // ST1Threev16b |
| 17000 | 0U, // ST1Threev16b_POST |
| 17001 | 0U, // ST1Threev1d |
| 17002 | 0U, // ST1Threev1d_POST |
| 17003 | 0U, // ST1Threev2d |
| 17004 | 0U, // ST1Threev2d_POST |
| 17005 | 0U, // ST1Threev2s |
| 17006 | 0U, // ST1Threev2s_POST |
| 17007 | 0U, // ST1Threev4h |
| 17008 | 0U, // ST1Threev4h_POST |
| 17009 | 0U, // ST1Threev4s |
| 17010 | 0U, // ST1Threev4s_POST |
| 17011 | 0U, // ST1Threev8b |
| 17012 | 0U, // ST1Threev8b_POST |
| 17013 | 0U, // ST1Threev8h |
| 17014 | 0U, // ST1Threev8h_POST |
| 17015 | 0U, // ST1Twov16b |
| 17016 | 0U, // ST1Twov16b_POST |
| 17017 | 0U, // ST1Twov1d |
| 17018 | 0U, // ST1Twov1d_POST |
| 17019 | 0U, // ST1Twov2d |
| 17020 | 0U, // ST1Twov2d_POST |
| 17021 | 0U, // ST1Twov2s |
| 17022 | 0U, // ST1Twov2s_POST |
| 17023 | 0U, // ST1Twov4h |
| 17024 | 0U, // ST1Twov4h_POST |
| 17025 | 0U, // ST1Twov4s |
| 17026 | 0U, // ST1Twov4s_POST |
| 17027 | 0U, // ST1Twov8b |
| 17028 | 0U, // ST1Twov8b_POST |
| 17029 | 0U, // ST1Twov8h |
| 17030 | 0U, // ST1Twov8h_POST |
| 17031 | 13129961U, // ST1W |
| 17032 | 13129961U, // ST1W_2Z |
| 17033 | 713578729U, // ST1W_2Z_IMM |
| 17034 | 13129961U, // ST1W_2Z_STRIDED |
| 17035 | 713578729U, // ST1W_2Z_STRIDED_IMM |
| 17036 | 13129961U, // ST1W_4Z |
| 17037 | 715151593U, // ST1W_4Z_IMM |
| 17038 | 13129961U, // ST1W_4Z_STRIDED |
| 17039 | 715151593U, // ST1W_4Z_STRIDED_IMM |
| 17040 | 13129961U, // ST1W_D |
| 17041 | 707025129U, // ST1W_D_IMM |
| 17042 | 707025129U, // ST1W_IMM |
| 17043 | 13129961U, // ST1W_Q |
| 17044 | 707025129U, // ST1W_Q_IMM |
| 17045 | 13796161U, // ST1_MXIPXX_H_B |
| 17046 | 14058305U, // ST1_MXIPXX_H_D |
| 17047 | 14320449U, // ST1_MXIPXX_H_H |
| 17048 | 14582593U, // ST1_MXIPXX_H_Q |
| 17049 | 14844737U, // ST1_MXIPXX_H_S |
| 17050 | 13796161U, // ST1_MXIPXX_V_B |
| 17051 | 14058305U, // ST1_MXIPXX_V_D |
| 17052 | 14320449U, // ST1_MXIPXX_V_H |
| 17053 | 14582593U, // ST1_MXIPXX_V_Q |
| 17054 | 14844737U, // ST1_MXIPXX_V_S |
| 17055 | 0U, // ST1i16 |
| 17056 | 9U, // ST1i16_POST |
| 17057 | 0U, // ST1i32 |
| 17058 | 9U, // ST1i32_POST |
| 17059 | 0U, // ST1i64 |
| 17060 | 9U, // ST1i64_POST |
| 17061 | 0U, // ST1i8 |
| 17062 | 9U, // ST1i8_POST |
| 17063 | 12081385U, // ST2B |
| 17064 | 713578729U, // ST2B_IMM |
| 17065 | 12343529U, // ST2D |
| 17066 | 713578729U, // ST2D_IMM |
| 17067 | 117618U, // ST2GPostIndex |
| 17068 | 16369730U, // ST2GPreIndex |
| 17069 | 4202560U, // ST2Gi |
| 17070 | 12605673U, // ST2H |
| 17071 | 713578729U, // ST2H_IMM |
| 17072 | 14964969U, // ST2Q |
| 17073 | 713578729U, // ST2Q_IMM |
| 17074 | 0U, // ST2Twov16b |
| 17075 | 0U, // ST2Twov16b_POST |
| 17076 | 0U, // ST2Twov2d |
| 17077 | 0U, // ST2Twov2d_POST |
| 17078 | 0U, // ST2Twov2s |
| 17079 | 0U, // ST2Twov2s_POST |
| 17080 | 0U, // ST2Twov4h |
| 17081 | 0U, // ST2Twov4h_POST |
| 17082 | 0U, // ST2Twov4s |
| 17083 | 0U, // ST2Twov4s_POST |
| 17084 | 0U, // ST2Twov8b |
| 17085 | 0U, // ST2Twov8b_POST |
| 17086 | 0U, // ST2Twov8h |
| 17087 | 0U, // ST2Twov8h_POST |
| 17088 | 13129961U, // ST2W |
| 17089 | 713578729U, // ST2W_IMM |
| 17090 | 0U, // ST2i16 |
| 17091 | 9U, // ST2i16_POST |
| 17092 | 0U, // ST2i32 |
| 17093 | 9U, // ST2i32_POST |
| 17094 | 0U, // ST2i64 |
| 17095 | 9U, // ST2i64_POST |
| 17096 | 0U, // ST2i8 |
| 17097 | 9U, // ST2i8_POST |
| 17098 | 12081385U, // ST3B |
| 17099 | 15227113U, // ST3B_IMM |
| 17100 | 12343529U, // ST3D |
| 17101 | 15227113U, // ST3D_IMM |
| 17102 | 12605673U, // ST3H |
| 17103 | 15227113U, // ST3H_IMM |
| 17104 | 14964969U, // ST3Q |
| 17105 | 15227113U, // ST3Q_IMM |
| 17106 | 0U, // ST3Threev16b |
| 17107 | 0U, // ST3Threev16b_POST |
| 17108 | 0U, // ST3Threev2d |
| 17109 | 0U, // ST3Threev2d_POST |
| 17110 | 0U, // ST3Threev2s |
| 17111 | 0U, // ST3Threev2s_POST |
| 17112 | 0U, // ST3Threev4h |
| 17113 | 0U, // ST3Threev4h_POST |
| 17114 | 0U, // ST3Threev4s |
| 17115 | 0U, // ST3Threev4s_POST |
| 17116 | 0U, // ST3Threev8b |
| 17117 | 0U, // ST3Threev8b_POST |
| 17118 | 0U, // ST3Threev8h |
| 17119 | 0U, // ST3Threev8h_POST |
| 17120 | 13129961U, // ST3W |
| 17121 | 15227113U, // ST3W_IMM |
| 17122 | 0U, // ST3i16 |
| 17123 | 10U, // ST3i16_POST |
| 17124 | 0U, // ST3i32 |
| 17125 | 10U, // ST3i32_POST |
| 17126 | 0U, // ST3i64 |
| 17127 | 10U, // ST3i64_POST |
| 17128 | 0U, // ST3i8 |
| 17129 | 10U, // ST3i8_POST |
| 17130 | 12081385U, // ST4B |
| 17131 | 715151593U, // ST4B_IMM |
| 17132 | 12343529U, // ST4D |
| 17133 | 715151593U, // ST4D_IMM |
| 17134 | 0U, // ST4Fourv16b |
| 17135 | 0U, // ST4Fourv16b_POST |
| 17136 | 0U, // ST4Fourv2d |
| 17137 | 0U, // ST4Fourv2d_POST |
| 17138 | 0U, // ST4Fourv2s |
| 17139 | 0U, // ST4Fourv2s_POST |
| 17140 | 0U, // ST4Fourv4h |
| 17141 | 0U, // ST4Fourv4h_POST |
| 17142 | 0U, // ST4Fourv4s |
| 17143 | 0U, // ST4Fourv4s_POST |
| 17144 | 0U, // ST4Fourv8b |
| 17145 | 0U, // ST4Fourv8b_POST |
| 17146 | 0U, // ST4Fourv8h |
| 17147 | 0U, // ST4Fourv8h_POST |
| 17148 | 12605673U, // ST4H |
| 17149 | 715151593U, // ST4H_IMM |
| 17150 | 14964969U, // ST4Q |
| 17151 | 715151593U, // ST4Q_IMM |
| 17152 | 13129961U, // ST4W |
| 17153 | 715151593U, // ST4W_IMM |
| 17154 | 0U, // ST4i16 |
| 17155 | 9U, // ST4i16_POST |
| 17156 | 0U, // ST4i32 |
| 17157 | 9U, // ST4i32_POST |
| 17158 | 0U, // ST4i64 |
| 17159 | 10U, // ST4i64_POST |
| 17160 | 0U, // ST4i8 |
| 17161 | 9U, // ST4i8_POST |
| 17162 | 0U, // ST64B |
| 17163 | 10U, // ST64BV |
| 17164 | 10U, // ST64BV0 |
| 17165 | 752U, // STGM |
| 17166 | 772020544U, // STGPi |
| 17167 | 117618U, // STGPostIndex |
| 17168 | 888488258U, // STGPpost |
| 17169 | 872759618U, // STGPpre |
| 17170 | 16369730U, // STGPreIndex |
| 17171 | 4202560U, // STGi |
| 17172 | 4200768U, // STILPW |
| 17173 | 18170178U, // STILPWpre |
| 17174 | 4200768U, // STILPX |
| 17175 | 18432322U, // STILPXpre |
| 17176 | 0U, // STL1 |
| 17177 | 752U, // STLLRB |
| 17178 | 752U, // STLLRH |
| 17179 | 752U, // STLLRW |
| 17180 | 752U, // STLLRX |
| 17181 | 752U, // STLRB |
| 17182 | 752U, // STLRH |
| 17183 | 752U, // STLRW |
| 17184 | 1522U, // STLRWpre |
| 17185 | 752U, // STLRX |
| 17186 | 1538U, // STLRXpre |
| 17187 | 4200512U, // STLURBi |
| 17188 | 4200512U, // STLURHi |
| 17189 | 4200512U, // STLURWi |
| 17190 | 4200512U, // STLURXi |
| 17191 | 752U, // STLURbi |
| 17192 | 752U, // STLURdi |
| 17193 | 752U, // STLURhi |
| 17194 | 752U, // STLURqi |
| 17195 | 752U, // STLURsi |
| 17196 | 18618432U, // STLXPW |
| 17197 | 18618432U, // STLXPX |
| 17198 | 4200768U, // STLXRB |
| 17199 | 4200768U, // STLXRH |
| 17200 | 4200768U, // STLXRW |
| 17201 | 4200768U, // STLXRX |
| 17202 | 738466112U, // STNPDi |
| 17203 | 772020544U, // STNPQi |
| 17204 | 805574976U, // STNPSi |
| 17205 | 805574976U, // STNPWi |
| 17206 | 738466112U, // STNPXi |
| 17207 | 12081385U, // STNT1B_2Z |
| 17208 | 713578729U, // STNT1B_2Z_IMM |
| 17209 | 1275337031U, // STNT1B_2Z_STRIDED |
| 17210 | 1308891463U, // STNT1B_2Z_STRIDED_IMM |
| 17211 | 12081385U, // STNT1B_4Z |
| 17212 | 715151593U, // STNT1B_4Z_IMM |
| 17213 | 12081385U, // STNT1B_4Z_STRIDED |
| 17214 | 715151593U, // STNT1B_4Z_STRIDED_IMM |
| 17215 | 707025129U, // STNT1B_ZRI |
| 17216 | 12081385U, // STNT1B_ZRR |
| 17217 | 673470617U, // STNT1B_ZZR_D |
| 17218 | 673470553U, // STNT1B_ZZR_S |
| 17219 | 12343529U, // STNT1D_2Z |
| 17220 | 713578729U, // STNT1D_2Z_IMM |
| 17221 | 12343529U, // STNT1D_2Z_STRIDED |
| 17222 | 713578729U, // STNT1D_2Z_STRIDED_IMM |
| 17223 | 12343529U, // STNT1D_4Z |
| 17224 | 715151593U, // STNT1D_4Z_IMM |
| 17225 | 12343529U, // STNT1D_4Z_STRIDED |
| 17226 | 715151593U, // STNT1D_4Z_STRIDED_IMM |
| 17227 | 707025129U, // STNT1D_ZRI |
| 17228 | 12343529U, // STNT1D_ZRR |
| 17229 | 673470617U, // STNT1D_ZZR_D |
| 17230 | 12605673U, // STNT1H_2Z |
| 17231 | 713578729U, // STNT1H_2Z_IMM |
| 17232 | 1342445895U, // STNT1H_2Z_STRIDED |
| 17233 | 1308891463U, // STNT1H_2Z_STRIDED_IMM |
| 17234 | 12605673U, // STNT1H_4Z |
| 17235 | 715151593U, // STNT1H_4Z_IMM |
| 17236 | 12605673U, // STNT1H_4Z_STRIDED |
| 17237 | 715151593U, // STNT1H_4Z_STRIDED_IMM |
| 17238 | 707025129U, // STNT1H_ZRI |
| 17239 | 12605673U, // STNT1H_ZRR |
| 17240 | 673470617U, // STNT1H_ZZR_D |
| 17241 | 673470553U, // STNT1H_ZZR_S |
| 17242 | 13129961U, // STNT1W_2Z |
| 17243 | 713578729U, // STNT1W_2Z_IMM |
| 17244 | 13129961U, // STNT1W_2Z_STRIDED |
| 17245 | 713578729U, // STNT1W_2Z_STRIDED_IMM |
| 17246 | 13129961U, // STNT1W_4Z |
| 17247 | 715151593U, // STNT1W_4Z_IMM |
| 17248 | 13129961U, // STNT1W_4Z_STRIDED |
| 17249 | 715151593U, // STNT1W_4Z_STRIDED_IMM |
| 17250 | 707025129U, // STNT1W_ZRI |
| 17251 | 13129961U, // STNT1W_ZRR |
| 17252 | 673470617U, // STNT1W_ZZR_D |
| 17253 | 673470553U, // STNT1W_ZZR_S |
| 17254 | 738466112U, // STPDi |
| 17255 | 854933826U, // STPDpost |
| 17256 | 839205186U, // STPDpre |
| 17257 | 772020544U, // STPQi |
| 17258 | 888488258U, // STPQpost |
| 17259 | 872759618U, // STPQpre |
| 17260 | 805574976U, // STPSi |
| 17261 | 922042690U, // STPSpost |
| 17262 | 906314050U, // STPSpre |
| 17263 | 805574976U, // STPWi |
| 17264 | 922042690U, // STPWpost |
| 17265 | 906314050U, // STPWpre |
| 17266 | 738466112U, // STPXi |
| 17267 | 854933826U, // STPXpost |
| 17268 | 839205186U, // STPXpre |
| 17269 | 82802U, // STRBBpost |
| 17270 | 16334914U, // STRBBpre |
| 17271 | 939792448U, // STRBBroW |
| 17272 | 973346880U, // STRBBroX |
| 17273 | 122944U, // STRBBui |
| 17274 | 82802U, // STRBpost |
| 17275 | 16334914U, // STRBpre |
| 17276 | 939792448U, // STRBroW |
| 17277 | 973346880U, // STRBroX |
| 17278 | 122944U, // STRBui |
| 17279 | 82802U, // STRDpost |
| 17280 | 16334914U, // STRDpre |
| 17281 | 1006901312U, // STRDroW |
| 17282 | 1040455744U, // STRDroX |
| 17283 | 124992U, // STRDui |
| 17284 | 82802U, // STRHHpost |
| 17285 | 16334914U, // STRHHpre |
| 17286 | 1074010176U, // STRHHroW |
| 17287 | 1107564608U, // STRHHroX |
| 17288 | 127040U, // STRHHui |
| 17289 | 82802U, // STRHpost |
| 17290 | 16334914U, // STRHpre |
| 17291 | 1074010176U, // STRHroW |
| 17292 | 1107564608U, // STRHroX |
| 17293 | 127040U, // STRHui |
| 17294 | 82802U, // STRQpost |
| 17295 | 16334914U, // STRQpre |
| 17296 | 1141119040U, // STRQroW |
| 17297 | 1174673472U, // STRQroX |
| 17298 | 129088U, // STRQui |
| 17299 | 82802U, // STRSpost |
| 17300 | 16334914U, // STRSpre |
| 17301 | 1208227904U, // STRSroW |
| 17302 | 1241782336U, // STRSroX |
| 17303 | 131136U, // STRSui |
| 17304 | 82802U, // STRWpost |
| 17305 | 16334914U, // STRWpre |
| 17306 | 1208227904U, // STRWroW |
| 17307 | 1241782336U, // STRWroX |
| 17308 | 131136U, // STRWui |
| 17309 | 82802U, // STRXpost |
| 17310 | 16334914U, // STRXpre |
| 17311 | 1006901312U, // STRXroW |
| 17312 | 1040455744U, // STRXroX |
| 17313 | 124992U, // STRXui |
| 17314 | 16521280U, // STR_PXI |
| 17315 | 752U, // STR_TX |
| 17316 | 0U, // STR_ZA |
| 17317 | 16521280U, // STR_ZXI |
| 17318 | 4200512U, // STTRBi |
| 17319 | 4200512U, // STTRHi |
| 17320 | 4200512U, // STTRWi |
| 17321 | 4200512U, // STTRXi |
| 17322 | 4200512U, // STURBBi |
| 17323 | 4200512U, // STURBi |
| 17324 | 4200512U, // STURDi |
| 17325 | 4200512U, // STURHHi |
| 17326 | 4200512U, // STURHi |
| 17327 | 4200512U, // STURQi |
| 17328 | 4200512U, // STURSi |
| 17329 | 4200512U, // STURWi |
| 17330 | 4200512U, // STURXi |
| 17331 | 18618432U, // STXPW |
| 17332 | 18618432U, // STXPX |
| 17333 | 4200768U, // STXRB |
| 17334 | 4200768U, // STXRH |
| 17335 | 4200768U, // STXRW |
| 17336 | 4200768U, // STXRX |
| 17337 | 117618U, // STZ2GPostIndex |
| 17338 | 16369730U, // STZ2GPreIndex |
| 17339 | 4202560U, // STZ2Gi |
| 17340 | 752U, // STZGM |
| 17341 | 117618U, // STZGPostIndex |
| 17342 | 16369730U, // STZGPreIndex |
| 17343 | 4202560U, // STZGi |
| 17344 | 270400U, // SUBG |
| 17345 | 10304U, // SUBHNB_ZZZ_B |
| 17346 | 81U, // SUBHNB_ZZZ_H |
| 17347 | 12353U, // SUBHNB_ZZZ_S |
| 17348 | 14401U, // SUBHNT_ZZZ_B |
| 17349 | 49U, // SUBHNT_ZZZ_H |
| 17350 | 2112U, // SUBHNT_ZZZ_S |
| 17351 | 16448U, // SUBHNv2i64_v2i32 |
| 17352 | 18497U, // SUBHNv2i64_v4i32 |
| 17353 | 16448U, // SUBHNv4i32_v4i16 |
| 17354 | 18497U, // SUBHNv4i32_v8i16 |
| 17355 | 18497U, // SUBHNv8i16_v16i8 |
| 17356 | 16448U, // SUBHNv8i16_v8i8 |
| 17357 | 6208U, // SUBP |
| 17358 | 6208U, // SUBPS |
| 17359 | 530496U, // SUBPT_shift |
| 17360 | 32834U, // SUBR_ZI_B |
| 17361 | 34881U, // SUBR_ZI_D |
| 17362 | 193U, // SUBR_ZI_H |
| 17363 | 36930U, // SUBR_ZI_S |
| 17364 | 33837153U, // SUBR_ZPmZ_B |
| 17365 | 67383393U, // SUBR_ZPmZ_D |
| 17366 | 101472369U, // SUBR_ZPmZ_H |
| 17367 | 134504545U, // SUBR_ZPmZ_S |
| 17368 | 26688U, // SUBSWri |
| 17369 | 28736U, // SUBSWrs |
| 17370 | 30784U, // SUBSWrx |
| 17371 | 26688U, // SUBSXri |
| 17372 | 28736U, // SUBSXrs |
| 17373 | 30784U, // SUBSXrx |
| 17374 | 1054784U, // SUBSXrx64 |
| 17375 | 26688U, // SUBWri |
| 17376 | 28736U, // SUBWrs |
| 17377 | 30784U, // SUBWrx |
| 17378 | 26688U, // SUBXri |
| 17379 | 28736U, // SUBXrs |
| 17380 | 30784U, // SUBXrx |
| 17381 | 1054784U, // SUBXrx64 |
| 17382 | 1333409U, // SUB_VG2_M2Z2Z_D |
| 17383 | 1595569U, // SUB_VG2_M2Z2Z_S |
| 17384 | 102520993U, // SUB_VG2_M2ZZ_D |
| 17385 | 102783153U, // SUB_VG2_M2ZZ_S |
| 17386 | 161U, // SUB_VG2_M2Z_D |
| 17387 | 177U, // SUB_VG2_M2Z_S |
| 17388 | 1333409U, // SUB_VG4_M4Z4Z_D |
| 17389 | 1595569U, // SUB_VG4_M4Z4Z_S |
| 17390 | 102520993U, // SUB_VG4_M4ZZ_D |
| 17391 | 102783153U, // SUB_VG4_M4ZZ_S |
| 17392 | 161U, // SUB_VG4_M4Z_D |
| 17393 | 177U, // SUB_VG4_M4Z_S |
| 17394 | 32834U, // SUB_ZI_B |
| 17395 | 34881U, // SUB_ZI_D |
| 17396 | 193U, // SUB_ZI_H |
| 17397 | 36930U, // SUB_ZI_S |
| 17398 | 33837153U, // SUB_ZPmZ_B |
| 17399 | 67383393U, // SUB_ZPmZ_CPA |
| 17400 | 67383393U, // SUB_ZPmZ_D |
| 17401 | 101472369U, // SUB_ZPmZ_H |
| 17402 | 134504545U, // SUB_ZPmZ_S |
| 17403 | 20546U, // SUB_ZZZ_B |
| 17404 | 12353U, // SUB_ZZZ_CPA |
| 17405 | 12353U, // SUB_ZZZ_D |
| 17406 | 113U, // SUB_ZZZ_H |
| 17407 | 24642U, // SUB_ZZZ_S |
| 17408 | 16448U, // SUBv16i8 |
| 17409 | 6208U, // SUBv1i64 |
| 17410 | 16448U, // SUBv2i32 |
| 17411 | 16448U, // SUBv2i64 |
| 17412 | 16448U, // SUBv4i16 |
| 17413 | 16448U, // SUBv4i32 |
| 17414 | 16448U, // SUBv8i16 |
| 17415 | 16448U, // SUBv8i8 |
| 17416 | 5599937U, // SUDOT_VG2_M2ZZI_BToS |
| 17417 | 94913U, // SUDOT_VG2_M2ZZ_BToS |
| 17418 | 5599937U, // SUDOT_VG4_M4ZZI_BToS |
| 17419 | 94913U, // SUDOT_VG4_M4ZZ_BToS |
| 17420 | 77843U, // SUDOT_ZZZI |
| 17421 | 103565377U, // SUDOTlanev16i8 |
| 17422 | 103565377U, // SUDOTlanev8i8 |
| 17423 | 76498U, // SUMLALL_MZZI_BtoS |
| 17424 | 5599937U, // SUMLALL_VG2_M2ZZI_BtoS |
| 17425 | 94917U, // SUMLALL_VG2_M2ZZ_BtoS |
| 17426 | 5599937U, // SUMLALL_VG4_M4ZZI_BtoS |
| 17427 | 94918U, // SUMLALL_VG4_M4ZZ_BtoS |
| 17428 | 0U, // SUMOPA_MPPZZ_D |
| 17429 | 0U, // SUMOPA_MPPZZ_S |
| 17430 | 0U, // SUMOPS_MPPZZ_D |
| 17431 | 0U, // SUMOPS_MPPZZ_S |
| 17432 | 2U, // SUNPKHI_ZZ_D |
| 17433 | 0U, // SUNPKHI_ZZ_H |
| 17434 | 0U, // SUNPKHI_ZZ_S |
| 17435 | 2U, // SUNPKLO_ZZ_D |
| 17436 | 0U, // SUNPKLO_ZZ_H |
| 17437 | 0U, // SUNPKLO_ZZ_S |
| 17438 | 0U, // SUNPK_VG2_2ZZ_D |
| 17439 | 0U, // SUNPK_VG2_2ZZ_H |
| 17440 | 0U, // SUNPK_VG2_2ZZ_S |
| 17441 | 0U, // SUNPK_VG4_4Z2Z_D |
| 17442 | 0U, // SUNPK_VG4_4Z2Z_H |
| 17443 | 0U, // SUNPK_VG4_4Z2Z_S |
| 17444 | 33837153U, // SUQADD_ZPmZ_B |
| 17445 | 67383393U, // SUQADD_ZPmZ_D |
| 17446 | 101472369U, // SUQADD_ZPmZ_H |
| 17447 | 134504545U, // SUQADD_ZPmZ_S |
| 17448 | 1U, // SUQADDv16i8 |
| 17449 | 2U, // SUQADDv1i16 |
| 17450 | 2U, // SUQADDv1i32 |
| 17451 | 2U, // SUQADDv1i64 |
| 17452 | 2U, // SUQADDv1i8 |
| 17453 | 1U, // SUQADDv2i32 |
| 17454 | 1U, // SUQADDv2i64 |
| 17455 | 1U, // SUQADDv4i16 |
| 17456 | 1U, // SUQADDv4i32 |
| 17457 | 1U, // SUQADDv8i16 |
| 17458 | 1U, // SUQADDv8i8 |
| 17459 | 5599937U, // SUVDOT_VG4_M4ZZI_BToS |
| 17460 | 0U, // SVC |
| 17461 | 204757233U, // SVDOT_VG2_M2ZZI_HtoS |
| 17462 | 5599937U, // SVDOT_VG4_M4ZZI_BtoS |
| 17463 | 204757233U, // SVDOT_VG4_M4ZZI_HtoD |
| 17464 | 7U, // SWPAB |
| 17465 | 7U, // SWPAH |
| 17466 | 7U, // SWPALB |
| 17467 | 7U, // SWPALH |
| 17468 | 7U, // SWPALW |
| 17469 | 7U, // SWPALX |
| 17470 | 7U, // SWPAW |
| 17471 | 7U, // SWPAX |
| 17472 | 7U, // SWPB |
| 17473 | 7U, // SWPH |
| 17474 | 7U, // SWPLB |
| 17475 | 7U, // SWPLH |
| 17476 | 7U, // SWPLW |
| 17477 | 7U, // SWPLX |
| 17478 | 115012U, // SWPP |
| 17479 | 115012U, // SWPPA |
| 17480 | 115012U, // SWPPAL |
| 17481 | 115012U, // SWPPL |
| 17482 | 7U, // SWPW |
| 17483 | 7U, // SWPX |
| 17484 | 32U, // SXTB_ZPmZ_D |
| 17485 | 0U, // SXTB_ZPmZ_H |
| 17486 | 48U, // SXTB_ZPmZ_S |
| 17487 | 32U, // SXTH_ZPmZ_D |
| 17488 | 48U, // SXTH_ZPmZ_S |
| 17489 | 32U, // SXTW_ZPmZ_D |
| 17490 | 165952U, // SYSLxt |
| 17491 | 1562U, // SYSPxt |
| 17492 | 1578U, // SYSPxt_XZR |
| 17493 | 1594U, // SYSxt |
| 17494 | 133U, // TBLQ_ZZZ_B |
| 17495 | 10U, // TBLQ_ZZZ_D |
| 17496 | 113U, // TBLQ_ZZZ_H |
| 17497 | 24645U, // TBLQ_ZZZ_S |
| 17498 | 133U, // TBL_ZZZZ_B |
| 17499 | 10U, // TBL_ZZZZ_D |
| 17500 | 113U, // TBL_ZZZZ_H |
| 17501 | 24645U, // TBL_ZZZZ_S |
| 17502 | 133U, // TBL_ZZZ_B |
| 17503 | 10U, // TBL_ZZZ_D |
| 17504 | 113U, // TBL_ZZZ_H |
| 17505 | 24645U, // TBL_ZZZ_S |
| 17506 | 1607U, // TBLv16i8Four |
| 17507 | 1607U, // TBLv16i8One |
| 17508 | 1607U, // TBLv16i8Three |
| 17509 | 1607U, // TBLv16i8Two |
| 17510 | 1623U, // TBLv8i8Four |
| 17511 | 1623U, // TBLv8i8One |
| 17512 | 1623U, // TBLv8i8Three |
| 17513 | 1623U, // TBLv8i8Two |
| 17514 | 168000U, // TBNZW |
| 17515 | 168000U, // TBNZX |
| 17516 | 19U, // TBXQ_ZZZ_B |
| 17517 | 2112U, // TBXQ_ZZZ_D |
| 17518 | 257U, // TBXQ_ZZZ_H |
| 17519 | 4160U, // TBXQ_ZZZ_S |
| 17520 | 19U, // TBX_ZZZ_B |
| 17521 | 2112U, // TBX_ZZZ_D |
| 17522 | 257U, // TBX_ZZZ_H |
| 17523 | 4160U, // TBX_ZZZ_S |
| 17524 | 1611U, // TBXv16i8Four |
| 17525 | 1611U, // TBXv16i8One |
| 17526 | 1611U, // TBXv16i8Three |
| 17527 | 1611U, // TBXv16i8Two |
| 17528 | 1627U, // TBXv8i8Four |
| 17529 | 1627U, // TBXv8i8One |
| 17530 | 1627U, // TBXv8i8Three |
| 17531 | 1627U, // TBXv8i8Two |
| 17532 | 168000U, // TBZW |
| 17533 | 168000U, // TBZX |
| 17534 | 0U, // TCANCEL |
| 17535 | 0U, // TCOMMIT |
| 17536 | 0U, // TRCIT |
| 17537 | 20546U, // TRN1_PPP_B |
| 17538 | 12353U, // TRN1_PPP_D |
| 17539 | 113U, // TRN1_PPP_H |
| 17540 | 24642U, // TRN1_PPP_S |
| 17541 | 20546U, // TRN1_ZZZ_B |
| 17542 | 12353U, // TRN1_ZZZ_D |
| 17543 | 113U, // TRN1_ZZZ_H |
| 17544 | 1633U, // TRN1_ZZZ_Q |
| 17545 | 24642U, // TRN1_ZZZ_S |
| 17546 | 16448U, // TRN1v16i8 |
| 17547 | 16448U, // TRN1v2i32 |
| 17548 | 16448U, // TRN1v2i64 |
| 17549 | 16448U, // TRN1v4i16 |
| 17550 | 16448U, // TRN1v4i32 |
| 17551 | 16448U, // TRN1v8i16 |
| 17552 | 16448U, // TRN1v8i8 |
| 17553 | 20546U, // TRN2_PPP_B |
| 17554 | 12353U, // TRN2_PPP_D |
| 17555 | 113U, // TRN2_PPP_H |
| 17556 | 24642U, // TRN2_PPP_S |
| 17557 | 20546U, // TRN2_ZZZ_B |
| 17558 | 12353U, // TRN2_ZZZ_D |
| 17559 | 113U, // TRN2_ZZZ_H |
| 17560 | 1633U, // TRN2_ZZZ_Q |
| 17561 | 24642U, // TRN2_ZZZ_S |
| 17562 | 16448U, // TRN2v16i8 |
| 17563 | 16448U, // TRN2v2i32 |
| 17564 | 16448U, // TRN2v2i64 |
| 17565 | 16448U, // TRN2v4i16 |
| 17566 | 16448U, // TRN2v4i32 |
| 17567 | 16448U, // TRN2v8i16 |
| 17568 | 16448U, // TRN2v8i8 |
| 17569 | 0U, // TSB |
| 17570 | 0U, // TSTART |
| 17571 | 0U, // TTEST |
| 17572 | 4160U, // UABALB_ZZZ_D |
| 17573 | 17U, // UABALB_ZZZ_H |
| 17574 | 14401U, // UABALB_ZZZ_S |
| 17575 | 4160U, // UABALT_ZZZ_D |
| 17576 | 17U, // UABALT_ZZZ_H |
| 17577 | 14401U, // UABALT_ZZZ_S |
| 17578 | 18497U, // UABALv16i8_v8i16 |
| 17579 | 18497U, // UABALv2i32_v2i64 |
| 17580 | 18497U, // UABALv4i16_v4i32 |
| 17581 | 18497U, // UABALv4i32_v2i64 |
| 17582 | 18497U, // UABALv8i16_v4i32 |
| 17583 | 18497U, // UABALv8i8_v8i16 |
| 17584 | 19U, // UABA_ZZZ_B |
| 17585 | 2112U, // UABA_ZZZ_D |
| 17586 | 257U, // UABA_ZZZ_H |
| 17587 | 4160U, // UABA_ZZZ_S |
| 17588 | 18497U, // UABAv16i8 |
| 17589 | 18497U, // UABAv2i32 |
| 17590 | 18497U, // UABAv4i16 |
| 17591 | 18497U, // UABAv4i32 |
| 17592 | 18497U, // UABAv8i16 |
| 17593 | 18497U, // UABAv8i8 |
| 17594 | 24642U, // UABDLB_ZZZ_D |
| 17595 | 129U, // UABDLB_ZZZ_H |
| 17596 | 10304U, // UABDLB_ZZZ_S |
| 17597 | 24642U, // UABDLT_ZZZ_D |
| 17598 | 129U, // UABDLT_ZZZ_H |
| 17599 | 10304U, // UABDLT_ZZZ_S |
| 17600 | 16448U, // UABDLv16i8_v8i16 |
| 17601 | 16448U, // UABDLv2i32_v2i64 |
| 17602 | 16448U, // UABDLv4i16_v4i32 |
| 17603 | 16448U, // UABDLv4i32_v2i64 |
| 17604 | 16448U, // UABDLv8i16_v4i32 |
| 17605 | 16448U, // UABDLv8i8_v8i16 |
| 17606 | 33837153U, // UABD_ZPmZ_B |
| 17607 | 67383393U, // UABD_ZPmZ_D |
| 17608 | 101472369U, // UABD_ZPmZ_H |
| 17609 | 134504545U, // UABD_ZPmZ_S |
| 17610 | 16448U, // UABDv16i8 |
| 17611 | 16448U, // UABDv2i32 |
| 17612 | 16448U, // UABDv4i16 |
| 17613 | 16448U, // UABDv4i32 |
| 17614 | 16448U, // UABDv8i16 |
| 17615 | 16448U, // UABDv8i8 |
| 17616 | 4193U, // UADALP_ZPmZ_D |
| 17617 | 17U, // UADALP_ZPmZ_H |
| 17618 | 14433U, // UADALP_ZPmZ_S |
| 17619 | 1U, // UADALPv16i8_v8i16 |
| 17620 | 1U, // UADALPv2i32_v1i64 |
| 17621 | 1U, // UADALPv4i16_v2i32 |
| 17622 | 1U, // UADALPv4i32_v2i64 |
| 17623 | 1U, // UADALPv8i16_v4i32 |
| 17624 | 1U, // UADALPv8i8_v4i16 |
| 17625 | 24642U, // UADDLB_ZZZ_D |
| 17626 | 129U, // UADDLB_ZZZ_H |
| 17627 | 10304U, // UADDLB_ZZZ_S |
| 17628 | 0U, // UADDLPv16i8_v8i16 |
| 17629 | 0U, // UADDLPv2i32_v1i64 |
| 17630 | 0U, // UADDLPv4i16_v2i32 |
| 17631 | 0U, // UADDLPv4i32_v2i64 |
| 17632 | 0U, // UADDLPv8i16_v4i32 |
| 17633 | 0U, // UADDLPv8i8_v4i16 |
| 17634 | 24642U, // UADDLT_ZZZ_D |
| 17635 | 129U, // UADDLT_ZZZ_H |
| 17636 | 10304U, // UADDLT_ZZZ_S |
| 17637 | 0U, // UADDLVv16i8v |
| 17638 | 0U, // UADDLVv4i16v |
| 17639 | 0U, // UADDLVv4i32v |
| 17640 | 0U, // UADDLVv8i16v |
| 17641 | 0U, // UADDLVv8i8v |
| 17642 | 16448U, // UADDLv16i8_v8i16 |
| 17643 | 16448U, // UADDLv2i32_v2i64 |
| 17644 | 16448U, // UADDLv4i16_v4i32 |
| 17645 | 16448U, // UADDLv4i32_v2i64 |
| 17646 | 16448U, // UADDLv8i16_v4i32 |
| 17647 | 16448U, // UADDLv8i8_v8i16 |
| 17648 | 0U, // UADDV_VPZ_B |
| 17649 | 0U, // UADDV_VPZ_D |
| 17650 | 0U, // UADDV_VPZ_H |
| 17651 | 0U, // UADDV_VPZ_S |
| 17652 | 24641U, // UADDWB_ZZZ_D |
| 17653 | 129U, // UADDWB_ZZZ_H |
| 17654 | 10306U, // UADDWB_ZZZ_S |
| 17655 | 24641U, // UADDWT_ZZZ_D |
| 17656 | 129U, // UADDWT_ZZZ_H |
| 17657 | 10306U, // UADDWT_ZZZ_S |
| 17658 | 16448U, // UADDWv16i8_v8i16 |
| 17659 | 16448U, // UADDWv2i32_v2i64 |
| 17660 | 16448U, // UADDWv4i16_v4i32 |
| 17661 | 16448U, // UADDWv4i32_v2i64 |
| 17662 | 16448U, // UADDWv8i16_v4i32 |
| 17663 | 16448U, // UADDWv8i8_v8i16 |
| 17664 | 268352U, // UBFMWri |
| 17665 | 268352U, // UBFMXri |
| 17666 | 17U, // UCLAMP_VG2_2Z2Z_B |
| 17667 | 33U, // UCLAMP_VG2_2Z2Z_D |
| 17668 | 257U, // UCLAMP_VG2_2Z2Z_H |
| 17669 | 49U, // UCLAMP_VG2_2Z2Z_S |
| 17670 | 17U, // UCLAMP_VG4_4Z4Z_B |
| 17671 | 33U, // UCLAMP_VG4_4Z4Z_D |
| 17672 | 257U, // UCLAMP_VG4_4Z4Z_H |
| 17673 | 49U, // UCLAMP_VG4_4Z4Z_S |
| 17674 | 19U, // UCLAMP_ZZZ_B |
| 17675 | 2112U, // UCLAMP_ZZZ_D |
| 17676 | 257U, // UCLAMP_ZZZ_H |
| 17677 | 4160U, // UCLAMP_ZZZ_S |
| 17678 | 6208U, // UCVTFSWDri |
| 17679 | 6208U, // UCVTFSWHri |
| 17680 | 6208U, // UCVTFSWSri |
| 17681 | 6208U, // UCVTFSXDri |
| 17682 | 6208U, // UCVTFSXHri |
| 17683 | 6208U, // UCVTFSXSri |
| 17684 | 0U, // UCVTFUWDri |
| 17685 | 0U, // UCVTFUWHri |
| 17686 | 0U, // UCVTFUWSri |
| 17687 | 0U, // UCVTFUXDri |
| 17688 | 0U, // UCVTFUXHri |
| 17689 | 0U, // UCVTFUXSri |
| 17690 | 0U, // UCVTF_2Z2Z_StoS |
| 17691 | 0U, // UCVTF_4Z4Z_StoS |
| 17692 | 32U, // UCVTF_ZPmZ_DtoD |
| 17693 | 5U, // UCVTF_ZPmZ_DtoH |
| 17694 | 32U, // UCVTF_ZPmZ_DtoS |
| 17695 | 0U, // UCVTF_ZPmZ_HtoH |
| 17696 | 48U, // UCVTF_ZPmZ_StoD |
| 17697 | 2U, // UCVTF_ZPmZ_StoH |
| 17698 | 48U, // UCVTF_ZPmZ_StoS |
| 17699 | 6208U, // UCVTFd |
| 17700 | 6208U, // UCVTFh |
| 17701 | 6208U, // UCVTFs |
| 17702 | 0U, // UCVTFv1i16 |
| 17703 | 0U, // UCVTFv1i32 |
| 17704 | 0U, // UCVTFv1i64 |
| 17705 | 0U, // UCVTFv2f32 |
| 17706 | 0U, // UCVTFv2f64 |
| 17707 | 6208U, // UCVTFv2i32_shift |
| 17708 | 6208U, // UCVTFv2i64_shift |
| 17709 | 0U, // UCVTFv4f16 |
| 17710 | 0U, // UCVTFv4f32 |
| 17711 | 6208U, // UCVTFv4i16_shift |
| 17712 | 6208U, // UCVTFv4i32_shift |
| 17713 | 0U, // UCVTFv8f16 |
| 17714 | 6208U, // UCVTFv8i16_shift |
| 17715 | 0U, // UDF |
| 17716 | 67383393U, // UDIVR_ZPmZ_D |
| 17717 | 134504545U, // UDIVR_ZPmZ_S |
| 17718 | 6208U, // UDIVWr |
| 17719 | 6208U, // UDIVXr |
| 17720 | 67383393U, // UDIV_ZPmZ_D |
| 17721 | 134504545U, // UDIV_ZPmZ_S |
| 17722 | 92865U, // UDOT_VG2_M2Z2Z_BtoS |
| 17723 | 3168497U, // UDOT_VG2_M2Z2Z_HtoD |
| 17724 | 3168497U, // UDOT_VG2_M2Z2Z_HtoS |
| 17725 | 5599937U, // UDOT_VG2_M2ZZI_BToS |
| 17726 | 204757233U, // UDOT_VG2_M2ZZI_HToS |
| 17727 | 204757233U, // UDOT_VG2_M2ZZI_HtoD |
| 17728 | 94913U, // UDOT_VG2_M2ZZ_BtoS |
| 17729 | 104093937U, // UDOT_VG2_M2ZZ_HtoD |
| 17730 | 104093937U, // UDOT_VG2_M2ZZ_HtoS |
| 17731 | 92865U, // UDOT_VG4_M4Z4Z_BtoS |
| 17732 | 3168497U, // UDOT_VG4_M4Z4Z_HtoD |
| 17733 | 3168497U, // UDOT_VG4_M4Z4Z_HtoS |
| 17734 | 5599937U, // UDOT_VG4_M4ZZI_BtoS |
| 17735 | 204757233U, // UDOT_VG4_M4ZZI_HToS |
| 17736 | 204757233U, // UDOT_VG4_M4ZZI_HtoD |
| 17737 | 94913U, // UDOT_VG4_M4ZZ_BtoS |
| 17738 | 104093937U, // UDOT_VG4_M4ZZ_HtoD |
| 17739 | 104093937U, // UDOT_VG4_M4ZZ_HtoS |
| 17740 | 103561281U, // UDOT_ZZZI_D |
| 17741 | 103561281U, // UDOT_ZZZI_HtoS |
| 17742 | 77843U, // UDOT_ZZZI_S |
| 17743 | 14401U, // UDOT_ZZZ_D |
| 17744 | 14401U, // UDOT_ZZZ_HtoS |
| 17745 | 19U, // UDOT_ZZZ_S |
| 17746 | 103565377U, // UDOTlanev16i8 |
| 17747 | 103565377U, // UDOTlanev8i8 |
| 17748 | 0U, // UDOTv16i8 |
| 17749 | 0U, // UDOTv8i8 |
| 17750 | 33837153U, // UHADD_ZPmZ_B |
| 17751 | 67383393U, // UHADD_ZPmZ_D |
| 17752 | 101472369U, // UHADD_ZPmZ_H |
| 17753 | 134504545U, // UHADD_ZPmZ_S |
| 17754 | 16448U, // UHADDv16i8 |
| 17755 | 16448U, // UHADDv2i32 |
| 17756 | 16448U, // UHADDv4i16 |
| 17757 | 16448U, // UHADDv4i32 |
| 17758 | 16448U, // UHADDv8i16 |
| 17759 | 16448U, // UHADDv8i8 |
| 17760 | 33837153U, // UHSUBR_ZPmZ_B |
| 17761 | 67383393U, // UHSUBR_ZPmZ_D |
| 17762 | 101472369U, // UHSUBR_ZPmZ_H |
| 17763 | 134504545U, // UHSUBR_ZPmZ_S |
| 17764 | 33837153U, // UHSUB_ZPmZ_B |
| 17765 | 67383393U, // UHSUB_ZPmZ_D |
| 17766 | 101472369U, // UHSUB_ZPmZ_H |
| 17767 | 134504545U, // UHSUB_ZPmZ_S |
| 17768 | 16448U, // UHSUBv16i8 |
| 17769 | 16448U, // UHSUBv2i32 |
| 17770 | 16448U, // UHSUBv4i16 |
| 17771 | 16448U, // UHSUBv4i32 |
| 17772 | 16448U, // UHSUBv8i16 |
| 17773 | 16448U, // UHSUBv8i8 |
| 17774 | 268352U, // UMADDLrrr |
| 17775 | 33837153U, // UMAXP_ZPmZ_B |
| 17776 | 67383393U, // UMAXP_ZPmZ_D |
| 17777 | 101472369U, // UMAXP_ZPmZ_H |
| 17778 | 134504545U, // UMAXP_ZPmZ_S |
| 17779 | 16448U, // UMAXPv16i8 |
| 17780 | 16448U, // UMAXPv2i32 |
| 17781 | 16448U, // UMAXPv4i16 |
| 17782 | 16448U, // UMAXPv4i32 |
| 17783 | 16448U, // UMAXPv8i16 |
| 17784 | 16448U, // UMAXPv8i8 |
| 17785 | 20545U, // UMAXQV_VPZ_B |
| 17786 | 12353U, // UMAXQV_VPZ_D |
| 17787 | 10305U, // UMAXQV_VPZ_H |
| 17788 | 24641U, // UMAXQV_VPZ_S |
| 17789 | 0U, // UMAXV_VPZ_B |
| 17790 | 0U, // UMAXV_VPZ_D |
| 17791 | 0U, // UMAXV_VPZ_H |
| 17792 | 0U, // UMAXV_VPZ_S |
| 17793 | 0U, // UMAXVv16i8v |
| 17794 | 0U, // UMAXVv4i16v |
| 17795 | 0U, // UMAXVv4i32v |
| 17796 | 0U, // UMAXVv8i16v |
| 17797 | 0U, // UMAXVv8i8v |
| 17798 | 6208U, // UMAXWri |
| 17799 | 6208U, // UMAXWrr |
| 17800 | 6208U, // UMAXXri |
| 17801 | 6208U, // UMAXXrr |
| 17802 | 1457U, // UMAX_VG2_2Z2Z_B |
| 17803 | 513U, // UMAX_VG2_2Z2Z_D |
| 17804 | 273U, // UMAX_VG2_2Z2Z_H |
| 17805 | 529U, // UMAX_VG2_2Z2Z_S |
| 17806 | 129U, // UMAX_VG2_2ZZ_B |
| 17807 | 145U, // UMAX_VG2_2ZZ_D |
| 17808 | 113U, // UMAX_VG2_2ZZ_H |
| 17809 | 81U, // UMAX_VG2_2ZZ_S |
| 17810 | 1457U, // UMAX_VG4_4Z4Z_B |
| 17811 | 513U, // UMAX_VG4_4Z4Z_D |
| 17812 | 273U, // UMAX_VG4_4Z4Z_H |
| 17813 | 529U, // UMAX_VG4_4Z4Z_S |
| 17814 | 129U, // UMAX_VG4_4ZZ_B |
| 17815 | 145U, // UMAX_VG4_4ZZ_D |
| 17816 | 113U, // UMAX_VG4_4ZZ_H |
| 17817 | 81U, // UMAX_VG4_4ZZ_S |
| 17818 | 170050U, // UMAX_ZI_B |
| 17819 | 170049U, // UMAX_ZI_D |
| 17820 | 497U, // UMAX_ZI_H |
| 17821 | 170050U, // UMAX_ZI_S |
| 17822 | 33837153U, // UMAX_ZPmZ_B |
| 17823 | 67383393U, // UMAX_ZPmZ_D |
| 17824 | 101472369U, // UMAX_ZPmZ_H |
| 17825 | 134504545U, // UMAX_ZPmZ_S |
| 17826 | 16448U, // UMAXv16i8 |
| 17827 | 16448U, // UMAXv2i32 |
| 17828 | 16448U, // UMAXv4i16 |
| 17829 | 16448U, // UMAXv4i32 |
| 17830 | 16448U, // UMAXv8i16 |
| 17831 | 16448U, // UMAXv8i8 |
| 17832 | 33837153U, // UMINP_ZPmZ_B |
| 17833 | 67383393U, // UMINP_ZPmZ_D |
| 17834 | 101472369U, // UMINP_ZPmZ_H |
| 17835 | 134504545U, // UMINP_ZPmZ_S |
| 17836 | 16448U, // UMINPv16i8 |
| 17837 | 16448U, // UMINPv2i32 |
| 17838 | 16448U, // UMINPv4i16 |
| 17839 | 16448U, // UMINPv4i32 |
| 17840 | 16448U, // UMINPv8i16 |
| 17841 | 16448U, // UMINPv8i8 |
| 17842 | 20545U, // UMINQV_VPZ_B |
| 17843 | 12353U, // UMINQV_VPZ_D |
| 17844 | 10305U, // UMINQV_VPZ_H |
| 17845 | 24641U, // UMINQV_VPZ_S |
| 17846 | 0U, // UMINV_VPZ_B |
| 17847 | 0U, // UMINV_VPZ_D |
| 17848 | 0U, // UMINV_VPZ_H |
| 17849 | 0U, // UMINV_VPZ_S |
| 17850 | 0U, // UMINVv16i8v |
| 17851 | 0U, // UMINVv4i16v |
| 17852 | 0U, // UMINVv4i32v |
| 17853 | 0U, // UMINVv8i16v |
| 17854 | 0U, // UMINVv8i8v |
| 17855 | 6208U, // UMINWri |
| 17856 | 6208U, // UMINWrr |
| 17857 | 6208U, // UMINXri |
| 17858 | 6208U, // UMINXrr |
| 17859 | 1457U, // UMIN_VG2_2Z2Z_B |
| 17860 | 513U, // UMIN_VG2_2Z2Z_D |
| 17861 | 273U, // UMIN_VG2_2Z2Z_H |
| 17862 | 529U, // UMIN_VG2_2Z2Z_S |
| 17863 | 129U, // UMIN_VG2_2ZZ_B |
| 17864 | 145U, // UMIN_VG2_2ZZ_D |
| 17865 | 113U, // UMIN_VG2_2ZZ_H |
| 17866 | 81U, // UMIN_VG2_2ZZ_S |
| 17867 | 1457U, // UMIN_VG4_4Z4Z_B |
| 17868 | 513U, // UMIN_VG4_4Z4Z_D |
| 17869 | 273U, // UMIN_VG4_4Z4Z_H |
| 17870 | 529U, // UMIN_VG4_4Z4Z_S |
| 17871 | 129U, // UMIN_VG4_4ZZ_B |
| 17872 | 145U, // UMIN_VG4_4ZZ_D |
| 17873 | 113U, // UMIN_VG4_4ZZ_H |
| 17874 | 81U, // UMIN_VG4_4ZZ_S |
| 17875 | 170050U, // UMIN_ZI_B |
| 17876 | 170049U, // UMIN_ZI_D |
| 17877 | 497U, // UMIN_ZI_H |
| 17878 | 170050U, // UMIN_ZI_S |
| 17879 | 33837153U, // UMIN_ZPmZ_B |
| 17880 | 67383393U, // UMIN_ZPmZ_D |
| 17881 | 101472369U, // UMIN_ZPmZ_H |
| 17882 | 134504545U, // UMIN_ZPmZ_S |
| 17883 | 16448U, // UMINv16i8 |
| 17884 | 16448U, // UMINv2i32 |
| 17885 | 16448U, // UMINv4i16 |
| 17886 | 16448U, // UMINv4i32 |
| 17887 | 16448U, // UMINv8i16 |
| 17888 | 16448U, // UMINv8i8 |
| 17889 | 103551040U, // UMLALB_ZZZI_D |
| 17890 | 103561281U, // UMLALB_ZZZI_S |
| 17891 | 4160U, // UMLALB_ZZZ_D |
| 17892 | 17U, // UMLALB_ZZZ_H |
| 17893 | 14401U, // UMLALB_ZZZ_S |
| 17894 | 76498U, // UMLALL_MZZI_BtoS |
| 17895 | 76066U, // UMLALL_MZZI_HtoD |
| 17896 | 722U, // UMLALL_MZZ_BtoS |
| 17897 | 290U, // UMLALL_MZZ_HtoD |
| 17898 | 92865U, // UMLALL_VG2_M2Z2Z_BtoS |
| 17899 | 3168497U, // UMLALL_VG2_M2Z2Z_HtoD |
| 17900 | 5599937U, // UMLALL_VG2_M2ZZI_BtoS |
| 17901 | 204757233U, // UMLALL_VG2_M2ZZI_HtoD |
| 17902 | 94917U, // UMLALL_VG2_M2ZZ_BtoS |
| 17903 | 104093941U, // UMLALL_VG2_M2ZZ_HtoD |
| 17904 | 92865U, // UMLALL_VG4_M4Z4Z_BtoS |
| 17905 | 3168497U, // UMLALL_VG4_M4Z4Z_HtoD |
| 17906 | 5599937U, // UMLALL_VG4_M4ZZI_BtoS |
| 17907 | 204757233U, // UMLALL_VG4_M4ZZI_HtoD |
| 17908 | 94918U, // UMLALL_VG4_M4ZZ_BtoS |
| 17909 | 104093942U, // UMLALL_VG4_M4ZZ_HtoD |
| 17910 | 103551040U, // UMLALT_ZZZI_D |
| 17911 | 103561281U, // UMLALT_ZZZI_S |
| 17912 | 4160U, // UMLALT_ZZZ_D |
| 17913 | 17U, // UMLALT_ZZZ_H |
| 17914 | 14401U, // UMLALT_ZZZ_S |
| 17915 | 76066U, // UMLAL_MZZI_HtoS |
| 17916 | 290U, // UMLAL_MZZ_HtoS |
| 17917 | 3168497U, // UMLAL_VG2_M2Z2Z_HtoS |
| 17918 | 204757233U, // UMLAL_VG2_M2ZZI_S |
| 17919 | 104093937U, // UMLAL_VG2_M2ZZ_HtoS |
| 17920 | 3168497U, // UMLAL_VG4_M4Z4Z_HtoS |
| 17921 | 204757233U, // UMLAL_VG4_M4ZZI_HtoS |
| 17922 | 104093937U, // UMLAL_VG4_M4ZZ_HtoS |
| 17923 | 18497U, // UMLALv16i8_v8i16 |
| 17924 | 103565377U, // UMLALv2i32_indexed |
| 17925 | 18497U, // UMLALv2i32_v2i64 |
| 17926 | 103565377U, // UMLALv4i16_indexed |
| 17927 | 18497U, // UMLALv4i16_v4i32 |
| 17928 | 103565377U, // UMLALv4i32_indexed |
| 17929 | 18497U, // UMLALv4i32_v2i64 |
| 17930 | 103565377U, // UMLALv8i16_indexed |
| 17931 | 18497U, // UMLALv8i16_v4i32 |
| 17932 | 18497U, // UMLALv8i8_v8i16 |
| 17933 | 103551040U, // UMLSLB_ZZZI_D |
| 17934 | 103561281U, // UMLSLB_ZZZI_S |
| 17935 | 4160U, // UMLSLB_ZZZ_D |
| 17936 | 17U, // UMLSLB_ZZZ_H |
| 17937 | 14401U, // UMLSLB_ZZZ_S |
| 17938 | 76498U, // UMLSLL_MZZI_BtoS |
| 17939 | 76066U, // UMLSLL_MZZI_HtoD |
| 17940 | 722U, // UMLSLL_MZZ_BtoS |
| 17941 | 290U, // UMLSLL_MZZ_HtoD |
| 17942 | 92865U, // UMLSLL_VG2_M2Z2Z_BtoS |
| 17943 | 3168497U, // UMLSLL_VG2_M2Z2Z_HtoD |
| 17944 | 5599937U, // UMLSLL_VG2_M2ZZI_BtoS |
| 17945 | 204757233U, // UMLSLL_VG2_M2ZZI_HtoD |
| 17946 | 94917U, // UMLSLL_VG2_M2ZZ_BtoS |
| 17947 | 104093941U, // UMLSLL_VG2_M2ZZ_HtoD |
| 17948 | 92865U, // UMLSLL_VG4_M4Z4Z_BtoS |
| 17949 | 3168497U, // UMLSLL_VG4_M4Z4Z_HtoD |
| 17950 | 5599937U, // UMLSLL_VG4_M4ZZI_BtoS |
| 17951 | 204757233U, // UMLSLL_VG4_M4ZZI_HtoD |
| 17952 | 94918U, // UMLSLL_VG4_M4ZZ_BtoS |
| 17953 | 104093942U, // UMLSLL_VG4_M4ZZ_HtoD |
| 17954 | 103551040U, // UMLSLT_ZZZI_D |
| 17955 | 103561281U, // UMLSLT_ZZZI_S |
| 17956 | 4160U, // UMLSLT_ZZZ_D |
| 17957 | 17U, // UMLSLT_ZZZ_H |
| 17958 | 14401U, // UMLSLT_ZZZ_S |
| 17959 | 76066U, // UMLSL_MZZI_HtoS |
| 17960 | 290U, // UMLSL_MZZ_HtoS |
| 17961 | 3168497U, // UMLSL_VG2_M2Z2Z_HtoS |
| 17962 | 204757233U, // UMLSL_VG2_M2ZZI_S |
| 17963 | 104093937U, // UMLSL_VG2_M2ZZ_HtoS |
| 17964 | 3168497U, // UMLSL_VG4_M4Z4Z_HtoS |
| 17965 | 204757233U, // UMLSL_VG4_M4ZZI_HtoS |
| 17966 | 104093937U, // UMLSL_VG4_M4ZZ_HtoS |
| 17967 | 18497U, // UMLSLv16i8_v8i16 |
| 17968 | 103565377U, // UMLSLv2i32_indexed |
| 17969 | 18497U, // UMLSLv2i32_v2i64 |
| 17970 | 103565377U, // UMLSLv4i16_indexed |
| 17971 | 18497U, // UMLSLv4i16_v4i32 |
| 17972 | 103565377U, // UMLSLv4i32_indexed |
| 17973 | 18497U, // UMLSLv4i32_v2i64 |
| 17974 | 103565377U, // UMLSLv8i16_indexed |
| 17975 | 18497U, // UMLSLv8i16_v4i32 |
| 17976 | 18497U, // UMLSLv8i8_v8i16 |
| 17977 | 0U, // UMMLA |
| 17978 | 19U, // UMMLA_ZZZ |
| 17979 | 0U, // UMOPA_MPPZZ_D |
| 17980 | 0U, // UMOPA_MPPZZ_HtoS |
| 17981 | 0U, // UMOPA_MPPZZ_S |
| 17982 | 0U, // UMOPS_MPPZZ_D |
| 17983 | 0U, // UMOPS_MPPZZ_HtoS |
| 17984 | 0U, // UMOPS_MPPZZ_S |
| 17985 | 448U, // UMOVvi16 |
| 17986 | 448U, // UMOVvi16_idx0 |
| 17987 | 448U, // UMOVvi32 |
| 17988 | 448U, // UMOVvi32_idx0 |
| 17989 | 448U, // UMOVvi64 |
| 17990 | 448U, // UMOVvi64_idx0 |
| 17991 | 448U, // UMOVvi8 |
| 17992 | 448U, // UMOVvi8_idx0 |
| 17993 | 268352U, // UMSUBLrrr |
| 17994 | 33837153U, // UMULH_ZPmZ_B |
| 17995 | 67383393U, // UMULH_ZPmZ_D |
| 17996 | 101472369U, // UMULH_ZPmZ_H |
| 17997 | 134504545U, // UMULH_ZPmZ_S |
| 17998 | 20546U, // UMULH_ZZZ_B |
| 17999 | 12353U, // UMULH_ZZZ_D |
| 18000 | 113U, // UMULH_ZZZ_H |
| 18001 | 24642U, // UMULH_ZZZ_S |
| 18002 | 6208U, // UMULHrr |
| 18003 | 6053954U, // UMULLB_ZZZI_D |
| 18004 | 6039616U, // UMULLB_ZZZI_S |
| 18005 | 24642U, // UMULLB_ZZZ_D |
| 18006 | 129U, // UMULLB_ZZZ_H |
| 18007 | 10304U, // UMULLB_ZZZ_S |
| 18008 | 6053954U, // UMULLT_ZZZI_D |
| 18009 | 6039616U, // UMULLT_ZZZI_S |
| 18010 | 24642U, // UMULLT_ZZZ_D |
| 18011 | 129U, // UMULLT_ZZZ_H |
| 18012 | 10304U, // UMULLT_ZZZ_S |
| 18013 | 16448U, // UMULLv16i8_v8i16 |
| 18014 | 6045760U, // UMULLv2i32_indexed |
| 18015 | 16448U, // UMULLv2i32_v2i64 |
| 18016 | 6045760U, // UMULLv4i16_indexed |
| 18017 | 16448U, // UMULLv4i16_v4i32 |
| 18018 | 6045760U, // UMULLv4i32_indexed |
| 18019 | 16448U, // UMULLv4i32_v2i64 |
| 18020 | 6045760U, // UMULLv8i16_indexed |
| 18021 | 16448U, // UMULLv8i16_v4i32 |
| 18022 | 16448U, // UMULLv8i8_v8i16 |
| 18023 | 32834U, // UQADD_ZI_B |
| 18024 | 34881U, // UQADD_ZI_D |
| 18025 | 193U, // UQADD_ZI_H |
| 18026 | 36930U, // UQADD_ZI_S |
| 18027 | 33837153U, // UQADD_ZPmZ_B |
| 18028 | 67383393U, // UQADD_ZPmZ_D |
| 18029 | 101472369U, // UQADD_ZPmZ_H |
| 18030 | 134504545U, // UQADD_ZPmZ_S |
| 18031 | 20546U, // UQADD_ZZZ_B |
| 18032 | 12353U, // UQADD_ZZZ_D |
| 18033 | 113U, // UQADD_ZZZ_H |
| 18034 | 24642U, // UQADD_ZZZ_S |
| 18035 | 16448U, // UQADDv16i8 |
| 18036 | 6208U, // UQADDv1i16 |
| 18037 | 6208U, // UQADDv1i32 |
| 18038 | 6208U, // UQADDv1i64 |
| 18039 | 6208U, // UQADDv1i8 |
| 18040 | 16448U, // UQADDv2i32 |
| 18041 | 16448U, // UQADDv2i64 |
| 18042 | 16448U, // UQADDv4i16 |
| 18043 | 16448U, // UQADDv4i32 |
| 18044 | 16448U, // UQADDv8i16 |
| 18045 | 16448U, // UQADDv8i8 |
| 18046 | 0U, // UQCVTN_Z2Z_StoH |
| 18047 | 0U, // UQCVTN_Z4Z_DtoH |
| 18048 | 5U, // UQCVTN_Z4Z_StoB |
| 18049 | 0U, // UQCVT_Z2Z_StoH |
| 18050 | 0U, // UQCVT_Z4Z_DtoH |
| 18051 | 5U, // UQCVT_Z4Z_StoB |
| 18052 | 4U, // UQDECB_WPiI |
| 18053 | 4U, // UQDECB_XPiI |
| 18054 | 4U, // UQDECD_WPiI |
| 18055 | 4U, // UQDECD_XPiI |
| 18056 | 4U, // UQDECD_ZPiI |
| 18057 | 4U, // UQDECH_WPiI |
| 18058 | 4U, // UQDECH_XPiI |
| 18059 | 0U, // UQDECH_ZPiI |
| 18060 | 2U, // UQDECP_WP_B |
| 18061 | 1U, // UQDECP_WP_D |
| 18062 | 0U, // UQDECP_WP_H |
| 18063 | 2U, // UQDECP_WP_S |
| 18064 | 2U, // UQDECP_XP_B |
| 18065 | 1U, // UQDECP_XP_D |
| 18066 | 0U, // UQDECP_XP_H |
| 18067 | 2U, // UQDECP_XP_S |
| 18068 | 0U, // UQDECP_ZP_D |
| 18069 | 0U, // UQDECP_ZP_H |
| 18070 | 0U, // UQDECP_ZP_S |
| 18071 | 4U, // UQDECW_WPiI |
| 18072 | 4U, // UQDECW_XPiI |
| 18073 | 4U, // UQDECW_ZPiI |
| 18074 | 4U, // UQINCB_WPiI |
| 18075 | 4U, // UQINCB_XPiI |
| 18076 | 4U, // UQINCD_WPiI |
| 18077 | 4U, // UQINCD_XPiI |
| 18078 | 4U, // UQINCD_ZPiI |
| 18079 | 4U, // UQINCH_WPiI |
| 18080 | 4U, // UQINCH_XPiI |
| 18081 | 0U, // UQINCH_ZPiI |
| 18082 | 2U, // UQINCP_WP_B |
| 18083 | 1U, // UQINCP_WP_D |
| 18084 | 0U, // UQINCP_WP_H |
| 18085 | 2U, // UQINCP_WP_S |
| 18086 | 2U, // UQINCP_XP_B |
| 18087 | 1U, // UQINCP_XP_D |
| 18088 | 0U, // UQINCP_XP_H |
| 18089 | 2U, // UQINCP_XP_S |
| 18090 | 0U, // UQINCP_ZP_D |
| 18091 | 0U, // UQINCP_ZP_H |
| 18092 | 0U, // UQINCP_ZP_S |
| 18093 | 4U, // UQINCW_WPiI |
| 18094 | 4U, // UQINCW_XPiI |
| 18095 | 4U, // UQINCW_ZPiI |
| 18096 | 33837153U, // UQRSHLR_ZPmZ_B |
| 18097 | 67383393U, // UQRSHLR_ZPmZ_D |
| 18098 | 101472369U, // UQRSHLR_ZPmZ_H |
| 18099 | 134504545U, // UQRSHLR_ZPmZ_S |
| 18100 | 33837153U, // UQRSHL_ZPmZ_B |
| 18101 | 67383393U, // UQRSHL_ZPmZ_D |
| 18102 | 101472369U, // UQRSHL_ZPmZ_H |
| 18103 | 134504545U, // UQRSHL_ZPmZ_S |
| 18104 | 16448U, // UQRSHLv16i8 |
| 18105 | 6208U, // UQRSHLv1i16 |
| 18106 | 6208U, // UQRSHLv1i32 |
| 18107 | 6208U, // UQRSHLv1i64 |
| 18108 | 6208U, // UQRSHLv1i8 |
| 18109 | 16448U, // UQRSHLv2i32 |
| 18110 | 16448U, // UQRSHLv2i64 |
| 18111 | 16448U, // UQRSHLv4i16 |
| 18112 | 16448U, // UQRSHLv4i32 |
| 18113 | 16448U, // UQRSHLv8i16 |
| 18114 | 16448U, // UQRSHLv8i8 |
| 18115 | 6208U, // UQRSHRNB_ZZI_B |
| 18116 | 225U, // UQRSHRNB_ZZI_H |
| 18117 | 6209U, // UQRSHRNB_ZZI_S |
| 18118 | 81985U, // UQRSHRNT_ZZI_B |
| 18119 | 417U, // UQRSHRNT_ZZI_H |
| 18120 | 81984U, // UQRSHRNT_ZZI_S |
| 18121 | 6213U, // UQRSHRN_VG4_Z4ZI_B |
| 18122 | 225U, // UQRSHRN_VG4_Z4ZI_H |
| 18123 | 225U, // UQRSHRN_Z2ZI_StoH |
| 18124 | 6208U, // UQRSHRNb |
| 18125 | 6208U, // UQRSHRNh |
| 18126 | 6208U, // UQRSHRNs |
| 18127 | 81985U, // UQRSHRNv16i8_shift |
| 18128 | 6208U, // UQRSHRNv2i32_shift |
| 18129 | 6208U, // UQRSHRNv4i16_shift |
| 18130 | 81985U, // UQRSHRNv4i32_shift |
| 18131 | 81985U, // UQRSHRNv8i16_shift |
| 18132 | 6208U, // UQRSHRNv8i8_shift |
| 18133 | 225U, // UQRSHR_VG2_Z2ZI_H |
| 18134 | 6213U, // UQRSHR_VG4_Z4ZI_B |
| 18135 | 225U, // UQRSHR_VG4_Z4ZI_H |
| 18136 | 33837153U, // UQSHLR_ZPmZ_B |
| 18137 | 67383393U, // UQSHLR_ZPmZ_D |
| 18138 | 101472369U, // UQSHLR_ZPmZ_H |
| 18139 | 134504545U, // UQSHLR_ZPmZ_S |
| 18140 | 282721U, // UQSHL_ZPmI_B |
| 18141 | 274529U, // UQSHL_ZPmI_D |
| 18142 | 103045233U, // UQSHL_ZPmI_H |
| 18143 | 286817U, // UQSHL_ZPmI_S |
| 18144 | 33837153U, // UQSHL_ZPmZ_B |
| 18145 | 67383393U, // UQSHL_ZPmZ_D |
| 18146 | 101472369U, // UQSHL_ZPmZ_H |
| 18147 | 134504545U, // UQSHL_ZPmZ_S |
| 18148 | 6208U, // UQSHLb |
| 18149 | 6208U, // UQSHLd |
| 18150 | 6208U, // UQSHLh |
| 18151 | 6208U, // UQSHLs |
| 18152 | 16448U, // UQSHLv16i8 |
| 18153 | 6208U, // UQSHLv16i8_shift |
| 18154 | 6208U, // UQSHLv1i16 |
| 18155 | 6208U, // UQSHLv1i32 |
| 18156 | 6208U, // UQSHLv1i64 |
| 18157 | 6208U, // UQSHLv1i8 |
| 18158 | 16448U, // UQSHLv2i32 |
| 18159 | 6208U, // UQSHLv2i32_shift |
| 18160 | 16448U, // UQSHLv2i64 |
| 18161 | 6208U, // UQSHLv2i64_shift |
| 18162 | 16448U, // UQSHLv4i16 |
| 18163 | 6208U, // UQSHLv4i16_shift |
| 18164 | 16448U, // UQSHLv4i32 |
| 18165 | 6208U, // UQSHLv4i32_shift |
| 18166 | 16448U, // UQSHLv8i16 |
| 18167 | 6208U, // UQSHLv8i16_shift |
| 18168 | 16448U, // UQSHLv8i8 |
| 18169 | 6208U, // UQSHLv8i8_shift |
| 18170 | 6208U, // UQSHRNB_ZZI_B |
| 18171 | 225U, // UQSHRNB_ZZI_H |
| 18172 | 6209U, // UQSHRNB_ZZI_S |
| 18173 | 81985U, // UQSHRNT_ZZI_B |
| 18174 | 417U, // UQSHRNT_ZZI_H |
| 18175 | 81984U, // UQSHRNT_ZZI_S |
| 18176 | 6208U, // UQSHRNb |
| 18177 | 6208U, // UQSHRNh |
| 18178 | 6208U, // UQSHRNs |
| 18179 | 81985U, // UQSHRNv16i8_shift |
| 18180 | 6208U, // UQSHRNv2i32_shift |
| 18181 | 6208U, // UQSHRNv4i16_shift |
| 18182 | 81985U, // UQSHRNv4i32_shift |
| 18183 | 81985U, // UQSHRNv8i16_shift |
| 18184 | 6208U, // UQSHRNv8i8_shift |
| 18185 | 33837153U, // UQSUBR_ZPmZ_B |
| 18186 | 67383393U, // UQSUBR_ZPmZ_D |
| 18187 | 101472369U, // UQSUBR_ZPmZ_H |
| 18188 | 134504545U, // UQSUBR_ZPmZ_S |
| 18189 | 32834U, // UQSUB_ZI_B |
| 18190 | 34881U, // UQSUB_ZI_D |
| 18191 | 193U, // UQSUB_ZI_H |
| 18192 | 36930U, // UQSUB_ZI_S |
| 18193 | 33837153U, // UQSUB_ZPmZ_B |
| 18194 | 67383393U, // UQSUB_ZPmZ_D |
| 18195 | 101472369U, // UQSUB_ZPmZ_H |
| 18196 | 134504545U, // UQSUB_ZPmZ_S |
| 18197 | 20546U, // UQSUB_ZZZ_B |
| 18198 | 12353U, // UQSUB_ZZZ_D |
| 18199 | 113U, // UQSUB_ZZZ_H |
| 18200 | 24642U, // UQSUB_ZZZ_S |
| 18201 | 16448U, // UQSUBv16i8 |
| 18202 | 6208U, // UQSUBv1i16 |
| 18203 | 6208U, // UQSUBv1i32 |
| 18204 | 6208U, // UQSUBv1i64 |
| 18205 | 6208U, // UQSUBv1i8 |
| 18206 | 16448U, // UQSUBv2i32 |
| 18207 | 16448U, // UQSUBv2i64 |
| 18208 | 16448U, // UQSUBv4i16 |
| 18209 | 16448U, // UQSUBv4i32 |
| 18210 | 16448U, // UQSUBv8i16 |
| 18211 | 16448U, // UQSUBv8i8 |
| 18212 | 0U, // UQXTNB_ZZ_B |
| 18213 | 0U, // UQXTNB_ZZ_H |
| 18214 | 1U, // UQXTNB_ZZ_S |
| 18215 | 1U, // UQXTNT_ZZ_B |
| 18216 | 0U, // UQXTNT_ZZ_H |
| 18217 | 0U, // UQXTNT_ZZ_S |
| 18218 | 1U, // UQXTNv16i8 |
| 18219 | 0U, // UQXTNv1i16 |
| 18220 | 0U, // UQXTNv1i32 |
| 18221 | 0U, // UQXTNv1i8 |
| 18222 | 0U, // UQXTNv2i32 |
| 18223 | 0U, // UQXTNv4i16 |
| 18224 | 1U, // UQXTNv4i32 |
| 18225 | 1U, // UQXTNv8i16 |
| 18226 | 0U, // UQXTNv8i8 |
| 18227 | 48U, // URECPE_ZPmZ_S |
| 18228 | 0U, // URECPEv2i32 |
| 18229 | 0U, // URECPEv4i32 |
| 18230 | 33837153U, // URHADD_ZPmZ_B |
| 18231 | 67383393U, // URHADD_ZPmZ_D |
| 18232 | 101472369U, // URHADD_ZPmZ_H |
| 18233 | 134504545U, // URHADD_ZPmZ_S |
| 18234 | 16448U, // URHADDv16i8 |
| 18235 | 16448U, // URHADDv2i32 |
| 18236 | 16448U, // URHADDv4i16 |
| 18237 | 16448U, // URHADDv4i32 |
| 18238 | 16448U, // URHADDv8i16 |
| 18239 | 16448U, // URHADDv8i8 |
| 18240 | 33837153U, // URSHLR_ZPmZ_B |
| 18241 | 67383393U, // URSHLR_ZPmZ_D |
| 18242 | 101472369U, // URSHLR_ZPmZ_H |
| 18243 | 134504545U, // URSHLR_ZPmZ_S |
| 18244 | 1457U, // URSHL_VG2_2Z2Z_B |
| 18245 | 513U, // URSHL_VG2_2Z2Z_D |
| 18246 | 273U, // URSHL_VG2_2Z2Z_H |
| 18247 | 529U, // URSHL_VG2_2Z2Z_S |
| 18248 | 129U, // URSHL_VG2_2ZZ_B |
| 18249 | 145U, // URSHL_VG2_2ZZ_D |
| 18250 | 113U, // URSHL_VG2_2ZZ_H |
| 18251 | 81U, // URSHL_VG2_2ZZ_S |
| 18252 | 1457U, // URSHL_VG4_4Z4Z_B |
| 18253 | 513U, // URSHL_VG4_4Z4Z_D |
| 18254 | 273U, // URSHL_VG4_4Z4Z_H |
| 18255 | 529U, // URSHL_VG4_4Z4Z_S |
| 18256 | 129U, // URSHL_VG4_4ZZ_B |
| 18257 | 145U, // URSHL_VG4_4ZZ_D |
| 18258 | 113U, // URSHL_VG4_4ZZ_H |
| 18259 | 81U, // URSHL_VG4_4ZZ_S |
| 18260 | 33837153U, // URSHL_ZPmZ_B |
| 18261 | 67383393U, // URSHL_ZPmZ_D |
| 18262 | 101472369U, // URSHL_ZPmZ_H |
| 18263 | 134504545U, // URSHL_ZPmZ_S |
| 18264 | 16448U, // URSHLv16i8 |
| 18265 | 6208U, // URSHLv1i64 |
| 18266 | 16448U, // URSHLv2i32 |
| 18267 | 16448U, // URSHLv2i64 |
| 18268 | 16448U, // URSHLv4i16 |
| 18269 | 16448U, // URSHLv4i32 |
| 18270 | 16448U, // URSHLv8i16 |
| 18271 | 16448U, // URSHLv8i8 |
| 18272 | 282721U, // URSHR_ZPmI_B |
| 18273 | 274529U, // URSHR_ZPmI_D |
| 18274 | 103045233U, // URSHR_ZPmI_H |
| 18275 | 286817U, // URSHR_ZPmI_S |
| 18276 | 6208U, // URSHRd |
| 18277 | 6208U, // URSHRv16i8_shift |
| 18278 | 6208U, // URSHRv2i32_shift |
| 18279 | 6208U, // URSHRv2i64_shift |
| 18280 | 6208U, // URSHRv4i16_shift |
| 18281 | 6208U, // URSHRv4i32_shift |
| 18282 | 6208U, // URSHRv8i16_shift |
| 18283 | 6208U, // URSHRv8i8_shift |
| 18284 | 48U, // URSQRTE_ZPmZ_S |
| 18285 | 0U, // URSQRTEv2i32 |
| 18286 | 0U, // URSQRTEv4i32 |
| 18287 | 419U, // URSRA_ZZI_B |
| 18288 | 81984U, // URSRA_ZZI_D |
| 18289 | 417U, // URSRA_ZZI_H |
| 18290 | 81984U, // URSRA_ZZI_S |
| 18291 | 81986U, // URSRAd |
| 18292 | 81985U, // URSRAv16i8_shift |
| 18293 | 81985U, // URSRAv2i32_shift |
| 18294 | 81985U, // URSRAv2i64_shift |
| 18295 | 81985U, // URSRAv4i16_shift |
| 18296 | 81985U, // URSRAv4i32_shift |
| 18297 | 81985U, // URSRAv8i16_shift |
| 18298 | 81985U, // URSRAv8i8_shift |
| 18299 | 92865U, // USDOT_VG2_M2Z2Z_BToS |
| 18300 | 5599937U, // USDOT_VG2_M2ZZI_BToS |
| 18301 | 94913U, // USDOT_VG2_M2ZZ_BToS |
| 18302 | 92865U, // USDOT_VG4_M4Z4Z_BToS |
| 18303 | 5599937U, // USDOT_VG4_M4ZZI_BToS |
| 18304 | 94913U, // USDOT_VG4_M4ZZ_BToS |
| 18305 | 19U, // USDOT_ZZZ |
| 18306 | 77843U, // USDOT_ZZZI |
| 18307 | 103565377U, // USDOTlanev16i8 |
| 18308 | 103565377U, // USDOTlanev8i8 |
| 18309 | 0U, // USDOTv16i8 |
| 18310 | 0U, // USDOTv8i8 |
| 18311 | 6210U, // USHLLB_ZZI_D |
| 18312 | 225U, // USHLLB_ZZI_H |
| 18313 | 6208U, // USHLLB_ZZI_S |
| 18314 | 6210U, // USHLLT_ZZI_D |
| 18315 | 225U, // USHLLT_ZZI_H |
| 18316 | 6208U, // USHLLT_ZZI_S |
| 18317 | 6208U, // USHLLv16i8_shift |
| 18318 | 6208U, // USHLLv2i32_shift |
| 18319 | 6208U, // USHLLv4i16_shift |
| 18320 | 6208U, // USHLLv4i32_shift |
| 18321 | 6208U, // USHLLv8i16_shift |
| 18322 | 6208U, // USHLLv8i8_shift |
| 18323 | 16448U, // USHLv16i8 |
| 18324 | 6208U, // USHLv1i64 |
| 18325 | 16448U, // USHLv2i32 |
| 18326 | 16448U, // USHLv2i64 |
| 18327 | 16448U, // USHLv4i16 |
| 18328 | 16448U, // USHLv4i32 |
| 18329 | 16448U, // USHLv8i16 |
| 18330 | 16448U, // USHLv8i8 |
| 18331 | 6208U, // USHRd |
| 18332 | 6208U, // USHRv16i8_shift |
| 18333 | 6208U, // USHRv2i32_shift |
| 18334 | 6208U, // USHRv2i64_shift |
| 18335 | 6208U, // USHRv4i16_shift |
| 18336 | 6208U, // USHRv4i32_shift |
| 18337 | 6208U, // USHRv8i16_shift |
| 18338 | 6208U, // USHRv8i8_shift |
| 18339 | 76498U, // USMLALL_MZZI_BtoS |
| 18340 | 722U, // USMLALL_MZZ_BtoS |
| 18341 | 92865U, // USMLALL_VG2_M2Z2Z_BtoS |
| 18342 | 5599937U, // USMLALL_VG2_M2ZZI_BtoS |
| 18343 | 94917U, // USMLALL_VG2_M2ZZ_BtoS |
| 18344 | 92865U, // USMLALL_VG4_M4Z4Z_BtoS |
| 18345 | 5599937U, // USMLALL_VG4_M4ZZI_BtoS |
| 18346 | 94918U, // USMLALL_VG4_M4ZZ_BtoS |
| 18347 | 0U, // USMMLA |
| 18348 | 19U, // USMMLA_ZZZ |
| 18349 | 0U, // USMOPA_MPPZZ_D |
| 18350 | 0U, // USMOPA_MPPZZ_S |
| 18351 | 0U, // USMOPS_MPPZZ_D |
| 18352 | 0U, // USMOPS_MPPZZ_S |
| 18353 | 33837153U, // USQADD_ZPmZ_B |
| 18354 | 67383393U, // USQADD_ZPmZ_D |
| 18355 | 101472369U, // USQADD_ZPmZ_H |
| 18356 | 134504545U, // USQADD_ZPmZ_S |
| 18357 | 1U, // USQADDv16i8 |
| 18358 | 2U, // USQADDv1i16 |
| 18359 | 2U, // USQADDv1i32 |
| 18360 | 2U, // USQADDv1i64 |
| 18361 | 2U, // USQADDv1i8 |
| 18362 | 1U, // USQADDv2i32 |
| 18363 | 1U, // USQADDv2i64 |
| 18364 | 1U, // USQADDv4i16 |
| 18365 | 1U, // USQADDv4i32 |
| 18366 | 1U, // USQADDv8i16 |
| 18367 | 1U, // USQADDv8i8 |
| 18368 | 419U, // USRA_ZZI_B |
| 18369 | 81984U, // USRA_ZZI_D |
| 18370 | 417U, // USRA_ZZI_H |
| 18371 | 81984U, // USRA_ZZI_S |
| 18372 | 81986U, // USRAd |
| 18373 | 81985U, // USRAv16i8_shift |
| 18374 | 81985U, // USRAv2i32_shift |
| 18375 | 81985U, // USRAv2i64_shift |
| 18376 | 81985U, // USRAv4i16_shift |
| 18377 | 81985U, // USRAv4i32_shift |
| 18378 | 81985U, // USRAv8i16_shift |
| 18379 | 81985U, // USRAv8i8_shift |
| 18380 | 24642U, // USUBLB_ZZZ_D |
| 18381 | 129U, // USUBLB_ZZZ_H |
| 18382 | 10304U, // USUBLB_ZZZ_S |
| 18383 | 24642U, // USUBLT_ZZZ_D |
| 18384 | 129U, // USUBLT_ZZZ_H |
| 18385 | 10304U, // USUBLT_ZZZ_S |
| 18386 | 16448U, // USUBLv16i8_v8i16 |
| 18387 | 16448U, // USUBLv2i32_v2i64 |
| 18388 | 16448U, // USUBLv4i16_v4i32 |
| 18389 | 16448U, // USUBLv4i32_v2i64 |
| 18390 | 16448U, // USUBLv8i16_v4i32 |
| 18391 | 16448U, // USUBLv8i8_v8i16 |
| 18392 | 24641U, // USUBWB_ZZZ_D |
| 18393 | 129U, // USUBWB_ZZZ_H |
| 18394 | 10306U, // USUBWB_ZZZ_S |
| 18395 | 24641U, // USUBWT_ZZZ_D |
| 18396 | 129U, // USUBWT_ZZZ_H |
| 18397 | 10306U, // USUBWT_ZZZ_S |
| 18398 | 16448U, // USUBWv16i8_v8i16 |
| 18399 | 16448U, // USUBWv2i32_v2i64 |
| 18400 | 16448U, // USUBWv4i16_v4i32 |
| 18401 | 16448U, // USUBWv4i32_v2i64 |
| 18402 | 16448U, // USUBWv8i16_v4i32 |
| 18403 | 16448U, // USUBWv8i8_v8i16 |
| 18404 | 5599937U, // USVDOT_VG4_M4ZZI_BToS |
| 18405 | 2U, // UUNPKHI_ZZ_D |
| 18406 | 0U, // UUNPKHI_ZZ_H |
| 18407 | 0U, // UUNPKHI_ZZ_S |
| 18408 | 2U, // UUNPKLO_ZZ_D |
| 18409 | 0U, // UUNPKLO_ZZ_H |
| 18410 | 0U, // UUNPKLO_ZZ_S |
| 18411 | 0U, // UUNPK_VG2_2ZZ_D |
| 18412 | 0U, // UUNPK_VG2_2ZZ_H |
| 18413 | 0U, // UUNPK_VG2_2ZZ_S |
| 18414 | 0U, // UUNPK_VG4_4Z2Z_D |
| 18415 | 0U, // UUNPK_VG4_4Z2Z_H |
| 18416 | 0U, // UUNPK_VG4_4Z2Z_S |
| 18417 | 204757233U, // UVDOT_VG2_M2ZZI_HtoS |
| 18418 | 5599937U, // UVDOT_VG4_M4ZZI_BtoS |
| 18419 | 204757233U, // UVDOT_VG4_M4ZZI_HtoD |
| 18420 | 32U, // UXTB_ZPmZ_D |
| 18421 | 0U, // UXTB_ZPmZ_H |
| 18422 | 48U, // UXTB_ZPmZ_S |
| 18423 | 32U, // UXTH_ZPmZ_D |
| 18424 | 48U, // UXTH_ZPmZ_S |
| 18425 | 32U, // UXTW_ZPmZ_D |
| 18426 | 20546U, // UZP1_PPP_B |
| 18427 | 12353U, // UZP1_PPP_D |
| 18428 | 113U, // UZP1_PPP_H |
| 18429 | 24642U, // UZP1_PPP_S |
| 18430 | 20546U, // UZP1_ZZZ_B |
| 18431 | 12353U, // UZP1_ZZZ_D |
| 18432 | 113U, // UZP1_ZZZ_H |
| 18433 | 1633U, // UZP1_ZZZ_Q |
| 18434 | 24642U, // UZP1_ZZZ_S |
| 18435 | 16448U, // UZP1v16i8 |
| 18436 | 16448U, // UZP1v2i32 |
| 18437 | 16448U, // UZP1v2i64 |
| 18438 | 16448U, // UZP1v4i16 |
| 18439 | 16448U, // UZP1v4i32 |
| 18440 | 16448U, // UZP1v8i16 |
| 18441 | 16448U, // UZP1v8i8 |
| 18442 | 20546U, // UZP2_PPP_B |
| 18443 | 12353U, // UZP2_PPP_D |
| 18444 | 113U, // UZP2_PPP_H |
| 18445 | 24642U, // UZP2_PPP_S |
| 18446 | 20546U, // UZP2_ZZZ_B |
| 18447 | 12353U, // UZP2_ZZZ_D |
| 18448 | 113U, // UZP2_ZZZ_H |
| 18449 | 1633U, // UZP2_ZZZ_Q |
| 18450 | 24642U, // UZP2_ZZZ_S |
| 18451 | 16448U, // UZP2v16i8 |
| 18452 | 16448U, // UZP2v2i32 |
| 18453 | 16448U, // UZP2v2i64 |
| 18454 | 16448U, // UZP2v4i16 |
| 18455 | 16448U, // UZP2v4i32 |
| 18456 | 16448U, // UZP2v8i16 |
| 18457 | 16448U, // UZP2v8i8 |
| 18458 | 20546U, // UZPQ1_ZZZ_B |
| 18459 | 12353U, // UZPQ1_ZZZ_D |
| 18460 | 113U, // UZPQ1_ZZZ_H |
| 18461 | 24642U, // UZPQ1_ZZZ_S |
| 18462 | 20546U, // UZPQ2_ZZZ_B |
| 18463 | 12353U, // UZPQ2_ZZZ_D |
| 18464 | 113U, // UZPQ2_ZZZ_H |
| 18465 | 24642U, // UZPQ2_ZZZ_S |
| 18466 | 129U, // UZP_VG2_2ZZZ_B |
| 18467 | 0U, // UZP_VG2_2ZZZ_D |
| 18468 | 113U, // UZP_VG2_2ZZZ_H |
| 18469 | 1633U, // UZP_VG2_2ZZZ_Q |
| 18470 | 81U, // UZP_VG2_2ZZZ_S |
| 18471 | 0U, // UZP_VG4_4Z4Z_B |
| 18472 | 0U, // UZP_VG4_4Z4Z_D |
| 18473 | 0U, // UZP_VG4_4Z4Z_H |
| 18474 | 0U, // UZP_VG4_4Z4Z_Q |
| 18475 | 0U, // UZP_VG4_4Z4Z_S |
| 18476 | 0U, // WFET |
| 18477 | 0U, // WFIT |
| 18478 | 225U, // WHILEGE_2PXX_B |
| 18479 | 225U, // WHILEGE_2PXX_D |
| 18480 | 225U, // WHILEGE_2PXX_H |
| 18481 | 225U, // WHILEGE_2PXX_S |
| 18482 | 1376000064U, // WHILEGE_CXX_B |
| 18483 | 1376000064U, // WHILEGE_CXX_D |
| 18484 | 1376000064U, // WHILEGE_CXX_H |
| 18485 | 1376000064U, // WHILEGE_CXX_S |
| 18486 | 6208U, // WHILEGE_PWW_B |
| 18487 | 6208U, // WHILEGE_PWW_D |
| 18488 | 225U, // WHILEGE_PWW_H |
| 18489 | 6208U, // WHILEGE_PWW_S |
| 18490 | 6208U, // WHILEGE_PXX_B |
| 18491 | 6208U, // WHILEGE_PXX_D |
| 18492 | 225U, // WHILEGE_PXX_H |
| 18493 | 6208U, // WHILEGE_PXX_S |
| 18494 | 225U, // WHILEGT_2PXX_B |
| 18495 | 225U, // WHILEGT_2PXX_D |
| 18496 | 225U, // WHILEGT_2PXX_H |
| 18497 | 225U, // WHILEGT_2PXX_S |
| 18498 | 1376000064U, // WHILEGT_CXX_B |
| 18499 | 1376000064U, // WHILEGT_CXX_D |
| 18500 | 1376000064U, // WHILEGT_CXX_H |
| 18501 | 1376000064U, // WHILEGT_CXX_S |
| 18502 | 6208U, // WHILEGT_PWW_B |
| 18503 | 6208U, // WHILEGT_PWW_D |
| 18504 | 225U, // WHILEGT_PWW_H |
| 18505 | 6208U, // WHILEGT_PWW_S |
| 18506 | 6208U, // WHILEGT_PXX_B |
| 18507 | 6208U, // WHILEGT_PXX_D |
| 18508 | 225U, // WHILEGT_PXX_H |
| 18509 | 6208U, // WHILEGT_PXX_S |
| 18510 | 225U, // WHILEHI_2PXX_B |
| 18511 | 225U, // WHILEHI_2PXX_D |
| 18512 | 225U, // WHILEHI_2PXX_H |
| 18513 | 225U, // WHILEHI_2PXX_S |
| 18514 | 1376000064U, // WHILEHI_CXX_B |
| 18515 | 1376000064U, // WHILEHI_CXX_D |
| 18516 | 1376000064U, // WHILEHI_CXX_H |
| 18517 | 1376000064U, // WHILEHI_CXX_S |
| 18518 | 6208U, // WHILEHI_PWW_B |
| 18519 | 6208U, // WHILEHI_PWW_D |
| 18520 | 225U, // WHILEHI_PWW_H |
| 18521 | 6208U, // WHILEHI_PWW_S |
| 18522 | 6208U, // WHILEHI_PXX_B |
| 18523 | 6208U, // WHILEHI_PXX_D |
| 18524 | 225U, // WHILEHI_PXX_H |
| 18525 | 6208U, // WHILEHI_PXX_S |
| 18526 | 225U, // WHILEHS_2PXX_B |
| 18527 | 225U, // WHILEHS_2PXX_D |
| 18528 | 225U, // WHILEHS_2PXX_H |
| 18529 | 225U, // WHILEHS_2PXX_S |
| 18530 | 1376000064U, // WHILEHS_CXX_B |
| 18531 | 1376000064U, // WHILEHS_CXX_D |
| 18532 | 1376000064U, // WHILEHS_CXX_H |
| 18533 | 1376000064U, // WHILEHS_CXX_S |
| 18534 | 6208U, // WHILEHS_PWW_B |
| 18535 | 6208U, // WHILEHS_PWW_D |
| 18536 | 225U, // WHILEHS_PWW_H |
| 18537 | 6208U, // WHILEHS_PWW_S |
| 18538 | 6208U, // WHILEHS_PXX_B |
| 18539 | 6208U, // WHILEHS_PXX_D |
| 18540 | 225U, // WHILEHS_PXX_H |
| 18541 | 6208U, // WHILEHS_PXX_S |
| 18542 | 225U, // WHILELE_2PXX_B |
| 18543 | 225U, // WHILELE_2PXX_D |
| 18544 | 225U, // WHILELE_2PXX_H |
| 18545 | 225U, // WHILELE_2PXX_S |
| 18546 | 1376000064U, // WHILELE_CXX_B |
| 18547 | 1376000064U, // WHILELE_CXX_D |
| 18548 | 1376000064U, // WHILELE_CXX_H |
| 18549 | 1376000064U, // WHILELE_CXX_S |
| 18550 | 6208U, // WHILELE_PWW_B |
| 18551 | 6208U, // WHILELE_PWW_D |
| 18552 | 225U, // WHILELE_PWW_H |
| 18553 | 6208U, // WHILELE_PWW_S |
| 18554 | 6208U, // WHILELE_PXX_B |
| 18555 | 6208U, // WHILELE_PXX_D |
| 18556 | 225U, // WHILELE_PXX_H |
| 18557 | 6208U, // WHILELE_PXX_S |
| 18558 | 225U, // WHILELO_2PXX_B |
| 18559 | 225U, // WHILELO_2PXX_D |
| 18560 | 225U, // WHILELO_2PXX_H |
| 18561 | 225U, // WHILELO_2PXX_S |
| 18562 | 1376000064U, // WHILELO_CXX_B |
| 18563 | 1376000064U, // WHILELO_CXX_D |
| 18564 | 1376000064U, // WHILELO_CXX_H |
| 18565 | 1376000064U, // WHILELO_CXX_S |
| 18566 | 6208U, // WHILELO_PWW_B |
| 18567 | 6208U, // WHILELO_PWW_D |
| 18568 | 225U, // WHILELO_PWW_H |
| 18569 | 6208U, // WHILELO_PWW_S |
| 18570 | 6208U, // WHILELO_PXX_B |
| 18571 | 6208U, // WHILELO_PXX_D |
| 18572 | 225U, // WHILELO_PXX_H |
| 18573 | 6208U, // WHILELO_PXX_S |
| 18574 | 225U, // WHILELS_2PXX_B |
| 18575 | 225U, // WHILELS_2PXX_D |
| 18576 | 225U, // WHILELS_2PXX_H |
| 18577 | 225U, // WHILELS_2PXX_S |
| 18578 | 1376000064U, // WHILELS_CXX_B |
| 18579 | 1376000064U, // WHILELS_CXX_D |
| 18580 | 1376000064U, // WHILELS_CXX_H |
| 18581 | 1376000064U, // WHILELS_CXX_S |
| 18582 | 6208U, // WHILELS_PWW_B |
| 18583 | 6208U, // WHILELS_PWW_D |
| 18584 | 225U, // WHILELS_PWW_H |
| 18585 | 6208U, // WHILELS_PWW_S |
| 18586 | 6208U, // WHILELS_PXX_B |
| 18587 | 6208U, // WHILELS_PXX_D |
| 18588 | 225U, // WHILELS_PXX_H |
| 18589 | 6208U, // WHILELS_PXX_S |
| 18590 | 225U, // WHILELT_2PXX_B |
| 18591 | 225U, // WHILELT_2PXX_D |
| 18592 | 225U, // WHILELT_2PXX_H |
| 18593 | 225U, // WHILELT_2PXX_S |
| 18594 | 1376000064U, // WHILELT_CXX_B |
| 18595 | 1376000064U, // WHILELT_CXX_D |
| 18596 | 1376000064U, // WHILELT_CXX_H |
| 18597 | 1376000064U, // WHILELT_CXX_S |
| 18598 | 6208U, // WHILELT_PWW_B |
| 18599 | 6208U, // WHILELT_PWW_D |
| 18600 | 225U, // WHILELT_PWW_H |
| 18601 | 6208U, // WHILELT_PWW_S |
| 18602 | 6208U, // WHILELT_PXX_B |
| 18603 | 6208U, // WHILELT_PXX_D |
| 18604 | 225U, // WHILELT_PXX_H |
| 18605 | 6208U, // WHILELT_PXX_S |
| 18606 | 6208U, // WHILERW_PXX_B |
| 18607 | 6208U, // WHILERW_PXX_D |
| 18608 | 225U, // WHILERW_PXX_H |
| 18609 | 6208U, // WHILERW_PXX_S |
| 18610 | 6208U, // WHILEWR_PXX_B |
| 18611 | 6208U, // WHILEWR_PXX_D |
| 18612 | 225U, // WHILEWR_PXX_H |
| 18613 | 6208U, // WHILEWR_PXX_S |
| 18614 | 0U, // WRFFR |
| 18615 | 0U, // XAFLAG |
| 18616 | 278592U, // XAR |
| 18617 | 282690U, // XAR_ZZZI_B |
| 18618 | 274497U, // XAR_ZZZI_D |
| 18619 | 103045233U, // XAR_ZZZI_H |
| 18620 | 286786U, // XAR_ZZZI_S |
| 18621 | 0U, // XPACD |
| 18622 | 0U, // XPACI |
| 18623 | 0U, // XPACLRI |
| 18624 | 1U, // XTNv16i8 |
| 18625 | 0U, // XTNv2i32 |
| 18626 | 0U, // XTNv4i16 |
| 18627 | 1U, // XTNv4i32 |
| 18628 | 1U, // XTNv8i16 |
| 18629 | 0U, // XTNv8i8 |
| 18630 | 0U, // ZERO_M |
| 18631 | 11U, // ZERO_MXI_2Z |
| 18632 | 11U, // ZERO_MXI_4Z |
| 18633 | 7U, // ZERO_MXI_VG2_2Z |
| 18634 | 7U, // ZERO_MXI_VG2_4Z |
| 18635 | 7U, // ZERO_MXI_VG2_Z |
| 18636 | 7U, // ZERO_MXI_VG4_2Z |
| 18637 | 7U, // ZERO_MXI_VG4_4Z |
| 18638 | 7U, // ZERO_MXI_VG4_Z |
| 18639 | 0U, // ZERO_T |
| 18640 | 20546U, // ZIP1_PPP_B |
| 18641 | 12353U, // ZIP1_PPP_D |
| 18642 | 113U, // ZIP1_PPP_H |
| 18643 | 24642U, // ZIP1_PPP_S |
| 18644 | 20546U, // ZIP1_ZZZ_B |
| 18645 | 12353U, // ZIP1_ZZZ_D |
| 18646 | 113U, // ZIP1_ZZZ_H |
| 18647 | 1633U, // ZIP1_ZZZ_Q |
| 18648 | 24642U, // ZIP1_ZZZ_S |
| 18649 | 16448U, // ZIP1v16i8 |
| 18650 | 16448U, // ZIP1v2i32 |
| 18651 | 16448U, // ZIP1v2i64 |
| 18652 | 16448U, // ZIP1v4i16 |
| 18653 | 16448U, // ZIP1v4i32 |
| 18654 | 16448U, // ZIP1v8i16 |
| 18655 | 16448U, // ZIP1v8i8 |
| 18656 | 20546U, // ZIP2_PPP_B |
| 18657 | 12353U, // ZIP2_PPP_D |
| 18658 | 113U, // ZIP2_PPP_H |
| 18659 | 24642U, // ZIP2_PPP_S |
| 18660 | 20546U, // ZIP2_ZZZ_B |
| 18661 | 12353U, // ZIP2_ZZZ_D |
| 18662 | 113U, // ZIP2_ZZZ_H |
| 18663 | 1633U, // ZIP2_ZZZ_Q |
| 18664 | 24642U, // ZIP2_ZZZ_S |
| 18665 | 16448U, // ZIP2v16i8 |
| 18666 | 16448U, // ZIP2v2i32 |
| 18667 | 16448U, // ZIP2v2i64 |
| 18668 | 16448U, // ZIP2v4i16 |
| 18669 | 16448U, // ZIP2v4i32 |
| 18670 | 16448U, // ZIP2v8i16 |
| 18671 | 16448U, // ZIP2v8i8 |
| 18672 | 20546U, // ZIPQ1_ZZZ_B |
| 18673 | 12353U, // ZIPQ1_ZZZ_D |
| 18674 | 113U, // ZIPQ1_ZZZ_H |
| 18675 | 24642U, // ZIPQ1_ZZZ_S |
| 18676 | 20546U, // ZIPQ2_ZZZ_B |
| 18677 | 12353U, // ZIPQ2_ZZZ_D |
| 18678 | 113U, // ZIPQ2_ZZZ_H |
| 18679 | 24642U, // ZIPQ2_ZZZ_S |
| 18680 | 129U, // ZIP_VG2_2ZZZ_B |
| 18681 | 0U, // ZIP_VG2_2ZZZ_D |
| 18682 | 113U, // ZIP_VG2_2ZZZ_H |
| 18683 | 1633U, // ZIP_VG2_2ZZZ_Q |
| 18684 | 81U, // ZIP_VG2_2ZZZ_S |
| 18685 | 0U, // ZIP_VG4_4Z4Z_B |
| 18686 | 0U, // ZIP_VG4_4Z4Z_D |
| 18687 | 0U, // ZIP_VG4_4Z4Z_H |
| 18688 | 0U, // ZIP_VG4_4Z4Z_Q |
| 18689 | 0U, // ZIP_VG4_4Z4Z_S |
| 18690 | }; |
| 18691 | |
| 18692 | // Emit the opcode for the instruction. |
| 18693 | uint64_t Bits = 0; |
| 18694 | Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| 18695 | Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| 18696 | if (Bits == 0) |
| 18697 | return {nullptr, Bits}; |
| 18698 | return {AsmStrs+(Bits & 32767)-1, Bits}; |
| 18699 | |
| 18700 | } |
| 18701 | /// printInstruction - This method is automatically generated by tablegen |
| 18702 | /// from the instruction set description. |
| 18703 | LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| 18704 | void AArch64AppleInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| 18705 | O << "\t"; |
| 18706 | |
| 18707 | auto MnemonicInfo = getMnemonic(MI); |
| 18708 | |
| 18709 | O << MnemonicInfo.first; |
| 18710 | |
| 18711 | uint64_t Bits = MnemonicInfo.second; |
| 18712 | assert(Bits != 0 && "Cannot print this instruction."); |
| 18713 | |
| 18714 | // Fragment 0 encoded into 7 bits for 78 unique commands. |
| 18715 | switch ((Bits >> 15) & 127) { |
| 18716 | default: llvm_unreachable("Invalid command number."); |
| 18717 | case 0: |
| 18718 | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| 18719 | return; |
| 18720 | break; |
| 18721 | case 1: |
| 18722 | // TLSDESCCALL, ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADD... |
| 18723 | printOperand(MI, OpNo: 0, STI, O); |
| 18724 | break; |
| 18725 | case 2: |
| 18726 | // ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm... |
| 18727 | printSVERegOp<'b'>(MI, OpNum: 0, STI, O); |
| 18728 | break; |
| 18729 | case 3: |
| 18730 | // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_... |
| 18731 | printSVERegOp<'d'>(MI, OpNum: 0, STI, O); |
| 18732 | break; |
| 18733 | case 4: |
| 18734 | // ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm... |
| 18735 | printSVERegOp<'h'>(MI, OpNum: 0, STI, O); |
| 18736 | O << ", "; |
| 18737 | break; |
| 18738 | case 5: |
| 18739 | // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP... |
| 18740 | printSVERegOp<'s'>(MI, OpNum: 0, STI, O); |
| 18741 | break; |
| 18742 | case 6: |
| 18743 | // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| 18744 | printVRegOperand(MI, OpNo: 0, STI, O); |
| 18745 | break; |
| 18746 | case 7: |
| 18747 | // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOPA_MPPZZ, ... |
| 18748 | printMatrixTile(MI, OpNum: 0, STI, O); |
| 18749 | O << ", "; |
| 18750 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 18751 | O << "/m, "; |
| 18752 | printSVERegOp<>(MI, OpNum: 3, STI, O); |
| 18753 | O << "/m, "; |
| 18754 | break; |
| 18755 | case 8: |
| 18756 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| 18757 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 18758 | break; |
| 18759 | case 9: |
| 18760 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, LD1B, LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1... |
| 18761 | printTypedVectorList<0,'b'>(MI, OpNum: 0, STI, O); |
| 18762 | O << ", "; |
| 18763 | break; |
| 18764 | case 10: |
| 18765 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D... |
| 18766 | printTypedVectorList<0,'d'>(MI, OpNum: 0, STI, O); |
| 18767 | O << ", "; |
| 18768 | break; |
| 18769 | case 11: |
| 18770 | // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BF1CVTL_2ZZ_BtoH_NAME, BF1CVT_2ZZ_BtoH_N... |
| 18771 | printTypedVectorList<0,'h'>(MI, OpNum: 0, STI, O); |
| 18772 | O << ", "; |
| 18773 | break; |
| 18774 | case 12: |
| 18775 | // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S... |
| 18776 | printTypedVectorList<0,'s'>(MI, OpNum: 0, STI, O); |
| 18777 | O << ", "; |
| 18778 | break; |
| 18779 | case 13: |
| 18780 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| 18781 | printMatrix<64>(MI, OpNum: 0, STI, O); |
| 18782 | O << '['; |
| 18783 | printOperand(MI, OpNo: 2, STI, O); |
| 18784 | O << ", "; |
| 18785 | break; |
| 18786 | case 14: |
| 18787 | // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| 18788 | printMatrix<32>(MI, OpNum: 0, STI, O); |
| 18789 | O << '['; |
| 18790 | printOperand(MI, OpNo: 2, STI, O); |
| 18791 | O << ", "; |
| 18792 | break; |
| 18793 | case 15: |
| 18794 | // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ... |
| 18795 | printZPRasFPR<8>(MI, OpNum: 0, STI, O); |
| 18796 | O << ", "; |
| 18797 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 18798 | O << ", "; |
| 18799 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 18800 | return; |
| 18801 | break; |
| 18802 | case 16: |
| 18803 | // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV... |
| 18804 | printZPRasFPR<64>(MI, OpNum: 0, STI, O); |
| 18805 | O << ", "; |
| 18806 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 18807 | O << ", "; |
| 18808 | break; |
| 18809 | case 17: |
| 18810 | // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV... |
| 18811 | printZPRasFPR<16>(MI, OpNum: 0, STI, O); |
| 18812 | O << ", "; |
| 18813 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 18814 | O << ", "; |
| 18815 | break; |
| 18816 | case 18: |
| 18817 | // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV... |
| 18818 | printZPRasFPR<32>(MI, OpNum: 0, STI, O); |
| 18819 | O << ", "; |
| 18820 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 18821 | O << ", "; |
| 18822 | break; |
| 18823 | case 19: |
| 18824 | // AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB, CASAB, CAS... |
| 18825 | printOperand(MI, OpNo: 1, STI, O); |
| 18826 | break; |
| 18827 | case 20: |
| 18828 | // AUTIASPPCi, AUTIBSPPCi, B, BL, RETAASPPCi, RETABSPPCi |
| 18829 | printAlignedLabel(MI, Address, OpNum: 0, STI, O); |
| 18830 | return; |
| 18831 | break; |
| 18832 | case 21: |
| 18833 | // BCcc, Bcc |
| 18834 | printCondCode(MI, OpNum: 0, STI, O); |
| 18835 | O << "\t"; |
| 18836 | printAlignedLabel(MI, Address, OpNum: 1, STI, O); |
| 18837 | return; |
| 18838 | break; |
| 18839 | case 22: |
| 18840 | // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFMLA_VG2_M2Z2Z, BFMLA_VG2_M2ZZ, BFM... |
| 18841 | printMatrix<16>(MI, OpNum: 0, STI, O); |
| 18842 | O << '['; |
| 18843 | printOperand(MI, OpNo: 2, STI, O); |
| 18844 | O << ", "; |
| 18845 | break; |
| 18846 | case 23: |
| 18847 | // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL |
| 18848 | printImmHex(MI, OpNo: 0, STI, O); |
| 18849 | return; |
| 18850 | break; |
| 18851 | case 24: |
| 18852 | // CASPALW, CASPAW, CASPLW, CASPW |
| 18853 | printGPRSeqPairsClassOperand<32>(MI, OpNum: 1, STI, O); |
| 18854 | O << ", "; |
| 18855 | printGPRSeqPairsClassOperand<32>(MI, OpNum: 2, STI, O); |
| 18856 | O << ", ["; |
| 18857 | printOperand(MI, OpNo: 3, STI, O); |
| 18858 | O << ']'; |
| 18859 | return; |
| 18860 | break; |
| 18861 | case 25: |
| 18862 | // CASPALX, CASPAX, CASPLX, CASPX, RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL... |
| 18863 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 1, STI, O); |
| 18864 | O << ", "; |
| 18865 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 2, STI, O); |
| 18866 | O << ", ["; |
| 18867 | printOperand(MI, OpNo: 3, STI, O); |
| 18868 | O << ']'; |
| 18869 | return; |
| 18870 | break; |
| 18871 | case 26: |
| 18872 | // CPYE, CPYEN, CPYERN, CPYERT, CPYERTN, CPYERTRN, CPYERTWN, CPYET, CPYET... |
| 18873 | printOperand(MI, OpNo: 3, STI, O); |
| 18874 | O << "]!, ["; |
| 18875 | printOperand(MI, OpNo: 4, STI, O); |
| 18876 | O << "]!, "; |
| 18877 | printOperand(MI, OpNo: 5, STI, O); |
| 18878 | O << '!'; |
| 18879 | return; |
| 18880 | break; |
| 18881 | case 27: |
| 18882 | // DMB, DSB, ISB, TSB |
| 18883 | printBarrierOption(MI, OpNum: 0, STI, O); |
| 18884 | return; |
| 18885 | break; |
| 18886 | case 28: |
| 18887 | // DSBnXS |
| 18888 | printBarriernXSOption(MI, OpNum: 0, STI, O); |
| 18889 | return; |
| 18890 | break; |
| 18891 | case 29: |
| 18892 | // DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, MOVAZ_ZMI_H_Q, MOVAZ_... |
| 18893 | printSVERegOp<'q'>(MI, OpNum: 0, STI, O); |
| 18894 | O << ", "; |
| 18895 | break; |
| 18896 | case 30: |
| 18897 | // GLD1Q, LD1D_Q, LD1D_Q_IMM, LD1W_Q, LD1W_Q_IMM, LD2Q, LD2Q_IMM, LD3Q, L... |
| 18898 | printTypedVectorList<0,'q'>(MI, OpNum: 0, STI, O); |
| 18899 | O << ", "; |
| 18900 | break; |
| 18901 | case 31: |
| 18902 | // HINT |
| 18903 | printImm(MI, OpNo: 0, STI, O); |
| 18904 | return; |
| 18905 | break; |
| 18906 | case 32: |
| 18907 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 18908 | printMatrixTileVector<0>(MI, OpNum: 0, STI, O); |
| 18909 | O << '['; |
| 18910 | break; |
| 18911 | case 33: |
| 18912 | // INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q... |
| 18913 | printMatrixTileVector<1>(MI, OpNum: 0, STI, O); |
| 18914 | O << '['; |
| 18915 | break; |
| 18916 | case 34: |
| 18917 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED, LDNT1B_2Z_STR... |
| 18918 | printTypedVectorList<0, 'b'>(MI, OpNum: 0, STI, O); |
| 18919 | break; |
| 18920 | case 35: |
| 18921 | // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| 18922 | printTypedVectorList<16, 'b'>(MI, OpNum: 0, STI, O); |
| 18923 | O << ", ["; |
| 18924 | printOperand(MI, OpNo: 1, STI, O); |
| 18925 | O << ']'; |
| 18926 | return; |
| 18927 | break; |
| 18928 | case 36: |
| 18929 | // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| 18930 | printTypedVectorList<16, 'b'>(MI, OpNum: 1, STI, O); |
| 18931 | O << ", ["; |
| 18932 | printOperand(MI, OpNo: 2, STI, O); |
| 18933 | O << "], "; |
| 18934 | break; |
| 18935 | case 37: |
| 18936 | // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| 18937 | printTypedVectorList<1, 'd'>(MI, OpNum: 0, STI, O); |
| 18938 | O << ", ["; |
| 18939 | printOperand(MI, OpNo: 1, STI, O); |
| 18940 | O << ']'; |
| 18941 | return; |
| 18942 | break; |
| 18943 | case 38: |
| 18944 | // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| 18945 | printTypedVectorList<1, 'd'>(MI, OpNum: 1, STI, O); |
| 18946 | O << ", ["; |
| 18947 | printOperand(MI, OpNo: 2, STI, O); |
| 18948 | O << "], "; |
| 18949 | break; |
| 18950 | case 39: |
| 18951 | // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| 18952 | printTypedVectorList<2, 'd'>(MI, OpNum: 0, STI, O); |
| 18953 | O << ", ["; |
| 18954 | printOperand(MI, OpNo: 1, STI, O); |
| 18955 | O << ']'; |
| 18956 | return; |
| 18957 | break; |
| 18958 | case 40: |
| 18959 | // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| 18960 | printTypedVectorList<2, 'd'>(MI, OpNum: 1, STI, O); |
| 18961 | O << ", ["; |
| 18962 | printOperand(MI, OpNo: 2, STI, O); |
| 18963 | O << "], "; |
| 18964 | break; |
| 18965 | case 41: |
| 18966 | // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| 18967 | printTypedVectorList<2, 's'>(MI, OpNum: 0, STI, O); |
| 18968 | O << ", ["; |
| 18969 | printOperand(MI, OpNo: 1, STI, O); |
| 18970 | O << ']'; |
| 18971 | return; |
| 18972 | break; |
| 18973 | case 42: |
| 18974 | // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| 18975 | printTypedVectorList<2, 's'>(MI, OpNum: 1, STI, O); |
| 18976 | O << ", ["; |
| 18977 | printOperand(MI, OpNo: 2, STI, O); |
| 18978 | O << "], "; |
| 18979 | break; |
| 18980 | case 43: |
| 18981 | // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| 18982 | printTypedVectorList<4, 'h'>(MI, OpNum: 0, STI, O); |
| 18983 | O << ", ["; |
| 18984 | printOperand(MI, OpNo: 1, STI, O); |
| 18985 | O << ']'; |
| 18986 | return; |
| 18987 | break; |
| 18988 | case 44: |
| 18989 | // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| 18990 | printTypedVectorList<4, 'h'>(MI, OpNum: 1, STI, O); |
| 18991 | O << ", ["; |
| 18992 | printOperand(MI, OpNo: 2, STI, O); |
| 18993 | O << "], "; |
| 18994 | break; |
| 18995 | case 45: |
| 18996 | // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| 18997 | printTypedVectorList<4, 's'>(MI, OpNum: 0, STI, O); |
| 18998 | O << ", ["; |
| 18999 | printOperand(MI, OpNo: 1, STI, O); |
| 19000 | O << ']'; |
| 19001 | return; |
| 19002 | break; |
| 19003 | case 46: |
| 19004 | // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| 19005 | printTypedVectorList<4, 's'>(MI, OpNum: 1, STI, O); |
| 19006 | O << ", ["; |
| 19007 | printOperand(MI, OpNo: 2, STI, O); |
| 19008 | O << "], "; |
| 19009 | break; |
| 19010 | case 47: |
| 19011 | // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| 19012 | printTypedVectorList<8, 'b'>(MI, OpNum: 0, STI, O); |
| 19013 | O << ", ["; |
| 19014 | printOperand(MI, OpNo: 1, STI, O); |
| 19015 | O << ']'; |
| 19016 | return; |
| 19017 | break; |
| 19018 | case 48: |
| 19019 | // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| 19020 | printTypedVectorList<8, 'b'>(MI, OpNum: 1, STI, O); |
| 19021 | O << ", ["; |
| 19022 | printOperand(MI, OpNo: 2, STI, O); |
| 19023 | O << "], "; |
| 19024 | break; |
| 19025 | case 49: |
| 19026 | // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| 19027 | printTypedVectorList<8, 'h'>(MI, OpNum: 0, STI, O); |
| 19028 | O << ", ["; |
| 19029 | printOperand(MI, OpNo: 1, STI, O); |
| 19030 | O << ']'; |
| 19031 | return; |
| 19032 | break; |
| 19033 | case 50: |
| 19034 | // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| 19035 | printTypedVectorList<8, 'h'>(MI, OpNum: 1, STI, O); |
| 19036 | O << ", ["; |
| 19037 | printOperand(MI, OpNo: 2, STI, O); |
| 19038 | O << "], "; |
| 19039 | break; |
| 19040 | case 51: |
| 19041 | // LD1H_2Z_STRIDED, LD1H_2Z_STRIDED_IMM, LDNT1H_2Z_STRIDED, LDNT1H_2Z_STR... |
| 19042 | printTypedVectorList<0, 'h'>(MI, OpNum: 0, STI, O); |
| 19043 | break; |
| 19044 | case 52: |
| 19045 | // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| 19046 | printTypedVectorList<0, 'h'>(MI, OpNum: 1, STI, O); |
| 19047 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 19048 | O << ", ["; |
| 19049 | printOperand(MI, OpNo: 3, STI, O); |
| 19050 | break; |
| 19051 | case 53: |
| 19052 | // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| 19053 | printTypedVectorList<0, 'h'>(MI, OpNum: 2, STI, O); |
| 19054 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 19055 | O << ", ["; |
| 19056 | printOperand(MI, OpNo: 4, STI, O); |
| 19057 | O << "], "; |
| 19058 | break; |
| 19059 | case 54: |
| 19060 | // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| 19061 | printTypedVectorList<0, 's'>(MI, OpNum: 1, STI, O); |
| 19062 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 19063 | O << ", ["; |
| 19064 | printOperand(MI, OpNo: 3, STI, O); |
| 19065 | break; |
| 19066 | case 55: |
| 19067 | // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| 19068 | printTypedVectorList<0, 's'>(MI, OpNum: 2, STI, O); |
| 19069 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 19070 | O << ", ["; |
| 19071 | printOperand(MI, OpNo: 4, STI, O); |
| 19072 | O << "], "; |
| 19073 | break; |
| 19074 | case 56: |
| 19075 | // LD1i64, LD2i64, LD3i64, LD4i64, LDAP1, ST1i64_POST, ST2i64_POST, ST3i6... |
| 19076 | printTypedVectorList<0, 'd'>(MI, OpNum: 1, STI, O); |
| 19077 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 19078 | O << ", ["; |
| 19079 | printOperand(MI, OpNo: 3, STI, O); |
| 19080 | break; |
| 19081 | case 57: |
| 19082 | // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| 19083 | printTypedVectorList<0, 'd'>(MI, OpNum: 2, STI, O); |
| 19084 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 19085 | O << ", ["; |
| 19086 | printOperand(MI, OpNo: 4, STI, O); |
| 19087 | O << "], "; |
| 19088 | break; |
| 19089 | case 58: |
| 19090 | // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| 19091 | printTypedVectorList<0, 'b'>(MI, OpNum: 1, STI, O); |
| 19092 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 19093 | O << ", ["; |
| 19094 | printOperand(MI, OpNo: 3, STI, O); |
| 19095 | break; |
| 19096 | case 59: |
| 19097 | // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| 19098 | printTypedVectorList<0, 'b'>(MI, OpNum: 2, STI, O); |
| 19099 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 19100 | O << ", ["; |
| 19101 | printOperand(MI, OpNo: 4, STI, O); |
| 19102 | O << "], "; |
| 19103 | break; |
| 19104 | case 60: |
| 19105 | // LD64B, ST64B |
| 19106 | printGPR64x8(MI, OpNum: 0, STI, O); |
| 19107 | O << ", ["; |
| 19108 | printOperand(MI, OpNo: 1, STI, O); |
| 19109 | O << ']'; |
| 19110 | return; |
| 19111 | break; |
| 19112 | case 61: |
| 19113 | // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| 19114 | printOperand(MI, OpNo: 2, STI, O); |
| 19115 | break; |
| 19116 | case 62: |
| 19117 | // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV... |
| 19118 | printSVERegOp<>(MI, OpNum: 0, STI, O); |
| 19119 | break; |
| 19120 | case 63: |
| 19121 | // LDR_ZA, STR_ZA |
| 19122 | printMatrix<0>(MI, OpNum: 0, STI, O); |
| 19123 | O << '['; |
| 19124 | printOperand(MI, OpNo: 1, STI, O); |
| 19125 | O << ", "; |
| 19126 | printMatrixIndex(MI, OpNum: 2, STI, O); |
| 19127 | O << "], ["; |
| 19128 | printOperand(MI, OpNo: 3, STI, O); |
| 19129 | O << ", "; |
| 19130 | printOperand(MI, OpNo: 4, STI, O); |
| 19131 | O << ", mul vl]"; |
| 19132 | return; |
| 19133 | break; |
| 19134 | case 64: |
| 19135 | // MRRS |
| 19136 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 0, STI, O); |
| 19137 | O << ", "; |
| 19138 | printMRSSystemRegister(MI, OpNum: 1, STI, O); |
| 19139 | return; |
| 19140 | break; |
| 19141 | case 65: |
| 19142 | // MSR, MSRR |
| 19143 | printMSRSystemRegister(MI, OpNum: 0, STI, O); |
| 19144 | O << ", "; |
| 19145 | break; |
| 19146 | case 66: |
| 19147 | // MSRpstateImm1, MSRpstateImm4 |
| 19148 | printSystemPStateField(MI, OpNum: 0, STI, O); |
| 19149 | O << ", "; |
| 19150 | printOperand(MI, OpNo: 1, STI, O); |
| 19151 | return; |
| 19152 | break; |
| 19153 | case 67: |
| 19154 | // MSRpstatesvcrImm1 |
| 19155 | printSVCROp(MI, OpNum: 0, STI, O); |
| 19156 | O << ", "; |
| 19157 | printOperand(MI, OpNo: 1, STI, O); |
| 19158 | return; |
| 19159 | break; |
| 19160 | case 68: |
| 19161 | // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| 19162 | printPrefetchOp<true>(MI, OpNum: 0, STI, O); |
| 19163 | O << ", "; |
| 19164 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19165 | O << ", ["; |
| 19166 | break; |
| 19167 | case 69: |
| 19168 | // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| 19169 | printPrefetchOp(MI, OpNum: 0, STI, O); |
| 19170 | break; |
| 19171 | case 70: |
| 19172 | // PTRUE_C_B, WHILEGE_CXX_B, WHILEGT_CXX_B, WHILEHI_CXX_B, WHILEHS_CXX_B,... |
| 19173 | printPredicateAsCounter<8>(MI, OpNum: 0, STI, O); |
| 19174 | break; |
| 19175 | case 71: |
| 19176 | // PTRUE_C_D, WHILEGE_CXX_D, WHILEGT_CXX_D, WHILEHI_CXX_D, WHILEHS_CXX_D,... |
| 19177 | printPredicateAsCounter<64>(MI, OpNum: 0, STI, O); |
| 19178 | break; |
| 19179 | case 72: |
| 19180 | // PTRUE_C_H, WHILEGE_CXX_H, WHILEGT_CXX_H, WHILEHI_CXX_H, WHILEHS_CXX_H,... |
| 19181 | printPredicateAsCounter<16>(MI, OpNum: 0, STI, O); |
| 19182 | break; |
| 19183 | case 73: |
| 19184 | // PTRUE_C_S, WHILEGE_CXX_S, WHILEGT_CXX_S, WHILEHI_CXX_S, WHILEHS_CXX_S,... |
| 19185 | printPredicateAsCounter<32>(MI, OpNum: 0, STI, O); |
| 19186 | break; |
| 19187 | case 74: |
| 19188 | // RPRFM |
| 19189 | printRPRFMOperand(MI, OpNum: 0, STI, O); |
| 19190 | O << ", "; |
| 19191 | printOperand(MI, OpNo: 1, STI, O); |
| 19192 | O << ", ["; |
| 19193 | printOperand(MI, OpNo: 2, STI, O); |
| 19194 | O << ']'; |
| 19195 | return; |
| 19196 | break; |
| 19197 | case 75: |
| 19198 | // ST1i32, ST2i32, ST3i32, ST4i32 |
| 19199 | printTypedVectorList<0, 's'>(MI, OpNum: 0, STI, O); |
| 19200 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 19201 | O << ", ["; |
| 19202 | printOperand(MI, OpNo: 2, STI, O); |
| 19203 | O << ']'; |
| 19204 | return; |
| 19205 | break; |
| 19206 | case 76: |
| 19207 | // ST1i64, ST2i64, ST3i64, ST4i64, STL1 |
| 19208 | printTypedVectorList<0, 'd'>(MI, OpNum: 0, STI, O); |
| 19209 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 19210 | O << ", ["; |
| 19211 | printOperand(MI, OpNo: 2, STI, O); |
| 19212 | O << ']'; |
| 19213 | return; |
| 19214 | break; |
| 19215 | case 77: |
| 19216 | // ZERO_M |
| 19217 | printMatrixTileList(MI, OpNum: 0, STI, O); |
| 19218 | return; |
| 19219 | break; |
| 19220 | } |
| 19221 | |
| 19222 | |
| 19223 | // Fragment 1 encoded into 7 bits for 81 unique commands. |
| 19224 | switch ((Bits >> 22) & 127) { |
| 19225 | default: llvm_unreachable("Invalid command number."); |
| 19226 | case 0: |
| 19227 | // TLSDESCCALL, AUTDZA, AUTDZB, AUTIASPPCr, AUTIBSPPCr, AUTIZA, AUTIZB, B... |
| 19228 | return; |
| 19229 | break; |
| 19230 | case 1: |
| 19231 | // ABSWr, ABSXr, ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv16i8, ABSv1i64, ... |
| 19232 | O << ", "; |
| 19233 | break; |
| 19234 | case 2: |
| 19235 | // ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm... |
| 19236 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 19237 | O << "/m, "; |
| 19238 | break; |
| 19239 | case 3: |
| 19240 | // ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| 19241 | printSVERegOp<'d'>(MI, OpNum: 4, STI, O); |
| 19242 | break; |
| 19243 | case 4: |
| 19244 | // ADDHA_MPPZ_S, ADDVA_MPPZ_S, BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_... |
| 19245 | printSVERegOp<'s'>(MI, OpNum: 4, STI, O); |
| 19246 | break; |
| 19247 | case 5: |
| 19248 | // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,... |
| 19249 | printSVERegOp<'s'>(MI, OpNum: 1, STI, O); |
| 19250 | break; |
| 19251 | case 6: |
| 19252 | // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FCLAMP_VG2_2Z2Z_S, ... |
| 19253 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 19254 | break; |
| 19255 | case 7: |
| 19256 | // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| 19257 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19258 | break; |
| 19259 | case 8: |
| 19260 | // ADDQV_VPZ_B, ANDQV_VPZ_B, EORQV_VPZ_B, FCVTN_F16_F8v16f8, LUT2v16f8, L... |
| 19261 | O << ".16b, "; |
| 19262 | break; |
| 19263 | case 9: |
| 19264 | // ADDQV_VPZ_D, ANDQV_VPZ_D, EORQV_VPZ_D, FADDQV_D, FCVTLv2i32, FCVTLv4i3... |
| 19265 | O << ".2d, "; |
| 19266 | break; |
| 19267 | case 10: |
| 19268 | // ADDQV_VPZ_H, ANDQV_VPZ_H, EORQV_VPZ_H, FADDQV_H, FCVTNv8i16, FMAXNMQV_... |
| 19269 | O << ".8h, "; |
| 19270 | break; |
| 19271 | case 11: |
| 19272 | // ADDQV_VPZ_S, ANDQV_VPZ_S, EORQV_VPZ_S, FADDQV_S, FCVTLv4i16, FCVTLv8i1... |
| 19273 | O << ".4s, "; |
| 19274 | break; |
| 19275 | case 12: |
| 19276 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, SMAX_VG2_2Z2Z_B, SMAX_VG2_2ZZ_B, SMAX_VG... |
| 19277 | printTypedVectorList<0,'b'>(MI, OpNum: 1, STI, O); |
| 19278 | break; |
| 19279 | case 13: |
| 19280 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D... |
| 19281 | printTypedVectorList<0,'d'>(MI, OpNum: 1, STI, O); |
| 19282 | break; |
| 19283 | case 14: |
| 19284 | // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG2_2ZZ_H, B... |
| 19285 | printTypedVectorList<0,'h'>(MI, OpNum: 1, STI, O); |
| 19286 | break; |
| 19287 | case 15: |
| 19288 | // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVTN_Z2Z_StoH, BFCVT_Z2Z_StoH, FAMAX_2... |
| 19289 | printTypedVectorList<0,'s'>(MI, OpNum: 1, STI, O); |
| 19290 | break; |
| 19291 | case 16: |
| 19292 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| 19293 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 19294 | break; |
| 19295 | case 17: |
| 19296 | // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H... |
| 19297 | printSVERegOp<'h'>(MI, OpNum: 1, STI, O); |
| 19298 | break; |
| 19299 | case 18: |
| 19300 | // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| 19301 | O << ", ["; |
| 19302 | break; |
| 19303 | case 19: |
| 19304 | // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4... |
| 19305 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 19306 | break; |
| 19307 | case 20: |
| 19308 | // ANDV_VPZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA... |
| 19309 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 19310 | break; |
| 19311 | case 21: |
| 19312 | // BF1CVTLT_ZZ_BtoH, BF1CVTL_2ZZ_BtoH_NAME, BF1CVT_2ZZ_BtoH_NAME, BF1CVT_... |
| 19313 | printSVERegOp<'b'>(MI, OpNum: 1, STI, O); |
| 19314 | break; |
| 19315 | case 22: |
| 19316 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFMLAL_VG2_M... |
| 19317 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 19318 | break; |
| 19319 | case 23: |
| 19320 | // BFMOPA_MPPZZ, BFMOPA_MPPZZ_H, BFMOPS_MPPZZ, BFMOPS_MPPZZ_H, FMOPAL_MPP... |
| 19321 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 19322 | O << ", "; |
| 19323 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 19324 | return; |
| 19325 | break; |
| 19326 | case 24: |
| 19327 | // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| 19328 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 19329 | O << ", mul "; |
| 19330 | printOperand(MI, OpNo: 3, STI, O); |
| 19331 | return; |
| 19332 | break; |
| 19333 | case 25: |
| 19334 | // DUP_ZI_H |
| 19335 | printImm8OptLsl<int16_t>(MI, OpNum: 1, STI, O); |
| 19336 | return; |
| 19337 | break; |
| 19338 | case 26: |
| 19339 | // DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_... |
| 19340 | printOperand(MI, OpNo: 1, STI, O); |
| 19341 | break; |
| 19342 | case 27: |
| 19343 | // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZ... |
| 19344 | printSVERegOp<'q'>(MI, OpNum: 1, STI, O); |
| 19345 | break; |
| 19346 | case 28: |
| 19347 | // FADDA_VPZ_D |
| 19348 | printZPRasFPR<64>(MI, OpNum: 2, STI, O); |
| 19349 | O << ", "; |
| 19350 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 19351 | return; |
| 19352 | break; |
| 19353 | case 29: |
| 19354 | // FADDA_VPZ_H, INSR_ZV_H |
| 19355 | printZPRasFPR<16>(MI, OpNum: 2, STI, O); |
| 19356 | break; |
| 19357 | case 30: |
| 19358 | // FADDA_VPZ_S |
| 19359 | printZPRasFPR<32>(MI, OpNum: 2, STI, O); |
| 19360 | O << ", "; |
| 19361 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 19362 | return; |
| 19363 | break; |
| 19364 | case 31: |
| 19365 | // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| 19366 | O << ", #0.0"; |
| 19367 | return; |
| 19368 | break; |
| 19369 | case 32: |
| 19370 | // FCVTN_F16_F8v8f8, FCVTN_F32_F8v8f8, TBLv8i8Four, TBLv8i8One, TBLv8i8Th... |
| 19371 | O << ".8b, "; |
| 19372 | break; |
| 19373 | case 33: |
| 19374 | // FCVTNv2i32, FCVTXNv2f32 |
| 19375 | O << ".2s, "; |
| 19376 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 19377 | O << ".2d"; |
| 19378 | return; |
| 19379 | break; |
| 19380 | case 34: |
| 19381 | // FCVTNv4i16 |
| 19382 | O << ".4h, "; |
| 19383 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 19384 | O << ".4s"; |
| 19385 | return; |
| 19386 | break; |
| 19387 | case 35: |
| 19388 | // FDOT_ZZZI_BtoH, FDOT_ZZZ_BtoH, FMLALB_ZZZ, FMLALB_ZZZI, FMLALT_ZZZ, FM... |
| 19389 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 19390 | break; |
| 19391 | case 36: |
| 19392 | // FDUP_ZI_H |
| 19393 | printFPImmOperand(MI, OpNum: 1, STI, O); |
| 19394 | return; |
| 19395 | break; |
| 19396 | case 37: |
| 19397 | // FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLALL_VG2_M2Z2Z_BtoS, FMLALL_VG2_M... |
| 19398 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 19399 | break; |
| 19400 | case 38: |
| 19401 | // FMOPA_MPPZZ_BtoH, FMOPA_MPPZZ_BtoS, SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMO... |
| 19402 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 19403 | O << ", "; |
| 19404 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 19405 | return; |
| 19406 | break; |
| 19407 | case 39: |
| 19408 | // FMOVXDHighr, INSvi16gpr, INSvi16lane, INSvi32gpr, INSvi32lane, INSvi64... |
| 19409 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 19410 | O << ", "; |
| 19411 | break; |
| 19412 | case 40: |
| 19413 | // INDEX_II_H, INDEX_IR_H |
| 19414 | printSImm<16>(MI, OpNo: 1, STI, O); |
| 19415 | O << ", "; |
| 19416 | break; |
| 19417 | case 41: |
| 19418 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 19419 | printOperand(MI, OpNo: 2, STI, O); |
| 19420 | break; |
| 19421 | case 42: |
| 19422 | // LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1B_4Z_IMM, LD1B_4Z_STRIDED, LD1B_4Z_S... |
| 19423 | printPredicateAsCounter<0>(MI, OpNum: 1, STI, O); |
| 19424 | break; |
| 19425 | case 43: |
| 19426 | // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| 19427 | printPostIncOperand<64>(MI, OpNo: 3, STI, O); |
| 19428 | return; |
| 19429 | break; |
| 19430 | case 44: |
| 19431 | // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| 19432 | printPostIncOperand<32>(MI, OpNo: 3, STI, O); |
| 19433 | return; |
| 19434 | break; |
| 19435 | case 45: |
| 19436 | // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| 19437 | printPostIncOperand<16>(MI, OpNo: 3, STI, O); |
| 19438 | return; |
| 19439 | break; |
| 19440 | case 46: |
| 19441 | // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| 19442 | printPostIncOperand<8>(MI, OpNo: 3, STI, O); |
| 19443 | return; |
| 19444 | break; |
| 19445 | case 47: |
| 19446 | // LD1Rv16b_POST, LD1Rv8b_POST |
| 19447 | printPostIncOperand<1>(MI, OpNo: 3, STI, O); |
| 19448 | return; |
| 19449 | break; |
| 19450 | case 48: |
| 19451 | // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| 19452 | printPostIncOperand<4>(MI, OpNo: 3, STI, O); |
| 19453 | return; |
| 19454 | break; |
| 19455 | case 49: |
| 19456 | // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| 19457 | printPostIncOperand<2>(MI, OpNo: 3, STI, O); |
| 19458 | return; |
| 19459 | break; |
| 19460 | case 50: |
| 19461 | // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| 19462 | printPostIncOperand<48>(MI, OpNo: 3, STI, O); |
| 19463 | return; |
| 19464 | break; |
| 19465 | case 51: |
| 19466 | // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| 19467 | printPostIncOperand<24>(MI, OpNo: 3, STI, O); |
| 19468 | return; |
| 19469 | break; |
| 19470 | case 52: |
| 19471 | // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| 19472 | O << ']'; |
| 19473 | return; |
| 19474 | break; |
| 19475 | case 53: |
| 19476 | // LD1i16_POST, LD2i8_POST |
| 19477 | printPostIncOperand<2>(MI, OpNo: 5, STI, O); |
| 19478 | return; |
| 19479 | break; |
| 19480 | case 54: |
| 19481 | // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| 19482 | printPostIncOperand<4>(MI, OpNo: 5, STI, O); |
| 19483 | return; |
| 19484 | break; |
| 19485 | case 55: |
| 19486 | // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| 19487 | printPostIncOperand<8>(MI, OpNo: 5, STI, O); |
| 19488 | return; |
| 19489 | break; |
| 19490 | case 56: |
| 19491 | // LD1i8_POST |
| 19492 | printPostIncOperand<1>(MI, OpNo: 5, STI, O); |
| 19493 | return; |
| 19494 | break; |
| 19495 | case 57: |
| 19496 | // LD2i64_POST, LD4i32_POST |
| 19497 | printPostIncOperand<16>(MI, OpNo: 5, STI, O); |
| 19498 | return; |
| 19499 | break; |
| 19500 | case 58: |
| 19501 | // LD3Rv16b_POST, LD3Rv8b_POST |
| 19502 | printPostIncOperand<3>(MI, OpNo: 3, STI, O); |
| 19503 | return; |
| 19504 | break; |
| 19505 | case 59: |
| 19506 | // LD3Rv2s_POST, LD3Rv4s_POST |
| 19507 | printPostIncOperand<12>(MI, OpNo: 3, STI, O); |
| 19508 | return; |
| 19509 | break; |
| 19510 | case 60: |
| 19511 | // LD3Rv4h_POST, LD3Rv8h_POST |
| 19512 | printPostIncOperand<6>(MI, OpNo: 3, STI, O); |
| 19513 | return; |
| 19514 | break; |
| 19515 | case 61: |
| 19516 | // LD3i16_POST |
| 19517 | printPostIncOperand<6>(MI, OpNo: 5, STI, O); |
| 19518 | return; |
| 19519 | break; |
| 19520 | case 62: |
| 19521 | // LD3i32_POST |
| 19522 | printPostIncOperand<12>(MI, OpNo: 5, STI, O); |
| 19523 | return; |
| 19524 | break; |
| 19525 | case 63: |
| 19526 | // LD3i64_POST |
| 19527 | printPostIncOperand<24>(MI, OpNo: 5, STI, O); |
| 19528 | return; |
| 19529 | break; |
| 19530 | case 64: |
| 19531 | // LD3i8_POST |
| 19532 | printPostIncOperand<3>(MI, OpNo: 5, STI, O); |
| 19533 | return; |
| 19534 | break; |
| 19535 | case 65: |
| 19536 | // LD4i64_POST |
| 19537 | printPostIncOperand<32>(MI, OpNo: 5, STI, O); |
| 19538 | return; |
| 19539 | break; |
| 19540 | case 66: |
| 19541 | // MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE... |
| 19542 | O << "]!, "; |
| 19543 | printOperand(MI, OpNo: 3, STI, O); |
| 19544 | O << "!, "; |
| 19545 | printOperand(MI, OpNo: 4, STI, O); |
| 19546 | return; |
| 19547 | break; |
| 19548 | case 67: |
| 19549 | // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| 19550 | printMatrixTileVector<0>(MI, OpNum: 2, STI, O); |
| 19551 | O << '['; |
| 19552 | printOperand(MI, OpNo: 3, STI, O); |
| 19553 | O << ", "; |
| 19554 | break; |
| 19555 | case 68: |
| 19556 | // MOVAZ_2ZMI_V_B, MOVAZ_2ZMI_V_D, MOVAZ_2ZMI_V_H, MOVAZ_2ZMI_V_S, MOVAZ_... |
| 19557 | printMatrixTileVector<1>(MI, OpNum: 2, STI, O); |
| 19558 | O << '['; |
| 19559 | printOperand(MI, OpNo: 3, STI, O); |
| 19560 | O << ", "; |
| 19561 | break; |
| 19562 | case 69: |
| 19563 | // MOVAZ_VG2_2ZMXI, MOVAZ_VG4_4ZMXI |
| 19564 | printMatrix<64>(MI, OpNum: 2, STI, O); |
| 19565 | O << '['; |
| 19566 | printOperand(MI, OpNo: 3, STI, O); |
| 19567 | O << ", "; |
| 19568 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 19569 | break; |
| 19570 | case 70: |
| 19571 | // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZM... |
| 19572 | printMatrixTileVector<0>(MI, OpNum: 1, STI, O); |
| 19573 | O << '['; |
| 19574 | break; |
| 19575 | case 71: |
| 19576 | // MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q, MOVA_2ZMXI_V_B, MOVA_2ZMXI_V_D, MOVA_2ZM... |
| 19577 | printMatrixTileVector<1>(MI, OpNum: 1, STI, O); |
| 19578 | O << '['; |
| 19579 | break; |
| 19580 | case 72: |
| 19581 | // MOVA_VG2_2ZMXI, MOVA_VG4_4ZMXI |
| 19582 | printMatrix<64>(MI, OpNum: 1, STI, O); |
| 19583 | O << '['; |
| 19584 | printOperand(MI, OpNo: 2, STI, O); |
| 19585 | O << ", "; |
| 19586 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 19587 | break; |
| 19588 | case 73: |
| 19589 | // MOVT, MOVT_TIX |
| 19590 | O << '['; |
| 19591 | break; |
| 19592 | case 74: |
| 19593 | // MSRR |
| 19594 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 1, STI, O); |
| 19595 | return; |
| 19596 | break; |
| 19597 | case 75: |
| 19598 | // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, UZP_VG2_2ZZZ_D, ZIP_VG2_2ZZZ_D |
| 19599 | printSVERegOp<'d'>(MI, OpNum: 1, STI, O); |
| 19600 | O << ", "; |
| 19601 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 19602 | return; |
| 19603 | break; |
| 19604 | case 76: |
| 19605 | // PTRUES_H, PTRUE_H |
| 19606 | printSVEPattern(MI, OpNum: 1, STI, O); |
| 19607 | return; |
| 19608 | break; |
| 19609 | case 77: |
| 19610 | // ST1i16, ST1i8, ST2i16, ST2i8, ST3i16, ST3i8, ST4i16, ST4i8 |
| 19611 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 19612 | O << ", ["; |
| 19613 | printOperand(MI, OpNo: 2, STI, O); |
| 19614 | O << ']'; |
| 19615 | return; |
| 19616 | break; |
| 19617 | case 78: |
| 19618 | // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| 19619 | O << "], "; |
| 19620 | break; |
| 19621 | case 79: |
| 19622 | // UZP_VG4_4Z4Z_Q, ZIP_VG4_4Z4Z_Q |
| 19623 | printTypedVectorList<0,'q'>(MI, OpNum: 1, STI, O); |
| 19624 | return; |
| 19625 | break; |
| 19626 | case 80: |
| 19627 | // ZERO_T |
| 19628 | O << " }"; |
| 19629 | return; |
| 19630 | break; |
| 19631 | } |
| 19632 | |
| 19633 | |
| 19634 | // Fragment 2 encoded into 7 bits for 90 unique commands. |
| 19635 | switch ((Bits >> 29) & 127) { |
| 19636 | default: llvm_unreachable("Invalid command number."); |
| 19637 | case 0: |
| 19638 | // ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI,... |
| 19639 | printOperand(MI, OpNo: 1, STI, O); |
| 19640 | break; |
| 19641 | case 1: |
| 19642 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| 19643 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 19644 | O << "/m, "; |
| 19645 | break; |
| 19646 | case 2: |
| 19647 | // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... |
| 19648 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 19649 | return; |
| 19650 | break; |
| 19651 | case 3: |
| 19652 | // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| 19653 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 19654 | break; |
| 19655 | case 4: |
| 19656 | // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z... |
| 19657 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 19658 | break; |
| 19659 | case 5: |
| 19660 | // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ... |
| 19661 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 19662 | break; |
| 19663 | case 6: |
| 19664 | // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, ANDV_VPZ_D, AN... |
| 19665 | return; |
| 19666 | break; |
| 19667 | case 7: |
| 19668 | // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH... |
| 19669 | printSVERegOp<'h'>(MI, OpNum: 1, STI, O); |
| 19670 | break; |
| 19671 | case 8: |
| 19672 | // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_VG2_2ZZ_B, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_... |
| 19673 | O << ", "; |
| 19674 | break; |
| 19675 | case 9: |
| 19676 | // ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_CPA, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_L... |
| 19677 | printSVERegOp<'d'>(MI, OpNum: 1, STI, O); |
| 19678 | break; |
| 19679 | case 10: |
| 19680 | // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| 19681 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 19682 | break; |
| 19683 | case 11: |
| 19684 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| 19685 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 19686 | break; |
| 19687 | case 12: |
| 19688 | // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADDQV_VPZ_B, ADDQV_VPZ_D, ADDQV... |
| 19689 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19690 | break; |
| 19691 | case 13: |
| 19692 | // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| 19693 | O << "/m, "; |
| 19694 | break; |
| 19695 | case 14: |
| 19696 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| 19697 | O << ", vgx2], "; |
| 19698 | break; |
| 19699 | case 15: |
| 19700 | // ADD_VG4_M4Z4Z_D, ADD_VG4_M4Z4Z_S, ADD_VG4_M4ZZ_D, ADD_VG4_M4ZZ_S, ADD_... |
| 19701 | O << ", vgx4], "; |
| 19702 | break; |
| 19703 | case 16: |
| 19704 | // ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ... |
| 19705 | printSVERegOp<'b'>(MI, OpNum: 1, STI, O); |
| 19706 | break; |
| 19707 | case 17: |
| 19708 | // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... |
| 19709 | printSVERegOp<'s'>(MI, OpNum: 1, STI, O); |
| 19710 | break; |
| 19711 | case 18: |
| 19712 | // ADR, ADRP |
| 19713 | printAdrAdrpLabel(MI, Address, OpNum: 1, STI, O); |
| 19714 | return; |
| 19715 | break; |
| 19716 | case 19: |
| 19717 | // AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA... |
| 19718 | printOperand(MI, OpNo: 2, STI, O); |
| 19719 | break; |
| 19720 | case 20: |
| 19721 | // BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, PMOV_ZIP_S... |
| 19722 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 19723 | return; |
| 19724 | break; |
| 19725 | case 21: |
| 19726 | // BFCVTN_Z2Z_HtoB, BFCVT_Z2Z_HtoB, FCVTN_Z2Z_HtoB, FCVT_Z2Z_HtoB |
| 19727 | printTypedVectorList<0,'h'>(MI, OpNum: 1, STI, O); |
| 19728 | return; |
| 19729 | break; |
| 19730 | case 22: |
| 19731 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ... |
| 19732 | O << "], "; |
| 19733 | break; |
| 19734 | case 23: |
| 19735 | // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| 19736 | printImm(MI, OpNo: 2, STI, O); |
| 19737 | printShifter(MI, OpNum: 3, STI, O); |
| 19738 | return; |
| 19739 | break; |
| 19740 | case 24: |
| 19741 | // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| 19742 | printAlignedLabel(MI, Address, OpNum: 1, STI, O); |
| 19743 | return; |
| 19744 | break; |
| 19745 | case 25: |
| 19746 | // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, FDOT_ZZ... |
| 19747 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 19748 | O << ", "; |
| 19749 | break; |
| 19750 | case 26: |
| 19751 | // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... |
| 19752 | O << "/z, "; |
| 19753 | break; |
| 19754 | case 27: |
| 19755 | // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| 19756 | printSVEPattern(MI, OpNum: 1, STI, O); |
| 19757 | break; |
| 19758 | case 28: |
| 19759 | // CNTP_XCI_B |
| 19760 | printPredicateAsCounter<8>(MI, OpNum: 1, STI, O); |
| 19761 | O << ", "; |
| 19762 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 19763 | return; |
| 19764 | break; |
| 19765 | case 29: |
| 19766 | // CNTP_XCI_D |
| 19767 | printPredicateAsCounter<64>(MI, OpNum: 1, STI, O); |
| 19768 | O << ", "; |
| 19769 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 19770 | return; |
| 19771 | break; |
| 19772 | case 30: |
| 19773 | // CNTP_XCI_H |
| 19774 | printPredicateAsCounter<16>(MI, OpNum: 1, STI, O); |
| 19775 | O << ", "; |
| 19776 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 19777 | return; |
| 19778 | break; |
| 19779 | case 31: |
| 19780 | // CNTP_XCI_S |
| 19781 | printPredicateAsCounter<32>(MI, OpNum: 1, STI, O); |
| 19782 | O << ", "; |
| 19783 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 19784 | return; |
| 19785 | break; |
| 19786 | case 32: |
| 19787 | // CPY_ZPmI_H |
| 19788 | printImm8OptLsl<int16_t>(MI, OpNum: 3, STI, O); |
| 19789 | return; |
| 19790 | break; |
| 19791 | case 33: |
| 19792 | // CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr,... |
| 19793 | printOperand(MI, OpNo: 3, STI, O); |
| 19794 | break; |
| 19795 | case 34: |
| 19796 | // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| 19797 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 19798 | O << ", mul "; |
| 19799 | printOperand(MI, OpNo: 3, STI, O); |
| 19800 | return; |
| 19801 | break; |
| 19802 | case 35: |
| 19803 | // DUPM_ZI |
| 19804 | printLogicalImm<int64_t>(MI, OpNum: 1, STI, O); |
| 19805 | return; |
| 19806 | break; |
| 19807 | case 36: |
| 19808 | // DUPQ_ZZI_H, DUP_ZZI_H, DUP_ZZI_Q, PEXT_2PCI_B, PEXT_2PCI_D, PEXT_2PCI_... |
| 19809 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 19810 | return; |
| 19811 | break; |
| 19812 | case 37: |
| 19813 | // DUP_ZI_B |
| 19814 | printImm8OptLsl<int8_t>(MI, OpNum: 1, STI, O); |
| 19815 | return; |
| 19816 | break; |
| 19817 | case 38: |
| 19818 | // DUP_ZI_D |
| 19819 | printImm8OptLsl<int64_t>(MI, OpNum: 1, STI, O); |
| 19820 | return; |
| 19821 | break; |
| 19822 | case 39: |
| 19823 | // DUP_ZI_S |
| 19824 | printImm8OptLsl<int32_t>(MI, OpNum: 1, STI, O); |
| 19825 | return; |
| 19826 | break; |
| 19827 | case 40: |
| 19828 | // EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q |
| 19829 | printMatrixTileVector<0>(MI, OpNum: 3, STI, O); |
| 19830 | O << '['; |
| 19831 | printOperand(MI, OpNo: 4, STI, O); |
| 19832 | O << ", "; |
| 19833 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 19834 | O << ']'; |
| 19835 | return; |
| 19836 | break; |
| 19837 | case 41: |
| 19838 | // EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q |
| 19839 | printMatrixTileVector<1>(MI, OpNum: 3, STI, O); |
| 19840 | O << '['; |
| 19841 | printOperand(MI, OpNo: 4, STI, O); |
| 19842 | O << ", "; |
| 19843 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 19844 | O << ']'; |
| 19845 | return; |
| 19846 | break; |
| 19847 | case 42: |
| 19848 | // EXT_ZZI_B, LUTI2_ZZZI_B, LUTI4_ZZZI_B, TBLQ_ZZZ_B, TBL_ZZZZ_B, TBL_ZZZ... |
| 19849 | printTypedVectorList<0,'b'>(MI, OpNum: 1, STI, O); |
| 19850 | O << ", "; |
| 19851 | break; |
| 19852 | case 43: |
| 19853 | // FCPY_ZPmI_H |
| 19854 | printFPImmOperand(MI, OpNum: 3, STI, O); |
| 19855 | return; |
| 19856 | break; |
| 19857 | case 44: |
| 19858 | // FCVTNB_Z2Z_StoB, FCVTNT_Z2Z_StoB, FCVTN_Z4Z_StoB_NAME, FCVT_Z4Z_StoB_N... |
| 19859 | printTypedVectorList<0,'s'>(MI, OpNum: 1, STI, O); |
| 19860 | break; |
| 19861 | case 45: |
| 19862 | // FCVT_ZPmZ_DtoH, PMOV_ZIP_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH |
| 19863 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 19864 | return; |
| 19865 | break; |
| 19866 | case 46: |
| 19867 | // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| 19868 | printFPImmOperand(MI, OpNum: 1, STI, O); |
| 19869 | return; |
| 19870 | break; |
| 19871 | case 47: |
| 19872 | // FMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_HtoD, SMLS... |
| 19873 | O << ", vgx2], "; |
| 19874 | break; |
| 19875 | case 48: |
| 19876 | // FMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_HtoD, SMLS... |
| 19877 | O << ", vgx4], "; |
| 19878 | break; |
| 19879 | case 49: |
| 19880 | // GLD1B_D, GLD1B_D_IMM, GLD1B_D_SXTW, GLD1B_D_UXTW, GLD1B_S_IMM, GLD1B_S... |
| 19881 | O << "/z, ["; |
| 19882 | break; |
| 19883 | case 50: |
| 19884 | // INDEX_II_B, INDEX_IR_B |
| 19885 | printSImm<8>(MI, OpNo: 1, STI, O); |
| 19886 | O << ", "; |
| 19887 | break; |
| 19888 | case 51: |
| 19889 | // INDEX_II_H |
| 19890 | printSImm<16>(MI, OpNo: 2, STI, O); |
| 19891 | return; |
| 19892 | break; |
| 19893 | case 52: |
| 19894 | // INSR_ZV_B |
| 19895 | printZPRasFPR<8>(MI, OpNum: 2, STI, O); |
| 19896 | return; |
| 19897 | break; |
| 19898 | case 53: |
| 19899 | // INSR_ZV_D |
| 19900 | printZPRasFPR<64>(MI, OpNum: 2, STI, O); |
| 19901 | return; |
| 19902 | break; |
| 19903 | case 54: |
| 19904 | // INSR_ZV_S |
| 19905 | printZPRasFPR<32>(MI, OpNum: 2, STI, O); |
| 19906 | return; |
| 19907 | break; |
| 19908 | case 55: |
| 19909 | // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| 19910 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 19911 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 19912 | return; |
| 19913 | break; |
| 19914 | case 56: |
| 19915 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED... |
| 19916 | printPredicateAsCounter<0>(MI, OpNum: 1, STI, O); |
| 19917 | break; |
| 19918 | case 57: |
| 19919 | // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| 19920 | printOperand(MI, OpNo: 0, STI, O); |
| 19921 | O << ", ["; |
| 19922 | printOperand(MI, OpNo: 2, STI, O); |
| 19923 | O << ']'; |
| 19924 | return; |
| 19925 | break; |
| 19926 | case 58: |
| 19927 | // LUT2v16f8, LUT4v16f8, TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16... |
| 19928 | printTypedVectorList<16, 'b'>(MI, OpNum: 1, STI, O); |
| 19929 | O << ", "; |
| 19930 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 19931 | break; |
| 19932 | case 59: |
| 19933 | // LUT2v8f16, LUT4v8f16 |
| 19934 | printTypedVectorList<8, 'h'>(MI, OpNum: 1, STI, O); |
| 19935 | O << ", "; |
| 19936 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 19937 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 19938 | return; |
| 19939 | break; |
| 19940 | case 60: |
| 19941 | // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| 19942 | printImmRangeScale<2, 1>(MI, OpNum: 4, STI, O); |
| 19943 | O << ']'; |
| 19944 | return; |
| 19945 | break; |
| 19946 | case 61: |
| 19947 | // MOVAZ_4ZMI_H_B, MOVAZ_4ZMI_H_D, MOVAZ_4ZMI_H_H, MOVAZ_4ZMI_H_S, MOVAZ_... |
| 19948 | printImmRangeScale<4, 3>(MI, OpNum: 4, STI, O); |
| 19949 | O << ']'; |
| 19950 | return; |
| 19951 | break; |
| 19952 | case 62: |
| 19953 | // MOVAZ_VG2_2ZMXI, MOVA_VG2_2ZMXI, ZERO_MXI_VG2_2Z, ZERO_MXI_VG2_4Z, ZER... |
| 19954 | O << ", vgx2]"; |
| 19955 | return; |
| 19956 | break; |
| 19957 | case 63: |
| 19958 | // MOVAZ_VG4_4ZMXI, MOVA_VG4_4ZMXI, ZERO_MXI_VG4_2Z, ZERO_MXI_VG4_4Z, ZER... |
| 19959 | O << ", vgx4]"; |
| 19960 | return; |
| 19961 | break; |
| 19962 | case 64: |
| 19963 | // MOVAZ_ZMI_H_B, MOVAZ_ZMI_H_D, MOVAZ_ZMI_H_S |
| 19964 | printMatrixTileVector<0>(MI, OpNum: 1, STI, O); |
| 19965 | O << '['; |
| 19966 | printOperand(MI, OpNo: 3, STI, O); |
| 19967 | O << ", "; |
| 19968 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 19969 | O << ']'; |
| 19970 | return; |
| 19971 | break; |
| 19972 | case 65: |
| 19973 | // MOVAZ_ZMI_V_B, MOVAZ_ZMI_V_D, MOVAZ_ZMI_V_S |
| 19974 | printMatrixTileVector<1>(MI, OpNum: 1, STI, O); |
| 19975 | O << '['; |
| 19976 | printOperand(MI, OpNo: 3, STI, O); |
| 19977 | O << ", "; |
| 19978 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 19979 | O << ']'; |
| 19980 | return; |
| 19981 | break; |
| 19982 | case 66: |
| 19983 | // MOVID, MOVIv2d_ns |
| 19984 | printSIMDType10Operand(MI, OpNum: 1, STI, O); |
| 19985 | return; |
| 19986 | break; |
| 19987 | case 67: |
| 19988 | // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| 19989 | printImm(MI, OpNo: 1, STI, O); |
| 19990 | break; |
| 19991 | case 68: |
| 19992 | // MOVT |
| 19993 | printMatrixIndex(MI, OpNum: 1, STI, O); |
| 19994 | O << ", mul vl], "; |
| 19995 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 19996 | return; |
| 19997 | break; |
| 19998 | case 69: |
| 19999 | // MOVT_TIX |
| 20000 | printMatrixIndex<8>(MI, OpNum: 1, STI, O); |
| 20001 | O << "], "; |
| 20002 | printOperand(MI, OpNo: 2, STI, O); |
| 20003 | return; |
| 20004 | break; |
| 20005 | case 70: |
| 20006 | // MRS |
| 20007 | printMRSSystemRegister(MI, OpNum: 1, STI, O); |
| 20008 | return; |
| 20009 | break; |
| 20010 | case 71: |
| 20011 | // PMOV_ZIP_B |
| 20012 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 20013 | return; |
| 20014 | break; |
| 20015 | case 72: |
| 20016 | // REVD_ZPmZ |
| 20017 | printSVERegOp<'q'>(MI, OpNum: 3, STI, O); |
| 20018 | return; |
| 20019 | break; |
| 20020 | case 73: |
| 20021 | // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| 20022 | printGPR64as32(MI, OpNum: 1, STI, O); |
| 20023 | O << ", "; |
| 20024 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 20025 | O << ", mul "; |
| 20026 | printOperand(MI, OpNo: 3, STI, O); |
| 20027 | return; |
| 20028 | break; |
| 20029 | case 74: |
| 20030 | // SST1B_D, SST1B_D_IMM, SST1B_D_SXTW, SST1B_D_UXTW, SST1B_S_IMM, SST1B_S... |
| 20031 | O << ", ["; |
| 20032 | break; |
| 20033 | case 75: |
| 20034 | // ST1i16_POST, ST2i8_POST |
| 20035 | printPostIncOperand<2>(MI, OpNo: 4, STI, O); |
| 20036 | return; |
| 20037 | break; |
| 20038 | case 76: |
| 20039 | // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| 20040 | printPostIncOperand<4>(MI, OpNo: 4, STI, O); |
| 20041 | return; |
| 20042 | break; |
| 20043 | case 77: |
| 20044 | // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| 20045 | printPostIncOperand<8>(MI, OpNo: 4, STI, O); |
| 20046 | return; |
| 20047 | break; |
| 20048 | case 78: |
| 20049 | // ST1i8_POST |
| 20050 | printPostIncOperand<1>(MI, OpNo: 4, STI, O); |
| 20051 | return; |
| 20052 | break; |
| 20053 | case 79: |
| 20054 | // ST2i64_POST, ST4i32_POST |
| 20055 | printPostIncOperand<16>(MI, OpNo: 4, STI, O); |
| 20056 | return; |
| 20057 | break; |
| 20058 | case 80: |
| 20059 | // ST3i16_POST |
| 20060 | printPostIncOperand<6>(MI, OpNo: 4, STI, O); |
| 20061 | return; |
| 20062 | break; |
| 20063 | case 81: |
| 20064 | // ST3i32_POST |
| 20065 | printPostIncOperand<12>(MI, OpNo: 4, STI, O); |
| 20066 | return; |
| 20067 | break; |
| 20068 | case 82: |
| 20069 | // ST3i64_POST |
| 20070 | printPostIncOperand<24>(MI, OpNo: 4, STI, O); |
| 20071 | return; |
| 20072 | break; |
| 20073 | case 83: |
| 20074 | // ST3i8_POST |
| 20075 | printPostIncOperand<3>(MI, OpNo: 4, STI, O); |
| 20076 | return; |
| 20077 | break; |
| 20078 | case 84: |
| 20079 | // ST4i64_POST |
| 20080 | printPostIncOperand<32>(MI, OpNo: 4, STI, O); |
| 20081 | return; |
| 20082 | break; |
| 20083 | case 85: |
| 20084 | // ST64BV, ST64BV0 |
| 20085 | printGPR64x8(MI, OpNum: 1, STI, O); |
| 20086 | O << ", ["; |
| 20087 | printOperand(MI, OpNo: 2, STI, O); |
| 20088 | O << ']'; |
| 20089 | return; |
| 20090 | break; |
| 20091 | case 86: |
| 20092 | // SYSPxt, SYSPxt_XZR, SYSxt |
| 20093 | printSysCROperand(MI, OpNo: 1, STI, O); |
| 20094 | O << ", "; |
| 20095 | printSysCROperand(MI, OpNo: 2, STI, O); |
| 20096 | O << ", "; |
| 20097 | printOperand(MI, OpNo: 3, STI, O); |
| 20098 | O << ", "; |
| 20099 | break; |
| 20100 | case 87: |
| 20101 | // TBLQ_ZZZ_D, TBL_ZZZZ_D, TBL_ZZZ_D |
| 20102 | printTypedVectorList<0,'d'>(MI, OpNum: 1, STI, O); |
| 20103 | O << ", "; |
| 20104 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 20105 | return; |
| 20106 | break; |
| 20107 | case 88: |
| 20108 | // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| 20109 | printTypedVectorList<16, 'b'>(MI, OpNum: 2, STI, O); |
| 20110 | O << ", "; |
| 20111 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 20112 | break; |
| 20113 | case 89: |
| 20114 | // ZERO_MXI_2Z, ZERO_MXI_4Z |
| 20115 | O << ']'; |
| 20116 | return; |
| 20117 | break; |
| 20118 | } |
| 20119 | |
| 20120 | |
| 20121 | // Fragment 3 encoded into 7 bits for 103 unique commands. |
| 20122 | switch ((Bits >> 36) & 127) { |
| 20123 | default: llvm_unreachable("Invalid command number."); |
| 20124 | case 0: |
| 20125 | // ABSWr, ABSXr, ABSv16i8, ABSv1i64, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i... |
| 20126 | return; |
| 20127 | break; |
| 20128 | case 1: |
| 20129 | // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,... |
| 20130 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 20131 | break; |
| 20132 | case 2: |
| 20133 | // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... |
| 20134 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 20135 | return; |
| 20136 | break; |
| 20137 | case 3: |
| 20138 | // ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm... |
| 20139 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 20140 | return; |
| 20141 | break; |
| 20142 | case 4: |
| 20143 | // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| 20144 | O << ", "; |
| 20145 | break; |
| 20146 | case 5: |
| 20147 | // ADDHNB_ZZZ_H, ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FMAXNM_VG2_2ZZ_S, FMAXNM_V... |
| 20148 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 20149 | break; |
| 20150 | case 6: |
| 20151 | // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_CPA, ADD_Z... |
| 20152 | O << "/m, "; |
| 20153 | break; |
| 20154 | case 7: |
| 20155 | // ADDP_ZPmZ_H, ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_... |
| 20156 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 20157 | break; |
| 20158 | case 8: |
| 20159 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H... |
| 20160 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 20161 | return; |
| 20162 | break; |
| 20163 | case 9: |
| 20164 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, ASR_WIDE_ZZZ_H, FMAXNM_VG2_2ZZ_D, FMAXNM... |
| 20165 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 20166 | break; |
| 20167 | case 10: |
| 20168 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| 20169 | printTypedVectorList<0,'d'>(MI, OpNum: 4, STI, O); |
| 20170 | break; |
| 20171 | case 11: |
| 20172 | // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| 20173 | printTypedVectorList<0,'s'>(MI, OpNum: 4, STI, O); |
| 20174 | break; |
| 20175 | case 12: |
| 20176 | // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| 20177 | printImm8OptLsl<uint16_t>(MI, OpNum: 2, STI, O); |
| 20178 | return; |
| 20179 | break; |
| 20180 | case 13: |
| 20181 | // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... |
| 20182 | O << "/z, "; |
| 20183 | break; |
| 20184 | case 14: |
| 20185 | // ASR_ZZI_H, GLD1B_D, GLD1B_D_SXTW, GLD1B_D_UXTW, GLD1B_S_SXTW, GLD1B_S_... |
| 20186 | printOperand(MI, OpNo: 2, STI, O); |
| 20187 | break; |
| 20188 | case 15: |
| 20189 | // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG2_M2ZZ... |
| 20190 | printTypedVectorList<0,'h'>(MI, OpNum: 4, STI, O); |
| 20191 | break; |
| 20192 | case 16: |
| 20193 | // BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA_ZPmZZ, BFML... |
| 20194 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 20195 | break; |
| 20196 | case 17: |
| 20197 | // BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG4_4Z2Z_H, BFMAX_VG2_2Z2Z_H, BFMAX_VG4_4Z... |
| 20198 | printTypedVectorList<0,'h'>(MI, OpNum: 2, STI, O); |
| 20199 | break; |
| 20200 | case 18: |
| 20201 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ... |
| 20202 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 20203 | O << ", "; |
| 20204 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 20205 | break; |
| 20206 | case 19: |
| 20207 | // BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S |
| 20208 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 20209 | return; |
| 20210 | break; |
| 20211 | case 20: |
| 20212 | // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| 20213 | O << ", ["; |
| 20214 | break; |
| 20215 | case 21: |
| 20216 | // CMEQv16i8rz, CMEQv1i64rz, CMEQv2i32rz, CMEQv2i64rz, CMEQv4i16rz, CMEQv... |
| 20217 | O << ", #0"; |
| 20218 | return; |
| 20219 | break; |
| 20220 | case 22: |
| 20221 | // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| 20222 | O << ", mul "; |
| 20223 | printOperand(MI, OpNo: 2, STI, O); |
| 20224 | return; |
| 20225 | break; |
| 20226 | case 23: |
| 20227 | // CPY_ZPmI_B |
| 20228 | printImm8OptLsl<int8_t>(MI, OpNum: 3, STI, O); |
| 20229 | return; |
| 20230 | break; |
| 20231 | case 24: |
| 20232 | // CPY_ZPmI_D |
| 20233 | printImm8OptLsl<int64_t>(MI, OpNum: 3, STI, O); |
| 20234 | return; |
| 20235 | break; |
| 20236 | case 25: |
| 20237 | // CPY_ZPmI_S |
| 20238 | printImm8OptLsl<int32_t>(MI, OpNum: 3, STI, O); |
| 20239 | return; |
| 20240 | break; |
| 20241 | case 26: |
| 20242 | // CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S... |
| 20243 | printOperand(MI, OpNo: 3, STI, O); |
| 20244 | break; |
| 20245 | case 27: |
| 20246 | // CPY_ZPzI_H |
| 20247 | printImm8OptLsl<int16_t>(MI, OpNum: 2, STI, O); |
| 20248 | return; |
| 20249 | break; |
| 20250 | case 28: |
| 20251 | // DUPQ_ZZI_B, DUPQ_ZZI_D, DUPQ_ZZI_S, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, D... |
| 20252 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20253 | return; |
| 20254 | break; |
| 20255 | case 29: |
| 20256 | // EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S |
| 20257 | printMatrixTileVector<0>(MI, OpNum: 3, STI, O); |
| 20258 | O << '['; |
| 20259 | printOperand(MI, OpNo: 4, STI, O); |
| 20260 | O << ", "; |
| 20261 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 20262 | O << ']'; |
| 20263 | return; |
| 20264 | break; |
| 20265 | case 30: |
| 20266 | // EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S |
| 20267 | printMatrixTileVector<1>(MI, OpNum: 3, STI, O); |
| 20268 | O << '['; |
| 20269 | printOperand(MI, OpNo: 4, STI, O); |
| 20270 | O << ", "; |
| 20271 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 20272 | O << ']'; |
| 20273 | return; |
| 20274 | break; |
| 20275 | case 31: |
| 20276 | // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H |
| 20277 | printImm(MI, OpNo: 2, STI, O); |
| 20278 | return; |
| 20279 | break; |
| 20280 | case 32: |
| 20281 | // FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D, FAMIN_4Z4Z_D, FMAXNM_VG2_2Z2... |
| 20282 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 20283 | break; |
| 20284 | case 33: |
| 20285 | // FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S, FAMIN_4Z4Z_S, FMAXNM_VG2_2Z2... |
| 20286 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 20287 | break; |
| 20288 | case 34: |
| 20289 | // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMEQv2i32rz, FCMEQv2i64rz, ... |
| 20290 | O << ", #0.0"; |
| 20291 | return; |
| 20292 | break; |
| 20293 | case 35: |
| 20294 | // FCPY_ZPmI_D, FCPY_ZPmI_S |
| 20295 | printFPImmOperand(MI, OpNum: 3, STI, O); |
| 20296 | return; |
| 20297 | break; |
| 20298 | case 36: |
| 20299 | // FCVTLv2i32 |
| 20300 | O << ".2s"; |
| 20301 | return; |
| 20302 | break; |
| 20303 | case 37: |
| 20304 | // FCVTLv4i16 |
| 20305 | O << ".4h"; |
| 20306 | return; |
| 20307 | break; |
| 20308 | case 38: |
| 20309 | // FCVTLv4i32, FCVTNv8i16 |
| 20310 | O << ".4s"; |
| 20311 | return; |
| 20312 | break; |
| 20313 | case 39: |
| 20314 | // FCVTLv8i16 |
| 20315 | O << ".8h"; |
| 20316 | return; |
| 20317 | break; |
| 20318 | case 40: |
| 20319 | // FCVTN_F16_F8v16f8 |
| 20320 | O << ".8h, "; |
| 20321 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 20322 | O << ".8h"; |
| 20323 | return; |
| 20324 | break; |
| 20325 | case 41: |
| 20326 | // FCVTN_F16_F8v8f8 |
| 20327 | O << ".4h, "; |
| 20328 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 20329 | O << ".4h"; |
| 20330 | return; |
| 20331 | break; |
| 20332 | case 42: |
| 20333 | // FCVTN_F32_F8v8f8 |
| 20334 | O << ".4s, "; |
| 20335 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 20336 | O << ".4s"; |
| 20337 | return; |
| 20338 | break; |
| 20339 | case 43: |
| 20340 | // FCVTNv4i32, FCVTXNv4f32 |
| 20341 | O << ".2d"; |
| 20342 | return; |
| 20343 | break; |
| 20344 | case 44: |
| 20345 | // FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG2_M2ZZI_BtoH, FDOT_VG... |
| 20346 | printTypedVectorList<0,'b'>(MI, OpNum: 4, STI, O); |
| 20347 | O << ", "; |
| 20348 | break; |
| 20349 | case 45: |
| 20350 | // FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLAL_MZZI_BtoH, FMLAL_VG2_MZZ_BtoH... |
| 20351 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 20352 | O << ", "; |
| 20353 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 20354 | break; |
| 20355 | case 46: |
| 20356 | // FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| 20357 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 20358 | return; |
| 20359 | break; |
| 20360 | case 47: |
| 20361 | // GCSSTR, GCSSTTR, LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDAPURbi, LDAPURdi, L... |
| 20362 | O << ']'; |
| 20363 | return; |
| 20364 | break; |
| 20365 | case 48: |
| 20366 | // INDEX_II_B |
| 20367 | printSImm<8>(MI, OpNo: 2, STI, O); |
| 20368 | return; |
| 20369 | break; |
| 20370 | case 49: |
| 20371 | // INDEX_RI_H |
| 20372 | printSImm<16>(MI, OpNo: 2, STI, O); |
| 20373 | return; |
| 20374 | break; |
| 20375 | case 50: |
| 20376 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 20377 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 20378 | O << "], "; |
| 20379 | printSVERegOp<>(MI, OpNum: 4, STI, O); |
| 20380 | O << "/m, "; |
| 20381 | break; |
| 20382 | case 51: |
| 20383 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED... |
| 20384 | O << "/z, ["; |
| 20385 | printOperand(MI, OpNo: 2, STI, O); |
| 20386 | O << ", "; |
| 20387 | break; |
| 20388 | case 52: |
| 20389 | // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| 20390 | printMatrixIndex(MI, OpNum: 2, STI, O); |
| 20391 | O << "]}, "; |
| 20392 | printSVERegOp<>(MI, OpNum: 3, STI, O); |
| 20393 | break; |
| 20394 | case 53: |
| 20395 | // LDAPRWpost |
| 20396 | O << "], #4"; |
| 20397 | return; |
| 20398 | break; |
| 20399 | case 54: |
| 20400 | // LDAPRXpost |
| 20401 | O << "], #8"; |
| 20402 | return; |
| 20403 | break; |
| 20404 | case 55: |
| 20405 | // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| 20406 | O << "], "; |
| 20407 | break; |
| 20408 | case 56: |
| 20409 | // LUT2v16f8, LUT4v16f8 |
| 20410 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20411 | return; |
| 20412 | break; |
| 20413 | case 57: |
| 20414 | // LUTI2_2ZTZI_B, LUTI2_2ZTZI_H, LUTI2_2ZTZI_S, LUTI2_4ZTZI_B, LUTI2_4ZTZ... |
| 20415 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 20416 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20417 | return; |
| 20418 | break; |
| 20419 | case 58: |
| 20420 | // LUTI4_4ZZT2Z, LUTI4_S_4ZZT2Z |
| 20421 | printTypedVectorList<0,0>(MI, OpNum: 2, STI, O); |
| 20422 | return; |
| 20423 | break; |
| 20424 | case 59: |
| 20425 | // MOVA_MXI2Z_H_B, MOVA_MXI2Z_H_D, MOVA_MXI2Z_H_H, MOVA_MXI2Z_H_S, MOVA_M... |
| 20426 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 20427 | O << "], "; |
| 20428 | break; |
| 20429 | case 60: |
| 20430 | // MOVA_MXI4Z_H_B, MOVA_MXI4Z_H_D, MOVA_MXI4Z_H_H, MOVA_MXI4Z_H_S, MOVA_M... |
| 20431 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 20432 | O << "], "; |
| 20433 | break; |
| 20434 | case 61: |
| 20435 | // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| 20436 | printShifter(MI, OpNum: 2, STI, O); |
| 20437 | return; |
| 20438 | break; |
| 20439 | case 62: |
| 20440 | // MOVT_XTI |
| 20441 | O << '['; |
| 20442 | printMatrixIndex<8>(MI, OpNum: 2, STI, O); |
| 20443 | O << ']'; |
| 20444 | return; |
| 20445 | break; |
| 20446 | case 63: |
| 20447 | // PRFB_D_SCALED |
| 20448 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 20449 | O << ']'; |
| 20450 | return; |
| 20451 | break; |
| 20452 | case 64: |
| 20453 | // PRFB_D_SXTW_SCALED |
| 20454 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20455 | O << ']'; |
| 20456 | return; |
| 20457 | break; |
| 20458 | case 65: |
| 20459 | // PRFB_D_UXTW_SCALED |
| 20460 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20461 | O << ']'; |
| 20462 | return; |
| 20463 | break; |
| 20464 | case 66: |
| 20465 | // PRFB_PRR |
| 20466 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 20467 | O << ']'; |
| 20468 | return; |
| 20469 | break; |
| 20470 | case 67: |
| 20471 | // PRFB_S_SXTW_SCALED |
| 20472 | printRegWithShiftExtend<true, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20473 | O << ']'; |
| 20474 | return; |
| 20475 | break; |
| 20476 | case 68: |
| 20477 | // PRFB_S_UXTW_SCALED |
| 20478 | printRegWithShiftExtend<false, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20479 | O << ']'; |
| 20480 | return; |
| 20481 | break; |
| 20482 | case 69: |
| 20483 | // PRFD_D_PZI, PRFD_S_PZI |
| 20484 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 20485 | O << ']'; |
| 20486 | return; |
| 20487 | break; |
| 20488 | case 70: |
| 20489 | // PRFD_D_SCALED |
| 20490 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 20491 | O << ']'; |
| 20492 | return; |
| 20493 | break; |
| 20494 | case 71: |
| 20495 | // PRFD_D_SXTW_SCALED |
| 20496 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20497 | O << ']'; |
| 20498 | return; |
| 20499 | break; |
| 20500 | case 72: |
| 20501 | // PRFD_D_UXTW_SCALED |
| 20502 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20503 | O << ']'; |
| 20504 | return; |
| 20505 | break; |
| 20506 | case 73: |
| 20507 | // PRFD_PRR |
| 20508 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 3, STI, O); |
| 20509 | O << ']'; |
| 20510 | return; |
| 20511 | break; |
| 20512 | case 74: |
| 20513 | // PRFD_S_SXTW_SCALED |
| 20514 | printRegWithShiftExtend<true, 64, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20515 | O << ']'; |
| 20516 | return; |
| 20517 | break; |
| 20518 | case 75: |
| 20519 | // PRFD_S_UXTW_SCALED |
| 20520 | printRegWithShiftExtend<false, 64, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20521 | O << ']'; |
| 20522 | return; |
| 20523 | break; |
| 20524 | case 76: |
| 20525 | // PRFH_D_PZI, PRFH_S_PZI |
| 20526 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 20527 | O << ']'; |
| 20528 | return; |
| 20529 | break; |
| 20530 | case 77: |
| 20531 | // PRFH_D_SCALED |
| 20532 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 20533 | O << ']'; |
| 20534 | return; |
| 20535 | break; |
| 20536 | case 78: |
| 20537 | // PRFH_D_SXTW_SCALED |
| 20538 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20539 | O << ']'; |
| 20540 | return; |
| 20541 | break; |
| 20542 | case 79: |
| 20543 | // PRFH_D_UXTW_SCALED |
| 20544 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20545 | O << ']'; |
| 20546 | return; |
| 20547 | break; |
| 20548 | case 80: |
| 20549 | // PRFH_PRR |
| 20550 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 20551 | O << ']'; |
| 20552 | return; |
| 20553 | break; |
| 20554 | case 81: |
| 20555 | // PRFH_S_SXTW_SCALED |
| 20556 | printRegWithShiftExtend<true, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20557 | O << ']'; |
| 20558 | return; |
| 20559 | break; |
| 20560 | case 82: |
| 20561 | // PRFH_S_UXTW_SCALED |
| 20562 | printRegWithShiftExtend<false, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20563 | O << ']'; |
| 20564 | return; |
| 20565 | break; |
| 20566 | case 83: |
| 20567 | // PRFW_D_PZI, PRFW_S_PZI |
| 20568 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 20569 | O << ']'; |
| 20570 | return; |
| 20571 | break; |
| 20572 | case 84: |
| 20573 | // PRFW_D_SCALED |
| 20574 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 20575 | O << ']'; |
| 20576 | return; |
| 20577 | break; |
| 20578 | case 85: |
| 20579 | // PRFW_D_SXTW_SCALED |
| 20580 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20581 | O << ']'; |
| 20582 | return; |
| 20583 | break; |
| 20584 | case 86: |
| 20585 | // PRFW_D_UXTW_SCALED |
| 20586 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 20587 | O << ']'; |
| 20588 | return; |
| 20589 | break; |
| 20590 | case 87: |
| 20591 | // PRFW_PRR |
| 20592 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 3, STI, O); |
| 20593 | O << ']'; |
| 20594 | return; |
| 20595 | break; |
| 20596 | case 88: |
| 20597 | // PRFW_S_SXTW_SCALED |
| 20598 | printRegWithShiftExtend<true, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20599 | O << ']'; |
| 20600 | return; |
| 20601 | break; |
| 20602 | case 89: |
| 20603 | // PRFW_S_UXTW_SCALED |
| 20604 | printRegWithShiftExtend<false, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 20605 | O << ']'; |
| 20606 | return; |
| 20607 | break; |
| 20608 | case 90: |
| 20609 | // RDFFRS_PPz, RDFFR_PPz |
| 20610 | O << "/z"; |
| 20611 | return; |
| 20612 | break; |
| 20613 | case 91: |
| 20614 | // SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B, SMAX_VG2_2Z2Z_B, SMAX_VG4_4Z4Z_B... |
| 20615 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 20616 | break; |
| 20617 | case 92: |
| 20618 | // SHLLv16i8, SHLLv8i8 |
| 20619 | O << ", #8"; |
| 20620 | return; |
| 20621 | break; |
| 20622 | case 93: |
| 20623 | // SHLLv2i32, SHLLv4i32 |
| 20624 | O << ", #32"; |
| 20625 | return; |
| 20626 | break; |
| 20627 | case 94: |
| 20628 | // SHLLv4i16, SHLLv8i16 |
| 20629 | O << ", #16"; |
| 20630 | return; |
| 20631 | break; |
| 20632 | case 95: |
| 20633 | // STLRWpre |
| 20634 | O << ", #-4]!"; |
| 20635 | return; |
| 20636 | break; |
| 20637 | case 96: |
| 20638 | // STLRXpre |
| 20639 | O << ", #-8]!"; |
| 20640 | return; |
| 20641 | break; |
| 20642 | case 97: |
| 20643 | // SYSPxt |
| 20644 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 4, STI, O); |
| 20645 | return; |
| 20646 | break; |
| 20647 | case 98: |
| 20648 | // SYSPxt_XZR |
| 20649 | printSyspXzrPair(MI, OpNum: 4, STI, O); |
| 20650 | return; |
| 20651 | break; |
| 20652 | case 99: |
| 20653 | // SYSxt |
| 20654 | printOperand(MI, OpNo: 4, STI, O); |
| 20655 | return; |
| 20656 | break; |
| 20657 | case 100: |
| 20658 | // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBXv16i8Four, T... |
| 20659 | O << ".16b"; |
| 20660 | return; |
| 20661 | break; |
| 20662 | case 101: |
| 20663 | // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i... |
| 20664 | O << ".8b"; |
| 20665 | return; |
| 20666 | break; |
| 20667 | case 102: |
| 20668 | // TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZZ_Q, ZIP1_Z... |
| 20669 | printSVERegOp<'q'>(MI, OpNum: 2, STI, O); |
| 20670 | return; |
| 20671 | break; |
| 20672 | } |
| 20673 | |
| 20674 | |
| 20675 | // Fragment 4 encoded into 7 bits for 84 unique commands. |
| 20676 | switch ((Bits >> 43) & 127) { |
| 20677 | default: llvm_unreachable("Invalid command number."); |
| 20678 | case 0: |
| 20679 | // ABS_ZPmZ_B, ADDHNB_ZZZ_H, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_H, ADD_VG2_2ZZ_S,... |
| 20680 | return; |
| 20681 | break; |
| 20682 | case 1: |
| 20683 | // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB... |
| 20684 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 20685 | break; |
| 20686 | case 2: |
| 20687 | // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_... |
| 20688 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 20689 | break; |
| 20690 | case 3: |
| 20691 | // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPT_shift, ADDSPL_XXI, ADDS... |
| 20692 | printOperand(MI, OpNo: 2, STI, O); |
| 20693 | break; |
| 20694 | case 4: |
| 20695 | // ADDG, ST2Gi, STGi, STZ2Gi, STZGi, SUBG |
| 20696 | printImmScale<16>(MI, OpNum: 2, STI, O); |
| 20697 | break; |
| 20698 | case 5: |
| 20699 | // ADDHNB_ZZZ_B, ADDQV_VPZ_H, ANDQV_VPZ_H, CNTP_XPP_H, EORQV_VPZ_H, FADDQ... |
| 20700 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 20701 | break; |
| 20702 | case 6: |
| 20703 | // ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADDQV_VPZ_D, ADD_ZPmZ_CPA, ADD_ZPmZ_D, ADD_... |
| 20704 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 20705 | break; |
| 20706 | case 7: |
| 20707 | // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| 20708 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 20709 | break; |
| 20710 | case 8: |
| 20711 | // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| 20712 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 20713 | break; |
| 20714 | case 9: |
| 20715 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1... |
| 20716 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 20717 | break; |
| 20718 | case 10: |
| 20719 | // ADDP_ZPmZ_B, ADDQV_VPZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_... |
| 20720 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 20721 | break; |
| 20722 | case 11: |
| 20723 | // ADDP_ZPmZ_H, ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2... |
| 20724 | O << ", "; |
| 20725 | break; |
| 20726 | case 12: |
| 20727 | // ADDP_ZPmZ_S, ADDQV_VPZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, ANDQV_VPZ_S, AND_ZPmZ... |
| 20728 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 20729 | break; |
| 20730 | case 13: |
| 20731 | // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| 20732 | printAddSubImm(MI, OpNum: 2, STI, O); |
| 20733 | return; |
| 20734 | break; |
| 20735 | case 14: |
| 20736 | // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| 20737 | printShiftedRegister(MI, OpNum: 2, STI, O); |
| 20738 | return; |
| 20739 | break; |
| 20740 | case 15: |
| 20741 | // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| 20742 | printExtendedRegister(MI, OpNum: 2, STI, O); |
| 20743 | return; |
| 20744 | break; |
| 20745 | case 16: |
| 20746 | // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| 20747 | printImm8OptLsl<uint8_t>(MI, OpNum: 2, STI, O); |
| 20748 | return; |
| 20749 | break; |
| 20750 | case 17: |
| 20751 | // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| 20752 | printImm8OptLsl<uint64_t>(MI, OpNum: 2, STI, O); |
| 20753 | return; |
| 20754 | break; |
| 20755 | case 18: |
| 20756 | // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| 20757 | printImm8OptLsl<uint32_t>(MI, OpNum: 2, STI, O); |
| 20758 | return; |
| 20759 | break; |
| 20760 | case 19: |
| 20761 | // ADR_LSL_ZZZ_D_0 |
| 20762 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 20763 | O << ']'; |
| 20764 | return; |
| 20765 | break; |
| 20766 | case 20: |
| 20767 | // ADR_LSL_ZZZ_D_1 |
| 20768 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 20769 | O << ']'; |
| 20770 | return; |
| 20771 | break; |
| 20772 | case 21: |
| 20773 | // ADR_LSL_ZZZ_D_2 |
| 20774 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 20775 | O << ']'; |
| 20776 | return; |
| 20777 | break; |
| 20778 | case 22: |
| 20779 | // ADR_LSL_ZZZ_D_3 |
| 20780 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 20781 | O << ']'; |
| 20782 | return; |
| 20783 | break; |
| 20784 | case 23: |
| 20785 | // ADR_LSL_ZZZ_S_0 |
| 20786 | printRegWithShiftExtend<false, 8, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 20787 | O << ']'; |
| 20788 | return; |
| 20789 | break; |
| 20790 | case 24: |
| 20791 | // ADR_LSL_ZZZ_S_1 |
| 20792 | printRegWithShiftExtend<false, 16, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 20793 | O << ']'; |
| 20794 | return; |
| 20795 | break; |
| 20796 | case 25: |
| 20797 | // ADR_LSL_ZZZ_S_2 |
| 20798 | printRegWithShiftExtend<false, 32, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 20799 | O << ']'; |
| 20800 | return; |
| 20801 | break; |
| 20802 | case 26: |
| 20803 | // ADR_LSL_ZZZ_S_3 |
| 20804 | printRegWithShiftExtend<false, 64, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 20805 | O << ']'; |
| 20806 | return; |
| 20807 | break; |
| 20808 | case 27: |
| 20809 | // ADR_SXTW_ZZZ_D_0 |
| 20810 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20811 | O << ']'; |
| 20812 | return; |
| 20813 | break; |
| 20814 | case 28: |
| 20815 | // ADR_SXTW_ZZZ_D_1 |
| 20816 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20817 | O << ']'; |
| 20818 | return; |
| 20819 | break; |
| 20820 | case 29: |
| 20821 | // ADR_SXTW_ZZZ_D_2 |
| 20822 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20823 | O << ']'; |
| 20824 | return; |
| 20825 | break; |
| 20826 | case 30: |
| 20827 | // ADR_SXTW_ZZZ_D_3 |
| 20828 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20829 | O << ']'; |
| 20830 | return; |
| 20831 | break; |
| 20832 | case 31: |
| 20833 | // ADR_UXTW_ZZZ_D_0 |
| 20834 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20835 | O << ']'; |
| 20836 | return; |
| 20837 | break; |
| 20838 | case 32: |
| 20839 | // ADR_UXTW_ZZZ_D_1 |
| 20840 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20841 | O << ']'; |
| 20842 | return; |
| 20843 | break; |
| 20844 | case 33: |
| 20845 | // ADR_UXTW_ZZZ_D_2 |
| 20846 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20847 | O << ']'; |
| 20848 | return; |
| 20849 | break; |
| 20850 | case 34: |
| 20851 | // ADR_UXTW_ZZZ_D_3 |
| 20852 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 20853 | O << ']'; |
| 20854 | return; |
| 20855 | break; |
| 20856 | case 35: |
| 20857 | // ANDSWri, ANDWri, EORWri, ORRWri |
| 20858 | printLogicalImm<int32_t>(MI, OpNum: 2, STI, O); |
| 20859 | return; |
| 20860 | break; |
| 20861 | case 36: |
| 20862 | // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| 20863 | printLogicalImm<int64_t>(MI, OpNum: 2, STI, O); |
| 20864 | return; |
| 20865 | break; |
| 20866 | case 37: |
| 20867 | // BFMLAL_MZZI_HtoS, BFMLSL_MZZI_HtoS, FMLALL_MZZI_BtoS, FMLAL_MZZI_BtoH,... |
| 20868 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 20869 | return; |
| 20870 | break; |
| 20871 | case 38: |
| 20872 | // BFMLA_ZZZI, BFMLS_ZZZI, CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FDOT_Z... |
| 20873 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 20874 | break; |
| 20875 | case 39: |
| 20876 | // BFMUL_ZZZI, FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H |
| 20877 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20878 | return; |
| 20879 | break; |
| 20880 | case 40: |
| 20881 | // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| 20882 | printOperand(MI, OpNo: 3, STI, O); |
| 20883 | break; |
| 20884 | case 41: |
| 20885 | // CPY_ZPzI_B |
| 20886 | printImm8OptLsl<int8_t>(MI, OpNum: 2, STI, O); |
| 20887 | return; |
| 20888 | break; |
| 20889 | case 42: |
| 20890 | // CPY_ZPzI_D |
| 20891 | printImm8OptLsl<int64_t>(MI, OpNum: 2, STI, O); |
| 20892 | return; |
| 20893 | break; |
| 20894 | case 43: |
| 20895 | // CPY_ZPzI_S |
| 20896 | printImm8OptLsl<int32_t>(MI, OpNum: 2, STI, O); |
| 20897 | return; |
| 20898 | break; |
| 20899 | case 44: |
| 20900 | // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| 20901 | O << ", #0.0"; |
| 20902 | return; |
| 20903 | break; |
| 20904 | case 45: |
| 20905 | // FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG4_M4Z4Z_BtoH, FDOT_VG... |
| 20906 | printTypedVectorList<0,'b'>(MI, OpNum: 5, STI, O); |
| 20907 | return; |
| 20908 | break; |
| 20909 | case 46: |
| 20910 | // FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG2_M2ZZ_BtoH, FDOT_VG2... |
| 20911 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 20912 | break; |
| 20913 | case 47: |
| 20914 | // INDEX_RI_B |
| 20915 | printSImm<8>(MI, OpNo: 2, STI, O); |
| 20916 | return; |
| 20917 | break; |
| 20918 | case 48: |
| 20919 | // INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D |
| 20920 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 20921 | return; |
| 20922 | break; |
| 20923 | case 49: |
| 20924 | // INSERT_MXIPZ_H_H, INSERT_MXIPZ_V_H |
| 20925 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 20926 | return; |
| 20927 | break; |
| 20928 | case 50: |
| 20929 | // INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q |
| 20930 | printSVERegOp<'q'>(MI, OpNum: 5, STI, O); |
| 20931 | return; |
| 20932 | break; |
| 20933 | case 51: |
| 20934 | // INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S |
| 20935 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 20936 | return; |
| 20937 | break; |
| 20938 | case 52: |
| 20939 | // LD1B_2Z_STRIDED, LDNT1B_2Z_STRIDED |
| 20940 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 20941 | O << ']'; |
| 20942 | return; |
| 20943 | break; |
| 20944 | case 53: |
| 20945 | // LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED_IMM, LDNT1... |
| 20946 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 20947 | O << ", mul vl]"; |
| 20948 | return; |
| 20949 | break; |
| 20950 | case 54: |
| 20951 | // LD1H_2Z_STRIDED, LDNT1H_2Z_STRIDED |
| 20952 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 20953 | O << ']'; |
| 20954 | return; |
| 20955 | break; |
| 20956 | case 55: |
| 20957 | // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| 20958 | O << "/z, ["; |
| 20959 | printOperand(MI, OpNo: 4, STI, O); |
| 20960 | O << ", "; |
| 20961 | break; |
| 20962 | case 56: |
| 20963 | // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| 20964 | printOperand(MI, OpNo: 4, STI, O); |
| 20965 | O << ']'; |
| 20966 | return; |
| 20967 | break; |
| 20968 | case 57: |
| 20969 | // LDG, ST2GPostIndex, ST2GPreIndex, STGPostIndex, STGPreIndex, STZ2GPost... |
| 20970 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 20971 | break; |
| 20972 | case 58: |
| 20973 | // LDRAAindexed, LDRABindexed |
| 20974 | printImmScale<8>(MI, OpNum: 2, STI, O); |
| 20975 | O << ']'; |
| 20976 | return; |
| 20977 | break; |
| 20978 | case 59: |
| 20979 | // LDRAAwriteback, LDRABwriteback |
| 20980 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 20981 | O << "]!"; |
| 20982 | return; |
| 20983 | break; |
| 20984 | case 60: |
| 20985 | // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| 20986 | printUImm12Offset<1>(MI, OpNum: 2, STI, O); |
| 20987 | O << ']'; |
| 20988 | return; |
| 20989 | break; |
| 20990 | case 61: |
| 20991 | // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| 20992 | printUImm12Offset<8>(MI, OpNum: 2, STI, O); |
| 20993 | O << ']'; |
| 20994 | return; |
| 20995 | break; |
| 20996 | case 62: |
| 20997 | // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| 20998 | printUImm12Offset<2>(MI, OpNum: 2, STI, O); |
| 20999 | O << ']'; |
| 21000 | return; |
| 21001 | break; |
| 21002 | case 63: |
| 21003 | // LDRQui, STRQui |
| 21004 | printUImm12Offset<16>(MI, OpNum: 2, STI, O); |
| 21005 | O << ']'; |
| 21006 | return; |
| 21007 | break; |
| 21008 | case 64: |
| 21009 | // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| 21010 | printUImm12Offset<4>(MI, OpNum: 2, STI, O); |
| 21011 | O << ']'; |
| 21012 | return; |
| 21013 | break; |
| 21014 | case 65: |
| 21015 | // LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI_B, LUTI2_ZTZI_S, LUTI4_S_... |
| 21016 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 21017 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 21018 | return; |
| 21019 | break; |
| 21020 | case 66: |
| 21021 | // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| 21022 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 21023 | O << ", "; |
| 21024 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 21025 | return; |
| 21026 | break; |
| 21027 | case 67: |
| 21028 | // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q |
| 21029 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 21030 | O << ']'; |
| 21031 | return; |
| 21032 | break; |
| 21033 | case 68: |
| 21034 | // MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZMXI_H_H, MOVA_2ZMXI_H_S, MOVA_2... |
| 21035 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 21036 | O << ']'; |
| 21037 | return; |
| 21038 | break; |
| 21039 | case 69: |
| 21040 | // MOVA_4ZMXI_H_B, MOVA_4ZMXI_H_D, MOVA_4ZMXI_H_H, MOVA_4ZMXI_H_S, MOVA_4... |
| 21041 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 21042 | O << ']'; |
| 21043 | return; |
| 21044 | break; |
| 21045 | case 70: |
| 21046 | // MOVA_MXI2Z_H_B, MOVA_MXI2Z_V_B, MOVA_MXI4Z_H_B, MOVA_MXI4Z_V_B |
| 21047 | printTypedVectorList<0,'b'>(MI, OpNum: 4, STI, O); |
| 21048 | return; |
| 21049 | break; |
| 21050 | case 71: |
| 21051 | // MOVA_MXI2Z_H_D, MOVA_MXI2Z_V_D, MOVA_MXI4Z_H_D, MOVA_MXI4Z_V_D |
| 21052 | printTypedVectorList<0,'d'>(MI, OpNum: 4, STI, O); |
| 21053 | return; |
| 21054 | break; |
| 21055 | case 72: |
| 21056 | // MOVA_MXI2Z_H_H, MOVA_MXI2Z_V_H, MOVA_MXI4Z_H_H, MOVA_MXI4Z_V_H |
| 21057 | printTypedVectorList<0,'h'>(MI, OpNum: 4, STI, O); |
| 21058 | return; |
| 21059 | break; |
| 21060 | case 73: |
| 21061 | // MOVA_MXI2Z_H_S, MOVA_MXI2Z_V_S, MOVA_MXI4Z_H_S, MOVA_MXI4Z_V_S |
| 21062 | printTypedVectorList<0,'s'>(MI, OpNum: 4, STI, O); |
| 21063 | return; |
| 21064 | break; |
| 21065 | case 74: |
| 21066 | // PRFB_D_PZI, PRFB_S_PZI |
| 21067 | O << ']'; |
| 21068 | return; |
| 21069 | break; |
| 21070 | case 75: |
| 21071 | // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| 21072 | O << ", mul vl]"; |
| 21073 | return; |
| 21074 | break; |
| 21075 | case 76: |
| 21076 | // SPLICE_ZPZZ_B |
| 21077 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 21078 | return; |
| 21079 | break; |
| 21080 | case 77: |
| 21081 | // SPLICE_ZPZZ_D |
| 21082 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 21083 | return; |
| 21084 | break; |
| 21085 | case 78: |
| 21086 | // SPLICE_ZPZZ_S |
| 21087 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 21088 | return; |
| 21089 | break; |
| 21090 | case 79: |
| 21091 | // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| 21092 | printGPR64as32(MI, OpNum: 2, STI, O); |
| 21093 | return; |
| 21094 | break; |
| 21095 | case 80: |
| 21096 | // ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX... |
| 21097 | O << ", ["; |
| 21098 | printOperand(MI, OpNo: 4, STI, O); |
| 21099 | O << ", "; |
| 21100 | break; |
| 21101 | case 81: |
| 21102 | // SYSLxt |
| 21103 | printSysCROperand(MI, OpNo: 2, STI, O); |
| 21104 | O << ", "; |
| 21105 | printSysCROperand(MI, OpNo: 3, STI, O); |
| 21106 | O << ", "; |
| 21107 | printOperand(MI, OpNo: 4, STI, O); |
| 21108 | return; |
| 21109 | break; |
| 21110 | case 82: |
| 21111 | // TBNZW, TBNZX, TBZW, TBZX |
| 21112 | printAlignedLabel(MI, Address, OpNum: 2, STI, O); |
| 21113 | return; |
| 21114 | break; |
| 21115 | case 83: |
| 21116 | // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| 21117 | printImm(MI, OpNo: 2, STI, O); |
| 21118 | return; |
| 21119 | break; |
| 21120 | } |
| 21121 | |
| 21122 | |
| 21123 | // Fragment 5 encoded into 7 bits for 72 unique commands. |
| 21124 | switch ((Bits >> 50) & 127) { |
| 21125 | default: llvm_unreachable("Invalid command number."); |
| 21126 | case 0: |
| 21127 | // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| 21128 | return; |
| 21129 | break; |
| 21130 | case 1: |
| 21131 | // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_CPA,... |
| 21132 | O << ", "; |
| 21133 | break; |
| 21134 | case 2: |
| 21135 | // ADDPT_shift, SUBPT_shift |
| 21136 | printShifter(MI, OpNum: 3, STI, O); |
| 21137 | return; |
| 21138 | break; |
| 21139 | case 3: |
| 21140 | // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFADD_ZP... |
| 21141 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 21142 | break; |
| 21143 | case 4: |
| 21144 | // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| 21145 | printArithExtend(MI, OpNum: 3, STI, O); |
| 21146 | return; |
| 21147 | break; |
| 21148 | case 5: |
| 21149 | // ADD_VG2_M2Z2Z_D, ADD_VG4_M4Z4Z_D, FMLA_VG2_M2Z2Z_D, FMLA_VG4_M4Z4Z_D, ... |
| 21150 | printTypedVectorList<0,'d'>(MI, OpNum: 5, STI, O); |
| 21151 | return; |
| 21152 | break; |
| 21153 | case 6: |
| 21154 | // ADD_VG2_M2Z2Z_S, ADD_VG4_M4Z4Z_S, FMLA_VG2_M2Z2Z_S, FMLA_VG4_M4Z4Z_S, ... |
| 21155 | printTypedVectorList<0,'s'>(MI, OpNum: 5, STI, O); |
| 21156 | return; |
| 21157 | break; |
| 21158 | case 7: |
| 21159 | // ADD_VG2_M2ZZ_D, ADD_VG4_M4ZZ_D, FMLA_VG2_M2ZZI_D, FMLA_VG2_M2ZZ_D, FML... |
| 21160 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 21161 | break; |
| 21162 | case 8: |
| 21163 | // ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_S, FMLA_VG2_M2ZZI_S, FMLA_VG2_M2ZZ_S, FML... |
| 21164 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 21165 | break; |
| 21166 | case 9: |
| 21167 | // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| 21168 | printOperand(MI, OpNo: 3, STI, O); |
| 21169 | break; |
| 21170 | case 10: |
| 21171 | // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| 21172 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 21173 | return; |
| 21174 | break; |
| 21175 | case 11: |
| 21176 | // BF16DOTlanev4bf16, BF16DOTlanev8bf16, BFDOT_ZZI, BFMLALB_ZZZI, BFMLALT... |
| 21177 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 21178 | break; |
| 21179 | case 12: |
| 21180 | // BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG4_M4Z4Z_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFM... |
| 21181 | printTypedVectorList<0,'h'>(MI, OpNum: 5, STI, O); |
| 21182 | return; |
| 21183 | break; |
| 21184 | case 13: |
| 21185 | // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFDOT... |
| 21186 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 21187 | break; |
| 21188 | case 14: |
| 21189 | // BFMLA_ZPmZZ, BFMLS_ZPmZZ, FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, F... |
| 21190 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 21191 | break; |
| 21192 | case 15: |
| 21193 | // CADD_ZZI_H, SQCADD_ZZI_H |
| 21194 | printComplexRotationOp<180, 90>(MI, OpNo: 3, STI, O); |
| 21195 | return; |
| 21196 | break; |
| 21197 | case 16: |
| 21198 | // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| 21199 | O << ']'; |
| 21200 | return; |
| 21201 | break; |
| 21202 | case 17: |
| 21203 | // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H |
| 21204 | printComplexRotationOp<90, 0>(MI, OpNo: 4, STI, O); |
| 21205 | return; |
| 21206 | break; |
| 21207 | case 18: |
| 21208 | // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| 21209 | printImm(MI, OpNo: 3, STI, O); |
| 21210 | return; |
| 21211 | break; |
| 21212 | case 19: |
| 21213 | // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| 21214 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 21215 | return; |
| 21216 | break; |
| 21217 | case 20: |
| 21218 | // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| 21219 | O << ", #0.0"; |
| 21220 | return; |
| 21221 | break; |
| 21222 | case 21: |
| 21223 | // FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG4_M4ZZI_BtoH, FDOT_VG... |
| 21224 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 21225 | return; |
| 21226 | break; |
| 21227 | case 22: |
| 21228 | // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| 21229 | printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 21230 | return; |
| 21231 | break; |
| 21232 | case 23: |
| 21233 | // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| 21234 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 21235 | return; |
| 21236 | break; |
| 21237 | case 24: |
| 21238 | // FMUL_ZPmI_H |
| 21239 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, OpNum: 3, STI, O); |
| 21240 | return; |
| 21241 | break; |
| 21242 | case 25: |
| 21243 | // GLD1B_D, GLD1D, GLD1H_D, GLD1SB_D, GLD1SH_D, GLD1SW_D, GLD1W_D, GLDFF1... |
| 21244 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21245 | O << ']'; |
| 21246 | return; |
| 21247 | break; |
| 21248 | case 26: |
| 21249 | // GLD1B_D_SXTW, GLD1D_SXTW, GLD1H_D_SXTW, GLD1SB_D_SXTW, GLD1SH_D_SXTW, ... |
| 21250 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21251 | O << ']'; |
| 21252 | return; |
| 21253 | break; |
| 21254 | case 27: |
| 21255 | // GLD1B_D_UXTW, GLD1D_UXTW, GLD1H_D_UXTW, GLD1SB_D_UXTW, GLD1SH_D_UXTW, ... |
| 21256 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21257 | O << ']'; |
| 21258 | return; |
| 21259 | break; |
| 21260 | case 28: |
| 21261 | // GLD1B_S_SXTW, GLD1H_S_SXTW, GLD1SB_S_SXTW, GLD1SH_S_SXTW, GLD1W_SXTW, ... |
| 21262 | printRegWithShiftExtend<true, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21263 | O << ']'; |
| 21264 | return; |
| 21265 | break; |
| 21266 | case 29: |
| 21267 | // GLD1B_S_UXTW, GLD1H_S_UXTW, GLD1SB_S_UXTW, GLD1SH_S_UXTW, GLD1W_UXTW, ... |
| 21268 | printRegWithShiftExtend<false, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21269 | O << ']'; |
| 21270 | return; |
| 21271 | break; |
| 21272 | case 30: |
| 21273 | // GLD1D_IMM, GLDFF1D_IMM, LD1RD_IMM, SST1D_IMM |
| 21274 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 21275 | O << ']'; |
| 21276 | return; |
| 21277 | break; |
| 21278 | case 31: |
| 21279 | // GLD1D_SCALED, GLDFF1D_SCALED, SST1D_SCALED |
| 21280 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21281 | O << ']'; |
| 21282 | return; |
| 21283 | break; |
| 21284 | case 32: |
| 21285 | // GLD1D_SXTW_SCALED, GLDFF1D_SXTW_SCALED, SST1D_SXTW_SCALED |
| 21286 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21287 | O << ']'; |
| 21288 | return; |
| 21289 | break; |
| 21290 | case 33: |
| 21291 | // GLD1D_UXTW_SCALED, GLDFF1D_UXTW_SCALED, SST1D_UXTW_SCALED |
| 21292 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21293 | O << ']'; |
| 21294 | return; |
| 21295 | break; |
| 21296 | case 34: |
| 21297 | // GLD1H_D_IMM, GLD1H_S_IMM, GLD1SH_D_IMM, GLD1SH_S_IMM, GLDFF1H_D_IMM, G... |
| 21298 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 21299 | break; |
| 21300 | case 35: |
| 21301 | // GLD1H_D_SCALED, GLD1SH_D_SCALED, GLDFF1H_D_SCALED, GLDFF1SH_D_SCALED, ... |
| 21302 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21303 | O << ']'; |
| 21304 | return; |
| 21305 | break; |
| 21306 | case 36: |
| 21307 | // GLD1H_D_SXTW_SCALED, GLD1SH_D_SXTW_SCALED, GLDFF1H_D_SXTW_SCALED, GLDF... |
| 21308 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21309 | O << ']'; |
| 21310 | return; |
| 21311 | break; |
| 21312 | case 37: |
| 21313 | // GLD1H_D_UXTW_SCALED, GLD1SH_D_UXTW_SCALED, GLDFF1H_D_UXTW_SCALED, GLDF... |
| 21314 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21315 | O << ']'; |
| 21316 | return; |
| 21317 | break; |
| 21318 | case 38: |
| 21319 | // GLD1H_S_SXTW_SCALED, GLD1SH_S_SXTW_SCALED, GLDFF1H_S_SXTW_SCALED, GLDF... |
| 21320 | printRegWithShiftExtend<true, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21321 | O << ']'; |
| 21322 | return; |
| 21323 | break; |
| 21324 | case 39: |
| 21325 | // GLD1H_S_UXTW_SCALED, GLD1SH_S_UXTW_SCALED, GLDFF1H_S_UXTW_SCALED, GLDF... |
| 21326 | printRegWithShiftExtend<false, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21327 | O << ']'; |
| 21328 | return; |
| 21329 | break; |
| 21330 | case 40: |
| 21331 | // GLD1SW_D_IMM, GLD1W_D_IMM, GLD1W_IMM, GLDFF1SW_D_IMM, GLDFF1W_D_IMM, G... |
| 21332 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 21333 | break; |
| 21334 | case 41: |
| 21335 | // GLD1SW_D_SCALED, GLD1W_D_SCALED, GLDFF1SW_D_SCALED, GLDFF1W_D_SCALED, ... |
| 21336 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21337 | O << ']'; |
| 21338 | return; |
| 21339 | break; |
| 21340 | case 42: |
| 21341 | // GLD1SW_D_SXTW_SCALED, GLD1W_D_SXTW_SCALED, GLDFF1SW_D_SXTW_SCALED, GLD... |
| 21342 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21343 | O << ']'; |
| 21344 | return; |
| 21345 | break; |
| 21346 | case 43: |
| 21347 | // GLD1SW_D_UXTW_SCALED, GLD1W_D_UXTW_SCALED, GLDFF1SW_D_UXTW_SCALED, GLD... |
| 21348 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21349 | O << ']'; |
| 21350 | return; |
| 21351 | break; |
| 21352 | case 44: |
| 21353 | // GLD1W_SXTW_SCALED, GLDFF1W_SXTW_SCALED, SST1W_SXTW_SCALED |
| 21354 | printRegWithShiftExtend<true, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21355 | O << ']'; |
| 21356 | return; |
| 21357 | break; |
| 21358 | case 45: |
| 21359 | // GLD1W_UXTW_SCALED, GLDFF1W_UXTW_SCALED, SST1W_UXTW_SCALED |
| 21360 | printRegWithShiftExtend<false, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21361 | O << ']'; |
| 21362 | return; |
| 21363 | break; |
| 21364 | case 46: |
| 21365 | // LD1B, LD1B_2Z, LD1B_4Z, LD1B_4Z_STRIDED, LD1B_D, LD1B_H, LD1B_S, LD1RO... |
| 21366 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21367 | O << ']'; |
| 21368 | return; |
| 21369 | break; |
| 21370 | case 47: |
| 21371 | // LD1D, LD1D_2Z, LD1D_2Z_STRIDED, LD1D_4Z, LD1D_4Z_STRIDED, LD1D_Q, LD1R... |
| 21372 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21373 | O << ']'; |
| 21374 | return; |
| 21375 | break; |
| 21376 | case 48: |
| 21377 | // LD1H, LD1H_2Z, LD1H_4Z, LD1H_4Z_STRIDED, LD1H_D, LD1H_S, LD1RO_H, LD1R... |
| 21378 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21379 | O << ']'; |
| 21380 | return; |
| 21381 | break; |
| 21382 | case 49: |
| 21383 | // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM |
| 21384 | printImmScale<32>(MI, OpNum: 3, STI, O); |
| 21385 | O << ']'; |
| 21386 | return; |
| 21387 | break; |
| 21388 | case 50: |
| 21389 | // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_2Z, LD1W_2Z_STRIDED, LD1W_4Z, LD... |
| 21390 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21391 | O << ']'; |
| 21392 | return; |
| 21393 | break; |
| 21394 | case 51: |
| 21395 | // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM |
| 21396 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 21397 | O << ']'; |
| 21398 | return; |
| 21399 | break; |
| 21400 | case 52: |
| 21401 | // LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B |
| 21402 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 5, STI, O); |
| 21403 | O << ']'; |
| 21404 | return; |
| 21405 | break; |
| 21406 | case 53: |
| 21407 | // LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D |
| 21408 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 5, STI, O); |
| 21409 | O << ']'; |
| 21410 | return; |
| 21411 | break; |
| 21412 | case 54: |
| 21413 | // LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H |
| 21414 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 5, STI, O); |
| 21415 | O << ']'; |
| 21416 | return; |
| 21417 | break; |
| 21418 | case 55: |
| 21419 | // LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q |
| 21420 | printRegWithShiftExtend<false, 128, 'x', 0>(MI, OpNum: 5, STI, O); |
| 21421 | O << ']'; |
| 21422 | return; |
| 21423 | break; |
| 21424 | case 56: |
| 21425 | // LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S |
| 21426 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 5, STI, O); |
| 21427 | O << ']'; |
| 21428 | return; |
| 21429 | break; |
| 21430 | case 57: |
| 21431 | // LD2Q, LD3Q, LD4Q, ST2Q, ST3Q, ST4Q |
| 21432 | printRegWithShiftExtend<false, 128, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21433 | O << ']'; |
| 21434 | return; |
| 21435 | break; |
| 21436 | case 58: |
| 21437 | // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3Q_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ... |
| 21438 | printImmScale<3>(MI, OpNum: 3, STI, O); |
| 21439 | O << ", mul vl]"; |
| 21440 | return; |
| 21441 | break; |
| 21442 | case 59: |
| 21443 | // LDIAPPWpost |
| 21444 | O << "], #8"; |
| 21445 | return; |
| 21446 | break; |
| 21447 | case 60: |
| 21448 | // LDIAPPXpost |
| 21449 | O << "], #16"; |
| 21450 | return; |
| 21451 | break; |
| 21452 | case 61: |
| 21453 | // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,... |
| 21454 | O << "], "; |
| 21455 | break; |
| 21456 | case 62: |
| 21457 | // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... |
| 21458 | O << "]!"; |
| 21459 | return; |
| 21460 | break; |
| 21461 | case 63: |
| 21462 | // LDR_PXI, LDR_ZXI, STR_PXI, STR_ZXI |
| 21463 | O << ", mul vl]"; |
| 21464 | return; |
| 21465 | break; |
| 21466 | case 64: |
| 21467 | // PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S |
| 21468 | O << '['; |
| 21469 | printOperand(MI, OpNo: 3, STI, O); |
| 21470 | O << ", "; |
| 21471 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 21472 | O << ']'; |
| 21473 | return; |
| 21474 | break; |
| 21475 | case 65: |
| 21476 | // SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B |
| 21477 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 21478 | return; |
| 21479 | break; |
| 21480 | case 66: |
| 21481 | // SEL_VG2_2ZC2Z2Z_D, SEL_VG4_4ZC4Z4Z_D |
| 21482 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 21483 | return; |
| 21484 | break; |
| 21485 | case 67: |
| 21486 | // SEL_VG2_2ZC2Z2Z_H, SEL_VG4_4ZC4Z4Z_H |
| 21487 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 21488 | return; |
| 21489 | break; |
| 21490 | case 68: |
| 21491 | // SEL_VG2_2ZC2Z2Z_S, SEL_VG4_4ZC4Z4Z_S |
| 21492 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 21493 | return; |
| 21494 | break; |
| 21495 | case 69: |
| 21496 | // STILPWpre |
| 21497 | O << ", #-8]!"; |
| 21498 | return; |
| 21499 | break; |
| 21500 | case 70: |
| 21501 | // STILPXpre |
| 21502 | O << ", #-16]!"; |
| 21503 | return; |
| 21504 | break; |
| 21505 | case 71: |
| 21506 | // STLXPW, STLXPX, STXPW, STXPX |
| 21507 | O << ", ["; |
| 21508 | printOperand(MI, OpNo: 3, STI, O); |
| 21509 | O << ']'; |
| 21510 | return; |
| 21511 | break; |
| 21512 | } |
| 21513 | |
| 21514 | |
| 21515 | // Fragment 6 encoded into 6 bits for 42 unique commands. |
| 21516 | switch ((Bits >> 57) & 63) { |
| 21517 | default: llvm_unreachable("Invalid command number."); |
| 21518 | case 0: |
| 21519 | // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A... |
| 21520 | printOperand(MI, OpNo: 3, STI, O); |
| 21521 | return; |
| 21522 | break; |
| 21523 | case 1: |
| 21524 | // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_... |
| 21525 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 21526 | return; |
| 21527 | break; |
| 21528 | case 2: |
| 21529 | // ADDP_ZPmZ_D, ADD_ZPmZ_CPA, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WI... |
| 21530 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 21531 | break; |
| 21532 | case 3: |
| 21533 | // ADDP_ZPmZ_H, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_D, ADD_VG4_M... |
| 21534 | return; |
| 21535 | break; |
| 21536 | case 4: |
| 21537 | // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ... |
| 21538 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 21539 | break; |
| 21540 | case 5: |
| 21541 | // BCAX, EOR3, SM3SS1 |
| 21542 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 21543 | return; |
| 21544 | break; |
| 21545 | case 6: |
| 21546 | // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFMLAL_VG2_M2ZZI_HtoS, BFM... |
| 21547 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 21548 | return; |
| 21549 | break; |
| 21550 | case 7: |
| 21551 | // BFMWri, BFMXri |
| 21552 | printOperand(MI, OpNo: 4, STI, O); |
| 21553 | return; |
| 21554 | break; |
| 21555 | case 8: |
| 21556 | // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16... |
| 21557 | printComplexRotationOp<180, 90>(MI, OpNo: 3, STI, O); |
| 21558 | return; |
| 21559 | break; |
| 21560 | case 9: |
| 21561 | // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| 21562 | printCondCode(MI, OpNum: 3, STI, O); |
| 21563 | return; |
| 21564 | break; |
| 21565 | case 10: |
| 21566 | // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, F... |
| 21567 | O << ", "; |
| 21568 | break; |
| 21569 | case 11: |
| 21570 | // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H |
| 21571 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 21572 | return; |
| 21573 | break; |
| 21574 | case 12: |
| 21575 | // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16... |
| 21576 | printComplexRotationOp<90, 0>(MI, OpNo: 4, STI, O); |
| 21577 | return; |
| 21578 | break; |
| 21579 | case 13: |
| 21580 | // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H |
| 21581 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 21582 | return; |
| 21583 | break; |
| 21584 | case 14: |
| 21585 | // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| 21586 | printImm(MI, OpNo: 3, STI, O); |
| 21587 | return; |
| 21588 | break; |
| 21589 | case 15: |
| 21590 | // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| 21591 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 21592 | return; |
| 21593 | break; |
| 21594 | case 16: |
| 21595 | // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| 21596 | printSVERegOp<'d'>(MI, OpNum: 4, STI, O); |
| 21597 | break; |
| 21598 | case 17: |
| 21599 | // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| 21600 | printSVERegOp<'s'>(MI, OpNum: 4, STI, O); |
| 21601 | break; |
| 21602 | case 18: |
| 21603 | // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| 21604 | printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 21605 | return; |
| 21606 | break; |
| 21607 | case 19: |
| 21608 | // FMUL_ZPmI_D, FMUL_ZPmI_S |
| 21609 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, OpNum: 3, STI, O); |
| 21610 | return; |
| 21611 | break; |
| 21612 | case 20: |
| 21613 | // GLD1B_D_IMM, GLD1B_S_IMM, GLD1H_D_IMM, GLD1H_S_IMM, GLD1Q, GLD1SB_D_IM... |
| 21614 | O << ']'; |
| 21615 | return; |
| 21616 | break; |
| 21617 | case 21: |
| 21618 | // LD1B_2Z_IMM, LD1B_4Z_IMM, LD1B_4Z_STRIDED_IMM, LD1B_D_IMM, LD1B_H_IMM,... |
| 21619 | O << ", mul vl]"; |
| 21620 | return; |
| 21621 | break; |
| 21622 | case 22: |
| 21623 | // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi |
| 21624 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 21625 | O << ']'; |
| 21626 | return; |
| 21627 | break; |
| 21628 | case 23: |
| 21629 | // LDNPQi, LDPQi, STGPi, STNPQi, STPQi |
| 21630 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 21631 | O << ']'; |
| 21632 | return; |
| 21633 | break; |
| 21634 | case 24: |
| 21635 | // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| 21636 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 21637 | O << ']'; |
| 21638 | return; |
| 21639 | break; |
| 21640 | case 25: |
| 21641 | // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... |
| 21642 | printImmScale<8>(MI, OpNum: 4, STI, O); |
| 21643 | break; |
| 21644 | case 26: |
| 21645 | // LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre |
| 21646 | printImmScale<16>(MI, OpNum: 4, STI, O); |
| 21647 | break; |
| 21648 | case 27: |
| 21649 | // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| 21650 | printImmScale<4>(MI, OpNum: 4, STI, O); |
| 21651 | break; |
| 21652 | case 28: |
| 21653 | // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| 21654 | printMemExtend<'w', 8>(MI, OpNum: 3, STI, O); |
| 21655 | O << ']'; |
| 21656 | return; |
| 21657 | break; |
| 21658 | case 29: |
| 21659 | // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| 21660 | printMemExtend<'x', 8>(MI, OpNum: 3, STI, O); |
| 21661 | O << ']'; |
| 21662 | return; |
| 21663 | break; |
| 21664 | case 30: |
| 21665 | // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| 21666 | printMemExtend<'w', 64>(MI, OpNum: 3, STI, O); |
| 21667 | O << ']'; |
| 21668 | return; |
| 21669 | break; |
| 21670 | case 31: |
| 21671 | // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| 21672 | printMemExtend<'x', 64>(MI, OpNum: 3, STI, O); |
| 21673 | O << ']'; |
| 21674 | return; |
| 21675 | break; |
| 21676 | case 32: |
| 21677 | // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| 21678 | printMemExtend<'w', 16>(MI, OpNum: 3, STI, O); |
| 21679 | O << ']'; |
| 21680 | return; |
| 21681 | break; |
| 21682 | case 33: |
| 21683 | // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| 21684 | printMemExtend<'x', 16>(MI, OpNum: 3, STI, O); |
| 21685 | O << ']'; |
| 21686 | return; |
| 21687 | break; |
| 21688 | case 34: |
| 21689 | // LDRQroW, STRQroW |
| 21690 | printMemExtend<'w', 128>(MI, OpNum: 3, STI, O); |
| 21691 | O << ']'; |
| 21692 | return; |
| 21693 | break; |
| 21694 | case 35: |
| 21695 | // LDRQroX, STRQroX |
| 21696 | printMemExtend<'x', 128>(MI, OpNum: 3, STI, O); |
| 21697 | O << ']'; |
| 21698 | return; |
| 21699 | break; |
| 21700 | case 36: |
| 21701 | // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| 21702 | printMemExtend<'w', 32>(MI, OpNum: 3, STI, O); |
| 21703 | O << ']'; |
| 21704 | return; |
| 21705 | break; |
| 21706 | case 37: |
| 21707 | // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| 21708 | printMemExtend<'x', 32>(MI, OpNum: 3, STI, O); |
| 21709 | O << ']'; |
| 21710 | return; |
| 21711 | break; |
| 21712 | case 38: |
| 21713 | // ST1B_2Z_STRIDED, STNT1B_2Z_STRIDED |
| 21714 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21715 | O << ']'; |
| 21716 | return; |
| 21717 | break; |
| 21718 | case 39: |
| 21719 | // ST1B_2Z_STRIDED_IMM, ST1H_2Z_STRIDED_IMM, STNT1B_2Z_STRIDED_IMM, STNT1... |
| 21720 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 21721 | O << ", mul vl]"; |
| 21722 | return; |
| 21723 | break; |
| 21724 | case 40: |
| 21725 | // ST1H_2Z_STRIDED, STNT1H_2Z_STRIDED |
| 21726 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21727 | O << ']'; |
| 21728 | return; |
| 21729 | break; |
| 21730 | case 41: |
| 21731 | // WHILEGE_CXX_B, WHILEGE_CXX_D, WHILEGE_CXX_H, WHILEGE_CXX_S, WHILEGT_CX... |
| 21732 | printSVEVecLenSpecifier(MI, OpNum: 3, STI, O); |
| 21733 | return; |
| 21734 | break; |
| 21735 | } |
| 21736 | |
| 21737 | switch (MI->getOpcode()) { |
| 21738 | default: llvm_unreachable("Unexpected opcode."); |
| 21739 | case AArch64::ADDP_ZPmZ_D: |
| 21740 | case AArch64::ADDP_ZPmZ_S: |
| 21741 | case AArch64::ADD_ZPmZ_CPA: |
| 21742 | case AArch64::ADD_ZPmZ_D: |
| 21743 | case AArch64::ADD_ZPmZ_S: |
| 21744 | case AArch64::AND_ZPmZ_D: |
| 21745 | case AArch64::AND_ZPmZ_S: |
| 21746 | case AArch64::ASRR_ZPmZ_D: |
| 21747 | case AArch64::ASRR_ZPmZ_S: |
| 21748 | case AArch64::ASR_WIDE_ZPmZ_B: |
| 21749 | case AArch64::ASR_WIDE_ZPmZ_S: |
| 21750 | case AArch64::ASR_ZPmZ_D: |
| 21751 | case AArch64::ASR_ZPmZ_S: |
| 21752 | case AArch64::BCAX_ZZZZ: |
| 21753 | case AArch64::BIC_ZPmZ_D: |
| 21754 | case AArch64::BIC_ZPmZ_S: |
| 21755 | case AArch64::BSL1N_ZZZZ: |
| 21756 | case AArch64::BSL2N_ZZZZ: |
| 21757 | case AArch64::BSL_ZZZZ: |
| 21758 | case AArch64::CLASTA_RPZ_D: |
| 21759 | case AArch64::CLASTA_RPZ_S: |
| 21760 | case AArch64::CLASTA_VPZ_D: |
| 21761 | case AArch64::CLASTA_VPZ_S: |
| 21762 | case AArch64::CLASTA_ZPZ_D: |
| 21763 | case AArch64::CLASTA_ZPZ_S: |
| 21764 | case AArch64::CLASTB_RPZ_D: |
| 21765 | case AArch64::CLASTB_RPZ_S: |
| 21766 | case AArch64::CLASTB_VPZ_D: |
| 21767 | case AArch64::CLASTB_VPZ_S: |
| 21768 | case AArch64::CLASTB_ZPZ_D: |
| 21769 | case AArch64::CLASTB_ZPZ_S: |
| 21770 | case AArch64::CMPEQ_PPzZZ_D: |
| 21771 | case AArch64::CMPEQ_PPzZZ_S: |
| 21772 | case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| 21773 | case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| 21774 | case AArch64::CMPGE_PPzZZ_D: |
| 21775 | case AArch64::CMPGE_PPzZZ_S: |
| 21776 | case AArch64::CMPGE_WIDE_PPzZZ_B: |
| 21777 | case AArch64::CMPGE_WIDE_PPzZZ_S: |
| 21778 | case AArch64::CMPGT_PPzZZ_D: |
| 21779 | case AArch64::CMPGT_PPzZZ_S: |
| 21780 | case AArch64::CMPGT_WIDE_PPzZZ_B: |
| 21781 | case AArch64::CMPGT_WIDE_PPzZZ_S: |
| 21782 | case AArch64::CMPHI_PPzZZ_D: |
| 21783 | case AArch64::CMPHI_PPzZZ_S: |
| 21784 | case AArch64::CMPHI_WIDE_PPzZZ_B: |
| 21785 | case AArch64::CMPHI_WIDE_PPzZZ_S: |
| 21786 | case AArch64::CMPHS_PPzZZ_D: |
| 21787 | case AArch64::CMPHS_PPzZZ_S: |
| 21788 | case AArch64::CMPHS_WIDE_PPzZZ_B: |
| 21789 | case AArch64::CMPHS_WIDE_PPzZZ_S: |
| 21790 | case AArch64::CMPLE_WIDE_PPzZZ_B: |
| 21791 | case AArch64::CMPLE_WIDE_PPzZZ_S: |
| 21792 | case AArch64::CMPLO_WIDE_PPzZZ_B: |
| 21793 | case AArch64::CMPLO_WIDE_PPzZZ_S: |
| 21794 | case AArch64::CMPLS_WIDE_PPzZZ_B: |
| 21795 | case AArch64::CMPLS_WIDE_PPzZZ_S: |
| 21796 | case AArch64::CMPLT_WIDE_PPzZZ_B: |
| 21797 | case AArch64::CMPLT_WIDE_PPzZZ_S: |
| 21798 | case AArch64::CMPNE_PPzZZ_D: |
| 21799 | case AArch64::CMPNE_PPzZZ_S: |
| 21800 | case AArch64::CMPNE_WIDE_PPzZZ_B: |
| 21801 | case AArch64::CMPNE_WIDE_PPzZZ_S: |
| 21802 | case AArch64::EOR3_ZZZZ: |
| 21803 | case AArch64::EOR_ZPmZ_D: |
| 21804 | case AArch64::EOR_ZPmZ_S: |
| 21805 | case AArch64::FABD_ZPmZ_D: |
| 21806 | case AArch64::FABD_ZPmZ_S: |
| 21807 | case AArch64::FACGE_PPzZZ_D: |
| 21808 | case AArch64::FACGE_PPzZZ_S: |
| 21809 | case AArch64::FACGT_PPzZZ_D: |
| 21810 | case AArch64::FACGT_PPzZZ_S: |
| 21811 | case AArch64::FADDP_ZPmZZ_D: |
| 21812 | case AArch64::FADDP_ZPmZZ_S: |
| 21813 | case AArch64::FADD_ZPmZ_D: |
| 21814 | case AArch64::FADD_ZPmZ_S: |
| 21815 | case AArch64::FAMAX_ZPmZ_D: |
| 21816 | case AArch64::FAMAX_ZPmZ_S: |
| 21817 | case AArch64::FAMIN_ZPmZ_D: |
| 21818 | case AArch64::FAMIN_ZPmZ_S: |
| 21819 | case AArch64::FCMEQ_PPzZZ_D: |
| 21820 | case AArch64::FCMEQ_PPzZZ_S: |
| 21821 | case AArch64::FCMGE_PPzZZ_D: |
| 21822 | case AArch64::FCMGE_PPzZZ_S: |
| 21823 | case AArch64::FCMGT_PPzZZ_D: |
| 21824 | case AArch64::FCMGT_PPzZZ_S: |
| 21825 | case AArch64::FCMNE_PPzZZ_D: |
| 21826 | case AArch64::FCMNE_PPzZZ_S: |
| 21827 | case AArch64::FCMUO_PPzZZ_D: |
| 21828 | case AArch64::FCMUO_PPzZZ_S: |
| 21829 | case AArch64::FDIVR_ZPmZ_D: |
| 21830 | case AArch64::FDIVR_ZPmZ_S: |
| 21831 | case AArch64::FDIV_ZPmZ_D: |
| 21832 | case AArch64::FDIV_ZPmZ_S: |
| 21833 | case AArch64::FMAD_ZPmZZ_D: |
| 21834 | case AArch64::FMAD_ZPmZZ_S: |
| 21835 | case AArch64::FMAXNMP_ZPmZZ_D: |
| 21836 | case AArch64::FMAXNMP_ZPmZZ_S: |
| 21837 | case AArch64::FMAXNM_ZPmZ_D: |
| 21838 | case AArch64::FMAXNM_ZPmZ_S: |
| 21839 | case AArch64::FMAXP_ZPmZZ_D: |
| 21840 | case AArch64::FMAXP_ZPmZZ_S: |
| 21841 | case AArch64::FMAX_ZPmZ_D: |
| 21842 | case AArch64::FMAX_ZPmZ_S: |
| 21843 | case AArch64::FMINNMP_ZPmZZ_D: |
| 21844 | case AArch64::FMINNMP_ZPmZZ_S: |
| 21845 | case AArch64::FMINNM_ZPmZ_D: |
| 21846 | case AArch64::FMINNM_ZPmZ_S: |
| 21847 | case AArch64::FMINP_ZPmZZ_D: |
| 21848 | case AArch64::FMINP_ZPmZZ_S: |
| 21849 | case AArch64::FMIN_ZPmZ_D: |
| 21850 | case AArch64::FMIN_ZPmZ_S: |
| 21851 | case AArch64::FMLA_ZPmZZ_D: |
| 21852 | case AArch64::FMLA_ZPmZZ_S: |
| 21853 | case AArch64::FMLS_ZPmZZ_D: |
| 21854 | case AArch64::FMLS_ZPmZZ_S: |
| 21855 | case AArch64::FMSB_ZPmZZ_D: |
| 21856 | case AArch64::FMSB_ZPmZZ_S: |
| 21857 | case AArch64::FMULX_ZPmZ_D: |
| 21858 | case AArch64::FMULX_ZPmZ_S: |
| 21859 | case AArch64::FMUL_ZPmZ_D: |
| 21860 | case AArch64::FMUL_ZPmZ_S: |
| 21861 | case AArch64::FNMAD_ZPmZZ_D: |
| 21862 | case AArch64::FNMAD_ZPmZZ_S: |
| 21863 | case AArch64::FNMLA_ZPmZZ_D: |
| 21864 | case AArch64::FNMLA_ZPmZZ_S: |
| 21865 | case AArch64::FNMLS_ZPmZZ_D: |
| 21866 | case AArch64::FNMLS_ZPmZZ_S: |
| 21867 | case AArch64::FNMSB_ZPmZZ_D: |
| 21868 | case AArch64::FNMSB_ZPmZZ_S: |
| 21869 | case AArch64::FSCALE_ZPmZ_D: |
| 21870 | case AArch64::FSCALE_ZPmZ_S: |
| 21871 | case AArch64::FSUBR_ZPmZ_D: |
| 21872 | case AArch64::FSUBR_ZPmZ_S: |
| 21873 | case AArch64::FSUB_ZPmZ_D: |
| 21874 | case AArch64::FSUB_ZPmZ_S: |
| 21875 | case AArch64::HISTCNT_ZPzZZ_D: |
| 21876 | case AArch64::HISTCNT_ZPzZZ_S: |
| 21877 | case AArch64::LDPDpost: |
| 21878 | case AArch64::LDPQpost: |
| 21879 | case AArch64::LDPSWpost: |
| 21880 | case AArch64::LDPSpost: |
| 21881 | case AArch64::LDPWpost: |
| 21882 | case AArch64::LDPXpost: |
| 21883 | case AArch64::LSLR_ZPmZ_D: |
| 21884 | case AArch64::LSLR_ZPmZ_S: |
| 21885 | case AArch64::LSL_WIDE_ZPmZ_B: |
| 21886 | case AArch64::LSL_WIDE_ZPmZ_S: |
| 21887 | case AArch64::LSL_ZPmZ_D: |
| 21888 | case AArch64::LSL_ZPmZ_S: |
| 21889 | case AArch64::LSRR_ZPmZ_D: |
| 21890 | case AArch64::LSRR_ZPmZ_S: |
| 21891 | case AArch64::LSR_WIDE_ZPmZ_B: |
| 21892 | case AArch64::LSR_WIDE_ZPmZ_S: |
| 21893 | case AArch64::LSR_ZPmZ_D: |
| 21894 | case AArch64::LSR_ZPmZ_S: |
| 21895 | case AArch64::MAD_ZPmZZ_D: |
| 21896 | case AArch64::MAD_ZPmZZ_S: |
| 21897 | case AArch64::MLA_ZPmZZ_D: |
| 21898 | case AArch64::MLA_ZPmZZ_S: |
| 21899 | case AArch64::MLS_ZPmZZ_D: |
| 21900 | case AArch64::MLS_ZPmZZ_S: |
| 21901 | case AArch64::MSB_ZPmZZ_D: |
| 21902 | case AArch64::MSB_ZPmZZ_S: |
| 21903 | case AArch64::MUL_ZPmZ_D: |
| 21904 | case AArch64::MUL_ZPmZ_S: |
| 21905 | case AArch64::NBSL_ZZZZ: |
| 21906 | case AArch64::ORR_ZPmZ_D: |
| 21907 | case AArch64::ORR_ZPmZ_S: |
| 21908 | case AArch64::SABD_ZPmZ_D: |
| 21909 | case AArch64::SABD_ZPmZ_S: |
| 21910 | case AArch64::SDIVR_ZPmZ_D: |
| 21911 | case AArch64::SDIVR_ZPmZ_S: |
| 21912 | case AArch64::SDIV_ZPmZ_D: |
| 21913 | case AArch64::SDIV_ZPmZ_S: |
| 21914 | case AArch64::SEL_ZPZZ_D: |
| 21915 | case AArch64::SEL_ZPZZ_S: |
| 21916 | case AArch64::SHADD_ZPmZ_D: |
| 21917 | case AArch64::SHADD_ZPmZ_S: |
| 21918 | case AArch64::SHSUBR_ZPmZ_D: |
| 21919 | case AArch64::SHSUBR_ZPmZ_S: |
| 21920 | case AArch64::SHSUB_ZPmZ_D: |
| 21921 | case AArch64::SHSUB_ZPmZ_S: |
| 21922 | case AArch64::SMAXP_ZPmZ_D: |
| 21923 | case AArch64::SMAXP_ZPmZ_S: |
| 21924 | case AArch64::SMAX_ZPmZ_D: |
| 21925 | case AArch64::SMAX_ZPmZ_S: |
| 21926 | case AArch64::SMINP_ZPmZ_D: |
| 21927 | case AArch64::SMINP_ZPmZ_S: |
| 21928 | case AArch64::SMIN_ZPmZ_D: |
| 21929 | case AArch64::SMIN_ZPmZ_S: |
| 21930 | case AArch64::SMULH_ZPmZ_D: |
| 21931 | case AArch64::SMULH_ZPmZ_S: |
| 21932 | case AArch64::SPLICE_ZPZ_D: |
| 21933 | case AArch64::SPLICE_ZPZ_S: |
| 21934 | case AArch64::SQADD_ZPmZ_D: |
| 21935 | case AArch64::SQADD_ZPmZ_S: |
| 21936 | case AArch64::SQRSHLR_ZPmZ_D: |
| 21937 | case AArch64::SQRSHLR_ZPmZ_S: |
| 21938 | case AArch64::SQRSHL_ZPmZ_D: |
| 21939 | case AArch64::SQRSHL_ZPmZ_S: |
| 21940 | case AArch64::SQSHLR_ZPmZ_D: |
| 21941 | case AArch64::SQSHLR_ZPmZ_S: |
| 21942 | case AArch64::SQSHL_ZPmZ_D: |
| 21943 | case AArch64::SQSHL_ZPmZ_S: |
| 21944 | case AArch64::SQSUBR_ZPmZ_D: |
| 21945 | case AArch64::SQSUBR_ZPmZ_S: |
| 21946 | case AArch64::SQSUB_ZPmZ_D: |
| 21947 | case AArch64::SQSUB_ZPmZ_S: |
| 21948 | case AArch64::SRHADD_ZPmZ_D: |
| 21949 | case AArch64::SRHADD_ZPmZ_S: |
| 21950 | case AArch64::SRSHLR_ZPmZ_D: |
| 21951 | case AArch64::SRSHLR_ZPmZ_S: |
| 21952 | case AArch64::SRSHL_ZPmZ_D: |
| 21953 | case AArch64::SRSHL_ZPmZ_S: |
| 21954 | case AArch64::STGPpost: |
| 21955 | case AArch64::STPDpost: |
| 21956 | case AArch64::STPQpost: |
| 21957 | case AArch64::STPSpost: |
| 21958 | case AArch64::STPWpost: |
| 21959 | case AArch64::STPXpost: |
| 21960 | case AArch64::SUBR_ZPmZ_D: |
| 21961 | case AArch64::SUBR_ZPmZ_S: |
| 21962 | case AArch64::SUB_ZPmZ_CPA: |
| 21963 | case AArch64::SUB_ZPmZ_D: |
| 21964 | case AArch64::SUB_ZPmZ_S: |
| 21965 | case AArch64::SUQADD_ZPmZ_D: |
| 21966 | case AArch64::SUQADD_ZPmZ_S: |
| 21967 | case AArch64::UABD_ZPmZ_D: |
| 21968 | case AArch64::UABD_ZPmZ_S: |
| 21969 | case AArch64::UDIVR_ZPmZ_D: |
| 21970 | case AArch64::UDIVR_ZPmZ_S: |
| 21971 | case AArch64::UDIV_ZPmZ_D: |
| 21972 | case AArch64::UDIV_ZPmZ_S: |
| 21973 | case AArch64::UHADD_ZPmZ_D: |
| 21974 | case AArch64::UHADD_ZPmZ_S: |
| 21975 | case AArch64::UHSUBR_ZPmZ_D: |
| 21976 | case AArch64::UHSUBR_ZPmZ_S: |
| 21977 | case AArch64::UHSUB_ZPmZ_D: |
| 21978 | case AArch64::UHSUB_ZPmZ_S: |
| 21979 | case AArch64::UMAXP_ZPmZ_D: |
| 21980 | case AArch64::UMAXP_ZPmZ_S: |
| 21981 | case AArch64::UMAX_ZPmZ_D: |
| 21982 | case AArch64::UMAX_ZPmZ_S: |
| 21983 | case AArch64::UMINP_ZPmZ_D: |
| 21984 | case AArch64::UMINP_ZPmZ_S: |
| 21985 | case AArch64::UMIN_ZPmZ_D: |
| 21986 | case AArch64::UMIN_ZPmZ_S: |
| 21987 | case AArch64::UMULH_ZPmZ_D: |
| 21988 | case AArch64::UMULH_ZPmZ_S: |
| 21989 | case AArch64::UQADD_ZPmZ_D: |
| 21990 | case AArch64::UQADD_ZPmZ_S: |
| 21991 | case AArch64::UQRSHLR_ZPmZ_D: |
| 21992 | case AArch64::UQRSHLR_ZPmZ_S: |
| 21993 | case AArch64::UQRSHL_ZPmZ_D: |
| 21994 | case AArch64::UQRSHL_ZPmZ_S: |
| 21995 | case AArch64::UQSHLR_ZPmZ_D: |
| 21996 | case AArch64::UQSHLR_ZPmZ_S: |
| 21997 | case AArch64::UQSHL_ZPmZ_D: |
| 21998 | case AArch64::UQSHL_ZPmZ_S: |
| 21999 | case AArch64::UQSUBR_ZPmZ_D: |
| 22000 | case AArch64::UQSUBR_ZPmZ_S: |
| 22001 | case AArch64::UQSUB_ZPmZ_D: |
| 22002 | case AArch64::UQSUB_ZPmZ_S: |
| 22003 | case AArch64::URHADD_ZPmZ_D: |
| 22004 | case AArch64::URHADD_ZPmZ_S: |
| 22005 | case AArch64::URSHLR_ZPmZ_D: |
| 22006 | case AArch64::URSHLR_ZPmZ_S: |
| 22007 | case AArch64::URSHL_ZPmZ_D: |
| 22008 | case AArch64::URSHL_ZPmZ_S: |
| 22009 | case AArch64::USQADD_ZPmZ_D: |
| 22010 | case AArch64::USQADD_ZPmZ_S: |
| 22011 | return; |
| 22012 | break; |
| 22013 | case AArch64::CDOT_ZZZI_D: |
| 22014 | case AArch64::CMLA_ZZZI_S: |
| 22015 | case AArch64::FCADD_ZPmZ_H: |
| 22016 | case AArch64::FCMLA_ZPmZZ_H: |
| 22017 | case AArch64::FCMLA_ZZZI_S: |
| 22018 | case AArch64::FCMLAv4f16_indexed: |
| 22019 | case AArch64::FCMLAv4f32_indexed: |
| 22020 | case AArch64::FCMLAv8f16_indexed: |
| 22021 | case AArch64::LDPDpre: |
| 22022 | case AArch64::LDPQpre: |
| 22023 | case AArch64::LDPSWpre: |
| 22024 | case AArch64::LDPSpre: |
| 22025 | case AArch64::LDPWpre: |
| 22026 | case AArch64::LDPXpre: |
| 22027 | case AArch64::SQRDCMLAH_ZZZI_S: |
| 22028 | case AArch64::STGPpre: |
| 22029 | case AArch64::STPDpre: |
| 22030 | case AArch64::STPQpre: |
| 22031 | case AArch64::STPSpre: |
| 22032 | case AArch64::STPWpre: |
| 22033 | case AArch64::STPXpre: |
| 22034 | switch (MI->getOpcode()) { |
| 22035 | default: llvm_unreachable("Unexpected opcode."); |
| 22036 | case AArch64::CDOT_ZZZI_D: |
| 22037 | case AArch64::CMLA_ZZZI_S: |
| 22038 | case AArch64::FCMLA_ZPmZZ_H: |
| 22039 | case AArch64::FCMLA_ZZZI_S: |
| 22040 | case AArch64::FCMLAv4f16_indexed: |
| 22041 | case AArch64::FCMLAv4f32_indexed: |
| 22042 | case AArch64::FCMLAv8f16_indexed: |
| 22043 | case AArch64::SQRDCMLAH_ZZZI_S: |
| 22044 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 22045 | break; |
| 22046 | case AArch64::FCADD_ZPmZ_H: |
| 22047 | printComplexRotationOp<180, 90>(MI, OpNo: 4, STI, O); |
| 22048 | break; |
| 22049 | case AArch64::LDPDpre: |
| 22050 | case AArch64::LDPQpre: |
| 22051 | case AArch64::LDPSWpre: |
| 22052 | case AArch64::LDPSpre: |
| 22053 | case AArch64::LDPWpre: |
| 22054 | case AArch64::LDPXpre: |
| 22055 | case AArch64::STGPpre: |
| 22056 | case AArch64::STPDpre: |
| 22057 | case AArch64::STPQpre: |
| 22058 | case AArch64::STPSpre: |
| 22059 | case AArch64::STPWpre: |
| 22060 | case AArch64::STPXpre: |
| 22061 | O << "]!"; |
| 22062 | break; |
| 22063 | } |
| 22064 | return; |
| 22065 | break; |
| 22066 | case AArch64::FCADD_ZPmZ_D: |
| 22067 | case AArch64::FCADD_ZPmZ_S: |
| 22068 | case AArch64::FCMLA_ZPmZZ_D: |
| 22069 | case AArch64::FCMLA_ZPmZZ_S: |
| 22070 | O << ", "; |
| 22071 | switch (MI->getOpcode()) { |
| 22072 | default: llvm_unreachable("Unexpected opcode."); |
| 22073 | case AArch64::FCADD_ZPmZ_D: |
| 22074 | case AArch64::FCADD_ZPmZ_S: |
| 22075 | printComplexRotationOp<180, 90>(MI, OpNo: 4, STI, O); |
| 22076 | break; |
| 22077 | case AArch64::FCMLA_ZPmZZ_D: |
| 22078 | case AArch64::FCMLA_ZPmZZ_S: |
| 22079 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 22080 | break; |
| 22081 | } |
| 22082 | return; |
| 22083 | break; |
| 22084 | } |
| 22085 | } |
| 22086 | |
| 22087 | |
| 22088 | /// getRegisterName - This method is automatically generated by tblgen |
| 22089 | /// from the register set description. This returns the assembler name |
| 22090 | /// for the specified register. |
| 22091 | const char *AArch64AppleInstPrinter:: |
| 22092 | getRegisterName(MCRegister Reg, unsigned AltIdx) { |
| 22093 | unsigned RegNo = Reg.id(); |
| 22094 | assert(RegNo && RegNo < 701 && "Invalid register number!"); |
| 22095 | |
| 22096 | |
| 22097 | #ifdef __GNUC__ |
| 22098 | #pragma GCC diagnostic push |
| 22099 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 22100 | #endif |
| 22101 | static const char AsmStrsNoRegAltName[] = { |
| 22102 | /* 0 */ "D7_D8_D9_D10\0" |
| 22103 | /* 13 */ "P9_P10\0" |
| 22104 | /* 20 */ "Q7_Q8_Q9_Q10\0" |
| 22105 | /* 33 */ "Z2_Z10\0" |
| 22106 | /* 40 */ "Z7_Z8_Z9_Z10\0" |
| 22107 | /* 53 */ "b10\0" |
| 22108 | /* 57 */ "d10\0" |
| 22109 | /* 61 */ "h10\0" |
| 22110 | /* 65 */ "pn10\0" |
| 22111 | /* 70 */ "p10\0" |
| 22112 | /* 74 */ "q10\0" |
| 22113 | /* 78 */ "s10\0" |
| 22114 | /* 82 */ "w10\0" |
| 22115 | /* 86 */ "x10\0" |
| 22116 | /* 90 */ "z10\0" |
| 22117 | /* 94 */ "D17_D18_D19_D20\0" |
| 22118 | /* 110 */ "Q17_Q18_Q19_Q20\0" |
| 22119 | /* 126 */ "Z17_Z18_Z19_Z20\0" |
| 22120 | /* 142 */ "b20\0" |
| 22121 | /* 146 */ "d20\0" |
| 22122 | /* 150 */ "h20\0" |
| 22123 | /* 154 */ "q20\0" |
| 22124 | /* 158 */ "s20\0" |
| 22125 | /* 162 */ "w20\0" |
| 22126 | /* 166 */ "x20\0" |
| 22127 | /* 170 */ "z20\0" |
| 22128 | /* 174 */ "D27_D28_D29_D30\0" |
| 22129 | /* 190 */ "Q27_Q28_Q29_Q30\0" |
| 22130 | /* 206 */ "Z22_Z30\0" |
| 22131 | /* 214 */ "Z18_Z22_Z26_Z30\0" |
| 22132 | /* 230 */ "Z27_Z28_Z29_Z30\0" |
| 22133 | /* 246 */ "b30\0" |
| 22134 | /* 250 */ "d30\0" |
| 22135 | /* 254 */ "h30\0" |
| 22136 | /* 258 */ "q30\0" |
| 22137 | /* 262 */ "s30\0" |
| 22138 | /* 266 */ "w30\0" |
| 22139 | /* 270 */ "x30\0" |
| 22140 | /* 274 */ "z30\0" |
| 22141 | /* 278 */ "D29_D30_D31_D0\0" |
| 22142 | /* 293 */ "P15_P0\0" |
| 22143 | /* 300 */ "Q29_Q30_Q31_Q0\0" |
| 22144 | /* 315 */ "Z29_Z30_Z31_Z0\0" |
| 22145 | /* 330 */ "b0\0" |
| 22146 | /* 333 */ "d0\0" |
| 22147 | /* 336 */ "h0\0" |
| 22148 | /* 339 */ "pn0\0" |
| 22149 | /* 343 */ "p0\0" |
| 22150 | /* 346 */ "q0\0" |
| 22151 | /* 349 */ "s0\0" |
| 22152 | /* 352 */ "zt0\0" |
| 22153 | /* 356 */ "w0\0" |
| 22154 | /* 359 */ "x0\0" |
| 22155 | /* 362 */ "z0\0" |
| 22156 | /* 365 */ "D8_D9_D10_D11\0" |
| 22157 | /* 379 */ "P10_P11\0" |
| 22158 | /* 387 */ "Q8_Q9_Q10_Q11\0" |
| 22159 | /* 401 */ "W10_W11\0" |
| 22160 | /* 409 */ "X4_X5_X6_X7_X8_X9_X10_X11\0" |
| 22161 | /* 435 */ "Z8_Z9_Z10_Z11\0" |
| 22162 | /* 449 */ "Z3_Z11\0" |
| 22163 | /* 456 */ "b11\0" |
| 22164 | /* 460 */ "d11\0" |
| 22165 | /* 464 */ "h11\0" |
| 22166 | /* 468 */ "pn11\0" |
| 22167 | /* 473 */ "p11\0" |
| 22168 | /* 477 */ "q11\0" |
| 22169 | /* 481 */ "s11\0" |
| 22170 | /* 485 */ "w11\0" |
| 22171 | /* 489 */ "x11\0" |
| 22172 | /* 493 */ "z11\0" |
| 22173 | /* 497 */ "D18_D19_D20_D21\0" |
| 22174 | /* 513 */ "Q18_Q19_Q20_Q21\0" |
| 22175 | /* 529 */ "W20_W21\0" |
| 22176 | /* 537 */ "X14_X15_X16_X17_X18_X19_X20_X21\0" |
| 22177 | /* 569 */ "Z18_Z19_Z20_Z21\0" |
| 22178 | /* 585 */ "b21\0" |
| 22179 | /* 589 */ "d21\0" |
| 22180 | /* 593 */ "h21\0" |
| 22181 | /* 597 */ "q21\0" |
| 22182 | /* 601 */ "s21\0" |
| 22183 | /* 605 */ "w21\0" |
| 22184 | /* 609 */ "x21\0" |
| 22185 | /* 613 */ "z21\0" |
| 22186 | /* 617 */ "D28_D29_D30_D31\0" |
| 22187 | /* 633 */ "Q28_Q29_Q30_Q31\0" |
| 22188 | /* 649 */ "Z28_Z29_Z30_Z31\0" |
| 22189 | /* 665 */ "Z23_Z31\0" |
| 22190 | /* 673 */ "Z19_Z23_Z27_Z31\0" |
| 22191 | /* 689 */ "b31\0" |
| 22192 | /* 693 */ "d31\0" |
| 22193 | /* 697 */ "h31\0" |
| 22194 | /* 701 */ "q31\0" |
| 22195 | /* 705 */ "s31\0" |
| 22196 | /* 709 */ "z31\0" |
| 22197 | /* 713 */ "D30_D31_D0_D1\0" |
| 22198 | /* 727 */ "P0_P1\0" |
| 22199 | /* 733 */ "Q30_Q31_Q0_Q1\0" |
| 22200 | /* 747 */ "W0_W1\0" |
| 22201 | /* 753 */ "X0_X1\0" |
| 22202 | /* 759 */ "Z30_Z31_Z0_Z1\0" |
| 22203 | /* 773 */ "b1\0" |
| 22204 | /* 776 */ "d1\0" |
| 22205 | /* 779 */ "h1\0" |
| 22206 | /* 782 */ "pn1\0" |
| 22207 | /* 786 */ "p1\0" |
| 22208 | /* 789 */ "q1\0" |
| 22209 | /* 792 */ "s1\0" |
| 22210 | /* 795 */ "w1\0" |
| 22211 | /* 798 */ "x1\0" |
| 22212 | /* 801 */ "z1\0" |
| 22213 | /* 804 */ "D9_D10_D11_D12\0" |
| 22214 | /* 819 */ "P11_P12\0" |
| 22215 | /* 827 */ "Q9_Q10_Q11_Q12\0" |
| 22216 | /* 842 */ "Z9_Z10_Z11_Z12\0" |
| 22217 | /* 857 */ "Z4_Z12\0" |
| 22218 | /* 864 */ "Z0_Z4_Z8_Z12\0" |
| 22219 | /* 877 */ "b12\0" |
| 22220 | /* 881 */ "d12\0" |
| 22221 | /* 885 */ "h12\0" |
| 22222 | /* 889 */ "pn12\0" |
| 22223 | /* 894 */ "p12\0" |
| 22224 | /* 898 */ "q12\0" |
| 22225 | /* 902 */ "s12\0" |
| 22226 | /* 906 */ "w12\0" |
| 22227 | /* 910 */ "x12\0" |
| 22228 | /* 914 */ "z12\0" |
| 22229 | /* 918 */ "D19_D20_D21_D22\0" |
| 22230 | /* 934 */ "Q19_Q20_Q21_Q22\0" |
| 22231 | /* 950 */ "Z19_Z20_Z21_Z22\0" |
| 22232 | /* 966 */ "b22\0" |
| 22233 | /* 970 */ "d22\0" |
| 22234 | /* 974 */ "h22\0" |
| 22235 | /* 978 */ "q22\0" |
| 22236 | /* 982 */ "s22\0" |
| 22237 | /* 986 */ "w22\0" |
| 22238 | /* 990 */ "x22\0" |
| 22239 | /* 994 */ "z22\0" |
| 22240 | /* 998 */ "D31_D0_D1_D2\0" |
| 22241 | /* 1011 */ "P1_P2\0" |
| 22242 | /* 1017 */ "Q31_Q0_Q1_Q2\0" |
| 22243 | /* 1030 */ "Z31_Z0_Z1_Z2\0" |
| 22244 | /* 1043 */ "b2\0" |
| 22245 | /* 1046 */ "d2\0" |
| 22246 | /* 1049 */ "h2\0" |
| 22247 | /* 1052 */ "pn2\0" |
| 22248 | /* 1056 */ "p2\0" |
| 22249 | /* 1059 */ "q2\0" |
| 22250 | /* 1062 */ "s2\0" |
| 22251 | /* 1065 */ "w2\0" |
| 22252 | /* 1068 */ "x2\0" |
| 22253 | /* 1071 */ "z2\0" |
| 22254 | /* 1074 */ "D10_D11_D12_D13\0" |
| 22255 | /* 1090 */ "P12_P13\0" |
| 22256 | /* 1098 */ "Q10_Q11_Q12_Q13\0" |
| 22257 | /* 1114 */ "W12_W13\0" |
| 22258 | /* 1122 */ "X6_X7_X8_X9_X10_X11_X12_X13\0" |
| 22259 | /* 1150 */ "Z10_Z11_Z12_Z13\0" |
| 22260 | /* 1166 */ "Z5_Z13\0" |
| 22261 | /* 1173 */ "Z1_Z5_Z9_Z13\0" |
| 22262 | /* 1186 */ "b13\0" |
| 22263 | /* 1190 */ "d13\0" |
| 22264 | /* 1194 */ "h13\0" |
| 22265 | /* 1198 */ "pn13\0" |
| 22266 | /* 1203 */ "p13\0" |
| 22267 | /* 1207 */ "q13\0" |
| 22268 | /* 1211 */ "s13\0" |
| 22269 | /* 1215 */ "w13\0" |
| 22270 | /* 1219 */ "x13\0" |
| 22271 | /* 1223 */ "z13\0" |
| 22272 | /* 1227 */ "D20_D21_D22_D23\0" |
| 22273 | /* 1243 */ "Q20_Q21_Q22_Q23\0" |
| 22274 | /* 1259 */ "W22_W23\0" |
| 22275 | /* 1267 */ "X16_X17_X18_X19_X20_X21_X22_X23\0" |
| 22276 | /* 1299 */ "Z20_Z21_Z22_Z23\0" |
| 22277 | /* 1315 */ "b23\0" |
| 22278 | /* 1319 */ "d23\0" |
| 22279 | /* 1323 */ "h23\0" |
| 22280 | /* 1327 */ "q23\0" |
| 22281 | /* 1331 */ "s23\0" |
| 22282 | /* 1335 */ "w23\0" |
| 22283 | /* 1339 */ "x23\0" |
| 22284 | /* 1343 */ "z23\0" |
| 22285 | /* 1347 */ "D0_D1_D2_D3\0" |
| 22286 | /* 1359 */ "P2_P3\0" |
| 22287 | /* 1365 */ "Q0_Q1_Q2_Q3\0" |
| 22288 | /* 1377 */ "W2_W3\0" |
| 22289 | /* 1383 */ "X2_X3\0" |
| 22290 | /* 1389 */ "Z0_Z1_Z2_Z3\0" |
| 22291 | /* 1401 */ "b3\0" |
| 22292 | /* 1404 */ "d3\0" |
| 22293 | /* 1407 */ "h3\0" |
| 22294 | /* 1410 */ "pn3\0" |
| 22295 | /* 1414 */ "p3\0" |
| 22296 | /* 1417 */ "q3\0" |
| 22297 | /* 1420 */ "s3\0" |
| 22298 | /* 1423 */ "w3\0" |
| 22299 | /* 1426 */ "x3\0" |
| 22300 | /* 1429 */ "z3\0" |
| 22301 | /* 1432 */ "D11_D12_D13_D14\0" |
| 22302 | /* 1448 */ "P13_P14\0" |
| 22303 | /* 1456 */ "Q11_Q12_Q13_Q14\0" |
| 22304 | /* 1472 */ "Z2_Z6_Z10_Z14\0" |
| 22305 | /* 1486 */ "Z11_Z12_Z13_Z14\0" |
| 22306 | /* 1502 */ "Z6_Z14\0" |
| 22307 | /* 1509 */ "b14\0" |
| 22308 | /* 1513 */ "d14\0" |
| 22309 | /* 1517 */ "h14\0" |
| 22310 | /* 1521 */ "pn14\0" |
| 22311 | /* 1526 */ "p14\0" |
| 22312 | /* 1530 */ "q14\0" |
| 22313 | /* 1534 */ "s14\0" |
| 22314 | /* 1538 */ "w14\0" |
| 22315 | /* 1542 */ "x14\0" |
| 22316 | /* 1546 */ "z14\0" |
| 22317 | /* 1550 */ "D21_D22_D23_D24\0" |
| 22318 | /* 1566 */ "Q21_Q22_Q23_Q24\0" |
| 22319 | /* 1582 */ "Z21_Z22_Z23_Z24\0" |
| 22320 | /* 1598 */ "Z16_Z24\0" |
| 22321 | /* 1606 */ "b24\0" |
| 22322 | /* 1610 */ "d24\0" |
| 22323 | /* 1614 */ "h24\0" |
| 22324 | /* 1618 */ "q24\0" |
| 22325 | /* 1622 */ "s24\0" |
| 22326 | /* 1626 */ "w24\0" |
| 22327 | /* 1630 */ "x24\0" |
| 22328 | /* 1634 */ "z24\0" |
| 22329 | /* 1638 */ "D1_D2_D3_D4\0" |
| 22330 | /* 1650 */ "P3_P4\0" |
| 22331 | /* 1656 */ "Q1_Q2_Q3_Q4\0" |
| 22332 | /* 1668 */ "Z1_Z2_Z3_Z4\0" |
| 22333 | /* 1680 */ "b4\0" |
| 22334 | /* 1683 */ "d4\0" |
| 22335 | /* 1686 */ "h4\0" |
| 22336 | /* 1689 */ "pn4\0" |
| 22337 | /* 1693 */ "p4\0" |
| 22338 | /* 1696 */ "q4\0" |
| 22339 | /* 1699 */ "s4\0" |
| 22340 | /* 1702 */ "w4\0" |
| 22341 | /* 1705 */ "x4\0" |
| 22342 | /* 1708 */ "z4\0" |
| 22343 | /* 1711 */ "D12_D13_D14_D15\0" |
| 22344 | /* 1727 */ "P14_P15\0" |
| 22345 | /* 1735 */ "Q12_Q13_Q14_Q15\0" |
| 22346 | /* 1751 */ "W14_W15\0" |
| 22347 | /* 1759 */ "X8_X9_X10_X11_X12_X13_X14_X15\0" |
| 22348 | /* 1789 */ "Z3_Z7_Z11_Z15\0" |
| 22349 | /* 1803 */ "Z12_Z13_Z14_Z15\0" |
| 22350 | /* 1819 */ "Z7_Z15\0" |
| 22351 | /* 1826 */ "b15\0" |
| 22352 | /* 1830 */ "d15\0" |
| 22353 | /* 1834 */ "h15\0" |
| 22354 | /* 1838 */ "pn15\0" |
| 22355 | /* 1843 */ "p15\0" |
| 22356 | /* 1847 */ "q15\0" |
| 22357 | /* 1851 */ "s15\0" |
| 22358 | /* 1855 */ "w15\0" |
| 22359 | /* 1859 */ "x15\0" |
| 22360 | /* 1863 */ "z15\0" |
| 22361 | /* 1867 */ "D22_D23_D24_D25\0" |
| 22362 | /* 1883 */ "Q22_Q23_Q24_Q25\0" |
| 22363 | /* 1899 */ "W24_W25\0" |
| 22364 | /* 1907 */ "X18_X19_X20_X21_X22_X23_X24_X25\0" |
| 22365 | /* 1939 */ "Z22_Z23_Z24_Z25\0" |
| 22366 | /* 1955 */ "Z17_Z25\0" |
| 22367 | /* 1963 */ "b25\0" |
| 22368 | /* 1967 */ "d25\0" |
| 22369 | /* 1971 */ "h25\0" |
| 22370 | /* 1975 */ "q25\0" |
| 22371 | /* 1979 */ "s25\0" |
| 22372 | /* 1983 */ "w25\0" |
| 22373 | /* 1987 */ "x25\0" |
| 22374 | /* 1991 */ "z25\0" |
| 22375 | /* 1995 */ "D2_D3_D4_D5\0" |
| 22376 | /* 2007 */ "P4_P5\0" |
| 22377 | /* 2013 */ "Q2_Q3_Q4_Q5\0" |
| 22378 | /* 2025 */ "W4_W5\0" |
| 22379 | /* 2031 */ "X4_X5\0" |
| 22380 | /* 2037 */ "Z2_Z3_Z4_Z5\0" |
| 22381 | /* 2049 */ "b5\0" |
| 22382 | /* 2052 */ "d5\0" |
| 22383 | /* 2055 */ "h5\0" |
| 22384 | /* 2058 */ "pn5\0" |
| 22385 | /* 2062 */ "p5\0" |
| 22386 | /* 2065 */ "q5\0" |
| 22387 | /* 2068 */ "s5\0" |
| 22388 | /* 2071 */ "w5\0" |
| 22389 | /* 2074 */ "x5\0" |
| 22390 | /* 2077 */ "z5\0" |
| 22391 | /* 2080 */ "D13_D14_D15_D16\0" |
| 22392 | /* 2096 */ "Q13_Q14_Q15_Q16\0" |
| 22393 | /* 2112 */ "Z13_Z14_Z15_Z16\0" |
| 22394 | /* 2128 */ "b16\0" |
| 22395 | /* 2132 */ "d16\0" |
| 22396 | /* 2136 */ "h16\0" |
| 22397 | /* 2140 */ "q16\0" |
| 22398 | /* 2144 */ "s16\0" |
| 22399 | /* 2148 */ "w16\0" |
| 22400 | /* 2152 */ "x16\0" |
| 22401 | /* 2156 */ "z16\0" |
| 22402 | /* 2160 */ "D23_D24_D25_D26\0" |
| 22403 | /* 2176 */ "Q23_Q24_Q25_Q26\0" |
| 22404 | /* 2192 */ "Z23_Z24_Z25_Z26\0" |
| 22405 | /* 2208 */ "Z18_Z26\0" |
| 22406 | /* 2216 */ "b26\0" |
| 22407 | /* 2220 */ "d26\0" |
| 22408 | /* 2224 */ "h26\0" |
| 22409 | /* 2228 */ "q26\0" |
| 22410 | /* 2232 */ "s26\0" |
| 22411 | /* 2236 */ "w26\0" |
| 22412 | /* 2240 */ "x26\0" |
| 22413 | /* 2244 */ "z26\0" |
| 22414 | /* 2248 */ "D3_D4_D5_D6\0" |
| 22415 | /* 2260 */ "P5_P6\0" |
| 22416 | /* 2266 */ "Q3_Q4_Q5_Q6\0" |
| 22417 | /* 2278 */ "Z3_Z4_Z5_Z6\0" |
| 22418 | /* 2290 */ "b6\0" |
| 22419 | /* 2293 */ "d6\0" |
| 22420 | /* 2296 */ "h6\0" |
| 22421 | /* 2299 */ "pn6\0" |
| 22422 | /* 2303 */ "p6\0" |
| 22423 | /* 2306 */ "q6\0" |
| 22424 | /* 2309 */ "s6\0" |
| 22425 | /* 2312 */ "w6\0" |
| 22426 | /* 2315 */ "x6\0" |
| 22427 | /* 2318 */ "z6\0" |
| 22428 | /* 2321 */ "D14_D15_D16_D17\0" |
| 22429 | /* 2337 */ "Q14_Q15_Q16_Q17\0" |
| 22430 | /* 2353 */ "W16_W17\0" |
| 22431 | /* 2361 */ "X10_X11_X12_X13_X14_X15_X16_X17\0" |
| 22432 | /* 2393 */ "Z14_Z15_Z16_Z17\0" |
| 22433 | /* 2409 */ "b17\0" |
| 22434 | /* 2413 */ "d17\0" |
| 22435 | /* 2417 */ "h17\0" |
| 22436 | /* 2421 */ "q17\0" |
| 22437 | /* 2425 */ "s17\0" |
| 22438 | /* 2429 */ "w17\0" |
| 22439 | /* 2433 */ "x17\0" |
| 22440 | /* 2437 */ "z17\0" |
| 22441 | /* 2441 */ "D24_D25_D26_D27\0" |
| 22442 | /* 2457 */ "Q24_Q25_Q26_Q27\0" |
| 22443 | /* 2473 */ "W26_W27\0" |
| 22444 | /* 2481 */ "X20_X21_X22_X23_X24_X25_X26_X27\0" |
| 22445 | /* 2513 */ "Z24_Z25_Z26_Z27\0" |
| 22446 | /* 2529 */ "Z19_Z27\0" |
| 22447 | /* 2537 */ "b27\0" |
| 22448 | /* 2541 */ "d27\0" |
| 22449 | /* 2545 */ "h27\0" |
| 22450 | /* 2549 */ "q27\0" |
| 22451 | /* 2553 */ "s27\0" |
| 22452 | /* 2557 */ "w27\0" |
| 22453 | /* 2561 */ "x27\0" |
| 22454 | /* 2565 */ "z27\0" |
| 22455 | /* 2569 */ "D4_D5_D6_D7\0" |
| 22456 | /* 2581 */ "P6_P7\0" |
| 22457 | /* 2587 */ "Q4_Q5_Q6_Q7\0" |
| 22458 | /* 2599 */ "W6_W7\0" |
| 22459 | /* 2605 */ "X0_X1_X2_X3_X4_X5_X6_X7\0" |
| 22460 | /* 2629 */ "Z4_Z5_Z6_Z7\0" |
| 22461 | /* 2641 */ "b7\0" |
| 22462 | /* 2644 */ "d7\0" |
| 22463 | /* 2647 */ "h7\0" |
| 22464 | /* 2650 */ "pn7\0" |
| 22465 | /* 2654 */ "p7\0" |
| 22466 | /* 2657 */ "q7\0" |
| 22467 | /* 2660 */ "s7\0" |
| 22468 | /* 2663 */ "w7\0" |
| 22469 | /* 2666 */ "x7\0" |
| 22470 | /* 2669 */ "z7\0" |
| 22471 | /* 2672 */ "D15_D16_D17_D18\0" |
| 22472 | /* 2688 */ "Q15_Q16_Q17_Q18\0" |
| 22473 | /* 2704 */ "Z15_Z16_Z17_Z18\0" |
| 22474 | /* 2720 */ "b18\0" |
| 22475 | /* 2724 */ "d18\0" |
| 22476 | /* 2728 */ "h18\0" |
| 22477 | /* 2732 */ "q18\0" |
| 22478 | /* 2736 */ "s18\0" |
| 22479 | /* 2740 */ "w18\0" |
| 22480 | /* 2744 */ "x18\0" |
| 22481 | /* 2748 */ "z18\0" |
| 22482 | /* 2752 */ "D25_D26_D27_D28\0" |
| 22483 | /* 2768 */ "Q25_Q26_Q27_Q28\0" |
| 22484 | /* 2784 */ "Z20_Z28\0" |
| 22485 | /* 2792 */ "Z16_Z20_Z24_Z28\0" |
| 22486 | /* 2808 */ "Z25_Z26_Z27_Z28\0" |
| 22487 | /* 2824 */ "b28\0" |
| 22488 | /* 2828 */ "d28\0" |
| 22489 | /* 2832 */ "h28\0" |
| 22490 | /* 2836 */ "q28\0" |
| 22491 | /* 2840 */ "s28\0" |
| 22492 | /* 2844 */ "w28\0" |
| 22493 | /* 2848 */ "x28\0" |
| 22494 | /* 2852 */ "z28\0" |
| 22495 | /* 2856 */ "D5_D6_D7_D8\0" |
| 22496 | /* 2868 */ "P7_P8\0" |
| 22497 | /* 2874 */ "Q5_Q6_Q7_Q8\0" |
| 22498 | /* 2886 */ "Z0_Z8\0" |
| 22499 | /* 2892 */ "Z5_Z6_Z7_Z8\0" |
| 22500 | /* 2904 */ "b8\0" |
| 22501 | /* 2907 */ "d8\0" |
| 22502 | /* 2910 */ "h8\0" |
| 22503 | /* 2913 */ "pn8\0" |
| 22504 | /* 2917 */ "p8\0" |
| 22505 | /* 2920 */ "q8\0" |
| 22506 | /* 2923 */ "s8\0" |
| 22507 | /* 2926 */ "w8\0" |
| 22508 | /* 2929 */ "x8\0" |
| 22509 | /* 2932 */ "z8\0" |
| 22510 | /* 2935 */ "D16_D17_D18_D19\0" |
| 22511 | /* 2951 */ "Q16_Q17_Q18_Q19\0" |
| 22512 | /* 2967 */ "W18_W19\0" |
| 22513 | /* 2975 */ "X12_X13_X14_X15_X16_X17_X18_X19\0" |
| 22514 | /* 3007 */ "Z16_Z17_Z18_Z19\0" |
| 22515 | /* 3023 */ "b19\0" |
| 22516 | /* 3027 */ "d19\0" |
| 22517 | /* 3031 */ "h19\0" |
| 22518 | /* 3035 */ "q19\0" |
| 22519 | /* 3039 */ "s19\0" |
| 22520 | /* 3043 */ "w19\0" |
| 22521 | /* 3047 */ "x19\0" |
| 22522 | /* 3051 */ "z19\0" |
| 22523 | /* 3055 */ "D26_D27_D28_D29\0" |
| 22524 | /* 3071 */ "Q26_Q27_Q28_Q29\0" |
| 22525 | /* 3087 */ "W28_W29\0" |
| 22526 | /* 3095 */ "Z21_Z29\0" |
| 22527 | /* 3103 */ "Z17_Z21_Z25_Z29\0" |
| 22528 | /* 3119 */ "Z26_Z27_Z28_Z29\0" |
| 22529 | /* 3135 */ "b29\0" |
| 22530 | /* 3139 */ "d29\0" |
| 22531 | /* 3143 */ "h29\0" |
| 22532 | /* 3147 */ "q29\0" |
| 22533 | /* 3151 */ "s29\0" |
| 22534 | /* 3155 */ "w29\0" |
| 22535 | /* 3159 */ "x29\0" |
| 22536 | /* 3163 */ "z29\0" |
| 22537 | /* 3167 */ "D6_D7_D8_D9\0" |
| 22538 | /* 3179 */ "P8_P9\0" |
| 22539 | /* 3185 */ "Q6_Q7_Q8_Q9\0" |
| 22540 | /* 3197 */ "W8_W9\0" |
| 22541 | /* 3203 */ "X2_X3_X4_X5_X6_X7_X8_X9\0" |
| 22542 | /* 3227 */ "Z1_Z9\0" |
| 22543 | /* 3233 */ "Z6_Z7_Z8_Z9\0" |
| 22544 | /* 3245 */ "b9\0" |
| 22545 | /* 3248 */ "d9\0" |
| 22546 | /* 3251 */ "h9\0" |
| 22547 | /* 3254 */ "pn9\0" |
| 22548 | /* 3258 */ "p9\0" |
| 22549 | /* 3261 */ "q9\0" |
| 22550 | /* 3264 */ "s9\0" |
| 22551 | /* 3267 */ "w9\0" |
| 22552 | /* 3270 */ "x9\0" |
| 22553 | /* 3273 */ "z9\0" |
| 22554 | /* 3276 */ "X22_X23_X24_X25_X26_X27_X28_FP\0" |
| 22555 | /* 3307 */ "W30_WZR\0" |
| 22556 | /* 3315 */ "LR_XZR\0" |
| 22557 | /* 3322 */ "za\0" |
| 22558 | /* 3325 */ "za0.b\0" |
| 22559 | /* 3331 */ "za0.d\0" |
| 22560 | /* 3337 */ "za1.d\0" |
| 22561 | /* 3343 */ "za2.d\0" |
| 22562 | /* 3349 */ "za3.d\0" |
| 22563 | /* 3355 */ "za4.d\0" |
| 22564 | /* 3361 */ "za5.d\0" |
| 22565 | /* 3367 */ "za6.d\0" |
| 22566 | /* 3373 */ "za7.d\0" |
| 22567 | /* 3379 */ "vg\0" |
| 22568 | /* 3382 */ "za0.h\0" |
| 22569 | /* 3388 */ "za1.h\0" |
| 22570 | /* 3394 */ "wsp\0" |
| 22571 | /* 3398 */ "za10.q\0" |
| 22572 | /* 3405 */ "za0.q\0" |
| 22573 | /* 3411 */ "za11.q\0" |
| 22574 | /* 3418 */ "za1.q\0" |
| 22575 | /* 3424 */ "za12.q\0" |
| 22576 | /* 3431 */ "za2.q\0" |
| 22577 | /* 3437 */ "za13.q\0" |
| 22578 | /* 3444 */ "za3.q\0" |
| 22579 | /* 3450 */ "za14.q\0" |
| 22580 | /* 3457 */ "za4.q\0" |
| 22581 | /* 3463 */ "za15.q\0" |
| 22582 | /* 3470 */ "za5.q\0" |
| 22583 | /* 3476 */ "za6.q\0" |
| 22584 | /* 3482 */ "za7.q\0" |
| 22585 | /* 3488 */ "za8.q\0" |
| 22586 | /* 3494 */ "za9.q\0" |
| 22587 | /* 3500 */ "fpcr\0" |
| 22588 | /* 3505 */ "ffr\0" |
| 22589 | /* 3509 */ "fpsr\0" |
| 22590 | /* 3514 */ "wzr\0" |
| 22591 | /* 3518 */ "xzr\0" |
| 22592 | /* 3522 */ "za0.s\0" |
| 22593 | /* 3528 */ "za1.s\0" |
| 22594 | /* 3534 */ "za2.s\0" |
| 22595 | /* 3540 */ "za3.s\0" |
| 22596 | /* 3546 */ "nzcv\0" |
| 22597 | }; |
| 22598 | #ifdef __GNUC__ |
| 22599 | #pragma GCC diagnostic pop |
| 22600 | #endif |
| 22601 | |
| 22602 | static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 22603 | 3505, 3159, 3500, 3509, 270, 3546, 3395, 3379, 3394, 3514, 3518, 3322, 330, 773, |
| 22604 | 1043, 1401, 1680, 2049, 2290, 2641, 2904, 3245, 53, 456, 877, 1186, 1509, 1826, |
| 22605 | 2128, 2409, 2720, 3023, 142, 585, 966, 1315, 1606, 1963, 2216, 2537, 2824, 3135, |
| 22606 | 246, 689, 333, 776, 1046, 1404, 1683, 2052, 2293, 2644, 2907, 3248, 57, 460, |
| 22607 | 881, 1190, 1513, 1830, 2132, 2413, 2724, 3027, 146, 589, 970, 1319, 1610, 1967, |
| 22608 | 2220, 2541, 2828, 3139, 250, 693, 336, 779, 1049, 1407, 1686, 2055, 2296, 2647, |
| 22609 | 2910, 3251, 61, 464, 885, 1194, 1517, 1834, 2136, 2417, 2728, 3031, 150, 593, |
| 22610 | 974, 1323, 1614, 1971, 2224, 2545, 2832, 3143, 254, 697, 343, 786, 1056, 1414, |
| 22611 | 1693, 2062, 2303, 2654, 2917, 3258, 70, 473, 894, 1203, 1526, 1843, 339, 782, |
| 22612 | 1052, 1410, 1689, 2058, 2299, 2650, 2913, 3254, 65, 468, 889, 1198, 1521, 1838, |
| 22613 | 346, 789, 1059, 1417, 1696, 2065, 2306, 2657, 2920, 3261, 74, 477, 898, 1207, |
| 22614 | 1530, 1847, 2140, 2421, 2732, 3035, 154, 597, 978, 1327, 1618, 1975, 2228, 2549, |
| 22615 | 2836, 3147, 258, 701, 349, 792, 1062, 1420, 1699, 2068, 2309, 2660, 2923, 3264, |
| 22616 | 78, 481, 902, 1211, 1534, 1851, 2144, 2425, 2736, 3039, 158, 601, 982, 1331, |
| 22617 | 1622, 1979, 2232, 2553, 2840, 3151, 262, 705, 356, 795, 1065, 1423, 1702, 2071, |
| 22618 | 2312, 2663, 2926, 3267, 82, 485, 906, 1215, 1538, 1855, 2148, 2429, 2740, 3043, |
| 22619 | 162, 605, 986, 1335, 1626, 1983, 2236, 2557, 2844, 3155, 266, 359, 798, 1068, |
| 22620 | 1426, 1705, 2074, 2315, 2666, 2929, 3270, 86, 489, 910, 1219, 1542, 1859, 2152, |
| 22621 | 2433, 2744, 3047, 166, 609, 990, 1339, 1630, 1987, 2240, 2561, 2848, 362, 801, |
| 22622 | 1071, 1429, 1708, 2077, 2318, 2669, 2932, 3273, 90, 493, 914, 1223, 1546, 1863, |
| 22623 | 2156, 2437, 2748, 3051, 170, 613, 994, 1343, 1634, 1991, 2244, 2565, 2852, 3163, |
| 22624 | 274, 709, 3325, 3331, 3337, 3343, 3349, 3355, 3361, 3367, 3373, 3382, 3388, 3405, |
| 22625 | 3418, 3431, 3444, 3457, 3470, 3476, 3482, 3488, 3494, 3398, 3411, 3424, 3437, 3450, |
| 22626 | 3463, 3522, 3528, 3534, 3540, 352, 721, 1005, 1353, 1644, 2001, 2254, 2575, 2862, |
| 22627 | 3173, 6, 371, 811, 1082, 1440, 1719, 2088, 2329, 2680, 2943, 102, 505, 926, |
| 22628 | 1235, 1558, 1875, 2168, 2449, 2760, 3063, 182, 625, 286, 1347, 1638, 1995, 2248, |
| 22629 | 2569, 2856, 3167, 0, 365, 804, 1074, 1432, 1711, 2080, 2321, 2672, 2935, 94, |
| 22630 | 497, 918, 1227, 1550, 1867, 2160, 2441, 2752, 3055, 174, 617, 278, 713, 998, |
| 22631 | 1002, 1350, 1641, 1998, 2251, 2572, 2859, 3170, 3, 368, 807, 1078, 1436, 1715, |
| 22632 | 2084, 2325, 2676, 2939, 98, 501, 922, 1231, 1554, 1871, 2164, 2445, 2756, 3059, |
| 22633 | 178, 621, 282, 717, 727, 1011, 1359, 1650, 2007, 2260, 2581, 2868, 3179, 13, |
| 22634 | 379, 819, 1090, 1448, 1727, 293, 741, 1024, 1371, 1662, 2019, 2272, 2593, 2880, |
| 22635 | 3191, 26, 393, 834, 1106, 1464, 1743, 2104, 2345, 2696, 2959, 118, 521, 942, |
| 22636 | 1251, 1574, 1891, 2184, 2465, 2776, 3079, 198, 641, 308, 1365, 1656, 2013, 2266, |
| 22637 | 2587, 2874, 3185, 20, 387, 827, 1098, 1456, 1735, 2096, 2337, 2688, 2951, 110, |
| 22638 | 513, 934, 1243, 1566, 1883, 2176, 2457, 2768, 3071, 190, 633, 300, 733, 1017, |
| 22639 | 1021, 1368, 1659, 2016, 2269, 2590, 2877, 3188, 23, 390, 830, 1102, 1460, 1739, |
| 22640 | 2100, 2341, 2692, 2955, 114, 517, 938, 1247, 1570, 1887, 2180, 2461, 2772, 3075, |
| 22641 | 194, 637, 304, 737, 3276, 2605, 3203, 409, 1122, 1759, 2361, 2975, 537, 1267, |
| 22642 | 1907, 2481, 3307, 747, 1377, 2025, 2599, 3197, 401, 1114, 1751, 2353, 2967, 529, |
| 22643 | 1259, 1899, 2473, 3087, 3315, 3300, 753, 1383, 2031, 2623, 3221, 427, 1142, 1781, |
| 22644 | 2385, 2999, 561, 1291, 1931, 2505, 767, 1037, 1395, 1674, 2043, 2284, 2635, 2898, |
| 22645 | 3239, 46, 441, 849, 1158, 1494, 1811, 2120, 2401, 2712, 3015, 134, 577, 958, |
| 22646 | 1307, 1590, 1947, 2200, 2521, 2816, 3127, 238, 657, 323, 1389, 1668, 2037, 2278, |
| 22647 | 2629, 2892, 3233, 40, 435, 842, 1150, 1486, 1803, 2112, 2393, 2704, 3007, 126, |
| 22648 | 569, 950, 1299, 1582, 1939, 2192, 2513, 2808, 3119, 230, 649, 315, 759, 1030, |
| 22649 | 1034, 1392, 1671, 2040, 2281, 2632, 2895, 3236, 43, 438, 845, 1154, 1490, 1807, |
| 22650 | 2116, 2397, 2708, 3011, 130, 573, 954, 1303, 1586, 1943, 2196, 2517, 2812, 3123, |
| 22651 | 234, 653, 319, 763, 1598, 1955, 2208, 2529, 2784, 3095, 206, 665, 2886, 3227, |
| 22652 | 33, 449, 857, 1166, 1502, 1819, 2792, 3103, 214, 673, 864, 1173, 1472, 1789, |
| 22653 | }; |
| 22654 | |
| 22655 | |
| 22656 | #ifdef __GNUC__ |
| 22657 | #pragma GCC diagnostic push |
| 22658 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 22659 | #endif |
| 22660 | static const char AsmStrsvlist1[] = { |
| 22661 | /* 0 */ "\0" |
| 22662 | }; |
| 22663 | #ifdef __GNUC__ |
| 22664 | #pragma GCC diagnostic pop |
| 22665 | #endif |
| 22666 | |
| 22667 | static const uint8_t RegAsmOffsetvlist1[] = { |
| 22668 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22669 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22670 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22671 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22672 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22673 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22674 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22675 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22676 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22677 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22678 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22679 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22680 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22681 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22682 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22683 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22684 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22685 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22686 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22687 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22688 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22689 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22690 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22691 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22692 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22693 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22694 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22695 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22696 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22697 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22698 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22699 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22700 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22701 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22702 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22703 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22704 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22705 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22706 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22707 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22708 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22709 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22710 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22711 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22712 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22713 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22714 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22715 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22716 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22717 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 22718 | }; |
| 22719 | |
| 22720 | |
| 22721 | #ifdef __GNUC__ |
| 22722 | #pragma GCC diagnostic push |
| 22723 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 22724 | #endif |
| 22725 | static const char AsmStrsvreg[] = { |
| 22726 | /* 0 */ "v10\0" |
| 22727 | /* 4 */ "v20\0" |
| 22728 | /* 8 */ "v30\0" |
| 22729 | /* 12 */ "v0\0" |
| 22730 | /* 15 */ "v11\0" |
| 22731 | /* 19 */ "v21\0" |
| 22732 | /* 23 */ "v31\0" |
| 22733 | /* 27 */ "v1\0" |
| 22734 | /* 30 */ "v12\0" |
| 22735 | /* 34 */ "v22\0" |
| 22736 | /* 38 */ "v2\0" |
| 22737 | /* 41 */ "v13\0" |
| 22738 | /* 45 */ "v23\0" |
| 22739 | /* 49 */ "v3\0" |
| 22740 | /* 52 */ "v14\0" |
| 22741 | /* 56 */ "v24\0" |
| 22742 | /* 60 */ "v4\0" |
| 22743 | /* 63 */ "v15\0" |
| 22744 | /* 67 */ "v25\0" |
| 22745 | /* 71 */ "v5\0" |
| 22746 | /* 74 */ "v16\0" |
| 22747 | /* 78 */ "v26\0" |
| 22748 | /* 82 */ "v6\0" |
| 22749 | /* 85 */ "v17\0" |
| 22750 | /* 89 */ "v27\0" |
| 22751 | /* 93 */ "v7\0" |
| 22752 | /* 96 */ "v18\0" |
| 22753 | /* 100 */ "v28\0" |
| 22754 | /* 104 */ "v8\0" |
| 22755 | /* 107 */ "v19\0" |
| 22756 | /* 111 */ "v29\0" |
| 22757 | /* 115 */ "v9\0" |
| 22758 | }; |
| 22759 | #ifdef __GNUC__ |
| 22760 | #pragma GCC diagnostic pop |
| 22761 | #endif |
| 22762 | |
| 22763 | static const uint8_t RegAsmOffsetvreg[] = { |
| 22764 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22765 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22766 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22767 | 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, |
| 22768 | 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, |
| 22769 | 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22770 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22771 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22772 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22773 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22774 | 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, |
| 22775 | 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, |
| 22776 | 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22777 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22778 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22779 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22780 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22781 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22782 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22783 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22784 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22785 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22786 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22787 | 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, |
| 22788 | 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, |
| 22789 | 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, |
| 22790 | 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, |
| 22791 | 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, |
| 22792 | 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, |
| 22793 | 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, |
| 22794 | 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22795 | 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, |
| 22796 | 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, |
| 22797 | 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, |
| 22798 | 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, |
| 22799 | 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, |
| 22800 | 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, |
| 22801 | 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, |
| 22802 | 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22803 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22804 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22805 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22806 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22807 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22808 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22809 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22810 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22811 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22812 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22813 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 22814 | }; |
| 22815 | |
| 22816 | switch(AltIdx) { |
| 22817 | default: llvm_unreachable("Invalid register alt name index!"); |
| 22818 | case AArch64::NoRegAltName: |
| 22819 | assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| 22820 | "Invalid alt name index for register!"); |
| 22821 | return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| 22822 | case AArch64::vlist1: |
| 22823 | assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| 22824 | "Invalid alt name index for register!"); |
| 22825 | return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| 22826 | case AArch64::vreg: |
| 22827 | assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| 22828 | "Invalid alt name index for register!"); |
| 22829 | return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| 22830 | } |
| 22831 | } |
| 22832 | |
| 22833 | #ifdef PRINT_ALIAS_INSTR |
| 22834 | #undef PRINT_ALIAS_INSTR |
| 22835 | |
| 22836 | static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| 22837 | const MCSubtargetInfo &STI, |
| 22838 | unsigned PredicateIndex); |
| 22839 | bool AArch64AppleInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| 22840 | static const PatternsForOpcode OpToPatterns[] = { |
| 22841 | {.Opcode: AArch64::ADDPT_shift, .PatternStart: 0, .NumPatterns: 1 }, |
| 22842 | {.Opcode: AArch64::ADDSWri, .PatternStart: 1, .NumPatterns: 1 }, |
| 22843 | {.Opcode: AArch64::ADDSWrs, .PatternStart: 2, .NumPatterns: 3 }, |
| 22844 | {.Opcode: AArch64::ADDSWrx, .PatternStart: 5, .NumPatterns: 3 }, |
| 22845 | {.Opcode: AArch64::ADDSXri, .PatternStart: 8, .NumPatterns: 1 }, |
| 22846 | {.Opcode: AArch64::ADDSXrs, .PatternStart: 9, .NumPatterns: 3 }, |
| 22847 | {.Opcode: AArch64::ADDSXrx, .PatternStart: 12, .NumPatterns: 1 }, |
| 22848 | {.Opcode: AArch64::ADDSXrx64, .PatternStart: 13, .NumPatterns: 3 }, |
| 22849 | {.Opcode: AArch64::ADDWri, .PatternStart: 16, .NumPatterns: 2 }, |
| 22850 | {.Opcode: AArch64::ADDWrs, .PatternStart: 18, .NumPatterns: 1 }, |
| 22851 | {.Opcode: AArch64::ADDWrx, .PatternStart: 19, .NumPatterns: 2 }, |
| 22852 | {.Opcode: AArch64::ADDXri, .PatternStart: 21, .NumPatterns: 2 }, |
| 22853 | {.Opcode: AArch64::ADDXrs, .PatternStart: 23, .NumPatterns: 1 }, |
| 22854 | {.Opcode: AArch64::ADDXrx64, .PatternStart: 24, .NumPatterns: 2 }, |
| 22855 | {.Opcode: AArch64::ANDSWri, .PatternStart: 26, .NumPatterns: 1 }, |
| 22856 | {.Opcode: AArch64::ANDSWrs, .PatternStart: 27, .NumPatterns: 3 }, |
| 22857 | {.Opcode: AArch64::ANDSXri, .PatternStart: 30, .NumPatterns: 1 }, |
| 22858 | {.Opcode: AArch64::ANDSXrs, .PatternStart: 31, .NumPatterns: 3 }, |
| 22859 | {.Opcode: AArch64::ANDS_PPzPP, .PatternStart: 34, .NumPatterns: 1 }, |
| 22860 | {.Opcode: AArch64::ANDWrs, .PatternStart: 35, .NumPatterns: 1 }, |
| 22861 | {.Opcode: AArch64::ANDXrs, .PatternStart: 36, .NumPatterns: 1 }, |
| 22862 | {.Opcode: AArch64::AND_PPzPP, .PatternStart: 37, .NumPatterns: 1 }, |
| 22863 | {.Opcode: AArch64::AND_ZI, .PatternStart: 38, .NumPatterns: 3 }, |
| 22864 | {.Opcode: AArch64::AUTIA1716, .PatternStart: 41, .NumPatterns: 1 }, |
| 22865 | {.Opcode: AArch64::AUTIASP, .PatternStart: 42, .NumPatterns: 1 }, |
| 22866 | {.Opcode: AArch64::AUTIAZ, .PatternStart: 43, .NumPatterns: 1 }, |
| 22867 | {.Opcode: AArch64::AUTIB1716, .PatternStart: 44, .NumPatterns: 1 }, |
| 22868 | {.Opcode: AArch64::AUTIBSP, .PatternStart: 45, .NumPatterns: 1 }, |
| 22869 | {.Opcode: AArch64::AUTIBZ, .PatternStart: 46, .NumPatterns: 1 }, |
| 22870 | {.Opcode: AArch64::BICSWrs, .PatternStart: 47, .NumPatterns: 1 }, |
| 22871 | {.Opcode: AArch64::BICSXrs, .PatternStart: 48, .NumPatterns: 1 }, |
| 22872 | {.Opcode: AArch64::BICWrs, .PatternStart: 49, .NumPatterns: 1 }, |
| 22873 | {.Opcode: AArch64::BICXrs, .PatternStart: 50, .NumPatterns: 1 }, |
| 22874 | {.Opcode: AArch64::CHKFEAT, .PatternStart: 51, .NumPatterns: 1 }, |
| 22875 | {.Opcode: AArch64::CLREX, .PatternStart: 52, .NumPatterns: 1 }, |
| 22876 | {.Opcode: AArch64::CNTB_XPiI, .PatternStart: 53, .NumPatterns: 2 }, |
| 22877 | {.Opcode: AArch64::CNTD_XPiI, .PatternStart: 55, .NumPatterns: 2 }, |
| 22878 | {.Opcode: AArch64::CNTH_XPiI, .PatternStart: 57, .NumPatterns: 2 }, |
| 22879 | {.Opcode: AArch64::CNTW_XPiI, .PatternStart: 59, .NumPatterns: 2 }, |
| 22880 | {.Opcode: AArch64::CPY_ZPmI_B, .PatternStart: 61, .NumPatterns: 1 }, |
| 22881 | {.Opcode: AArch64::CPY_ZPmI_D, .PatternStart: 62, .NumPatterns: 1 }, |
| 22882 | {.Opcode: AArch64::CPY_ZPmI_H, .PatternStart: 63, .NumPatterns: 1 }, |
| 22883 | {.Opcode: AArch64::CPY_ZPmI_S, .PatternStart: 64, .NumPatterns: 1 }, |
| 22884 | {.Opcode: AArch64::CPY_ZPmR_B, .PatternStart: 65, .NumPatterns: 1 }, |
| 22885 | {.Opcode: AArch64::CPY_ZPmR_D, .PatternStart: 66, .NumPatterns: 1 }, |
| 22886 | {.Opcode: AArch64::CPY_ZPmR_H, .PatternStart: 67, .NumPatterns: 1 }, |
| 22887 | {.Opcode: AArch64::CPY_ZPmR_S, .PatternStart: 68, .NumPatterns: 1 }, |
| 22888 | {.Opcode: AArch64::CPY_ZPmV_B, .PatternStart: 69, .NumPatterns: 1 }, |
| 22889 | {.Opcode: AArch64::CPY_ZPmV_D, .PatternStart: 70, .NumPatterns: 1 }, |
| 22890 | {.Opcode: AArch64::CPY_ZPmV_H, .PatternStart: 71, .NumPatterns: 1 }, |
| 22891 | {.Opcode: AArch64::CPY_ZPmV_S, .PatternStart: 72, .NumPatterns: 1 }, |
| 22892 | {.Opcode: AArch64::CPY_ZPzI_B, .PatternStart: 73, .NumPatterns: 1 }, |
| 22893 | {.Opcode: AArch64::CPY_ZPzI_D, .PatternStart: 74, .NumPatterns: 1 }, |
| 22894 | {.Opcode: AArch64::CPY_ZPzI_H, .PatternStart: 75, .NumPatterns: 1 }, |
| 22895 | {.Opcode: AArch64::CPY_ZPzI_S, .PatternStart: 76, .NumPatterns: 1 }, |
| 22896 | {.Opcode: AArch64::CSINCWr, .PatternStart: 77, .NumPatterns: 2 }, |
| 22897 | {.Opcode: AArch64::CSINCXr, .PatternStart: 79, .NumPatterns: 2 }, |
| 22898 | {.Opcode: AArch64::CSINVWr, .PatternStart: 81, .NumPatterns: 2 }, |
| 22899 | {.Opcode: AArch64::CSINVXr, .PatternStart: 83, .NumPatterns: 2 }, |
| 22900 | {.Opcode: AArch64::CSNEGWr, .PatternStart: 85, .NumPatterns: 1 }, |
| 22901 | {.Opcode: AArch64::CSNEGXr, .PatternStart: 86, .NumPatterns: 1 }, |
| 22902 | {.Opcode: AArch64::DCPS1, .PatternStart: 87, .NumPatterns: 1 }, |
| 22903 | {.Opcode: AArch64::DCPS2, .PatternStart: 88, .NumPatterns: 1 }, |
| 22904 | {.Opcode: AArch64::DCPS3, .PatternStart: 89, .NumPatterns: 1 }, |
| 22905 | {.Opcode: AArch64::DECB_XPiI, .PatternStart: 90, .NumPatterns: 2 }, |
| 22906 | {.Opcode: AArch64::DECD_XPiI, .PatternStart: 92, .NumPatterns: 2 }, |
| 22907 | {.Opcode: AArch64::DECD_ZPiI, .PatternStart: 94, .NumPatterns: 2 }, |
| 22908 | {.Opcode: AArch64::DECH_XPiI, .PatternStart: 96, .NumPatterns: 2 }, |
| 22909 | {.Opcode: AArch64::DECH_ZPiI, .PatternStart: 98, .NumPatterns: 2 }, |
| 22910 | {.Opcode: AArch64::DECW_XPiI, .PatternStart: 100, .NumPatterns: 2 }, |
| 22911 | {.Opcode: AArch64::DECW_ZPiI, .PatternStart: 102, .NumPatterns: 2 }, |
| 22912 | {.Opcode: AArch64::DSB, .PatternStart: 104, .NumPatterns: 3 }, |
| 22913 | {.Opcode: AArch64::DUPM_ZI, .PatternStart: 107, .NumPatterns: 6 }, |
| 22914 | {.Opcode: AArch64::DUP_ZI_B, .PatternStart: 113, .NumPatterns: 1 }, |
| 22915 | {.Opcode: AArch64::DUP_ZI_D, .PatternStart: 114, .NumPatterns: 2 }, |
| 22916 | {.Opcode: AArch64::DUP_ZI_H, .PatternStart: 116, .NumPatterns: 2 }, |
| 22917 | {.Opcode: AArch64::DUP_ZI_S, .PatternStart: 118, .NumPatterns: 2 }, |
| 22918 | {.Opcode: AArch64::DUP_ZR_B, .PatternStart: 120, .NumPatterns: 1 }, |
| 22919 | {.Opcode: AArch64::DUP_ZR_D, .PatternStart: 121, .NumPatterns: 1 }, |
| 22920 | {.Opcode: AArch64::DUP_ZR_H, .PatternStart: 122, .NumPatterns: 1 }, |
| 22921 | {.Opcode: AArch64::DUP_ZR_S, .PatternStart: 123, .NumPatterns: 1 }, |
| 22922 | {.Opcode: AArch64::DUP_ZZI_B, .PatternStart: 124, .NumPatterns: 2 }, |
| 22923 | {.Opcode: AArch64::DUP_ZZI_D, .PatternStart: 126, .NumPatterns: 2 }, |
| 22924 | {.Opcode: AArch64::DUP_ZZI_H, .PatternStart: 128, .NumPatterns: 2 }, |
| 22925 | {.Opcode: AArch64::DUP_ZZI_Q, .PatternStart: 130, .NumPatterns: 2 }, |
| 22926 | {.Opcode: AArch64::DUP_ZZI_S, .PatternStart: 132, .NumPatterns: 2 }, |
| 22927 | {.Opcode: AArch64::EONWrs, .PatternStart: 134, .NumPatterns: 1 }, |
| 22928 | {.Opcode: AArch64::EONXrs, .PatternStart: 135, .NumPatterns: 1 }, |
| 22929 | {.Opcode: AArch64::EORS_PPzPP, .PatternStart: 136, .NumPatterns: 1 }, |
| 22930 | {.Opcode: AArch64::EORWrs, .PatternStart: 137, .NumPatterns: 1 }, |
| 22931 | {.Opcode: AArch64::EORXrs, .PatternStart: 138, .NumPatterns: 1 }, |
| 22932 | {.Opcode: AArch64::EOR_PPzPP, .PatternStart: 139, .NumPatterns: 1 }, |
| 22933 | {.Opcode: AArch64::EOR_ZI, .PatternStart: 140, .NumPatterns: 3 }, |
| 22934 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_B, .PatternStart: 143, .NumPatterns: 1 }, |
| 22935 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_D, .PatternStart: 144, .NumPatterns: 1 }, |
| 22936 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_H, .PatternStart: 145, .NumPatterns: 1 }, |
| 22937 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_Q, .PatternStart: 146, .NumPatterns: 1 }, |
| 22938 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_S, .PatternStart: 147, .NumPatterns: 1 }, |
| 22939 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_B, .PatternStart: 148, .NumPatterns: 1 }, |
| 22940 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_D, .PatternStart: 149, .NumPatterns: 1 }, |
| 22941 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_H, .PatternStart: 150, .NumPatterns: 1 }, |
| 22942 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_Q, .PatternStart: 151, .NumPatterns: 1 }, |
| 22943 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_S, .PatternStart: 152, .NumPatterns: 1 }, |
| 22944 | {.Opcode: AArch64::EXTRWrri, .PatternStart: 153, .NumPatterns: 1 }, |
| 22945 | {.Opcode: AArch64::EXTRXrri, .PatternStart: 154, .NumPatterns: 1 }, |
| 22946 | {.Opcode: AArch64::FCPY_ZPmI_D, .PatternStart: 155, .NumPatterns: 1 }, |
| 22947 | {.Opcode: AArch64::FCPY_ZPmI_H, .PatternStart: 156, .NumPatterns: 1 }, |
| 22948 | {.Opcode: AArch64::FCPY_ZPmI_S, .PatternStart: 157, .NumPatterns: 1 }, |
| 22949 | {.Opcode: AArch64::FDUP_ZI_D, .PatternStart: 158, .NumPatterns: 1 }, |
| 22950 | {.Opcode: AArch64::FDUP_ZI_H, .PatternStart: 159, .NumPatterns: 1 }, |
| 22951 | {.Opcode: AArch64::FDUP_ZI_S, .PatternStart: 160, .NumPatterns: 1 }, |
| 22952 | {.Opcode: AArch64::GCSPOPM, .PatternStart: 161, .NumPatterns: 1 }, |
| 22953 | {.Opcode: AArch64::GLD1B_D_IMM, .PatternStart: 162, .NumPatterns: 1 }, |
| 22954 | {.Opcode: AArch64::GLD1B_S_IMM, .PatternStart: 163, .NumPatterns: 1 }, |
| 22955 | {.Opcode: AArch64::GLD1D_IMM, .PatternStart: 164, .NumPatterns: 1 }, |
| 22956 | {.Opcode: AArch64::GLD1H_D_IMM, .PatternStart: 165, .NumPatterns: 1 }, |
| 22957 | {.Opcode: AArch64::GLD1H_S_IMM, .PatternStart: 166, .NumPatterns: 1 }, |
| 22958 | {.Opcode: AArch64::GLD1Q, .PatternStart: 167, .NumPatterns: 1 }, |
| 22959 | {.Opcode: AArch64::GLD1SB_D_IMM, .PatternStart: 168, .NumPatterns: 1 }, |
| 22960 | {.Opcode: AArch64::GLD1SB_S_IMM, .PatternStart: 169, .NumPatterns: 1 }, |
| 22961 | {.Opcode: AArch64::GLD1SH_D_IMM, .PatternStart: 170, .NumPatterns: 1 }, |
| 22962 | {.Opcode: AArch64::GLD1SH_S_IMM, .PatternStart: 171, .NumPatterns: 1 }, |
| 22963 | {.Opcode: AArch64::GLD1SW_D_IMM, .PatternStart: 172, .NumPatterns: 1 }, |
| 22964 | {.Opcode: AArch64::GLD1W_D_IMM, .PatternStart: 173, .NumPatterns: 1 }, |
| 22965 | {.Opcode: AArch64::GLD1W_IMM, .PatternStart: 174, .NumPatterns: 1 }, |
| 22966 | {.Opcode: AArch64::GLDFF1B_D_IMM, .PatternStart: 175, .NumPatterns: 1 }, |
| 22967 | {.Opcode: AArch64::GLDFF1B_S_IMM, .PatternStart: 176, .NumPatterns: 1 }, |
| 22968 | {.Opcode: AArch64::GLDFF1D_IMM, .PatternStart: 177, .NumPatterns: 1 }, |
| 22969 | {.Opcode: AArch64::GLDFF1H_D_IMM, .PatternStart: 178, .NumPatterns: 1 }, |
| 22970 | {.Opcode: AArch64::GLDFF1H_S_IMM, .PatternStart: 179, .NumPatterns: 1 }, |
| 22971 | {.Opcode: AArch64::GLDFF1SB_D_IMM, .PatternStart: 180, .NumPatterns: 1 }, |
| 22972 | {.Opcode: AArch64::GLDFF1SB_S_IMM, .PatternStart: 181, .NumPatterns: 1 }, |
| 22973 | {.Opcode: AArch64::GLDFF1SH_D_IMM, .PatternStart: 182, .NumPatterns: 1 }, |
| 22974 | {.Opcode: AArch64::GLDFF1SH_S_IMM, .PatternStart: 183, .NumPatterns: 1 }, |
| 22975 | {.Opcode: AArch64::GLDFF1SW_D_IMM, .PatternStart: 184, .NumPatterns: 1 }, |
| 22976 | {.Opcode: AArch64::GLDFF1W_D_IMM, .PatternStart: 185, .NumPatterns: 1 }, |
| 22977 | {.Opcode: AArch64::GLDFF1W_IMM, .PatternStart: 186, .NumPatterns: 1 }, |
| 22978 | {.Opcode: AArch64::HINT, .PatternStart: 187, .NumPatterns: 14 }, |
| 22979 | {.Opcode: AArch64::INCB_XPiI, .PatternStart: 201, .NumPatterns: 2 }, |
| 22980 | {.Opcode: AArch64::INCD_XPiI, .PatternStart: 203, .NumPatterns: 2 }, |
| 22981 | {.Opcode: AArch64::INCD_ZPiI, .PatternStart: 205, .NumPatterns: 2 }, |
| 22982 | {.Opcode: AArch64::INCH_XPiI, .PatternStart: 207, .NumPatterns: 2 }, |
| 22983 | {.Opcode: AArch64::INCH_ZPiI, .PatternStart: 209, .NumPatterns: 2 }, |
| 22984 | {.Opcode: AArch64::INCW_XPiI, .PatternStart: 211, .NumPatterns: 2 }, |
| 22985 | {.Opcode: AArch64::INCW_ZPiI, .PatternStart: 213, .NumPatterns: 2 }, |
| 22986 | {.Opcode: AArch64::INSERT_MXIPZ_H_B, .PatternStart: 215, .NumPatterns: 1 }, |
| 22987 | {.Opcode: AArch64::INSERT_MXIPZ_H_D, .PatternStart: 216, .NumPatterns: 1 }, |
| 22988 | {.Opcode: AArch64::INSERT_MXIPZ_H_H, .PatternStart: 217, .NumPatterns: 1 }, |
| 22989 | {.Opcode: AArch64::INSERT_MXIPZ_H_Q, .PatternStart: 218, .NumPatterns: 1 }, |
| 22990 | {.Opcode: AArch64::INSERT_MXIPZ_H_S, .PatternStart: 219, .NumPatterns: 1 }, |
| 22991 | {.Opcode: AArch64::INSERT_MXIPZ_V_B, .PatternStart: 220, .NumPatterns: 1 }, |
| 22992 | {.Opcode: AArch64::INSERT_MXIPZ_V_D, .PatternStart: 221, .NumPatterns: 1 }, |
| 22993 | {.Opcode: AArch64::INSERT_MXIPZ_V_H, .PatternStart: 222, .NumPatterns: 1 }, |
| 22994 | {.Opcode: AArch64::INSERT_MXIPZ_V_Q, .PatternStart: 223, .NumPatterns: 1 }, |
| 22995 | {.Opcode: AArch64::INSERT_MXIPZ_V_S, .PatternStart: 224, .NumPatterns: 1 }, |
| 22996 | {.Opcode: AArch64::INSvi16gpr, .PatternStart: 225, .NumPatterns: 1 }, |
| 22997 | {.Opcode: AArch64::INSvi16lane, .PatternStart: 226, .NumPatterns: 1 }, |
| 22998 | {.Opcode: AArch64::INSvi32gpr, .PatternStart: 227, .NumPatterns: 1 }, |
| 22999 | {.Opcode: AArch64::INSvi32lane, .PatternStart: 228, .NumPatterns: 1 }, |
| 23000 | {.Opcode: AArch64::INSvi64gpr, .PatternStart: 229, .NumPatterns: 1 }, |
| 23001 | {.Opcode: AArch64::INSvi64lane, .PatternStart: 230, .NumPatterns: 1 }, |
| 23002 | {.Opcode: AArch64::INSvi8gpr, .PatternStart: 231, .NumPatterns: 1 }, |
| 23003 | {.Opcode: AArch64::INSvi8lane, .PatternStart: 232, .NumPatterns: 1 }, |
| 23004 | {.Opcode: AArch64::IRG, .PatternStart: 233, .NumPatterns: 1 }, |
| 23005 | {.Opcode: AArch64::ISB, .PatternStart: 234, .NumPatterns: 1 }, |
| 23006 | {.Opcode: AArch64::LD1B_2Z_IMM, .PatternStart: 235, .NumPatterns: 1 }, |
| 23007 | {.Opcode: AArch64::LD1B_2Z_STRIDED_IMM, .PatternStart: 236, .NumPatterns: 1 }, |
| 23008 | {.Opcode: AArch64::LD1B_4Z_IMM, .PatternStart: 237, .NumPatterns: 1 }, |
| 23009 | {.Opcode: AArch64::LD1B_4Z_STRIDED_IMM, .PatternStart: 238, .NumPatterns: 1 }, |
| 23010 | {.Opcode: AArch64::LD1B_D_IMM, .PatternStart: 239, .NumPatterns: 1 }, |
| 23011 | {.Opcode: AArch64::LD1B_H_IMM, .PatternStart: 240, .NumPatterns: 1 }, |
| 23012 | {.Opcode: AArch64::LD1B_IMM, .PatternStart: 241, .NumPatterns: 1 }, |
| 23013 | {.Opcode: AArch64::LD1B_S_IMM, .PatternStart: 242, .NumPatterns: 1 }, |
| 23014 | {.Opcode: AArch64::LD1D_2Z_IMM, .PatternStart: 243, .NumPatterns: 1 }, |
| 23015 | {.Opcode: AArch64::LD1D_2Z_STRIDED_IMM, .PatternStart: 244, .NumPatterns: 1 }, |
| 23016 | {.Opcode: AArch64::LD1D_4Z_IMM, .PatternStart: 245, .NumPatterns: 1 }, |
| 23017 | {.Opcode: AArch64::LD1D_4Z_STRIDED_IMM, .PatternStart: 246, .NumPatterns: 1 }, |
| 23018 | {.Opcode: AArch64::LD1D_IMM, .PatternStart: 247, .NumPatterns: 1 }, |
| 23019 | {.Opcode: AArch64::LD1D_Q_IMM, .PatternStart: 248, .NumPatterns: 1 }, |
| 23020 | {.Opcode: AArch64::LD1Fourv16b_POST, .PatternStart: 249, .NumPatterns: 1 }, |
| 23021 | {.Opcode: AArch64::LD1Fourv1d_POST, .PatternStart: 250, .NumPatterns: 1 }, |
| 23022 | {.Opcode: AArch64::LD1Fourv2d_POST, .PatternStart: 251, .NumPatterns: 1 }, |
| 23023 | {.Opcode: AArch64::LD1Fourv2s_POST, .PatternStart: 252, .NumPatterns: 1 }, |
| 23024 | {.Opcode: AArch64::LD1Fourv4h_POST, .PatternStart: 253, .NumPatterns: 1 }, |
| 23025 | {.Opcode: AArch64::LD1Fourv4s_POST, .PatternStart: 254, .NumPatterns: 1 }, |
| 23026 | {.Opcode: AArch64::LD1Fourv8b_POST, .PatternStart: 255, .NumPatterns: 1 }, |
| 23027 | {.Opcode: AArch64::LD1Fourv8h_POST, .PatternStart: 256, .NumPatterns: 1 }, |
| 23028 | {.Opcode: AArch64::LD1H_2Z_IMM, .PatternStart: 257, .NumPatterns: 1 }, |
| 23029 | {.Opcode: AArch64::LD1H_2Z_STRIDED_IMM, .PatternStart: 258, .NumPatterns: 1 }, |
| 23030 | {.Opcode: AArch64::LD1H_4Z_IMM, .PatternStart: 259, .NumPatterns: 1 }, |
| 23031 | {.Opcode: AArch64::LD1H_4Z_STRIDED_IMM, .PatternStart: 260, .NumPatterns: 1 }, |
| 23032 | {.Opcode: AArch64::LD1H_D_IMM, .PatternStart: 261, .NumPatterns: 1 }, |
| 23033 | {.Opcode: AArch64::LD1H_IMM, .PatternStart: 262, .NumPatterns: 1 }, |
| 23034 | {.Opcode: AArch64::LD1H_S_IMM, .PatternStart: 263, .NumPatterns: 1 }, |
| 23035 | {.Opcode: AArch64::LD1Onev16b_POST, .PatternStart: 264, .NumPatterns: 1 }, |
| 23036 | {.Opcode: AArch64::LD1Onev1d_POST, .PatternStart: 265, .NumPatterns: 1 }, |
| 23037 | {.Opcode: AArch64::LD1Onev2d_POST, .PatternStart: 266, .NumPatterns: 1 }, |
| 23038 | {.Opcode: AArch64::LD1Onev2s_POST, .PatternStart: 267, .NumPatterns: 1 }, |
| 23039 | {.Opcode: AArch64::LD1Onev4h_POST, .PatternStart: 268, .NumPatterns: 1 }, |
| 23040 | {.Opcode: AArch64::LD1Onev4s_POST, .PatternStart: 269, .NumPatterns: 1 }, |
| 23041 | {.Opcode: AArch64::LD1Onev8b_POST, .PatternStart: 270, .NumPatterns: 1 }, |
| 23042 | {.Opcode: AArch64::LD1Onev8h_POST, .PatternStart: 271, .NumPatterns: 1 }, |
| 23043 | {.Opcode: AArch64::LD1RB_D_IMM, .PatternStart: 272, .NumPatterns: 1 }, |
| 23044 | {.Opcode: AArch64::LD1RB_H_IMM, .PatternStart: 273, .NumPatterns: 1 }, |
| 23045 | {.Opcode: AArch64::LD1RB_IMM, .PatternStart: 274, .NumPatterns: 1 }, |
| 23046 | {.Opcode: AArch64::LD1RB_S_IMM, .PatternStart: 275, .NumPatterns: 1 }, |
| 23047 | {.Opcode: AArch64::LD1RD_IMM, .PatternStart: 276, .NumPatterns: 1 }, |
| 23048 | {.Opcode: AArch64::LD1RH_D_IMM, .PatternStart: 277, .NumPatterns: 1 }, |
| 23049 | {.Opcode: AArch64::LD1RH_IMM, .PatternStart: 278, .NumPatterns: 1 }, |
| 23050 | {.Opcode: AArch64::LD1RH_S_IMM, .PatternStart: 279, .NumPatterns: 1 }, |
| 23051 | {.Opcode: AArch64::LD1RO_B_IMM, .PatternStart: 280, .NumPatterns: 1 }, |
| 23052 | {.Opcode: AArch64::LD1RO_D_IMM, .PatternStart: 281, .NumPatterns: 1 }, |
| 23053 | {.Opcode: AArch64::LD1RO_H_IMM, .PatternStart: 282, .NumPatterns: 1 }, |
| 23054 | {.Opcode: AArch64::LD1RO_W_IMM, .PatternStart: 283, .NumPatterns: 1 }, |
| 23055 | {.Opcode: AArch64::LD1RQ_B_IMM, .PatternStart: 284, .NumPatterns: 1 }, |
| 23056 | {.Opcode: AArch64::LD1RQ_D_IMM, .PatternStart: 285, .NumPatterns: 1 }, |
| 23057 | {.Opcode: AArch64::LD1RQ_H_IMM, .PatternStart: 286, .NumPatterns: 1 }, |
| 23058 | {.Opcode: AArch64::LD1RQ_W_IMM, .PatternStart: 287, .NumPatterns: 1 }, |
| 23059 | {.Opcode: AArch64::LD1RSB_D_IMM, .PatternStart: 288, .NumPatterns: 1 }, |
| 23060 | {.Opcode: AArch64::LD1RSB_H_IMM, .PatternStart: 289, .NumPatterns: 1 }, |
| 23061 | {.Opcode: AArch64::LD1RSB_S_IMM, .PatternStart: 290, .NumPatterns: 1 }, |
| 23062 | {.Opcode: AArch64::LD1RSH_D_IMM, .PatternStart: 291, .NumPatterns: 1 }, |
| 23063 | {.Opcode: AArch64::LD1RSH_S_IMM, .PatternStart: 292, .NumPatterns: 1 }, |
| 23064 | {.Opcode: AArch64::LD1RSW_IMM, .PatternStart: 293, .NumPatterns: 1 }, |
| 23065 | {.Opcode: AArch64::LD1RW_D_IMM, .PatternStart: 294, .NumPatterns: 1 }, |
| 23066 | {.Opcode: AArch64::LD1RW_IMM, .PatternStart: 295, .NumPatterns: 1 }, |
| 23067 | {.Opcode: AArch64::LD1Rv16b_POST, .PatternStart: 296, .NumPatterns: 1 }, |
| 23068 | {.Opcode: AArch64::LD1Rv1d_POST, .PatternStart: 297, .NumPatterns: 1 }, |
| 23069 | {.Opcode: AArch64::LD1Rv2d_POST, .PatternStart: 298, .NumPatterns: 1 }, |
| 23070 | {.Opcode: AArch64::LD1Rv2s_POST, .PatternStart: 299, .NumPatterns: 1 }, |
| 23071 | {.Opcode: AArch64::LD1Rv4h_POST, .PatternStart: 300, .NumPatterns: 1 }, |
| 23072 | {.Opcode: AArch64::LD1Rv4s_POST, .PatternStart: 301, .NumPatterns: 1 }, |
| 23073 | {.Opcode: AArch64::LD1Rv8b_POST, .PatternStart: 302, .NumPatterns: 1 }, |
| 23074 | {.Opcode: AArch64::LD1Rv8h_POST, .PatternStart: 303, .NumPatterns: 1 }, |
| 23075 | {.Opcode: AArch64::LD1SB_D_IMM, .PatternStart: 304, .NumPatterns: 1 }, |
| 23076 | {.Opcode: AArch64::LD1SB_H_IMM, .PatternStart: 305, .NumPatterns: 1 }, |
| 23077 | {.Opcode: AArch64::LD1SB_S_IMM, .PatternStart: 306, .NumPatterns: 1 }, |
| 23078 | {.Opcode: AArch64::LD1SH_D_IMM, .PatternStart: 307, .NumPatterns: 1 }, |
| 23079 | {.Opcode: AArch64::LD1SH_S_IMM, .PatternStart: 308, .NumPatterns: 1 }, |
| 23080 | {.Opcode: AArch64::LD1SW_D_IMM, .PatternStart: 309, .NumPatterns: 1 }, |
| 23081 | {.Opcode: AArch64::LD1Threev16b_POST, .PatternStart: 310, .NumPatterns: 1 }, |
| 23082 | {.Opcode: AArch64::LD1Threev1d_POST, .PatternStart: 311, .NumPatterns: 1 }, |
| 23083 | {.Opcode: AArch64::LD1Threev2d_POST, .PatternStart: 312, .NumPatterns: 1 }, |
| 23084 | {.Opcode: AArch64::LD1Threev2s_POST, .PatternStart: 313, .NumPatterns: 1 }, |
| 23085 | {.Opcode: AArch64::LD1Threev4h_POST, .PatternStart: 314, .NumPatterns: 1 }, |
| 23086 | {.Opcode: AArch64::LD1Threev4s_POST, .PatternStart: 315, .NumPatterns: 1 }, |
| 23087 | {.Opcode: AArch64::LD1Threev8b_POST, .PatternStart: 316, .NumPatterns: 1 }, |
| 23088 | {.Opcode: AArch64::LD1Threev8h_POST, .PatternStart: 317, .NumPatterns: 1 }, |
| 23089 | {.Opcode: AArch64::LD1Twov16b_POST, .PatternStart: 318, .NumPatterns: 1 }, |
| 23090 | {.Opcode: AArch64::LD1Twov1d_POST, .PatternStart: 319, .NumPatterns: 1 }, |
| 23091 | {.Opcode: AArch64::LD1Twov2d_POST, .PatternStart: 320, .NumPatterns: 1 }, |
| 23092 | {.Opcode: AArch64::LD1Twov2s_POST, .PatternStart: 321, .NumPatterns: 1 }, |
| 23093 | {.Opcode: AArch64::LD1Twov4h_POST, .PatternStart: 322, .NumPatterns: 1 }, |
| 23094 | {.Opcode: AArch64::LD1Twov4s_POST, .PatternStart: 323, .NumPatterns: 1 }, |
| 23095 | {.Opcode: AArch64::LD1Twov8b_POST, .PatternStart: 324, .NumPatterns: 1 }, |
| 23096 | {.Opcode: AArch64::LD1Twov8h_POST, .PatternStart: 325, .NumPatterns: 1 }, |
| 23097 | {.Opcode: AArch64::LD1W_2Z_IMM, .PatternStart: 326, .NumPatterns: 1 }, |
| 23098 | {.Opcode: AArch64::LD1W_2Z_STRIDED_IMM, .PatternStart: 327, .NumPatterns: 1 }, |
| 23099 | {.Opcode: AArch64::LD1W_4Z_IMM, .PatternStart: 328, .NumPatterns: 1 }, |
| 23100 | {.Opcode: AArch64::LD1W_4Z_STRIDED_IMM, .PatternStart: 329, .NumPatterns: 1 }, |
| 23101 | {.Opcode: AArch64::LD1W_D_IMM, .PatternStart: 330, .NumPatterns: 1 }, |
| 23102 | {.Opcode: AArch64::LD1W_IMM, .PatternStart: 331, .NumPatterns: 1 }, |
| 23103 | {.Opcode: AArch64::LD1W_Q_IMM, .PatternStart: 332, .NumPatterns: 1 }, |
| 23104 | {.Opcode: AArch64::LD1_MXIPXX_H_B, .PatternStart: 333, .NumPatterns: 1 }, |
| 23105 | {.Opcode: AArch64::LD1_MXIPXX_H_D, .PatternStart: 334, .NumPatterns: 1 }, |
| 23106 | {.Opcode: AArch64::LD1_MXIPXX_H_H, .PatternStart: 335, .NumPatterns: 1 }, |
| 23107 | {.Opcode: AArch64::LD1_MXIPXX_H_Q, .PatternStart: 336, .NumPatterns: 1 }, |
| 23108 | {.Opcode: AArch64::LD1_MXIPXX_H_S, .PatternStart: 337, .NumPatterns: 1 }, |
| 23109 | {.Opcode: AArch64::LD1_MXIPXX_V_B, .PatternStart: 338, .NumPatterns: 1 }, |
| 23110 | {.Opcode: AArch64::LD1_MXIPXX_V_D, .PatternStart: 339, .NumPatterns: 1 }, |
| 23111 | {.Opcode: AArch64::LD1_MXIPXX_V_H, .PatternStart: 340, .NumPatterns: 1 }, |
| 23112 | {.Opcode: AArch64::LD1_MXIPXX_V_Q, .PatternStart: 341, .NumPatterns: 1 }, |
| 23113 | {.Opcode: AArch64::LD1_MXIPXX_V_S, .PatternStart: 342, .NumPatterns: 1 }, |
| 23114 | {.Opcode: AArch64::LD1i16_POST, .PatternStart: 343, .NumPatterns: 1 }, |
| 23115 | {.Opcode: AArch64::LD1i32_POST, .PatternStart: 344, .NumPatterns: 1 }, |
| 23116 | {.Opcode: AArch64::LD1i64_POST, .PatternStart: 345, .NumPatterns: 1 }, |
| 23117 | {.Opcode: AArch64::LD1i8_POST, .PatternStart: 346, .NumPatterns: 1 }, |
| 23118 | {.Opcode: AArch64::LD2B_IMM, .PatternStart: 347, .NumPatterns: 1 }, |
| 23119 | {.Opcode: AArch64::LD2D_IMM, .PatternStart: 348, .NumPatterns: 1 }, |
| 23120 | {.Opcode: AArch64::LD2H_IMM, .PatternStart: 349, .NumPatterns: 1 }, |
| 23121 | {.Opcode: AArch64::LD2Q_IMM, .PatternStart: 350, .NumPatterns: 1 }, |
| 23122 | {.Opcode: AArch64::LD2Rv16b_POST, .PatternStart: 351, .NumPatterns: 1 }, |
| 23123 | {.Opcode: AArch64::LD2Rv1d_POST, .PatternStart: 352, .NumPatterns: 1 }, |
| 23124 | {.Opcode: AArch64::LD2Rv2d_POST, .PatternStart: 353, .NumPatterns: 1 }, |
| 23125 | {.Opcode: AArch64::LD2Rv2s_POST, .PatternStart: 354, .NumPatterns: 1 }, |
| 23126 | {.Opcode: AArch64::LD2Rv4h_POST, .PatternStart: 355, .NumPatterns: 1 }, |
| 23127 | {.Opcode: AArch64::LD2Rv4s_POST, .PatternStart: 356, .NumPatterns: 1 }, |
| 23128 | {.Opcode: AArch64::LD2Rv8b_POST, .PatternStart: 357, .NumPatterns: 1 }, |
| 23129 | {.Opcode: AArch64::LD2Rv8h_POST, .PatternStart: 358, .NumPatterns: 1 }, |
| 23130 | {.Opcode: AArch64::LD2Twov16b_POST, .PatternStart: 359, .NumPatterns: 1 }, |
| 23131 | {.Opcode: AArch64::LD2Twov2d_POST, .PatternStart: 360, .NumPatterns: 1 }, |
| 23132 | {.Opcode: AArch64::LD2Twov2s_POST, .PatternStart: 361, .NumPatterns: 1 }, |
| 23133 | {.Opcode: AArch64::LD2Twov4h_POST, .PatternStart: 362, .NumPatterns: 1 }, |
| 23134 | {.Opcode: AArch64::LD2Twov4s_POST, .PatternStart: 363, .NumPatterns: 1 }, |
| 23135 | {.Opcode: AArch64::LD2Twov8b_POST, .PatternStart: 364, .NumPatterns: 1 }, |
| 23136 | {.Opcode: AArch64::LD2Twov8h_POST, .PatternStart: 365, .NumPatterns: 1 }, |
| 23137 | {.Opcode: AArch64::LD2W_IMM, .PatternStart: 366, .NumPatterns: 1 }, |
| 23138 | {.Opcode: AArch64::LD2i16_POST, .PatternStart: 367, .NumPatterns: 1 }, |
| 23139 | {.Opcode: AArch64::LD2i32_POST, .PatternStart: 368, .NumPatterns: 1 }, |
| 23140 | {.Opcode: AArch64::LD2i64_POST, .PatternStart: 369, .NumPatterns: 1 }, |
| 23141 | {.Opcode: AArch64::LD2i8_POST, .PatternStart: 370, .NumPatterns: 1 }, |
| 23142 | {.Opcode: AArch64::LD3B_IMM, .PatternStart: 371, .NumPatterns: 1 }, |
| 23143 | {.Opcode: AArch64::LD3D_IMM, .PatternStart: 372, .NumPatterns: 1 }, |
| 23144 | {.Opcode: AArch64::LD3H_IMM, .PatternStart: 373, .NumPatterns: 1 }, |
| 23145 | {.Opcode: AArch64::LD3Q_IMM, .PatternStart: 374, .NumPatterns: 1 }, |
| 23146 | {.Opcode: AArch64::LD3Rv16b_POST, .PatternStart: 375, .NumPatterns: 1 }, |
| 23147 | {.Opcode: AArch64::LD3Rv1d_POST, .PatternStart: 376, .NumPatterns: 1 }, |
| 23148 | {.Opcode: AArch64::LD3Rv2d_POST, .PatternStart: 377, .NumPatterns: 1 }, |
| 23149 | {.Opcode: AArch64::LD3Rv2s_POST, .PatternStart: 378, .NumPatterns: 1 }, |
| 23150 | {.Opcode: AArch64::LD3Rv4h_POST, .PatternStart: 379, .NumPatterns: 1 }, |
| 23151 | {.Opcode: AArch64::LD3Rv4s_POST, .PatternStart: 380, .NumPatterns: 1 }, |
| 23152 | {.Opcode: AArch64::LD3Rv8b_POST, .PatternStart: 381, .NumPatterns: 1 }, |
| 23153 | {.Opcode: AArch64::LD3Rv8h_POST, .PatternStart: 382, .NumPatterns: 1 }, |
| 23154 | {.Opcode: AArch64::LD3Threev16b_POST, .PatternStart: 383, .NumPatterns: 1 }, |
| 23155 | {.Opcode: AArch64::LD3Threev2d_POST, .PatternStart: 384, .NumPatterns: 1 }, |
| 23156 | {.Opcode: AArch64::LD3Threev2s_POST, .PatternStart: 385, .NumPatterns: 1 }, |
| 23157 | {.Opcode: AArch64::LD3Threev4h_POST, .PatternStart: 386, .NumPatterns: 1 }, |
| 23158 | {.Opcode: AArch64::LD3Threev4s_POST, .PatternStart: 387, .NumPatterns: 1 }, |
| 23159 | {.Opcode: AArch64::LD3Threev8b_POST, .PatternStart: 388, .NumPatterns: 1 }, |
| 23160 | {.Opcode: AArch64::LD3Threev8h_POST, .PatternStart: 389, .NumPatterns: 1 }, |
| 23161 | {.Opcode: AArch64::LD3W_IMM, .PatternStart: 390, .NumPatterns: 1 }, |
| 23162 | {.Opcode: AArch64::LD3i16_POST, .PatternStart: 391, .NumPatterns: 1 }, |
| 23163 | {.Opcode: AArch64::LD3i32_POST, .PatternStart: 392, .NumPatterns: 1 }, |
| 23164 | {.Opcode: AArch64::LD3i64_POST, .PatternStart: 393, .NumPatterns: 1 }, |
| 23165 | {.Opcode: AArch64::LD3i8_POST, .PatternStart: 394, .NumPatterns: 1 }, |
| 23166 | {.Opcode: AArch64::LD4B_IMM, .PatternStart: 395, .NumPatterns: 1 }, |
| 23167 | {.Opcode: AArch64::LD4D_IMM, .PatternStart: 396, .NumPatterns: 1 }, |
| 23168 | {.Opcode: AArch64::LD4Fourv16b_POST, .PatternStart: 397, .NumPatterns: 1 }, |
| 23169 | {.Opcode: AArch64::LD4Fourv2d_POST, .PatternStart: 398, .NumPatterns: 1 }, |
| 23170 | {.Opcode: AArch64::LD4Fourv2s_POST, .PatternStart: 399, .NumPatterns: 1 }, |
| 23171 | {.Opcode: AArch64::LD4Fourv4h_POST, .PatternStart: 400, .NumPatterns: 1 }, |
| 23172 | {.Opcode: AArch64::LD4Fourv4s_POST, .PatternStart: 401, .NumPatterns: 1 }, |
| 23173 | {.Opcode: AArch64::LD4Fourv8b_POST, .PatternStart: 402, .NumPatterns: 1 }, |
| 23174 | {.Opcode: AArch64::LD4Fourv8h_POST, .PatternStart: 403, .NumPatterns: 1 }, |
| 23175 | {.Opcode: AArch64::LD4H_IMM, .PatternStart: 404, .NumPatterns: 1 }, |
| 23176 | {.Opcode: AArch64::LD4Q_IMM, .PatternStart: 405, .NumPatterns: 1 }, |
| 23177 | {.Opcode: AArch64::LD4Rv16b_POST, .PatternStart: 406, .NumPatterns: 1 }, |
| 23178 | {.Opcode: AArch64::LD4Rv1d_POST, .PatternStart: 407, .NumPatterns: 1 }, |
| 23179 | {.Opcode: AArch64::LD4Rv2d_POST, .PatternStart: 408, .NumPatterns: 1 }, |
| 23180 | {.Opcode: AArch64::LD4Rv2s_POST, .PatternStart: 409, .NumPatterns: 1 }, |
| 23181 | {.Opcode: AArch64::LD4Rv4h_POST, .PatternStart: 410, .NumPatterns: 1 }, |
| 23182 | {.Opcode: AArch64::LD4Rv4s_POST, .PatternStart: 411, .NumPatterns: 1 }, |
| 23183 | {.Opcode: AArch64::LD4Rv8b_POST, .PatternStart: 412, .NumPatterns: 1 }, |
| 23184 | {.Opcode: AArch64::LD4Rv8h_POST, .PatternStart: 413, .NumPatterns: 1 }, |
| 23185 | {.Opcode: AArch64::LD4W_IMM, .PatternStart: 414, .NumPatterns: 1 }, |
| 23186 | {.Opcode: AArch64::LD4i16_POST, .PatternStart: 415, .NumPatterns: 1 }, |
| 23187 | {.Opcode: AArch64::LD4i32_POST, .PatternStart: 416, .NumPatterns: 1 }, |
| 23188 | {.Opcode: AArch64::LD4i64_POST, .PatternStart: 417, .NumPatterns: 1 }, |
| 23189 | {.Opcode: AArch64::LD4i8_POST, .PatternStart: 418, .NumPatterns: 1 }, |
| 23190 | {.Opcode: AArch64::LDADDB, .PatternStart: 419, .NumPatterns: 1 }, |
| 23191 | {.Opcode: AArch64::LDADDH, .PatternStart: 420, .NumPatterns: 1 }, |
| 23192 | {.Opcode: AArch64::LDADDLB, .PatternStart: 421, .NumPatterns: 1 }, |
| 23193 | {.Opcode: AArch64::LDADDLH, .PatternStart: 422, .NumPatterns: 1 }, |
| 23194 | {.Opcode: AArch64::LDADDLW, .PatternStart: 423, .NumPatterns: 1 }, |
| 23195 | {.Opcode: AArch64::LDADDLX, .PatternStart: 424, .NumPatterns: 1 }, |
| 23196 | {.Opcode: AArch64::LDADDW, .PatternStart: 425, .NumPatterns: 1 }, |
| 23197 | {.Opcode: AArch64::LDADDX, .PatternStart: 426, .NumPatterns: 1 }, |
| 23198 | {.Opcode: AArch64::LDAPURBi, .PatternStart: 427, .NumPatterns: 1 }, |
| 23199 | {.Opcode: AArch64::LDAPURHi, .PatternStart: 428, .NumPatterns: 1 }, |
| 23200 | {.Opcode: AArch64::LDAPURSBWi, .PatternStart: 429, .NumPatterns: 1 }, |
| 23201 | {.Opcode: AArch64::LDAPURSBXi, .PatternStart: 430, .NumPatterns: 1 }, |
| 23202 | {.Opcode: AArch64::LDAPURSHWi, .PatternStart: 431, .NumPatterns: 1 }, |
| 23203 | {.Opcode: AArch64::LDAPURSHXi, .PatternStart: 432, .NumPatterns: 1 }, |
| 23204 | {.Opcode: AArch64::LDAPURSWi, .PatternStart: 433, .NumPatterns: 1 }, |
| 23205 | {.Opcode: AArch64::LDAPURXi, .PatternStart: 434, .NumPatterns: 1 }, |
| 23206 | {.Opcode: AArch64::LDAPURbi, .PatternStart: 435, .NumPatterns: 1 }, |
| 23207 | {.Opcode: AArch64::LDAPURdi, .PatternStart: 436, .NumPatterns: 1 }, |
| 23208 | {.Opcode: AArch64::LDAPURhi, .PatternStart: 437, .NumPatterns: 1 }, |
| 23209 | {.Opcode: AArch64::LDAPURi, .PatternStart: 438, .NumPatterns: 1 }, |
| 23210 | {.Opcode: AArch64::LDAPURqi, .PatternStart: 439, .NumPatterns: 1 }, |
| 23211 | {.Opcode: AArch64::LDAPURsi, .PatternStart: 440, .NumPatterns: 1 }, |
| 23212 | {.Opcode: AArch64::LDCLRB, .PatternStart: 441, .NumPatterns: 1 }, |
| 23213 | {.Opcode: AArch64::LDCLRH, .PatternStart: 442, .NumPatterns: 1 }, |
| 23214 | {.Opcode: AArch64::LDCLRLB, .PatternStart: 443, .NumPatterns: 1 }, |
| 23215 | {.Opcode: AArch64::LDCLRLH, .PatternStart: 444, .NumPatterns: 1 }, |
| 23216 | {.Opcode: AArch64::LDCLRLW, .PatternStart: 445, .NumPatterns: 1 }, |
| 23217 | {.Opcode: AArch64::LDCLRLX, .PatternStart: 446, .NumPatterns: 1 }, |
| 23218 | {.Opcode: AArch64::LDCLRW, .PatternStart: 447, .NumPatterns: 1 }, |
| 23219 | {.Opcode: AArch64::LDCLRX, .PatternStart: 448, .NumPatterns: 1 }, |
| 23220 | {.Opcode: AArch64::LDEORB, .PatternStart: 449, .NumPatterns: 1 }, |
| 23221 | {.Opcode: AArch64::LDEORH, .PatternStart: 450, .NumPatterns: 1 }, |
| 23222 | {.Opcode: AArch64::LDEORLB, .PatternStart: 451, .NumPatterns: 1 }, |
| 23223 | {.Opcode: AArch64::LDEORLH, .PatternStart: 452, .NumPatterns: 1 }, |
| 23224 | {.Opcode: AArch64::LDEORLW, .PatternStart: 453, .NumPatterns: 1 }, |
| 23225 | {.Opcode: AArch64::LDEORLX, .PatternStart: 454, .NumPatterns: 1 }, |
| 23226 | {.Opcode: AArch64::LDEORW, .PatternStart: 455, .NumPatterns: 1 }, |
| 23227 | {.Opcode: AArch64::LDEORX, .PatternStart: 456, .NumPatterns: 1 }, |
| 23228 | {.Opcode: AArch64::LDFF1B, .PatternStart: 457, .NumPatterns: 1 }, |
| 23229 | {.Opcode: AArch64::LDFF1B_D, .PatternStart: 458, .NumPatterns: 1 }, |
| 23230 | {.Opcode: AArch64::LDFF1B_H, .PatternStart: 459, .NumPatterns: 1 }, |
| 23231 | {.Opcode: AArch64::LDFF1B_S, .PatternStart: 460, .NumPatterns: 1 }, |
| 23232 | {.Opcode: AArch64::LDFF1D, .PatternStart: 461, .NumPatterns: 1 }, |
| 23233 | {.Opcode: AArch64::LDFF1H, .PatternStart: 462, .NumPatterns: 1 }, |
| 23234 | {.Opcode: AArch64::LDFF1H_D, .PatternStart: 463, .NumPatterns: 1 }, |
| 23235 | {.Opcode: AArch64::LDFF1H_S, .PatternStart: 464, .NumPatterns: 1 }, |
| 23236 | {.Opcode: AArch64::LDFF1SB_D, .PatternStart: 465, .NumPatterns: 1 }, |
| 23237 | {.Opcode: AArch64::LDFF1SB_H, .PatternStart: 466, .NumPatterns: 1 }, |
| 23238 | {.Opcode: AArch64::LDFF1SB_S, .PatternStart: 467, .NumPatterns: 1 }, |
| 23239 | {.Opcode: AArch64::LDFF1SH_D, .PatternStart: 468, .NumPatterns: 1 }, |
| 23240 | {.Opcode: AArch64::LDFF1SH_S, .PatternStart: 469, .NumPatterns: 1 }, |
| 23241 | {.Opcode: AArch64::LDFF1SW_D, .PatternStart: 470, .NumPatterns: 1 }, |
| 23242 | {.Opcode: AArch64::LDFF1W, .PatternStart: 471, .NumPatterns: 1 }, |
| 23243 | {.Opcode: AArch64::LDFF1W_D, .PatternStart: 472, .NumPatterns: 1 }, |
| 23244 | {.Opcode: AArch64::LDG, .PatternStart: 473, .NumPatterns: 1 }, |
| 23245 | {.Opcode: AArch64::LDNF1B_D_IMM, .PatternStart: 474, .NumPatterns: 1 }, |
| 23246 | {.Opcode: AArch64::LDNF1B_H_IMM, .PatternStart: 475, .NumPatterns: 1 }, |
| 23247 | {.Opcode: AArch64::LDNF1B_IMM, .PatternStart: 476, .NumPatterns: 1 }, |
| 23248 | {.Opcode: AArch64::LDNF1B_S_IMM, .PatternStart: 477, .NumPatterns: 1 }, |
| 23249 | {.Opcode: AArch64::LDNF1D_IMM, .PatternStart: 478, .NumPatterns: 1 }, |
| 23250 | {.Opcode: AArch64::LDNF1H_D_IMM, .PatternStart: 479, .NumPatterns: 1 }, |
| 23251 | {.Opcode: AArch64::LDNF1H_IMM, .PatternStart: 480, .NumPatterns: 1 }, |
| 23252 | {.Opcode: AArch64::LDNF1H_S_IMM, .PatternStart: 481, .NumPatterns: 1 }, |
| 23253 | {.Opcode: AArch64::LDNF1SB_D_IMM, .PatternStart: 482, .NumPatterns: 1 }, |
| 23254 | {.Opcode: AArch64::LDNF1SB_H_IMM, .PatternStart: 483, .NumPatterns: 1 }, |
| 23255 | {.Opcode: AArch64::LDNF1SB_S_IMM, .PatternStart: 484, .NumPatterns: 1 }, |
| 23256 | {.Opcode: AArch64::LDNF1SH_D_IMM, .PatternStart: 485, .NumPatterns: 1 }, |
| 23257 | {.Opcode: AArch64::LDNF1SH_S_IMM, .PatternStart: 486, .NumPatterns: 1 }, |
| 23258 | {.Opcode: AArch64::LDNF1SW_D_IMM, .PatternStart: 487, .NumPatterns: 1 }, |
| 23259 | {.Opcode: AArch64::LDNF1W_D_IMM, .PatternStart: 488, .NumPatterns: 1 }, |
| 23260 | {.Opcode: AArch64::LDNF1W_IMM, .PatternStart: 489, .NumPatterns: 1 }, |
| 23261 | {.Opcode: AArch64::LDNPDi, .PatternStart: 490, .NumPatterns: 1 }, |
| 23262 | {.Opcode: AArch64::LDNPQi, .PatternStart: 491, .NumPatterns: 1 }, |
| 23263 | {.Opcode: AArch64::LDNPSi, .PatternStart: 492, .NumPatterns: 1 }, |
| 23264 | {.Opcode: AArch64::LDNPWi, .PatternStart: 493, .NumPatterns: 1 }, |
| 23265 | {.Opcode: AArch64::LDNPXi, .PatternStart: 494, .NumPatterns: 1 }, |
| 23266 | {.Opcode: AArch64::LDNT1B_2Z_IMM, .PatternStart: 495, .NumPatterns: 1 }, |
| 23267 | {.Opcode: AArch64::LDNT1B_2Z_STRIDED_IMM, .PatternStart: 496, .NumPatterns: 1 }, |
| 23268 | {.Opcode: AArch64::LDNT1B_4Z_IMM, .PatternStart: 497, .NumPatterns: 1 }, |
| 23269 | {.Opcode: AArch64::LDNT1B_4Z_STRIDED_IMM, .PatternStart: 498, .NumPatterns: 1 }, |
| 23270 | {.Opcode: AArch64::LDNT1B_ZRI, .PatternStart: 499, .NumPatterns: 1 }, |
| 23271 | {.Opcode: AArch64::LDNT1B_ZZR_D, .PatternStart: 500, .NumPatterns: 1 }, |
| 23272 | {.Opcode: AArch64::LDNT1B_ZZR_S, .PatternStart: 501, .NumPatterns: 1 }, |
| 23273 | {.Opcode: AArch64::LDNT1D_2Z_IMM, .PatternStart: 502, .NumPatterns: 1 }, |
| 23274 | {.Opcode: AArch64::LDNT1D_2Z_STRIDED_IMM, .PatternStart: 503, .NumPatterns: 1 }, |
| 23275 | {.Opcode: AArch64::LDNT1D_4Z_IMM, .PatternStart: 504, .NumPatterns: 1 }, |
| 23276 | {.Opcode: AArch64::LDNT1D_4Z_STRIDED_IMM, .PatternStart: 505, .NumPatterns: 1 }, |
| 23277 | {.Opcode: AArch64::LDNT1D_ZRI, .PatternStart: 506, .NumPatterns: 1 }, |
| 23278 | {.Opcode: AArch64::LDNT1D_ZZR_D, .PatternStart: 507, .NumPatterns: 1 }, |
| 23279 | {.Opcode: AArch64::LDNT1H_2Z_IMM, .PatternStart: 508, .NumPatterns: 1 }, |
| 23280 | {.Opcode: AArch64::LDNT1H_2Z_STRIDED_IMM, .PatternStart: 509, .NumPatterns: 1 }, |
| 23281 | {.Opcode: AArch64::LDNT1H_4Z_IMM, .PatternStart: 510, .NumPatterns: 1 }, |
| 23282 | {.Opcode: AArch64::LDNT1H_4Z_STRIDED_IMM, .PatternStart: 511, .NumPatterns: 1 }, |
| 23283 | {.Opcode: AArch64::LDNT1H_ZRI, .PatternStart: 512, .NumPatterns: 1 }, |
| 23284 | {.Opcode: AArch64::LDNT1H_ZZR_D, .PatternStart: 513, .NumPatterns: 1 }, |
| 23285 | {.Opcode: AArch64::LDNT1H_ZZR_S, .PatternStart: 514, .NumPatterns: 1 }, |
| 23286 | {.Opcode: AArch64::LDNT1SB_ZZR_D, .PatternStart: 515, .NumPatterns: 1 }, |
| 23287 | {.Opcode: AArch64::LDNT1SB_ZZR_S, .PatternStart: 516, .NumPatterns: 1 }, |
| 23288 | {.Opcode: AArch64::LDNT1SH_ZZR_D, .PatternStart: 517, .NumPatterns: 1 }, |
| 23289 | {.Opcode: AArch64::LDNT1SH_ZZR_S, .PatternStart: 518, .NumPatterns: 1 }, |
| 23290 | {.Opcode: AArch64::LDNT1SW_ZZR_D, .PatternStart: 519, .NumPatterns: 1 }, |
| 23291 | {.Opcode: AArch64::LDNT1W_2Z_IMM, .PatternStart: 520, .NumPatterns: 1 }, |
| 23292 | {.Opcode: AArch64::LDNT1W_2Z_STRIDED_IMM, .PatternStart: 521, .NumPatterns: 1 }, |
| 23293 | {.Opcode: AArch64::LDNT1W_4Z_IMM, .PatternStart: 522, .NumPatterns: 1 }, |
| 23294 | {.Opcode: AArch64::LDNT1W_4Z_STRIDED_IMM, .PatternStart: 523, .NumPatterns: 1 }, |
| 23295 | {.Opcode: AArch64::LDNT1W_ZRI, .PatternStart: 524, .NumPatterns: 1 }, |
| 23296 | {.Opcode: AArch64::LDNT1W_ZZR_D, .PatternStart: 525, .NumPatterns: 1 }, |
| 23297 | {.Opcode: AArch64::LDNT1W_ZZR_S, .PatternStart: 526, .NumPatterns: 1 }, |
| 23298 | {.Opcode: AArch64::LDPDi, .PatternStart: 527, .NumPatterns: 1 }, |
| 23299 | {.Opcode: AArch64::LDPQi, .PatternStart: 528, .NumPatterns: 1 }, |
| 23300 | {.Opcode: AArch64::LDPSWi, .PatternStart: 529, .NumPatterns: 1 }, |
| 23301 | {.Opcode: AArch64::LDPSi, .PatternStart: 530, .NumPatterns: 1 }, |
| 23302 | {.Opcode: AArch64::LDPWi, .PatternStart: 531, .NumPatterns: 1 }, |
| 23303 | {.Opcode: AArch64::LDPXi, .PatternStart: 532, .NumPatterns: 1 }, |
| 23304 | {.Opcode: AArch64::LDRAAindexed, .PatternStart: 533, .NumPatterns: 1 }, |
| 23305 | {.Opcode: AArch64::LDRABindexed, .PatternStart: 534, .NumPatterns: 1 }, |
| 23306 | {.Opcode: AArch64::LDRBBroX, .PatternStart: 535, .NumPatterns: 1 }, |
| 23307 | {.Opcode: AArch64::LDRBBui, .PatternStart: 536, .NumPatterns: 1 }, |
| 23308 | {.Opcode: AArch64::LDRBroX, .PatternStart: 537, .NumPatterns: 1 }, |
| 23309 | {.Opcode: AArch64::LDRBui, .PatternStart: 538, .NumPatterns: 1 }, |
| 23310 | {.Opcode: AArch64::LDRDroX, .PatternStart: 539, .NumPatterns: 1 }, |
| 23311 | {.Opcode: AArch64::LDRDui, .PatternStart: 540, .NumPatterns: 1 }, |
| 23312 | {.Opcode: AArch64::LDRHHroX, .PatternStart: 541, .NumPatterns: 1 }, |
| 23313 | {.Opcode: AArch64::LDRHHui, .PatternStart: 542, .NumPatterns: 1 }, |
| 23314 | {.Opcode: AArch64::LDRHroX, .PatternStart: 543, .NumPatterns: 1 }, |
| 23315 | {.Opcode: AArch64::LDRHui, .PatternStart: 544, .NumPatterns: 1 }, |
| 23316 | {.Opcode: AArch64::LDRQroX, .PatternStart: 545, .NumPatterns: 1 }, |
| 23317 | {.Opcode: AArch64::LDRQui, .PatternStart: 546, .NumPatterns: 1 }, |
| 23318 | {.Opcode: AArch64::LDRSBWroX, .PatternStart: 547, .NumPatterns: 1 }, |
| 23319 | {.Opcode: AArch64::LDRSBWui, .PatternStart: 548, .NumPatterns: 1 }, |
| 23320 | {.Opcode: AArch64::LDRSBXroX, .PatternStart: 549, .NumPatterns: 1 }, |
| 23321 | {.Opcode: AArch64::LDRSBXui, .PatternStart: 550, .NumPatterns: 1 }, |
| 23322 | {.Opcode: AArch64::LDRSHWroX, .PatternStart: 551, .NumPatterns: 1 }, |
| 23323 | {.Opcode: AArch64::LDRSHWui, .PatternStart: 552, .NumPatterns: 1 }, |
| 23324 | {.Opcode: AArch64::LDRSHXroX, .PatternStart: 553, .NumPatterns: 1 }, |
| 23325 | {.Opcode: AArch64::LDRSHXui, .PatternStart: 554, .NumPatterns: 1 }, |
| 23326 | {.Opcode: AArch64::LDRSWroX, .PatternStart: 555, .NumPatterns: 1 }, |
| 23327 | {.Opcode: AArch64::LDRSWui, .PatternStart: 556, .NumPatterns: 1 }, |
| 23328 | {.Opcode: AArch64::LDRSroX, .PatternStart: 557, .NumPatterns: 1 }, |
| 23329 | {.Opcode: AArch64::LDRSui, .PatternStart: 558, .NumPatterns: 1 }, |
| 23330 | {.Opcode: AArch64::LDRWroX, .PatternStart: 559, .NumPatterns: 1 }, |
| 23331 | {.Opcode: AArch64::LDRWui, .PatternStart: 560, .NumPatterns: 1 }, |
| 23332 | {.Opcode: AArch64::LDRXroX, .PatternStart: 561, .NumPatterns: 1 }, |
| 23333 | {.Opcode: AArch64::LDRXui, .PatternStart: 562, .NumPatterns: 1 }, |
| 23334 | {.Opcode: AArch64::LDR_PXI, .PatternStart: 563, .NumPatterns: 1 }, |
| 23335 | {.Opcode: AArch64::LDR_ZA, .PatternStart: 564, .NumPatterns: 1 }, |
| 23336 | {.Opcode: AArch64::LDR_ZXI, .PatternStart: 565, .NumPatterns: 1 }, |
| 23337 | {.Opcode: AArch64::LDSETB, .PatternStart: 566, .NumPatterns: 1 }, |
| 23338 | {.Opcode: AArch64::LDSETH, .PatternStart: 567, .NumPatterns: 1 }, |
| 23339 | {.Opcode: AArch64::LDSETLB, .PatternStart: 568, .NumPatterns: 1 }, |
| 23340 | {.Opcode: AArch64::LDSETLH, .PatternStart: 569, .NumPatterns: 1 }, |
| 23341 | {.Opcode: AArch64::LDSETLW, .PatternStart: 570, .NumPatterns: 1 }, |
| 23342 | {.Opcode: AArch64::LDSETLX, .PatternStart: 571, .NumPatterns: 1 }, |
| 23343 | {.Opcode: AArch64::LDSETW, .PatternStart: 572, .NumPatterns: 1 }, |
| 23344 | {.Opcode: AArch64::LDSETX, .PatternStart: 573, .NumPatterns: 1 }, |
| 23345 | {.Opcode: AArch64::LDSMAXB, .PatternStart: 574, .NumPatterns: 1 }, |
| 23346 | {.Opcode: AArch64::LDSMAXH, .PatternStart: 575, .NumPatterns: 1 }, |
| 23347 | {.Opcode: AArch64::LDSMAXLB, .PatternStart: 576, .NumPatterns: 1 }, |
| 23348 | {.Opcode: AArch64::LDSMAXLH, .PatternStart: 577, .NumPatterns: 1 }, |
| 23349 | {.Opcode: AArch64::LDSMAXLW, .PatternStart: 578, .NumPatterns: 1 }, |
| 23350 | {.Opcode: AArch64::LDSMAXLX, .PatternStart: 579, .NumPatterns: 1 }, |
| 23351 | {.Opcode: AArch64::LDSMAXW, .PatternStart: 580, .NumPatterns: 1 }, |
| 23352 | {.Opcode: AArch64::LDSMAXX, .PatternStart: 581, .NumPatterns: 1 }, |
| 23353 | {.Opcode: AArch64::LDSMINB, .PatternStart: 582, .NumPatterns: 1 }, |
| 23354 | {.Opcode: AArch64::LDSMINH, .PatternStart: 583, .NumPatterns: 1 }, |
| 23355 | {.Opcode: AArch64::LDSMINLB, .PatternStart: 584, .NumPatterns: 1 }, |
| 23356 | {.Opcode: AArch64::LDSMINLH, .PatternStart: 585, .NumPatterns: 1 }, |
| 23357 | {.Opcode: AArch64::LDSMINLW, .PatternStart: 586, .NumPatterns: 1 }, |
| 23358 | {.Opcode: AArch64::LDSMINLX, .PatternStart: 587, .NumPatterns: 1 }, |
| 23359 | {.Opcode: AArch64::LDSMINW, .PatternStart: 588, .NumPatterns: 1 }, |
| 23360 | {.Opcode: AArch64::LDSMINX, .PatternStart: 589, .NumPatterns: 1 }, |
| 23361 | {.Opcode: AArch64::LDTRBi, .PatternStart: 590, .NumPatterns: 1 }, |
| 23362 | {.Opcode: AArch64::LDTRHi, .PatternStart: 591, .NumPatterns: 1 }, |
| 23363 | {.Opcode: AArch64::LDTRSBWi, .PatternStart: 592, .NumPatterns: 1 }, |
| 23364 | {.Opcode: AArch64::LDTRSBXi, .PatternStart: 593, .NumPatterns: 1 }, |
| 23365 | {.Opcode: AArch64::LDTRSHWi, .PatternStart: 594, .NumPatterns: 1 }, |
| 23366 | {.Opcode: AArch64::LDTRSHXi, .PatternStart: 595, .NumPatterns: 1 }, |
| 23367 | {.Opcode: AArch64::LDTRSWi, .PatternStart: 596, .NumPatterns: 1 }, |
| 23368 | {.Opcode: AArch64::LDTRWi, .PatternStart: 597, .NumPatterns: 1 }, |
| 23369 | {.Opcode: AArch64::LDTRXi, .PatternStart: 598, .NumPatterns: 1 }, |
| 23370 | {.Opcode: AArch64::LDUMAXB, .PatternStart: 599, .NumPatterns: 1 }, |
| 23371 | {.Opcode: AArch64::LDUMAXH, .PatternStart: 600, .NumPatterns: 1 }, |
| 23372 | {.Opcode: AArch64::LDUMAXLB, .PatternStart: 601, .NumPatterns: 1 }, |
| 23373 | {.Opcode: AArch64::LDUMAXLH, .PatternStart: 602, .NumPatterns: 1 }, |
| 23374 | {.Opcode: AArch64::LDUMAXLW, .PatternStart: 603, .NumPatterns: 1 }, |
| 23375 | {.Opcode: AArch64::LDUMAXLX, .PatternStart: 604, .NumPatterns: 1 }, |
| 23376 | {.Opcode: AArch64::LDUMAXW, .PatternStart: 605, .NumPatterns: 1 }, |
| 23377 | {.Opcode: AArch64::LDUMAXX, .PatternStart: 606, .NumPatterns: 1 }, |
| 23378 | {.Opcode: AArch64::LDUMINB, .PatternStart: 607, .NumPatterns: 1 }, |
| 23379 | {.Opcode: AArch64::LDUMINH, .PatternStart: 608, .NumPatterns: 1 }, |
| 23380 | {.Opcode: AArch64::LDUMINLB, .PatternStart: 609, .NumPatterns: 1 }, |
| 23381 | {.Opcode: AArch64::LDUMINLH, .PatternStart: 610, .NumPatterns: 1 }, |
| 23382 | {.Opcode: AArch64::LDUMINLW, .PatternStart: 611, .NumPatterns: 1 }, |
| 23383 | {.Opcode: AArch64::LDUMINLX, .PatternStart: 612, .NumPatterns: 1 }, |
| 23384 | {.Opcode: AArch64::LDUMINW, .PatternStart: 613, .NumPatterns: 1 }, |
| 23385 | {.Opcode: AArch64::LDUMINX, .PatternStart: 614, .NumPatterns: 1 }, |
| 23386 | {.Opcode: AArch64::LDURBBi, .PatternStart: 615, .NumPatterns: 1 }, |
| 23387 | {.Opcode: AArch64::LDURBi, .PatternStart: 616, .NumPatterns: 1 }, |
| 23388 | {.Opcode: AArch64::LDURDi, .PatternStart: 617, .NumPatterns: 1 }, |
| 23389 | {.Opcode: AArch64::LDURHHi, .PatternStart: 618, .NumPatterns: 1 }, |
| 23390 | {.Opcode: AArch64::LDURHi, .PatternStart: 619, .NumPatterns: 1 }, |
| 23391 | {.Opcode: AArch64::LDURQi, .PatternStart: 620, .NumPatterns: 1 }, |
| 23392 | {.Opcode: AArch64::LDURSBWi, .PatternStart: 621, .NumPatterns: 1 }, |
| 23393 | {.Opcode: AArch64::LDURSBXi, .PatternStart: 622, .NumPatterns: 1 }, |
| 23394 | {.Opcode: AArch64::LDURSHWi, .PatternStart: 623, .NumPatterns: 1 }, |
| 23395 | {.Opcode: AArch64::LDURSHXi, .PatternStart: 624, .NumPatterns: 1 }, |
| 23396 | {.Opcode: AArch64::LDURSWi, .PatternStart: 625, .NumPatterns: 1 }, |
| 23397 | {.Opcode: AArch64::LDURSi, .PatternStart: 626, .NumPatterns: 1 }, |
| 23398 | {.Opcode: AArch64::LDURWi, .PatternStart: 627, .NumPatterns: 1 }, |
| 23399 | {.Opcode: AArch64::LDURXi, .PatternStart: 628, .NumPatterns: 1 }, |
| 23400 | {.Opcode: AArch64::MADDWrrr, .PatternStart: 629, .NumPatterns: 1 }, |
| 23401 | {.Opcode: AArch64::MADDXrrr, .PatternStart: 630, .NumPatterns: 1 }, |
| 23402 | {.Opcode: AArch64::MOVA_2ZMXI_H_B, .PatternStart: 631, .NumPatterns: 1 }, |
| 23403 | {.Opcode: AArch64::MOVA_2ZMXI_H_D, .PatternStart: 632, .NumPatterns: 1 }, |
| 23404 | {.Opcode: AArch64::MOVA_2ZMXI_H_H, .PatternStart: 633, .NumPatterns: 1 }, |
| 23405 | {.Opcode: AArch64::MOVA_2ZMXI_H_S, .PatternStart: 634, .NumPatterns: 1 }, |
| 23406 | {.Opcode: AArch64::MOVA_2ZMXI_V_B, .PatternStart: 635, .NumPatterns: 1 }, |
| 23407 | {.Opcode: AArch64::MOVA_2ZMXI_V_D, .PatternStart: 636, .NumPatterns: 1 }, |
| 23408 | {.Opcode: AArch64::MOVA_2ZMXI_V_H, .PatternStart: 637, .NumPatterns: 1 }, |
| 23409 | {.Opcode: AArch64::MOVA_2ZMXI_V_S, .PatternStart: 638, .NumPatterns: 1 }, |
| 23410 | {.Opcode: AArch64::MOVA_4ZMXI_H_B, .PatternStart: 639, .NumPatterns: 1 }, |
| 23411 | {.Opcode: AArch64::MOVA_4ZMXI_H_D, .PatternStart: 640, .NumPatterns: 1 }, |
| 23412 | {.Opcode: AArch64::MOVA_4ZMXI_H_H, .PatternStart: 641, .NumPatterns: 1 }, |
| 23413 | {.Opcode: AArch64::MOVA_4ZMXI_H_S, .PatternStart: 642, .NumPatterns: 1 }, |
| 23414 | {.Opcode: AArch64::MOVA_4ZMXI_V_B, .PatternStart: 643, .NumPatterns: 1 }, |
| 23415 | {.Opcode: AArch64::MOVA_4ZMXI_V_D, .PatternStart: 644, .NumPatterns: 1 }, |
| 23416 | {.Opcode: AArch64::MOVA_4ZMXI_V_H, .PatternStart: 645, .NumPatterns: 1 }, |
| 23417 | {.Opcode: AArch64::MOVA_4ZMXI_V_S, .PatternStart: 646, .NumPatterns: 1 }, |
| 23418 | {.Opcode: AArch64::MOVA_MXI2Z_H_B, .PatternStart: 647, .NumPatterns: 1 }, |
| 23419 | {.Opcode: AArch64::MOVA_MXI2Z_H_D, .PatternStart: 648, .NumPatterns: 1 }, |
| 23420 | {.Opcode: AArch64::MOVA_MXI2Z_H_H, .PatternStart: 649, .NumPatterns: 1 }, |
| 23421 | {.Opcode: AArch64::MOVA_MXI2Z_H_S, .PatternStart: 650, .NumPatterns: 1 }, |
| 23422 | {.Opcode: AArch64::MOVA_MXI2Z_V_B, .PatternStart: 651, .NumPatterns: 1 }, |
| 23423 | {.Opcode: AArch64::MOVA_MXI2Z_V_D, .PatternStart: 652, .NumPatterns: 1 }, |
| 23424 | {.Opcode: AArch64::MOVA_MXI2Z_V_H, .PatternStart: 653, .NumPatterns: 1 }, |
| 23425 | {.Opcode: AArch64::MOVA_MXI2Z_V_S, .PatternStart: 654, .NumPatterns: 1 }, |
| 23426 | {.Opcode: AArch64::MOVA_MXI4Z_H_B, .PatternStart: 655, .NumPatterns: 1 }, |
| 23427 | {.Opcode: AArch64::MOVA_MXI4Z_H_D, .PatternStart: 656, .NumPatterns: 1 }, |
| 23428 | {.Opcode: AArch64::MOVA_MXI4Z_H_H, .PatternStart: 657, .NumPatterns: 1 }, |
| 23429 | {.Opcode: AArch64::MOVA_MXI4Z_H_S, .PatternStart: 658, .NumPatterns: 1 }, |
| 23430 | {.Opcode: AArch64::MOVA_MXI4Z_V_B, .PatternStart: 659, .NumPatterns: 1 }, |
| 23431 | {.Opcode: AArch64::MOVA_MXI4Z_V_D, .PatternStart: 660, .NumPatterns: 1 }, |
| 23432 | {.Opcode: AArch64::MOVA_MXI4Z_V_H, .PatternStart: 661, .NumPatterns: 1 }, |
| 23433 | {.Opcode: AArch64::MOVA_MXI4Z_V_S, .PatternStart: 662, .NumPatterns: 1 }, |
| 23434 | {.Opcode: AArch64::MOVA_VG2_2ZMXI, .PatternStart: 663, .NumPatterns: 1 }, |
| 23435 | {.Opcode: AArch64::MOVA_VG2_MXI2Z, .PatternStart: 664, .NumPatterns: 1 }, |
| 23436 | {.Opcode: AArch64::MOVA_VG4_4ZMXI, .PatternStart: 665, .NumPatterns: 1 }, |
| 23437 | {.Opcode: AArch64::MOVA_VG4_MXI4Z, .PatternStart: 666, .NumPatterns: 1 }, |
| 23438 | {.Opcode: AArch64::MOVT, .PatternStart: 667, .NumPatterns: 1 }, |
| 23439 | {.Opcode: AArch64::MSRpstatesvcrImm1, .PatternStart: 668, .NumPatterns: 6 }, |
| 23440 | {.Opcode: AArch64::MSUBWrrr, .PatternStart: 674, .NumPatterns: 1 }, |
| 23441 | {.Opcode: AArch64::MSUBXrrr, .PatternStart: 675, .NumPatterns: 1 }, |
| 23442 | {.Opcode: AArch64::NOTv16i8, .PatternStart: 676, .NumPatterns: 1 }, |
| 23443 | {.Opcode: AArch64::NOTv8i8, .PatternStart: 677, .NumPatterns: 1 }, |
| 23444 | {.Opcode: AArch64::ORNWrs, .PatternStart: 678, .NumPatterns: 3 }, |
| 23445 | {.Opcode: AArch64::ORNXrs, .PatternStart: 681, .NumPatterns: 3 }, |
| 23446 | {.Opcode: AArch64::ORRS_PPzPP, .PatternStart: 684, .NumPatterns: 1 }, |
| 23447 | {.Opcode: AArch64::ORRWrs, .PatternStart: 685, .NumPatterns: 2 }, |
| 23448 | {.Opcode: AArch64::ORRXrs, .PatternStart: 687, .NumPatterns: 2 }, |
| 23449 | {.Opcode: AArch64::ORR_PPzPP, .PatternStart: 689, .NumPatterns: 1 }, |
| 23450 | {.Opcode: AArch64::ORR_ZI, .PatternStart: 690, .NumPatterns: 3 }, |
| 23451 | {.Opcode: AArch64::ORR_ZZZ, .PatternStart: 693, .NumPatterns: 1 }, |
| 23452 | {.Opcode: AArch64::ORRv16i8, .PatternStart: 694, .NumPatterns: 1 }, |
| 23453 | {.Opcode: AArch64::ORRv8i8, .PatternStart: 695, .NumPatterns: 1 }, |
| 23454 | {.Opcode: AArch64::PACIA1716, .PatternStart: 696, .NumPatterns: 1 }, |
| 23455 | {.Opcode: AArch64::PACIASP, .PatternStart: 697, .NumPatterns: 1 }, |
| 23456 | {.Opcode: AArch64::PACIAZ, .PatternStart: 698, .NumPatterns: 1 }, |
| 23457 | {.Opcode: AArch64::PACIB1716, .PatternStart: 699, .NumPatterns: 1 }, |
| 23458 | {.Opcode: AArch64::PACIBSP, .PatternStart: 700, .NumPatterns: 1 }, |
| 23459 | {.Opcode: AArch64::PACIBZ, .PatternStart: 701, .NumPatterns: 1 }, |
| 23460 | {.Opcode: AArch64::PACM, .PatternStart: 702, .NumPatterns: 1 }, |
| 23461 | {.Opcode: AArch64::PMOV_PZI_B, .PatternStart: 703, .NumPatterns: 1 }, |
| 23462 | {.Opcode: AArch64::PMOV_ZIP_B, .PatternStart: 704, .NumPatterns: 1 }, |
| 23463 | {.Opcode: AArch64::PRFB_D_PZI, .PatternStart: 705, .NumPatterns: 1 }, |
| 23464 | {.Opcode: AArch64::PRFB_PRI, .PatternStart: 706, .NumPatterns: 1 }, |
| 23465 | {.Opcode: AArch64::PRFB_S_PZI, .PatternStart: 707, .NumPatterns: 1 }, |
| 23466 | {.Opcode: AArch64::PRFD_D_PZI, .PatternStart: 708, .NumPatterns: 1 }, |
| 23467 | {.Opcode: AArch64::PRFD_PRI, .PatternStart: 709, .NumPatterns: 1 }, |
| 23468 | {.Opcode: AArch64::PRFD_S_PZI, .PatternStart: 710, .NumPatterns: 1 }, |
| 23469 | {.Opcode: AArch64::PRFH_D_PZI, .PatternStart: 711, .NumPatterns: 1 }, |
| 23470 | {.Opcode: AArch64::PRFH_PRI, .PatternStart: 712, .NumPatterns: 1 }, |
| 23471 | {.Opcode: AArch64::PRFH_S_PZI, .PatternStart: 713, .NumPatterns: 1 }, |
| 23472 | {.Opcode: AArch64::PRFMroX, .PatternStart: 714, .NumPatterns: 1 }, |
| 23473 | {.Opcode: AArch64::PRFMui, .PatternStart: 715, .NumPatterns: 1 }, |
| 23474 | {.Opcode: AArch64::PRFUMi, .PatternStart: 716, .NumPatterns: 1 }, |
| 23475 | {.Opcode: AArch64::PRFW_D_PZI, .PatternStart: 717, .NumPatterns: 1 }, |
| 23476 | {.Opcode: AArch64::PRFW_PRI, .PatternStart: 718, .NumPatterns: 1 }, |
| 23477 | {.Opcode: AArch64::PRFW_S_PZI, .PatternStart: 719, .NumPatterns: 1 }, |
| 23478 | {.Opcode: AArch64::PTRUES_B, .PatternStart: 720, .NumPatterns: 1 }, |
| 23479 | {.Opcode: AArch64::PTRUES_D, .PatternStart: 721, .NumPatterns: 1 }, |
| 23480 | {.Opcode: AArch64::PTRUES_H, .PatternStart: 722, .NumPatterns: 1 }, |
| 23481 | {.Opcode: AArch64::PTRUES_S, .PatternStart: 723, .NumPatterns: 1 }, |
| 23482 | {.Opcode: AArch64::PTRUE_B, .PatternStart: 724, .NumPatterns: 1 }, |
| 23483 | {.Opcode: AArch64::PTRUE_D, .PatternStart: 725, .NumPatterns: 1 }, |
| 23484 | {.Opcode: AArch64::PTRUE_H, .PatternStart: 726, .NumPatterns: 1 }, |
| 23485 | {.Opcode: AArch64::PTRUE_S, .PatternStart: 727, .NumPatterns: 1 }, |
| 23486 | {.Opcode: AArch64::RET, .PatternStart: 728, .NumPatterns: 1 }, |
| 23487 | {.Opcode: AArch64::SBCSWr, .PatternStart: 729, .NumPatterns: 1 }, |
| 23488 | {.Opcode: AArch64::SBCSXr, .PatternStart: 730, .NumPatterns: 1 }, |
| 23489 | {.Opcode: AArch64::SBCWr, .PatternStart: 731, .NumPatterns: 1 }, |
| 23490 | {.Opcode: AArch64::SBCXr, .PatternStart: 732, .NumPatterns: 1 }, |
| 23491 | {.Opcode: AArch64::SBFMWri, .PatternStart: 733, .NumPatterns: 3 }, |
| 23492 | {.Opcode: AArch64::SBFMXri, .PatternStart: 736, .NumPatterns: 4 }, |
| 23493 | {.Opcode: AArch64::SEL_PPPP, .PatternStart: 740, .NumPatterns: 1 }, |
| 23494 | {.Opcode: AArch64::SEL_ZPZZ_B, .PatternStart: 741, .NumPatterns: 1 }, |
| 23495 | {.Opcode: AArch64::SEL_ZPZZ_D, .PatternStart: 742, .NumPatterns: 1 }, |
| 23496 | {.Opcode: AArch64::SEL_ZPZZ_H, .PatternStart: 743, .NumPatterns: 1 }, |
| 23497 | {.Opcode: AArch64::SEL_ZPZZ_S, .PatternStart: 744, .NumPatterns: 1 }, |
| 23498 | {.Opcode: AArch64::SMADDLrrr, .PatternStart: 745, .NumPatterns: 1 }, |
| 23499 | {.Opcode: AArch64::SMSUBLrrr, .PatternStart: 746, .NumPatterns: 1 }, |
| 23500 | {.Opcode: AArch64::SQDECB_XPiI, .PatternStart: 747, .NumPatterns: 2 }, |
| 23501 | {.Opcode: AArch64::SQDECB_XPiWdI, .PatternStart: 749, .NumPatterns: 2 }, |
| 23502 | {.Opcode: AArch64::SQDECD_XPiI, .PatternStart: 751, .NumPatterns: 2 }, |
| 23503 | {.Opcode: AArch64::SQDECD_XPiWdI, .PatternStart: 753, .NumPatterns: 2 }, |
| 23504 | {.Opcode: AArch64::SQDECD_ZPiI, .PatternStart: 755, .NumPatterns: 2 }, |
| 23505 | {.Opcode: AArch64::SQDECH_XPiI, .PatternStart: 757, .NumPatterns: 2 }, |
| 23506 | {.Opcode: AArch64::SQDECH_XPiWdI, .PatternStart: 759, .NumPatterns: 2 }, |
| 23507 | {.Opcode: AArch64::SQDECH_ZPiI, .PatternStart: 761, .NumPatterns: 2 }, |
| 23508 | {.Opcode: AArch64::SQDECW_XPiI, .PatternStart: 763, .NumPatterns: 2 }, |
| 23509 | {.Opcode: AArch64::SQDECW_XPiWdI, .PatternStart: 765, .NumPatterns: 2 }, |
| 23510 | {.Opcode: AArch64::SQDECW_ZPiI, .PatternStart: 767, .NumPatterns: 2 }, |
| 23511 | {.Opcode: AArch64::SQINCB_XPiI, .PatternStart: 769, .NumPatterns: 2 }, |
| 23512 | {.Opcode: AArch64::SQINCB_XPiWdI, .PatternStart: 771, .NumPatterns: 2 }, |
| 23513 | {.Opcode: AArch64::SQINCD_XPiI, .PatternStart: 773, .NumPatterns: 2 }, |
| 23514 | {.Opcode: AArch64::SQINCD_XPiWdI, .PatternStart: 775, .NumPatterns: 2 }, |
| 23515 | {.Opcode: AArch64::SQINCD_ZPiI, .PatternStart: 777, .NumPatterns: 2 }, |
| 23516 | {.Opcode: AArch64::SQINCH_XPiI, .PatternStart: 779, .NumPatterns: 2 }, |
| 23517 | {.Opcode: AArch64::SQINCH_XPiWdI, .PatternStart: 781, .NumPatterns: 2 }, |
| 23518 | {.Opcode: AArch64::SQINCH_ZPiI, .PatternStart: 783, .NumPatterns: 2 }, |
| 23519 | {.Opcode: AArch64::SQINCW_XPiI, .PatternStart: 785, .NumPatterns: 2 }, |
| 23520 | {.Opcode: AArch64::SQINCW_XPiWdI, .PatternStart: 787, .NumPatterns: 2 }, |
| 23521 | {.Opcode: AArch64::SQINCW_ZPiI, .PatternStart: 789, .NumPatterns: 2 }, |
| 23522 | {.Opcode: AArch64::SST1B_D_IMM, .PatternStart: 791, .NumPatterns: 1 }, |
| 23523 | {.Opcode: AArch64::SST1B_S_IMM, .PatternStart: 792, .NumPatterns: 1 }, |
| 23524 | {.Opcode: AArch64::SST1D_IMM, .PatternStart: 793, .NumPatterns: 1 }, |
| 23525 | {.Opcode: AArch64::SST1H_D_IMM, .PatternStart: 794, .NumPatterns: 1 }, |
| 23526 | {.Opcode: AArch64::SST1H_S_IMM, .PatternStart: 795, .NumPatterns: 1 }, |
| 23527 | {.Opcode: AArch64::SST1Q, .PatternStart: 796, .NumPatterns: 1 }, |
| 23528 | {.Opcode: AArch64::SST1W_D_IMM, .PatternStart: 797, .NumPatterns: 1 }, |
| 23529 | {.Opcode: AArch64::SST1W_IMM, .PatternStart: 798, .NumPatterns: 1 }, |
| 23530 | {.Opcode: AArch64::ST1B_2Z_IMM, .PatternStart: 799, .NumPatterns: 1 }, |
| 23531 | {.Opcode: AArch64::ST1B_2Z_STRIDED_IMM, .PatternStart: 800, .NumPatterns: 1 }, |
| 23532 | {.Opcode: AArch64::ST1B_4Z_IMM, .PatternStart: 801, .NumPatterns: 1 }, |
| 23533 | {.Opcode: AArch64::ST1B_4Z_STRIDED_IMM, .PatternStart: 802, .NumPatterns: 1 }, |
| 23534 | {.Opcode: AArch64::ST1B_D_IMM, .PatternStart: 803, .NumPatterns: 1 }, |
| 23535 | {.Opcode: AArch64::ST1B_H_IMM, .PatternStart: 804, .NumPatterns: 1 }, |
| 23536 | {.Opcode: AArch64::ST1B_IMM, .PatternStart: 805, .NumPatterns: 1 }, |
| 23537 | {.Opcode: AArch64::ST1B_S_IMM, .PatternStart: 806, .NumPatterns: 1 }, |
| 23538 | {.Opcode: AArch64::ST1D_2Z_IMM, .PatternStart: 807, .NumPatterns: 1 }, |
| 23539 | {.Opcode: AArch64::ST1D_2Z_STRIDED_IMM, .PatternStart: 808, .NumPatterns: 1 }, |
| 23540 | {.Opcode: AArch64::ST1D_4Z_IMM, .PatternStart: 809, .NumPatterns: 1 }, |
| 23541 | {.Opcode: AArch64::ST1D_4Z_STRIDED_IMM, .PatternStart: 810, .NumPatterns: 1 }, |
| 23542 | {.Opcode: AArch64::ST1D_IMM, .PatternStart: 811, .NumPatterns: 1 }, |
| 23543 | {.Opcode: AArch64::ST1D_Q_IMM, .PatternStart: 812, .NumPatterns: 1 }, |
| 23544 | {.Opcode: AArch64::ST1Fourv16b_POST, .PatternStart: 813, .NumPatterns: 1 }, |
| 23545 | {.Opcode: AArch64::ST1Fourv1d_POST, .PatternStart: 814, .NumPatterns: 1 }, |
| 23546 | {.Opcode: AArch64::ST1Fourv2d_POST, .PatternStart: 815, .NumPatterns: 1 }, |
| 23547 | {.Opcode: AArch64::ST1Fourv2s_POST, .PatternStart: 816, .NumPatterns: 1 }, |
| 23548 | {.Opcode: AArch64::ST1Fourv4h_POST, .PatternStart: 817, .NumPatterns: 1 }, |
| 23549 | {.Opcode: AArch64::ST1Fourv4s_POST, .PatternStart: 818, .NumPatterns: 1 }, |
| 23550 | {.Opcode: AArch64::ST1Fourv8b_POST, .PatternStart: 819, .NumPatterns: 1 }, |
| 23551 | {.Opcode: AArch64::ST1Fourv8h_POST, .PatternStart: 820, .NumPatterns: 1 }, |
| 23552 | {.Opcode: AArch64::ST1H_2Z_IMM, .PatternStart: 821, .NumPatterns: 1 }, |
| 23553 | {.Opcode: AArch64::ST1H_2Z_STRIDED_IMM, .PatternStart: 822, .NumPatterns: 1 }, |
| 23554 | {.Opcode: AArch64::ST1H_4Z_IMM, .PatternStart: 823, .NumPatterns: 1 }, |
| 23555 | {.Opcode: AArch64::ST1H_4Z_STRIDED_IMM, .PatternStart: 824, .NumPatterns: 1 }, |
| 23556 | {.Opcode: AArch64::ST1H_D_IMM, .PatternStart: 825, .NumPatterns: 1 }, |
| 23557 | {.Opcode: AArch64::ST1H_IMM, .PatternStart: 826, .NumPatterns: 1 }, |
| 23558 | {.Opcode: AArch64::ST1H_S_IMM, .PatternStart: 827, .NumPatterns: 1 }, |
| 23559 | {.Opcode: AArch64::ST1Onev16b_POST, .PatternStart: 828, .NumPatterns: 1 }, |
| 23560 | {.Opcode: AArch64::ST1Onev1d_POST, .PatternStart: 829, .NumPatterns: 1 }, |
| 23561 | {.Opcode: AArch64::ST1Onev2d_POST, .PatternStart: 830, .NumPatterns: 1 }, |
| 23562 | {.Opcode: AArch64::ST1Onev2s_POST, .PatternStart: 831, .NumPatterns: 1 }, |
| 23563 | {.Opcode: AArch64::ST1Onev4h_POST, .PatternStart: 832, .NumPatterns: 1 }, |
| 23564 | {.Opcode: AArch64::ST1Onev4s_POST, .PatternStart: 833, .NumPatterns: 1 }, |
| 23565 | {.Opcode: AArch64::ST1Onev8b_POST, .PatternStart: 834, .NumPatterns: 1 }, |
| 23566 | {.Opcode: AArch64::ST1Onev8h_POST, .PatternStart: 835, .NumPatterns: 1 }, |
| 23567 | {.Opcode: AArch64::ST1Threev16b_POST, .PatternStart: 836, .NumPatterns: 1 }, |
| 23568 | {.Opcode: AArch64::ST1Threev1d_POST, .PatternStart: 837, .NumPatterns: 1 }, |
| 23569 | {.Opcode: AArch64::ST1Threev2d_POST, .PatternStart: 838, .NumPatterns: 1 }, |
| 23570 | {.Opcode: AArch64::ST1Threev2s_POST, .PatternStart: 839, .NumPatterns: 1 }, |
| 23571 | {.Opcode: AArch64::ST1Threev4h_POST, .PatternStart: 840, .NumPatterns: 1 }, |
| 23572 | {.Opcode: AArch64::ST1Threev4s_POST, .PatternStart: 841, .NumPatterns: 1 }, |
| 23573 | {.Opcode: AArch64::ST1Threev8b_POST, .PatternStart: 842, .NumPatterns: 1 }, |
| 23574 | {.Opcode: AArch64::ST1Threev8h_POST, .PatternStart: 843, .NumPatterns: 1 }, |
| 23575 | {.Opcode: AArch64::ST1Twov16b_POST, .PatternStart: 844, .NumPatterns: 1 }, |
| 23576 | {.Opcode: AArch64::ST1Twov1d_POST, .PatternStart: 845, .NumPatterns: 1 }, |
| 23577 | {.Opcode: AArch64::ST1Twov2d_POST, .PatternStart: 846, .NumPatterns: 1 }, |
| 23578 | {.Opcode: AArch64::ST1Twov2s_POST, .PatternStart: 847, .NumPatterns: 1 }, |
| 23579 | {.Opcode: AArch64::ST1Twov4h_POST, .PatternStart: 848, .NumPatterns: 1 }, |
| 23580 | {.Opcode: AArch64::ST1Twov4s_POST, .PatternStart: 849, .NumPatterns: 1 }, |
| 23581 | {.Opcode: AArch64::ST1Twov8b_POST, .PatternStart: 850, .NumPatterns: 1 }, |
| 23582 | {.Opcode: AArch64::ST1Twov8h_POST, .PatternStart: 851, .NumPatterns: 1 }, |
| 23583 | {.Opcode: AArch64::ST1W_2Z_IMM, .PatternStart: 852, .NumPatterns: 1 }, |
| 23584 | {.Opcode: AArch64::ST1W_2Z_STRIDED_IMM, .PatternStart: 853, .NumPatterns: 1 }, |
| 23585 | {.Opcode: AArch64::ST1W_4Z_IMM, .PatternStart: 854, .NumPatterns: 1 }, |
| 23586 | {.Opcode: AArch64::ST1W_4Z_STRIDED_IMM, .PatternStart: 855, .NumPatterns: 1 }, |
| 23587 | {.Opcode: AArch64::ST1W_D_IMM, .PatternStart: 856, .NumPatterns: 1 }, |
| 23588 | {.Opcode: AArch64::ST1W_IMM, .PatternStart: 857, .NumPatterns: 1 }, |
| 23589 | {.Opcode: AArch64::ST1W_Q_IMM, .PatternStart: 858, .NumPatterns: 1 }, |
| 23590 | {.Opcode: AArch64::ST1_MXIPXX_H_B, .PatternStart: 859, .NumPatterns: 1 }, |
| 23591 | {.Opcode: AArch64::ST1_MXIPXX_H_D, .PatternStart: 860, .NumPatterns: 1 }, |
| 23592 | {.Opcode: AArch64::ST1_MXIPXX_H_H, .PatternStart: 861, .NumPatterns: 1 }, |
| 23593 | {.Opcode: AArch64::ST1_MXIPXX_H_Q, .PatternStart: 862, .NumPatterns: 1 }, |
| 23594 | {.Opcode: AArch64::ST1_MXIPXX_H_S, .PatternStart: 863, .NumPatterns: 1 }, |
| 23595 | {.Opcode: AArch64::ST1_MXIPXX_V_B, .PatternStart: 864, .NumPatterns: 1 }, |
| 23596 | {.Opcode: AArch64::ST1_MXIPXX_V_D, .PatternStart: 865, .NumPatterns: 1 }, |
| 23597 | {.Opcode: AArch64::ST1_MXIPXX_V_H, .PatternStart: 866, .NumPatterns: 1 }, |
| 23598 | {.Opcode: AArch64::ST1_MXIPXX_V_Q, .PatternStart: 867, .NumPatterns: 1 }, |
| 23599 | {.Opcode: AArch64::ST1_MXIPXX_V_S, .PatternStart: 868, .NumPatterns: 1 }, |
| 23600 | {.Opcode: AArch64::ST1i16_POST, .PatternStart: 869, .NumPatterns: 1 }, |
| 23601 | {.Opcode: AArch64::ST1i32_POST, .PatternStart: 870, .NumPatterns: 1 }, |
| 23602 | {.Opcode: AArch64::ST1i64_POST, .PatternStart: 871, .NumPatterns: 1 }, |
| 23603 | {.Opcode: AArch64::ST1i8_POST, .PatternStart: 872, .NumPatterns: 1 }, |
| 23604 | {.Opcode: AArch64::ST2B_IMM, .PatternStart: 873, .NumPatterns: 1 }, |
| 23605 | {.Opcode: AArch64::ST2D_IMM, .PatternStart: 874, .NumPatterns: 1 }, |
| 23606 | {.Opcode: AArch64::ST2Gi, .PatternStart: 875, .NumPatterns: 1 }, |
| 23607 | {.Opcode: AArch64::ST2H_IMM, .PatternStart: 876, .NumPatterns: 1 }, |
| 23608 | {.Opcode: AArch64::ST2Q_IMM, .PatternStart: 877, .NumPatterns: 1 }, |
| 23609 | {.Opcode: AArch64::ST2Twov16b_POST, .PatternStart: 878, .NumPatterns: 1 }, |
| 23610 | {.Opcode: AArch64::ST2Twov2d_POST, .PatternStart: 879, .NumPatterns: 1 }, |
| 23611 | {.Opcode: AArch64::ST2Twov2s_POST, .PatternStart: 880, .NumPatterns: 1 }, |
| 23612 | {.Opcode: AArch64::ST2Twov4h_POST, .PatternStart: 881, .NumPatterns: 1 }, |
| 23613 | {.Opcode: AArch64::ST2Twov4s_POST, .PatternStart: 882, .NumPatterns: 1 }, |
| 23614 | {.Opcode: AArch64::ST2Twov8b_POST, .PatternStart: 883, .NumPatterns: 1 }, |
| 23615 | {.Opcode: AArch64::ST2Twov8h_POST, .PatternStart: 884, .NumPatterns: 1 }, |
| 23616 | {.Opcode: AArch64::ST2W_IMM, .PatternStart: 885, .NumPatterns: 1 }, |
| 23617 | {.Opcode: AArch64::ST2i16_POST, .PatternStart: 886, .NumPatterns: 1 }, |
| 23618 | {.Opcode: AArch64::ST2i32_POST, .PatternStart: 887, .NumPatterns: 1 }, |
| 23619 | {.Opcode: AArch64::ST2i64_POST, .PatternStart: 888, .NumPatterns: 1 }, |
| 23620 | {.Opcode: AArch64::ST2i8_POST, .PatternStart: 889, .NumPatterns: 1 }, |
| 23621 | {.Opcode: AArch64::ST3B_IMM, .PatternStart: 890, .NumPatterns: 1 }, |
| 23622 | {.Opcode: AArch64::ST3D_IMM, .PatternStart: 891, .NumPatterns: 1 }, |
| 23623 | {.Opcode: AArch64::ST3H_IMM, .PatternStart: 892, .NumPatterns: 1 }, |
| 23624 | {.Opcode: AArch64::ST3Q_IMM, .PatternStart: 893, .NumPatterns: 1 }, |
| 23625 | {.Opcode: AArch64::ST3Threev16b_POST, .PatternStart: 894, .NumPatterns: 1 }, |
| 23626 | {.Opcode: AArch64::ST3Threev2d_POST, .PatternStart: 895, .NumPatterns: 1 }, |
| 23627 | {.Opcode: AArch64::ST3Threev2s_POST, .PatternStart: 896, .NumPatterns: 1 }, |
| 23628 | {.Opcode: AArch64::ST3Threev4h_POST, .PatternStart: 897, .NumPatterns: 1 }, |
| 23629 | {.Opcode: AArch64::ST3Threev4s_POST, .PatternStart: 898, .NumPatterns: 1 }, |
| 23630 | {.Opcode: AArch64::ST3Threev8b_POST, .PatternStart: 899, .NumPatterns: 1 }, |
| 23631 | {.Opcode: AArch64::ST3Threev8h_POST, .PatternStart: 900, .NumPatterns: 1 }, |
| 23632 | {.Opcode: AArch64::ST3W_IMM, .PatternStart: 901, .NumPatterns: 1 }, |
| 23633 | {.Opcode: AArch64::ST3i16_POST, .PatternStart: 902, .NumPatterns: 1 }, |
| 23634 | {.Opcode: AArch64::ST3i32_POST, .PatternStart: 903, .NumPatterns: 1 }, |
| 23635 | {.Opcode: AArch64::ST3i64_POST, .PatternStart: 904, .NumPatterns: 1 }, |
| 23636 | {.Opcode: AArch64::ST3i8_POST, .PatternStart: 905, .NumPatterns: 1 }, |
| 23637 | {.Opcode: AArch64::ST4B_IMM, .PatternStart: 906, .NumPatterns: 1 }, |
| 23638 | {.Opcode: AArch64::ST4D_IMM, .PatternStart: 907, .NumPatterns: 1 }, |
| 23639 | {.Opcode: AArch64::ST4Fourv16b_POST, .PatternStart: 908, .NumPatterns: 1 }, |
| 23640 | {.Opcode: AArch64::ST4Fourv2d_POST, .PatternStart: 909, .NumPatterns: 1 }, |
| 23641 | {.Opcode: AArch64::ST4Fourv2s_POST, .PatternStart: 910, .NumPatterns: 1 }, |
| 23642 | {.Opcode: AArch64::ST4Fourv4h_POST, .PatternStart: 911, .NumPatterns: 1 }, |
| 23643 | {.Opcode: AArch64::ST4Fourv4s_POST, .PatternStart: 912, .NumPatterns: 1 }, |
| 23644 | {.Opcode: AArch64::ST4Fourv8b_POST, .PatternStart: 913, .NumPatterns: 1 }, |
| 23645 | {.Opcode: AArch64::ST4Fourv8h_POST, .PatternStart: 914, .NumPatterns: 1 }, |
| 23646 | {.Opcode: AArch64::ST4H_IMM, .PatternStart: 915, .NumPatterns: 1 }, |
| 23647 | {.Opcode: AArch64::ST4Q_IMM, .PatternStart: 916, .NumPatterns: 1 }, |
| 23648 | {.Opcode: AArch64::ST4W_IMM, .PatternStart: 917, .NumPatterns: 1 }, |
| 23649 | {.Opcode: AArch64::ST4i16_POST, .PatternStart: 918, .NumPatterns: 1 }, |
| 23650 | {.Opcode: AArch64::ST4i32_POST, .PatternStart: 919, .NumPatterns: 1 }, |
| 23651 | {.Opcode: AArch64::ST4i64_POST, .PatternStart: 920, .NumPatterns: 1 }, |
| 23652 | {.Opcode: AArch64::ST4i8_POST, .PatternStart: 921, .NumPatterns: 1 }, |
| 23653 | {.Opcode: AArch64::STGPi, .PatternStart: 922, .NumPatterns: 1 }, |
| 23654 | {.Opcode: AArch64::STGi, .PatternStart: 923, .NumPatterns: 1 }, |
| 23655 | {.Opcode: AArch64::STLURBi, .PatternStart: 924, .NumPatterns: 1 }, |
| 23656 | {.Opcode: AArch64::STLURHi, .PatternStart: 925, .NumPatterns: 1 }, |
| 23657 | {.Opcode: AArch64::STLURWi, .PatternStart: 926, .NumPatterns: 1 }, |
| 23658 | {.Opcode: AArch64::STLURXi, .PatternStart: 927, .NumPatterns: 1 }, |
| 23659 | {.Opcode: AArch64::STLURbi, .PatternStart: 928, .NumPatterns: 1 }, |
| 23660 | {.Opcode: AArch64::STLURdi, .PatternStart: 929, .NumPatterns: 1 }, |
| 23661 | {.Opcode: AArch64::STLURhi, .PatternStart: 930, .NumPatterns: 1 }, |
| 23662 | {.Opcode: AArch64::STLURqi, .PatternStart: 931, .NumPatterns: 1 }, |
| 23663 | {.Opcode: AArch64::STLURsi, .PatternStart: 932, .NumPatterns: 1 }, |
| 23664 | {.Opcode: AArch64::STNPDi, .PatternStart: 933, .NumPatterns: 1 }, |
| 23665 | {.Opcode: AArch64::STNPQi, .PatternStart: 934, .NumPatterns: 1 }, |
| 23666 | {.Opcode: AArch64::STNPSi, .PatternStart: 935, .NumPatterns: 1 }, |
| 23667 | {.Opcode: AArch64::STNPWi, .PatternStart: 936, .NumPatterns: 1 }, |
| 23668 | {.Opcode: AArch64::STNPXi, .PatternStart: 937, .NumPatterns: 1 }, |
| 23669 | {.Opcode: AArch64::STNT1B_2Z_IMM, .PatternStart: 938, .NumPatterns: 1 }, |
| 23670 | {.Opcode: AArch64::STNT1B_2Z_STRIDED_IMM, .PatternStart: 939, .NumPatterns: 1 }, |
| 23671 | {.Opcode: AArch64::STNT1B_4Z_IMM, .PatternStart: 940, .NumPatterns: 1 }, |
| 23672 | {.Opcode: AArch64::STNT1B_4Z_STRIDED_IMM, .PatternStart: 941, .NumPatterns: 1 }, |
| 23673 | {.Opcode: AArch64::STNT1B_ZRI, .PatternStart: 942, .NumPatterns: 1 }, |
| 23674 | {.Opcode: AArch64::STNT1B_ZZR_D, .PatternStart: 943, .NumPatterns: 1 }, |
| 23675 | {.Opcode: AArch64::STNT1B_ZZR_S, .PatternStart: 944, .NumPatterns: 1 }, |
| 23676 | {.Opcode: AArch64::STNT1D_2Z_IMM, .PatternStart: 945, .NumPatterns: 1 }, |
| 23677 | {.Opcode: AArch64::STNT1D_2Z_STRIDED_IMM, .PatternStart: 946, .NumPatterns: 1 }, |
| 23678 | {.Opcode: AArch64::STNT1D_4Z_IMM, .PatternStart: 947, .NumPatterns: 1 }, |
| 23679 | {.Opcode: AArch64::STNT1D_4Z_STRIDED_IMM, .PatternStart: 948, .NumPatterns: 1 }, |
| 23680 | {.Opcode: AArch64::STNT1D_ZRI, .PatternStart: 949, .NumPatterns: 1 }, |
| 23681 | {.Opcode: AArch64::STNT1D_ZZR_D, .PatternStart: 950, .NumPatterns: 1 }, |
| 23682 | {.Opcode: AArch64::STNT1H_2Z_IMM, .PatternStart: 951, .NumPatterns: 1 }, |
| 23683 | {.Opcode: AArch64::STNT1H_2Z_STRIDED_IMM, .PatternStart: 952, .NumPatterns: 1 }, |
| 23684 | {.Opcode: AArch64::STNT1H_4Z_IMM, .PatternStart: 953, .NumPatterns: 1 }, |
| 23685 | {.Opcode: AArch64::STNT1H_4Z_STRIDED_IMM, .PatternStart: 954, .NumPatterns: 1 }, |
| 23686 | {.Opcode: AArch64::STNT1H_ZRI, .PatternStart: 955, .NumPatterns: 1 }, |
| 23687 | {.Opcode: AArch64::STNT1H_ZZR_D, .PatternStart: 956, .NumPatterns: 1 }, |
| 23688 | {.Opcode: AArch64::STNT1H_ZZR_S, .PatternStart: 957, .NumPatterns: 1 }, |
| 23689 | {.Opcode: AArch64::STNT1W_2Z_IMM, .PatternStart: 958, .NumPatterns: 1 }, |
| 23690 | {.Opcode: AArch64::STNT1W_2Z_STRIDED_IMM, .PatternStart: 959, .NumPatterns: 1 }, |
| 23691 | {.Opcode: AArch64::STNT1W_4Z_IMM, .PatternStart: 960, .NumPatterns: 1 }, |
| 23692 | {.Opcode: AArch64::STNT1W_4Z_STRIDED_IMM, .PatternStart: 961, .NumPatterns: 1 }, |
| 23693 | {.Opcode: AArch64::STNT1W_ZRI, .PatternStart: 962, .NumPatterns: 1 }, |
| 23694 | {.Opcode: AArch64::STNT1W_ZZR_D, .PatternStart: 963, .NumPatterns: 1 }, |
| 23695 | {.Opcode: AArch64::STNT1W_ZZR_S, .PatternStart: 964, .NumPatterns: 1 }, |
| 23696 | {.Opcode: AArch64::STPDi, .PatternStart: 965, .NumPatterns: 1 }, |
| 23697 | {.Opcode: AArch64::STPQi, .PatternStart: 966, .NumPatterns: 1 }, |
| 23698 | {.Opcode: AArch64::STPSi, .PatternStart: 967, .NumPatterns: 1 }, |
| 23699 | {.Opcode: AArch64::STPWi, .PatternStart: 968, .NumPatterns: 1 }, |
| 23700 | {.Opcode: AArch64::STPXi, .PatternStart: 969, .NumPatterns: 1 }, |
| 23701 | {.Opcode: AArch64::STRBBroX, .PatternStart: 970, .NumPatterns: 1 }, |
| 23702 | {.Opcode: AArch64::STRBBui, .PatternStart: 971, .NumPatterns: 1 }, |
| 23703 | {.Opcode: AArch64::STRBroX, .PatternStart: 972, .NumPatterns: 1 }, |
| 23704 | {.Opcode: AArch64::STRBui, .PatternStart: 973, .NumPatterns: 1 }, |
| 23705 | {.Opcode: AArch64::STRDroX, .PatternStart: 974, .NumPatterns: 1 }, |
| 23706 | {.Opcode: AArch64::STRDui, .PatternStart: 975, .NumPatterns: 1 }, |
| 23707 | {.Opcode: AArch64::STRHHroX, .PatternStart: 976, .NumPatterns: 1 }, |
| 23708 | {.Opcode: AArch64::STRHHui, .PatternStart: 977, .NumPatterns: 1 }, |
| 23709 | {.Opcode: AArch64::STRHroX, .PatternStart: 978, .NumPatterns: 1 }, |
| 23710 | {.Opcode: AArch64::STRHui, .PatternStart: 979, .NumPatterns: 1 }, |
| 23711 | {.Opcode: AArch64::STRQroX, .PatternStart: 980, .NumPatterns: 1 }, |
| 23712 | {.Opcode: AArch64::STRQui, .PatternStart: 981, .NumPatterns: 1 }, |
| 23713 | {.Opcode: AArch64::STRSroX, .PatternStart: 982, .NumPatterns: 1 }, |
| 23714 | {.Opcode: AArch64::STRSui, .PatternStart: 983, .NumPatterns: 1 }, |
| 23715 | {.Opcode: AArch64::STRWroX, .PatternStart: 984, .NumPatterns: 1 }, |
| 23716 | {.Opcode: AArch64::STRWui, .PatternStart: 985, .NumPatterns: 1 }, |
| 23717 | {.Opcode: AArch64::STRXroX, .PatternStart: 986, .NumPatterns: 1 }, |
| 23718 | {.Opcode: AArch64::STRXui, .PatternStart: 987, .NumPatterns: 1 }, |
| 23719 | {.Opcode: AArch64::STR_PXI, .PatternStart: 988, .NumPatterns: 1 }, |
| 23720 | {.Opcode: AArch64::STR_ZA, .PatternStart: 989, .NumPatterns: 1 }, |
| 23721 | {.Opcode: AArch64::STR_ZXI, .PatternStart: 990, .NumPatterns: 1 }, |
| 23722 | {.Opcode: AArch64::STTRBi, .PatternStart: 991, .NumPatterns: 1 }, |
| 23723 | {.Opcode: AArch64::STTRHi, .PatternStart: 992, .NumPatterns: 1 }, |
| 23724 | {.Opcode: AArch64::STTRWi, .PatternStart: 993, .NumPatterns: 1 }, |
| 23725 | {.Opcode: AArch64::STTRXi, .PatternStart: 994, .NumPatterns: 1 }, |
| 23726 | {.Opcode: AArch64::STURBBi, .PatternStart: 995, .NumPatterns: 1 }, |
| 23727 | {.Opcode: AArch64::STURBi, .PatternStart: 996, .NumPatterns: 1 }, |
| 23728 | {.Opcode: AArch64::STURDi, .PatternStart: 997, .NumPatterns: 1 }, |
| 23729 | {.Opcode: AArch64::STURHHi, .PatternStart: 998, .NumPatterns: 1 }, |
| 23730 | {.Opcode: AArch64::STURHi, .PatternStart: 999, .NumPatterns: 1 }, |
| 23731 | {.Opcode: AArch64::STURQi, .PatternStart: 1000, .NumPatterns: 1 }, |
| 23732 | {.Opcode: AArch64::STURSi, .PatternStart: 1001, .NumPatterns: 1 }, |
| 23733 | {.Opcode: AArch64::STURWi, .PatternStart: 1002, .NumPatterns: 1 }, |
| 23734 | {.Opcode: AArch64::STURXi, .PatternStart: 1003, .NumPatterns: 1 }, |
| 23735 | {.Opcode: AArch64::STZ2Gi, .PatternStart: 1004, .NumPatterns: 1 }, |
| 23736 | {.Opcode: AArch64::STZGi, .PatternStart: 1005, .NumPatterns: 1 }, |
| 23737 | {.Opcode: AArch64::SUBPT_shift, .PatternStart: 1006, .NumPatterns: 1 }, |
| 23738 | {.Opcode: AArch64::SUBSWri, .PatternStart: 1007, .NumPatterns: 1 }, |
| 23739 | {.Opcode: AArch64::SUBSWrs, .PatternStart: 1008, .NumPatterns: 5 }, |
| 23740 | {.Opcode: AArch64::SUBSWrx, .PatternStart: 1013, .NumPatterns: 3 }, |
| 23741 | {.Opcode: AArch64::SUBSXri, .PatternStart: 1016, .NumPatterns: 1 }, |
| 23742 | {.Opcode: AArch64::SUBSXrs, .PatternStart: 1017, .NumPatterns: 5 }, |
| 23743 | {.Opcode: AArch64::SUBSXrx, .PatternStart: 1022, .NumPatterns: 1 }, |
| 23744 | {.Opcode: AArch64::SUBSXrx64, .PatternStart: 1023, .NumPatterns: 3 }, |
| 23745 | {.Opcode: AArch64::SUBWrs, .PatternStart: 1026, .NumPatterns: 3 }, |
| 23746 | {.Opcode: AArch64::SUBWrx, .PatternStart: 1029, .NumPatterns: 2 }, |
| 23747 | {.Opcode: AArch64::SUBXrs, .PatternStart: 1031, .NumPatterns: 3 }, |
| 23748 | {.Opcode: AArch64::SUBXrx64, .PatternStart: 1034, .NumPatterns: 2 }, |
| 23749 | {.Opcode: AArch64::SYSPxt_XZR, .PatternStart: 1036, .NumPatterns: 1 }, |
| 23750 | {.Opcode: AArch64::SYSxt, .PatternStart: 1037, .NumPatterns: 1 }, |
| 23751 | {.Opcode: AArch64::UBFMWri, .PatternStart: 1038, .NumPatterns: 3 }, |
| 23752 | {.Opcode: AArch64::UBFMXri, .PatternStart: 1041, .NumPatterns: 4 }, |
| 23753 | {.Opcode: AArch64::UMADDLrrr, .PatternStart: 1045, .NumPatterns: 1 }, |
| 23754 | {.Opcode: AArch64::UMOVvi32, .PatternStart: 1046, .NumPatterns: 1 }, |
| 23755 | {.Opcode: AArch64::UMOVvi32_idx0, .PatternStart: 1047, .NumPatterns: 1 }, |
| 23756 | {.Opcode: AArch64::UMOVvi64, .PatternStart: 1048, .NumPatterns: 1 }, |
| 23757 | {.Opcode: AArch64::UMOVvi64_idx0, .PatternStart: 1049, .NumPatterns: 1 }, |
| 23758 | {.Opcode: AArch64::UMSUBLrrr, .PatternStart: 1050, .NumPatterns: 1 }, |
| 23759 | {.Opcode: AArch64::UQDECB_WPiI, .PatternStart: 1051, .NumPatterns: 2 }, |
| 23760 | {.Opcode: AArch64::UQDECB_XPiI, .PatternStart: 1053, .NumPatterns: 2 }, |
| 23761 | {.Opcode: AArch64::UQDECD_WPiI, .PatternStart: 1055, .NumPatterns: 2 }, |
| 23762 | {.Opcode: AArch64::UQDECD_XPiI, .PatternStart: 1057, .NumPatterns: 2 }, |
| 23763 | {.Opcode: AArch64::UQDECD_ZPiI, .PatternStart: 1059, .NumPatterns: 2 }, |
| 23764 | {.Opcode: AArch64::UQDECH_WPiI, .PatternStart: 1061, .NumPatterns: 2 }, |
| 23765 | {.Opcode: AArch64::UQDECH_XPiI, .PatternStart: 1063, .NumPatterns: 2 }, |
| 23766 | {.Opcode: AArch64::UQDECH_ZPiI, .PatternStart: 1065, .NumPatterns: 2 }, |
| 23767 | {.Opcode: AArch64::UQDECW_WPiI, .PatternStart: 1067, .NumPatterns: 2 }, |
| 23768 | {.Opcode: AArch64::UQDECW_XPiI, .PatternStart: 1069, .NumPatterns: 2 }, |
| 23769 | {.Opcode: AArch64::UQDECW_ZPiI, .PatternStart: 1071, .NumPatterns: 2 }, |
| 23770 | {.Opcode: AArch64::UQINCB_WPiI, .PatternStart: 1073, .NumPatterns: 2 }, |
| 23771 | {.Opcode: AArch64::UQINCB_XPiI, .PatternStart: 1075, .NumPatterns: 2 }, |
| 23772 | {.Opcode: AArch64::UQINCD_WPiI, .PatternStart: 1077, .NumPatterns: 2 }, |
| 23773 | {.Opcode: AArch64::UQINCD_XPiI, .PatternStart: 1079, .NumPatterns: 2 }, |
| 23774 | {.Opcode: AArch64::UQINCD_ZPiI, .PatternStart: 1081, .NumPatterns: 2 }, |
| 23775 | {.Opcode: AArch64::UQINCH_WPiI, .PatternStart: 1083, .NumPatterns: 2 }, |
| 23776 | {.Opcode: AArch64::UQINCH_XPiI, .PatternStart: 1085, .NumPatterns: 2 }, |
| 23777 | {.Opcode: AArch64::UQINCH_ZPiI, .PatternStart: 1087, .NumPatterns: 2 }, |
| 23778 | {.Opcode: AArch64::UQINCW_WPiI, .PatternStart: 1089, .NumPatterns: 2 }, |
| 23779 | {.Opcode: AArch64::UQINCW_XPiI, .PatternStart: 1091, .NumPatterns: 2 }, |
| 23780 | {.Opcode: AArch64::UQINCW_ZPiI, .PatternStart: 1093, .NumPatterns: 2 }, |
| 23781 | {.Opcode: AArch64::XPACLRI, .PatternStart: 1095, .NumPatterns: 1 }, |
| 23782 | {.Opcode: AArch64::ZERO_M, .PatternStart: 1096, .NumPatterns: 15 }, |
| 23783 | }; |
| 23784 | |
| 23785 | static const AliasPattern Patterns[] = { |
| 23786 | // AArch64::ADDPT_shift - 0 |
| 23787 | {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 4, .NumConds: 7 }, |
| 23788 | // AArch64::ADDSWri - 1 |
| 23789 | {.AsmStrOffset: 17, .AliasCondStart: 7, .NumOperands: 4, .NumConds: 2 }, |
| 23790 | // AArch64::ADDSWrs - 2 |
| 23791 | {.AsmStrOffset: 30, .AliasCondStart: 9, .NumOperands: 4, .NumConds: 4 }, |
| 23792 | {.AsmStrOffset: 41, .AliasCondStart: 13, .NumOperands: 4, .NumConds: 3 }, |
| 23793 | {.AsmStrOffset: 56, .AliasCondStart: 16, .NumOperands: 4, .NumConds: 4 }, |
| 23794 | // AArch64::ADDSWrx - 5 |
| 23795 | {.AsmStrOffset: 30, .AliasCondStart: 20, .NumOperands: 4, .NumConds: 4 }, |
| 23796 | {.AsmStrOffset: 72, .AliasCondStart: 24, .NumOperands: 4, .NumConds: 3 }, |
| 23797 | {.AsmStrOffset: 56, .AliasCondStart: 27, .NumOperands: 4, .NumConds: 4 }, |
| 23798 | // AArch64::ADDSXri - 8 |
| 23799 | {.AsmStrOffset: 17, .AliasCondStart: 31, .NumOperands: 4, .NumConds: 2 }, |
| 23800 | // AArch64::ADDSXrs - 9 |
| 23801 | {.AsmStrOffset: 30, .AliasCondStart: 33, .NumOperands: 4, .NumConds: 4 }, |
| 23802 | {.AsmStrOffset: 41, .AliasCondStart: 37, .NumOperands: 4, .NumConds: 3 }, |
| 23803 | {.AsmStrOffset: 56, .AliasCondStart: 40, .NumOperands: 4, .NumConds: 4 }, |
| 23804 | // AArch64::ADDSXrx - 12 |
| 23805 | {.AsmStrOffset: 72, .AliasCondStart: 44, .NumOperands: 4, .NumConds: 3 }, |
| 23806 | // AArch64::ADDSXrx64 - 13 |
| 23807 | {.AsmStrOffset: 30, .AliasCondStart: 47, .NumOperands: 4, .NumConds: 4 }, |
| 23808 | {.AsmStrOffset: 72, .AliasCondStart: 51, .NumOperands: 4, .NumConds: 3 }, |
| 23809 | {.AsmStrOffset: 56, .AliasCondStart: 54, .NumOperands: 4, .NumConds: 4 }, |
| 23810 | // AArch64::ADDWri - 16 |
| 23811 | {.AsmStrOffset: 87, .AliasCondStart: 58, .NumOperands: 4, .NumConds: 4 }, |
| 23812 | {.AsmStrOffset: 87, .AliasCondStart: 62, .NumOperands: 4, .NumConds: 4 }, |
| 23813 | // AArch64::ADDWrs - 18 |
| 23814 | {.AsmStrOffset: 98, .AliasCondStart: 66, .NumOperands: 4, .NumConds: 4 }, |
| 23815 | // AArch64::ADDWrx - 19 |
| 23816 | {.AsmStrOffset: 98, .AliasCondStart: 70, .NumOperands: 4, .NumConds: 4 }, |
| 23817 | {.AsmStrOffset: 98, .AliasCondStart: 74, .NumOperands: 4, .NumConds: 4 }, |
| 23818 | // AArch64::ADDXri - 21 |
| 23819 | {.AsmStrOffset: 87, .AliasCondStart: 78, .NumOperands: 4, .NumConds: 4 }, |
| 23820 | {.AsmStrOffset: 87, .AliasCondStart: 82, .NumOperands: 4, .NumConds: 4 }, |
| 23821 | // AArch64::ADDXrs - 23 |
| 23822 | {.AsmStrOffset: 98, .AliasCondStart: 86, .NumOperands: 4, .NumConds: 4 }, |
| 23823 | // AArch64::ADDXrx64 - 24 |
| 23824 | {.AsmStrOffset: 98, .AliasCondStart: 90, .NumOperands: 4, .NumConds: 4 }, |
| 23825 | {.AsmStrOffset: 98, .AliasCondStart: 94, .NumOperands: 4, .NumConds: 4 }, |
| 23826 | // AArch64::ANDSWri - 26 |
| 23827 | {.AsmStrOffset: 113, .AliasCondStart: 98, .NumOperands: 3, .NumConds: 2 }, |
| 23828 | // AArch64::ANDSWrs - 27 |
| 23829 | {.AsmStrOffset: 126, .AliasCondStart: 100, .NumOperands: 4, .NumConds: 4 }, |
| 23830 | {.AsmStrOffset: 137, .AliasCondStart: 104, .NumOperands: 4, .NumConds: 3 }, |
| 23831 | {.AsmStrOffset: 152, .AliasCondStart: 107, .NumOperands: 4, .NumConds: 4 }, |
| 23832 | // AArch64::ANDSXri - 30 |
| 23833 | {.AsmStrOffset: 168, .AliasCondStart: 111, .NumOperands: 3, .NumConds: 2 }, |
| 23834 | // AArch64::ANDSXrs - 31 |
| 23835 | {.AsmStrOffset: 126, .AliasCondStart: 113, .NumOperands: 4, .NumConds: 4 }, |
| 23836 | {.AsmStrOffset: 137, .AliasCondStart: 117, .NumOperands: 4, .NumConds: 3 }, |
| 23837 | {.AsmStrOffset: 152, .AliasCondStart: 120, .NumOperands: 4, .NumConds: 4 }, |
| 23838 | // AArch64::ANDS_PPzPP - 34 |
| 23839 | {.AsmStrOffset: 181, .AliasCondStart: 124, .NumOperands: 4, .NumConds: 8 }, |
| 23840 | // AArch64::ANDWrs - 35 |
| 23841 | {.AsmStrOffset: 205, .AliasCondStart: 132, .NumOperands: 4, .NumConds: 4 }, |
| 23842 | // AArch64::ANDXrs - 36 |
| 23843 | {.AsmStrOffset: 205, .AliasCondStart: 136, .NumOperands: 4, .NumConds: 4 }, |
| 23844 | // AArch64::AND_PPzPP - 37 |
| 23845 | {.AsmStrOffset: 220, .AliasCondStart: 140, .NumOperands: 4, .NumConds: 8 }, |
| 23846 | // AArch64::AND_ZI - 38 |
| 23847 | {.AsmStrOffset: 243, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 7 }, |
| 23848 | {.AsmStrOffset: 264, .AliasCondStart: 155, .NumOperands: 3, .NumConds: 7 }, |
| 23849 | {.AsmStrOffset: 285, .AliasCondStart: 162, .NumOperands: 3, .NumConds: 7 }, |
| 23850 | // AArch64::AUTIA1716 - 41 |
| 23851 | {.AsmStrOffset: 306, .AliasCondStart: 169, .NumOperands: 0, .NumConds: 3 }, |
| 23852 | // AArch64::AUTIASP - 42 |
| 23853 | {.AsmStrOffset: 316, .AliasCondStart: 172, .NumOperands: 0, .NumConds: 3 }, |
| 23854 | // AArch64::AUTIAZ - 43 |
| 23855 | {.AsmStrOffset: 324, .AliasCondStart: 175, .NumOperands: 0, .NumConds: 3 }, |
| 23856 | // AArch64::AUTIB1716 - 44 |
| 23857 | {.AsmStrOffset: 331, .AliasCondStart: 178, .NumOperands: 0, .NumConds: 3 }, |
| 23858 | // AArch64::AUTIBSP - 45 |
| 23859 | {.AsmStrOffset: 341, .AliasCondStart: 181, .NumOperands: 0, .NumConds: 3 }, |
| 23860 | // AArch64::AUTIBZ - 46 |
| 23861 | {.AsmStrOffset: 349, .AliasCondStart: 184, .NumOperands: 0, .NumConds: 3 }, |
| 23862 | // AArch64::BICSWrs - 47 |
| 23863 | {.AsmStrOffset: 356, .AliasCondStart: 187, .NumOperands: 4, .NumConds: 4 }, |
| 23864 | // AArch64::BICSXrs - 48 |
| 23865 | {.AsmStrOffset: 356, .AliasCondStart: 191, .NumOperands: 4, .NumConds: 4 }, |
| 23866 | // AArch64::BICWrs - 49 |
| 23867 | {.AsmStrOffset: 372, .AliasCondStart: 195, .NumOperands: 4, .NumConds: 4 }, |
| 23868 | // AArch64::BICXrs - 50 |
| 23869 | {.AsmStrOffset: 372, .AliasCondStart: 199, .NumOperands: 4, .NumConds: 4 }, |
| 23870 | // AArch64::CHKFEAT - 51 |
| 23871 | {.AsmStrOffset: 387, .AliasCondStart: 203, .NumOperands: 0, .NumConds: 3 }, |
| 23872 | // AArch64::CLREX - 52 |
| 23873 | {.AsmStrOffset: 399, .AliasCondStart: 206, .NumOperands: 1, .NumConds: 1 }, |
| 23874 | // AArch64::CNTB_XPiI - 53 |
| 23875 | {.AsmStrOffset: 405, .AliasCondStart: 207, .NumOperands: 3, .NumConds: 7 }, |
| 23876 | {.AsmStrOffset: 413, .AliasCondStart: 214, .NumOperands: 3, .NumConds: 7 }, |
| 23877 | // AArch64::CNTD_XPiI - 55 |
| 23878 | {.AsmStrOffset: 427, .AliasCondStart: 221, .NumOperands: 3, .NumConds: 7 }, |
| 23879 | {.AsmStrOffset: 435, .AliasCondStart: 228, .NumOperands: 3, .NumConds: 7 }, |
| 23880 | // AArch64::CNTH_XPiI - 57 |
| 23881 | {.AsmStrOffset: 449, .AliasCondStart: 235, .NumOperands: 3, .NumConds: 7 }, |
| 23882 | {.AsmStrOffset: 457, .AliasCondStart: 242, .NumOperands: 3, .NumConds: 7 }, |
| 23883 | // AArch64::CNTW_XPiI - 59 |
| 23884 | {.AsmStrOffset: 471, .AliasCondStart: 249, .NumOperands: 3, .NumConds: 7 }, |
| 23885 | {.AsmStrOffset: 479, .AliasCondStart: 256, .NumOperands: 3, .NumConds: 7 }, |
| 23886 | // AArch64::CPY_ZPmI_B - 61 |
| 23887 | {.AsmStrOffset: 493, .AliasCondStart: 263, .NumOperands: 5, .NumConds: 7 }, |
| 23888 | // AArch64::CPY_ZPmI_D - 62 |
| 23889 | {.AsmStrOffset: 516, .AliasCondStart: 270, .NumOperands: 5, .NumConds: 7 }, |
| 23890 | // AArch64::CPY_ZPmI_H - 63 |
| 23891 | {.AsmStrOffset: 539, .AliasCondStart: 277, .NumOperands: 5, .NumConds: 7 }, |
| 23892 | // AArch64::CPY_ZPmI_S - 64 |
| 23893 | {.AsmStrOffset: 562, .AliasCondStart: 284, .NumOperands: 5, .NumConds: 7 }, |
| 23894 | // AArch64::CPY_ZPmR_B - 65 |
| 23895 | {.AsmStrOffset: 585, .AliasCondStart: 291, .NumOperands: 4, .NumConds: 8 }, |
| 23896 | // AArch64::CPY_ZPmR_D - 66 |
| 23897 | {.AsmStrOffset: 606, .AliasCondStart: 299, .NumOperands: 4, .NumConds: 8 }, |
| 23898 | // AArch64::CPY_ZPmR_H - 67 |
| 23899 | {.AsmStrOffset: 627, .AliasCondStart: 307, .NumOperands: 4, .NumConds: 8 }, |
| 23900 | // AArch64::CPY_ZPmR_S - 68 |
| 23901 | {.AsmStrOffset: 648, .AliasCondStart: 315, .NumOperands: 4, .NumConds: 8 }, |
| 23902 | // AArch64::CPY_ZPmV_B - 69 |
| 23903 | {.AsmStrOffset: 585, .AliasCondStart: 323, .NumOperands: 4, .NumConds: 8 }, |
| 23904 | // AArch64::CPY_ZPmV_D - 70 |
| 23905 | {.AsmStrOffset: 606, .AliasCondStart: 331, .NumOperands: 4, .NumConds: 8 }, |
| 23906 | // AArch64::CPY_ZPmV_H - 71 |
| 23907 | {.AsmStrOffset: 627, .AliasCondStart: 339, .NumOperands: 4, .NumConds: 8 }, |
| 23908 | // AArch64::CPY_ZPmV_S - 72 |
| 23909 | {.AsmStrOffset: 648, .AliasCondStart: 347, .NumOperands: 4, .NumConds: 8 }, |
| 23910 | // AArch64::CPY_ZPzI_B - 73 |
| 23911 | {.AsmStrOffset: 669, .AliasCondStart: 355, .NumOperands: 4, .NumConds: 6 }, |
| 23912 | // AArch64::CPY_ZPzI_D - 74 |
| 23913 | {.AsmStrOffset: 692, .AliasCondStart: 361, .NumOperands: 4, .NumConds: 6 }, |
| 23914 | // AArch64::CPY_ZPzI_H - 75 |
| 23915 | {.AsmStrOffset: 715, .AliasCondStart: 367, .NumOperands: 4, .NumConds: 6 }, |
| 23916 | // AArch64::CPY_ZPzI_S - 76 |
| 23917 | {.AsmStrOffset: 738, .AliasCondStart: 373, .NumOperands: 4, .NumConds: 6 }, |
| 23918 | // AArch64::CSINCWr - 77 |
| 23919 | {.AsmStrOffset: 761, .AliasCondStart: 379, .NumOperands: 4, .NumConds: 4 }, |
| 23920 | {.AsmStrOffset: 775, .AliasCondStart: 383, .NumOperands: 4, .NumConds: 4 }, |
| 23921 | // AArch64::CSINCXr - 79 |
| 23922 | {.AsmStrOffset: 761, .AliasCondStart: 387, .NumOperands: 4, .NumConds: 4 }, |
| 23923 | {.AsmStrOffset: 775, .AliasCondStart: 391, .NumOperands: 4, .NumConds: 4 }, |
| 23924 | // AArch64::CSINVWr - 81 |
| 23925 | {.AsmStrOffset: 793, .AliasCondStart: 395, .NumOperands: 4, .NumConds: 4 }, |
| 23926 | {.AsmStrOffset: 808, .AliasCondStart: 399, .NumOperands: 4, .NumConds: 4 }, |
| 23927 | // AArch64::CSINVXr - 83 |
| 23928 | {.AsmStrOffset: 793, .AliasCondStart: 403, .NumOperands: 4, .NumConds: 4 }, |
| 23929 | {.AsmStrOffset: 808, .AliasCondStart: 407, .NumOperands: 4, .NumConds: 4 }, |
| 23930 | // AArch64::CSNEGWr - 85 |
| 23931 | {.AsmStrOffset: 826, .AliasCondStart: 411, .NumOperands: 4, .NumConds: 4 }, |
| 23932 | // AArch64::CSNEGXr - 86 |
| 23933 | {.AsmStrOffset: 826, .AliasCondStart: 415, .NumOperands: 4, .NumConds: 4 }, |
| 23934 | // AArch64::DCPS1 - 87 |
| 23935 | {.AsmStrOffset: 844, .AliasCondStart: 419, .NumOperands: 1, .NumConds: 1 }, |
| 23936 | // AArch64::DCPS2 - 88 |
| 23937 | {.AsmStrOffset: 850, .AliasCondStart: 420, .NumOperands: 1, .NumConds: 1 }, |
| 23938 | // AArch64::DCPS3 - 89 |
| 23939 | {.AsmStrOffset: 856, .AliasCondStart: 421, .NumOperands: 1, .NumConds: 4 }, |
| 23940 | // AArch64::DECB_XPiI - 90 |
| 23941 | {.AsmStrOffset: 862, .AliasCondStart: 425, .NumOperands: 4, .NumConds: 8 }, |
| 23942 | {.AsmStrOffset: 870, .AliasCondStart: 433, .NumOperands: 4, .NumConds: 8 }, |
| 23943 | // AArch64::DECD_XPiI - 92 |
| 23944 | {.AsmStrOffset: 884, .AliasCondStart: 441, .NumOperands: 4, .NumConds: 8 }, |
| 23945 | {.AsmStrOffset: 892, .AliasCondStart: 449, .NumOperands: 4, .NumConds: 8 }, |
| 23946 | // AArch64::DECD_ZPiI - 94 |
| 23947 | {.AsmStrOffset: 906, .AliasCondStart: 457, .NumOperands: 4, .NumConds: 8 }, |
| 23948 | {.AsmStrOffset: 916, .AliasCondStart: 465, .NumOperands: 4, .NumConds: 8 }, |
| 23949 | // AArch64::DECH_XPiI - 96 |
| 23950 | {.AsmStrOffset: 932, .AliasCondStart: 473, .NumOperands: 4, .NumConds: 8 }, |
| 23951 | {.AsmStrOffset: 940, .AliasCondStart: 481, .NumOperands: 4, .NumConds: 8 }, |
| 23952 | // AArch64::DECH_ZPiI - 98 |
| 23953 | {.AsmStrOffset: 954, .AliasCondStart: 489, .NumOperands: 4, .NumConds: 8 }, |
| 23954 | {.AsmStrOffset: 964, .AliasCondStart: 497, .NumOperands: 4, .NumConds: 8 }, |
| 23955 | // AArch64::DECW_XPiI - 100 |
| 23956 | {.AsmStrOffset: 980, .AliasCondStart: 505, .NumOperands: 4, .NumConds: 8 }, |
| 23957 | {.AsmStrOffset: 988, .AliasCondStart: 513, .NumOperands: 4, .NumConds: 8 }, |
| 23958 | // AArch64::DECW_ZPiI - 102 |
| 23959 | {.AsmStrOffset: 1002, .AliasCondStart: 521, .NumOperands: 4, .NumConds: 8 }, |
| 23960 | {.AsmStrOffset: 1012, .AliasCondStart: 529, .NumOperands: 4, .NumConds: 8 }, |
| 23961 | // AArch64::DSB - 104 |
| 23962 | {.AsmStrOffset: 1028, .AliasCondStart: 537, .NumOperands: 1, .NumConds: 1 }, |
| 23963 | {.AsmStrOffset: 1033, .AliasCondStart: 538, .NumOperands: 1, .NumConds: 1 }, |
| 23964 | {.AsmStrOffset: 1039, .AliasCondStart: 539, .NumOperands: 1, .NumConds: 4 }, |
| 23965 | // AArch64::DUPM_ZI - 107 |
| 23966 | {.AsmStrOffset: 1043, .AliasCondStart: 543, .NumOperands: 2, .NumConds: 6 }, |
| 23967 | {.AsmStrOffset: 1058, .AliasCondStart: 549, .NumOperands: 2, .NumConds: 6 }, |
| 23968 | {.AsmStrOffset: 1073, .AliasCondStart: 555, .NumOperands: 2, .NumConds: 6 }, |
| 23969 | {.AsmStrOffset: 1088, .AliasCondStart: 561, .NumOperands: 2, .NumConds: 6 }, |
| 23970 | {.AsmStrOffset: 1104, .AliasCondStart: 567, .NumOperands: 2, .NumConds: 6 }, |
| 23971 | {.AsmStrOffset: 1120, .AliasCondStart: 573, .NumOperands: 2, .NumConds: 6 }, |
| 23972 | // AArch64::DUP_ZI_B - 113 |
| 23973 | {.AsmStrOffset: 1136, .AliasCondStart: 579, .NumOperands: 3, .NumConds: 5 }, |
| 23974 | // AArch64::DUP_ZI_D - 114 |
| 23975 | {.AsmStrOffset: 1151, .AliasCondStart: 584, .NumOperands: 3, .NumConds: 5 }, |
| 23976 | {.AsmStrOffset: 1166, .AliasCondStart: 589, .NumOperands: 3, .NumConds: 7 }, |
| 23977 | // AArch64::DUP_ZI_H - 116 |
| 23978 | {.AsmStrOffset: 1182, .AliasCondStart: 596, .NumOperands: 3, .NumConds: 5 }, |
| 23979 | {.AsmStrOffset: 1197, .AliasCondStart: 601, .NumOperands: 3, .NumConds: 7 }, |
| 23980 | // AArch64::DUP_ZI_S - 118 |
| 23981 | {.AsmStrOffset: 1213, .AliasCondStart: 608, .NumOperands: 3, .NumConds: 5 }, |
| 23982 | {.AsmStrOffset: 1228, .AliasCondStart: 613, .NumOperands: 3, .NumConds: 7 }, |
| 23983 | // AArch64::DUP_ZR_B - 120 |
| 23984 | {.AsmStrOffset: 1244, .AliasCondStart: 620, .NumOperands: 2, .NumConds: 6 }, |
| 23985 | // AArch64::DUP_ZR_D - 121 |
| 23986 | {.AsmStrOffset: 1257, .AliasCondStart: 626, .NumOperands: 2, .NumConds: 6 }, |
| 23987 | // AArch64::DUP_ZR_H - 122 |
| 23988 | {.AsmStrOffset: 1270, .AliasCondStart: 632, .NumOperands: 2, .NumConds: 6 }, |
| 23989 | // AArch64::DUP_ZR_S - 123 |
| 23990 | {.AsmStrOffset: 1283, .AliasCondStart: 638, .NumOperands: 2, .NumConds: 6 }, |
| 23991 | // AArch64::DUP_ZZI_B - 124 |
| 23992 | {.AsmStrOffset: 1296, .AliasCondStart: 644, .NumOperands: 3, .NumConds: 7 }, |
| 23993 | {.AsmStrOffset: 1311, .AliasCondStart: 651, .NumOperands: 3, .NumConds: 6 }, |
| 23994 | // AArch64::DUP_ZZI_D - 126 |
| 23995 | {.AsmStrOffset: 1330, .AliasCondStart: 657, .NumOperands: 3, .NumConds: 7 }, |
| 23996 | {.AsmStrOffset: 1345, .AliasCondStart: 664, .NumOperands: 3, .NumConds: 6 }, |
| 23997 | // AArch64::DUP_ZZI_H - 128 |
| 23998 | {.AsmStrOffset: 1364, .AliasCondStart: 670, .NumOperands: 3, .NumConds: 7 }, |
| 23999 | {.AsmStrOffset: 1379, .AliasCondStart: 677, .NumOperands: 3, .NumConds: 6 }, |
| 24000 | // AArch64::DUP_ZZI_Q - 130 |
| 24001 | {.AsmStrOffset: 1398, .AliasCondStart: 683, .NumOperands: 3, .NumConds: 7 }, |
| 24002 | {.AsmStrOffset: 1413, .AliasCondStart: 690, .NumOperands: 3, .NumConds: 6 }, |
| 24003 | // AArch64::DUP_ZZI_S - 132 |
| 24004 | {.AsmStrOffset: 1432, .AliasCondStart: 696, .NumOperands: 3, .NumConds: 7 }, |
| 24005 | {.AsmStrOffset: 1447, .AliasCondStart: 703, .NumOperands: 3, .NumConds: 6 }, |
| 24006 | // AArch64::EONWrs - 134 |
| 24007 | {.AsmStrOffset: 1466, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 4 }, |
| 24008 | // AArch64::EONXrs - 135 |
| 24009 | {.AsmStrOffset: 1466, .AliasCondStart: 713, .NumOperands: 4, .NumConds: 4 }, |
| 24010 | // AArch64::EORS_PPzPP - 136 |
| 24011 | {.AsmStrOffset: 1481, .AliasCondStart: 717, .NumOperands: 4, .NumConds: 8 }, |
| 24012 | // AArch64::EORWrs - 137 |
| 24013 | {.AsmStrOffset: 1505, .AliasCondStart: 725, .NumOperands: 4, .NumConds: 4 }, |
| 24014 | // AArch64::EORXrs - 138 |
| 24015 | {.AsmStrOffset: 1505, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 4 }, |
| 24016 | // AArch64::EOR_PPzPP - 139 |
| 24017 | {.AsmStrOffset: 1520, .AliasCondStart: 733, .NumOperands: 4, .NumConds: 8 }, |
| 24018 | // AArch64::EOR_ZI - 140 |
| 24019 | {.AsmStrOffset: 1543, .AliasCondStart: 741, .NumOperands: 3, .NumConds: 7 }, |
| 24020 | {.AsmStrOffset: 1564, .AliasCondStart: 748, .NumOperands: 3, .NumConds: 7 }, |
| 24021 | {.AsmStrOffset: 1585, .AliasCondStart: 755, .NumOperands: 3, .NumConds: 7 }, |
| 24022 | // AArch64::EXTRACT_ZPMXI_H_B - 143 |
| 24023 | {.AsmStrOffset: 1606, .AliasCondStart: 762, .NumOperands: 6, .NumConds: 8 }, |
| 24024 | // AArch64::EXTRACT_ZPMXI_H_D - 144 |
| 24025 | {.AsmStrOffset: 1639, .AliasCondStart: 770, .NumOperands: 6, .NumConds: 8 }, |
| 24026 | // AArch64::EXTRACT_ZPMXI_H_H - 145 |
| 24027 | {.AsmStrOffset: 1672, .AliasCondStart: 778, .NumOperands: 6, .NumConds: 8 }, |
| 24028 | // AArch64::EXTRACT_ZPMXI_H_Q - 146 |
| 24029 | {.AsmStrOffset: 1705, .AliasCondStart: 786, .NumOperands: 6, .NumConds: 8 }, |
| 24030 | // AArch64::EXTRACT_ZPMXI_H_S - 147 |
| 24031 | {.AsmStrOffset: 1738, .AliasCondStart: 794, .NumOperands: 6, .NumConds: 8 }, |
| 24032 | // AArch64::EXTRACT_ZPMXI_V_B - 148 |
| 24033 | {.AsmStrOffset: 1771, .AliasCondStart: 802, .NumOperands: 6, .NumConds: 8 }, |
| 24034 | // AArch64::EXTRACT_ZPMXI_V_D - 149 |
| 24035 | {.AsmStrOffset: 1804, .AliasCondStart: 810, .NumOperands: 6, .NumConds: 8 }, |
| 24036 | // AArch64::EXTRACT_ZPMXI_V_H - 150 |
| 24037 | {.AsmStrOffset: 1837, .AliasCondStart: 818, .NumOperands: 6, .NumConds: 8 }, |
| 24038 | // AArch64::EXTRACT_ZPMXI_V_Q - 151 |
| 24039 | {.AsmStrOffset: 1870, .AliasCondStart: 826, .NumOperands: 6, .NumConds: 8 }, |
| 24040 | // AArch64::EXTRACT_ZPMXI_V_S - 152 |
| 24041 | {.AsmStrOffset: 1903, .AliasCondStart: 834, .NumOperands: 6, .NumConds: 8 }, |
| 24042 | // AArch64::EXTRWrri - 153 |
| 24043 | {.AsmStrOffset: 1936, .AliasCondStart: 842, .NumOperands: 4, .NumConds: 3 }, |
| 24044 | // AArch64::EXTRXrri - 154 |
| 24045 | {.AsmStrOffset: 1936, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 3 }, |
| 24046 | // AArch64::FCPY_ZPmI_D - 155 |
| 24047 | {.AsmStrOffset: 1951, .AliasCondStart: 848, .NumOperands: 4, .NumConds: 7 }, |
| 24048 | // AArch64::FCPY_ZPmI_H - 156 |
| 24049 | {.AsmStrOffset: 1975, .AliasCondStart: 855, .NumOperands: 4, .NumConds: 7 }, |
| 24050 | // AArch64::FCPY_ZPmI_S - 157 |
| 24051 | {.AsmStrOffset: 1999, .AliasCondStart: 862, .NumOperands: 4, .NumConds: 7 }, |
| 24052 | // AArch64::FDUP_ZI_D - 158 |
| 24053 | {.AsmStrOffset: 2023, .AliasCondStart: 869, .NumOperands: 2, .NumConds: 5 }, |
| 24054 | // AArch64::FDUP_ZI_H - 159 |
| 24055 | {.AsmStrOffset: 2039, .AliasCondStart: 874, .NumOperands: 2, .NumConds: 5 }, |
| 24056 | // AArch64::FDUP_ZI_S - 160 |
| 24057 | {.AsmStrOffset: 2055, .AliasCondStart: 879, .NumOperands: 2, .NumConds: 5 }, |
| 24058 | // AArch64::GCSPOPM - 161 |
| 24059 | {.AsmStrOffset: 2071, .AliasCondStart: 884, .NumOperands: 2, .NumConds: 4 }, |
| 24060 | // AArch64::GLD1B_D_IMM - 162 |
| 24061 | {.AsmStrOffset: 2079, .AliasCondStart: 888, .NumOperands: 4, .NumConds: 7 }, |
| 24062 | // AArch64::GLD1B_S_IMM - 163 |
| 24063 | {.AsmStrOffset: 2105, .AliasCondStart: 895, .NumOperands: 4, .NumConds: 7 }, |
| 24064 | // AArch64::GLD1D_IMM - 164 |
| 24065 | {.AsmStrOffset: 2131, .AliasCondStart: 902, .NumOperands: 4, .NumConds: 7 }, |
| 24066 | // AArch64::GLD1H_D_IMM - 165 |
| 24067 | {.AsmStrOffset: 2157, .AliasCondStart: 909, .NumOperands: 4, .NumConds: 7 }, |
| 24068 | // AArch64::GLD1H_S_IMM - 166 |
| 24069 | {.AsmStrOffset: 2183, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 7 }, |
| 24070 | // AArch64::GLD1Q - 167 |
| 24071 | {.AsmStrOffset: 2209, .AliasCondStart: 923, .NumOperands: 4, .NumConds: 7 }, |
| 24072 | // AArch64::GLD1SB_D_IMM - 168 |
| 24073 | {.AsmStrOffset: 2235, .AliasCondStart: 930, .NumOperands: 4, .NumConds: 7 }, |
| 24074 | // AArch64::GLD1SB_S_IMM - 169 |
| 24075 | {.AsmStrOffset: 2262, .AliasCondStart: 937, .NumOperands: 4, .NumConds: 7 }, |
| 24076 | // AArch64::GLD1SH_D_IMM - 170 |
| 24077 | {.AsmStrOffset: 2289, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 7 }, |
| 24078 | // AArch64::GLD1SH_S_IMM - 171 |
| 24079 | {.AsmStrOffset: 2316, .AliasCondStart: 951, .NumOperands: 4, .NumConds: 7 }, |
| 24080 | // AArch64::GLD1SW_D_IMM - 172 |
| 24081 | {.AsmStrOffset: 2343, .AliasCondStart: 958, .NumOperands: 4, .NumConds: 7 }, |
| 24082 | // AArch64::GLD1W_D_IMM - 173 |
| 24083 | {.AsmStrOffset: 2370, .AliasCondStart: 965, .NumOperands: 4, .NumConds: 7 }, |
| 24084 | // AArch64::GLD1W_IMM - 174 |
| 24085 | {.AsmStrOffset: 2396, .AliasCondStart: 972, .NumOperands: 4, .NumConds: 7 }, |
| 24086 | // AArch64::GLDFF1B_D_IMM - 175 |
| 24087 | {.AsmStrOffset: 2422, .AliasCondStart: 979, .NumOperands: 4, .NumConds: 7 }, |
| 24088 | // AArch64::GLDFF1B_S_IMM - 176 |
| 24089 | {.AsmStrOffset: 2450, .AliasCondStart: 986, .NumOperands: 4, .NumConds: 7 }, |
| 24090 | // AArch64::GLDFF1D_IMM - 177 |
| 24091 | {.AsmStrOffset: 2478, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 7 }, |
| 24092 | // AArch64::GLDFF1H_D_IMM - 178 |
| 24093 | {.AsmStrOffset: 2506, .AliasCondStart: 1000, .NumOperands: 4, .NumConds: 7 }, |
| 24094 | // AArch64::GLDFF1H_S_IMM - 179 |
| 24095 | {.AsmStrOffset: 2534, .AliasCondStart: 1007, .NumOperands: 4, .NumConds: 7 }, |
| 24096 | // AArch64::GLDFF1SB_D_IMM - 180 |
| 24097 | {.AsmStrOffset: 2562, .AliasCondStart: 1014, .NumOperands: 4, .NumConds: 7 }, |
| 24098 | // AArch64::GLDFF1SB_S_IMM - 181 |
| 24099 | {.AsmStrOffset: 2591, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 7 }, |
| 24100 | // AArch64::GLDFF1SH_D_IMM - 182 |
| 24101 | {.AsmStrOffset: 2620, .AliasCondStart: 1028, .NumOperands: 4, .NumConds: 7 }, |
| 24102 | // AArch64::GLDFF1SH_S_IMM - 183 |
| 24103 | {.AsmStrOffset: 2649, .AliasCondStart: 1035, .NumOperands: 4, .NumConds: 7 }, |
| 24104 | // AArch64::GLDFF1SW_D_IMM - 184 |
| 24105 | {.AsmStrOffset: 2678, .AliasCondStart: 1042, .NumOperands: 4, .NumConds: 7 }, |
| 24106 | // AArch64::GLDFF1W_D_IMM - 185 |
| 24107 | {.AsmStrOffset: 2707, .AliasCondStart: 1049, .NumOperands: 4, .NumConds: 7 }, |
| 24108 | // AArch64::GLDFF1W_IMM - 186 |
| 24109 | {.AsmStrOffset: 2735, .AliasCondStart: 1056, .NumOperands: 4, .NumConds: 7 }, |
| 24110 | // AArch64::HINT - 187 |
| 24111 | {.AsmStrOffset: 2763, .AliasCondStart: 1063, .NumOperands: 1, .NumConds: 1 }, |
| 24112 | {.AsmStrOffset: 2767, .AliasCondStart: 1064, .NumOperands: 1, .NumConds: 1 }, |
| 24113 | {.AsmStrOffset: 2773, .AliasCondStart: 1065, .NumOperands: 1, .NumConds: 1 }, |
| 24114 | {.AsmStrOffset: 2777, .AliasCondStart: 1066, .NumOperands: 1, .NumConds: 1 }, |
| 24115 | {.AsmStrOffset: 2781, .AliasCondStart: 1067, .NumOperands: 1, .NumConds: 1 }, |
| 24116 | {.AsmStrOffset: 2785, .AliasCondStart: 1068, .NumOperands: 1, .NumConds: 1 }, |
| 24117 | {.AsmStrOffset: 2790, .AliasCondStart: 1069, .NumOperands: 1, .NumConds: 1 }, |
| 24118 | {.AsmStrOffset: 2794, .AliasCondStart: 1070, .NumOperands: 1, .NumConds: 4 }, |
| 24119 | {.AsmStrOffset: 2798, .AliasCondStart: 1074, .NumOperands: 1, .NumConds: 1 }, |
| 24120 | {.AsmStrOffset: 2803, .AliasCondStart: 1075, .NumOperands: 1, .NumConds: 4 }, |
| 24121 | {.AsmStrOffset: 2807, .AliasCondStart: 1079, .NumOperands: 1, .NumConds: 4 }, |
| 24122 | {.AsmStrOffset: 2816, .AliasCondStart: 1083, .NumOperands: 1, .NumConds: 4 }, |
| 24123 | {.AsmStrOffset: 2825, .AliasCondStart: 1087, .NumOperands: 1, .NumConds: 4 }, |
| 24124 | {.AsmStrOffset: 2836, .AliasCondStart: 1091, .NumOperands: 1, .NumConds: 4 }, |
| 24125 | // AArch64::INCB_XPiI - 201 |
| 24126 | {.AsmStrOffset: 2843, .AliasCondStart: 1095, .NumOperands: 4, .NumConds: 8 }, |
| 24127 | {.AsmStrOffset: 2851, .AliasCondStart: 1103, .NumOperands: 4, .NumConds: 8 }, |
| 24128 | // AArch64::INCD_XPiI - 203 |
| 24129 | {.AsmStrOffset: 2865, .AliasCondStart: 1111, .NumOperands: 4, .NumConds: 8 }, |
| 24130 | {.AsmStrOffset: 2873, .AliasCondStart: 1119, .NumOperands: 4, .NumConds: 8 }, |
| 24131 | // AArch64::INCD_ZPiI - 205 |
| 24132 | {.AsmStrOffset: 2887, .AliasCondStart: 1127, .NumOperands: 4, .NumConds: 8 }, |
| 24133 | {.AsmStrOffset: 2897, .AliasCondStart: 1135, .NumOperands: 4, .NumConds: 8 }, |
| 24134 | // AArch64::INCH_XPiI - 207 |
| 24135 | {.AsmStrOffset: 2913, .AliasCondStart: 1143, .NumOperands: 4, .NumConds: 8 }, |
| 24136 | {.AsmStrOffset: 2921, .AliasCondStart: 1151, .NumOperands: 4, .NumConds: 8 }, |
| 24137 | // AArch64::INCH_ZPiI - 209 |
| 24138 | {.AsmStrOffset: 2935, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 8 }, |
| 24139 | {.AsmStrOffset: 2945, .AliasCondStart: 1167, .NumOperands: 4, .NumConds: 8 }, |
| 24140 | // AArch64::INCW_XPiI - 211 |
| 24141 | {.AsmStrOffset: 2961, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 8 }, |
| 24142 | {.AsmStrOffset: 2969, .AliasCondStart: 1183, .NumOperands: 4, .NumConds: 8 }, |
| 24143 | // AArch64::INCW_ZPiI - 213 |
| 24144 | {.AsmStrOffset: 2983, .AliasCondStart: 1191, .NumOperands: 4, .NumConds: 8 }, |
| 24145 | {.AsmStrOffset: 2993, .AliasCondStart: 1199, .NumOperands: 4, .NumConds: 8 }, |
| 24146 | // AArch64::INSERT_MXIPZ_H_B - 215 |
| 24147 | {.AsmStrOffset: 3009, .AliasCondStart: 1207, .NumOperands: 6, .NumConds: 9 }, |
| 24148 | // AArch64::INSERT_MXIPZ_H_D - 216 |
| 24149 | {.AsmStrOffset: 3042, .AliasCondStart: 1216, .NumOperands: 6, .NumConds: 9 }, |
| 24150 | // AArch64::INSERT_MXIPZ_H_H - 217 |
| 24151 | {.AsmStrOffset: 3075, .AliasCondStart: 1225, .NumOperands: 6, .NumConds: 9 }, |
| 24152 | // AArch64::INSERT_MXIPZ_H_Q - 218 |
| 24153 | {.AsmStrOffset: 3108, .AliasCondStart: 1234, .NumOperands: 6, .NumConds: 9 }, |
| 24154 | // AArch64::INSERT_MXIPZ_H_S - 219 |
| 24155 | {.AsmStrOffset: 3141, .AliasCondStart: 1243, .NumOperands: 6, .NumConds: 9 }, |
| 24156 | // AArch64::INSERT_MXIPZ_V_B - 220 |
| 24157 | {.AsmStrOffset: 3174, .AliasCondStart: 1252, .NumOperands: 6, .NumConds: 9 }, |
| 24158 | // AArch64::INSERT_MXIPZ_V_D - 221 |
| 24159 | {.AsmStrOffset: 3207, .AliasCondStart: 1261, .NumOperands: 6, .NumConds: 9 }, |
| 24160 | // AArch64::INSERT_MXIPZ_V_H - 222 |
| 24161 | {.AsmStrOffset: 3240, .AliasCondStart: 1270, .NumOperands: 6, .NumConds: 9 }, |
| 24162 | // AArch64::INSERT_MXIPZ_V_Q - 223 |
| 24163 | {.AsmStrOffset: 3273, .AliasCondStart: 1279, .NumOperands: 6, .NumConds: 9 }, |
| 24164 | // AArch64::INSERT_MXIPZ_V_S - 224 |
| 24165 | {.AsmStrOffset: 3306, .AliasCondStart: 1288, .NumOperands: 6, .NumConds: 9 }, |
| 24166 | // AArch64::INSvi16gpr - 225 |
| 24167 | {.AsmStrOffset: 3339, .AliasCondStart: 1297, .NumOperands: 4, .NumConds: 7 }, |
| 24168 | // AArch64::INSvi16lane - 226 |
| 24169 | {.AsmStrOffset: 3358, .AliasCondStart: 1304, .NumOperands: 5, .NumConds: 7 }, |
| 24170 | // AArch64::INSvi32gpr - 227 |
| 24171 | {.AsmStrOffset: 3383, .AliasCondStart: 1311, .NumOperands: 4, .NumConds: 7 }, |
| 24172 | // AArch64::INSvi32lane - 228 |
| 24173 | {.AsmStrOffset: 3402, .AliasCondStart: 1318, .NumOperands: 5, .NumConds: 7 }, |
| 24174 | // AArch64::INSvi64gpr - 229 |
| 24175 | {.AsmStrOffset: 3427, .AliasCondStart: 1325, .NumOperands: 4, .NumConds: 7 }, |
| 24176 | // AArch64::INSvi64lane - 230 |
| 24177 | {.AsmStrOffset: 3446, .AliasCondStart: 1332, .NumOperands: 5, .NumConds: 7 }, |
| 24178 | // AArch64::INSvi8gpr - 231 |
| 24179 | {.AsmStrOffset: 3471, .AliasCondStart: 1339, .NumOperands: 4, .NumConds: 7 }, |
| 24180 | // AArch64::INSvi8lane - 232 |
| 24181 | {.AsmStrOffset: 3490, .AliasCondStart: 1346, .NumOperands: 5, .NumConds: 7 }, |
| 24182 | // AArch64::IRG - 233 |
| 24183 | {.AsmStrOffset: 3515, .AliasCondStart: 1353, .NumOperands: 3, .NumConds: 6 }, |
| 24184 | // AArch64::ISB - 234 |
| 24185 | {.AsmStrOffset: 3526, .AliasCondStart: 1359, .NumOperands: 1, .NumConds: 1 }, |
| 24186 | // AArch64::LD1B_2Z_IMM - 235 |
| 24187 | {.AsmStrOffset: 3530, .AliasCondStart: 1360, .NumOperands: 4, .NumConds: 8 }, |
| 24188 | // AArch64::LD1B_2Z_STRIDED_IMM - 236 |
| 24189 | {.AsmStrOffset: 3554, .AliasCondStart: 1368, .NumOperands: 4, .NumConds: 7 }, |
| 24190 | // AArch64::LD1B_4Z_IMM - 237 |
| 24191 | {.AsmStrOffset: 3530, .AliasCondStart: 1375, .NumOperands: 4, .NumConds: 8 }, |
| 24192 | // AArch64::LD1B_4Z_STRIDED_IMM - 238 |
| 24193 | {.AsmStrOffset: 3578, .AliasCondStart: 1383, .NumOperands: 4, .NumConds: 7 }, |
| 24194 | // AArch64::LD1B_D_IMM - 239 |
| 24195 | {.AsmStrOffset: 3602, .AliasCondStart: 1390, .NumOperands: 4, .NumConds: 8 }, |
| 24196 | // AArch64::LD1B_H_IMM - 240 |
| 24197 | {.AsmStrOffset: 3626, .AliasCondStart: 1398, .NumOperands: 4, .NumConds: 8 }, |
| 24198 | // AArch64::LD1B_IMM - 241 |
| 24199 | {.AsmStrOffset: 3650, .AliasCondStart: 1406, .NumOperands: 4, .NumConds: 8 }, |
| 24200 | // AArch64::LD1B_S_IMM - 242 |
| 24201 | {.AsmStrOffset: 3674, .AliasCondStart: 1414, .NumOperands: 4, .NumConds: 8 }, |
| 24202 | // AArch64::LD1D_2Z_IMM - 243 |
| 24203 | {.AsmStrOffset: 3698, .AliasCondStart: 1422, .NumOperands: 4, .NumConds: 8 }, |
| 24204 | // AArch64::LD1D_2Z_STRIDED_IMM - 244 |
| 24205 | {.AsmStrOffset: 3722, .AliasCondStart: 1430, .NumOperands: 4, .NumConds: 7 }, |
| 24206 | // AArch64::LD1D_4Z_IMM - 245 |
| 24207 | {.AsmStrOffset: 3698, .AliasCondStart: 1437, .NumOperands: 4, .NumConds: 8 }, |
| 24208 | // AArch64::LD1D_4Z_STRIDED_IMM - 246 |
| 24209 | {.AsmStrOffset: 3722, .AliasCondStart: 1445, .NumOperands: 4, .NumConds: 7 }, |
| 24210 | // AArch64::LD1D_IMM - 247 |
| 24211 | {.AsmStrOffset: 3746, .AliasCondStart: 1452, .NumOperands: 4, .NumConds: 8 }, |
| 24212 | // AArch64::LD1D_Q_IMM - 248 |
| 24213 | {.AsmStrOffset: 3770, .AliasCondStart: 1460, .NumOperands: 4, .NumConds: 7 }, |
| 24214 | // AArch64::LD1Fourv16b_POST - 249 |
| 24215 | {.AsmStrOffset: 3794, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 7 }, |
| 24216 | // AArch64::LD1Fourv1d_POST - 250 |
| 24217 | {.AsmStrOffset: 3814, .AliasCondStart: 1474, .NumOperands: 4, .NumConds: 7 }, |
| 24218 | // AArch64::LD1Fourv2d_POST - 251 |
| 24219 | {.AsmStrOffset: 3834, .AliasCondStart: 1481, .NumOperands: 4, .NumConds: 7 }, |
| 24220 | // AArch64::LD1Fourv2s_POST - 252 |
| 24221 | {.AsmStrOffset: 3854, .AliasCondStart: 1488, .NumOperands: 4, .NumConds: 7 }, |
| 24222 | // AArch64::LD1Fourv4h_POST - 253 |
| 24223 | {.AsmStrOffset: 3874, .AliasCondStart: 1495, .NumOperands: 4, .NumConds: 7 }, |
| 24224 | // AArch64::LD1Fourv4s_POST - 254 |
| 24225 | {.AsmStrOffset: 3894, .AliasCondStart: 1502, .NumOperands: 4, .NumConds: 7 }, |
| 24226 | // AArch64::LD1Fourv8b_POST - 255 |
| 24227 | {.AsmStrOffset: 3914, .AliasCondStart: 1509, .NumOperands: 4, .NumConds: 7 }, |
| 24228 | // AArch64::LD1Fourv8h_POST - 256 |
| 24229 | {.AsmStrOffset: 3934, .AliasCondStart: 1516, .NumOperands: 4, .NumConds: 7 }, |
| 24230 | // AArch64::LD1H_2Z_IMM - 257 |
| 24231 | {.AsmStrOffset: 3954, .AliasCondStart: 1523, .NumOperands: 4, .NumConds: 8 }, |
| 24232 | // AArch64::LD1H_2Z_STRIDED_IMM - 258 |
| 24233 | {.AsmStrOffset: 3978, .AliasCondStart: 1531, .NumOperands: 4, .NumConds: 7 }, |
| 24234 | // AArch64::LD1H_4Z_IMM - 259 |
| 24235 | {.AsmStrOffset: 3954, .AliasCondStart: 1538, .NumOperands: 4, .NumConds: 8 }, |
| 24236 | // AArch64::LD1H_4Z_STRIDED_IMM - 260 |
| 24237 | {.AsmStrOffset: 4002, .AliasCondStart: 1546, .NumOperands: 4, .NumConds: 7 }, |
| 24238 | // AArch64::LD1H_D_IMM - 261 |
| 24239 | {.AsmStrOffset: 4026, .AliasCondStart: 1553, .NumOperands: 4, .NumConds: 8 }, |
| 24240 | // AArch64::LD1H_IMM - 262 |
| 24241 | {.AsmStrOffset: 4050, .AliasCondStart: 1561, .NumOperands: 4, .NumConds: 8 }, |
| 24242 | // AArch64::LD1H_S_IMM - 263 |
| 24243 | {.AsmStrOffset: 4074, .AliasCondStart: 1569, .NumOperands: 4, .NumConds: 8 }, |
| 24244 | // AArch64::LD1Onev16b_POST - 264 |
| 24245 | {.AsmStrOffset: 4098, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 7 }, |
| 24246 | // AArch64::LD1Onev1d_POST - 265 |
| 24247 | {.AsmStrOffset: 4118, .AliasCondStart: 1584, .NumOperands: 4, .NumConds: 7 }, |
| 24248 | // AArch64::LD1Onev2d_POST - 266 |
| 24249 | {.AsmStrOffset: 4137, .AliasCondStart: 1591, .NumOperands: 4, .NumConds: 7 }, |
| 24250 | // AArch64::LD1Onev2s_POST - 267 |
| 24251 | {.AsmStrOffset: 4157, .AliasCondStart: 1598, .NumOperands: 4, .NumConds: 7 }, |
| 24252 | // AArch64::LD1Onev4h_POST - 268 |
| 24253 | {.AsmStrOffset: 4176, .AliasCondStart: 1605, .NumOperands: 4, .NumConds: 7 }, |
| 24254 | // AArch64::LD1Onev4s_POST - 269 |
| 24255 | {.AsmStrOffset: 4195, .AliasCondStart: 1612, .NumOperands: 4, .NumConds: 7 }, |
| 24256 | // AArch64::LD1Onev8b_POST - 270 |
| 24257 | {.AsmStrOffset: 4215, .AliasCondStart: 1619, .NumOperands: 4, .NumConds: 7 }, |
| 24258 | // AArch64::LD1Onev8h_POST - 271 |
| 24259 | {.AsmStrOffset: 4234, .AliasCondStart: 1626, .NumOperands: 4, .NumConds: 7 }, |
| 24260 | // AArch64::LD1RB_D_IMM - 272 |
| 24261 | {.AsmStrOffset: 4254, .AliasCondStart: 1633, .NumOperands: 4, .NumConds: 8 }, |
| 24262 | // AArch64::LD1RB_H_IMM - 273 |
| 24263 | {.AsmStrOffset: 4279, .AliasCondStart: 1641, .NumOperands: 4, .NumConds: 8 }, |
| 24264 | // AArch64::LD1RB_IMM - 274 |
| 24265 | {.AsmStrOffset: 4304, .AliasCondStart: 1649, .NumOperands: 4, .NumConds: 8 }, |
| 24266 | // AArch64::LD1RB_S_IMM - 275 |
| 24267 | {.AsmStrOffset: 4329, .AliasCondStart: 1657, .NumOperands: 4, .NumConds: 8 }, |
| 24268 | // AArch64::LD1RD_IMM - 276 |
| 24269 | {.AsmStrOffset: 4354, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 8 }, |
| 24270 | // AArch64::LD1RH_D_IMM - 277 |
| 24271 | {.AsmStrOffset: 4379, .AliasCondStart: 1673, .NumOperands: 4, .NumConds: 8 }, |
| 24272 | // AArch64::LD1RH_IMM - 278 |
| 24273 | {.AsmStrOffset: 4404, .AliasCondStart: 1681, .NumOperands: 4, .NumConds: 8 }, |
| 24274 | // AArch64::LD1RH_S_IMM - 279 |
| 24275 | {.AsmStrOffset: 4429, .AliasCondStart: 1689, .NumOperands: 4, .NumConds: 8 }, |
| 24276 | // AArch64::LD1RO_B_IMM - 280 |
| 24277 | {.AsmStrOffset: 4454, .AliasCondStart: 1697, .NumOperands: 4, .NumConds: 10 }, |
| 24278 | // AArch64::LD1RO_D_IMM - 281 |
| 24279 | {.AsmStrOffset: 4480, .AliasCondStart: 1707, .NumOperands: 4, .NumConds: 10 }, |
| 24280 | // AArch64::LD1RO_H_IMM - 282 |
| 24281 | {.AsmStrOffset: 4506, .AliasCondStart: 1717, .NumOperands: 4, .NumConds: 10 }, |
| 24282 | // AArch64::LD1RO_W_IMM - 283 |
| 24283 | {.AsmStrOffset: 4532, .AliasCondStart: 1727, .NumOperands: 4, .NumConds: 10 }, |
| 24284 | // AArch64::LD1RQ_B_IMM - 284 |
| 24285 | {.AsmStrOffset: 4558, .AliasCondStart: 1737, .NumOperands: 4, .NumConds: 8 }, |
| 24286 | // AArch64::LD1RQ_D_IMM - 285 |
| 24287 | {.AsmStrOffset: 4584, .AliasCondStart: 1745, .NumOperands: 4, .NumConds: 8 }, |
| 24288 | // AArch64::LD1RQ_H_IMM - 286 |
| 24289 | {.AsmStrOffset: 4610, .AliasCondStart: 1753, .NumOperands: 4, .NumConds: 8 }, |
| 24290 | // AArch64::LD1RQ_W_IMM - 287 |
| 24291 | {.AsmStrOffset: 4636, .AliasCondStart: 1761, .NumOperands: 4, .NumConds: 8 }, |
| 24292 | // AArch64::LD1RSB_D_IMM - 288 |
| 24293 | {.AsmStrOffset: 4662, .AliasCondStart: 1769, .NumOperands: 4, .NumConds: 8 }, |
| 24294 | // AArch64::LD1RSB_H_IMM - 289 |
| 24295 | {.AsmStrOffset: 4688, .AliasCondStart: 1777, .NumOperands: 4, .NumConds: 8 }, |
| 24296 | // AArch64::LD1RSB_S_IMM - 290 |
| 24297 | {.AsmStrOffset: 4714, .AliasCondStart: 1785, .NumOperands: 4, .NumConds: 8 }, |
| 24298 | // AArch64::LD1RSH_D_IMM - 291 |
| 24299 | {.AsmStrOffset: 4740, .AliasCondStart: 1793, .NumOperands: 4, .NumConds: 8 }, |
| 24300 | // AArch64::LD1RSH_S_IMM - 292 |
| 24301 | {.AsmStrOffset: 4766, .AliasCondStart: 1801, .NumOperands: 4, .NumConds: 8 }, |
| 24302 | // AArch64::LD1RSW_IMM - 293 |
| 24303 | {.AsmStrOffset: 4792, .AliasCondStart: 1809, .NumOperands: 4, .NumConds: 8 }, |
| 24304 | // AArch64::LD1RW_D_IMM - 294 |
| 24305 | {.AsmStrOffset: 4818, .AliasCondStart: 1817, .NumOperands: 4, .NumConds: 8 }, |
| 24306 | // AArch64::LD1RW_IMM - 295 |
| 24307 | {.AsmStrOffset: 4843, .AliasCondStart: 1825, .NumOperands: 4, .NumConds: 8 }, |
| 24308 | // AArch64::LD1Rv16b_POST - 296 |
| 24309 | {.AsmStrOffset: 4868, .AliasCondStart: 1833, .NumOperands: 4, .NumConds: 7 }, |
| 24310 | // AArch64::LD1Rv1d_POST - 297 |
| 24311 | {.AsmStrOffset: 4888, .AliasCondStart: 1840, .NumOperands: 4, .NumConds: 7 }, |
| 24312 | // AArch64::LD1Rv2d_POST - 298 |
| 24313 | {.AsmStrOffset: 4908, .AliasCondStart: 1847, .NumOperands: 4, .NumConds: 7 }, |
| 24314 | // AArch64::LD1Rv2s_POST - 299 |
| 24315 | {.AsmStrOffset: 4928, .AliasCondStart: 1854, .NumOperands: 4, .NumConds: 7 }, |
| 24316 | // AArch64::LD1Rv4h_POST - 300 |
| 24317 | {.AsmStrOffset: 4948, .AliasCondStart: 1861, .NumOperands: 4, .NumConds: 7 }, |
| 24318 | // AArch64::LD1Rv4s_POST - 301 |
| 24319 | {.AsmStrOffset: 4968, .AliasCondStart: 1868, .NumOperands: 4, .NumConds: 7 }, |
| 24320 | // AArch64::LD1Rv8b_POST - 302 |
| 24321 | {.AsmStrOffset: 4988, .AliasCondStart: 1875, .NumOperands: 4, .NumConds: 7 }, |
| 24322 | // AArch64::LD1Rv8h_POST - 303 |
| 24323 | {.AsmStrOffset: 5008, .AliasCondStart: 1882, .NumOperands: 4, .NumConds: 7 }, |
| 24324 | // AArch64::LD1SB_D_IMM - 304 |
| 24325 | {.AsmStrOffset: 5028, .AliasCondStart: 1889, .NumOperands: 4, .NumConds: 8 }, |
| 24326 | // AArch64::LD1SB_H_IMM - 305 |
| 24327 | {.AsmStrOffset: 5053, .AliasCondStart: 1897, .NumOperands: 4, .NumConds: 8 }, |
| 24328 | // AArch64::LD1SB_S_IMM - 306 |
| 24329 | {.AsmStrOffset: 5078, .AliasCondStart: 1905, .NumOperands: 4, .NumConds: 8 }, |
| 24330 | // AArch64::LD1SH_D_IMM - 307 |
| 24331 | {.AsmStrOffset: 5103, .AliasCondStart: 1913, .NumOperands: 4, .NumConds: 8 }, |
| 24332 | // AArch64::LD1SH_S_IMM - 308 |
| 24333 | {.AsmStrOffset: 5128, .AliasCondStart: 1921, .NumOperands: 4, .NumConds: 8 }, |
| 24334 | // AArch64::LD1SW_D_IMM - 309 |
| 24335 | {.AsmStrOffset: 5153, .AliasCondStart: 1929, .NumOperands: 4, .NumConds: 8 }, |
| 24336 | // AArch64::LD1Threev16b_POST - 310 |
| 24337 | {.AsmStrOffset: 5178, .AliasCondStart: 1937, .NumOperands: 4, .NumConds: 7 }, |
| 24338 | // AArch64::LD1Threev1d_POST - 311 |
| 24339 | {.AsmStrOffset: 5198, .AliasCondStart: 1944, .NumOperands: 4, .NumConds: 7 }, |
| 24340 | // AArch64::LD1Threev2d_POST - 312 |
| 24341 | {.AsmStrOffset: 5218, .AliasCondStart: 1951, .NumOperands: 4, .NumConds: 7 }, |
| 24342 | // AArch64::LD1Threev2s_POST - 313 |
| 24343 | {.AsmStrOffset: 5238, .AliasCondStart: 1958, .NumOperands: 4, .NumConds: 7 }, |
| 24344 | // AArch64::LD1Threev4h_POST - 314 |
| 24345 | {.AsmStrOffset: 5258, .AliasCondStart: 1965, .NumOperands: 4, .NumConds: 7 }, |
| 24346 | // AArch64::LD1Threev4s_POST - 315 |
| 24347 | {.AsmStrOffset: 5278, .AliasCondStart: 1972, .NumOperands: 4, .NumConds: 7 }, |
| 24348 | // AArch64::LD1Threev8b_POST - 316 |
| 24349 | {.AsmStrOffset: 5298, .AliasCondStart: 1979, .NumOperands: 4, .NumConds: 7 }, |
| 24350 | // AArch64::LD1Threev8h_POST - 317 |
| 24351 | {.AsmStrOffset: 5318, .AliasCondStart: 1986, .NumOperands: 4, .NumConds: 7 }, |
| 24352 | // AArch64::LD1Twov16b_POST - 318 |
| 24353 | {.AsmStrOffset: 5338, .AliasCondStart: 1993, .NumOperands: 4, .NumConds: 7 }, |
| 24354 | // AArch64::LD1Twov1d_POST - 319 |
| 24355 | {.AsmStrOffset: 5358, .AliasCondStart: 2000, .NumOperands: 4, .NumConds: 7 }, |
| 24356 | // AArch64::LD1Twov2d_POST - 320 |
| 24357 | {.AsmStrOffset: 5378, .AliasCondStart: 2007, .NumOperands: 4, .NumConds: 7 }, |
| 24358 | // AArch64::LD1Twov2s_POST - 321 |
| 24359 | {.AsmStrOffset: 5398, .AliasCondStart: 2014, .NumOperands: 4, .NumConds: 7 }, |
| 24360 | // AArch64::LD1Twov4h_POST - 322 |
| 24361 | {.AsmStrOffset: 5418, .AliasCondStart: 2021, .NumOperands: 4, .NumConds: 7 }, |
| 24362 | // AArch64::LD1Twov4s_POST - 323 |
| 24363 | {.AsmStrOffset: 5438, .AliasCondStart: 2028, .NumOperands: 4, .NumConds: 7 }, |
| 24364 | // AArch64::LD1Twov8b_POST - 324 |
| 24365 | {.AsmStrOffset: 5458, .AliasCondStart: 2035, .NumOperands: 4, .NumConds: 7 }, |
| 24366 | // AArch64::LD1Twov8h_POST - 325 |
| 24367 | {.AsmStrOffset: 5478, .AliasCondStart: 2042, .NumOperands: 4, .NumConds: 7 }, |
| 24368 | // AArch64::LD1W_2Z_IMM - 326 |
| 24369 | {.AsmStrOffset: 5498, .AliasCondStart: 2049, .NumOperands: 4, .NumConds: 8 }, |
| 24370 | // AArch64::LD1W_2Z_STRIDED_IMM - 327 |
| 24371 | {.AsmStrOffset: 5522, .AliasCondStart: 2057, .NumOperands: 4, .NumConds: 7 }, |
| 24372 | // AArch64::LD1W_4Z_IMM - 328 |
| 24373 | {.AsmStrOffset: 5498, .AliasCondStart: 2064, .NumOperands: 4, .NumConds: 8 }, |
| 24374 | // AArch64::LD1W_4Z_STRIDED_IMM - 329 |
| 24375 | {.AsmStrOffset: 5522, .AliasCondStart: 2072, .NumOperands: 4, .NumConds: 7 }, |
| 24376 | // AArch64::LD1W_D_IMM - 330 |
| 24377 | {.AsmStrOffset: 5546, .AliasCondStart: 2079, .NumOperands: 4, .NumConds: 8 }, |
| 24378 | // AArch64::LD1W_IMM - 331 |
| 24379 | {.AsmStrOffset: 5570, .AliasCondStart: 2087, .NumOperands: 4, .NumConds: 8 }, |
| 24380 | // AArch64::LD1W_Q_IMM - 332 |
| 24381 | {.AsmStrOffset: 5594, .AliasCondStart: 2095, .NumOperands: 4, .NumConds: 7 }, |
| 24382 | // AArch64::LD1_MXIPXX_H_B - 333 |
| 24383 | {.AsmStrOffset: 5618, .AliasCondStart: 2102, .NumOperands: 6, .NumConds: 9 }, |
| 24384 | // AArch64::LD1_MXIPXX_H_D - 334 |
| 24385 | {.AsmStrOffset: 5654, .AliasCondStart: 2111, .NumOperands: 6, .NumConds: 9 }, |
| 24386 | // AArch64::LD1_MXIPXX_H_H - 335 |
| 24387 | {.AsmStrOffset: 5690, .AliasCondStart: 2120, .NumOperands: 6, .NumConds: 9 }, |
| 24388 | // AArch64::LD1_MXIPXX_H_Q - 336 |
| 24389 | {.AsmStrOffset: 5726, .AliasCondStart: 2129, .NumOperands: 6, .NumConds: 9 }, |
| 24390 | // AArch64::LD1_MXIPXX_H_S - 337 |
| 24391 | {.AsmStrOffset: 5762, .AliasCondStart: 2138, .NumOperands: 6, .NumConds: 9 }, |
| 24392 | // AArch64::LD1_MXIPXX_V_B - 338 |
| 24393 | {.AsmStrOffset: 5798, .AliasCondStart: 2147, .NumOperands: 6, .NumConds: 9 }, |
| 24394 | // AArch64::LD1_MXIPXX_V_D - 339 |
| 24395 | {.AsmStrOffset: 5834, .AliasCondStart: 2156, .NumOperands: 6, .NumConds: 9 }, |
| 24396 | // AArch64::LD1_MXIPXX_V_H - 340 |
| 24397 | {.AsmStrOffset: 5870, .AliasCondStart: 2165, .NumOperands: 6, .NumConds: 9 }, |
| 24398 | // AArch64::LD1_MXIPXX_V_Q - 341 |
| 24399 | {.AsmStrOffset: 5906, .AliasCondStart: 2174, .NumOperands: 6, .NumConds: 9 }, |
| 24400 | // AArch64::LD1_MXIPXX_V_S - 342 |
| 24401 | {.AsmStrOffset: 5942, .AliasCondStart: 2183, .NumOperands: 6, .NumConds: 9 }, |
| 24402 | // AArch64::LD1i16_POST - 343 |
| 24403 | {.AsmStrOffset: 5978, .AliasCondStart: 2192, .NumOperands: 6, .NumConds: 9 }, |
| 24404 | // AArch64::LD1i32_POST - 344 |
| 24405 | {.AsmStrOffset: 6001, .AliasCondStart: 2201, .NumOperands: 6, .NumConds: 9 }, |
| 24406 | // AArch64::LD1i64_POST - 345 |
| 24407 | {.AsmStrOffset: 6024, .AliasCondStart: 2210, .NumOperands: 6, .NumConds: 9 }, |
| 24408 | // AArch64::LD1i8_POST - 346 |
| 24409 | {.AsmStrOffset: 6047, .AliasCondStart: 2219, .NumOperands: 6, .NumConds: 9 }, |
| 24410 | // AArch64::LD2B_IMM - 347 |
| 24411 | {.AsmStrOffset: 6070, .AliasCondStart: 2228, .NumOperands: 4, .NumConds: 8 }, |
| 24412 | // AArch64::LD2D_IMM - 348 |
| 24413 | {.AsmStrOffset: 6094, .AliasCondStart: 2236, .NumOperands: 4, .NumConds: 8 }, |
| 24414 | // AArch64::LD2H_IMM - 349 |
| 24415 | {.AsmStrOffset: 6118, .AliasCondStart: 2244, .NumOperands: 4, .NumConds: 8 }, |
| 24416 | // AArch64::LD2Q_IMM - 350 |
| 24417 | {.AsmStrOffset: 6142, .AliasCondStart: 2252, .NumOperands: 4, .NumConds: 8 }, |
| 24418 | // AArch64::LD2Rv16b_POST - 351 |
| 24419 | {.AsmStrOffset: 6166, .AliasCondStart: 2260, .NumOperands: 4, .NumConds: 7 }, |
| 24420 | // AArch64::LD2Rv1d_POST - 352 |
| 24421 | {.AsmStrOffset: 6186, .AliasCondStart: 2267, .NumOperands: 4, .NumConds: 7 }, |
| 24422 | // AArch64::LD2Rv2d_POST - 353 |
| 24423 | {.AsmStrOffset: 6207, .AliasCondStart: 2274, .NumOperands: 4, .NumConds: 7 }, |
| 24424 | // AArch64::LD2Rv2s_POST - 354 |
| 24425 | {.AsmStrOffset: 6228, .AliasCondStart: 2281, .NumOperands: 4, .NumConds: 7 }, |
| 24426 | // AArch64::LD2Rv4h_POST - 355 |
| 24427 | {.AsmStrOffset: 6248, .AliasCondStart: 2288, .NumOperands: 4, .NumConds: 7 }, |
| 24428 | // AArch64::LD2Rv4s_POST - 356 |
| 24429 | {.AsmStrOffset: 6268, .AliasCondStart: 2295, .NumOperands: 4, .NumConds: 7 }, |
| 24430 | // AArch64::LD2Rv8b_POST - 357 |
| 24431 | {.AsmStrOffset: 6288, .AliasCondStart: 2302, .NumOperands: 4, .NumConds: 7 }, |
| 24432 | // AArch64::LD2Rv8h_POST - 358 |
| 24433 | {.AsmStrOffset: 6308, .AliasCondStart: 2309, .NumOperands: 4, .NumConds: 7 }, |
| 24434 | // AArch64::LD2Twov16b_POST - 359 |
| 24435 | {.AsmStrOffset: 6328, .AliasCondStart: 2316, .NumOperands: 4, .NumConds: 7 }, |
| 24436 | // AArch64::LD2Twov2d_POST - 360 |
| 24437 | {.AsmStrOffset: 6348, .AliasCondStart: 2323, .NumOperands: 4, .NumConds: 7 }, |
| 24438 | // AArch64::LD2Twov2s_POST - 361 |
| 24439 | {.AsmStrOffset: 6368, .AliasCondStart: 2330, .NumOperands: 4, .NumConds: 7 }, |
| 24440 | // AArch64::LD2Twov4h_POST - 362 |
| 24441 | {.AsmStrOffset: 6388, .AliasCondStart: 2337, .NumOperands: 4, .NumConds: 7 }, |
| 24442 | // AArch64::LD2Twov4s_POST - 363 |
| 24443 | {.AsmStrOffset: 6408, .AliasCondStart: 2344, .NumOperands: 4, .NumConds: 7 }, |
| 24444 | // AArch64::LD2Twov8b_POST - 364 |
| 24445 | {.AsmStrOffset: 6428, .AliasCondStart: 2351, .NumOperands: 4, .NumConds: 7 }, |
| 24446 | // AArch64::LD2Twov8h_POST - 365 |
| 24447 | {.AsmStrOffset: 6448, .AliasCondStart: 2358, .NumOperands: 4, .NumConds: 7 }, |
| 24448 | // AArch64::LD2W_IMM - 366 |
| 24449 | {.AsmStrOffset: 6468, .AliasCondStart: 2365, .NumOperands: 4, .NumConds: 8 }, |
| 24450 | // AArch64::LD2i16_POST - 367 |
| 24451 | {.AsmStrOffset: 6492, .AliasCondStart: 2373, .NumOperands: 6, .NumConds: 9 }, |
| 24452 | // AArch64::LD2i32_POST - 368 |
| 24453 | {.AsmStrOffset: 6515, .AliasCondStart: 2382, .NumOperands: 6, .NumConds: 9 }, |
| 24454 | // AArch64::LD2i64_POST - 369 |
| 24455 | {.AsmStrOffset: 6538, .AliasCondStart: 2391, .NumOperands: 6, .NumConds: 9 }, |
| 24456 | // AArch64::LD2i8_POST - 370 |
| 24457 | {.AsmStrOffset: 6562, .AliasCondStart: 2400, .NumOperands: 6, .NumConds: 9 }, |
| 24458 | // AArch64::LD3B_IMM - 371 |
| 24459 | {.AsmStrOffset: 6585, .AliasCondStart: 2409, .NumOperands: 4, .NumConds: 8 }, |
| 24460 | // AArch64::LD3D_IMM - 372 |
| 24461 | {.AsmStrOffset: 6609, .AliasCondStart: 2417, .NumOperands: 4, .NumConds: 8 }, |
| 24462 | // AArch64::LD3H_IMM - 373 |
| 24463 | {.AsmStrOffset: 6633, .AliasCondStart: 2425, .NumOperands: 4, .NumConds: 8 }, |
| 24464 | // AArch64::LD3Q_IMM - 374 |
| 24465 | {.AsmStrOffset: 6657, .AliasCondStart: 2433, .NumOperands: 4, .NumConds: 8 }, |
| 24466 | // AArch64::LD3Rv16b_POST - 375 |
| 24467 | {.AsmStrOffset: 6681, .AliasCondStart: 2441, .NumOperands: 4, .NumConds: 7 }, |
| 24468 | // AArch64::LD3Rv1d_POST - 376 |
| 24469 | {.AsmStrOffset: 6701, .AliasCondStart: 2448, .NumOperands: 4, .NumConds: 7 }, |
| 24470 | // AArch64::LD3Rv2d_POST - 377 |
| 24471 | {.AsmStrOffset: 6722, .AliasCondStart: 2455, .NumOperands: 4, .NumConds: 7 }, |
| 24472 | // AArch64::LD3Rv2s_POST - 378 |
| 24473 | {.AsmStrOffset: 6743, .AliasCondStart: 2462, .NumOperands: 4, .NumConds: 7 }, |
| 24474 | // AArch64::LD3Rv4h_POST - 379 |
| 24475 | {.AsmStrOffset: 6764, .AliasCondStart: 2469, .NumOperands: 4, .NumConds: 7 }, |
| 24476 | // AArch64::LD3Rv4s_POST - 380 |
| 24477 | {.AsmStrOffset: 6784, .AliasCondStart: 2476, .NumOperands: 4, .NumConds: 7 }, |
| 24478 | // AArch64::LD3Rv8b_POST - 381 |
| 24479 | {.AsmStrOffset: 6805, .AliasCondStart: 2483, .NumOperands: 4, .NumConds: 7 }, |
| 24480 | // AArch64::LD3Rv8h_POST - 382 |
| 24481 | {.AsmStrOffset: 6825, .AliasCondStart: 2490, .NumOperands: 4, .NumConds: 7 }, |
| 24482 | // AArch64::LD3Threev16b_POST - 383 |
| 24483 | {.AsmStrOffset: 6845, .AliasCondStart: 2497, .NumOperands: 4, .NumConds: 7 }, |
| 24484 | // AArch64::LD3Threev2d_POST - 384 |
| 24485 | {.AsmStrOffset: 6865, .AliasCondStart: 2504, .NumOperands: 4, .NumConds: 7 }, |
| 24486 | // AArch64::LD3Threev2s_POST - 385 |
| 24487 | {.AsmStrOffset: 6885, .AliasCondStart: 2511, .NumOperands: 4, .NumConds: 7 }, |
| 24488 | // AArch64::LD3Threev4h_POST - 386 |
| 24489 | {.AsmStrOffset: 6905, .AliasCondStart: 2518, .NumOperands: 4, .NumConds: 7 }, |
| 24490 | // AArch64::LD3Threev4s_POST - 387 |
| 24491 | {.AsmStrOffset: 6925, .AliasCondStart: 2525, .NumOperands: 4, .NumConds: 7 }, |
| 24492 | // AArch64::LD3Threev8b_POST - 388 |
| 24493 | {.AsmStrOffset: 6945, .AliasCondStart: 2532, .NumOperands: 4, .NumConds: 7 }, |
| 24494 | // AArch64::LD3Threev8h_POST - 389 |
| 24495 | {.AsmStrOffset: 6965, .AliasCondStart: 2539, .NumOperands: 4, .NumConds: 7 }, |
| 24496 | // AArch64::LD3W_IMM - 390 |
| 24497 | {.AsmStrOffset: 6985, .AliasCondStart: 2546, .NumOperands: 4, .NumConds: 8 }, |
| 24498 | // AArch64::LD3i16_POST - 391 |
| 24499 | {.AsmStrOffset: 7009, .AliasCondStart: 2554, .NumOperands: 6, .NumConds: 9 }, |
| 24500 | // AArch64::LD3i32_POST - 392 |
| 24501 | {.AsmStrOffset: 7032, .AliasCondStart: 2563, .NumOperands: 6, .NumConds: 9 }, |
| 24502 | // AArch64::LD3i64_POST - 393 |
| 24503 | {.AsmStrOffset: 7056, .AliasCondStart: 2572, .NumOperands: 6, .NumConds: 9 }, |
| 24504 | // AArch64::LD3i8_POST - 394 |
| 24505 | {.AsmStrOffset: 7080, .AliasCondStart: 2581, .NumOperands: 6, .NumConds: 9 }, |
| 24506 | // AArch64::LD4B_IMM - 395 |
| 24507 | {.AsmStrOffset: 7103, .AliasCondStart: 2590, .NumOperands: 4, .NumConds: 8 }, |
| 24508 | // AArch64::LD4D_IMM - 396 |
| 24509 | {.AsmStrOffset: 7127, .AliasCondStart: 2598, .NumOperands: 4, .NumConds: 8 }, |
| 24510 | // AArch64::LD4Fourv16b_POST - 397 |
| 24511 | {.AsmStrOffset: 7151, .AliasCondStart: 2606, .NumOperands: 4, .NumConds: 7 }, |
| 24512 | // AArch64::LD4Fourv2d_POST - 398 |
| 24513 | {.AsmStrOffset: 7171, .AliasCondStart: 2613, .NumOperands: 4, .NumConds: 7 }, |
| 24514 | // AArch64::LD4Fourv2s_POST - 399 |
| 24515 | {.AsmStrOffset: 7191, .AliasCondStart: 2620, .NumOperands: 4, .NumConds: 7 }, |
| 24516 | // AArch64::LD4Fourv4h_POST - 400 |
| 24517 | {.AsmStrOffset: 7211, .AliasCondStart: 2627, .NumOperands: 4, .NumConds: 7 }, |
| 24518 | // AArch64::LD4Fourv4s_POST - 401 |
| 24519 | {.AsmStrOffset: 7231, .AliasCondStart: 2634, .NumOperands: 4, .NumConds: 7 }, |
| 24520 | // AArch64::LD4Fourv8b_POST - 402 |
| 24521 | {.AsmStrOffset: 7251, .AliasCondStart: 2641, .NumOperands: 4, .NumConds: 7 }, |
| 24522 | // AArch64::LD4Fourv8h_POST - 403 |
| 24523 | {.AsmStrOffset: 7271, .AliasCondStart: 2648, .NumOperands: 4, .NumConds: 7 }, |
| 24524 | // AArch64::LD4H_IMM - 404 |
| 24525 | {.AsmStrOffset: 7291, .AliasCondStart: 2655, .NumOperands: 4, .NumConds: 8 }, |
| 24526 | // AArch64::LD4Q_IMM - 405 |
| 24527 | {.AsmStrOffset: 7315, .AliasCondStart: 2663, .NumOperands: 4, .NumConds: 8 }, |
| 24528 | // AArch64::LD4Rv16b_POST - 406 |
| 24529 | {.AsmStrOffset: 7339, .AliasCondStart: 2671, .NumOperands: 4, .NumConds: 7 }, |
| 24530 | // AArch64::LD4Rv1d_POST - 407 |
| 24531 | {.AsmStrOffset: 7359, .AliasCondStart: 2678, .NumOperands: 4, .NumConds: 7 }, |
| 24532 | // AArch64::LD4Rv2d_POST - 408 |
| 24533 | {.AsmStrOffset: 7380, .AliasCondStart: 2685, .NumOperands: 4, .NumConds: 7 }, |
| 24534 | // AArch64::LD4Rv2s_POST - 409 |
| 24535 | {.AsmStrOffset: 7401, .AliasCondStart: 2692, .NumOperands: 4, .NumConds: 7 }, |
| 24536 | // AArch64::LD4Rv4h_POST - 410 |
| 24537 | {.AsmStrOffset: 7422, .AliasCondStart: 2699, .NumOperands: 4, .NumConds: 7 }, |
| 24538 | // AArch64::LD4Rv4s_POST - 411 |
| 24539 | {.AsmStrOffset: 7442, .AliasCondStart: 2706, .NumOperands: 4, .NumConds: 7 }, |
| 24540 | // AArch64::LD4Rv8b_POST - 412 |
| 24541 | {.AsmStrOffset: 7463, .AliasCondStart: 2713, .NumOperands: 4, .NumConds: 7 }, |
| 24542 | // AArch64::LD4Rv8h_POST - 413 |
| 24543 | {.AsmStrOffset: 7483, .AliasCondStart: 2720, .NumOperands: 4, .NumConds: 7 }, |
| 24544 | // AArch64::LD4W_IMM - 414 |
| 24545 | {.AsmStrOffset: 7503, .AliasCondStart: 2727, .NumOperands: 4, .NumConds: 8 }, |
| 24546 | // AArch64::LD4i16_POST - 415 |
| 24547 | {.AsmStrOffset: 7527, .AliasCondStart: 2735, .NumOperands: 6, .NumConds: 9 }, |
| 24548 | // AArch64::LD4i32_POST - 416 |
| 24549 | {.AsmStrOffset: 7550, .AliasCondStart: 2744, .NumOperands: 6, .NumConds: 9 }, |
| 24550 | // AArch64::LD4i64_POST - 417 |
| 24551 | {.AsmStrOffset: 7574, .AliasCondStart: 2753, .NumOperands: 6, .NumConds: 9 }, |
| 24552 | // AArch64::LD4i8_POST - 418 |
| 24553 | {.AsmStrOffset: 7598, .AliasCondStart: 2762, .NumOperands: 6, .NumConds: 9 }, |
| 24554 | // AArch64::LDADDB - 419 |
| 24555 | {.AsmStrOffset: 7621, .AliasCondStart: 2771, .NumOperands: 3, .NumConds: 6 }, |
| 24556 | // AArch64::LDADDH - 420 |
| 24557 | {.AsmStrOffset: 7637, .AliasCondStart: 2777, .NumOperands: 3, .NumConds: 6 }, |
| 24558 | // AArch64::LDADDLB - 421 |
| 24559 | {.AsmStrOffset: 7653, .AliasCondStart: 2783, .NumOperands: 3, .NumConds: 6 }, |
| 24560 | // AArch64::LDADDLH - 422 |
| 24561 | {.AsmStrOffset: 7670, .AliasCondStart: 2789, .NumOperands: 3, .NumConds: 6 }, |
| 24562 | // AArch64::LDADDLW - 423 |
| 24563 | {.AsmStrOffset: 7687, .AliasCondStart: 2795, .NumOperands: 3, .NumConds: 6 }, |
| 24564 | // AArch64::LDADDLX - 424 |
| 24565 | {.AsmStrOffset: 7687, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 6 }, |
| 24566 | // AArch64::LDADDW - 425 |
| 24567 | {.AsmStrOffset: 7703, .AliasCondStart: 2807, .NumOperands: 3, .NumConds: 6 }, |
| 24568 | // AArch64::LDADDX - 426 |
| 24569 | {.AsmStrOffset: 7703, .AliasCondStart: 2813, .NumOperands: 3, .NumConds: 6 }, |
| 24570 | // AArch64::LDAPURBi - 427 |
| 24571 | {.AsmStrOffset: 7718, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 6 }, |
| 24572 | // AArch64::LDAPURHi - 428 |
| 24573 | {.AsmStrOffset: 7735, .AliasCondStart: 2825, .NumOperands: 3, .NumConds: 6 }, |
| 24574 | // AArch64::LDAPURSBWi - 429 |
| 24575 | {.AsmStrOffset: 7752, .AliasCondStart: 2831, .NumOperands: 3, .NumConds: 6 }, |
| 24576 | // AArch64::LDAPURSBXi - 430 |
| 24577 | {.AsmStrOffset: 7752, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 6 }, |
| 24578 | // AArch64::LDAPURSHWi - 431 |
| 24579 | {.AsmStrOffset: 7770, .AliasCondStart: 2843, .NumOperands: 3, .NumConds: 6 }, |
| 24580 | // AArch64::LDAPURSHXi - 432 |
| 24581 | {.AsmStrOffset: 7770, .AliasCondStart: 2849, .NumOperands: 3, .NumConds: 6 }, |
| 24582 | // AArch64::LDAPURSWi - 433 |
| 24583 | {.AsmStrOffset: 7788, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 6 }, |
| 24584 | // AArch64::LDAPURXi - 434 |
| 24585 | {.AsmStrOffset: 7806, .AliasCondStart: 2861, .NumOperands: 3, .NumConds: 6 }, |
| 24586 | // AArch64::LDAPURbi - 435 |
| 24587 | {.AsmStrOffset: 7806, .AliasCondStart: 2867, .NumOperands: 3, .NumConds: 9 }, |
| 24588 | // AArch64::LDAPURdi - 436 |
| 24589 | {.AsmStrOffset: 7806, .AliasCondStart: 2876, .NumOperands: 3, .NumConds: 9 }, |
| 24590 | // AArch64::LDAPURhi - 437 |
| 24591 | {.AsmStrOffset: 7806, .AliasCondStart: 2885, .NumOperands: 3, .NumConds: 9 }, |
| 24592 | // AArch64::LDAPURi - 438 |
| 24593 | {.AsmStrOffset: 7806, .AliasCondStart: 2894, .NumOperands: 3, .NumConds: 6 }, |
| 24594 | // AArch64::LDAPURqi - 439 |
| 24595 | {.AsmStrOffset: 7806, .AliasCondStart: 2900, .NumOperands: 3, .NumConds: 9 }, |
| 24596 | // AArch64::LDAPURsi - 440 |
| 24597 | {.AsmStrOffset: 7806, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 9 }, |
| 24598 | // AArch64::LDCLRB - 441 |
| 24599 | {.AsmStrOffset: 7822, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 6 }, |
| 24600 | // AArch64::LDCLRH - 442 |
| 24601 | {.AsmStrOffset: 7838, .AliasCondStart: 2924, .NumOperands: 3, .NumConds: 6 }, |
| 24602 | // AArch64::LDCLRLB - 443 |
| 24603 | {.AsmStrOffset: 7854, .AliasCondStart: 2930, .NumOperands: 3, .NumConds: 6 }, |
| 24604 | // AArch64::LDCLRLH - 444 |
| 24605 | {.AsmStrOffset: 7871, .AliasCondStart: 2936, .NumOperands: 3, .NumConds: 6 }, |
| 24606 | // AArch64::LDCLRLW - 445 |
| 24607 | {.AsmStrOffset: 7888, .AliasCondStart: 2942, .NumOperands: 3, .NumConds: 6 }, |
| 24608 | // AArch64::LDCLRLX - 446 |
| 24609 | {.AsmStrOffset: 7888, .AliasCondStart: 2948, .NumOperands: 3, .NumConds: 6 }, |
| 24610 | // AArch64::LDCLRW - 447 |
| 24611 | {.AsmStrOffset: 7904, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 6 }, |
| 24612 | // AArch64::LDCLRX - 448 |
| 24613 | {.AsmStrOffset: 7904, .AliasCondStart: 2960, .NumOperands: 3, .NumConds: 6 }, |
| 24614 | // AArch64::LDEORB - 449 |
| 24615 | {.AsmStrOffset: 7919, .AliasCondStart: 2966, .NumOperands: 3, .NumConds: 6 }, |
| 24616 | // AArch64::LDEORH - 450 |
| 24617 | {.AsmStrOffset: 7935, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 6 }, |
| 24618 | // AArch64::LDEORLB - 451 |
| 24619 | {.AsmStrOffset: 7951, .AliasCondStart: 2978, .NumOperands: 3, .NumConds: 6 }, |
| 24620 | // AArch64::LDEORLH - 452 |
| 24621 | {.AsmStrOffset: 7968, .AliasCondStart: 2984, .NumOperands: 3, .NumConds: 6 }, |
| 24622 | // AArch64::LDEORLW - 453 |
| 24623 | {.AsmStrOffset: 7985, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 6 }, |
| 24624 | // AArch64::LDEORLX - 454 |
| 24625 | {.AsmStrOffset: 7985, .AliasCondStart: 2996, .NumOperands: 3, .NumConds: 6 }, |
| 24626 | // AArch64::LDEORW - 455 |
| 24627 | {.AsmStrOffset: 8001, .AliasCondStart: 3002, .NumOperands: 3, .NumConds: 6 }, |
| 24628 | // AArch64::LDEORX - 456 |
| 24629 | {.AsmStrOffset: 8001, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 6 }, |
| 24630 | // AArch64::LDFF1B - 457 |
| 24631 | {.AsmStrOffset: 8016, .AliasCondStart: 3014, .NumOperands: 4, .NumConds: 7 }, |
| 24632 | // AArch64::LDFF1B_D - 458 |
| 24633 | {.AsmStrOffset: 8042, .AliasCondStart: 3021, .NumOperands: 4, .NumConds: 7 }, |
| 24634 | // AArch64::LDFF1B_H - 459 |
| 24635 | {.AsmStrOffset: 8068, .AliasCondStart: 3028, .NumOperands: 4, .NumConds: 7 }, |
| 24636 | // AArch64::LDFF1B_S - 460 |
| 24637 | {.AsmStrOffset: 8094, .AliasCondStart: 3035, .NumOperands: 4, .NumConds: 7 }, |
| 24638 | // AArch64::LDFF1D - 461 |
| 24639 | {.AsmStrOffset: 8120, .AliasCondStart: 3042, .NumOperands: 4, .NumConds: 7 }, |
| 24640 | // AArch64::LDFF1H - 462 |
| 24641 | {.AsmStrOffset: 8146, .AliasCondStart: 3049, .NumOperands: 4, .NumConds: 7 }, |
| 24642 | // AArch64::LDFF1H_D - 463 |
| 24643 | {.AsmStrOffset: 8172, .AliasCondStart: 3056, .NumOperands: 4, .NumConds: 7 }, |
| 24644 | // AArch64::LDFF1H_S - 464 |
| 24645 | {.AsmStrOffset: 8198, .AliasCondStart: 3063, .NumOperands: 4, .NumConds: 7 }, |
| 24646 | // AArch64::LDFF1SB_D - 465 |
| 24647 | {.AsmStrOffset: 8224, .AliasCondStart: 3070, .NumOperands: 4, .NumConds: 7 }, |
| 24648 | // AArch64::LDFF1SB_H - 466 |
| 24649 | {.AsmStrOffset: 8251, .AliasCondStart: 3077, .NumOperands: 4, .NumConds: 7 }, |
| 24650 | // AArch64::LDFF1SB_S - 467 |
| 24651 | {.AsmStrOffset: 8278, .AliasCondStart: 3084, .NumOperands: 4, .NumConds: 7 }, |
| 24652 | // AArch64::LDFF1SH_D - 468 |
| 24653 | {.AsmStrOffset: 8305, .AliasCondStart: 3091, .NumOperands: 4, .NumConds: 7 }, |
| 24654 | // AArch64::LDFF1SH_S - 469 |
| 24655 | {.AsmStrOffset: 8332, .AliasCondStart: 3098, .NumOperands: 4, .NumConds: 7 }, |
| 24656 | // AArch64::LDFF1SW_D - 470 |
| 24657 | {.AsmStrOffset: 8359, .AliasCondStart: 3105, .NumOperands: 4, .NumConds: 7 }, |
| 24658 | // AArch64::LDFF1W - 471 |
| 24659 | {.AsmStrOffset: 8386, .AliasCondStart: 3112, .NumOperands: 4, .NumConds: 7 }, |
| 24660 | // AArch64::LDFF1W_D - 472 |
| 24661 | {.AsmStrOffset: 8412, .AliasCondStart: 3119, .NumOperands: 4, .NumConds: 7 }, |
| 24662 | // AArch64::LDG - 473 |
| 24663 | {.AsmStrOffset: 8438, .AliasCondStart: 3126, .NumOperands: 4, .NumConds: 7 }, |
| 24664 | // AArch64::LDNF1B_D_IMM - 474 |
| 24665 | {.AsmStrOffset: 8451, .AliasCondStart: 3133, .NumOperands: 4, .NumConds: 7 }, |
| 24666 | // AArch64::LDNF1B_H_IMM - 475 |
| 24667 | {.AsmStrOffset: 8477, .AliasCondStart: 3140, .NumOperands: 4, .NumConds: 7 }, |
| 24668 | // AArch64::LDNF1B_IMM - 476 |
| 24669 | {.AsmStrOffset: 8503, .AliasCondStart: 3147, .NumOperands: 4, .NumConds: 7 }, |
| 24670 | // AArch64::LDNF1B_S_IMM - 477 |
| 24671 | {.AsmStrOffset: 8529, .AliasCondStart: 3154, .NumOperands: 4, .NumConds: 7 }, |
| 24672 | // AArch64::LDNF1D_IMM - 478 |
| 24673 | {.AsmStrOffset: 8555, .AliasCondStart: 3161, .NumOperands: 4, .NumConds: 7 }, |
| 24674 | // AArch64::LDNF1H_D_IMM - 479 |
| 24675 | {.AsmStrOffset: 8581, .AliasCondStart: 3168, .NumOperands: 4, .NumConds: 7 }, |
| 24676 | // AArch64::LDNF1H_IMM - 480 |
| 24677 | {.AsmStrOffset: 8607, .AliasCondStart: 3175, .NumOperands: 4, .NumConds: 7 }, |
| 24678 | // AArch64::LDNF1H_S_IMM - 481 |
| 24679 | {.AsmStrOffset: 8633, .AliasCondStart: 3182, .NumOperands: 4, .NumConds: 7 }, |
| 24680 | // AArch64::LDNF1SB_D_IMM - 482 |
| 24681 | {.AsmStrOffset: 8659, .AliasCondStart: 3189, .NumOperands: 4, .NumConds: 7 }, |
| 24682 | // AArch64::LDNF1SB_H_IMM - 483 |
| 24683 | {.AsmStrOffset: 8686, .AliasCondStart: 3196, .NumOperands: 4, .NumConds: 7 }, |
| 24684 | // AArch64::LDNF1SB_S_IMM - 484 |
| 24685 | {.AsmStrOffset: 8713, .AliasCondStart: 3203, .NumOperands: 4, .NumConds: 7 }, |
| 24686 | // AArch64::LDNF1SH_D_IMM - 485 |
| 24687 | {.AsmStrOffset: 8740, .AliasCondStart: 3210, .NumOperands: 4, .NumConds: 7 }, |
| 24688 | // AArch64::LDNF1SH_S_IMM - 486 |
| 24689 | {.AsmStrOffset: 8767, .AliasCondStart: 3217, .NumOperands: 4, .NumConds: 7 }, |
| 24690 | // AArch64::LDNF1SW_D_IMM - 487 |
| 24691 | {.AsmStrOffset: 8794, .AliasCondStart: 3224, .NumOperands: 4, .NumConds: 7 }, |
| 24692 | // AArch64::LDNF1W_D_IMM - 488 |
| 24693 | {.AsmStrOffset: 8821, .AliasCondStart: 3231, .NumOperands: 4, .NumConds: 7 }, |
| 24694 | // AArch64::LDNF1W_IMM - 489 |
| 24695 | {.AsmStrOffset: 8847, .AliasCondStart: 3238, .NumOperands: 4, .NumConds: 7 }, |
| 24696 | // AArch64::LDNPDi - 490 |
| 24697 | {.AsmStrOffset: 8873, .AliasCondStart: 3245, .NumOperands: 4, .NumConds: 7 }, |
| 24698 | // AArch64::LDNPQi - 491 |
| 24699 | {.AsmStrOffset: 8873, .AliasCondStart: 3252, .NumOperands: 4, .NumConds: 7 }, |
| 24700 | // AArch64::LDNPSi - 492 |
| 24701 | {.AsmStrOffset: 8873, .AliasCondStart: 3259, .NumOperands: 4, .NumConds: 7 }, |
| 24702 | // AArch64::LDNPWi - 493 |
| 24703 | {.AsmStrOffset: 8873, .AliasCondStart: 3266, .NumOperands: 4, .NumConds: 4 }, |
| 24704 | // AArch64::LDNPXi - 494 |
| 24705 | {.AsmStrOffset: 8873, .AliasCondStart: 3270, .NumOperands: 4, .NumConds: 4 }, |
| 24706 | // AArch64::LDNT1B_2Z_IMM - 495 |
| 24707 | {.AsmStrOffset: 8891, .AliasCondStart: 3274, .NumOperands: 4, .NumConds: 8 }, |
| 24708 | // AArch64::LDNT1B_2Z_STRIDED_IMM - 496 |
| 24709 | {.AsmStrOffset: 8917, .AliasCondStart: 3282, .NumOperands: 4, .NumConds: 7 }, |
| 24710 | // AArch64::LDNT1B_4Z_IMM - 497 |
| 24711 | {.AsmStrOffset: 8891, .AliasCondStart: 3289, .NumOperands: 4, .NumConds: 8 }, |
| 24712 | // AArch64::LDNT1B_4Z_STRIDED_IMM - 498 |
| 24713 | {.AsmStrOffset: 8943, .AliasCondStart: 3297, .NumOperands: 4, .NumConds: 7 }, |
| 24714 | // AArch64::LDNT1B_ZRI - 499 |
| 24715 | {.AsmStrOffset: 8969, .AliasCondStart: 3304, .NumOperands: 4, .NumConds: 8 }, |
| 24716 | // AArch64::LDNT1B_ZZR_D - 500 |
| 24717 | {.AsmStrOffset: 8995, .AliasCondStart: 3312, .NumOperands: 4, .NumConds: 7 }, |
| 24718 | // AArch64::LDNT1B_ZZR_S - 501 |
| 24719 | {.AsmStrOffset: 9023, .AliasCondStart: 3319, .NumOperands: 4, .NumConds: 7 }, |
| 24720 | // AArch64::LDNT1D_2Z_IMM - 502 |
| 24721 | {.AsmStrOffset: 9051, .AliasCondStart: 3326, .NumOperands: 4, .NumConds: 8 }, |
| 24722 | // AArch64::LDNT1D_2Z_STRIDED_IMM - 503 |
| 24723 | {.AsmStrOffset: 9077, .AliasCondStart: 3334, .NumOperands: 4, .NumConds: 7 }, |
| 24724 | // AArch64::LDNT1D_4Z_IMM - 504 |
| 24725 | {.AsmStrOffset: 9051, .AliasCondStart: 3341, .NumOperands: 4, .NumConds: 8 }, |
| 24726 | // AArch64::LDNT1D_4Z_STRIDED_IMM - 505 |
| 24727 | {.AsmStrOffset: 9077, .AliasCondStart: 3349, .NumOperands: 4, .NumConds: 7 }, |
| 24728 | // AArch64::LDNT1D_ZRI - 506 |
| 24729 | {.AsmStrOffset: 9103, .AliasCondStart: 3356, .NumOperands: 4, .NumConds: 8 }, |
| 24730 | // AArch64::LDNT1D_ZZR_D - 507 |
| 24731 | {.AsmStrOffset: 9129, .AliasCondStart: 3364, .NumOperands: 4, .NumConds: 7 }, |
| 24732 | // AArch64::LDNT1H_2Z_IMM - 508 |
| 24733 | {.AsmStrOffset: 9157, .AliasCondStart: 3371, .NumOperands: 4, .NumConds: 8 }, |
| 24734 | // AArch64::LDNT1H_2Z_STRIDED_IMM - 509 |
| 24735 | {.AsmStrOffset: 9183, .AliasCondStart: 3379, .NumOperands: 4, .NumConds: 7 }, |
| 24736 | // AArch64::LDNT1H_4Z_IMM - 510 |
| 24737 | {.AsmStrOffset: 9157, .AliasCondStart: 3386, .NumOperands: 4, .NumConds: 8 }, |
| 24738 | // AArch64::LDNT1H_4Z_STRIDED_IMM - 511 |
| 24739 | {.AsmStrOffset: 9209, .AliasCondStart: 3394, .NumOperands: 4, .NumConds: 7 }, |
| 24740 | // AArch64::LDNT1H_ZRI - 512 |
| 24741 | {.AsmStrOffset: 9235, .AliasCondStart: 3401, .NumOperands: 4, .NumConds: 8 }, |
| 24742 | // AArch64::LDNT1H_ZZR_D - 513 |
| 24743 | {.AsmStrOffset: 9261, .AliasCondStart: 3409, .NumOperands: 4, .NumConds: 7 }, |
| 24744 | // AArch64::LDNT1H_ZZR_S - 514 |
| 24745 | {.AsmStrOffset: 9289, .AliasCondStart: 3416, .NumOperands: 4, .NumConds: 7 }, |
| 24746 | // AArch64::LDNT1SB_ZZR_D - 515 |
| 24747 | {.AsmStrOffset: 9317, .AliasCondStart: 3423, .NumOperands: 4, .NumConds: 7 }, |
| 24748 | // AArch64::LDNT1SB_ZZR_S - 516 |
| 24749 | {.AsmStrOffset: 9346, .AliasCondStart: 3430, .NumOperands: 4, .NumConds: 7 }, |
| 24750 | // AArch64::LDNT1SH_ZZR_D - 517 |
| 24751 | {.AsmStrOffset: 9375, .AliasCondStart: 3437, .NumOperands: 4, .NumConds: 7 }, |
| 24752 | // AArch64::LDNT1SH_ZZR_S - 518 |
| 24753 | {.AsmStrOffset: 9404, .AliasCondStart: 3444, .NumOperands: 4, .NumConds: 7 }, |
| 24754 | // AArch64::LDNT1SW_ZZR_D - 519 |
| 24755 | {.AsmStrOffset: 9433, .AliasCondStart: 3451, .NumOperands: 4, .NumConds: 7 }, |
| 24756 | // AArch64::LDNT1W_2Z_IMM - 520 |
| 24757 | {.AsmStrOffset: 9462, .AliasCondStart: 3458, .NumOperands: 4, .NumConds: 8 }, |
| 24758 | // AArch64::LDNT1W_2Z_STRIDED_IMM - 521 |
| 24759 | {.AsmStrOffset: 9488, .AliasCondStart: 3466, .NumOperands: 4, .NumConds: 7 }, |
| 24760 | // AArch64::LDNT1W_4Z_IMM - 522 |
| 24761 | {.AsmStrOffset: 9462, .AliasCondStart: 3473, .NumOperands: 4, .NumConds: 8 }, |
| 24762 | // AArch64::LDNT1W_4Z_STRIDED_IMM - 523 |
| 24763 | {.AsmStrOffset: 9488, .AliasCondStart: 3481, .NumOperands: 4, .NumConds: 7 }, |
| 24764 | // AArch64::LDNT1W_ZRI - 524 |
| 24765 | {.AsmStrOffset: 9514, .AliasCondStart: 3488, .NumOperands: 4, .NumConds: 8 }, |
| 24766 | // AArch64::LDNT1W_ZZR_D - 525 |
| 24767 | {.AsmStrOffset: 9540, .AliasCondStart: 3496, .NumOperands: 4, .NumConds: 7 }, |
| 24768 | // AArch64::LDNT1W_ZZR_S - 526 |
| 24769 | {.AsmStrOffset: 9568, .AliasCondStart: 3503, .NumOperands: 4, .NumConds: 7 }, |
| 24770 | // AArch64::LDPDi - 527 |
| 24771 | {.AsmStrOffset: 9596, .AliasCondStart: 3510, .NumOperands: 4, .NumConds: 7 }, |
| 24772 | // AArch64::LDPQi - 528 |
| 24773 | {.AsmStrOffset: 9596, .AliasCondStart: 3517, .NumOperands: 4, .NumConds: 7 }, |
| 24774 | // AArch64::LDPSWi - 529 |
| 24775 | {.AsmStrOffset: 9613, .AliasCondStart: 3524, .NumOperands: 4, .NumConds: 4 }, |
| 24776 | // AArch64::LDPSi - 530 |
| 24777 | {.AsmStrOffset: 9596, .AliasCondStart: 3528, .NumOperands: 4, .NumConds: 7 }, |
| 24778 | // AArch64::LDPWi - 531 |
| 24779 | {.AsmStrOffset: 9596, .AliasCondStart: 3535, .NumOperands: 4, .NumConds: 4 }, |
| 24780 | // AArch64::LDPXi - 532 |
| 24781 | {.AsmStrOffset: 9596, .AliasCondStart: 3539, .NumOperands: 4, .NumConds: 4 }, |
| 24782 | // AArch64::LDRAAindexed - 533 |
| 24783 | {.AsmStrOffset: 9632, .AliasCondStart: 3543, .NumOperands: 3, .NumConds: 6 }, |
| 24784 | // AArch64::LDRABindexed - 534 |
| 24785 | {.AsmStrOffset: 9647, .AliasCondStart: 3549, .NumOperands: 3, .NumConds: 6 }, |
| 24786 | // AArch64::LDRBBroX - 535 |
| 24787 | {.AsmStrOffset: 9662, .AliasCondStart: 3555, .NumOperands: 5, .NumConds: 5 }, |
| 24788 | // AArch64::LDRBBui - 536 |
| 24789 | {.AsmStrOffset: 9680, .AliasCondStart: 3560, .NumOperands: 3, .NumConds: 3 }, |
| 24790 | // AArch64::LDRBroX - 537 |
| 24791 | {.AsmStrOffset: 9694, .AliasCondStart: 3563, .NumOperands: 5, .NumConds: 8 }, |
| 24792 | // AArch64::LDRBui - 538 |
| 24793 | {.AsmStrOffset: 9711, .AliasCondStart: 3571, .NumOperands: 3, .NumConds: 6 }, |
| 24794 | // AArch64::LDRDroX - 539 |
| 24795 | {.AsmStrOffset: 9694, .AliasCondStart: 3577, .NumOperands: 5, .NumConds: 8 }, |
| 24796 | // AArch64::LDRDui - 540 |
| 24797 | {.AsmStrOffset: 9711, .AliasCondStart: 3585, .NumOperands: 3, .NumConds: 6 }, |
| 24798 | // AArch64::LDRHHroX - 541 |
| 24799 | {.AsmStrOffset: 9724, .AliasCondStart: 3591, .NumOperands: 5, .NumConds: 5 }, |
| 24800 | // AArch64::LDRHHui - 542 |
| 24801 | {.AsmStrOffset: 9742, .AliasCondStart: 3596, .NumOperands: 3, .NumConds: 3 }, |
| 24802 | // AArch64::LDRHroX - 543 |
| 24803 | {.AsmStrOffset: 9694, .AliasCondStart: 3599, .NumOperands: 5, .NumConds: 8 }, |
| 24804 | // AArch64::LDRHui - 544 |
| 24805 | {.AsmStrOffset: 9711, .AliasCondStart: 3607, .NumOperands: 3, .NumConds: 6 }, |
| 24806 | // AArch64::LDRQroX - 545 |
| 24807 | {.AsmStrOffset: 9694, .AliasCondStart: 3613, .NumOperands: 5, .NumConds: 8 }, |
| 24808 | // AArch64::LDRQui - 546 |
| 24809 | {.AsmStrOffset: 9711, .AliasCondStart: 3621, .NumOperands: 3, .NumConds: 6 }, |
| 24810 | // AArch64::LDRSBWroX - 547 |
| 24811 | {.AsmStrOffset: 9756, .AliasCondStart: 3627, .NumOperands: 5, .NumConds: 5 }, |
| 24812 | // AArch64::LDRSBWui - 548 |
| 24813 | {.AsmStrOffset: 9775, .AliasCondStart: 3632, .NumOperands: 3, .NumConds: 3 }, |
| 24814 | // AArch64::LDRSBXroX - 549 |
| 24815 | {.AsmStrOffset: 9756, .AliasCondStart: 3635, .NumOperands: 5, .NumConds: 5 }, |
| 24816 | // AArch64::LDRSBXui - 550 |
| 24817 | {.AsmStrOffset: 9775, .AliasCondStart: 3640, .NumOperands: 3, .NumConds: 3 }, |
| 24818 | // AArch64::LDRSHWroX - 551 |
| 24819 | {.AsmStrOffset: 9790, .AliasCondStart: 3643, .NumOperands: 5, .NumConds: 5 }, |
| 24820 | // AArch64::LDRSHWui - 552 |
| 24821 | {.AsmStrOffset: 9809, .AliasCondStart: 3648, .NumOperands: 3, .NumConds: 3 }, |
| 24822 | // AArch64::LDRSHXroX - 553 |
| 24823 | {.AsmStrOffset: 9790, .AliasCondStart: 3651, .NumOperands: 5, .NumConds: 5 }, |
| 24824 | // AArch64::LDRSHXui - 554 |
| 24825 | {.AsmStrOffset: 9809, .AliasCondStart: 3656, .NumOperands: 3, .NumConds: 3 }, |
| 24826 | // AArch64::LDRSWroX - 555 |
| 24827 | {.AsmStrOffset: 9824, .AliasCondStart: 3659, .NumOperands: 5, .NumConds: 5 }, |
| 24828 | // AArch64::LDRSWui - 556 |
| 24829 | {.AsmStrOffset: 9843, .AliasCondStart: 3664, .NumOperands: 3, .NumConds: 3 }, |
| 24830 | // AArch64::LDRSroX - 557 |
| 24831 | {.AsmStrOffset: 9694, .AliasCondStart: 3667, .NumOperands: 5, .NumConds: 8 }, |
| 24832 | // AArch64::LDRSui - 558 |
| 24833 | {.AsmStrOffset: 9711, .AliasCondStart: 3675, .NumOperands: 3, .NumConds: 6 }, |
| 24834 | // AArch64::LDRWroX - 559 |
| 24835 | {.AsmStrOffset: 9694, .AliasCondStart: 3681, .NumOperands: 5, .NumConds: 5 }, |
| 24836 | // AArch64::LDRWui - 560 |
| 24837 | {.AsmStrOffset: 9711, .AliasCondStart: 3686, .NumOperands: 3, .NumConds: 3 }, |
| 24838 | // AArch64::LDRXroX - 561 |
| 24839 | {.AsmStrOffset: 9694, .AliasCondStart: 3689, .NumOperands: 5, .NumConds: 5 }, |
| 24840 | // AArch64::LDRXui - 562 |
| 24841 | {.AsmStrOffset: 9711, .AliasCondStart: 3694, .NumOperands: 3, .NumConds: 3 }, |
| 24842 | // AArch64::LDR_PXI - 563 |
| 24843 | {.AsmStrOffset: 9858, .AliasCondStart: 3697, .NumOperands: 3, .NumConds: 7 }, |
| 24844 | // AArch64::LDR_ZA - 564 |
| 24845 | {.AsmStrOffset: 9873, .AliasCondStart: 3704, .NumOperands: 5, .NumConds: 8 }, |
| 24846 | // AArch64::LDR_ZXI - 565 |
| 24847 | {.AsmStrOffset: 9858, .AliasCondStart: 3712, .NumOperands: 3, .NumConds: 7 }, |
| 24848 | // AArch64::LDSETB - 566 |
| 24849 | {.AsmStrOffset: 9898, .AliasCondStart: 3719, .NumOperands: 3, .NumConds: 6 }, |
| 24850 | // AArch64::LDSETH - 567 |
| 24851 | {.AsmStrOffset: 9914, .AliasCondStart: 3725, .NumOperands: 3, .NumConds: 6 }, |
| 24852 | // AArch64::LDSETLB - 568 |
| 24853 | {.AsmStrOffset: 9930, .AliasCondStart: 3731, .NumOperands: 3, .NumConds: 6 }, |
| 24854 | // AArch64::LDSETLH - 569 |
| 24855 | {.AsmStrOffset: 9947, .AliasCondStart: 3737, .NumOperands: 3, .NumConds: 6 }, |
| 24856 | // AArch64::LDSETLW - 570 |
| 24857 | {.AsmStrOffset: 9964, .AliasCondStart: 3743, .NumOperands: 3, .NumConds: 6 }, |
| 24858 | // AArch64::LDSETLX - 571 |
| 24859 | {.AsmStrOffset: 9964, .AliasCondStart: 3749, .NumOperands: 3, .NumConds: 6 }, |
| 24860 | // AArch64::LDSETW - 572 |
| 24861 | {.AsmStrOffset: 9980, .AliasCondStart: 3755, .NumOperands: 3, .NumConds: 6 }, |
| 24862 | // AArch64::LDSETX - 573 |
| 24863 | {.AsmStrOffset: 9980, .AliasCondStart: 3761, .NumOperands: 3, .NumConds: 6 }, |
| 24864 | // AArch64::LDSMAXB - 574 |
| 24865 | {.AsmStrOffset: 9995, .AliasCondStart: 3767, .NumOperands: 3, .NumConds: 6 }, |
| 24866 | // AArch64::LDSMAXH - 575 |
| 24867 | {.AsmStrOffset: 10012, .AliasCondStart: 3773, .NumOperands: 3, .NumConds: 6 }, |
| 24868 | // AArch64::LDSMAXLB - 576 |
| 24869 | {.AsmStrOffset: 10029, .AliasCondStart: 3779, .NumOperands: 3, .NumConds: 6 }, |
| 24870 | // AArch64::LDSMAXLH - 577 |
| 24871 | {.AsmStrOffset: 10047, .AliasCondStart: 3785, .NumOperands: 3, .NumConds: 6 }, |
| 24872 | // AArch64::LDSMAXLW - 578 |
| 24873 | {.AsmStrOffset: 10065, .AliasCondStart: 3791, .NumOperands: 3, .NumConds: 6 }, |
| 24874 | // AArch64::LDSMAXLX - 579 |
| 24875 | {.AsmStrOffset: 10065, .AliasCondStart: 3797, .NumOperands: 3, .NumConds: 6 }, |
| 24876 | // AArch64::LDSMAXW - 580 |
| 24877 | {.AsmStrOffset: 10082, .AliasCondStart: 3803, .NumOperands: 3, .NumConds: 6 }, |
| 24878 | // AArch64::LDSMAXX - 581 |
| 24879 | {.AsmStrOffset: 10082, .AliasCondStart: 3809, .NumOperands: 3, .NumConds: 6 }, |
| 24880 | // AArch64::LDSMINB - 582 |
| 24881 | {.AsmStrOffset: 10098, .AliasCondStart: 3815, .NumOperands: 3, .NumConds: 6 }, |
| 24882 | // AArch64::LDSMINH - 583 |
| 24883 | {.AsmStrOffset: 10115, .AliasCondStart: 3821, .NumOperands: 3, .NumConds: 6 }, |
| 24884 | // AArch64::LDSMINLB - 584 |
| 24885 | {.AsmStrOffset: 10132, .AliasCondStart: 3827, .NumOperands: 3, .NumConds: 6 }, |
| 24886 | // AArch64::LDSMINLH - 585 |
| 24887 | {.AsmStrOffset: 10150, .AliasCondStart: 3833, .NumOperands: 3, .NumConds: 6 }, |
| 24888 | // AArch64::LDSMINLW - 586 |
| 24889 | {.AsmStrOffset: 10168, .AliasCondStart: 3839, .NumOperands: 3, .NumConds: 6 }, |
| 24890 | // AArch64::LDSMINLX - 587 |
| 24891 | {.AsmStrOffset: 10168, .AliasCondStart: 3845, .NumOperands: 3, .NumConds: 6 }, |
| 24892 | // AArch64::LDSMINW - 588 |
| 24893 | {.AsmStrOffset: 10185, .AliasCondStart: 3851, .NumOperands: 3, .NumConds: 6 }, |
| 24894 | // AArch64::LDSMINX - 589 |
| 24895 | {.AsmStrOffset: 10185, .AliasCondStart: 3857, .NumOperands: 3, .NumConds: 6 }, |
| 24896 | // AArch64::LDTRBi - 590 |
| 24897 | {.AsmStrOffset: 10201, .AliasCondStart: 3863, .NumOperands: 3, .NumConds: 3 }, |
| 24898 | // AArch64::LDTRHi - 591 |
| 24899 | {.AsmStrOffset: 10216, .AliasCondStart: 3866, .NumOperands: 3, .NumConds: 3 }, |
| 24900 | // AArch64::LDTRSBWi - 592 |
| 24901 | {.AsmStrOffset: 10231, .AliasCondStart: 3869, .NumOperands: 3, .NumConds: 3 }, |
| 24902 | // AArch64::LDTRSBXi - 593 |
| 24903 | {.AsmStrOffset: 10231, .AliasCondStart: 3872, .NumOperands: 3, .NumConds: 3 }, |
| 24904 | // AArch64::LDTRSHWi - 594 |
| 24905 | {.AsmStrOffset: 10247, .AliasCondStart: 3875, .NumOperands: 3, .NumConds: 3 }, |
| 24906 | // AArch64::LDTRSHXi - 595 |
| 24907 | {.AsmStrOffset: 10247, .AliasCondStart: 3878, .NumOperands: 3, .NumConds: 3 }, |
| 24908 | // AArch64::LDTRSWi - 596 |
| 24909 | {.AsmStrOffset: 10263, .AliasCondStart: 3881, .NumOperands: 3, .NumConds: 3 }, |
| 24910 | // AArch64::LDTRWi - 597 |
| 24911 | {.AsmStrOffset: 10279, .AliasCondStart: 3884, .NumOperands: 3, .NumConds: 3 }, |
| 24912 | // AArch64::LDTRXi - 598 |
| 24913 | {.AsmStrOffset: 10279, .AliasCondStart: 3887, .NumOperands: 3, .NumConds: 3 }, |
| 24914 | // AArch64::LDUMAXB - 599 |
| 24915 | {.AsmStrOffset: 10293, .AliasCondStart: 3890, .NumOperands: 3, .NumConds: 6 }, |
| 24916 | // AArch64::LDUMAXH - 600 |
| 24917 | {.AsmStrOffset: 10310, .AliasCondStart: 3896, .NumOperands: 3, .NumConds: 6 }, |
| 24918 | // AArch64::LDUMAXLB - 601 |
| 24919 | {.AsmStrOffset: 10327, .AliasCondStart: 3902, .NumOperands: 3, .NumConds: 6 }, |
| 24920 | // AArch64::LDUMAXLH - 602 |
| 24921 | {.AsmStrOffset: 10345, .AliasCondStart: 3908, .NumOperands: 3, .NumConds: 6 }, |
| 24922 | // AArch64::LDUMAXLW - 603 |
| 24923 | {.AsmStrOffset: 10363, .AliasCondStart: 3914, .NumOperands: 3, .NumConds: 6 }, |
| 24924 | // AArch64::LDUMAXLX - 604 |
| 24925 | {.AsmStrOffset: 10363, .AliasCondStart: 3920, .NumOperands: 3, .NumConds: 6 }, |
| 24926 | // AArch64::LDUMAXW - 605 |
| 24927 | {.AsmStrOffset: 10380, .AliasCondStart: 3926, .NumOperands: 3, .NumConds: 6 }, |
| 24928 | // AArch64::LDUMAXX - 606 |
| 24929 | {.AsmStrOffset: 10380, .AliasCondStart: 3932, .NumOperands: 3, .NumConds: 6 }, |
| 24930 | // AArch64::LDUMINB - 607 |
| 24931 | {.AsmStrOffset: 10396, .AliasCondStart: 3938, .NumOperands: 3, .NumConds: 6 }, |
| 24932 | // AArch64::LDUMINH - 608 |
| 24933 | {.AsmStrOffset: 10413, .AliasCondStart: 3944, .NumOperands: 3, .NumConds: 6 }, |
| 24934 | // AArch64::LDUMINLB - 609 |
| 24935 | {.AsmStrOffset: 10430, .AliasCondStart: 3950, .NumOperands: 3, .NumConds: 6 }, |
| 24936 | // AArch64::LDUMINLH - 610 |
| 24937 | {.AsmStrOffset: 10448, .AliasCondStart: 3956, .NumOperands: 3, .NumConds: 6 }, |
| 24938 | // AArch64::LDUMINLW - 611 |
| 24939 | {.AsmStrOffset: 10466, .AliasCondStart: 3962, .NumOperands: 3, .NumConds: 6 }, |
| 24940 | // AArch64::LDUMINLX - 612 |
| 24941 | {.AsmStrOffset: 10466, .AliasCondStart: 3968, .NumOperands: 3, .NumConds: 6 }, |
| 24942 | // AArch64::LDUMINW - 613 |
| 24943 | {.AsmStrOffset: 10483, .AliasCondStart: 3974, .NumOperands: 3, .NumConds: 6 }, |
| 24944 | // AArch64::LDUMINX - 614 |
| 24945 | {.AsmStrOffset: 10483, .AliasCondStart: 3980, .NumOperands: 3, .NumConds: 6 }, |
| 24946 | // AArch64::LDURBBi - 615 |
| 24947 | {.AsmStrOffset: 10499, .AliasCondStart: 3986, .NumOperands: 3, .NumConds: 3 }, |
| 24948 | // AArch64::LDURBi - 616 |
| 24949 | {.AsmStrOffset: 10514, .AliasCondStart: 3989, .NumOperands: 3, .NumConds: 6 }, |
| 24950 | // AArch64::LDURDi - 617 |
| 24951 | {.AsmStrOffset: 10514, .AliasCondStart: 3995, .NumOperands: 3, .NumConds: 6 }, |
| 24952 | // AArch64::LDURHHi - 618 |
| 24953 | {.AsmStrOffset: 10528, .AliasCondStart: 4001, .NumOperands: 3, .NumConds: 3 }, |
| 24954 | // AArch64::LDURHi - 619 |
| 24955 | {.AsmStrOffset: 10514, .AliasCondStart: 4004, .NumOperands: 3, .NumConds: 6 }, |
| 24956 | // AArch64::LDURQi - 620 |
| 24957 | {.AsmStrOffset: 10514, .AliasCondStart: 4010, .NumOperands: 3, .NumConds: 6 }, |
| 24958 | // AArch64::LDURSBWi - 621 |
| 24959 | {.AsmStrOffset: 10543, .AliasCondStart: 4016, .NumOperands: 3, .NumConds: 3 }, |
| 24960 | // AArch64::LDURSBXi - 622 |
| 24961 | {.AsmStrOffset: 10543, .AliasCondStart: 4019, .NumOperands: 3, .NumConds: 3 }, |
| 24962 | // AArch64::LDURSHWi - 623 |
| 24963 | {.AsmStrOffset: 10559, .AliasCondStart: 4022, .NumOperands: 3, .NumConds: 3 }, |
| 24964 | // AArch64::LDURSHXi - 624 |
| 24965 | {.AsmStrOffset: 10559, .AliasCondStart: 4025, .NumOperands: 3, .NumConds: 3 }, |
| 24966 | // AArch64::LDURSWi - 625 |
| 24967 | {.AsmStrOffset: 10575, .AliasCondStart: 4028, .NumOperands: 3, .NumConds: 3 }, |
| 24968 | // AArch64::LDURSi - 626 |
| 24969 | {.AsmStrOffset: 10514, .AliasCondStart: 4031, .NumOperands: 3, .NumConds: 6 }, |
| 24970 | // AArch64::LDURWi - 627 |
| 24971 | {.AsmStrOffset: 10514, .AliasCondStart: 4037, .NumOperands: 3, .NumConds: 3 }, |
| 24972 | // AArch64::LDURXi - 628 |
| 24973 | {.AsmStrOffset: 10514, .AliasCondStart: 4040, .NumOperands: 3, .NumConds: 3 }, |
| 24974 | // AArch64::MADDWrrr - 629 |
| 24975 | {.AsmStrOffset: 10591, .AliasCondStart: 4043, .NumOperands: 4, .NumConds: 4 }, |
| 24976 | // AArch64::MADDXrrr - 630 |
| 24977 | {.AsmStrOffset: 10591, .AliasCondStart: 4047, .NumOperands: 4, .NumConds: 4 }, |
| 24978 | // AArch64::MOVA_2ZMXI_H_B - 631 |
| 24979 | {.AsmStrOffset: 10606, .AliasCondStart: 4051, .NumOperands: 4, .NumConds: 6 }, |
| 24980 | // AArch64::MOVA_2ZMXI_H_D - 632 |
| 24981 | {.AsmStrOffset: 10631, .AliasCondStart: 4057, .NumOperands: 4, .NumConds: 6 }, |
| 24982 | // AArch64::MOVA_2ZMXI_H_H - 633 |
| 24983 | {.AsmStrOffset: 10656, .AliasCondStart: 4063, .NumOperands: 4, .NumConds: 6 }, |
| 24984 | // AArch64::MOVA_2ZMXI_H_S - 634 |
| 24985 | {.AsmStrOffset: 10681, .AliasCondStart: 4069, .NumOperands: 4, .NumConds: 6 }, |
| 24986 | // AArch64::MOVA_2ZMXI_V_B - 635 |
| 24987 | {.AsmStrOffset: 10706, .AliasCondStart: 4075, .NumOperands: 4, .NumConds: 6 }, |
| 24988 | // AArch64::MOVA_2ZMXI_V_D - 636 |
| 24989 | {.AsmStrOffset: 10731, .AliasCondStart: 4081, .NumOperands: 4, .NumConds: 6 }, |
| 24990 | // AArch64::MOVA_2ZMXI_V_H - 637 |
| 24991 | {.AsmStrOffset: 10756, .AliasCondStart: 4087, .NumOperands: 4, .NumConds: 6 }, |
| 24992 | // AArch64::MOVA_2ZMXI_V_S - 638 |
| 24993 | {.AsmStrOffset: 10781, .AliasCondStart: 4093, .NumOperands: 4, .NumConds: 6 }, |
| 24994 | // AArch64::MOVA_4ZMXI_H_B - 639 |
| 24995 | {.AsmStrOffset: 10806, .AliasCondStart: 4099, .NumOperands: 4, .NumConds: 6 }, |
| 24996 | // AArch64::MOVA_4ZMXI_H_D - 640 |
| 24997 | {.AsmStrOffset: 10831, .AliasCondStart: 4105, .NumOperands: 4, .NumConds: 6 }, |
| 24998 | // AArch64::MOVA_4ZMXI_H_H - 641 |
| 24999 | {.AsmStrOffset: 10856, .AliasCondStart: 4111, .NumOperands: 4, .NumConds: 6 }, |
| 25000 | // AArch64::MOVA_4ZMXI_H_S - 642 |
| 25001 | {.AsmStrOffset: 10881, .AliasCondStart: 4117, .NumOperands: 4, .NumConds: 6 }, |
| 25002 | // AArch64::MOVA_4ZMXI_V_B - 643 |
| 25003 | {.AsmStrOffset: 10906, .AliasCondStart: 4123, .NumOperands: 4, .NumConds: 6 }, |
| 25004 | // AArch64::MOVA_4ZMXI_V_D - 644 |
| 25005 | {.AsmStrOffset: 10931, .AliasCondStart: 4129, .NumOperands: 4, .NumConds: 6 }, |
| 25006 | // AArch64::MOVA_4ZMXI_V_H - 645 |
| 25007 | {.AsmStrOffset: 10956, .AliasCondStart: 4135, .NumOperands: 4, .NumConds: 6 }, |
| 25008 | // AArch64::MOVA_4ZMXI_V_S - 646 |
| 25009 | {.AsmStrOffset: 10981, .AliasCondStart: 4141, .NumOperands: 4, .NumConds: 6 }, |
| 25010 | // AArch64::MOVA_MXI2Z_H_B - 647 |
| 25011 | {.AsmStrOffset: 11006, .AliasCondStart: 4147, .NumOperands: 5, .NumConds: 8 }, |
| 25012 | // AArch64::MOVA_MXI2Z_H_D - 648 |
| 25013 | {.AsmStrOffset: 11031, .AliasCondStart: 4155, .NumOperands: 5, .NumConds: 8 }, |
| 25014 | // AArch64::MOVA_MXI2Z_H_H - 649 |
| 25015 | {.AsmStrOffset: 11056, .AliasCondStart: 4163, .NumOperands: 5, .NumConds: 8 }, |
| 25016 | // AArch64::MOVA_MXI2Z_H_S - 650 |
| 25017 | {.AsmStrOffset: 11081, .AliasCondStart: 4171, .NumOperands: 5, .NumConds: 8 }, |
| 25018 | // AArch64::MOVA_MXI2Z_V_B - 651 |
| 25019 | {.AsmStrOffset: 11106, .AliasCondStart: 4179, .NumOperands: 5, .NumConds: 8 }, |
| 25020 | // AArch64::MOVA_MXI2Z_V_D - 652 |
| 25021 | {.AsmStrOffset: 11131, .AliasCondStart: 4187, .NumOperands: 5, .NumConds: 8 }, |
| 25022 | // AArch64::MOVA_MXI2Z_V_H - 653 |
| 25023 | {.AsmStrOffset: 11156, .AliasCondStart: 4195, .NumOperands: 5, .NumConds: 8 }, |
| 25024 | // AArch64::MOVA_MXI2Z_V_S - 654 |
| 25025 | {.AsmStrOffset: 11181, .AliasCondStart: 4203, .NumOperands: 5, .NumConds: 8 }, |
| 25026 | // AArch64::MOVA_MXI4Z_H_B - 655 |
| 25027 | {.AsmStrOffset: 11206, .AliasCondStart: 4211, .NumOperands: 5, .NumConds: 8 }, |
| 25028 | // AArch64::MOVA_MXI4Z_H_D - 656 |
| 25029 | {.AsmStrOffset: 11231, .AliasCondStart: 4219, .NumOperands: 5, .NumConds: 8 }, |
| 25030 | // AArch64::MOVA_MXI4Z_H_H - 657 |
| 25031 | {.AsmStrOffset: 11256, .AliasCondStart: 4227, .NumOperands: 5, .NumConds: 8 }, |
| 25032 | // AArch64::MOVA_MXI4Z_H_S - 658 |
| 25033 | {.AsmStrOffset: 11281, .AliasCondStart: 4235, .NumOperands: 5, .NumConds: 8 }, |
| 25034 | // AArch64::MOVA_MXI4Z_V_B - 659 |
| 25035 | {.AsmStrOffset: 11306, .AliasCondStart: 4243, .NumOperands: 5, .NumConds: 8 }, |
| 25036 | // AArch64::MOVA_MXI4Z_V_D - 660 |
| 25037 | {.AsmStrOffset: 11331, .AliasCondStart: 4251, .NumOperands: 5, .NumConds: 8 }, |
| 25038 | // AArch64::MOVA_MXI4Z_V_H - 661 |
| 25039 | {.AsmStrOffset: 11356, .AliasCondStart: 4259, .NumOperands: 5, .NumConds: 8 }, |
| 25040 | // AArch64::MOVA_MXI4Z_V_S - 662 |
| 25041 | {.AsmStrOffset: 11381, .AliasCondStart: 4267, .NumOperands: 5, .NumConds: 8 }, |
| 25042 | // AArch64::MOVA_VG2_2ZMXI - 663 |
| 25043 | {.AsmStrOffset: 11406, .AliasCondStart: 4275, .NumOperands: 4, .NumConds: 6 }, |
| 25044 | // AArch64::MOVA_VG2_MXI2Z - 664 |
| 25045 | {.AsmStrOffset: 11437, .AliasCondStart: 4281, .NumOperands: 5, .NumConds: 8 }, |
| 25046 | // AArch64::MOVA_VG4_4ZMXI - 665 |
| 25047 | {.AsmStrOffset: 11468, .AliasCondStart: 4289, .NumOperands: 4, .NumConds: 6 }, |
| 25048 | // AArch64::MOVA_VG4_MXI4Z - 666 |
| 25049 | {.AsmStrOffset: 11499, .AliasCondStart: 4295, .NumOperands: 5, .NumConds: 8 }, |
| 25050 | // AArch64::MOVT - 667 |
| 25051 | {.AsmStrOffset: 11530, .AliasCondStart: 4303, .NumOperands: 3, .NumConds: 9 }, |
| 25052 | // AArch64::MSRpstatesvcrImm1 - 668 |
| 25053 | {.AsmStrOffset: 11544, .AliasCondStart: 4312, .NumOperands: 2, .NumConds: 2 }, |
| 25054 | {.AsmStrOffset: 11552, .AliasCondStart: 4314, .NumOperands: 2, .NumConds: 2 }, |
| 25055 | {.AsmStrOffset: 11563, .AliasCondStart: 4316, .NumOperands: 2, .NumConds: 2 }, |
| 25056 | {.AsmStrOffset: 11574, .AliasCondStart: 4318, .NumOperands: 2, .NumConds: 2 }, |
| 25057 | {.AsmStrOffset: 11581, .AliasCondStart: 4320, .NumOperands: 2, .NumConds: 2 }, |
| 25058 | {.AsmStrOffset: 11591, .AliasCondStart: 4322, .NumOperands: 2, .NumConds: 2 }, |
| 25059 | // AArch64::MSUBWrrr - 674 |
| 25060 | {.AsmStrOffset: 11601, .AliasCondStart: 4324, .NumOperands: 4, .NumConds: 4 }, |
| 25061 | // AArch64::MSUBXrrr - 675 |
| 25062 | {.AsmStrOffset: 11601, .AliasCondStart: 4328, .NumOperands: 4, .NumConds: 4 }, |
| 25063 | // AArch64::NOTv16i8 - 676 |
| 25064 | {.AsmStrOffset: 11617, .AliasCondStart: 4332, .NumOperands: 2, .NumConds: 5 }, |
| 25065 | // AArch64::NOTv8i8 - 677 |
| 25066 | {.AsmStrOffset: 11636, .AliasCondStart: 4337, .NumOperands: 2, .NumConds: 5 }, |
| 25067 | // AArch64::ORNWrs - 678 |
| 25068 | {.AsmStrOffset: 11654, .AliasCondStart: 4342, .NumOperands: 4, .NumConds: 4 }, |
| 25069 | {.AsmStrOffset: 11665, .AliasCondStart: 4346, .NumOperands: 4, .NumConds: 3 }, |
| 25070 | {.AsmStrOffset: 11680, .AliasCondStart: 4349, .NumOperands: 4, .NumConds: 4 }, |
| 25071 | // AArch64::ORNXrs - 681 |
| 25072 | {.AsmStrOffset: 11654, .AliasCondStart: 4353, .NumOperands: 4, .NumConds: 4 }, |
| 25073 | {.AsmStrOffset: 11665, .AliasCondStart: 4357, .NumOperands: 4, .NumConds: 3 }, |
| 25074 | {.AsmStrOffset: 11680, .AliasCondStart: 4360, .NumOperands: 4, .NumConds: 4 }, |
| 25075 | // AArch64::ORRS_PPzPP - 684 |
| 25076 | {.AsmStrOffset: 11695, .AliasCondStart: 4364, .NumOperands: 4, .NumConds: 8 }, |
| 25077 | // AArch64::ORRWrs - 685 |
| 25078 | {.AsmStrOffset: 11711, .AliasCondStart: 4372, .NumOperands: 4, .NumConds: 4 }, |
| 25079 | {.AsmStrOffset: 11722, .AliasCondStart: 4376, .NumOperands: 4, .NumConds: 4 }, |
| 25080 | // AArch64::ORRXrs - 687 |
| 25081 | {.AsmStrOffset: 11711, .AliasCondStart: 4380, .NumOperands: 4, .NumConds: 4 }, |
| 25082 | {.AsmStrOffset: 11722, .AliasCondStart: 4384, .NumOperands: 4, .NumConds: 4 }, |
| 25083 | // AArch64::ORR_PPzPP - 689 |
| 25084 | {.AsmStrOffset: 11737, .AliasCondStart: 4388, .NumOperands: 4, .NumConds: 8 }, |
| 25085 | // AArch64::ORR_ZI - 690 |
| 25086 | {.AsmStrOffset: 11752, .AliasCondStart: 4396, .NumOperands: 3, .NumConds: 7 }, |
| 25087 | {.AsmStrOffset: 11773, .AliasCondStart: 4403, .NumOperands: 3, .NumConds: 7 }, |
| 25088 | {.AsmStrOffset: 11794, .AliasCondStart: 4410, .NumOperands: 3, .NumConds: 7 }, |
| 25089 | // AArch64::ORR_ZZZ - 693 |
| 25090 | {.AsmStrOffset: 11815, .AliasCondStart: 4417, .NumOperands: 3, .NumConds: 7 }, |
| 25091 | // AArch64::ORRv16i8 - 694 |
| 25092 | {.AsmStrOffset: 11830, .AliasCondStart: 4424, .NumOperands: 3, .NumConds: 6 }, |
| 25093 | // AArch64::ORRv8i8 - 695 |
| 25094 | {.AsmStrOffset: 11849, .AliasCondStart: 4430, .NumOperands: 3, .NumConds: 6 }, |
| 25095 | // AArch64::PACIA1716 - 696 |
| 25096 | {.AsmStrOffset: 11867, .AliasCondStart: 4436, .NumOperands: 0, .NumConds: 3 }, |
| 25097 | // AArch64::PACIASP - 697 |
| 25098 | {.AsmStrOffset: 11877, .AliasCondStart: 4439, .NumOperands: 0, .NumConds: 3 }, |
| 25099 | // AArch64::PACIAZ - 698 |
| 25100 | {.AsmStrOffset: 11885, .AliasCondStart: 4442, .NumOperands: 0, .NumConds: 3 }, |
| 25101 | // AArch64::PACIB1716 - 699 |
| 25102 | {.AsmStrOffset: 11892, .AliasCondStart: 4445, .NumOperands: 0, .NumConds: 3 }, |
| 25103 | // AArch64::PACIBSP - 700 |
| 25104 | {.AsmStrOffset: 11902, .AliasCondStart: 4448, .NumOperands: 0, .NumConds: 3 }, |
| 25105 | // AArch64::PACIBZ - 701 |
| 25106 | {.AsmStrOffset: 11910, .AliasCondStart: 4451, .NumOperands: 0, .NumConds: 3 }, |
| 25107 | // AArch64::PACM - 702 |
| 25108 | {.AsmStrOffset: 11917, .AliasCondStart: 4454, .NumOperands: 0, .NumConds: 3 }, |
| 25109 | // AArch64::PMOV_PZI_B - 703 |
| 25110 | {.AsmStrOffset: 11922, .AliasCondStart: 4457, .NumOperands: 3, .NumConds: 7 }, |
| 25111 | // AArch64::PMOV_ZIP_B - 704 |
| 25112 | {.AsmStrOffset: 11938, .AliasCondStart: 4464, .NumOperands: 4, .NumConds: 8 }, |
| 25113 | // AArch64::PRFB_D_PZI - 705 |
| 25114 | {.AsmStrOffset: 11954, .AliasCondStart: 4472, .NumOperands: 4, .NumConds: 7 }, |
| 25115 | // AArch64::PRFB_PRI - 706 |
| 25116 | {.AsmStrOffset: 11978, .AliasCondStart: 4479, .NumOperands: 4, .NumConds: 8 }, |
| 25117 | // AArch64::PRFB_S_PZI - 707 |
| 25118 | {.AsmStrOffset: 12000, .AliasCondStart: 4487, .NumOperands: 4, .NumConds: 7 }, |
| 25119 | // AArch64::PRFD_D_PZI - 708 |
| 25120 | {.AsmStrOffset: 12024, .AliasCondStart: 4494, .NumOperands: 4, .NumConds: 7 }, |
| 25121 | // AArch64::PRFD_PRI - 709 |
| 25122 | {.AsmStrOffset: 12048, .AliasCondStart: 4501, .NumOperands: 4, .NumConds: 8 }, |
| 25123 | // AArch64::PRFD_S_PZI - 710 |
| 25124 | {.AsmStrOffset: 12070, .AliasCondStart: 4509, .NumOperands: 4, .NumConds: 7 }, |
| 25125 | // AArch64::PRFH_D_PZI - 711 |
| 25126 | {.AsmStrOffset: 12094, .AliasCondStart: 4516, .NumOperands: 4, .NumConds: 7 }, |
| 25127 | // AArch64::PRFH_PRI - 712 |
| 25128 | {.AsmStrOffset: 12118, .AliasCondStart: 4523, .NumOperands: 4, .NumConds: 8 }, |
| 25129 | // AArch64::PRFH_S_PZI - 713 |
| 25130 | {.AsmStrOffset: 12140, .AliasCondStart: 4531, .NumOperands: 4, .NumConds: 7 }, |
| 25131 | // AArch64::PRFMroX - 714 |
| 25132 | {.AsmStrOffset: 12164, .AliasCondStart: 4538, .NumOperands: 5, .NumConds: 5 }, |
| 25133 | // AArch64::PRFMui - 715 |
| 25134 | {.AsmStrOffset: 12184, .AliasCondStart: 4543, .NumOperands: 3, .NumConds: 3 }, |
| 25135 | // AArch64::PRFUMi - 716 |
| 25136 | {.AsmStrOffset: 12200, .AliasCondStart: 4546, .NumOperands: 3, .NumConds: 3 }, |
| 25137 | // AArch64::PRFW_D_PZI - 717 |
| 25138 | {.AsmStrOffset: 12217, .AliasCondStart: 4549, .NumOperands: 4, .NumConds: 7 }, |
| 25139 | // AArch64::PRFW_PRI - 718 |
| 25140 | {.AsmStrOffset: 12241, .AliasCondStart: 4556, .NumOperands: 4, .NumConds: 8 }, |
| 25141 | // AArch64::PRFW_S_PZI - 719 |
| 25142 | {.AsmStrOffset: 12263, .AliasCondStart: 4564, .NumOperands: 4, .NumConds: 7 }, |
| 25143 | // AArch64::PTRUES_B - 720 |
| 25144 | {.AsmStrOffset: 12287, .AliasCondStart: 4571, .NumOperands: 2, .NumConds: 6 }, |
| 25145 | // AArch64::PTRUES_D - 721 |
| 25146 | {.AsmStrOffset: 12299, .AliasCondStart: 4577, .NumOperands: 2, .NumConds: 6 }, |
| 25147 | // AArch64::PTRUES_H - 722 |
| 25148 | {.AsmStrOffset: 12311, .AliasCondStart: 4583, .NumOperands: 2, .NumConds: 6 }, |
| 25149 | // AArch64::PTRUES_S - 723 |
| 25150 | {.AsmStrOffset: 12323, .AliasCondStart: 4589, .NumOperands: 2, .NumConds: 6 }, |
| 25151 | // AArch64::PTRUE_B - 724 |
| 25152 | {.AsmStrOffset: 12335, .AliasCondStart: 4595, .NumOperands: 2, .NumConds: 6 }, |
| 25153 | // AArch64::PTRUE_D - 725 |
| 25154 | {.AsmStrOffset: 12346, .AliasCondStart: 4601, .NumOperands: 2, .NumConds: 6 }, |
| 25155 | // AArch64::PTRUE_H - 726 |
| 25156 | {.AsmStrOffset: 12357, .AliasCondStart: 4607, .NumOperands: 2, .NumConds: 6 }, |
| 25157 | // AArch64::PTRUE_S - 727 |
| 25158 | {.AsmStrOffset: 12368, .AliasCondStart: 4613, .NumOperands: 2, .NumConds: 6 }, |
| 25159 | // AArch64::RET - 728 |
| 25160 | {.AsmStrOffset: 12379, .AliasCondStart: 4619, .NumOperands: 1, .NumConds: 1 }, |
| 25161 | // AArch64::SBCSWr - 729 |
| 25162 | {.AsmStrOffset: 12383, .AliasCondStart: 4620, .NumOperands: 3, .NumConds: 3 }, |
| 25163 | // AArch64::SBCSXr - 730 |
| 25164 | {.AsmStrOffset: 12383, .AliasCondStart: 4623, .NumOperands: 3, .NumConds: 3 }, |
| 25165 | // AArch64::SBCWr - 731 |
| 25166 | {.AsmStrOffset: 12395, .AliasCondStart: 4626, .NumOperands: 3, .NumConds: 3 }, |
| 25167 | // AArch64::SBCXr - 732 |
| 25168 | {.AsmStrOffset: 12395, .AliasCondStart: 4629, .NumOperands: 3, .NumConds: 3 }, |
| 25169 | // AArch64::SBFMWri - 733 |
| 25170 | {.AsmStrOffset: 12406, .AliasCondStart: 4632, .NumOperands: 4, .NumConds: 4 }, |
| 25171 | {.AsmStrOffset: 12421, .AliasCondStart: 4636, .NumOperands: 4, .NumConds: 4 }, |
| 25172 | {.AsmStrOffset: 12433, .AliasCondStart: 4640, .NumOperands: 4, .NumConds: 4 }, |
| 25173 | // AArch64::SBFMXri - 736 |
| 25174 | {.AsmStrOffset: 12406, .AliasCondStart: 4644, .NumOperands: 4, .NumConds: 4 }, |
| 25175 | {.AsmStrOffset: 12421, .AliasCondStart: 4648, .NumOperands: 4, .NumConds: 4 }, |
| 25176 | {.AsmStrOffset: 12433, .AliasCondStart: 4652, .NumOperands: 4, .NumConds: 4 }, |
| 25177 | {.AsmStrOffset: 12445, .AliasCondStart: 4656, .NumOperands: 4, .NumConds: 4 }, |
| 25178 | // AArch64::SEL_PPPP - 740 |
| 25179 | {.AsmStrOffset: 12457, .AliasCondStart: 4660, .NumOperands: 4, .NumConds: 8 }, |
| 25180 | // AArch64::SEL_ZPZZ_B - 741 |
| 25181 | {.AsmStrOffset: 12457, .AliasCondStart: 4668, .NumOperands: 4, .NumConds: 8 }, |
| 25182 | // AArch64::SEL_ZPZZ_D - 742 |
| 25183 | {.AsmStrOffset: 12480, .AliasCondStart: 4676, .NumOperands: 4, .NumConds: 8 }, |
| 25184 | // AArch64::SEL_ZPZZ_H - 743 |
| 25185 | {.AsmStrOffset: 12503, .AliasCondStart: 4684, .NumOperands: 4, .NumConds: 8 }, |
| 25186 | // AArch64::SEL_ZPZZ_S - 744 |
| 25187 | {.AsmStrOffset: 12526, .AliasCondStart: 4692, .NumOperands: 4, .NumConds: 8 }, |
| 25188 | // AArch64::SMADDLrrr - 745 |
| 25189 | {.AsmStrOffset: 12549, .AliasCondStart: 4700, .NumOperands: 4, .NumConds: 4 }, |
| 25190 | // AArch64::SMSUBLrrr - 746 |
| 25191 | {.AsmStrOffset: 12566, .AliasCondStart: 4704, .NumOperands: 4, .NumConds: 4 }, |
| 25192 | // AArch64::SQDECB_XPiI - 747 |
| 25193 | {.AsmStrOffset: 12584, .AliasCondStart: 4708, .NumOperands: 4, .NumConds: 8 }, |
| 25194 | {.AsmStrOffset: 12594, .AliasCondStart: 4716, .NumOperands: 4, .NumConds: 8 }, |
| 25195 | // AArch64::SQDECB_XPiWdI - 749 |
| 25196 | {.AsmStrOffset: 12610, .AliasCondStart: 4724, .NumOperands: 4, .NumConds: 8 }, |
| 25197 | {.AsmStrOffset: 12626, .AliasCondStart: 4732, .NumOperands: 4, .NumConds: 8 }, |
| 25198 | // AArch64::SQDECD_XPiI - 751 |
| 25199 | {.AsmStrOffset: 12648, .AliasCondStart: 4740, .NumOperands: 4, .NumConds: 8 }, |
| 25200 | {.AsmStrOffset: 12658, .AliasCondStart: 4748, .NumOperands: 4, .NumConds: 8 }, |
| 25201 | // AArch64::SQDECD_XPiWdI - 753 |
| 25202 | {.AsmStrOffset: 12674, .AliasCondStart: 4756, .NumOperands: 4, .NumConds: 8 }, |
| 25203 | {.AsmStrOffset: 12690, .AliasCondStart: 4764, .NumOperands: 4, .NumConds: 8 }, |
| 25204 | // AArch64::SQDECD_ZPiI - 755 |
| 25205 | {.AsmStrOffset: 12712, .AliasCondStart: 4772, .NumOperands: 4, .NumConds: 8 }, |
| 25206 | {.AsmStrOffset: 12724, .AliasCondStart: 4780, .NumOperands: 4, .NumConds: 8 }, |
| 25207 | // AArch64::SQDECH_XPiI - 757 |
| 25208 | {.AsmStrOffset: 12742, .AliasCondStart: 4788, .NumOperands: 4, .NumConds: 8 }, |
| 25209 | {.AsmStrOffset: 12752, .AliasCondStart: 4796, .NumOperands: 4, .NumConds: 8 }, |
| 25210 | // AArch64::SQDECH_XPiWdI - 759 |
| 25211 | {.AsmStrOffset: 12768, .AliasCondStart: 4804, .NumOperands: 4, .NumConds: 8 }, |
| 25212 | {.AsmStrOffset: 12784, .AliasCondStart: 4812, .NumOperands: 4, .NumConds: 8 }, |
| 25213 | // AArch64::SQDECH_ZPiI - 761 |
| 25214 | {.AsmStrOffset: 12806, .AliasCondStart: 4820, .NumOperands: 4, .NumConds: 8 }, |
| 25215 | {.AsmStrOffset: 12818, .AliasCondStart: 4828, .NumOperands: 4, .NumConds: 8 }, |
| 25216 | // AArch64::SQDECW_XPiI - 763 |
| 25217 | {.AsmStrOffset: 12836, .AliasCondStart: 4836, .NumOperands: 4, .NumConds: 8 }, |
| 25218 | {.AsmStrOffset: 12846, .AliasCondStart: 4844, .NumOperands: 4, .NumConds: 8 }, |
| 25219 | // AArch64::SQDECW_XPiWdI - 765 |
| 25220 | {.AsmStrOffset: 12862, .AliasCondStart: 4852, .NumOperands: 4, .NumConds: 8 }, |
| 25221 | {.AsmStrOffset: 12878, .AliasCondStart: 4860, .NumOperands: 4, .NumConds: 8 }, |
| 25222 | // AArch64::SQDECW_ZPiI - 767 |
| 25223 | {.AsmStrOffset: 12900, .AliasCondStart: 4868, .NumOperands: 4, .NumConds: 8 }, |
| 25224 | {.AsmStrOffset: 12912, .AliasCondStart: 4876, .NumOperands: 4, .NumConds: 8 }, |
| 25225 | // AArch64::SQINCB_XPiI - 769 |
| 25226 | {.AsmStrOffset: 12930, .AliasCondStart: 4884, .NumOperands: 4, .NumConds: 8 }, |
| 25227 | {.AsmStrOffset: 12940, .AliasCondStart: 4892, .NumOperands: 4, .NumConds: 8 }, |
| 25228 | // AArch64::SQINCB_XPiWdI - 771 |
| 25229 | {.AsmStrOffset: 12956, .AliasCondStart: 4900, .NumOperands: 4, .NumConds: 8 }, |
| 25230 | {.AsmStrOffset: 12972, .AliasCondStart: 4908, .NumOperands: 4, .NumConds: 8 }, |
| 25231 | // AArch64::SQINCD_XPiI - 773 |
| 25232 | {.AsmStrOffset: 12994, .AliasCondStart: 4916, .NumOperands: 4, .NumConds: 8 }, |
| 25233 | {.AsmStrOffset: 13004, .AliasCondStart: 4924, .NumOperands: 4, .NumConds: 8 }, |
| 25234 | // AArch64::SQINCD_XPiWdI - 775 |
| 25235 | {.AsmStrOffset: 13020, .AliasCondStart: 4932, .NumOperands: 4, .NumConds: 8 }, |
| 25236 | {.AsmStrOffset: 13036, .AliasCondStart: 4940, .NumOperands: 4, .NumConds: 8 }, |
| 25237 | // AArch64::SQINCD_ZPiI - 777 |
| 25238 | {.AsmStrOffset: 13058, .AliasCondStart: 4948, .NumOperands: 4, .NumConds: 8 }, |
| 25239 | {.AsmStrOffset: 13070, .AliasCondStart: 4956, .NumOperands: 4, .NumConds: 8 }, |
| 25240 | // AArch64::SQINCH_XPiI - 779 |
| 25241 | {.AsmStrOffset: 13088, .AliasCondStart: 4964, .NumOperands: 4, .NumConds: 8 }, |
| 25242 | {.AsmStrOffset: 13098, .AliasCondStart: 4972, .NumOperands: 4, .NumConds: 8 }, |
| 25243 | // AArch64::SQINCH_XPiWdI - 781 |
| 25244 | {.AsmStrOffset: 13114, .AliasCondStart: 4980, .NumOperands: 4, .NumConds: 8 }, |
| 25245 | {.AsmStrOffset: 13130, .AliasCondStart: 4988, .NumOperands: 4, .NumConds: 8 }, |
| 25246 | // AArch64::SQINCH_ZPiI - 783 |
| 25247 | {.AsmStrOffset: 13152, .AliasCondStart: 4996, .NumOperands: 4, .NumConds: 8 }, |
| 25248 | {.AsmStrOffset: 13164, .AliasCondStart: 5004, .NumOperands: 4, .NumConds: 8 }, |
| 25249 | // AArch64::SQINCW_XPiI - 785 |
| 25250 | {.AsmStrOffset: 13182, .AliasCondStart: 5012, .NumOperands: 4, .NumConds: 8 }, |
| 25251 | {.AsmStrOffset: 13192, .AliasCondStart: 5020, .NumOperands: 4, .NumConds: 8 }, |
| 25252 | // AArch64::SQINCW_XPiWdI - 787 |
| 25253 | {.AsmStrOffset: 13208, .AliasCondStart: 5028, .NumOperands: 4, .NumConds: 8 }, |
| 25254 | {.AsmStrOffset: 13224, .AliasCondStart: 5036, .NumOperands: 4, .NumConds: 8 }, |
| 25255 | // AArch64::SQINCW_ZPiI - 789 |
| 25256 | {.AsmStrOffset: 13246, .AliasCondStart: 5044, .NumOperands: 4, .NumConds: 8 }, |
| 25257 | {.AsmStrOffset: 13258, .AliasCondStart: 5052, .NumOperands: 4, .NumConds: 8 }, |
| 25258 | // AArch64::SST1B_D_IMM - 791 |
| 25259 | {.AsmStrOffset: 13276, .AliasCondStart: 5060, .NumOperands: 4, .NumConds: 7 }, |
| 25260 | // AArch64::SST1B_S_IMM - 792 |
| 25261 | {.AsmStrOffset: 13300, .AliasCondStart: 5067, .NumOperands: 4, .NumConds: 7 }, |
| 25262 | // AArch64::SST1D_IMM - 793 |
| 25263 | {.AsmStrOffset: 13324, .AliasCondStart: 5074, .NumOperands: 4, .NumConds: 7 }, |
| 25264 | // AArch64::SST1H_D_IMM - 794 |
| 25265 | {.AsmStrOffset: 13348, .AliasCondStart: 5081, .NumOperands: 4, .NumConds: 7 }, |
| 25266 | // AArch64::SST1H_S_IMM - 795 |
| 25267 | {.AsmStrOffset: 13372, .AliasCondStart: 5088, .NumOperands: 4, .NumConds: 7 }, |
| 25268 | // AArch64::SST1Q - 796 |
| 25269 | {.AsmStrOffset: 13396, .AliasCondStart: 5095, .NumOperands: 4, .NumConds: 7 }, |
| 25270 | // AArch64::SST1W_D_IMM - 797 |
| 25271 | {.AsmStrOffset: 13420, .AliasCondStart: 5102, .NumOperands: 4, .NumConds: 7 }, |
| 25272 | // AArch64::SST1W_IMM - 798 |
| 25273 | {.AsmStrOffset: 13444, .AliasCondStart: 5109, .NumOperands: 4, .NumConds: 7 }, |
| 25274 | // AArch64::ST1B_2Z_IMM - 799 |
| 25275 | {.AsmStrOffset: 13468, .AliasCondStart: 5116, .NumOperands: 4, .NumConds: 8 }, |
| 25276 | // AArch64::ST1B_2Z_STRIDED_IMM - 800 |
| 25277 | {.AsmStrOffset: 13490, .AliasCondStart: 5124, .NumOperands: 4, .NumConds: 7 }, |
| 25278 | // AArch64::ST1B_4Z_IMM - 801 |
| 25279 | {.AsmStrOffset: 13468, .AliasCondStart: 5131, .NumOperands: 4, .NumConds: 8 }, |
| 25280 | // AArch64::ST1B_4Z_STRIDED_IMM - 802 |
| 25281 | {.AsmStrOffset: 13512, .AliasCondStart: 5139, .NumOperands: 4, .NumConds: 7 }, |
| 25282 | // AArch64::ST1B_D_IMM - 803 |
| 25283 | {.AsmStrOffset: 13534, .AliasCondStart: 5146, .NumOperands: 4, .NumConds: 8 }, |
| 25284 | // AArch64::ST1B_H_IMM - 804 |
| 25285 | {.AsmStrOffset: 13556, .AliasCondStart: 5154, .NumOperands: 4, .NumConds: 8 }, |
| 25286 | // AArch64::ST1B_IMM - 805 |
| 25287 | {.AsmStrOffset: 13578, .AliasCondStart: 5162, .NumOperands: 4, .NumConds: 8 }, |
| 25288 | // AArch64::ST1B_S_IMM - 806 |
| 25289 | {.AsmStrOffset: 13600, .AliasCondStart: 5170, .NumOperands: 4, .NumConds: 8 }, |
| 25290 | // AArch64::ST1D_2Z_IMM - 807 |
| 25291 | {.AsmStrOffset: 13622, .AliasCondStart: 5178, .NumOperands: 4, .NumConds: 8 }, |
| 25292 | // AArch64::ST1D_2Z_STRIDED_IMM - 808 |
| 25293 | {.AsmStrOffset: 13644, .AliasCondStart: 5186, .NumOperands: 4, .NumConds: 7 }, |
| 25294 | // AArch64::ST1D_4Z_IMM - 809 |
| 25295 | {.AsmStrOffset: 13622, .AliasCondStart: 5193, .NumOperands: 4, .NumConds: 8 }, |
| 25296 | // AArch64::ST1D_4Z_STRIDED_IMM - 810 |
| 25297 | {.AsmStrOffset: 13644, .AliasCondStart: 5201, .NumOperands: 4, .NumConds: 7 }, |
| 25298 | // AArch64::ST1D_IMM - 811 |
| 25299 | {.AsmStrOffset: 13666, .AliasCondStart: 5208, .NumOperands: 4, .NumConds: 8 }, |
| 25300 | // AArch64::ST1D_Q_IMM - 812 |
| 25301 | {.AsmStrOffset: 13688, .AliasCondStart: 5216, .NumOperands: 4, .NumConds: 7 }, |
| 25302 | // AArch64::ST1Fourv16b_POST - 813 |
| 25303 | {.AsmStrOffset: 13710, .AliasCondStart: 5223, .NumOperands: 4, .NumConds: 7 }, |
| 25304 | // AArch64::ST1Fourv1d_POST - 814 |
| 25305 | {.AsmStrOffset: 13730, .AliasCondStart: 5230, .NumOperands: 4, .NumConds: 7 }, |
| 25306 | // AArch64::ST1Fourv2d_POST - 815 |
| 25307 | {.AsmStrOffset: 13750, .AliasCondStart: 5237, .NumOperands: 4, .NumConds: 7 }, |
| 25308 | // AArch64::ST1Fourv2s_POST - 816 |
| 25309 | {.AsmStrOffset: 13770, .AliasCondStart: 5244, .NumOperands: 4, .NumConds: 7 }, |
| 25310 | // AArch64::ST1Fourv4h_POST - 817 |
| 25311 | {.AsmStrOffset: 13790, .AliasCondStart: 5251, .NumOperands: 4, .NumConds: 7 }, |
| 25312 | // AArch64::ST1Fourv4s_POST - 818 |
| 25313 | {.AsmStrOffset: 13810, .AliasCondStart: 5258, .NumOperands: 4, .NumConds: 7 }, |
| 25314 | // AArch64::ST1Fourv8b_POST - 819 |
| 25315 | {.AsmStrOffset: 13830, .AliasCondStart: 5265, .NumOperands: 4, .NumConds: 7 }, |
| 25316 | // AArch64::ST1Fourv8h_POST - 820 |
| 25317 | {.AsmStrOffset: 13850, .AliasCondStart: 5272, .NumOperands: 4, .NumConds: 7 }, |
| 25318 | // AArch64::ST1H_2Z_IMM - 821 |
| 25319 | {.AsmStrOffset: 13870, .AliasCondStart: 5279, .NumOperands: 4, .NumConds: 8 }, |
| 25320 | // AArch64::ST1H_2Z_STRIDED_IMM - 822 |
| 25321 | {.AsmStrOffset: 13892, .AliasCondStart: 5287, .NumOperands: 4, .NumConds: 7 }, |
| 25322 | // AArch64::ST1H_4Z_IMM - 823 |
| 25323 | {.AsmStrOffset: 13870, .AliasCondStart: 5294, .NumOperands: 4, .NumConds: 8 }, |
| 25324 | // AArch64::ST1H_4Z_STRIDED_IMM - 824 |
| 25325 | {.AsmStrOffset: 13914, .AliasCondStart: 5302, .NumOperands: 4, .NumConds: 7 }, |
| 25326 | // AArch64::ST1H_D_IMM - 825 |
| 25327 | {.AsmStrOffset: 13936, .AliasCondStart: 5309, .NumOperands: 4, .NumConds: 8 }, |
| 25328 | // AArch64::ST1H_IMM - 826 |
| 25329 | {.AsmStrOffset: 13958, .AliasCondStart: 5317, .NumOperands: 4, .NumConds: 8 }, |
| 25330 | // AArch64::ST1H_S_IMM - 827 |
| 25331 | {.AsmStrOffset: 13980, .AliasCondStart: 5325, .NumOperands: 4, .NumConds: 8 }, |
| 25332 | // AArch64::ST1Onev16b_POST - 828 |
| 25333 | {.AsmStrOffset: 14002, .AliasCondStart: 5333, .NumOperands: 4, .NumConds: 7 }, |
| 25334 | // AArch64::ST1Onev1d_POST - 829 |
| 25335 | {.AsmStrOffset: 14022, .AliasCondStart: 5340, .NumOperands: 4, .NumConds: 7 }, |
| 25336 | // AArch64::ST1Onev2d_POST - 830 |
| 25337 | {.AsmStrOffset: 14041, .AliasCondStart: 5347, .NumOperands: 4, .NumConds: 7 }, |
| 25338 | // AArch64::ST1Onev2s_POST - 831 |
| 25339 | {.AsmStrOffset: 14061, .AliasCondStart: 5354, .NumOperands: 4, .NumConds: 7 }, |
| 25340 | // AArch64::ST1Onev4h_POST - 832 |
| 25341 | {.AsmStrOffset: 14080, .AliasCondStart: 5361, .NumOperands: 4, .NumConds: 7 }, |
| 25342 | // AArch64::ST1Onev4s_POST - 833 |
| 25343 | {.AsmStrOffset: 14099, .AliasCondStart: 5368, .NumOperands: 4, .NumConds: 7 }, |
| 25344 | // AArch64::ST1Onev8b_POST - 834 |
| 25345 | {.AsmStrOffset: 14119, .AliasCondStart: 5375, .NumOperands: 4, .NumConds: 7 }, |
| 25346 | // AArch64::ST1Onev8h_POST - 835 |
| 25347 | {.AsmStrOffset: 14138, .AliasCondStart: 5382, .NumOperands: 4, .NumConds: 7 }, |
| 25348 | // AArch64::ST1Threev16b_POST - 836 |
| 25349 | {.AsmStrOffset: 14158, .AliasCondStart: 5389, .NumOperands: 4, .NumConds: 7 }, |
| 25350 | // AArch64::ST1Threev1d_POST - 837 |
| 25351 | {.AsmStrOffset: 14178, .AliasCondStart: 5396, .NumOperands: 4, .NumConds: 7 }, |
| 25352 | // AArch64::ST1Threev2d_POST - 838 |
| 25353 | {.AsmStrOffset: 14198, .AliasCondStart: 5403, .NumOperands: 4, .NumConds: 7 }, |
| 25354 | // AArch64::ST1Threev2s_POST - 839 |
| 25355 | {.AsmStrOffset: 14218, .AliasCondStart: 5410, .NumOperands: 4, .NumConds: 7 }, |
| 25356 | // AArch64::ST1Threev4h_POST - 840 |
| 25357 | {.AsmStrOffset: 14238, .AliasCondStart: 5417, .NumOperands: 4, .NumConds: 7 }, |
| 25358 | // AArch64::ST1Threev4s_POST - 841 |
| 25359 | {.AsmStrOffset: 14258, .AliasCondStart: 5424, .NumOperands: 4, .NumConds: 7 }, |
| 25360 | // AArch64::ST1Threev8b_POST - 842 |
| 25361 | {.AsmStrOffset: 14278, .AliasCondStart: 5431, .NumOperands: 4, .NumConds: 7 }, |
| 25362 | // AArch64::ST1Threev8h_POST - 843 |
| 25363 | {.AsmStrOffset: 14298, .AliasCondStart: 5438, .NumOperands: 4, .NumConds: 7 }, |
| 25364 | // AArch64::ST1Twov16b_POST - 844 |
| 25365 | {.AsmStrOffset: 14318, .AliasCondStart: 5445, .NumOperands: 4, .NumConds: 7 }, |
| 25366 | // AArch64::ST1Twov1d_POST - 845 |
| 25367 | {.AsmStrOffset: 14338, .AliasCondStart: 5452, .NumOperands: 4, .NumConds: 7 }, |
| 25368 | // AArch64::ST1Twov2d_POST - 846 |
| 25369 | {.AsmStrOffset: 14358, .AliasCondStart: 5459, .NumOperands: 4, .NumConds: 7 }, |
| 25370 | // AArch64::ST1Twov2s_POST - 847 |
| 25371 | {.AsmStrOffset: 14378, .AliasCondStart: 5466, .NumOperands: 4, .NumConds: 7 }, |
| 25372 | // AArch64::ST1Twov4h_POST - 848 |
| 25373 | {.AsmStrOffset: 14398, .AliasCondStart: 5473, .NumOperands: 4, .NumConds: 7 }, |
| 25374 | // AArch64::ST1Twov4s_POST - 849 |
| 25375 | {.AsmStrOffset: 14418, .AliasCondStart: 5480, .NumOperands: 4, .NumConds: 7 }, |
| 25376 | // AArch64::ST1Twov8b_POST - 850 |
| 25377 | {.AsmStrOffset: 14438, .AliasCondStart: 5487, .NumOperands: 4, .NumConds: 7 }, |
| 25378 | // AArch64::ST1Twov8h_POST - 851 |
| 25379 | {.AsmStrOffset: 14458, .AliasCondStart: 5494, .NumOperands: 4, .NumConds: 7 }, |
| 25380 | // AArch64::ST1W_2Z_IMM - 852 |
| 25381 | {.AsmStrOffset: 14478, .AliasCondStart: 5501, .NumOperands: 4, .NumConds: 8 }, |
| 25382 | // AArch64::ST1W_2Z_STRIDED_IMM - 853 |
| 25383 | {.AsmStrOffset: 14500, .AliasCondStart: 5509, .NumOperands: 4, .NumConds: 7 }, |
| 25384 | // AArch64::ST1W_4Z_IMM - 854 |
| 25385 | {.AsmStrOffset: 14478, .AliasCondStart: 5516, .NumOperands: 4, .NumConds: 8 }, |
| 25386 | // AArch64::ST1W_4Z_STRIDED_IMM - 855 |
| 25387 | {.AsmStrOffset: 14500, .AliasCondStart: 5524, .NumOperands: 4, .NumConds: 7 }, |
| 25388 | // AArch64::ST1W_D_IMM - 856 |
| 25389 | {.AsmStrOffset: 14522, .AliasCondStart: 5531, .NumOperands: 4, .NumConds: 8 }, |
| 25390 | // AArch64::ST1W_IMM - 857 |
| 25391 | {.AsmStrOffset: 14544, .AliasCondStart: 5539, .NumOperands: 4, .NumConds: 8 }, |
| 25392 | // AArch64::ST1W_Q_IMM - 858 |
| 25393 | {.AsmStrOffset: 14566, .AliasCondStart: 5547, .NumOperands: 4, .NumConds: 7 }, |
| 25394 | // AArch64::ST1_MXIPXX_H_B - 859 |
| 25395 | {.AsmStrOffset: 14588, .AliasCondStart: 5554, .NumOperands: 6, .NumConds: 9 }, |
| 25396 | // AArch64::ST1_MXIPXX_H_D - 860 |
| 25397 | {.AsmStrOffset: 14622, .AliasCondStart: 5563, .NumOperands: 6, .NumConds: 9 }, |
| 25398 | // AArch64::ST1_MXIPXX_H_H - 861 |
| 25399 | {.AsmStrOffset: 14656, .AliasCondStart: 5572, .NumOperands: 6, .NumConds: 9 }, |
| 25400 | // AArch64::ST1_MXIPXX_H_Q - 862 |
| 25401 | {.AsmStrOffset: 14690, .AliasCondStart: 5581, .NumOperands: 6, .NumConds: 9 }, |
| 25402 | // AArch64::ST1_MXIPXX_H_S - 863 |
| 25403 | {.AsmStrOffset: 14724, .AliasCondStart: 5590, .NumOperands: 6, .NumConds: 9 }, |
| 25404 | // AArch64::ST1_MXIPXX_V_B - 864 |
| 25405 | {.AsmStrOffset: 14758, .AliasCondStart: 5599, .NumOperands: 6, .NumConds: 9 }, |
| 25406 | // AArch64::ST1_MXIPXX_V_D - 865 |
| 25407 | {.AsmStrOffset: 14792, .AliasCondStart: 5608, .NumOperands: 6, .NumConds: 9 }, |
| 25408 | // AArch64::ST1_MXIPXX_V_H - 866 |
| 25409 | {.AsmStrOffset: 14826, .AliasCondStart: 5617, .NumOperands: 6, .NumConds: 9 }, |
| 25410 | // AArch64::ST1_MXIPXX_V_Q - 867 |
| 25411 | {.AsmStrOffset: 14860, .AliasCondStart: 5626, .NumOperands: 6, .NumConds: 9 }, |
| 25412 | // AArch64::ST1_MXIPXX_V_S - 868 |
| 25413 | {.AsmStrOffset: 14894, .AliasCondStart: 5635, .NumOperands: 6, .NumConds: 9 }, |
| 25414 | // AArch64::ST1i16_POST - 869 |
| 25415 | {.AsmStrOffset: 14928, .AliasCondStart: 5644, .NumOperands: 5, .NumConds: 8 }, |
| 25416 | // AArch64::ST1i32_POST - 870 |
| 25417 | {.AsmStrOffset: 14951, .AliasCondStart: 5652, .NumOperands: 5, .NumConds: 8 }, |
| 25418 | // AArch64::ST1i64_POST - 871 |
| 25419 | {.AsmStrOffset: 14974, .AliasCondStart: 5660, .NumOperands: 5, .NumConds: 8 }, |
| 25420 | // AArch64::ST1i8_POST - 872 |
| 25421 | {.AsmStrOffset: 14997, .AliasCondStart: 5668, .NumOperands: 5, .NumConds: 8 }, |
| 25422 | // AArch64::ST2B_IMM - 873 |
| 25423 | {.AsmStrOffset: 15020, .AliasCondStart: 5676, .NumOperands: 4, .NumConds: 8 }, |
| 25424 | // AArch64::ST2D_IMM - 874 |
| 25425 | {.AsmStrOffset: 15042, .AliasCondStart: 5684, .NumOperands: 4, .NumConds: 8 }, |
| 25426 | // AArch64::ST2Gi - 875 |
| 25427 | {.AsmStrOffset: 15064, .AliasCondStart: 5692, .NumOperands: 3, .NumConds: 6 }, |
| 25428 | // AArch64::ST2H_IMM - 876 |
| 25429 | {.AsmStrOffset: 15078, .AliasCondStart: 5698, .NumOperands: 4, .NumConds: 8 }, |
| 25430 | // AArch64::ST2Q_IMM - 877 |
| 25431 | {.AsmStrOffset: 15100, .AliasCondStart: 5706, .NumOperands: 4, .NumConds: 8 }, |
| 25432 | // AArch64::ST2Twov16b_POST - 878 |
| 25433 | {.AsmStrOffset: 15122, .AliasCondStart: 5714, .NumOperands: 4, .NumConds: 7 }, |
| 25434 | // AArch64::ST2Twov2d_POST - 879 |
| 25435 | {.AsmStrOffset: 15142, .AliasCondStart: 5721, .NumOperands: 4, .NumConds: 7 }, |
| 25436 | // AArch64::ST2Twov2s_POST - 880 |
| 25437 | {.AsmStrOffset: 15162, .AliasCondStart: 5728, .NumOperands: 4, .NumConds: 7 }, |
| 25438 | // AArch64::ST2Twov4h_POST - 881 |
| 25439 | {.AsmStrOffset: 15182, .AliasCondStart: 5735, .NumOperands: 4, .NumConds: 7 }, |
| 25440 | // AArch64::ST2Twov4s_POST - 882 |
| 25441 | {.AsmStrOffset: 15202, .AliasCondStart: 5742, .NumOperands: 4, .NumConds: 7 }, |
| 25442 | // AArch64::ST2Twov8b_POST - 883 |
| 25443 | {.AsmStrOffset: 15222, .AliasCondStart: 5749, .NumOperands: 4, .NumConds: 7 }, |
| 25444 | // AArch64::ST2Twov8h_POST - 884 |
| 25445 | {.AsmStrOffset: 15242, .AliasCondStart: 5756, .NumOperands: 4, .NumConds: 7 }, |
| 25446 | // AArch64::ST2W_IMM - 885 |
| 25447 | {.AsmStrOffset: 15262, .AliasCondStart: 5763, .NumOperands: 4, .NumConds: 8 }, |
| 25448 | // AArch64::ST2i16_POST - 886 |
| 25449 | {.AsmStrOffset: 15284, .AliasCondStart: 5771, .NumOperands: 5, .NumConds: 8 }, |
| 25450 | // AArch64::ST2i32_POST - 887 |
| 25451 | {.AsmStrOffset: 15307, .AliasCondStart: 5779, .NumOperands: 5, .NumConds: 8 }, |
| 25452 | // AArch64::ST2i64_POST - 888 |
| 25453 | {.AsmStrOffset: 15330, .AliasCondStart: 5787, .NumOperands: 5, .NumConds: 8 }, |
| 25454 | // AArch64::ST2i8_POST - 889 |
| 25455 | {.AsmStrOffset: 15354, .AliasCondStart: 5795, .NumOperands: 5, .NumConds: 8 }, |
| 25456 | // AArch64::ST3B_IMM - 890 |
| 25457 | {.AsmStrOffset: 15377, .AliasCondStart: 5803, .NumOperands: 4, .NumConds: 8 }, |
| 25458 | // AArch64::ST3D_IMM - 891 |
| 25459 | {.AsmStrOffset: 15399, .AliasCondStart: 5811, .NumOperands: 4, .NumConds: 8 }, |
| 25460 | // AArch64::ST3H_IMM - 892 |
| 25461 | {.AsmStrOffset: 15421, .AliasCondStart: 5819, .NumOperands: 4, .NumConds: 8 }, |
| 25462 | // AArch64::ST3Q_IMM - 893 |
| 25463 | {.AsmStrOffset: 15443, .AliasCondStart: 5827, .NumOperands: 4, .NumConds: 8 }, |
| 25464 | // AArch64::ST3Threev16b_POST - 894 |
| 25465 | {.AsmStrOffset: 15465, .AliasCondStart: 5835, .NumOperands: 4, .NumConds: 7 }, |
| 25466 | // AArch64::ST3Threev2d_POST - 895 |
| 25467 | {.AsmStrOffset: 15485, .AliasCondStart: 5842, .NumOperands: 4, .NumConds: 7 }, |
| 25468 | // AArch64::ST3Threev2s_POST - 896 |
| 25469 | {.AsmStrOffset: 15505, .AliasCondStart: 5849, .NumOperands: 4, .NumConds: 7 }, |
| 25470 | // AArch64::ST3Threev4h_POST - 897 |
| 25471 | {.AsmStrOffset: 15525, .AliasCondStart: 5856, .NumOperands: 4, .NumConds: 7 }, |
| 25472 | // AArch64::ST3Threev4s_POST - 898 |
| 25473 | {.AsmStrOffset: 15545, .AliasCondStart: 5863, .NumOperands: 4, .NumConds: 7 }, |
| 25474 | // AArch64::ST3Threev8b_POST - 899 |
| 25475 | {.AsmStrOffset: 15565, .AliasCondStart: 5870, .NumOperands: 4, .NumConds: 7 }, |
| 25476 | // AArch64::ST3Threev8h_POST - 900 |
| 25477 | {.AsmStrOffset: 15585, .AliasCondStart: 5877, .NumOperands: 4, .NumConds: 7 }, |
| 25478 | // AArch64::ST3W_IMM - 901 |
| 25479 | {.AsmStrOffset: 15605, .AliasCondStart: 5884, .NumOperands: 4, .NumConds: 8 }, |
| 25480 | // AArch64::ST3i16_POST - 902 |
| 25481 | {.AsmStrOffset: 15627, .AliasCondStart: 5892, .NumOperands: 5, .NumConds: 8 }, |
| 25482 | // AArch64::ST3i32_POST - 903 |
| 25483 | {.AsmStrOffset: 15650, .AliasCondStart: 5900, .NumOperands: 5, .NumConds: 8 }, |
| 25484 | // AArch64::ST3i64_POST - 904 |
| 25485 | {.AsmStrOffset: 15674, .AliasCondStart: 5908, .NumOperands: 5, .NumConds: 8 }, |
| 25486 | // AArch64::ST3i8_POST - 905 |
| 25487 | {.AsmStrOffset: 15698, .AliasCondStart: 5916, .NumOperands: 5, .NumConds: 8 }, |
| 25488 | // AArch64::ST4B_IMM - 906 |
| 25489 | {.AsmStrOffset: 15721, .AliasCondStart: 5924, .NumOperands: 4, .NumConds: 8 }, |
| 25490 | // AArch64::ST4D_IMM - 907 |
| 25491 | {.AsmStrOffset: 15743, .AliasCondStart: 5932, .NumOperands: 4, .NumConds: 8 }, |
| 25492 | // AArch64::ST4Fourv16b_POST - 908 |
| 25493 | {.AsmStrOffset: 15765, .AliasCondStart: 5940, .NumOperands: 4, .NumConds: 7 }, |
| 25494 | // AArch64::ST4Fourv2d_POST - 909 |
| 25495 | {.AsmStrOffset: 15785, .AliasCondStart: 5947, .NumOperands: 4, .NumConds: 7 }, |
| 25496 | // AArch64::ST4Fourv2s_POST - 910 |
| 25497 | {.AsmStrOffset: 15805, .AliasCondStart: 5954, .NumOperands: 4, .NumConds: 7 }, |
| 25498 | // AArch64::ST4Fourv4h_POST - 911 |
| 25499 | {.AsmStrOffset: 15825, .AliasCondStart: 5961, .NumOperands: 4, .NumConds: 7 }, |
| 25500 | // AArch64::ST4Fourv4s_POST - 912 |
| 25501 | {.AsmStrOffset: 15845, .AliasCondStart: 5968, .NumOperands: 4, .NumConds: 7 }, |
| 25502 | // AArch64::ST4Fourv8b_POST - 913 |
| 25503 | {.AsmStrOffset: 15865, .AliasCondStart: 5975, .NumOperands: 4, .NumConds: 7 }, |
| 25504 | // AArch64::ST4Fourv8h_POST - 914 |
| 25505 | {.AsmStrOffset: 15885, .AliasCondStart: 5982, .NumOperands: 4, .NumConds: 7 }, |
| 25506 | // AArch64::ST4H_IMM - 915 |
| 25507 | {.AsmStrOffset: 15905, .AliasCondStart: 5989, .NumOperands: 4, .NumConds: 8 }, |
| 25508 | // AArch64::ST4Q_IMM - 916 |
| 25509 | {.AsmStrOffset: 15927, .AliasCondStart: 5997, .NumOperands: 4, .NumConds: 8 }, |
| 25510 | // AArch64::ST4W_IMM - 917 |
| 25511 | {.AsmStrOffset: 15949, .AliasCondStart: 6005, .NumOperands: 4, .NumConds: 8 }, |
| 25512 | // AArch64::ST4i16_POST - 918 |
| 25513 | {.AsmStrOffset: 15971, .AliasCondStart: 6013, .NumOperands: 5, .NumConds: 8 }, |
| 25514 | // AArch64::ST4i32_POST - 919 |
| 25515 | {.AsmStrOffset: 15994, .AliasCondStart: 6021, .NumOperands: 5, .NumConds: 8 }, |
| 25516 | // AArch64::ST4i64_POST - 920 |
| 25517 | {.AsmStrOffset: 16018, .AliasCondStart: 6029, .NumOperands: 5, .NumConds: 8 }, |
| 25518 | // AArch64::ST4i8_POST - 921 |
| 25519 | {.AsmStrOffset: 16042, .AliasCondStart: 6037, .NumOperands: 5, .NumConds: 8 }, |
| 25520 | // AArch64::STGPi - 922 |
| 25521 | {.AsmStrOffset: 16065, .AliasCondStart: 6045, .NumOperands: 4, .NumConds: 7 }, |
| 25522 | // AArch64::STGi - 923 |
| 25523 | {.AsmStrOffset: 16083, .AliasCondStart: 6052, .NumOperands: 3, .NumConds: 6 }, |
| 25524 | // AArch64::STLURBi - 924 |
| 25525 | {.AsmStrOffset: 16096, .AliasCondStart: 6058, .NumOperands: 3, .NumConds: 6 }, |
| 25526 | // AArch64::STLURHi - 925 |
| 25527 | {.AsmStrOffset: 16112, .AliasCondStart: 6064, .NumOperands: 3, .NumConds: 6 }, |
| 25528 | // AArch64::STLURWi - 926 |
| 25529 | {.AsmStrOffset: 16128, .AliasCondStart: 6070, .NumOperands: 3, .NumConds: 6 }, |
| 25530 | // AArch64::STLURXi - 927 |
| 25531 | {.AsmStrOffset: 16128, .AliasCondStart: 6076, .NumOperands: 3, .NumConds: 6 }, |
| 25532 | // AArch64::STLURbi - 928 |
| 25533 | {.AsmStrOffset: 16128, .AliasCondStart: 6082, .NumOperands: 3, .NumConds: 9 }, |
| 25534 | // AArch64::STLURdi - 929 |
| 25535 | {.AsmStrOffset: 16128, .AliasCondStart: 6091, .NumOperands: 3, .NumConds: 9 }, |
| 25536 | // AArch64::STLURhi - 930 |
| 25537 | {.AsmStrOffset: 16128, .AliasCondStart: 6100, .NumOperands: 3, .NumConds: 9 }, |
| 25538 | // AArch64::STLURqi - 931 |
| 25539 | {.AsmStrOffset: 16128, .AliasCondStart: 6109, .NumOperands: 3, .NumConds: 9 }, |
| 25540 | // AArch64::STLURsi - 932 |
| 25541 | {.AsmStrOffset: 16128, .AliasCondStart: 6118, .NumOperands: 3, .NumConds: 9 }, |
| 25542 | // AArch64::STNPDi - 933 |
| 25543 | {.AsmStrOffset: 16143, .AliasCondStart: 6127, .NumOperands: 4, .NumConds: 7 }, |
| 25544 | // AArch64::STNPQi - 934 |
| 25545 | {.AsmStrOffset: 16143, .AliasCondStart: 6134, .NumOperands: 4, .NumConds: 7 }, |
| 25546 | // AArch64::STNPSi - 935 |
| 25547 | {.AsmStrOffset: 16143, .AliasCondStart: 6141, .NumOperands: 4, .NumConds: 7 }, |
| 25548 | // AArch64::STNPWi - 936 |
| 25549 | {.AsmStrOffset: 16143, .AliasCondStart: 6148, .NumOperands: 4, .NumConds: 4 }, |
| 25550 | // AArch64::STNPXi - 937 |
| 25551 | {.AsmStrOffset: 16143, .AliasCondStart: 6152, .NumOperands: 4, .NumConds: 4 }, |
| 25552 | // AArch64::STNT1B_2Z_IMM - 938 |
| 25553 | {.AsmStrOffset: 16161, .AliasCondStart: 6156, .NumOperands: 4, .NumConds: 8 }, |
| 25554 | // AArch64::STNT1B_2Z_STRIDED_IMM - 939 |
| 25555 | {.AsmStrOffset: 16185, .AliasCondStart: 6164, .NumOperands: 4, .NumConds: 7 }, |
| 25556 | // AArch64::STNT1B_4Z_IMM - 940 |
| 25557 | {.AsmStrOffset: 16161, .AliasCondStart: 6171, .NumOperands: 4, .NumConds: 8 }, |
| 25558 | // AArch64::STNT1B_4Z_STRIDED_IMM - 941 |
| 25559 | {.AsmStrOffset: 16209, .AliasCondStart: 6179, .NumOperands: 4, .NumConds: 7 }, |
| 25560 | // AArch64::STNT1B_ZRI - 942 |
| 25561 | {.AsmStrOffset: 16233, .AliasCondStart: 6186, .NumOperands: 4, .NumConds: 8 }, |
| 25562 | // AArch64::STNT1B_ZZR_D - 943 |
| 25563 | {.AsmStrOffset: 16257, .AliasCondStart: 6194, .NumOperands: 4, .NumConds: 7 }, |
| 25564 | // AArch64::STNT1B_ZZR_S - 944 |
| 25565 | {.AsmStrOffset: 16283, .AliasCondStart: 6201, .NumOperands: 4, .NumConds: 7 }, |
| 25566 | // AArch64::STNT1D_2Z_IMM - 945 |
| 25567 | {.AsmStrOffset: 16309, .AliasCondStart: 6208, .NumOperands: 4, .NumConds: 8 }, |
| 25568 | // AArch64::STNT1D_2Z_STRIDED_IMM - 946 |
| 25569 | {.AsmStrOffset: 16333, .AliasCondStart: 6216, .NumOperands: 4, .NumConds: 7 }, |
| 25570 | // AArch64::STNT1D_4Z_IMM - 947 |
| 25571 | {.AsmStrOffset: 16309, .AliasCondStart: 6223, .NumOperands: 4, .NumConds: 8 }, |
| 25572 | // AArch64::STNT1D_4Z_STRIDED_IMM - 948 |
| 25573 | {.AsmStrOffset: 16333, .AliasCondStart: 6231, .NumOperands: 4, .NumConds: 7 }, |
| 25574 | // AArch64::STNT1D_ZRI - 949 |
| 25575 | {.AsmStrOffset: 16357, .AliasCondStart: 6238, .NumOperands: 4, .NumConds: 8 }, |
| 25576 | // AArch64::STNT1D_ZZR_D - 950 |
| 25577 | {.AsmStrOffset: 16381, .AliasCondStart: 6246, .NumOperands: 4, .NumConds: 7 }, |
| 25578 | // AArch64::STNT1H_2Z_IMM - 951 |
| 25579 | {.AsmStrOffset: 16407, .AliasCondStart: 6253, .NumOperands: 4, .NumConds: 8 }, |
| 25580 | // AArch64::STNT1H_2Z_STRIDED_IMM - 952 |
| 25581 | {.AsmStrOffset: 16431, .AliasCondStart: 6261, .NumOperands: 4, .NumConds: 7 }, |
| 25582 | // AArch64::STNT1H_4Z_IMM - 953 |
| 25583 | {.AsmStrOffset: 16407, .AliasCondStart: 6268, .NumOperands: 4, .NumConds: 8 }, |
| 25584 | // AArch64::STNT1H_4Z_STRIDED_IMM - 954 |
| 25585 | {.AsmStrOffset: 16455, .AliasCondStart: 6276, .NumOperands: 4, .NumConds: 7 }, |
| 25586 | // AArch64::STNT1H_ZRI - 955 |
| 25587 | {.AsmStrOffset: 16479, .AliasCondStart: 6283, .NumOperands: 4, .NumConds: 8 }, |
| 25588 | // AArch64::STNT1H_ZZR_D - 956 |
| 25589 | {.AsmStrOffset: 16503, .AliasCondStart: 6291, .NumOperands: 4, .NumConds: 7 }, |
| 25590 | // AArch64::STNT1H_ZZR_S - 957 |
| 25591 | {.AsmStrOffset: 16529, .AliasCondStart: 6298, .NumOperands: 4, .NumConds: 7 }, |
| 25592 | // AArch64::STNT1W_2Z_IMM - 958 |
| 25593 | {.AsmStrOffset: 16555, .AliasCondStart: 6305, .NumOperands: 4, .NumConds: 8 }, |
| 25594 | // AArch64::STNT1W_2Z_STRIDED_IMM - 959 |
| 25595 | {.AsmStrOffset: 16579, .AliasCondStart: 6313, .NumOperands: 4, .NumConds: 7 }, |
| 25596 | // AArch64::STNT1W_4Z_IMM - 960 |
| 25597 | {.AsmStrOffset: 16555, .AliasCondStart: 6320, .NumOperands: 4, .NumConds: 8 }, |
| 25598 | // AArch64::STNT1W_4Z_STRIDED_IMM - 961 |
| 25599 | {.AsmStrOffset: 16579, .AliasCondStart: 6328, .NumOperands: 4, .NumConds: 7 }, |
| 25600 | // AArch64::STNT1W_ZRI - 962 |
| 25601 | {.AsmStrOffset: 16603, .AliasCondStart: 6335, .NumOperands: 4, .NumConds: 8 }, |
| 25602 | // AArch64::STNT1W_ZZR_D - 963 |
| 25603 | {.AsmStrOffset: 16627, .AliasCondStart: 6343, .NumOperands: 4, .NumConds: 7 }, |
| 25604 | // AArch64::STNT1W_ZZR_S - 964 |
| 25605 | {.AsmStrOffset: 16653, .AliasCondStart: 6350, .NumOperands: 4, .NumConds: 7 }, |
| 25606 | // AArch64::STPDi - 965 |
| 25607 | {.AsmStrOffset: 16679, .AliasCondStart: 6357, .NumOperands: 4, .NumConds: 7 }, |
| 25608 | // AArch64::STPQi - 966 |
| 25609 | {.AsmStrOffset: 16679, .AliasCondStart: 6364, .NumOperands: 4, .NumConds: 7 }, |
| 25610 | // AArch64::STPSi - 967 |
| 25611 | {.AsmStrOffset: 16679, .AliasCondStart: 6371, .NumOperands: 4, .NumConds: 7 }, |
| 25612 | // AArch64::STPWi - 968 |
| 25613 | {.AsmStrOffset: 16679, .AliasCondStart: 6378, .NumOperands: 4, .NumConds: 4 }, |
| 25614 | // AArch64::STPXi - 969 |
| 25615 | {.AsmStrOffset: 16679, .AliasCondStart: 6382, .NumOperands: 4, .NumConds: 4 }, |
| 25616 | // AArch64::STRBBroX - 970 |
| 25617 | {.AsmStrOffset: 16696, .AliasCondStart: 6386, .NumOperands: 5, .NumConds: 5 }, |
| 25618 | // AArch64::STRBBui - 971 |
| 25619 | {.AsmStrOffset: 16714, .AliasCondStart: 6391, .NumOperands: 3, .NumConds: 3 }, |
| 25620 | // AArch64::STRBroX - 972 |
| 25621 | {.AsmStrOffset: 16728, .AliasCondStart: 6394, .NumOperands: 5, .NumConds: 8 }, |
| 25622 | // AArch64::STRBui - 973 |
| 25623 | {.AsmStrOffset: 16745, .AliasCondStart: 6402, .NumOperands: 3, .NumConds: 6 }, |
| 25624 | // AArch64::STRDroX - 974 |
| 25625 | {.AsmStrOffset: 16728, .AliasCondStart: 6408, .NumOperands: 5, .NumConds: 8 }, |
| 25626 | // AArch64::STRDui - 975 |
| 25627 | {.AsmStrOffset: 16745, .AliasCondStart: 6416, .NumOperands: 3, .NumConds: 6 }, |
| 25628 | // AArch64::STRHHroX - 976 |
| 25629 | {.AsmStrOffset: 16758, .AliasCondStart: 6422, .NumOperands: 5, .NumConds: 5 }, |
| 25630 | // AArch64::STRHHui - 977 |
| 25631 | {.AsmStrOffset: 16776, .AliasCondStart: 6427, .NumOperands: 3, .NumConds: 3 }, |
| 25632 | // AArch64::STRHroX - 978 |
| 25633 | {.AsmStrOffset: 16728, .AliasCondStart: 6430, .NumOperands: 5, .NumConds: 8 }, |
| 25634 | // AArch64::STRHui - 979 |
| 25635 | {.AsmStrOffset: 16745, .AliasCondStart: 6438, .NumOperands: 3, .NumConds: 6 }, |
| 25636 | // AArch64::STRQroX - 980 |
| 25637 | {.AsmStrOffset: 16728, .AliasCondStart: 6444, .NumOperands: 5, .NumConds: 8 }, |
| 25638 | // AArch64::STRQui - 981 |
| 25639 | {.AsmStrOffset: 16745, .AliasCondStart: 6452, .NumOperands: 3, .NumConds: 6 }, |
| 25640 | // AArch64::STRSroX - 982 |
| 25641 | {.AsmStrOffset: 16728, .AliasCondStart: 6458, .NumOperands: 5, .NumConds: 8 }, |
| 25642 | // AArch64::STRSui - 983 |
| 25643 | {.AsmStrOffset: 16745, .AliasCondStart: 6466, .NumOperands: 3, .NumConds: 6 }, |
| 25644 | // AArch64::STRWroX - 984 |
| 25645 | {.AsmStrOffset: 16728, .AliasCondStart: 6472, .NumOperands: 5, .NumConds: 5 }, |
| 25646 | // AArch64::STRWui - 985 |
| 25647 | {.AsmStrOffset: 16745, .AliasCondStart: 6477, .NumOperands: 3, .NumConds: 3 }, |
| 25648 | // AArch64::STRXroX - 986 |
| 25649 | {.AsmStrOffset: 16728, .AliasCondStart: 6480, .NumOperands: 5, .NumConds: 5 }, |
| 25650 | // AArch64::STRXui - 987 |
| 25651 | {.AsmStrOffset: 16745, .AliasCondStart: 6485, .NumOperands: 3, .NumConds: 3 }, |
| 25652 | // AArch64::STR_PXI - 988 |
| 25653 | {.AsmStrOffset: 16790, .AliasCondStart: 6488, .NumOperands: 3, .NumConds: 7 }, |
| 25654 | // AArch64::STR_ZA - 989 |
| 25655 | {.AsmStrOffset: 16805, .AliasCondStart: 6495, .NumOperands: 5, .NumConds: 8 }, |
| 25656 | // AArch64::STR_ZXI - 990 |
| 25657 | {.AsmStrOffset: 16790, .AliasCondStart: 6503, .NumOperands: 3, .NumConds: 7 }, |
| 25658 | // AArch64::STTRBi - 991 |
| 25659 | {.AsmStrOffset: 16830, .AliasCondStart: 6510, .NumOperands: 3, .NumConds: 3 }, |
| 25660 | // AArch64::STTRHi - 992 |
| 25661 | {.AsmStrOffset: 16845, .AliasCondStart: 6513, .NumOperands: 3, .NumConds: 3 }, |
| 25662 | // AArch64::STTRWi - 993 |
| 25663 | {.AsmStrOffset: 16860, .AliasCondStart: 6516, .NumOperands: 3, .NumConds: 3 }, |
| 25664 | // AArch64::STTRXi - 994 |
| 25665 | {.AsmStrOffset: 16860, .AliasCondStart: 6519, .NumOperands: 3, .NumConds: 3 }, |
| 25666 | // AArch64::STURBBi - 995 |
| 25667 | {.AsmStrOffset: 16874, .AliasCondStart: 6522, .NumOperands: 3, .NumConds: 3 }, |
| 25668 | // AArch64::STURBi - 996 |
| 25669 | {.AsmStrOffset: 16889, .AliasCondStart: 6525, .NumOperands: 3, .NumConds: 6 }, |
| 25670 | // AArch64::STURDi - 997 |
| 25671 | {.AsmStrOffset: 16889, .AliasCondStart: 6531, .NumOperands: 3, .NumConds: 6 }, |
| 25672 | // AArch64::STURHHi - 998 |
| 25673 | {.AsmStrOffset: 16903, .AliasCondStart: 6537, .NumOperands: 3, .NumConds: 3 }, |
| 25674 | // AArch64::STURHi - 999 |
| 25675 | {.AsmStrOffset: 16889, .AliasCondStart: 6540, .NumOperands: 3, .NumConds: 6 }, |
| 25676 | // AArch64::STURQi - 1000 |
| 25677 | {.AsmStrOffset: 16889, .AliasCondStart: 6546, .NumOperands: 3, .NumConds: 6 }, |
| 25678 | // AArch64::STURSi - 1001 |
| 25679 | {.AsmStrOffset: 16889, .AliasCondStart: 6552, .NumOperands: 3, .NumConds: 6 }, |
| 25680 | // AArch64::STURWi - 1002 |
| 25681 | {.AsmStrOffset: 16889, .AliasCondStart: 6558, .NumOperands: 3, .NumConds: 3 }, |
| 25682 | // AArch64::STURXi - 1003 |
| 25683 | {.AsmStrOffset: 16889, .AliasCondStart: 6561, .NumOperands: 3, .NumConds: 3 }, |
| 25684 | // AArch64::STZ2Gi - 1004 |
| 25685 | {.AsmStrOffset: 16918, .AliasCondStart: 6564, .NumOperands: 3, .NumConds: 6 }, |
| 25686 | // AArch64::STZGi - 1005 |
| 25687 | {.AsmStrOffset: 16933, .AliasCondStart: 6570, .NumOperands: 3, .NumConds: 6 }, |
| 25688 | // AArch64::SUBPT_shift - 1006 |
| 25689 | {.AsmStrOffset: 16947, .AliasCondStart: 6576, .NumOperands: 4, .NumConds: 7 }, |
| 25690 | // AArch64::SUBSWri - 1007 |
| 25691 | {.AsmStrOffset: 16964, .AliasCondStart: 6583, .NumOperands: 4, .NumConds: 2 }, |
| 25692 | // AArch64::SUBSWrs - 1008 |
| 25693 | {.AsmStrOffset: 16977, .AliasCondStart: 6585, .NumOperands: 4, .NumConds: 4 }, |
| 25694 | {.AsmStrOffset: 16988, .AliasCondStart: 6589, .NumOperands: 4, .NumConds: 3 }, |
| 25695 | {.AsmStrOffset: 17003, .AliasCondStart: 6592, .NumOperands: 4, .NumConds: 4 }, |
| 25696 | {.AsmStrOffset: 17015, .AliasCondStart: 6596, .NumOperands: 4, .NumConds: 3 }, |
| 25697 | {.AsmStrOffset: 17031, .AliasCondStart: 6599, .NumOperands: 4, .NumConds: 4 }, |
| 25698 | // AArch64::SUBSWrx - 1013 |
| 25699 | {.AsmStrOffset: 16977, .AliasCondStart: 6603, .NumOperands: 4, .NumConds: 4 }, |
| 25700 | {.AsmStrOffset: 17047, .AliasCondStart: 6607, .NumOperands: 4, .NumConds: 3 }, |
| 25701 | {.AsmStrOffset: 17031, .AliasCondStart: 6610, .NumOperands: 4, .NumConds: 4 }, |
| 25702 | // AArch64::SUBSXri - 1016 |
| 25703 | {.AsmStrOffset: 16964, .AliasCondStart: 6614, .NumOperands: 4, .NumConds: 2 }, |
| 25704 | // AArch64::SUBSXrs - 1017 |
| 25705 | {.AsmStrOffset: 16977, .AliasCondStart: 6616, .NumOperands: 4, .NumConds: 4 }, |
| 25706 | {.AsmStrOffset: 16988, .AliasCondStart: 6620, .NumOperands: 4, .NumConds: 3 }, |
| 25707 | {.AsmStrOffset: 17003, .AliasCondStart: 6623, .NumOperands: 4, .NumConds: 4 }, |
| 25708 | {.AsmStrOffset: 17015, .AliasCondStart: 6627, .NumOperands: 4, .NumConds: 3 }, |
| 25709 | {.AsmStrOffset: 17031, .AliasCondStart: 6630, .NumOperands: 4, .NumConds: 4 }, |
| 25710 | // AArch64::SUBSXrx - 1022 |
| 25711 | {.AsmStrOffset: 17047, .AliasCondStart: 6634, .NumOperands: 4, .NumConds: 3 }, |
| 25712 | // AArch64::SUBSXrx64 - 1023 |
| 25713 | {.AsmStrOffset: 16977, .AliasCondStart: 6637, .NumOperands: 4, .NumConds: 4 }, |
| 25714 | {.AsmStrOffset: 17047, .AliasCondStart: 6641, .NumOperands: 4, .NumConds: 3 }, |
| 25715 | {.AsmStrOffset: 17031, .AliasCondStart: 6644, .NumOperands: 4, .NumConds: 4 }, |
| 25716 | // AArch64::SUBWrs - 1026 |
| 25717 | {.AsmStrOffset: 17062, .AliasCondStart: 6648, .NumOperands: 4, .NumConds: 4 }, |
| 25718 | {.AsmStrOffset: 17073, .AliasCondStart: 6652, .NumOperands: 4, .NumConds: 3 }, |
| 25719 | {.AsmStrOffset: 17088, .AliasCondStart: 6655, .NumOperands: 4, .NumConds: 4 }, |
| 25720 | // AArch64::SUBWrx - 1029 |
| 25721 | {.AsmStrOffset: 17088, .AliasCondStart: 6659, .NumOperands: 4, .NumConds: 4 }, |
| 25722 | {.AsmStrOffset: 17088, .AliasCondStart: 6663, .NumOperands: 4, .NumConds: 4 }, |
| 25723 | // AArch64::SUBXrs - 1031 |
| 25724 | {.AsmStrOffset: 17062, .AliasCondStart: 6667, .NumOperands: 4, .NumConds: 4 }, |
| 25725 | {.AsmStrOffset: 17073, .AliasCondStart: 6671, .NumOperands: 4, .NumConds: 3 }, |
| 25726 | {.AsmStrOffset: 17088, .AliasCondStart: 6674, .NumOperands: 4, .NumConds: 4 }, |
| 25727 | // AArch64::SUBXrx64 - 1034 |
| 25728 | {.AsmStrOffset: 17088, .AliasCondStart: 6678, .NumOperands: 4, .NumConds: 4 }, |
| 25729 | {.AsmStrOffset: 17088, .AliasCondStart: 6682, .NumOperands: 4, .NumConds: 4 }, |
| 25730 | // AArch64::SYSPxt_XZR - 1036 |
| 25731 | {.AsmStrOffset: 17103, .AliasCondStart: 6686, .NumOperands: 5, .NumConds: 8 }, |
| 25732 | // AArch64::SYSxt - 1037 |
| 25733 | {.AsmStrOffset: 17127, .AliasCondStart: 6694, .NumOperands: 5, .NumConds: 5 }, |
| 25734 | // AArch64::UBFMWri - 1038 |
| 25735 | {.AsmStrOffset: 17150, .AliasCondStart: 6699, .NumOperands: 4, .NumConds: 4 }, |
| 25736 | {.AsmStrOffset: 17165, .AliasCondStart: 6703, .NumOperands: 4, .NumConds: 4 }, |
| 25737 | {.AsmStrOffset: 17177, .AliasCondStart: 6707, .NumOperands: 4, .NumConds: 4 }, |
| 25738 | // AArch64::UBFMXri - 1041 |
| 25739 | {.AsmStrOffset: 17150, .AliasCondStart: 6711, .NumOperands: 4, .NumConds: 4 }, |
| 25740 | {.AsmStrOffset: 17165, .AliasCondStart: 6715, .NumOperands: 4, .NumConds: 4 }, |
| 25741 | {.AsmStrOffset: 17177, .AliasCondStart: 6719, .NumOperands: 4, .NumConds: 4 }, |
| 25742 | {.AsmStrOffset: 17189, .AliasCondStart: 6723, .NumOperands: 4, .NumConds: 4 }, |
| 25743 | // AArch64::UMADDLrrr - 1045 |
| 25744 | {.AsmStrOffset: 17201, .AliasCondStart: 6727, .NumOperands: 4, .NumConds: 4 }, |
| 25745 | // AArch64::UMOVvi32 - 1046 |
| 25746 | {.AsmStrOffset: 17218, .AliasCondStart: 6731, .NumOperands: 3, .NumConds: 5 }, |
| 25747 | // AArch64::UMOVvi32_idx0 - 1047 |
| 25748 | {.AsmStrOffset: 17218, .AliasCondStart: 6736, .NumOperands: 3, .NumConds: 5 }, |
| 25749 | // AArch64::UMOVvi64 - 1048 |
| 25750 | {.AsmStrOffset: 17237, .AliasCondStart: 6741, .NumOperands: 3, .NumConds: 5 }, |
| 25751 | // AArch64::UMOVvi64_idx0 - 1049 |
| 25752 | {.AsmStrOffset: 17237, .AliasCondStart: 6746, .NumOperands: 3, .NumConds: 5 }, |
| 25753 | // AArch64::UMSUBLrrr - 1050 |
| 25754 | {.AsmStrOffset: 17256, .AliasCondStart: 6751, .NumOperands: 4, .NumConds: 4 }, |
| 25755 | // AArch64::UQDECB_WPiI - 1051 |
| 25756 | {.AsmStrOffset: 17274, .AliasCondStart: 6755, .NumOperands: 4, .NumConds: 8 }, |
| 25757 | {.AsmStrOffset: 17284, .AliasCondStart: 6763, .NumOperands: 4, .NumConds: 8 }, |
| 25758 | // AArch64::UQDECB_XPiI - 1053 |
| 25759 | {.AsmStrOffset: 17274, .AliasCondStart: 6771, .NumOperands: 4, .NumConds: 8 }, |
| 25760 | {.AsmStrOffset: 17284, .AliasCondStart: 6779, .NumOperands: 4, .NumConds: 8 }, |
| 25761 | // AArch64::UQDECD_WPiI - 1055 |
| 25762 | {.AsmStrOffset: 17300, .AliasCondStart: 6787, .NumOperands: 4, .NumConds: 8 }, |
| 25763 | {.AsmStrOffset: 17310, .AliasCondStart: 6795, .NumOperands: 4, .NumConds: 8 }, |
| 25764 | // AArch64::UQDECD_XPiI - 1057 |
| 25765 | {.AsmStrOffset: 17300, .AliasCondStart: 6803, .NumOperands: 4, .NumConds: 8 }, |
| 25766 | {.AsmStrOffset: 17310, .AliasCondStart: 6811, .NumOperands: 4, .NumConds: 8 }, |
| 25767 | // AArch64::UQDECD_ZPiI - 1059 |
| 25768 | {.AsmStrOffset: 17326, .AliasCondStart: 6819, .NumOperands: 4, .NumConds: 8 }, |
| 25769 | {.AsmStrOffset: 17338, .AliasCondStart: 6827, .NumOperands: 4, .NumConds: 8 }, |
| 25770 | // AArch64::UQDECH_WPiI - 1061 |
| 25771 | {.AsmStrOffset: 17356, .AliasCondStart: 6835, .NumOperands: 4, .NumConds: 8 }, |
| 25772 | {.AsmStrOffset: 17366, .AliasCondStart: 6843, .NumOperands: 4, .NumConds: 8 }, |
| 25773 | // AArch64::UQDECH_XPiI - 1063 |
| 25774 | {.AsmStrOffset: 17356, .AliasCondStart: 6851, .NumOperands: 4, .NumConds: 8 }, |
| 25775 | {.AsmStrOffset: 17366, .AliasCondStart: 6859, .NumOperands: 4, .NumConds: 8 }, |
| 25776 | // AArch64::UQDECH_ZPiI - 1065 |
| 25777 | {.AsmStrOffset: 17382, .AliasCondStart: 6867, .NumOperands: 4, .NumConds: 8 }, |
| 25778 | {.AsmStrOffset: 17394, .AliasCondStart: 6875, .NumOperands: 4, .NumConds: 8 }, |
| 25779 | // AArch64::UQDECW_WPiI - 1067 |
| 25780 | {.AsmStrOffset: 17412, .AliasCondStart: 6883, .NumOperands: 4, .NumConds: 8 }, |
| 25781 | {.AsmStrOffset: 17422, .AliasCondStart: 6891, .NumOperands: 4, .NumConds: 8 }, |
| 25782 | // AArch64::UQDECW_XPiI - 1069 |
| 25783 | {.AsmStrOffset: 17412, .AliasCondStart: 6899, .NumOperands: 4, .NumConds: 8 }, |
| 25784 | {.AsmStrOffset: 17422, .AliasCondStart: 6907, .NumOperands: 4, .NumConds: 8 }, |
| 25785 | // AArch64::UQDECW_ZPiI - 1071 |
| 25786 | {.AsmStrOffset: 17438, .AliasCondStart: 6915, .NumOperands: 4, .NumConds: 8 }, |
| 25787 | {.AsmStrOffset: 17450, .AliasCondStart: 6923, .NumOperands: 4, .NumConds: 8 }, |
| 25788 | // AArch64::UQINCB_WPiI - 1073 |
| 25789 | {.AsmStrOffset: 17468, .AliasCondStart: 6931, .NumOperands: 4, .NumConds: 8 }, |
| 25790 | {.AsmStrOffset: 17478, .AliasCondStart: 6939, .NumOperands: 4, .NumConds: 8 }, |
| 25791 | // AArch64::UQINCB_XPiI - 1075 |
| 25792 | {.AsmStrOffset: 17468, .AliasCondStart: 6947, .NumOperands: 4, .NumConds: 8 }, |
| 25793 | {.AsmStrOffset: 17478, .AliasCondStart: 6955, .NumOperands: 4, .NumConds: 8 }, |
| 25794 | // AArch64::UQINCD_WPiI - 1077 |
| 25795 | {.AsmStrOffset: 17494, .AliasCondStart: 6963, .NumOperands: 4, .NumConds: 8 }, |
| 25796 | {.AsmStrOffset: 17504, .AliasCondStart: 6971, .NumOperands: 4, .NumConds: 8 }, |
| 25797 | // AArch64::UQINCD_XPiI - 1079 |
| 25798 | {.AsmStrOffset: 17494, .AliasCondStart: 6979, .NumOperands: 4, .NumConds: 8 }, |
| 25799 | {.AsmStrOffset: 17504, .AliasCondStart: 6987, .NumOperands: 4, .NumConds: 8 }, |
| 25800 | // AArch64::UQINCD_ZPiI - 1081 |
| 25801 | {.AsmStrOffset: 17520, .AliasCondStart: 6995, .NumOperands: 4, .NumConds: 8 }, |
| 25802 | {.AsmStrOffset: 17532, .AliasCondStart: 7003, .NumOperands: 4, .NumConds: 8 }, |
| 25803 | // AArch64::UQINCH_WPiI - 1083 |
| 25804 | {.AsmStrOffset: 17550, .AliasCondStart: 7011, .NumOperands: 4, .NumConds: 8 }, |
| 25805 | {.AsmStrOffset: 17560, .AliasCondStart: 7019, .NumOperands: 4, .NumConds: 8 }, |
| 25806 | // AArch64::UQINCH_XPiI - 1085 |
| 25807 | {.AsmStrOffset: 17550, .AliasCondStart: 7027, .NumOperands: 4, .NumConds: 8 }, |
| 25808 | {.AsmStrOffset: 17560, .AliasCondStart: 7035, .NumOperands: 4, .NumConds: 8 }, |
| 25809 | // AArch64::UQINCH_ZPiI - 1087 |
| 25810 | {.AsmStrOffset: 17576, .AliasCondStart: 7043, .NumOperands: 4, .NumConds: 8 }, |
| 25811 | {.AsmStrOffset: 17588, .AliasCondStart: 7051, .NumOperands: 4, .NumConds: 8 }, |
| 25812 | // AArch64::UQINCW_WPiI - 1089 |
| 25813 | {.AsmStrOffset: 17606, .AliasCondStart: 7059, .NumOperands: 4, .NumConds: 8 }, |
| 25814 | {.AsmStrOffset: 17616, .AliasCondStart: 7067, .NumOperands: 4, .NumConds: 8 }, |
| 25815 | // AArch64::UQINCW_XPiI - 1091 |
| 25816 | {.AsmStrOffset: 17606, .AliasCondStart: 7075, .NumOperands: 4, .NumConds: 8 }, |
| 25817 | {.AsmStrOffset: 17616, .AliasCondStart: 7083, .NumOperands: 4, .NumConds: 8 }, |
| 25818 | // AArch64::UQINCW_ZPiI - 1093 |
| 25819 | {.AsmStrOffset: 17632, .AliasCondStart: 7091, .NumOperands: 4, .NumConds: 8 }, |
| 25820 | {.AsmStrOffset: 17644, .AliasCondStart: 7099, .NumOperands: 4, .NumConds: 8 }, |
| 25821 | // AArch64::XPACLRI - 1095 |
| 25822 | {.AsmStrOffset: 17662, .AliasCondStart: 7107, .NumOperands: 0, .NumConds: 3 }, |
| 25823 | // AArch64::ZERO_M - 1096 |
| 25824 | {.AsmStrOffset: 17670, .AliasCondStart: 7110, .NumOperands: 1, .NumConds: 4 }, |
| 25825 | {.AsmStrOffset: 17680, .AliasCondStart: 7114, .NumOperands: 1, .NumConds: 4 }, |
| 25826 | {.AsmStrOffset: 17693, .AliasCondStart: 7118, .NumOperands: 1, .NumConds: 4 }, |
| 25827 | {.AsmStrOffset: 17706, .AliasCondStart: 7122, .NumOperands: 1, .NumConds: 4 }, |
| 25828 | {.AsmStrOffset: 17719, .AliasCondStart: 7126, .NumOperands: 1, .NumConds: 4 }, |
| 25829 | {.AsmStrOffset: 17732, .AliasCondStart: 7130, .NumOperands: 1, .NumConds: 4 }, |
| 25830 | {.AsmStrOffset: 17745, .AliasCondStart: 7134, .NumOperands: 1, .NumConds: 4 }, |
| 25831 | {.AsmStrOffset: 17758, .AliasCondStart: 7138, .NumOperands: 1, .NumConds: 4 }, |
| 25832 | {.AsmStrOffset: 17777, .AliasCondStart: 7142, .NumOperands: 1, .NumConds: 4 }, |
| 25833 | {.AsmStrOffset: 17796, .AliasCondStart: 7146, .NumOperands: 1, .NumConds: 4 }, |
| 25834 | {.AsmStrOffset: 17815, .AliasCondStart: 7150, .NumOperands: 1, .NumConds: 4 }, |
| 25835 | {.AsmStrOffset: 17834, .AliasCondStart: 7154, .NumOperands: 1, .NumConds: 4 }, |
| 25836 | {.AsmStrOffset: 17859, .AliasCondStart: 7158, .NumOperands: 1, .NumConds: 4 }, |
| 25837 | {.AsmStrOffset: 17884, .AliasCondStart: 7162, .NumOperands: 1, .NumConds: 4 }, |
| 25838 | {.AsmStrOffset: 17909, .AliasCondStart: 7166, .NumOperands: 1, .NumConds: 4 }, |
| 25839 | }; |
| 25840 | |
| 25841 | static const AliasPatternCond Conds[] = { |
| 25842 | // (ADDPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 0 |
| 25843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25844 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25845 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25846 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25847 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25848 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCPA}, |
| 25849 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25850 | // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 7 |
| 25851 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 25853 | // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 9 |
| 25854 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25857 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25858 | // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 13 |
| 25859 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25860 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25861 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25862 | // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 16 |
| 25863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25866 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25867 | // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 20 |
| 25868 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25869 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 25870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25871 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 25872 | // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 24 |
| 25873 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 25875 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25876 | // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 27 |
| 25877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 25879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25880 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 25881 | // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 31 |
| 25882 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25884 | // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 33 |
| 25885 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25889 | // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 37 |
| 25890 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25893 | // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 40 |
| 25894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25897 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25898 | // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 44 |
| 25899 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25902 | // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 47 |
| 25903 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 25905 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25906 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 25907 | // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 51 |
| 25908 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25911 | // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 54 |
| 25912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 25914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25915 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 25916 | // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 58 |
| 25917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 25918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 25919 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25920 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25921 | // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 62 |
| 25922 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 25923 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 25924 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25925 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25926 | // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 66 |
| 25927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25930 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25931 | // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 70 |
| 25932 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 25933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 25934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25935 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 25936 | // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 74 |
| 25937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 25938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 25939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25940 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 25941 | // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 78 |
| 25942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 25943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25945 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25946 | // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 82 |
| 25947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25948 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 25949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25950 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25951 | // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 86 |
| 25952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25955 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25956 | // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 90 |
| 25957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 25958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 25961 | // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 94 |
| 25962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25963 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 25964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25965 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 25966 | // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 98 |
| 25967 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25969 | // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 100 |
| 25970 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25971 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25973 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25974 | // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 104 |
| 25975 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 25976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25978 | // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 107 |
| 25979 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25982 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25983 | // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 111 |
| 25984 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25985 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25986 | // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 113 |
| 25987 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25990 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25991 | // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 117 |
| 25992 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25995 | // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 120 |
| 25996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25998 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26000 | // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 124 |
| 26001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26004 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 2}, |
| 26005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26007 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26008 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26009 | // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 132 |
| 26010 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26011 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26012 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26013 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26014 | // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 136 |
| 26015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26018 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26019 | // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 140 |
| 26020 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26023 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 2}, |
| 26024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26027 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26028 | // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 148 |
| 26029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26030 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26031 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 26032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26035 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26036 | // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 155 |
| 26037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26038 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26039 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 26040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26044 | // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 162 |
| 26045 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26047 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 26048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26051 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26052 | // (AUTIA1716) - 169 |
| 26053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 26055 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26056 | // (AUTIASP) - 172 |
| 26057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 26059 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26060 | // (AUTIAZ) - 175 |
| 26061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26062 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 26063 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26064 | // (AUTIB1716) - 178 |
| 26065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 26067 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26068 | // (AUTIBSP) - 181 |
| 26069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 26071 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26072 | // (AUTIBZ) - 184 |
| 26073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 26075 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26076 | // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 187 |
| 26077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26078 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26079 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26080 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26081 | // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 191 |
| 26082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26085 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26086 | // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 195 |
| 26087 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26088 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26090 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26091 | // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 199 |
| 26092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26094 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26095 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26096 | // (CHKFEAT) - 203 |
| 26097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26098 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCHK}, |
| 26099 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26100 | // (CLREX 15) - 206 |
| 26101 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 26102 | // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 207 |
| 26103 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26104 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26109 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26110 | // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 214 |
| 26111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26112 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26113 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26115 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26117 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26118 | // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 221 |
| 26119 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26120 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26121 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26122 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26125 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26126 | // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 228 |
| 26127 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26128 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26129 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26132 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26133 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26134 | // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 235 |
| 26135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26136 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26137 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26139 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26140 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26141 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26142 | // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 242 |
| 26143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26144 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26145 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26147 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26149 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26150 | // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 249 |
| 26151 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26152 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26153 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26155 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26156 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26157 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26158 | // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 256 |
| 26159 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26160 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26161 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26164 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26165 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26166 | // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 263 |
| 26167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26168 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26169 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26173 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26174 | // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 270 |
| 26175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26176 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26177 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26178 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26181 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26182 | // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 277 |
| 26183 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26184 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26187 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26189 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26190 | // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 284 |
| 26191 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26192 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26194 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26197 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26198 | // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 291 |
| 26199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26200 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26201 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26203 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26204 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26205 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26206 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26207 | // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 299 |
| 26208 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26209 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26212 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26213 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26214 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26215 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26216 | // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 307 |
| 26217 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26218 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26221 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26225 | // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 315 |
| 26226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26227 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26233 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26234 | // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 323 |
| 26235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26236 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26238 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 26239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26241 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26242 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26243 | // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 331 |
| 26244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26245 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 26248 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26249 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26251 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26252 | // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 339 |
| 26253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26254 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 26257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26259 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26260 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26261 | // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 347 |
| 26262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26263 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 26266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26268 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26269 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26270 | // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 355 |
| 26271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26276 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26277 | // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 361 |
| 26278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26280 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26281 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26283 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26284 | // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 367 |
| 26285 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26289 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26290 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26291 | // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 373 |
| 26292 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26294 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26297 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26298 | // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 379 |
| 26299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26300 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26301 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26302 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26303 | // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 383 |
| 26304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26306 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26307 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26308 | // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 387 |
| 26309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26310 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26311 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26312 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26313 | // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 391 |
| 26314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26316 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26317 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26318 | // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 395 |
| 26319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26320 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26321 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26322 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26323 | // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 399 |
| 26324 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26326 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26327 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26328 | // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 403 |
| 26329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26330 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26331 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26332 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26333 | // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 407 |
| 26334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26335 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26336 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26337 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26338 | // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 411 |
| 26339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26340 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26341 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26342 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26343 | // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 415 |
| 26344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26346 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26347 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 26348 | // (DCPS1 0) - 419 |
| 26349 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26350 | // (DCPS2 0) - 420 |
| 26351 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26352 | // (DCPS3 0) - 421 |
| 26353 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26354 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26355 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureEL3}, |
| 26356 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26357 | // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 425 |
| 26358 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26359 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26360 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26361 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26363 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26364 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26365 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26366 | // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 433 |
| 26367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26368 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26369 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26370 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26371 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26372 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26373 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26374 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26375 | // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 441 |
| 26376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26377 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26378 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26379 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26380 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26381 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26382 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26383 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26384 | // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 449 |
| 26385 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26386 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26387 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26388 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26389 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26390 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26391 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26392 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26393 | // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 457 |
| 26394 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26395 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26396 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26397 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26399 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26401 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26402 | // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 465 |
| 26403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26404 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26405 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26406 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26407 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26408 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26409 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26410 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26411 | // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 473 |
| 26412 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26413 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26414 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26415 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26416 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26419 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26420 | // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 481 |
| 26421 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26422 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26423 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26424 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26428 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26429 | // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 489 |
| 26430 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26431 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26432 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26433 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26434 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26435 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26436 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26437 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26438 | // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 497 |
| 26439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26440 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26441 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26442 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26443 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26444 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26445 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26446 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26447 | // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 505 |
| 26448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26449 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26451 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26454 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26455 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26456 | // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 513 |
| 26457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26458 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26459 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26460 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26462 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26463 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26464 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26465 | // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 521 |
| 26466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26467 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26468 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26469 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26471 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26472 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26473 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26474 | // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 529 |
| 26475 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26476 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26477 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26478 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26479 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26480 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26481 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26482 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26483 | // (DSB 0) - 537 |
| 26484 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26485 | // (DSB 4) - 538 |
| 26486 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 26487 | // (DSB { 1, 1, 0, 0 }) - 539 |
| 26488 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 26489 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26490 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::HasV8_0rOps}, |
| 26491 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26492 | // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 543 |
| 26493 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26494 | {.Kind: AliasPatternCond::K_Custom, .Value: 5}, |
| 26495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26496 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26497 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26498 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26499 | // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 549 |
| 26500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26501 | {.Kind: AliasPatternCond::K_Custom, .Value: 6}, |
| 26502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26503 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26504 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26505 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26506 | // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 555 |
| 26507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26508 | {.Kind: AliasPatternCond::K_Custom, .Value: 7}, |
| 26509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26511 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26512 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26513 | // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 561 |
| 26514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26515 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 26516 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26517 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26519 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26520 | // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 567 |
| 26521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26522 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 26523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26524 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26525 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26526 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26527 | // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 573 |
| 26528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26529 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 26530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26532 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26533 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26534 | // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 579 |
| 26535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26540 | // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 584 |
| 26541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26543 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26544 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26545 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26546 | // (DUP_ZI_D ZPR64:$Zd, 0, 0) - 589 |
| 26547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26548 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26549 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26552 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26553 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26554 | // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 596 |
| 26555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26556 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26557 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26559 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26560 | // (DUP_ZI_H ZPR16:$Zd, 0, 0) - 601 |
| 26561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26562 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26563 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26565 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26566 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26567 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26568 | // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 608 |
| 26569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26573 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26574 | // (DUP_ZI_S ZPR32:$Zd, 0, 0) - 613 |
| 26575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26576 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26577 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26578 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26579 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26580 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26581 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26582 | // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 620 |
| 26583 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26585 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26586 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26587 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26588 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26589 | // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 626 |
| 26590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26591 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26593 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26594 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26595 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26596 | // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 632 |
| 26597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26598 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26601 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26602 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26603 | // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 638 |
| 26604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26606 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26607 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26609 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26610 | // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 644 |
| 26611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26613 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26614 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26615 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26617 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26618 | // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 651 |
| 26619 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26621 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26622 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26623 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26624 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26625 | // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 657 |
| 26626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26628 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26630 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26631 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26632 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26633 | // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 664 |
| 26634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26636 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26639 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26640 | // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 670 |
| 26641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26643 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26644 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26647 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26648 | // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 677 |
| 26649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26652 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26654 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26655 | // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 683 |
| 26656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26658 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26661 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26662 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26663 | // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 690 |
| 26664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26666 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26669 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26670 | // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 696 |
| 26671 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26673 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26674 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26676 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26677 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26678 | // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 703 |
| 26679 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26680 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26682 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26683 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26684 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26685 | // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 709 |
| 26686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26687 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26688 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26689 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26690 | // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 713 |
| 26691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26694 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26695 | // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 717 |
| 26696 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26697 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26699 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26700 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26703 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26704 | // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 725 |
| 26705 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26706 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26708 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26709 | // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 729 |
| 26710 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26711 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26713 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26714 | // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 733 |
| 26715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26718 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26721 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26722 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26723 | // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 741 |
| 26724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26725 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26726 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 26727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26730 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26731 | // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 748 |
| 26732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26733 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26734 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 26735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26738 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26739 | // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 755 |
| 26740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26741 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26742 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 26743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26746 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26747 | // (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 762 |
| 26748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26749 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 26752 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26755 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26756 | // (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 770 |
| 26757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26758 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26760 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 26761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26764 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26765 | // (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 778 |
| 26766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26767 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26769 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 26770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26772 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26773 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26774 | // (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 786 |
| 26775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26776 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26778 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 26779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26781 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26782 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26783 | // (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 794 |
| 26784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26785 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26786 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26787 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 26788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26791 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26792 | // (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 802 |
| 26793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26794 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26795 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 26797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26799 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26800 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26801 | // (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 810 |
| 26802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26803 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 26806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26809 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26810 | // (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 818 |
| 26811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 26815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26819 | // (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 826 |
| 26820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26821 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 26824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26827 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26828 | // (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 834 |
| 26829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26830 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 26833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26837 | // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 842 |
| 26838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26840 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26841 | // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 845 |
| 26842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26844 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 26845 | // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 848 |
| 26846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26847 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26852 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26853 | // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 855 |
| 26854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26855 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26857 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26860 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26861 | // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 862 |
| 26862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26863 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 26865 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26866 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26868 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26869 | // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 869 |
| 26870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26871 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26872 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26873 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26874 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26875 | // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 874 |
| 26876 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26879 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26880 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26881 | // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 879 |
| 26882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26884 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26885 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26886 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26887 | // (GCSPOPM XZR) - 884 |
| 26888 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureGCS}, |
| 26891 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26892 | // (GLD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 888 |
| 26893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26896 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26899 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26900 | // (GLD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 895 |
| 26901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26907 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26908 | // (GLD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 902 |
| 26909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26912 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26913 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26915 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26916 | // (GLD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 909 |
| 26917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26920 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26923 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26924 | // (GLD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 916 |
| 26925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26931 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26932 | // (GLD1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 923 |
| 26933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26936 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26939 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26940 | // (GLD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 930 |
| 26941 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26945 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26947 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26948 | // (GLD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 937 |
| 26949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26952 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26953 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26954 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26955 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26956 | // (GLD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 944 |
| 26957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26962 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26963 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26964 | // (GLD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 951 |
| 26965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26968 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26971 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26972 | // (GLD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 958 |
| 26973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26975 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26976 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26979 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26980 | // (GLD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 965 |
| 26981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26983 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26984 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26987 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26988 | // (GLD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 972 |
| 26989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26990 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26991 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26992 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26994 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26995 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26996 | // (GLDFF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 979 |
| 26997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26998 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27000 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27003 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27004 | // (GLDFF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 986 |
| 27005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27006 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27008 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27011 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27012 | // (GLDFF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 993 |
| 27013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27019 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27020 | // (GLDFF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1000 |
| 27021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27024 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27027 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27028 | // (GLDFF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1007 |
| 27029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27030 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27031 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27032 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27035 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27036 | // (GLDFF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1014 |
| 27037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27038 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27039 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27040 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27044 | // (GLDFF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1021 |
| 27045 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27046 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27047 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27048 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27051 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27052 | // (GLDFF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1028 |
| 27053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27054 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27056 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27059 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27060 | // (GLDFF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1035 |
| 27061 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27062 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27064 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27067 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27068 | // (GLDFF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1042 |
| 27069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27070 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27071 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27072 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27075 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27076 | // (GLDFF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1049 |
| 27077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27078 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27079 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27080 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27082 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27083 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27084 | // (GLDFF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1056 |
| 27085 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27086 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27087 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27088 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27089 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27090 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27091 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27092 | // (HINT { 0, 0, 0 }) - 1063 |
| 27093 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27094 | // (HINT { 0, 0, 1 }) - 1064 |
| 27095 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27096 | // (HINT { 0, 1, 0 }) - 1065 |
| 27097 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 27098 | // (HINT { 0, 1, 1 }) - 1066 |
| 27099 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 27100 | // (HINT { 1, 0, 0 }) - 1067 |
| 27101 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 27102 | // (HINT { 1, 0, 1 }) - 1068 |
| 27103 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 27104 | // (HINT { 1, 1, 0 }) - 1069 |
| 27105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 27106 | // (HINT { 1, 0, 0, 0, 0 }) - 1070 |
| 27107 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 27108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27109 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRAS}, |
| 27110 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27111 | // (HINT 20) - 1074 |
| 27112 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(20)}, |
| 27113 | // (HINT 32) - 1075 |
| 27114 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(32)}, |
| 27115 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 27117 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27118 | // (HINT btihint_op:$op) - 1079 |
| 27119 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 27120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 27122 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27123 | // (HINT psbhint_op:$op) - 1083 |
| 27124 | {.Kind: AliasPatternCond::K_Custom, .Value: 9}, |
| 27125 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSPE}, |
| 27127 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27128 | // (HINT 19) - 1087 |
| 27129 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(19)}, |
| 27130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureGCS}, |
| 27132 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27133 | // (HINT 22) - 1091 |
| 27134 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(22)}, |
| 27135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCLRBHB}, |
| 27137 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27138 | // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1095 |
| 27139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27140 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27141 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27142 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27146 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27147 | // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1103 |
| 27148 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27149 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27150 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27151 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27155 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27156 | // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1111 |
| 27157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27158 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27160 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27164 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27165 | // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1119 |
| 27166 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27167 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27168 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27169 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27173 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27174 | // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1127 |
| 27175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27176 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27177 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27178 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27182 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27183 | // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 1135 |
| 27184 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27185 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27186 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27187 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27192 | // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1143 |
| 27193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27194 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27195 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27196 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27200 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27201 | // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1151 |
| 27202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27203 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27204 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27205 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27209 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27210 | // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1159 |
| 27211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27212 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27213 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27214 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27218 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27219 | // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 1167 |
| 27220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27221 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27222 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27223 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27227 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27228 | // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1175 |
| 27229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27230 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27231 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27232 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27233 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27234 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27235 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27236 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27237 | // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1183 |
| 27238 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27239 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27240 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27241 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27242 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27244 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27245 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27246 | // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1191 |
| 27247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27248 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27249 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27250 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27251 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27252 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27254 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27255 | // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 1199 |
| 27256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27257 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27258 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27259 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27261 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27262 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27263 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27264 | // (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1207 |
| 27265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 27266 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27268 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27271 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27273 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27274 | // (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1216 |
| 27275 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 27276 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27278 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27281 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27283 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27284 | // (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1225 |
| 27285 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 27286 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27288 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27291 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27293 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27294 | // (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1234 |
| 27295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 27296 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27298 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27301 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27303 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27304 | // (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1243 |
| 27305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 27306 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27308 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27311 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27312 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27313 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27314 | // (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1252 |
| 27315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 27316 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27317 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27318 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27321 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27323 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27324 | // (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1261 |
| 27325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 27326 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27328 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27333 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27334 | // (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1270 |
| 27335 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 27336 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27338 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27340 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27344 | // (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1279 |
| 27345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 27346 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27348 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27349 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27350 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27352 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27353 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27354 | // (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1288 |
| 27355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 27356 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27357 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 27358 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27359 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27361 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27363 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27364 | // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1297 |
| 27365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27366 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27367 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27371 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27372 | // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 1304 |
| 27373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27374 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27375 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27379 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27380 | // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1311 |
| 27381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27382 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27383 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27387 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27388 | // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 1318 |
| 27389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27390 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27391 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27395 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27396 | // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1325 |
| 27397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27398 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27399 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27400 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27402 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27403 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27404 | // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 1332 |
| 27405 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27406 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27407 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27409 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27411 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27412 | // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1339 |
| 27413 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27414 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27415 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27419 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27420 | // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 1346 |
| 27421 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27422 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27423 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27427 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27428 | // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1353 |
| 27429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27430 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27431 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 27434 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27435 | // (ISB 15) - 1359 |
| 27436 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 27437 | // (LD1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1360 |
| 27438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 27439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27440 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27441 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27442 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27443 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27444 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27445 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27446 | // (LD1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1368 |
| 27447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 27448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27449 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27453 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27454 | // (LD1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1375 |
| 27455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 27456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27458 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27462 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27463 | // (LD1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1383 |
| 27464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 27465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27467 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27468 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27470 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27471 | // (LD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1390 |
| 27472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27475 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27478 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27479 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27480 | // (LD1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1398 |
| 27481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27483 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27484 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27488 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27489 | // (LD1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1406 |
| 27490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27491 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27493 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27496 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27497 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27498 | // (LD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1414 |
| 27499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27501 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27502 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27503 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27504 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27506 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27507 | // (LD1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1422 |
| 27508 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 27509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27511 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27512 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27513 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27515 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27516 | // (LD1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1430 |
| 27517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 27518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27520 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27521 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27523 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27524 | // (LD1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1437 |
| 27525 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 27526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27528 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27532 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27533 | // (LD1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1445 |
| 27534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 27535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27536 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27537 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27539 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27540 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27541 | // (LD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1452 |
| 27542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27543 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27544 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27545 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27547 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27548 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27549 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27550 | // (LD1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1460 |
| 27551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27552 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27554 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27555 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27556 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27557 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27558 | // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1467 |
| 27559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 27561 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27562 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27565 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27566 | // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1474 |
| 27567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 27569 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27570 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27573 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27574 | // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1481 |
| 27575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 27577 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27578 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27579 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27580 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27581 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27582 | // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1488 |
| 27583 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 27585 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27586 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27587 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27588 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27589 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27590 | // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1495 |
| 27591 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27592 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 27593 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27594 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27595 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27596 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27597 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27598 | // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1502 |
| 27599 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27600 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 27601 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27602 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27603 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27604 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27605 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27606 | // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1509 |
| 27607 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 27609 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27610 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27611 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27612 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27613 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27614 | // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1516 |
| 27615 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 27617 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27618 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27619 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27620 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27621 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27622 | // (LD1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1523 |
| 27623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 27624 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27626 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27627 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27628 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27630 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27631 | // (LD1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1531 |
| 27632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 27633 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27635 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27636 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27638 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27639 | // (LD1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1538 |
| 27640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 27641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27643 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27644 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 27647 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27648 | // (LD1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1546 |
| 27649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 27650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 27651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27652 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 27655 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27656 | // (LD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1553 |
| 27657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27660 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27661 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27664 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27665 | // (LD1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1561 |
| 27666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27669 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27670 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27673 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27674 | // (LD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1569 |
| 27675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27678 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27682 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27683 | // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1577 |
| 27684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27686 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27687 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27690 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27691 | // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1584 |
| 27692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 27694 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27695 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27698 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27699 | // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1591 |
| 27700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27701 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27702 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27703 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27706 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27707 | // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1598 |
| 27708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 27710 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27711 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27713 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27714 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27715 | // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1605 |
| 27716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 27718 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27719 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27721 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27722 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27723 | // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1612 |
| 27724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27726 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27727 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27730 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27731 | // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1619 |
| 27732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 27734 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27735 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27738 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27739 | // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1626 |
| 27740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27742 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27743 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27746 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27747 | // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1633 |
| 27748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27751 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27755 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27756 | // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1641 |
| 27757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27764 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27765 | // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1649 |
| 27766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27769 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27772 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27773 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27774 | // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1657 |
| 27775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27778 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27781 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27782 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27783 | // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1665 |
| 27784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27786 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27787 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27791 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27792 | // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1673 |
| 27793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27794 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27795 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27796 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27799 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27800 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27801 | // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1681 |
| 27802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27803 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27805 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27809 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27810 | // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1689 |
| 27811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27814 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27819 | // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1697 |
| 27820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27827 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27828 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 27829 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27830 | // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1707 |
| 27831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27834 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27836 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27837 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27838 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27839 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 27840 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27841 | // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1717 |
| 27842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27844 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27845 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27846 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27847 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27848 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 27851 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27852 | // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1727 |
| 27853 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27856 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27857 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27859 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 27862 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27863 | // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1737 |
| 27864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27871 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27872 | // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1745 |
| 27873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27875 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27876 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27879 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27880 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27881 | // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1753 |
| 27882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27885 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27886 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27889 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27890 | // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1761 |
| 27891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27894 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27898 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27899 | // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1769 |
| 27900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27903 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27907 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27908 | // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1777 |
| 27909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27912 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27913 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27916 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27917 | // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1785 |
| 27918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27921 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27925 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27926 | // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1793 |
| 27927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27930 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27931 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27934 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27935 | // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1801 |
| 27936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27939 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27943 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27944 | // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1809 |
| 27945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27948 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27951 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27952 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27953 | // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1817 |
| 27954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27957 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27958 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27959 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27961 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27962 | // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1825 |
| 27963 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 27965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27966 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27967 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27970 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27971 | // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1833 |
| 27972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27974 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27975 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27978 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27979 | // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1840 |
| 27980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 27982 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27983 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27986 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27987 | // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1847 |
| 27988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 27990 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27991 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 27994 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27995 | // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1854 |
| 27996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 27998 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27999 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28002 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28003 | // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1861 |
| 28004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 28006 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28007 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28008 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28010 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28011 | // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1868 |
| 28012 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 28014 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28015 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28018 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28019 | // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1875 |
| 28020 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 28022 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28023 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28026 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28027 | // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1882 |
| 28028 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 28030 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28031 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28034 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28035 | // (LD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1889 |
| 28036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28038 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28039 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28044 | // (LD1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1897 |
| 28045 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28046 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28047 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28048 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28052 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28053 | // (LD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1905 |
| 28054 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28057 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28059 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28061 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28062 | // (LD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1913 |
| 28063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28064 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28065 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28066 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28067 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28068 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28070 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28071 | // (LD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1921 |
| 28072 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28073 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28074 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28075 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28079 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28080 | // (LD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1929 |
| 28081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28084 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28088 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28089 | // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1937 |
| 28090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28092 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28093 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28096 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28097 | // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1944 |
| 28098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28100 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28101 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28104 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28105 | // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1951 |
| 28106 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28108 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28109 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28113 | // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1958 |
| 28114 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28116 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28117 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28120 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28121 | // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1965 |
| 28122 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28124 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28125 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28128 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28129 | // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1972 |
| 28130 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28132 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28133 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28136 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28137 | // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1979 |
| 28138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28140 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28141 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28142 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28144 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28145 | // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1986 |
| 28146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28147 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28148 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28149 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28150 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28152 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28153 | // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1993 |
| 28154 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28156 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28157 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28161 | // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2000 |
| 28162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28164 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28165 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28168 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28169 | // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2007 |
| 28170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28172 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28173 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28176 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28177 | // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2014 |
| 28178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28180 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28181 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28184 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28185 | // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2021 |
| 28186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28188 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28189 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28192 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28193 | // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2028 |
| 28194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28196 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28197 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28200 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28201 | // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2035 |
| 28202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28204 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28205 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28208 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28209 | // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2042 |
| 28210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28212 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28213 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28214 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28216 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28217 | // (LD1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2049 |
| 28218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 28219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 28220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28221 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 28224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28225 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28226 | // (LD1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2057 |
| 28227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 28228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 28229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28230 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 28233 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28234 | // (LD1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2064 |
| 28235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 28236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 28237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28238 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 28241 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28242 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28243 | // (LD1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2072 |
| 28244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 28245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 28246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28247 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28248 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28249 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 28250 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28251 | // (LD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2079 |
| 28252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28255 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28259 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28260 | // (LD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2087 |
| 28261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28264 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28265 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28268 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28269 | // (LD1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2095 |
| 28270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28273 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28276 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28277 | // (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2102 |
| 28278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 28279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28280 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28282 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28283 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28284 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28285 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28286 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28287 | // (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2111 |
| 28288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 28289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28290 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28292 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28293 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28294 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28296 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28297 | // (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2120 |
| 28298 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 28299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28300 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28301 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28303 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28305 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28306 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28307 | // (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2129 |
| 28308 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 28309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28310 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28311 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28312 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28313 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28314 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28315 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28316 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28317 | // (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2138 |
| 28318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 28319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28320 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28323 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28324 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28325 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28326 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28327 | // (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2147 |
| 28328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 28329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28330 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28332 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28333 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28334 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28335 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28336 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28337 | // (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2156 |
| 28338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 28339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28340 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28341 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28343 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28344 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28345 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28346 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28347 | // (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2165 |
| 28348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 28349 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28350 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28351 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28353 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28354 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28355 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28356 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28357 | // (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2174 |
| 28358 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 28359 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28360 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28363 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28364 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28365 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28366 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28367 | // (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2183 |
| 28368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 28369 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28370 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28372 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28373 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28375 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28376 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28377 | // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 2192 |
| 28378 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 28380 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28381 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28382 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28383 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28386 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28387 | // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 2201 |
| 28388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 28390 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28391 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28392 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28393 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28396 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28397 | // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 2210 |
| 28398 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28399 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 28400 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28401 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28402 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28403 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28406 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28407 | // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 2219 |
| 28408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 28410 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28411 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28412 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28413 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28415 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28416 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28417 | // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2228 |
| 28418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 28419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28420 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28421 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28423 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28425 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28426 | // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2236 |
| 28427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 28428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28430 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28434 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28435 | // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2244 |
| 28436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 28437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28439 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28441 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28442 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28443 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28444 | // (LD2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2252 |
| 28445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 28446 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28448 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28449 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28450 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 28451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28452 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28453 | // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2260 |
| 28454 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28456 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28457 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28458 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28460 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28461 | // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2267 |
| 28462 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28464 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28465 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28468 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28469 | // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2274 |
| 28470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28472 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28473 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28476 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28477 | // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2281 |
| 28478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28479 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28480 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28481 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28482 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28483 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28484 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28485 | // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2288 |
| 28486 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28487 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28488 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28489 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28490 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28491 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28492 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28493 | // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2295 |
| 28494 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28495 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28496 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28497 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28498 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28499 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28500 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28501 | // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2302 |
| 28502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28503 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28504 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28505 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28507 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28508 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28509 | // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2309 |
| 28510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28512 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28513 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28515 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28516 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28517 | // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2316 |
| 28518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28520 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28521 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28524 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28525 | // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2323 |
| 28526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28528 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28529 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28532 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28533 | // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2330 |
| 28534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28536 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28537 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28539 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28540 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28541 | // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2337 |
| 28542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28543 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28544 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28545 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28547 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28548 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28549 | // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2344 |
| 28550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28552 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28553 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28555 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28556 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28557 | // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2351 |
| 28558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 28560 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28561 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28562 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28564 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28565 | // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2358 |
| 28566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28568 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28569 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28572 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28573 | // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2365 |
| 28574 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 28575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28577 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28578 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28579 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28580 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28581 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28582 | // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 2373 |
| 28583 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28585 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28586 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28587 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28588 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28591 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28592 | // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 2382 |
| 28593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28595 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28596 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28597 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28598 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28601 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28602 | // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 2391 |
| 28603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28605 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28606 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28607 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28608 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28610 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28611 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28612 | // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 2400 |
| 28613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 28615 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28616 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28617 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28618 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28619 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28620 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28621 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28622 | // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2409 |
| 28623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 28624 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28626 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28627 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28628 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28630 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28631 | // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2417 |
| 28632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 28633 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28635 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28636 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28639 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28640 | // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2425 |
| 28641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 28642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28644 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28648 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28649 | // (LD3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2433 |
| 28650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 28651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28652 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28653 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 28656 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28657 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28658 | // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2441 |
| 28659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28660 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28661 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28662 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28665 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28666 | // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 2448 |
| 28667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28669 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28670 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28673 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28674 | // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2455 |
| 28675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28677 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28678 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28681 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28682 | // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2462 |
| 28683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28685 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28686 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28689 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28690 | // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2469 |
| 28691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28693 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28694 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28695 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28697 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28698 | // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2476 |
| 28699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28701 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28702 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28703 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28705 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28706 | // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2483 |
| 28707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28709 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28710 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28713 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28714 | // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2490 |
| 28715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28717 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28718 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28721 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28722 | // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2497 |
| 28723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28725 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28726 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28729 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28730 | // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2504 |
| 28731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28733 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28734 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28737 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28738 | // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2511 |
| 28739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28741 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28742 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28745 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28746 | // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2518 |
| 28747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28749 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28750 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28753 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28754 | // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2525 |
| 28755 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28757 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28758 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28759 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28761 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28762 | // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2532 |
| 28763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28764 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 28765 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28766 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28767 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28769 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28770 | // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2539 |
| 28771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28773 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28774 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28775 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28777 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28778 | // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2546 |
| 28779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 28780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28782 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28783 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28786 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28787 | // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 2554 |
| 28788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28790 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28791 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28792 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28793 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28794 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28795 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28796 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28797 | // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 2563 |
| 28798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28800 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28801 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28802 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28803 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28804 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28805 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28806 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28807 | // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 2572 |
| 28808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28810 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28811 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28813 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28814 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28816 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28817 | // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 2581 |
| 28818 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 28820 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28821 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28822 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28823 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28827 | // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2590 |
| 28828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 28829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28832 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28835 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28836 | // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2598 |
| 28837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 28838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28841 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28844 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28845 | // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2606 |
| 28846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28849 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28852 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28853 | // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2613 |
| 28854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28856 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28857 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28860 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28861 | // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2620 |
| 28862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28864 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28865 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28866 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28868 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28869 | // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2627 |
| 28870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28872 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28873 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28874 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28876 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28877 | // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2634 |
| 28878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28880 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28881 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28882 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28884 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28885 | // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2641 |
| 28886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28888 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28889 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28891 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28892 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28893 | // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2648 |
| 28894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28896 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28897 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28899 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28900 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28901 | // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2655 |
| 28902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 28903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28905 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28908 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28909 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28910 | // (LD4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2663 |
| 28911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 28912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28914 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 28917 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28918 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28919 | // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2671 |
| 28920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28922 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28923 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28926 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28927 | // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2678 |
| 28928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28930 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28931 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28934 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28935 | // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2685 |
| 28936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28938 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28939 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28942 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28943 | // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2692 |
| 28944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28946 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28947 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28951 | // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2699 |
| 28952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28954 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28955 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28958 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28959 | // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2706 |
| 28960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28962 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28963 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28967 | // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2713 |
| 28968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 28970 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28971 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28974 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28975 | // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2720 |
| 28976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28978 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28979 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28980 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28981 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 28982 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28983 | // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2727 |
| 28984 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 28985 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28987 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28989 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28990 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28991 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28992 | // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 2735 |
| 28993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 28995 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28996 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28997 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28998 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28999 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29001 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29002 | // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 2744 |
| 29003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29005 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29006 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29007 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29008 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29011 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29012 | // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 2753 |
| 29013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29015 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29016 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29017 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29018 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29021 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29022 | // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 2762 |
| 29023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29024 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29025 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29026 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29027 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29028 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29030 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29031 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29032 | // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2771 |
| 29033 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29034 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29035 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29037 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29038 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29039 | // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2777 |
| 29040 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29041 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29043 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29045 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29046 | // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2783 |
| 29047 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29048 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29052 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29053 | // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2789 |
| 29054 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29059 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29060 | // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2795 |
| 29061 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29062 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29066 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29067 | // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2801 |
| 29068 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29070 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29073 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29074 | // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2807 |
| 29075 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29080 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29081 | // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2813 |
| 29082 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29087 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29088 | // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2819 |
| 29089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29091 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29094 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29095 | // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2825 |
| 29096 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29097 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29098 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29099 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29101 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29102 | // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2831 |
| 29103 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29108 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29109 | // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2837 |
| 29110 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29112 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29116 | // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2843 |
| 29117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29119 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29122 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29123 | // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2849 |
| 29124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29126 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29129 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29130 | // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2855 |
| 29131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29133 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29136 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29137 | // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2861 |
| 29138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29140 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29141 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29142 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29143 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29144 | // (LDAPURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 2867 |
| 29145 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 29146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29147 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29149 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 29150 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29153 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29154 | // (LDAPURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 2876 |
| 29155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29156 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29157 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 29160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29163 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29164 | // (LDAPURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 2885 |
| 29165 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 29166 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29167 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29168 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 29170 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29173 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29174 | // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2894 |
| 29175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29176 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29177 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29178 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 29180 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29181 | // (LDAPURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 2900 |
| 29182 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29183 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29184 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29185 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 29187 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29190 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29191 | // (LDAPURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 2909 |
| 29192 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 29193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29194 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 29197 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29200 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29201 | // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2918 |
| 29202 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29205 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29207 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29208 | // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2924 |
| 29209 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29212 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29213 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29214 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29215 | // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2930 |
| 29216 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29217 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29219 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29220 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29221 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29222 | // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2936 |
| 29223 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29225 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29227 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29228 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29229 | // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2942 |
| 29230 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29231 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29232 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29233 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29234 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29235 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29236 | // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2948 |
| 29237 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29238 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29239 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29241 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29242 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29243 | // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2954 |
| 29244 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29248 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29249 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29250 | // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2960 |
| 29251 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29254 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29255 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29256 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29257 | // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2966 |
| 29258 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29261 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29262 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29263 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29264 | // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2972 |
| 29265 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29268 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29269 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29270 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29271 | // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2978 |
| 29272 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29274 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29276 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29277 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29278 | // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2984 |
| 29279 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29285 | // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2990 |
| 29286 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29289 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29290 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29291 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29292 | // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2996 |
| 29293 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29297 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29298 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29299 | // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3002 |
| 29300 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 29301 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29303 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29305 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29306 | // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3008 |
| 29307 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29308 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29310 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29311 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 29312 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29313 | // (LDFF1B Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3014 |
| 29314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29317 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29318 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29319 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29320 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29321 | // (LDFF1B_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3021 |
| 29322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29324 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29325 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29326 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29327 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29328 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29329 | // (LDFF1B_H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3028 |
| 29330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29332 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29333 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29334 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29335 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29336 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29337 | // (LDFF1B_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3035 |
| 29338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29340 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29341 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29343 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29344 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29345 | // (LDFF1D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3042 |
| 29346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29349 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29352 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29353 | // (LDFF1H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3049 |
| 29354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29357 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29358 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29359 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29360 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29361 | // (LDFF1H_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3056 |
| 29362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29363 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29364 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29365 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29368 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29369 | // (LDFF1H_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3063 |
| 29370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29372 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29373 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29375 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29376 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29377 | // (LDFF1SB_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3070 |
| 29378 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29380 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29381 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29382 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29384 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29385 | // (LDFF1SB_H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3077 |
| 29386 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29387 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29389 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29390 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29391 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29392 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29393 | // (LDFF1SB_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3084 |
| 29394 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29395 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29397 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29399 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29400 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29401 | // (LDFF1SH_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3091 |
| 29402 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29405 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29407 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29408 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29409 | // (LDFF1SH_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3098 |
| 29410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29412 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29413 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29415 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29416 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29417 | // (LDFF1SW_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3105 |
| 29418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29420 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29421 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29423 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29424 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29425 | // (LDFF1W Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3112 |
| 29426 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29429 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29432 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29433 | // (LDFF1W_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3119 |
| 29434 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29435 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29437 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29438 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29440 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29441 | // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 3126 |
| 29442 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29443 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29445 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 29448 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29449 | // (LDNF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3133 |
| 29450 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29453 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29454 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29455 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29456 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29457 | // (LDNF1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3140 |
| 29458 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29459 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29461 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29462 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29463 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29464 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29465 | // (LDNF1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3147 |
| 29466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29468 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29469 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29471 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29472 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29473 | // (LDNF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3154 |
| 29474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29475 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29476 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29477 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29478 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29479 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29480 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29481 | // (LDNF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3161 |
| 29482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29483 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29484 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29485 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29488 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29489 | // (LDNF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3168 |
| 29490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29491 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29493 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29496 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29497 | // (LDNF1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3175 |
| 29498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29501 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29503 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29504 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29505 | // (LDNF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3182 |
| 29506 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29508 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29509 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29511 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29512 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29513 | // (LDNF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3189 |
| 29514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29516 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29517 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29519 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29520 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29521 | // (LDNF1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3196 |
| 29522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29523 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29524 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29525 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29526 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29527 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29528 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29529 | // (LDNF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3203 |
| 29530 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29531 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29533 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29534 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29535 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29536 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29537 | // (LDNF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3210 |
| 29538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29540 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29541 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29543 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29544 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29545 | // (LDNF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3217 |
| 29546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29549 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29552 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29553 | // (LDNF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3224 |
| 29554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29557 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29560 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29561 | // (LDNF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3231 |
| 29562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29565 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29566 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29567 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29568 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29569 | // (LDNF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3238 |
| 29570 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29573 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29574 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29575 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29576 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29577 | // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3245 |
| 29578 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29579 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29581 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29584 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29585 | // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3252 |
| 29586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29587 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29589 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29592 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29593 | // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3259 |
| 29594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 29595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 29596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29597 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29600 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29601 | // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3266 |
| 29602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29605 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29606 | // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3270 |
| 29607 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29610 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29611 | // (LDNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3274 |
| 29612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29615 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29618 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29619 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29620 | // (LDNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3282 |
| 29621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29624 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29627 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29628 | // (LDNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3289 |
| 29629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29632 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29635 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29636 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29637 | // (LDNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3297 |
| 29638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29641 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29643 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29644 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29645 | // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3304 |
| 29646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29647 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29648 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29649 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29650 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29652 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29653 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29654 | // (LDNT1B_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3312 |
| 29655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29658 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29661 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29662 | // (LDNT1B_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3319 |
| 29663 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29666 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29669 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29670 | // (LDNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3326 |
| 29671 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29674 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29676 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29678 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29679 | // (LDNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3334 |
| 29680 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29681 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29683 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29684 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29685 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29686 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29687 | // (LDNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3341 |
| 29688 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29689 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29691 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29692 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29694 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29695 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29696 | // (LDNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3349 |
| 29697 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29700 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29703 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29704 | // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3356 |
| 29705 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29706 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29708 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29709 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29710 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29712 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29713 | // (LDNT1D_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3364 |
| 29714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29717 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29720 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29721 | // (LDNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3371 |
| 29722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29725 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29726 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29729 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29730 | // (LDNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3379 |
| 29731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29734 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29737 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29738 | // (LDNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3386 |
| 29739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29742 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29746 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29747 | // (LDNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3394 |
| 29748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29751 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29754 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29755 | // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3401 |
| 29756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29759 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29763 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29764 | // (LDNT1H_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3409 |
| 29765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29768 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29771 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29772 | // (LDNT1H_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3416 |
| 29773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29776 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29778 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29779 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29780 | // (LDNT1SB_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3423 |
| 29781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29784 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29786 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29787 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29788 | // (LDNT1SB_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3430 |
| 29789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29791 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29792 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29794 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29795 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29796 | // (LDNT1SH_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3437 |
| 29797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29800 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29802 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29803 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29804 | // (LDNT1SH_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3444 |
| 29805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29808 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29810 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29811 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29812 | // (LDNT1SW_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3451 |
| 29813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29816 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29818 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29819 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29820 | // (LDNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3458 |
| 29821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29824 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29827 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29828 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29829 | // (LDNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3466 |
| 29830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29833 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29837 | // (LDNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3473 |
| 29838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29841 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29844 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29845 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29846 | // (LDNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3481 |
| 29847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29850 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29852 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29853 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29854 | // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3488 |
| 29855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29858 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29862 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29863 | // (LDNT1W_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3496 |
| 29864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29867 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29870 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29871 | // (LDNT1W_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3503 |
| 29872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29875 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 29878 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29879 | // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3510 |
| 29880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29883 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29884 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29885 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29886 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29887 | // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3517 |
| 29888 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29889 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29890 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29891 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29892 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29893 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29894 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29895 | // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3524 |
| 29896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29897 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29898 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29899 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29900 | // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3528 |
| 29901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 29902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 29903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29907 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29908 | // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3535 |
| 29909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29912 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29913 | // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3539 |
| 29914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29916 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29917 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29918 | // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3543 |
| 29919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29921 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 29924 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29925 | // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3549 |
| 29926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 29931 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29932 | // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3555 |
| 29933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29936 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29937 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29938 | // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 3560 |
| 29939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29940 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29941 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29942 | // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3563 |
| 29943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 29944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29946 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29947 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29951 | // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3571 |
| 29952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 29953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29954 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29957 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29958 | // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3577 |
| 29959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29962 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29963 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29967 | // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3585 |
| 29968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29970 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29971 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29973 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29974 | // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3591 |
| 29975 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29978 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29979 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29980 | // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 3596 |
| 29981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29983 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29984 | // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3599 |
| 29985 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 29986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29987 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29988 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29989 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29990 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29992 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29993 | // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3607 |
| 29994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 29995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29996 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29998 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 29999 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30000 | // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3613 |
| 30001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30004 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30005 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30007 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30008 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30009 | // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3621 |
| 30010 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30011 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30012 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30014 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30015 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30016 | // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3627 |
| 30017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30019 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30020 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30021 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30022 | // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3632 |
| 30023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30024 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30025 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30026 | // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3635 |
| 30027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30028 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30030 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30031 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30032 | // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3640 |
| 30033 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30034 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30035 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30036 | // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3643 |
| 30037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30038 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30039 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30040 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30041 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30042 | // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3648 |
| 30043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30045 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30046 | // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3651 |
| 30047 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30048 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30050 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30051 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30052 | // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3656 |
| 30053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30054 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30055 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30056 | // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3659 |
| 30057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30058 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30060 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30061 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30062 | // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 3664 |
| 30063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30064 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30065 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30066 | // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3667 |
| 30067 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 30068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30070 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30071 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30074 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30075 | // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3675 |
| 30076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 30077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30078 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30081 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30082 | // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3681 |
| 30083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30085 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30086 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30087 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30088 | // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3686 |
| 30089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30091 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30092 | // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3689 |
| 30093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30094 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30095 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30097 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30098 | // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3694 |
| 30099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30101 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30102 | // (LDR_PXI PPRorPNRAny:$Pt, GPR64sp:$Rn, 0) - 3697 |
| 30103 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRorPNRRegClassID}, |
| 30104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30109 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30110 | // (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 3704 |
| 30111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 30112 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30113 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30114 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30115 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30117 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30118 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30119 | // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3712 |
| 30120 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30121 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30122 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30125 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30126 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30127 | // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3719 |
| 30128 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30129 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30130 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30132 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30133 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30134 | // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3725 |
| 30135 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30137 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30139 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30140 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30141 | // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3731 |
| 30142 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30144 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30147 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30148 | // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3737 |
| 30149 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30151 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30154 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30155 | // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3743 |
| 30156 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30160 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30161 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30162 | // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3749 |
| 30163 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30164 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30165 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30168 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30169 | // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3755 |
| 30170 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30172 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30175 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30176 | // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3761 |
| 30177 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30182 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30183 | // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3767 |
| 30184 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30187 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30189 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30190 | // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3773 |
| 30191 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30192 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30194 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30196 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30197 | // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3779 |
| 30198 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30201 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30202 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30203 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30204 | // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3785 |
| 30205 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30210 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30211 | // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3791 |
| 30212 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30217 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30218 | // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3797 |
| 30219 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30221 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30225 | // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3803 |
| 30226 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30229 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30231 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30232 | // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3809 |
| 30233 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30236 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30237 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30238 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30239 | // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3815 |
| 30240 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30244 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30245 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30246 | // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3821 |
| 30247 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30249 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30251 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30252 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30253 | // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3827 |
| 30254 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30259 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30260 | // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3833 |
| 30261 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30264 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30265 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30266 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30267 | // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3839 |
| 30268 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30271 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30273 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30274 | // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3845 |
| 30275 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30278 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30280 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30281 | // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3851 |
| 30282 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30285 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30286 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30287 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30288 | // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3857 |
| 30289 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30293 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30294 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30295 | // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3863 |
| 30296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30298 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30299 | // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3866 |
| 30300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30301 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30302 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30303 | // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3869 |
| 30304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30306 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30307 | // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3872 |
| 30308 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30310 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30311 | // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3875 |
| 30312 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30314 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30315 | // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3878 |
| 30316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30317 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30318 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30319 | // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 3881 |
| 30320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30322 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30323 | // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3884 |
| 30324 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30326 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30327 | // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3887 |
| 30328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30330 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30331 | // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3890 |
| 30332 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30333 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30335 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30336 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30337 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30338 | // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3896 |
| 30339 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30340 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30341 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30343 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30344 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30345 | // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3902 |
| 30346 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30351 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30352 | // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3908 |
| 30353 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30358 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30359 | // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3914 |
| 30360 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30363 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30364 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30365 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30366 | // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3920 |
| 30367 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30369 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30371 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30372 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30373 | // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3926 |
| 30374 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30375 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30379 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30380 | // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3932 |
| 30381 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30386 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30387 | // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3938 |
| 30388 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30391 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30393 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30394 | // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3944 |
| 30395 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30399 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30400 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30401 | // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3950 |
| 30402 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30407 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30408 | // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3956 |
| 30409 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30414 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30415 | // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3962 |
| 30416 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30420 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30421 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30422 | // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3968 |
| 30423 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30425 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30428 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30429 | // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3974 |
| 30430 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30432 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30434 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30435 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30436 | // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3980 |
| 30437 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30441 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30442 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30443 | // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3986 |
| 30444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30446 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30447 | // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3989 |
| 30448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 30449 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30453 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30454 | // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3995 |
| 30455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 30456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30457 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30458 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30460 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30461 | // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4001 |
| 30462 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30464 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30465 | // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4004 |
| 30466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 30467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30468 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30471 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30472 | // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4010 |
| 30473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30475 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30478 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30479 | // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4016 |
| 30480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30482 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30483 | // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4019 |
| 30484 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30485 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30486 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30487 | // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4022 |
| 30488 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30490 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30491 | // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4025 |
| 30492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30493 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30494 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30495 | // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 4028 |
| 30496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30497 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30498 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30499 | // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4031 |
| 30500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 30501 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30502 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30503 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30504 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 30505 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30506 | // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4037 |
| 30507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30508 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30509 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30510 | // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 4040 |
| 30511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30513 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30514 | // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4043 |
| 30515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30516 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30518 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30519 | // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4047 |
| 30520 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30523 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30524 | // (MOVA_2ZMXI_H_B ZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4051 |
| 30525 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30528 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30530 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30531 | // (MOVA_2ZMXI_H_D ZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4057 |
| 30532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30533 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30535 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30537 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30538 | // (MOVA_2ZMXI_H_H ZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4063 |
| 30539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30540 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30543 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30544 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30545 | // (MOVA_2ZMXI_H_S ZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4069 |
| 30546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30549 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30551 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30552 | // (MOVA_2ZMXI_V_B ZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4075 |
| 30553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30556 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30557 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30558 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30559 | // (MOVA_2ZMXI_V_D ZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4081 |
| 30560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30565 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30566 | // (MOVA_2ZMXI_V_H ZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4087 |
| 30567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30572 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30573 | // (MOVA_2ZMXI_V_S ZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4093 |
| 30574 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30578 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30579 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30580 | // (MOVA_4ZMXI_H_B ZZZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4099 |
| 30581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30583 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30585 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30586 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30587 | // (MOVA_4ZMXI_H_D ZZZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4105 |
| 30588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30593 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30594 | // (MOVA_4ZMXI_H_H ZZZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4111 |
| 30595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30600 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30601 | // (MOVA_4ZMXI_H_S ZZZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4117 |
| 30602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30605 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30606 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30607 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30608 | // (MOVA_4ZMXI_V_B ZZZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4123 |
| 30609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30612 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30613 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30614 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30615 | // (MOVA_4ZMXI_V_D ZZZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4129 |
| 30616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30619 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30620 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30621 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30622 | // (MOVA_4ZMXI_V_H ZZZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4135 |
| 30623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30624 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30627 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30628 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30629 | // (MOVA_4ZMXI_V_S ZZZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4141 |
| 30630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30635 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30636 | // (MOVA_MXI2Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4147 |
| 30637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30638 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30640 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30643 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30644 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30645 | // (MOVA_MXI2Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4155 |
| 30646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30647 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30648 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30649 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30652 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30653 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30654 | // (MOVA_MXI2Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4163 |
| 30655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30656 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30658 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30661 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30662 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30663 | // (MOVA_MXI2Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4171 |
| 30664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30665 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30667 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30669 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30670 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30671 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30672 | // (MOVA_MXI2Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4179 |
| 30673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30674 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30676 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30678 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30680 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30681 | // (MOVA_MXI2Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4187 |
| 30682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30683 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30685 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30689 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30690 | // (MOVA_MXI2Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4195 |
| 30691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30692 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30694 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30695 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30698 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30699 | // (MOVA_MXI2Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4203 |
| 30700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30701 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30703 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30704 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30706 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30707 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30708 | // (MOVA_MXI4Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4211 |
| 30709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30710 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30711 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30712 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30714 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30715 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30716 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30717 | // (MOVA_MXI4Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4219 |
| 30718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30719 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30720 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30721 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30723 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30724 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30725 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30726 | // (MOVA_MXI4Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4227 |
| 30727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30728 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30729 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30730 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30732 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30734 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30735 | // (MOVA_MXI4Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4235 |
| 30736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30737 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30739 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30741 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30743 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30744 | // (MOVA_MXI4Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4243 |
| 30745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30746 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30748 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30752 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30753 | // (MOVA_MXI4Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4251 |
| 30754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30755 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30757 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30759 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30761 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30762 | // (MOVA_MXI4Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4259 |
| 30763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30764 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30766 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30770 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30771 | // (MOVA_MXI4Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4267 |
| 30772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30773 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30775 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30778 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30779 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30780 | // (MOVA_VG2_2ZMXI ZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4275 |
| 30781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 30783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 30784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30786 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30787 | // (MOVA_VG2_MXI2Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZ_d_mul_r:$Zn) - 4281 |
| 30788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 30789 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 30791 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30794 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30795 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30796 | // (MOVA_VG4_4ZMXI ZZZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4289 |
| 30797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 30799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 30800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30803 | // (MOVA_VG4_MXI4Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZZZ_d_mul_r:$Zn) - 4295 |
| 30804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 30805 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 30807 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30810 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30811 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30812 | // (MOVT ZTR:$ZTt, 0, ZPRAny:$Zt) - 4303 |
| 30813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZTRRegClassID}, |
| 30814 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30819 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30820 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME_LUTv2}, |
| 30821 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30822 | // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 4312 |
| 30823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 30824 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 30825 | // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 4314 |
| 30826 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 30827 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 30828 | // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 4316 |
| 30829 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 30830 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 30831 | // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 4318 |
| 30832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 30833 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30834 | // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 4320 |
| 30835 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 30836 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30837 | // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 4322 |
| 30838 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 30839 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30840 | // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4324 |
| 30841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30844 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30845 | // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4328 |
| 30846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30849 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30850 | // (NOTv16i8 V128:$Vd, V128:$Vn) - 4332 |
| 30851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30855 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30856 | // (NOTv8i8 V64:$Vd, V64:$Vn) - 4337 |
| 30857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 30858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 30859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30861 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30862 | // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 4342 |
| 30863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30864 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30866 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30867 | // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 4346 |
| 30868 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30869 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30871 | // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4349 |
| 30872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30875 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30876 | // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 4353 |
| 30877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30878 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30880 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30881 | // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 4357 |
| 30882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30883 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30885 | // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4360 |
| 30886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30888 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30889 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30890 | // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4364 |
| 30891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 30892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 30893 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30894 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30898 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30899 | // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4372 |
| 30900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30901 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30903 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30904 | // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4376 |
| 30905 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30906 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30907 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30908 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30909 | // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4380 |
| 30910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30911 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30913 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30914 | // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4384 |
| 30915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30916 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30918 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30919 | // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4388 |
| 30920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 30921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 30922 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30923 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30926 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30927 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30928 | // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 4396 |
| 30929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30930 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30931 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 30932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30934 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30935 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30936 | // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 4403 |
| 30937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30938 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30939 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 30940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30943 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30944 | // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 4410 |
| 30945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30946 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30947 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 30948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30951 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30952 | // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 4417 |
| 30953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30955 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30958 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30959 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30960 | // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 4424 |
| 30961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30963 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30967 | // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 4430 |
| 30968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 30969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 30970 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 30971 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30973 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30974 | // (PACIA1716) - 4436 |
| 30975 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 30977 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30978 | // (PACIASP) - 4439 |
| 30979 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30980 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 30981 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30982 | // (PACIAZ) - 4442 |
| 30983 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 30985 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30986 | // (PACIB1716) - 4445 |
| 30987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 30989 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30990 | // (PACIBSP) - 4448 |
| 30991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 30993 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30994 | // (PACIBZ) - 4451 |
| 30995 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 30997 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30998 | // (PACM) - 4454 |
| 30999 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuthLR}, |
| 31001 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31002 | // (PMOV_PZI_B PPR8:$Pd, ZPRAny:$Zn, 0) - 4457 |
| 31003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31005 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31007 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 31008 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31009 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31010 | // (PMOV_ZIP_B ZPRAny:$Zd, 0, PPR8:$Pn) - 4464 |
| 31011 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31012 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31013 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31015 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 31017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31018 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31019 | // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4472 |
| 31020 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31023 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31026 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31027 | // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4479 |
| 31028 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31030 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31031 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31035 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31036 | // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4487 |
| 31037 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31038 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31039 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31040 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31044 | // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4494 |
| 31045 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31046 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31047 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31048 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31051 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31052 | // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4501 |
| 31053 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31054 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31056 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31059 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31060 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31061 | // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4509 |
| 31062 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31064 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31065 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31067 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31068 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31069 | // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4516 |
| 31070 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31071 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31072 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31073 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31075 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31076 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31077 | // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4523 |
| 31078 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31079 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31080 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31081 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31082 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31083 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31085 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31086 | // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4531 |
| 31087 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31088 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31090 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31091 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31093 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31094 | // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4538 |
| 31095 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31096 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31097 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31098 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31099 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31100 | // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 4543 |
| 31101 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31102 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31103 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31104 | // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 4546 |
| 31105 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31106 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31107 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31108 | // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4549 |
| 31109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31110 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31112 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31116 | // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4556 |
| 31117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31119 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31120 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31122 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31124 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31125 | // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4564 |
| 31126 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31127 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31128 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31129 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31132 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31133 | // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4571 |
| 31134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31135 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31139 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31140 | // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4577 |
| 31141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31142 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31146 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31147 | // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4583 |
| 31148 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31149 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31150 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31153 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31154 | // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4589 |
| 31155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31156 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31157 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31161 | // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4595 |
| 31162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31163 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31164 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31167 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31168 | // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4601 |
| 31169 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31170 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31174 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31175 | // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4607 |
| 31176 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31177 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31178 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31181 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31182 | // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4613 |
| 31183 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31184 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31185 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31187 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31188 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31189 | // (RET LR) - 4619 |
| 31190 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::LR}, |
| 31191 | // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 4620 |
| 31192 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31193 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31195 | // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 4623 |
| 31196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31197 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31198 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31199 | // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 4626 |
| 31200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31201 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31203 | // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 4629 |
| 31204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31205 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31207 | // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4632 |
| 31208 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31209 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31210 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31211 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31212 | // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4636 |
| 31213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31215 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31216 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 31217 | // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4640 |
| 31218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31220 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31221 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 31222 | // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4644 |
| 31223 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31225 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31226 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(63)}, |
| 31227 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4648 |
| 31228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31230 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31231 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 31232 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4652 |
| 31233 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31235 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31236 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 31237 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4656 |
| 31238 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31239 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31240 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31241 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31242 | // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 4660 |
| 31243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31246 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 31247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31248 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31249 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31250 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31251 | // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 4668 |
| 31252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31255 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 31256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31259 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31260 | // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 4676 |
| 31261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31264 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 31265 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31268 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31269 | // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 4684 |
| 31270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31273 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 31274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31276 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31277 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31278 | // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 4692 |
| 31279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 31281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31282 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 31283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31284 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31285 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31286 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31287 | // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4700 |
| 31288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31291 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31292 | // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4704 |
| 31293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31296 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31297 | // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4708 |
| 31298 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31299 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31300 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31301 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31303 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31305 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31306 | // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4716 |
| 31307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31308 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31309 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31310 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31311 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31312 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31313 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31314 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31315 | // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4724 |
| 31316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31317 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31318 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31319 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31320 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31321 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31323 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31324 | // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4732 |
| 31325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31327 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31328 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31329 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31330 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31332 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31333 | // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4740 |
| 31334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31335 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31336 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31337 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31338 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31339 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31340 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31341 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31342 | // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4748 |
| 31343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31344 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31345 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31346 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31347 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31348 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31350 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31351 | // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4756 |
| 31352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31354 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31355 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31358 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31359 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31360 | // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4764 |
| 31361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31363 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31364 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31365 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31368 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31369 | // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4772 |
| 31370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31371 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31372 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31373 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31375 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31377 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31378 | // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4780 |
| 31379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31380 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31381 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31382 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31386 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31387 | // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4788 |
| 31388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31389 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31390 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31391 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31395 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31396 | // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4796 |
| 31397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31398 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31399 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31400 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31402 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31403 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31404 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31405 | // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4804 |
| 31406 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31407 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31408 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31409 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31413 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31414 | // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4812 |
| 31415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31417 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31418 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31420 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31422 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31423 | // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4820 |
| 31424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31425 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31426 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31427 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31428 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31429 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31431 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31432 | // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4828 |
| 31433 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31434 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31435 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31436 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31437 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31438 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31440 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31441 | // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4836 |
| 31442 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31443 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31444 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31445 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31448 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31449 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31450 | // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4844 |
| 31451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31452 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31453 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31454 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31455 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31456 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31457 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31458 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31459 | // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4852 |
| 31460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31461 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31462 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31463 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31464 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31465 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31467 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31468 | // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4860 |
| 31469 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31471 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31472 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31476 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31477 | // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4868 |
| 31478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31479 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31480 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31481 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31482 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31483 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31485 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31486 | // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4876 |
| 31487 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31488 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31489 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31490 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31491 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31492 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31494 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31495 | // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4884 |
| 31496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31497 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31498 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31499 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31500 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31503 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31504 | // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4892 |
| 31505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31506 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31507 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31508 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31511 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31512 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31513 | // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4900 |
| 31514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31516 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31517 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31519 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31520 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31521 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31522 | // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4908 |
| 31523 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31524 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31525 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31526 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31527 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31528 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31530 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31531 | // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4916 |
| 31532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31533 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31534 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31535 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31540 | // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4924 |
| 31541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31542 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31543 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31544 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31547 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31548 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31549 | // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4932 |
| 31550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31552 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31555 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31556 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31557 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31558 | // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4940 |
| 31559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31561 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31562 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31565 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31566 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31567 | // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4948 |
| 31568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31569 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31570 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31571 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31573 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31574 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31575 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31576 | // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4956 |
| 31577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31578 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31579 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31580 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31581 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31584 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31585 | // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4964 |
| 31586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31587 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31588 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31589 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31593 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31594 | // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4972 |
| 31595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31596 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31597 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31598 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31601 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31602 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31603 | // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4980 |
| 31604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31606 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31607 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31610 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31611 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31612 | // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4988 |
| 31613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31615 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31616 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31618 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31619 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31620 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31621 | // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4996 |
| 31622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31623 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31624 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31625 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31627 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31628 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31629 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31630 | // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 5004 |
| 31631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31632 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31633 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31634 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31635 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31636 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31638 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31639 | // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5012 |
| 31640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31641 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31642 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31643 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31644 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31647 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31648 | // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5020 |
| 31649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31650 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31651 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31652 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31656 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31657 | // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5028 |
| 31658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31660 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31661 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31665 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31666 | // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5036 |
| 31667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31669 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31673 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31674 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31675 | // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5044 |
| 31676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31677 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31678 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 31679 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31682 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31683 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31684 | // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 5052 |
| 31685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31686 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31687 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31688 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 31689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31690 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31691 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31692 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31693 | // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5060 |
| 31694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31695 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31696 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31697 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31698 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31699 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31700 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31701 | // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5067 |
| 31702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31704 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31705 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31706 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31707 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31708 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31709 | // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5074 |
| 31710 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31711 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31713 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31714 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31715 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31716 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31717 | // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5081 |
| 31718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31719 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31720 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31721 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31722 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31723 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31724 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31725 | // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5088 |
| 31726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31728 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31729 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31730 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31731 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31732 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31733 | // (SST1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 5095 |
| 31734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31737 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31738 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31739 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31740 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31741 | // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5102 |
| 31742 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31743 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31744 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31745 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31746 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31747 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31748 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31749 | // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5109 |
| 31750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31752 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31753 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31755 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31756 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31757 | // (ST1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5116 |
| 31758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31760 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31761 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31764 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31765 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31766 | // (ST1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5124 |
| 31767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31769 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31770 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31772 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31773 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31774 | // (ST1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5131 |
| 31775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31778 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31781 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31782 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31783 | // (ST1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5139 |
| 31784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31786 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31787 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31790 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31791 | // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5146 |
| 31792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31794 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31795 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31796 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31799 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31800 | // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5154 |
| 31801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31803 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31804 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31805 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31808 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31809 | // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5162 |
| 31810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31814 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31817 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31818 | // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5170 |
| 31819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31822 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31823 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31827 | // (ST1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5178 |
| 31828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31832 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31835 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31836 | // (ST1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5186 |
| 31837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31841 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31843 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31844 | // (ST1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5193 |
| 31845 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31848 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31852 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31853 | // (ST1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5201 |
| 31854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31857 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31860 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31861 | // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5208 |
| 31862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31866 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31869 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31870 | // (ST1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5216 |
| 31871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31874 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31877 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31878 | // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5223 |
| 31879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 31881 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31882 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31884 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31885 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31886 | // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 5230 |
| 31887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31888 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 31889 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31890 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31891 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31892 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31893 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31894 | // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5237 |
| 31895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 31897 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31898 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31899 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31900 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31901 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31902 | // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5244 |
| 31903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 31905 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31906 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31908 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31909 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31910 | // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5251 |
| 31911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 31913 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31914 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31917 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31918 | // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5258 |
| 31919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 31921 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31922 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31925 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31926 | // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5265 |
| 31927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 31929 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31930 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31931 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31933 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31934 | // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5272 |
| 31935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 31937 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31938 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31939 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31941 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31942 | // (ST1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5279 |
| 31943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31946 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31951 | // (ST1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5287 |
| 31952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31955 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31958 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31959 | // (ST1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5294 |
| 31960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31963 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31966 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31967 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31968 | // (ST1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5302 |
| 31969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31970 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31971 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31972 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31974 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31975 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31976 | // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5309 |
| 31977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31978 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31979 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31980 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31981 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31982 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31983 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31984 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31985 | // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5317 |
| 31986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31987 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31989 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31990 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31993 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31994 | // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5325 |
| 31995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31998 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31999 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32002 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32003 | // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 5333 |
| 32004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32006 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32007 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32008 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32010 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32011 | // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 5340 |
| 32012 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32014 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32015 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32018 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32019 | // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 5347 |
| 32020 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32022 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32023 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32026 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32027 | // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 5354 |
| 32028 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32030 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32031 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32034 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32035 | // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 5361 |
| 32036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32038 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32039 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32042 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32043 | // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 5368 |
| 32044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32045 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32047 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32050 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32051 | // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 5375 |
| 32052 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32054 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32055 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32058 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32059 | // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 5382 |
| 32060 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32061 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32062 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32063 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32066 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32067 | // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5389 |
| 32068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32070 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32071 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32074 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32075 | // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 5396 |
| 32076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32078 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32079 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32082 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32083 | // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5403 |
| 32084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32085 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32086 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32087 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32088 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32089 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32090 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32091 | // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5410 |
| 32092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32094 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32095 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32098 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32099 | // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5417 |
| 32100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32101 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32102 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32103 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32105 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32106 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32107 | // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5424 |
| 32108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32109 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32110 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32111 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32114 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32115 | // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5431 |
| 32116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32118 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32119 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32122 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32123 | // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5438 |
| 32124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32126 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32127 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32130 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32131 | // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5445 |
| 32132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32133 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32134 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32135 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32138 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32139 | // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 5452 |
| 32140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32142 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32143 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32146 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32147 | // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5459 |
| 32148 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32150 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32151 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32154 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32155 | // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5466 |
| 32156 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32158 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32159 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32160 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32162 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32163 | // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5473 |
| 32164 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32165 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32166 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32167 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32168 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32170 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32171 | // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5480 |
| 32172 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32173 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32174 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32175 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32177 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32178 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32179 | // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5487 |
| 32180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32181 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32182 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32183 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32184 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32185 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32186 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32187 | // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5494 |
| 32188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32189 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32190 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32191 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32192 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32193 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32194 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32195 | // (ST1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5501 |
| 32196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32197 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32198 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32199 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32201 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32202 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32203 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32204 | // (ST1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5509 |
| 32205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 32206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32208 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32211 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32212 | // (ST1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5516 |
| 32213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32215 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32216 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32218 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32219 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32220 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32221 | // (ST1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5524 |
| 32222 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 32223 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32225 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32227 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32228 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32229 | // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5531 |
| 32230 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32231 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32232 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32233 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32234 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32235 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32236 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32237 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32238 | // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5539 |
| 32239 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32240 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32242 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32244 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32245 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32246 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32247 | // (ST1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5547 |
| 32248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32249 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32251 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32252 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32254 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32255 | // (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5554 |
| 32256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32258 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32261 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32262 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32263 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32264 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32265 | // (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5563 |
| 32266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32268 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32271 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32274 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32275 | // (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5572 |
| 32276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32278 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32281 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32285 | // (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5581 |
| 32286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 32287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32288 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32291 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32293 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32294 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32295 | // (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5590 |
| 32296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32298 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32301 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32303 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32304 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32305 | // (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5599 |
| 32306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32308 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32311 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32312 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32313 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32314 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32315 | // (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5608 |
| 32316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32317 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32318 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32321 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32324 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32325 | // (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5617 |
| 32326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32328 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32331 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32334 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32335 | // (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5626 |
| 32336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 32337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32338 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32340 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32341 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32343 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32344 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32345 | // (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5635 |
| 32346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32348 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32349 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32350 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32351 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32352 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32353 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32354 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32355 | // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 5644 |
| 32356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32357 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32358 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32359 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32360 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32361 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32363 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32364 | // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 5652 |
| 32365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32367 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32368 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32369 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32371 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32372 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32373 | // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 5660 |
| 32374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32375 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32376 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32377 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32378 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32380 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32381 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32382 | // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 5668 |
| 32383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32385 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32386 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32387 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32388 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32389 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32390 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32391 | // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5676 |
| 32392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 32393 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32394 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32395 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32399 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32400 | // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5684 |
| 32401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 32402 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32404 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32407 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32408 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32409 | // (ST2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 5692 |
| 32410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32412 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 32415 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32416 | // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5698 |
| 32417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 32418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32420 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32423 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32424 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32425 | // (ST2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5706 |
| 32426 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 32427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32429 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 32432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32433 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32434 | // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5714 |
| 32435 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32437 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32438 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32441 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32442 | // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5721 |
| 32443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32445 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32446 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32448 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32449 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32450 | // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5728 |
| 32451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32453 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32454 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32455 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32456 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32457 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32458 | // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5735 |
| 32459 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32461 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32462 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32463 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32464 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32465 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32466 | // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5742 |
| 32467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32468 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32469 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32470 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32471 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32472 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32473 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32474 | // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5749 |
| 32475 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32476 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 32477 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32478 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32479 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32480 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32481 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32482 | // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5756 |
| 32483 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32484 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32485 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32486 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32488 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32489 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32490 | // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5763 |
| 32491 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 32492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32493 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32494 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32496 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32497 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32498 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32499 | // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 5771 |
| 32500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32501 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32502 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32503 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32504 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32507 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32508 | // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 5779 |
| 32509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32511 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32512 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32513 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32515 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32516 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32517 | // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 5787 |
| 32518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32520 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32521 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32522 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32524 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32525 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32526 | // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 5795 |
| 32527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 32529 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32530 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32531 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32532 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32533 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32534 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32535 | // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5803 |
| 32536 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 32537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32539 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32540 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32541 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32543 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32544 | // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5811 |
| 32545 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 32546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32548 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32549 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32552 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32553 | // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5819 |
| 32554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 32555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32557 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32560 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32561 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32562 | // (ST3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5827 |
| 32563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 32564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32565 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32566 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32567 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32568 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 32569 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32570 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32571 | // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5835 |
| 32572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32573 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32574 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32575 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32576 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32578 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32579 | // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5842 |
| 32580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32582 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32583 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32585 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32586 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32587 | // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5849 |
| 32588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32590 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32591 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32593 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32594 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32595 | // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5856 |
| 32596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32598 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32599 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32601 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32602 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32603 | // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5863 |
| 32604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32606 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32607 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32610 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32611 | // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5870 |
| 32612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 32614 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32615 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32618 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32619 | // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5877 |
| 32620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32622 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32623 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32624 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32626 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32627 | // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5884 |
| 32628 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 32629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32631 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32632 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32635 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32636 | // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 5892 |
| 32637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32639 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32640 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32641 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32643 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32644 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32645 | // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 5900 |
| 32646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32647 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32648 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32649 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32650 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32652 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32653 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32654 | // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 5908 |
| 32655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32657 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32658 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32659 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32661 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32662 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32663 | // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 5916 |
| 32664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 32666 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32667 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32668 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32669 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32670 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32671 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32672 | // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5924 |
| 32673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 32674 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32676 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32678 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32680 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32681 | // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5932 |
| 32682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 32683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32685 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32689 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32690 | // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5940 |
| 32691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32693 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32694 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32695 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32697 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32698 | // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5947 |
| 32699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32701 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32702 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32703 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32705 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32706 | // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5954 |
| 32707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 32709 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32710 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32713 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32714 | // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5961 |
| 32715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 32717 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32718 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32721 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32722 | // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5968 |
| 32723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32725 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32726 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32729 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32730 | // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5975 |
| 32731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 32733 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32734 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32737 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32738 | // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5982 |
| 32739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32741 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32742 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32745 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32746 | // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5989 |
| 32747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 32748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32750 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32754 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32755 | // (ST4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5997 |
| 32756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 32757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32759 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 32762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32763 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32764 | // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6005 |
| 32765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 32766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32768 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32772 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32773 | // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 6013 |
| 32774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32776 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32777 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32778 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32781 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32782 | // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 6021 |
| 32783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32785 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32786 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32787 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32790 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32791 | // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 6029 |
| 32792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32794 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32795 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32796 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32799 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32800 | // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 6037 |
| 32801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 32803 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32804 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32805 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32808 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32809 | // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6045 |
| 32810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32814 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 32816 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32817 | // (STGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6052 |
| 32818 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32820 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32821 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32822 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 32823 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32824 | // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6058 |
| 32825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32826 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32827 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32828 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32829 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 32830 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32831 | // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6064 |
| 32832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32834 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32836 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 32837 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32838 | // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6070 |
| 32839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32841 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 32844 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32845 | // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6076 |
| 32846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32848 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 32851 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32852 | // (STLURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 6082 |
| 32853 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 32854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32856 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32857 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 32858 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32861 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32862 | // (STLURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 6091 |
| 32863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32866 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 32868 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32871 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32872 | // (STLURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 6100 |
| 32873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 32874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32875 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 32878 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32879 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32880 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32881 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32882 | // (STLURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 6109 |
| 32883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32885 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32886 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 32888 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32891 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32892 | // (STLURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 6118 |
| 32893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 32894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 32898 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32899 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32900 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32901 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32902 | // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6127 |
| 32903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32905 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32906 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32908 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32909 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32910 | // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6134 |
| 32911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32914 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32917 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32918 | // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6141 |
| 32919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 32920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 32921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32922 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32925 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32926 | // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6148 |
| 32927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32930 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32931 | // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6152 |
| 32932 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32935 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32936 | // (STNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6156 |
| 32937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32940 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32943 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32944 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32945 | // (STNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6164 |
| 32946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 32947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32948 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32951 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32952 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32953 | // (STNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6171 |
| 32954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32957 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32958 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32959 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 32961 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32962 | // (STNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6179 |
| 32963 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 32964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32966 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32967 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32969 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32970 | // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6186 |
| 32971 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32974 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32975 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32978 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32979 | // (STNT1B_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6194 |
| 32980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32983 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 32986 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32987 | // (STNT1B_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6201 |
| 32988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 32990 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32991 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 32994 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32995 | // (STNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6208 |
| 32996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 32998 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33003 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33004 | // (STNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6216 |
| 33005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 33006 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33008 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33011 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33012 | // (STNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6223 |
| 33013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 33014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33020 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33021 | // (STNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6231 |
| 33022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 33023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33024 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33025 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33027 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33028 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33029 | // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6238 |
| 33030 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33031 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33032 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33033 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33035 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33037 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33038 | // (STNT1D_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6246 |
| 33039 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33040 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33041 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33042 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33043 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 33045 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33046 | // (STNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6253 |
| 33047 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 33048 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33050 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33052 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33054 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33055 | // (STNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6261 |
| 33056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 33057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33058 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33059 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33062 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33063 | // (STNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6268 |
| 33064 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 33065 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33066 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33067 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33068 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33071 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33072 | // (STNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6276 |
| 33073 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 33074 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33076 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33079 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33080 | // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6283 |
| 33081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33084 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33088 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33089 | // (STNT1H_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6291 |
| 33090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33093 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 33096 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33097 | // (STNT1H_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6298 |
| 33098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33101 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 33104 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33105 | // (STNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6305 |
| 33106 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 33107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33109 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33113 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33114 | // (STNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6313 |
| 33115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 33116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33118 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33121 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33122 | // (STNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6320 |
| 33123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 33124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33126 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33130 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33131 | // (STNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6328 |
| 33132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 33133 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33135 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33138 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33139 | // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6335 |
| 33140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33142 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33143 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33147 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33148 | // (STNT1W_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6343 |
| 33149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33151 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33152 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 33155 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33156 | // (STNT1W_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6350 |
| 33157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33159 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33160 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 33163 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33164 | // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6357 |
| 33165 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33166 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33168 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33171 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33172 | // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6364 |
| 33173 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33174 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33176 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33177 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33178 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33179 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33180 | // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6371 |
| 33181 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 33182 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 33183 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33184 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33185 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33187 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33188 | // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6378 |
| 33189 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33190 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33191 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33192 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33193 | // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6382 |
| 33194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33197 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33198 | // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6386 |
| 33199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33201 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33202 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33203 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33204 | // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6391 |
| 33205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33207 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33208 | // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6394 |
| 33209 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 33210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33212 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33213 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33214 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33216 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33217 | // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6402 |
| 33218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 33219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33220 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33221 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33223 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33224 | // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6408 |
| 33225 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33228 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33229 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33232 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33233 | // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6416 |
| 33234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33236 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33237 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33239 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33240 | // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6422 |
| 33241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33244 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33245 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33246 | // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6427 |
| 33247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33249 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33250 | // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6430 |
| 33251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 33252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33254 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33255 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33258 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33259 | // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6438 |
| 33260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 33261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33262 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33263 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33264 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33265 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33266 | // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6444 |
| 33267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33268 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33270 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33271 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33274 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33275 | // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6452 |
| 33276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33278 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33280 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33281 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33282 | // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6458 |
| 33283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 33284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33285 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33286 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33287 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33289 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33290 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33291 | // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6466 |
| 33292 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 33293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33294 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33297 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33298 | // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6472 |
| 33299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33301 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33302 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33303 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33304 | // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6477 |
| 33305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33307 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33308 | // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6480 |
| 33309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33311 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33312 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33313 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33314 | // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 6485 |
| 33315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33317 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33318 | // (STR_PXI PPRorPNRAny:$Pt, GPR64sp:$Rn, 0) - 6488 |
| 33319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRorPNRRegClassID}, |
| 33320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33321 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33324 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33325 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33326 | // (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 6495 |
| 33327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 33328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 33329 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33331 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33334 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33335 | // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 6503 |
| 33336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33338 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33339 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33340 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33342 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33343 | // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6510 |
| 33344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33346 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33347 | // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6513 |
| 33348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33349 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33350 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33351 | // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6516 |
| 33352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33354 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33355 | // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6519 |
| 33356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33357 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33358 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33359 | // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6522 |
| 33360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33362 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33363 | // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6525 |
| 33364 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 33365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33366 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33368 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33369 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33370 | // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6531 |
| 33371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33372 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33373 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33375 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33376 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33377 | // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6537 |
| 33378 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33380 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33381 | // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6540 |
| 33382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 33383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33384 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33387 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33388 | // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6546 |
| 33389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33391 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33394 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33395 | // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6552 |
| 33396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 33397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33398 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33399 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 33401 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33402 | // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6558 |
| 33403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33405 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33406 | // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 6561 |
| 33407 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33409 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33410 | // (STZ2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6564 |
| 33411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33412 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33413 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33415 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 33416 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33417 | // (STZGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6570 |
| 33418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33420 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 33423 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33424 | // (SUBPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 6576 |
| 33425 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33426 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33428 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33429 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCPA}, |
| 33431 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33432 | // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 6583 |
| 33433 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33434 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 33435 | // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 6585 |
| 33436 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33439 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33440 | // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6589 |
| 33441 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33442 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33444 | // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 6592 |
| 33445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33446 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33448 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33449 | // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 6596 |
| 33450 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33451 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33453 | // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 6599 |
| 33454 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33457 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33458 | // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 6603 |
| 33459 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 33461 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33462 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 33463 | // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 6607 |
| 33464 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 33466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33467 | // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 6610 |
| 33468 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33469 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 33470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33471 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 33472 | // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 6614 |
| 33473 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33475 | // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 6616 |
| 33476 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33477 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33479 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33480 | // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 6620 |
| 33481 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33483 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33484 | // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 6623 |
| 33485 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33486 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33487 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33488 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33489 | // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 6627 |
| 33490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33491 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33493 | // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 6630 |
| 33494 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33495 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33497 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33498 | // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 6634 |
| 33499 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33501 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33502 | // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 6637 |
| 33503 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33504 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 33505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33506 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 33507 | // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 6641 |
| 33508 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33511 | // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6644 |
| 33512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33513 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 33514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33515 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 33516 | // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 6648 |
| 33517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33518 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33520 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33521 | // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 6652 |
| 33522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33523 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33524 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33525 | // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 6655 |
| 33526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33529 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33530 | // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 6659 |
| 33531 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 33532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 33533 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33534 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 33535 | // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 6663 |
| 33536 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 33537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 33538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33539 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 33540 | // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 6667 |
| 33541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33542 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33543 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33544 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33545 | // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 6671 |
| 33546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33547 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33549 | // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 6674 |
| 33550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33552 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33554 | // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 6678 |
| 33555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 33556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33558 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 33559 | // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6682 |
| 33560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 33562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33563 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 33564 | // (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6686 |
| 33565 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33566 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33567 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33568 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33569 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureD128}, |
| 33572 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33573 | // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6694 |
| 33574 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33575 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33576 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33577 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33578 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33579 | // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 6699 |
| 33580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33582 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33583 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33584 | // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 6703 |
| 33585 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33587 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33588 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 33589 | // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 6707 |
| 33590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33591 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33592 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33593 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 33594 | // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 6711 |
| 33595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33597 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33598 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(63)}, |
| 33599 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 6715 |
| 33600 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33602 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33603 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 33604 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 6719 |
| 33605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33606 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33607 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33608 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 33609 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 6723 |
| 33610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33612 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33613 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33614 | // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6727 |
| 33615 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33618 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33619 | // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 6731 |
| 33620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33622 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33623 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33624 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33625 | // (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 6736 |
| 33626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33628 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33630 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33631 | // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 6741 |
| 33632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33633 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33635 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33636 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33637 | // (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 6746 |
| 33638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33640 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33641 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33642 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33643 | // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6751 |
| 33644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33647 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33648 | // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6755 |
| 33649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33650 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33651 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33652 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33656 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33657 | // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6763 |
| 33658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33659 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33660 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33661 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33665 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33666 | // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6771 |
| 33667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33668 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33669 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33673 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33674 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33675 | // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6779 |
| 33676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33677 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33678 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33679 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33682 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33683 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33684 | // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6787 |
| 33685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33686 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33687 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33688 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33690 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33691 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33692 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33693 | // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6795 |
| 33694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33695 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33696 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33697 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33698 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33699 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33700 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33701 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33702 | // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6803 |
| 33703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33704 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33705 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33706 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33707 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33708 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33709 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33710 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33711 | // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6811 |
| 33712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33713 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33714 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33715 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33716 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33717 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33719 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33720 | // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6819 |
| 33721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33722 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33723 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33724 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33725 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33726 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33728 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33729 | // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 6827 |
| 33730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33731 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33732 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33733 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33734 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33737 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33738 | // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6835 |
| 33739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33740 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33741 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33742 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33746 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33747 | // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6843 |
| 33748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33749 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33750 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33751 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33755 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33756 | // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6851 |
| 33757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33758 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33759 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33764 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33765 | // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6859 |
| 33766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33767 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33768 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33769 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33772 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33773 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33774 | // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6867 |
| 33775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33776 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33777 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33778 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33781 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33782 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33783 | // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 6875 |
| 33784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33785 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33786 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33787 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33791 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33792 | // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6883 |
| 33793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33794 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33795 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33796 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33799 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33800 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33801 | // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6891 |
| 33802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33803 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33804 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33805 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33809 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33810 | // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6899 |
| 33811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33814 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33819 | // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6907 |
| 33820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33821 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33822 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33827 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33828 | // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6915 |
| 33829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33830 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33837 | // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 6923 |
| 33838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33839 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33840 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33841 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33844 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33845 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33846 | // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6931 |
| 33847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33849 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33850 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33852 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33854 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33855 | // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6939 |
| 33856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33857 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33858 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33859 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33862 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33863 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33864 | // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6947 |
| 33865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33866 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33871 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33872 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33873 | // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6955 |
| 33874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33875 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33876 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33877 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33879 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33880 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33881 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33882 | // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6963 |
| 33883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33884 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33885 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33886 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33890 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33891 | // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6971 |
| 33892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33893 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33894 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33899 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33900 | // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6979 |
| 33901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33902 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33903 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33908 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33909 | // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6987 |
| 33910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33911 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33912 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33913 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33917 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33918 | // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6995 |
| 33919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33920 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33921 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33922 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33926 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33927 | // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 7003 |
| 33928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33929 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33930 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33931 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33934 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33935 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33936 | // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7011 |
| 33937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33938 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33939 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33940 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33943 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33944 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33945 | // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7019 |
| 33946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33947 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33948 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33951 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33952 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33953 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33954 | // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7027 |
| 33955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33956 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33957 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33958 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33959 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33962 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33963 | // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7035 |
| 33964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33965 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33966 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33967 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33971 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33972 | // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7043 |
| 33973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33974 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33975 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33976 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33979 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33980 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33981 | // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 7051 |
| 33982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33983 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33984 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33985 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33989 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33990 | // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7059 |
| 33991 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33992 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33993 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33994 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33995 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33998 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33999 | // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7067 |
| 34000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 34001 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34002 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 34004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34007 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34008 | // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7075 |
| 34009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34010 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34011 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 34012 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 34013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34014 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34015 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34016 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34017 | // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7083 |
| 34018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34019 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34020 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34021 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 34022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34025 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34026 | // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7091 |
| 34027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34028 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34029 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 34030 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 34031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34034 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34035 | // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 7099 |
| 34036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34037 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34038 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34039 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 34040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34044 | // (XPACLRI) - 7107 |
| 34045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 34047 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34048 | // (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 7110 |
| 34049 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(255)}, |
| 34050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34052 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34053 | // (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 7114 |
| 34054 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(85)}, |
| 34055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34057 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34058 | // (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 7118 |
| 34059 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(170)}, |
| 34060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34062 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34063 | // (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 7122 |
| 34064 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(17)}, |
| 34065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34067 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34068 | // (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 7126 |
| 34069 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(34)}, |
| 34070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34072 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34073 | // (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 7130 |
| 34074 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(68)}, |
| 34075 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34077 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34078 | // (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 7134 |
| 34079 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)}, |
| 34080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34082 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34083 | // (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 7138 |
| 34084 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(51)}, |
| 34085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34087 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34088 | // (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 7142 |
| 34089 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(153)}, |
| 34090 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34091 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34092 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34093 | // (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 7146 |
| 34094 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(102)}, |
| 34095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34097 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34098 | // (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 7150 |
| 34099 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(204)}, |
| 34100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34102 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34103 | // (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 7154 |
| 34104 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(119)}, |
| 34105 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34107 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34108 | // (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 7158 |
| 34109 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(187)}, |
| 34110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34113 | // (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 7162 |
| 34114 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(221)}, |
| 34115 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34117 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34118 | // (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 7166 |
| 34119 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(238)}, |
| 34120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34122 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34123 | }; |
| 34124 | |
| 34125 | static const char AsmStrings[] = |
| 34126 | /* 0 */ "addpt $\x01, $\x02, $\x03\0" |
| 34127 | /* 17 */ "cmn $\x02, $\xFF\x03\x01\0" |
| 34128 | /* 30 */ "cmn $\x02, $\x03\0" |
| 34129 | /* 41 */ "cmn $\x02, $\x03$\xFF\x04\x02\0" |
| 34130 | /* 56 */ "adds $\x01, $\x02, $\x03\0" |
| 34131 | /* 72 */ "cmn $\x02, $\x03$\xFF\x04\x03\0" |
| 34132 | /* 87 */ "mov $\x01, $\x02\0" |
| 34133 | /* 98 */ "add $\x01, $\x02, $\x03\0" |
| 34134 | /* 113 */ "tst $\x02, $\xFF\x03\x04\0" |
| 34135 | /* 126 */ "tst $\x02, $\x03\0" |
| 34136 | /* 137 */ "tst $\x02, $\x03$\xFF\x04\x02\0" |
| 34137 | /* 152 */ "ands $\x01, $\x02, $\x03\0" |
| 34138 | /* 168 */ "tst $\x02, $\xFF\x03\x05\0" |
| 34139 | /* 181 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 34140 | /* 205 */ "and $\x01, $\x02, $\x03\0" |
| 34141 | /* 220 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 34142 | /* 243 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 34143 | /* 264 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 34144 | /* 285 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 34145 | /* 306 */ "autia1716\0" |
| 34146 | /* 316 */ "autiasp\0" |
| 34147 | /* 324 */ "autiaz\0" |
| 34148 | /* 331 */ "autib1716\0" |
| 34149 | /* 341 */ "autibsp\0" |
| 34150 | /* 349 */ "autibz\0" |
| 34151 | /* 356 */ "bics $\x01, $\x02, $\x03\0" |
| 34152 | /* 372 */ "bic $\x01, $\x02, $\x03\0" |
| 34153 | /* 387 */ "chkfeat x16\0" |
| 34154 | /* 399 */ "clrex\0" |
| 34155 | /* 405 */ "cntb $\x01\0" |
| 34156 | /* 413 */ "cntb $\x01, $\xFF\x02\x0E\0" |
| 34157 | /* 427 */ "cntd $\x01\0" |
| 34158 | /* 435 */ "cntd $\x01, $\xFF\x02\x0E\0" |
| 34159 | /* 449 */ "cnth $\x01\0" |
| 34160 | /* 457 */ "cnth $\x01, $\xFF\x02\x0E\0" |
| 34161 | /* 471 */ "cntw $\x01\0" |
| 34162 | /* 479 */ "cntw $\x01, $\xFF\x02\x0E\0" |
| 34163 | /* 493 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0" |
| 34164 | /* 516 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0" |
| 34165 | /* 539 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0" |
| 34166 | /* 562 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0" |
| 34167 | /* 585 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0" |
| 34168 | /* 606 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0" |
| 34169 | /* 627 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0" |
| 34170 | /* 648 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0" |
| 34171 | /* 669 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0" |
| 34172 | /* 692 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0" |
| 34173 | /* 715 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0" |
| 34174 | /* 738 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0" |
| 34175 | /* 761 */ "cset $\x01, $\xFF\x04\x14\0" |
| 34176 | /* 775 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0" |
| 34177 | /* 793 */ "csetm $\x01, $\xFF\x04\x14\0" |
| 34178 | /* 808 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0" |
| 34179 | /* 826 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0" |
| 34180 | /* 844 */ "dcps1\0" |
| 34181 | /* 850 */ "dcps2\0" |
| 34182 | /* 856 */ "dcps3\0" |
| 34183 | /* 862 */ "decb $\x01\0" |
| 34184 | /* 870 */ "decb $\x01, $\xFF\x03\x0E\0" |
| 34185 | /* 884 */ "decd $\x01\0" |
| 34186 | /* 892 */ "decd $\x01, $\xFF\x03\x0E\0" |
| 34187 | /* 906 */ "decd $\xFF\x01\x10\0" |
| 34188 | /* 916 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 34189 | /* 932 */ "dech $\x01\0" |
| 34190 | /* 940 */ "dech $\x01, $\xFF\x03\x0E\0" |
| 34191 | /* 954 */ "dech $\xFF\x01\x09\0" |
| 34192 | /* 964 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 34193 | /* 980 */ "decw $\x01\0" |
| 34194 | /* 988 */ "decw $\x01, $\xFF\x03\x0E\0" |
| 34195 | /* 1002 */ "decw $\xFF\x01\x0B\0" |
| 34196 | /* 1012 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 34197 | /* 1028 */ "ssbb\0" |
| 34198 | /* 1033 */ "pssbb\0" |
| 34199 | /* 1039 */ "dfb\0" |
| 34200 | /* 1043 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0" |
| 34201 | /* 1058 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0" |
| 34202 | /* 1073 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0" |
| 34203 | /* 1088 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0" |
| 34204 | /* 1104 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0" |
| 34205 | /* 1120 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0" |
| 34206 | /* 1136 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0" |
| 34207 | /* 1151 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0" |
| 34208 | /* 1166 */ "fmov $\xFF\x01\x10, #0.0\0" |
| 34209 | /* 1182 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0" |
| 34210 | /* 1197 */ "fmov $\xFF\x01\x09, #0.0\0" |
| 34211 | /* 1213 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0" |
| 34212 | /* 1228 */ "fmov $\xFF\x01\x0B, #0.0\0" |
| 34213 | /* 1244 */ "mov $\xFF\x01\x06, $\x02\0" |
| 34214 | /* 1257 */ "mov $\xFF\x01\x10, $\x02\0" |
| 34215 | /* 1270 */ "mov $\xFF\x01\x09, $\x02\0" |
| 34216 | /* 1283 */ "mov $\xFF\x01\x0B, $\x02\0" |
| 34217 | /* 1296 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0" |
| 34218 | /* 1311 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0" |
| 34219 | /* 1330 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0" |
| 34220 | /* 1345 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0" |
| 34221 | /* 1364 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0" |
| 34222 | /* 1379 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0" |
| 34223 | /* 1398 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0" |
| 34224 | /* 1413 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0" |
| 34225 | /* 1432 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0" |
| 34226 | /* 1447 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0" |
| 34227 | /* 1466 */ "eon $\x01, $\x02, $\x03\0" |
| 34228 | /* 1481 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 34229 | /* 1505 */ "eor $\x01, $\x02, $\x03\0" |
| 34230 | /* 1520 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 34231 | /* 1543 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 34232 | /* 1564 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 34233 | /* 1585 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 34234 | /* 1606 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 34235 | /* 1639 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 34236 | /* 1672 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 34237 | /* 1705 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 34238 | /* 1738 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 34239 | /* 1771 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 34240 | /* 1804 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 34241 | /* 1837 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 34242 | /* 1870 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 34243 | /* 1903 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 34244 | /* 1936 */ "ror $\x01, $\x02, $\x04\0" |
| 34245 | /* 1951 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 34246 | /* 1975 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 34247 | /* 1999 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 34248 | /* 2023 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0" |
| 34249 | /* 2039 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0" |
| 34250 | /* 2055 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0" |
| 34251 | /* 2071 */ "gcspopm\0" |
| 34252 | /* 2079 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34253 | /* 2105 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34254 | /* 2131 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34255 | /* 2157 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34256 | /* 2183 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34257 | /* 2209 */ "ld1q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34258 | /* 2235 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34259 | /* 2262 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34260 | /* 2289 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34261 | /* 2316 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34262 | /* 2343 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34263 | /* 2370 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34264 | /* 2396 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34265 | /* 2422 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34266 | /* 2450 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34267 | /* 2478 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34268 | /* 2506 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34269 | /* 2534 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34270 | /* 2562 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34271 | /* 2591 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34272 | /* 2620 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34273 | /* 2649 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34274 | /* 2678 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34275 | /* 2707 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34276 | /* 2735 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34277 | /* 2763 */ "nop\0" |
| 34278 | /* 2767 */ "yield\0" |
| 34279 | /* 2773 */ "wfe\0" |
| 34280 | /* 2777 */ "wfi\0" |
| 34281 | /* 2781 */ "sev\0" |
| 34282 | /* 2785 */ "sevl\0" |
| 34283 | /* 2790 */ "dgh\0" |
| 34284 | /* 2794 */ "esb\0" |
| 34285 | /* 2798 */ "csdb\0" |
| 34286 | /* 2803 */ "bti\0" |
| 34287 | /* 2807 */ "bti $\xFF\x01\x26\0" |
| 34288 | /* 2816 */ "psb $\xFF\x01\x27\0" |
| 34289 | /* 2825 */ "gcsb dsync\0" |
| 34290 | /* 2836 */ "clrbhb\0" |
| 34291 | /* 2843 */ "incb $\x01\0" |
| 34292 | /* 2851 */ "incb $\x01, $\xFF\x03\x0E\0" |
| 34293 | /* 2865 */ "incd $\x01\0" |
| 34294 | /* 2873 */ "incd $\x01, $\xFF\x03\x0E\0" |
| 34295 | /* 2887 */ "incd $\xFF\x01\x10\0" |
| 34296 | /* 2897 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 34297 | /* 2913 */ "inch $\x01\0" |
| 34298 | /* 2921 */ "inch $\x01, $\xFF\x03\x0E\0" |
| 34299 | /* 2935 */ "inch $\xFF\x01\x09\0" |
| 34300 | /* 2945 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 34301 | /* 2961 */ "incw $\x01\0" |
| 34302 | /* 2969 */ "incw $\x01, $\xFF\x03\x0E\0" |
| 34303 | /* 2983 */ "incw $\xFF\x01\x0B\0" |
| 34304 | /* 2993 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 34305 | /* 3009 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| 34306 | /* 3042 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| 34307 | /* 3075 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| 34308 | /* 3108 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| 34309 | /* 3141 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| 34310 | /* 3174 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| 34311 | /* 3207 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| 34312 | /* 3240 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| 34313 | /* 3273 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| 34314 | /* 3306 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| 34315 | /* 3339 */ "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| 34316 | /* 3358 */ "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| 34317 | /* 3383 */ "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| 34318 | /* 3402 */ "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| 34319 | /* 3427 */ "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| 34320 | /* 3446 */ "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| 34321 | /* 3471 */ "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| 34322 | /* 3490 */ "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| 34323 | /* 3515 */ "irg $\x01, $\x02\0" |
| 34324 | /* 3526 */ "isb\0" |
| 34325 | /* 3530 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 34326 | /* 3554 */ "ld1b $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| 34327 | /* 3578 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 34328 | /* 3602 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34329 | /* 3626 */ "ld1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34330 | /* 3650 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34331 | /* 3674 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34332 | /* 3698 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 34333 | /* 3722 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 34334 | /* 3746 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34335 | /* 3770 */ "ld1d $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 34336 | /* 3794 */ "ld1 $\xFF\x02\x2C, [$\x01], #64\0" |
| 34337 | /* 3814 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0" |
| 34338 | /* 3834 */ "ld1 $\xFF\x02\x2E, [$\x01], #64\0" |
| 34339 | /* 3854 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0" |
| 34340 | /* 3874 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0" |
| 34341 | /* 3894 */ "ld1 $\xFF\x02\x31, [$\x01], #64\0" |
| 34342 | /* 3914 */ "ld1 $\xFF\x02\x32, [$\x01], #32\0" |
| 34343 | /* 3934 */ "ld1 $\xFF\x02\x33, [$\x01], #64\0" |
| 34344 | /* 3954 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 34345 | /* 3978 */ "ld1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0" |
| 34346 | /* 4002 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 34347 | /* 4026 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34348 | /* 4050 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34349 | /* 4074 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34350 | /* 4098 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0" |
| 34351 | /* 4118 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0" |
| 34352 | /* 4137 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0" |
| 34353 | /* 4157 */ "ld1 $\xFF\x02\x2F, [$\x01], #8\0" |
| 34354 | /* 4176 */ "ld1 $\xFF\x02\x30, [$\x01], #8\0" |
| 34355 | /* 4195 */ "ld1 $\xFF\x02\x31, [$\x01], #16\0" |
| 34356 | /* 4215 */ "ld1 $\xFF\x02\x32, [$\x01], #8\0" |
| 34357 | /* 4234 */ "ld1 $\xFF\x02\x33, [$\x01], #16\0" |
| 34358 | /* 4254 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34359 | /* 4279 */ "ld1rb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34360 | /* 4304 */ "ld1rb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34361 | /* 4329 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34362 | /* 4354 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34363 | /* 4379 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34364 | /* 4404 */ "ld1rh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34365 | /* 4429 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34366 | /* 4454 */ "ld1rob $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34367 | /* 4480 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34368 | /* 4506 */ "ld1roh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34369 | /* 4532 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34370 | /* 4558 */ "ld1rqb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34371 | /* 4584 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34372 | /* 4610 */ "ld1rqh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34373 | /* 4636 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34374 | /* 4662 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34375 | /* 4688 */ "ld1rsb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34376 | /* 4714 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34377 | /* 4740 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34378 | /* 4766 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34379 | /* 4792 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34380 | /* 4818 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34381 | /* 4843 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34382 | /* 4868 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0" |
| 34383 | /* 4888 */ "ld1r $\xFF\x02\x2D, [$\x01], #8\0" |
| 34384 | /* 4908 */ "ld1r $\xFF\x02\x2E, [$\x01], #8\0" |
| 34385 | /* 4928 */ "ld1r $\xFF\x02\x2F, [$\x01], #4\0" |
| 34386 | /* 4948 */ "ld1r $\xFF\x02\x30, [$\x01], #2\0" |
| 34387 | /* 4968 */ "ld1r $\xFF\x02\x31, [$\x01], #4\0" |
| 34388 | /* 4988 */ "ld1r $\xFF\x02\x32, [$\x01], #1\0" |
| 34389 | /* 5008 */ "ld1r $\xFF\x02\x33, [$\x01], #2\0" |
| 34390 | /* 5028 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34391 | /* 5053 */ "ld1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34392 | /* 5078 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34393 | /* 5103 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34394 | /* 5128 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34395 | /* 5153 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34396 | /* 5178 */ "ld1 $\xFF\x02\x2C, [$\x01], #48\0" |
| 34397 | /* 5198 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0" |
| 34398 | /* 5218 */ "ld1 $\xFF\x02\x2E, [$\x01], #48\0" |
| 34399 | /* 5238 */ "ld1 $\xFF\x02\x2F, [$\x01], #24\0" |
| 34400 | /* 5258 */ "ld1 $\xFF\x02\x30, [$\x01], #24\0" |
| 34401 | /* 5278 */ "ld1 $\xFF\x02\x31, [$\x01], #48\0" |
| 34402 | /* 5298 */ "ld1 $\xFF\x02\x32, [$\x01], #24\0" |
| 34403 | /* 5318 */ "ld1 $\xFF\x02\x33, [$\x01], #48\0" |
| 34404 | /* 5338 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0" |
| 34405 | /* 5358 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0" |
| 34406 | /* 5378 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0" |
| 34407 | /* 5398 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0" |
| 34408 | /* 5418 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0" |
| 34409 | /* 5438 */ "ld1 $\xFF\x02\x31, [$\x01], #32\0" |
| 34410 | /* 5458 */ "ld1 $\xFF\x02\x32, [$\x01], #16\0" |
| 34411 | /* 5478 */ "ld1 $\xFF\x02\x33, [$\x01], #32\0" |
| 34412 | /* 5498 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 34413 | /* 5522 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 34414 | /* 5546 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34415 | /* 5570 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34416 | /* 5594 */ "ld1w $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 34417 | /* 5618 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34418 | /* 5654 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34419 | /* 5690 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34420 | /* 5726 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34421 | /* 5762 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34422 | /* 5798 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34423 | /* 5834 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34424 | /* 5870 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34425 | /* 5906 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34426 | /* 5942 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 34427 | /* 5978 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #2\0" |
| 34428 | /* 6001 */ "ld1 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #4\0" |
| 34429 | /* 6024 */ "ld1 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #8\0" |
| 34430 | /* 6047 */ "ld1 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #1\0" |
| 34431 | /* 6070 */ "ld2b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34432 | /* 6094 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34433 | /* 6118 */ "ld2h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34434 | /* 6142 */ "ld2q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 34435 | /* 6166 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0" |
| 34436 | /* 6186 */ "ld2r $\xFF\x02\x2D, [$\x01], #16\0" |
| 34437 | /* 6207 */ "ld2r $\xFF\x02\x2E, [$\x01], #16\0" |
| 34438 | /* 6228 */ "ld2r $\xFF\x02\x2F, [$\x01], #8\0" |
| 34439 | /* 6248 */ "ld2r $\xFF\x02\x30, [$\x01], #4\0" |
| 34440 | /* 6268 */ "ld2r $\xFF\x02\x31, [$\x01], #8\0" |
| 34441 | /* 6288 */ "ld2r $\xFF\x02\x32, [$\x01], #2\0" |
| 34442 | /* 6308 */ "ld2r $\xFF\x02\x33, [$\x01], #4\0" |
| 34443 | /* 6328 */ "ld2 $\xFF\x02\x2C, [$\x01], #32\0" |
| 34444 | /* 6348 */ "ld2 $\xFF\x02\x2E, [$\x01], #32\0" |
| 34445 | /* 6368 */ "ld2 $\xFF\x02\x2F, [$\x01], #16\0" |
| 34446 | /* 6388 */ "ld2 $\xFF\x02\x30, [$\x01], #16\0" |
| 34447 | /* 6408 */ "ld2 $\xFF\x02\x31, [$\x01], #32\0" |
| 34448 | /* 6428 */ "ld2 $\xFF\x02\x32, [$\x01], #16\0" |
| 34449 | /* 6448 */ "ld2 $\xFF\x02\x33, [$\x01], #32\0" |
| 34450 | /* 6468 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34451 | /* 6492 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #4\0" |
| 34452 | /* 6515 */ "ld2 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #8\0" |
| 34453 | /* 6538 */ "ld2 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #16\0" |
| 34454 | /* 6562 */ "ld2 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #2\0" |
| 34455 | /* 6585 */ "ld3b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34456 | /* 6609 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34457 | /* 6633 */ "ld3h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34458 | /* 6657 */ "ld3q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 34459 | /* 6681 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0" |
| 34460 | /* 6701 */ "ld3r $\xFF\x02\x2D, [$\x01], #24\0" |
| 34461 | /* 6722 */ "ld3r $\xFF\x02\x2E, [$\x01], #24\0" |
| 34462 | /* 6743 */ "ld3r $\xFF\x02\x2F, [$\x01], #12\0" |
| 34463 | /* 6764 */ "ld3r $\xFF\x02\x30, [$\x01], #6\0" |
| 34464 | /* 6784 */ "ld3r $\xFF\x02\x31, [$\x01], #12\0" |
| 34465 | /* 6805 */ "ld3r $\xFF\x02\x32, [$\x01], #3\0" |
| 34466 | /* 6825 */ "ld3r $\xFF\x02\x33, [$\x01], #6\0" |
| 34467 | /* 6845 */ "ld3 $\xFF\x02\x2C, [$\x01], #48\0" |
| 34468 | /* 6865 */ "ld3 $\xFF\x02\x2E, [$\x01], #48\0" |
| 34469 | /* 6885 */ "ld3 $\xFF\x02\x2F, [$\x01], #24\0" |
| 34470 | /* 6905 */ "ld3 $\xFF\x02\x30, [$\x01], #24\0" |
| 34471 | /* 6925 */ "ld3 $\xFF\x02\x31, [$\x01], #48\0" |
| 34472 | /* 6945 */ "ld3 $\xFF\x02\x32, [$\x01], #24\0" |
| 34473 | /* 6965 */ "ld3 $\xFF\x02\x33, [$\x01], #48\0" |
| 34474 | /* 6985 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34475 | /* 7009 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #6\0" |
| 34476 | /* 7032 */ "ld3 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #12\0" |
| 34477 | /* 7056 */ "ld3 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #24\0" |
| 34478 | /* 7080 */ "ld3 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #3\0" |
| 34479 | /* 7103 */ "ld4b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34480 | /* 7127 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34481 | /* 7151 */ "ld4 $\xFF\x02\x2C, [$\x01], #64\0" |
| 34482 | /* 7171 */ "ld4 $\xFF\x02\x2E, [$\x01], #64\0" |
| 34483 | /* 7191 */ "ld4 $\xFF\x02\x2F, [$\x01], #32\0" |
| 34484 | /* 7211 */ "ld4 $\xFF\x02\x30, [$\x01], #32\0" |
| 34485 | /* 7231 */ "ld4 $\xFF\x02\x31, [$\x01], #64\0" |
| 34486 | /* 7251 */ "ld4 $\xFF\x02\x32, [$\x01], #32\0" |
| 34487 | /* 7271 */ "ld4 $\xFF\x02\x33, [$\x01], #64\0" |
| 34488 | /* 7291 */ "ld4h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34489 | /* 7315 */ "ld4q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 34490 | /* 7339 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0" |
| 34491 | /* 7359 */ "ld4r $\xFF\x02\x2D, [$\x01], #32\0" |
| 34492 | /* 7380 */ "ld4r $\xFF\x02\x2E, [$\x01], #32\0" |
| 34493 | /* 7401 */ "ld4r $\xFF\x02\x2F, [$\x01], #16\0" |
| 34494 | /* 7422 */ "ld4r $\xFF\x02\x30, [$\x01], #8\0" |
| 34495 | /* 7442 */ "ld4r $\xFF\x02\x31, [$\x01], #16\0" |
| 34496 | /* 7463 */ "ld4r $\xFF\x02\x32, [$\x01], #4\0" |
| 34497 | /* 7483 */ "ld4r $\xFF\x02\x33, [$\x01], #8\0" |
| 34498 | /* 7503 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34499 | /* 7527 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #8\0" |
| 34500 | /* 7550 */ "ld4 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #16\0" |
| 34501 | /* 7574 */ "ld4 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #32\0" |
| 34502 | /* 7598 */ "ld4 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #4\0" |
| 34503 | /* 7621 */ "staddb $\x02, [$\x03]\0" |
| 34504 | /* 7637 */ "staddh $\x02, [$\x03]\0" |
| 34505 | /* 7653 */ "staddlb $\x02, [$\x03]\0" |
| 34506 | /* 7670 */ "staddlh $\x02, [$\x03]\0" |
| 34507 | /* 7687 */ "staddl $\x02, [$\x03]\0" |
| 34508 | /* 7703 */ "stadd $\x02, [$\x03]\0" |
| 34509 | /* 7718 */ "ldapurb $\x01, [$\x02]\0" |
| 34510 | /* 7735 */ "ldapurh $\x01, [$\x02]\0" |
| 34511 | /* 7752 */ "ldapursb $\x01, [$\x02]\0" |
| 34512 | /* 7770 */ "ldapursh $\x01, [$\x02]\0" |
| 34513 | /* 7788 */ "ldapursw $\x01, [$\x02]\0" |
| 34514 | /* 7806 */ "ldapur $\x01, [$\x02]\0" |
| 34515 | /* 7822 */ "stclrb $\x02, [$\x03]\0" |
| 34516 | /* 7838 */ "stclrh $\x02, [$\x03]\0" |
| 34517 | /* 7854 */ "stclrlb $\x02, [$\x03]\0" |
| 34518 | /* 7871 */ "stclrlh $\x02, [$\x03]\0" |
| 34519 | /* 7888 */ "stclrl $\x02, [$\x03]\0" |
| 34520 | /* 7904 */ "stclr $\x02, [$\x03]\0" |
| 34521 | /* 7919 */ "steorb $\x02, [$\x03]\0" |
| 34522 | /* 7935 */ "steorh $\x02, [$\x03]\0" |
| 34523 | /* 7951 */ "steorlb $\x02, [$\x03]\0" |
| 34524 | /* 7968 */ "steorlh $\x02, [$\x03]\0" |
| 34525 | /* 7985 */ "steorl $\x02, [$\x03]\0" |
| 34526 | /* 8001 */ "steor $\x02, [$\x03]\0" |
| 34527 | /* 8016 */ "ldff1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34528 | /* 8042 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34529 | /* 8068 */ "ldff1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34530 | /* 8094 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34531 | /* 8120 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34532 | /* 8146 */ "ldff1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34533 | /* 8172 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34534 | /* 8198 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34535 | /* 8224 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34536 | /* 8251 */ "ldff1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34537 | /* 8278 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34538 | /* 8305 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34539 | /* 8332 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34540 | /* 8359 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34541 | /* 8386 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34542 | /* 8412 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34543 | /* 8438 */ "ldg $\x01, [$\x03]\0" |
| 34544 | /* 8451 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34545 | /* 8477 */ "ldnf1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34546 | /* 8503 */ "ldnf1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34547 | /* 8529 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34548 | /* 8555 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34549 | /* 8581 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34550 | /* 8607 */ "ldnf1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34551 | /* 8633 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34552 | /* 8659 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34553 | /* 8686 */ "ldnf1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34554 | /* 8713 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34555 | /* 8740 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34556 | /* 8767 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34557 | /* 8794 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34558 | /* 8821 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34559 | /* 8847 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34560 | /* 8873 */ "ldnp $\x01, $\x02, [$\x03]\0" |
| 34561 | /* 8891 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 34562 | /* 8917 */ "ldnt1b $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| 34563 | /* 8943 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 34564 | /* 8969 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 34565 | /* 8995 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34566 | /* 9023 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34567 | /* 9051 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 34568 | /* 9077 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 34569 | /* 9103 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 34570 | /* 9129 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34571 | /* 9157 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 34572 | /* 9183 */ "ldnt1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0" |
| 34573 | /* 9209 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 34574 | /* 9235 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 34575 | /* 9261 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34576 | /* 9289 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34577 | /* 9317 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34578 | /* 9346 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34579 | /* 9375 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34580 | /* 9404 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34581 | /* 9433 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34582 | /* 9462 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 34583 | /* 9488 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 34584 | /* 9514 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 34585 | /* 9540 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 34586 | /* 9568 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 34587 | /* 9596 */ "ldp $\x01, $\x02, [$\x03]\0" |
| 34588 | /* 9613 */ "ldpsw $\x01, $\x02, [$\x03]\0" |
| 34589 | /* 9632 */ "ldraa $\x01, [$\x02]\0" |
| 34590 | /* 9647 */ "ldrab $\x01, [$\x02]\0" |
| 34591 | /* 9662 */ "ldrb $\x01, [$\x02, $\x03]\0" |
| 34592 | /* 9680 */ "ldrb $\x01, [$\x02]\0" |
| 34593 | /* 9694 */ "ldr $\x01, [$\x02, $\x03]\0" |
| 34594 | /* 9711 */ "ldr $\x01, [$\x02]\0" |
| 34595 | /* 9724 */ "ldrh $\x01, [$\x02, $\x03]\0" |
| 34596 | /* 9742 */ "ldrh $\x01, [$\x02]\0" |
| 34597 | /* 9756 */ "ldrsb $\x01, [$\x02, $\x03]\0" |
| 34598 | /* 9775 */ "ldrsb $\x01, [$\x02]\0" |
| 34599 | /* 9790 */ "ldrsh $\x01, [$\x02, $\x03]\0" |
| 34600 | /* 9809 */ "ldrsh $\x01, [$\x02]\0" |
| 34601 | /* 9824 */ "ldrsw $\x01, [$\x02, $\x03]\0" |
| 34602 | /* 9843 */ "ldrsw $\x01, [$\x02]\0" |
| 34603 | /* 9858 */ "ldr $\xFF\x01\x07, [$\x02]\0" |
| 34604 | /* 9873 */ "ldr $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| 34605 | /* 9898 */ "stsetb $\x02, [$\x03]\0" |
| 34606 | /* 9914 */ "stseth $\x02, [$\x03]\0" |
| 34607 | /* 9930 */ "stsetlb $\x02, [$\x03]\0" |
| 34608 | /* 9947 */ "stsetlh $\x02, [$\x03]\0" |
| 34609 | /* 9964 */ "stsetl $\x02, [$\x03]\0" |
| 34610 | /* 9980 */ "stset $\x02, [$\x03]\0" |
| 34611 | /* 9995 */ "stsmaxb $\x02, [$\x03]\0" |
| 34612 | /* 10012 */ "stsmaxh $\x02, [$\x03]\0" |
| 34613 | /* 10029 */ "stsmaxlb $\x02, [$\x03]\0" |
| 34614 | /* 10047 */ "stsmaxlh $\x02, [$\x03]\0" |
| 34615 | /* 10065 */ "stsmaxl $\x02, [$\x03]\0" |
| 34616 | /* 10082 */ "stsmax $\x02, [$\x03]\0" |
| 34617 | /* 10098 */ "stsminb $\x02, [$\x03]\0" |
| 34618 | /* 10115 */ "stsminh $\x02, [$\x03]\0" |
| 34619 | /* 10132 */ "stsminlb $\x02, [$\x03]\0" |
| 34620 | /* 10150 */ "stsminlh $\x02, [$\x03]\0" |
| 34621 | /* 10168 */ "stsminl $\x02, [$\x03]\0" |
| 34622 | /* 10185 */ "stsmin $\x02, [$\x03]\0" |
| 34623 | /* 10201 */ "ldtrb $\x01, [$\x02]\0" |
| 34624 | /* 10216 */ "ldtrh $\x01, [$\x02]\0" |
| 34625 | /* 10231 */ "ldtrsb $\x01, [$\x02]\0" |
| 34626 | /* 10247 */ "ldtrsh $\x01, [$\x02]\0" |
| 34627 | /* 10263 */ "ldtrsw $\x01, [$\x02]\0" |
| 34628 | /* 10279 */ "ldtr $\x01, [$\x02]\0" |
| 34629 | /* 10293 */ "stumaxb $\x02, [$\x03]\0" |
| 34630 | /* 10310 */ "stumaxh $\x02, [$\x03]\0" |
| 34631 | /* 10327 */ "stumaxlb $\x02, [$\x03]\0" |
| 34632 | /* 10345 */ "stumaxlh $\x02, [$\x03]\0" |
| 34633 | /* 10363 */ "stumaxl $\x02, [$\x03]\0" |
| 34634 | /* 10380 */ "stumax $\x02, [$\x03]\0" |
| 34635 | /* 10396 */ "stuminb $\x02, [$\x03]\0" |
| 34636 | /* 10413 */ "stuminh $\x02, [$\x03]\0" |
| 34637 | /* 10430 */ "stuminlb $\x02, [$\x03]\0" |
| 34638 | /* 10448 */ "stuminlh $\x02, [$\x03]\0" |
| 34639 | /* 10466 */ "stuminl $\x02, [$\x03]\0" |
| 34640 | /* 10483 */ "stumin $\x02, [$\x03]\0" |
| 34641 | /* 10499 */ "ldurb $\x01, [$\x02]\0" |
| 34642 | /* 10514 */ "ldur $\x01, [$\x02]\0" |
| 34643 | /* 10528 */ "ldurh $\x01, [$\x02]\0" |
| 34644 | /* 10543 */ "ldursb $\x01, [$\x02]\0" |
| 34645 | /* 10559 */ "ldursh $\x01, [$\x02]\0" |
| 34646 | /* 10575 */ "ldursw $\x01, [$\x02]\0" |
| 34647 | /* 10591 */ "mul $\x01, $\x02, $\x03\0" |
| 34648 | /* 10606 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 34649 | /* 10631 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 34650 | /* 10656 */ "mov $\xFF\x01\x2B, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 34651 | /* 10681 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 34652 | /* 10706 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 34653 | /* 10731 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 34654 | /* 10756 */ "mov $\xFF\x01\x2B, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 34655 | /* 10781 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 34656 | /* 10806 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 34657 | /* 10831 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 34658 | /* 10856 */ "mov $\xFF\x01\x2B, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 34659 | /* 10881 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 34660 | /* 10906 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 34661 | /* 10931 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 34662 | /* 10956 */ "mov $\xFF\x01\x2B, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 34663 | /* 10981 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 34664 | /* 11006 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0" |
| 34665 | /* 11031 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0" |
| 34666 | /* 11056 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x2B\0" |
| 34667 | /* 11081 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0" |
| 34668 | /* 11106 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0" |
| 34669 | /* 11131 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0" |
| 34670 | /* 11156 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x2B\0" |
| 34671 | /* 11181 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0" |
| 34672 | /* 11206 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0" |
| 34673 | /* 11231 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0" |
| 34674 | /* 11256 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x2B\0" |
| 34675 | /* 11281 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0" |
| 34676 | /* 11306 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0" |
| 34677 | /* 11331 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0" |
| 34678 | /* 11356 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x2B\0" |
| 34679 | /* 11381 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0" |
| 34680 | /* 11406 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx2]\0" |
| 34681 | /* 11437 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx2], $\xFF\x05\x23\0" |
| 34682 | /* 11468 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx4]\0" |
| 34683 | /* 11499 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx4], $\xFF\x05\x23\0" |
| 34684 | /* 11530 */ "movt $\x01, $\xFF\x03\x07\0" |
| 34685 | /* 11544 */ "smstart\0" |
| 34686 | /* 11552 */ "smstart sm\0" |
| 34687 | /* 11563 */ "smstart za\0" |
| 34688 | /* 11574 */ "smstop\0" |
| 34689 | /* 11581 */ "smstop sm\0" |
| 34690 | /* 11591 */ "smstop za\0" |
| 34691 | /* 11601 */ "mneg $\x01, $\x02, $\x03\0" |
| 34692 | /* 11617 */ "mvn.16b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| 34693 | /* 11636 */ "mvn.8b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| 34694 | /* 11654 */ "mvn $\x01, $\x03\0" |
| 34695 | /* 11665 */ "mvn $\x01, $\x03$\xFF\x04\x02\0" |
| 34696 | /* 11680 */ "orn $\x01, $\x02, $\x03\0" |
| 34697 | /* 11695 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0" |
| 34698 | /* 11711 */ "mov $\x01, $\x03\0" |
| 34699 | /* 11722 */ "orr $\x01, $\x02, $\x03\0" |
| 34700 | /* 11737 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0" |
| 34701 | /* 11752 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 34702 | /* 11773 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 34703 | /* 11794 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 34704 | /* 11815 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0" |
| 34705 | /* 11830 */ "mov.16b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| 34706 | /* 11849 */ "mov.8b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| 34707 | /* 11867 */ "pacia1716\0" |
| 34708 | /* 11877 */ "paciasp\0" |
| 34709 | /* 11885 */ "paciaz\0" |
| 34710 | /* 11892 */ "pacib1716\0" |
| 34711 | /* 11902 */ "pacibsp\0" |
| 34712 | /* 11910 */ "pacibz\0" |
| 34713 | /* 11917 */ "pacm\0" |
| 34714 | /* 11922 */ "pmov $\xFF\x01\x06, $\xFF\x02\x07\0" |
| 34715 | /* 11938 */ "pmov $\xFF\x01\x07, $\xFF\x04\x06\0" |
| 34716 | /* 11954 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34717 | /* 11978 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 34718 | /* 12000 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34719 | /* 12024 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34720 | /* 12048 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 34721 | /* 12070 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34722 | /* 12094 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34723 | /* 12118 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 34724 | /* 12140 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34725 | /* 12164 */ "prfm $\xFF\x01\x3D, [$\x02, $\x03]\0" |
| 34726 | /* 12184 */ "prfm $\xFF\x01\x3D, [$\x02]\0" |
| 34727 | /* 12200 */ "prfum $\xFF\x01\x3D, [$\x02]\0" |
| 34728 | /* 12217 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34729 | /* 12241 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 34730 | /* 12263 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34731 | /* 12287 */ "ptrues $\xFF\x01\x06\0" |
| 34732 | /* 12299 */ "ptrues $\xFF\x01\x10\0" |
| 34733 | /* 12311 */ "ptrues $\xFF\x01\x09\0" |
| 34734 | /* 12323 */ "ptrues $\xFF\x01\x0B\0" |
| 34735 | /* 12335 */ "ptrue $\xFF\x01\x06\0" |
| 34736 | /* 12346 */ "ptrue $\xFF\x01\x10\0" |
| 34737 | /* 12357 */ "ptrue $\xFF\x01\x09\0" |
| 34738 | /* 12368 */ "ptrue $\xFF\x01\x0B\0" |
| 34739 | /* 12379 */ "ret\0" |
| 34740 | /* 12383 */ "ngcs $\x01, $\x03\0" |
| 34741 | /* 12395 */ "ngc $\x01, $\x03\0" |
| 34742 | /* 12406 */ "asr $\x01, $\x02, $\x03\0" |
| 34743 | /* 12421 */ "sxtb $\x01, $\x02\0" |
| 34744 | /* 12433 */ "sxth $\x01, $\x02\0" |
| 34745 | /* 12445 */ "sxtw $\x01, $\x02\0" |
| 34746 | /* 12457 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0" |
| 34747 | /* 12480 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0" |
| 34748 | /* 12503 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0" |
| 34749 | /* 12526 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0" |
| 34750 | /* 12549 */ "smull $\x01, $\x02, $\x03\0" |
| 34751 | /* 12566 */ "smnegl $\x01, $\x02, $\x03\0" |
| 34752 | /* 12584 */ "sqdecb $\x01\0" |
| 34753 | /* 12594 */ "sqdecb $\x01, $\xFF\x03\x0E\0" |
| 34754 | /* 12610 */ "sqdecb $\x01, $\xFF\x02\x3E\0" |
| 34755 | /* 12626 */ "sqdecb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34756 | /* 12648 */ "sqdecd $\x01\0" |
| 34757 | /* 12658 */ "sqdecd $\x01, $\xFF\x03\x0E\0" |
| 34758 | /* 12674 */ "sqdecd $\x01, $\xFF\x02\x3E\0" |
| 34759 | /* 12690 */ "sqdecd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34760 | /* 12712 */ "sqdecd $\xFF\x01\x10\0" |
| 34761 | /* 12724 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 34762 | /* 12742 */ "sqdech $\x01\0" |
| 34763 | /* 12752 */ "sqdech $\x01, $\xFF\x03\x0E\0" |
| 34764 | /* 12768 */ "sqdech $\x01, $\xFF\x02\x3E\0" |
| 34765 | /* 12784 */ "sqdech $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34766 | /* 12806 */ "sqdech $\xFF\x01\x09\0" |
| 34767 | /* 12818 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 34768 | /* 12836 */ "sqdecw $\x01\0" |
| 34769 | /* 12846 */ "sqdecw $\x01, $\xFF\x03\x0E\0" |
| 34770 | /* 12862 */ "sqdecw $\x01, $\xFF\x02\x3E\0" |
| 34771 | /* 12878 */ "sqdecw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34772 | /* 12900 */ "sqdecw $\xFF\x01\x0B\0" |
| 34773 | /* 12912 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 34774 | /* 12930 */ "sqincb $\x01\0" |
| 34775 | /* 12940 */ "sqincb $\x01, $\xFF\x03\x0E\0" |
| 34776 | /* 12956 */ "sqincb $\x01, $\xFF\x02\x3E\0" |
| 34777 | /* 12972 */ "sqincb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34778 | /* 12994 */ "sqincd $\x01\0" |
| 34779 | /* 13004 */ "sqincd $\x01, $\xFF\x03\x0E\0" |
| 34780 | /* 13020 */ "sqincd $\x01, $\xFF\x02\x3E\0" |
| 34781 | /* 13036 */ "sqincd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34782 | /* 13058 */ "sqincd $\xFF\x01\x10\0" |
| 34783 | /* 13070 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 34784 | /* 13088 */ "sqinch $\x01\0" |
| 34785 | /* 13098 */ "sqinch $\x01, $\xFF\x03\x0E\0" |
| 34786 | /* 13114 */ "sqinch $\x01, $\xFF\x02\x3E\0" |
| 34787 | /* 13130 */ "sqinch $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34788 | /* 13152 */ "sqinch $\xFF\x01\x09\0" |
| 34789 | /* 13164 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 34790 | /* 13182 */ "sqincw $\x01\0" |
| 34791 | /* 13192 */ "sqincw $\x01, $\xFF\x03\x0E\0" |
| 34792 | /* 13208 */ "sqincw $\x01, $\xFF\x02\x3E\0" |
| 34793 | /* 13224 */ "sqincw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 34794 | /* 13246 */ "sqincw $\xFF\x01\x0B\0" |
| 34795 | /* 13258 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 34796 | /* 13276 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34797 | /* 13300 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34798 | /* 13324 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34799 | /* 13348 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34800 | /* 13372 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34801 | /* 13396 */ "st1q $\xFF\x01\x25, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34802 | /* 13420 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34803 | /* 13444 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34804 | /* 13468 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 34805 | /* 13490 */ "st1b $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| 34806 | /* 13512 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 34807 | /* 13534 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34808 | /* 13556 */ "st1b $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 34809 | /* 13578 */ "st1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 34810 | /* 13600 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34811 | /* 13622 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 34812 | /* 13644 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 34813 | /* 13666 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34814 | /* 13688 */ "st1d $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 34815 | /* 13710 */ "st1 $\xFF\x02\x2C, [$\x01], #64\0" |
| 34816 | /* 13730 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0" |
| 34817 | /* 13750 */ "st1 $\xFF\x02\x2E, [$\x01], #64\0" |
| 34818 | /* 13770 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0" |
| 34819 | /* 13790 */ "st1 $\xFF\x02\x30, [$\x01], #32\0" |
| 34820 | /* 13810 */ "st1 $\xFF\x02\x31, [$\x01], #64\0" |
| 34821 | /* 13830 */ "st1 $\xFF\x02\x32, [$\x01], #32\0" |
| 34822 | /* 13850 */ "st1 $\xFF\x02\x33, [$\x01], #64\0" |
| 34823 | /* 13870 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 34824 | /* 13892 */ "st1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0" |
| 34825 | /* 13914 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 34826 | /* 13936 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34827 | /* 13958 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 34828 | /* 13980 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34829 | /* 14002 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0" |
| 34830 | /* 14022 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0" |
| 34831 | /* 14041 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0" |
| 34832 | /* 14061 */ "st1 $\xFF\x02\x2F, [$\x01], #8\0" |
| 34833 | /* 14080 */ "st1 $\xFF\x02\x30, [$\x01], #8\0" |
| 34834 | /* 14099 */ "st1 $\xFF\x02\x31, [$\x01], #16\0" |
| 34835 | /* 14119 */ "st1 $\xFF\x02\x32, [$\x01], #8\0" |
| 34836 | /* 14138 */ "st1 $\xFF\x02\x33, [$\x01], #16\0" |
| 34837 | /* 14158 */ "st1 $\xFF\x02\x2C, [$\x01], #48\0" |
| 34838 | /* 14178 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0" |
| 34839 | /* 14198 */ "st1 $\xFF\x02\x2E, [$\x01], #48\0" |
| 34840 | /* 14218 */ "st1 $\xFF\x02\x2F, [$\x01], #24\0" |
| 34841 | /* 14238 */ "st1 $\xFF\x02\x30, [$\x01], #24\0" |
| 34842 | /* 14258 */ "st1 $\xFF\x02\x31, [$\x01], #48\0" |
| 34843 | /* 14278 */ "st1 $\xFF\x02\x32, [$\x01], #24\0" |
| 34844 | /* 14298 */ "st1 $\xFF\x02\x33, [$\x01], #48\0" |
| 34845 | /* 14318 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0" |
| 34846 | /* 14338 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0" |
| 34847 | /* 14358 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0" |
| 34848 | /* 14378 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0" |
| 34849 | /* 14398 */ "st1 $\xFF\x02\x30, [$\x01], #16\0" |
| 34850 | /* 14418 */ "st1 $\xFF\x02\x31, [$\x01], #32\0" |
| 34851 | /* 14438 */ "st1 $\xFF\x02\x32, [$\x01], #16\0" |
| 34852 | /* 14458 */ "st1 $\xFF\x02\x33, [$\x01], #32\0" |
| 34853 | /* 14478 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 34854 | /* 14500 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 34855 | /* 14522 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34856 | /* 14544 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34857 | /* 14566 */ "st1w $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 34858 | /* 14588 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34859 | /* 14622 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34860 | /* 14656 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34861 | /* 14690 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34862 | /* 14724 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34863 | /* 14758 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34864 | /* 14792 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34865 | /* 14826 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34866 | /* 14860 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34867 | /* 14894 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 34868 | /* 14928 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #2\0" |
| 34869 | /* 14951 */ "st1 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #4\0" |
| 34870 | /* 14974 */ "st1 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #8\0" |
| 34871 | /* 14997 */ "st1 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #1\0" |
| 34872 | /* 15020 */ "st2b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 34873 | /* 15042 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34874 | /* 15064 */ "st2g $\x01, [$\x02]\0" |
| 34875 | /* 15078 */ "st2h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 34876 | /* 15100 */ "st2q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 34877 | /* 15122 */ "st2 $\xFF\x02\x2C, [$\x01], #32\0" |
| 34878 | /* 15142 */ "st2 $\xFF\x02\x2E, [$\x01], #32\0" |
| 34879 | /* 15162 */ "st2 $\xFF\x02\x2F, [$\x01], #16\0" |
| 34880 | /* 15182 */ "st2 $\xFF\x02\x30, [$\x01], #16\0" |
| 34881 | /* 15202 */ "st2 $\xFF\x02\x31, [$\x01], #32\0" |
| 34882 | /* 15222 */ "st2 $\xFF\x02\x32, [$\x01], #16\0" |
| 34883 | /* 15242 */ "st2 $\xFF\x02\x33, [$\x01], #32\0" |
| 34884 | /* 15262 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34885 | /* 15284 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #4\0" |
| 34886 | /* 15307 */ "st2 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #8\0" |
| 34887 | /* 15330 */ "st2 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #16\0" |
| 34888 | /* 15354 */ "st2 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #2\0" |
| 34889 | /* 15377 */ "st3b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 34890 | /* 15399 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34891 | /* 15421 */ "st3h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 34892 | /* 15443 */ "st3q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 34893 | /* 15465 */ "st3 $\xFF\x02\x2C, [$\x01], #48\0" |
| 34894 | /* 15485 */ "st3 $\xFF\x02\x2E, [$\x01], #48\0" |
| 34895 | /* 15505 */ "st3 $\xFF\x02\x2F, [$\x01], #24\0" |
| 34896 | /* 15525 */ "st3 $\xFF\x02\x30, [$\x01], #24\0" |
| 34897 | /* 15545 */ "st3 $\xFF\x02\x31, [$\x01], #48\0" |
| 34898 | /* 15565 */ "st3 $\xFF\x02\x32, [$\x01], #24\0" |
| 34899 | /* 15585 */ "st3 $\xFF\x02\x33, [$\x01], #48\0" |
| 34900 | /* 15605 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34901 | /* 15627 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #6\0" |
| 34902 | /* 15650 */ "st3 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #12\0" |
| 34903 | /* 15674 */ "st3 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #24\0" |
| 34904 | /* 15698 */ "st3 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #3\0" |
| 34905 | /* 15721 */ "st4b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 34906 | /* 15743 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34907 | /* 15765 */ "st4 $\xFF\x02\x2C, [$\x01], #64\0" |
| 34908 | /* 15785 */ "st4 $\xFF\x02\x2E, [$\x01], #64\0" |
| 34909 | /* 15805 */ "st4 $\xFF\x02\x2F, [$\x01], #32\0" |
| 34910 | /* 15825 */ "st4 $\xFF\x02\x30, [$\x01], #32\0" |
| 34911 | /* 15845 */ "st4 $\xFF\x02\x31, [$\x01], #64\0" |
| 34912 | /* 15865 */ "st4 $\xFF\x02\x32, [$\x01], #32\0" |
| 34913 | /* 15885 */ "st4 $\xFF\x02\x33, [$\x01], #64\0" |
| 34914 | /* 15905 */ "st4h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 34915 | /* 15927 */ "st4q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 34916 | /* 15949 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34917 | /* 15971 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #8\0" |
| 34918 | /* 15994 */ "st4 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #16\0" |
| 34919 | /* 16018 */ "st4 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #32\0" |
| 34920 | /* 16042 */ "st4 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #4\0" |
| 34921 | /* 16065 */ "stgp $\x01, $\x02, [$\x03]\0" |
| 34922 | /* 16083 */ "stg $\x01, [$\x02]\0" |
| 34923 | /* 16096 */ "stlurb $\x01, [$\x02]\0" |
| 34924 | /* 16112 */ "stlurh $\x01, [$\x02]\0" |
| 34925 | /* 16128 */ "stlur $\x01, [$\x02]\0" |
| 34926 | /* 16143 */ "stnp $\x01, $\x02, [$\x03]\0" |
| 34927 | /* 16161 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 34928 | /* 16185 */ "stnt1b $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| 34929 | /* 16209 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 34930 | /* 16233 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 34931 | /* 16257 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34932 | /* 16283 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34933 | /* 16309 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 34934 | /* 16333 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 34935 | /* 16357 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 34936 | /* 16381 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34937 | /* 16407 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 34938 | /* 16431 */ "stnt1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0" |
| 34939 | /* 16455 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 34940 | /* 16479 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 34941 | /* 16503 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34942 | /* 16529 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34943 | /* 16555 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 34944 | /* 16579 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 34945 | /* 16603 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 34946 | /* 16627 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 34947 | /* 16653 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 34948 | /* 16679 */ "stp $\x01, $\x02, [$\x03]\0" |
| 34949 | /* 16696 */ "strb $\x01, [$\x02, $\x03]\0" |
| 34950 | /* 16714 */ "strb $\x01, [$\x02]\0" |
| 34951 | /* 16728 */ "str $\x01, [$\x02, $\x03]\0" |
| 34952 | /* 16745 */ "str $\x01, [$\x02]\0" |
| 34953 | /* 16758 */ "strh $\x01, [$\x02, $\x03]\0" |
| 34954 | /* 16776 */ "strh $\x01, [$\x02]\0" |
| 34955 | /* 16790 */ "str $\xFF\x01\x07, [$\x02]\0" |
| 34956 | /* 16805 */ "str $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| 34957 | /* 16830 */ "sttrb $\x01, [$\x02]\0" |
| 34958 | /* 16845 */ "sttrh $\x01, [$\x02]\0" |
| 34959 | /* 16860 */ "sttr $\x01, [$\x02]\0" |
| 34960 | /* 16874 */ "sturb $\x01, [$\x02]\0" |
| 34961 | /* 16889 */ "stur $\x01, [$\x02]\0" |
| 34962 | /* 16903 */ "sturh $\x01, [$\x02]\0" |
| 34963 | /* 16918 */ "stz2g $\x01, [$\x02]\0" |
| 34964 | /* 16933 */ "stzg $\x01, [$\x02]\0" |
| 34965 | /* 16947 */ "subpt $\x01, $\x02, $\x03\0" |
| 34966 | /* 16964 */ "cmp $\x02, $\xFF\x03\x01\0" |
| 34967 | /* 16977 */ "cmp $\x02, $\x03\0" |
| 34968 | /* 16988 */ "cmp $\x02, $\x03$\xFF\x04\x02\0" |
| 34969 | /* 17003 */ "negs $\x01, $\x03\0" |
| 34970 | /* 17015 */ "negs $\x01, $\x03$\xFF\x04\x02\0" |
| 34971 | /* 17031 */ "subs $\x01, $\x02, $\x03\0" |
| 34972 | /* 17047 */ "cmp $\x02, $\x03$\xFF\x04\x03\0" |
| 34973 | /* 17062 */ "neg $\x01, $\x03\0" |
| 34974 | /* 17073 */ "neg $\x01, $\x03$\xFF\x04\x02\0" |
| 34975 | /* 17088 */ "sub $\x01, $\x02, $\x03\0" |
| 34976 | /* 17103 */ "sysp $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0" |
| 34977 | /* 17127 */ "sys $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0" |
| 34978 | /* 17150 */ "lsr $\x01, $\x02, $\x03\0" |
| 34979 | /* 17165 */ "uxtb $\x01, $\x02\0" |
| 34980 | /* 17177 */ "uxth $\x01, $\x02\0" |
| 34981 | /* 17189 */ "uxtw $\x01, $\x02\0" |
| 34982 | /* 17201 */ "umull $\x01, $\x02, $\x03\0" |
| 34983 | /* 17218 */ "mov.s $\x01, $\xFF\x02\x0C$\xFF\x03\x19\0" |
| 34984 | /* 17237 */ "mov.d $\x01, $\xFF\x02\x0C$\xFF\x03\x19\0" |
| 34985 | /* 17256 */ "umnegl $\x01, $\x02, $\x03\0" |
| 34986 | /* 17274 */ "uqdecb $\x01\0" |
| 34987 | /* 17284 */ "uqdecb $\x01, $\xFF\x03\x0E\0" |
| 34988 | /* 17300 */ "uqdecd $\x01\0" |
| 34989 | /* 17310 */ "uqdecd $\x01, $\xFF\x03\x0E\0" |
| 34990 | /* 17326 */ "uqdecd $\xFF\x01\x10\0" |
| 34991 | /* 17338 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 34992 | /* 17356 */ "uqdech $\x01\0" |
| 34993 | /* 17366 */ "uqdech $\x01, $\xFF\x03\x0E\0" |
| 34994 | /* 17382 */ "uqdech $\xFF\x01\x09\0" |
| 34995 | /* 17394 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 34996 | /* 17412 */ "uqdecw $\x01\0" |
| 34997 | /* 17422 */ "uqdecw $\x01, $\xFF\x03\x0E\0" |
| 34998 | /* 17438 */ "uqdecw $\xFF\x01\x0B\0" |
| 34999 | /* 17450 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 35000 | /* 17468 */ "uqincb $\x01\0" |
| 35001 | /* 17478 */ "uqincb $\x01, $\xFF\x03\x0E\0" |
| 35002 | /* 17494 */ "uqincd $\x01\0" |
| 35003 | /* 17504 */ "uqincd $\x01, $\xFF\x03\x0E\0" |
| 35004 | /* 17520 */ "uqincd $\xFF\x01\x10\0" |
| 35005 | /* 17532 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 35006 | /* 17550 */ "uqinch $\x01\0" |
| 35007 | /* 17560 */ "uqinch $\x01, $\xFF\x03\x0E\0" |
| 35008 | /* 17576 */ "uqinch $\xFF\x01\x09\0" |
| 35009 | /* 17588 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 35010 | /* 17606 */ "uqincw $\x01\0" |
| 35011 | /* 17616 */ "uqincw $\x01, $\xFF\x03\x0E\0" |
| 35012 | /* 17632 */ "uqincw $\xFF\x01\x0B\0" |
| 35013 | /* 17644 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 35014 | /* 17662 */ "xpaclri\0" |
| 35015 | /* 17670 */ "zero {za}\0" |
| 35016 | /* 17680 */ "zero {za0.h}\0" |
| 35017 | /* 17693 */ "zero {za1.h}\0" |
| 35018 | /* 17706 */ "zero {za0.s}\0" |
| 35019 | /* 17719 */ "zero {za1.s}\0" |
| 35020 | /* 17732 */ "zero {za2.s}\0" |
| 35021 | /* 17745 */ "zero {za3.s}\0" |
| 35022 | /* 17758 */ "zero {za0.s,za1.s}\0" |
| 35023 | /* 17777 */ "zero {za0.s,za3.s}\0" |
| 35024 | /* 17796 */ "zero {za1.s,za2.s}\0" |
| 35025 | /* 17815 */ "zero {za2.s,za3.s}\0" |
| 35026 | /* 17834 */ "zero {za0.s,za1.s,za2.s}\0" |
| 35027 | /* 17859 */ "zero {za0.s,za1.s,za3.s}\0" |
| 35028 | /* 17884 */ "zero {za0.s,za2.s,za3.s}\0" |
| 35029 | /* 17909 */ "zero {za1.s,za2.s,za3.s}\0" |
| 35030 | ; |
| 35031 | |
| 35032 | #ifndef NDEBUG |
| 35033 | static struct SortCheck { |
| 35034 | SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| 35035 | assert(std::is_sorted( |
| 35036 | OpToPatterns.begin(), OpToPatterns.end(), |
| 35037 | [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| 35038 | return L.Opcode < R.Opcode; |
| 35039 | }) && |
| 35040 | "tablegen failed to sort opcode patterns"); |
| 35041 | } |
| 35042 | } sortCheckVar(OpToPatterns); |
| 35043 | #endif |
| 35044 | |
| 35045 | AliasMatchingData M { |
| 35046 | .OpToPatterns: ArrayRef(OpToPatterns), |
| 35047 | .Patterns: ArrayRef(Patterns), |
| 35048 | .PatternConds: ArrayRef(Conds), |
| 35049 | .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)), |
| 35050 | .ValidateMCOperand: &AArch64AppleInstPrinterValidateMCOperand, |
| 35051 | }; |
| 35052 | const char *AsmString = matchAliasPatterns(MI, STI: &STI, M); |
| 35053 | if (!AsmString) return false; |
| 35054 | |
| 35055 | unsigned I = 0; |
| 35056 | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| 35057 | AsmString[I] != '$' && AsmString[I] != '\0') |
| 35058 | ++I; |
| 35059 | OS << '\t' << StringRef(AsmString, I); |
| 35060 | if (AsmString[I] != '\0') { |
| 35061 | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| 35062 | OS << '\t'; |
| 35063 | ++I; |
| 35064 | } |
| 35065 | do { |
| 35066 | if (AsmString[I] == '$') { |
| 35067 | ++I; |
| 35068 | if (AsmString[I] == (char)0xff) { |
| 35069 | ++I; |
| 35070 | int OpIdx = AsmString[I++] - 1; |
| 35071 | int PrintMethodIdx = AsmString[I++] - 1; |
| 35072 | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS); |
| 35073 | } else |
| 35074 | printOperand(MI, OpNo: unsigned(AsmString[I++]) - 1, STI, O&: OS); |
| 35075 | } else { |
| 35076 | OS << AsmString[I++]; |
| 35077 | } |
| 35078 | } while (AsmString[I] != '\0'); |
| 35079 | } |
| 35080 | |
| 35081 | return true; |
| 35082 | } |
| 35083 | |
| 35084 | void AArch64AppleInstPrinter::printCustomAliasOperand( |
| 35085 | const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| 35086 | unsigned PrintMethodIdx, |
| 35087 | const MCSubtargetInfo &STI, |
| 35088 | raw_ostream &OS) { |
| 35089 | switch (PrintMethodIdx) { |
| 35090 | default: |
| 35091 | llvm_unreachable("Unknown PrintMethod kind"); |
| 35092 | break; |
| 35093 | case 0: |
| 35094 | printAddSubImm(MI, OpNum: OpIdx, STI, O&: OS); |
| 35095 | break; |
| 35096 | case 1: |
| 35097 | printShifter(MI, OpNum: OpIdx, STI, O&: OS); |
| 35098 | break; |
| 35099 | case 2: |
| 35100 | printArithExtend(MI, OpNum: OpIdx, STI, O&: OS); |
| 35101 | break; |
| 35102 | case 3: |
| 35103 | printLogicalImm<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35104 | break; |
| 35105 | case 4: |
| 35106 | printLogicalImm<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35107 | break; |
| 35108 | case 5: |
| 35109 | printSVERegOp<'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35110 | break; |
| 35111 | case 6: |
| 35112 | printSVERegOp<>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35113 | break; |
| 35114 | case 7: |
| 35115 | printLogicalImm<int8_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35116 | break; |
| 35117 | case 8: |
| 35118 | printSVERegOp<'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35119 | break; |
| 35120 | case 9: |
| 35121 | printLogicalImm<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35122 | break; |
| 35123 | case 10: |
| 35124 | printSVERegOp<'s'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35125 | break; |
| 35126 | case 11: |
| 35127 | printVRegOperand(MI, OpNo: OpIdx, STI, O&: OS); |
| 35128 | break; |
| 35129 | case 12: |
| 35130 | printImm(MI, OpNo: OpIdx, STI, O&: OS); |
| 35131 | break; |
| 35132 | case 13: |
| 35133 | printSVEPattern(MI, OpNum: OpIdx, STI, O&: OS); |
| 35134 | break; |
| 35135 | case 14: |
| 35136 | printImm8OptLsl<int8_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35137 | break; |
| 35138 | case 15: |
| 35139 | printSVERegOp<'d'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35140 | break; |
| 35141 | case 16: |
| 35142 | printImm8OptLsl<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35143 | break; |
| 35144 | case 17: |
| 35145 | printImm8OptLsl<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35146 | break; |
| 35147 | case 18: |
| 35148 | printImm8OptLsl<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35149 | break; |
| 35150 | case 19: |
| 35151 | printInverseCondCode(MI, OpNum: OpIdx, STI, O&: OS); |
| 35152 | break; |
| 35153 | case 20: |
| 35154 | printSVELogicalImm<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35155 | break; |
| 35156 | case 21: |
| 35157 | printSVELogicalImm<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35158 | break; |
| 35159 | case 22: |
| 35160 | printSVELogicalImm<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35161 | break; |
| 35162 | case 23: |
| 35163 | printZPRasFPR<8>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35164 | break; |
| 35165 | case 24: |
| 35166 | printVectorIndex(MI, OpNum: OpIdx, STI, O&: OS); |
| 35167 | break; |
| 35168 | case 25: |
| 35169 | printZPRasFPR<64>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35170 | break; |
| 35171 | case 26: |
| 35172 | printZPRasFPR<16>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35173 | break; |
| 35174 | case 27: |
| 35175 | printSVERegOp<'q'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35176 | break; |
| 35177 | case 28: |
| 35178 | printZPRasFPR<128>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35179 | break; |
| 35180 | case 29: |
| 35181 | printZPRasFPR<32>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35182 | break; |
| 35183 | case 30: |
| 35184 | printMatrixTileVector<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35185 | break; |
| 35186 | case 31: |
| 35187 | printMatrixIndex(MI, OpNum: OpIdx, STI, O&: OS); |
| 35188 | break; |
| 35189 | case 32: |
| 35190 | printMatrixTileVector<1>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35191 | break; |
| 35192 | case 33: |
| 35193 | printFPImmOperand(MI, OpNum: OpIdx, STI, O&: OS); |
| 35194 | break; |
| 35195 | case 34: |
| 35196 | printTypedVectorList<0,'d'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35197 | break; |
| 35198 | case 35: |
| 35199 | printTypedVectorList<0,'s'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35200 | break; |
| 35201 | case 36: |
| 35202 | printTypedVectorList<0,'q'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35203 | break; |
| 35204 | case 37: |
| 35205 | printBTIHintOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 35206 | break; |
| 35207 | case 38: |
| 35208 | printPSBHintOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 35209 | break; |
| 35210 | case 39: |
| 35211 | printTypedVectorList<0,'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35212 | break; |
| 35213 | case 40: |
| 35214 | printPredicateAsCounter<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35215 | break; |
| 35216 | case 41: |
| 35217 | printTypedVectorList<0, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35218 | break; |
| 35219 | case 42: |
| 35220 | printTypedVectorList<0,'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35221 | break; |
| 35222 | case 43: |
| 35223 | printTypedVectorList<16, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35224 | break; |
| 35225 | case 44: |
| 35226 | printTypedVectorList<1, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35227 | break; |
| 35228 | case 45: |
| 35229 | printTypedVectorList<2, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35230 | break; |
| 35231 | case 46: |
| 35232 | printTypedVectorList<2, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35233 | break; |
| 35234 | case 47: |
| 35235 | printTypedVectorList<4, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35236 | break; |
| 35237 | case 48: |
| 35238 | printTypedVectorList<4, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35239 | break; |
| 35240 | case 49: |
| 35241 | printTypedVectorList<8, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35242 | break; |
| 35243 | case 50: |
| 35244 | printTypedVectorList<8, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35245 | break; |
| 35246 | case 51: |
| 35247 | printTypedVectorList<0, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35248 | break; |
| 35249 | case 52: |
| 35250 | printTypedVectorList<0, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35251 | break; |
| 35252 | case 53: |
| 35253 | printTypedVectorList<0, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35254 | break; |
| 35255 | case 54: |
| 35256 | printMatrix<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35257 | break; |
| 35258 | case 55: |
| 35259 | printImmRangeScale<2, 1>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35260 | break; |
| 35261 | case 56: |
| 35262 | printImmRangeScale<4, 3>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35263 | break; |
| 35264 | case 57: |
| 35265 | printMatrix<64>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35266 | break; |
| 35267 | case 58: |
| 35268 | printImmHex(MI, OpNo: OpIdx, STI, O&: OS); |
| 35269 | break; |
| 35270 | case 59: |
| 35271 | printPrefetchOp<true>(MI, OpNum: OpIdx, STI, O&: OS); |
| 35272 | break; |
| 35273 | case 60: |
| 35274 | printPrefetchOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 35275 | break; |
| 35276 | case 61: |
| 35277 | printGPR64as32(MI, OpNum: OpIdx, STI, O&: OS); |
| 35278 | break; |
| 35279 | case 62: |
| 35280 | printSysCROperand(MI, OpNo: OpIdx, STI, O&: OS); |
| 35281 | break; |
| 35282 | } |
| 35283 | } |
| 35284 | |
| 35285 | static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| 35286 | const MCSubtargetInfo &STI, |
| 35287 | unsigned PredicateIndex) { |
| 35288 | switch (PredicateIndex) { |
| 35289 | default: |
| 35290 | llvm_unreachable("Unknown MCOperandPredicate kind"); |
| 35291 | break; |
| 35292 | case 1: { |
| 35293 | |
| 35294 | if (!MCOp.isImm()) |
| 35295 | return false; |
| 35296 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 35297 | return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Imm: Val); |
| 35298 | |
| 35299 | } |
| 35300 | case 2: { |
| 35301 | |
| 35302 | if (!MCOp.isImm()) |
| 35303 | return false; |
| 35304 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 35305 | return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Imm: Val); |
| 35306 | |
| 35307 | } |
| 35308 | case 3: { |
| 35309 | |
| 35310 | if (!MCOp.isImm()) |
| 35311 | return false; |
| 35312 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 35313 | return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Imm: Val); |
| 35314 | |
| 35315 | } |
| 35316 | case 4: { |
| 35317 | |
| 35318 | return MCOp.isImm() && |
| 35319 | MCOp.getImm() != AArch64CC::AL && |
| 35320 | MCOp.getImm() != AArch64CC::NV; |
| 35321 | |
| 35322 | } |
| 35323 | case 5: { |
| 35324 | |
| 35325 | if (!MCOp.isImm()) |
| 35326 | return false; |
| 35327 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 35328 | return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Imm: Val) && |
| 35329 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 35330 | |
| 35331 | } |
| 35332 | case 6: { |
| 35333 | |
| 35334 | if (!MCOp.isImm()) |
| 35335 | return false; |
| 35336 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 35337 | return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Imm: Val) && |
| 35338 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 35339 | |
| 35340 | } |
| 35341 | case 7: { |
| 35342 | |
| 35343 | if (!MCOp.isImm()) |
| 35344 | return false; |
| 35345 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 35346 | return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Imm: Val) && |
| 35347 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 35348 | |
| 35349 | } |
| 35350 | case 8: { |
| 35351 | |
| 35352 | // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| 35353 | if (!MCOp.isImm()) |
| 35354 | return false; |
| 35355 | return AArch64BTIHint::lookupBTIByEncoding(Encoding: MCOp.getImm() ^ 32) != nullptr; |
| 35356 | |
| 35357 | } |
| 35358 | case 9: { |
| 35359 | |
| 35360 | // Check, if operand is valid, to fix exhaustive aliasing in disassembly. |
| 35361 | // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| 35362 | if (!MCOp.isImm()) |
| 35363 | return false; |
| 35364 | return AArch64PSBHint::lookupPSBByEncoding(Encoding: MCOp.getImm()) != nullptr; |
| 35365 | |
| 35366 | } |
| 35367 | } |
| 35368 | } |
| 35369 | |
| 35370 | #endif // PRINT_ALIAS_INSTR |
| 35371 |
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