1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace AArch64 {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 CCRegBankID = 0,
16 FPRRegBankID = 1,
17 GPRRegBankID = 2,
18 NumRegisterBanks,
19};
20} // end namespace AArch64
21} // end namespace llvm
22#endif // GET_REGBANK_DECLARATIONS
23
24#ifdef GET_TARGET_REGBANK_CLASS
25#undef GET_TARGET_REGBANK_CLASS
26private:
27 static const RegisterBank *RegBanks[];
28 static const unsigned Sizes[];
29
30protected:
31 AArch64GenRegisterBankInfo(unsigned HwMode = 0);
32
33#endif // GET_TARGET_REGBANK_CLASS
34
35#ifdef GET_TARGET_REGBANK_IMPL
36#undef GET_TARGET_REGBANK_IMPL
37namespace llvm {
38namespace AArch64 {
39const uint32_t CCRegBankCoverageData[] = {
40 // 0-31
41 (1u << (AArch64::CCRRegClassID - 0)) |
42 0,
43 // 32-63
44 0,
45 // 64-95
46 0,
47 // 96-127
48 0,
49 // 128-159
50 0,
51 // 160-191
52 0,
53 // 192-223
54 0,
55 // 224-255
56 0,
57 // 256-287
58 0,
59 // 288-319
60 0,
61};
62const uint32_t FPRRegBankCoverageData[] = {
63 // 0-31
64 (1u << (AArch64::FPR8RegClassID - 0)) |
65 (1u << (AArch64::FPR16RegClassID - 0)) |
66 (1u << (AArch64::FPR32RegClassID - 0)) |
67 (1u << (AArch64::FPR16_loRegClassID - 0)) |
68 (1u << (AArch64::FPR32_with_hsub_in_FPR16_loRegClassID - 0)) |
69 0,
70 // 32-63
71 (1u << (AArch64::FPR64RegClassID - 32)) |
72 (1u << (AArch64::DDRegClassID - 32)) |
73 (1u << (AArch64::FPR64_loRegClassID - 32)) |
74 (1u << (AArch64::DD_with_dsub0_in_FPR64_loRegClassID - 32)) |
75 (1u << (AArch64::DD_with_dsub1_in_FPR64_loRegClassID - 32)) |
76 (1u << (AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID - 32)) |
77 0,
78 // 64-95
79 (1u << (AArch64::FPR128RegClassID - 64)) |
80 (1u << (AArch64::DDDRegClassID - 64)) |
81 (1u << (AArch64::DDDDRegClassID - 64)) |
82 (1u << (AArch64::FPR128_loRegClassID - 64)) |
83 (1u << (AArch64::DDD_with_dsub0_in_FPR64_loRegClassID - 64)) |
84 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID - 64)) |
85 (1u << (AArch64::DDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
86 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
87 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
88 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
89 (1u << (AArch64::DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
90 (1u << (AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
91 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
92 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
93 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
94 (1u << (AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) |
95 (1u << (AArch64::FPR128_0to7RegClassID - 64)) |
96 (1u << (AArch64::ZPRRegClassID - 64)) |
97 (1u << (AArch64::ZPR_4bRegClassID - 64)) |
98 (1u << (AArch64::ZPR_3bRegClassID - 64)) |
99 0,
100 // 96-127
101 (1u << (AArch64::QQRegClassID - 96)) |
102 (1u << (AArch64::QQQRegClassID - 96)) |
103 (1u << (AArch64::QQ_with_dsub_in_FPR64_loRegClassID - 96)) |
104 (1u << (AArch64::QQQ_with_dsub_in_FPR64_loRegClassID - 96)) |
105 (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 96)) |
106 (1u << (AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 96)) |
107 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 96)) |
108 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
109 (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 96)) |
110 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
111 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
112 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
113 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7RegClassID - 96)) |
114 (1u << (AArch64::QQ_with_qsub1_in_FPR128_0to7RegClassID - 96)) |
115 (1u << (AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_0to7RegClassID - 96)) |
116 0,
117 // 128-159
118 (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 128)) |
119 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 128)) |
120 (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 128)) |
121 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7RegClassID - 128)) |
122 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
123 (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
124 (1u << (AArch64::QQQ_with_qsub2_in_FPR128_0to7RegClassID - 128)) |
125 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 128)) |
126 (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 128)) |
127 0,
128 // 160-191
129 (1u << (AArch64::QQQQRegClassID - 160)) |
130 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_loRegClassID - 160)) |
131 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 160)) |
132 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) |
133 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
134 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7RegClassID - 160)) |
135 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 160)) |
136 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) |
137 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
138 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 160)) |
139 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) |
140 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
141 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 160)) |
142 (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) |
143 (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 160)) |
144 0,
145 // 192-223
146 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 192)) |
147 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
148 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 192)) |
149 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
150 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 192)) |
151 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 192)) |
152 0,
153 // 224-255
154 0,
155 // 256-287
156 0,
157 // 288-319
158 0,
159};
160const uint32_t GPRRegBankCoverageData[] = {
161 // 0-31
162 (1u << (AArch64::GPR32allRegClassID - 0)) |
163 (1u << (AArch64::GPR32RegClassID - 0)) |
164 (1u << (AArch64::GPR32spRegClassID - 0)) |
165 (1u << (AArch64::GPR32commonRegClassID - 0)) |
166 (1u << (AArch64::GPR32argRegClassID - 0)) |
167 (1u << (AArch64::MatrixIndexGPR32_12_15RegClassID - 0)) |
168 (1u << (AArch64::MatrixIndexGPR32_8_11RegClassID - 0)) |
169 0,
170 // 32-63
171 (1u << (AArch64::XSeqPairsClassRegClassID - 32)) |
172 (1u << (AArch64::WSeqPairsClassRegClassID - 32)) |
173 (1u << (AArch64::GPR64allRegClassID - 32)) |
174 (1u << (AArch64::GPR64RegClassID - 32)) |
175 (1u << (AArch64::GPR64spRegClassID - 32)) |
176 (1u << (AArch64::GPR64commonRegClassID - 32)) |
177 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID - 32)) |
178 (1u << (AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID - 32)) |
179 (1u << (AArch64::GPR64noipRegClassID - 32)) |
180 (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 32)) |
181 (1u << (AArch64::tcGPR64RegClassID - 32)) |
182 (1u << (AArch64::tcGPRnotx16RegClassID - 32)) |
183 (1u << (AArch64::GPR64noip_and_tcGPR64RegClassID - 32)) |
184 (1u << (AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID - 32)) |
185 (1u << (AArch64::GPR64argRegClassID - 32)) |
186 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
187 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
188 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
189 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
190 (1u << (AArch64::FIXED_REGSRegClassID - 32)) |
191 (1u << (AArch64::FIXED_REGS_with_sub_32RegClassID - 32)) |
192 (1u << (AArch64::FIXED_REGS_and_GPR64RegClassID - 32)) |
193 (1u << (AArch64::tcGPRx16x17RegClassID - 32)) |
194 (1u << (AArch64::tcGPRx17RegClassID - 32)) |
195 0,
196 // 64-95
197 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID - 64)) |
198 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID - 64)) |
199 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID - 64)) |
200 (1u << (AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClassID - 64)) |
201 (1u << (AArch64::XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
202 (1u << (AArch64::XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
203 (1u << (AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID - 64)) |
204 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID - 64)) |
205 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID - 64)) |
206 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID - 64)) |
207 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID - 64)) |
208 0,
209 // 96-127
210 0,
211 // 128-159
212 0,
213 // 160-191
214 0,
215 // 192-223
216 0,
217 // 224-255
218 0,
219 // 256-287
220 0,
221 // 288-319
222 0,
223};
224
225constexpr RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 305);
226constexpr RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 305);
227constexpr RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 305);
228} // end namespace AArch64
229
230const RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
231 &AArch64::CCRegBank,
232 &AArch64::FPRRegBank,
233 &AArch64::GPRRegBank,
234};
235
236const unsigned AArch64GenRegisterBankInfo::Sizes[] = {
237 // Mode = 0 (Default)
238 32,
239 512,
240 128,
241};
242
243AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo(unsigned HwMode)
244 : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks, Sizes, HwMode) {
245 // Assert that RegBank indices match their ID's
246#ifndef NDEBUG
247 for (auto RB : enumerate(RegBanks))
248 assert(RB.index() == RB.value()->getID() && "Index != ID");
249#endif // NDEBUG
250}
251} // end namespace llvm
252#endif // GET_TARGET_REGBANK_IMPL
253