1#ifdef GET_AMDGPUImageDMaskIntrinsicTable_DECL
2const AMDGPUImageDMaskIntrinsic *getAMDGPUImageDMaskIntrinsic(unsigned Intr);
3#endif
4
5#ifdef GET_AMDGPUImageDMaskIntrinsicTable_IMPL
6constexpr AMDGPUImageDMaskIntrinsic AMDGPUImageDMaskIntrinsicTable[] = {
7 { .Intr: Intrinsic::amdgcn_image_getlod_1d }, // 0
8 { .Intr: Intrinsic::amdgcn_image_getlod_1darray }, // 1
9 { .Intr: Intrinsic::amdgcn_image_getlod_2d }, // 2
10 { .Intr: Intrinsic::amdgcn_image_getlod_2darray }, // 3
11 { .Intr: Intrinsic::amdgcn_image_getlod_3d }, // 4
12 { .Intr: Intrinsic::amdgcn_image_getlod_cube }, // 5
13 { .Intr: Intrinsic::amdgcn_image_getresinfo_1d }, // 6
14 { .Intr: Intrinsic::amdgcn_image_getresinfo_1darray }, // 7
15 { .Intr: Intrinsic::amdgcn_image_getresinfo_2d }, // 8
16 { .Intr: Intrinsic::amdgcn_image_getresinfo_2darray }, // 9
17 { .Intr: Intrinsic::amdgcn_image_getresinfo_2darraymsaa }, // 10
18 { .Intr: Intrinsic::amdgcn_image_getresinfo_2dmsaa }, // 11
19 { .Intr: Intrinsic::amdgcn_image_getresinfo_3d }, // 12
20 { .Intr: Intrinsic::amdgcn_image_getresinfo_cube }, // 13
21 { .Intr: Intrinsic::amdgcn_image_load_1d }, // 14
22 { .Intr: Intrinsic::amdgcn_image_load_1darray }, // 15
23 { .Intr: Intrinsic::amdgcn_image_load_2d }, // 16
24 { .Intr: Intrinsic::amdgcn_image_load_2darray }, // 17
25 { .Intr: Intrinsic::amdgcn_image_load_2darraymsaa }, // 18
26 { .Intr: Intrinsic::amdgcn_image_load_2dmsaa }, // 19
27 { .Intr: Intrinsic::amdgcn_image_load_3d }, // 20
28 { .Intr: Intrinsic::amdgcn_image_load_cube }, // 21
29 { .Intr: Intrinsic::amdgcn_image_load_mip_1d }, // 22
30 { .Intr: Intrinsic::amdgcn_image_load_mip_1darray }, // 23
31 { .Intr: Intrinsic::amdgcn_image_load_mip_2d }, // 24
32 { .Intr: Intrinsic::amdgcn_image_load_mip_2darray }, // 25
33 { .Intr: Intrinsic::amdgcn_image_load_mip_3d }, // 26
34 { .Intr: Intrinsic::amdgcn_image_load_mip_cube }, // 27
35 { .Intr: Intrinsic::amdgcn_image_sample_1d }, // 28
36 { .Intr: Intrinsic::amdgcn_image_sample_1d_nortn }, // 29
37 { .Intr: Intrinsic::amdgcn_image_sample_1darray }, // 30
38 { .Intr: Intrinsic::amdgcn_image_sample_1darray_nortn }, // 31
39 { .Intr: Intrinsic::amdgcn_image_sample_2d }, // 32
40 { .Intr: Intrinsic::amdgcn_image_sample_2d_nortn }, // 33
41 { .Intr: Intrinsic::amdgcn_image_sample_2darray }, // 34
42 { .Intr: Intrinsic::amdgcn_image_sample_2darray_nortn }, // 35
43 { .Intr: Intrinsic::amdgcn_image_sample_3d }, // 36
44 { .Intr: Intrinsic::amdgcn_image_sample_3d_nortn }, // 37
45 { .Intr: Intrinsic::amdgcn_image_sample_b_1d }, // 38
46 { .Intr: Intrinsic::amdgcn_image_sample_b_1d_nortn }, // 39
47 { .Intr: Intrinsic::amdgcn_image_sample_b_1darray }, // 40
48 { .Intr: Intrinsic::amdgcn_image_sample_b_1darray_nortn }, // 41
49 { .Intr: Intrinsic::amdgcn_image_sample_b_2d }, // 42
50 { .Intr: Intrinsic::amdgcn_image_sample_b_2d_nortn }, // 43
51 { .Intr: Intrinsic::amdgcn_image_sample_b_2darray }, // 44
52 { .Intr: Intrinsic::amdgcn_image_sample_b_2darray_nortn }, // 45
53 { .Intr: Intrinsic::amdgcn_image_sample_b_3d }, // 46
54 { .Intr: Intrinsic::amdgcn_image_sample_b_3d_nortn }, // 47
55 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_1d }, // 48
56 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_1d_nortn }, // 49
57 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_1darray }, // 50
58 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_1darray_nortn }, // 51
59 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_2d }, // 52
60 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_2d_nortn }, // 53
61 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_2darray }, // 54
62 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_2darray_nortn }, // 55
63 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_3d }, // 56
64 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_3d_nortn }, // 57
65 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_cube }, // 58
66 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_cube_nortn }, // 59
67 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_1d }, // 60
68 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_1d_nortn }, // 61
69 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_1darray }, // 62
70 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_1darray_nortn }, // 63
71 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_2d }, // 64
72 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_2d_nortn }, // 65
73 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_2darray }, // 66
74 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_2darray_nortn }, // 67
75 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_3d }, // 68
76 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_3d_nortn }, // 69
77 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_cube }, // 70
78 { .Intr: Intrinsic::amdgcn_image_sample_b_cl_o_cube_nortn }, // 71
79 { .Intr: Intrinsic::amdgcn_image_sample_b_cube }, // 72
80 { .Intr: Intrinsic::amdgcn_image_sample_b_cube_nortn }, // 73
81 { .Intr: Intrinsic::amdgcn_image_sample_b_o_1d }, // 74
82 { .Intr: Intrinsic::amdgcn_image_sample_b_o_1d_nortn }, // 75
83 { .Intr: Intrinsic::amdgcn_image_sample_b_o_1darray }, // 76
84 { .Intr: Intrinsic::amdgcn_image_sample_b_o_1darray_nortn }, // 77
85 { .Intr: Intrinsic::amdgcn_image_sample_b_o_2d }, // 78
86 { .Intr: Intrinsic::amdgcn_image_sample_b_o_2d_nortn }, // 79
87 { .Intr: Intrinsic::amdgcn_image_sample_b_o_2darray }, // 80
88 { .Intr: Intrinsic::amdgcn_image_sample_b_o_2darray_nortn }, // 81
89 { .Intr: Intrinsic::amdgcn_image_sample_b_o_3d }, // 82
90 { .Intr: Intrinsic::amdgcn_image_sample_b_o_3d_nortn }, // 83
91 { .Intr: Intrinsic::amdgcn_image_sample_b_o_cube }, // 84
92 { .Intr: Intrinsic::amdgcn_image_sample_b_o_cube_nortn }, // 85
93 { .Intr: Intrinsic::amdgcn_image_sample_c_1d }, // 86
94 { .Intr: Intrinsic::amdgcn_image_sample_c_1d_nortn }, // 87
95 { .Intr: Intrinsic::amdgcn_image_sample_c_1darray }, // 88
96 { .Intr: Intrinsic::amdgcn_image_sample_c_1darray_nortn }, // 89
97 { .Intr: Intrinsic::amdgcn_image_sample_c_2d }, // 90
98 { .Intr: Intrinsic::amdgcn_image_sample_c_2d_nortn }, // 91
99 { .Intr: Intrinsic::amdgcn_image_sample_c_2darray }, // 92
100 { .Intr: Intrinsic::amdgcn_image_sample_c_2darray_nortn }, // 93
101 { .Intr: Intrinsic::amdgcn_image_sample_c_3d }, // 94
102 { .Intr: Intrinsic::amdgcn_image_sample_c_3d_nortn }, // 95
103 { .Intr: Intrinsic::amdgcn_image_sample_c_b_1d }, // 96
104 { .Intr: Intrinsic::amdgcn_image_sample_c_b_1d_nortn }, // 97
105 { .Intr: Intrinsic::amdgcn_image_sample_c_b_1darray }, // 98
106 { .Intr: Intrinsic::amdgcn_image_sample_c_b_1darray_nortn }, // 99
107 { .Intr: Intrinsic::amdgcn_image_sample_c_b_2d }, // 100
108 { .Intr: Intrinsic::amdgcn_image_sample_c_b_2d_nortn }, // 101
109 { .Intr: Intrinsic::amdgcn_image_sample_c_b_2darray }, // 102
110 { .Intr: Intrinsic::amdgcn_image_sample_c_b_2darray_nortn }, // 103
111 { .Intr: Intrinsic::amdgcn_image_sample_c_b_3d }, // 104
112 { .Intr: Intrinsic::amdgcn_image_sample_c_b_3d_nortn }, // 105
113 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_1d }, // 106
114 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_1d_nortn }, // 107
115 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_1darray }, // 108
116 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_1darray_nortn }, // 109
117 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_2d }, // 110
118 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_2d_nortn }, // 111
119 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_2darray }, // 112
120 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_2darray_nortn }, // 113
121 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_3d }, // 114
122 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_3d_nortn }, // 115
123 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_cube }, // 116
124 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_cube_nortn }, // 117
125 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_1d }, // 118
126 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_1d_nortn }, // 119
127 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_1darray }, // 120
128 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_1darray_nortn }, // 121
129 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_2d }, // 122
130 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_2d_nortn }, // 123
131 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_2darray }, // 124
132 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_2darray_nortn }, // 125
133 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_3d }, // 126
134 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_3d_nortn }, // 127
135 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_cube }, // 128
136 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cl_o_cube_nortn }, // 129
137 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cube }, // 130
138 { .Intr: Intrinsic::amdgcn_image_sample_c_b_cube_nortn }, // 131
139 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_1d }, // 132
140 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_1d_nortn }, // 133
141 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_1darray }, // 134
142 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_1darray_nortn }, // 135
143 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_2d }, // 136
144 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_2d_nortn }, // 137
145 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_2darray }, // 138
146 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_2darray_nortn }, // 139
147 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_3d }, // 140
148 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_3d_nortn }, // 141
149 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_cube }, // 142
150 { .Intr: Intrinsic::amdgcn_image_sample_c_b_o_cube_nortn }, // 143
151 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_1d }, // 144
152 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_1d_nortn }, // 145
153 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_1darray }, // 146
154 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_1darray_nortn }, // 147
155 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_2d }, // 148
156 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_2d_nortn }, // 149
157 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_2darray }, // 150
158 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_2darray_nortn }, // 151
159 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_3d }, // 152
160 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_3d_nortn }, // 153
161 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_1d }, // 154
162 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_1d_nortn }, // 155
163 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_1darray }, // 156
164 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_1darray_nortn }, // 157
165 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_2d }, // 158
166 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_2d_nortn }, // 159
167 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_2darray }, // 160
168 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_2darray_nortn }, // 161
169 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_3d }, // 162
170 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_3d_nortn }, // 163
171 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_cube }, // 164
172 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_cube_nortn }, // 165
173 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_1d }, // 166
174 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_1d_nortn }, // 167
175 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_1darray }, // 168
176 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_1darray_nortn }, // 169
177 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_2d }, // 170
178 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_2d_nortn }, // 171
179 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_2darray }, // 172
180 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_2darray_nortn }, // 173
181 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_3d }, // 174
182 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_3d_nortn }, // 175
183 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_cube }, // 176
184 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cl_o_cube_nortn }, // 177
185 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cube }, // 178
186 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_cube_nortn }, // 179
187 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_1d }, // 180
188 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_1d_nortn }, // 181
189 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_1darray }, // 182
190 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_1darray_nortn }, // 183
191 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_2d }, // 184
192 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_2d_nortn }, // 185
193 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_2darray }, // 186
194 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_2darray_nortn }, // 187
195 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_3d }, // 188
196 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_3d_nortn }, // 189
197 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_cube }, // 190
198 { .Intr: Intrinsic::amdgcn_image_sample_c_cd_o_cube_nortn }, // 191
199 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_1d }, // 192
200 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_1d_nortn }, // 193
201 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_1darray }, // 194
202 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_1darray_nortn }, // 195
203 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_2d }, // 196
204 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_2d_nortn }, // 197
205 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_2darray }, // 198
206 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_2darray_nortn }, // 199
207 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_3d }, // 200
208 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_3d_nortn }, // 201
209 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_cube }, // 202
210 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_cube_nortn }, // 203
211 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_1d }, // 204
212 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_1d_nortn }, // 205
213 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_1darray }, // 206
214 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_1darray_nortn }, // 207
215 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_2d }, // 208
216 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_2d_nortn }, // 209
217 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_2darray }, // 210
218 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_2darray_nortn }, // 211
219 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_3d }, // 212
220 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_3d_nortn }, // 213
221 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_cube }, // 214
222 { .Intr: Intrinsic::amdgcn_image_sample_c_cl_o_cube_nortn }, // 215
223 { .Intr: Intrinsic::amdgcn_image_sample_c_cube }, // 216
224 { .Intr: Intrinsic::amdgcn_image_sample_c_cube_nortn }, // 217
225 { .Intr: Intrinsic::amdgcn_image_sample_c_d_1d }, // 218
226 { .Intr: Intrinsic::amdgcn_image_sample_c_d_1d_nortn }, // 219
227 { .Intr: Intrinsic::amdgcn_image_sample_c_d_1darray }, // 220
228 { .Intr: Intrinsic::amdgcn_image_sample_c_d_1darray_nortn }, // 221
229 { .Intr: Intrinsic::amdgcn_image_sample_c_d_2d }, // 222
230 { .Intr: Intrinsic::amdgcn_image_sample_c_d_2d_nortn }, // 223
231 { .Intr: Intrinsic::amdgcn_image_sample_c_d_2darray }, // 224
232 { .Intr: Intrinsic::amdgcn_image_sample_c_d_2darray_nortn }, // 225
233 { .Intr: Intrinsic::amdgcn_image_sample_c_d_3d }, // 226
234 { .Intr: Intrinsic::amdgcn_image_sample_c_d_3d_nortn }, // 227
235 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_1d }, // 228
236 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_1d_nortn }, // 229
237 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_1darray }, // 230
238 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_1darray_nortn }, // 231
239 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_2d }, // 232
240 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_2d_nortn }, // 233
241 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_2darray }, // 234
242 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_2darray_nortn }, // 235
243 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_3d }, // 236
244 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_3d_nortn }, // 237
245 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_cube }, // 238
246 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_cube_nortn }, // 239
247 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_1d }, // 240
248 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_1d_nortn }, // 241
249 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_1darray }, // 242
250 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_1darray_nortn }, // 243
251 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_2d }, // 244
252 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_2d_nortn }, // 245
253 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_2darray }, // 246
254 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_2darray_nortn }, // 247
255 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_3d }, // 248
256 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_3d_nortn }, // 249
257 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_cube }, // 250
258 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cl_o_cube_nortn }, // 251
259 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cube }, // 252
260 { .Intr: Intrinsic::amdgcn_image_sample_c_d_cube_nortn }, // 253
261 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_1d }, // 254
262 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_1d_nortn }, // 255
263 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_1darray }, // 256
264 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_1darray_nortn }, // 257
265 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_2d }, // 258
266 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_2d_nortn }, // 259
267 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_2darray }, // 260
268 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_2darray_nortn }, // 261
269 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_3d }, // 262
270 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_3d_nortn }, // 263
271 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_cube }, // 264
272 { .Intr: Intrinsic::amdgcn_image_sample_c_d_o_cube_nortn }, // 265
273 { .Intr: Intrinsic::amdgcn_image_sample_c_l_1d }, // 266
274 { .Intr: Intrinsic::amdgcn_image_sample_c_l_1d_nortn }, // 267
275 { .Intr: Intrinsic::amdgcn_image_sample_c_l_1darray }, // 268
276 { .Intr: Intrinsic::amdgcn_image_sample_c_l_1darray_nortn }, // 269
277 { .Intr: Intrinsic::amdgcn_image_sample_c_l_2d }, // 270
278 { .Intr: Intrinsic::amdgcn_image_sample_c_l_2d_nortn }, // 271
279 { .Intr: Intrinsic::amdgcn_image_sample_c_l_2darray }, // 272
280 { .Intr: Intrinsic::amdgcn_image_sample_c_l_2darray_nortn }, // 273
281 { .Intr: Intrinsic::amdgcn_image_sample_c_l_3d }, // 274
282 { .Intr: Intrinsic::amdgcn_image_sample_c_l_3d_nortn }, // 275
283 { .Intr: Intrinsic::amdgcn_image_sample_c_l_cube }, // 276
284 { .Intr: Intrinsic::amdgcn_image_sample_c_l_cube_nortn }, // 277
285 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_1d }, // 278
286 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_1d_nortn }, // 279
287 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_1darray }, // 280
288 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_1darray_nortn }, // 281
289 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_2d }, // 282
290 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_2d_nortn }, // 283
291 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_2darray }, // 284
292 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_2darray_nortn }, // 285
293 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_3d }, // 286
294 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_3d_nortn }, // 287
295 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_cube }, // 288
296 { .Intr: Intrinsic::amdgcn_image_sample_c_l_o_cube_nortn }, // 289
297 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_1d }, // 290
298 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_1d_nortn }, // 291
299 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_1darray }, // 292
300 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_1darray_nortn }, // 293
301 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_2d }, // 294
302 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_2d_nortn }, // 295
303 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_2darray }, // 296
304 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_2darray_nortn }, // 297
305 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_3d }, // 298
306 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_3d_nortn }, // 299
307 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_cube }, // 300
308 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_cube_nortn }, // 301
309 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_1d }, // 302
310 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_1d_nortn }, // 303
311 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_1darray }, // 304
312 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_1darray_nortn }, // 305
313 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_2d }, // 306
314 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_2d_nortn }, // 307
315 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_2darray }, // 308
316 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_2darray_nortn }, // 309
317 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_3d }, // 310
318 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_3d_nortn }, // 311
319 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_cube }, // 312
320 { .Intr: Intrinsic::amdgcn_image_sample_c_lz_o_cube_nortn }, // 313
321 { .Intr: Intrinsic::amdgcn_image_sample_c_o_1d }, // 314
322 { .Intr: Intrinsic::amdgcn_image_sample_c_o_1d_nortn }, // 315
323 { .Intr: Intrinsic::amdgcn_image_sample_c_o_1darray }, // 316
324 { .Intr: Intrinsic::amdgcn_image_sample_c_o_1darray_nortn }, // 317
325 { .Intr: Intrinsic::amdgcn_image_sample_c_o_2d }, // 318
326 { .Intr: Intrinsic::amdgcn_image_sample_c_o_2d_nortn }, // 319
327 { .Intr: Intrinsic::amdgcn_image_sample_c_o_2darray }, // 320
328 { .Intr: Intrinsic::amdgcn_image_sample_c_o_2darray_nortn }, // 321
329 { .Intr: Intrinsic::amdgcn_image_sample_c_o_3d }, // 322
330 { .Intr: Intrinsic::amdgcn_image_sample_c_o_3d_nortn }, // 323
331 { .Intr: Intrinsic::amdgcn_image_sample_c_o_cube }, // 324
332 { .Intr: Intrinsic::amdgcn_image_sample_c_o_cube_nortn }, // 325
333 { .Intr: Intrinsic::amdgcn_image_sample_cd_1d }, // 326
334 { .Intr: Intrinsic::amdgcn_image_sample_cd_1d_nortn }, // 327
335 { .Intr: Intrinsic::amdgcn_image_sample_cd_1darray }, // 328
336 { .Intr: Intrinsic::amdgcn_image_sample_cd_1darray_nortn }, // 329
337 { .Intr: Intrinsic::amdgcn_image_sample_cd_2d }, // 330
338 { .Intr: Intrinsic::amdgcn_image_sample_cd_2d_nortn }, // 331
339 { .Intr: Intrinsic::amdgcn_image_sample_cd_2darray }, // 332
340 { .Intr: Intrinsic::amdgcn_image_sample_cd_2darray_nortn }, // 333
341 { .Intr: Intrinsic::amdgcn_image_sample_cd_3d }, // 334
342 { .Intr: Intrinsic::amdgcn_image_sample_cd_3d_nortn }, // 335
343 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_1d }, // 336
344 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_1d_nortn }, // 337
345 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_1darray }, // 338
346 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_1darray_nortn }, // 339
347 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_2d }, // 340
348 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_2d_nortn }, // 341
349 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_2darray }, // 342
350 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_2darray_nortn }, // 343
351 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_3d }, // 344
352 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_3d_nortn }, // 345
353 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_cube }, // 346
354 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_cube_nortn }, // 347
355 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_1d }, // 348
356 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_1d_nortn }, // 349
357 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_1darray }, // 350
358 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_1darray_nortn }, // 351
359 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_2d }, // 352
360 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_2d_nortn }, // 353
361 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_2darray }, // 354
362 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_2darray_nortn }, // 355
363 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_3d }, // 356
364 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_3d_nortn }, // 357
365 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_cube }, // 358
366 { .Intr: Intrinsic::amdgcn_image_sample_cd_cl_o_cube_nortn }, // 359
367 { .Intr: Intrinsic::amdgcn_image_sample_cd_cube }, // 360
368 { .Intr: Intrinsic::amdgcn_image_sample_cd_cube_nortn }, // 361
369 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_1d }, // 362
370 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_1d_nortn }, // 363
371 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_1darray }, // 364
372 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_1darray_nortn }, // 365
373 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_2d }, // 366
374 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_2d_nortn }, // 367
375 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_2darray }, // 368
376 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_2darray_nortn }, // 369
377 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_3d }, // 370
378 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_3d_nortn }, // 371
379 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_cube }, // 372
380 { .Intr: Intrinsic::amdgcn_image_sample_cd_o_cube_nortn }, // 373
381 { .Intr: Intrinsic::amdgcn_image_sample_cl_1d }, // 374
382 { .Intr: Intrinsic::amdgcn_image_sample_cl_1d_nortn }, // 375
383 { .Intr: Intrinsic::amdgcn_image_sample_cl_1darray }, // 376
384 { .Intr: Intrinsic::amdgcn_image_sample_cl_1darray_nortn }, // 377
385 { .Intr: Intrinsic::amdgcn_image_sample_cl_2d }, // 378
386 { .Intr: Intrinsic::amdgcn_image_sample_cl_2d_nortn }, // 379
387 { .Intr: Intrinsic::amdgcn_image_sample_cl_2darray }, // 380
388 { .Intr: Intrinsic::amdgcn_image_sample_cl_2darray_nortn }, // 381
389 { .Intr: Intrinsic::amdgcn_image_sample_cl_3d }, // 382
390 { .Intr: Intrinsic::amdgcn_image_sample_cl_3d_nortn }, // 383
391 { .Intr: Intrinsic::amdgcn_image_sample_cl_cube }, // 384
392 { .Intr: Intrinsic::amdgcn_image_sample_cl_cube_nortn }, // 385
393 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_1d }, // 386
394 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_1d_nortn }, // 387
395 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_1darray }, // 388
396 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_1darray_nortn }, // 389
397 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_2d }, // 390
398 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_2d_nortn }, // 391
399 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_2darray }, // 392
400 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_2darray_nortn }, // 393
401 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_3d }, // 394
402 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_3d_nortn }, // 395
403 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_cube }, // 396
404 { .Intr: Intrinsic::amdgcn_image_sample_cl_o_cube_nortn }, // 397
405 { .Intr: Intrinsic::amdgcn_image_sample_cube }, // 398
406 { .Intr: Intrinsic::amdgcn_image_sample_cube_nortn }, // 399
407 { .Intr: Intrinsic::amdgcn_image_sample_d_1d }, // 400
408 { .Intr: Intrinsic::amdgcn_image_sample_d_1d_nortn }, // 401
409 { .Intr: Intrinsic::amdgcn_image_sample_d_1darray }, // 402
410 { .Intr: Intrinsic::amdgcn_image_sample_d_1darray_nortn }, // 403
411 { .Intr: Intrinsic::amdgcn_image_sample_d_2d }, // 404
412 { .Intr: Intrinsic::amdgcn_image_sample_d_2d_nortn }, // 405
413 { .Intr: Intrinsic::amdgcn_image_sample_d_2darray }, // 406
414 { .Intr: Intrinsic::amdgcn_image_sample_d_2darray_nortn }, // 407
415 { .Intr: Intrinsic::amdgcn_image_sample_d_3d }, // 408
416 { .Intr: Intrinsic::amdgcn_image_sample_d_3d_nortn }, // 409
417 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_1d }, // 410
418 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_1d_nortn }, // 411
419 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_1darray }, // 412
420 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_1darray_nortn }, // 413
421 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_2d }, // 414
422 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_2d_nortn }, // 415
423 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_2darray }, // 416
424 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_2darray_nortn }, // 417
425 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_3d }, // 418
426 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_3d_nortn }, // 419
427 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_cube }, // 420
428 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_cube_nortn }, // 421
429 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_1d }, // 422
430 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_1d_nortn }, // 423
431 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_1darray }, // 424
432 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_1darray_nortn }, // 425
433 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_2d }, // 426
434 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_2d_nortn }, // 427
435 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_2darray }, // 428
436 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_2darray_nortn }, // 429
437 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_3d }, // 430
438 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_3d_nortn }, // 431
439 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_cube }, // 432
440 { .Intr: Intrinsic::amdgcn_image_sample_d_cl_o_cube_nortn }, // 433
441 { .Intr: Intrinsic::amdgcn_image_sample_d_cube }, // 434
442 { .Intr: Intrinsic::amdgcn_image_sample_d_cube_nortn }, // 435
443 { .Intr: Intrinsic::amdgcn_image_sample_d_o_1d }, // 436
444 { .Intr: Intrinsic::amdgcn_image_sample_d_o_1d_nortn }, // 437
445 { .Intr: Intrinsic::amdgcn_image_sample_d_o_1darray }, // 438
446 { .Intr: Intrinsic::amdgcn_image_sample_d_o_1darray_nortn }, // 439
447 { .Intr: Intrinsic::amdgcn_image_sample_d_o_2d }, // 440
448 { .Intr: Intrinsic::amdgcn_image_sample_d_o_2d_nortn }, // 441
449 { .Intr: Intrinsic::amdgcn_image_sample_d_o_2darray }, // 442
450 { .Intr: Intrinsic::amdgcn_image_sample_d_o_2darray_nortn }, // 443
451 { .Intr: Intrinsic::amdgcn_image_sample_d_o_3d }, // 444
452 { .Intr: Intrinsic::amdgcn_image_sample_d_o_3d_nortn }, // 445
453 { .Intr: Intrinsic::amdgcn_image_sample_d_o_cube }, // 446
454 { .Intr: Intrinsic::amdgcn_image_sample_d_o_cube_nortn }, // 447
455 { .Intr: Intrinsic::amdgcn_image_sample_l_1d }, // 448
456 { .Intr: Intrinsic::amdgcn_image_sample_l_1d_nortn }, // 449
457 { .Intr: Intrinsic::amdgcn_image_sample_l_1darray }, // 450
458 { .Intr: Intrinsic::amdgcn_image_sample_l_1darray_nortn }, // 451
459 { .Intr: Intrinsic::amdgcn_image_sample_l_2d }, // 452
460 { .Intr: Intrinsic::amdgcn_image_sample_l_2d_nortn }, // 453
461 { .Intr: Intrinsic::amdgcn_image_sample_l_2darray }, // 454
462 { .Intr: Intrinsic::amdgcn_image_sample_l_2darray_nortn }, // 455
463 { .Intr: Intrinsic::amdgcn_image_sample_l_3d }, // 456
464 { .Intr: Intrinsic::amdgcn_image_sample_l_3d_nortn }, // 457
465 { .Intr: Intrinsic::amdgcn_image_sample_l_cube }, // 458
466 { .Intr: Intrinsic::amdgcn_image_sample_l_cube_nortn }, // 459
467 { .Intr: Intrinsic::amdgcn_image_sample_l_o_1d }, // 460
468 { .Intr: Intrinsic::amdgcn_image_sample_l_o_1d_nortn }, // 461
469 { .Intr: Intrinsic::amdgcn_image_sample_l_o_1darray }, // 462
470 { .Intr: Intrinsic::amdgcn_image_sample_l_o_1darray_nortn }, // 463
471 { .Intr: Intrinsic::amdgcn_image_sample_l_o_2d }, // 464
472 { .Intr: Intrinsic::amdgcn_image_sample_l_o_2d_nortn }, // 465
473 { .Intr: Intrinsic::amdgcn_image_sample_l_o_2darray }, // 466
474 { .Intr: Intrinsic::amdgcn_image_sample_l_o_2darray_nortn }, // 467
475 { .Intr: Intrinsic::amdgcn_image_sample_l_o_3d }, // 468
476 { .Intr: Intrinsic::amdgcn_image_sample_l_o_3d_nortn }, // 469
477 { .Intr: Intrinsic::amdgcn_image_sample_l_o_cube }, // 470
478 { .Intr: Intrinsic::amdgcn_image_sample_l_o_cube_nortn }, // 471
479 { .Intr: Intrinsic::amdgcn_image_sample_lz_1d }, // 472
480 { .Intr: Intrinsic::amdgcn_image_sample_lz_1d_nortn }, // 473
481 { .Intr: Intrinsic::amdgcn_image_sample_lz_1darray }, // 474
482 { .Intr: Intrinsic::amdgcn_image_sample_lz_1darray_nortn }, // 475
483 { .Intr: Intrinsic::amdgcn_image_sample_lz_2d }, // 476
484 { .Intr: Intrinsic::amdgcn_image_sample_lz_2d_nortn }, // 477
485 { .Intr: Intrinsic::amdgcn_image_sample_lz_2darray }, // 478
486 { .Intr: Intrinsic::amdgcn_image_sample_lz_2darray_nortn }, // 479
487 { .Intr: Intrinsic::amdgcn_image_sample_lz_3d }, // 480
488 { .Intr: Intrinsic::amdgcn_image_sample_lz_3d_nortn }, // 481
489 { .Intr: Intrinsic::amdgcn_image_sample_lz_cube }, // 482
490 { .Intr: Intrinsic::amdgcn_image_sample_lz_cube_nortn }, // 483
491 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_1d }, // 484
492 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_1d_nortn }, // 485
493 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_1darray }, // 486
494 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_1darray_nortn }, // 487
495 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_2d }, // 488
496 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_2d_nortn }, // 489
497 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_2darray }, // 490
498 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_2darray_nortn }, // 491
499 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_3d }, // 492
500 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_3d_nortn }, // 493
501 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_cube }, // 494
502 { .Intr: Intrinsic::amdgcn_image_sample_lz_o_cube_nortn }, // 495
503 { .Intr: Intrinsic::amdgcn_image_sample_o_1d }, // 496
504 { .Intr: Intrinsic::amdgcn_image_sample_o_1d_nortn }, // 497
505 { .Intr: Intrinsic::amdgcn_image_sample_o_1darray }, // 498
506 { .Intr: Intrinsic::amdgcn_image_sample_o_1darray_nortn }, // 499
507 { .Intr: Intrinsic::amdgcn_image_sample_o_2d }, // 500
508 { .Intr: Intrinsic::amdgcn_image_sample_o_2d_nortn }, // 501
509 { .Intr: Intrinsic::amdgcn_image_sample_o_2darray }, // 502
510 { .Intr: Intrinsic::amdgcn_image_sample_o_2darray_nortn }, // 503
511 { .Intr: Intrinsic::amdgcn_image_sample_o_3d }, // 504
512 { .Intr: Intrinsic::amdgcn_image_sample_o_3d_nortn }, // 505
513 { .Intr: Intrinsic::amdgcn_image_sample_o_cube }, // 506
514 { .Intr: Intrinsic::amdgcn_image_sample_o_cube_nortn }, // 507
515 { .Intr: Intrinsic::amdgcn_image_store_1d }, // 508
516 { .Intr: Intrinsic::amdgcn_image_store_1darray }, // 509
517 { .Intr: Intrinsic::amdgcn_image_store_2d }, // 510
518 { .Intr: Intrinsic::amdgcn_image_store_2darray }, // 511
519 { .Intr: Intrinsic::amdgcn_image_store_2darraymsaa }, // 512
520 { .Intr: Intrinsic::amdgcn_image_store_2dmsaa }, // 513
521 { .Intr: Intrinsic::amdgcn_image_store_3d }, // 514
522 { .Intr: Intrinsic::amdgcn_image_store_cube }, // 515
523 { .Intr: Intrinsic::amdgcn_image_store_mip_1d }, // 516
524 { .Intr: Intrinsic::amdgcn_image_store_mip_1darray }, // 517
525 { .Intr: Intrinsic::amdgcn_image_store_mip_2d }, // 518
526 { .Intr: Intrinsic::amdgcn_image_store_mip_2darray }, // 519
527 { .Intr: Intrinsic::amdgcn_image_store_mip_3d }, // 520
528 { .Intr: Intrinsic::amdgcn_image_store_mip_cube }, // 521
529 };
530
531const AMDGPUImageDMaskIntrinsic *getAMDGPUImageDMaskIntrinsic(unsigned Intr) {
532 if ((Intr < Intrinsic::amdgcn_image_getlod_1d) ||
533 (Intr > Intrinsic::amdgcn_image_store_mip_cube))
534 return nullptr;
535
536 struct KeyType {
537 unsigned Intr;
538 };
539 KeyType Key = {.Intr: Intr};
540 struct Comp {
541 bool operator()(const AMDGPUImageDMaskIntrinsic &LHS, const KeyType &RHS) const {
542 if (LHS.Intr < RHS.Intr)
543 return true;
544 if (LHS.Intr > RHS.Intr)
545 return false;
546 return false;
547 }
548 };
549 auto Table = ArrayRef(AMDGPUImageDMaskIntrinsicTable);
550 auto Idx = std::lower_bound(first: Table.begin(), last: Table.end(), val: Key, comp: Comp());
551 if (Idx == Table.end() ||
552 Key.Intr != Idx->Intr)
553 return nullptr;
554
555 return &*Idx;
556}
557#endif
558
559#undef GET_AMDGPUImageDMaskIntrinsicTable_DECL
560#undef GET_AMDGPUImageDMaskIntrinsicTable_IMPL
561