1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace R600 {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 BRANCH = 295,
311 BRANCH_COND_f32 = 296,
312 BRANCH_COND_i32 = 297,
313 BREAK = 298,
314 BREAKC_f32 = 299,
315 BREAKC_i32 = 300,
316 BREAK_LOGICALNZ_f32 = 301,
317 BREAK_LOGICALNZ_i32 = 302,
318 BREAK_LOGICALZ_f32 = 303,
319 BREAK_LOGICALZ_i32 = 304,
320 CONST_COPY = 305,
321 CONTINUE = 306,
322 CONTINUEC_f32 = 307,
323 CONTINUEC_i32 = 308,
324 CONTINUE_LOGICALNZ_f32 = 309,
325 CONTINUE_LOGICALNZ_i32 = 310,
326 CONTINUE_LOGICALZ_f32 = 311,
327 CONTINUE_LOGICALZ_i32 = 312,
328 CUBE_eg_pseudo = 313,
329 CUBE_r600_pseudo = 314,
330 DEFAULT = 315,
331 DOT_4 = 316,
332 DUMMY_CHAIN = 317,
333 ELSE = 318,
334 END = 319,
335 ENDFUNC = 320,
336 ENDIF = 321,
337 ENDLOOP = 322,
338 ENDMAIN = 323,
339 ENDSWITCH = 324,
340 FABS_R600 = 325,
341 FNEG_R600 = 326,
342 FUNC = 327,
343 IFC_f32 = 328,
344 IFC_i32 = 329,
345 IF_LOGICALNZ_f32 = 330,
346 IF_LOGICALNZ_i32 = 331,
347 IF_LOGICALZ_f32 = 332,
348 IF_LOGICALZ_i32 = 333,
349 IF_PREDICATE_SET = 334,
350 JUMP = 335,
351 JUMP_COND = 336,
352 MASK_WRITE = 337,
353 MOV_IMM_F32 = 338,
354 MOV_IMM_GLOBAL_ADDR = 339,
355 MOV_IMM_I32 = 340,
356 PRED_X = 341,
357 R600_EXTRACT_ELT_V2 = 342,
358 R600_EXTRACT_ELT_V4 = 343,
359 R600_INSERT_ELT_V2 = 344,
360 R600_INSERT_ELT_V4 = 345,
361 R600_RegisterLoad = 346,
362 R600_RegisterStore = 347,
363 RETDYN = 348,
364 RETURN = 349,
365 TXD = 350,
366 TXD_SHADOW = 351,
367 WHILELOOP = 352,
368 ADD = 353,
369 ADDC_UINT = 354,
370 ADD_INT = 355,
371 ALU_CLAUSE = 356,
372 AND_INT = 357,
373 ASHR_eg = 358,
374 ASHR_r600 = 359,
375 BCNT_INT = 360,
376 BFE_INT_eg = 361,
377 BFE_UINT_eg = 362,
378 BFI_INT_eg = 363,
379 BFM_INT_eg = 364,
380 BIT_ALIGN_INT_eg = 365,
381 CEIL = 366,
382 CF_ALU = 367,
383 CF_ALU_BREAK = 368,
384 CF_ALU_CONTINUE = 369,
385 CF_ALU_ELSE_AFTER = 370,
386 CF_ALU_POP_AFTER = 371,
387 CF_ALU_PUSH_BEFORE = 372,
388 CF_CALL_FS_EG = 373,
389 CF_CALL_FS_R600 = 374,
390 CF_CONTINUE_EG = 375,
391 CF_CONTINUE_R600 = 376,
392 CF_ELSE_EG = 377,
393 CF_ELSE_R600 = 378,
394 CF_END_CM = 379,
395 CF_END_EG = 380,
396 CF_END_R600 = 381,
397 CF_JUMP_EG = 382,
398 CF_JUMP_R600 = 383,
399 CF_PUSH_EG = 384,
400 CF_PUSH_ELSE_R600 = 385,
401 CF_TC_EG = 386,
402 CF_TC_R600 = 387,
403 CF_VC_EG = 388,
404 CF_VC_R600 = 389,
405 CNDE_INT = 390,
406 CNDE_eg = 391,
407 CNDE_r600 = 392,
408 CNDGE_INT = 393,
409 CNDGE_eg = 394,
410 CNDGE_r600 = 395,
411 CNDGT_INT = 396,
412 CNDGT_eg = 397,
413 CNDGT_r600 = 398,
414 COS_cm = 399,
415 COS_eg = 400,
416 COS_r600 = 401,
417 COS_r700 = 402,
418 CUBE_eg_real = 403,
419 CUBE_r600_real = 404,
420 DOT4_eg = 405,
421 DOT4_r600 = 406,
422 EG_ExportBuf = 407,
423 EG_ExportSwz = 408,
424 END_LOOP_EG = 409,
425 END_LOOP_R600 = 410,
426 EXP_IEEE_cm = 411,
427 EXP_IEEE_eg = 412,
428 EXP_IEEE_r600 = 413,
429 FETCH_CLAUSE = 414,
430 FFBH_UINT = 415,
431 FFBL_INT = 416,
432 FLOOR = 417,
433 FLT16_TO_FLT32 = 418,
434 FLT32_TO_FLT16 = 419,
435 FLT_TO_INT_eg = 420,
436 FLT_TO_INT_r600 = 421,
437 FLT_TO_UINT_eg = 422,
438 FLT_TO_UINT_r600 = 423,
439 FMA_eg = 424,
440 FRACT = 425,
441 GROUP_BARRIER = 426,
442 INTERP_LOAD_P0 = 427,
443 INTERP_PAIR_XY = 428,
444 INTERP_PAIR_ZW = 429,
445 INTERP_VEC_LOAD = 430,
446 INTERP_XY = 431,
447 INTERP_ZW = 432,
448 INT_TO_FLT_eg = 433,
449 INT_TO_FLT_r600 = 434,
450 KILLGT = 435,
451 LDS_ADD = 436,
452 LDS_ADD_RET = 437,
453 LDS_AND = 438,
454 LDS_AND_RET = 439,
455 LDS_BYTE_READ_RET = 440,
456 LDS_BYTE_WRITE = 441,
457 LDS_CMPST = 442,
458 LDS_CMPST_RET = 443,
459 LDS_MAX_INT = 444,
460 LDS_MAX_INT_RET = 445,
461 LDS_MAX_UINT = 446,
462 LDS_MAX_UINT_RET = 447,
463 LDS_MIN_INT = 448,
464 LDS_MIN_INT_RET = 449,
465 LDS_MIN_UINT = 450,
466 LDS_MIN_UINT_RET = 451,
467 LDS_OR = 452,
468 LDS_OR_RET = 453,
469 LDS_READ_RET = 454,
470 LDS_SHORT_READ_RET = 455,
471 LDS_SHORT_WRITE = 456,
472 LDS_SUB = 457,
473 LDS_SUB_RET = 458,
474 LDS_UBYTE_READ_RET = 459,
475 LDS_USHORT_READ_RET = 460,
476 LDS_WRITE = 461,
477 LDS_WRXCHG = 462,
478 LDS_WRXCHG_RET = 463,
479 LDS_XOR = 464,
480 LDS_XOR_RET = 465,
481 LITERALS = 466,
482 LOG_CLAMPED_eg = 467,
483 LOG_CLAMPED_r600 = 468,
484 LOG_IEEE_cm = 469,
485 LOG_IEEE_eg = 470,
486 LOG_IEEE_r600 = 471,
487 LOOP_BREAK_EG = 472,
488 LOOP_BREAK_R600 = 473,
489 LSHL_eg = 474,
490 LSHL_r600 = 475,
491 LSHR_eg = 476,
492 LSHR_r600 = 477,
493 MAX = 478,
494 MAX_DX10 = 479,
495 MAX_INT = 480,
496 MAX_UINT = 481,
497 MIN = 482,
498 MIN_DX10 = 483,
499 MIN_INT = 484,
500 MIN_UINT = 485,
501 MOV = 486,
502 MOVA_INT_eg = 487,
503 MUL = 488,
504 MULADD_IEEE_eg = 489,
505 MULADD_IEEE_r600 = 490,
506 MULADD_INT24_cm = 491,
507 MULADD_UINT24_eg = 492,
508 MULADD_eg = 493,
509 MULADD_r600 = 494,
510 MULHI_INT_cm = 495,
511 MULHI_INT_cm24 = 496,
512 MULHI_INT_eg = 497,
513 MULHI_INT_r600 = 498,
514 MULHI_UINT24_eg = 499,
515 MULHI_UINT_cm = 500,
516 MULHI_UINT_cm24 = 501,
517 MULHI_UINT_eg = 502,
518 MULHI_UINT_r600 = 503,
519 MULLO_INT_cm = 504,
520 MULLO_INT_eg = 505,
521 MULLO_INT_r600 = 506,
522 MULLO_UINT_cm = 507,
523 MULLO_UINT_eg = 508,
524 MULLO_UINT_r600 = 509,
525 MUL_IEEE = 510,
526 MUL_INT24_cm = 511,
527 MUL_LIT_eg = 512,
528 MUL_LIT_r600 = 513,
529 MUL_UINT24_eg = 514,
530 NOT_INT = 515,
531 OR_INT = 516,
532 PAD = 517,
533 POP_EG = 518,
534 POP_R600 = 519,
535 PRED_SETE = 520,
536 PRED_SETE_INT = 521,
537 PRED_SETGE = 522,
538 PRED_SETGE_INT = 523,
539 PRED_SETGT = 524,
540 PRED_SETGT_INT = 525,
541 PRED_SETNE = 526,
542 PRED_SETNE_INT = 527,
543 R600_ExportBuf = 528,
544 R600_ExportSwz = 529,
545 RAT_ATOMIC_ADD_NORET = 530,
546 RAT_ATOMIC_ADD_RTN = 531,
547 RAT_ATOMIC_AND_NORET = 532,
548 RAT_ATOMIC_AND_RTN = 533,
549 RAT_ATOMIC_CMPXCHG_INT_NORET = 534,
550 RAT_ATOMIC_CMPXCHG_INT_RTN = 535,
551 RAT_ATOMIC_DEC_UINT_NORET = 536,
552 RAT_ATOMIC_DEC_UINT_RTN = 537,
553 RAT_ATOMIC_INC_UINT_NORET = 538,
554 RAT_ATOMIC_INC_UINT_RTN = 539,
555 RAT_ATOMIC_MAX_INT_NORET = 540,
556 RAT_ATOMIC_MAX_INT_RTN = 541,
557 RAT_ATOMIC_MAX_UINT_NORET = 542,
558 RAT_ATOMIC_MAX_UINT_RTN = 543,
559 RAT_ATOMIC_MIN_INT_NORET = 544,
560 RAT_ATOMIC_MIN_INT_RTN = 545,
561 RAT_ATOMIC_MIN_UINT_NORET = 546,
562 RAT_ATOMIC_MIN_UINT_RTN = 547,
563 RAT_ATOMIC_OR_NORET = 548,
564 RAT_ATOMIC_OR_RTN = 549,
565 RAT_ATOMIC_RSUB_NORET = 550,
566 RAT_ATOMIC_RSUB_RTN = 551,
567 RAT_ATOMIC_SUB_NORET = 552,
568 RAT_ATOMIC_SUB_RTN = 553,
569 RAT_ATOMIC_XCHG_INT_NORET = 554,
570 RAT_ATOMIC_XCHG_INT_RTN = 555,
571 RAT_ATOMIC_XOR_NORET = 556,
572 RAT_ATOMIC_XOR_RTN = 557,
573 RAT_MSKOR = 558,
574 RAT_STORE_DWORD128 = 559,
575 RAT_STORE_DWORD32 = 560,
576 RAT_STORE_DWORD64 = 561,
577 RAT_STORE_TYPED_cm = 562,
578 RAT_STORE_TYPED_eg = 563,
579 RAT_WRITE_CACHELESS_128_eg = 564,
580 RAT_WRITE_CACHELESS_32_eg = 565,
581 RAT_WRITE_CACHELESS_64_eg = 566,
582 RECIPSQRT_CLAMPED_cm = 567,
583 RECIPSQRT_CLAMPED_eg = 568,
584 RECIPSQRT_CLAMPED_r600 = 569,
585 RECIPSQRT_IEEE_cm = 570,
586 RECIPSQRT_IEEE_eg = 571,
587 RECIPSQRT_IEEE_r600 = 572,
588 RECIP_CLAMPED_cm = 573,
589 RECIP_CLAMPED_eg = 574,
590 RECIP_CLAMPED_r600 = 575,
591 RECIP_IEEE_cm = 576,
592 RECIP_IEEE_eg = 577,
593 RECIP_IEEE_r600 = 578,
594 RECIP_UINT_eg = 579,
595 RECIP_UINT_r600 = 580,
596 RNDNE = 581,
597 SETE = 582,
598 SETE_DX10 = 583,
599 SETE_INT = 584,
600 SETGE_DX10 = 585,
601 SETGE_INT = 586,
602 SETGE_UINT = 587,
603 SETGT_DX10 = 588,
604 SETGT_INT = 589,
605 SETGT_UINT = 590,
606 SETNE_DX10 = 591,
607 SETNE_INT = 592,
608 SGE = 593,
609 SGT = 594,
610 SIN_cm = 595,
611 SIN_eg = 596,
612 SIN_r600 = 597,
613 SIN_r700 = 598,
614 SNE = 599,
615 SUBB_UINT = 600,
616 SUB_INT = 601,
617 TEX_GET_GRADIENTS_H = 602,
618 TEX_GET_GRADIENTS_V = 603,
619 TEX_GET_TEXTURE_RESINFO = 604,
620 TEX_LD = 605,
621 TEX_LDPTR = 606,
622 TEX_SAMPLE = 607,
623 TEX_SAMPLE_C = 608,
624 TEX_SAMPLE_C_G = 609,
625 TEX_SAMPLE_C_L = 610,
626 TEX_SAMPLE_C_LB = 611,
627 TEX_SAMPLE_G = 612,
628 TEX_SAMPLE_L = 613,
629 TEX_SAMPLE_LB = 614,
630 TEX_SET_GRADIENTS_H = 615,
631 TEX_SET_GRADIENTS_V = 616,
632 TEX_VTX_CONSTBUF = 617,
633 TEX_VTX_TEXBUF = 618,
634 TRUNC = 619,
635 UINT_TO_FLT_eg = 620,
636 UINT_TO_FLT_r600 = 621,
637 VTX_READ_128_cm = 622,
638 VTX_READ_128_eg = 623,
639 VTX_READ_16_cm = 624,
640 VTX_READ_16_eg = 625,
641 VTX_READ_32_cm = 626,
642 VTX_READ_32_eg = 627,
643 VTX_READ_64_cm = 628,
644 VTX_READ_64_eg = 629,
645 VTX_READ_8_cm = 630,
646 VTX_READ_8_eg = 631,
647 WHILE_LOOP_EG = 632,
648 WHILE_LOOP_R600 = 633,
649 XOR_INT = 634,
650 INSTRUCTION_LIST_END = 635
651 };
652
653} // end namespace R600
654} // end namespace llvm
655#endif // GET_INSTRINFO_ENUM
656
657#ifdef GET_INSTRINFO_SCHED_ENUM
658#undef GET_INSTRINFO_SCHED_ENUM
659namespace llvm {
660
661namespace R600 {
662namespace Sched {
663 enum {
664 NoInstrModel = 0,
665 NullALU = 1,
666 VecALU = 2,
667 AnyALU = 3,
668 TransALU = 4,
669 XALU = 5,
670 SCHED_LIST_END = 6
671 };
672} // end namespace Sched
673} // end namespace R600
674} // end namespace llvm
675#endif // GET_INSTRINFO_SCHED_ENUM
676
677#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
678namespace llvm {
679
680struct R600InstrTable {
681 MCInstrDesc Insts[635];
682 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
683 MCOperandInfo OperandInfo[462];
684 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
685 MCPhysReg ImplicitOps[1];
686};
687
688} // end namespace llvm
689#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
690
691#ifdef GET_INSTRINFO_MC_DESC
692#undef GET_INSTRINFO_MC_DESC
693namespace llvm {
694
695static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
696static constexpr unsigned R600ImpOpBase = sizeof R600InstrTable::OperandInfo / (sizeof(MCPhysReg));
697
698extern const R600InstrTable R600Descs = {
699 {
700 { 634, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #634 = XOR_INT
701 { 633, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = WHILE_LOOP_R600
702 { 632, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #632 = WHILE_LOOP_EG
703 { 631, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #631 = VTX_READ_8_eg
704 { 630, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #630 = VTX_READ_8_cm
705 { 629, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 458, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #629 = VTX_READ_64_eg
706 { 628, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 458, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #628 = VTX_READ_64_cm
707 { 627, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 454, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #627 = VTX_READ_32_eg
708 { 626, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 454, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #626 = VTX_READ_32_cm
709 { 625, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #625 = VTX_READ_16_eg
710 { 624, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #624 = VTX_READ_16_cm
711 { 623, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #623 = VTX_READ_128_eg
712 { 622, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #622 = VTX_READ_128_cm
713 { 621, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #621 = UINT_TO_FLT_r600
714 { 620, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #620 = UINT_TO_FLT_eg
715 { 619, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #619 = TRUNC
716 { 618, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // Inst #618 = TEX_VTX_TEXBUF
717 { 617, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0, 0x1000ULL }, // Inst #617 = TEX_VTX_CONSTBUF
718 { 616, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #616 = TEX_SET_GRADIENTS_V
719 { 615, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #615 = TEX_SET_GRADIENTS_H
720 { 614, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #614 = TEX_SAMPLE_LB
721 { 613, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #613 = TEX_SAMPLE_L
722 { 612, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #612 = TEX_SAMPLE_G
723 { 611, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #611 = TEX_SAMPLE_C_LB
724 { 610, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #610 = TEX_SAMPLE_C_L
725 { 609, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #609 = TEX_SAMPLE_C_G
726 { 608, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #608 = TEX_SAMPLE_C
727 { 607, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #607 = TEX_SAMPLE
728 { 606, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #606 = TEX_LDPTR
729 { 605, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #605 = TEX_LD
730 { 604, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #604 = TEX_GET_TEXTURE_RESINFO
731 { 603, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #603 = TEX_GET_GRADIENTS_V
732 { 602, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #602 = TEX_GET_GRADIENTS_H
733 { 601, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #601 = SUB_INT
734 { 600, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #600 = SUBB_UINT
735 { 599, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #599 = SNE
736 { 598, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #598 = SIN_r700
737 { 597, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #597 = SIN_r600
738 { 596, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #596 = SIN_eg
739 { 595, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // Inst #595 = SIN_cm
740 { 594, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #594 = SGT
741 { 593, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #593 = SGE
742 { 592, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #592 = SETNE_INT
743 { 591, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #591 = SETNE_DX10
744 { 590, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #590 = SETGT_UINT
745 { 589, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #589 = SETGT_INT
746 { 588, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #588 = SETGT_DX10
747 { 587, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #587 = SETGE_UINT
748 { 586, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #586 = SETGE_INT
749 { 585, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #585 = SETGE_DX10
750 { 584, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #584 = SETE_INT
751 { 583, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #583 = SETE_DX10
752 { 582, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #582 = SETE
753 { 581, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #581 = RNDNE
754 { 580, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #580 = RECIP_UINT_r600
755 { 579, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #579 = RECIP_UINT_eg
756 { 578, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #578 = RECIP_IEEE_r600
757 { 577, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #577 = RECIP_IEEE_eg
758 { 576, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #576 = RECIP_IEEE_cm
759 { 575, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #575 = RECIP_CLAMPED_r600
760 { 574, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #574 = RECIP_CLAMPED_eg
761 { 573, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #573 = RECIP_CLAMPED_cm
762 { 572, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #572 = RECIPSQRT_IEEE_r600
763 { 571, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #571 = RECIPSQRT_IEEE_eg
764 { 570, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #570 = RECIPSQRT_IEEE_cm
765 { 569, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #569 = RECIPSQRT_CLAMPED_r600
766 { 568, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #568 = RECIPSQRT_CLAMPED_eg
767 { 567, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #567 = RECIPSQRT_CLAMPED_cm
768 { 566, 3, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 424, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #566 = RAT_WRITE_CACHELESS_64_eg
769 { 565, 3, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 421, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #565 = RAT_WRITE_CACHELESS_32_eg
770 { 564, 3, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 418, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #564 = RAT_WRITE_CACHELESS_128_eg
771 { 563, 4, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 414, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #563 = RAT_STORE_TYPED_eg
772 { 562, 4, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 414, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #562 = RAT_STORE_TYPED_cm
773 { 561, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 412, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #561 = RAT_STORE_DWORD64
774 { 560, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 410, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #560 = RAT_STORE_DWORD32
775 { 559, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 408, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #559 = RAT_STORE_DWORD128
776 { 558, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 408, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #558 = RAT_MSKOR
777 { 557, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #557 = RAT_ATOMIC_XOR_RTN
778 { 556, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #556 = RAT_ATOMIC_XOR_NORET
779 { 555, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #555 = RAT_ATOMIC_XCHG_INT_RTN
780 { 554, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #554 = RAT_ATOMIC_XCHG_INT_NORET
781 { 553, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #553 = RAT_ATOMIC_SUB_RTN
782 { 552, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #552 = RAT_ATOMIC_SUB_NORET
783 { 551, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #551 = RAT_ATOMIC_RSUB_RTN
784 { 550, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #550 = RAT_ATOMIC_RSUB_NORET
785 { 549, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #549 = RAT_ATOMIC_OR_RTN
786 { 548, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #548 = RAT_ATOMIC_OR_NORET
787 { 547, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #547 = RAT_ATOMIC_MIN_UINT_RTN
788 { 546, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #546 = RAT_ATOMIC_MIN_UINT_NORET
789 { 545, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #545 = RAT_ATOMIC_MIN_INT_RTN
790 { 544, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #544 = RAT_ATOMIC_MIN_INT_NORET
791 { 543, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #543 = RAT_ATOMIC_MAX_UINT_RTN
792 { 542, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #542 = RAT_ATOMIC_MAX_UINT_NORET
793 { 541, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #541 = RAT_ATOMIC_MAX_INT_RTN
794 { 540, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #540 = RAT_ATOMIC_MAX_INT_NORET
795 { 539, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #539 = RAT_ATOMIC_INC_UINT_RTN
796 { 538, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #538 = RAT_ATOMIC_INC_UINT_NORET
797 { 537, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #537 = RAT_ATOMIC_DEC_UINT_RTN
798 { 536, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #536 = RAT_ATOMIC_DEC_UINT_NORET
799 { 535, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #535 = RAT_ATOMIC_CMPXCHG_INT_RTN
800 { 534, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #534 = RAT_ATOMIC_CMPXCHG_INT_NORET
801 { 533, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #533 = RAT_ATOMIC_AND_RTN
802 { 532, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #532 = RAT_ATOMIC_AND_NORET
803 { 531, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #531 = RAT_ATOMIC_ADD_RTN
804 { 530, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #530 = RAT_ATOMIC_ADD_NORET
805 { 529, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 333, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #529 = R600_ExportSwz
806 { 528, 7, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 326, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #528 = R600_ExportBuf
807 { 527, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #527 = PRED_SETNE_INT
808 { 526, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #526 = PRED_SETNE
809 { 525, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #525 = PRED_SETGT_INT
810 { 524, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #524 = PRED_SETGT
811 { 523, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #523 = PRED_SETGE_INT
812 { 522, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #522 = PRED_SETGE
813 { 521, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #521 = PRED_SETE_INT
814 { 520, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #520 = PRED_SETE
815 { 519, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = POP_R600
816 { 518, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = POP_EG
817 { 517, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = PAD
818 { 516, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #516 = OR_INT
819 { 515, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #515 = NOT_INT
820 { 514, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #514 = MUL_UINT24_eg
821 { 513, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #513 = MUL_LIT_r600
822 { 512, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #512 = MUL_LIT_eg
823 { 511, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #511 = MUL_INT24_cm
824 { 510, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #510 = MUL_IEEE
825 { 509, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #509 = MULLO_UINT_r600
826 { 508, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #508 = MULLO_UINT_eg
827 { 507, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #507 = MULLO_UINT_cm
828 { 506, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #506 = MULLO_INT_r600
829 { 505, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #505 = MULLO_INT_eg
830 { 504, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #504 = MULLO_INT_cm
831 { 503, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #503 = MULHI_UINT_r600
832 { 502, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #502 = MULHI_UINT_eg
833 { 501, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #501 = MULHI_UINT_cm24
834 { 500, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #500 = MULHI_UINT_cm
835 { 499, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #499 = MULHI_UINT24_eg
836 { 498, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #498 = MULHI_INT_r600
837 { 497, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #497 = MULHI_INT_eg
838 { 496, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #496 = MULHI_INT_cm24
839 { 495, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #495 = MULHI_INT_cm
840 { 494, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #494 = MULADD_r600
841 { 493, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #493 = MULADD_eg
842 { 492, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #492 = MULADD_UINT24_eg
843 { 491, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #491 = MULADD_INT24_cm
844 { 490, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #490 = MULADD_IEEE_r600
845 { 489, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #489 = MULADD_IEEE_eg
846 { 488, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #488 = MUL
847 { 487, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // Inst #487 = MOVA_INT_eg
848 { 486, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #486 = MOV
849 { 485, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #485 = MIN_UINT
850 { 484, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #484 = MIN_INT
851 { 483, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #483 = MIN_DX10
852 { 482, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #482 = MIN
853 { 481, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #481 = MAX_UINT
854 { 480, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #480 = MAX_INT
855 { 479, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #479 = MAX_DX10
856 { 478, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #478 = MAX
857 { 477, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #477 = LSHR_r600
858 { 476, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #476 = LSHR_eg
859 { 475, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #475 = LSHL_r600
860 { 474, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #474 = LSHL_eg
861 { 473, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = LOOP_BREAK_R600
862 { 472, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #472 = LOOP_BREAK_EG
863 { 471, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #471 = LOG_IEEE_r600
864 { 470, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #470 = LOG_IEEE_eg
865 { 469, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #469 = LOG_IEEE_cm
866 { 468, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #468 = LOG_CLAMPED_r600
867 { 467, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #467 = LOG_CLAMPED_eg
868 { 466, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = LITERALS
869 { 465, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #465 = LDS_XOR_RET
870 { 464, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #464 = LDS_XOR
871 { 463, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #463 = LDS_WRXCHG_RET
872 { 462, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #462 = LDS_WRXCHG
873 { 461, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #461 = LDS_WRITE
874 { 460, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #460 = LDS_USHORT_READ_RET
875 { 459, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #459 = LDS_UBYTE_READ_RET
876 { 458, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #458 = LDS_SUB_RET
877 { 457, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #457 = LDS_SUB
878 { 456, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #456 = LDS_SHORT_WRITE
879 { 455, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #455 = LDS_SHORT_READ_RET
880 { 454, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #454 = LDS_READ_RET
881 { 453, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #453 = LDS_OR_RET
882 { 452, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #452 = LDS_OR
883 { 451, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #451 = LDS_MIN_UINT_RET
884 { 450, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #450 = LDS_MIN_UINT
885 { 449, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #449 = LDS_MIN_INT_RET
886 { 448, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #448 = LDS_MIN_INT
887 { 447, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #447 = LDS_MAX_UINT_RET
888 { 446, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #446 = LDS_MAX_UINT
889 { 445, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #445 = LDS_MAX_INT_RET
890 { 444, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #444 = LDS_MAX_INT
891 { 443, 13, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 392, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // Inst #443 = LDS_CMPST_RET
892 { 442, 12, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // Inst #442 = LDS_CMPST
893 { 441, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #441 = LDS_BYTE_WRITE
894 { 440, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #440 = LDS_BYTE_READ_RET
895 { 439, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #439 = LDS_AND_RET
896 { 438, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #438 = LDS_AND
897 { 437, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #437 = LDS_ADD_RET
898 { 436, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #436 = LDS_ADD
899 { 435, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // Inst #435 = KILLGT
900 { 434, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #434 = INT_TO_FLT_r600
901 { 433, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #433 = INT_TO_FLT_eg
902 { 432, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #432 = INTERP_ZW
903 { 431, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #431 = INTERP_XY
904 { 430, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 352, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #430 = INTERP_VEC_LOAD
905 { 429, 5, 2, 0, 1, 0, 0, R600ImpOpBase + 0, 347, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #429 = INTERP_PAIR_ZW
906 { 428, 5, 2, 0, 1, 0, 0, R600ImpOpBase + 0, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #428 = INTERP_PAIR_XY
907 { 427, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #427 = INTERP_LOAD_P0
908 { 426, 0, 0, 0, 3, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // Inst #426 = GROUP_BARRIER
909 { 425, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #425 = FRACT
910 { 424, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #424 = FMA_eg
911 { 423, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #423 = FLT_TO_UINT_r600
912 { 422, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #422 = FLT_TO_UINT_eg
913 { 421, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #421 = FLT_TO_INT_r600
914 { 420, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #420 = FLT_TO_INT_eg
915 { 419, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #419 = FLT32_TO_FLT16
916 { 418, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #418 = FLT16_TO_FLT32
917 { 417, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #417 = FLOOR
918 { 416, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #416 = FFBL_INT
919 { 415, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #415 = FFBH_UINT
920 { 414, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #414 = FETCH_CLAUSE
921 { 413, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #413 = EXP_IEEE_r600
922 { 412, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #412 = EXP_IEEE_eg
923 { 411, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #411 = EXP_IEEE_cm
924 { 410, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #410 = END_LOOP_R600
925 { 409, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #409 = END_LOOP_EG
926 { 408, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 333, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #408 = EG_ExportSwz
927 { 407, 7, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 326, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #407 = EG_ExportBuf
928 { 406, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #406 = DOT4_r600
929 { 405, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #405 = DOT4_eg
930 { 404, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #404 = CUBE_r600_real
931 { 403, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #403 = CUBE_eg_real
932 { 402, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #402 = COS_r700
933 { 401, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #401 = COS_r600
934 { 400, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #400 = COS_eg
935 { 399, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // Inst #399 = COS_cm
936 { 398, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #398 = CNDGT_r600
937 { 397, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #397 = CNDGT_eg
938 { 396, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #396 = CNDGT_INT
939 { 395, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #395 = CNDGE_r600
940 { 394, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #394 = CNDGE_eg
941 { 393, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #393 = CNDGE_INT
942 { 392, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #392 = CNDE_r600
943 { 391, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #391 = CNDE_eg
944 { 390, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #390 = CNDE_INT
945 { 389, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = CF_VC_R600
946 { 388, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #388 = CF_VC_EG
947 { 387, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = CF_TC_R600
948 { 386, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = CF_TC_EG
949 { 385, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = CF_PUSH_ELSE_R600
950 { 384, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #384 = CF_PUSH_EG
951 { 383, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #383 = CF_JUMP_R600
952 { 382, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #382 = CF_JUMP_EG
953 { 381, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #381 = CF_END_R600
954 { 380, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = CF_END_EG
955 { 379, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = CF_END_CM
956 { 378, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = CF_ELSE_R600
957 { 377, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #377 = CF_ELSE_EG
958 { 376, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = CF_CONTINUE_R600
959 { 375, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #375 = CF_CONTINUE_EG
960 { 374, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = CF_CALL_FS_R600
961 { 373, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = CF_CALL_FS_EG
962 { 372, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = CF_ALU_PUSH_BEFORE
963 { 371, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = CF_ALU_POP_AFTER
964 { 370, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = CF_ALU_ELSE_AFTER
965 { 369, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = CF_ALU_CONTINUE
966 { 368, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = CF_ALU_BREAK
967 { 367, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #367 = CF_ALU
968 { 366, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #366 = CEIL
969 { 365, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #365 = BIT_ALIGN_INT_eg
970 { 364, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #364 = BFM_INT_eg
971 { 363, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #363 = BFI_INT_eg
972 { 362, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #362 = BFE_UINT_eg
973 { 361, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #361 = BFE_INT_eg
974 { 360, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #360 = BCNT_INT
975 { 359, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #359 = ASHR_r600
976 { 358, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #358 = ASHR_eg
977 { 357, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #357 = AND_INT
978 { 356, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #356 = ALU_CLAUSE
979 { 355, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #355 = ADD_INT
980 { 354, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #354 = ADDC_UINT
981 { 353, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #353 = ADD
982 { 352, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #352 = WHILELOOP
983 { 351, 7, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // Inst #351 = TXD_SHADOW
984 { 350, 7, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // Inst #350 = TXD
985 { 349, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #349 = RETURN
986 { 348, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #348 = RETDYN
987 { 347, 4, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // Inst #347 = R600_RegisterStore
988 { 346, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // Inst #346 = R600_RegisterLoad
989 { 345, 4, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 248, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #345 = R600_INSERT_ELT_V4
990 { 344, 4, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 244, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #344 = R600_INSERT_ELT_V2
991 { 343, 3, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #343 = R600_EXTRACT_ELT_V4
992 { 342, 3, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #342 = R600_EXTRACT_ELT_V2
993 { 341, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 234, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #341 = PRED_X
994 { 340, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #340 = MOV_IMM_I32
995 { 339, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #339 = MOV_IMM_GLOBAL_ADDR
996 { 338, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #338 = MOV_IMM_F32
997 { 337, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #337 = MASK_WRITE
998 { 336, 2, 0, 0, 3, 0, 0, R600ImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #336 = JUMP_COND
999 { 335, 1, 0, 0, 3, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #335 = JUMP
1000 { 334, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #334 = IF_PREDICATE_SET
1001 { 333, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #333 = IF_LOGICALZ_i32
1002 { 332, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #332 = IF_LOGICALZ_f32
1003 { 331, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #331 = IF_LOGICALNZ_i32
1004 { 330, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #330 = IF_LOGICALNZ_f32
1005 { 329, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #329 = IFC_i32
1006 { 328, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #328 = IFC_f32
1007 { 327, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #327 = FUNC
1008 { 326, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #326 = FNEG_R600
1009 { 325, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #325 = FABS_R600
1010 { 324, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #324 = ENDSWITCH
1011 { 323, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #323 = ENDMAIN
1012 { 322, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #322 = ENDLOOP
1013 { 321, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #321 = ENDIF
1014 { 320, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #320 = ENDFUNC
1015 { 319, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #319 = END
1016 { 318, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #318 = ELSE
1017 { 317, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #317 = DUMMY_CHAIN
1018 { 316, 71, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #316 = DOT_4
1019 { 315, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #315 = DEFAULT
1020 { 314, 2, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #314 = CUBE_r600_pseudo
1021 { 313, 2, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #313 = CUBE_eg_pseudo
1022 { 312, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #312 = CONTINUE_LOGICALZ_i32
1023 { 311, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #311 = CONTINUE_LOGICALZ_f32
1024 { 310, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #310 = CONTINUE_LOGICALNZ_i32
1025 { 309, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #309 = CONTINUE_LOGICALNZ_f32
1026 { 308, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #308 = CONTINUEC_i32
1027 { 307, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #307 = CONTINUEC_f32
1028 { 306, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #306 = CONTINUE
1029 { 305, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #305 = CONST_COPY
1030 { 304, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #304 = BREAK_LOGICALZ_i32
1031 { 303, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #303 = BREAK_LOGICALZ_f32
1032 { 302, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #302 = BREAK_LOGICALNZ_i32
1033 { 301, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #301 = BREAK_LOGICALNZ_f32
1034 { 300, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #300 = BREAKC_i32
1035 { 299, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #299 = BREAKC_f32
1036 { 298, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #298 = BREAK
1037 { 297, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #297 = BRANCH_COND_i32
1038 { 296, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #296 = BRANCH_COND_f32
1039 { 295, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #295 = BRANCH
1040 { 294, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_UBFX
1041 { 293, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_SBFX
1042 { 292, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
1043 { 291, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
1044 { 290, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
1045 { 289, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
1046 { 288, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
1047 { 287, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
1048 { 286, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
1049 { 285, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
1050 { 284, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
1051 { 283, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
1052 { 282, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
1053 { 281, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
1054 { 280, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
1055 { 279, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
1056 { 278, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
1057 { 277, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
1058 { 276, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
1059 { 275, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_UBSANTRAP
1060 { 274, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
1061 { 273, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_TRAP
1062 { 272, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_BZERO
1063 { 271, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMSET
1064 { 270, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMMOVE
1065 { 269, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
1066 { 268, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #268 = G_MEMCPY
1067 { 267, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
1068 { 266, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
1069 { 265, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
1070 { 264, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
1071 { 263, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FMA
1072 { 262, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FREM
1073 { 261, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
1074 { 260, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
1075 { 259, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
1076 { 258, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STRICT_FADD
1077 { 257, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKRESTORE
1078 { 256, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_STACKSAVE
1079 { 255, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
1080 { 254, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
1081 { 253, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
1082 { 252, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
1083 { 251, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FNEARBYINT
1084 { 250, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FRINT
1085 { 249, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FFLOOR
1086 { 248, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FSQRT
1087 { 247, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTANH
1088 { 246, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSINH
1089 { 245, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOSH
1090 { 244, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FATAN
1091 { 243, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FASIN
1092 { 242, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FACOS
1093 { 241, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FTAN
1094 { 240, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FSIN
1095 { 239, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCOS
1096 { 238, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_FCEIL
1097 { 237, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BITREVERSE
1098 { 236, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_BSWAP
1099 { 235, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTPOP
1100 { 234, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
1101 { 233, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTLZ
1102 { 232, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
1103 { 231, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_CTTZ
1104 { 230, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
1105 { 229, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
1106 { 228, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
1107 { 227, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
1108 { 226, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
1109 { 225, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
1110 { 224, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
1111 { 223, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_VSCALE
1112 { 222, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BRJT
1113 { 221, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #221 = G_BR
1114 { 220, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LLROUND
1115 { 219, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_LROUND
1116 { 218, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_ABS
1117 { 217, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMAX
1118 { 216, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_UMIN
1119 { 215, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMAX
1120 { 214, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_SMIN
1121 { 213, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTRMASK
1122 { 212, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #212 = G_PTR_ADD
1123 { 211, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
1124 { 210, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_SET_FPMODE
1125 { 209, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_GET_FPMODE
1126 { 208, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_RESET_FPENV
1127 { 207, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_SET_FPENV
1128 { 206, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #206 = G_GET_FPENV
1129 { 205, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMAXIMUM
1130 { 204, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMINIMUM
1131 { 203, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
1132 { 202, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
1133 { 201, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMAXNUM
1134 { 200, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #200 = G_FMINNUM
1135 { 199, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
1136 { 198, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
1137 { 197, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
1138 { 196, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FABS
1139 { 195, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_UITOFP
1140 { 194, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_SITOFP
1141 { 193, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOUI
1142 { 192, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTOSI
1143 { 191, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPTRUNC
1144 { 190, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FPEXT
1145 { 189, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FNEG
1146 { 188, 3, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FFREXP
1147 { 187, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLDEXP
1148 { 186, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG10
1149 { 185, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG2
1150 { 184, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FLOG
1151 { 183, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP10
1152 { 182, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP2
1153 { 181, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FEXP
1154 { 180, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOWI
1155 { 179, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FPOW
1156 { 178, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FREM
1157 { 177, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FDIV
1158 { 176, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMAD
1159 { 175, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FMA
1160 { 174, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_FMUL
1161 { 173, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FSUB
1162 { 172, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_FADD
1163 { 171, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
1164 { 170, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
1165 { 169, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_UDIVFIX
1166 { 168, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_SDIVFIX
1167 { 167, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
1168 { 166, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
1169 { 165, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_UMULFIX
1170 { 164, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_SMULFIX
1171 { 163, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_SSHLSAT
1172 { 162, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_USHLSAT
1173 { 161, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBSAT
1174 { 160, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_USUBSAT
1175 { 159, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SADDSAT
1176 { 158, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UADDSAT
1177 { 157, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULH
1178 { 156, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULH
1179 { 155, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULO
1180 { 154, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UMULO
1181 { 153, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBE
1182 { 152, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBO
1183 { 151, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SADDE
1184 { 150, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDO
1185 { 149, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBE
1186 { 148, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_USUBO
1187 { 147, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_UADDE
1188 { 146, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_UADDO
1189 { 145, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_SELECT
1190 { 144, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_UCMP
1191 { 143, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SCMP
1192 { 142, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FCMP
1193 { 141, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ICMP
1194 { 140, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTL
1195 { 139, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_ROTR
1196 { 138, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHR
1197 { 137, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_FSHL
1198 { 136, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_ASHR
1199 { 135, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_LSHR
1200 { 134, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_SHL
1201 { 133, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ZEXT
1202 { 132, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT_INREG
1203 { 131, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_SEXT
1204 { 130, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VAARG
1205 { 129, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #129 = G_VASTART
1206 { 128, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_FCONSTANT
1207 { 127, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_CONSTANT
1208 { 126, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_TRUNC
1209 { 125, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_ANYEXT
1210 { 124, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1211 { 123, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
1212 { 122, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
1213 { 121, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #121 = G_INTRINSIC
1214 { 120, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
1215 { 119, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRINDIRECT
1216 { 118, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #118 = G_BRCOND
1217 { 117, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_PREFETCH
1218 { 116, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #116 = G_FENCE
1219 { 115, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
1220 { 114, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
1221 { 113, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
1222 { 112, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
1223 { 111, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
1224 { 110, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
1225 { 109, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
1226 { 108, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
1227 { 107, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
1228 { 106, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
1229 { 105, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
1230 { 104, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
1231 { 103, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
1232 { 102, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
1233 { 101, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
1234 { 100, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
1235 { 99, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
1236 { 98, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
1237 { 97, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1238 { 96, 5, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
1239 { 95, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_STORE
1240 { 94, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
1241 { 93, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
1242 { 92, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
1243 { 91, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
1244 { 90, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_SEXTLOAD
1245 { 89, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #89 = G_LOAD
1246 { 88, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
1247 { 87, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
1248 { 86, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
1249 { 85, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
1250 { 84, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
1251 { 83, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
1252 { 82, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
1253 { 81, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
1254 { 80, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
1255 { 79, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_FREEZE
1256 { 78, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_BITCAST
1257 { 77, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTTOPTR
1258 { 76, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_PTRTOINT
1259 { 75, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
1260 { 74, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
1261 { 73, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
1262 { 72, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
1263 { 71, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_INSERT
1264 { 70, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
1265 { 69, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_EXTRACT
1266 { 68, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
1267 { 67, 5, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
1268 { 66, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
1269 { 65, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
1270 { 64, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #64 = G_PHI
1271 { 63, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
1272 { 62, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_XOR
1273 { 61, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_OR
1274 { 60, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #60 = G_AND
1275 { 59, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UDIVREM
1276 { 58, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SDIVREM
1277 { 57, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UREM
1278 { 56, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SREM
1279 { 55, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIV
1280 { 54, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIV
1281 { 53, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_MUL
1282 { 52, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SUB
1283 { 51, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #51 = G_ADD
1284 { 50, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
1285 { 49, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
1286 { 48, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
1287 { 47, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
1288 { 46, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
1289 { 45, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
1290 { 44, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
1291 { 43, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
1292 { 42, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER
1293 { 41, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
1294 { 40, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1295 { 39, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
1296 { 38, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
1297 { 37, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
1298 { 36, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET
1299 { 35, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
1300 { 34, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP
1301 { 33, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP
1302 { 32, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
1303 { 31, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT
1304 { 30, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
1305 { 29, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
1306 { 28, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
1307 { 27, 6, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT
1308 { 26, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL
1309 { 25, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP
1310 { 24, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE
1311 { 23, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
1312 { 22, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END
1313 { 21, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START
1314 { 20, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE
1315 { 19, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY
1316 { 18, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE
1317 { 17, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL
1318 { 16, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI
1319 { 15, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
1320 { 14, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
1321 { 13, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE
1322 { 12, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
1323 { 11, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
1324 { 10, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1325 { 9, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1326 { 8, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1327 { 7, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
1328 { 6, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1329 { 5, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
1330 { 4, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
1331 { 3, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1332 { 2, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
1333 { 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
1334 { 0, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
1335 }, {
1336 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1337 /* 1 */
1338 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1339 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1340 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1341 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1342 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1343 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1344 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1345 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1346 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1347 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1348 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1349 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1350 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1351 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1352 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1353 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1354 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1355 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1356 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1357 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1358 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1359 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1360 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1361 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1362 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1363 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1364 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1365 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1366 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1367 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1368 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1369 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1370 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1371 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1372 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1373 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1374 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1375 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1376 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1377 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1378 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1379 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1380 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1381 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1382 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1383 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1384 /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1385 /* 154 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1386 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1387 /* 157 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1388 /* 159 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1389 /* 161 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1390 /* 232 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1391 /* 234 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1392 /* 238 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1393 /* 241 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1394 /* 244 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1395 /* 248 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1396 /* 252 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1397 /* 256 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1398 /* 263 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1399 /* 284 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1400 /* 298 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1401 /* 317 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1402 /* 326 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1403 /* 333 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1404 /* 342 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1405 /* 347 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1406 /* 352 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1407 /* 354 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1408 /* 363 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1409 /* 373 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1410 /* 380 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1411 /* 392 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1412 /* 405 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1413 /* 408 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1414 /* 410 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1415 /* 412 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1416 /* 414 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1417 /* 418 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1418 /* 421 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1419 /* 424 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1420 /* 427 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1421 /* 446 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1422 /* 450 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1423 /* 454 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1424 /* 458 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 }, {
1426 /* 0 */
1427 }
1428};
1429
1430
1431#ifdef __GNUC__
1432#pragma GCC diagnostic push
1433#pragma GCC diagnostic ignored "-Woverlength-strings"
1434#endif
1435extern const char R600InstrNameData[] = {
1436 /* 0 */ "CF_TC_R600\0"
1437 /* 11 */ "CF_VC_R600\0"
1438 /* 22 */ "CF_END_R600\0"
1439 /* 34 */ "CF_ELSE_R600\0"
1440 /* 47 */ "CF_PUSH_ELSE_R600\0"
1441 /* 65 */ "CF_CONTINUE_R600\0"
1442 /* 82 */ "FNEG_R600\0"
1443 /* 92 */ "LOOP_BREAK_R600\0"
1444 /* 108 */ "CF_JUMP_R600\0"
1445 /* 121 */ "END_LOOP_R600\0"
1446 /* 135 */ "WHILE_LOOP_R600\0"
1447 /* 151 */ "POP_R600\0"
1448 /* 160 */ "FABS_R600\0"
1449 /* 170 */ "CF_CALL_FS_R600\0"
1450 /* 186 */ "DOT4_r600\0"
1451 /* 196 */ "MULADD_r600\0"
1452 /* 208 */ "LOG_CLAMPED_r600\0"
1453 /* 225 */ "RECIP_CLAMPED_r600\0"
1454 /* 244 */ "RECIPSQRT_CLAMPED_r600\0"
1455 /* 267 */ "CNDE_r600\0"
1456 /* 277 */ "MULADD_IEEE_r600\0"
1457 /* 294 */ "LOG_IEEE_r600\0"
1458 /* 308 */ "RECIP_IEEE_r600\0"
1459 /* 324 */ "EXP_IEEE_r600\0"
1460 /* 338 */ "RECIPSQRT_IEEE_r600\0"
1461 /* 358 */ "CNDGE_r600\0"
1462 /* 369 */ "LSHL_r600\0"
1463 /* 379 */ "SIN_r600\0"
1464 /* 388 */ "ASHR_r600\0"
1465 /* 398 */ "LSHR_r600\0"
1466 /* 408 */ "COS_r600\0"
1467 /* 417 */ "CNDGT_r600\0"
1468 /* 428 */ "MUL_LIT_r600\0"
1469 /* 441 */ "UINT_TO_FLT_r600\0"
1470 /* 458 */ "MULHI_UINT_r600\0"
1471 /* 474 */ "MULLO_UINT_r600\0"
1472 /* 490 */ "FLT_TO_UINT_r600\0"
1473 /* 507 */ "RECIP_UINT_r600\0"
1474 /* 523 */ "MULHI_INT_r600\0"
1475 /* 538 */ "MULLO_INT_r600\0"
1476 /* 553 */ "FLT_TO_INT_r600\0"
1477 /* 569 */ "SIN_r700\0"
1478 /* 578 */ "COS_r700\0"
1479 /* 587 */ "G_FLOG10\0"
1480 /* 596 */ "G_FEXP10\0"
1481 /* 605 */ "SETGE_DX10\0"
1482 /* 616 */ "SETNE_DX10\0"
1483 /* 627 */ "SETE_DX10\0"
1484 /* 637 */ "MIN_DX10\0"
1485 /* 646 */ "SETGT_DX10\0"
1486 /* 657 */ "MAX_DX10\0"
1487 /* 666 */ "INTERP_LOAD_P0\0"
1488 /* 681 */ "RAT_STORE_DWORD32\0"
1489 /* 699 */ "MOV_IMM_F32\0"
1490 /* 711 */ "MOV_IMM_I32\0"
1491 /* 723 */ "FLT16_TO_FLT32\0"
1492 /* 738 */ "CONTINUEC_f32\0"
1493 /* 752 */ "IFC_f32\0"
1494 /* 760 */ "BREAKC_f32\0"
1495 /* 771 */ "BRANCH_COND_f32\0"
1496 /* 787 */ "CONTINUE_LOGICALZ_f32\0"
1497 /* 809 */ "IF_LOGICALZ_f32\0"
1498 /* 825 */ "BREAK_LOGICALZ_f32\0"
1499 /* 844 */ "CONTINUE_LOGICALNZ_f32\0"
1500 /* 867 */ "IF_LOGICALNZ_f32\0"
1501 /* 884 */ "BREAK_LOGICALNZ_f32\0"
1502 /* 904 */ "CONTINUEC_i32\0"
1503 /* 918 */ "IFC_i32\0"
1504 /* 926 */ "BREAKC_i32\0"
1505 /* 937 */ "BRANCH_COND_i32\0"
1506 /* 953 */ "CONTINUE_LOGICALZ_i32\0"
1507 /* 975 */ "IF_LOGICALZ_i32\0"
1508 /* 991 */ "BREAK_LOGICALZ_i32\0"
1509 /* 1010 */ "CONTINUE_LOGICALNZ_i32\0"
1510 /* 1033 */ "IF_LOGICALNZ_i32\0"
1511 /* 1050 */ "BREAK_LOGICALNZ_i32\0"
1512 /* 1070 */ "G_FLOG2\0"
1513 /* 1078 */ "G_FEXP2\0"
1514 /* 1086 */ "R600_EXTRACT_ELT_V2\0"
1515 /* 1106 */ "R600_INSERT_ELT_V2\0"
1516 /* 1125 */ "MULHI_UINT_cm24\0"
1517 /* 1141 */ "MULHI_INT_cm24\0"
1518 /* 1156 */ "RAT_STORE_DWORD64\0"
1519 /* 1174 */ "R600_EXTRACT_ELT_V4\0"
1520 /* 1194 */ "R600_INSERT_ELT_V4\0"
1521 /* 1213 */ "DOT_4\0"
1522 /* 1219 */ "FLT32_TO_FLT16\0"
1523 /* 1234 */ "RAT_STORE_DWORD128\0"
1524 /* 1253 */ "G_FMA\0"
1525 /* 1259 */ "G_STRICT_FMA\0"
1526 /* 1272 */ "TEX_SAMPLE_C_LB\0"
1527 /* 1288 */ "TEX_SAMPLE_LB\0"
1528 /* 1302 */ "G_FSUB\0"
1529 /* 1309 */ "G_STRICT_FSUB\0"
1530 /* 1323 */ "G_ATOMICRMW_FSUB\0"
1531 /* 1340 */ "G_SUB\0"
1532 /* 1346 */ "LDS_SUB\0"
1533 /* 1354 */ "G_ATOMICRMW_SUB\0"
1534 /* 1370 */ "G_INTRINSIC\0"
1535 /* 1382 */ "ENDFUNC\0"
1536 /* 1390 */ "G_FPTRUNC\0"
1537 /* 1400 */ "G_INTRINSIC_TRUNC\0"
1538 /* 1418 */ "G_TRUNC\0"
1539 /* 1426 */ "G_BUILD_VECTOR_TRUNC\0"
1540 /* 1447 */ "G_DYN_STACKALLOC\0"
1541 /* 1464 */ "TEX_SAMPLE_C\0"
1542 /* 1477 */ "G_FMAD\0"
1543 /* 1484 */ "G_INDEXED_SEXTLOAD\0"
1544 /* 1503 */ "G_SEXTLOAD\0"
1545 /* 1514 */ "G_INDEXED_ZEXTLOAD\0"
1546 /* 1533 */ "G_ZEXTLOAD\0"
1547 /* 1544 */ "INTERP_VEC_LOAD\0"
1548 /* 1560 */ "G_INDEXED_LOAD\0"
1549 /* 1575 */ "G_LOAD\0"
1550 /* 1582 */ "PAD\0"
1551 /* 1586 */ "G_VECREDUCE_FADD\0"
1552 /* 1603 */ "G_FADD\0"
1553 /* 1610 */ "G_VECREDUCE_SEQ_FADD\0"
1554 /* 1631 */ "G_STRICT_FADD\0"
1555 /* 1645 */ "G_ATOMICRMW_FADD\0"
1556 /* 1662 */ "G_VECREDUCE_ADD\0"
1557 /* 1678 */ "G_ADD\0"
1558 /* 1684 */ "G_PTR_ADD\0"
1559 /* 1694 */ "LDS_ADD\0"
1560 /* 1702 */ "G_ATOMICRMW_ADD\0"
1561 /* 1718 */ "TEX_LD\0"
1562 /* 1725 */ "G_ATOMICRMW_NAND\0"
1563 /* 1742 */ "G_VECREDUCE_AND\0"
1564 /* 1758 */ "G_AND\0"
1565 /* 1764 */ "LDS_AND\0"
1566 /* 1772 */ "G_ATOMICRMW_AND\0"
1567 /* 1788 */ "LIFETIME_END\0"
1568 /* 1801 */ "G_BRCOND\0"
1569 /* 1810 */ "JUMP_COND\0"
1570 /* 1820 */ "G_LLROUND\0"
1571 /* 1830 */ "G_LROUND\0"
1572 /* 1839 */ "G_INTRINSIC_ROUND\0"
1573 /* 1857 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1574 /* 1883 */ "LOAD_STACK_GUARD\0"
1575 /* 1900 */ "TXD\0"
1576 /* 1904 */ "PSEUDO_PROBE\0"
1577 /* 1917 */ "G_SSUBE\0"
1578 /* 1925 */ "G_USUBE\0"
1579 /* 1933 */ "G_FENCE\0"
1580 /* 1941 */ "ARITH_FENCE\0"
1581 /* 1953 */ "REG_SEQUENCE\0"
1582 /* 1966 */ "G_SADDE\0"
1583 /* 1974 */ "G_UADDE\0"
1584 /* 1982 */ "G_GET_FPMODE\0"
1585 /* 1995 */ "G_RESET_FPMODE\0"
1586 /* 2010 */ "G_SET_FPMODE\0"
1587 /* 2023 */ "MUL_IEEE\0"
1588 /* 2032 */ "G_FMINNUM_IEEE\0"
1589 /* 2047 */ "G_FMAXNUM_IEEE\0"
1590 /* 2062 */ "SGE\0"
1591 /* 2066 */ "PRED_SETGE\0"
1592 /* 2077 */ "G_VSCALE\0"
1593 /* 2086 */ "G_JUMP_TABLE\0"
1594 /* 2099 */ "BUNDLE\0"
1595 /* 2106 */ "TEX_SAMPLE\0"
1596 /* 2117 */ "RNDNE\0"
1597 /* 2123 */ "G_MEMCPY_INLINE\0"
1598 /* 2139 */ "SNE\0"
1599 /* 2143 */ "PRED_SETNE\0"
1600 /* 2154 */ "LOCAL_ESCAPE\0"
1601 /* 2167 */ "CF_ALU_PUSH_BEFORE\0"
1602 /* 2186 */ "G_STACKRESTORE\0"
1603 /* 2201 */ "G_INDEXED_STORE\0"
1604 /* 2217 */ "G_STORE\0"
1605 /* 2225 */ "ELSE\0"
1606 /* 2230 */ "G_BITREVERSE\0"
1607 /* 2243 */ "FETCH_CLAUSE\0"
1608 /* 2256 */ "ALU_CLAUSE\0"
1609 /* 2267 */ "PRED_SETE\0"
1610 /* 2277 */ "LDS_BYTE_WRITE\0"
1611 /* 2292 */ "MASK_WRITE\0"
1612 /* 2303 */ "LDS_WRITE\0"
1613 /* 2313 */ "LDS_SHORT_WRITE\0"
1614 /* 2329 */ "DBG_VALUE\0"
1615 /* 2339 */ "G_GLOBAL_VALUE\0"
1616 /* 2354 */ "G_PTRAUTH_GLOBAL_VALUE\0"
1617 /* 2377 */ "CONVERGENCECTRL_GLUE\0"
1618 /* 2398 */ "CF_ALU_CONTINUE\0"
1619 /* 2414 */ "G_STACKSAVE\0"
1620 /* 2426 */ "G_MEMMOVE\0"
1621 /* 2436 */ "G_FREEZE\0"
1622 /* 2445 */ "G_FCANONICALIZE\0"
1623 /* 2461 */ "G_CTLZ_ZERO_UNDEF\0"
1624 /* 2479 */ "G_CTTZ_ZERO_UNDEF\0"
1625 /* 2497 */ "G_IMPLICIT_DEF\0"
1626 /* 2512 */ "DBG_INSTR_REF\0"
1627 /* 2526 */ "ENDIF\0"
1628 /* 2532 */ "TEX_VTX_CONSTBUF\0"
1629 /* 2549 */ "TEX_VTX_TEXBUF\0"
1630 /* 2564 */ "G_FNEG\0"
1631 /* 2571 */ "EXTRACT_SUBREG\0"
1632 /* 2586 */ "INSERT_SUBREG\0"
1633 /* 2600 */ "G_SEXT_INREG\0"
1634 /* 2613 */ "SUBREG_TO_REG\0"
1635 /* 2627 */ "CF_TC_EG\0"
1636 /* 2636 */ "CF_VC_EG\0"
1637 /* 2645 */ "CF_END_EG\0"
1638 /* 2655 */ "CF_ELSE_EG\0"
1639 /* 2666 */ "CF_CONTINUE_EG\0"
1640 /* 2681 */ "CF_PUSH_EG\0"
1641 /* 2692 */ "LOOP_BREAK_EG\0"
1642 /* 2706 */ "CF_JUMP_EG\0"
1643 /* 2717 */ "END_LOOP_EG\0"
1644 /* 2729 */ "WHILE_LOOP_EG\0"
1645 /* 2743 */ "POP_EG\0"
1646 /* 2750 */ "CF_CALL_FS_EG\0"
1647 /* 2764 */ "G_ATOMIC_CMPXCHG\0"
1648 /* 2781 */ "LDS_WRXCHG\0"
1649 /* 2792 */ "G_ATOMICRMW_XCHG\0"
1650 /* 2809 */ "G_FLOG\0"
1651 /* 2816 */ "G_VAARG\0"
1652 /* 2824 */ "PREALLOCATED_ARG\0"
1653 /* 2841 */ "TEX_SAMPLE_C_G\0"
1654 /* 2856 */ "TEX_SAMPLE_G\0"
1655 /* 2869 */ "BRANCH\0"
1656 /* 2876 */ "G_PREFETCH\0"
1657 /* 2887 */ "ENDSWITCH\0"
1658 /* 2897 */ "G_SMULH\0"
1659 /* 2905 */ "G_UMULH\0"
1660 /* 2913 */ "G_FTANH\0"
1661 /* 2921 */ "G_FSINH\0"
1662 /* 2929 */ "G_FCOSH\0"
1663 /* 2937 */ "TEX_GET_GRADIENTS_H\0"
1664 /* 2957 */ "TEX_SET_GRADIENTS_H\0"
1665 /* 2977 */ "DBG_PHI\0"
1666 /* 2985 */ "G_FPTOSI\0"
1667 /* 2994 */ "G_FPTOUI\0"
1668 /* 3003 */ "G_FPOWI\0"
1669 /* 3011 */ "CF_ALU_BREAK\0"
1670 /* 3024 */ "G_PTRMASK\0"
1671 /* 3034 */ "GC_LABEL\0"
1672 /* 3043 */ "DBG_LABEL\0"
1673 /* 3053 */ "EH_LABEL\0"
1674 /* 3062 */ "ANNOTATION_LABEL\0"
1675 /* 3079 */ "ICALL_BRANCH_FUNNEL\0"
1676 /* 3099 */ "G_FSHL\0"
1677 /* 3106 */ "G_SHL\0"
1678 /* 3112 */ "G_FCEIL\0"
1679 /* 3120 */ "PATCHABLE_TAIL_CALL\0"
1680 /* 3140 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1681 /* 3167 */ "PATCHABLE_EVENT_CALL\0"
1682 /* 3188 */ "FENTRY_CALL\0"
1683 /* 3200 */ "KILL\0"
1684 /* 3205 */ "G_CONSTANT_POOL\0"
1685 /* 3221 */ "G_ROTL\0"
1686 /* 3228 */ "G_VECREDUCE_FMUL\0"
1687 /* 3245 */ "G_FMUL\0"
1688 /* 3252 */ "G_VECREDUCE_SEQ_FMUL\0"
1689 /* 3273 */ "G_STRICT_FMUL\0"
1690 /* 3287 */ "G_VECREDUCE_MUL\0"
1691 /* 3303 */ "G_MUL\0"
1692 /* 3309 */ "TEX_SAMPLE_C_L\0"
1693 /* 3324 */ "TEX_SAMPLE_L\0"
1694 /* 3337 */ "CF_END_CM\0"
1695 /* 3347 */ "G_FREM\0"
1696 /* 3354 */ "G_STRICT_FREM\0"
1697 /* 3368 */ "G_SREM\0"
1698 /* 3375 */ "G_UREM\0"
1699 /* 3382 */ "G_SDIVREM\0"
1700 /* 3392 */ "G_UDIVREM\0"
1701 /* 3402 */ "INLINEASM\0"
1702 /* 3412 */ "G_VECREDUCE_FMINIMUM\0"
1703 /* 3433 */ "G_FMINIMUM\0"
1704 /* 3444 */ "G_VECREDUCE_FMAXIMUM\0"
1705 /* 3465 */ "G_FMAXIMUM\0"
1706 /* 3476 */ "G_FMINNUM\0"
1707 /* 3486 */ "G_FMAXNUM\0"
1708 /* 3496 */ "G_FATAN\0"
1709 /* 3504 */ "G_FTAN\0"
1710 /* 3511 */ "G_INTRINSIC_ROUNDEVEN\0"
1711 /* 3533 */ "G_ASSERT_ALIGN\0"
1712 /* 3548 */ "G_FCOPYSIGN\0"
1713 /* 3560 */ "DUMMY_CHAIN\0"
1714 /* 3572 */ "ENDMAIN\0"
1715 /* 3580 */ "G_VECREDUCE_FMIN\0"
1716 /* 3597 */ "G_ATOMICRMW_FMIN\0"
1717 /* 3614 */ "G_VECREDUCE_SMIN\0"
1718 /* 3631 */ "G_SMIN\0"
1719 /* 3638 */ "G_VECREDUCE_UMIN\0"
1720 /* 3655 */ "G_UMIN\0"
1721 /* 3662 */ "G_ATOMICRMW_UMIN\0"
1722 /* 3679 */ "G_ATOMICRMW_MIN\0"
1723 /* 3695 */ "G_FASIN\0"
1724 /* 3703 */ "G_FSIN\0"
1725 /* 3710 */ "CFI_INSTRUCTION\0"
1726 /* 3726 */ "RETURN\0"
1727 /* 3733 */ "RAT_ATOMIC_RSUB_RTN\0"
1728 /* 3753 */ "RAT_ATOMIC_SUB_RTN\0"
1729 /* 3772 */ "RAT_ATOMIC_ADD_RTN\0"
1730 /* 3791 */ "RAT_ATOMIC_AND_RTN\0"
1731 /* 3810 */ "RAT_ATOMIC_XOR_RTN\0"
1732 /* 3829 */ "RAT_ATOMIC_OR_RTN\0"
1733 /* 3847 */ "RAT_ATOMIC_DEC_UINT_RTN\0"
1734 /* 3871 */ "RAT_ATOMIC_INC_UINT_RTN\0"
1735 /* 3895 */ "RAT_ATOMIC_MIN_UINT_RTN\0"
1736 /* 3919 */ "RAT_ATOMIC_MAX_UINT_RTN\0"
1737 /* 3943 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\0"
1738 /* 3970 */ "RAT_ATOMIC_XCHG_INT_RTN\0"
1739 /* 3994 */ "RAT_ATOMIC_MIN_INT_RTN\0"
1740 /* 4017 */ "RAT_ATOMIC_MAX_INT_RTN\0"
1741 /* 4040 */ "RETDYN\0"
1742 /* 4047 */ "G_SSUBO\0"
1743 /* 4055 */ "G_USUBO\0"
1744 /* 4063 */ "G_SADDO\0"
1745 /* 4071 */ "G_UADDO\0"
1746 /* 4079 */ "TEX_GET_TEXTURE_RESINFO\0"
1747 /* 4103 */ "JUMP_TABLE_DEBUG_INFO\0"
1748 /* 4125 */ "G_SMULO\0"
1749 /* 4133 */ "G_UMULO\0"
1750 /* 4141 */ "G_BZERO\0"
1751 /* 4149 */ "STACKMAP\0"
1752 /* 4158 */ "G_DEBUGTRAP\0"
1753 /* 4170 */ "G_UBSANTRAP\0"
1754 /* 4182 */ "G_TRAP\0"
1755 /* 4189 */ "G_ATOMICRMW_UDEC_WRAP\0"
1756 /* 4211 */ "G_ATOMICRMW_UINC_WRAP\0"
1757 /* 4233 */ "G_BSWAP\0"
1758 /* 4241 */ "G_SITOFP\0"
1759 /* 4250 */ "G_UITOFP\0"
1760 /* 4259 */ "G_FCMP\0"
1761 /* 4266 */ "G_ICMP\0"
1762 /* 4273 */ "G_SCMP\0"
1763 /* 4280 */ "G_UCMP\0"
1764 /* 4287 */ "JUMP\0"
1765 /* 4292 */ "ENDLOOP\0"
1766 /* 4300 */ "WHILELOOP\0"
1767 /* 4310 */ "CONVERGENCECTRL_LOOP\0"
1768 /* 4331 */ "G_CTPOP\0"
1769 /* 4339 */ "PATCHABLE_OP\0"
1770 /* 4352 */ "FAULTING_OP\0"
1771 /* 4364 */ "PREALLOCATED_SETUP\0"
1772 /* 4383 */ "G_FLDEXP\0"
1773 /* 4392 */ "G_STRICT_FLDEXP\0"
1774 /* 4408 */ "G_FEXP\0"
1775 /* 4415 */ "G_FFREXP\0"
1776 /* 4424 */ "G_BR\0"
1777 /* 4429 */ "INLINEASM_BR\0"
1778 /* 4442 */ "G_BLOCK_ADDR\0"
1779 /* 4455 */ "MOV_IMM_GLOBAL_ADDR\0"
1780 /* 4475 */ "MEMBARRIER\0"
1781 /* 4486 */ "G_CONSTANT_FOLD_BARRIER\0"
1782 /* 4510 */ "GROUP_BARRIER\0"
1783 /* 4524 */ "CF_ALU_ELSE_AFTER\0"
1784 /* 4542 */ "CF_ALU_POP_AFTER\0"
1785 /* 4559 */ "PATCHABLE_FUNCTION_ENTER\0"
1786 /* 4584 */ "G_READCYCLECOUNTER\0"
1787 /* 4603 */ "G_READSTEADYCOUNTER\0"
1788 /* 4623 */ "G_READ_REGISTER\0"
1789 /* 4639 */ "G_WRITE_REGISTER\0"
1790 /* 4656 */ "G_ASHR\0"
1791 /* 4663 */ "G_FSHR\0"
1792 /* 4670 */ "G_LSHR\0"
1793 /* 4677 */ "CONVERGENCECTRL_ANCHOR\0"
1794 /* 4700 */ "RAT_MSKOR\0"
1795 /* 4710 */ "G_FFLOOR\0"
1796 /* 4719 */ "G_EXTRACT_SUBVECTOR\0"
1797 /* 4739 */ "G_INSERT_SUBVECTOR\0"
1798 /* 4758 */ "G_BUILD_VECTOR\0"
1799 /* 4773 */ "G_SHUFFLE_VECTOR\0"
1800 /* 4790 */ "G_SPLAT_VECTOR\0"
1801 /* 4805 */ "G_VECREDUCE_XOR\0"
1802 /* 4821 */ "G_XOR\0"
1803 /* 4827 */ "LDS_XOR\0"
1804 /* 4835 */ "G_ATOMICRMW_XOR\0"
1805 /* 4851 */ "G_VECREDUCE_OR\0"
1806 /* 4866 */ "G_OR\0"
1807 /* 4871 */ "LDS_OR\0"
1808 /* 4878 */ "G_ATOMICRMW_OR\0"
1809 /* 4893 */ "G_ROTR\0"
1810 /* 4900 */ "TEX_LDPTR\0"
1811 /* 4910 */ "G_INTTOPTR\0"
1812 /* 4921 */ "G_FABS\0"
1813 /* 4928 */ "G_ABS\0"
1814 /* 4934 */ "G_UNMERGE_VALUES\0"
1815 /* 4951 */ "G_MERGE_VALUES\0"
1816 /* 4966 */ "LITERALS\0"
1817 /* 4975 */ "G_FACOS\0"
1818 /* 4983 */ "G_FCOS\0"
1819 /* 4990 */ "G_CONCAT_VECTORS\0"
1820 /* 5007 */ "COPY_TO_REGCLASS\0"
1821 /* 5024 */ "G_IS_FPCLASS\0"
1822 /* 5037 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1823 /* 5067 */ "G_VECTOR_COMPRESS\0"
1824 /* 5085 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1825 /* 5112 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1826 /* 5150 */ "G_SSUBSAT\0"
1827 /* 5160 */ "G_USUBSAT\0"
1828 /* 5170 */ "G_SADDSAT\0"
1829 /* 5180 */ "G_UADDSAT\0"
1830 /* 5190 */ "G_SSHLSAT\0"
1831 /* 5200 */ "G_USHLSAT\0"
1832 /* 5210 */ "G_SMULFIXSAT\0"
1833 /* 5223 */ "G_UMULFIXSAT\0"
1834 /* 5236 */ "G_SDIVFIXSAT\0"
1835 /* 5249 */ "G_UDIVFIXSAT\0"
1836 /* 5262 */ "FRACT\0"
1837 /* 5268 */ "G_EXTRACT\0"
1838 /* 5278 */ "G_SELECT\0"
1839 /* 5287 */ "G_BRINDIRECT\0"
1840 /* 5300 */ "RAT_ATOMIC_RSUB_NORET\0"
1841 /* 5322 */ "RAT_ATOMIC_SUB_NORET\0"
1842 /* 5343 */ "RAT_ATOMIC_ADD_NORET\0"
1843 /* 5364 */ "RAT_ATOMIC_AND_NORET\0"
1844 /* 5385 */ "RAT_ATOMIC_XOR_NORET\0"
1845 /* 5406 */ "RAT_ATOMIC_OR_NORET\0"
1846 /* 5426 */ "RAT_ATOMIC_DEC_UINT_NORET\0"
1847 /* 5452 */ "RAT_ATOMIC_INC_UINT_NORET\0"
1848 /* 5478 */ "RAT_ATOMIC_MIN_UINT_NORET\0"
1849 /* 5504 */ "RAT_ATOMIC_MAX_UINT_NORET\0"
1850 /* 5530 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\0"
1851 /* 5559 */ "RAT_ATOMIC_XCHG_INT_NORET\0"
1852 /* 5585 */ "RAT_ATOMIC_MIN_INT_NORET\0"
1853 /* 5610 */ "RAT_ATOMIC_MAX_INT_NORET\0"
1854 /* 5635 */ "LDS_SUB_RET\0"
1855 /* 5647 */ "LDS_UBYTE_READ_RET\0"
1856 /* 5666 */ "LDS_BYTE_READ_RET\0"
1857 /* 5684 */ "LDS_READ_RET\0"
1858 /* 5697 */ "LDS_USHORT_READ_RET\0"
1859 /* 5717 */ "LDS_SHORT_READ_RET\0"
1860 /* 5736 */ "LDS_ADD_RET\0"
1861 /* 5748 */ "LDS_AND_RET\0"
1862 /* 5760 */ "PATCHABLE_RET\0"
1863 /* 5774 */ "LDS_WRXCHG_RET\0"
1864 /* 5789 */ "LDS_XOR_RET\0"
1865 /* 5801 */ "LDS_OR_RET\0"
1866 /* 5812 */ "LDS_MIN_UINT_RET\0"
1867 /* 5829 */ "LDS_MAX_UINT_RET\0"
1868 /* 5846 */ "LDS_MIN_INT_RET\0"
1869 /* 5862 */ "LDS_MAX_INT_RET\0"
1870 /* 5878 */ "LDS_CMPST_RET\0"
1871 /* 5892 */ "G_MEMSET\0"
1872 /* 5901 */ "IF_PREDICATE_SET\0"
1873 /* 5918 */ "KILLGT\0"
1874 /* 5925 */ "SGT\0"
1875 /* 5929 */ "PRED_SETGT\0"
1876 /* 5940 */ "PATCHABLE_FUNCTION_EXIT\0"
1877 /* 5964 */ "G_BRJT\0"
1878 /* 5971 */ "G_EXTRACT_VECTOR_ELT\0"
1879 /* 5992 */ "G_INSERT_VECTOR_ELT\0"
1880 /* 6012 */ "DEFAULT\0"
1881 /* 6020 */ "G_FCONSTANT\0"
1882 /* 6032 */ "G_CONSTANT\0"
1883 /* 6043 */ "G_INTRINSIC_CONVERGENT\0"
1884 /* 6066 */ "STATEPOINT\0"
1885 /* 6077 */ "PATCHPOINT\0"
1886 /* 6088 */ "G_PTRTOINT\0"
1887 /* 6099 */ "G_FRINT\0"
1888 /* 6107 */ "G_INTRINSIC_LLRINT\0"
1889 /* 6126 */ "G_INTRINSIC_LRINT\0"
1890 /* 6144 */ "SUBB_UINT\0"
1891 /* 6154 */ "ADDC_UINT\0"
1892 /* 6164 */ "SETGE_UINT\0"
1893 /* 6175 */ "FFBH_UINT\0"
1894 /* 6185 */ "LDS_MIN_UINT\0"
1895 /* 6198 */ "SETGT_UINT\0"
1896 /* 6209 */ "LDS_MAX_UINT\0"
1897 /* 6222 */ "G_FNEARBYINT\0"
1898 /* 6235 */ "SUB_INT\0"
1899 /* 6243 */ "ADD_INT\0"
1900 /* 6251 */ "AND_INT\0"
1901 /* 6259 */ "CNDE_INT\0"
1902 /* 6268 */ "CNDGE_INT\0"
1903 /* 6278 */ "PRED_SETGE_INT\0"
1904 /* 6293 */ "PRED_SETNE_INT\0"
1905 /* 6308 */ "PRED_SETE_INT\0"
1906 /* 6322 */ "FFBL_INT\0"
1907 /* 6331 */ "LDS_MIN_INT\0"
1908 /* 6343 */ "XOR_INT\0"
1909 /* 6351 */ "CNDGT_INT\0"
1910 /* 6361 */ "PRED_SETGT_INT\0"
1911 /* 6376 */ "BCNT_INT\0"
1912 /* 6385 */ "NOT_INT\0"
1913 /* 6393 */ "LDS_MAX_INT\0"
1914 /* 6405 */ "G_VASTART\0"
1915 /* 6415 */ "LIFETIME_START\0"
1916 /* 6430 */ "G_INVOKE_REGION_START\0"
1917 /* 6452 */ "G_INSERT\0"
1918 /* 6461 */ "G_FSQRT\0"
1919 /* 6469 */ "G_STRICT_FSQRT\0"
1920 /* 6484 */ "G_BITCAST\0"
1921 /* 6494 */ "G_ADDRSPACE_CAST\0"
1922 /* 6511 */ "DBG_VALUE_LIST\0"
1923 /* 6526 */ "LDS_CMPST\0"
1924 /* 6536 */ "G_FPEXT\0"
1925 /* 6544 */ "G_SEXT\0"
1926 /* 6551 */ "G_ASSERT_SEXT\0"
1927 /* 6565 */ "G_ANYEXT\0"
1928 /* 6574 */ "G_ZEXT\0"
1929 /* 6581 */ "G_ASSERT_ZEXT\0"
1930 /* 6595 */ "CF_ALU\0"
1931 /* 6602 */ "G_FDIV\0"
1932 /* 6609 */ "G_STRICT_FDIV\0"
1933 /* 6623 */ "G_SDIV\0"
1934 /* 6630 */ "G_UDIV\0"
1935 /* 6637 */ "G_GET_FPENV\0"
1936 /* 6649 */ "G_RESET_FPENV\0"
1937 /* 6663 */ "G_SET_FPENV\0"
1938 /* 6675 */ "MOV\0"
1939 /* 6679 */ "TEX_GET_GRADIENTS_V\0"
1940 /* 6699 */ "TEX_SET_GRADIENTS_V\0"
1941 /* 6719 */ "TXD_SHADOW\0"
1942 /* 6730 */ "G_FPOW\0"
1943 /* 6737 */ "INTERP_ZW\0"
1944 /* 6747 */ "INTERP_PAIR_ZW\0"
1945 /* 6762 */ "G_VECREDUCE_FMAX\0"
1946 /* 6779 */ "G_ATOMICRMW_FMAX\0"
1947 /* 6796 */ "G_VECREDUCE_SMAX\0"
1948 /* 6813 */ "G_SMAX\0"
1949 /* 6820 */ "G_VECREDUCE_UMAX\0"
1950 /* 6837 */ "G_UMAX\0"
1951 /* 6844 */ "G_ATOMICRMW_UMAX\0"
1952 /* 6861 */ "G_ATOMICRMW_MAX\0"
1953 /* 6877 */ "G_FRAME_INDEX\0"
1954 /* 6891 */ "G_SBFX\0"
1955 /* 6898 */ "G_UBFX\0"
1956 /* 6905 */ "G_SMULFIX\0"
1957 /* 6915 */ "G_UMULFIX\0"
1958 /* 6925 */ "G_SDIVFIX\0"
1959 /* 6935 */ "G_UDIVFIX\0"
1960 /* 6945 */ "PRED_X\0"
1961 /* 6952 */ "G_MEMCPY\0"
1962 /* 6961 */ "CONST_COPY\0"
1963 /* 6972 */ "CONVERGENCECTRL_ENTRY\0"
1964 /* 6994 */ "INTERP_XY\0"
1965 /* 7004 */ "INTERP_PAIR_XY\0"
1966 /* 7019 */ "G_CTLZ\0"
1967 /* 7026 */ "G_CTTZ\0"
1968 /* 7033 */ "R600_RegisterLoad\0"
1969 /* 7051 */ "R600_RegisterStore\0"
1970 /* 7070 */ "R600_ExportBuf\0"
1971 /* 7085 */ "EG_ExportBuf\0"
1972 /* 7098 */ "VTX_READ_32_eg\0"
1973 /* 7113 */ "RAT_WRITE_CACHELESS_32_eg\0"
1974 /* 7139 */ "MULADD_UINT24_eg\0"
1975 /* 7156 */ "MULHI_UINT24_eg\0"
1976 /* 7172 */ "MUL_UINT24_eg\0"
1977 /* 7186 */ "VTX_READ_64_eg\0"
1978 /* 7201 */ "RAT_WRITE_CACHELESS_64_eg\0"
1979 /* 7227 */ "DOT4_eg\0"
1980 /* 7235 */ "VTX_READ_16_eg\0"
1981 /* 7250 */ "VTX_READ_128_eg\0"
1982 /* 7266 */ "RAT_WRITE_CACHELESS_128_eg\0"
1983 /* 7293 */ "VTX_READ_8_eg\0"
1984 /* 7307 */ "FMA_eg\0"
1985 /* 7314 */ "MULADD_eg\0"
1986 /* 7324 */ "LOG_CLAMPED_eg\0"
1987 /* 7339 */ "RECIP_CLAMPED_eg\0"
1988 /* 7356 */ "RECIPSQRT_CLAMPED_eg\0"
1989 /* 7377 */ "RAT_STORE_TYPED_eg\0"
1990 /* 7396 */ "CNDE_eg\0"
1991 /* 7404 */ "MULADD_IEEE_eg\0"
1992 /* 7419 */ "LOG_IEEE_eg\0"
1993 /* 7431 */ "RECIP_IEEE_eg\0"
1994 /* 7445 */ "EXP_IEEE_eg\0"
1995 /* 7457 */ "RECIPSQRT_IEEE_eg\0"
1996 /* 7475 */ "CNDGE_eg\0"
1997 /* 7484 */ "LSHL_eg\0"
1998 /* 7492 */ "SIN_eg\0"
1999 /* 7499 */ "ASHR_eg\0"
2000 /* 7507 */ "LSHR_eg\0"
2001 /* 7515 */ "COS_eg\0"
2002 /* 7522 */ "CNDGT_eg\0"
2003 /* 7531 */ "MUL_LIT_eg\0"
2004 /* 7542 */ "UINT_TO_FLT_eg\0"
2005 /* 7557 */ "BFE_UINT_eg\0"
2006 /* 7569 */ "MULHI_UINT_eg\0"
2007 /* 7583 */ "MULLO_UINT_eg\0"
2008 /* 7597 */ "FLT_TO_UINT_eg\0"
2009 /* 7612 */ "RECIP_UINT_eg\0"
2010 /* 7626 */ "MOVA_INT_eg\0"
2011 /* 7638 */ "BFE_INT_eg\0"
2012 /* 7649 */ "BFI_INT_eg\0"
2013 /* 7660 */ "MULHI_INT_eg\0"
2014 /* 7673 */ "BFM_INT_eg\0"
2015 /* 7684 */ "BIT_ALIGN_INT_eg\0"
2016 /* 7701 */ "MULLO_INT_eg\0"
2017 /* 7714 */ "FLT_TO_INT_eg\0"
2018 /* 7728 */ "CUBE_r600_real\0"
2019 /* 7743 */ "CUBE_eg_real\0"
2020 /* 7756 */ "VTX_READ_32_cm\0"
2021 /* 7771 */ "MULADD_INT24_cm\0"
2022 /* 7787 */ "MUL_INT24_cm\0"
2023 /* 7800 */ "VTX_READ_64_cm\0"
2024 /* 7815 */ "VTX_READ_16_cm\0"
2025 /* 7830 */ "VTX_READ_128_cm\0"
2026 /* 7846 */ "VTX_READ_8_cm\0"
2027 /* 7860 */ "RECIP_CLAMPED_cm\0"
2028 /* 7877 */ "RECIPSQRT_CLAMPED_cm\0"
2029 /* 7898 */ "RAT_STORE_TYPED_cm\0"
2030 /* 7917 */ "LOG_IEEE_cm\0"
2031 /* 7929 */ "RECIP_IEEE_cm\0"
2032 /* 7943 */ "EXP_IEEE_cm\0"
2033 /* 7955 */ "RECIPSQRT_IEEE_cm\0"
2034 /* 7973 */ "SIN_cm\0"
2035 /* 7980 */ "COS_cm\0"
2036 /* 7987 */ "MULHI_UINT_cm\0"
2037 /* 8001 */ "MULLO_UINT_cm\0"
2038 /* 8015 */ "MULHI_INT_cm\0"
2039 /* 8028 */ "MULLO_INT_cm\0"
2040 /* 8041 */ "CUBE_r600_pseudo\0"
2041 /* 8058 */ "CUBE_eg_pseudo\0"
2042 /* 8073 */ "R600_ExportSwz\0"
2043 /* 8088 */ "EG_ExportSwz\0"
2044};
2045#ifdef __GNUC__
2046#pragma GCC diagnostic pop
2047#endif
2048
2049extern const unsigned R600InstrNameIndices[] = {
2050 2981U, 3402U, 4429U, 3710U, 3053U, 3034U, 3062U, 3200U,
2051 2571U, 2586U, 2499U, 2613U, 5007U, 2329U, 6511U, 2512U,
2052 2977U, 3043U, 1953U, 6967U, 2099U, 6415U, 1788U, 1904U,
2053 1941U, 4149U, 3188U, 6077U, 1883U, 4364U, 2824U, 6066U,
2054 2154U, 4352U, 4339U, 4559U, 5760U, 5940U, 3120U, 3167U,
2055 3140U, 3079U, 4475U, 4103U, 6972U, 4677U, 4310U, 2377U,
2056 6551U, 6581U, 3533U, 1678U, 1340U, 3303U, 6623U, 6630U,
2057 3368U, 3375U, 3382U, 3392U, 1758U, 4866U, 4821U, 2497U,
2058 2979U, 6877U, 2339U, 2354U, 3205U, 5268U, 4934U, 6452U,
2059 4951U, 4758U, 1426U, 4990U, 6088U, 4910U, 6484U, 2436U,
2060 4486U, 1857U, 1400U, 1839U, 6126U, 6107U, 3511U, 4584U,
2061 4603U, 1575U, 1503U, 1533U, 1560U, 1484U, 1514U, 2217U,
2062 2201U, 5037U, 2764U, 2792U, 1702U, 1354U, 1772U, 1725U,
2063 4878U, 4835U, 6861U, 3679U, 6844U, 3662U, 1645U, 1323U,
2064 6779U, 3597U, 4211U, 4189U, 1933U, 2876U, 1801U, 5287U,
2065 6430U, 1370U, 5085U, 6043U, 5112U, 6565U, 1418U, 6032U,
2066 6020U, 6405U, 2816U, 6544U, 2600U, 6574U, 3106U, 4670U,
2067 4656U, 3099U, 4663U, 4893U, 3221U, 4266U, 4259U, 4273U,
2068 4280U, 5278U, 4071U, 1974U, 4055U, 1925U, 4063U, 1966U,
2069 4047U, 1917U, 4133U, 4125U, 2905U, 2897U, 5180U, 5170U,
2070 5160U, 5150U, 5200U, 5190U, 6905U, 6915U, 5210U, 5223U,
2071 6925U, 6935U, 5236U, 5249U, 1603U, 1302U, 3245U, 1253U,
2072 1477U, 6602U, 3347U, 6730U, 3003U, 4408U, 1078U, 596U,
2073 2809U, 1070U, 587U, 4383U, 4415U, 2564U, 6536U, 1390U,
2074 2985U, 2994U, 4241U, 4250U, 4921U, 3548U, 5024U, 2445U,
2075 3476U, 3486U, 2032U, 2047U, 3433U, 3465U, 6637U, 6663U,
2076 6649U, 1982U, 2010U, 1995U, 1684U, 3024U, 3631U, 6813U,
2077 3655U, 6837U, 4928U, 1830U, 1820U, 4424U, 5964U, 2077U,
2078 4739U, 4719U, 5992U, 5971U, 4773U, 4790U, 5067U, 7026U,
2079 2479U, 7019U, 2461U, 4331U, 4233U, 2230U, 3112U, 4983U,
2080 3703U, 3504U, 4975U, 3695U, 3496U, 2929U, 2921U, 2913U,
2081 6461U, 4710U, 6099U, 6222U, 6494U, 4442U, 2086U, 1447U,
2082 2414U, 2186U, 1631U, 1309U, 3273U, 6609U, 3354U, 1259U,
2083 6469U, 4392U, 4623U, 4639U, 6952U, 2123U, 2426U, 5892U,
2084 4141U, 4182U, 4158U, 4170U, 1610U, 3252U, 1586U, 3228U,
2085 6762U, 3580U, 3444U, 3412U, 1662U, 3287U, 1742U, 4851U,
2086 4805U, 6796U, 3614U, 6820U, 3638U, 6891U, 6898U, 2869U,
2087 771U, 937U, 3018U, 760U, 926U, 884U, 1050U, 825U,
2088 991U, 6961U, 2405U, 738U, 904U, 844U, 1010U, 787U,
2089 953U, 8058U, 8041U, 6012U, 1213U, 3560U, 2225U, 1797U,
2090 1382U, 2526U, 4292U, 3572U, 2887U, 160U, 82U, 1385U,
2091 752U, 918U, 867U, 1033U, 809U, 975U, 5901U, 4287U,
2092 1810U, 2292U, 699U, 4455U, 711U, 6945U, 1086U, 1174U,
2093 1106U, 1194U, 7033U, 7051U, 4040U, 3726U, 1900U, 6719U,
2094 4300U, 1599U, 6154U, 6243U, 2256U, 6251U, 7499U, 388U,
2095 6376U, 7638U, 7557U, 7649U, 7673U, 7684U, 3115U, 6595U,
2096 3011U, 2398U, 4524U, 4542U, 2167U, 2750U, 170U, 2666U,
2097 65U, 2655U, 34U, 3337U, 2645U, 22U, 2706U, 108U,
2098 2681U, 47U, 2627U, 0U, 2636U, 11U, 6259U, 7396U,
2099 267U, 6268U, 7475U, 358U, 6351U, 7522U, 417U, 7980U,
2100 7515U, 408U, 578U, 7743U, 7728U, 7227U, 186U, 7085U,
2101 8088U, 2717U, 121U, 7943U, 7445U, 324U, 2243U, 6175U,
2102 6322U, 4713U, 723U, 1219U, 7714U, 553U, 7597U, 490U,
2103 7307U, 5262U, 4510U, 666U, 7004U, 6747U, 1544U, 6994U,
2104 6737U, 7543U, 442U, 5918U, 1694U, 5736U, 1764U, 5748U,
2105 5666U, 2277U, 6526U, 5878U, 6393U, 5862U, 6209U, 5829U,
2106 6331U, 5846U, 6185U, 5812U, 4871U, 5801U, 5684U, 5717U,
2107 2313U, 1346U, 5635U, 5647U, 5697U, 2303U, 2781U, 5774U,
2108 4827U, 5789U, 4966U, 7324U, 208U, 7917U, 7419U, 294U,
2109 2692U, 92U, 7484U, 369U, 7507U, 398U, 6775U, 657U,
2110 6397U, 6213U, 3593U, 637U, 6335U, 6189U, 6675U, 7626U,
2111 3241U, 7404U, 277U, 7771U, 7139U, 7314U, 196U, 8015U,
2112 1141U, 7660U, 523U, 7156U, 7987U, 1125U, 7569U, 458U,
2113 8028U, 7701U, 538U, 8001U, 7583U, 474U, 2023U, 7787U,
2114 7531U, 428U, 7172U, 6385U, 6344U, 1582U, 2743U, 151U,
2115 2267U, 6308U, 2066U, 6278U, 5929U, 6361U, 2143U, 6293U,
2116 7070U, 8073U, 5343U, 3772U, 5364U, 3791U, 5530U, 3943U,
2117 5426U, 3847U, 5452U, 3871U, 5610U, 4017U, 5504U, 3919U,
2118 5585U, 3994U, 5478U, 3895U, 5406U, 3829U, 5300U, 3733U,
2119 5322U, 3753U, 5559U, 3970U, 5385U, 3810U, 4700U, 1234U,
2120 681U, 1156U, 7898U, 7377U, 7266U, 7113U, 7201U, 7877U,
2121 7356U, 244U, 7955U, 7457U, 338U, 7860U, 7339U, 225U,
2122 7929U, 7431U, 308U, 7612U, 507U, 2117U, 2272U, 627U,
2123 6313U, 605U, 6283U, 6164U, 646U, 6366U, 6198U, 616U,
2124 6298U, 2062U, 5925U, 7973U, 7492U, 379U, 569U, 2139U,
2125 6144U, 6235U, 2937U, 6679U, 4079U, 1718U, 4900U, 2106U,
2126 1464U, 2841U, 3309U, 1272U, 2856U, 3324U, 1288U, 2957U,
2127 6699U, 2532U, 2549U, 1394U, 7542U, 441U, 7830U, 7250U,
2128 7815U, 7235U, 7756U, 7098U, 7800U, 7186U, 7846U, 7293U,
2129 2729U, 135U, 6343U,
2130};
2131
2132static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2133 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 635);
2134}
2135
2136} // end namespace llvm
2137#endif // GET_INSTRINFO_MC_DESC
2138
2139#ifdef GET_INSTRINFO_HEADER
2140#undef GET_INSTRINFO_HEADER
2141namespace llvm {
2142struct R600GenInstrInfo : public TargetInstrInfo {
2143 explicit R600GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2144 ~R600GenInstrInfo() override = default;
2145
2146};
2147} // end namespace llvm
2148#endif // GET_INSTRINFO_HEADER
2149
2150#ifdef GET_INSTRINFO_HELPER_DECLS
2151#undef GET_INSTRINFO_HELPER_DECLS
2152
2153
2154#endif // GET_INSTRINFO_HELPER_DECLS
2155
2156#ifdef GET_INSTRINFO_HELPERS
2157#undef GET_INSTRINFO_HELPERS
2158
2159#endif // GET_INSTRINFO_HELPERS
2160
2161#ifdef GET_INSTRINFO_CTOR_DTOR
2162#undef GET_INSTRINFO_CTOR_DTOR
2163namespace llvm {
2164extern const R600InstrTable R600Descs;
2165extern const unsigned R600InstrNameIndices[];
2166extern const char R600InstrNameData[];
2167R600GenInstrInfo::R600GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2168 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2169 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 635);
2170}
2171} // end namespace llvm
2172#endif // GET_INSTRINFO_CTOR_DTOR
2173
2174#ifdef GET_INSTRINFO_OPERAND_ENUM
2175#undef GET_INSTRINFO_OPERAND_ENUM
2176namespace llvm {
2177namespace R600 {
2178namespace OpName {
2179enum {
2180 ADDR = 98,
2181 COUNT = 105,
2182 Enabled = 106,
2183 KCACHE_ADDR0 = 103,
2184 KCACHE_ADDR1 = 104,
2185 KCACHE_BANK0 = 99,
2186 KCACHE_BANK1 = 100,
2187 KCACHE_MODE0 = 101,
2188 KCACHE_MODE1 = 102,
2189 addr = 72,
2190 bank_swizzle = 93,
2191 chan = 73,
2192 clamp = 80,
2193 clamp_W = 58,
2194 clamp_X = 7,
2195 clamp_Y = 24,
2196 clamp_Z = 41,
2197 dst = 0,
2198 dst_rel = 79,
2199 dst_rel_W = 57,
2200 dst_rel_X = 6,
2201 dst_rel_Y = 23,
2202 dst_rel_Z = 40,
2203 last = 90,
2204 literal = 92,
2205 literal0 = 70,
2206 literal1 = 71,
2207 omod = 78,
2208 omod_W = 56,
2209 omod_X = 5,
2210 omod_Y = 22,
2211 omod_Z = 39,
2212 pred_sel = 91,
2213 pred_sel_W = 69,
2214 pred_sel_X = 18,
2215 pred_sel_Y = 35,
2216 pred_sel_Z = 52,
2217 src0 = 1,
2218 src0_W = 59,
2219 src0_X = 8,
2220 src0_Y = 25,
2221 src0_Z = 42,
2222 src0_abs = 83,
2223 src0_abs_W = 62,
2224 src0_abs_X = 11,
2225 src0_abs_Y = 28,
2226 src0_abs_Z = 45,
2227 src0_neg = 81,
2228 src0_neg_W = 60,
2229 src0_neg_X = 9,
2230 src0_neg_Y = 26,
2231 src0_neg_Z = 43,
2232 src0_rel = 82,
2233 src0_rel_W = 61,
2234 src0_rel_X = 10,
2235 src0_rel_Y = 27,
2236 src0_rel_Z = 44,
2237 src0_sel = 84,
2238 src0_sel_W = 63,
2239 src0_sel_X = 12,
2240 src0_sel_Y = 29,
2241 src0_sel_Z = 46,
2242 src1 = 85,
2243 src1_W = 64,
2244 src1_X = 13,
2245 src1_Y = 30,
2246 src1_Z = 47,
2247 src1_abs = 88,
2248 src1_abs_W = 67,
2249 src1_abs_X = 16,
2250 src1_abs_Y = 33,
2251 src1_abs_Z = 50,
2252 src1_neg = 86,
2253 src1_neg_W = 65,
2254 src1_neg_X = 14,
2255 src1_neg_Y = 31,
2256 src1_neg_Z = 48,
2257 src1_rel = 87,
2258 src1_rel_W = 66,
2259 src1_rel_X = 15,
2260 src1_rel_Y = 32,
2261 src1_rel_Z = 49,
2262 src1_sel = 89,
2263 src1_sel_W = 68,
2264 src1_sel_X = 17,
2265 src1_sel_Y = 34,
2266 src1_sel_Z = 51,
2267 src2 = 94,
2268 src2_neg = 95,
2269 src2_rel = 96,
2270 src2_sel = 97,
2271 update_exec_mask = 75,
2272 update_exec_mask_W = 53,
2273 update_exec_mask_X = 2,
2274 update_exec_mask_Y = 19,
2275 update_exec_mask_Z = 36,
2276 update_pred = 76,
2277 update_pred_W = 54,
2278 update_pred_X = 3,
2279 update_pred_Y = 20,
2280 update_pred_Z = 37,
2281 val = 74,
2282 write = 77,
2283 write_W = 55,
2284 write_X = 4,
2285 write_Y = 21,
2286 write_Z = 38,
2287 OPERAND_LAST
2288};
2289} // end namespace OpName
2290} // end namespace R600
2291} // end namespace llvm
2292#endif //GET_INSTRINFO_OPERAND_ENUM
2293
2294#ifdef GET_INSTRINFO_NAMED_OPS
2295#undef GET_INSTRINFO_NAMED_OPS
2296namespace llvm {
2297namespace R600 {
2298LLVM_READONLY
2299int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
2300 static const int16_t OperandMap [][107] = {
2301{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2302{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2303{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2304{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2305{0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2306{0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2307{0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2308{0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2309{0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2310{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2311{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2312{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2313{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2314};
2315 switch(Opcode) {
2316 case R600::CUBE_eg_pseudo:
2317 case R600::CUBE_r600_pseudo:
2318 return OperandMap[0][NamedIdx];
2319 case R600::LDS_ADD_RET:
2320 case R600::LDS_AND_RET:
2321 case R600::LDS_MAX_INT_RET:
2322 case R600::LDS_MAX_UINT_RET:
2323 case R600::LDS_MIN_INT_RET:
2324 case R600::LDS_MIN_UINT_RET:
2325 case R600::LDS_OR_RET:
2326 case R600::LDS_SUB_RET:
2327 case R600::LDS_WRXCHG_RET:
2328 case R600::LDS_XOR_RET:
2329 return OperandMap[1][NamedIdx];
2330 case R600::LDS_CMPST_RET:
2331 return OperandMap[2][NamedIdx];
2332 case R600::LDS_BYTE_READ_RET:
2333 case R600::LDS_READ_RET:
2334 case R600::LDS_SHORT_READ_RET:
2335 case R600::LDS_UBYTE_READ_RET:
2336 case R600::LDS_USHORT_READ_RET:
2337 return OperandMap[3][NamedIdx];
2338 case R600::BFE_INT_eg:
2339 case R600::BFE_UINT_eg:
2340 case R600::BFI_INT_eg:
2341 case R600::BIT_ALIGN_INT_eg:
2342 case R600::CNDE_INT:
2343 case R600::CNDE_eg:
2344 case R600::CNDE_r600:
2345 case R600::CNDGE_INT:
2346 case R600::CNDGE_eg:
2347 case R600::CNDGE_r600:
2348 case R600::CNDGT_INT:
2349 case R600::CNDGT_eg:
2350 case R600::CNDGT_r600:
2351 case R600::FMA_eg:
2352 case R600::MULADD_IEEE_eg:
2353 case R600::MULADD_IEEE_r600:
2354 case R600::MULADD_INT24_cm:
2355 case R600::MULADD_UINT24_eg:
2356 case R600::MULADD_eg:
2357 case R600::MULADD_r600:
2358 case R600::MUL_LIT_eg:
2359 case R600::MUL_LIT_r600:
2360 return OperandMap[4][NamedIdx];
2361 case R600::BCNT_INT:
2362 case R600::CEIL:
2363 case R600::COS_cm:
2364 case R600::COS_eg:
2365 case R600::COS_r600:
2366 case R600::COS_r700:
2367 case R600::EXP_IEEE_cm:
2368 case R600::EXP_IEEE_eg:
2369 case R600::EXP_IEEE_r600:
2370 case R600::FFBH_UINT:
2371 case R600::FFBL_INT:
2372 case R600::FLOOR:
2373 case R600::FLT16_TO_FLT32:
2374 case R600::FLT32_TO_FLT16:
2375 case R600::FLT_TO_INT_eg:
2376 case R600::FLT_TO_INT_r600:
2377 case R600::FLT_TO_UINT_eg:
2378 case R600::FLT_TO_UINT_r600:
2379 case R600::FRACT:
2380 case R600::INTERP_LOAD_P0:
2381 case R600::INT_TO_FLT_eg:
2382 case R600::INT_TO_FLT_r600:
2383 case R600::LOG_CLAMPED_eg:
2384 case R600::LOG_CLAMPED_r600:
2385 case R600::LOG_IEEE_cm:
2386 case R600::LOG_IEEE_eg:
2387 case R600::LOG_IEEE_r600:
2388 case R600::MOV:
2389 case R600::MOVA_INT_eg:
2390 case R600::NOT_INT:
2391 case R600::RECIPSQRT_CLAMPED_cm:
2392 case R600::RECIPSQRT_CLAMPED_eg:
2393 case R600::RECIPSQRT_CLAMPED_r600:
2394 case R600::RECIPSQRT_IEEE_cm:
2395 case R600::RECIPSQRT_IEEE_eg:
2396 case R600::RECIPSQRT_IEEE_r600:
2397 case R600::RECIP_CLAMPED_cm:
2398 case R600::RECIP_CLAMPED_eg:
2399 case R600::RECIP_CLAMPED_r600:
2400 case R600::RECIP_IEEE_cm:
2401 case R600::RECIP_IEEE_eg:
2402 case R600::RECIP_IEEE_r600:
2403 case R600::RECIP_UINT_eg:
2404 case R600::RECIP_UINT_r600:
2405 case R600::RNDNE:
2406 case R600::SIN_cm:
2407 case R600::SIN_eg:
2408 case R600::SIN_r600:
2409 case R600::SIN_r700:
2410 case R600::TRUNC:
2411 case R600::UINT_TO_FLT_eg:
2412 case R600::UINT_TO_FLT_r600:
2413 return OperandMap[5][NamedIdx];
2414 case R600::ADD:
2415 case R600::ADDC_UINT:
2416 case R600::ADD_INT:
2417 case R600::AND_INT:
2418 case R600::ASHR_eg:
2419 case R600::ASHR_r600:
2420 case R600::BFM_INT_eg:
2421 case R600::CUBE_eg_real:
2422 case R600::CUBE_r600_real:
2423 case R600::DOT4_eg:
2424 case R600::DOT4_r600:
2425 case R600::INTERP_XY:
2426 case R600::INTERP_ZW:
2427 case R600::KILLGT:
2428 case R600::LSHL_eg:
2429 case R600::LSHL_r600:
2430 case R600::LSHR_eg:
2431 case R600::LSHR_r600:
2432 case R600::MAX:
2433 case R600::MAX_DX10:
2434 case R600::MAX_INT:
2435 case R600::MAX_UINT:
2436 case R600::MIN:
2437 case R600::MIN_DX10:
2438 case R600::MIN_INT:
2439 case R600::MIN_UINT:
2440 case R600::MUL:
2441 case R600::MULHI_INT_cm:
2442 case R600::MULHI_INT_cm24:
2443 case R600::MULHI_INT_eg:
2444 case R600::MULHI_INT_r600:
2445 case R600::MULHI_UINT24_eg:
2446 case R600::MULHI_UINT_cm:
2447 case R600::MULHI_UINT_cm24:
2448 case R600::MULHI_UINT_eg:
2449 case R600::MULHI_UINT_r600:
2450 case R600::MULLO_INT_cm:
2451 case R600::MULLO_INT_eg:
2452 case R600::MULLO_INT_r600:
2453 case R600::MULLO_UINT_cm:
2454 case R600::MULLO_UINT_eg:
2455 case R600::MULLO_UINT_r600:
2456 case R600::MUL_IEEE:
2457 case R600::MUL_INT24_cm:
2458 case R600::MUL_UINT24_eg:
2459 case R600::OR_INT:
2460 case R600::PRED_SETE:
2461 case R600::PRED_SETE_INT:
2462 case R600::PRED_SETGE:
2463 case R600::PRED_SETGE_INT:
2464 case R600::PRED_SETGT:
2465 case R600::PRED_SETGT_INT:
2466 case R600::PRED_SETNE:
2467 case R600::PRED_SETNE_INT:
2468 case R600::SETE:
2469 case R600::SETE_DX10:
2470 case R600::SETE_INT:
2471 case R600::SETGE_DX10:
2472 case R600::SETGE_INT:
2473 case R600::SETGE_UINT:
2474 case R600::SETGT_DX10:
2475 case R600::SETGT_INT:
2476 case R600::SETGT_UINT:
2477 case R600::SETNE_DX10:
2478 case R600::SETNE_INT:
2479 case R600::SGE:
2480 case R600::SGT:
2481 case R600::SNE:
2482 case R600::SUBB_UINT:
2483 case R600::SUB_INT:
2484 case R600::XOR_INT:
2485 return OperandMap[6][NamedIdx];
2486 case R600::DOT_4:
2487 return OperandMap[7][NamedIdx];
2488 case R600::R600_RegisterLoad:
2489 return OperandMap[8][NamedIdx];
2490 case R600::LDS_ADD:
2491 case R600::LDS_AND:
2492 case R600::LDS_BYTE_WRITE:
2493 case R600::LDS_MAX_INT:
2494 case R600::LDS_MAX_UINT:
2495 case R600::LDS_MIN_INT:
2496 case R600::LDS_MIN_UINT:
2497 case R600::LDS_OR:
2498 case R600::LDS_SHORT_WRITE:
2499 case R600::LDS_SUB:
2500 case R600::LDS_WRITE:
2501 case R600::LDS_WRXCHG:
2502 case R600::LDS_XOR:
2503 return OperandMap[9][NamedIdx];
2504 case R600::LDS_CMPST:
2505 return OperandMap[10][NamedIdx];
2506 case R600::R600_RegisterStore:
2507 return OperandMap[11][NamedIdx];
2508 case R600::CF_ALU:
2509 case R600::CF_ALU_BREAK:
2510 case R600::CF_ALU_CONTINUE:
2511 case R600::CF_ALU_ELSE_AFTER:
2512 case R600::CF_ALU_POP_AFTER:
2513 case R600::CF_ALU_PUSH_BEFORE:
2514 return OperandMap[12][NamedIdx];
2515 default: return -1;
2516 }
2517}
2518} // end namespace R600
2519} // end namespace llvm
2520#endif //GET_INSTRINFO_NAMED_OPS
2521
2522#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
2523#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
2524namespace llvm {
2525namespace R600 {
2526namespace OpTypes {
2527enum OperandType {
2528 ABS = 0,
2529 BANK_SWIZZLE = 1,
2530 CLAMP = 2,
2531 CT = 3,
2532 FRAMEri = 4,
2533 InstFlag = 5,
2534 KCACHE = 6,
2535 LAST = 7,
2536 LITERAL = 8,
2537 MEMrr = 9,
2538 MEMxi = 10,
2539 NEG = 11,
2540 OMOD = 12,
2541 R600_Pred = 13,
2542 REL = 14,
2543 RSel = 15,
2544 SEL = 16,
2545 UEM = 17,
2546 UP = 18,
2547 WRITE = 19,
2548 brtarget = 20,
2549 f32imm = 21,
2550 f64imm = 22,
2551 i1imm = 23,
2552 i1imm_0 = 24,
2553 i8imm = 25,
2554 i16imm = 26,
2555 i32imm = 27,
2556 i64imm = 28,
2557 ptype0 = 29,
2558 ptype1 = 30,
2559 ptype2 = 31,
2560 ptype3 = 32,
2561 ptype4 = 33,
2562 ptype5 = 34,
2563 s16imm = 35,
2564 type0 = 36,
2565 type1 = 37,
2566 type2 = 38,
2567 type3 = 39,
2568 type4 = 40,
2569 type5 = 41,
2570 u16imm = 42,
2571 untyped_imm_0 = 43,
2572 R600_Addr = 44,
2573 R600_Addr_W = 45,
2574 R600_Addr_Y = 46,
2575 R600_Addr_Z = 47,
2576 R600_ArrayBase = 48,
2577 R600_KC0 = 49,
2578 R600_KC0_W = 50,
2579 R600_KC0_X = 51,
2580 R600_KC0_Y = 52,
2581 R600_KC0_Z = 53,
2582 R600_KC1 = 54,
2583 R600_KC1_W = 55,
2584 R600_KC1_X = 56,
2585 R600_KC1_Y = 57,
2586 R600_KC1_Z = 58,
2587 R600_LDS_SRC_REG = 59,
2588 R600_Predicate = 60,
2589 R600_Predicate_Bit = 61,
2590 R600_Reg32 = 62,
2591 R600_Reg64 = 63,
2592 R600_Reg64Vertical = 64,
2593 R600_Reg128 = 65,
2594 R600_Reg128Vertical = 66,
2595 R600_TReg32 = 67,
2596 R600_TReg32_W = 68,
2597 R600_TReg32_X = 69,
2598 R600_TReg32_Y = 70,
2599 R600_TReg32_Z = 71,
2600 OPERAND_TYPE_LIST_END
2601};
2602} // end namespace OpTypes
2603} // end namespace R600
2604} // end namespace llvm
2605#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2606
2607#ifdef GET_INSTRINFO_OPERAND_TYPE
2608#undef GET_INSTRINFO_OPERAND_TYPE
2609namespace llvm {
2610namespace R600 {
2611LLVM_READONLY
2612static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
2613 static const uint16_t Offsets[] = {
2614 /* PHI */
2615 0,
2616 /* INLINEASM */
2617 1,
2618 /* INLINEASM_BR */
2619 1,
2620 /* CFI_INSTRUCTION */
2621 1,
2622 /* EH_LABEL */
2623 2,
2624 /* GC_LABEL */
2625 3,
2626 /* ANNOTATION_LABEL */
2627 4,
2628 /* KILL */
2629 5,
2630 /* EXTRACT_SUBREG */
2631 5,
2632 /* INSERT_SUBREG */
2633 8,
2634 /* IMPLICIT_DEF */
2635 12,
2636 /* SUBREG_TO_REG */
2637 13,
2638 /* COPY_TO_REGCLASS */
2639 17,
2640 /* DBG_VALUE */
2641 20,
2642 /* DBG_VALUE_LIST */
2643 20,
2644 /* DBG_INSTR_REF */
2645 20,
2646 /* DBG_PHI */
2647 20,
2648 /* DBG_LABEL */
2649 20,
2650 /* REG_SEQUENCE */
2651 21,
2652 /* COPY */
2653 23,
2654 /* BUNDLE */
2655 25,
2656 /* LIFETIME_START */
2657 25,
2658 /* LIFETIME_END */
2659 26,
2660 /* PSEUDO_PROBE */
2661 27,
2662 /* ARITH_FENCE */
2663 31,
2664 /* STACKMAP */
2665 33,
2666 /* FENTRY_CALL */
2667 35,
2668 /* PATCHPOINT */
2669 35,
2670 /* LOAD_STACK_GUARD */
2671 41,
2672 /* PREALLOCATED_SETUP */
2673 42,
2674 /* PREALLOCATED_ARG */
2675 43,
2676 /* STATEPOINT */
2677 46,
2678 /* LOCAL_ESCAPE */
2679 46,
2680 /* FAULTING_OP */
2681 48,
2682 /* PATCHABLE_OP */
2683 49,
2684 /* PATCHABLE_FUNCTION_ENTER */
2685 49,
2686 /* PATCHABLE_RET */
2687 49,
2688 /* PATCHABLE_FUNCTION_EXIT */
2689 49,
2690 /* PATCHABLE_TAIL_CALL */
2691 49,
2692 /* PATCHABLE_EVENT_CALL */
2693 49,
2694 /* PATCHABLE_TYPED_EVENT_CALL */
2695 51,
2696 /* ICALL_BRANCH_FUNNEL */
2697 54,
2698 /* MEMBARRIER */
2699 54,
2700 /* JUMP_TABLE_DEBUG_INFO */
2701 54,
2702 /* CONVERGENCECTRL_ENTRY */
2703 55,
2704 /* CONVERGENCECTRL_ANCHOR */
2705 56,
2706 /* CONVERGENCECTRL_LOOP */
2707 57,
2708 /* CONVERGENCECTRL_GLUE */
2709 59,
2710 /* G_ASSERT_SEXT */
2711 60,
2712 /* G_ASSERT_ZEXT */
2713 63,
2714 /* G_ASSERT_ALIGN */
2715 66,
2716 /* G_ADD */
2717 69,
2718 /* G_SUB */
2719 72,
2720 /* G_MUL */
2721 75,
2722 /* G_SDIV */
2723 78,
2724 /* G_UDIV */
2725 81,
2726 /* G_SREM */
2727 84,
2728 /* G_UREM */
2729 87,
2730 /* G_SDIVREM */
2731 90,
2732 /* G_UDIVREM */
2733 94,
2734 /* G_AND */
2735 98,
2736 /* G_OR */
2737 101,
2738 /* G_XOR */
2739 104,
2740 /* G_IMPLICIT_DEF */
2741 107,
2742 /* G_PHI */
2743 108,
2744 /* G_FRAME_INDEX */
2745 109,
2746 /* G_GLOBAL_VALUE */
2747 111,
2748 /* G_PTRAUTH_GLOBAL_VALUE */
2749 113,
2750 /* G_CONSTANT_POOL */
2751 118,
2752 /* G_EXTRACT */
2753 120,
2754 /* G_UNMERGE_VALUES */
2755 123,
2756 /* G_INSERT */
2757 125,
2758 /* G_MERGE_VALUES */
2759 129,
2760 /* G_BUILD_VECTOR */
2761 131,
2762 /* G_BUILD_VECTOR_TRUNC */
2763 133,
2764 /* G_CONCAT_VECTORS */
2765 135,
2766 /* G_PTRTOINT */
2767 137,
2768 /* G_INTTOPTR */
2769 139,
2770 /* G_BITCAST */
2771 141,
2772 /* G_FREEZE */
2773 143,
2774 /* G_CONSTANT_FOLD_BARRIER */
2775 145,
2776 /* G_INTRINSIC_FPTRUNC_ROUND */
2777 147,
2778 /* G_INTRINSIC_TRUNC */
2779 150,
2780 /* G_INTRINSIC_ROUND */
2781 152,
2782 /* G_INTRINSIC_LRINT */
2783 154,
2784 /* G_INTRINSIC_LLRINT */
2785 156,
2786 /* G_INTRINSIC_ROUNDEVEN */
2787 158,
2788 /* G_READCYCLECOUNTER */
2789 160,
2790 /* G_READSTEADYCOUNTER */
2791 161,
2792 /* G_LOAD */
2793 162,
2794 /* G_SEXTLOAD */
2795 164,
2796 /* G_ZEXTLOAD */
2797 166,
2798 /* G_INDEXED_LOAD */
2799 168,
2800 /* G_INDEXED_SEXTLOAD */
2801 173,
2802 /* G_INDEXED_ZEXTLOAD */
2803 178,
2804 /* G_STORE */
2805 183,
2806 /* G_INDEXED_STORE */
2807 185,
2808 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2809 190,
2810 /* G_ATOMIC_CMPXCHG */
2811 195,
2812 /* G_ATOMICRMW_XCHG */
2813 199,
2814 /* G_ATOMICRMW_ADD */
2815 202,
2816 /* G_ATOMICRMW_SUB */
2817 205,
2818 /* G_ATOMICRMW_AND */
2819 208,
2820 /* G_ATOMICRMW_NAND */
2821 211,
2822 /* G_ATOMICRMW_OR */
2823 214,
2824 /* G_ATOMICRMW_XOR */
2825 217,
2826 /* G_ATOMICRMW_MAX */
2827 220,
2828 /* G_ATOMICRMW_MIN */
2829 223,
2830 /* G_ATOMICRMW_UMAX */
2831 226,
2832 /* G_ATOMICRMW_UMIN */
2833 229,
2834 /* G_ATOMICRMW_FADD */
2835 232,
2836 /* G_ATOMICRMW_FSUB */
2837 235,
2838 /* G_ATOMICRMW_FMAX */
2839 238,
2840 /* G_ATOMICRMW_FMIN */
2841 241,
2842 /* G_ATOMICRMW_UINC_WRAP */
2843 244,
2844 /* G_ATOMICRMW_UDEC_WRAP */
2845 247,
2846 /* G_FENCE */
2847 250,
2848 /* G_PREFETCH */
2849 252,
2850 /* G_BRCOND */
2851 256,
2852 /* G_BRINDIRECT */
2853 258,
2854 /* G_INVOKE_REGION_START */
2855 259,
2856 /* G_INTRINSIC */
2857 259,
2858 /* G_INTRINSIC_W_SIDE_EFFECTS */
2859 260,
2860 /* G_INTRINSIC_CONVERGENT */
2861 261,
2862 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2863 262,
2864 /* G_ANYEXT */
2865 263,
2866 /* G_TRUNC */
2867 265,
2868 /* G_CONSTANT */
2869 267,
2870 /* G_FCONSTANT */
2871 269,
2872 /* G_VASTART */
2873 271,
2874 /* G_VAARG */
2875 272,
2876 /* G_SEXT */
2877 275,
2878 /* G_SEXT_INREG */
2879 277,
2880 /* G_ZEXT */
2881 280,
2882 /* G_SHL */
2883 282,
2884 /* G_LSHR */
2885 285,
2886 /* G_ASHR */
2887 288,
2888 /* G_FSHL */
2889 291,
2890 /* G_FSHR */
2891 295,
2892 /* G_ROTR */
2893 299,
2894 /* G_ROTL */
2895 302,
2896 /* G_ICMP */
2897 305,
2898 /* G_FCMP */
2899 309,
2900 /* G_SCMP */
2901 313,
2902 /* G_UCMP */
2903 316,
2904 /* G_SELECT */
2905 319,
2906 /* G_UADDO */
2907 323,
2908 /* G_UADDE */
2909 327,
2910 /* G_USUBO */
2911 332,
2912 /* G_USUBE */
2913 336,
2914 /* G_SADDO */
2915 341,
2916 /* G_SADDE */
2917 345,
2918 /* G_SSUBO */
2919 350,
2920 /* G_SSUBE */
2921 354,
2922 /* G_UMULO */
2923 359,
2924 /* G_SMULO */
2925 363,
2926 /* G_UMULH */
2927 367,
2928 /* G_SMULH */
2929 370,
2930 /* G_UADDSAT */
2931 373,
2932 /* G_SADDSAT */
2933 376,
2934 /* G_USUBSAT */
2935 379,
2936 /* G_SSUBSAT */
2937 382,
2938 /* G_USHLSAT */
2939 385,
2940 /* G_SSHLSAT */
2941 388,
2942 /* G_SMULFIX */
2943 391,
2944 /* G_UMULFIX */
2945 395,
2946 /* G_SMULFIXSAT */
2947 399,
2948 /* G_UMULFIXSAT */
2949 403,
2950 /* G_SDIVFIX */
2951 407,
2952 /* G_UDIVFIX */
2953 411,
2954 /* G_SDIVFIXSAT */
2955 415,
2956 /* G_UDIVFIXSAT */
2957 419,
2958 /* G_FADD */
2959 423,
2960 /* G_FSUB */
2961 426,
2962 /* G_FMUL */
2963 429,
2964 /* G_FMA */
2965 432,
2966 /* G_FMAD */
2967 436,
2968 /* G_FDIV */
2969 440,
2970 /* G_FREM */
2971 443,
2972 /* G_FPOW */
2973 446,
2974 /* G_FPOWI */
2975 449,
2976 /* G_FEXP */
2977 452,
2978 /* G_FEXP2 */
2979 454,
2980 /* G_FEXP10 */
2981 456,
2982 /* G_FLOG */
2983 458,
2984 /* G_FLOG2 */
2985 460,
2986 /* G_FLOG10 */
2987 462,
2988 /* G_FLDEXP */
2989 464,
2990 /* G_FFREXP */
2991 467,
2992 /* G_FNEG */
2993 470,
2994 /* G_FPEXT */
2995 472,
2996 /* G_FPTRUNC */
2997 474,
2998 /* G_FPTOSI */
2999 476,
3000 /* G_FPTOUI */
3001 478,
3002 /* G_SITOFP */
3003 480,
3004 /* G_UITOFP */
3005 482,
3006 /* G_FABS */
3007 484,
3008 /* G_FCOPYSIGN */
3009 486,
3010 /* G_IS_FPCLASS */
3011 489,
3012 /* G_FCANONICALIZE */
3013 492,
3014 /* G_FMINNUM */
3015 494,
3016 /* G_FMAXNUM */
3017 497,
3018 /* G_FMINNUM_IEEE */
3019 500,
3020 /* G_FMAXNUM_IEEE */
3021 503,
3022 /* G_FMINIMUM */
3023 506,
3024 /* G_FMAXIMUM */
3025 509,
3026 /* G_GET_FPENV */
3027 512,
3028 /* G_SET_FPENV */
3029 513,
3030 /* G_RESET_FPENV */
3031 514,
3032 /* G_GET_FPMODE */
3033 514,
3034 /* G_SET_FPMODE */
3035 515,
3036 /* G_RESET_FPMODE */
3037 516,
3038 /* G_PTR_ADD */
3039 516,
3040 /* G_PTRMASK */
3041 519,
3042 /* G_SMIN */
3043 522,
3044 /* G_SMAX */
3045 525,
3046 /* G_UMIN */
3047 528,
3048 /* G_UMAX */
3049 531,
3050 /* G_ABS */
3051 534,
3052 /* G_LROUND */
3053 536,
3054 /* G_LLROUND */
3055 538,
3056 /* G_BR */
3057 540,
3058 /* G_BRJT */
3059 541,
3060 /* G_VSCALE */
3061 544,
3062 /* G_INSERT_SUBVECTOR */
3063 546,
3064 /* G_EXTRACT_SUBVECTOR */
3065 550,
3066 /* G_INSERT_VECTOR_ELT */
3067 553,
3068 /* G_EXTRACT_VECTOR_ELT */
3069 557,
3070 /* G_SHUFFLE_VECTOR */
3071 560,
3072 /* G_SPLAT_VECTOR */
3073 564,
3074 /* G_VECTOR_COMPRESS */
3075 566,
3076 /* G_CTTZ */
3077 570,
3078 /* G_CTTZ_ZERO_UNDEF */
3079 572,
3080 /* G_CTLZ */
3081 574,
3082 /* G_CTLZ_ZERO_UNDEF */
3083 576,
3084 /* G_CTPOP */
3085 578,
3086 /* G_BSWAP */
3087 580,
3088 /* G_BITREVERSE */
3089 582,
3090 /* G_FCEIL */
3091 584,
3092 /* G_FCOS */
3093 586,
3094 /* G_FSIN */
3095 588,
3096 /* G_FTAN */
3097 590,
3098 /* G_FACOS */
3099 592,
3100 /* G_FASIN */
3101 594,
3102 /* G_FATAN */
3103 596,
3104 /* G_FCOSH */
3105 598,
3106 /* G_FSINH */
3107 600,
3108 /* G_FTANH */
3109 602,
3110 /* G_FSQRT */
3111 604,
3112 /* G_FFLOOR */
3113 606,
3114 /* G_FRINT */
3115 608,
3116 /* G_FNEARBYINT */
3117 610,
3118 /* G_ADDRSPACE_CAST */
3119 612,
3120 /* G_BLOCK_ADDR */
3121 614,
3122 /* G_JUMP_TABLE */
3123 616,
3124 /* G_DYN_STACKALLOC */
3125 618,
3126 /* G_STACKSAVE */
3127 621,
3128 /* G_STACKRESTORE */
3129 622,
3130 /* G_STRICT_FADD */
3131 623,
3132 /* G_STRICT_FSUB */
3133 626,
3134 /* G_STRICT_FMUL */
3135 629,
3136 /* G_STRICT_FDIV */
3137 632,
3138 /* G_STRICT_FREM */
3139 635,
3140 /* G_STRICT_FMA */
3141 638,
3142 /* G_STRICT_FSQRT */
3143 642,
3144 /* G_STRICT_FLDEXP */
3145 644,
3146 /* G_READ_REGISTER */
3147 647,
3148 /* G_WRITE_REGISTER */
3149 649,
3150 /* G_MEMCPY */
3151 651,
3152 /* G_MEMCPY_INLINE */
3153 655,
3154 /* G_MEMMOVE */
3155 658,
3156 /* G_MEMSET */
3157 662,
3158 /* G_BZERO */
3159 666,
3160 /* G_TRAP */
3161 669,
3162 /* G_DEBUGTRAP */
3163 669,
3164 /* G_UBSANTRAP */
3165 669,
3166 /* G_VECREDUCE_SEQ_FADD */
3167 670,
3168 /* G_VECREDUCE_SEQ_FMUL */
3169 673,
3170 /* G_VECREDUCE_FADD */
3171 676,
3172 /* G_VECREDUCE_FMUL */
3173 678,
3174 /* G_VECREDUCE_FMAX */
3175 680,
3176 /* G_VECREDUCE_FMIN */
3177 682,
3178 /* G_VECREDUCE_FMAXIMUM */
3179 684,
3180 /* G_VECREDUCE_FMINIMUM */
3181 686,
3182 /* G_VECREDUCE_ADD */
3183 688,
3184 /* G_VECREDUCE_MUL */
3185 690,
3186 /* G_VECREDUCE_AND */
3187 692,
3188 /* G_VECREDUCE_OR */
3189 694,
3190 /* G_VECREDUCE_XOR */
3191 696,
3192 /* G_VECREDUCE_SMAX */
3193 698,
3194 /* G_VECREDUCE_SMIN */
3195 700,
3196 /* G_VECREDUCE_UMAX */
3197 702,
3198 /* G_VECREDUCE_UMIN */
3199 704,
3200 /* G_SBFX */
3201 706,
3202 /* G_UBFX */
3203 710,
3204 /* BRANCH */
3205 714,
3206 /* BRANCH_COND_f32 */
3207 715,
3208 /* BRANCH_COND_i32 */
3209 717,
3210 /* BREAK */
3211 719,
3212 /* BREAKC_f32 */
3213 719,
3214 /* BREAKC_i32 */
3215 721,
3216 /* BREAK_LOGICALNZ_f32 */
3217 723,
3218 /* BREAK_LOGICALNZ_i32 */
3219 724,
3220 /* BREAK_LOGICALZ_f32 */
3221 725,
3222 /* BREAK_LOGICALZ_i32 */
3223 726,
3224 /* CONST_COPY */
3225 727,
3226 /* CONTINUE */
3227 729,
3228 /* CONTINUEC_f32 */
3229 729,
3230 /* CONTINUEC_i32 */
3231 731,
3232 /* CONTINUE_LOGICALNZ_f32 */
3233 733,
3234 /* CONTINUE_LOGICALNZ_i32 */
3235 734,
3236 /* CONTINUE_LOGICALZ_f32 */
3237 735,
3238 /* CONTINUE_LOGICALZ_i32 */
3239 736,
3240 /* CUBE_eg_pseudo */
3241 737,
3242 /* CUBE_r600_pseudo */
3243 739,
3244 /* DEFAULT */
3245 741,
3246 /* DOT_4 */
3247 741,
3248 /* DUMMY_CHAIN */
3249 812,
3250 /* ELSE */
3251 812,
3252 /* END */
3253 812,
3254 /* ENDFUNC */
3255 812,
3256 /* ENDIF */
3257 812,
3258 /* ENDLOOP */
3259 812,
3260 /* ENDMAIN */
3261 812,
3262 /* ENDSWITCH */
3263 812,
3264 /* FABS_R600 */
3265 812,
3266 /* FNEG_R600 */
3267 814,
3268 /* FUNC */
3269 816,
3270 /* IFC_f32 */
3271 816,
3272 /* IFC_i32 */
3273 818,
3274 /* IF_LOGICALNZ_f32 */
3275 820,
3276 /* IF_LOGICALNZ_i32 */
3277 821,
3278 /* IF_LOGICALZ_f32 */
3279 822,
3280 /* IF_LOGICALZ_i32 */
3281 823,
3282 /* IF_PREDICATE_SET */
3283 824,
3284 /* JUMP */
3285 825,
3286 /* JUMP_COND */
3287 826,
3288 /* MASK_WRITE */
3289 828,
3290 /* MOV_IMM_F32 */
3291 829,
3292 /* MOV_IMM_GLOBAL_ADDR */
3293 831,
3294 /* MOV_IMM_I32 */
3295 833,
3296 /* PRED_X */
3297 835,
3298 /* R600_EXTRACT_ELT_V2 */
3299 839,
3300 /* R600_EXTRACT_ELT_V4 */
3301 842,
3302 /* R600_INSERT_ELT_V2 */
3303 845,
3304 /* R600_INSERT_ELT_V4 */
3305 849,
3306 /* R600_RegisterLoad */
3307 853,
3308 /* R600_RegisterStore */
3309 857,
3310 /* RETDYN */
3311 861,
3312 /* RETURN */
3313 861,
3314 /* TXD */
3315 861,
3316 /* TXD_SHADOW */
3317 868,
3318 /* WHILELOOP */
3319 875,
3320 /* ADD */
3321 875,
3322 /* ADDC_UINT */
3323 896,
3324 /* ADD_INT */
3325 917,
3326 /* ALU_CLAUSE */
3327 938,
3328 /* AND_INT */
3329 939,
3330 /* ASHR_eg */
3331 960,
3332 /* ASHR_r600 */
3333 981,
3334 /* BCNT_INT */
3335 1002,
3336 /* BFE_INT_eg */
3337 1016,
3338 /* BFE_UINT_eg */
3339 1035,
3340 /* BFI_INT_eg */
3341 1054,
3342 /* BFM_INT_eg */
3343 1073,
3344 /* BIT_ALIGN_INT_eg */
3345 1094,
3346 /* CEIL */
3347 1113,
3348 /* CF_ALU */
3349 1127,
3350 /* CF_ALU_BREAK */
3351 1136,
3352 /* CF_ALU_CONTINUE */
3353 1145,
3354 /* CF_ALU_ELSE_AFTER */
3355 1154,
3356 /* CF_ALU_POP_AFTER */
3357 1163,
3358 /* CF_ALU_PUSH_BEFORE */
3359 1172,
3360 /* CF_CALL_FS_EG */
3361 1181,
3362 /* CF_CALL_FS_R600 */
3363 1181,
3364 /* CF_CONTINUE_EG */
3365 1181,
3366 /* CF_CONTINUE_R600 */
3367 1182,
3368 /* CF_ELSE_EG */
3369 1183,
3370 /* CF_ELSE_R600 */
3371 1185,
3372 /* CF_END_CM */
3373 1187,
3374 /* CF_END_EG */
3375 1187,
3376 /* CF_END_R600 */
3377 1187,
3378 /* CF_JUMP_EG */
3379 1187,
3380 /* CF_JUMP_R600 */
3381 1189,
3382 /* CF_PUSH_EG */
3383 1191,
3384 /* CF_PUSH_ELSE_R600 */
3385 1193,
3386 /* CF_TC_EG */
3387 1194,
3388 /* CF_TC_R600 */
3389 1196,
3390 /* CF_VC_EG */
3391 1198,
3392 /* CF_VC_R600 */
3393 1200,
3394 /* CNDE_INT */
3395 1202,
3396 /* CNDE_eg */
3397 1221,
3398 /* CNDE_r600 */
3399 1240,
3400 /* CNDGE_INT */
3401 1259,
3402 /* CNDGE_eg */
3403 1278,
3404 /* CNDGE_r600 */
3405 1297,
3406 /* CNDGT_INT */
3407 1316,
3408 /* CNDGT_eg */
3409 1335,
3410 /* CNDGT_r600 */
3411 1354,
3412 /* COS_cm */
3413 1373,
3414 /* COS_eg */
3415 1387,
3416 /* COS_r600 */
3417 1401,
3418 /* COS_r700 */
3419 1415,
3420 /* CUBE_eg_real */
3421 1429,
3422 /* CUBE_r600_real */
3423 1450,
3424 /* DOT4_eg */
3425 1471,
3426 /* DOT4_r600 */
3427 1492,
3428 /* EG_ExportBuf */
3429 1513,
3430 /* EG_ExportSwz */
3431 1520,
3432 /* END_LOOP_EG */
3433 1529,
3434 /* END_LOOP_R600 */
3435 1530,
3436 /* EXP_IEEE_cm */
3437 1531,
3438 /* EXP_IEEE_eg */
3439 1545,
3440 /* EXP_IEEE_r600 */
3441 1559,
3442 /* FETCH_CLAUSE */
3443 1573,
3444 /* FFBH_UINT */
3445 1574,
3446 /* FFBL_INT */
3447 1588,
3448 /* FLOOR */
3449 1602,
3450 /* FLT16_TO_FLT32 */
3451 1616,
3452 /* FLT32_TO_FLT16 */
3453 1630,
3454 /* FLT_TO_INT_eg */
3455 1644,
3456 /* FLT_TO_INT_r600 */
3457 1658,
3458 /* FLT_TO_UINT_eg */
3459 1672,
3460 /* FLT_TO_UINT_r600 */
3461 1686,
3462 /* FMA_eg */
3463 1700,
3464 /* FRACT */
3465 1719,
3466 /* GROUP_BARRIER */
3467 1733,
3468 /* INTERP_LOAD_P0 */
3469 1733,
3470 /* INTERP_PAIR_XY */
3471 1747,
3472 /* INTERP_PAIR_ZW */
3473 1752,
3474 /* INTERP_VEC_LOAD */
3475 1757,
3476 /* INTERP_XY */
3477 1759,
3478 /* INTERP_ZW */
3479 1780,
3480 /* INT_TO_FLT_eg */
3481 1801,
3482 /* INT_TO_FLT_r600 */
3483 1815,
3484 /* KILLGT */
3485 1829,
3486 /* LDS_ADD */
3487 1850,
3488 /* LDS_ADD_RET */
3489 1859,
3490 /* LDS_AND */
3491 1869,
3492 /* LDS_AND_RET */
3493 1878,
3494 /* LDS_BYTE_READ_RET */
3495 1888,
3496 /* LDS_BYTE_WRITE */
3497 1895,
3498 /* LDS_CMPST */
3499 1904,
3500 /* LDS_CMPST_RET */
3501 1916,
3502 /* LDS_MAX_INT */
3503 1929,
3504 /* LDS_MAX_INT_RET */
3505 1938,
3506 /* LDS_MAX_UINT */
3507 1948,
3508 /* LDS_MAX_UINT_RET */
3509 1957,
3510 /* LDS_MIN_INT */
3511 1967,
3512 /* LDS_MIN_INT_RET */
3513 1976,
3514 /* LDS_MIN_UINT */
3515 1986,
3516 /* LDS_MIN_UINT_RET */
3517 1995,
3518 /* LDS_OR */
3519 2005,
3520 /* LDS_OR_RET */
3521 2014,
3522 /* LDS_READ_RET */
3523 2024,
3524 /* LDS_SHORT_READ_RET */
3525 2031,
3526 /* LDS_SHORT_WRITE */
3527 2038,
3528 /* LDS_SUB */
3529 2047,
3530 /* LDS_SUB_RET */
3531 2056,
3532 /* LDS_UBYTE_READ_RET */
3533 2066,
3534 /* LDS_USHORT_READ_RET */
3535 2073,
3536 /* LDS_WRITE */
3537 2080,
3538 /* LDS_WRXCHG */
3539 2089,
3540 /* LDS_WRXCHG_RET */
3541 2098,
3542 /* LDS_XOR */
3543 2108,
3544 /* LDS_XOR_RET */
3545 2117,
3546 /* LITERALS */
3547 2127,
3548 /* LOG_CLAMPED_eg */
3549 2129,
3550 /* LOG_CLAMPED_r600 */
3551 2143,
3552 /* LOG_IEEE_cm */
3553 2157,
3554 /* LOG_IEEE_eg */
3555 2171,
3556 /* LOG_IEEE_r600 */
3557 2185,
3558 /* LOOP_BREAK_EG */
3559 2199,
3560 /* LOOP_BREAK_R600 */
3561 2200,
3562 /* LSHL_eg */
3563 2201,
3564 /* LSHL_r600 */
3565 2222,
3566 /* LSHR_eg */
3567 2243,
3568 /* LSHR_r600 */
3569 2264,
3570 /* MAX */
3571 2285,
3572 /* MAX_DX10 */
3573 2306,
3574 /* MAX_INT */
3575 2327,
3576 /* MAX_UINT */
3577 2348,
3578 /* MIN */
3579 2369,
3580 /* MIN_DX10 */
3581 2390,
3582 /* MIN_INT */
3583 2411,
3584 /* MIN_UINT */
3585 2432,
3586 /* MOV */
3587 2453,
3588 /* MOVA_INT_eg */
3589 2467,
3590 /* MUL */
3591 2481,
3592 /* MULADD_IEEE_eg */
3593 2502,
3594 /* MULADD_IEEE_r600 */
3595 2521,
3596 /* MULADD_INT24_cm */
3597 2540,
3598 /* MULADD_UINT24_eg */
3599 2559,
3600 /* MULADD_eg */
3601 2578,
3602 /* MULADD_r600 */
3603 2597,
3604 /* MULHI_INT_cm */
3605 2616,
3606 /* MULHI_INT_cm24 */
3607 2637,
3608 /* MULHI_INT_eg */
3609 2658,
3610 /* MULHI_INT_r600 */
3611 2679,
3612 /* MULHI_UINT24_eg */
3613 2700,
3614 /* MULHI_UINT_cm */
3615 2721,
3616 /* MULHI_UINT_cm24 */
3617 2742,
3618 /* MULHI_UINT_eg */
3619 2763,
3620 /* MULHI_UINT_r600 */
3621 2784,
3622 /* MULLO_INT_cm */
3623 2805,
3624 /* MULLO_INT_eg */
3625 2826,
3626 /* MULLO_INT_r600 */
3627 2847,
3628 /* MULLO_UINT_cm */
3629 2868,
3630 /* MULLO_UINT_eg */
3631 2889,
3632 /* MULLO_UINT_r600 */
3633 2910,
3634 /* MUL_IEEE */
3635 2931,
3636 /* MUL_INT24_cm */
3637 2952,
3638 /* MUL_LIT_eg */
3639 2973,
3640 /* MUL_LIT_r600 */
3641 2992,
3642 /* MUL_UINT24_eg */
3643 3011,
3644 /* NOT_INT */
3645 3032,
3646 /* OR_INT */
3647 3046,
3648 /* PAD */
3649 3067,
3650 /* POP_EG */
3651 3067,
3652 /* POP_R600 */
3653 3069,
3654 /* PRED_SETE */
3655 3071,
3656 /* PRED_SETE_INT */
3657 3092,
3658 /* PRED_SETGE */
3659 3113,
3660 /* PRED_SETGE_INT */
3661 3134,
3662 /* PRED_SETGT */
3663 3155,
3664 /* PRED_SETGT_INT */
3665 3176,
3666 /* PRED_SETNE */
3667 3197,
3668 /* PRED_SETNE_INT */
3669 3218,
3670 /* R600_ExportBuf */
3671 3239,
3672 /* R600_ExportSwz */
3673 3246,
3674 /* RAT_ATOMIC_ADD_NORET */
3675 3255,
3676 /* RAT_ATOMIC_ADD_RTN */
3677 3258,
3678 /* RAT_ATOMIC_AND_NORET */
3679 3261,
3680 /* RAT_ATOMIC_AND_RTN */
3681 3264,
3682 /* RAT_ATOMIC_CMPXCHG_INT_NORET */
3683 3267,
3684 /* RAT_ATOMIC_CMPXCHG_INT_RTN */
3685 3270,
3686 /* RAT_ATOMIC_DEC_UINT_NORET */
3687 3273,
3688 /* RAT_ATOMIC_DEC_UINT_RTN */
3689 3276,
3690 /* RAT_ATOMIC_INC_UINT_NORET */
3691 3279,
3692 /* RAT_ATOMIC_INC_UINT_RTN */
3693 3282,
3694 /* RAT_ATOMIC_MAX_INT_NORET */
3695 3285,
3696 /* RAT_ATOMIC_MAX_INT_RTN */
3697 3288,
3698 /* RAT_ATOMIC_MAX_UINT_NORET */
3699 3291,
3700 /* RAT_ATOMIC_MAX_UINT_RTN */
3701 3294,
3702 /* RAT_ATOMIC_MIN_INT_NORET */
3703 3297,
3704 /* RAT_ATOMIC_MIN_INT_RTN */
3705 3300,
3706 /* RAT_ATOMIC_MIN_UINT_NORET */
3707 3303,
3708 /* RAT_ATOMIC_MIN_UINT_RTN */
3709 3306,
3710 /* RAT_ATOMIC_OR_NORET */
3711 3309,
3712 /* RAT_ATOMIC_OR_RTN */
3713 3312,
3714 /* RAT_ATOMIC_RSUB_NORET */
3715 3315,
3716 /* RAT_ATOMIC_RSUB_RTN */
3717 3318,
3718 /* RAT_ATOMIC_SUB_NORET */
3719 3321,
3720 /* RAT_ATOMIC_SUB_RTN */
3721 3324,
3722 /* RAT_ATOMIC_XCHG_INT_NORET */
3723 3327,
3724 /* RAT_ATOMIC_XCHG_INT_RTN */
3725 3330,
3726 /* RAT_ATOMIC_XOR_NORET */
3727 3333,
3728 /* RAT_ATOMIC_XOR_RTN */
3729 3336,
3730 /* RAT_MSKOR */
3731 3339,
3732 /* RAT_STORE_DWORD128 */
3733 3341,
3734 /* RAT_STORE_DWORD32 */
3735 3343,
3736 /* RAT_STORE_DWORD64 */
3737 3345,
3738 /* RAT_STORE_TYPED_cm */
3739 3347,
3740 /* RAT_STORE_TYPED_eg */
3741 3351,
3742 /* RAT_WRITE_CACHELESS_128_eg */
3743 3355,
3744 /* RAT_WRITE_CACHELESS_32_eg */
3745 3358,
3746 /* RAT_WRITE_CACHELESS_64_eg */
3747 3361,
3748 /* RECIPSQRT_CLAMPED_cm */
3749 3364,
3750 /* RECIPSQRT_CLAMPED_eg */
3751 3378,
3752 /* RECIPSQRT_CLAMPED_r600 */
3753 3392,
3754 /* RECIPSQRT_IEEE_cm */
3755 3406,
3756 /* RECIPSQRT_IEEE_eg */
3757 3420,
3758 /* RECIPSQRT_IEEE_r600 */
3759 3434,
3760 /* RECIP_CLAMPED_cm */
3761 3448,
3762 /* RECIP_CLAMPED_eg */
3763 3462,
3764 /* RECIP_CLAMPED_r600 */
3765 3476,
3766 /* RECIP_IEEE_cm */
3767 3490,
3768 /* RECIP_IEEE_eg */
3769 3504,
3770 /* RECIP_IEEE_r600 */
3771 3518,
3772 /* RECIP_UINT_eg */
3773 3532,
3774 /* RECIP_UINT_r600 */
3775 3546,
3776 /* RNDNE */
3777 3560,
3778 /* SETE */
3779 3574,
3780 /* SETE_DX10 */
3781 3595,
3782 /* SETE_INT */
3783 3616,
3784 /* SETGE_DX10 */
3785 3637,
3786 /* SETGE_INT */
3787 3658,
3788 /* SETGE_UINT */
3789 3679,
3790 /* SETGT_DX10 */
3791 3700,
3792 /* SETGT_INT */
3793 3721,
3794 /* SETGT_UINT */
3795 3742,
3796 /* SETNE_DX10 */
3797 3763,
3798 /* SETNE_INT */
3799 3784,
3800 /* SGE */
3801 3805,
3802 /* SGT */
3803 3826,
3804 /* SIN_cm */
3805 3847,
3806 /* SIN_eg */
3807 3861,
3808 /* SIN_r600 */
3809 3875,
3810 /* SIN_r700 */
3811 3889,
3812 /* SNE */
3813 3903,
3814 /* SUBB_UINT */
3815 3924,
3816 /* SUB_INT */
3817 3945,
3818 /* TEX_GET_GRADIENTS_H */
3819 3966,
3820 /* TEX_GET_GRADIENTS_V */
3821 3985,
3822 /* TEX_GET_TEXTURE_RESINFO */
3823 4004,
3824 /* TEX_LD */
3825 4023,
3826 /* TEX_LDPTR */
3827 4042,
3828 /* TEX_SAMPLE */
3829 4061,
3830 /* TEX_SAMPLE_C */
3831 4080,
3832 /* TEX_SAMPLE_C_G */
3833 4099,
3834 /* TEX_SAMPLE_C_L */
3835 4118,
3836 /* TEX_SAMPLE_C_LB */
3837 4137,
3838 /* TEX_SAMPLE_G */
3839 4156,
3840 /* TEX_SAMPLE_L */
3841 4175,
3842 /* TEX_SAMPLE_LB */
3843 4194,
3844 /* TEX_SET_GRADIENTS_H */
3845 4213,
3846 /* TEX_SET_GRADIENTS_V */
3847 4232,
3848 /* TEX_VTX_CONSTBUF */
3849 4251,
3850 /* TEX_VTX_TEXBUF */
3851 4255,
3852 /* TRUNC */
3853 4259,
3854 /* UINT_TO_FLT_eg */
3855 4273,
3856 /* UINT_TO_FLT_r600 */
3857 4287,
3858 /* VTX_READ_128_cm */
3859 4301,
3860 /* VTX_READ_128_eg */
3861 4305,
3862 /* VTX_READ_16_cm */
3863 4309,
3864 /* VTX_READ_16_eg */
3865 4313,
3866 /* VTX_READ_32_cm */
3867 4317,
3868 /* VTX_READ_32_eg */
3869 4321,
3870 /* VTX_READ_64_cm */
3871 4325,
3872 /* VTX_READ_64_eg */
3873 4329,
3874 /* VTX_READ_8_cm */
3875 4333,
3876 /* VTX_READ_8_eg */
3877 4337,
3878 /* WHILE_LOOP_EG */
3879 4341,
3880 /* WHILE_LOOP_R600 */
3881 4342,
3882 /* XOR_INT */
3883 4343,
3884 };
3885
3886 using namespace OpTypes;
3887 static const int8_t OpcodeOperandTypes[] = {
3888
3889 /* PHI */
3890 -1,
3891 /* INLINEASM */
3892 /* INLINEASM_BR */
3893 /* CFI_INSTRUCTION */
3894 i32imm,
3895 /* EH_LABEL */
3896 i32imm,
3897 /* GC_LABEL */
3898 i32imm,
3899 /* ANNOTATION_LABEL */
3900 i32imm,
3901 /* KILL */
3902 /* EXTRACT_SUBREG */
3903 -1, -1, i32imm,
3904 /* INSERT_SUBREG */
3905 -1, -1, -1, i32imm,
3906 /* IMPLICIT_DEF */
3907 -1,
3908 /* SUBREG_TO_REG */
3909 -1, -1, -1, i32imm,
3910 /* COPY_TO_REGCLASS */
3911 -1, -1, i32imm,
3912 /* DBG_VALUE */
3913 /* DBG_VALUE_LIST */
3914 /* DBG_INSTR_REF */
3915 /* DBG_PHI */
3916 /* DBG_LABEL */
3917 -1,
3918 /* REG_SEQUENCE */
3919 -1, -1,
3920 /* COPY */
3921 -1, -1,
3922 /* BUNDLE */
3923 /* LIFETIME_START */
3924 i32imm,
3925 /* LIFETIME_END */
3926 i32imm,
3927 /* PSEUDO_PROBE */
3928 i64imm, i64imm, i8imm, i32imm,
3929 /* ARITH_FENCE */
3930 -1, -1,
3931 /* STACKMAP */
3932 i64imm, i32imm,
3933 /* FENTRY_CALL */
3934 /* PATCHPOINT */
3935 -1, i64imm, i32imm, -1, i32imm, i32imm,
3936 /* LOAD_STACK_GUARD */
3937 -1,
3938 /* PREALLOCATED_SETUP */
3939 i32imm,
3940 /* PREALLOCATED_ARG */
3941 -1, i32imm, i32imm,
3942 /* STATEPOINT */
3943 /* LOCAL_ESCAPE */
3944 -1, i32imm,
3945 /* FAULTING_OP */
3946 -1,
3947 /* PATCHABLE_OP */
3948 /* PATCHABLE_FUNCTION_ENTER */
3949 /* PATCHABLE_RET */
3950 /* PATCHABLE_FUNCTION_EXIT */
3951 /* PATCHABLE_TAIL_CALL */
3952 /* PATCHABLE_EVENT_CALL */
3953 -1, -1,
3954 /* PATCHABLE_TYPED_EVENT_CALL */
3955 -1, -1, -1,
3956 /* ICALL_BRANCH_FUNNEL */
3957 /* MEMBARRIER */
3958 /* JUMP_TABLE_DEBUG_INFO */
3959 i64imm,
3960 /* CONVERGENCECTRL_ENTRY */
3961 -1,
3962 /* CONVERGENCECTRL_ANCHOR */
3963 -1,
3964 /* CONVERGENCECTRL_LOOP */
3965 -1, -1,
3966 /* CONVERGENCECTRL_GLUE */
3967 -1,
3968 /* G_ASSERT_SEXT */
3969 type0, type0, untyped_imm_0,
3970 /* G_ASSERT_ZEXT */
3971 type0, type0, untyped_imm_0,
3972 /* G_ASSERT_ALIGN */
3973 type0, type0, untyped_imm_0,
3974 /* G_ADD */
3975 type0, type0, type0,
3976 /* G_SUB */
3977 type0, type0, type0,
3978 /* G_MUL */
3979 type0, type0, type0,
3980 /* G_SDIV */
3981 type0, type0, type0,
3982 /* G_UDIV */
3983 type0, type0, type0,
3984 /* G_SREM */
3985 type0, type0, type0,
3986 /* G_UREM */
3987 type0, type0, type0,
3988 /* G_SDIVREM */
3989 type0, type0, type0, type0,
3990 /* G_UDIVREM */
3991 type0, type0, type0, type0,
3992 /* G_AND */
3993 type0, type0, type0,
3994 /* G_OR */
3995 type0, type0, type0,
3996 /* G_XOR */
3997 type0, type0, type0,
3998 /* G_IMPLICIT_DEF */
3999 type0,
4000 /* G_PHI */
4001 type0,
4002 /* G_FRAME_INDEX */
4003 type0, -1,
4004 /* G_GLOBAL_VALUE */
4005 type0, -1,
4006 /* G_PTRAUTH_GLOBAL_VALUE */
4007 type0, -1, i32imm, type1, i64imm,
4008 /* G_CONSTANT_POOL */
4009 type0, -1,
4010 /* G_EXTRACT */
4011 type0, type1, untyped_imm_0,
4012 /* G_UNMERGE_VALUES */
4013 type0, type1,
4014 /* G_INSERT */
4015 type0, type0, type1, untyped_imm_0,
4016 /* G_MERGE_VALUES */
4017 type0, type1,
4018 /* G_BUILD_VECTOR */
4019 type0, type1,
4020 /* G_BUILD_VECTOR_TRUNC */
4021 type0, type1,
4022 /* G_CONCAT_VECTORS */
4023 type0, type1,
4024 /* G_PTRTOINT */
4025 type0, type1,
4026 /* G_INTTOPTR */
4027 type0, type1,
4028 /* G_BITCAST */
4029 type0, type1,
4030 /* G_FREEZE */
4031 type0, type0,
4032 /* G_CONSTANT_FOLD_BARRIER */
4033 type0, type0,
4034 /* G_INTRINSIC_FPTRUNC_ROUND */
4035 type0, type1, i32imm,
4036 /* G_INTRINSIC_TRUNC */
4037 type0, type0,
4038 /* G_INTRINSIC_ROUND */
4039 type0, type0,
4040 /* G_INTRINSIC_LRINT */
4041 type0, type1,
4042 /* G_INTRINSIC_LLRINT */
4043 type0, type1,
4044 /* G_INTRINSIC_ROUNDEVEN */
4045 type0, type0,
4046 /* G_READCYCLECOUNTER */
4047 type0,
4048 /* G_READSTEADYCOUNTER */
4049 type0,
4050 /* G_LOAD */
4051 type0, ptype1,
4052 /* G_SEXTLOAD */
4053 type0, ptype1,
4054 /* G_ZEXTLOAD */
4055 type0, ptype1,
4056 /* G_INDEXED_LOAD */
4057 type0, ptype1, ptype1, type2, -1,
4058 /* G_INDEXED_SEXTLOAD */
4059 type0, ptype1, ptype1, type2, -1,
4060 /* G_INDEXED_ZEXTLOAD */
4061 type0, ptype1, ptype1, type2, -1,
4062 /* G_STORE */
4063 type0, ptype1,
4064 /* G_INDEXED_STORE */
4065 ptype0, type1, ptype0, ptype2, -1,
4066 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
4067 type0, type1, type2, type0, type0,
4068 /* G_ATOMIC_CMPXCHG */
4069 type0, ptype1, type0, type0,
4070 /* G_ATOMICRMW_XCHG */
4071 type0, ptype1, type0,
4072 /* G_ATOMICRMW_ADD */
4073 type0, ptype1, type0,
4074 /* G_ATOMICRMW_SUB */
4075 type0, ptype1, type0,
4076 /* G_ATOMICRMW_AND */
4077 type0, ptype1, type0,
4078 /* G_ATOMICRMW_NAND */
4079 type0, ptype1, type0,
4080 /* G_ATOMICRMW_OR */
4081 type0, ptype1, type0,
4082 /* G_ATOMICRMW_XOR */
4083 type0, ptype1, type0,
4084 /* G_ATOMICRMW_MAX */
4085 type0, ptype1, type0,
4086 /* G_ATOMICRMW_MIN */
4087 type0, ptype1, type0,
4088 /* G_ATOMICRMW_UMAX */
4089 type0, ptype1, type0,
4090 /* G_ATOMICRMW_UMIN */
4091 type0, ptype1, type0,
4092 /* G_ATOMICRMW_FADD */
4093 type0, ptype1, type0,
4094 /* G_ATOMICRMW_FSUB */
4095 type0, ptype1, type0,
4096 /* G_ATOMICRMW_FMAX */
4097 type0, ptype1, type0,
4098 /* G_ATOMICRMW_FMIN */
4099 type0, ptype1, type0,
4100 /* G_ATOMICRMW_UINC_WRAP */
4101 type0, ptype1, type0,
4102 /* G_ATOMICRMW_UDEC_WRAP */
4103 type0, ptype1, type0,
4104 /* G_FENCE */
4105 i32imm, i32imm,
4106 /* G_PREFETCH */
4107 ptype0, i32imm, i32imm, i32imm,
4108 /* G_BRCOND */
4109 type0, -1,
4110 /* G_BRINDIRECT */
4111 type0,
4112 /* G_INVOKE_REGION_START */
4113 /* G_INTRINSIC */
4114 -1,
4115 /* G_INTRINSIC_W_SIDE_EFFECTS */
4116 -1,
4117 /* G_INTRINSIC_CONVERGENT */
4118 -1,
4119 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
4120 -1,
4121 /* G_ANYEXT */
4122 type0, type1,
4123 /* G_TRUNC */
4124 type0, type1,
4125 /* G_CONSTANT */
4126 type0, -1,
4127 /* G_FCONSTANT */
4128 type0, -1,
4129 /* G_VASTART */
4130 type0,
4131 /* G_VAARG */
4132 type0, type1, -1,
4133 /* G_SEXT */
4134 type0, type1,
4135 /* G_SEXT_INREG */
4136 type0, type0, untyped_imm_0,
4137 /* G_ZEXT */
4138 type0, type1,
4139 /* G_SHL */
4140 type0, type0, type1,
4141 /* G_LSHR */
4142 type0, type0, type1,
4143 /* G_ASHR */
4144 type0, type0, type1,
4145 /* G_FSHL */
4146 type0, type0, type0, type1,
4147 /* G_FSHR */
4148 type0, type0, type0, type1,
4149 /* G_ROTR */
4150 type0, type0, type1,
4151 /* G_ROTL */
4152 type0, type0, type1,
4153 /* G_ICMP */
4154 type0, -1, type1, type1,
4155 /* G_FCMP */
4156 type0, -1, type1, type1,
4157 /* G_SCMP */
4158 type0, type1, type1,
4159 /* G_UCMP */
4160 type0, type1, type1,
4161 /* G_SELECT */
4162 type0, type1, type0, type0,
4163 /* G_UADDO */
4164 type0, type1, type0, type0,
4165 /* G_UADDE */
4166 type0, type1, type0, type0, type1,
4167 /* G_USUBO */
4168 type0, type1, type0, type0,
4169 /* G_USUBE */
4170 type0, type1, type0, type0, type1,
4171 /* G_SADDO */
4172 type0, type1, type0, type0,
4173 /* G_SADDE */
4174 type0, type1, type0, type0, type1,
4175 /* G_SSUBO */
4176 type0, type1, type0, type0,
4177 /* G_SSUBE */
4178 type0, type1, type0, type0, type1,
4179 /* G_UMULO */
4180 type0, type1, type0, type0,
4181 /* G_SMULO */
4182 type0, type1, type0, type0,
4183 /* G_UMULH */
4184 type0, type0, type0,
4185 /* G_SMULH */
4186 type0, type0, type0,
4187 /* G_UADDSAT */
4188 type0, type0, type0,
4189 /* G_SADDSAT */
4190 type0, type0, type0,
4191 /* G_USUBSAT */
4192 type0, type0, type0,
4193 /* G_SSUBSAT */
4194 type0, type0, type0,
4195 /* G_USHLSAT */
4196 type0, type0, type1,
4197 /* G_SSHLSAT */
4198 type0, type0, type1,
4199 /* G_SMULFIX */
4200 type0, type0, type0, untyped_imm_0,
4201 /* G_UMULFIX */
4202 type0, type0, type0, untyped_imm_0,
4203 /* G_SMULFIXSAT */
4204 type0, type0, type0, untyped_imm_0,
4205 /* G_UMULFIXSAT */
4206 type0, type0, type0, untyped_imm_0,
4207 /* G_SDIVFIX */
4208 type0, type0, type0, untyped_imm_0,
4209 /* G_UDIVFIX */
4210 type0, type0, type0, untyped_imm_0,
4211 /* G_SDIVFIXSAT */
4212 type0, type0, type0, untyped_imm_0,
4213 /* G_UDIVFIXSAT */
4214 type0, type0, type0, untyped_imm_0,
4215 /* G_FADD */
4216 type0, type0, type0,
4217 /* G_FSUB */
4218 type0, type0, type0,
4219 /* G_FMUL */
4220 type0, type0, type0,
4221 /* G_FMA */
4222 type0, type0, type0, type0,
4223 /* G_FMAD */
4224 type0, type0, type0, type0,
4225 /* G_FDIV */
4226 type0, type0, type0,
4227 /* G_FREM */
4228 type0, type0, type0,
4229 /* G_FPOW */
4230 type0, type0, type0,
4231 /* G_FPOWI */
4232 type0, type0, type1,
4233 /* G_FEXP */
4234 type0, type0,
4235 /* G_FEXP2 */
4236 type0, type0,
4237 /* G_FEXP10 */
4238 type0, type0,
4239 /* G_FLOG */
4240 type0, type0,
4241 /* G_FLOG2 */
4242 type0, type0,
4243 /* G_FLOG10 */
4244 type0, type0,
4245 /* G_FLDEXP */
4246 type0, type0, type1,
4247 /* G_FFREXP */
4248 type0, type1, type0,
4249 /* G_FNEG */
4250 type0, type0,
4251 /* G_FPEXT */
4252 type0, type1,
4253 /* G_FPTRUNC */
4254 type0, type1,
4255 /* G_FPTOSI */
4256 type0, type1,
4257 /* G_FPTOUI */
4258 type0, type1,
4259 /* G_SITOFP */
4260 type0, type1,
4261 /* G_UITOFP */
4262 type0, type1,
4263 /* G_FABS */
4264 type0, type0,
4265 /* G_FCOPYSIGN */
4266 type0, type0, type1,
4267 /* G_IS_FPCLASS */
4268 type0, type1, -1,
4269 /* G_FCANONICALIZE */
4270 type0, type0,
4271 /* G_FMINNUM */
4272 type0, type0, type0,
4273 /* G_FMAXNUM */
4274 type0, type0, type0,
4275 /* G_FMINNUM_IEEE */
4276 type0, type0, type0,
4277 /* G_FMAXNUM_IEEE */
4278 type0, type0, type0,
4279 /* G_FMINIMUM */
4280 type0, type0, type0,
4281 /* G_FMAXIMUM */
4282 type0, type0, type0,
4283 /* G_GET_FPENV */
4284 type0,
4285 /* G_SET_FPENV */
4286 type0,
4287 /* G_RESET_FPENV */
4288 /* G_GET_FPMODE */
4289 type0,
4290 /* G_SET_FPMODE */
4291 type0,
4292 /* G_RESET_FPMODE */
4293 /* G_PTR_ADD */
4294 ptype0, ptype0, type1,
4295 /* G_PTRMASK */
4296 ptype0, ptype0, type1,
4297 /* G_SMIN */
4298 type0, type0, type0,
4299 /* G_SMAX */
4300 type0, type0, type0,
4301 /* G_UMIN */
4302 type0, type0, type0,
4303 /* G_UMAX */
4304 type0, type0, type0,
4305 /* G_ABS */
4306 type0, type0,
4307 /* G_LROUND */
4308 type0, type1,
4309 /* G_LLROUND */
4310 type0, type1,
4311 /* G_BR */
4312 -1,
4313 /* G_BRJT */
4314 ptype0, -1, type1,
4315 /* G_VSCALE */
4316 type0, -1,
4317 /* G_INSERT_SUBVECTOR */
4318 type0, type0, type1, untyped_imm_0,
4319 /* G_EXTRACT_SUBVECTOR */
4320 type0, type0, untyped_imm_0,
4321 /* G_INSERT_VECTOR_ELT */
4322 type0, type0, type1, type2,
4323 /* G_EXTRACT_VECTOR_ELT */
4324 type0, type1, type2,
4325 /* G_SHUFFLE_VECTOR */
4326 type0, type1, type1, -1,
4327 /* G_SPLAT_VECTOR */
4328 type0, type1,
4329 /* G_VECTOR_COMPRESS */
4330 type0, type0, type1, type0,
4331 /* G_CTTZ */
4332 type0, type1,
4333 /* G_CTTZ_ZERO_UNDEF */
4334 type0, type1,
4335 /* G_CTLZ */
4336 type0, type1,
4337 /* G_CTLZ_ZERO_UNDEF */
4338 type0, type1,
4339 /* G_CTPOP */
4340 type0, type1,
4341 /* G_BSWAP */
4342 type0, type0,
4343 /* G_BITREVERSE */
4344 type0, type0,
4345 /* G_FCEIL */
4346 type0, type0,
4347 /* G_FCOS */
4348 type0, type0,
4349 /* G_FSIN */
4350 type0, type0,
4351 /* G_FTAN */
4352 type0, type0,
4353 /* G_FACOS */
4354 type0, type0,
4355 /* G_FASIN */
4356 type0, type0,
4357 /* G_FATAN */
4358 type0, type0,
4359 /* G_FCOSH */
4360 type0, type0,
4361 /* G_FSINH */
4362 type0, type0,
4363 /* G_FTANH */
4364 type0, type0,
4365 /* G_FSQRT */
4366 type0, type0,
4367 /* G_FFLOOR */
4368 type0, type0,
4369 /* G_FRINT */
4370 type0, type0,
4371 /* G_FNEARBYINT */
4372 type0, type0,
4373 /* G_ADDRSPACE_CAST */
4374 type0, type1,
4375 /* G_BLOCK_ADDR */
4376 type0, -1,
4377 /* G_JUMP_TABLE */
4378 type0, -1,
4379 /* G_DYN_STACKALLOC */
4380 ptype0, type1, i32imm,
4381 /* G_STACKSAVE */
4382 ptype0,
4383 /* G_STACKRESTORE */
4384 ptype0,
4385 /* G_STRICT_FADD */
4386 type0, type0, type0,
4387 /* G_STRICT_FSUB */
4388 type0, type0, type0,
4389 /* G_STRICT_FMUL */
4390 type0, type0, type0,
4391 /* G_STRICT_FDIV */
4392 type0, type0, type0,
4393 /* G_STRICT_FREM */
4394 type0, type0, type0,
4395 /* G_STRICT_FMA */
4396 type0, type0, type0, type0,
4397 /* G_STRICT_FSQRT */
4398 type0, type0,
4399 /* G_STRICT_FLDEXP */
4400 type0, type0, type1,
4401 /* G_READ_REGISTER */
4402 type0, -1,
4403 /* G_WRITE_REGISTER */
4404 -1, type0,
4405 /* G_MEMCPY */
4406 ptype0, ptype1, type2, untyped_imm_0,
4407 /* G_MEMCPY_INLINE */
4408 ptype0, ptype1, type2,
4409 /* G_MEMMOVE */
4410 ptype0, ptype1, type2, untyped_imm_0,
4411 /* G_MEMSET */
4412 ptype0, type1, type2, untyped_imm_0,
4413 /* G_BZERO */
4414 ptype0, type1, untyped_imm_0,
4415 /* G_TRAP */
4416 /* G_DEBUGTRAP */
4417 /* G_UBSANTRAP */
4418 i8imm,
4419 /* G_VECREDUCE_SEQ_FADD */
4420 type0, type1, type2,
4421 /* G_VECREDUCE_SEQ_FMUL */
4422 type0, type1, type2,
4423 /* G_VECREDUCE_FADD */
4424 type0, type1,
4425 /* G_VECREDUCE_FMUL */
4426 type0, type1,
4427 /* G_VECREDUCE_FMAX */
4428 type0, type1,
4429 /* G_VECREDUCE_FMIN */
4430 type0, type1,
4431 /* G_VECREDUCE_FMAXIMUM */
4432 type0, type1,
4433 /* G_VECREDUCE_FMINIMUM */
4434 type0, type1,
4435 /* G_VECREDUCE_ADD */
4436 type0, type1,
4437 /* G_VECREDUCE_MUL */
4438 type0, type1,
4439 /* G_VECREDUCE_AND */
4440 type0, type1,
4441 /* G_VECREDUCE_OR */
4442 type0, type1,
4443 /* G_VECREDUCE_XOR */
4444 type0, type1,
4445 /* G_VECREDUCE_SMAX */
4446 type0, type1,
4447 /* G_VECREDUCE_SMIN */
4448 type0, type1,
4449 /* G_VECREDUCE_UMAX */
4450 type0, type1,
4451 /* G_VECREDUCE_UMIN */
4452 type0, type1,
4453 /* G_SBFX */
4454 type0, type0, type1, type1,
4455 /* G_UBFX */
4456 type0, type0, type1, type1,
4457 /* BRANCH */
4458 brtarget,
4459 /* BRANCH_COND_f32 */
4460 brtarget, R600_Reg32,
4461 /* BRANCH_COND_i32 */
4462 brtarget, R600_Reg32,
4463 /* BREAK */
4464 /* BREAKC_f32 */
4465 R600_Reg32, R600_Reg32,
4466 /* BREAKC_i32 */
4467 R600_Reg32, R600_Reg32,
4468 /* BREAK_LOGICALNZ_f32 */
4469 R600_Reg32,
4470 /* BREAK_LOGICALNZ_i32 */
4471 R600_Reg32,
4472 /* BREAK_LOGICALZ_f32 */
4473 R600_Reg32,
4474 /* BREAK_LOGICALZ_i32 */
4475 R600_Reg32,
4476 /* CONST_COPY */
4477 R600_Reg32, i32imm,
4478 /* CONTINUE */
4479 /* CONTINUEC_f32 */
4480 R600_Reg32, R600_Reg32,
4481 /* CONTINUEC_i32 */
4482 R600_Reg32, R600_Reg32,
4483 /* CONTINUE_LOGICALNZ_f32 */
4484 R600_Reg32,
4485 /* CONTINUE_LOGICALNZ_i32 */
4486 R600_Reg32,
4487 /* CONTINUE_LOGICALZ_f32 */
4488 R600_Reg32,
4489 /* CONTINUE_LOGICALZ_i32 */
4490 R600_Reg32,
4491 /* CUBE_eg_pseudo */
4492 R600_Reg128, R600_Reg128,
4493 /* CUBE_r600_pseudo */
4494 R600_Reg128, R600_Reg128,
4495 /* DEFAULT */
4496 /* DOT_4 */
4497 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_X, NEG, REL, ABS, SEL, R600_TReg32_X, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_Y, NEG, REL, ABS, SEL, R600_TReg32_Y, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_Z, NEG, REL, ABS, SEL, R600_TReg32_Z, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_W, NEG, REL, ABS, SEL, R600_TReg32_W, NEG, REL, ABS, SEL, R600_Predicate, LITERAL, LITERAL,
4498 /* DUMMY_CHAIN */
4499 /* ELSE */
4500 /* END */
4501 /* ENDFUNC */
4502 /* ENDIF */
4503 /* ENDLOOP */
4504 /* ENDMAIN */
4505 /* ENDSWITCH */
4506 /* FABS_R600 */
4507 R600_Reg32, R600_Reg32,
4508 /* FNEG_R600 */
4509 R600_Reg32, R600_Reg32,
4510 /* FUNC */
4511 /* IFC_f32 */
4512 R600_Reg32, R600_Reg32,
4513 /* IFC_i32 */
4514 R600_Reg32, R600_Reg32,
4515 /* IF_LOGICALNZ_f32 */
4516 R600_Reg32,
4517 /* IF_LOGICALNZ_i32 */
4518 R600_Reg32,
4519 /* IF_LOGICALZ_f32 */
4520 R600_Reg32,
4521 /* IF_LOGICALZ_i32 */
4522 R600_Reg32,
4523 /* IF_PREDICATE_SET */
4524 R600_Reg32,
4525 /* JUMP */
4526 brtarget,
4527 /* JUMP_COND */
4528 brtarget, R600_Predicate_Bit,
4529 /* MASK_WRITE */
4530 R600_Reg32,
4531 /* MOV_IMM_F32 */
4532 R600_Reg32, f32imm,
4533 /* MOV_IMM_GLOBAL_ADDR */
4534 R600_Reg32, i32imm,
4535 /* MOV_IMM_I32 */
4536 R600_Reg32, i32imm,
4537 /* PRED_X */
4538 R600_Predicate_Bit, R600_Reg32, i32imm, i32imm,
4539 /* R600_EXTRACT_ELT_V2 */
4540 R600_Reg32, R600_Reg64Vertical, R600_Reg32,
4541 /* R600_EXTRACT_ELT_V4 */
4542 R600_Reg32, R600_Reg128Vertical, R600_Reg32,
4543 /* R600_INSERT_ELT_V2 */
4544 R600_Reg64Vertical, R600_Reg64Vertical, R600_Reg32, R600_Reg32,
4545 /* R600_INSERT_ELT_V4 */
4546 R600_Reg128Vertical, R600_Reg128Vertical, R600_Reg32, R600_Reg32,
4547 /* R600_RegisterLoad */
4548 R600_Reg32, R600_Reg32, i32imm, i32imm,
4549 /* R600_RegisterStore */
4550 R600_Reg32, R600_Reg32, i32imm, i32imm,
4551 /* RETDYN */
4552 /* RETURN */
4553 /* TXD */
4554 R600_Reg128, R600_Reg128, R600_Reg128, R600_Reg128, i32imm, i32imm, i32imm,
4555 /* TXD_SHADOW */
4556 R600_Reg128, R600_Reg128, R600_Reg128, R600_Reg128, i32imm, i32imm, i32imm,
4557 /* WHILELOOP */
4558 /* ADD */
4559 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4560 /* ADDC_UINT */
4561 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4562 /* ADD_INT */
4563 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4564 /* ALU_CLAUSE */
4565 i32imm,
4566 /* AND_INT */
4567 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4568 /* ASHR_eg */
4569 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4570 /* ASHR_r600 */
4571 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4572 /* BCNT_INT */
4573 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4574 /* BFE_INT_eg */
4575 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4576 /* BFE_UINT_eg */
4577 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4578 /* BFI_INT_eg */
4579 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4580 /* BFM_INT_eg */
4581 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4582 /* BIT_ALIGN_INT_eg */
4583 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4584 /* CEIL */
4585 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4586 /* CF_ALU */
4587 i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm,
4588 /* CF_ALU_BREAK */
4589 i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm,
4590 /* CF_ALU_CONTINUE */
4591 i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm,
4592 /* CF_ALU_ELSE_AFTER */
4593 i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm,
4594 /* CF_ALU_POP_AFTER */
4595 i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm,
4596 /* CF_ALU_PUSH_BEFORE */
4597 i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm,
4598 /* CF_CALL_FS_EG */
4599 /* CF_CALL_FS_R600 */
4600 /* CF_CONTINUE_EG */
4601 i32imm,
4602 /* CF_CONTINUE_R600 */
4603 i32imm,
4604 /* CF_ELSE_EG */
4605 i32imm, i32imm,
4606 /* CF_ELSE_R600 */
4607 i32imm, i32imm,
4608 /* CF_END_CM */
4609 /* CF_END_EG */
4610 /* CF_END_R600 */
4611 /* CF_JUMP_EG */
4612 i32imm, i32imm,
4613 /* CF_JUMP_R600 */
4614 i32imm, i32imm,
4615 /* CF_PUSH_EG */
4616 i32imm, i32imm,
4617 /* CF_PUSH_ELSE_R600 */
4618 i32imm,
4619 /* CF_TC_EG */
4620 i32imm, i32imm,
4621 /* CF_TC_R600 */
4622 i32imm, i32imm,
4623 /* CF_VC_EG */
4624 i32imm, i32imm,
4625 /* CF_VC_R600 */
4626 i32imm, i32imm,
4627 /* CNDE_INT */
4628 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4629 /* CNDE_eg */
4630 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4631 /* CNDE_r600 */
4632 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4633 /* CNDGE_INT */
4634 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4635 /* CNDGE_eg */
4636 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4637 /* CNDGE_r600 */
4638 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4639 /* CNDGT_INT */
4640 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4641 /* CNDGT_eg */
4642 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4643 /* CNDGT_r600 */
4644 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4645 /* COS_cm */
4646 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4647 /* COS_eg */
4648 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4649 /* COS_r600 */
4650 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4651 /* COS_r700 */
4652 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4653 /* CUBE_eg_real */
4654 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4655 /* CUBE_r600_real */
4656 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4657 /* DOT4_eg */
4658 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4659 /* DOT4_r600 */
4660 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4661 /* EG_ExportBuf */
4662 R600_Reg128, i32imm, i32imm, i32imm, i32imm, i32imm, i32imm,
4663 /* EG_ExportSwz */
4664 R600_Reg128, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm,
4665 /* END_LOOP_EG */
4666 i32imm,
4667 /* END_LOOP_R600 */
4668 i32imm,
4669 /* EXP_IEEE_cm */
4670 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4671 /* EXP_IEEE_eg */
4672 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4673 /* EXP_IEEE_r600 */
4674 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4675 /* FETCH_CLAUSE */
4676 i32imm,
4677 /* FFBH_UINT */
4678 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4679 /* FFBL_INT */
4680 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4681 /* FLOOR */
4682 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4683 /* FLT16_TO_FLT32 */
4684 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4685 /* FLT32_TO_FLT16 */
4686 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4687 /* FLT_TO_INT_eg */
4688 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4689 /* FLT_TO_INT_r600 */
4690 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4691 /* FLT_TO_UINT_eg */
4692 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4693 /* FLT_TO_UINT_r600 */
4694 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4695 /* FMA_eg */
4696 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4697 /* FRACT */
4698 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4699 /* GROUP_BARRIER */
4700 /* INTERP_LOAD_P0 */
4701 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4702 /* INTERP_PAIR_XY */
4703 R600_TReg32_X, R600_TReg32_Y, i32imm, R600_TReg32_Y, R600_TReg32_X,
4704 /* INTERP_PAIR_ZW */
4705 R600_TReg32_Z, R600_TReg32_W, i32imm, R600_TReg32_Y, R600_TReg32_X,
4706 /* INTERP_VEC_LOAD */
4707 R600_Reg128, i32imm,
4708 /* INTERP_XY */
4709 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4710 /* INTERP_ZW */
4711 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4712 /* INT_TO_FLT_eg */
4713 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4714 /* INT_TO_FLT_r600 */
4715 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4716 /* KILLGT */
4717 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4718 /* LDS_ADD */
4719 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4720 /* LDS_ADD_RET */
4721 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4722 /* LDS_AND */
4723 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4724 /* LDS_AND_RET */
4725 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4726 /* LDS_BYTE_READ_RET */
4727 R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4728 /* LDS_BYTE_WRITE */
4729 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4730 /* LDS_CMPST */
4731 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4732 /* LDS_CMPST_RET */
4733 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4734 /* LDS_MAX_INT */
4735 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4736 /* LDS_MAX_INT_RET */
4737 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4738 /* LDS_MAX_UINT */
4739 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4740 /* LDS_MAX_UINT_RET */
4741 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4742 /* LDS_MIN_INT */
4743 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4744 /* LDS_MIN_INT_RET */
4745 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4746 /* LDS_MIN_UINT */
4747 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4748 /* LDS_MIN_UINT_RET */
4749 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4750 /* LDS_OR */
4751 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4752 /* LDS_OR_RET */
4753 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4754 /* LDS_READ_RET */
4755 R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4756 /* LDS_SHORT_READ_RET */
4757 R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4758 /* LDS_SHORT_WRITE */
4759 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4760 /* LDS_SUB */
4761 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4762 /* LDS_SUB_RET */
4763 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4764 /* LDS_UBYTE_READ_RET */
4765 R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4766 /* LDS_USHORT_READ_RET */
4767 R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4768 /* LDS_WRITE */
4769 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4770 /* LDS_WRXCHG */
4771 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4772 /* LDS_WRXCHG_RET */
4773 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4774 /* LDS_XOR */
4775 R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4776 /* LDS_XOR_RET */
4777 R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE,
4778 /* LITERALS */
4779 LITERAL, LITERAL,
4780 /* LOG_CLAMPED_eg */
4781 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4782 /* LOG_CLAMPED_r600 */
4783 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4784 /* LOG_IEEE_cm */
4785 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4786 /* LOG_IEEE_eg */
4787 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4788 /* LOG_IEEE_r600 */
4789 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4790 /* LOOP_BREAK_EG */
4791 i32imm,
4792 /* LOOP_BREAK_R600 */
4793 i32imm,
4794 /* LSHL_eg */
4795 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4796 /* LSHL_r600 */
4797 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4798 /* LSHR_eg */
4799 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4800 /* LSHR_r600 */
4801 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4802 /* MAX */
4803 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4804 /* MAX_DX10 */
4805 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4806 /* MAX_INT */
4807 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4808 /* MAX_UINT */
4809 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4810 /* MIN */
4811 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4812 /* MIN_DX10 */
4813 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4814 /* MIN_INT */
4815 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4816 /* MIN_UINT */
4817 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4818 /* MOV */
4819 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4820 /* MOVA_INT_eg */
4821 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4822 /* MUL */
4823 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4824 /* MULADD_IEEE_eg */
4825 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4826 /* MULADD_IEEE_r600 */
4827 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4828 /* MULADD_INT24_cm */
4829 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4830 /* MULADD_UINT24_eg */
4831 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4832 /* MULADD_eg */
4833 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4834 /* MULADD_r600 */
4835 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4836 /* MULHI_INT_cm */
4837 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4838 /* MULHI_INT_cm24 */
4839 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4840 /* MULHI_INT_eg */
4841 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4842 /* MULHI_INT_r600 */
4843 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4844 /* MULHI_UINT24_eg */
4845 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4846 /* MULHI_UINT_cm */
4847 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4848 /* MULHI_UINT_cm24 */
4849 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4850 /* MULHI_UINT_eg */
4851 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4852 /* MULHI_UINT_r600 */
4853 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4854 /* MULLO_INT_cm */
4855 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4856 /* MULLO_INT_eg */
4857 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4858 /* MULLO_INT_r600 */
4859 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4860 /* MULLO_UINT_cm */
4861 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4862 /* MULLO_UINT_eg */
4863 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4864 /* MULLO_UINT_r600 */
4865 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4866 /* MUL_IEEE */
4867 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4868 /* MUL_INT24_cm */
4869 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4870 /* MUL_LIT_eg */
4871 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4872 /* MUL_LIT_r600 */
4873 R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4874 /* MUL_UINT24_eg */
4875 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4876 /* NOT_INT */
4877 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4878 /* OR_INT */
4879 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4880 /* PAD */
4881 /* POP_EG */
4882 i32imm, i32imm,
4883 /* POP_R600 */
4884 i32imm, i32imm,
4885 /* PRED_SETE */
4886 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4887 /* PRED_SETE_INT */
4888 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4889 /* PRED_SETGE */
4890 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4891 /* PRED_SETGE_INT */
4892 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4893 /* PRED_SETGT */
4894 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4895 /* PRED_SETGT_INT */
4896 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4897 /* PRED_SETNE */
4898 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4899 /* PRED_SETNE_INT */
4900 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4901 /* R600_ExportBuf */
4902 R600_Reg128, i32imm, i32imm, i32imm, i32imm, i32imm, i32imm,
4903 /* R600_ExportSwz */
4904 R600_Reg128, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm,
4905 /* RAT_ATOMIC_ADD_NORET */
4906 R600_Reg128, R600_Reg128, R600_TReg32_X,
4907 /* RAT_ATOMIC_ADD_RTN */
4908 R600_Reg128, R600_Reg128, R600_TReg32_X,
4909 /* RAT_ATOMIC_AND_NORET */
4910 R600_Reg128, R600_Reg128, R600_TReg32_X,
4911 /* RAT_ATOMIC_AND_RTN */
4912 R600_Reg128, R600_Reg128, R600_TReg32_X,
4913 /* RAT_ATOMIC_CMPXCHG_INT_NORET */
4914 R600_Reg128, R600_Reg128, R600_TReg32_X,
4915 /* RAT_ATOMIC_CMPXCHG_INT_RTN */
4916 R600_Reg128, R600_Reg128, R600_TReg32_X,
4917 /* RAT_ATOMIC_DEC_UINT_NORET */
4918 R600_Reg128, R600_Reg128, R600_TReg32_X,
4919 /* RAT_ATOMIC_DEC_UINT_RTN */
4920 R600_Reg128, R600_Reg128, R600_TReg32_X,
4921 /* RAT_ATOMIC_INC_UINT_NORET */
4922 R600_Reg128, R600_Reg128, R600_TReg32_X,
4923 /* RAT_ATOMIC_INC_UINT_RTN */
4924 R600_Reg128, R600_Reg128, R600_TReg32_X,
4925 /* RAT_ATOMIC_MAX_INT_NORET */
4926 R600_Reg128, R600_Reg128, R600_TReg32_X,
4927 /* RAT_ATOMIC_MAX_INT_RTN */
4928 R600_Reg128, R600_Reg128, R600_TReg32_X,
4929 /* RAT_ATOMIC_MAX_UINT_NORET */
4930 R600_Reg128, R600_Reg128, R600_TReg32_X,
4931 /* RAT_ATOMIC_MAX_UINT_RTN */
4932 R600_Reg128, R600_Reg128, R600_TReg32_X,
4933 /* RAT_ATOMIC_MIN_INT_NORET */
4934 R600_Reg128, R600_Reg128, R600_TReg32_X,
4935 /* RAT_ATOMIC_MIN_INT_RTN */
4936 R600_Reg128, R600_Reg128, R600_TReg32_X,
4937 /* RAT_ATOMIC_MIN_UINT_NORET */
4938 R600_Reg128, R600_Reg128, R600_TReg32_X,
4939 /* RAT_ATOMIC_MIN_UINT_RTN */
4940 R600_Reg128, R600_Reg128, R600_TReg32_X,
4941 /* RAT_ATOMIC_OR_NORET */
4942 R600_Reg128, R600_Reg128, R600_TReg32_X,
4943 /* RAT_ATOMIC_OR_RTN */
4944 R600_Reg128, R600_Reg128, R600_TReg32_X,
4945 /* RAT_ATOMIC_RSUB_NORET */
4946 R600_Reg128, R600_Reg128, R600_TReg32_X,
4947 /* RAT_ATOMIC_RSUB_RTN */
4948 R600_Reg128, R600_Reg128, R600_TReg32_X,
4949 /* RAT_ATOMIC_SUB_NORET */
4950 R600_Reg128, R600_Reg128, R600_TReg32_X,
4951 /* RAT_ATOMIC_SUB_RTN */
4952 R600_Reg128, R600_Reg128, R600_TReg32_X,
4953 /* RAT_ATOMIC_XCHG_INT_NORET */
4954 R600_Reg128, R600_Reg128, R600_TReg32_X,
4955 /* RAT_ATOMIC_XCHG_INT_RTN */
4956 R600_Reg128, R600_Reg128, R600_TReg32_X,
4957 /* RAT_ATOMIC_XOR_NORET */
4958 R600_Reg128, R600_Reg128, R600_TReg32_X,
4959 /* RAT_ATOMIC_XOR_RTN */
4960 R600_Reg128, R600_Reg128, R600_TReg32_X,
4961 /* RAT_MSKOR */
4962 R600_Reg128, R600_TReg32_X,
4963 /* RAT_STORE_DWORD128 */
4964 R600_Reg128, R600_TReg32_X,
4965 /* RAT_STORE_DWORD32 */
4966 R600_TReg32_X, R600_TReg32_X,
4967 /* RAT_STORE_DWORD64 */
4968 R600_Reg64, R600_TReg32_X,
4969 /* RAT_STORE_TYPED_cm */
4970 R600_Reg128, R600_Reg128, i32imm, InstFlag,
4971 /* RAT_STORE_TYPED_eg */
4972 R600_Reg128, R600_Reg128, i32imm, InstFlag,
4973 /* RAT_WRITE_CACHELESS_128_eg */
4974 R600_Reg128, R600_TReg32_X, InstFlag,
4975 /* RAT_WRITE_CACHELESS_32_eg */
4976 R600_TReg32_X, R600_TReg32_X, InstFlag,
4977 /* RAT_WRITE_CACHELESS_64_eg */
4978 R600_Reg64, R600_TReg32_X, InstFlag,
4979 /* RECIPSQRT_CLAMPED_cm */
4980 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4981 /* RECIPSQRT_CLAMPED_eg */
4982 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4983 /* RECIPSQRT_CLAMPED_r600 */
4984 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4985 /* RECIPSQRT_IEEE_cm */
4986 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4987 /* RECIPSQRT_IEEE_eg */
4988 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4989 /* RECIPSQRT_IEEE_r600 */
4990 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4991 /* RECIP_CLAMPED_cm */
4992 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4993 /* RECIP_CLAMPED_eg */
4994 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4995 /* RECIP_CLAMPED_r600 */
4996 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4997 /* RECIP_IEEE_cm */
4998 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
4999 /* RECIP_IEEE_eg */
5000 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5001 /* RECIP_IEEE_r600 */
5002 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5003 /* RECIP_UINT_eg */
5004 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5005 /* RECIP_UINT_r600 */
5006 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5007 /* RNDNE */
5008 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5009 /* SETE */
5010 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5011 /* SETE_DX10 */
5012 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5013 /* SETE_INT */
5014 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5015 /* SETGE_DX10 */
5016 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5017 /* SETGE_INT */
5018 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5019 /* SETGE_UINT */
5020 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5021 /* SETGT_DX10 */
5022 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5023 /* SETGT_INT */
5024 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5025 /* SETGT_UINT */
5026 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5027 /* SETNE_DX10 */
5028 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5029 /* SETNE_INT */
5030 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5031 /* SGE */
5032 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5033 /* SGT */
5034 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5035 /* SIN_cm */
5036 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5037 /* SIN_eg */
5038 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5039 /* SIN_r600 */
5040 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5041 /* SIN_r700 */
5042 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5043 /* SNE */
5044 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5045 /* SUBB_UINT */
5046 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5047 /* SUB_INT */
5048 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5049 /* TEX_GET_GRADIENTS_H */
5050 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5051 /* TEX_GET_GRADIENTS_V */
5052 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5053 /* TEX_GET_TEXTURE_RESINFO */
5054 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5055 /* TEX_LD */
5056 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5057 /* TEX_LDPTR */
5058 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5059 /* TEX_SAMPLE */
5060 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5061 /* TEX_SAMPLE_C */
5062 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5063 /* TEX_SAMPLE_C_G */
5064 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5065 /* TEX_SAMPLE_C_L */
5066 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5067 /* TEX_SAMPLE_C_LB */
5068 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5069 /* TEX_SAMPLE_G */
5070 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5071 /* TEX_SAMPLE_L */
5072 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5073 /* TEX_SAMPLE_LB */
5074 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5075 /* TEX_SET_GRADIENTS_H */
5076 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5077 /* TEX_SET_GRADIENTS_V */
5078 R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT,
5079 /* TEX_VTX_CONSTBUF */
5080 R600_Reg128, R600_TReg32_X, i32imm, i32imm,
5081 /* TEX_VTX_TEXBUF */
5082 R600_Reg128, R600_TReg32_X, i32imm, i32imm,
5083 /* TRUNC */
5084 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5085 /* UINT_TO_FLT_eg */
5086 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5087 /* UINT_TO_FLT_r600 */
5088 R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5089 /* VTX_READ_128_cm */
5090 R600_Reg128, R600_TReg32_X, i32imm, i8imm,
5091 /* VTX_READ_128_eg */
5092 R600_Reg128, R600_TReg32_X, i32imm, i8imm,
5093 /* VTX_READ_16_cm */
5094 R600_TReg32_X, R600_TReg32_X, i32imm, i8imm,
5095 /* VTX_READ_16_eg */
5096 R600_TReg32_X, R600_TReg32_X, i32imm, i8imm,
5097 /* VTX_READ_32_cm */
5098 R600_TReg32_X, R600_TReg32_X, i32imm, i8imm,
5099 /* VTX_READ_32_eg */
5100 R600_TReg32_X, R600_TReg32_X, i32imm, i8imm,
5101 /* VTX_READ_64_cm */
5102 R600_Reg64, R600_TReg32_X, i32imm, i8imm,
5103 /* VTX_READ_64_eg */
5104 R600_Reg64, R600_TReg32_X, i32imm, i8imm,
5105 /* VTX_READ_8_cm */
5106 R600_TReg32_X, R600_TReg32_X, i32imm, i8imm,
5107 /* VTX_READ_8_eg */
5108 R600_TReg32_X, R600_TReg32_X, i32imm, i8imm,
5109 /* WHILE_LOOP_EG */
5110 i32imm,
5111 /* WHILE_LOOP_R600 */
5112 i32imm,
5113 /* XOR_INT */
5114 R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE,
5115 };
5116 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
5117}
5118} // end namespace R600
5119} // end namespace llvm
5120#endif // GET_INSTRINFO_OPERAND_TYPE
5121
5122#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
5123#undef GET_INSTRINFO_MEM_OPERAND_SIZE
5124namespace llvm {
5125namespace R600 {
5126LLVM_READONLY
5127static int getMemOperandSize(int OpType) {
5128 switch (OpType) {
5129 default: return 0;
5130 }
5131}
5132} // end namespace R600
5133} // end namespace llvm
5134#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
5135
5136#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
5137#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
5138namespace llvm {
5139namespace R600 {
5140LLVM_READONLY static unsigned
5141getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
5142 return LogicalOpIdx;
5143}
5144LLVM_READONLY static inline unsigned
5145getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
5146 auto S = 0U;
5147 for (auto i = 0U; i < LogicalOpIdx; ++i)
5148 S += getLogicalOperandSize(Opcode, i);
5149 return S;
5150}
5151} // end namespace R600
5152} // end namespace llvm
5153#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
5154
5155#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
5156#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
5157namespace llvm {
5158namespace R600 {
5159LLVM_READONLY static int
5160getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
5161 return -1;
5162}
5163} // end namespace R600
5164} // end namespace llvm
5165#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
5166
5167#ifdef GET_INSTRINFO_MC_HELPER_DECLS
5168#undef GET_INSTRINFO_MC_HELPER_DECLS
5169
5170namespace llvm {
5171class MCInst;
5172class FeatureBitset;
5173
5174namespace R600_MC {
5175
5176void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
5177
5178} // end namespace R600_MC
5179} // end namespace llvm
5180
5181#endif // GET_INSTRINFO_MC_HELPER_DECLS
5182
5183#ifdef GET_INSTRINFO_MC_HELPERS
5184#undef GET_INSTRINFO_MC_HELPERS
5185
5186namespace llvm {
5187namespace R600_MC {
5188
5189} // end namespace R600_MC
5190} // end namespace llvm
5191
5192#endif // GET_GENISTRINFO_MC_HELPERS
5193
5194#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
5195 defined(GET_AVAILABLE_OPCODE_CHECKER)
5196#define GET_COMPUTE_FEATURES
5197#endif
5198#ifdef GET_COMPUTE_FEATURES
5199#undef GET_COMPUTE_FEATURES
5200namespace llvm {
5201namespace R600_MC {
5202
5203// Bits for subtarget features that participate in instruction matching.
5204enum SubtargetFeatureBits : uint8_t {
5205};
5206
5207inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
5208 FeatureBitset Features;
5209 return Features;
5210}
5211
5212inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
5213 enum : uint8_t {
5214 CEFBS_None,
5215 };
5216
5217 static constexpr FeatureBitset FeatureBitsets[] = {
5218 {}, // CEFBS_None
5219 };
5220 static constexpr uint8_t RequiredFeaturesRefs[] = {
5221 CEFBS_None, // PHI = 0
5222 CEFBS_None, // INLINEASM = 1
5223 CEFBS_None, // INLINEASM_BR = 2
5224 CEFBS_None, // CFI_INSTRUCTION = 3
5225 CEFBS_None, // EH_LABEL = 4
5226 CEFBS_None, // GC_LABEL = 5
5227 CEFBS_None, // ANNOTATION_LABEL = 6
5228 CEFBS_None, // KILL = 7
5229 CEFBS_None, // EXTRACT_SUBREG = 8
5230 CEFBS_None, // INSERT_SUBREG = 9
5231 CEFBS_None, // IMPLICIT_DEF = 10
5232 CEFBS_None, // SUBREG_TO_REG = 11
5233 CEFBS_None, // COPY_TO_REGCLASS = 12
5234 CEFBS_None, // DBG_VALUE = 13
5235 CEFBS_None, // DBG_VALUE_LIST = 14
5236 CEFBS_None, // DBG_INSTR_REF = 15
5237 CEFBS_None, // DBG_PHI = 16
5238 CEFBS_None, // DBG_LABEL = 17
5239 CEFBS_None, // REG_SEQUENCE = 18
5240 CEFBS_None, // COPY = 19
5241 CEFBS_None, // BUNDLE = 20
5242 CEFBS_None, // LIFETIME_START = 21
5243 CEFBS_None, // LIFETIME_END = 22
5244 CEFBS_None, // PSEUDO_PROBE = 23
5245 CEFBS_None, // ARITH_FENCE = 24
5246 CEFBS_None, // STACKMAP = 25
5247 CEFBS_None, // FENTRY_CALL = 26
5248 CEFBS_None, // PATCHPOINT = 27
5249 CEFBS_None, // LOAD_STACK_GUARD = 28
5250 CEFBS_None, // PREALLOCATED_SETUP = 29
5251 CEFBS_None, // PREALLOCATED_ARG = 30
5252 CEFBS_None, // STATEPOINT = 31
5253 CEFBS_None, // LOCAL_ESCAPE = 32
5254 CEFBS_None, // FAULTING_OP = 33
5255 CEFBS_None, // PATCHABLE_OP = 34
5256 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
5257 CEFBS_None, // PATCHABLE_RET = 36
5258 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
5259 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
5260 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
5261 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
5262 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
5263 CEFBS_None, // MEMBARRIER = 42
5264 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
5265 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
5266 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
5267 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
5268 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
5269 CEFBS_None, // G_ASSERT_SEXT = 48
5270 CEFBS_None, // G_ASSERT_ZEXT = 49
5271 CEFBS_None, // G_ASSERT_ALIGN = 50
5272 CEFBS_None, // G_ADD = 51
5273 CEFBS_None, // G_SUB = 52
5274 CEFBS_None, // G_MUL = 53
5275 CEFBS_None, // G_SDIV = 54
5276 CEFBS_None, // G_UDIV = 55
5277 CEFBS_None, // G_SREM = 56
5278 CEFBS_None, // G_UREM = 57
5279 CEFBS_None, // G_SDIVREM = 58
5280 CEFBS_None, // G_UDIVREM = 59
5281 CEFBS_None, // G_AND = 60
5282 CEFBS_None, // G_OR = 61
5283 CEFBS_None, // G_XOR = 62
5284 CEFBS_None, // G_IMPLICIT_DEF = 63
5285 CEFBS_None, // G_PHI = 64
5286 CEFBS_None, // G_FRAME_INDEX = 65
5287 CEFBS_None, // G_GLOBAL_VALUE = 66
5288 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
5289 CEFBS_None, // G_CONSTANT_POOL = 68
5290 CEFBS_None, // G_EXTRACT = 69
5291 CEFBS_None, // G_UNMERGE_VALUES = 70
5292 CEFBS_None, // G_INSERT = 71
5293 CEFBS_None, // G_MERGE_VALUES = 72
5294 CEFBS_None, // G_BUILD_VECTOR = 73
5295 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
5296 CEFBS_None, // G_CONCAT_VECTORS = 75
5297 CEFBS_None, // G_PTRTOINT = 76
5298 CEFBS_None, // G_INTTOPTR = 77
5299 CEFBS_None, // G_BITCAST = 78
5300 CEFBS_None, // G_FREEZE = 79
5301 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
5302 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
5303 CEFBS_None, // G_INTRINSIC_TRUNC = 82
5304 CEFBS_None, // G_INTRINSIC_ROUND = 83
5305 CEFBS_None, // G_INTRINSIC_LRINT = 84
5306 CEFBS_None, // G_INTRINSIC_LLRINT = 85
5307 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
5308 CEFBS_None, // G_READCYCLECOUNTER = 87
5309 CEFBS_None, // G_READSTEADYCOUNTER = 88
5310 CEFBS_None, // G_LOAD = 89
5311 CEFBS_None, // G_SEXTLOAD = 90
5312 CEFBS_None, // G_ZEXTLOAD = 91
5313 CEFBS_None, // G_INDEXED_LOAD = 92
5314 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
5315 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
5316 CEFBS_None, // G_STORE = 95
5317 CEFBS_None, // G_INDEXED_STORE = 96
5318 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
5319 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
5320 CEFBS_None, // G_ATOMICRMW_XCHG = 99
5321 CEFBS_None, // G_ATOMICRMW_ADD = 100
5322 CEFBS_None, // G_ATOMICRMW_SUB = 101
5323 CEFBS_None, // G_ATOMICRMW_AND = 102
5324 CEFBS_None, // G_ATOMICRMW_NAND = 103
5325 CEFBS_None, // G_ATOMICRMW_OR = 104
5326 CEFBS_None, // G_ATOMICRMW_XOR = 105
5327 CEFBS_None, // G_ATOMICRMW_MAX = 106
5328 CEFBS_None, // G_ATOMICRMW_MIN = 107
5329 CEFBS_None, // G_ATOMICRMW_UMAX = 108
5330 CEFBS_None, // G_ATOMICRMW_UMIN = 109
5331 CEFBS_None, // G_ATOMICRMW_FADD = 110
5332 CEFBS_None, // G_ATOMICRMW_FSUB = 111
5333 CEFBS_None, // G_ATOMICRMW_FMAX = 112
5334 CEFBS_None, // G_ATOMICRMW_FMIN = 113
5335 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
5336 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
5337 CEFBS_None, // G_FENCE = 116
5338 CEFBS_None, // G_PREFETCH = 117
5339 CEFBS_None, // G_BRCOND = 118
5340 CEFBS_None, // G_BRINDIRECT = 119
5341 CEFBS_None, // G_INVOKE_REGION_START = 120
5342 CEFBS_None, // G_INTRINSIC = 121
5343 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
5344 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
5345 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
5346 CEFBS_None, // G_ANYEXT = 125
5347 CEFBS_None, // G_TRUNC = 126
5348 CEFBS_None, // G_CONSTANT = 127
5349 CEFBS_None, // G_FCONSTANT = 128
5350 CEFBS_None, // G_VASTART = 129
5351 CEFBS_None, // G_VAARG = 130
5352 CEFBS_None, // G_SEXT = 131
5353 CEFBS_None, // G_SEXT_INREG = 132
5354 CEFBS_None, // G_ZEXT = 133
5355 CEFBS_None, // G_SHL = 134
5356 CEFBS_None, // G_LSHR = 135
5357 CEFBS_None, // G_ASHR = 136
5358 CEFBS_None, // G_FSHL = 137
5359 CEFBS_None, // G_FSHR = 138
5360 CEFBS_None, // G_ROTR = 139
5361 CEFBS_None, // G_ROTL = 140
5362 CEFBS_None, // G_ICMP = 141
5363 CEFBS_None, // G_FCMP = 142
5364 CEFBS_None, // G_SCMP = 143
5365 CEFBS_None, // G_UCMP = 144
5366 CEFBS_None, // G_SELECT = 145
5367 CEFBS_None, // G_UADDO = 146
5368 CEFBS_None, // G_UADDE = 147
5369 CEFBS_None, // G_USUBO = 148
5370 CEFBS_None, // G_USUBE = 149
5371 CEFBS_None, // G_SADDO = 150
5372 CEFBS_None, // G_SADDE = 151
5373 CEFBS_None, // G_SSUBO = 152
5374 CEFBS_None, // G_SSUBE = 153
5375 CEFBS_None, // G_UMULO = 154
5376 CEFBS_None, // G_SMULO = 155
5377 CEFBS_None, // G_UMULH = 156
5378 CEFBS_None, // G_SMULH = 157
5379 CEFBS_None, // G_UADDSAT = 158
5380 CEFBS_None, // G_SADDSAT = 159
5381 CEFBS_None, // G_USUBSAT = 160
5382 CEFBS_None, // G_SSUBSAT = 161
5383 CEFBS_None, // G_USHLSAT = 162
5384 CEFBS_None, // G_SSHLSAT = 163
5385 CEFBS_None, // G_SMULFIX = 164
5386 CEFBS_None, // G_UMULFIX = 165
5387 CEFBS_None, // G_SMULFIXSAT = 166
5388 CEFBS_None, // G_UMULFIXSAT = 167
5389 CEFBS_None, // G_SDIVFIX = 168
5390 CEFBS_None, // G_UDIVFIX = 169
5391 CEFBS_None, // G_SDIVFIXSAT = 170
5392 CEFBS_None, // G_UDIVFIXSAT = 171
5393 CEFBS_None, // G_FADD = 172
5394 CEFBS_None, // G_FSUB = 173
5395 CEFBS_None, // G_FMUL = 174
5396 CEFBS_None, // G_FMA = 175
5397 CEFBS_None, // G_FMAD = 176
5398 CEFBS_None, // G_FDIV = 177
5399 CEFBS_None, // G_FREM = 178
5400 CEFBS_None, // G_FPOW = 179
5401 CEFBS_None, // G_FPOWI = 180
5402 CEFBS_None, // G_FEXP = 181
5403 CEFBS_None, // G_FEXP2 = 182
5404 CEFBS_None, // G_FEXP10 = 183
5405 CEFBS_None, // G_FLOG = 184
5406 CEFBS_None, // G_FLOG2 = 185
5407 CEFBS_None, // G_FLOG10 = 186
5408 CEFBS_None, // G_FLDEXP = 187
5409 CEFBS_None, // G_FFREXP = 188
5410 CEFBS_None, // G_FNEG = 189
5411 CEFBS_None, // G_FPEXT = 190
5412 CEFBS_None, // G_FPTRUNC = 191
5413 CEFBS_None, // G_FPTOSI = 192
5414 CEFBS_None, // G_FPTOUI = 193
5415 CEFBS_None, // G_SITOFP = 194
5416 CEFBS_None, // G_UITOFP = 195
5417 CEFBS_None, // G_FABS = 196
5418 CEFBS_None, // G_FCOPYSIGN = 197
5419 CEFBS_None, // G_IS_FPCLASS = 198
5420 CEFBS_None, // G_FCANONICALIZE = 199
5421 CEFBS_None, // G_FMINNUM = 200
5422 CEFBS_None, // G_FMAXNUM = 201
5423 CEFBS_None, // G_FMINNUM_IEEE = 202
5424 CEFBS_None, // G_FMAXNUM_IEEE = 203
5425 CEFBS_None, // G_FMINIMUM = 204
5426 CEFBS_None, // G_FMAXIMUM = 205
5427 CEFBS_None, // G_GET_FPENV = 206
5428 CEFBS_None, // G_SET_FPENV = 207
5429 CEFBS_None, // G_RESET_FPENV = 208
5430 CEFBS_None, // G_GET_FPMODE = 209
5431 CEFBS_None, // G_SET_FPMODE = 210
5432 CEFBS_None, // G_RESET_FPMODE = 211
5433 CEFBS_None, // G_PTR_ADD = 212
5434 CEFBS_None, // G_PTRMASK = 213
5435 CEFBS_None, // G_SMIN = 214
5436 CEFBS_None, // G_SMAX = 215
5437 CEFBS_None, // G_UMIN = 216
5438 CEFBS_None, // G_UMAX = 217
5439 CEFBS_None, // G_ABS = 218
5440 CEFBS_None, // G_LROUND = 219
5441 CEFBS_None, // G_LLROUND = 220
5442 CEFBS_None, // G_BR = 221
5443 CEFBS_None, // G_BRJT = 222
5444 CEFBS_None, // G_VSCALE = 223
5445 CEFBS_None, // G_INSERT_SUBVECTOR = 224
5446 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
5447 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
5448 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
5449 CEFBS_None, // G_SHUFFLE_VECTOR = 228
5450 CEFBS_None, // G_SPLAT_VECTOR = 229
5451 CEFBS_None, // G_VECTOR_COMPRESS = 230
5452 CEFBS_None, // G_CTTZ = 231
5453 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
5454 CEFBS_None, // G_CTLZ = 233
5455 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
5456 CEFBS_None, // G_CTPOP = 235
5457 CEFBS_None, // G_BSWAP = 236
5458 CEFBS_None, // G_BITREVERSE = 237
5459 CEFBS_None, // G_FCEIL = 238
5460 CEFBS_None, // G_FCOS = 239
5461 CEFBS_None, // G_FSIN = 240
5462 CEFBS_None, // G_FTAN = 241
5463 CEFBS_None, // G_FACOS = 242
5464 CEFBS_None, // G_FASIN = 243
5465 CEFBS_None, // G_FATAN = 244
5466 CEFBS_None, // G_FCOSH = 245
5467 CEFBS_None, // G_FSINH = 246
5468 CEFBS_None, // G_FTANH = 247
5469 CEFBS_None, // G_FSQRT = 248
5470 CEFBS_None, // G_FFLOOR = 249
5471 CEFBS_None, // G_FRINT = 250
5472 CEFBS_None, // G_FNEARBYINT = 251
5473 CEFBS_None, // G_ADDRSPACE_CAST = 252
5474 CEFBS_None, // G_BLOCK_ADDR = 253
5475 CEFBS_None, // G_JUMP_TABLE = 254
5476 CEFBS_None, // G_DYN_STACKALLOC = 255
5477 CEFBS_None, // G_STACKSAVE = 256
5478 CEFBS_None, // G_STACKRESTORE = 257
5479 CEFBS_None, // G_STRICT_FADD = 258
5480 CEFBS_None, // G_STRICT_FSUB = 259
5481 CEFBS_None, // G_STRICT_FMUL = 260
5482 CEFBS_None, // G_STRICT_FDIV = 261
5483 CEFBS_None, // G_STRICT_FREM = 262
5484 CEFBS_None, // G_STRICT_FMA = 263
5485 CEFBS_None, // G_STRICT_FSQRT = 264
5486 CEFBS_None, // G_STRICT_FLDEXP = 265
5487 CEFBS_None, // G_READ_REGISTER = 266
5488 CEFBS_None, // G_WRITE_REGISTER = 267
5489 CEFBS_None, // G_MEMCPY = 268
5490 CEFBS_None, // G_MEMCPY_INLINE = 269
5491 CEFBS_None, // G_MEMMOVE = 270
5492 CEFBS_None, // G_MEMSET = 271
5493 CEFBS_None, // G_BZERO = 272
5494 CEFBS_None, // G_TRAP = 273
5495 CEFBS_None, // G_DEBUGTRAP = 274
5496 CEFBS_None, // G_UBSANTRAP = 275
5497 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
5498 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
5499 CEFBS_None, // G_VECREDUCE_FADD = 278
5500 CEFBS_None, // G_VECREDUCE_FMUL = 279
5501 CEFBS_None, // G_VECREDUCE_FMAX = 280
5502 CEFBS_None, // G_VECREDUCE_FMIN = 281
5503 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
5504 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
5505 CEFBS_None, // G_VECREDUCE_ADD = 284
5506 CEFBS_None, // G_VECREDUCE_MUL = 285
5507 CEFBS_None, // G_VECREDUCE_AND = 286
5508 CEFBS_None, // G_VECREDUCE_OR = 287
5509 CEFBS_None, // G_VECREDUCE_XOR = 288
5510 CEFBS_None, // G_VECREDUCE_SMAX = 289
5511 CEFBS_None, // G_VECREDUCE_SMIN = 290
5512 CEFBS_None, // G_VECREDUCE_UMAX = 291
5513 CEFBS_None, // G_VECREDUCE_UMIN = 292
5514 CEFBS_None, // G_SBFX = 293
5515 CEFBS_None, // G_UBFX = 294
5516 CEFBS_None, // BRANCH = 295
5517 CEFBS_None, // BRANCH_COND_f32 = 296
5518 CEFBS_None, // BRANCH_COND_i32 = 297
5519 CEFBS_None, // BREAK = 298
5520 CEFBS_None, // BREAKC_f32 = 299
5521 CEFBS_None, // BREAKC_i32 = 300
5522 CEFBS_None, // BREAK_LOGICALNZ_f32 = 301
5523 CEFBS_None, // BREAK_LOGICALNZ_i32 = 302
5524 CEFBS_None, // BREAK_LOGICALZ_f32 = 303
5525 CEFBS_None, // BREAK_LOGICALZ_i32 = 304
5526 CEFBS_None, // CONST_COPY = 305
5527 CEFBS_None, // CONTINUE = 306
5528 CEFBS_None, // CONTINUEC_f32 = 307
5529 CEFBS_None, // CONTINUEC_i32 = 308
5530 CEFBS_None, // CONTINUE_LOGICALNZ_f32 = 309
5531 CEFBS_None, // CONTINUE_LOGICALNZ_i32 = 310
5532 CEFBS_None, // CONTINUE_LOGICALZ_f32 = 311
5533 CEFBS_None, // CONTINUE_LOGICALZ_i32 = 312
5534 CEFBS_None, // CUBE_eg_pseudo = 313
5535 CEFBS_None, // CUBE_r600_pseudo = 314
5536 CEFBS_None, // DEFAULT = 315
5537 CEFBS_None, // DOT_4 = 316
5538 CEFBS_None, // DUMMY_CHAIN = 317
5539 CEFBS_None, // ELSE = 318
5540 CEFBS_None, // END = 319
5541 CEFBS_None, // ENDFUNC = 320
5542 CEFBS_None, // ENDIF = 321
5543 CEFBS_None, // ENDLOOP = 322
5544 CEFBS_None, // ENDMAIN = 323
5545 CEFBS_None, // ENDSWITCH = 324
5546 CEFBS_None, // FABS_R600 = 325
5547 CEFBS_None, // FNEG_R600 = 326
5548 CEFBS_None, // FUNC = 327
5549 CEFBS_None, // IFC_f32 = 328
5550 CEFBS_None, // IFC_i32 = 329
5551 CEFBS_None, // IF_LOGICALNZ_f32 = 330
5552 CEFBS_None, // IF_LOGICALNZ_i32 = 331
5553 CEFBS_None, // IF_LOGICALZ_f32 = 332
5554 CEFBS_None, // IF_LOGICALZ_i32 = 333
5555 CEFBS_None, // IF_PREDICATE_SET = 334
5556 CEFBS_None, // JUMP = 335
5557 CEFBS_None, // JUMP_COND = 336
5558 CEFBS_None, // MASK_WRITE = 337
5559 CEFBS_None, // MOV_IMM_F32 = 338
5560 CEFBS_None, // MOV_IMM_GLOBAL_ADDR = 339
5561 CEFBS_None, // MOV_IMM_I32 = 340
5562 CEFBS_None, // PRED_X = 341
5563 CEFBS_None, // R600_EXTRACT_ELT_V2 = 342
5564 CEFBS_None, // R600_EXTRACT_ELT_V4 = 343
5565 CEFBS_None, // R600_INSERT_ELT_V2 = 344
5566 CEFBS_None, // R600_INSERT_ELT_V4 = 345
5567 CEFBS_None, // R600_RegisterLoad = 346
5568 CEFBS_None, // R600_RegisterStore = 347
5569 CEFBS_None, // RETDYN = 348
5570 CEFBS_None, // RETURN = 349
5571 CEFBS_None, // TXD = 350
5572 CEFBS_None, // TXD_SHADOW = 351
5573 CEFBS_None, // WHILELOOP = 352
5574 CEFBS_None, // ADD = 353
5575 CEFBS_None, // ADDC_UINT = 354
5576 CEFBS_None, // ADD_INT = 355
5577 CEFBS_None, // ALU_CLAUSE = 356
5578 CEFBS_None, // AND_INT = 357
5579 CEFBS_None, // ASHR_eg = 358
5580 CEFBS_None, // ASHR_r600 = 359
5581 CEFBS_None, // BCNT_INT = 360
5582 CEFBS_None, // BFE_INT_eg = 361
5583 CEFBS_None, // BFE_UINT_eg = 362
5584 CEFBS_None, // BFI_INT_eg = 363
5585 CEFBS_None, // BFM_INT_eg = 364
5586 CEFBS_None, // BIT_ALIGN_INT_eg = 365
5587 CEFBS_None, // CEIL = 366
5588 CEFBS_None, // CF_ALU = 367
5589 CEFBS_None, // CF_ALU_BREAK = 368
5590 CEFBS_None, // CF_ALU_CONTINUE = 369
5591 CEFBS_None, // CF_ALU_ELSE_AFTER = 370
5592 CEFBS_None, // CF_ALU_POP_AFTER = 371
5593 CEFBS_None, // CF_ALU_PUSH_BEFORE = 372
5594 CEFBS_None, // CF_CALL_FS_EG = 373
5595 CEFBS_None, // CF_CALL_FS_R600 = 374
5596 CEFBS_None, // CF_CONTINUE_EG = 375
5597 CEFBS_None, // CF_CONTINUE_R600 = 376
5598 CEFBS_None, // CF_ELSE_EG = 377
5599 CEFBS_None, // CF_ELSE_R600 = 378
5600 CEFBS_None, // CF_END_CM = 379
5601 CEFBS_None, // CF_END_EG = 380
5602 CEFBS_None, // CF_END_R600 = 381
5603 CEFBS_None, // CF_JUMP_EG = 382
5604 CEFBS_None, // CF_JUMP_R600 = 383
5605 CEFBS_None, // CF_PUSH_EG = 384
5606 CEFBS_None, // CF_PUSH_ELSE_R600 = 385
5607 CEFBS_None, // CF_TC_EG = 386
5608 CEFBS_None, // CF_TC_R600 = 387
5609 CEFBS_None, // CF_VC_EG = 388
5610 CEFBS_None, // CF_VC_R600 = 389
5611 CEFBS_None, // CNDE_INT = 390
5612 CEFBS_None, // CNDE_eg = 391
5613 CEFBS_None, // CNDE_r600 = 392
5614 CEFBS_None, // CNDGE_INT = 393
5615 CEFBS_None, // CNDGE_eg = 394
5616 CEFBS_None, // CNDGE_r600 = 395
5617 CEFBS_None, // CNDGT_INT = 396
5618 CEFBS_None, // CNDGT_eg = 397
5619 CEFBS_None, // CNDGT_r600 = 398
5620 CEFBS_None, // COS_cm = 399
5621 CEFBS_None, // COS_eg = 400
5622 CEFBS_None, // COS_r600 = 401
5623 CEFBS_None, // COS_r700 = 402
5624 CEFBS_None, // CUBE_eg_real = 403
5625 CEFBS_None, // CUBE_r600_real = 404
5626 CEFBS_None, // DOT4_eg = 405
5627 CEFBS_None, // DOT4_r600 = 406
5628 CEFBS_None, // EG_ExportBuf = 407
5629 CEFBS_None, // EG_ExportSwz = 408
5630 CEFBS_None, // END_LOOP_EG = 409
5631 CEFBS_None, // END_LOOP_R600 = 410
5632 CEFBS_None, // EXP_IEEE_cm = 411
5633 CEFBS_None, // EXP_IEEE_eg = 412
5634 CEFBS_None, // EXP_IEEE_r600 = 413
5635 CEFBS_None, // FETCH_CLAUSE = 414
5636 CEFBS_None, // FFBH_UINT = 415
5637 CEFBS_None, // FFBL_INT = 416
5638 CEFBS_None, // FLOOR = 417
5639 CEFBS_None, // FLT16_TO_FLT32 = 418
5640 CEFBS_None, // FLT32_TO_FLT16 = 419
5641 CEFBS_None, // FLT_TO_INT_eg = 420
5642 CEFBS_None, // FLT_TO_INT_r600 = 421
5643 CEFBS_None, // FLT_TO_UINT_eg = 422
5644 CEFBS_None, // FLT_TO_UINT_r600 = 423
5645 CEFBS_None, // FMA_eg = 424
5646 CEFBS_None, // FRACT = 425
5647 CEFBS_None, // GROUP_BARRIER = 426
5648 CEFBS_None, // INTERP_LOAD_P0 = 427
5649 CEFBS_None, // INTERP_PAIR_XY = 428
5650 CEFBS_None, // INTERP_PAIR_ZW = 429
5651 CEFBS_None, // INTERP_VEC_LOAD = 430
5652 CEFBS_None, // INTERP_XY = 431
5653 CEFBS_None, // INTERP_ZW = 432
5654 CEFBS_None, // INT_TO_FLT_eg = 433
5655 CEFBS_None, // INT_TO_FLT_r600 = 434
5656 CEFBS_None, // KILLGT = 435
5657 CEFBS_None, // LDS_ADD = 436
5658 CEFBS_None, // LDS_ADD_RET = 437
5659 CEFBS_None, // LDS_AND = 438
5660 CEFBS_None, // LDS_AND_RET = 439
5661 CEFBS_None, // LDS_BYTE_READ_RET = 440
5662 CEFBS_None, // LDS_BYTE_WRITE = 441
5663 CEFBS_None, // LDS_CMPST = 442
5664 CEFBS_None, // LDS_CMPST_RET = 443
5665 CEFBS_None, // LDS_MAX_INT = 444
5666 CEFBS_None, // LDS_MAX_INT_RET = 445
5667 CEFBS_None, // LDS_MAX_UINT = 446
5668 CEFBS_None, // LDS_MAX_UINT_RET = 447
5669 CEFBS_None, // LDS_MIN_INT = 448
5670 CEFBS_None, // LDS_MIN_INT_RET = 449
5671 CEFBS_None, // LDS_MIN_UINT = 450
5672 CEFBS_None, // LDS_MIN_UINT_RET = 451
5673 CEFBS_None, // LDS_OR = 452
5674 CEFBS_None, // LDS_OR_RET = 453
5675 CEFBS_None, // LDS_READ_RET = 454
5676 CEFBS_None, // LDS_SHORT_READ_RET = 455
5677 CEFBS_None, // LDS_SHORT_WRITE = 456
5678 CEFBS_None, // LDS_SUB = 457
5679 CEFBS_None, // LDS_SUB_RET = 458
5680 CEFBS_None, // LDS_UBYTE_READ_RET = 459
5681 CEFBS_None, // LDS_USHORT_READ_RET = 460
5682 CEFBS_None, // LDS_WRITE = 461
5683 CEFBS_None, // LDS_WRXCHG = 462
5684 CEFBS_None, // LDS_WRXCHG_RET = 463
5685 CEFBS_None, // LDS_XOR = 464
5686 CEFBS_None, // LDS_XOR_RET = 465
5687 CEFBS_None, // LITERALS = 466
5688 CEFBS_None, // LOG_CLAMPED_eg = 467
5689 CEFBS_None, // LOG_CLAMPED_r600 = 468
5690 CEFBS_None, // LOG_IEEE_cm = 469
5691 CEFBS_None, // LOG_IEEE_eg = 470
5692 CEFBS_None, // LOG_IEEE_r600 = 471
5693 CEFBS_None, // LOOP_BREAK_EG = 472
5694 CEFBS_None, // LOOP_BREAK_R600 = 473
5695 CEFBS_None, // LSHL_eg = 474
5696 CEFBS_None, // LSHL_r600 = 475
5697 CEFBS_None, // LSHR_eg = 476
5698 CEFBS_None, // LSHR_r600 = 477
5699 CEFBS_None, // MAX = 478
5700 CEFBS_None, // MAX_DX10 = 479
5701 CEFBS_None, // MAX_INT = 480
5702 CEFBS_None, // MAX_UINT = 481
5703 CEFBS_None, // MIN = 482
5704 CEFBS_None, // MIN_DX10 = 483
5705 CEFBS_None, // MIN_INT = 484
5706 CEFBS_None, // MIN_UINT = 485
5707 CEFBS_None, // MOV = 486
5708 CEFBS_None, // MOVA_INT_eg = 487
5709 CEFBS_None, // MUL = 488
5710 CEFBS_None, // MULADD_IEEE_eg = 489
5711 CEFBS_None, // MULADD_IEEE_r600 = 490
5712 CEFBS_None, // MULADD_INT24_cm = 491
5713 CEFBS_None, // MULADD_UINT24_eg = 492
5714 CEFBS_None, // MULADD_eg = 493
5715 CEFBS_None, // MULADD_r600 = 494
5716 CEFBS_None, // MULHI_INT_cm = 495
5717 CEFBS_None, // MULHI_INT_cm24 = 496
5718 CEFBS_None, // MULHI_INT_eg = 497
5719 CEFBS_None, // MULHI_INT_r600 = 498
5720 CEFBS_None, // MULHI_UINT24_eg = 499
5721 CEFBS_None, // MULHI_UINT_cm = 500
5722 CEFBS_None, // MULHI_UINT_cm24 = 501
5723 CEFBS_None, // MULHI_UINT_eg = 502
5724 CEFBS_None, // MULHI_UINT_r600 = 503
5725 CEFBS_None, // MULLO_INT_cm = 504
5726 CEFBS_None, // MULLO_INT_eg = 505
5727 CEFBS_None, // MULLO_INT_r600 = 506
5728 CEFBS_None, // MULLO_UINT_cm = 507
5729 CEFBS_None, // MULLO_UINT_eg = 508
5730 CEFBS_None, // MULLO_UINT_r600 = 509
5731 CEFBS_None, // MUL_IEEE = 510
5732 CEFBS_None, // MUL_INT24_cm = 511
5733 CEFBS_None, // MUL_LIT_eg = 512
5734 CEFBS_None, // MUL_LIT_r600 = 513
5735 CEFBS_None, // MUL_UINT24_eg = 514
5736 CEFBS_None, // NOT_INT = 515
5737 CEFBS_None, // OR_INT = 516
5738 CEFBS_None, // PAD = 517
5739 CEFBS_None, // POP_EG = 518
5740 CEFBS_None, // POP_R600 = 519
5741 CEFBS_None, // PRED_SETE = 520
5742 CEFBS_None, // PRED_SETE_INT = 521
5743 CEFBS_None, // PRED_SETGE = 522
5744 CEFBS_None, // PRED_SETGE_INT = 523
5745 CEFBS_None, // PRED_SETGT = 524
5746 CEFBS_None, // PRED_SETGT_INT = 525
5747 CEFBS_None, // PRED_SETNE = 526
5748 CEFBS_None, // PRED_SETNE_INT = 527
5749 CEFBS_None, // R600_ExportBuf = 528
5750 CEFBS_None, // R600_ExportSwz = 529
5751 CEFBS_None, // RAT_ATOMIC_ADD_NORET = 530
5752 CEFBS_None, // RAT_ATOMIC_ADD_RTN = 531
5753 CEFBS_None, // RAT_ATOMIC_AND_NORET = 532
5754 CEFBS_None, // RAT_ATOMIC_AND_RTN = 533
5755 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET = 534
5756 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN = 535
5757 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET = 536
5758 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN = 537
5759 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET = 538
5760 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN = 539
5761 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET = 540
5762 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN = 541
5763 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET = 542
5764 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN = 543
5765 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET = 544
5766 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN = 545
5767 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET = 546
5768 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN = 547
5769 CEFBS_None, // RAT_ATOMIC_OR_NORET = 548
5770 CEFBS_None, // RAT_ATOMIC_OR_RTN = 549
5771 CEFBS_None, // RAT_ATOMIC_RSUB_NORET = 550
5772 CEFBS_None, // RAT_ATOMIC_RSUB_RTN = 551
5773 CEFBS_None, // RAT_ATOMIC_SUB_NORET = 552
5774 CEFBS_None, // RAT_ATOMIC_SUB_RTN = 553
5775 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET = 554
5776 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN = 555
5777 CEFBS_None, // RAT_ATOMIC_XOR_NORET = 556
5778 CEFBS_None, // RAT_ATOMIC_XOR_RTN = 557
5779 CEFBS_None, // RAT_MSKOR = 558
5780 CEFBS_None, // RAT_STORE_DWORD128 = 559
5781 CEFBS_None, // RAT_STORE_DWORD32 = 560
5782 CEFBS_None, // RAT_STORE_DWORD64 = 561
5783 CEFBS_None, // RAT_STORE_TYPED_cm = 562
5784 CEFBS_None, // RAT_STORE_TYPED_eg = 563
5785 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg = 564
5786 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg = 565
5787 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg = 566
5788 CEFBS_None, // RECIPSQRT_CLAMPED_cm = 567
5789 CEFBS_None, // RECIPSQRT_CLAMPED_eg = 568
5790 CEFBS_None, // RECIPSQRT_CLAMPED_r600 = 569
5791 CEFBS_None, // RECIPSQRT_IEEE_cm = 570
5792 CEFBS_None, // RECIPSQRT_IEEE_eg = 571
5793 CEFBS_None, // RECIPSQRT_IEEE_r600 = 572
5794 CEFBS_None, // RECIP_CLAMPED_cm = 573
5795 CEFBS_None, // RECIP_CLAMPED_eg = 574
5796 CEFBS_None, // RECIP_CLAMPED_r600 = 575
5797 CEFBS_None, // RECIP_IEEE_cm = 576
5798 CEFBS_None, // RECIP_IEEE_eg = 577
5799 CEFBS_None, // RECIP_IEEE_r600 = 578
5800 CEFBS_None, // RECIP_UINT_eg = 579
5801 CEFBS_None, // RECIP_UINT_r600 = 580
5802 CEFBS_None, // RNDNE = 581
5803 CEFBS_None, // SETE = 582
5804 CEFBS_None, // SETE_DX10 = 583
5805 CEFBS_None, // SETE_INT = 584
5806 CEFBS_None, // SETGE_DX10 = 585
5807 CEFBS_None, // SETGE_INT = 586
5808 CEFBS_None, // SETGE_UINT = 587
5809 CEFBS_None, // SETGT_DX10 = 588
5810 CEFBS_None, // SETGT_INT = 589
5811 CEFBS_None, // SETGT_UINT = 590
5812 CEFBS_None, // SETNE_DX10 = 591
5813 CEFBS_None, // SETNE_INT = 592
5814 CEFBS_None, // SGE = 593
5815 CEFBS_None, // SGT = 594
5816 CEFBS_None, // SIN_cm = 595
5817 CEFBS_None, // SIN_eg = 596
5818 CEFBS_None, // SIN_r600 = 597
5819 CEFBS_None, // SIN_r700 = 598
5820 CEFBS_None, // SNE = 599
5821 CEFBS_None, // SUBB_UINT = 600
5822 CEFBS_None, // SUB_INT = 601
5823 CEFBS_None, // TEX_GET_GRADIENTS_H = 602
5824 CEFBS_None, // TEX_GET_GRADIENTS_V = 603
5825 CEFBS_None, // TEX_GET_TEXTURE_RESINFO = 604
5826 CEFBS_None, // TEX_LD = 605
5827 CEFBS_None, // TEX_LDPTR = 606
5828 CEFBS_None, // TEX_SAMPLE = 607
5829 CEFBS_None, // TEX_SAMPLE_C = 608
5830 CEFBS_None, // TEX_SAMPLE_C_G = 609
5831 CEFBS_None, // TEX_SAMPLE_C_L = 610
5832 CEFBS_None, // TEX_SAMPLE_C_LB = 611
5833 CEFBS_None, // TEX_SAMPLE_G = 612
5834 CEFBS_None, // TEX_SAMPLE_L = 613
5835 CEFBS_None, // TEX_SAMPLE_LB = 614
5836 CEFBS_None, // TEX_SET_GRADIENTS_H = 615
5837 CEFBS_None, // TEX_SET_GRADIENTS_V = 616
5838 CEFBS_None, // TEX_VTX_CONSTBUF = 617
5839 CEFBS_None, // TEX_VTX_TEXBUF = 618
5840 CEFBS_None, // TRUNC = 619
5841 CEFBS_None, // UINT_TO_FLT_eg = 620
5842 CEFBS_None, // UINT_TO_FLT_r600 = 621
5843 CEFBS_None, // VTX_READ_128_cm = 622
5844 CEFBS_None, // VTX_READ_128_eg = 623
5845 CEFBS_None, // VTX_READ_16_cm = 624
5846 CEFBS_None, // VTX_READ_16_eg = 625
5847 CEFBS_None, // VTX_READ_32_cm = 626
5848 CEFBS_None, // VTX_READ_32_eg = 627
5849 CEFBS_None, // VTX_READ_64_cm = 628
5850 CEFBS_None, // VTX_READ_64_eg = 629
5851 CEFBS_None, // VTX_READ_8_cm = 630
5852 CEFBS_None, // VTX_READ_8_eg = 631
5853 CEFBS_None, // WHILE_LOOP_EG = 632
5854 CEFBS_None, // WHILE_LOOP_R600 = 633
5855 CEFBS_None, // XOR_INT = 634
5856 };
5857
5858 assert(Opcode < 635);
5859 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
5860}
5861
5862} // end namespace R600_MC
5863} // end namespace llvm
5864#endif // GET_COMPUTE_FEATURES
5865
5866#ifdef GET_AVAILABLE_OPCODE_CHECKER
5867#undef GET_AVAILABLE_OPCODE_CHECKER
5868namespace llvm {
5869namespace R600_MC {
5870bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
5871 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
5872 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
5873 FeatureBitset MissingFeatures =
5874 (AvailableFeatures & RequiredFeatures) ^
5875 RequiredFeatures;
5876 return !MissingFeatures.any();
5877}
5878} // end namespace R600_MC
5879} // end namespace llvm
5880#endif // GET_AVAILABLE_OPCODE_CHECKER
5881
5882#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
5883#undef ENABLE_INSTR_PREDICATE_VERIFIER
5884#include <sstream>
5885
5886namespace llvm {
5887namespace R600_MC {
5888
5889#ifndef NDEBUG
5890static const char *SubtargetFeatureNames[] = {
5891 nullptr
5892};
5893
5894#endif // NDEBUG
5895
5896void verifyInstructionPredicates(
5897 unsigned Opcode, const FeatureBitset &Features) {
5898#ifndef NDEBUG
5899 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
5900 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
5901 FeatureBitset MissingFeatures =
5902 (AvailableFeatures & RequiredFeatures) ^
5903 RequiredFeatures;
5904 if (MissingFeatures.any()) {
5905 std::ostringstream Msg;
5906 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
5907 << " instruction but the ";
5908 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
5909 if (MissingFeatures.test(i))
5910 Msg << SubtargetFeatureNames[i] << " ";
5911 Msg << "predicate(s) are not met";
5912 report_fatal_error(Msg.str().c_str());
5913 }
5914#endif // NDEBUG
5915}
5916} // end namespace R600_MC
5917} // end namespace llvm
5918#endif // ENABLE_INSTR_PREDICATE_VERIFIER
5919
5920#ifdef GET_INSTRMAP_INFO
5921#undef GET_INSTRMAP_INFO
5922namespace llvm {
5923
5924namespace R600 {
5925
5926enum DisableEncoding {
5927 DisableEncoding_
5928};
5929
5930// getLDSNoRetOp
5931LLVM_READONLY
5932int getLDSNoRetOp(uint16_t Opcode) {
5933static const uint16_t getLDSNoRetOpTable[][2] = {
5934 { R600::LDS_ADD_RET, R600::LDS_ADD },
5935 { R600::LDS_AND_RET, R600::LDS_AND },
5936 { R600::LDS_MAX_INT_RET, R600::LDS_MAX_INT },
5937 { R600::LDS_MAX_UINT_RET, R600::LDS_MAX_UINT },
5938 { R600::LDS_MIN_INT_RET, R600::LDS_MIN_INT },
5939 { R600::LDS_MIN_UINT_RET, R600::LDS_MIN_UINT },
5940 { R600::LDS_OR_RET, R600::LDS_OR },
5941 { R600::LDS_SUB_RET, R600::LDS_SUB },
5942 { R600::LDS_WRXCHG_RET, R600::LDS_WRXCHG },
5943 { R600::LDS_XOR_RET, R600::LDS_XOR },
5944}; // End of getLDSNoRetOpTable
5945
5946 unsigned mid;
5947 unsigned start = 0;
5948 unsigned end = 10;
5949 while (start < end) {
5950 mid = start + (end - start) / 2;
5951 if (Opcode == getLDSNoRetOpTable[mid][0]) {
5952 break;
5953 }
5954 if (Opcode < getLDSNoRetOpTable[mid][0])
5955 end = mid;
5956 else
5957 start = mid + 1;
5958 }
5959 if (start == end)
5960 return -1; // Instruction doesn't exist in this table.
5961
5962 return getLDSNoRetOpTable[mid][1];
5963}
5964
5965} // end namespace R600
5966} // end namespace llvm
5967#endif // GET_INSTRMAP_INFO
5968
5969