1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace R600 {
15enum {
16 FeatureCFALUBug = 0,
17 FeatureCaymanISA = 1,
18 FeatureEvergreen = 2,
19 FeatureFMA = 3,
20 FeatureFP64 = 4,
21 FeatureFetchLimit8 = 5,
22 FeatureFetchLimit16 = 6,
23 FeatureLocalMemorySize32768 = 7,
24 FeatureLocalMemorySize65536 = 8,
25 FeatureNorthernIslands = 9,
26 FeaturePromoteAlloca = 10,
27 FeatureR600 = 11,
28 FeatureR600ALUInst = 12,
29 FeatureR700 = 13,
30 FeatureVertexCache = 14,
31 FeatureWavefrontSize16 = 15,
32 FeatureWavefrontSize32 = 16,
33 FeatureWavefrontSize64 = 17,
34 NumSubtargetFeatures = 18
35};
36} // end namespace R600
37} // end namespace llvm
38
39#endif // GET_SUBTARGETINFO_ENUM
40
41
42#ifdef GET_SUBTARGETINFO_MACRO
43GET_SUBTARGETINFO_MACRO(CFALUBug, false, cFALUBug)
44GET_SUBTARGETINFO_MACRO(CaymanISA, false, caymanISA)
45GET_SUBTARGETINFO_MACRO(EnablePromoteAlloca, false, enablePromoteAlloca)
46GET_SUBTARGETINFO_MACRO(FMA, false, fMA)
47GET_SUBTARGETINFO_MACRO(FP64, false, fP64)
48GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
49GET_SUBTARGETINFO_MACRO(R600ALUInst, true, r600ALUInst)
50#undef GET_SUBTARGETINFO_MACRO
51#endif // GET_SUBTARGETINFO_MACRO
52
53
54#ifdef GET_SUBTARGETINFO_MC_DESC
55#undef GET_SUBTARGETINFO_MC_DESC
56
57namespace llvm {
58// Sorted (by key) array of values for CPU features.
59extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
60 { "HasVertexCache", "Specify use of dedicated vertex cache", R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
61 { "R600ALUInst", "Older version of ALU instructions encoding", R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
62 { "caymanISA", "Use Cayman ISA", R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
63 { "cfalubug", "GPU has CF_ALU bug", R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
64 { "evergreen", "EVERGREEN GPU generation", R600::FeatureEvergreen, { { { 0xc0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
65 { "fetch16", "Limit the maximum number of fetches in a clause to 16", R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
66 { "fetch8", "Limit the maximum number of fetches in a clause to 8", R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
67 { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
68 { "fp64", "Enable double precision operations", R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "localmemorysize32768", "The size of local memory in bytes", R600::FeatureLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "localmemorysize65536", "The size of local memory in bytes", R600::FeatureLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "northern-islands", "NORTHERN_ISLANDS GPU generation", R600::FeatureNorthernIslands, { { { 0x200c0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "promote-alloca", "Enable promote alloca pass", R600::FeaturePromoteAlloca, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "r600", "R600 GPU generation", R600::FeatureR600, { { { 0x1020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "r700", "R700 GPU generation", R600::FeatureR700, { { { 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "wavefrontsize16", "The number of threads per wavefront", R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "wavefrontsize32", "The number of threads per wavefront", R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "wavefrontsize64", "The number of threads per wavefront", R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78};
79
80#ifdef DBGFIELD
81#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
82#endif
83#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
84#define DBGFIELD(x) x,
85#else
86#define DBGFIELD(x)
87#endif
88
89// Functional units for "R600_VLIW5_Itin"
90namespace R600_VLIW5_ItinFU {
91 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
92 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
93 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
94 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
95 const InstrStage::FuncUnits TRANS = 1ULL << 4;
96 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
97} // end namespace R600_VLIW5_ItinFU
98
99// Functional units for "R600_VLIW4_Itin"
100namespace R600_VLIW4_ItinFU {
101 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
102 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
103 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
104 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
105 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
106} // end namespace R600_VLIW4_ItinFU
107
108extern const llvm::InstrStage R600Stages[] = {
109 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
110 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
111 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
112 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
113 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
114 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
115 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
116 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
117 { 0, 0, 0, llvm::InstrStage::Required } // End stages
118};
119extern const unsigned R600OperandCycles[] = {
120 0, // No itinerary
121 0 // End operand cycles
122};
123extern const unsigned R600ForwardingPaths[] = {
124 0, // No itinerary
125 0 // End bypass tables
126};
127
128static const llvm::InstrItinerary R600_VLIW5_Itin[] = {
129 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
130 { 1, 1, 2, 0, 0 }, // 1 NullALU
131 { 1, 2, 3, 0, 0 }, // 2 VecALU
132 { 1, 3, 4, 0, 0 }, // 3 AnyALU
133 { 1, 4, 5, 0, 0 }, // 4 TransALU
134 { 1, 5, 6, 0, 0 }, // 5 XALU
135 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
136};
137
138static const llvm::InstrItinerary R600_VLIW4_Itin[] = {
139 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
140 { 1, 6, 7, 0, 0 }, // 1 NullALU
141 { 1, 7, 8, 0, 0 }, // 2 VecALU
142 { 1, 7, 8, 0, 0 }, // 3 AnyALU
143 { 1, 6, 7, 0, 0 }, // 4 TransALU
144 { 0, 0, 0, 0, 0 }, // 5 XALU
145 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
146};
147
148// ===============================================================
149// Data tables for the new per-operand machine model.
150
151// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
152extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
153 { 0, 0, 0 }, // Invalid
154}; // R600WriteProcResTable
155
156// {Cycles, WriteResourceID}
157extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
158 { 0, 0}, // Invalid
159}; // R600WriteLatencyTable
160
161// {UseIdx, WriteResourceID, Cycles}
162extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
163 {0, 0, 0}, // Invalid
164}; // R600ReadAdvanceTable
165
166#undef DBGFIELD
167
168static const llvm::MCSchedModel NoSchedModel = {
169 MCSchedModel::DefaultIssueWidth,
170 MCSchedModel::DefaultMicroOpBufferSize,
171 MCSchedModel::DefaultLoopMicroOpBufferSize,
172 MCSchedModel::DefaultLoadLatency,
173 MCSchedModel::DefaultHighLatency,
174 MCSchedModel::DefaultMispredictPenalty,
175 false, // PostRAScheduler
176 false, // CompleteModel
177 false, // EnableIntervals
178 0, // Processor ID
179 nullptr, nullptr, 0, 0, // No instruction-level machine model.
180 nullptr, // No Itinerary
181 nullptr // No extra processor descriptor
182};
183
184static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
185 MCSchedModel::DefaultIssueWidth,
186 MCSchedModel::DefaultMicroOpBufferSize,
187 MCSchedModel::DefaultLoopMicroOpBufferSize,
188 MCSchedModel::DefaultLoadLatency,
189 MCSchedModel::DefaultHighLatency,
190 MCSchedModel::DefaultMispredictPenalty,
191 false, // PostRAScheduler
192 false, // CompleteModel
193 false, // EnableIntervals
194 1, // Processor ID
195 nullptr, nullptr, 0, 0, // No instruction-level machine model.
196 R600_VLIW5_Itin,
197 nullptr // No extra processor descriptor
198};
199
200static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
201 MCSchedModel::DefaultIssueWidth,
202 MCSchedModel::DefaultMicroOpBufferSize,
203 MCSchedModel::DefaultLoopMicroOpBufferSize,
204 MCSchedModel::DefaultLoadLatency,
205 MCSchedModel::DefaultHighLatency,
206 MCSchedModel::DefaultMispredictPenalty,
207 false, // PostRAScheduler
208 false, // CompleteModel
209 false, // EnableIntervals
210 2, // Processor ID
211 nullptr, nullptr, 0, 0, // No instruction-level machine model.
212 R600_VLIW4_Itin,
213 nullptr // No extra processor descriptor
214};
215
216// Sorted (by key) array of values for CPU subtype.
217extern const llvm::SubtargetSubTypeKV R600SubTypeKV[] = {
218 { "barts", { { { 0x4201ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
219 { "caicos", { { { 0x201ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
220 { "cayman", { { { 0x20aULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW4_ItinModel },
221 { "cedar", { { { 0x14005ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
222 { "cypress", { { { 0x2400cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
223 { "juniper", { { { 0x24004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
224 { "r600", { { { 0x24800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
225 { "r630", { { { 0x14800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
226 { "redwood", { { { 0x24005ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
227 { "rs880", { { { 0x8800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
228 { "rv670", { { { 0x24800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
229 { "rv710", { { { 0x16000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
230 { "rv730", { { { 0x16000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
231 { "rv770", { { { 0x26000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
232 { "sumo", { { { 0x20005ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
233 { "turks", { { { 0x4201ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
234};
235
236namespace R600_MC {
237unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
238 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
239 // Don't know how to resolve this scheduling class.
240 return 0;
241}
242} // end namespace R600_MC
243
244struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
245 R600GenMCSubtargetInfo(const Triple &TT,
246 StringRef CPU, StringRef TuneCPU, StringRef FS,
247 ArrayRef<SubtargetFeatureKV> PF,
248 ArrayRef<SubtargetSubTypeKV> PD,
249 const MCWriteProcResEntry *WPR,
250 const MCWriteLatencyEntry *WL,
251 const MCReadAdvanceEntry *RA, const InstrStage *IS,
252 const unsigned *OC, const unsigned *FP) :
253 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
254 WPR, WL, RA, IS, OC, FP) { }
255
256 unsigned resolveVariantSchedClass(unsigned SchedClass,
257 const MCInst *MI, const MCInstrInfo *MCII,
258 unsigned CPUID) const override {
259 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
260 }
261};
262
263static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
264 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, R600FeatureKV, R600SubTypeKV,
265 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
266 R600Stages, R600OperandCycles, R600ForwardingPaths);
267}
268
269} // end namespace llvm
270
271#endif // GET_SUBTARGETINFO_MC_DESC
272
273
274#ifdef GET_SUBTARGETINFO_TARGET_DESC
275#undef GET_SUBTARGETINFO_TARGET_DESC
276
277#include "llvm/Support/Debug.h"
278#include "llvm/Support/raw_ostream.h"
279
280// ParseSubtargetFeatures - Parses features string setting specified
281// subtarget options.
282void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
283 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
284 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
285 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
286 InitMCProcessorInfo(CPU, TuneCPU, FS);
287 const FeatureBitset &Bits = getFeatureBits();
288 if (Bits[R600::FeatureCFALUBug]) CFALUBug = true;
289 if (Bits[R600::FeatureCaymanISA]) CaymanISA = true;
290 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
291 if (Bits[R600::FeatureFMA]) FMA = true;
292 if (Bits[R600::FeatureFP64]) FP64 = true;
293 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
294 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
295 if (Bits[R600::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
296 if (Bits[R600::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
297 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
298 if (Bits[R600::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
299 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
300 if (Bits[R600::FeatureR600ALUInst]) R600ALUInst = false;
301 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
302 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
303 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
304 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
305 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
306}
307#endif // GET_SUBTARGETINFO_TARGET_DESC
308
309
310#ifdef GET_SUBTARGETINFO_HEADER
311#undef GET_SUBTARGETINFO_HEADER
312
313namespace llvm {
314class DFAPacketizer;
315namespace R600_MC {
316unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
317} // end namespace R600_MC
318
319struct R600GenSubtargetInfo : public TargetSubtargetInfo {
320 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
321public:
322 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
323 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
324 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
325};
326} // end namespace llvm
327
328#endif // GET_SUBTARGETINFO_HEADER
329
330
331#ifdef GET_SUBTARGETINFO_CTOR
332#undef GET_SUBTARGETINFO_CTOR
333
334#include "llvm/CodeGen/TargetSchedule.h"
335
336namespace llvm {
337extern const llvm::SubtargetFeatureKV R600FeatureKV[];
338extern const llvm::SubtargetSubTypeKV R600SubTypeKV[];
339extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
340extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
341extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
342extern const llvm::InstrStage R600Stages[];
343extern const unsigned R600OperandCycles[];
344extern const unsigned R600ForwardingPaths[];
345R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
346 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(R600FeatureKV, 18), ArrayRef(R600SubTypeKV, 16),
347 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
348 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
349
350unsigned R600GenSubtargetInfo
351::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
352 report_fatal_error("Expected a variant SchedClass");
353} // R600GenSubtargetInfo::resolveSchedClass
354
355unsigned R600GenSubtargetInfo
356::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
357 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
358} // R600GenSubtargetInfo::resolveVariantSchedClass
359
360} // end namespace llvm
361
362#endif // GET_SUBTARGETINFO_CTOR
363
364
365#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
366#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
367
368#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
369
370
371#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
372#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
373
374#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
375
376