1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: ARM.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 SmallVectorImpl<NearMissInfo> *NearMisses,
25 bool matchingInlineAsm,
26 unsigned VariantID = 0);
27 ParseStatus MatchOperandParserImpl(
28 OperandVector &Operands,
29 StringRef Mnemonic,
30 bool ParseForAllFeatures = false);
31 ParseStatus tryCustomParseOperand(
32 OperandVector &Operands,
33 unsigned MCK);
34
35#endif // GET_ASSEMBLER_HEADER
36
37
38#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
39#undef GET_OPERAND_DIAGNOSTIC_TYPES
40
41 Match_AlignedMemory16,
42 Match_AlignedMemory32,
43 Match_AlignedMemory64,
44 Match_AlignedMemory64or128,
45 Match_AlignedMemory64or128or256,
46 Match_AlignedMemoryNone,
47 Match_ComplexRotationEven,
48 Match_ComplexRotationOdd,
49 Match_CondCodeRestrictedFP,
50 Match_CondCodeRestrictedI,
51 Match_CondCodeRestrictedS,
52 Match_CondCodeRestrictedU,
53 Match_DPR,
54 Match_DPR_8,
55 Match_DPR_RegList,
56 Match_DPR_VFP2,
57 Match_DupAlignedMemory16,
58 Match_DupAlignedMemory32,
59 Match_DupAlignedMemory64,
60 Match_DupAlignedMemory64or128,
61 Match_DupAlignedMemoryNone,
62 Match_GPR,
63 Match_GPRnoip,
64 Match_GPRnopc,
65 Match_GPRnosp,
66 Match_GPRsp,
67 Match_GPRwithAPSR,
68 Match_GPRwithAPSR_NZCVnosp,
69 Match_GPRwithZR,
70 Match_GPRwithZRnosp,
71 Match_Imm0_1,
72 Match_Imm0_15,
73 Match_Imm0_239,
74 Match_Imm0_255,
75 Match_Imm0_255Expr,
76 Match_Imm0_3,
77 Match_Imm0_31,
78 Match_Imm0_32,
79 Match_Imm0_4095,
80 Match_Imm0_63,
81 Match_Imm0_65535,
82 Match_Imm0_65535Expr,
83 Match_Imm0_7,
84 Match_Imm11b,
85 Match_Imm12b,
86 Match_Imm13b,
87 Match_Imm16,
88 Match_Imm1_15,
89 Match_Imm1_31,
90 Match_Imm1_7,
91 Match_Imm24bit,
92 Match_Imm256_65535Expr,
93 Match_Imm32,
94 Match_Imm3b,
95 Match_Imm4b,
96 Match_Imm6b,
97 Match_Imm7b,
98 Match_Imm8,
99 Match_Imm8_255,
100 Match_Imm9b,
101 Match_ImmRange1_16,
102 Match_ImmRange1_32,
103 Match_ImmThumbSR,
104 Match_LELabel,
105 Match_MVELongShift,
106 Match_MVEShiftImm1_15,
107 Match_MVEShiftImm1_7,
108 Match_MVEVcvtImm16,
109 Match_MVEVcvtImm32,
110 Match_MveSaturate,
111 Match_PKHLSLImm,
112 Match_QPR,
113 Match_QPR_8,
114 Match_QPR_VFP2,
115 Match_SPR,
116 Match_SPRRegList,
117 Match_SPR_8,
118 Match_SetEndImm,
119 Match_ShrImm16,
120 Match_ShrImm32,
121 Match_ShrImm64,
122 Match_ShrImm8,
123 Match_VIDUP_imm,
124 Match_VecListFourMQ,
125 Match_VecListTwoMQ,
126 Match_WLSLabel,
127 Match_hGPR,
128 Match_rGPR,
129 Match_tGPR,
130 Match_tGPREven,
131 Match_tGPROdd,
132 END_OPERAND_DIAGNOSTIC_TYPES
133#endif // GET_OPERAND_DIAGNOSTIC_TYPES
134
135
136#ifdef GET_REGISTER_MATCHER
137#undef GET_REGISTER_MATCHER
138
139// Bits for subtarget features that participate in instruction matching.
140enum SubtargetFeatureBits : uint8_t {
141 Feature_HasV4TBit = 35,
142 Feature_HasV5TBit = 36,
143 Feature_HasV5TEBit = 37,
144 Feature_HasV6Bit = 38,
145 Feature_HasV6MBit = 40,
146 Feature_HasV8MBaselineBit = 45,
147 Feature_HasV8MMainlineBit = 46,
148 Feature_HasV8_1MMainlineBit = 47,
149 Feature_HasMVEIntBit = 26,
150 Feature_HasMVEFloatBit = 25,
151 Feature_HasCDEBit = 4,
152 Feature_HasFPRegsBit = 18,
153 Feature_HasFPRegs16Bit = 19,
154 Feature_HasNoFPRegs16Bit = 29,
155 Feature_HasFPRegs64Bit = 20,
156 Feature_HasFPRegsV8_1MBit = 21,
157 Feature_HasV6T2Bit = 41,
158 Feature_HasV6KBit = 39,
159 Feature_HasV7Bit = 42,
160 Feature_HasV8Bit = 44,
161 Feature_PreV8Bit = 64,
162 Feature_HasV8_1aBit = 48,
163 Feature_HasV8_2aBit = 49,
164 Feature_HasV8_3aBit = 50,
165 Feature_HasV8_4aBit = 51,
166 Feature_HasV8_5aBit = 52,
167 Feature_HasV8_6aBit = 53,
168 Feature_HasV8_7aBit = 54,
169 Feature_HasVFP2Bit = 55,
170 Feature_HasVFP3Bit = 56,
171 Feature_HasVFP4Bit = 57,
172 Feature_HasDPVFPBit = 10,
173 Feature_HasFPARMv8Bit = 17,
174 Feature_HasNEONBit = 28,
175 Feature_HasSHA2Bit = 33,
176 Feature_HasAESBit = 1,
177 Feature_HasCryptoBit = 7,
178 Feature_HasDotProdBit = 14,
179 Feature_HasCRCBit = 6,
180 Feature_HasRASBit = 31,
181 Feature_HasLOBBit = 23,
182 Feature_HasPACBTIBit = 30,
183 Feature_HasFP16Bit = 15,
184 Feature_HasFullFP16Bit = 22,
185 Feature_HasFP16FMLBit = 16,
186 Feature_HasBF16Bit = 3,
187 Feature_HasMatMulInt8Bit = 27,
188 Feature_HasDivideInThumbBit = 13,
189 Feature_HasDivideInARMBit = 12,
190 Feature_HasDSPBit = 11,
191 Feature_HasDBBit = 8,
192 Feature_HasDFBBit = 9,
193 Feature_HasV7ClrexBit = 43,
194 Feature_HasAcquireReleaseBit = 2,
195 Feature_HasMPBit = 24,
196 Feature_HasVirtualizationBit = 58,
197 Feature_HasTrustZoneBit = 34,
198 Feature_Has8MSecExtBit = 0,
199 Feature_IsThumbBit = 62,
200 Feature_IsThumb2Bit = 63,
201 Feature_IsMClassBit = 60,
202 Feature_IsNotMClassBit = 61,
203 Feature_IsARMBit = 59,
204 Feature_UseNaClTrapBit = 65,
205 Feature_UseNegativeImmediatesBit = 66,
206 Feature_HasSBBit = 32,
207 Feature_HasCLRBHBBit = 5,
208};
209
210static MCRegister MatchRegisterName(StringRef Name) {
211 switch (Name.size()) {
212 default: break;
213 case 2: // 45 strings to match.
214 switch (Name[0]) {
215 default: break;
216 case 'd': // 10 strings to match.
217 switch (Name[1]) {
218 default: break;
219 case '0': // 1 string to match.
220 return ARM::D0; // "d0"
221 case '1': // 1 string to match.
222 return ARM::D1; // "d1"
223 case '2': // 1 string to match.
224 return ARM::D2; // "d2"
225 case '3': // 1 string to match.
226 return ARM::D3; // "d3"
227 case '4': // 1 string to match.
228 return ARM::D4; // "d4"
229 case '5': // 1 string to match.
230 return ARM::D5; // "d5"
231 case '6': // 1 string to match.
232 return ARM::D6; // "d6"
233 case '7': // 1 string to match.
234 return ARM::D7; // "d7"
235 case '8': // 1 string to match.
236 return ARM::D8; // "d8"
237 case '9': // 1 string to match.
238 return ARM::D9; // "d9"
239 }
240 break;
241 case 'l': // 1 string to match.
242 if (Name[1] != 'r')
243 break;
244 return ARM::LR; // "lr"
245 case 'p': // 2 strings to match.
246 switch (Name[1]) {
247 default: break;
248 case '0': // 1 string to match.
249 return ARM::P0; // "p0"
250 case 'c': // 1 string to match.
251 return ARM::PC; // "pc"
252 }
253 break;
254 case 'q': // 10 strings to match.
255 switch (Name[1]) {
256 default: break;
257 case '0': // 1 string to match.
258 return ARM::Q0; // "q0"
259 case '1': // 1 string to match.
260 return ARM::Q1; // "q1"
261 case '2': // 1 string to match.
262 return ARM::Q2; // "q2"
263 case '3': // 1 string to match.
264 return ARM::Q3; // "q3"
265 case '4': // 1 string to match.
266 return ARM::Q4; // "q4"
267 case '5': // 1 string to match.
268 return ARM::Q5; // "q5"
269 case '6': // 1 string to match.
270 return ARM::Q6; // "q6"
271 case '7': // 1 string to match.
272 return ARM::Q7; // "q7"
273 case '8': // 1 string to match.
274 return ARM::Q8; // "q8"
275 case '9': // 1 string to match.
276 return ARM::Q9; // "q9"
277 }
278 break;
279 case 'r': // 10 strings to match.
280 switch (Name[1]) {
281 default: break;
282 case '0': // 1 string to match.
283 return ARM::R0; // "r0"
284 case '1': // 1 string to match.
285 return ARM::R1; // "r1"
286 case '2': // 1 string to match.
287 return ARM::R2; // "r2"
288 case '3': // 1 string to match.
289 return ARM::R3; // "r3"
290 case '4': // 1 string to match.
291 return ARM::R4; // "r4"
292 case '5': // 1 string to match.
293 return ARM::R5; // "r5"
294 case '6': // 1 string to match.
295 return ARM::R6; // "r6"
296 case '7': // 1 string to match.
297 return ARM::R7; // "r7"
298 case '8': // 1 string to match.
299 return ARM::R8; // "r8"
300 case '9': // 1 string to match.
301 return ARM::R9; // "r9"
302 }
303 break;
304 case 's': // 11 strings to match.
305 switch (Name[1]) {
306 default: break;
307 case '0': // 1 string to match.
308 return ARM::S0; // "s0"
309 case '1': // 1 string to match.
310 return ARM::S1; // "s1"
311 case '2': // 1 string to match.
312 return ARM::S2; // "s2"
313 case '3': // 1 string to match.
314 return ARM::S3; // "s3"
315 case '4': // 1 string to match.
316 return ARM::S4; // "s4"
317 case '5': // 1 string to match.
318 return ARM::S5; // "s5"
319 case '6': // 1 string to match.
320 return ARM::S6; // "s6"
321 case '7': // 1 string to match.
322 return ARM::S7; // "s7"
323 case '8': // 1 string to match.
324 return ARM::S8; // "s8"
325 case '9': // 1 string to match.
326 return ARM::S9; // "s9"
327 case 'p': // 1 string to match.
328 return ARM::SP; // "sp"
329 }
330 break;
331 case 'z': // 1 string to match.
332 if (Name[1] != 'r')
333 break;
334 return ARM::ZR; // "zr"
335 }
336 break;
337 case 3: // 54 strings to match.
338 switch (Name[0]) {
339 default: break;
340 case 'd': // 22 strings to match.
341 switch (Name[1]) {
342 default: break;
343 case '1': // 10 strings to match.
344 switch (Name[2]) {
345 default: break;
346 case '0': // 1 string to match.
347 return ARM::D10; // "d10"
348 case '1': // 1 string to match.
349 return ARM::D11; // "d11"
350 case '2': // 1 string to match.
351 return ARM::D12; // "d12"
352 case '3': // 1 string to match.
353 return ARM::D13; // "d13"
354 case '4': // 1 string to match.
355 return ARM::D14; // "d14"
356 case '5': // 1 string to match.
357 return ARM::D15; // "d15"
358 case '6': // 1 string to match.
359 return ARM::D16; // "d16"
360 case '7': // 1 string to match.
361 return ARM::D17; // "d17"
362 case '8': // 1 string to match.
363 return ARM::D18; // "d18"
364 case '9': // 1 string to match.
365 return ARM::D19; // "d19"
366 }
367 break;
368 case '2': // 10 strings to match.
369 switch (Name[2]) {
370 default: break;
371 case '0': // 1 string to match.
372 return ARM::D20; // "d20"
373 case '1': // 1 string to match.
374 return ARM::D21; // "d21"
375 case '2': // 1 string to match.
376 return ARM::D22; // "d22"
377 case '3': // 1 string to match.
378 return ARM::D23; // "d23"
379 case '4': // 1 string to match.
380 return ARM::D24; // "d24"
381 case '5': // 1 string to match.
382 return ARM::D25; // "d25"
383 case '6': // 1 string to match.
384 return ARM::D26; // "d26"
385 case '7': // 1 string to match.
386 return ARM::D27; // "d27"
387 case '8': // 1 string to match.
388 return ARM::D28; // "d28"
389 case '9': // 1 string to match.
390 return ARM::D29; // "d29"
391 }
392 break;
393 case '3': // 2 strings to match.
394 switch (Name[2]) {
395 default: break;
396 case '0': // 1 string to match.
397 return ARM::D30; // "d30"
398 case '1': // 1 string to match.
399 return ARM::D31; // "d31"
400 }
401 break;
402 }
403 break;
404 case 'q': // 6 strings to match.
405 if (Name[1] != '1')
406 break;
407 switch (Name[2]) {
408 default: break;
409 case '0': // 1 string to match.
410 return ARM::Q10; // "q10"
411 case '1': // 1 string to match.
412 return ARM::Q11; // "q11"
413 case '2': // 1 string to match.
414 return ARM::Q12; // "q12"
415 case '3': // 1 string to match.
416 return ARM::Q13; // "q13"
417 case '4': // 1 string to match.
418 return ARM::Q14; // "q14"
419 case '5': // 1 string to match.
420 return ARM::Q15; // "q15"
421 }
422 break;
423 case 'r': // 3 strings to match.
424 if (Name[1] != '1')
425 break;
426 switch (Name[2]) {
427 default: break;
428 case '0': // 1 string to match.
429 return ARM::R10; // "r10"
430 case '1': // 1 string to match.
431 return ARM::R11; // "r11"
432 case '2': // 1 string to match.
433 return ARM::R12; // "r12"
434 }
435 break;
436 case 's': // 22 strings to match.
437 switch (Name[1]) {
438 default: break;
439 case '1': // 10 strings to match.
440 switch (Name[2]) {
441 default: break;
442 case '0': // 1 string to match.
443 return ARM::S10; // "s10"
444 case '1': // 1 string to match.
445 return ARM::S11; // "s11"
446 case '2': // 1 string to match.
447 return ARM::S12; // "s12"
448 case '3': // 1 string to match.
449 return ARM::S13; // "s13"
450 case '4': // 1 string to match.
451 return ARM::S14; // "s14"
452 case '5': // 1 string to match.
453 return ARM::S15; // "s15"
454 case '6': // 1 string to match.
455 return ARM::S16; // "s16"
456 case '7': // 1 string to match.
457 return ARM::S17; // "s17"
458 case '8': // 1 string to match.
459 return ARM::S18; // "s18"
460 case '9': // 1 string to match.
461 return ARM::S19; // "s19"
462 }
463 break;
464 case '2': // 10 strings to match.
465 switch (Name[2]) {
466 default: break;
467 case '0': // 1 string to match.
468 return ARM::S20; // "s20"
469 case '1': // 1 string to match.
470 return ARM::S21; // "s21"
471 case '2': // 1 string to match.
472 return ARM::S22; // "s22"
473 case '3': // 1 string to match.
474 return ARM::S23; // "s23"
475 case '4': // 1 string to match.
476 return ARM::S24; // "s24"
477 case '5': // 1 string to match.
478 return ARM::S25; // "s25"
479 case '6': // 1 string to match.
480 return ARM::S26; // "s26"
481 case '7': // 1 string to match.
482 return ARM::S27; // "s27"
483 case '8': // 1 string to match.
484 return ARM::S28; // "s28"
485 case '9': // 1 string to match.
486 return ARM::S29; // "s29"
487 }
488 break;
489 case '3': // 2 strings to match.
490 switch (Name[2]) {
491 default: break;
492 case '0': // 1 string to match.
493 return ARM::S30; // "s30"
494 case '1': // 1 string to match.
495 return ARM::S31; // "s31"
496 }
497 break;
498 }
499 break;
500 case 'v': // 1 string to match.
501 if (memcmp(Name.data()+1, "pr", 2) != 0)
502 break;
503 return ARM::VPR; // "vpr"
504 }
505 break;
506 case 4: // 3 strings to match.
507 switch (Name[0]) {
508 default: break;
509 case 'a': // 1 string to match.
510 if (memcmp(Name.data()+1, "psr", 3) != 0)
511 break;
512 return ARM::APSR; // "apsr"
513 case 'c': // 1 string to match.
514 if (memcmp(Name.data()+1, "psr", 3) != 0)
515 break;
516 return ARM::CPSR; // "cpsr"
517 case 's': // 1 string to match.
518 if (memcmp(Name.data()+1, "psr", 3) != 0)
519 break;
520 return ARM::SPSR; // "spsr"
521 }
522 break;
523 case 5: // 6 strings to match.
524 switch (Name[0]) {
525 default: break;
526 case 'f': // 3 strings to match.
527 if (Name[1] != 'p')
528 break;
529 switch (Name[2]) {
530 default: break;
531 case 'e': // 1 string to match.
532 if (memcmp(Name.data()+3, "xc", 2) != 0)
533 break;
534 return ARM::FPEXC; // "fpexc"
535 case 's': // 2 strings to match.
536 switch (Name[3]) {
537 default: break;
538 case 'c': // 1 string to match.
539 if (Name[4] != 'r')
540 break;
541 return ARM::FPSCR; // "fpscr"
542 case 'i': // 1 string to match.
543 if (Name[4] != 'd')
544 break;
545 return ARM::FPSID; // "fpsid"
546 }
547 break;
548 }
549 break;
550 case 'm': // 3 strings to match.
551 if (memcmp(Name.data()+1, "vfr", 3) != 0)
552 break;
553 switch (Name[4]) {
554 default: break;
555 case '0': // 1 string to match.
556 return ARM::MVFR0; // "mvfr0"
557 case '1': // 1 string to match.
558 return ARM::MVFR1; // "mvfr1"
559 case '2': // 1 string to match.
560 return ARM::MVFR2; // "mvfr2"
561 }
562 break;
563 }
564 break;
565 case 6: // 2 strings to match.
566 if (memcmp(Name.data()+0, "fp", 2) != 0)
567 break;
568 switch (Name[2]) {
569 default: break;
570 case 'c': // 1 string to match.
571 if (memcmp(Name.data()+3, "xts", 3) != 0)
572 break;
573 return ARM::FPCXTS; // "fpcxts"
574 case 'i': // 1 string to match.
575 if (memcmp(Name.data()+3, "nst", 3) != 0)
576 break;
577 return ARM::FPINST; // "fpinst"
578 }
579 break;
580 case 7: // 3 strings to match.
581 switch (Name[0]) {
582 default: break;
583 case 'f': // 2 strings to match.
584 if (Name[1] != 'p')
585 break;
586 switch (Name[2]) {
587 default: break;
588 case 'c': // 1 string to match.
589 if (memcmp(Name.data()+3, "xtns", 4) != 0)
590 break;
591 return ARM::FPCXTNS; // "fpcxtns"
592 case 'i': // 1 string to match.
593 if (memcmp(Name.data()+3, "nst2", 4) != 0)
594 break;
595 return ARM::FPINST2; // "fpinst2"
596 }
597 break;
598 case 'i': // 1 string to match.
599 if (memcmp(Name.data()+1, "tstate", 6) != 0)
600 break;
601 return ARM::ITSTATE; // "itstate"
602 }
603 break;
604 case 9: // 1 string to match.
605 if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
606 break;
607 return ARM::APSR_NZCV; // "apsr_nzcv"
608 case 10: // 1 string to match.
609 if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
610 break;
611 return ARM::FPSCR_NZCV; // "fpscr_nzcv"
612 case 12: // 2 strings to match.
613 switch (Name[0]) {
614 default: break;
615 case 'f': // 1 string to match.
616 if (memcmp(Name.data()+1, "pscr_nzcvqc", 11) != 0)
617 break;
618 return ARM::FPSCR_NZCVQC; // "fpscr_nzcvqc"
619 case 'r': // 1 string to match.
620 if (memcmp(Name.data()+1, "a_auth_code", 11) != 0)
621 break;
622 return ARM::RA_AUTH_CODE; // "ra_auth_code"
623 }
624 break;
625 }
626 return ARM::NoRegister;
627}
628
629#endif // GET_REGISTER_MATCHER
630
631
632#ifdef GET_SUBTARGET_FEATURE_NAME
633#undef GET_SUBTARGET_FEATURE_NAME
634
635// User-level names for subtarget features that participate in
636// instruction matching.
637static const char *getSubtargetFeatureName(uint64_t Val) {
638 switch(Val) {
639 case Feature_HasV4TBit: return "armv4t";
640 case Feature_HasV5TBit: return "armv5t";
641 case Feature_HasV5TEBit: return "armv5te";
642 case Feature_HasV6Bit: return "armv6";
643 case Feature_HasV6MBit: return "armv6m or armv6t2";
644 case Feature_HasV8MBaselineBit: return "armv8m.base";
645 case Feature_HasV8MMainlineBit: return "armv8m.main";
646 case Feature_HasV8_1MMainlineBit: return "armv8.1m.main";
647 case Feature_HasMVEIntBit: return "mve";
648 case Feature_HasMVEFloatBit: return "mve.fp";
649 case Feature_HasCDEBit: return "cde";
650 case Feature_HasFPRegsBit: return "fp registers";
651 case Feature_HasFPRegs16Bit: return "16-bit fp registers";
652 case Feature_HasNoFPRegs16Bit: return "16-bit fp registers";
653 case Feature_HasFPRegs64Bit: return "64-bit fp registers";
654 case Feature_HasFPRegsV8_1MBit: return "armv8.1m.main with FP or MVE";
655 case Feature_HasV6T2Bit: return "armv6t2";
656 case Feature_HasV6KBit: return "armv6k";
657 case Feature_HasV7Bit: return "armv7";
658 case Feature_HasV8Bit: return "armv8";
659 case Feature_PreV8Bit: return "armv7 or earlier";
660 case Feature_HasV8_1aBit: return "armv8.1a";
661 case Feature_HasV8_2aBit: return "armv8.2a";
662 case Feature_HasV8_3aBit: return "armv8.3a";
663 case Feature_HasV8_4aBit: return "armv8.4a";
664 case Feature_HasV8_5aBit: return "armv8.5a";
665 case Feature_HasV8_6aBit: return "armv8.6a";
666 case Feature_HasV8_7aBit: return "armv8.7a";
667 case Feature_HasVFP2Bit: return "VFP2";
668 case Feature_HasVFP3Bit: return "VFP3";
669 case Feature_HasVFP4Bit: return "VFP4";
670 case Feature_HasDPVFPBit: return "double precision VFP";
671 case Feature_HasFPARMv8Bit: return "FPARMv8";
672 case Feature_HasNEONBit: return "NEON";
673 case Feature_HasSHA2Bit: return "sha2";
674 case Feature_HasAESBit: return "aes";
675 case Feature_HasCryptoBit: return "crypto";
676 case Feature_HasDotProdBit: return "dotprod";
677 case Feature_HasCRCBit: return "crc";
678 case Feature_HasRASBit: return "ras";
679 case Feature_HasLOBBit: return "lob";
680 case Feature_HasPACBTIBit: return "pacbti";
681 case Feature_HasFP16Bit: return "half-float conversions";
682 case Feature_HasFullFP16Bit: return "full half-float";
683 case Feature_HasFP16FMLBit: return "full half-float fml";
684 case Feature_HasBF16Bit: return "BFloat16 floating point extension";
685 case Feature_HasMatMulInt8Bit: return "8-bit integer matrix multiply";
686 case Feature_HasDivideInThumbBit: return "divide in THUMB";
687 case Feature_HasDivideInARMBit: return "divide in ARM";
688 case Feature_HasDSPBit: return "dsp";
689 case Feature_HasDBBit: return "data-barriers";
690 case Feature_HasDFBBit: return "full-data-barrier";
691 case Feature_HasV7ClrexBit: return "v7 clrex";
692 case Feature_HasAcquireReleaseBit: return "acquire/release";
693 case Feature_HasMPBit: return "mp-extensions";
694 case Feature_HasVirtualizationBit: return "virtualization-extensions";
695 case Feature_HasTrustZoneBit: return "TrustZone";
696 case Feature_Has8MSecExtBit: return "ARMv8-M Security Extensions";
697 case Feature_IsThumbBit: return "thumb";
698 case Feature_IsThumb2Bit: return "thumb2";
699 case Feature_IsMClassBit: return "armv*m";
700 case Feature_IsNotMClassBit: return "!armv*m";
701 case Feature_IsARMBit: return "arm-mode";
702 case Feature_UseNaClTrapBit: return "NaCl";
703 case Feature_UseNegativeImmediatesBit: return "NegativeImmediates";
704 case Feature_HasSBBit: return "sb";
705 case Feature_HasCLRBHBBit: return "clrbhb";
706 default: return "(unknown)";
707 }
708}
709
710#endif // GET_SUBTARGET_FEATURE_NAME
711
712
713#ifdef GET_MATCHER_IMPLEMENTATION
714#undef GET_MATCHER_IMPLEMENTATION
715
716static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
717 switch (VariantID) {
718 case 0:
719 break;
720 }
721 switch (Mnemonic.size()) {
722 default: break;
723 case 3: // 4 strings to match.
724 switch (Mnemonic[0]) {
725 default: break;
726 case 'r': // 1 string to match.
727 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
728 break;
729 Mnemonic = "rfeia"; // "rfe"
730 return;
731 case 's': // 3 strings to match.
732 switch (Mnemonic[1]) {
733 default: break;
734 case 'm': // 1 string to match.
735 if (Mnemonic[2] != 'i')
736 break;
737 Mnemonic = "smc"; // "smi"
738 return;
739 case 'r': // 1 string to match.
740 if (Mnemonic[2] != 's')
741 break;
742 Mnemonic = "srsia"; // "srs"
743 return;
744 case 'w': // 1 string to match.
745 if (Mnemonic[2] != 'i')
746 break;
747 Mnemonic = "svc"; // "swi"
748 return;
749 }
750 break;
751 }
752 break;
753 case 4: // 10 strings to match.
754 switch (Mnemonic[0]) {
755 default: break;
756 case 'f': // 8 strings to match.
757 switch (Mnemonic[1]) {
758 default: break;
759 case 'l': // 2 strings to match.
760 if (Mnemonic[2] != 'd')
761 break;
762 switch (Mnemonic[3]) {
763 default: break;
764 case 'd': // 1 string to match.
765 if (Features.test(Feature_HasVFP2Bit)) // "fldd"
766 Mnemonic = "vldr";
767 return;
768 case 's': // 1 string to match.
769 if (Features.test(Feature_HasVFP2Bit)) // "flds"
770 Mnemonic = "vldr";
771 return;
772 }
773 break;
774 case 'm': // 4 strings to match.
775 switch (Mnemonic[2]) {
776 default: break;
777 case 'r': // 2 strings to match.
778 switch (Mnemonic[3]) {
779 default: break;
780 case 's': // 1 string to match.
781 if (Features.test(Feature_HasVFP2Bit)) // "fmrs"
782 Mnemonic = "vmov";
783 return;
784 case 'x': // 1 string to match.
785 if (Features.test(Feature_HasVFP2Bit)) // "fmrx"
786 Mnemonic = "vmrs";
787 return;
788 }
789 break;
790 case 's': // 1 string to match.
791 if (Mnemonic[3] != 'r')
792 break;
793 if (Features.test(Feature_HasVFP2Bit)) // "fmsr"
794 Mnemonic = "vmov";
795 return;
796 case 'x': // 1 string to match.
797 if (Mnemonic[3] != 'r')
798 break;
799 if (Features.test(Feature_HasVFP2Bit)) // "fmxr"
800 Mnemonic = "vmsr";
801 return;
802 }
803 break;
804 case 's': // 2 strings to match.
805 if (Mnemonic[2] != 't')
806 break;
807 switch (Mnemonic[3]) {
808 default: break;
809 case 'd': // 1 string to match.
810 if (Features.test(Feature_HasVFP2Bit)) // "fstd"
811 Mnemonic = "vstr";
812 return;
813 case 's': // 1 string to match.
814 if (Features.test(Feature_HasVFP2Bit)) // "fsts"
815 Mnemonic = "vstr";
816 return;
817 }
818 break;
819 }
820 break;
821 case 'v': // 2 strings to match.
822 switch (Mnemonic[1]) {
823 default: break;
824 case 'l': // 1 string to match.
825 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
826 break;
827 Mnemonic = "vldmia"; // "vldm"
828 return;
829 case 's': // 1 string to match.
830 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
831 break;
832 Mnemonic = "vstmia"; // "vstm"
833 return;
834 }
835 break;
836 }
837 break;
838 case 5: // 51 strings to match.
839 switch (Mnemonic[0]) {
840 default: break;
841 case 'f': // 18 strings to match.
842 switch (Mnemonic[1]) {
843 default: break;
844 case 'a': // 2 strings to match.
845 if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
846 break;
847 switch (Mnemonic[4]) {
848 default: break;
849 case 'd': // 1 string to match.
850 if (Features.test(Feature_HasVFP2Bit)) // "faddd"
851 Mnemonic = "vadd.f64";
852 return;
853 case 's': // 1 string to match.
854 if (Features.test(Feature_HasVFP2Bit)) // "fadds"
855 Mnemonic = "vadd.f32";
856 return;
857 }
858 break;
859 case 'c': // 4 strings to match.
860 switch (Mnemonic[2]) {
861 default: break;
862 case 'm': // 2 strings to match.
863 if (Mnemonic[3] != 'p')
864 break;
865 switch (Mnemonic[4]) {
866 default: break;
867 case 'd': // 1 string to match.
868 if (Features.test(Feature_HasVFP2Bit)) // "fcmpd"
869 Mnemonic = "vcmp.f64";
870 return;
871 case 's': // 1 string to match.
872 if (Features.test(Feature_HasVFP2Bit)) // "fcmps"
873 Mnemonic = "vcmp.f32";
874 return;
875 }
876 break;
877 case 'p': // 2 strings to match.
878 if (Mnemonic[3] != 'y')
879 break;
880 switch (Mnemonic[4]) {
881 default: break;
882 case 'd': // 1 string to match.
883 if (Features.test(Feature_HasVFP2Bit)) // "fcpyd"
884 Mnemonic = "vmov.f64";
885 return;
886 case 's': // 1 string to match.
887 if (Features.test(Feature_HasVFP2Bit)) // "fcpys"
888 Mnemonic = "vmov.f32";
889 return;
890 }
891 break;
892 }
893 break;
894 case 'd': // 2 strings to match.
895 if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
896 break;
897 switch (Mnemonic[4]) {
898 default: break;
899 case 'd': // 1 string to match.
900 if (Features.test(Feature_HasVFP2Bit)) // "fdivd"
901 Mnemonic = "vdiv.f64";
902 return;
903 case 's': // 1 string to match.
904 if (Features.test(Feature_HasVFP2Bit)) // "fdivs"
905 Mnemonic = "vdiv.f32";
906 return;
907 }
908 break;
909 case 'm': // 8 strings to match.
910 switch (Mnemonic[2]) {
911 default: break;
912 case 'a': // 2 strings to match.
913 if (Mnemonic[3] != 'c')
914 break;
915 switch (Mnemonic[4]) {
916 default: break;
917 case 'd': // 1 string to match.
918 if (Features.test(Feature_HasVFP2Bit)) // "fmacd"
919 Mnemonic = "vmla.f64";
920 return;
921 case 's': // 1 string to match.
922 if (Features.test(Feature_HasVFP2Bit)) // "fmacs"
923 Mnemonic = "vmla.f32";
924 return;
925 }
926 break;
927 case 'd': // 1 string to match.
928 if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
929 break;
930 if (Features.test(Feature_HasVFP2Bit)) // "fmdrr"
931 Mnemonic = "vmov";
932 return;
933 case 'r': // 3 strings to match.
934 switch (Mnemonic[3]) {
935 default: break;
936 case 'd': // 2 strings to match.
937 switch (Mnemonic[4]) {
938 default: break;
939 case 'd': // 1 string to match.
940 if (Features.test(Feature_HasVFP2Bit)) // "fmrdd"
941 Mnemonic = "vmov";
942 return;
943 case 's': // 1 string to match.
944 if (Features.test(Feature_HasVFP2Bit)) // "fmrds"
945 Mnemonic = "vmov";
946 return;
947 }
948 break;
949 case 'r': // 1 string to match.
950 if (Mnemonic[4] != 'd')
951 break;
952 if (Features.test(Feature_HasVFP2Bit)) // "fmrrd"
953 Mnemonic = "vmov";
954 return;
955 }
956 break;
957 case 'u': // 2 strings to match.
958 if (Mnemonic[3] != 'l')
959 break;
960 switch (Mnemonic[4]) {
961 default: break;
962 case 'd': // 1 string to match.
963 if (Features.test(Feature_HasVFP2Bit)) // "fmuld"
964 Mnemonic = "vmul.f64";
965 return;
966 case 's': // 1 string to match.
967 if (Features.test(Feature_HasVFP2Bit)) // "fmuls"
968 Mnemonic = "vmul.f32";
969 return;
970 }
971 break;
972 }
973 break;
974 case 'n': // 2 strings to match.
975 if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
976 break;
977 switch (Mnemonic[4]) {
978 default: break;
979 case 'd': // 1 string to match.
980 if (Features.test(Feature_HasVFP2Bit)) // "fnegd"
981 Mnemonic = "vneg.f64";
982 return;
983 case 's': // 1 string to match.
984 if (Features.test(Feature_HasVFP2Bit)) // "fnegs"
985 Mnemonic = "vneg.f32";
986 return;
987 }
988 break;
989 }
990 break;
991 case 'l': // 3 strings to match.
992 if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
993 break;
994 switch (Mnemonic[3]) {
995 default: break;
996 case 'e': // 1 string to match.
997 if (Mnemonic[4] != 'a')
998 break;
999 Mnemonic = "ldmdb"; // "ldmea"
1000 return;
1001 case 'f': // 1 string to match.
1002 if (Mnemonic[4] != 'd')
1003 break;
1004 Mnemonic = "ldm"; // "ldmfd"
1005 return;
1006 case 'i': // 1 string to match.
1007 if (Mnemonic[4] != 'a')
1008 break;
1009 Mnemonic = "ldm"; // "ldmia"
1010 return;
1011 }
1012 break;
1013 case 'r': // 4 strings to match.
1014 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
1015 break;
1016 switch (Mnemonic[3]) {
1017 default: break;
1018 case 'e': // 2 strings to match.
1019 switch (Mnemonic[4]) {
1020 default: break;
1021 case 'a': // 1 string to match.
1022 Mnemonic = "rfedb"; // "rfeea"
1023 return;
1024 case 'd': // 1 string to match.
1025 Mnemonic = "rfeib"; // "rfeed"
1026 return;
1027 }
1028 break;
1029 case 'f': // 2 strings to match.
1030 switch (Mnemonic[4]) {
1031 default: break;
1032 case 'a': // 1 string to match.
1033 Mnemonic = "rfeda"; // "rfefa"
1034 return;
1035 case 'd': // 1 string to match.
1036 Mnemonic = "rfeia"; // "rfefd"
1037 return;
1038 }
1039 break;
1040 }
1041 break;
1042 case 's': // 7 strings to match.
1043 switch (Mnemonic[1]) {
1044 default: break;
1045 case 'r': // 4 strings to match.
1046 if (Mnemonic[2] != 's')
1047 break;
1048 switch (Mnemonic[3]) {
1049 default: break;
1050 case 'e': // 2 strings to match.
1051 switch (Mnemonic[4]) {
1052 default: break;
1053 case 'a': // 1 string to match.
1054 Mnemonic = "srsia"; // "srsea"
1055 return;
1056 case 'd': // 1 string to match.
1057 Mnemonic = "srsda"; // "srsed"
1058 return;
1059 }
1060 break;
1061 case 'f': // 2 strings to match.
1062 switch (Mnemonic[4]) {
1063 default: break;
1064 case 'a': // 1 string to match.
1065 Mnemonic = "srsib"; // "srsfa"
1066 return;
1067 case 'd': // 1 string to match.
1068 Mnemonic = "srsdb"; // "srsfd"
1069 return;
1070 }
1071 break;
1072 }
1073 break;
1074 case 't': // 3 strings to match.
1075 if (Mnemonic[2] != 'm')
1076 break;
1077 switch (Mnemonic[3]) {
1078 default: break;
1079 case 'e': // 1 string to match.
1080 if (Mnemonic[4] != 'a')
1081 break;
1082 Mnemonic = "stm"; // "stmea"
1083 return;
1084 case 'f': // 1 string to match.
1085 if (Mnemonic[4] != 'd')
1086 break;
1087 Mnemonic = "stmdb"; // "stmfd"
1088 return;
1089 case 'i': // 1 string to match.
1090 if (Mnemonic[4] != 'a')
1091 break;
1092 Mnemonic = "stm"; // "stmia"
1093 return;
1094 }
1095 break;
1096 }
1097 break;
1098 case 'v': // 19 strings to match.
1099 switch (Mnemonic[1]) {
1100 default: break;
1101 case 'a': // 3 strings to match.
1102 switch (Mnemonic[2]) {
1103 default: break;
1104 case 'b': // 1 string to match.
1105 if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
1106 break;
1107 if (Features.test(Feature_HasNEONBit)) // "vabsq"
1108 Mnemonic = "vabs";
1109 return;
1110 case 'd': // 1 string to match.
1111 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1112 break;
1113 if (Features.test(Feature_HasNEONBit)) // "vaddq"
1114 Mnemonic = "vadd";
1115 return;
1116 case 'n': // 1 string to match.
1117 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1118 break;
1119 if (Features.test(Feature_HasNEONBit)) // "vandq"
1120 Mnemonic = "vand";
1121 return;
1122 }
1123 break;
1124 case 'b': // 1 string to match.
1125 if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
1126 break;
1127 if (Features.test(Feature_HasNEONBit)) // "vbicq"
1128 Mnemonic = "vbic";
1129 return;
1130 case 'c': // 3 strings to match.
1131 switch (Mnemonic[2]) {
1132 default: break;
1133 case 'e': // 1 string to match.
1134 if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
1135 break;
1136 if (Features.test(Feature_HasNEONBit)) // "vceqq"
1137 Mnemonic = "vceq";
1138 return;
1139 case 'l': // 1 string to match.
1140 if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
1141 break;
1142 if (Features.test(Feature_HasNEONBit)) // "vcleq"
1143 Mnemonic = "vcle";
1144 return;
1145 case 'v': // 1 string to match.
1146 if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
1147 break;
1148 if (Features.test(Feature_HasNEONBit)) // "vcvtq"
1149 Mnemonic = "vcvt";
1150 return;
1151 }
1152 break;
1153 case 'e': // 1 string to match.
1154 if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
1155 break;
1156 if (Features.test(Feature_HasNEONBit)) // "veorq"
1157 Mnemonic = "veor";
1158 return;
1159 case 'm': // 5 strings to match.
1160 switch (Mnemonic[2]) {
1161 default: break;
1162 case 'a': // 1 string to match.
1163 if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
1164 break;
1165 if (Features.test(Feature_HasNEONBit)) // "vmaxq"
1166 Mnemonic = "vmax";
1167 return;
1168 case 'i': // 1 string to match.
1169 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1170 break;
1171 if (Features.test(Feature_HasNEONBit)) // "vminq"
1172 Mnemonic = "vmin";
1173 return;
1174 case 'o': // 1 string to match.
1175 if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
1176 break;
1177 if (Features.test(Feature_HasNEONBit)) // "vmovq"
1178 Mnemonic = "vmov";
1179 return;
1180 case 'u': // 1 string to match.
1181 if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
1182 break;
1183 if (Features.test(Feature_HasNEONBit)) // "vmulq"
1184 Mnemonic = "vmul";
1185 return;
1186 case 'v': // 1 string to match.
1187 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1188 break;
1189 if (Features.test(Feature_HasNEONBit)) // "vmvnq"
1190 Mnemonic = "vmvn";
1191 return;
1192 }
1193 break;
1194 case 'o': // 1 string to match.
1195 if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
1196 break;
1197 if (Features.test(Feature_HasNEONBit)) // "vorrq"
1198 Mnemonic = "vorr";
1199 return;
1200 case 's': // 4 strings to match.
1201 switch (Mnemonic[2]) {
1202 default: break;
1203 case 'h': // 2 strings to match.
1204 switch (Mnemonic[3]) {
1205 default: break;
1206 case 'l': // 1 string to match.
1207 if (Mnemonic[4] != 'q')
1208 break;
1209 if (Features.test(Feature_HasNEONBit)) // "vshlq"
1210 Mnemonic = "vshl";
1211 return;
1212 case 'r': // 1 string to match.
1213 if (Mnemonic[4] != 'q')
1214 break;
1215 if (Features.test(Feature_HasNEONBit)) // "vshrq"
1216 Mnemonic = "vshr";
1217 return;
1218 }
1219 break;
1220 case 'u': // 1 string to match.
1221 if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
1222 break;
1223 if (Features.test(Feature_HasNEONBit)) // "vsubq"
1224 Mnemonic = "vsub";
1225 return;
1226 case 'w': // 1 string to match.
1227 if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
1228 break;
1229 if (Features.test(Feature_HasNEONBit)) // "vswpq"
1230 Mnemonic = "vswp";
1231 return;
1232 }
1233 break;
1234 case 'z': // 1 string to match.
1235 if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
1236 break;
1237 if (Features.test(Feature_HasNEONBit)) // "vzipq"
1238 Mnemonic = "vzip";
1239 return;
1240 }
1241 break;
1242 }
1243 break;
1244 case 6: // 10 strings to match.
1245 if (Mnemonic[0] != 'f')
1246 break;
1247 switch (Mnemonic[1]) {
1248 default: break;
1249 case 's': // 4 strings to match.
1250 switch (Mnemonic[2]) {
1251 default: break;
1252 case 'i': // 2 strings to match.
1253 if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
1254 break;
1255 switch (Mnemonic[5]) {
1256 default: break;
1257 case 'd': // 1 string to match.
1258 if (Features.test(Feature_HasVFP2Bit)) // "fsitod"
1259 Mnemonic = "vcvt.f64.s32";
1260 return;
1261 case 's': // 1 string to match.
1262 if (Features.test(Feature_HasVFP2Bit)) // "fsitos"
1263 Mnemonic = "vcvt.f32.s32";
1264 return;
1265 }
1266 break;
1267 case 'q': // 2 strings to match.
1268 if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
1269 break;
1270 switch (Mnemonic[5]) {
1271 default: break;
1272 case 'd': // 1 string to match.
1273 if (Features.test(Feature_HasVFP2Bit)) // "fsqrtd"
1274 Mnemonic = "vsqrt";
1275 return;
1276 case 's': // 1 string to match.
1277 if (Features.test(Feature_HasVFP2Bit)) // "fsqrts"
1278 Mnemonic = "vsqrt";
1279 return;
1280 }
1281 break;
1282 }
1283 break;
1284 case 't': // 4 strings to match.
1285 if (Mnemonic[2] != 'o')
1286 break;
1287 switch (Mnemonic[3]) {
1288 default: break;
1289 case 's': // 2 strings to match.
1290 if (Mnemonic[4] != 'i')
1291 break;
1292 switch (Mnemonic[5]) {
1293 default: break;
1294 case 'd': // 1 string to match.
1295 if (Features.test(Feature_HasVFP2Bit)) // "ftosid"
1296 Mnemonic = "vcvtr.s32.f64";
1297 return;
1298 case 's': // 1 string to match.
1299 if (Features.test(Feature_HasVFP2Bit)) // "ftosis"
1300 Mnemonic = "vcvtr.s32.f32";
1301 return;
1302 }
1303 break;
1304 case 'u': // 2 strings to match.
1305 if (Mnemonic[4] != 'i')
1306 break;
1307 switch (Mnemonic[5]) {
1308 default: break;
1309 case 'd': // 1 string to match.
1310 if (Features.test(Feature_HasVFP2Bit)) // "ftouid"
1311 Mnemonic = "vcvtr.u32.f64";
1312 return;
1313 case 's': // 1 string to match.
1314 if (Features.test(Feature_HasVFP2Bit)) // "ftouis"
1315 Mnemonic = "vcvtr.u32.f32";
1316 return;
1317 }
1318 break;
1319 }
1320 break;
1321 case 'u': // 2 strings to match.
1322 if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
1323 break;
1324 switch (Mnemonic[5]) {
1325 default: break;
1326 case 'd': // 1 string to match.
1327 if (Features.test(Feature_HasVFP2Bit)) // "fuitod"
1328 Mnemonic = "vcvt.f64.u32";
1329 return;
1330 case 's': // 1 string to match.
1331 if (Features.test(Feature_HasVFP2Bit)) // "fuitos"
1332 Mnemonic = "vcvt.f32.u32";
1333 return;
1334 }
1335 break;
1336 }
1337 break;
1338 case 7: // 9 strings to match.
1339 switch (Mnemonic[0]) {
1340 default: break;
1341 case 'f': // 8 strings to match.
1342 switch (Mnemonic[1]) {
1343 default: break;
1344 case 'l': // 2 strings to match.
1345 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
1346 break;
1347 switch (Mnemonic[4]) {
1348 default: break;
1349 case 'e': // 1 string to match.
1350 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1351 break;
1352 if (Features.test(Feature_HasVFP2Bit)) // "fldmeax"
1353 Mnemonic = "fldmdbx";
1354 return;
1355 case 'f': // 1 string to match.
1356 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1357 break;
1358 if (Features.test(Feature_HasVFP2Bit)) // "fldmfdx"
1359 Mnemonic = "fldmiax";
1360 return;
1361 }
1362 break;
1363 case 's': // 2 strings to match.
1364 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
1365 break;
1366 switch (Mnemonic[4]) {
1367 default: break;
1368 case 'e': // 1 string to match.
1369 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1370 break;
1371 if (Features.test(Feature_HasVFP2Bit)) // "fstmeax"
1372 Mnemonic = "fstmiax";
1373 return;
1374 case 'f': // 1 string to match.
1375 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1376 break;
1377 if (Features.test(Feature_HasVFP2Bit)) // "fstmfdx"
1378 Mnemonic = "fstmdbx";
1379 return;
1380 }
1381 break;
1382 case 't': // 4 strings to match.
1383 if (Mnemonic[2] != 'o')
1384 break;
1385 switch (Mnemonic[3]) {
1386 default: break;
1387 case 's': // 2 strings to match.
1388 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1389 break;
1390 switch (Mnemonic[6]) {
1391 default: break;
1392 case 'd': // 1 string to match.
1393 if (Features.test(Feature_HasVFP2Bit)) // "ftosizd"
1394 Mnemonic = "vcvt.s32.f64";
1395 return;
1396 case 's': // 1 string to match.
1397 if (Features.test(Feature_HasVFP2Bit)) // "ftosizs"
1398 Mnemonic = "vcvt.s32.f32";
1399 return;
1400 }
1401 break;
1402 case 'u': // 2 strings to match.
1403 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1404 break;
1405 switch (Mnemonic[6]) {
1406 default: break;
1407 case 'd': // 1 string to match.
1408 if (Features.test(Feature_HasVFP2Bit)) // "ftouizd"
1409 Mnemonic = "vcvt.u32.f64";
1410 return;
1411 case 's': // 1 string to match.
1412 if (Features.test(Feature_HasVFP2Bit)) // "ftouizs"
1413 Mnemonic = "vcvt.u32.f32";
1414 return;
1415 }
1416 break;
1417 }
1418 break;
1419 }
1420 break;
1421 case 'v': // 1 string to match.
1422 if (memcmp(Mnemonic.data()+1, "ldrb.8", 6) != 0)
1423 break;
1424 Mnemonic = "vldrb.u8"; // "vldrb.8"
1425 return;
1426 }
1427 break;
1428 case 8: // 13 strings to match.
1429 switch (Mnemonic[0]) {
1430 default: break;
1431 case 'q': // 1 string to match.
1432 if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
1433 break;
1434 Mnemonic = "qsax"; // "qsubaddx"
1435 return;
1436 case 's': // 2 strings to match.
1437 switch (Mnemonic[1]) {
1438 default: break;
1439 case 'a': // 1 string to match.
1440 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1441 break;
1442 Mnemonic = "sasx"; // "saddsubx"
1443 return;
1444 case 's': // 1 string to match.
1445 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1446 break;
1447 Mnemonic = "ssax"; // "ssubaddx"
1448 return;
1449 }
1450 break;
1451 case 'u': // 2 strings to match.
1452 switch (Mnemonic[1]) {
1453 default: break;
1454 case 'a': // 1 string to match.
1455 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1456 break;
1457 Mnemonic = "uasx"; // "uaddsubx"
1458 return;
1459 case 's': // 1 string to match.
1460 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1461 break;
1462 Mnemonic = "usax"; // "usubaddx"
1463 return;
1464 }
1465 break;
1466 case 'v': // 8 strings to match.
1467 switch (Mnemonic[1]) {
1468 default: break;
1469 case 'l': // 6 strings to match.
1470 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1471 break;
1472 switch (Mnemonic[4]) {
1473 default: break;
1474 case 'b': // 3 strings to match.
1475 switch (Mnemonic[5]) {
1476 default: break;
1477 case '.': // 1 string to match.
1478 if (memcmp(Mnemonic.data()+6, "s8", 2) != 0)
1479 break;
1480 Mnemonic = "vldrb.u8"; // "vldrb.s8"
1481 return;
1482 case 'e': // 1 string to match.
1483 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0)
1484 break;
1485 Mnemonic = "vldrbe.u8"; // "vldrbe.8"
1486 return;
1487 case 't': // 1 string to match.
1488 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0)
1489 break;
1490 Mnemonic = "vldrbt.u8"; // "vldrbt.8"
1491 return;
1492 }
1493 break;
1494 case 'd': // 1 string to match.
1495 if (memcmp(Mnemonic.data()+5, ".64", 3) != 0)
1496 break;
1497 Mnemonic = "vldrd.u64"; // "vldrd.64"
1498 return;
1499 case 'h': // 1 string to match.
1500 if (memcmp(Mnemonic.data()+5, ".16", 3) != 0)
1501 break;
1502 Mnemonic = "vldrh.u16"; // "vldrh.16"
1503 return;
1504 case 'w': // 1 string to match.
1505 if (memcmp(Mnemonic.data()+5, ".32", 3) != 0)
1506 break;
1507 Mnemonic = "vldrw.u32"; // "vldrw.32"
1508 return;
1509 }
1510 break;
1511 case 's': // 2 strings to match.
1512 if (memcmp(Mnemonic.data()+2, "trb.", 4) != 0)
1513 break;
1514 switch (Mnemonic[6]) {
1515 default: break;
1516 case 's': // 1 string to match.
1517 if (Mnemonic[7] != '8')
1518 break;
1519 Mnemonic = "vstrb.8"; // "vstrb.s8"
1520 return;
1521 case 'u': // 1 string to match.
1522 if (Mnemonic[7] != '8')
1523 break;
1524 Mnemonic = "vstrb.8"; // "vstrb.u8"
1525 return;
1526 }
1527 break;
1528 }
1529 break;
1530 }
1531 break;
1532 case 9: // 35 strings to match.
1533 switch (Mnemonic[0]) {
1534 default: break;
1535 case 's': // 2 strings to match.
1536 if (Mnemonic[1] != 'h')
1537 break;
1538 switch (Mnemonic[2]) {
1539 default: break;
1540 case 'a': // 1 string to match.
1541 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1542 break;
1543 Mnemonic = "shasx"; // "shaddsubx"
1544 return;
1545 case 's': // 1 string to match.
1546 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1547 break;
1548 Mnemonic = "shsax"; // "shsubaddx"
1549 return;
1550 }
1551 break;
1552 case 'u': // 4 strings to match.
1553 switch (Mnemonic[1]) {
1554 default: break;
1555 case 'h': // 2 strings to match.
1556 switch (Mnemonic[2]) {
1557 default: break;
1558 case 'a': // 1 string to match.
1559 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1560 break;
1561 Mnemonic = "uhasx"; // "uhaddsubx"
1562 return;
1563 case 's': // 1 string to match.
1564 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1565 break;
1566 Mnemonic = "uhsax"; // "uhsubaddx"
1567 return;
1568 }
1569 break;
1570 case 'q': // 2 strings to match.
1571 switch (Mnemonic[2]) {
1572 default: break;
1573 case 'a': // 1 string to match.
1574 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1575 break;
1576 Mnemonic = "uqasx"; // "uqaddsubx"
1577 return;
1578 case 's': // 1 string to match.
1579 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1580 break;
1581 Mnemonic = "uqsax"; // "uqsubaddx"
1582 return;
1583 }
1584 break;
1585 }
1586 break;
1587 case 'v': // 29 strings to match.
1588 switch (Mnemonic[1]) {
1589 default: break;
1590 case 'l': // 14 strings to match.
1591 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1592 break;
1593 switch (Mnemonic[4]) {
1594 default: break;
1595 case 'b': // 2 strings to match.
1596 switch (Mnemonic[5]) {
1597 default: break;
1598 case 'e': // 1 string to match.
1599 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0)
1600 break;
1601 Mnemonic = "vldrbe.u8"; // "vldrbe.s8"
1602 return;
1603 case 't': // 1 string to match.
1604 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0)
1605 break;
1606 Mnemonic = "vldrbt.u8"; // "vldrbt.s8"
1607 return;
1608 }
1609 break;
1610 case 'd': // 4 strings to match.
1611 switch (Mnemonic[5]) {
1612 default: break;
1613 case '.': // 2 strings to match.
1614 switch (Mnemonic[6]) {
1615 default: break;
1616 case 'f': // 1 string to match.
1617 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1618 break;
1619 Mnemonic = "vldrd.u64"; // "vldrd.f64"
1620 return;
1621 case 's': // 1 string to match.
1622 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1623 break;
1624 Mnemonic = "vldrd.u64"; // "vldrd.s64"
1625 return;
1626 }
1627 break;
1628 case 'e': // 1 string to match.
1629 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0)
1630 break;
1631 Mnemonic = "vldrde.u64"; // "vldrde.64"
1632 return;
1633 case 't': // 1 string to match.
1634 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0)
1635 break;
1636 Mnemonic = "vldrdt.u64"; // "vldrdt.64"
1637 return;
1638 }
1639 break;
1640 case 'h': // 4 strings to match.
1641 switch (Mnemonic[5]) {
1642 default: break;
1643 case '.': // 2 strings to match.
1644 switch (Mnemonic[6]) {
1645 default: break;
1646 case 'f': // 1 string to match.
1647 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1648 break;
1649 Mnemonic = "vldrh.u16"; // "vldrh.f16"
1650 return;
1651 case 's': // 1 string to match.
1652 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1653 break;
1654 Mnemonic = "vldrh.u16"; // "vldrh.s16"
1655 return;
1656 }
1657 break;
1658 case 'e': // 1 string to match.
1659 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0)
1660 break;
1661 Mnemonic = "vldrhe.u16"; // "vldrhe.16"
1662 return;
1663 case 't': // 1 string to match.
1664 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0)
1665 break;
1666 Mnemonic = "vldrht.u16"; // "vldrht.16"
1667 return;
1668 }
1669 break;
1670 case 'w': // 4 strings to match.
1671 switch (Mnemonic[5]) {
1672 default: break;
1673 case '.': // 2 strings to match.
1674 switch (Mnemonic[6]) {
1675 default: break;
1676 case 'f': // 1 string to match.
1677 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1678 break;
1679 Mnemonic = "vldrw.u32"; // "vldrw.f32"
1680 return;
1681 case 's': // 1 string to match.
1682 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1683 break;
1684 Mnemonic = "vldrw.u32"; // "vldrw.s32"
1685 return;
1686 }
1687 break;
1688 case 'e': // 1 string to match.
1689 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0)
1690 break;
1691 Mnemonic = "vldrwe.u32"; // "vldrwe.32"
1692 return;
1693 case 't': // 1 string to match.
1694 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0)
1695 break;
1696 Mnemonic = "vldrwt.u32"; // "vldrwt.32"
1697 return;
1698 }
1699 break;
1700 }
1701 break;
1702 case 'm': // 2 strings to match.
1703 if (memcmp(Mnemonic.data()+2, "ovq.f", 5) != 0)
1704 break;
1705 switch (Mnemonic[7]) {
1706 default: break;
1707 case '3': // 1 string to match.
1708 if (Mnemonic[8] != '2')
1709 break;
1710 if (Features.test(Feature_HasNEONBit)) // "vmovq.f32"
1711 Mnemonic = "vmov.f32";
1712 return;
1713 case '6': // 1 string to match.
1714 if (Mnemonic[8] != '4')
1715 break;
1716 if (Features.test(Feature_HasNEONBit)) // "vmovq.f64"
1717 Mnemonic = "vmov.f64";
1718 return;
1719 }
1720 break;
1721 case 's': // 13 strings to match.
1722 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0)
1723 break;
1724 switch (Mnemonic[4]) {
1725 default: break;
1726 case 'b': // 4 strings to match.
1727 switch (Mnemonic[5]) {
1728 default: break;
1729 case 'e': // 2 strings to match.
1730 if (Mnemonic[6] != '.')
1731 break;
1732 switch (Mnemonic[7]) {
1733 default: break;
1734 case 's': // 1 string to match.
1735 if (Mnemonic[8] != '8')
1736 break;
1737 Mnemonic = "vstrbe.8"; // "vstrbe.s8"
1738 return;
1739 case 'u': // 1 string to match.
1740 if (Mnemonic[8] != '8')
1741 break;
1742 Mnemonic = "vstrbe.8"; // "vstrbe.u8"
1743 return;
1744 }
1745 break;
1746 case 't': // 2 strings to match.
1747 if (Mnemonic[6] != '.')
1748 break;
1749 switch (Mnemonic[7]) {
1750 default: break;
1751 case 's': // 1 string to match.
1752 if (Mnemonic[8] != '8')
1753 break;
1754 Mnemonic = "vstrbt.8"; // "vstrbt.s8"
1755 return;
1756 case 'u': // 1 string to match.
1757 if (Mnemonic[8] != '8')
1758 break;
1759 Mnemonic = "vstrbt.8"; // "vstrbt.u8"
1760 return;
1761 }
1762 break;
1763 }
1764 break;
1765 case 'd': // 3 strings to match.
1766 if (Mnemonic[5] != '.')
1767 break;
1768 switch (Mnemonic[6]) {
1769 default: break;
1770 case 'f': // 1 string to match.
1771 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1772 break;
1773 Mnemonic = "vstrd.64"; // "vstrd.f64"
1774 return;
1775 case 's': // 1 string to match.
1776 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1777 break;
1778 Mnemonic = "vstrd.64"; // "vstrd.s64"
1779 return;
1780 case 'u': // 1 string to match.
1781 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1782 break;
1783 Mnemonic = "vstrd.64"; // "vstrd.u64"
1784 return;
1785 }
1786 break;
1787 case 'h': // 3 strings to match.
1788 if (Mnemonic[5] != '.')
1789 break;
1790 switch (Mnemonic[6]) {
1791 default: break;
1792 case 'f': // 1 string to match.
1793 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1794 break;
1795 Mnemonic = "vstrh.16"; // "vstrh.f16"
1796 return;
1797 case 's': // 1 string to match.
1798 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1799 break;
1800 Mnemonic = "vstrh.16"; // "vstrh.s16"
1801 return;
1802 case 'u': // 1 string to match.
1803 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1804 break;
1805 Mnemonic = "vstrh.16"; // "vstrh.u16"
1806 return;
1807 }
1808 break;
1809 case 'w': // 3 strings to match.
1810 if (Mnemonic[5] != '.')
1811 break;
1812 switch (Mnemonic[6]) {
1813 default: break;
1814 case 'f': // 1 string to match.
1815 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1816 break;
1817 Mnemonic = "vstrw.32"; // "vstrw.f32"
1818 return;
1819 case 's': // 1 string to match.
1820 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1821 break;
1822 Mnemonic = "vstrw.32"; // "vstrw.s32"
1823 return;
1824 case 'u': // 1 string to match.
1825 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1826 break;
1827 Mnemonic = "vstrw.32"; // "vstrw.u32"
1828 return;
1829 }
1830 break;
1831 }
1832 break;
1833 }
1834 break;
1835 }
1836 break;
1837 case 10: // 30 strings to match.
1838 if (Mnemonic[0] != 'v')
1839 break;
1840 switch (Mnemonic[1]) {
1841 default: break;
1842 case 'l': // 12 strings to match.
1843 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1844 break;
1845 switch (Mnemonic[4]) {
1846 default: break;
1847 case 'd': // 4 strings to match.
1848 switch (Mnemonic[5]) {
1849 default: break;
1850 case 'e': // 2 strings to match.
1851 if (Mnemonic[6] != '.')
1852 break;
1853 switch (Mnemonic[7]) {
1854 default: break;
1855 case 'f': // 1 string to match.
1856 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1857 break;
1858 Mnemonic = "vldrde.u64"; // "vldrde.f64"
1859 return;
1860 case 's': // 1 string to match.
1861 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1862 break;
1863 Mnemonic = "vldrde.u64"; // "vldrde.s64"
1864 return;
1865 }
1866 break;
1867 case 't': // 2 strings to match.
1868 if (Mnemonic[6] != '.')
1869 break;
1870 switch (Mnemonic[7]) {
1871 default: break;
1872 case 'f': // 1 string to match.
1873 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1874 break;
1875 Mnemonic = "vldrdt.u64"; // "vldrdt.f64"
1876 return;
1877 case 's': // 1 string to match.
1878 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1879 break;
1880 Mnemonic = "vldrdt.u64"; // "vldrdt.s64"
1881 return;
1882 }
1883 break;
1884 }
1885 break;
1886 case 'h': // 4 strings to match.
1887 switch (Mnemonic[5]) {
1888 default: break;
1889 case 'e': // 2 strings to match.
1890 if (Mnemonic[6] != '.')
1891 break;
1892 switch (Mnemonic[7]) {
1893 default: break;
1894 case 'f': // 1 string to match.
1895 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1896 break;
1897 Mnemonic = "vldrhe.u16"; // "vldrhe.f16"
1898 return;
1899 case 's': // 1 string to match.
1900 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1901 break;
1902 Mnemonic = "vldrhe.u16"; // "vldrhe.s16"
1903 return;
1904 }
1905 break;
1906 case 't': // 2 strings to match.
1907 if (Mnemonic[6] != '.')
1908 break;
1909 switch (Mnemonic[7]) {
1910 default: break;
1911 case 'f': // 1 string to match.
1912 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1913 break;
1914 Mnemonic = "vldrht.u16"; // "vldrht.f16"
1915 return;
1916 case 's': // 1 string to match.
1917 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1918 break;
1919 Mnemonic = "vldrht.u16"; // "vldrht.s16"
1920 return;
1921 }
1922 break;
1923 }
1924 break;
1925 case 'w': // 4 strings to match.
1926 switch (Mnemonic[5]) {
1927 default: break;
1928 case 'e': // 2 strings to match.
1929 if (Mnemonic[6] != '.')
1930 break;
1931 switch (Mnemonic[7]) {
1932 default: break;
1933 case 'f': // 1 string to match.
1934 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1935 break;
1936 Mnemonic = "vldrwe.u32"; // "vldrwe.f32"
1937 return;
1938 case 's': // 1 string to match.
1939 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1940 break;
1941 Mnemonic = "vldrwe.u32"; // "vldrwe.s32"
1942 return;
1943 }
1944 break;
1945 case 't': // 2 strings to match.
1946 if (Mnemonic[6] != '.')
1947 break;
1948 switch (Mnemonic[7]) {
1949 default: break;
1950 case 'f': // 1 string to match.
1951 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1952 break;
1953 Mnemonic = "vldrwt.u32"; // "vldrwt.f32"
1954 return;
1955 case 's': // 1 string to match.
1956 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1957 break;
1958 Mnemonic = "vldrwt.u32"; // "vldrwt.s32"
1959 return;
1960 }
1961 break;
1962 }
1963 break;
1964 }
1965 break;
1966 case 's': // 18 strings to match.
1967 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0)
1968 break;
1969 switch (Mnemonic[4]) {
1970 default: break;
1971 case 'd': // 6 strings to match.
1972 switch (Mnemonic[5]) {
1973 default: break;
1974 case 'e': // 3 strings to match.
1975 if (Mnemonic[6] != '.')
1976 break;
1977 switch (Mnemonic[7]) {
1978 default: break;
1979 case 'f': // 1 string to match.
1980 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1981 break;
1982 Mnemonic = "vstrde.64"; // "vstrde.f64"
1983 return;
1984 case 's': // 1 string to match.
1985 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1986 break;
1987 Mnemonic = "vstrde.64"; // "vstrde.s64"
1988 return;
1989 case 'u': // 1 string to match.
1990 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1991 break;
1992 Mnemonic = "vstrde.64"; // "vstrde.u64"
1993 return;
1994 }
1995 break;
1996 case 't': // 3 strings to match.
1997 if (Mnemonic[6] != '.')
1998 break;
1999 switch (Mnemonic[7]) {
2000 default: break;
2001 case 'f': // 1 string to match.
2002 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2003 break;
2004 Mnemonic = "vstrdt.64"; // "vstrdt.f64"
2005 return;
2006 case 's': // 1 string to match.
2007 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2008 break;
2009 Mnemonic = "vstrdt.64"; // "vstrdt.s64"
2010 return;
2011 case 'u': // 1 string to match.
2012 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2013 break;
2014 Mnemonic = "vstrdt.64"; // "vstrdt.u64"
2015 return;
2016 }
2017 break;
2018 }
2019 break;
2020 case 'h': // 6 strings to match.
2021 switch (Mnemonic[5]) {
2022 default: break;
2023 case 'e': // 3 strings to match.
2024 if (Mnemonic[6] != '.')
2025 break;
2026 switch (Mnemonic[7]) {
2027 default: break;
2028 case 'f': // 1 string to match.
2029 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2030 break;
2031 Mnemonic = "vstrhe.16"; // "vstrhe.f16"
2032 return;
2033 case 's': // 1 string to match.
2034 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2035 break;
2036 Mnemonic = "vstrhe.16"; // "vstrhe.s16"
2037 return;
2038 case 'u': // 1 string to match.
2039 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2040 break;
2041 Mnemonic = "vstrhe.16"; // "vstrhe.u16"
2042 return;
2043 }
2044 break;
2045 case 't': // 3 strings to match.
2046 if (Mnemonic[6] != '.')
2047 break;
2048 switch (Mnemonic[7]) {
2049 default: break;
2050 case 'f': // 1 string to match.
2051 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2052 break;
2053 Mnemonic = "vstrht.16"; // "vstrht.f16"
2054 return;
2055 case 's': // 1 string to match.
2056 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2057 break;
2058 Mnemonic = "vstrht.16"; // "vstrht.s16"
2059 return;
2060 case 'u': // 1 string to match.
2061 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2062 break;
2063 Mnemonic = "vstrht.16"; // "vstrht.u16"
2064 return;
2065 }
2066 break;
2067 }
2068 break;
2069 case 'w': // 6 strings to match.
2070 switch (Mnemonic[5]) {
2071 default: break;
2072 case 'e': // 3 strings to match.
2073 if (Mnemonic[6] != '.')
2074 break;
2075 switch (Mnemonic[7]) {
2076 default: break;
2077 case 'f': // 1 string to match.
2078 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2079 break;
2080 Mnemonic = "vstrwe.32"; // "vstrwe.f32"
2081 return;
2082 case 's': // 1 string to match.
2083 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2084 break;
2085 Mnemonic = "vstrwe.32"; // "vstrwe.s32"
2086 return;
2087 case 'u': // 1 string to match.
2088 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2089 break;
2090 Mnemonic = "vstrwe.32"; // "vstrwe.u32"
2091 return;
2092 }
2093 break;
2094 case 't': // 3 strings to match.
2095 if (Mnemonic[6] != '.')
2096 break;
2097 switch (Mnemonic[7]) {
2098 default: break;
2099 case 'f': // 1 string to match.
2100 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2101 break;
2102 Mnemonic = "vstrwt.32"; // "vstrwt.f32"
2103 return;
2104 case 's': // 1 string to match.
2105 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2106 break;
2107 Mnemonic = "vstrwt.32"; // "vstrwt.s32"
2108 return;
2109 case 'u': // 1 string to match.
2110 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2111 break;
2112 Mnemonic = "vstrwt.32"; // "vstrwt.u32"
2113 return;
2114 }
2115 break;
2116 }
2117 break;
2118 }
2119 break;
2120 }
2121 break;
2122 case 11: // 2 strings to match.
2123 if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
2124 break;
2125 switch (Mnemonic[8]) {
2126 default: break;
2127 case 'f': // 1 string to match.
2128 if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
2129 break;
2130 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.f32"
2131 Mnemonic = "vrecpe.f32";
2132 return;
2133 case 'u': // 1 string to match.
2134 if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
2135 break;
2136 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.u32"
2137 Mnemonic = "vrecpe.u32";
2138 return;
2139 }
2140 break;
2141 }
2142}
2143
2144enum {
2145 Tie0_1_1,
2146 Tie0_2_2,
2147 Tie0_2_4,
2148 Tie0_3_3,
2149 Tie0_4_4,
2150 Tie0_4_5,
2151 Tie1_1_1,
2152 Tie1_2_2,
2153 Tie1_3_3,
2154 Tie1_4_4,
2155 Tie2_4_4,
2156};
2157
2158static const uint8_t TiedAsmOperandTable[][3] = {
2159 /* Tie0_1_1 */ { 0, 1, 1 },
2160 /* Tie0_2_2 */ { 0, 2, 2 },
2161 /* Tie0_2_4 */ { 0, 2, 4 },
2162 /* Tie0_3_3 */ { 0, 3, 3 },
2163 /* Tie0_4_4 */ { 0, 4, 4 },
2164 /* Tie0_4_5 */ { 0, 4, 5 },
2165 /* Tie1_1_1 */ { 1, 1, 1 },
2166 /* Tie1_2_2 */ { 1, 2, 2 },
2167 /* Tie1_3_3 */ { 1, 3, 3 },
2168 /* Tie1_4_4 */ { 1, 4, 4 },
2169 /* Tie2_4_4 */ { 2, 4, 4 },
2170};
2171
2172namespace {
2173enum OperatorConversionKind {
2174 CVT_Done,
2175 CVT_Reg,
2176 CVT_Tied,
2177 CVT_95_Reg,
2178 CVT_95_addCCOutOperands_95_defaultCCOutOp,
2179 CVT_95_addCondCodeOperands_95_defaultCondCodeOp,
2180 CVT_95_addRegShiftedImmOperands,
2181 CVT_95_addImmOperands,
2182 CVT_95_addT2SOImmNotOperands,
2183 CVT_95_addRegShiftedRegOperands,
2184 CVT_95_addModImmOperands,
2185 CVT_95_addModImmNotOperands,
2186 CVT_95_addImm0_95_508s4Operands,
2187 CVT_regSP,
2188 CVT_95_addImm0_95_508s4NegOperands,
2189 CVT_95_addThumbModImmNeg8_95_255Operands,
2190 CVT_95_addImm0_95_1020s4Operands,
2191 CVT_95_addThumbModImmNeg1_95_7Operands,
2192 CVT_95_addImm0_95_4095NegOperands,
2193 CVT_95_addT2SOImmNegOperands,
2194 CVT_95_addModImmNegOperands,
2195 CVT_95_addUnsignedOffset_95_b8s2Operands,
2196 CVT_95_addAdrLabelOperands,
2197 CVT_imm_95_45,
2198 CVT_cvtThumbBranches,
2199 CVT_95_addARMBranchTargetOperands,
2200 CVT_95_addBitfieldOperands,
2201 CVT_95_addITCondCodeOperands,
2202 CVT_imm_95_0,
2203 CVT_95_addThumbBranchTargetOperands,
2204 CVT_imm_95_15,
2205 CVT_95_addCoprocNumOperands,
2206 CVT_95_addCoprocRegOperands,
2207 CVT_95_addITCondCodeInvOperands,
2208 CVT_imm_95_22,
2209 CVT_95_addRegListWithAPSROperands,
2210 CVT_95_addProcIFlagsOperands,
2211 CVT_imm_95_20,
2212 CVT_regZR,
2213 CVT_imm_95_12,
2214 CVT_95_addMemBarrierOptOperands,
2215 CVT_imm_95_16,
2216 CVT_95_addFPImmOperands,
2217 CVT_95_addDPRRegListOperands,
2218 CVT_imm_95_1,
2219 CVT_95_addInstSyncBarrierOptOperands,
2220 CVT_95_addITMaskOperands,
2221 CVT_95_addMemNoOffsetOperands,
2222 CVT_95_addAddrMode5Operands,
2223 CVT_95_addCoprocOptionOperands,
2224 CVT_95_addPostIdxImm8s4Operands,
2225 CVT_95_addRegListOperands,
2226 CVT_95_addThumbMemPCOperands,
2227 CVT_95_addMemThumbRIs4Operands,
2228 CVT_95_addMemThumbRROperands,
2229 CVT_95_addMemThumbSPIOperands,
2230 CVT_95_addConstPoolAsmImmOperands,
2231 CVT_95_addMemImm12OffsetOperands,
2232 CVT_95_addMemImmOffsetOperands,
2233 CVT_95_addMemRegOffsetOperands,
2234 CVT_95_addMemUImm12OffsetOperands,
2235 CVT_95_addT2MemRegOffsetOperands,
2236 CVT_95_addMemPCRelImm12Operands,
2237 CVT_95_addAM2OffsetImmOperands,
2238 CVT_95_addPostIdxRegShiftedOperands,
2239 CVT_95_addMemThumbRIs1Operands,
2240 CVT_95_addMemImm8s4OffsetOperands,
2241 CVT_95_addAddrMode3Operands,
2242 CVT_95_addAM3OffsetOperands,
2243 CVT_95_addMemImm0_95_1020s4OffsetOperands,
2244 CVT_95_addMemThumbRIs2Operands,
2245 CVT_95_addPostIdxRegOperands,
2246 CVT_95_addPostIdxImm8Operands,
2247 CVT_reg0,
2248 CVT_regCPSR,
2249 CVT_imm_95_14,
2250 CVT_95_addBankedRegOperands,
2251 CVT_95_addMSRMaskOperands,
2252 CVT_cvtThumbMultiply,
2253 CVT_regR8,
2254 CVT_regR0,
2255 CVT_imm_95_29,
2256 CVT_imm_95_13,
2257 CVT_95_addPKHASRImmOperands,
2258 CVT_imm_95_4,
2259 CVT_95_addImm1_95_32Operands,
2260 CVT_imm_95_5,
2261 CVT_95_addMveSaturateOperands,
2262 CVT_95_addShifterImmOperands,
2263 CVT_95_addImm1_95_16Operands,
2264 CVT_95_addRotImmOperands,
2265 CVT_95_addMemTBBOperands,
2266 CVT_95_addMemTBHOperands,
2267 CVT_95_addTraceSyncBarrierOptOperands,
2268 CVT_95_addVPTPredNOperands_95_defaultVPTPredOp,
2269 CVT_95_addVPTPredROperands_95_defaultVPTPredOp,
2270 CVT_95_addNEONi16splatNotOperands,
2271 CVT_95_addNEONi32splatNotOperands,
2272 CVT_95_addNEONi16splatOperands,
2273 CVT_95_addNEONi32splatOperands,
2274 CVT_95_addComplexRotationOddOperands,
2275 CVT_95_addComplexRotationEvenOperands,
2276 CVT_95_addVectorIndex64Operands,
2277 CVT_95_addVectorIndex32Operands,
2278 CVT_95_addFBits16Operands,
2279 CVT_95_addFBits32Operands,
2280 CVT_95_addPowerTwoOperands,
2281 CVT_95_addVectorIndex16Operands,
2282 CVT_95_addVectorIndex8Operands,
2283 CVT_95_addVecListOperands,
2284 CVT_95_addDupAlignedMemory16Operands,
2285 CVT_95_addAlignedMemory64or128Operands,
2286 CVT_95_addAlignedMemory64or128or256Operands,
2287 CVT_95_addAlignedMemory64Operands,
2288 CVT_95_addVecListIndexedOperands,
2289 CVT_95_addAlignedMemory16Operands,
2290 CVT_95_addDupAlignedMemory32Operands,
2291 CVT_95_addAlignedMemory32Operands,
2292 CVT_95_addDupAlignedMemoryNoneOperands,
2293 CVT_95_addAlignedMemoryNoneOperands,
2294 CVT_95_addAlignedMemoryOperands,
2295 CVT_95_addDupAlignedMemory64Operands,
2296 CVT_95_addMVEVecListOperands,
2297 CVT_95_addMemNoOffsetT2Operands,
2298 CVT_95_addMemNoOffsetT2NoSpOperands,
2299 CVT_95_addDupAlignedMemory64or128Operands,
2300 CVT_95_addSPRRegListOperands,
2301 CVT_95_addMemImm7s4OffsetOperands,
2302 CVT_95_addAddrMode5FP16Operands,
2303 CVT_95_addImm7s4Operands,
2304 CVT_95_addMemRegRQOffsetOperands,
2305 CVT_95_addMemNoOffsetTOperands,
2306 CVT_95_addImm7Shift0Operands,
2307 CVT_95_addImm7Shift1Operands,
2308 CVT_95_addImm7Shift2Operands,
2309 CVT_95_addNEONi32vmovOperands,
2310 CVT_95_addNEONvmovi8ReplicateOperands,
2311 CVT_95_addNEONvmovi16ReplicateOperands,
2312 CVT_95_addNEONi32vmovNegOperands,
2313 CVT_95_addNEONvmovi32ReplicateOperands,
2314 CVT_95_addNEONi64splatOperands,
2315 CVT_95_addNEONi8splatOperands,
2316 CVT_95_addMVEVectorIndexOperands,
2317 CVT_95_addMVEPairVectorIndexOperands,
2318 CVT_cvtMVEVMOVQtoDReg,
2319 CVT_95_addNEONinvi8ReplicateOperands,
2320 CVT_95_addFPDRegListWithVPROperands,
2321 CVT_95_addFPSRegListWithVPROperands,
2322 CVT_imm_95_2,
2323 CVT_imm_95_3,
2324 CVT_NUM_CONVERTERS
2325};
2326
2327enum InstructionConversionKind {
2328 Convert_NoOperands,
2329 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1,
2330 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
2331 Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
2332 Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
2333 Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
2334 Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
2335 Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
2336 Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
2337 Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2338 Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2339 Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2340 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2341 Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2342 Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2343 Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
2344 Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
2345 Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
2346 Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
2347 Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
2348 Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
2349 Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0,
2350 Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0,
2351 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0,
2352 Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
2353 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1,
2354 Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1,
2355 Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0,
2356 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0,
2357 Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
2358 Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
2359 Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
2360 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
2361 Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
2362 Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
2363 Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
2364 Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
2365 Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
2366 Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
2367 Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
2368 Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
2369 Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
2370 Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
2371 Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
2372 Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
2373 Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
2374 Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
2375 Convert__Reg1_1__Imm1_2__CondCode2_0,
2376 Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
2377 Convert__Reg1_2__Imm1_3__CondCode2_0,
2378 Convert__Reg1_1__Tie0_1_1__Reg1_2,
2379 Convert__Reg1_1__Reg1_2,
2380 Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
2381 Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0,
2382 Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
2383 Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
2384 Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
2385 Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
2386 Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
2387 Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
2388 Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
2389 Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
2390 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0,
2391 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0,
2392 Convert__imm_95_45__CondCode2_0,
2393 Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3,
2394 ConvertCustom_cvtThumbBranches,
2395 Convert__ARMBranchTarget1_1__CondCode2_0,
2396 Convert__Imm1_1__Imm1_2__CondCode2_0,
2397 Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0,
2398 Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3,
2399 Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0,
2400 Convert__Imm1_1__Reg1_2__CondCode2_0,
2401 Convert__imm_95_0,
2402 Convert__Imm0_2551_0,
2403 Convert__Imm0_655351_0,
2404 Convert__ARMBranchTarget1_0,
2405 Convert__CondCode2_0__ThumbBranchTarget1_1,
2406 Convert__CondCode2_0__ThumbBranchTarget1_2,
2407 Convert__CondCode2_0__Reg1_1,
2408 Convert__Reg1_0,
2409 Convert__ThumbBranchTarget1_0,
2410 Convert__Reg1_1__CondCode2_0,
2411 Convert__CondCode2_0__ARMBranchTarget1_1,
2412 Convert__imm_95_15__CondCode2_0,
2413 Convert__CondCode2_0,
2414 Convert__Reg1_0__ThumbBranchTarget1_1,
2415 Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2416 Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2417 Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2,
2418 Convert__imm_95_22__CondCode2_0,
2419 Convert__CondCode2_0__RegListWithAPSR1_1,
2420 Convert__Reg1_1__Reg1_2__CondCode2_0,
2421 Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
2422 Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
2423 Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
2424 Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
2425 Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
2426 Convert__Reg1_1__ModImm1_2__CondCode2_0,
2427 Convert__Reg1_2__Reg1_3__CondCode2_0,
2428 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
2429 Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
2430 Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
2431 Convert__Imm1_0__ProcIFlags1_1,
2432 Convert__Imm0_311_0,
2433 Convert__Imm0_311_1,
2434 Convert__Imm1_0__ProcIFlags1_2,
2435 Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
2436 Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
2437 Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
2438 Convert__Reg1_0__Reg1_1__Reg1_2,
2439 Convert__imm_95_20__CondCode2_0,
2440 Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3,
2441 Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1,
2442 Convert__Reg1_1__CoprocNum1_0__Imm13b1_2,
2443 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0,
2444 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3,
2445 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0,
2446 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4,
2447 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0,
2448 Convert__Imm0_151_1__CondCode2_0,
2449 Convert__Imm0_151_2__CondCode2_0,
2450 Convert__imm_95_12,
2451 Convert__imm_95_12__CondCode2_0,
2452 Convert__Reg1_0__Reg1_1,
2453 Convert__imm_95_15,
2454 Convert__MemBarrierOpt1_0,
2455 Convert__MemBarrierOpt1_1__CondCode2_0,
2456 Convert__MemBarrierOpt1_2__CondCode2_0,
2457 Convert__imm_95_0__CondCode2_0,
2458 Convert__imm_95_16__CondCode2_0,
2459 Convert__Reg1_1__FPImm1_2__CondCode2_0,
2460 Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3,
2461 Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
2462 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0,
2463 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0,
2464 Convert__Imm0_2391_1__CondCode2_0,
2465 Convert__Imm0_2391_2__CondCode2_0,
2466 Convert__Imm0_631_0,
2467 Convert__Imm0_655351_1,
2468 Convert__InstSyncBarrierOpt1_0,
2469 Convert__InstSyncBarrierOpt1_1__CondCode2_0,
2470 Convert__InstSyncBarrierOpt1_2__CondCode2_0,
2471 Convert__ITCondCode1_1__ITMask1_0,
2472 Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
2473 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
2474 Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
2475 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
2476 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
2477 Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
2478 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
2479 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
2480 Convert__Reg1_1__CondCode2_0__RegList1_2,
2481 Convert__Reg1_1__CondCode2_0__RegList1_3,
2482 Convert__Reg1_2__CondCode2_0__RegList1_3,
2483 Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3,
2484 Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4,
2485 Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
2486 Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
2487 Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
2488 Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
2489 Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
2490 Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
2491 Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
2492 Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
2493 Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
2494 Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
2495 Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
2496 Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
2497 Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
2498 Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
2499 Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
2500 Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
2501 Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
2502 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0,
2503 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0,
2504 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0,
2505 Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
2506 Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0,
2507 Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0,
2508 Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
2509 Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0,
2510 Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
2511 Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
2512 Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
2513 Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
2514 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0,
2515 Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
2516 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0,
2517 Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
2518 Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
2519 Convert__Reg1_1__AddrMode33_2__CondCode2_0,
2520 Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
2521 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0,
2522 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0,
2523 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0,
2524 Convert__LELabel1_0,
2525 Convert__imm_95_0__Reg1_0__LELabel1_1,
2526 Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
2527 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
2528 Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
2529 Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
2530 Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
2531 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
2532 Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
2533 Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
2534 Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
2535 Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2536 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
2537 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2538 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
2539 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2540 Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
2541 Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
2542 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
2543 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
2544 Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1,
2545 Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
2546 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
2547 Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
2548 Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
2549 Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
2550 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
2551 Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
2552 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
2553 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
2554 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
2555 Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
2556 Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2557 Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0,
2558 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
2559 Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
2560 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
2561 Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
2562 Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0,
2563 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
2564 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2565 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
2566 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2567 Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
2568 Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
2569 Convert__Reg1_1__BankedReg1_2__CondCode2_0,
2570 Convert__Reg1_1__MSRMask1_2__CondCode2_0,
2571 Convert__BankedReg1_1__Reg1_2__CondCode2_0,
2572 Convert__MSRMask1_1__Reg1_2__CondCode2_0,
2573 Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
2574 ConvertCustom_cvtThumbMultiply,
2575 Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
2576 Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
2577 Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
2578 Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
2579 Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2580 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
2581 Convert__regR8__regR8__imm_95_14__reg0,
2582 Convert__regR0__regR0__CondCode2_0__reg0,
2583 Convert__imm_95_29__CondCode2_0,
2584 Convert__imm_95_13__CondCode2_0,
2585 Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3,
2586 Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
2587 Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
2588 Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
2589 Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
2590 Convert__MemImm12Offset2_0,
2591 Convert__MemRegOffset3_0,
2592 Convert__Imm1_1__CondCode2_0,
2593 Convert__MemNegImm8Offset2_1__CondCode2_0,
2594 Convert__MemUImm12Offset2_1__CondCode2_0,
2595 Convert__T2MemRegOffset3_1__CondCode2_0,
2596 Convert__MemPCRelImm121_1__CondCode2_0,
2597 Convert__Imm1_2__CondCode2_0,
2598 Convert__MemNegImm8Offset2_2__CondCode2_0,
2599 Convert__MemUImm12Offset2_2__CondCode2_0,
2600 Convert__T2MemRegOffset3_2__CondCode2_0,
2601 Convert__MemPCRelImm121_2__CondCode2_0,
2602 Convert__CondCode2_0__RegList1_1,
2603 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1,
2604 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2,
2605 Convert__imm_95_4__imm_95_14__reg0,
2606 Convert__imm_95_4,
2607 Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
2608 Convert__SetEndImm1_0,
2609 Convert__Imm0_11_0,
2610 Convert__imm_95_4__CondCode2_0,
2611 Convert__imm_95_5__CondCode2_0,
2612 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3,
2613 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0,
2614 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0,
2615 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0,
2616 Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0,
2617 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0,
2618 Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0,
2619 Convert__Imm0_311_2,
2620 Convert__Imm0_311_1__CondCode2_0,
2621 Convert__Imm0_311_2__CondCode2_0,
2622 Convert__Imm0_311_3__CondCode2_0,
2623 Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
2624 Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
2625 Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
2626 Convert__imm_95_0__imm_95_14__reg0,
2627 Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
2628 Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
2629 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0,
2630 Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
2631 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0,
2632 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0,
2633 Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
2634 Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
2635 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0,
2636 Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
2637 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0,
2638 Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
2639 Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
2640 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0,
2641 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0,
2642 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0,
2643 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1,
2644 Convert__Imm0_2551_3__CondCode2_0,
2645 Convert__Imm0_2551_1__CondCode2_0,
2646 Convert__Imm24bit1_1__CondCode2_0,
2647 Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
2648 Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
2649 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
2650 Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
2651 Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
2652 Convert__MemTBB2_1__CondCode2_0,
2653 Convert__MemTBH2_1__CondCode2_0,
2654 Convert__TraceSyncBarrierOpt1_0,
2655 Convert__TraceSyncBarrierOpt1_1__CondCode2_0,
2656 Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
2657 Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
2658 Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
2659 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0,
2660 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0,
2661 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
2662 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
2663 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0,
2664 Convert__Reg1_2__Reg1_3__VPTPredR4_0,
2665 Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
2666 Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
2667 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0,
2668 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0,
2669 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0,
2670 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0,
2671 Convert__Reg1_2__Reg1_3__VPTPredN3_0,
2672 Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0,
2673 Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
2674 Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0,
2675 Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0,
2676 Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0,
2677 Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0,
2678 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0,
2679 Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0,
2680 Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0,
2681 Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0,
2682 Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0,
2683 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0,
2684 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0,
2685 Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4,
2686 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0,
2687 Convert__Reg1_2__Reg1_2__CondCode2_0,
2688 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4,
2689 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5,
2690 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5,
2691 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0,
2692 Convert__Reg1_2__CondCode2_0,
2693 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0,
2694 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0,
2695 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0,
2696 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0,
2697 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0,
2698 Convert__imm_95_0__Reg1_2__VPTPredN3_0,
2699 Convert__Reg1_3__Reg1_4__CondCode2_0,
2700 Convert__Reg1_3__Reg1_4__VPTPredR4_0,
2701 Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0,
2702 Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
2703 Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0,
2704 Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0,
2705 Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0,
2706 Convert__Reg1_2__Reg1_3,
2707 Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0,
2708 Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0,
2709 Convert__Reg1_1__CoprocNum1_0__Imm11b1_2,
2710 Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0,
2711 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2,
2712 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0,
2713 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3,
2714 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0,
2715 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3,
2716 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0,
2717 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4,
2718 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0,
2719 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4,
2720 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0,
2721 Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0,
2722 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3,
2723 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4,
2724 Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2725 Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2726 Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
2727 Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0,
2728 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
2729 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
2730 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
2731 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
2732 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
2733 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
2734 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
2735 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
2736 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4,
2737 Convert__Reg1_1__Reg1_2__Reg1_3,
2738 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4,
2739 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
2740 Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2741 Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
2742 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2743 Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2744 Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
2745 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
2746 Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
2747 Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2748 Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2749 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2750 Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2751 Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2752 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2753 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2754 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2755 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
2756 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2757 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
2758 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2759 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2760 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2761 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
2762 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
2763 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
2764 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
2765 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
2766 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2767 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2768 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2769 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2770 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2771 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
2772 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2773 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
2774 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2775 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2776 Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0,
2777 Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
2778 Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
2779 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2780 Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
2781 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2782 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2783 Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2784 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2785 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2786 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2787 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2788 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
2789 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2790 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2791 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
2792 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2793 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2794 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2795 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
2796 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2797 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
2798 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2799 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2800 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2801 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2802 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2803 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
2804 Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2,
2805 Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3,
2806 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2807 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2808 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2809 Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
2810 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2811 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2812 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2813 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2814 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2815 Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2816 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2817 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2818 Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2819 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2820 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2821 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2822 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2823 Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
2824 Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
2825 Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
2826 Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
2827 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2828 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2829 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2830 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2831 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2832 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2833 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2834 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2835 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2836 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2837 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
2838 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2839 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2840 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2841 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2842 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2843 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2844 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2845 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2846 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2847 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2848 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2849 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2850 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2851 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2852 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
2853 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
2854 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
2855 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
2856 Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2,
2857 Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3,
2858 Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3,
2859 Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
2860 Convert__MemImm7s4Offset2_2__CondCode2_0,
2861 Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0,
2862 Convert__Reg1_1__AddrMode52_2__CondCode2_0,
2863 Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
2864 Convert__Reg1_2__AddrMode52_3__CondCode2_0,
2865 Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0,
2866 Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0,
2867 Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0,
2868 Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0,
2869 Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0,
2870 Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0,
2871 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0,
2872 Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0,
2873 Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0,
2874 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0,
2875 Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0,
2876 Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0,
2877 Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0,
2878 Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0,
2879 Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0,
2880 Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0,
2881 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0,
2882 Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0,
2883 Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0,
2884 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0,
2885 Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0,
2886 Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0,
2887 Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0,
2888 Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0,
2889 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0,
2890 Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0,
2891 Convert__Reg1_1__CondCode2_0__imm_95_0,
2892 Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0,
2893 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2894 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2895 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0,
2896 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0,
2897 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0,
2898 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0,
2899 Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
2900 Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0,
2901 Convert__Reg1_2__FPImm1_3__CondCode2_0,
2902 Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
2903 Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0,
2904 Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
2905 Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0,
2906 Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0,
2907 Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
2908 Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0,
2909 Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0,
2910 Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0,
2911 Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
2912 Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
2913 Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
2914 Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0,
2915 Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0,
2916 Convert__Reg1_2__FPImm1_3__VPTPredR4_0,
2917 Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0,
2918 Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0,
2919 Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0,
2920 Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0,
2921 Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0,
2922 Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0,
2923 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0,
2924 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0,
2925 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0,
2926 Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0,
2927 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0,
2928 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0,
2929 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0,
2930 Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0,
2931 ConvertCustom_cvtMVEVMOVQtoDReg,
2932 Convert__Reg1_1__imm_95_0__CondCode2_0,
2933 Convert__imm_95_0__Reg1_2__CondCode2_0,
2934 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2935 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2936 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2937 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2938 Convert__Reg1_1__Reg1_2__VPTPredR4_0,
2939 Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0,
2940 Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0,
2941 Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0,
2942 Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0,
2943 Convert__imm_95_0__imm_95_0__VPTPredN3_0,
2944 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1,
2945 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1,
2946 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2,
2947 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2,
2948 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0,
2949 Convert__ITMask1_0,
2950 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2,
2951 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2,
2952 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2,
2953 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2,
2954 Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
2955 Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
2956 Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
2957 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0,
2958 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0,
2959 Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
2960 Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
2961 Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0,
2962 Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0,
2963 Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0,
2964 Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
2965 Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
2966 Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
2967 Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
2968 Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
2969 Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0,
2970 Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0,
2971 Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0,
2972 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,
2973 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,
2974 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,
2975 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0,
2976 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0,
2977 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0,
2978 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0,
2979 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0,
2980 Convert__CondCode2_0__FPDRegListWithVPR1_1,
2981 Convert__CondCode2_0__FPSRegListWithVPR1_1,
2982 Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0,
2983 Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
2984 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
2985 Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
2986 Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
2987 Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
2988 Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
2989 Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0,
2990 Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0,
2991 Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0,
2992 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0,
2993 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0,
2994 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0,
2995 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0,
2996 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0,
2997 Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2998 Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2999 Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
3000 Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
3001 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
3002 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
3003 Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
3004 Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
3005 Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
3006 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
3007 Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
3008 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
3009 Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
3010 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
3011 Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
3012 Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
3013 Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
3014 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
3015 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
3016 Convert__VecListTwoMQ1_1__MemNoOffsetT21_2,
3017 Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3,
3018 Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
3019 Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
3020 Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
3021 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
3022 Convert__VecListFourMQ1_1__MemNoOffsetT21_2,
3023 Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3,
3024 Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0,
3025 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0,
3026 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0,
3027 Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
3028 Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
3029 Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
3030 Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
3031 Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0,
3032 Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0,
3033 Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0,
3034 Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0,
3035 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0,
3036 Convert__imm_95_2__CondCode2_0,
3037 Convert__imm_95_3__CondCode2_0,
3038 Convert__Reg1_0__Reg1_1__WLSLabel1_2,
3039 Convert__Reg1_1__Reg1_2__WLSLabel1_3,
3040 Convert__imm_95_1__CondCode2_0,
3041 CVT_NUM_SIGNATURES
3042};
3043
3044} // end anonymous namespace
3045
3046static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
3047 // Convert_NoOperands
3048 { CVT_Done },
3049 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1
3050 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3051 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
3052 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3053 // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
3054 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3055 // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
3056 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3057 // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
3058 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3059 // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
3060 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3061 // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
3062 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3063 // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
3064 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3065 // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3066 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3067 // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3068 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3069 // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3070 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3071 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3072 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3073 // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3074 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3075 // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3076 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3077 // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
3078 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3079 // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
3080 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3081 // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
3082 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3083 // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
3084 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3085 // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
3086 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3087 // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
3088 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3089 // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0
3090 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3091 // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0
3092 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3093 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0
3094 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3095 // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
3096 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3097 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1
3098 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3099 // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1
3100 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3101 // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0
3102 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3103 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0
3104 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3105 // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
3106 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3107 // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
3108 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3109 // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
3110 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3111 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
3112 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3113 // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
3114 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3115 // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
3116 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3117 // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
3118 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3119 // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
3120 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3121 // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
3122 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3123 // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
3124 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3125 // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
3126 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3127 // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
3128 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3129 // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
3130 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3131 // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
3132 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3133 // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
3134 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3135 // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
3136 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3137 // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
3138 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3139 // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
3140 { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3141 // Convert__Reg1_1__Imm1_2__CondCode2_0
3142 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3143 // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
3144 { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3145 // Convert__Reg1_2__Imm1_3__CondCode2_0
3146 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3147 // Convert__Reg1_1__Tie0_1_1__Reg1_2
3148 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done },
3149 // Convert__Reg1_1__Reg1_2
3150 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3151 // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
3152 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3153 // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0
3154 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3155 // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
3156 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3157 // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
3158 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3159 // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
3160 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3161 // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
3162 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3163 // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
3164 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3165 // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
3166 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3167 // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
3168 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3169 // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
3170 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3171 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0
3172 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3173 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0
3174 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3175 // Convert__imm_95_45__CondCode2_0
3176 { CVT_imm_95_45, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3177 // Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3
3178 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3179 // ConvertCustom_cvtThumbBranches
3180 { CVT_cvtThumbBranches, 0, CVT_Done },
3181 // Convert__ARMBranchTarget1_1__CondCode2_0
3182 { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3183 // Convert__Imm1_1__Imm1_2__CondCode2_0
3184 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3185 // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0
3186 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3187 // Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3
3188 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done },
3189 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0
3190 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3191 // Convert__Imm1_1__Reg1_2__CondCode2_0
3192 { CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3193 // Convert__imm_95_0
3194 { CVT_imm_95_0, 0, CVT_Done },
3195 // Convert__Imm0_2551_0
3196 { CVT_95_addImmOperands, 1, CVT_Done },
3197 // Convert__Imm0_655351_0
3198 { CVT_95_addImmOperands, 1, CVT_Done },
3199 // Convert__ARMBranchTarget1_0
3200 { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
3201 // Convert__CondCode2_0__ThumbBranchTarget1_1
3202 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
3203 // Convert__CondCode2_0__ThumbBranchTarget1_2
3204 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addThumbBranchTargetOperands, 3, CVT_Done },
3205 // Convert__CondCode2_0__Reg1_1
3206 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 2, CVT_Done },
3207 // Convert__Reg1_0
3208 { CVT_95_Reg, 1, CVT_Done },
3209 // Convert__ThumbBranchTarget1_0
3210 { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
3211 // Convert__Reg1_1__CondCode2_0
3212 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3213 // Convert__CondCode2_0__ARMBranchTarget1_1
3214 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
3215 // Convert__imm_95_15__CondCode2_0
3216 { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3217 // Convert__CondCode2_0
3218 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3219 // Convert__Reg1_0__ThumbBranchTarget1_1
3220 { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
3221 // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3222 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3223 // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3224 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3225 // Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2
3226 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addITCondCodeInvOperands, 3, CVT_Done },
3227 // Convert__imm_95_22__CondCode2_0
3228 { CVT_imm_95_22, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3229 // Convert__CondCode2_0__RegListWithAPSR1_1
3230 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListWithAPSROperands, 2, CVT_Done },
3231 // Convert__Reg1_1__Reg1_2__CondCode2_0
3232 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3233 // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
3234 { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3235 // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
3236 { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3237 // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
3238 { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3239 // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
3240 { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3241 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
3242 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3243 // Convert__Reg1_1__ModImm1_2__CondCode2_0
3244 { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3245 // Convert__Reg1_2__Reg1_3__CondCode2_0
3246 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3247 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
3248 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3249 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
3250 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3251 // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
3252 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3253 // Convert__Imm1_0__ProcIFlags1_1
3254 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
3255 // Convert__Imm0_311_0
3256 { CVT_95_addImmOperands, 1, CVT_Done },
3257 // Convert__Imm0_311_1
3258 { CVT_95_addImmOperands, 2, CVT_Done },
3259 // Convert__Imm1_0__ProcIFlags1_2
3260 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
3261 // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
3262 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3263 // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
3264 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3265 // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
3266 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3267 // Convert__Reg1_0__Reg1_1__Reg1_2
3268 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3269 // Convert__imm_95_20__CondCode2_0
3270 { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3271 // Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3
3272 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done },
3273 // Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1
3274 { CVT_95_Reg, 1, CVT_regZR, 0, CVT_regZR, 0, CVT_95_addITCondCodeInvOperands, 2, CVT_Done },
3275 // Convert__Reg1_1__CoprocNum1_0__Imm13b1_2
3276 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
3277 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0
3278 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3279 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3
3280 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3281 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0
3282 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3283 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4
3284 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3285 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0
3286 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3287 // Convert__Imm0_151_1__CondCode2_0
3288 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3289 // Convert__Imm0_151_2__CondCode2_0
3290 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3291 // Convert__imm_95_12
3292 { CVT_imm_95_12, 0, CVT_Done },
3293 // Convert__imm_95_12__CondCode2_0
3294 { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3295 // Convert__Reg1_0__Reg1_1
3296 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
3297 // Convert__imm_95_15
3298 { CVT_imm_95_15, 0, CVT_Done },
3299 // Convert__MemBarrierOpt1_0
3300 { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
3301 // Convert__MemBarrierOpt1_1__CondCode2_0
3302 { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3303 // Convert__MemBarrierOpt1_2__CondCode2_0
3304 { CVT_95_addMemBarrierOptOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3305 // Convert__imm_95_0__CondCode2_0
3306 { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3307 // Convert__imm_95_16__CondCode2_0
3308 { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3309 // Convert__Reg1_1__FPImm1_2__CondCode2_0
3310 { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3311 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3
3312 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
3313 // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
3314 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
3315 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0
3316 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3317 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0
3318 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3319 // Convert__Imm0_2391_1__CondCode2_0
3320 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3321 // Convert__Imm0_2391_2__CondCode2_0
3322 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3323 // Convert__Imm0_631_0
3324 { CVT_95_addImmOperands, 1, CVT_Done },
3325 // Convert__Imm0_655351_1
3326 { CVT_95_addImmOperands, 2, CVT_Done },
3327 // Convert__InstSyncBarrierOpt1_0
3328 { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
3329 // Convert__InstSyncBarrierOpt1_1__CondCode2_0
3330 { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3331 // Convert__InstSyncBarrierOpt1_2__CondCode2_0
3332 { CVT_95_addInstSyncBarrierOptOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3333 // Convert__ITCondCode1_1__ITMask1_0
3334 { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
3335 // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
3336 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3337 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
3338 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3339 // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
3340 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3341 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
3342 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3343 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
3344 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3345 // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
3346 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
3347 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
3348 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
3349 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
3350 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
3351 // Convert__Reg1_1__CondCode2_0__RegList1_2
3352 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 3, CVT_Done },
3353 // Convert__Reg1_1__CondCode2_0__RegList1_3
3354 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3355 // Convert__Reg1_2__CondCode2_0__RegList1_3
3356 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3357 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3
3358 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3359 // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4
3360 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 5, CVT_Done },
3361 // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
3362 { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3363 // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
3364 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3365 // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
3366 { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3367 // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
3368 { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3369 // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
3370 { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3371 // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
3372 { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3373 // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
3374 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3375 // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
3376 { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3377 // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
3378 { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3379 // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
3380 { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3381 // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
3382 { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3383 // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
3384 { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3385 // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
3386 { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3387 // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
3388 { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3389 // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
3390 { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3391 // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
3392 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3393 // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
3394 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3395 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0
3396 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3397 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0
3398 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3399 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0
3400 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3401 // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
3402 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3403 // Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0
3404 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3405 // Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0
3406 { CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3407 // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
3408 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3409 // Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0
3410 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3411 // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
3412 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3413 // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
3414 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3415 // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
3416 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3417 // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
3418 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3419 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0
3420 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3421 // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
3422 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3423 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0
3424 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3425 // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
3426 { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3427 // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
3428 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3429 // Convert__Reg1_1__AddrMode33_2__CondCode2_0
3430 { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3431 // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
3432 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3433 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0
3434 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3435 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0
3436 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3437 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0
3438 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3439 // Convert__LELabel1_0
3440 { CVT_95_addImmOperands, 1, CVT_Done },
3441 // Convert__imm_95_0__Reg1_0__LELabel1_1
3442 { CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3443 // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
3444 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3445 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
3446 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3447 // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
3448 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3449 // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
3450 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3451 // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
3452 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3453 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
3454 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3455 // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
3456 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3457 // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
3458 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3459 // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
3460 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3461 // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3462 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3463 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
3464 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3465 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3466 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3467 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
3468 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
3469 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3470 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3471 // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
3472 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3473 // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
3474 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
3475 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
3476 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3477 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
3478 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3479 // Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1
3480 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3481 // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
3482 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3483 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
3484 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3485 // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
3486 { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3487 // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
3488 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3489 // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
3490 { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3491 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
3492 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3493 // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
3494 { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3495 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
3496 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3497 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
3498 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3499 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
3500 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3501 // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
3502 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3503 // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3504 { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3505 // Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0
3506 { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3507 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
3508 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3509 // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
3510 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3511 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
3512 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3513 // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
3514 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3515 // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0
3516 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3517 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
3518 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3519 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3520 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3521 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
3522 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
3523 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3524 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3525 // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
3526 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3527 // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
3528 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
3529 // Convert__Reg1_1__BankedReg1_2__CondCode2_0
3530 { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3531 // Convert__Reg1_1__MSRMask1_2__CondCode2_0
3532 { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3533 // Convert__BankedReg1_1__Reg1_2__CondCode2_0
3534 { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3535 // Convert__MSRMask1_1__Reg1_2__CondCode2_0
3536 { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3537 // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
3538 { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3539 // ConvertCustom_cvtThumbMultiply
3540 { CVT_cvtThumbMultiply, 0, CVT_Done },
3541 // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
3542 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3543 // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
3544 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3545 // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
3546 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3547 // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
3548 { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3549 // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3550 { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3551 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
3552 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3553 // Convert__regR8__regR8__imm_95_14__reg0
3554 { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3555 // Convert__regR0__regR0__CondCode2_0__reg0
3556 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3557 // Convert__imm_95_29__CondCode2_0
3558 { CVT_imm_95_29, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3559 // Convert__imm_95_13__CondCode2_0
3560 { CVT_imm_95_13, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3561 // Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3
3562 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3563 // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
3564 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3565 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
3566 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3567 // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
3568 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3569 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
3570 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3571 // Convert__MemImm12Offset2_0
3572 { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
3573 // Convert__MemRegOffset3_0
3574 { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
3575 // Convert__Imm1_1__CondCode2_0
3576 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3577 // Convert__MemNegImm8Offset2_1__CondCode2_0
3578 { CVT_95_addMemImmOffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3579 // Convert__MemUImm12Offset2_1__CondCode2_0
3580 { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3581 // Convert__T2MemRegOffset3_1__CondCode2_0
3582 { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3583 // Convert__MemPCRelImm121_1__CondCode2_0
3584 { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3585 // Convert__Imm1_2__CondCode2_0
3586 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3587 // Convert__MemNegImm8Offset2_2__CondCode2_0
3588 { CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3589 // Convert__MemUImm12Offset2_2__CondCode2_0
3590 { CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3591 // Convert__T2MemRegOffset3_2__CondCode2_0
3592 { CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3593 // Convert__MemPCRelImm121_2__CondCode2_0
3594 { CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3595 // Convert__CondCode2_0__RegList1_1
3596 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 2, CVT_Done },
3597 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1
3598 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 2, CVT_Done },
3599 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2
3600 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 3, CVT_Done },
3601 // Convert__imm_95_4__imm_95_14__reg0
3602 { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3603 // Convert__imm_95_4
3604 { CVT_imm_95_4, 0, CVT_Done },
3605 // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
3606 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3607 // Convert__SetEndImm1_0
3608 { CVT_95_addImmOperands, 1, CVT_Done },
3609 // Convert__Imm0_11_0
3610 { CVT_95_addImmOperands, 1, CVT_Done },
3611 // Convert__imm_95_4__CondCode2_0
3612 { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3613 // Convert__imm_95_5__CondCode2_0
3614 { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3615 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3
3616 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3617 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0
3618 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3619 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0
3620 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3621 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0
3622 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3623 // Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0
3624 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3625 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0
3626 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addMveSaturateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3627 // Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0
3628 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3629 // Convert__Imm0_311_2
3630 { CVT_95_addImmOperands, 3, CVT_Done },
3631 // Convert__Imm0_311_1__CondCode2_0
3632 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3633 // Convert__Imm0_311_2__CondCode2_0
3634 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3635 // Convert__Imm0_311_3__CondCode2_0
3636 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3637 // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
3638 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3639 // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
3640 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3641 // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
3642 { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3643 // Convert__imm_95_0__imm_95_14__reg0
3644 { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3645 // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
3646 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3647 // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
3648 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3649 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0
3650 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3651 // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
3652 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3653 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0
3654 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3655 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0
3656 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3657 // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
3658 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3659 // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
3660 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3661 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0
3662 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3663 // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
3664 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3665 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0
3666 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3667 // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
3668 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3669 // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
3670 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3671 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0
3672 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3673 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0
3674 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3675 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0
3676 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3677 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1
3678 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3679 // Convert__Imm0_2551_3__CondCode2_0
3680 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3681 // Convert__Imm0_2551_1__CondCode2_0
3682 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3683 // Convert__Imm24bit1_1__CondCode2_0
3684 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3685 // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
3686 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3687 // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
3688 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3689 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
3690 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3691 // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
3692 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3693 // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
3694 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3695 // Convert__MemTBB2_1__CondCode2_0
3696 { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3697 // Convert__MemTBH2_1__CondCode2_0
3698 { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3699 // Convert__TraceSyncBarrierOpt1_0
3700 { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done },
3701 // Convert__TraceSyncBarrierOpt1_1__CondCode2_0
3702 { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3703 // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
3704 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3705 // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
3706 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3707 // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
3708 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3709 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0
3710 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3711 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0
3712 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3713 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
3714 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3715 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
3716 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3717 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0
3718 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3719 // Convert__Reg1_2__Reg1_3__VPTPredR4_0
3720 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3721 // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
3722 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3723 // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
3724 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3725 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0
3726 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_imm_95_0, 0, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3727 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0
3728 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3729 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0
3730 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3731 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0
3732 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3733 // Convert__Reg1_2__Reg1_3__VPTPredN3_0
3734 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3735 // Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0
3736 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3737 // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
3738 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3739 // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0
3740 { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3741 // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0
3742 { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3743 // Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0
3744 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi16splatNotOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3745 // Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0
3746 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi32splatNotOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3747 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0
3748 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3749 // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0
3750 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3751 // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0
3752 { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3753 // Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0
3754 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3755 // Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0
3756 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi32splatOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3757 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0
3758 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3759 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0
3760 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3761 // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4
3762 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
3763 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0
3764 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationOddOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3765 // Convert__Reg1_2__Reg1_2__CondCode2_0
3766 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3767 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4
3768 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3769 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5
3770 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3771 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5
3772 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3773 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0
3774 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3775 // Convert__Reg1_2__CondCode2_0
3776 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3777 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0
3778 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3779 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0
3780 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3781 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0
3782 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3783 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0
3784 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3785 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0
3786 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3787 // Convert__imm_95_0__Reg1_2__VPTPredN3_0
3788 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3789 // Convert__Reg1_3__Reg1_4__CondCode2_0
3790 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3791 // Convert__Reg1_3__Reg1_4__VPTPredR4_0
3792 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3793 // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0
3794 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3795 // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
3796 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3797 // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0
3798 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3799 // Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0
3800 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3801 // Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0
3802 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3803 // Convert__Reg1_2__Reg1_3
3804 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3805 // Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0
3806 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3807 // Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0
3808 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3809 // Convert__Reg1_1__CoprocNum1_0__Imm11b1_2
3810 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
3811 // Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0
3812 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3813 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2
3814 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_Done },
3815 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0
3816 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3817 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3
3818 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3819 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0
3820 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3821 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3
3822 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3823 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0
3824 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3825 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4
3826 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3827 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0
3828 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3829 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4
3830 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3831 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0
3832 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3833 // Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0
3834 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_addPowerTwoOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3835 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3
3836 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3837 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4
3838 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3839 // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
3840 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3841 // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
3842 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3843 // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
3844 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3845 // Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0
3846 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addPowerTwoOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3847 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
3848 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3849 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
3850 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3851 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
3852 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3853 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
3854 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3855 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
3856 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3857 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
3858 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3859 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
3860 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3861 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
3862 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3863 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4
3864 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
3865 // Convert__Reg1_1__Reg1_2__Reg1_3
3866 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3867 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4
3868 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
3869 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
3870 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3871 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3872 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3873 // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
3874 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3875 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
3876 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3877 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3878 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3879 // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
3880 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3881 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
3882 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3883 // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
3884 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3885 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3886 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3887 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3888 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3889 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3890 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3891 // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
3892 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3893 // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
3894 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3895 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
3896 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3897 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3898 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3899 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3900 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3901 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
3902 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3903 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3904 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3905 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
3906 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3907 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3908 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3909 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3910 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3911 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3912 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3913 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
3914 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3915 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
3916 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3917 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
3918 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3919 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
3920 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3921 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
3922 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3923 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3924 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3925 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3926 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3927 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3928 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3929 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3930 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3931 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3932 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3933 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
3934 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3935 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
3936 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3937 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
3938 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3939 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
3940 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3941 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
3942 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3943 // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0
3944 { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3945 // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
3946 { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3947 // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
3948 { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3949 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3950 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3951 // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
3952 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3953 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3954 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3955 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3956 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3957 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
3958 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3959 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
3960 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3961 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3962 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3963 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3964 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3965 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3966 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3967 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
3968 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3969 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3970 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3971 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3972 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3973 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
3974 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3975 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3976 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3977 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3978 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3979 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3980 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3981 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
3982 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3983 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3984 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3985 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
3986 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3987 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3988 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3989 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3990 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3991 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3992 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3993 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3994 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3995 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3996 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3997 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
3998 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3999 // Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2
4000 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4001 // Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3
4002 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done },
4003 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
4004 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4005 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4006 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4007 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
4008 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4009 // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
4010 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4011 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4012 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4013 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4014 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4015 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4016 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4017 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4018 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4019 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
4020 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4021 // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4022 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4023 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4024 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4025 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
4026 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4027 // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4028 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4029 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4030 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4031 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4032 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4033 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4034 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4035 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4036 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4037 // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
4038 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4039 // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
4040 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4041 // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
4042 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4043 // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
4044 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4045 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
4046 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4047 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
4048 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4049 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
4050 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4051 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
4052 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4053 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
4054 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4055 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
4056 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4057 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
4058 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4059 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
4060 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4061 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
4062 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4063 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
4064 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4065 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
4066 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4067 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
4068 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4069 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
4070 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4071 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
4072 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4073 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4074 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4075 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
4076 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4077 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
4078 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4079 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4080 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4081 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
4082 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4083 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
4084 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4085 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
4086 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4087 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
4088 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4089 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
4090 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4091 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
4092 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4093 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
4094 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4095 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
4096 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4097 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
4098 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4099 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
4100 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4101 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
4102 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4103 // Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2
4104 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4105 // Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3
4106 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done },
4107 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3
4108 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
4109 // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
4110 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
4111 // Convert__MemImm7s4Offset2_2__CondCode2_0
4112 { CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4113 // Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0
4114 { CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4115 // Convert__Reg1_1__AddrMode52_2__CondCode2_0
4116 { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4117 // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
4118 { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4119 // Convert__Reg1_2__AddrMode52_3__CondCode2_0
4120 { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4121 // Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0
4122 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4123 // Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0
4124 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4125 // Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0
4126 { CVT_imm_95_0, 0, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4127 // Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0
4128 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4129 // Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0
4130 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4131 // Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0
4132 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4133 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0
4134 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4135 // Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0
4136 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4137 // Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0
4138 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4139 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0
4140 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4141 // Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0
4142 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4143 // Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0
4144 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4145 // Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0
4146 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4147 // Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0
4148 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4149 // Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0
4150 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4151 // Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0
4152 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4153 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0
4154 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4155 // Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0
4156 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4157 // Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0
4158 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4159 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0
4160 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4161 // Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0
4162 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4163 // Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0
4164 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4165 // Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0
4166 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4167 // Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0
4168 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4169 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0
4170 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift2Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4171 // Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0
4172 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4173 // Convert__Reg1_1__CondCode2_0__imm_95_0
4174 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_imm_95_0, 0, CVT_Done },
4175 // Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0
4176 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4177 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
4178 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4179 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
4180 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4181 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0
4182 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4183 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0
4184 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4185 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0
4186 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4187 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0
4188 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4189 // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
4190 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4191 // Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0
4192 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4193 // Convert__Reg1_2__FPImm1_3__CondCode2_0
4194 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4195 // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
4196 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4197 // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0
4198 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4199 // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
4200 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4201 // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0
4202 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4203 // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0
4204 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4205 // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
4206 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4207 // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0
4208 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4209 // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0
4210 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4211 // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0
4212 { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4213 // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
4214 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4215 // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
4216 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4217 // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
4218 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4219 // Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0
4220 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4221 // Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0
4222 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4223 // Convert__Reg1_2__FPImm1_3__VPTPredR4_0
4224 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4225 // Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0
4226 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4227 // Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0
4228 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4229 // Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0
4230 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4231 // Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0
4232 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4233 // Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0
4234 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4235 // Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0
4236 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4237 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0
4238 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4239 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0
4240 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4241 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0
4242 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4243 // Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0
4244 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4245 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0
4246 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4247 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0
4248 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4249 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0
4250 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4251 // Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0
4252 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_4, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addMVEPairVectorIndexOperands, 3, CVT_95_addMVEPairVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4253 // ConvertCustom_cvtMVEVMOVQtoDReg
4254 { CVT_cvtMVEVMOVQtoDReg, 0, CVT_Done },
4255 // Convert__Reg1_1__imm_95_0__CondCode2_0
4256 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4257 // Convert__imm_95_0__Reg1_2__CondCode2_0
4258 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4259 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
4260 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4261 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
4262 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4263 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
4264 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4265 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
4266 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4267 // Convert__Reg1_1__Reg1_2__VPTPredR4_0
4268 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4269 // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0
4270 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4271 // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0
4272 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4273 // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0
4274 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4275 // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0
4276 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4277 // Convert__imm_95_0__imm_95_0__VPTPredN3_0
4278 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4279 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1
4280 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
4281 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1
4282 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
4283 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2
4284 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
4285 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2
4286 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
4287 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0
4288 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4289 // Convert__ITMask1_0
4290 { CVT_95_addITMaskOperands, 1, CVT_Done },
4291 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2
4292 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4293 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2
4294 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4295 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2
4296 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4297 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2
4298 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4299 // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
4300 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4301 // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
4302 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4303 // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
4304 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4305 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0
4306 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4307 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0
4308 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4309 // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
4310 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4311 // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
4312 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4313 // Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0
4314 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4315 // Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0
4316 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4317 // Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0
4318 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4319 // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
4320 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4321 // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
4322 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4323 // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
4324 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4325 // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
4326 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4327 // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
4328 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4329 // Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0
4330 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4331 // Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0
4332 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4333 // Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0
4334 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4335 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0
4336 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4337 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0
4338 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4339 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0
4340 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4341 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0
4342 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4343 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0
4344 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4345 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0
4346 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4347 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0
4348 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4349 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0
4350 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4351 // Convert__CondCode2_0__FPDRegListWithVPR1_1
4352 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addFPDRegListWithVPROperands, 2, CVT_Done },
4353 // Convert__CondCode2_0__FPSRegListWithVPR1_1
4354 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addFPSRegListWithVPROperands, 2, CVT_Done },
4355 // Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0
4356 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4357 // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
4358 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4359 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
4360 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4361 // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
4362 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4363 // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
4364 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4365 // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
4366 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4367 // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
4368 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4369 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0
4370 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4371 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0
4372 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4373 // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0
4374 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4375 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0
4376 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4377 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0
4378 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4379 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0
4380 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4381 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0
4382 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4383 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0
4384 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4385 // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
4386 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4387 // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
4388 { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4389 // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
4390 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4391 // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
4392 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4393 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
4394 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4395 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
4396 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4397 // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
4398 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4399 // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
4400 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4401 // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
4402 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4403 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
4404 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4405 // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
4406 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4407 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
4408 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4409 // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
4410 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4411 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
4412 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4413 // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
4414 { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4415 // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
4416 { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4417 // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
4418 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4419 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
4420 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4421 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
4422 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4423 // Convert__VecListTwoMQ1_1__MemNoOffsetT21_2
4424 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4425 // Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3
4426 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done },
4427 // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
4428 { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4429 // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
4430 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4431 // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
4432 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4433 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
4434 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4435 // Convert__VecListFourMQ1_1__MemNoOffsetT21_2
4436 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4437 // Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3
4438 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done },
4439 // Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0
4440 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_imm_95_0, 0, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4441 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0
4442 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4443 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0
4444 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4445 // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
4446 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4447 // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
4448 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4449 // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
4450 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4451 // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
4452 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4453 // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0
4454 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4455 // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0
4456 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4457 // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0
4458 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4459 // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0
4460 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4461 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0
4462 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4463 // Convert__imm_95_2__CondCode2_0
4464 { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4465 // Convert__imm_95_3__CondCode2_0
4466 { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4467 // Convert__Reg1_0__Reg1_1__WLSLabel1_2
4468 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
4469 // Convert__Reg1_1__Reg1_2__WLSLabel1_3
4470 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4471 // Convert__imm_95_1__CondCode2_0
4472 { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4473};
4474
4475void ARMAsmParser::
4476convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4477 const OperandVector &Operands,
4478 const SmallBitVector &OptionalOperandsMask,
4479 ArrayRef<unsigned> DefaultsOffset) {
4480 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4481 const uint8_t *Converter = ConversionTable[Kind];
4482 Inst.setOpcode(Opcode);
4483 for (const uint8_t *p = Converter; *p; p += 2) {
4484 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
4485 switch (*p) {
4486 default: llvm_unreachable("invalid conversion entry!");
4487 case CVT_Reg:
4488 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4489 break;
4490 case CVT_Tied: {
4491 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
4492 std::begin(TiedAsmOperandTable)) &&
4493 "Tied operand not found");
4494 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
4495 if (TiedResOpnd != (uint8_t)-1)
4496 Inst.addOperand(Inst.getOperand(TiedResOpnd));
4497 break;
4498 }
4499 case CVT_95_Reg:
4500 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4501 break;
4502 case CVT_95_addCCOutOperands_95_defaultCCOutOp:
4503 if (OptionalOperandsMask[*(p + 1) - 1]) {
4504 defaultCCOutOp()->addCCOutOperands(Inst, 1);
4505 } else {
4506 static_cast<ARMOperand &>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
4507 }
4508 break;
4509 case CVT_95_addCondCodeOperands_95_defaultCondCodeOp:
4510 if (OptionalOperandsMask[*(p + 1) - 1]) {
4511 defaultCondCodeOp()->addCondCodeOperands(Inst, 2);
4512 } else {
4513 static_cast<ARMOperand &>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
4514 }
4515 break;
4516 case CVT_95_addRegShiftedImmOperands:
4517 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
4518 break;
4519 case CVT_95_addImmOperands:
4520 static_cast<ARMOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
4521 break;
4522 case CVT_95_addT2SOImmNotOperands:
4523 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
4524 break;
4525 case CVT_95_addRegShiftedRegOperands:
4526 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
4527 break;
4528 case CVT_95_addModImmOperands:
4529 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
4530 break;
4531 case CVT_95_addModImmNotOperands:
4532 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
4533 break;
4534 case CVT_95_addImm0_95_508s4Operands:
4535 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
4536 break;
4537 case CVT_regSP:
4538 Inst.addOperand(MCOperand::createReg(ARM::SP));
4539 break;
4540 case CVT_95_addImm0_95_508s4NegOperands:
4541 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
4542 break;
4543 case CVT_95_addThumbModImmNeg8_95_255Operands:
4544 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
4545 break;
4546 case CVT_95_addImm0_95_1020s4Operands:
4547 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
4548 break;
4549 case CVT_95_addThumbModImmNeg1_95_7Operands:
4550 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
4551 break;
4552 case CVT_95_addImm0_95_4095NegOperands:
4553 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
4554 break;
4555 case CVT_95_addT2SOImmNegOperands:
4556 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
4557 break;
4558 case CVT_95_addModImmNegOperands:
4559 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
4560 break;
4561 case CVT_95_addUnsignedOffset_95_b8s2Operands:
4562 static_cast<ARMOperand &>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
4563 break;
4564 case CVT_95_addAdrLabelOperands:
4565 static_cast<ARMOperand &>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
4566 break;
4567 case CVT_imm_95_45:
4568 Inst.addOperand(MCOperand::createImm(45));
4569 break;
4570 case CVT_cvtThumbBranches:
4571 cvtThumbBranches(Inst, Operands);
4572 break;
4573 case CVT_95_addARMBranchTargetOperands:
4574 static_cast<ARMOperand &>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
4575 break;
4576 case CVT_95_addBitfieldOperands:
4577 static_cast<ARMOperand &>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
4578 break;
4579 case CVT_95_addITCondCodeOperands:
4580 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
4581 break;
4582 case CVT_imm_95_0:
4583 Inst.addOperand(MCOperand::createImm(0));
4584 break;
4585 case CVT_95_addThumbBranchTargetOperands:
4586 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
4587 break;
4588 case CVT_imm_95_15:
4589 Inst.addOperand(MCOperand::createImm(15));
4590 break;
4591 case CVT_95_addCoprocNumOperands:
4592 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
4593 break;
4594 case CVT_95_addCoprocRegOperands:
4595 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
4596 break;
4597 case CVT_95_addITCondCodeInvOperands:
4598 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeInvOperands(Inst, 1);
4599 break;
4600 case CVT_imm_95_22:
4601 Inst.addOperand(MCOperand::createImm(22));
4602 break;
4603 case CVT_95_addRegListWithAPSROperands:
4604 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListWithAPSROperands(Inst, 1);
4605 break;
4606 case CVT_95_addProcIFlagsOperands:
4607 static_cast<ARMOperand &>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
4608 break;
4609 case CVT_imm_95_20:
4610 Inst.addOperand(MCOperand::createImm(20));
4611 break;
4612 case CVT_regZR:
4613 Inst.addOperand(MCOperand::createReg(ARM::ZR));
4614 break;
4615 case CVT_imm_95_12:
4616 Inst.addOperand(MCOperand::createImm(12));
4617 break;
4618 case CVT_95_addMemBarrierOptOperands:
4619 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
4620 break;
4621 case CVT_imm_95_16:
4622 Inst.addOperand(MCOperand::createImm(16));
4623 break;
4624 case CVT_95_addFPImmOperands:
4625 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
4626 break;
4627 case CVT_95_addDPRRegListOperands:
4628 static_cast<ARMOperand &>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
4629 break;
4630 case CVT_imm_95_1:
4631 Inst.addOperand(MCOperand::createImm(1));
4632 break;
4633 case CVT_95_addInstSyncBarrierOptOperands:
4634 static_cast<ARMOperand &>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
4635 break;
4636 case CVT_95_addITMaskOperands:
4637 static_cast<ARMOperand &>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
4638 break;
4639 case CVT_95_addMemNoOffsetOperands:
4640 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
4641 break;
4642 case CVT_95_addAddrMode5Operands:
4643 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
4644 break;
4645 case CVT_95_addCoprocOptionOperands:
4646 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
4647 break;
4648 case CVT_95_addPostIdxImm8s4Operands:
4649 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
4650 break;
4651 case CVT_95_addRegListOperands:
4652 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
4653 break;
4654 case CVT_95_addThumbMemPCOperands:
4655 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
4656 break;
4657 case CVT_95_addMemThumbRIs4Operands:
4658 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
4659 break;
4660 case CVT_95_addMemThumbRROperands:
4661 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
4662 break;
4663 case CVT_95_addMemThumbSPIOperands:
4664 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
4665 break;
4666 case CVT_95_addConstPoolAsmImmOperands:
4667 static_cast<ARMOperand &>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
4668 break;
4669 case CVT_95_addMemImm12OffsetOperands:
4670 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
4671 break;
4672 case CVT_95_addMemImmOffsetOperands:
4673 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImmOffsetOperands(Inst, 2);
4674 break;
4675 case CVT_95_addMemRegOffsetOperands:
4676 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
4677 break;
4678 case CVT_95_addMemUImm12OffsetOperands:
4679 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
4680 break;
4681 case CVT_95_addT2MemRegOffsetOperands:
4682 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
4683 break;
4684 case CVT_95_addMemPCRelImm12Operands:
4685 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
4686 break;
4687 case CVT_95_addAM2OffsetImmOperands:
4688 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
4689 break;
4690 case CVT_95_addPostIdxRegShiftedOperands:
4691 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
4692 break;
4693 case CVT_95_addMemThumbRIs1Operands:
4694 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
4695 break;
4696 case CVT_95_addMemImm8s4OffsetOperands:
4697 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
4698 break;
4699 case CVT_95_addAddrMode3Operands:
4700 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
4701 break;
4702 case CVT_95_addAM3OffsetOperands:
4703 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
4704 break;
4705 case CVT_95_addMemImm0_95_1020s4OffsetOperands:
4706 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
4707 break;
4708 case CVT_95_addMemThumbRIs2Operands:
4709 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
4710 break;
4711 case CVT_95_addPostIdxRegOperands:
4712 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
4713 break;
4714 case CVT_95_addPostIdxImm8Operands:
4715 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
4716 break;
4717 case CVT_reg0:
4718 Inst.addOperand(MCOperand::createReg(0));
4719 break;
4720 case CVT_regCPSR:
4721 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
4722 break;
4723 case CVT_imm_95_14:
4724 Inst.addOperand(MCOperand::createImm(14));
4725 break;
4726 case CVT_95_addBankedRegOperands:
4727 static_cast<ARMOperand &>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
4728 break;
4729 case CVT_95_addMSRMaskOperands:
4730 static_cast<ARMOperand &>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
4731 break;
4732 case CVT_cvtThumbMultiply:
4733 cvtThumbMultiply(Inst, Operands);
4734 break;
4735 case CVT_regR8:
4736 Inst.addOperand(MCOperand::createReg(ARM::R8));
4737 break;
4738 case CVT_regR0:
4739 Inst.addOperand(MCOperand::createReg(ARM::R0));
4740 break;
4741 case CVT_imm_95_29:
4742 Inst.addOperand(MCOperand::createImm(29));
4743 break;
4744 case CVT_imm_95_13:
4745 Inst.addOperand(MCOperand::createImm(13));
4746 break;
4747 case CVT_95_addPKHASRImmOperands:
4748 static_cast<ARMOperand &>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
4749 break;
4750 case CVT_imm_95_4:
4751 Inst.addOperand(MCOperand::createImm(4));
4752 break;
4753 case CVT_95_addImm1_95_32Operands:
4754 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
4755 break;
4756 case CVT_imm_95_5:
4757 Inst.addOperand(MCOperand::createImm(5));
4758 break;
4759 case CVT_95_addMveSaturateOperands:
4760 static_cast<ARMOperand &>(*Operands[OpIdx]).addMveSaturateOperands(Inst, 1);
4761 break;
4762 case CVT_95_addShifterImmOperands:
4763 static_cast<ARMOperand &>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
4764 break;
4765 case CVT_95_addImm1_95_16Operands:
4766 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
4767 break;
4768 case CVT_95_addRotImmOperands:
4769 static_cast<ARMOperand &>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
4770 break;
4771 case CVT_95_addMemTBBOperands:
4772 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
4773 break;
4774 case CVT_95_addMemTBHOperands:
4775 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
4776 break;
4777 case CVT_95_addTraceSyncBarrierOptOperands:
4778 static_cast<ARMOperand &>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1);
4779 break;
4780 case CVT_95_addVPTPredNOperands_95_defaultVPTPredOp:
4781 if (OptionalOperandsMask[*(p + 1) - 1]) {
4782 defaultVPTPredOp()->addVPTPredNOperands(Inst, 3);
4783 } else {
4784 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredNOperands(Inst, 3);
4785 }
4786 break;
4787 case CVT_95_addVPTPredROperands_95_defaultVPTPredOp:
4788 if (OptionalOperandsMask[*(p + 1) - 1]) {
4789 defaultVPTPredOp()->addVPTPredROperands(Inst, 4);
4790 } else {
4791 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredROperands(Inst, 4);
4792 }
4793 break;
4794 case CVT_95_addNEONi16splatNotOperands:
4795 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
4796 break;
4797 case CVT_95_addNEONi32splatNotOperands:
4798 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
4799 break;
4800 case CVT_95_addNEONi16splatOperands:
4801 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
4802 break;
4803 case CVT_95_addNEONi32splatOperands:
4804 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
4805 break;
4806 case CVT_95_addComplexRotationOddOperands:
4807 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
4808 break;
4809 case CVT_95_addComplexRotationEvenOperands:
4810 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
4811 break;
4812 case CVT_95_addVectorIndex64Operands:
4813 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1);
4814 break;
4815 case CVT_95_addVectorIndex32Operands:
4816 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
4817 break;
4818 case CVT_95_addFBits16Operands:
4819 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
4820 break;
4821 case CVT_95_addFBits32Operands:
4822 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
4823 break;
4824 case CVT_95_addPowerTwoOperands:
4825 static_cast<ARMOperand &>(*Operands[OpIdx]).addPowerTwoOperands(Inst, 1);
4826 break;
4827 case CVT_95_addVectorIndex16Operands:
4828 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
4829 break;
4830 case CVT_95_addVectorIndex8Operands:
4831 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
4832 break;
4833 case CVT_95_addVecListOperands:
4834 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
4835 break;
4836 case CVT_95_addDupAlignedMemory16Operands:
4837 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
4838 break;
4839 case CVT_95_addAlignedMemory64or128Operands:
4840 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
4841 break;
4842 case CVT_95_addAlignedMemory64or128or256Operands:
4843 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
4844 break;
4845 case CVT_95_addAlignedMemory64Operands:
4846 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
4847 break;
4848 case CVT_95_addVecListIndexedOperands:
4849 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
4850 break;
4851 case CVT_95_addAlignedMemory16Operands:
4852 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
4853 break;
4854 case CVT_95_addDupAlignedMemory32Operands:
4855 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
4856 break;
4857 case CVT_95_addAlignedMemory32Operands:
4858 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
4859 break;
4860 case CVT_95_addDupAlignedMemoryNoneOperands:
4861 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
4862 break;
4863 case CVT_95_addAlignedMemoryNoneOperands:
4864 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
4865 break;
4866 case CVT_95_addAlignedMemoryOperands:
4867 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
4868 break;
4869 case CVT_95_addDupAlignedMemory64Operands:
4870 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
4871 break;
4872 case CVT_95_addMVEVecListOperands:
4873 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVecListOperands(Inst, 1);
4874 break;
4875 case CVT_95_addMemNoOffsetT2Operands:
4876 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2Operands(Inst, 1);
4877 break;
4878 case CVT_95_addMemNoOffsetT2NoSpOperands:
4879 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2NoSpOperands(Inst, 1);
4880 break;
4881 case CVT_95_addDupAlignedMemory64or128Operands:
4882 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
4883 break;
4884 case CVT_95_addSPRRegListOperands:
4885 static_cast<ARMOperand &>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
4886 break;
4887 case CVT_95_addMemImm7s4OffsetOperands:
4888 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm7s4OffsetOperands(Inst, 2);
4889 break;
4890 case CVT_95_addAddrMode5FP16Operands:
4891 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
4892 break;
4893 case CVT_95_addImm7s4Operands:
4894 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7s4Operands(Inst, 1);
4895 break;
4896 case CVT_95_addMemRegRQOffsetOperands:
4897 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegRQOffsetOperands(Inst, 2);
4898 break;
4899 case CVT_95_addMemNoOffsetTOperands:
4900 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetTOperands(Inst, 1);
4901 break;
4902 case CVT_95_addImm7Shift0Operands:
4903 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift0Operands(Inst, 1);
4904 break;
4905 case CVT_95_addImm7Shift1Operands:
4906 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift1Operands(Inst, 1);
4907 break;
4908 case CVT_95_addImm7Shift2Operands:
4909 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift2Operands(Inst, 1);
4910 break;
4911 case CVT_95_addNEONi32vmovOperands:
4912 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
4913 break;
4914 case CVT_95_addNEONvmovi8ReplicateOperands:
4915 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1);
4916 break;
4917 case CVT_95_addNEONvmovi16ReplicateOperands:
4918 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1);
4919 break;
4920 case CVT_95_addNEONi32vmovNegOperands:
4921 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
4922 break;
4923 case CVT_95_addNEONvmovi32ReplicateOperands:
4924 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1);
4925 break;
4926 case CVT_95_addNEONi64splatOperands:
4927 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
4928 break;
4929 case CVT_95_addNEONi8splatOperands:
4930 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
4931 break;
4932 case CVT_95_addMVEVectorIndexOperands:
4933 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVectorIndexOperands(Inst, 1);
4934 break;
4935 case CVT_95_addMVEPairVectorIndexOperands:
4936 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEPairVectorIndexOperands(Inst, 1);
4937 break;
4938 case CVT_cvtMVEVMOVQtoDReg:
4939 cvtMVEVMOVQtoDReg(Inst, Operands);
4940 break;
4941 case CVT_95_addNEONinvi8ReplicateOperands:
4942 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1);
4943 break;
4944 case CVT_95_addFPDRegListWithVPROperands:
4945 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPDRegListWithVPROperands(Inst, 1);
4946 break;
4947 case CVT_95_addFPSRegListWithVPROperands:
4948 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPSRegListWithVPROperands(Inst, 1);
4949 break;
4950 case CVT_imm_95_2:
4951 Inst.addOperand(MCOperand::createImm(2));
4952 break;
4953 case CVT_imm_95_3:
4954 Inst.addOperand(MCOperand::createImm(3));
4955 break;
4956 }
4957 }
4958}
4959
4960void ARMAsmParser::
4961convertToMapAndConstraints(unsigned Kind,
4962 const OperandVector &Operands) {
4963 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4964 unsigned NumMCOperands = 0;
4965 const uint8_t *Converter = ConversionTable[Kind];
4966 for (const uint8_t *p = Converter; *p; p += 2) {
4967 switch (*p) {
4968 default: llvm_unreachable("invalid conversion entry!");
4969 case CVT_Reg:
4970 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4971 Operands[*(p + 1)]->setConstraint("r");
4972 ++NumMCOperands;
4973 break;
4974 case CVT_Tied:
4975 ++NumMCOperands;
4976 break;
4977 case CVT_95_Reg:
4978 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4979 Operands[*(p + 1)]->setConstraint("r");
4980 NumMCOperands += 1;
4981 break;
4982 case CVT_95_addCCOutOperands_95_defaultCCOutOp:
4983 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4984 Operands[*(p + 1)]->setConstraint("m");
4985 NumMCOperands += 1;
4986 break;
4987 case CVT_95_addCondCodeOperands_95_defaultCondCodeOp:
4988 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4989 Operands[*(p + 1)]->setConstraint("m");
4990 NumMCOperands += 2;
4991 break;
4992 case CVT_95_addRegShiftedImmOperands:
4993 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4994 Operands[*(p + 1)]->setConstraint("m");
4995 NumMCOperands += 2;
4996 break;
4997 case CVT_95_addImmOperands:
4998 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4999 Operands[*(p + 1)]->setConstraint("m");
5000 NumMCOperands += 1;
5001 break;
5002 case CVT_95_addT2SOImmNotOperands:
5003 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5004 Operands[*(p + 1)]->setConstraint("m");
5005 NumMCOperands += 1;
5006 break;
5007 case CVT_95_addRegShiftedRegOperands:
5008 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5009 Operands[*(p + 1)]->setConstraint("m");
5010 NumMCOperands += 3;
5011 break;
5012 case CVT_95_addModImmOperands:
5013 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5014 Operands[*(p + 1)]->setConstraint("m");
5015 NumMCOperands += 1;
5016 break;
5017 case CVT_95_addModImmNotOperands:
5018 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5019 Operands[*(p + 1)]->setConstraint("m");
5020 NumMCOperands += 1;
5021 break;
5022 case CVT_95_addImm0_95_508s4Operands:
5023 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5024 Operands[*(p + 1)]->setConstraint("m");
5025 NumMCOperands += 1;
5026 break;
5027 case CVT_regSP:
5028 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5029 Operands[*(p + 1)]->setConstraint("m");
5030 ++NumMCOperands;
5031 break;
5032 case CVT_95_addImm0_95_508s4NegOperands:
5033 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5034 Operands[*(p + 1)]->setConstraint("m");
5035 NumMCOperands += 1;
5036 break;
5037 case CVT_95_addThumbModImmNeg8_95_255Operands:
5038 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5039 Operands[*(p + 1)]->setConstraint("m");
5040 NumMCOperands += 1;
5041 break;
5042 case CVT_95_addImm0_95_1020s4Operands:
5043 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5044 Operands[*(p + 1)]->setConstraint("m");
5045 NumMCOperands += 1;
5046 break;
5047 case CVT_95_addThumbModImmNeg1_95_7Operands:
5048 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5049 Operands[*(p + 1)]->setConstraint("m");
5050 NumMCOperands += 1;
5051 break;
5052 case CVT_95_addImm0_95_4095NegOperands:
5053 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5054 Operands[*(p + 1)]->setConstraint("m");
5055 NumMCOperands += 1;
5056 break;
5057 case CVT_95_addT2SOImmNegOperands:
5058 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5059 Operands[*(p + 1)]->setConstraint("m");
5060 NumMCOperands += 1;
5061 break;
5062 case CVT_95_addModImmNegOperands:
5063 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5064 Operands[*(p + 1)]->setConstraint("m");
5065 NumMCOperands += 1;
5066 break;
5067 case CVT_95_addUnsignedOffset_95_b8s2Operands:
5068 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5069 Operands[*(p + 1)]->setConstraint("m");
5070 NumMCOperands += 1;
5071 break;
5072 case CVT_95_addAdrLabelOperands:
5073 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5074 Operands[*(p + 1)]->setConstraint("m");
5075 NumMCOperands += 1;
5076 break;
5077 case CVT_imm_95_45:
5078 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5079 Operands[*(p + 1)]->setConstraint("");
5080 ++NumMCOperands;
5081 break;
5082 case CVT_95_addARMBranchTargetOperands:
5083 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5084 Operands[*(p + 1)]->setConstraint("m");
5085 NumMCOperands += 1;
5086 break;
5087 case CVT_95_addBitfieldOperands:
5088 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5089 Operands[*(p + 1)]->setConstraint("m");
5090 NumMCOperands += 1;
5091 break;
5092 case CVT_95_addITCondCodeOperands:
5093 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5094 Operands[*(p + 1)]->setConstraint("m");
5095 NumMCOperands += 1;
5096 break;
5097 case CVT_imm_95_0:
5098 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5099 Operands[*(p + 1)]->setConstraint("");
5100 ++NumMCOperands;
5101 break;
5102 case CVT_95_addThumbBranchTargetOperands:
5103 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5104 Operands[*(p + 1)]->setConstraint("m");
5105 NumMCOperands += 1;
5106 break;
5107 case CVT_imm_95_15:
5108 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5109 Operands[*(p + 1)]->setConstraint("");
5110 ++NumMCOperands;
5111 break;
5112 case CVT_95_addCoprocNumOperands:
5113 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5114 Operands[*(p + 1)]->setConstraint("m");
5115 NumMCOperands += 1;
5116 break;
5117 case CVT_95_addCoprocRegOperands:
5118 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5119 Operands[*(p + 1)]->setConstraint("m");
5120 NumMCOperands += 1;
5121 break;
5122 case CVT_95_addITCondCodeInvOperands:
5123 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5124 Operands[*(p + 1)]->setConstraint("m");
5125 NumMCOperands += 1;
5126 break;
5127 case CVT_imm_95_22:
5128 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5129 Operands[*(p + 1)]->setConstraint("");
5130 ++NumMCOperands;
5131 break;
5132 case CVT_95_addRegListWithAPSROperands:
5133 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5134 Operands[*(p + 1)]->setConstraint("m");
5135 NumMCOperands += 1;
5136 break;
5137 case CVT_95_addProcIFlagsOperands:
5138 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5139 Operands[*(p + 1)]->setConstraint("m");
5140 NumMCOperands += 1;
5141 break;
5142 case CVT_imm_95_20:
5143 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5144 Operands[*(p + 1)]->setConstraint("");
5145 ++NumMCOperands;
5146 break;
5147 case CVT_regZR:
5148 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5149 Operands[*(p + 1)]->setConstraint("m");
5150 ++NumMCOperands;
5151 break;
5152 case CVT_imm_95_12:
5153 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5154 Operands[*(p + 1)]->setConstraint("");
5155 ++NumMCOperands;
5156 break;
5157 case CVT_95_addMemBarrierOptOperands:
5158 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5159 Operands[*(p + 1)]->setConstraint("m");
5160 NumMCOperands += 1;
5161 break;
5162 case CVT_imm_95_16:
5163 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5164 Operands[*(p + 1)]->setConstraint("");
5165 ++NumMCOperands;
5166 break;
5167 case CVT_95_addFPImmOperands:
5168 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5169 Operands[*(p + 1)]->setConstraint("m");
5170 NumMCOperands += 1;
5171 break;
5172 case CVT_95_addDPRRegListOperands:
5173 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5174 Operands[*(p + 1)]->setConstraint("m");
5175 NumMCOperands += 1;
5176 break;
5177 case CVT_imm_95_1:
5178 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5179 Operands[*(p + 1)]->setConstraint("");
5180 ++NumMCOperands;
5181 break;
5182 case CVT_95_addInstSyncBarrierOptOperands:
5183 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5184 Operands[*(p + 1)]->setConstraint("m");
5185 NumMCOperands += 1;
5186 break;
5187 case CVT_95_addITMaskOperands:
5188 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5189 Operands[*(p + 1)]->setConstraint("m");
5190 NumMCOperands += 1;
5191 break;
5192 case CVT_95_addMemNoOffsetOperands:
5193 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5194 Operands[*(p + 1)]->setConstraint("m");
5195 NumMCOperands += 1;
5196 break;
5197 case CVT_95_addAddrMode5Operands:
5198 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5199 Operands[*(p + 1)]->setConstraint("m");
5200 NumMCOperands += 2;
5201 break;
5202 case CVT_95_addCoprocOptionOperands:
5203 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5204 Operands[*(p + 1)]->setConstraint("m");
5205 NumMCOperands += 1;
5206 break;
5207 case CVT_95_addPostIdxImm8s4Operands:
5208 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5209 Operands[*(p + 1)]->setConstraint("m");
5210 NumMCOperands += 1;
5211 break;
5212 case CVT_95_addRegListOperands:
5213 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5214 Operands[*(p + 1)]->setConstraint("m");
5215 NumMCOperands += 1;
5216 break;
5217 case CVT_95_addThumbMemPCOperands:
5218 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5219 Operands[*(p + 1)]->setConstraint("m");
5220 NumMCOperands += 1;
5221 break;
5222 case CVT_95_addMemThumbRIs4Operands:
5223 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5224 Operands[*(p + 1)]->setConstraint("m");
5225 NumMCOperands += 2;
5226 break;
5227 case CVT_95_addMemThumbRROperands:
5228 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5229 Operands[*(p + 1)]->setConstraint("m");
5230 NumMCOperands += 2;
5231 break;
5232 case CVT_95_addMemThumbSPIOperands:
5233 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5234 Operands[*(p + 1)]->setConstraint("m");
5235 NumMCOperands += 2;
5236 break;
5237 case CVT_95_addConstPoolAsmImmOperands:
5238 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5239 Operands[*(p + 1)]->setConstraint("m");
5240 NumMCOperands += 1;
5241 break;
5242 case CVT_95_addMemImm12OffsetOperands:
5243 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5244 Operands[*(p + 1)]->setConstraint("m");
5245 NumMCOperands += 2;
5246 break;
5247 case CVT_95_addMemImmOffsetOperands:
5248 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5249 Operands[*(p + 1)]->setConstraint("m");
5250 NumMCOperands += 2;
5251 break;
5252 case CVT_95_addMemRegOffsetOperands:
5253 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5254 Operands[*(p + 1)]->setConstraint("m");
5255 NumMCOperands += 3;
5256 break;
5257 case CVT_95_addMemUImm12OffsetOperands:
5258 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5259 Operands[*(p + 1)]->setConstraint("m");
5260 NumMCOperands += 2;
5261 break;
5262 case CVT_95_addT2MemRegOffsetOperands:
5263 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5264 Operands[*(p + 1)]->setConstraint("m");
5265 NumMCOperands += 3;
5266 break;
5267 case CVT_95_addMemPCRelImm12Operands:
5268 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5269 Operands[*(p + 1)]->setConstraint("m");
5270 NumMCOperands += 1;
5271 break;
5272 case CVT_95_addAM2OffsetImmOperands:
5273 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5274 Operands[*(p + 1)]->setConstraint("m");
5275 NumMCOperands += 2;
5276 break;
5277 case CVT_95_addPostIdxRegShiftedOperands:
5278 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5279 Operands[*(p + 1)]->setConstraint("m");
5280 NumMCOperands += 2;
5281 break;
5282 case CVT_95_addMemThumbRIs1Operands:
5283 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5284 Operands[*(p + 1)]->setConstraint("m");
5285 NumMCOperands += 2;
5286 break;
5287 case CVT_95_addMemImm8s4OffsetOperands:
5288 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5289 Operands[*(p + 1)]->setConstraint("m");
5290 NumMCOperands += 2;
5291 break;
5292 case CVT_95_addAddrMode3Operands:
5293 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5294 Operands[*(p + 1)]->setConstraint("m");
5295 NumMCOperands += 3;
5296 break;
5297 case CVT_95_addAM3OffsetOperands:
5298 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5299 Operands[*(p + 1)]->setConstraint("m");
5300 NumMCOperands += 2;
5301 break;
5302 case CVT_95_addMemImm0_95_1020s4OffsetOperands:
5303 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5304 Operands[*(p + 1)]->setConstraint("m");
5305 NumMCOperands += 2;
5306 break;
5307 case CVT_95_addMemThumbRIs2Operands:
5308 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5309 Operands[*(p + 1)]->setConstraint("m");
5310 NumMCOperands += 2;
5311 break;
5312 case CVT_95_addPostIdxRegOperands:
5313 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5314 Operands[*(p + 1)]->setConstraint("m");
5315 NumMCOperands += 2;
5316 break;
5317 case CVT_95_addPostIdxImm8Operands:
5318 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5319 Operands[*(p + 1)]->setConstraint("m");
5320 NumMCOperands += 1;
5321 break;
5322 case CVT_reg0:
5323 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5324 Operands[*(p + 1)]->setConstraint("m");
5325 ++NumMCOperands;
5326 break;
5327 case CVT_regCPSR:
5328 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5329 Operands[*(p + 1)]->setConstraint("m");
5330 ++NumMCOperands;
5331 break;
5332 case CVT_imm_95_14:
5333 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5334 Operands[*(p + 1)]->setConstraint("");
5335 ++NumMCOperands;
5336 break;
5337 case CVT_95_addBankedRegOperands:
5338 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5339 Operands[*(p + 1)]->setConstraint("m");
5340 NumMCOperands += 1;
5341 break;
5342 case CVT_95_addMSRMaskOperands:
5343 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5344 Operands[*(p + 1)]->setConstraint("m");
5345 NumMCOperands += 1;
5346 break;
5347 case CVT_regR8:
5348 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5349 Operands[*(p + 1)]->setConstraint("m");
5350 ++NumMCOperands;
5351 break;
5352 case CVT_regR0:
5353 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5354 Operands[*(p + 1)]->setConstraint("m");
5355 ++NumMCOperands;
5356 break;
5357 case CVT_imm_95_29:
5358 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5359 Operands[*(p + 1)]->setConstraint("");
5360 ++NumMCOperands;
5361 break;
5362 case CVT_imm_95_13:
5363 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5364 Operands[*(p + 1)]->setConstraint("");
5365 ++NumMCOperands;
5366 break;
5367 case CVT_95_addPKHASRImmOperands:
5368 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5369 Operands[*(p + 1)]->setConstraint("m");
5370 NumMCOperands += 1;
5371 break;
5372 case CVT_imm_95_4:
5373 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5374 Operands[*(p + 1)]->setConstraint("");
5375 ++NumMCOperands;
5376 break;
5377 case CVT_95_addImm1_95_32Operands:
5378 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5379 Operands[*(p + 1)]->setConstraint("m");
5380 NumMCOperands += 1;
5381 break;
5382 case CVT_imm_95_5:
5383 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5384 Operands[*(p + 1)]->setConstraint("");
5385 ++NumMCOperands;
5386 break;
5387 case CVT_95_addMveSaturateOperands:
5388 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5389 Operands[*(p + 1)]->setConstraint("m");
5390 NumMCOperands += 1;
5391 break;
5392 case CVT_95_addShifterImmOperands:
5393 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5394 Operands[*(p + 1)]->setConstraint("m");
5395 NumMCOperands += 1;
5396 break;
5397 case CVT_95_addImm1_95_16Operands:
5398 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5399 Operands[*(p + 1)]->setConstraint("m");
5400 NumMCOperands += 1;
5401 break;
5402 case CVT_95_addRotImmOperands:
5403 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5404 Operands[*(p + 1)]->setConstraint("m");
5405 NumMCOperands += 1;
5406 break;
5407 case CVT_95_addMemTBBOperands:
5408 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5409 Operands[*(p + 1)]->setConstraint("m");
5410 NumMCOperands += 2;
5411 break;
5412 case CVT_95_addMemTBHOperands:
5413 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5414 Operands[*(p + 1)]->setConstraint("m");
5415 NumMCOperands += 2;
5416 break;
5417 case CVT_95_addTraceSyncBarrierOptOperands:
5418 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5419 Operands[*(p + 1)]->setConstraint("m");
5420 NumMCOperands += 1;
5421 break;
5422 case CVT_95_addVPTPredNOperands_95_defaultVPTPredOp:
5423 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5424 Operands[*(p + 1)]->setConstraint("m");
5425 NumMCOperands += 3;
5426 break;
5427 case CVT_95_addVPTPredROperands_95_defaultVPTPredOp:
5428 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5429 Operands[*(p + 1)]->setConstraint("m");
5430 NumMCOperands += 4;
5431 break;
5432 case CVT_95_addNEONi16splatNotOperands:
5433 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5434 Operands[*(p + 1)]->setConstraint("m");
5435 NumMCOperands += 1;
5436 break;
5437 case CVT_95_addNEONi32splatNotOperands:
5438 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5439 Operands[*(p + 1)]->setConstraint("m");
5440 NumMCOperands += 1;
5441 break;
5442 case CVT_95_addNEONi16splatOperands:
5443 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5444 Operands[*(p + 1)]->setConstraint("m");
5445 NumMCOperands += 1;
5446 break;
5447 case CVT_95_addNEONi32splatOperands:
5448 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5449 Operands[*(p + 1)]->setConstraint("m");
5450 NumMCOperands += 1;
5451 break;
5452 case CVT_95_addComplexRotationOddOperands:
5453 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5454 Operands[*(p + 1)]->setConstraint("m");
5455 NumMCOperands += 1;
5456 break;
5457 case CVT_95_addComplexRotationEvenOperands:
5458 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5459 Operands[*(p + 1)]->setConstraint("m");
5460 NumMCOperands += 1;
5461 break;
5462 case CVT_95_addVectorIndex64Operands:
5463 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5464 Operands[*(p + 1)]->setConstraint("m");
5465 NumMCOperands += 1;
5466 break;
5467 case CVT_95_addVectorIndex32Operands:
5468 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5469 Operands[*(p + 1)]->setConstraint("m");
5470 NumMCOperands += 1;
5471 break;
5472 case CVT_95_addFBits16Operands:
5473 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5474 Operands[*(p + 1)]->setConstraint("m");
5475 NumMCOperands += 1;
5476 break;
5477 case CVT_95_addFBits32Operands:
5478 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5479 Operands[*(p + 1)]->setConstraint("m");
5480 NumMCOperands += 1;
5481 break;
5482 case CVT_95_addPowerTwoOperands:
5483 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5484 Operands[*(p + 1)]->setConstraint("m");
5485 NumMCOperands += 1;
5486 break;
5487 case CVT_95_addVectorIndex16Operands:
5488 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5489 Operands[*(p + 1)]->setConstraint("m");
5490 NumMCOperands += 1;
5491 break;
5492 case CVT_95_addVectorIndex8Operands:
5493 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5494 Operands[*(p + 1)]->setConstraint("m");
5495 NumMCOperands += 1;
5496 break;
5497 case CVT_95_addVecListOperands:
5498 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5499 Operands[*(p + 1)]->setConstraint("m");
5500 NumMCOperands += 1;
5501 break;
5502 case CVT_95_addDupAlignedMemory16Operands:
5503 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5504 Operands[*(p + 1)]->setConstraint("m");
5505 NumMCOperands += 2;
5506 break;
5507 case CVT_95_addAlignedMemory64or128Operands:
5508 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5509 Operands[*(p + 1)]->setConstraint("m");
5510 NumMCOperands += 2;
5511 break;
5512 case CVT_95_addAlignedMemory64or128or256Operands:
5513 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5514 Operands[*(p + 1)]->setConstraint("m");
5515 NumMCOperands += 2;
5516 break;
5517 case CVT_95_addAlignedMemory64Operands:
5518 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5519 Operands[*(p + 1)]->setConstraint("m");
5520 NumMCOperands += 2;
5521 break;
5522 case CVT_95_addVecListIndexedOperands:
5523 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5524 Operands[*(p + 1)]->setConstraint("m");
5525 NumMCOperands += 2;
5526 break;
5527 case CVT_95_addAlignedMemory16Operands:
5528 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5529 Operands[*(p + 1)]->setConstraint("m");
5530 NumMCOperands += 2;
5531 break;
5532 case CVT_95_addDupAlignedMemory32Operands:
5533 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5534 Operands[*(p + 1)]->setConstraint("m");
5535 NumMCOperands += 2;
5536 break;
5537 case CVT_95_addAlignedMemory32Operands:
5538 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5539 Operands[*(p + 1)]->setConstraint("m");
5540 NumMCOperands += 2;
5541 break;
5542 case CVT_95_addDupAlignedMemoryNoneOperands:
5543 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5544 Operands[*(p + 1)]->setConstraint("m");
5545 NumMCOperands += 2;
5546 break;
5547 case CVT_95_addAlignedMemoryNoneOperands:
5548 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5549 Operands[*(p + 1)]->setConstraint("m");
5550 NumMCOperands += 2;
5551 break;
5552 case CVT_95_addAlignedMemoryOperands:
5553 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5554 Operands[*(p + 1)]->setConstraint("m");
5555 NumMCOperands += 2;
5556 break;
5557 case CVT_95_addDupAlignedMemory64Operands:
5558 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5559 Operands[*(p + 1)]->setConstraint("m");
5560 NumMCOperands += 2;
5561 break;
5562 case CVT_95_addMVEVecListOperands:
5563 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5564 Operands[*(p + 1)]->setConstraint("m");
5565 NumMCOperands += 1;
5566 break;
5567 case CVT_95_addMemNoOffsetT2Operands:
5568 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5569 Operands[*(p + 1)]->setConstraint("m");
5570 NumMCOperands += 1;
5571 break;
5572 case CVT_95_addMemNoOffsetT2NoSpOperands:
5573 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5574 Operands[*(p + 1)]->setConstraint("m");
5575 NumMCOperands += 1;
5576 break;
5577 case CVT_95_addDupAlignedMemory64or128Operands:
5578 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5579 Operands[*(p + 1)]->setConstraint("m");
5580 NumMCOperands += 2;
5581 break;
5582 case CVT_95_addSPRRegListOperands:
5583 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5584 Operands[*(p + 1)]->setConstraint("m");
5585 NumMCOperands += 1;
5586 break;
5587 case CVT_95_addMemImm7s4OffsetOperands:
5588 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5589 Operands[*(p + 1)]->setConstraint("m");
5590 NumMCOperands += 2;
5591 break;
5592 case CVT_95_addAddrMode5FP16Operands:
5593 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5594 Operands[*(p + 1)]->setConstraint("m");
5595 NumMCOperands += 2;
5596 break;
5597 case CVT_95_addImm7s4Operands:
5598 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5599 Operands[*(p + 1)]->setConstraint("m");
5600 NumMCOperands += 1;
5601 break;
5602 case CVT_95_addMemRegRQOffsetOperands:
5603 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5604 Operands[*(p + 1)]->setConstraint("m");
5605 NumMCOperands += 2;
5606 break;
5607 case CVT_95_addMemNoOffsetTOperands:
5608 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5609 Operands[*(p + 1)]->setConstraint("m");
5610 NumMCOperands += 1;
5611 break;
5612 case CVT_95_addImm7Shift0Operands:
5613 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5614 Operands[*(p + 1)]->setConstraint("m");
5615 NumMCOperands += 1;
5616 break;
5617 case CVT_95_addImm7Shift1Operands:
5618 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5619 Operands[*(p + 1)]->setConstraint("m");
5620 NumMCOperands += 1;
5621 break;
5622 case CVT_95_addImm7Shift2Operands:
5623 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5624 Operands[*(p + 1)]->setConstraint("m");
5625 NumMCOperands += 1;
5626 break;
5627 case CVT_95_addNEONi32vmovOperands:
5628 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5629 Operands[*(p + 1)]->setConstraint("m");
5630 NumMCOperands += 1;
5631 break;
5632 case CVT_95_addNEONvmovi8ReplicateOperands:
5633 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5634 Operands[*(p + 1)]->setConstraint("m");
5635 NumMCOperands += 1;
5636 break;
5637 case CVT_95_addNEONvmovi16ReplicateOperands:
5638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5639 Operands[*(p + 1)]->setConstraint("m");
5640 NumMCOperands += 1;
5641 break;
5642 case CVT_95_addNEONi32vmovNegOperands:
5643 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5644 Operands[*(p + 1)]->setConstraint("m");
5645 NumMCOperands += 1;
5646 break;
5647 case CVT_95_addNEONvmovi32ReplicateOperands:
5648 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5649 Operands[*(p + 1)]->setConstraint("m");
5650 NumMCOperands += 1;
5651 break;
5652 case CVT_95_addNEONi64splatOperands:
5653 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5654 Operands[*(p + 1)]->setConstraint("m");
5655 NumMCOperands += 1;
5656 break;
5657 case CVT_95_addNEONi8splatOperands:
5658 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5659 Operands[*(p + 1)]->setConstraint("m");
5660 NumMCOperands += 1;
5661 break;
5662 case CVT_95_addMVEVectorIndexOperands:
5663 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5664 Operands[*(p + 1)]->setConstraint("m");
5665 NumMCOperands += 1;
5666 break;
5667 case CVT_95_addMVEPairVectorIndexOperands:
5668 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5669 Operands[*(p + 1)]->setConstraint("m");
5670 NumMCOperands += 1;
5671 break;
5672 case CVT_95_addNEONinvi8ReplicateOperands:
5673 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5674 Operands[*(p + 1)]->setConstraint("m");
5675 NumMCOperands += 1;
5676 break;
5677 case CVT_95_addFPDRegListWithVPROperands:
5678 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5679 Operands[*(p + 1)]->setConstraint("m");
5680 NumMCOperands += 1;
5681 break;
5682 case CVT_95_addFPSRegListWithVPROperands:
5683 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5684 Operands[*(p + 1)]->setConstraint("m");
5685 NumMCOperands += 1;
5686 break;
5687 case CVT_imm_95_2:
5688 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5689 Operands[*(p + 1)]->setConstraint("");
5690 ++NumMCOperands;
5691 break;
5692 case CVT_imm_95_3:
5693 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5694 Operands[*(p + 1)]->setConstraint("");
5695 ++NumMCOperands;
5696 break;
5697 }
5698 }
5699}
5700
5701namespace {
5702
5703/// MatchClassKind - The kinds of classes which participate in
5704/// instruction matching.
5705enum MatchClassKind {
5706 InvalidMatchClass = 0,
5707 OptionalMatchClass = 1,
5708 MCK__DOT_d, // '.d'
5709 MCK__DOT_f, // '.f'
5710 MCK__DOT_s16, // '.s16'
5711 MCK__DOT_s32, // '.s32'
5712 MCK__DOT_s64, // '.s64'
5713 MCK__DOT_s8, // '.s8'
5714 MCK__DOT_u16, // '.u16'
5715 MCK__DOT_u32, // '.u32'
5716 MCK__DOT_u64, // '.u64'
5717 MCK__DOT_u8, // '.u8'
5718 MCK__DOT_f32, // '.f32'
5719 MCK__DOT_f64, // '.f64'
5720 MCK__DOT_i16, // '.i16'
5721 MCK__DOT_i32, // '.i32'
5722 MCK__DOT_i64, // '.i64'
5723 MCK__DOT_i8, // '.i8'
5724 MCK__DOT_p16, // '.p16'
5725 MCK__DOT_p8, // '.p8'
5726 MCK__EXCLAIM_, // '!'
5727 MCK__HASH_0, // '#0'
5728 MCK__HASH_16, // '#16'
5729 MCK__HASH_8, // '#8'
5730 MCK__DOT_16, // '.16'
5731 MCK__DOT_32, // '.32'
5732 MCK__DOT_64, // '.64'
5733 MCK__DOT_8, // '.8'
5734 MCK__DOT_bf16, // '.bf16'
5735 MCK__DOT_f16, // '.f16'
5736 MCK__DOT_p64, // '.p64'
5737 MCK__DOT_w, // '.w'
5738 MCK__91_, // '['
5739 MCK__93_, // ']'
5740 MCK__94_, // '^'
5741 MCK__123_, // '{'
5742 MCK__125_, // '}'
5743 MCK_LAST_TOKEN = MCK__125_,
5744 MCK_Reg107, // derived register class
5745 MCK_Reg91, // derived register class
5746 MCK_APSR, // register class 'APSR'
5747 MCK_APSR_NZCV, // register class 'APSR_NZCV'
5748 MCK_CCR, // register class 'CCR,CPSR'
5749 MCK_FPCXTRegs, // register class 'FPCXTRegs,FPCXTNS'
5750 MCK_FPCXTS, // register class 'FPCXTS'
5751 MCK_FPEXC, // register class 'FPEXC'
5752 MCK_FPINST, // register class 'FPINST'
5753 MCK_FPINST2, // register class 'FPINST2'
5754 MCK_FPSCR, // register class 'FPSCR'
5755 MCK_FPSCR_NZCVQC, // register class 'FPSCR_NZCVQC'
5756 MCK_FPSID, // register class 'FPSID'
5757 MCK_GPRlr, // register class 'GPRlr,LR'
5758 MCK_GPRsp, // register class 'GPRsp,SP'
5759 MCK_MVFR0, // register class 'MVFR0'
5760 MCK_MVFR1, // register class 'MVFR1'
5761 MCK_MVFR2, // register class 'MVFR2'
5762 MCK_P0, // register class 'P0'
5763 MCK_PC, // register class 'PC'
5764 MCK_R12, // register class 'R12'
5765 MCK_SPSR, // register class 'SPSR'
5766 MCK_VCCR, // register class 'VCCR,VPR'
5767 MCK_cl_FPSCR_NZCV, // register class 'cl_FPSCR_NZCV'
5768 MCK_Reg132, // derived register class
5769 MCK_Reg105, // derived register class
5770 MCK_Reg100, // derived register class
5771 MCK_Reg92, // derived register class
5772 MCK_Reg35, // derived register class
5773 MCK_Reg33, // derived register class
5774 MCK_Reg22, // derived register class
5775 MCK_Reg17, // derived register class
5776 MCK_Reg133, // derived register class
5777 MCK_Reg120, // derived register class
5778 MCK_Reg115, // derived register class
5779 MCK_Reg106, // derived register class
5780 MCK_Reg104, // derived register class
5781 MCK_Reg93, // derived register class
5782 MCK_Reg77, // derived register class
5783 MCK_Reg21, // derived register class
5784 MCK_Reg134, // derived register class
5785 MCK_Reg125, // derived register class
5786 MCK_Reg121, // derived register class
5787 MCK_Reg116, // derived register class
5788 MCK_Reg101, // derived register class
5789 MCK_Reg94, // derived register class
5790 MCK_Reg78, // derived register class
5791 MCK_Reg34, // derived register class
5792 MCK_Reg25, // derived register class
5793 MCK_Reg23, // derived register class
5794 MCK_Reg18, // derived register class
5795 MCK_QPR_8, // register class 'QPR_8'
5796 MCK_tcGPRnotr12, // register class 'tcGPRnotr12'
5797 MCK_Reg89, // derived register class
5798 MCK_Reg32, // derived register class
5799 MCK_Reg30, // derived register class
5800 MCK_MQQQQPR, // register class 'MQQQQPR'
5801 MCK_tcGPR, // register class 'tcGPR'
5802 MCK_Reg135, // derived register class
5803 MCK_Reg126, // derived register class
5804 MCK_Reg108, // derived register class
5805 MCK_Reg96, // derived register class
5806 MCK_Reg90, // derived register class
5807 MCK_Reg72, // derived register class
5808 MCK_Reg31, // derived register class
5809 MCK_Reg28, // derived register class
5810 MCK_Reg19, // derived register class
5811 MCK_GPRPairnosp, // register class 'GPRPairnosp'
5812 MCK_tGPROdd, // register class 'tGPROdd'
5813 MCK_Reg136, // derived register class
5814 MCK_Reg122, // derived register class
5815 MCK_Reg117, // derived register class
5816 MCK_Reg109, // derived register class
5817 MCK_Reg97, // derived register class
5818 MCK_Reg87, // derived register class
5819 MCK_Reg52, // derived register class
5820 MCK_Reg29, // derived register class
5821 MCK_Reg26, // derived register class
5822 MCK_GPRPair, // register class 'GPRPair'
5823 MCK_MQQPR, // register class 'MQQPR'
5824 MCK_Reg137, // derived register class
5825 MCK_Reg127, // derived register class
5826 MCK_Reg123, // derived register class
5827 MCK_Reg118, // derived register class
5828 MCK_Reg110, // derived register class
5829 MCK_Reg98, // derived register class
5830 MCK_Reg88, // derived register class
5831 MCK_Reg80, // derived register class
5832 MCK_Reg73, // derived register class
5833 MCK_Reg53, // derived register class
5834 MCK_DPR_8, // register class 'DPR_8'
5835 MCK_MQPR, // register class 'MQPR,QPR_VFP2'
5836 MCK_hGPR, // register class 'hGPR'
5837 MCK_tGPR, // register class 'tGPR'
5838 MCK_tGPREven, // register class 'tGPREven'
5839 MCK_tGPRwithpc, // register class 'tGPRwithpc'
5840 MCK_Reg128, // derived register class
5841 MCK_Reg2, // derived register class
5842 MCK_Reg85, // derived register class
5843 MCK_Reg14, // derived register class
5844 MCK_Reg12, // derived register class
5845 MCK_QQQQPR, // register class 'QQQQPR'
5846 MCK_Reg138, // derived register class
5847 MCK_Reg129, // derived register class
5848 MCK_Reg111, // derived register class
5849 MCK_Reg86, // derived register class
5850 MCK_Reg74, // derived register class
5851 MCK_GPRnoip, // register class 'GPRnoip'
5852 MCK_rGPR, // register class 'rGPR'
5853 MCK_Reg124, // derived register class
5854 MCK_Reg119, // derived register class
5855 MCK_Reg112, // derived register class
5856 MCK_Reg83, // derived register class
5857 MCK_Reg50, // derived register class
5858 MCK_GPRnopc, // register class 'GPRnopc'
5859 MCK_GPRnosp, // register class 'GPRnosp'
5860 MCK_GPRwithAPSR_NZCVnosp, // register class 'GPRwithAPSR_NZCVnosp'
5861 MCK_GPRwithAPSRnosp, // register class 'GPRwithAPSRnosp'
5862 MCK_GPRwithZRnosp, // register class 'GPRwithZRnosp'
5863 MCK_QQPR, // register class 'QQPR'
5864 MCK_Reg130, // derived register class
5865 MCK_Reg113, // derived register class
5866 MCK_Reg84, // derived register class
5867 MCK_Reg75, // derived register class
5868 MCK_Reg51, // derived register class
5869 MCK_DPR_VFP2, // register class 'DPR_VFP2'
5870 MCK_GPR, // register class 'GPR'
5871 MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
5872 MCK_GPRwithZR, // register class 'GPRwithZR'
5873 MCK_QPR, // register class 'QPR'
5874 MCK_SPR_8, // register class 'SPR_8'
5875 MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
5876 MCK_DQuad, // register class 'DQuad'
5877 MCK_DPairSpc, // register class 'DPairSpc'
5878 MCK_DTriple, // register class 'DTriple'
5879 MCK_DPair, // register class 'DPair'
5880 MCK_DPR, // register class 'DPR'
5881 MCK_HPR, // register class 'HPR,SPR'
5882 MCK_FPWithVPR, // register class 'FPWithVPR'
5883 MCK_LAST_REGISTER = MCK_FPWithVPR,
5884 MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
5885 MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
5886 MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
5887 MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
5888 MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
5889 MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
5890 MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
5891 MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
5892 MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
5893 MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
5894 MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
5895 MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
5896 MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
5897 MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
5898 MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
5899 MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
5900 MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
5901 MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
5902 MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
5903 MCK_BankedReg, // user defined class 'BankedRegOperand'
5904 MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
5905 MCK_CCOut, // user defined class 'CCOutOperand'
5906 MCK_CondCode, // user defined class 'CondCodeOperand'
5907 MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
5908 MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
5909 MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
5910 MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
5911 MCK_FPDRegListWithVPR, // user defined class 'FPDRegListWithVPRAsmOperand'
5912 MCK_FPImm, // user defined class 'FPImmOperand'
5913 MCK_FPSRegListWithVPR, // user defined class 'FPSRegListWithVPRAsmOperand'
5914 MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
5915 MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
5916 MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
5917 MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
5918 MCK_Imm0_255Expr, // user defined class 'Imm0_255ExprAsmOperand'
5919 MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
5920 MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
5921 MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
5922 MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
5923 MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
5924 MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
5925 MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
5926 MCK_Imm16, // user defined class 'Imm16AsmOperand'
5927 MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
5928 MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
5929 MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
5930 MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
5931 MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
5932 MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
5933 MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
5934 MCK_Imm32, // user defined class 'Imm32AsmOperand'
5935 MCK_Imm8, // user defined class 'Imm8AsmOperand'
5936 MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
5937 MCK_Imm, // user defined class 'ImmAsmOperand'
5938 MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
5939 MCK_MSRMask, // user defined class 'MSRMaskOperand'
5940 MCK_MVEShiftImm1_15, // user defined class 'MVEShiftImm1_15AsmOperand'
5941 MCK_MVEShiftImm1_7, // user defined class 'MVEShiftImm1_7AsmOperand'
5942 MCK_VIDUP_imm, // user defined class 'MVE_VIDUP_imm_asmoperand'
5943 MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
5944 MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
5945 MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
5946 MCK_MemImm7Shift0Offset, // user defined class 'MemImm7Shift0OffsetAsmOperand'
5947 MCK_MemImm7Shift0OffsetWB, // user defined class 'MemImm7Shift0OffsetWBAsmOperand'
5948 MCK_MemImm7Shift1Offset, // user defined class 'MemImm7Shift1OffsetAsmOperand'
5949 MCK_MemImm7Shift1OffsetWB, // user defined class 'MemImm7Shift1OffsetWBAsmOperand'
5950 MCK_MemImm7Shift2Offset, // user defined class 'MemImm7Shift2OffsetAsmOperand'
5951 MCK_MemImm7Shift2OffsetWB, // user defined class 'MemImm7Shift2OffsetWBAsmOperand'
5952 MCK_MemImm7s4Offset, // user defined class 'MemImm7s4OffsetAsmOperand'
5953 MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
5954 MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
5955 MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
5956 MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
5957 MCK_MemNoOffsetT2, // user defined class 'MemNoOffsetT2AsmOperand'
5958 MCK_MemNoOffsetT2NoSp, // user defined class 'MemNoOffsetT2NoSpAsmOperand'
5959 MCK_MemNoOffsetT, // user defined class 'MemNoOffsetTAsmOperand'
5960 MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
5961 MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
5962 MCK_MemRegQS2Offset, // user defined class 'MemRegQS2OffsetAsmOperand'
5963 MCK_MemRegQS3Offset, // user defined class 'MemRegQS3OffsetAsmOperand'
5964 MCK_MemRegRQS0Offset, // user defined class 'MemRegRQS0OffsetAsmOperand'
5965 MCK_MemRegRQS1Offset, // user defined class 'MemRegRQS1OffsetAsmOperand'
5966 MCK_MemRegRQS2Offset, // user defined class 'MemRegRQS2OffsetAsmOperand'
5967 MCK_MemRegRQS3Offset, // user defined class 'MemRegRQS3OffsetAsmOperand'
5968 MCK_ModImm, // user defined class 'ModImmAsmOperand'
5969 MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
5970 MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
5971 MCK_MveSaturate, // user defined class 'MveSaturateOperand'
5972 MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
5973 MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
5974 MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
5975 MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
5976 MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
5977 MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
5978 MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
5979 MCK_RegList, // user defined class 'RegListAsmOperand'
5980 MCK_RegListWithAPSR, // user defined class 'RegListWithAPSRAsmOperand'
5981 MCK_RotImm, // user defined class 'RotImmAsmOperand'
5982 MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
5983 MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
5984 MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
5985 MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
5986 MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
5987 MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
5988 MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
5989 MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
5990 MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
5991 MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
5992 MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand'
5993 MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
5994 MCK_VPTPredN, // user defined class 'VPTPredNOperand'
5995 MCK_VPTPredR, // user defined class 'VPTPredROperand'
5996 MCK_VecListTwoMQ, // user defined class 'VecList2QAsmOperand'
5997 MCK_VecListFourMQ, // user defined class 'VecList4QAsmOperand'
5998 MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
5999 MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
6000 MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
6001 MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
6002 MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
6003 MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
6004 MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
6005 MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
6006 MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
6007 MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
6008 MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
6009 MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
6010 MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
6011 MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
6012 MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
6013 MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
6014 MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
6015 MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
6016 MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
6017 MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
6018 MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
6019 MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
6020 MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
6021 MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
6022 MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
6023 MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
6024 MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
6025 MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
6026 MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
6027 MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
6028 MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
6029 MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
6030 MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
6031 MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
6032 MCK_VectorIndex64, // user defined class 'VectorIndex64Operand'
6033 MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
6034 MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
6035 MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
6036 MCK_MVEVectorIndex4, // user defined class 'anonymous_10871'
6037 MCK_MVEVectorIndex8, // user defined class 'anonymous_10873'
6038 MCK_MVEVectorIndex16, // user defined class 'anonymous_10875'
6039 MCK_MVEVcvtImm32, // user defined class 'anonymous_11635'
6040 MCK_MVEVcvtImm16, // user defined class 'anonymous_11637'
6041 MCK_TMemImm7Shift2Offset, // user defined class 'anonymous_11882'
6042 MCK_TMemImm7Shift0Offset, // user defined class 'anonymous_12629'
6043 MCK_TMemImm7Shift1Offset, // user defined class 'anonymous_12632'
6044 MCK_Imm3b, // user defined class 'anonymous_13164'
6045 MCK_Imm4b, // user defined class 'anonymous_13165'
6046 MCK_Imm6b, // user defined class 'anonymous_13166'
6047 MCK_Imm7b, // user defined class 'anonymous_13167'
6048 MCK_Imm9b, // user defined class 'anonymous_13168'
6049 MCK_Imm11b, // user defined class 'anonymous_13169'
6050 MCK_Imm12b, // user defined class 'anonymous_13170'
6051 MCK_Imm13b, // user defined class 'anonymous_13171'
6052 MCK_MVEPairVectorIndex0, // user defined class 'anonymous_8202'
6053 MCK_MVEPairVectorIndex2, // user defined class 'anonymous_8203'
6054 MCK_ComplexRotationEven, // user defined class 'anonymous_8212'
6055 MCK_ComplexRotationOdd, // user defined class 'anonymous_8213'
6056 MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_9557'
6057 MCK_NEONi16invi8Replicate, // user defined class 'anonymous_9559'
6058 MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_9562'
6059 MCK_NEONi32invi8Replicate, // user defined class 'anonymous_9564'
6060 MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_9571'
6061 MCK_NEONi64invi8Replicate, // user defined class 'anonymous_9573'
6062 MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_9584'
6063 MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_9587'
6064 MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_9594'
6065 MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
6066 MCK_FBits16, // user defined class 'fbits16_asm_operand'
6067 MCK_FBits32, // user defined class 'fbits32_asm_operand'
6068 MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
6069 MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
6070 MCK_ITMask, // user defined class 'it_mask_asmoperand'
6071 MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
6072 MCK_LELabel, // user defined class 'lelabel_u11_asmoperand'
6073 MCK_MVELongShift, // user defined class 'mve_shift_imm'
6074 MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
6075 MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
6076 MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
6077 MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
6078 MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
6079 MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
6080 MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
6081 MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
6082 MCK_CondCodeNoAL, // user defined class 'pred_noal_asmoperand'
6083 MCK_CondCodeNoALInv, // user defined class 'pred_noal_inv_asmoperand'
6084 MCK_CondCodeRestrictedFP, // user defined class 'pred_restricted_fp_asmoperand'
6085 MCK_CondCodeRestrictedI, // user defined class 'pred_restricted_i_asmoperand'
6086 MCK_CondCodeRestrictedS, // user defined class 'pred_restricted_s_asmoperand'
6087 MCK_CondCodeRestrictedU, // user defined class 'pred_restricted_u_asmoperand'
6088 MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
6089 MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
6090 MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
6091 MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
6092 MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
6093 MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
6094 MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
6095 MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
6096 MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
6097 MCK_Imm7s4, // user defined class 't2am_imm7s4_offset_asmoperand'
6098 MCK_Imm7Shift0, // user defined class 't2am_imm7shift0OffsetAsmOperand'
6099 MCK_Imm7Shift1, // user defined class 't2am_imm7shift1OffsetAsmOperand'
6100 MCK_Imm7Shift2, // user defined class 't2am_imm7shift2OffsetAsmOperand'
6101 MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
6102 MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
6103 MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
6104 MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
6105 MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
6106 MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
6107 MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
6108 MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
6109 MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
6110 MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
6111 MCK_WLSLabel, // user defined class 'wlslabel_u11_asmoperand'
6112 NumMatchClassKinds
6113};
6114
6115} // end anonymous namespace
6116
6117static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) {
6118 switch (MatchResult) {
6119 case ARMAsmParser::Match_GPRsp:
6120 return "operand must be a register sp";
6121 case ARMAsmParser::Match_QPR_8:
6122 return "operand must be a register in range [q0, q3]";
6123 case ARMAsmParser::Match_tGPROdd:
6124 return "operand must be an odd-numbered register in range [r1,r11]";
6125 case ARMAsmParser::Match_DPR_8:
6126 return "operand must be a register in range [d0, d7]";
6127 case ARMAsmParser::Match_QPR_VFP2:
6128 return "operand must be a register in range [q0, q7]";
6129 case ARMAsmParser::Match_hGPR:
6130 return "operand must be a register in range [r8, r15]";
6131 case ARMAsmParser::Match_tGPR:
6132 return "operand must be a register in range [r0, r7]";
6133 case ARMAsmParser::Match_tGPREven:
6134 return "operand must be an even-numbered register";
6135 case ARMAsmParser::Match_GPRnoip:
6136 return "operand must be a register in range [r0, r14]";
6137 case ARMAsmParser::Match_GPRnopc:
6138 return "operand must be a register in range [r0, r14]";
6139 case ARMAsmParser::Match_GPRnosp:
6140 return "operand must be a register in range [r0, r12] or LR or PC";
6141 case ARMAsmParser::Match_GPRwithAPSR_NZCVnosp:
6142 return "operand must be a register in the range [r0, r12], r14 or apsr_nzcv";
6143 case ARMAsmParser::Match_GPRwithZRnosp:
6144 return "operand must be a register in range [r0, r12] or r14 or zr";
6145 case ARMAsmParser::Match_DPR_VFP2:
6146 return "operand must be a register in range [d0, d15]";
6147 case ARMAsmParser::Match_GPR:
6148 return "operand must be a register in range [r0, r15]";
6149 case ARMAsmParser::Match_GPRwithAPSR:
6150 return "operand must be a register in range [r0, r14] or apsr_nzcv";
6151 case ARMAsmParser::Match_GPRwithZR:
6152 return "operand must be a register in range [r0, r14] or zr";
6153 case ARMAsmParser::Match_QPR:
6154 return "operand must be a register in range [q0, q15]";
6155 case ARMAsmParser::Match_SPR_8:
6156 return "operand must be a register in range [s0, s15]";
6157 case ARMAsmParser::Match_SPR:
6158 return "operand must be a register in range [s0, s31]";
6159 case ARMAsmParser::Match_AlignedMemory16:
6160 return "alignment must be 16 or omitted";
6161 case ARMAsmParser::Match_AlignedMemory32:
6162 return "alignment must be 32 or omitted";
6163 case ARMAsmParser::Match_AlignedMemory64:
6164 return "alignment must be 64 or omitted";
6165 case ARMAsmParser::Match_AlignedMemory64or128:
6166 return "alignment must be 64, 128 or omitted";
6167 case ARMAsmParser::Match_AlignedMemory64or128or256:
6168 return "alignment must be 64, 128, 256 or omitted";
6169 case ARMAsmParser::Match_AlignedMemoryNone:
6170 return "alignment must be omitted";
6171 case ARMAsmParser::Match_DupAlignedMemory16:
6172 return "alignment must be 16 or omitted";
6173 case ARMAsmParser::Match_DupAlignedMemory32:
6174 return "alignment must be 32 or omitted";
6175 case ARMAsmParser::Match_DupAlignedMemory64:
6176 return "alignment must be 64 or omitted";
6177 case ARMAsmParser::Match_DupAlignedMemory64or128:
6178 return "alignment must be 64, 128 or omitted";
6179 case ARMAsmParser::Match_DupAlignedMemoryNone:
6180 return "alignment must be omitted";
6181 case ARMAsmParser::Match_Imm0_15:
6182 return "operand must be an immediate in the range [0,15]";
6183 case ARMAsmParser::Match_Imm0_1:
6184 return "operand must be an immediate in the range [0,1]";
6185 case ARMAsmParser::Match_Imm0_239:
6186 return "operand must be an immediate in the range [0,239]";
6187 case ARMAsmParser::Match_Imm0_255:
6188 return "operand must be an immediate in the range [0,255]";
6189 case ARMAsmParser::Match_Imm0_255Expr:
6190 return "operand must be an immediate in the range [0,255] or a relocatable expression";
6191 case ARMAsmParser::Match_Imm0_31:
6192 return "operand must be an immediate in the range [0,31]";
6193 case ARMAsmParser::Match_Imm0_32:
6194 return "operand must be an immediate in the range [0,32]";
6195 case ARMAsmParser::Match_Imm0_3:
6196 return "operand must be an immediate in the range [0,3]";
6197 case ARMAsmParser::Match_Imm0_63:
6198 return "operand must be an immediate in the range [0,63]";
6199 case ARMAsmParser::Match_Imm0_65535:
6200 return "operand must be an immediate in the range [0,65535]";
6201 case ARMAsmParser::Match_Imm0_65535Expr:
6202 return "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
6203 case ARMAsmParser::Match_Imm0_7:
6204 return "operand must be an immediate in the range [0,7]";
6205 case ARMAsmParser::Match_Imm16:
6206 return "operand must be an immediate in the range [16,16]";
6207 case ARMAsmParser::Match_Imm1_15:
6208 return "operand must be an immediate in the range [1,15]";
6209 case ARMAsmParser::Match_ImmRange1_16:
6210 return "operand must be an immediate in the range [1,16]";
6211 case ARMAsmParser::Match_Imm1_31:
6212 return "operand must be an immediate in the range [1,31]";
6213 case ARMAsmParser::Match_ImmRange1_32:
6214 return "operand must be an immediate in the range [1,32]";
6215 case ARMAsmParser::Match_Imm1_7:
6216 return "operand must be an immediate in the range [1,7]";
6217 case ARMAsmParser::Match_Imm24bit:
6218 return "operand must be an immediate in the range [0,0xffffff]";
6219 case ARMAsmParser::Match_Imm256_65535Expr:
6220 return "operand must be an immediate in the range [256,65535]";
6221 case ARMAsmParser::Match_Imm32:
6222 return "operand must be an immediate in the range [32,32]";
6223 case ARMAsmParser::Match_Imm8:
6224 return "operand must be an immediate in the range [8,8]";
6225 case ARMAsmParser::Match_Imm8_255:
6226 return "operand must be an immediate in the range [8,255]";
6227 case ARMAsmParser::Match_MVEShiftImm1_15:
6228 return "operand must be an immediate in the range [1,16]";
6229 case ARMAsmParser::Match_MVEShiftImm1_7:
6230 return "operand must be an immediate in the range [1,8]";
6231 case ARMAsmParser::Match_VIDUP_imm:
6232 return "vector increment immediate must be 1, 2, 4 or 8";
6233 case ARMAsmParser::Match_MveSaturate:
6234 return "saturate operand must be 48 or 64";
6235 case ARMAsmParser::Match_PKHLSLImm:
6236 return "operand must be an immediate in the range [0,31]";
6237 case ARMAsmParser::Match_SPRRegList:
6238 return "operand must be a list of registers in range [s0, s31]";
6239 case ARMAsmParser::Match_SetEndImm:
6240 return "operand must be an immediate in the range [0,1]";
6241 case ARMAsmParser::Match_ImmThumbSR:
6242 return "operand must be an immediate in the range [1,32]";
6243 case ARMAsmParser::Match_VecListTwoMQ:
6244 return "operand must be a list of two consecutive q-registers in range [q0,q7]";
6245 case ARMAsmParser::Match_VecListFourMQ:
6246 return "operand must be a list of four consecutive q-registers in range [q0,q7]";
6247 case ARMAsmParser::Match_MVEVcvtImm32:
6248 return "MVE fixed-point immediate operand must be between 1 and 32";
6249 case ARMAsmParser::Match_MVEVcvtImm16:
6250 return "MVE fixed-point immediate operand must be between 1 and 16";
6251 case ARMAsmParser::Match_Imm3b:
6252 return "operand must be an immediate in the range [0,7]";
6253 case ARMAsmParser::Match_Imm4b:
6254 return "operand must be an immediate in the range [0,15]";
6255 case ARMAsmParser::Match_Imm6b:
6256 return "operand must be an immediate in the range [0,63]";
6257 case ARMAsmParser::Match_Imm7b:
6258 return "operand must be an immediate in the range [0,127]";
6259 case ARMAsmParser::Match_Imm9b:
6260 return "operand must be an immediate in the range [0,511]";
6261 case ARMAsmParser::Match_Imm11b:
6262 return "operand must be an immediate in the range [0,2047]";
6263 case ARMAsmParser::Match_Imm12b:
6264 return "operand must be an immediate in the range [0,4095]";
6265 case ARMAsmParser::Match_Imm13b:
6266 return "operand must be an immediate in the range [0,8191]";
6267 case ARMAsmParser::Match_ComplexRotationEven:
6268 return "complex rotation must be 0, 90, 180 or 270";
6269 case ARMAsmParser::Match_ComplexRotationOdd:
6270 return "complex rotation must be 90 or 270";
6271 case ARMAsmParser::Match_Imm0_4095:
6272 return "operand must be an immediate in the range [0,4095]";
6273 case ARMAsmParser::Match_LELabel:
6274 return "loop start is out of range or not a negative multiple of 2";
6275 case ARMAsmParser::Match_MVELongShift:
6276 return "operand must be an immediate in the range [1,32]";
6277 case ARMAsmParser::Match_CondCodeRestrictedFP:
6278 return "condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE";
6279 case ARMAsmParser::Match_CondCodeRestrictedI:
6280 return "condition code for sign-independent integer comparison must be EQ or NE";
6281 case ARMAsmParser::Match_CondCodeRestrictedS:
6282 return "condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE";
6283 case ARMAsmParser::Match_CondCodeRestrictedU:
6284 return "condition code for unsigned integer comparison must be EQ, NE, HS or HI";
6285 case ARMAsmParser::Match_ShrImm16:
6286 return "operand must be an immediate in the range [1,16]";
6287 case ARMAsmParser::Match_ShrImm32:
6288 return "operand must be an immediate in the range [1,32]";
6289 case ARMAsmParser::Match_ShrImm64:
6290 return "operand must be an immediate in the range [1,64]";
6291 case ARMAsmParser::Match_ShrImm8:
6292 return "operand must be an immediate in the range [1,8]";
6293 case ARMAsmParser::Match_WLSLabel:
6294 return "loop end is out of range or not a positive multiple of 2";
6295 default:
6296 return nullptr;
6297 }
6298}
6299
6300static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
6301 switch (RegisterClass) {
6302 case MCK_GPRsp:
6303 return ARMAsmParser::Match_GPRsp;
6304 case MCK_QPR_8:
6305 return ARMAsmParser::Match_QPR_8;
6306 case MCK_tGPROdd:
6307 return ARMAsmParser::Match_tGPROdd;
6308 case MCK_DPR_8:
6309 return ARMAsmParser::Match_DPR_8;
6310 case MCK_MQPR:
6311 return ARMAsmParser::Match_QPR_VFP2;
6312 case MCK_hGPR:
6313 return ARMAsmParser::Match_hGPR;
6314 case MCK_tGPR:
6315 return ARMAsmParser::Match_tGPR;
6316 case MCK_tGPREven:
6317 return ARMAsmParser::Match_tGPREven;
6318 case MCK_GPRnoip:
6319 return ARMAsmParser::Match_GPRnoip;
6320 case MCK_rGPR:
6321 return ARMAsmParser::Match_rGPR;
6322 case MCK_GPRnopc:
6323 return ARMAsmParser::Match_GPRnopc;
6324 case MCK_GPRnosp:
6325 return ARMAsmParser::Match_GPRnosp;
6326 case MCK_GPRwithAPSR_NZCVnosp:
6327 return ARMAsmParser::Match_GPRwithAPSR_NZCVnosp;
6328 case MCK_GPRwithZRnosp:
6329 return ARMAsmParser::Match_GPRwithZRnosp;
6330 case MCK_DPR_VFP2:
6331 return ARMAsmParser::Match_DPR_VFP2;
6332 case MCK_GPR:
6333 return ARMAsmParser::Match_GPR;
6334 case MCK_GPRwithAPSR:
6335 return ARMAsmParser::Match_GPRwithAPSR;
6336 case MCK_GPRwithZR:
6337 return ARMAsmParser::Match_GPRwithZR;
6338 case MCK_QPR:
6339 return ARMAsmParser::Match_QPR;
6340 case MCK_SPR_8:
6341 return ARMAsmParser::Match_SPR_8;
6342 case MCK_DPR:
6343 return ARMAsmParser::Match_DPR;
6344 case MCK_HPR:
6345 return ARMAsmParser::Match_SPR;
6346 default:
6347 return MCTargetAsmParser::Match_InvalidOperand;
6348 }
6349}
6350
6351static MatchClassKind matchTokenString(StringRef Name) {
6352 switch (Name.size()) {
6353 default: break;
6354 case 1: // 6 strings to match.
6355 switch (Name[0]) {
6356 default: break;
6357 case '!': // 1 string to match.
6358 return MCK__EXCLAIM_; // "!"
6359 case '[': // 1 string to match.
6360 return MCK__91_; // "["
6361 case ']': // 1 string to match.
6362 return MCK__93_; // "]"
6363 case '^': // 1 string to match.
6364 return MCK__94_; // "^"
6365 case '{': // 1 string to match.
6366 return MCK__123_; // "{"
6367 case '}': // 1 string to match.
6368 return MCK__125_; // "}"
6369 }
6370 break;
6371 case 2: // 6 strings to match.
6372 switch (Name[0]) {
6373 default: break;
6374 case '#': // 2 strings to match.
6375 switch (Name[1]) {
6376 default: break;
6377 case '0': // 1 string to match.
6378 return MCK__HASH_0; // "#0"
6379 case '8': // 1 string to match.
6380 return MCK__HASH_8; // "#8"
6381 }
6382 break;
6383 case '.': // 4 strings to match.
6384 switch (Name[1]) {
6385 default: break;
6386 case '8': // 1 string to match.
6387 return MCK__DOT_8; // ".8"
6388 case 'd': // 1 string to match.
6389 return MCK__DOT_d; // ".d"
6390 case 'f': // 1 string to match.
6391 return MCK__DOT_f; // ".f"
6392 case 'w': // 1 string to match.
6393 return MCK__DOT_w; // ".w"
6394 }
6395 break;
6396 }
6397 break;
6398 case 3: // 8 strings to match.
6399 switch (Name[0]) {
6400 default: break;
6401 case '#': // 1 string to match.
6402 if (memcmp(Name.data()+1, "16", 2) != 0)
6403 break;
6404 return MCK__HASH_16; // "#16"
6405 case '.': // 7 strings to match.
6406 switch (Name[1]) {
6407 default: break;
6408 case '1': // 1 string to match.
6409 if (Name[2] != '6')
6410 break;
6411 return MCK__DOT_16; // ".16"
6412 case '3': // 1 string to match.
6413 if (Name[2] != '2')
6414 break;
6415 return MCK__DOT_32; // ".32"
6416 case '6': // 1 string to match.
6417 if (Name[2] != '4')
6418 break;
6419 return MCK__DOT_64; // ".64"
6420 case 'i': // 1 string to match.
6421 if (Name[2] != '8')
6422 break;
6423 return MCK__DOT_i8; // ".i8"
6424 case 'p': // 1 string to match.
6425 if (Name[2] != '8')
6426 break;
6427 return MCK__DOT_p8; // ".p8"
6428 case 's': // 1 string to match.
6429 if (Name[2] != '8')
6430 break;
6431 return MCK__DOT_s8; // ".s8"
6432 case 'u': // 1 string to match.
6433 if (Name[2] != '8')
6434 break;
6435 return MCK__DOT_u8; // ".u8"
6436 }
6437 break;
6438 }
6439 break;
6440 case 4: // 14 strings to match.
6441 if (Name[0] != '.')
6442 break;
6443 switch (Name[1]) {
6444 default: break;
6445 case 'f': // 3 strings to match.
6446 switch (Name[2]) {
6447 default: break;
6448 case '1': // 1 string to match.
6449 if (Name[3] != '6')
6450 break;
6451 return MCK__DOT_f16; // ".f16"
6452 case '3': // 1 string to match.
6453 if (Name[3] != '2')
6454 break;
6455 return MCK__DOT_f32; // ".f32"
6456 case '6': // 1 string to match.
6457 if (Name[3] != '4')
6458 break;
6459 return MCK__DOT_f64; // ".f64"
6460 }
6461 break;
6462 case 'i': // 3 strings to match.
6463 switch (Name[2]) {
6464 default: break;
6465 case '1': // 1 string to match.
6466 if (Name[3] != '6')
6467 break;
6468 return MCK__DOT_i16; // ".i16"
6469 case '3': // 1 string to match.
6470 if (Name[3] != '2')
6471 break;
6472 return MCK__DOT_i32; // ".i32"
6473 case '6': // 1 string to match.
6474 if (Name[3] != '4')
6475 break;
6476 return MCK__DOT_i64; // ".i64"
6477 }
6478 break;
6479 case 'p': // 2 strings to match.
6480 switch (Name[2]) {
6481 default: break;
6482 case '1': // 1 string to match.
6483 if (Name[3] != '6')
6484 break;
6485 return MCK__DOT_p16; // ".p16"
6486 case '6': // 1 string to match.
6487 if (Name[3] != '4')
6488 break;
6489 return MCK__DOT_p64; // ".p64"
6490 }
6491 break;
6492 case 's': // 3 strings to match.
6493 switch (Name[2]) {
6494 default: break;
6495 case '1': // 1 string to match.
6496 if (Name[3] != '6')
6497 break;
6498 return MCK__DOT_s16; // ".s16"
6499 case '3': // 1 string to match.
6500 if (Name[3] != '2')
6501 break;
6502 return MCK__DOT_s32; // ".s32"
6503 case '6': // 1 string to match.
6504 if (Name[3] != '4')
6505 break;
6506 return MCK__DOT_s64; // ".s64"
6507 }
6508 break;
6509 case 'u': // 3 strings to match.
6510 switch (Name[2]) {
6511 default: break;
6512 case '1': // 1 string to match.
6513 if (Name[3] != '6')
6514 break;
6515 return MCK__DOT_u16; // ".u16"
6516 case '3': // 1 string to match.
6517 if (Name[3] != '2')
6518 break;
6519 return MCK__DOT_u32; // ".u32"
6520 case '6': // 1 string to match.
6521 if (Name[3] != '4')
6522 break;
6523 return MCK__DOT_u64; // ".u64"
6524 }
6525 break;
6526 }
6527 break;
6528 case 5: // 1 string to match.
6529 if (memcmp(Name.data()+0, ".bf16", 5) != 0)
6530 break;
6531 return MCK__DOT_bf16; // ".bf16"
6532 }
6533 return InvalidMatchClass;
6534}
6535
6536/// isSubclass - Compute whether \p A is a subclass of \p B.
6537static bool isSubclass(MatchClassKind A, MatchClassKind B) {
6538 if (A == B)
6539 return true;
6540
6541 switch (A) {
6542 default:
6543 return false;
6544
6545 case MCK__DOT_d:
6546 switch (B) {
6547 default: return false;
6548 case MCK__DOT_f64: return true;
6549 case MCK__DOT_64: return true;
6550 }
6551
6552 case MCK__DOT_f:
6553 switch (B) {
6554 default: return false;
6555 case MCK__DOT_f32: return true;
6556 case MCK__DOT_32: return true;
6557 }
6558
6559 case MCK__DOT_s16:
6560 switch (B) {
6561 default: return false;
6562 case MCK__DOT_i16: return true;
6563 case MCK__DOT_16: return true;
6564 }
6565
6566 case MCK__DOT_s32:
6567 switch (B) {
6568 default: return false;
6569 case MCK__DOT_i32: return true;
6570 case MCK__DOT_32: return true;
6571 }
6572
6573 case MCK__DOT_s64:
6574 switch (B) {
6575 default: return false;
6576 case MCK__DOT_i64: return true;
6577 case MCK__DOT_64: return true;
6578 }
6579
6580 case MCK__DOT_s8:
6581 switch (B) {
6582 default: return false;
6583 case MCK__DOT_i8: return true;
6584 case MCK__DOT_8: return true;
6585 }
6586
6587 case MCK__DOT_u16:
6588 switch (B) {
6589 default: return false;
6590 case MCK__DOT_i16: return true;
6591 case MCK__DOT_16: return true;
6592 }
6593
6594 case MCK__DOT_u32:
6595 switch (B) {
6596 default: return false;
6597 case MCK__DOT_i32: return true;
6598 case MCK__DOT_32: return true;
6599 }
6600
6601 case MCK__DOT_u64:
6602 switch (B) {
6603 default: return false;
6604 case MCK__DOT_i64: return true;
6605 case MCK__DOT_64: return true;
6606 }
6607
6608 case MCK__DOT_u8:
6609 switch (B) {
6610 default: return false;
6611 case MCK__DOT_i8: return true;
6612 case MCK__DOT_8: return true;
6613 }
6614
6615 case MCK__DOT_f32:
6616 return B == MCK__DOT_32;
6617
6618 case MCK__DOT_f64:
6619 return B == MCK__DOT_64;
6620
6621 case MCK__DOT_i16:
6622 return B == MCK__DOT_16;
6623
6624 case MCK__DOT_i32:
6625 return B == MCK__DOT_32;
6626
6627 case MCK__DOT_i64:
6628 return B == MCK__DOT_64;
6629
6630 case MCK__DOT_i8:
6631 return B == MCK__DOT_8;
6632
6633 case MCK__DOT_p16:
6634 return B == MCK__DOT_16;
6635
6636 case MCK__DOT_p8:
6637 return B == MCK__DOT_8;
6638
6639 case MCK_Reg107:
6640 switch (B) {
6641 default: return false;
6642 case MCK_Reg106: return true;
6643 case MCK_Reg104: return true;
6644 case MCK_GPRPair: return true;
6645 }
6646
6647 case MCK_Reg91:
6648 switch (B) {
6649 default: return false;
6650 case MCK_Reg92: return true;
6651 case MCK_Reg93: return true;
6652 case MCK_Reg94: return true;
6653 case MCK_MQQQQPR: return true;
6654 case MCK_Reg96: return true;
6655 case MCK_Reg97: return true;
6656 case MCK_Reg98: return true;
6657 case MCK_QQQQPR: return true;
6658 }
6659
6660 case MCK_APSR:
6661 return B == MCK_GPRwithAPSRnosp;
6662
6663 case MCK_APSR_NZCV:
6664 switch (B) {
6665 default: return false;
6666 case MCK_GPRwithAPSR_NZCVnosp: return true;
6667 case MCK_GPRwithAPSR: return true;
6668 }
6669
6670 case MCK_GPRlr:
6671 switch (B) {
6672 default: return false;
6673 case MCK_Reg34: return true;
6674 case MCK_Reg28: return true;
6675 case MCK_Reg29: return true;
6676 case MCK_Reg26: return true;
6677 case MCK_hGPR: return true;
6678 case MCK_tGPREven: return true;
6679 case MCK_rGPR: return true;
6680 case MCK_GPRnopc: return true;
6681 case MCK_GPRnosp: return true;
6682 case MCK_GPRwithAPSR_NZCVnosp: return true;
6683 case MCK_GPRwithAPSRnosp: return true;
6684 case MCK_GPRwithZRnosp: return true;
6685 case MCK_GPR: return true;
6686 case MCK_GPRwithAPSR: return true;
6687 case MCK_GPRwithZR: return true;
6688 }
6689
6690 case MCK_GPRsp:
6691 switch (B) {
6692 default: return false;
6693 case MCK_Reg30: return true;
6694 case MCK_Reg31: return true;
6695 case MCK_Reg26: return true;
6696 case MCK_hGPR: return true;
6697 case MCK_Reg12: return true;
6698 case MCK_GPRnoip: return true;
6699 case MCK_GPRnopc: return true;
6700 case MCK_GPR: return true;
6701 case MCK_GPRwithAPSR: return true;
6702 case MCK_GPRwithZR: return true;
6703 }
6704
6705 case MCK_PC:
6706 switch (B) {
6707 default: return false;
6708 case MCK_Reg32: return true;
6709 case MCK_Reg31: return true;
6710 case MCK_Reg29: return true;
6711 case MCK_hGPR: return true;
6712 case MCK_tGPRwithpc: return true;
6713 case MCK_Reg14: return true;
6714 case MCK_GPRnoip: return true;
6715 case MCK_GPRnosp: return true;
6716 case MCK_GPR: return true;
6717 }
6718
6719 case MCK_R12:
6720 switch (B) {
6721 default: return false;
6722 case MCK_Reg21: return true;
6723 case MCK_Reg34: return true;
6724 case MCK_tcGPR: return true;
6725 case MCK_Reg28: return true;
6726 case MCK_Reg29: return true;
6727 case MCK_Reg26: return true;
6728 case MCK_hGPR: return true;
6729 case MCK_tGPREven: return true;
6730 case MCK_rGPR: return true;
6731 case MCK_GPRnopc: return true;
6732 case MCK_GPRnosp: return true;
6733 case MCK_GPRwithAPSR_NZCVnosp: return true;
6734 case MCK_GPRwithAPSRnosp: return true;
6735 case MCK_GPRwithZRnosp: return true;
6736 case MCK_GPR: return true;
6737 case MCK_GPRwithAPSR: return true;
6738 case MCK_GPRwithZR: return true;
6739 }
6740
6741 case MCK_VCCR:
6742 return B == MCK_FPWithVPR;
6743
6744 case MCK_Reg132:
6745 switch (B) {
6746 default: return false;
6747 case MCK_Reg133: return true;
6748 case MCK_Reg134: return true;
6749 case MCK_Reg89: return true;
6750 case MCK_Reg135: return true;
6751 case MCK_Reg90: return true;
6752 case MCK_Reg136: return true;
6753 case MCK_Reg87: return true;
6754 case MCK_Reg137: return true;
6755 case MCK_Reg88: return true;
6756 case MCK_Reg85: return true;
6757 case MCK_Reg138: return true;
6758 case MCK_Reg86: return true;
6759 case MCK_Reg83: return true;
6760 case MCK_Reg84: return true;
6761 case MCK_DQuad: return true;
6762 }
6763
6764 case MCK_Reg105:
6765 switch (B) {
6766 default: return false;
6767 case MCK_Reg106: return true;
6768 case MCK_GPRPairnosp: return true;
6769 case MCK_GPRPair: return true;
6770 }
6771
6772 case MCK_Reg100:
6773 switch (B) {
6774 default: return false;
6775 case MCK_Reg104: return true;
6776 case MCK_Reg101: return true;
6777 case MCK_GPRPairnosp: return true;
6778 case MCK_GPRPair: return true;
6779 }
6780
6781 case MCK_Reg92:
6782 switch (B) {
6783 default: return false;
6784 case MCK_Reg93: return true;
6785 case MCK_Reg94: return true;
6786 case MCK_MQQQQPR: return true;
6787 case MCK_Reg96: return true;
6788 case MCK_Reg97: return true;
6789 case MCK_Reg98: return true;
6790 case MCK_QQQQPR: return true;
6791 }
6792
6793 case MCK_Reg35:
6794 switch (B) {
6795 default: return false;
6796 case MCK_Reg25: return true;
6797 case MCK_Reg32: return true;
6798 case MCK_Reg30: return true;
6799 case MCK_Reg31: return true;
6800 case MCK_Reg28: return true;
6801 case MCK_tGPROdd: return true;
6802 case MCK_Reg29: return true;
6803 case MCK_Reg26: return true;
6804 case MCK_hGPR: return true;
6805 case MCK_Reg2: return true;
6806 case MCK_Reg14: return true;
6807 case MCK_Reg12: return true;
6808 case MCK_GPRnoip: return true;
6809 case MCK_rGPR: return true;
6810 case MCK_GPRnopc: return true;
6811 case MCK_GPRnosp: return true;
6812 case MCK_GPRwithAPSR_NZCVnosp: return true;
6813 case MCK_GPRwithAPSRnosp: return true;
6814 case MCK_GPRwithZRnosp: return true;
6815 case MCK_GPR: return true;
6816 case MCK_GPRwithAPSR: return true;
6817 case MCK_GPRwithZR: return true;
6818 }
6819
6820 case MCK_Reg33:
6821 switch (B) {
6822 default: return false;
6823 case MCK_Reg34: return true;
6824 case MCK_Reg25: return true;
6825 case MCK_Reg32: return true;
6826 case MCK_Reg30: return true;
6827 case MCK_Reg31: return true;
6828 case MCK_Reg28: return true;
6829 case MCK_Reg19: return true;
6830 case MCK_Reg29: return true;
6831 case MCK_Reg26: return true;
6832 case MCK_hGPR: return true;
6833 case MCK_tGPREven: return true;
6834 case MCK_Reg2: return true;
6835 case MCK_Reg14: return true;
6836 case MCK_Reg12: return true;
6837 case MCK_GPRnoip: return true;
6838 case MCK_rGPR: return true;
6839 case MCK_GPRnopc: return true;
6840 case MCK_GPRnosp: return true;
6841 case MCK_GPRwithAPSR_NZCVnosp: return true;
6842 case MCK_GPRwithAPSRnosp: return true;
6843 case MCK_GPRwithZRnosp: return true;
6844 case MCK_GPR: return true;
6845 case MCK_GPRwithAPSR: return true;
6846 case MCK_GPRwithZR: return true;
6847 }
6848
6849 case MCK_Reg22:
6850 switch (B) {
6851 default: return false;
6852 case MCK_Reg23: return true;
6853 case MCK_tcGPRnotr12: return true;
6854 case MCK_tcGPR: return true;
6855 case MCK_tGPROdd: return true;
6856 case MCK_tGPR: return true;
6857 case MCK_tGPRwithpc: return true;
6858 case MCK_Reg2: return true;
6859 case MCK_Reg14: return true;
6860 case MCK_Reg12: return true;
6861 case MCK_GPRnoip: return true;
6862 case MCK_rGPR: return true;
6863 case MCK_GPRnopc: return true;
6864 case MCK_GPRnosp: return true;
6865 case MCK_GPRwithAPSR_NZCVnosp: return true;
6866 case MCK_GPRwithAPSRnosp: return true;
6867 case MCK_GPRwithZRnosp: return true;
6868 case MCK_GPR: return true;
6869 case MCK_GPRwithAPSR: return true;
6870 case MCK_GPRwithZR: return true;
6871 }
6872
6873 case MCK_Reg17:
6874 switch (B) {
6875 default: return false;
6876 case MCK_Reg21: return true;
6877 case MCK_Reg18: return true;
6878 case MCK_tcGPRnotr12: return true;
6879 case MCK_tcGPR: return true;
6880 case MCK_Reg19: return true;
6881 case MCK_tGPR: return true;
6882 case MCK_tGPREven: return true;
6883 case MCK_tGPRwithpc: return true;
6884 case MCK_Reg2: return true;
6885 case MCK_Reg14: return true;
6886 case MCK_Reg12: return true;
6887 case MCK_GPRnoip: return true;
6888 case MCK_rGPR: return true;
6889 case MCK_GPRnopc: return true;
6890 case MCK_GPRnosp: return true;
6891 case MCK_GPRwithAPSR_NZCVnosp: return true;
6892 case MCK_GPRwithAPSRnosp: return true;
6893 case MCK_GPRwithZRnosp: return true;
6894 case MCK_GPR: return true;
6895 case MCK_GPRwithAPSR: return true;
6896 case MCK_GPRwithZR: return true;
6897 }
6898
6899 case MCK_Reg133:
6900 switch (B) {
6901 default: return false;
6902 case MCK_Reg134: return true;
6903 case MCK_Reg135: return true;
6904 case MCK_Reg90: return true;
6905 case MCK_Reg136: return true;
6906 case MCK_Reg87: return true;
6907 case MCK_Reg137: return true;
6908 case MCK_Reg88: return true;
6909 case MCK_Reg85: return true;
6910 case MCK_Reg138: return true;
6911 case MCK_Reg86: return true;
6912 case MCK_Reg83: return true;
6913 case MCK_Reg84: return true;
6914 case MCK_DQuad: return true;
6915 }
6916
6917 case MCK_Reg120:
6918 switch (B) {
6919 default: return false;
6920 case MCK_Reg121: return true;
6921 case MCK_Reg108: return true;
6922 case MCK_Reg122: return true;
6923 case MCK_Reg109: return true;
6924 case MCK_Reg123: return true;
6925 case MCK_Reg110: return true;
6926 case MCK_Reg111: return true;
6927 case MCK_Reg124: return true;
6928 case MCK_Reg112: return true;
6929 case MCK_Reg113: return true;
6930 case MCK_DTriple: return true;
6931 }
6932
6933 case MCK_Reg115:
6934 switch (B) {
6935 default: return false;
6936 case MCK_Reg116: return true;
6937 case MCK_Reg108: return true;
6938 case MCK_Reg117: return true;
6939 case MCK_Reg109: return true;
6940 case MCK_Reg118: return true;
6941 case MCK_Reg110: return true;
6942 case MCK_Reg111: return true;
6943 case MCK_Reg119: return true;
6944 case MCK_Reg112: return true;
6945 case MCK_Reg113: return true;
6946 case MCK_DTriple: return true;
6947 }
6948
6949 case MCK_Reg106:
6950 return B == MCK_GPRPair;
6951
6952 case MCK_Reg104:
6953 return B == MCK_GPRPair;
6954
6955 case MCK_Reg93:
6956 switch (B) {
6957 default: return false;
6958 case MCK_Reg94: return true;
6959 case MCK_MQQQQPR: return true;
6960 case MCK_Reg96: return true;
6961 case MCK_Reg97: return true;
6962 case MCK_Reg98: return true;
6963 case MCK_QQQQPR: return true;
6964 }
6965
6966 case MCK_Reg77:
6967 switch (B) {
6968 default: return false;
6969 case MCK_Reg78: return true;
6970 case MCK_Reg89: return true;
6971 case MCK_Reg90: return true;
6972 case MCK_Reg87: return true;
6973 case MCK_MQQPR: return true;
6974 case MCK_Reg88: return true;
6975 case MCK_Reg80: return true;
6976 case MCK_Reg85: return true;
6977 case MCK_Reg86: return true;
6978 case MCK_Reg83: return true;
6979 case MCK_QQPR: return true;
6980 case MCK_Reg84: return true;
6981 case MCK_DQuad: return true;
6982 }
6983
6984 case MCK_Reg21:
6985 switch (B) {
6986 default: return false;
6987 case MCK_tcGPR: return true;
6988 case MCK_tGPREven: return true;
6989 case MCK_rGPR: return true;
6990 case MCK_GPRnopc: return true;
6991 case MCK_GPRnosp: return true;
6992 case MCK_GPRwithAPSR_NZCVnosp: return true;
6993 case MCK_GPRwithAPSRnosp: return true;
6994 case MCK_GPRwithZRnosp: return true;
6995 case MCK_GPR: return true;
6996 case MCK_GPRwithAPSR: return true;
6997 case MCK_GPRwithZR: return true;
6998 }
6999
7000 case MCK_Reg134:
7001 switch (B) {
7002 default: return false;
7003 case MCK_Reg135: return true;
7004 case MCK_Reg136: return true;
7005 case MCK_Reg137: return true;
7006 case MCK_Reg88: return true;
7007 case MCK_Reg85: return true;
7008 case MCK_Reg138: return true;
7009 case MCK_Reg86: return true;
7010 case MCK_Reg83: return true;
7011 case MCK_Reg84: return true;
7012 case MCK_DQuad: return true;
7013 }
7014
7015 case MCK_Reg125:
7016 switch (B) {
7017 default: return false;
7018 case MCK_Reg126: return true;
7019 case MCK_Reg127: return true;
7020 case MCK_Reg128: return true;
7021 case MCK_Reg129: return true;
7022 case MCK_Reg130: return true;
7023 case MCK_DTripleSpc: return true;
7024 }
7025
7026 case MCK_Reg121:
7027 switch (B) {
7028 default: return false;
7029 case MCK_Reg122: return true;
7030 case MCK_Reg123: return true;
7031 case MCK_Reg110: return true;
7032 case MCK_Reg111: return true;
7033 case MCK_Reg124: return true;
7034 case MCK_Reg112: return true;
7035 case MCK_Reg113: return true;
7036 case MCK_DTriple: return true;
7037 }
7038
7039 case MCK_Reg116:
7040 switch (B) {
7041 default: return false;
7042 case MCK_Reg117: return true;
7043 case MCK_Reg109: return true;
7044 case MCK_Reg118: return true;
7045 case MCK_Reg110: return true;
7046 case MCK_Reg111: return true;
7047 case MCK_Reg119: return true;
7048 case MCK_Reg112: return true;
7049 case MCK_Reg113: return true;
7050 case MCK_DTriple: return true;
7051 }
7052
7053 case MCK_Reg101:
7054 switch (B) {
7055 default: return false;
7056 case MCK_GPRPairnosp: return true;
7057 case MCK_GPRPair: return true;
7058 }
7059
7060 case MCK_Reg94:
7061 switch (B) {
7062 default: return false;
7063 case MCK_MQQQQPR: return true;
7064 case MCK_Reg96: return true;
7065 case MCK_Reg97: return true;
7066 case MCK_Reg98: return true;
7067 case MCK_QQQQPR: return true;
7068 }
7069
7070 case MCK_Reg78:
7071 switch (B) {
7072 default: return false;
7073 case MCK_Reg87: return true;
7074 case MCK_MQQPR: return true;
7075 case MCK_Reg88: return true;
7076 case MCK_Reg80: return true;
7077 case MCK_Reg85: return true;
7078 case MCK_Reg86: return true;
7079 case MCK_Reg83: return true;
7080 case MCK_QQPR: return true;
7081 case MCK_Reg84: return true;
7082 case MCK_DQuad: return true;
7083 }
7084
7085 case MCK_Reg34:
7086 switch (B) {
7087 default: return false;
7088 case MCK_Reg28: return true;
7089 case MCK_Reg29: return true;
7090 case MCK_Reg26: return true;
7091 case MCK_hGPR: return true;
7092 case MCK_tGPREven: return true;
7093 case MCK_rGPR: return true;
7094 case MCK_GPRnopc: return true;
7095 case MCK_GPRnosp: return true;
7096 case MCK_GPRwithAPSR_NZCVnosp: return true;
7097 case MCK_GPRwithAPSRnosp: return true;
7098 case MCK_GPRwithZRnosp: return true;
7099 case MCK_GPR: return true;
7100 case MCK_GPRwithAPSR: return true;
7101 case MCK_GPRwithZR: return true;
7102 }
7103
7104 case MCK_Reg25:
7105 switch (B) {
7106 default: return false;
7107 case MCK_Reg32: return true;
7108 case MCK_Reg30: return true;
7109 case MCK_Reg31: return true;
7110 case MCK_Reg28: return true;
7111 case MCK_Reg29: return true;
7112 case MCK_Reg26: return true;
7113 case MCK_hGPR: return true;
7114 case MCK_Reg2: return true;
7115 case MCK_Reg14: return true;
7116 case MCK_Reg12: return true;
7117 case MCK_GPRnoip: return true;
7118 case MCK_rGPR: return true;
7119 case MCK_GPRnopc: return true;
7120 case MCK_GPRnosp: return true;
7121 case MCK_GPRwithAPSR_NZCVnosp: return true;
7122 case MCK_GPRwithAPSRnosp: return true;
7123 case MCK_GPRwithZRnosp: return true;
7124 case MCK_GPR: return true;
7125 case MCK_GPRwithAPSR: return true;
7126 case MCK_GPRwithZR: return true;
7127 }
7128
7129 case MCK_Reg23:
7130 switch (B) {
7131 default: return false;
7132 case MCK_tGPROdd: return true;
7133 case MCK_tGPR: return true;
7134 case MCK_tGPRwithpc: return true;
7135 case MCK_Reg2: return true;
7136 case MCK_Reg14: return true;
7137 case MCK_Reg12: return true;
7138 case MCK_GPRnoip: return true;
7139 case MCK_rGPR: return true;
7140 case MCK_GPRnopc: return true;
7141 case MCK_GPRnosp: return true;
7142 case MCK_GPRwithAPSR_NZCVnosp: return true;
7143 case MCK_GPRwithAPSRnosp: return true;
7144 case MCK_GPRwithZRnosp: return true;
7145 case MCK_GPR: return true;
7146 case MCK_GPRwithAPSR: return true;
7147 case MCK_GPRwithZR: return true;
7148 }
7149
7150 case MCK_Reg18:
7151 switch (B) {
7152 default: return false;
7153 case MCK_Reg19: return true;
7154 case MCK_tGPR: return true;
7155 case MCK_tGPREven: return true;
7156 case MCK_tGPRwithpc: return true;
7157 case MCK_Reg2: return true;
7158 case MCK_Reg14: return true;
7159 case MCK_Reg12: return true;
7160 case MCK_GPRnoip: return true;
7161 case MCK_rGPR: return true;
7162 case MCK_GPRnopc: return true;
7163 case MCK_GPRnosp: return true;
7164 case MCK_GPRwithAPSR_NZCVnosp: return true;
7165 case MCK_GPRwithAPSRnosp: return true;
7166 case MCK_GPRwithZRnosp: return true;
7167 case MCK_GPR: return true;
7168 case MCK_GPRwithAPSR: return true;
7169 case MCK_GPRwithZR: return true;
7170 }
7171
7172 case MCK_QPR_8:
7173 switch (B) {
7174 default: return false;
7175 case MCK_Reg52: return true;
7176 case MCK_Reg53: return true;
7177 case MCK_MQPR: return true;
7178 case MCK_Reg50: return true;
7179 case MCK_Reg51: return true;
7180 case MCK_QPR: return true;
7181 case MCK_DPair: return true;
7182 }
7183
7184 case MCK_tcGPRnotr12:
7185 switch (B) {
7186 default: return false;
7187 case MCK_tcGPR: return true;
7188 case MCK_tGPR: return true;
7189 case MCK_tGPRwithpc: return true;
7190 case MCK_Reg2: return true;
7191 case MCK_Reg14: return true;
7192 case MCK_Reg12: return true;
7193 case MCK_GPRnoip: return true;
7194 case MCK_rGPR: return true;
7195 case MCK_GPRnopc: return true;
7196 case MCK_GPRnosp: return true;
7197 case MCK_GPRwithAPSR_NZCVnosp: return true;
7198 case MCK_GPRwithAPSRnosp: return true;
7199 case MCK_GPRwithZRnosp: return true;
7200 case MCK_GPR: return true;
7201 case MCK_GPRwithAPSR: return true;
7202 case MCK_GPRwithZR: return true;
7203 }
7204
7205 case MCK_Reg89:
7206 switch (B) {
7207 default: return false;
7208 case MCK_Reg90: return true;
7209 case MCK_Reg87: return true;
7210 case MCK_Reg88: return true;
7211 case MCK_Reg85: return true;
7212 case MCK_Reg86: return true;
7213 case MCK_Reg83: return true;
7214 case MCK_Reg84: return true;
7215 case MCK_DQuad: return true;
7216 }
7217
7218 case MCK_Reg32:
7219 switch (B) {
7220 default: return false;
7221 case MCK_Reg31: return true;
7222 case MCK_Reg29: return true;
7223 case MCK_hGPR: return true;
7224 case MCK_Reg14: return true;
7225 case MCK_GPRnoip: return true;
7226 case MCK_GPRnosp: return true;
7227 case MCK_GPR: return true;
7228 }
7229
7230 case MCK_Reg30:
7231 switch (B) {
7232 default: return false;
7233 case MCK_Reg31: return true;
7234 case MCK_Reg26: return true;
7235 case MCK_hGPR: return true;
7236 case MCK_Reg12: return true;
7237 case MCK_GPRnoip: return true;
7238 case MCK_GPRnopc: return true;
7239 case MCK_GPR: return true;
7240 case MCK_GPRwithAPSR: return true;
7241 case MCK_GPRwithZR: return true;
7242 }
7243
7244 case MCK_MQQQQPR:
7245 switch (B) {
7246 default: return false;
7247 case MCK_Reg96: return true;
7248 case MCK_Reg97: return true;
7249 case MCK_Reg98: return true;
7250 case MCK_QQQQPR: return true;
7251 }
7252
7253 case MCK_tcGPR:
7254 switch (B) {
7255 default: return false;
7256 case MCK_rGPR: return true;
7257 case MCK_GPRnopc: return true;
7258 case MCK_GPRnosp: return true;
7259 case MCK_GPRwithAPSR_NZCVnosp: return true;
7260 case MCK_GPRwithAPSRnosp: return true;
7261 case MCK_GPRwithZRnosp: return true;
7262 case MCK_GPR: return true;
7263 case MCK_GPRwithAPSR: return true;
7264 case MCK_GPRwithZR: return true;
7265 }
7266
7267 case MCK_Reg135:
7268 switch (B) {
7269 default: return false;
7270 case MCK_Reg136: return true;
7271 case MCK_Reg137: return true;
7272 case MCK_Reg85: return true;
7273 case MCK_Reg138: return true;
7274 case MCK_Reg86: return true;
7275 case MCK_Reg83: return true;
7276 case MCK_Reg84: return true;
7277 case MCK_DQuad: return true;
7278 }
7279
7280 case MCK_Reg126:
7281 switch (B) {
7282 default: return false;
7283 case MCK_Reg127: return true;
7284 case MCK_Reg128: return true;
7285 case MCK_Reg129: return true;
7286 case MCK_Reg130: return true;
7287 case MCK_DTripleSpc: return true;
7288 }
7289
7290 case MCK_Reg108:
7291 switch (B) {
7292 default: return false;
7293 case MCK_Reg109: return true;
7294 case MCK_Reg110: return true;
7295 case MCK_Reg111: return true;
7296 case MCK_Reg112: return true;
7297 case MCK_Reg113: return true;
7298 case MCK_DTriple: return true;
7299 }
7300
7301 case MCK_Reg96:
7302 switch (B) {
7303 default: return false;
7304 case MCK_Reg97: return true;
7305 case MCK_Reg98: return true;
7306 case MCK_QQQQPR: return true;
7307 }
7308
7309 case MCK_Reg90:
7310 switch (B) {
7311 default: return false;
7312 case MCK_Reg87: return true;
7313 case MCK_Reg88: return true;
7314 case MCK_Reg85: return true;
7315 case MCK_Reg86: return true;
7316 case MCK_Reg83: return true;
7317 case MCK_Reg84: return true;
7318 case MCK_DQuad: return true;
7319 }
7320
7321 case MCK_Reg72:
7322 switch (B) {
7323 default: return false;
7324 case MCK_Reg73: return true;
7325 case MCK_Reg74: return true;
7326 case MCK_Reg75: return true;
7327 case MCK_DPairSpc: return true;
7328 }
7329
7330 case MCK_Reg31:
7331 switch (B) {
7332 default: return false;
7333 case MCK_hGPR: return true;
7334 case MCK_GPRnoip: return true;
7335 case MCK_GPR: return true;
7336 }
7337
7338 case MCK_Reg28:
7339 switch (B) {
7340 default: return false;
7341 case MCK_Reg29: return true;
7342 case MCK_Reg26: return true;
7343 case MCK_hGPR: return true;
7344 case MCK_rGPR: return true;
7345 case MCK_GPRnopc: return true;
7346 case MCK_GPRnosp: return true;
7347 case MCK_GPRwithAPSR_NZCVnosp: return true;
7348 case MCK_GPRwithAPSRnosp: return true;
7349 case MCK_GPRwithZRnosp: return true;
7350 case MCK_GPR: return true;
7351 case MCK_GPRwithAPSR: return true;
7352 case MCK_GPRwithZR: return true;
7353 }
7354
7355 case MCK_Reg19:
7356 switch (B) {
7357 default: return false;
7358 case MCK_tGPREven: return true;
7359 case MCK_Reg2: return true;
7360 case MCK_Reg14: return true;
7361 case MCK_Reg12: return true;
7362 case MCK_GPRnoip: return true;
7363 case MCK_rGPR: return true;
7364 case MCK_GPRnopc: return true;
7365 case MCK_GPRnosp: return true;
7366 case MCK_GPRwithAPSR_NZCVnosp: return true;
7367 case MCK_GPRwithAPSRnosp: return true;
7368 case MCK_GPRwithZRnosp: return true;
7369 case MCK_GPR: return true;
7370 case MCK_GPRwithAPSR: return true;
7371 case MCK_GPRwithZR: return true;
7372 }
7373
7374 case MCK_GPRPairnosp:
7375 return B == MCK_GPRPair;
7376
7377 case MCK_tGPROdd:
7378 switch (B) {
7379 default: return false;
7380 case MCK_Reg2: return true;
7381 case MCK_Reg14: return true;
7382 case MCK_Reg12: return true;
7383 case MCK_GPRnoip: return true;
7384 case MCK_rGPR: return true;
7385 case MCK_GPRnopc: return true;
7386 case MCK_GPRnosp: return true;
7387 case MCK_GPRwithAPSR_NZCVnosp: return true;
7388 case MCK_GPRwithAPSRnosp: return true;
7389 case MCK_GPRwithZRnosp: return true;
7390 case MCK_GPR: return true;
7391 case MCK_GPRwithAPSR: return true;
7392 case MCK_GPRwithZR: return true;
7393 }
7394
7395 case MCK_Reg136:
7396 switch (B) {
7397 default: return false;
7398 case MCK_Reg137: return true;
7399 case MCK_Reg138: return true;
7400 case MCK_Reg86: return true;
7401 case MCK_Reg83: return true;
7402 case MCK_Reg84: return true;
7403 case MCK_DQuad: return true;
7404 }
7405
7406 case MCK_Reg122:
7407 switch (B) {
7408 default: return false;
7409 case MCK_Reg123: return true;
7410 case MCK_Reg111: return true;
7411 case MCK_Reg124: return true;
7412 case MCK_Reg112: return true;
7413 case MCK_Reg113: return true;
7414 case MCK_DTriple: return true;
7415 }
7416
7417 case MCK_Reg117:
7418 switch (B) {
7419 default: return false;
7420 case MCK_Reg118: return true;
7421 case MCK_Reg111: return true;
7422 case MCK_Reg119: return true;
7423 case MCK_Reg112: return true;
7424 case MCK_Reg113: return true;
7425 case MCK_DTriple: return true;
7426 }
7427
7428 case MCK_Reg109:
7429 switch (B) {
7430 default: return false;
7431 case MCK_Reg110: return true;
7432 case MCK_Reg111: return true;
7433 case MCK_Reg112: return true;
7434 case MCK_Reg113: return true;
7435 case MCK_DTriple: return true;
7436 }
7437
7438 case MCK_Reg97:
7439 switch (B) {
7440 default: return false;
7441 case MCK_Reg98: return true;
7442 case MCK_QQQQPR: return true;
7443 }
7444
7445 case MCK_Reg87:
7446 switch (B) {
7447 default: return false;
7448 case MCK_Reg88: return true;
7449 case MCK_Reg85: return true;
7450 case MCK_Reg86: return true;
7451 case MCK_Reg83: return true;
7452 case MCK_Reg84: return true;
7453 case MCK_DQuad: return true;
7454 }
7455
7456 case MCK_Reg52:
7457 switch (B) {
7458 default: return false;
7459 case MCK_Reg53: return true;
7460 case MCK_Reg50: return true;
7461 case MCK_Reg51: return true;
7462 case MCK_DPair: return true;
7463 }
7464
7465 case MCK_Reg29:
7466 switch (B) {
7467 default: return false;
7468 case MCK_hGPR: return true;
7469 case MCK_GPRnosp: return true;
7470 case MCK_GPR: return true;
7471 }
7472
7473 case MCK_Reg26:
7474 switch (B) {
7475 default: return false;
7476 case MCK_hGPR: return true;
7477 case MCK_GPRnopc: return true;
7478 case MCK_GPR: return true;
7479 case MCK_GPRwithAPSR: return true;
7480 case MCK_GPRwithZR: return true;
7481 }
7482
7483 case MCK_MQQPR:
7484 switch (B) {
7485 default: return false;
7486 case MCK_Reg80: return true;
7487 case MCK_Reg85: return true;
7488 case MCK_Reg86: return true;
7489 case MCK_Reg83: return true;
7490 case MCK_QQPR: return true;
7491 case MCK_Reg84: return true;
7492 case MCK_DQuad: return true;
7493 }
7494
7495 case MCK_Reg137:
7496 switch (B) {
7497 default: return false;
7498 case MCK_Reg138: return true;
7499 case MCK_Reg84: return true;
7500 case MCK_DQuad: return true;
7501 }
7502
7503 case MCK_Reg127:
7504 switch (B) {
7505 default: return false;
7506 case MCK_Reg128: return true;
7507 case MCK_Reg129: return true;
7508 case MCK_Reg130: return true;
7509 case MCK_DTripleSpc: return true;
7510 }
7511
7512 case MCK_Reg123:
7513 switch (B) {
7514 default: return false;
7515 case MCK_Reg124: return true;
7516 case MCK_Reg113: return true;
7517 case MCK_DTriple: return true;
7518 }
7519
7520 case MCK_Reg118:
7521 switch (B) {
7522 default: return false;
7523 case MCK_Reg119: return true;
7524 case MCK_Reg112: return true;
7525 case MCK_Reg113: return true;
7526 case MCK_DTriple: return true;
7527 }
7528
7529 case MCK_Reg110:
7530 switch (B) {
7531 default: return false;
7532 case MCK_Reg111: return true;
7533 case MCK_Reg112: return true;
7534 case MCK_Reg113: return true;
7535 case MCK_DTriple: return true;
7536 }
7537
7538 case MCK_Reg98:
7539 return B == MCK_QQQQPR;
7540
7541 case MCK_Reg88:
7542 switch (B) {
7543 default: return false;
7544 case MCK_Reg85: return true;
7545 case MCK_Reg86: return true;
7546 case MCK_Reg83: return true;
7547 case MCK_Reg84: return true;
7548 case MCK_DQuad: return true;
7549 }
7550
7551 case MCK_Reg80:
7552 switch (B) {
7553 default: return false;
7554 case MCK_Reg83: return true;
7555 case MCK_QQPR: return true;
7556 case MCK_Reg84: return true;
7557 case MCK_DQuad: return true;
7558 }
7559
7560 case MCK_Reg73:
7561 switch (B) {
7562 default: return false;
7563 case MCK_Reg74: return true;
7564 case MCK_Reg75: return true;
7565 case MCK_DPairSpc: return true;
7566 }
7567
7568 case MCK_Reg53:
7569 switch (B) {
7570 default: return false;
7571 case MCK_Reg50: return true;
7572 case MCK_Reg51: return true;
7573 case MCK_DPair: return true;
7574 }
7575
7576 case MCK_DPR_8:
7577 switch (B) {
7578 default: return false;
7579 case MCK_DPR_VFP2: return true;
7580 case MCK_DPR: return true;
7581 case MCK_FPWithVPR: return true;
7582 }
7583
7584 case MCK_MQPR:
7585 switch (B) {
7586 default: return false;
7587 case MCK_Reg50: return true;
7588 case MCK_Reg51: return true;
7589 case MCK_QPR: return true;
7590 case MCK_DPair: return true;
7591 }
7592
7593 case MCK_hGPR:
7594 return B == MCK_GPR;
7595
7596 case MCK_tGPR:
7597 switch (B) {
7598 default: return false;
7599 case MCK_tGPRwithpc: return true;
7600 case MCK_Reg2: return true;
7601 case MCK_Reg14: return true;
7602 case MCK_Reg12: return true;
7603 case MCK_GPRnoip: return true;
7604 case MCK_rGPR: return true;
7605 case MCK_GPRnopc: return true;
7606 case MCK_GPRnosp: return true;
7607 case MCK_GPRwithAPSR_NZCVnosp: return true;
7608 case MCK_GPRwithAPSRnosp: return true;
7609 case MCK_GPRwithZRnosp: return true;
7610 case MCK_GPR: return true;
7611 case MCK_GPRwithAPSR: return true;
7612 case MCK_GPRwithZR: return true;
7613 }
7614
7615 case MCK_tGPREven:
7616 switch (B) {
7617 default: return false;
7618 case MCK_rGPR: return true;
7619 case MCK_GPRnopc: return true;
7620 case MCK_GPRnosp: return true;
7621 case MCK_GPRwithAPSR_NZCVnosp: return true;
7622 case MCK_GPRwithAPSRnosp: return true;
7623 case MCK_GPRwithZRnosp: return true;
7624 case MCK_GPR: return true;
7625 case MCK_GPRwithAPSR: return true;
7626 case MCK_GPRwithZR: return true;
7627 }
7628
7629 case MCK_tGPRwithpc:
7630 switch (B) {
7631 default: return false;
7632 case MCK_Reg14: return true;
7633 case MCK_GPRnoip: return true;
7634 case MCK_GPRnosp: return true;
7635 case MCK_GPR: return true;
7636 }
7637
7638 case MCK_Reg128:
7639 switch (B) {
7640 default: return false;
7641 case MCK_Reg129: return true;
7642 case MCK_Reg130: return true;
7643 case MCK_DTripleSpc: return true;
7644 }
7645
7646 case MCK_Reg2:
7647 switch (B) {
7648 default: return false;
7649 case MCK_Reg14: return true;
7650 case MCK_Reg12: return true;
7651 case MCK_GPRnoip: return true;
7652 case MCK_rGPR: return true;
7653 case MCK_GPRnopc: return true;
7654 case MCK_GPRnosp: return true;
7655 case MCK_GPRwithAPSR_NZCVnosp: return true;
7656 case MCK_GPRwithAPSRnosp: return true;
7657 case MCK_GPRwithZRnosp: return true;
7658 case MCK_GPR: return true;
7659 case MCK_GPRwithAPSR: return true;
7660 case MCK_GPRwithZR: return true;
7661 }
7662
7663 case MCK_Reg85:
7664 switch (B) {
7665 default: return false;
7666 case MCK_Reg86: return true;
7667 case MCK_Reg83: return true;
7668 case MCK_Reg84: return true;
7669 case MCK_DQuad: return true;
7670 }
7671
7672 case MCK_Reg14:
7673 switch (B) {
7674 default: return false;
7675 case MCK_GPRnoip: return true;
7676 case MCK_GPRnosp: return true;
7677 case MCK_GPR: return true;
7678 }
7679
7680 case MCK_Reg12:
7681 switch (B) {
7682 default: return false;
7683 case MCK_GPRnoip: return true;
7684 case MCK_GPRnopc: return true;
7685 case MCK_GPR: return true;
7686 case MCK_GPRwithAPSR: return true;
7687 case MCK_GPRwithZR: return true;
7688 }
7689
7690 case MCK_Reg138:
7691 return B == MCK_DQuad;
7692
7693 case MCK_Reg129:
7694 switch (B) {
7695 default: return false;
7696 case MCK_Reg130: return true;
7697 case MCK_DTripleSpc: return true;
7698 }
7699
7700 case MCK_Reg111:
7701 switch (B) {
7702 default: return false;
7703 case MCK_Reg112: return true;
7704 case MCK_Reg113: return true;
7705 case MCK_DTriple: return true;
7706 }
7707
7708 case MCK_Reg86:
7709 switch (B) {
7710 default: return false;
7711 case MCK_Reg83: return true;
7712 case MCK_Reg84: return true;
7713 case MCK_DQuad: return true;
7714 }
7715
7716 case MCK_Reg74:
7717 switch (B) {
7718 default: return false;
7719 case MCK_Reg75: return true;
7720 case MCK_DPairSpc: return true;
7721 }
7722
7723 case MCK_GPRnoip:
7724 return B == MCK_GPR;
7725
7726 case MCK_rGPR:
7727 switch (B) {
7728 default: return false;
7729 case MCK_GPRnopc: return true;
7730 case MCK_GPRnosp: return true;
7731 case MCK_GPRwithAPSR_NZCVnosp: return true;
7732 case MCK_GPRwithAPSRnosp: return true;
7733 case MCK_GPRwithZRnosp: return true;
7734 case MCK_GPR: return true;
7735 case MCK_GPRwithAPSR: return true;
7736 case MCK_GPRwithZR: return true;
7737 }
7738
7739 case MCK_Reg124:
7740 return B == MCK_DTriple;
7741
7742 case MCK_Reg119:
7743 return B == MCK_DTriple;
7744
7745 case MCK_Reg112:
7746 switch (B) {
7747 default: return false;
7748 case MCK_Reg113: return true;
7749 case MCK_DTriple: return true;
7750 }
7751
7752 case MCK_Reg83:
7753 switch (B) {
7754 default: return false;
7755 case MCK_Reg84: return true;
7756 case MCK_DQuad: return true;
7757 }
7758
7759 case MCK_Reg50:
7760 switch (B) {
7761 default: return false;
7762 case MCK_Reg51: return true;
7763 case MCK_DPair: return true;
7764 }
7765
7766 case MCK_GPRnopc:
7767 switch (B) {
7768 default: return false;
7769 case MCK_GPR: return true;
7770 case MCK_GPRwithAPSR: return true;
7771 case MCK_GPRwithZR: return true;
7772 }
7773
7774 case MCK_GPRnosp:
7775 return B == MCK_GPR;
7776
7777 case MCK_GPRwithAPSR_NZCVnosp:
7778 return B == MCK_GPRwithAPSR;
7779
7780 case MCK_GPRwithZRnosp:
7781 return B == MCK_GPRwithZR;
7782
7783 case MCK_QQPR:
7784 return B == MCK_DQuad;
7785
7786 case MCK_Reg130:
7787 return B == MCK_DTripleSpc;
7788
7789 case MCK_Reg113:
7790 return B == MCK_DTriple;
7791
7792 case MCK_Reg84:
7793 return B == MCK_DQuad;
7794
7795 case MCK_Reg75:
7796 return B == MCK_DPairSpc;
7797
7798 case MCK_Reg51:
7799 return B == MCK_DPair;
7800
7801 case MCK_DPR_VFP2:
7802 switch (B) {
7803 default: return false;
7804 case MCK_DPR: return true;
7805 case MCK_FPWithVPR: return true;
7806 }
7807
7808 case MCK_QPR:
7809 return B == MCK_DPair;
7810
7811 case MCK_SPR_8:
7812 switch (B) {
7813 default: return false;
7814 case MCK_HPR: return true;
7815 case MCK_FPWithVPR: return true;
7816 }
7817
7818 case MCK_DPR:
7819 return B == MCK_FPWithVPR;
7820
7821 case MCK_HPR:
7822 return B == MCK_FPWithVPR;
7823
7824 case MCK_CCOut:
7825 return B == OptionalMatchClass;
7826
7827 case MCK_CondCode:
7828 return B == OptionalMatchClass;
7829
7830 case MCK_VPTPredN:
7831 return B == OptionalMatchClass;
7832
7833 case MCK_VPTPredR:
7834 return B == OptionalMatchClass;
7835 }
7836}
7837
7838static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
7839 ARMOperand &Operand = (ARMOperand &)GOp;
7840 if (Kind == InvalidMatchClass)
7841 return MCTargetAsmParser::Match_InvalidOperand;
7842
7843 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
7844 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
7845 MCTargetAsmParser::Match_Success :
7846 MCTargetAsmParser::Match_InvalidOperand;
7847
7848 switch (Kind) {
7849 default: break;
7850 // 'AM2OffsetImm' class
7851 case MCK_AM2OffsetImm: {
7852 DiagnosticPredicate DP(Operand.isAM2OffsetImm());
7853 if (DP.isMatch())
7854 return MCTargetAsmParser::Match_Success;
7855 break;
7856 }
7857 // 'AM3Offset' class
7858 case MCK_AM3Offset: {
7859 DiagnosticPredicate DP(Operand.isAM3Offset());
7860 if (DP.isMatch())
7861 return MCTargetAsmParser::Match_Success;
7862 break;
7863 }
7864 // 'ARMBranchTarget' class
7865 case MCK_ARMBranchTarget: {
7866 DiagnosticPredicate DP(Operand.isARMBranchTarget());
7867 if (DP.isMatch())
7868 return MCTargetAsmParser::Match_Success;
7869 break;
7870 }
7871 // 'AddrMode3' class
7872 case MCK_AddrMode3: {
7873 DiagnosticPredicate DP(Operand.isAddrMode3());
7874 if (DP.isMatch())
7875 return MCTargetAsmParser::Match_Success;
7876 break;
7877 }
7878 // 'AddrMode5' class
7879 case MCK_AddrMode5: {
7880 DiagnosticPredicate DP(Operand.isAddrMode5());
7881 if (DP.isMatch())
7882 return MCTargetAsmParser::Match_Success;
7883 break;
7884 }
7885 // 'AddrMode5FP16' class
7886 case MCK_AddrMode5FP16: {
7887 DiagnosticPredicate DP(Operand.isAddrMode5FP16());
7888 if (DP.isMatch())
7889 return MCTargetAsmParser::Match_Success;
7890 break;
7891 }
7892 // 'AlignedMemory16' class
7893 case MCK_AlignedMemory16: {
7894 DiagnosticPredicate DP(Operand.isAlignedMemory16());
7895 if (DP.isMatch())
7896 return MCTargetAsmParser::Match_Success;
7897 if (DP.isNearMatch())
7898 return ARMAsmParser::Match_AlignedMemory16;
7899 break;
7900 }
7901 // 'AlignedMemory32' class
7902 case MCK_AlignedMemory32: {
7903 DiagnosticPredicate DP(Operand.isAlignedMemory32());
7904 if (DP.isMatch())
7905 return MCTargetAsmParser::Match_Success;
7906 if (DP.isNearMatch())
7907 return ARMAsmParser::Match_AlignedMemory32;
7908 break;
7909 }
7910 // 'AlignedMemory64' class
7911 case MCK_AlignedMemory64: {
7912 DiagnosticPredicate DP(Operand.isAlignedMemory64());
7913 if (DP.isMatch())
7914 return MCTargetAsmParser::Match_Success;
7915 if (DP.isNearMatch())
7916 return ARMAsmParser::Match_AlignedMemory64;
7917 break;
7918 }
7919 // 'AlignedMemory64or128' class
7920 case MCK_AlignedMemory64or128: {
7921 DiagnosticPredicate DP(Operand.isAlignedMemory64or128());
7922 if (DP.isMatch())
7923 return MCTargetAsmParser::Match_Success;
7924 if (DP.isNearMatch())
7925 return ARMAsmParser::Match_AlignedMemory64or128;
7926 break;
7927 }
7928 // 'AlignedMemory64or128or256' class
7929 case MCK_AlignedMemory64or128or256: {
7930 DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256());
7931 if (DP.isMatch())
7932 return MCTargetAsmParser::Match_Success;
7933 if (DP.isNearMatch())
7934 return ARMAsmParser::Match_AlignedMemory64or128or256;
7935 break;
7936 }
7937 // 'AlignedMemoryNone' class
7938 case MCK_AlignedMemoryNone: {
7939 DiagnosticPredicate DP(Operand.isAlignedMemoryNone());
7940 if (DP.isMatch())
7941 return MCTargetAsmParser::Match_Success;
7942 if (DP.isNearMatch())
7943 return ARMAsmParser::Match_AlignedMemoryNone;
7944 break;
7945 }
7946 // 'AlignedMemory' class
7947 case MCK_AlignedMemory: {
7948 DiagnosticPredicate DP(Operand.isAlignedMemory());
7949 if (DP.isMatch())
7950 return MCTargetAsmParser::Match_Success;
7951 break;
7952 }
7953 // 'DupAlignedMemory16' class
7954 case MCK_DupAlignedMemory16: {
7955 DiagnosticPredicate DP(Operand.isDupAlignedMemory16());
7956 if (DP.isMatch())
7957 return MCTargetAsmParser::Match_Success;
7958 if (DP.isNearMatch())
7959 return ARMAsmParser::Match_DupAlignedMemory16;
7960 break;
7961 }
7962 // 'DupAlignedMemory32' class
7963 case MCK_DupAlignedMemory32: {
7964 DiagnosticPredicate DP(Operand.isDupAlignedMemory32());
7965 if (DP.isMatch())
7966 return MCTargetAsmParser::Match_Success;
7967 if (DP.isNearMatch())
7968 return ARMAsmParser::Match_DupAlignedMemory32;
7969 break;
7970 }
7971 // 'DupAlignedMemory64' class
7972 case MCK_DupAlignedMemory64: {
7973 DiagnosticPredicate DP(Operand.isDupAlignedMemory64());
7974 if (DP.isMatch())
7975 return MCTargetAsmParser::Match_Success;
7976 if (DP.isNearMatch())
7977 return ARMAsmParser::Match_DupAlignedMemory64;
7978 break;
7979 }
7980 // 'DupAlignedMemory64or128' class
7981 case MCK_DupAlignedMemory64or128: {
7982 DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128());
7983 if (DP.isMatch())
7984 return MCTargetAsmParser::Match_Success;
7985 if (DP.isNearMatch())
7986 return ARMAsmParser::Match_DupAlignedMemory64or128;
7987 break;
7988 }
7989 // 'DupAlignedMemoryNone' class
7990 case MCK_DupAlignedMemoryNone: {
7991 DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone());
7992 if (DP.isMatch())
7993 return MCTargetAsmParser::Match_Success;
7994 if (DP.isNearMatch())
7995 return ARMAsmParser::Match_DupAlignedMemoryNone;
7996 break;
7997 }
7998 // 'AdrLabel' class
7999 case MCK_AdrLabel: {
8000 DiagnosticPredicate DP(Operand.isAdrLabel());
8001 if (DP.isMatch())
8002 return MCTargetAsmParser::Match_Success;
8003 break;
8004 }
8005 // 'BankedReg' class
8006 case MCK_BankedReg: {
8007 DiagnosticPredicate DP(Operand.isBankedReg());
8008 if (DP.isMatch())
8009 return MCTargetAsmParser::Match_Success;
8010 break;
8011 }
8012 // 'Bitfield' class
8013 case MCK_Bitfield: {
8014 DiagnosticPredicate DP(Operand.isBitfield());
8015 if (DP.isMatch())
8016 return MCTargetAsmParser::Match_Success;
8017 break;
8018 }
8019 // 'CCOut' class
8020 case MCK_CCOut: {
8021 DiagnosticPredicate DP(Operand.isCCOut());
8022 if (DP.isMatch())
8023 return MCTargetAsmParser::Match_Success;
8024 break;
8025 }
8026 // 'CondCode' class
8027 case MCK_CondCode: {
8028 DiagnosticPredicate DP(Operand.isCondCode());
8029 if (DP.isMatch())
8030 return MCTargetAsmParser::Match_Success;
8031 break;
8032 }
8033 // 'CoprocNum' class
8034 case MCK_CoprocNum: {
8035 DiagnosticPredicate DP(Operand.isCoprocNum());
8036 if (DP.isMatch())
8037 return MCTargetAsmParser::Match_Success;
8038 break;
8039 }
8040 // 'CoprocOption' class
8041 case MCK_CoprocOption: {
8042 DiagnosticPredicate DP(Operand.isCoprocOption());
8043 if (DP.isMatch())
8044 return MCTargetAsmParser::Match_Success;
8045 break;
8046 }
8047 // 'CoprocReg' class
8048 case MCK_CoprocReg: {
8049 DiagnosticPredicate DP(Operand.isCoprocReg());
8050 if (DP.isMatch())
8051 return MCTargetAsmParser::Match_Success;
8052 break;
8053 }
8054 // 'DPRRegList' class
8055 case MCK_DPRRegList: {
8056 DiagnosticPredicate DP(Operand.isDPRRegList());
8057 if (DP.isMatch())
8058 return MCTargetAsmParser::Match_Success;
8059 if (DP.isNearMatch())
8060 return ARMAsmParser::Match_DPR_RegList;
8061 break;
8062 }
8063 // 'FPDRegListWithVPR' class
8064 case MCK_FPDRegListWithVPR: {
8065 DiagnosticPredicate DP(Operand.isFPDRegListWithVPR());
8066 if (DP.isMatch())
8067 return MCTargetAsmParser::Match_Success;
8068 break;
8069 }
8070 // 'FPImm' class
8071 case MCK_FPImm: {
8072 DiagnosticPredicate DP(Operand.isFPImm());
8073 if (DP.isMatch())
8074 return MCTargetAsmParser::Match_Success;
8075 break;
8076 }
8077 // 'FPSRegListWithVPR' class
8078 case MCK_FPSRegListWithVPR: {
8079 DiagnosticPredicate DP(Operand.isFPSRegListWithVPR());
8080 if (DP.isMatch())
8081 return MCTargetAsmParser::Match_Success;
8082 break;
8083 }
8084 // 'Imm0_15' class
8085 case MCK_Imm0_15: {
8086 DiagnosticPredicate DP(Operand.isImmediate<0,15>());
8087 if (DP.isMatch())
8088 return MCTargetAsmParser::Match_Success;
8089 if (DP.isNearMatch())
8090 return ARMAsmParser::Match_Imm0_15;
8091 break;
8092 }
8093 // 'Imm0_1' class
8094 case MCK_Imm0_1: {
8095 DiagnosticPredicate DP(Operand.isImmediate<0,1>());
8096 if (DP.isMatch())
8097 return MCTargetAsmParser::Match_Success;
8098 if (DP.isNearMatch())
8099 return ARMAsmParser::Match_Imm0_1;
8100 break;
8101 }
8102 // 'Imm0_239' class
8103 case MCK_Imm0_239: {
8104 DiagnosticPredicate DP(Operand.isImmediate<0,239>());
8105 if (DP.isMatch())
8106 return MCTargetAsmParser::Match_Success;
8107 if (DP.isNearMatch())
8108 return ARMAsmParser::Match_Imm0_239;
8109 break;
8110 }
8111 // 'Imm0_255' class
8112 case MCK_Imm0_255: {
8113 DiagnosticPredicate DP(Operand.isImmediate<0,255>());
8114 if (DP.isMatch())
8115 return MCTargetAsmParser::Match_Success;
8116 if (DP.isNearMatch())
8117 return ARMAsmParser::Match_Imm0_255;
8118 break;
8119 }
8120 // 'Imm0_255Expr' class
8121 case MCK_Imm0_255Expr: {
8122 DiagnosticPredicate DP(Operand.isImm0_255Expr());
8123 if (DP.isMatch())
8124 return MCTargetAsmParser::Match_Success;
8125 if (DP.isNearMatch())
8126 return ARMAsmParser::Match_Imm0_255Expr;
8127 break;
8128 }
8129 // 'Imm0_31' class
8130 case MCK_Imm0_31: {
8131 DiagnosticPredicate DP(Operand.isImmediate<0,31>());
8132 if (DP.isMatch())
8133 return MCTargetAsmParser::Match_Success;
8134 if (DP.isNearMatch())
8135 return ARMAsmParser::Match_Imm0_31;
8136 break;
8137 }
8138 // 'Imm0_32' class
8139 case MCK_Imm0_32: {
8140 DiagnosticPredicate DP(Operand.isImmediate<0,32>());
8141 if (DP.isMatch())
8142 return MCTargetAsmParser::Match_Success;
8143 if (DP.isNearMatch())
8144 return ARMAsmParser::Match_Imm0_32;
8145 break;
8146 }
8147 // 'Imm0_3' class
8148 case MCK_Imm0_3: {
8149 DiagnosticPredicate DP(Operand.isImmediate<0,3>());
8150 if (DP.isMatch())
8151 return MCTargetAsmParser::Match_Success;
8152 if (DP.isNearMatch())
8153 return ARMAsmParser::Match_Imm0_3;
8154 break;
8155 }
8156 // 'Imm0_63' class
8157 case MCK_Imm0_63: {
8158 DiagnosticPredicate DP(Operand.isImmediate<0,63>());
8159 if (DP.isMatch())
8160 return MCTargetAsmParser::Match_Success;
8161 if (DP.isNearMatch())
8162 return ARMAsmParser::Match_Imm0_63;
8163 break;
8164 }
8165 // 'Imm0_65535' class
8166 case MCK_Imm0_65535: {
8167 DiagnosticPredicate DP(Operand.isImmediate<0,65535>());
8168 if (DP.isMatch())
8169 return MCTargetAsmParser::Match_Success;
8170 if (DP.isNearMatch())
8171 return ARMAsmParser::Match_Imm0_65535;
8172 break;
8173 }
8174 // 'Imm0_65535Expr' class
8175 case MCK_Imm0_65535Expr: {
8176 DiagnosticPredicate DP(Operand.isImm0_65535Expr());
8177 if (DP.isMatch())
8178 return MCTargetAsmParser::Match_Success;
8179 if (DP.isNearMatch())
8180 return ARMAsmParser::Match_Imm0_65535Expr;
8181 break;
8182 }
8183 // 'Imm0_7' class
8184 case MCK_Imm0_7: {
8185 DiagnosticPredicate DP(Operand.isImmediate<0,7>());
8186 if (DP.isMatch())
8187 return MCTargetAsmParser::Match_Success;
8188 if (DP.isNearMatch())
8189 return ARMAsmParser::Match_Imm0_7;
8190 break;
8191 }
8192 // 'Imm16' class
8193 case MCK_Imm16: {
8194 DiagnosticPredicate DP(Operand.isImmediate<16,16>());
8195 if (DP.isMatch())
8196 return MCTargetAsmParser::Match_Success;
8197 if (DP.isNearMatch())
8198 return ARMAsmParser::Match_Imm16;
8199 break;
8200 }
8201 // 'Imm1_15' class
8202 case MCK_Imm1_15: {
8203 DiagnosticPredicate DP(Operand.isImmediate<1,15>());
8204 if (DP.isMatch())
8205 return MCTargetAsmParser::Match_Success;
8206 if (DP.isNearMatch())
8207 return ARMAsmParser::Match_Imm1_15;
8208 break;
8209 }
8210 // 'Imm1_16' class
8211 case MCK_Imm1_16: {
8212 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
8213 if (DP.isMatch())
8214 return MCTargetAsmParser::Match_Success;
8215 if (DP.isNearMatch())
8216 return ARMAsmParser::Match_ImmRange1_16;
8217 break;
8218 }
8219 // 'Imm1_31' class
8220 case MCK_Imm1_31: {
8221 DiagnosticPredicate DP(Operand.isImmediate<1,31>());
8222 if (DP.isMatch())
8223 return MCTargetAsmParser::Match_Success;
8224 if (DP.isNearMatch())
8225 return ARMAsmParser::Match_Imm1_31;
8226 break;
8227 }
8228 // 'Imm1_32' class
8229 case MCK_Imm1_32: {
8230 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8231 if (DP.isMatch())
8232 return MCTargetAsmParser::Match_Success;
8233 if (DP.isNearMatch())
8234 return ARMAsmParser::Match_ImmRange1_32;
8235 break;
8236 }
8237 // 'Imm1_7' class
8238 case MCK_Imm1_7: {
8239 DiagnosticPredicate DP(Operand.isImmediate<1,7>());
8240 if (DP.isMatch())
8241 return MCTargetAsmParser::Match_Success;
8242 if (DP.isNearMatch())
8243 return ARMAsmParser::Match_Imm1_7;
8244 break;
8245 }
8246 // 'Imm24bit' class
8247 case MCK_Imm24bit: {
8248 DiagnosticPredicate DP(Operand.isImmediate<0,16777215>());
8249 if (DP.isMatch())
8250 return MCTargetAsmParser::Match_Success;
8251 if (DP.isNearMatch())
8252 return ARMAsmParser::Match_Imm24bit;
8253 break;
8254 }
8255 // 'Imm256_65535Expr' class
8256 case MCK_Imm256_65535Expr: {
8257 DiagnosticPredicate DP(Operand.isImmediate<256,65535>());
8258 if (DP.isMatch())
8259 return MCTargetAsmParser::Match_Success;
8260 if (DP.isNearMatch())
8261 return ARMAsmParser::Match_Imm256_65535Expr;
8262 break;
8263 }
8264 // 'Imm32' class
8265 case MCK_Imm32: {
8266 DiagnosticPredicate DP(Operand.isImmediate<32,32>());
8267 if (DP.isMatch())
8268 return MCTargetAsmParser::Match_Success;
8269 if (DP.isNearMatch())
8270 return ARMAsmParser::Match_Imm32;
8271 break;
8272 }
8273 // 'Imm8' class
8274 case MCK_Imm8: {
8275 DiagnosticPredicate DP(Operand.isImmediate<8,8>());
8276 if (DP.isMatch())
8277 return MCTargetAsmParser::Match_Success;
8278 if (DP.isNearMatch())
8279 return ARMAsmParser::Match_Imm8;
8280 break;
8281 }
8282 // 'Imm8_255' class
8283 case MCK_Imm8_255: {
8284 DiagnosticPredicate DP(Operand.isImmediate<8,255>());
8285 if (DP.isMatch())
8286 return MCTargetAsmParser::Match_Success;
8287 if (DP.isNearMatch())
8288 return ARMAsmParser::Match_Imm8_255;
8289 break;
8290 }
8291 // 'Imm' class
8292 case MCK_Imm: {
8293 DiagnosticPredicate DP(Operand.isImm());
8294 if (DP.isMatch())
8295 return MCTargetAsmParser::Match_Success;
8296 break;
8297 }
8298 // 'InstSyncBarrierOpt' class
8299 case MCK_InstSyncBarrierOpt: {
8300 DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt());
8301 if (DP.isMatch())
8302 return MCTargetAsmParser::Match_Success;
8303 break;
8304 }
8305 // 'MSRMask' class
8306 case MCK_MSRMask: {
8307 DiagnosticPredicate DP(Operand.isMSRMask());
8308 if (DP.isMatch())
8309 return MCTargetAsmParser::Match_Success;
8310 break;
8311 }
8312 // 'MVEShiftImm1_15' class
8313 case MCK_MVEShiftImm1_15: {
8314 DiagnosticPredicate DP(Operand.isImmediate<1,15>());
8315 if (DP.isMatch())
8316 return MCTargetAsmParser::Match_Success;
8317 if (DP.isNearMatch())
8318 return ARMAsmParser::Match_MVEShiftImm1_15;
8319 break;
8320 }
8321 // 'MVEShiftImm1_7' class
8322 case MCK_MVEShiftImm1_7: {
8323 DiagnosticPredicate DP(Operand.isImmediate<1,7>());
8324 if (DP.isMatch())
8325 return MCTargetAsmParser::Match_Success;
8326 if (DP.isNearMatch())
8327 return ARMAsmParser::Match_MVEShiftImm1_7;
8328 break;
8329 }
8330 // 'VIDUP_imm' class
8331 case MCK_VIDUP_imm: {
8332 DiagnosticPredicate DP(Operand.isPowerTwoInRange<1,8>());
8333 if (DP.isMatch())
8334 return MCTargetAsmParser::Match_Success;
8335 if (DP.isNearMatch())
8336 return ARMAsmParser::Match_VIDUP_imm;
8337 break;
8338 }
8339 // 'MemBarrierOpt' class
8340 case MCK_MemBarrierOpt: {
8341 DiagnosticPredicate DP(Operand.isMemBarrierOpt());
8342 if (DP.isMatch())
8343 return MCTargetAsmParser::Match_Success;
8344 break;
8345 }
8346 // 'MemImm0_1020s4Offset' class
8347 case MCK_MemImm0_1020s4Offset: {
8348 DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset());
8349 if (DP.isMatch())
8350 return MCTargetAsmParser::Match_Success;
8351 break;
8352 }
8353 // 'MemImm12Offset' class
8354 case MCK_MemImm12Offset: {
8355 DiagnosticPredicate DP(Operand.isMemImm12Offset());
8356 if (DP.isMatch())
8357 return MCTargetAsmParser::Match_Success;
8358 break;
8359 }
8360 // 'MemImm7Shift0Offset' class
8361 case MCK_MemImm7Shift0Offset: {
8362 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>());
8363 if (DP.isMatch())
8364 return MCTargetAsmParser::Match_Success;
8365 break;
8366 }
8367 // 'MemImm7Shift0OffsetWB' class
8368 case MCK_MemImm7Shift0OffsetWB: {
8369 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>());
8370 if (DP.isMatch())
8371 return MCTargetAsmParser::Match_Success;
8372 break;
8373 }
8374 // 'MemImm7Shift1Offset' class
8375 case MCK_MemImm7Shift1Offset: {
8376 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>());
8377 if (DP.isMatch())
8378 return MCTargetAsmParser::Match_Success;
8379 break;
8380 }
8381 // 'MemImm7Shift1OffsetWB' class
8382 case MCK_MemImm7Shift1OffsetWB: {
8383 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>());
8384 if (DP.isMatch())
8385 return MCTargetAsmParser::Match_Success;
8386 break;
8387 }
8388 // 'MemImm7Shift2Offset' class
8389 case MCK_MemImm7Shift2Offset: {
8390 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::GPRnopcRegClassID>());
8391 if (DP.isMatch())
8392 return MCTargetAsmParser::Match_Success;
8393 break;
8394 }
8395 // 'MemImm7Shift2OffsetWB' class
8396 case MCK_MemImm7Shift2OffsetWB: {
8397 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::rGPRRegClassID>());
8398 if (DP.isMatch())
8399 return MCTargetAsmParser::Match_Success;
8400 break;
8401 }
8402 // 'MemImm7s4Offset' class
8403 case MCK_MemImm7s4Offset: {
8404 DiagnosticPredicate DP(Operand.isMemImm7s4Offset());
8405 if (DP.isMatch())
8406 return MCTargetAsmParser::Match_Success;
8407 break;
8408 }
8409 // 'MemImm8Offset' class
8410 case MCK_MemImm8Offset: {
8411 DiagnosticPredicate DP(Operand.isMemImm8Offset());
8412 if (DP.isMatch())
8413 return MCTargetAsmParser::Match_Success;
8414 break;
8415 }
8416 // 'MemImm8s4Offset' class
8417 case MCK_MemImm8s4Offset: {
8418 DiagnosticPredicate DP(Operand.isMemImm8s4Offset());
8419 if (DP.isMatch())
8420 return MCTargetAsmParser::Match_Success;
8421 break;
8422 }
8423 // 'MemNegImm8Offset' class
8424 case MCK_MemNegImm8Offset: {
8425 DiagnosticPredicate DP(Operand.isMemNegImm8Offset());
8426 if (DP.isMatch())
8427 return MCTargetAsmParser::Match_Success;
8428 break;
8429 }
8430 // 'MemNoOffset' class
8431 case MCK_MemNoOffset: {
8432 DiagnosticPredicate DP(Operand.isMemNoOffset());
8433 if (DP.isMatch())
8434 return MCTargetAsmParser::Match_Success;
8435 break;
8436 }
8437 // 'MemNoOffsetT2' class
8438 case MCK_MemNoOffsetT2: {
8439 DiagnosticPredicate DP(Operand.isMemNoOffsetT2());
8440 if (DP.isMatch())
8441 return MCTargetAsmParser::Match_Success;
8442 break;
8443 }
8444 // 'MemNoOffsetT2NoSp' class
8445 case MCK_MemNoOffsetT2NoSp: {
8446 DiagnosticPredicate DP(Operand.isMemNoOffsetT2NoSp());
8447 if (DP.isMatch())
8448 return MCTargetAsmParser::Match_Success;
8449 break;
8450 }
8451 // 'MemNoOffsetT' class
8452 case MCK_MemNoOffsetT: {
8453 DiagnosticPredicate DP(Operand.isMemNoOffsetT());
8454 if (DP.isMatch())
8455 return MCTargetAsmParser::Match_Success;
8456 break;
8457 }
8458 // 'MemPosImm8Offset' class
8459 case MCK_MemPosImm8Offset: {
8460 DiagnosticPredicate DP(Operand.isMemPosImm8Offset());
8461 if (DP.isMatch())
8462 return MCTargetAsmParser::Match_Success;
8463 break;
8464 }
8465 // 'MemRegOffset' class
8466 case MCK_MemRegOffset: {
8467 DiagnosticPredicate DP(Operand.isMemRegOffset());
8468 if (DP.isMatch())
8469 return MCTargetAsmParser::Match_Success;
8470 break;
8471 }
8472 // 'MemRegQS2Offset' class
8473 case MCK_MemRegQS2Offset: {
8474 DiagnosticPredicate DP(Operand.isMemRegQOffset<2>());
8475 if (DP.isMatch())
8476 return MCTargetAsmParser::Match_Success;
8477 break;
8478 }
8479 // 'MemRegQS3Offset' class
8480 case MCK_MemRegQS3Offset: {
8481 DiagnosticPredicate DP(Operand.isMemRegQOffset<3>());
8482 if (DP.isMatch())
8483 return MCTargetAsmParser::Match_Success;
8484 break;
8485 }
8486 // 'MemRegRQS0Offset' class
8487 case MCK_MemRegRQS0Offset: {
8488 DiagnosticPredicate DP(Operand.isMemRegRQOffset<0>());
8489 if (DP.isMatch())
8490 return MCTargetAsmParser::Match_Success;
8491 break;
8492 }
8493 // 'MemRegRQS1Offset' class
8494 case MCK_MemRegRQS1Offset: {
8495 DiagnosticPredicate DP(Operand.isMemRegRQOffset<1>());
8496 if (DP.isMatch())
8497 return MCTargetAsmParser::Match_Success;
8498 break;
8499 }
8500 // 'MemRegRQS2Offset' class
8501 case MCK_MemRegRQS2Offset: {
8502 DiagnosticPredicate DP(Operand.isMemRegRQOffset<2>());
8503 if (DP.isMatch())
8504 return MCTargetAsmParser::Match_Success;
8505 break;
8506 }
8507 // 'MemRegRQS3Offset' class
8508 case MCK_MemRegRQS3Offset: {
8509 DiagnosticPredicate DP(Operand.isMemRegRQOffset<3>());
8510 if (DP.isMatch())
8511 return MCTargetAsmParser::Match_Success;
8512 break;
8513 }
8514 // 'ModImm' class
8515 case MCK_ModImm: {
8516 DiagnosticPredicate DP(Operand.isModImm());
8517 if (DP.isMatch())
8518 return MCTargetAsmParser::Match_Success;
8519 break;
8520 }
8521 // 'ModImmNeg' class
8522 case MCK_ModImmNeg: {
8523 DiagnosticPredicate DP(Operand.isModImmNeg());
8524 if (DP.isMatch())
8525 return MCTargetAsmParser::Match_Success;
8526 break;
8527 }
8528 // 'ModImmNot' class
8529 case MCK_ModImmNot: {
8530 DiagnosticPredicate DP(Operand.isModImmNot());
8531 if (DP.isMatch())
8532 return MCTargetAsmParser::Match_Success;
8533 break;
8534 }
8535 // 'MveSaturate' class
8536 case MCK_MveSaturate: {
8537 DiagnosticPredicate DP(Operand.isMveSaturateOp());
8538 if (DP.isMatch())
8539 return MCTargetAsmParser::Match_Success;
8540 if (DP.isNearMatch())
8541 return ARMAsmParser::Match_MveSaturate;
8542 break;
8543 }
8544 // 'PKHASRImm' class
8545 case MCK_PKHASRImm: {
8546 DiagnosticPredicate DP(Operand.isPKHASRImm());
8547 if (DP.isMatch())
8548 return MCTargetAsmParser::Match_Success;
8549 break;
8550 }
8551 // 'PKHLSLImm' class
8552 case MCK_PKHLSLImm: {
8553 DiagnosticPredicate DP(Operand.isImmediate<0,31>());
8554 if (DP.isMatch())
8555 return MCTargetAsmParser::Match_Success;
8556 if (DP.isNearMatch())
8557 return ARMAsmParser::Match_PKHLSLImm;
8558 break;
8559 }
8560 // 'PostIdxImm8' class
8561 case MCK_PostIdxImm8: {
8562 DiagnosticPredicate DP(Operand.isPostIdxImm8());
8563 if (DP.isMatch())
8564 return MCTargetAsmParser::Match_Success;
8565 break;
8566 }
8567 // 'PostIdxImm8s4' class
8568 case MCK_PostIdxImm8s4: {
8569 DiagnosticPredicate DP(Operand.isPostIdxImm8s4());
8570 if (DP.isMatch())
8571 return MCTargetAsmParser::Match_Success;
8572 break;
8573 }
8574 // 'PostIdxReg' class
8575 case MCK_PostIdxReg: {
8576 DiagnosticPredicate DP(Operand.isPostIdxReg());
8577 if (DP.isMatch())
8578 return MCTargetAsmParser::Match_Success;
8579 break;
8580 }
8581 // 'PostIdxRegShifted' class
8582 case MCK_PostIdxRegShifted: {
8583 DiagnosticPredicate DP(Operand.isPostIdxRegShifted());
8584 if (DP.isMatch())
8585 return MCTargetAsmParser::Match_Success;
8586 break;
8587 }
8588 // 'ProcIFlags' class
8589 case MCK_ProcIFlags: {
8590 DiagnosticPredicate DP(Operand.isProcIFlags());
8591 if (DP.isMatch())
8592 return MCTargetAsmParser::Match_Success;
8593 break;
8594 }
8595 // 'RegList' class
8596 case MCK_RegList: {
8597 DiagnosticPredicate DP(Operand.isRegList());
8598 if (DP.isMatch())
8599 return MCTargetAsmParser::Match_Success;
8600 break;
8601 }
8602 // 'RegListWithAPSR' class
8603 case MCK_RegListWithAPSR: {
8604 DiagnosticPredicate DP(Operand.isRegListWithAPSR());
8605 if (DP.isMatch())
8606 return MCTargetAsmParser::Match_Success;
8607 break;
8608 }
8609 // 'RotImm' class
8610 case MCK_RotImm: {
8611 DiagnosticPredicate DP(Operand.isRotImm());
8612 if (DP.isMatch())
8613 return MCTargetAsmParser::Match_Success;
8614 break;
8615 }
8616 // 'SPRRegList' class
8617 case MCK_SPRRegList: {
8618 DiagnosticPredicate DP(Operand.isSPRRegList());
8619 if (DP.isMatch())
8620 return MCTargetAsmParser::Match_Success;
8621 if (DP.isNearMatch())
8622 return ARMAsmParser::Match_SPRRegList;
8623 break;
8624 }
8625 // 'SetEndImm' class
8626 case MCK_SetEndImm: {
8627 DiagnosticPredicate DP(Operand.isImmediate<0,1>());
8628 if (DP.isMatch())
8629 return MCTargetAsmParser::Match_Success;
8630 if (DP.isNearMatch())
8631 return ARMAsmParser::Match_SetEndImm;
8632 break;
8633 }
8634 // 'RegShiftedImm' class
8635 case MCK_RegShiftedImm: {
8636 DiagnosticPredicate DP(Operand.isRegShiftedImm());
8637 if (DP.isMatch())
8638 return MCTargetAsmParser::Match_Success;
8639 break;
8640 }
8641 // 'RegShiftedReg' class
8642 case MCK_RegShiftedReg: {
8643 DiagnosticPredicate DP(Operand.isRegShiftedReg());
8644 if (DP.isMatch())
8645 return MCTargetAsmParser::Match_Success;
8646 break;
8647 }
8648 // 'ShifterImm' class
8649 case MCK_ShifterImm: {
8650 DiagnosticPredicate DP(Operand.isShifterImm());
8651 if (DP.isMatch())
8652 return MCTargetAsmParser::Match_Success;
8653 break;
8654 }
8655 // 'ThumbBranchTarget' class
8656 case MCK_ThumbBranchTarget: {
8657 DiagnosticPredicate DP(Operand.isThumbBranchTarget());
8658 if (DP.isMatch())
8659 return MCTargetAsmParser::Match_Success;
8660 break;
8661 }
8662 // 'ThumbMemPC' class
8663 case MCK_ThumbMemPC: {
8664 DiagnosticPredicate DP(Operand.isThumbMemPC());
8665 if (DP.isMatch())
8666 return MCTargetAsmParser::Match_Success;
8667 break;
8668 }
8669 // 'ThumbModImmNeg1_7' class
8670 case MCK_ThumbModImmNeg1_7: {
8671 DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7());
8672 if (DP.isMatch())
8673 return MCTargetAsmParser::Match_Success;
8674 break;
8675 }
8676 // 'ThumbModImmNeg8_255' class
8677 case MCK_ThumbModImmNeg8_255: {
8678 DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255());
8679 if (DP.isMatch())
8680 return MCTargetAsmParser::Match_Success;
8681 break;
8682 }
8683 // 'ImmThumbSR' class
8684 case MCK_ImmThumbSR: {
8685 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8686 if (DP.isMatch())
8687 return MCTargetAsmParser::Match_Success;
8688 if (DP.isNearMatch())
8689 return ARMAsmParser::Match_ImmThumbSR;
8690 break;
8691 }
8692 // 'TraceSyncBarrierOpt' class
8693 case MCK_TraceSyncBarrierOpt: {
8694 DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt());
8695 if (DP.isMatch())
8696 return MCTargetAsmParser::Match_Success;
8697 break;
8698 }
8699 // 'UnsignedOffset_b8s2' class
8700 case MCK_UnsignedOffset_b8s2: {
8701 DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>());
8702 if (DP.isMatch())
8703 return MCTargetAsmParser::Match_Success;
8704 break;
8705 }
8706 // 'VPTPredN' class
8707 case MCK_VPTPredN: {
8708 DiagnosticPredicate DP(Operand.isVPTPred());
8709 if (DP.isMatch())
8710 return MCTargetAsmParser::Match_Success;
8711 break;
8712 }
8713 // 'VPTPredR' class
8714 case MCK_VPTPredR: {
8715 DiagnosticPredicate DP(Operand.isVPTPred());
8716 if (DP.isMatch())
8717 return MCTargetAsmParser::Match_Success;
8718 break;
8719 }
8720 // 'VecListTwoMQ' class
8721 case MCK_VecListTwoMQ: {
8722 DiagnosticPredicate DP(Operand.isVecListTwoMQ());
8723 if (DP.isMatch())
8724 return MCTargetAsmParser::Match_Success;
8725 if (DP.isNearMatch())
8726 return ARMAsmParser::Match_VecListTwoMQ;
8727 break;
8728 }
8729 // 'VecListFourMQ' class
8730 case MCK_VecListFourMQ: {
8731 DiagnosticPredicate DP(Operand.isVecListFourMQ());
8732 if (DP.isMatch())
8733 return MCTargetAsmParser::Match_Success;
8734 if (DP.isNearMatch())
8735 return ARMAsmParser::Match_VecListFourMQ;
8736 break;
8737 }
8738 // 'VecListDPairAllLanes' class
8739 case MCK_VecListDPairAllLanes: {
8740 DiagnosticPredicate DP(Operand.isVecListDPairAllLanes());
8741 if (DP.isMatch())
8742 return MCTargetAsmParser::Match_Success;
8743 break;
8744 }
8745 // 'VecListDPair' class
8746 case MCK_VecListDPair: {
8747 DiagnosticPredicate DP(Operand.isVecListDPair());
8748 if (DP.isMatch())
8749 return MCTargetAsmParser::Match_Success;
8750 break;
8751 }
8752 // 'VecListDPairSpacedAllLanes' class
8753 case MCK_VecListDPairSpacedAllLanes: {
8754 DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes());
8755 if (DP.isMatch())
8756 return MCTargetAsmParser::Match_Success;
8757 break;
8758 }
8759 // 'VecListDPairSpaced' class
8760 case MCK_VecListDPairSpaced: {
8761 DiagnosticPredicate DP(Operand.isVecListDPairSpaced());
8762 if (DP.isMatch())
8763 return MCTargetAsmParser::Match_Success;
8764 break;
8765 }
8766 // 'VecListFourDAllLanes' class
8767 case MCK_VecListFourDAllLanes: {
8768 DiagnosticPredicate DP(Operand.isVecListFourDAllLanes());
8769 if (DP.isMatch())
8770 return MCTargetAsmParser::Match_Success;
8771 break;
8772 }
8773 // 'VecListFourD' class
8774 case MCK_VecListFourD: {
8775 DiagnosticPredicate DP(Operand.isVecListFourD());
8776 if (DP.isMatch())
8777 return MCTargetAsmParser::Match_Success;
8778 break;
8779 }
8780 // 'VecListFourDByteIndexed' class
8781 case MCK_VecListFourDByteIndexed: {
8782 DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed());
8783 if (DP.isMatch())
8784 return MCTargetAsmParser::Match_Success;
8785 break;
8786 }
8787 // 'VecListFourDHWordIndexed' class
8788 case MCK_VecListFourDHWordIndexed: {
8789 DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed());
8790 if (DP.isMatch())
8791 return MCTargetAsmParser::Match_Success;
8792 break;
8793 }
8794 // 'VecListFourDWordIndexed' class
8795 case MCK_VecListFourDWordIndexed: {
8796 DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed());
8797 if (DP.isMatch())
8798 return MCTargetAsmParser::Match_Success;
8799 break;
8800 }
8801 // 'VecListFourQAllLanes' class
8802 case MCK_VecListFourQAllLanes: {
8803 DiagnosticPredicate DP(Operand.isVecListFourQAllLanes());
8804 if (DP.isMatch())
8805 return MCTargetAsmParser::Match_Success;
8806 break;
8807 }
8808 // 'VecListFourQ' class
8809 case MCK_VecListFourQ: {
8810 DiagnosticPredicate DP(Operand.isVecListFourQ());
8811 if (DP.isMatch())
8812 return MCTargetAsmParser::Match_Success;
8813 break;
8814 }
8815 // 'VecListFourQHWordIndexed' class
8816 case MCK_VecListFourQHWordIndexed: {
8817 DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed());
8818 if (DP.isMatch())
8819 return MCTargetAsmParser::Match_Success;
8820 break;
8821 }
8822 // 'VecListFourQWordIndexed' class
8823 case MCK_VecListFourQWordIndexed: {
8824 DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed());
8825 if (DP.isMatch())
8826 return MCTargetAsmParser::Match_Success;
8827 break;
8828 }
8829 // 'VecListOneDAllLanes' class
8830 case MCK_VecListOneDAllLanes: {
8831 DiagnosticPredicate DP(Operand.isVecListOneDAllLanes());
8832 if (DP.isMatch())
8833 return MCTargetAsmParser::Match_Success;
8834 break;
8835 }
8836 // 'VecListOneD' class
8837 case MCK_VecListOneD: {
8838 DiagnosticPredicate DP(Operand.isVecListOneD());
8839 if (DP.isMatch())
8840 return MCTargetAsmParser::Match_Success;
8841 break;
8842 }
8843 // 'VecListOneDByteIndexed' class
8844 case MCK_VecListOneDByteIndexed: {
8845 DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed());
8846 if (DP.isMatch())
8847 return MCTargetAsmParser::Match_Success;
8848 break;
8849 }
8850 // 'VecListOneDHWordIndexed' class
8851 case MCK_VecListOneDHWordIndexed: {
8852 DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed());
8853 if (DP.isMatch())
8854 return MCTargetAsmParser::Match_Success;
8855 break;
8856 }
8857 // 'VecListOneDWordIndexed' class
8858 case MCK_VecListOneDWordIndexed: {
8859 DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed());
8860 if (DP.isMatch())
8861 return MCTargetAsmParser::Match_Success;
8862 break;
8863 }
8864 // 'VecListThreeDAllLanes' class
8865 case MCK_VecListThreeDAllLanes: {
8866 DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes());
8867 if (DP.isMatch())
8868 return MCTargetAsmParser::Match_Success;
8869 break;
8870 }
8871 // 'VecListThreeD' class
8872 case MCK_VecListThreeD: {
8873 DiagnosticPredicate DP(Operand.isVecListThreeD());
8874 if (DP.isMatch())
8875 return MCTargetAsmParser::Match_Success;
8876 break;
8877 }
8878 // 'VecListThreeDByteIndexed' class
8879 case MCK_VecListThreeDByteIndexed: {
8880 DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed());
8881 if (DP.isMatch())
8882 return MCTargetAsmParser::Match_Success;
8883 break;
8884 }
8885 // 'VecListThreeDHWordIndexed' class
8886 case MCK_VecListThreeDHWordIndexed: {
8887 DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed());
8888 if (DP.isMatch())
8889 return MCTargetAsmParser::Match_Success;
8890 break;
8891 }
8892 // 'VecListThreeDWordIndexed' class
8893 case MCK_VecListThreeDWordIndexed: {
8894 DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed());
8895 if (DP.isMatch())
8896 return MCTargetAsmParser::Match_Success;
8897 break;
8898 }
8899 // 'VecListThreeQAllLanes' class
8900 case MCK_VecListThreeQAllLanes: {
8901 DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes());
8902 if (DP.isMatch())
8903 return MCTargetAsmParser::Match_Success;
8904 break;
8905 }
8906 // 'VecListThreeQ' class
8907 case MCK_VecListThreeQ: {
8908 DiagnosticPredicate DP(Operand.isVecListThreeQ());
8909 if (DP.isMatch())
8910 return MCTargetAsmParser::Match_Success;
8911 break;
8912 }
8913 // 'VecListThreeQHWordIndexed' class
8914 case MCK_VecListThreeQHWordIndexed: {
8915 DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed());
8916 if (DP.isMatch())
8917 return MCTargetAsmParser::Match_Success;
8918 break;
8919 }
8920 // 'VecListThreeQWordIndexed' class
8921 case MCK_VecListThreeQWordIndexed: {
8922 DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed());
8923 if (DP.isMatch())
8924 return MCTargetAsmParser::Match_Success;
8925 break;
8926 }
8927 // 'VecListTwoDByteIndexed' class
8928 case MCK_VecListTwoDByteIndexed: {
8929 DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed());
8930 if (DP.isMatch())
8931 return MCTargetAsmParser::Match_Success;
8932 break;
8933 }
8934 // 'VecListTwoDHWordIndexed' class
8935 case MCK_VecListTwoDHWordIndexed: {
8936 DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed());
8937 if (DP.isMatch())
8938 return MCTargetAsmParser::Match_Success;
8939 break;
8940 }
8941 // 'VecListTwoDWordIndexed' class
8942 case MCK_VecListTwoDWordIndexed: {
8943 DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed());
8944 if (DP.isMatch())
8945 return MCTargetAsmParser::Match_Success;
8946 break;
8947 }
8948 // 'VecListTwoQHWordIndexed' class
8949 case MCK_VecListTwoQHWordIndexed: {
8950 DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed());
8951 if (DP.isMatch())
8952 return MCTargetAsmParser::Match_Success;
8953 break;
8954 }
8955 // 'VecListTwoQWordIndexed' class
8956 case MCK_VecListTwoQWordIndexed: {
8957 DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed());
8958 if (DP.isMatch())
8959 return MCTargetAsmParser::Match_Success;
8960 break;
8961 }
8962 // 'VectorIndex16' class
8963 case MCK_VectorIndex16: {
8964 DiagnosticPredicate DP(Operand.isVectorIndex16());
8965 if (DP.isMatch())
8966 return MCTargetAsmParser::Match_Success;
8967 break;
8968 }
8969 // 'VectorIndex32' class
8970 case MCK_VectorIndex32: {
8971 DiagnosticPredicate DP(Operand.isVectorIndex32());
8972 if (DP.isMatch())
8973 return MCTargetAsmParser::Match_Success;
8974 break;
8975 }
8976 // 'VectorIndex64' class
8977 case MCK_VectorIndex64: {
8978 DiagnosticPredicate DP(Operand.isVectorIndex64());
8979 if (DP.isMatch())
8980 return MCTargetAsmParser::Match_Success;
8981 break;
8982 }
8983 // 'VectorIndex8' class
8984 case MCK_VectorIndex8: {
8985 DiagnosticPredicate DP(Operand.isVectorIndex8());
8986 if (DP.isMatch())
8987 return MCTargetAsmParser::Match_Success;
8988 break;
8989 }
8990 // 'MemTBB' class
8991 case MCK_MemTBB: {
8992 DiagnosticPredicate DP(Operand.isMemTBB());
8993 if (DP.isMatch())
8994 return MCTargetAsmParser::Match_Success;
8995 break;
8996 }
8997 // 'MemTBH' class
8998 case MCK_MemTBH: {
8999 DiagnosticPredicate DP(Operand.isMemTBH());
9000 if (DP.isMatch())
9001 return MCTargetAsmParser::Match_Success;
9002 break;
9003 }
9004 // 'MVEVectorIndex4' class
9005 case MCK_MVEVectorIndex4: {
9006 DiagnosticPredicate DP(Operand.isVectorIndexInRange<4>());
9007 if (DP.isMatch())
9008 return MCTargetAsmParser::Match_Success;
9009 break;
9010 }
9011 // 'MVEVectorIndex8' class
9012 case MCK_MVEVectorIndex8: {
9013 DiagnosticPredicate DP(Operand.isVectorIndexInRange<8>());
9014 if (DP.isMatch())
9015 return MCTargetAsmParser::Match_Success;
9016 break;
9017 }
9018 // 'MVEVectorIndex16' class
9019 case MCK_MVEVectorIndex16: {
9020 DiagnosticPredicate DP(Operand.isVectorIndexInRange<16>());
9021 if (DP.isMatch())
9022 return MCTargetAsmParser::Match_Success;
9023 break;
9024 }
9025 // 'MVEVcvtImm32' class
9026 case MCK_MVEVcvtImm32: {
9027 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
9028 if (DP.isMatch())
9029 return MCTargetAsmParser::Match_Success;
9030 if (DP.isNearMatch())
9031 return ARMAsmParser::Match_MVEVcvtImm32;
9032 break;
9033 }
9034 // 'MVEVcvtImm16' class
9035 case MCK_MVEVcvtImm16: {
9036 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
9037 if (DP.isMatch())
9038 return MCTargetAsmParser::Match_Success;
9039 if (DP.isNearMatch())
9040 return ARMAsmParser::Match_MVEVcvtImm16;
9041 break;
9042 }
9043 // 'TMemImm7Shift2Offset' class
9044 case MCK_TMemImm7Shift2Offset: {
9045 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::tGPRRegClassID>());
9046 if (DP.isMatch())
9047 return MCTargetAsmParser::Match_Success;
9048 break;
9049 }
9050 // 'TMemImm7Shift0Offset' class
9051 case MCK_TMemImm7Shift0Offset: {
9052 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::tGPRRegClassID>());
9053 if (DP.isMatch())
9054 return MCTargetAsmParser::Match_Success;
9055 break;
9056 }
9057 // 'TMemImm7Shift1Offset' class
9058 case MCK_TMemImm7Shift1Offset: {
9059 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::tGPRRegClassID>());
9060 if (DP.isMatch())
9061 return MCTargetAsmParser::Match_Success;
9062 break;
9063 }
9064 // 'Imm3b' class
9065 case MCK_Imm3b: {
9066 DiagnosticPredicate DP(Operand.isImmediate<0,7>());
9067 if (DP.isMatch())
9068 return MCTargetAsmParser::Match_Success;
9069 if (DP.isNearMatch())
9070 return ARMAsmParser::Match_Imm3b;
9071 break;
9072 }
9073 // 'Imm4b' class
9074 case MCK_Imm4b: {
9075 DiagnosticPredicate DP(Operand.isImmediate<0,15>());
9076 if (DP.isMatch())
9077 return MCTargetAsmParser::Match_Success;
9078 if (DP.isNearMatch())
9079 return ARMAsmParser::Match_Imm4b;
9080 break;
9081 }
9082 // 'Imm6b' class
9083 case MCK_Imm6b: {
9084 DiagnosticPredicate DP(Operand.isImmediate<0,63>());
9085 if (DP.isMatch())
9086 return MCTargetAsmParser::Match_Success;
9087 if (DP.isNearMatch())
9088 return ARMAsmParser::Match_Imm6b;
9089 break;
9090 }
9091 // 'Imm7b' class
9092 case MCK_Imm7b: {
9093 DiagnosticPredicate DP(Operand.isImmediate<0,127>());
9094 if (DP.isMatch())
9095 return MCTargetAsmParser::Match_Success;
9096 if (DP.isNearMatch())
9097 return ARMAsmParser::Match_Imm7b;
9098 break;
9099 }
9100 // 'Imm9b' class
9101 case MCK_Imm9b: {
9102 DiagnosticPredicate DP(Operand.isImmediate<0,511>());
9103 if (DP.isMatch())
9104 return MCTargetAsmParser::Match_Success;
9105 if (DP.isNearMatch())
9106 return ARMAsmParser::Match_Imm9b;
9107 break;
9108 }
9109 // 'Imm11b' class
9110 case MCK_Imm11b: {
9111 DiagnosticPredicate DP(Operand.isImmediate<0,2047>());
9112 if (DP.isMatch())
9113 return MCTargetAsmParser::Match_Success;
9114 if (DP.isNearMatch())
9115 return ARMAsmParser::Match_Imm11b;
9116 break;
9117 }
9118 // 'Imm12b' class
9119 case MCK_Imm12b: {
9120 DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
9121 if (DP.isMatch())
9122 return MCTargetAsmParser::Match_Success;
9123 if (DP.isNearMatch())
9124 return ARMAsmParser::Match_Imm12b;
9125 break;
9126 }
9127 // 'Imm13b' class
9128 case MCK_Imm13b: {
9129 DiagnosticPredicate DP(Operand.isImmediate<0,8191>());
9130 if (DP.isMatch())
9131 return MCTargetAsmParser::Match_Success;
9132 if (DP.isNearMatch())
9133 return ARMAsmParser::Match_Imm13b;
9134 break;
9135 }
9136 // 'MVEPairVectorIndex0' class
9137 case MCK_MVEPairVectorIndex0: {
9138 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<0, 1>());
9139 if (DP.isMatch())
9140 return MCTargetAsmParser::Match_Success;
9141 break;
9142 }
9143 // 'MVEPairVectorIndex2' class
9144 case MCK_MVEPairVectorIndex2: {
9145 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<2, 3>());
9146 if (DP.isMatch())
9147 return MCTargetAsmParser::Match_Success;
9148 break;
9149 }
9150 // 'ComplexRotationEven' class
9151 case MCK_ComplexRotationEven: {
9152 DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>());
9153 if (DP.isMatch())
9154 return MCTargetAsmParser::Match_Success;
9155 if (DP.isNearMatch())
9156 return ARMAsmParser::Match_ComplexRotationEven;
9157 break;
9158 }
9159 // 'ComplexRotationOdd' class
9160 case MCK_ComplexRotationOdd: {
9161 DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>());
9162 if (DP.isMatch())
9163 return MCTargetAsmParser::Match_Success;
9164 if (DP.isNearMatch())
9165 return ARMAsmParser::Match_ComplexRotationOdd;
9166 break;
9167 }
9168 // 'NEONi16vmovi8Replicate' class
9169 case MCK_NEONi16vmovi8Replicate: {
9170 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>());
9171 if (DP.isMatch())
9172 return MCTargetAsmParser::Match_Success;
9173 break;
9174 }
9175 // 'NEONi16invi8Replicate' class
9176 case MCK_NEONi16invi8Replicate: {
9177 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>());
9178 if (DP.isMatch())
9179 return MCTargetAsmParser::Match_Success;
9180 break;
9181 }
9182 // 'NEONi32vmovi8Replicate' class
9183 case MCK_NEONi32vmovi8Replicate: {
9184 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>());
9185 if (DP.isMatch())
9186 return MCTargetAsmParser::Match_Success;
9187 break;
9188 }
9189 // 'NEONi32invi8Replicate' class
9190 case MCK_NEONi32invi8Replicate: {
9191 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>());
9192 if (DP.isMatch())
9193 return MCTargetAsmParser::Match_Success;
9194 break;
9195 }
9196 // 'NEONi64vmovi8Replicate' class
9197 case MCK_NEONi64vmovi8Replicate: {
9198 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>());
9199 if (DP.isMatch())
9200 return MCTargetAsmParser::Match_Success;
9201 break;
9202 }
9203 // 'NEONi64invi8Replicate' class
9204 case MCK_NEONi64invi8Replicate: {
9205 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>());
9206 if (DP.isMatch())
9207 return MCTargetAsmParser::Match_Success;
9208 break;
9209 }
9210 // 'NEONi32vmovi16Replicate' class
9211 case MCK_NEONi32vmovi16Replicate: {
9212 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>());
9213 if (DP.isMatch())
9214 return MCTargetAsmParser::Match_Success;
9215 break;
9216 }
9217 // 'NEONi64vmovi16Replicate' class
9218 case MCK_NEONi64vmovi16Replicate: {
9219 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>());
9220 if (DP.isMatch())
9221 return MCTargetAsmParser::Match_Success;
9222 break;
9223 }
9224 // 'NEONi64vmovi32Replicate' class
9225 case MCK_NEONi64vmovi32Replicate: {
9226 DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>());
9227 if (DP.isMatch())
9228 return MCTargetAsmParser::Match_Success;
9229 break;
9230 }
9231 // 'ConstPoolAsmImm' class
9232 case MCK_ConstPoolAsmImm: {
9233 DiagnosticPredicate DP(Operand.isConstPoolAsmImm());
9234 if (DP.isMatch())
9235 return MCTargetAsmParser::Match_Success;
9236 break;
9237 }
9238 // 'FBits16' class
9239 case MCK_FBits16: {
9240 DiagnosticPredicate DP(Operand.isFBits16());
9241 if (DP.isMatch())
9242 return MCTargetAsmParser::Match_Success;
9243 break;
9244 }
9245 // 'FBits32' class
9246 case MCK_FBits32: {
9247 DiagnosticPredicate DP(Operand.isFBits32());
9248 if (DP.isMatch())
9249 return MCTargetAsmParser::Match_Success;
9250 break;
9251 }
9252 // 'Imm0_4095' class
9253 case MCK_Imm0_4095: {
9254 DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
9255 if (DP.isMatch())
9256 return MCTargetAsmParser::Match_Success;
9257 if (DP.isNearMatch())
9258 return ARMAsmParser::Match_Imm0_4095;
9259 break;
9260 }
9261 // 'Imm0_4095Neg' class
9262 case MCK_Imm0_4095Neg: {
9263 DiagnosticPredicate DP(Operand.isImm0_4095Neg());
9264 if (DP.isMatch())
9265 return MCTargetAsmParser::Match_Success;
9266 break;
9267 }
9268 // 'ITMask' class
9269 case MCK_ITMask: {
9270 DiagnosticPredicate DP(Operand.isITMask());
9271 if (DP.isMatch())
9272 return MCTargetAsmParser::Match_Success;
9273 break;
9274 }
9275 // 'ITCondCode' class
9276 case MCK_ITCondCode: {
9277 DiagnosticPredicate DP(Operand.isITCondCode());
9278 if (DP.isMatch())
9279 return MCTargetAsmParser::Match_Success;
9280 break;
9281 }
9282 // 'LELabel' class
9283 case MCK_LELabel: {
9284 DiagnosticPredicate DP(Operand.isLEOffset());
9285 if (DP.isMatch())
9286 return MCTargetAsmParser::Match_Success;
9287 if (DP.isNearMatch())
9288 return ARMAsmParser::Match_LELabel;
9289 break;
9290 }
9291 // 'MVELongShift' class
9292 case MCK_MVELongShift: {
9293 DiagnosticPredicate DP(Operand.isMVELongShift());
9294 if (DP.isMatch())
9295 return MCTargetAsmParser::Match_Success;
9296 if (DP.isNearMatch())
9297 return ARMAsmParser::Match_MVELongShift;
9298 break;
9299 }
9300 // 'NEONi16splat' class
9301 case MCK_NEONi16splat: {
9302 DiagnosticPredicate DP(Operand.isNEONi16splat());
9303 if (DP.isMatch())
9304 return MCTargetAsmParser::Match_Success;
9305 break;
9306 }
9307 // 'NEONi32splat' class
9308 case MCK_NEONi32splat: {
9309 DiagnosticPredicate DP(Operand.isNEONi32splat());
9310 if (DP.isMatch())
9311 return MCTargetAsmParser::Match_Success;
9312 break;
9313 }
9314 // 'NEONi64splat' class
9315 case MCK_NEONi64splat: {
9316 DiagnosticPredicate DP(Operand.isNEONi64splat());
9317 if (DP.isMatch())
9318 return MCTargetAsmParser::Match_Success;
9319 break;
9320 }
9321 // 'NEONi8splat' class
9322 case MCK_NEONi8splat: {
9323 DiagnosticPredicate DP(Operand.isNEONi8splat());
9324 if (DP.isMatch())
9325 return MCTargetAsmParser::Match_Success;
9326 break;
9327 }
9328 // 'NEONi16splatNot' class
9329 case MCK_NEONi16splatNot: {
9330 DiagnosticPredicate DP(Operand.isNEONi16splatNot());
9331 if (DP.isMatch())
9332 return MCTargetAsmParser::Match_Success;
9333 break;
9334 }
9335 // 'NEONi32splatNot' class
9336 case MCK_NEONi32splatNot: {
9337 DiagnosticPredicate DP(Operand.isNEONi32splatNot());
9338 if (DP.isMatch())
9339 return MCTargetAsmParser::Match_Success;
9340 break;
9341 }
9342 // 'NEONi32vmov' class
9343 case MCK_NEONi32vmov: {
9344 DiagnosticPredicate DP(Operand.isNEONi32vmov());
9345 if (DP.isMatch())
9346 return MCTargetAsmParser::Match_Success;
9347 break;
9348 }
9349 // 'NEONi32vmovNeg' class
9350 case MCK_NEONi32vmovNeg: {
9351 DiagnosticPredicate DP(Operand.isNEONi32vmovNeg());
9352 if (DP.isMatch())
9353 return MCTargetAsmParser::Match_Success;
9354 break;
9355 }
9356 // 'CondCodeNoAL' class
9357 case MCK_CondCodeNoAL: {
9358 DiagnosticPredicate DP(Operand.isITCondCodeNoAL());
9359 if (DP.isMatch())
9360 return MCTargetAsmParser::Match_Success;
9361 break;
9362 }
9363 // 'CondCodeNoALInv' class
9364 case MCK_CondCodeNoALInv: {
9365 DiagnosticPredicate DP(Operand.isITCondCodeNoAL());
9366 if (DP.isMatch())
9367 return MCTargetAsmParser::Match_Success;
9368 break;
9369 }
9370 // 'CondCodeRestrictedFP' class
9371 case MCK_CondCodeRestrictedFP: {
9372 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedFP());
9373 if (DP.isMatch())
9374 return MCTargetAsmParser::Match_Success;
9375 if (DP.isNearMatch())
9376 return ARMAsmParser::Match_CondCodeRestrictedFP;
9377 break;
9378 }
9379 // 'CondCodeRestrictedI' class
9380 case MCK_CondCodeRestrictedI: {
9381 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedI());
9382 if (DP.isMatch())
9383 return MCTargetAsmParser::Match_Success;
9384 if (DP.isNearMatch())
9385 return ARMAsmParser::Match_CondCodeRestrictedI;
9386 break;
9387 }
9388 // 'CondCodeRestrictedS' class
9389 case MCK_CondCodeRestrictedS: {
9390 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedS());
9391 if (DP.isMatch())
9392 return MCTargetAsmParser::Match_Success;
9393 if (DP.isNearMatch())
9394 return ARMAsmParser::Match_CondCodeRestrictedS;
9395 break;
9396 }
9397 // 'CondCodeRestrictedU' class
9398 case MCK_CondCodeRestrictedU: {
9399 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedU());
9400 if (DP.isMatch())
9401 return MCTargetAsmParser::Match_Success;
9402 if (DP.isNearMatch())
9403 return ARMAsmParser::Match_CondCodeRestrictedU;
9404 break;
9405 }
9406 // 'ShrImm16' class
9407 case MCK_ShrImm16: {
9408 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
9409 if (DP.isMatch())
9410 return MCTargetAsmParser::Match_Success;
9411 if (DP.isNearMatch())
9412 return ARMAsmParser::Match_ShrImm16;
9413 break;
9414 }
9415 // 'ShrImm32' class
9416 case MCK_ShrImm32: {
9417 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
9418 if (DP.isMatch())
9419 return MCTargetAsmParser::Match_Success;
9420 if (DP.isNearMatch())
9421 return ARMAsmParser::Match_ShrImm32;
9422 break;
9423 }
9424 // 'ShrImm64' class
9425 case MCK_ShrImm64: {
9426 DiagnosticPredicate DP(Operand.isImmediate<1,64>());
9427 if (DP.isMatch())
9428 return MCTargetAsmParser::Match_Success;
9429 if (DP.isNearMatch())
9430 return ARMAsmParser::Match_ShrImm64;
9431 break;
9432 }
9433 // 'ShrImm8' class
9434 case MCK_ShrImm8: {
9435 DiagnosticPredicate DP(Operand.isImmediate<1,8>());
9436 if (DP.isMatch())
9437 return MCTargetAsmParser::Match_Success;
9438 if (DP.isNearMatch())
9439 return ARMAsmParser::Match_ShrImm8;
9440 break;
9441 }
9442 // 'T2SOImm' class
9443 case MCK_T2SOImm: {
9444 DiagnosticPredicate DP(Operand.isT2SOImm());
9445 if (DP.isMatch())
9446 return MCTargetAsmParser::Match_Success;
9447 break;
9448 }
9449 // 'T2SOImmNeg' class
9450 case MCK_T2SOImmNeg: {
9451 DiagnosticPredicate DP(Operand.isT2SOImmNeg());
9452 if (DP.isMatch())
9453 return MCTargetAsmParser::Match_Success;
9454 break;
9455 }
9456 // 'T2SOImmNot' class
9457 case MCK_T2SOImmNot: {
9458 DiagnosticPredicate DP(Operand.isT2SOImmNot());
9459 if (DP.isMatch())
9460 return MCTargetAsmParser::Match_Success;
9461 break;
9462 }
9463 // 'MemUImm12Offset' class
9464 case MCK_MemUImm12Offset: {
9465 DiagnosticPredicate DP(Operand.isMemUImm12Offset());
9466 if (DP.isMatch())
9467 return MCTargetAsmParser::Match_Success;
9468 break;
9469 }
9470 // 'T2MemRegOffset' class
9471 case MCK_T2MemRegOffset: {
9472 DiagnosticPredicate DP(Operand.isT2MemRegOffset());
9473 if (DP.isMatch())
9474 return MCTargetAsmParser::Match_Success;
9475 break;
9476 }
9477 // 'Imm7s4' class
9478 case MCK_Imm7s4: {
9479 DiagnosticPredicate DP(Operand.isImm7s4());
9480 if (DP.isMatch())
9481 return MCTargetAsmParser::Match_Success;
9482 break;
9483 }
9484 // 'Imm7Shift0' class
9485 case MCK_Imm7Shift0: {
9486 DiagnosticPredicate DP(Operand.isImm7Shift0());
9487 if (DP.isMatch())
9488 return MCTargetAsmParser::Match_Success;
9489 break;
9490 }
9491 // 'Imm7Shift1' class
9492 case MCK_Imm7Shift1: {
9493 DiagnosticPredicate DP(Operand.isImm7Shift1());
9494 if (DP.isMatch())
9495 return MCTargetAsmParser::Match_Success;
9496 break;
9497 }
9498 // 'Imm7Shift2' class
9499 case MCK_Imm7Shift2: {
9500 DiagnosticPredicate DP(Operand.isImm7Shift2());
9501 if (DP.isMatch())
9502 return MCTargetAsmParser::Match_Success;
9503 break;
9504 }
9505 // 'Imm8s4' class
9506 case MCK_Imm8s4: {
9507 DiagnosticPredicate DP(Operand.isImm8s4());
9508 if (DP.isMatch())
9509 return MCTargetAsmParser::Match_Success;
9510 break;
9511 }
9512 // 'MemPCRelImm12' class
9513 case MCK_MemPCRelImm12: {
9514 DiagnosticPredicate DP(Operand.isMemPCRelImm12());
9515 if (DP.isMatch())
9516 return MCTargetAsmParser::Match_Success;
9517 break;
9518 }
9519 // 'MemThumbRIs1' class
9520 case MCK_MemThumbRIs1: {
9521 DiagnosticPredicate DP(Operand.isMemThumbRIs1());
9522 if (DP.isMatch())
9523 return MCTargetAsmParser::Match_Success;
9524 break;
9525 }
9526 // 'MemThumbRIs2' class
9527 case MCK_MemThumbRIs2: {
9528 DiagnosticPredicate DP(Operand.isMemThumbRIs2());
9529 if (DP.isMatch())
9530 return MCTargetAsmParser::Match_Success;
9531 break;
9532 }
9533 // 'MemThumbRIs4' class
9534 case MCK_MemThumbRIs4: {
9535 DiagnosticPredicate DP(Operand.isMemThumbRIs4());
9536 if (DP.isMatch())
9537 return MCTargetAsmParser::Match_Success;
9538 break;
9539 }
9540 // 'MemThumbRR' class
9541 case MCK_MemThumbRR: {
9542 DiagnosticPredicate DP(Operand.isMemThumbRR());
9543 if (DP.isMatch())
9544 return MCTargetAsmParser::Match_Success;
9545 break;
9546 }
9547 // 'MemThumbSPI' class
9548 case MCK_MemThumbSPI: {
9549 DiagnosticPredicate DP(Operand.isMemThumbSPI());
9550 if (DP.isMatch())
9551 return MCTargetAsmParser::Match_Success;
9552 break;
9553 }
9554 // 'Imm0_1020s4' class
9555 case MCK_Imm0_1020s4: {
9556 DiagnosticPredicate DP(Operand.isImm0_1020s4());
9557 if (DP.isMatch())
9558 return MCTargetAsmParser::Match_Success;
9559 break;
9560 }
9561 // 'Imm0_508s4' class
9562 case MCK_Imm0_508s4: {
9563 DiagnosticPredicate DP(Operand.isImm0_508s4());
9564 if (DP.isMatch())
9565 return MCTargetAsmParser::Match_Success;
9566 break;
9567 }
9568 // 'Imm0_508s4Neg' class
9569 case MCK_Imm0_508s4Neg: {
9570 DiagnosticPredicate DP(Operand.isImm0_508s4Neg());
9571 if (DP.isMatch())
9572 return MCTargetAsmParser::Match_Success;
9573 break;
9574 }
9575 // 'WLSLabel' class
9576 case MCK_WLSLabel: {
9577 DiagnosticPredicate DP(Operand.isUnsignedOffset<11, 1>());
9578 if (DP.isMatch())
9579 return MCTargetAsmParser::Match_Success;
9580 if (DP.isNearMatch())
9581 return ARMAsmParser::Match_WLSLabel;
9582 break;
9583 }
9584 } // end switch (Kind)
9585
9586 if (Operand.isReg()) {
9587 MatchClassKind OpKind;
9588 switch (Operand.getReg().id()) {
9589 default: OpKind = InvalidMatchClass; break;
9590 case ARM::R0: OpKind = MCK_Reg17; break;
9591 case ARM::R1: OpKind = MCK_Reg22; break;
9592 case ARM::R2: OpKind = MCK_Reg17; break;
9593 case ARM::R3: OpKind = MCK_Reg22; break;
9594 case ARM::R4: OpKind = MCK_Reg18; break;
9595 case ARM::R5: OpKind = MCK_Reg23; break;
9596 case ARM::R6: OpKind = MCK_Reg18; break;
9597 case ARM::R7: OpKind = MCK_Reg23; break;
9598 case ARM::R8: OpKind = MCK_Reg33; break;
9599 case ARM::R9: OpKind = MCK_Reg35; break;
9600 case ARM::R10: OpKind = MCK_Reg33; break;
9601 case ARM::R11: OpKind = MCK_Reg35; break;
9602 case ARM::R12: OpKind = MCK_R12; break;
9603 case ARM::SP: OpKind = MCK_GPRsp; break;
9604 case ARM::LR: OpKind = MCK_GPRlr; break;
9605 case ARM::PC: OpKind = MCK_PC; break;
9606 case ARM::S0: OpKind = MCK_SPR_8; break;
9607 case ARM::S1: OpKind = MCK_SPR_8; break;
9608 case ARM::S2: OpKind = MCK_SPR_8; break;
9609 case ARM::S3: OpKind = MCK_SPR_8; break;
9610 case ARM::S4: OpKind = MCK_SPR_8; break;
9611 case ARM::S5: OpKind = MCK_SPR_8; break;
9612 case ARM::S6: OpKind = MCK_SPR_8; break;
9613 case ARM::S7: OpKind = MCK_SPR_8; break;
9614 case ARM::S8: OpKind = MCK_SPR_8; break;
9615 case ARM::S9: OpKind = MCK_SPR_8; break;
9616 case ARM::S10: OpKind = MCK_SPR_8; break;
9617 case ARM::S11: OpKind = MCK_SPR_8; break;
9618 case ARM::S12: OpKind = MCK_SPR_8; break;
9619 case ARM::S13: OpKind = MCK_SPR_8; break;
9620 case ARM::S14: OpKind = MCK_SPR_8; break;
9621 case ARM::S15: OpKind = MCK_SPR_8; break;
9622 case ARM::S16: OpKind = MCK_HPR; break;
9623 case ARM::S17: OpKind = MCK_HPR; break;
9624 case ARM::S18: OpKind = MCK_HPR; break;
9625 case ARM::S19: OpKind = MCK_HPR; break;
9626 case ARM::S20: OpKind = MCK_HPR; break;
9627 case ARM::S21: OpKind = MCK_HPR; break;
9628 case ARM::S22: OpKind = MCK_HPR; break;
9629 case ARM::S23: OpKind = MCK_HPR; break;
9630 case ARM::S24: OpKind = MCK_HPR; break;
9631 case ARM::S25: OpKind = MCK_HPR; break;
9632 case ARM::S26: OpKind = MCK_HPR; break;
9633 case ARM::S27: OpKind = MCK_HPR; break;
9634 case ARM::S28: OpKind = MCK_HPR; break;
9635 case ARM::S29: OpKind = MCK_HPR; break;
9636 case ARM::S30: OpKind = MCK_HPR; break;
9637 case ARM::S31: OpKind = MCK_HPR; break;
9638 case ARM::D0: OpKind = MCK_DPR_8; break;
9639 case ARM::D1: OpKind = MCK_DPR_8; break;
9640 case ARM::D2: OpKind = MCK_DPR_8; break;
9641 case ARM::D3: OpKind = MCK_DPR_8; break;
9642 case ARM::D4: OpKind = MCK_DPR_8; break;
9643 case ARM::D5: OpKind = MCK_DPR_8; break;
9644 case ARM::D6: OpKind = MCK_DPR_8; break;
9645 case ARM::D7: OpKind = MCK_DPR_8; break;
9646 case ARM::D8: OpKind = MCK_DPR_VFP2; break;
9647 case ARM::D9: OpKind = MCK_DPR_VFP2; break;
9648 case ARM::D10: OpKind = MCK_DPR_VFP2; break;
9649 case ARM::D11: OpKind = MCK_DPR_VFP2; break;
9650 case ARM::D12: OpKind = MCK_DPR_VFP2; break;
9651 case ARM::D13: OpKind = MCK_DPR_VFP2; break;
9652 case ARM::D14: OpKind = MCK_DPR_VFP2; break;
9653 case ARM::D15: OpKind = MCK_DPR_VFP2; break;
9654 case ARM::D16: OpKind = MCK_DPR; break;
9655 case ARM::D17: OpKind = MCK_DPR; break;
9656 case ARM::D18: OpKind = MCK_DPR; break;
9657 case ARM::D19: OpKind = MCK_DPR; break;
9658 case ARM::D20: OpKind = MCK_DPR; break;
9659 case ARM::D21: OpKind = MCK_DPR; break;
9660 case ARM::D22: OpKind = MCK_DPR; break;
9661 case ARM::D23: OpKind = MCK_DPR; break;
9662 case ARM::D24: OpKind = MCK_DPR; break;
9663 case ARM::D25: OpKind = MCK_DPR; break;
9664 case ARM::D26: OpKind = MCK_DPR; break;
9665 case ARM::D27: OpKind = MCK_DPR; break;
9666 case ARM::D28: OpKind = MCK_DPR; break;
9667 case ARM::D29: OpKind = MCK_DPR; break;
9668 case ARM::D30: OpKind = MCK_DPR; break;
9669 case ARM::D31: OpKind = MCK_DPR; break;
9670 case ARM::Q0: OpKind = MCK_QPR_8; break;
9671 case ARM::Q1: OpKind = MCK_QPR_8; break;
9672 case ARM::Q2: OpKind = MCK_QPR_8; break;
9673 case ARM::Q3: OpKind = MCK_QPR_8; break;
9674 case ARM::Q4: OpKind = MCK_MQPR; break;
9675 case ARM::Q5: OpKind = MCK_MQPR; break;
9676 case ARM::Q6: OpKind = MCK_MQPR; break;
9677 case ARM::Q7: OpKind = MCK_MQPR; break;
9678 case ARM::Q8: OpKind = MCK_QPR; break;
9679 case ARM::Q9: OpKind = MCK_QPR; break;
9680 case ARM::Q10: OpKind = MCK_QPR; break;
9681 case ARM::Q11: OpKind = MCK_QPR; break;
9682 case ARM::Q12: OpKind = MCK_QPR; break;
9683 case ARM::Q13: OpKind = MCK_QPR; break;
9684 case ARM::Q14: OpKind = MCK_QPR; break;
9685 case ARM::Q15: OpKind = MCK_QPR; break;
9686 case ARM::CPSR: OpKind = MCK_CCR; break;
9687 case ARM::APSR: OpKind = MCK_APSR; break;
9688 case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break;
9689 case ARM::SPSR: OpKind = MCK_SPSR; break;
9690 case ARM::FPSCR: OpKind = MCK_FPSCR; break;
9691 case ARM::FPSCR_NZCV: OpKind = MCK_cl_FPSCR_NZCV; break;
9692 case ARM::FPSID: OpKind = MCK_FPSID; break;
9693 case ARM::MVFR2: OpKind = MCK_MVFR2; break;
9694 case ARM::MVFR1: OpKind = MCK_MVFR1; break;
9695 case ARM::MVFR0: OpKind = MCK_MVFR0; break;
9696 case ARM::FPEXC: OpKind = MCK_FPEXC; break;
9697 case ARM::FPINST: OpKind = MCK_FPINST; break;
9698 case ARM::FPINST2: OpKind = MCK_FPINST2; break;
9699 case ARM::VPR: OpKind = MCK_VCCR; break;
9700 case ARM::FPSCR_NZCVQC: OpKind = MCK_FPSCR_NZCVQC; break;
9701 case ARM::P0: OpKind = MCK_P0; break;
9702 case ARM::FPCXTNS: OpKind = MCK_FPCXTRegs; break;
9703 case ARM::FPCXTS: OpKind = MCK_FPCXTS; break;
9704 case ARM::ZR: OpKind = MCK_GPRwithZRnosp; break;
9705 case ARM::D0_D2: OpKind = MCK_Reg72; break;
9706 case ARM::D1_D3: OpKind = MCK_Reg72; break;
9707 case ARM::D2_D4: OpKind = MCK_Reg72; break;
9708 case ARM::D3_D5: OpKind = MCK_Reg72; break;
9709 case ARM::D4_D6: OpKind = MCK_Reg72; break;
9710 case ARM::D5_D7: OpKind = MCK_Reg72; break;
9711 case ARM::D6_D8: OpKind = MCK_Reg73; break;
9712 case ARM::D7_D9: OpKind = MCK_Reg73; break;
9713 case ARM::D8_D10: OpKind = MCK_Reg74; break;
9714 case ARM::D9_D11: OpKind = MCK_Reg74; break;
9715 case ARM::D10_D12: OpKind = MCK_Reg74; break;
9716 case ARM::D11_D13: OpKind = MCK_Reg74; break;
9717 case ARM::D12_D14: OpKind = MCK_Reg74; break;
9718 case ARM::D13_D15: OpKind = MCK_Reg74; break;
9719 case ARM::D14_D16: OpKind = MCK_Reg75; break;
9720 case ARM::D15_D17: OpKind = MCK_Reg75; break;
9721 case ARM::D16_D18: OpKind = MCK_DPairSpc; break;
9722 case ARM::D17_D19: OpKind = MCK_DPairSpc; break;
9723 case ARM::D18_D20: OpKind = MCK_DPairSpc; break;
9724 case ARM::D19_D21: OpKind = MCK_DPairSpc; break;
9725 case ARM::D20_D22: OpKind = MCK_DPairSpc; break;
9726 case ARM::D21_D23: OpKind = MCK_DPairSpc; break;
9727 case ARM::D22_D24: OpKind = MCK_DPairSpc; break;
9728 case ARM::D23_D25: OpKind = MCK_DPairSpc; break;
9729 case ARM::D24_D26: OpKind = MCK_DPairSpc; break;
9730 case ARM::D25_D27: OpKind = MCK_DPairSpc; break;
9731 case ARM::D26_D28: OpKind = MCK_DPairSpc; break;
9732 case ARM::D27_D29: OpKind = MCK_DPairSpc; break;
9733 case ARM::D28_D30: OpKind = MCK_DPairSpc; break;
9734 case ARM::D29_D31: OpKind = MCK_DPairSpc; break;
9735 case ARM::Q0_Q1: OpKind = MCK_Reg77; break;
9736 case ARM::Q1_Q2: OpKind = MCK_Reg77; break;
9737 case ARM::Q2_Q3: OpKind = MCK_Reg77; break;
9738 case ARM::Q3_Q4: OpKind = MCK_Reg78; break;
9739 case ARM::Q4_Q5: OpKind = MCK_MQQPR; break;
9740 case ARM::Q5_Q6: OpKind = MCK_MQQPR; break;
9741 case ARM::Q6_Q7: OpKind = MCK_MQQPR; break;
9742 case ARM::Q7_Q8: OpKind = MCK_Reg80; break;
9743 case ARM::Q8_Q9: OpKind = MCK_QQPR; break;
9744 case ARM::Q9_Q10: OpKind = MCK_QQPR; break;
9745 case ARM::Q10_Q11: OpKind = MCK_QQPR; break;
9746 case ARM::Q11_Q12: OpKind = MCK_QQPR; break;
9747 case ARM::Q12_Q13: OpKind = MCK_QQPR; break;
9748 case ARM::Q13_Q14: OpKind = MCK_QQPR; break;
9749 case ARM::Q14_Q15: OpKind = MCK_QQPR; break;
9750 case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg91; break;
9751 case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg92; break;
9752 case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg93; break;
9753 case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg94; break;
9754 case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_MQQQQPR; break;
9755 case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg96; break;
9756 case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg97; break;
9757 case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg98; break;
9758 case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break;
9759 case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break;
9760 case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break;
9761 case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break;
9762 case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break;
9763 case ARM::R0_R1: OpKind = MCK_Reg100; break;
9764 case ARM::R2_R3: OpKind = MCK_Reg100; break;
9765 case ARM::R4_R5: OpKind = MCK_Reg101; break;
9766 case ARM::R6_R7: OpKind = MCK_Reg101; break;
9767 case ARM::R8_R9: OpKind = MCK_Reg105; break;
9768 case ARM::R10_R11: OpKind = MCK_Reg105; break;
9769 case ARM::R12_SP: OpKind = MCK_Reg107; break;
9770 case ARM::D0_D1_D2: OpKind = MCK_Reg115; break;
9771 case ARM::D1_D2_D3: OpKind = MCK_Reg120; break;
9772 case ARM::D2_D3_D4: OpKind = MCK_Reg115; break;
9773 case ARM::D3_D4_D5: OpKind = MCK_Reg120; break;
9774 case ARM::D4_D5_D6: OpKind = MCK_Reg115; break;
9775 case ARM::D5_D6_D7: OpKind = MCK_Reg120; break;
9776 case ARM::D6_D7_D8: OpKind = MCK_Reg116; break;
9777 case ARM::D7_D8_D9: OpKind = MCK_Reg121; break;
9778 case ARM::D8_D9_D10: OpKind = MCK_Reg117; break;
9779 case ARM::D9_D10_D11: OpKind = MCK_Reg122; break;
9780 case ARM::D10_D11_D12: OpKind = MCK_Reg117; break;
9781 case ARM::D11_D12_D13: OpKind = MCK_Reg122; break;
9782 case ARM::D12_D13_D14: OpKind = MCK_Reg117; break;
9783 case ARM::D13_D14_D15: OpKind = MCK_Reg122; break;
9784 case ARM::D14_D15_D16: OpKind = MCK_Reg118; break;
9785 case ARM::D15_D16_D17: OpKind = MCK_Reg123; break;
9786 case ARM::D16_D17_D18: OpKind = MCK_Reg119; break;
9787 case ARM::D17_D18_D19: OpKind = MCK_Reg124; break;
9788 case ARM::D18_D19_D20: OpKind = MCK_Reg119; break;
9789 case ARM::D19_D20_D21: OpKind = MCK_Reg124; break;
9790 case ARM::D20_D21_D22: OpKind = MCK_Reg119; break;
9791 case ARM::D21_D22_D23: OpKind = MCK_Reg124; break;
9792 case ARM::D22_D23_D24: OpKind = MCK_Reg119; break;
9793 case ARM::D23_D24_D25: OpKind = MCK_Reg124; break;
9794 case ARM::D24_D25_D26: OpKind = MCK_Reg119; break;
9795 case ARM::D25_D26_D27: OpKind = MCK_Reg124; break;
9796 case ARM::D26_D27_D28: OpKind = MCK_Reg119; break;
9797 case ARM::D27_D28_D29: OpKind = MCK_Reg124; break;
9798 case ARM::D28_D29_D30: OpKind = MCK_Reg119; break;
9799 case ARM::D29_D30_D31: OpKind = MCK_Reg124; break;
9800 case ARM::D0_D2_D4: OpKind = MCK_Reg125; break;
9801 case ARM::D1_D3_D5: OpKind = MCK_Reg125; break;
9802 case ARM::D2_D4_D6: OpKind = MCK_Reg125; break;
9803 case ARM::D3_D5_D7: OpKind = MCK_Reg125; break;
9804 case ARM::D4_D6_D8: OpKind = MCK_Reg126; break;
9805 case ARM::D5_D7_D9: OpKind = MCK_Reg126; break;
9806 case ARM::D6_D8_D10: OpKind = MCK_Reg127; break;
9807 case ARM::D7_D9_D11: OpKind = MCK_Reg127; break;
9808 case ARM::D8_D10_D12: OpKind = MCK_Reg128; break;
9809 case ARM::D9_D11_D13: OpKind = MCK_Reg128; break;
9810 case ARM::D10_D12_D14: OpKind = MCK_Reg128; break;
9811 case ARM::D11_D13_D15: OpKind = MCK_Reg128; break;
9812 case ARM::D12_D14_D16: OpKind = MCK_Reg129; break;
9813 case ARM::D13_D15_D17: OpKind = MCK_Reg129; break;
9814 case ARM::D14_D16_D18: OpKind = MCK_Reg130; break;
9815 case ARM::D15_D17_D19: OpKind = MCK_Reg130; break;
9816 case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break;
9817 case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break;
9818 case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break;
9819 case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break;
9820 case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break;
9821 case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break;
9822 case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break;
9823 case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break;
9824 case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break;
9825 case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break;
9826 case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break;
9827 case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break;
9828 case ARM::D1_D2: OpKind = MCK_Reg52; break;
9829 case ARM::D3_D4: OpKind = MCK_Reg52; break;
9830 case ARM::D5_D6: OpKind = MCK_Reg52; break;
9831 case ARM::D7_D8: OpKind = MCK_Reg53; break;
9832 case ARM::D9_D10: OpKind = MCK_Reg50; break;
9833 case ARM::D11_D12: OpKind = MCK_Reg50; break;
9834 case ARM::D13_D14: OpKind = MCK_Reg50; break;
9835 case ARM::D15_D16: OpKind = MCK_Reg51; break;
9836 case ARM::D17_D18: OpKind = MCK_DPair; break;
9837 case ARM::D19_D20: OpKind = MCK_DPair; break;
9838 case ARM::D21_D22: OpKind = MCK_DPair; break;
9839 case ARM::D23_D24: OpKind = MCK_DPair; break;
9840 case ARM::D25_D26: OpKind = MCK_DPair; break;
9841 case ARM::D27_D28: OpKind = MCK_DPair; break;
9842 case ARM::D29_D30: OpKind = MCK_DPair; break;
9843 case ARM::D1_D2_D3_D4: OpKind = MCK_Reg132; break;
9844 case ARM::D3_D4_D5_D6: OpKind = MCK_Reg132; break;
9845 case ARM::D5_D6_D7_D8: OpKind = MCK_Reg133; break;
9846 case ARM::D7_D8_D9_D10: OpKind = MCK_Reg134; break;
9847 case ARM::D9_D10_D11_D12: OpKind = MCK_Reg135; break;
9848 case ARM::D11_D12_D13_D14: OpKind = MCK_Reg135; break;
9849 case ARM::D13_D14_D15_D16: OpKind = MCK_Reg136; break;
9850 case ARM::D15_D16_D17_D18: OpKind = MCK_Reg137; break;
9851 case ARM::D17_D18_D19_D20: OpKind = MCK_Reg138; break;
9852 case ARM::D19_D20_D21_D22: OpKind = MCK_Reg138; break;
9853 case ARM::D21_D22_D23_D24: OpKind = MCK_Reg138; break;
9854 case ARM::D23_D24_D25_D26: OpKind = MCK_Reg138; break;
9855 case ARM::D25_D26_D27_D28: OpKind = MCK_Reg138; break;
9856 case ARM::D27_D28_D29_D30: OpKind = MCK_Reg138; break;
9857 }
9858 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
9859 getDiagKindFromRegisterClass(Kind);
9860 }
9861
9862 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
9863 return getDiagKindFromRegisterClass(Kind);
9864
9865 return MCTargetAsmParser::Match_InvalidOperand;
9866}
9867
9868#ifndef NDEBUG
9869const char *getMatchClassName(MatchClassKind Kind) {
9870 switch (Kind) {
9871 case InvalidMatchClass: return "InvalidMatchClass";
9872 case OptionalMatchClass: return "OptionalMatchClass";
9873 case MCK__DOT_d: return "MCK__DOT_d";
9874 case MCK__DOT_f: return "MCK__DOT_f";
9875 case MCK__DOT_s16: return "MCK__DOT_s16";
9876 case MCK__DOT_s32: return "MCK__DOT_s32";
9877 case MCK__DOT_s64: return "MCK__DOT_s64";
9878 case MCK__DOT_s8: return "MCK__DOT_s8";
9879 case MCK__DOT_u16: return "MCK__DOT_u16";
9880 case MCK__DOT_u32: return "MCK__DOT_u32";
9881 case MCK__DOT_u64: return "MCK__DOT_u64";
9882 case MCK__DOT_u8: return "MCK__DOT_u8";
9883 case MCK__DOT_f32: return "MCK__DOT_f32";
9884 case MCK__DOT_f64: return "MCK__DOT_f64";
9885 case MCK__DOT_i16: return "MCK__DOT_i16";
9886 case MCK__DOT_i32: return "MCK__DOT_i32";
9887 case MCK__DOT_i64: return "MCK__DOT_i64";
9888 case MCK__DOT_i8: return "MCK__DOT_i8";
9889 case MCK__DOT_p16: return "MCK__DOT_p16";
9890 case MCK__DOT_p8: return "MCK__DOT_p8";
9891 case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
9892 case MCK__HASH_0: return "MCK__HASH_0";
9893 case MCK__HASH_16: return "MCK__HASH_16";
9894 case MCK__HASH_8: return "MCK__HASH_8";
9895 case MCK__DOT_16: return "MCK__DOT_16";
9896 case MCK__DOT_32: return "MCK__DOT_32";
9897 case MCK__DOT_64: return "MCK__DOT_64";
9898 case MCK__DOT_8: return "MCK__DOT_8";
9899 case MCK__DOT_bf16: return "MCK__DOT_bf16";
9900 case MCK__DOT_f16: return "MCK__DOT_f16";
9901 case MCK__DOT_p64: return "MCK__DOT_p64";
9902 case MCK__DOT_w: return "MCK__DOT_w";
9903 case MCK__91_: return "MCK__91_";
9904 case MCK__93_: return "MCK__93_";
9905 case MCK__94_: return "MCK__94_";
9906 case MCK__123_: return "MCK__123_";
9907 case MCK__125_: return "MCK__125_";
9908 case MCK_Reg107: return "MCK_Reg107";
9909 case MCK_Reg91: return "MCK_Reg91";
9910 case MCK_APSR: return "MCK_APSR";
9911 case MCK_APSR_NZCV: return "MCK_APSR_NZCV";
9912 case MCK_CCR: return "MCK_CCR";
9913 case MCK_FPCXTRegs: return "MCK_FPCXTRegs";
9914 case MCK_FPCXTS: return "MCK_FPCXTS";
9915 case MCK_FPEXC: return "MCK_FPEXC";
9916 case MCK_FPINST: return "MCK_FPINST";
9917 case MCK_FPINST2: return "MCK_FPINST2";
9918 case MCK_FPSCR: return "MCK_FPSCR";
9919 case MCK_FPSCR_NZCVQC: return "MCK_FPSCR_NZCVQC";
9920 case MCK_FPSID: return "MCK_FPSID";
9921 case MCK_GPRlr: return "MCK_GPRlr";
9922 case MCK_GPRsp: return "MCK_GPRsp";
9923 case MCK_MVFR0: return "MCK_MVFR0";
9924 case MCK_MVFR1: return "MCK_MVFR1";
9925 case MCK_MVFR2: return "MCK_MVFR2";
9926 case MCK_P0: return "MCK_P0";
9927 case MCK_PC: return "MCK_PC";
9928 case MCK_R12: return "MCK_R12";
9929 case MCK_SPSR: return "MCK_SPSR";
9930 case MCK_VCCR: return "MCK_VCCR";
9931 case MCK_cl_FPSCR_NZCV: return "MCK_cl_FPSCR_NZCV";
9932 case MCK_Reg132: return "MCK_Reg132";
9933 case MCK_Reg105: return "MCK_Reg105";
9934 case MCK_Reg100: return "MCK_Reg100";
9935 case MCK_Reg92: return "MCK_Reg92";
9936 case MCK_Reg35: return "MCK_Reg35";
9937 case MCK_Reg33: return "MCK_Reg33";
9938 case MCK_Reg22: return "MCK_Reg22";
9939 case MCK_Reg17: return "MCK_Reg17";
9940 case MCK_Reg133: return "MCK_Reg133";
9941 case MCK_Reg120: return "MCK_Reg120";
9942 case MCK_Reg115: return "MCK_Reg115";
9943 case MCK_Reg106: return "MCK_Reg106";
9944 case MCK_Reg104: return "MCK_Reg104";
9945 case MCK_Reg93: return "MCK_Reg93";
9946 case MCK_Reg77: return "MCK_Reg77";
9947 case MCK_Reg21: return "MCK_Reg21";
9948 case MCK_Reg134: return "MCK_Reg134";
9949 case MCK_Reg125: return "MCK_Reg125";
9950 case MCK_Reg121: return "MCK_Reg121";
9951 case MCK_Reg116: return "MCK_Reg116";
9952 case MCK_Reg101: return "MCK_Reg101";
9953 case MCK_Reg94: return "MCK_Reg94";
9954 case MCK_Reg78: return "MCK_Reg78";
9955 case MCK_Reg34: return "MCK_Reg34";
9956 case MCK_Reg25: return "MCK_Reg25";
9957 case MCK_Reg23: return "MCK_Reg23";
9958 case MCK_Reg18: return "MCK_Reg18";
9959 case MCK_QPR_8: return "MCK_QPR_8";
9960 case MCK_tcGPRnotr12: return "MCK_tcGPRnotr12";
9961 case MCK_Reg89: return "MCK_Reg89";
9962 case MCK_Reg32: return "MCK_Reg32";
9963 case MCK_Reg30: return "MCK_Reg30";
9964 case MCK_MQQQQPR: return "MCK_MQQQQPR";
9965 case MCK_tcGPR: return "MCK_tcGPR";
9966 case MCK_Reg135: return "MCK_Reg135";
9967 case MCK_Reg126: return "MCK_Reg126";
9968 case MCK_Reg108: return "MCK_Reg108";
9969 case MCK_Reg96: return "MCK_Reg96";
9970 case MCK_Reg90: return "MCK_Reg90";
9971 case MCK_Reg72: return "MCK_Reg72";
9972 case MCK_Reg31: return "MCK_Reg31";
9973 case MCK_Reg28: return "MCK_Reg28";
9974 case MCK_Reg19: return "MCK_Reg19";
9975 case MCK_GPRPairnosp: return "MCK_GPRPairnosp";
9976 case MCK_tGPROdd: return "MCK_tGPROdd";
9977 case MCK_Reg136: return "MCK_Reg136";
9978 case MCK_Reg122: return "MCK_Reg122";
9979 case MCK_Reg117: return "MCK_Reg117";
9980 case MCK_Reg109: return "MCK_Reg109";
9981 case MCK_Reg97: return "MCK_Reg97";
9982 case MCK_Reg87: return "MCK_Reg87";
9983 case MCK_Reg52: return "MCK_Reg52";
9984 case MCK_Reg29: return "MCK_Reg29";
9985 case MCK_Reg26: return "MCK_Reg26";
9986 case MCK_GPRPair: return "MCK_GPRPair";
9987 case MCK_MQQPR: return "MCK_MQQPR";
9988 case MCK_Reg137: return "MCK_Reg137";
9989 case MCK_Reg127: return "MCK_Reg127";
9990 case MCK_Reg123: return "MCK_Reg123";
9991 case MCK_Reg118: return "MCK_Reg118";
9992 case MCK_Reg110: return "MCK_Reg110";
9993 case MCK_Reg98: return "MCK_Reg98";
9994 case MCK_Reg88: return "MCK_Reg88";
9995 case MCK_Reg80: return "MCK_Reg80";
9996 case MCK_Reg73: return "MCK_Reg73";
9997 case MCK_Reg53: return "MCK_Reg53";
9998 case MCK_DPR_8: return "MCK_DPR_8";
9999 case MCK_MQPR: return "MCK_MQPR";
10000 case MCK_hGPR: return "MCK_hGPR";
10001 case MCK_tGPR: return "MCK_tGPR";
10002 case MCK_tGPREven: return "MCK_tGPREven";
10003 case MCK_tGPRwithpc: return "MCK_tGPRwithpc";
10004 case MCK_Reg128: return "MCK_Reg128";
10005 case MCK_Reg2: return "MCK_Reg2";
10006 case MCK_Reg85: return "MCK_Reg85";
10007 case MCK_Reg14: return "MCK_Reg14";
10008 case MCK_Reg12: return "MCK_Reg12";
10009 case MCK_QQQQPR: return "MCK_QQQQPR";
10010 case MCK_Reg138: return "MCK_Reg138";
10011 case MCK_Reg129: return "MCK_Reg129";
10012 case MCK_Reg111: return "MCK_Reg111";
10013 case MCK_Reg86: return "MCK_Reg86";
10014 case MCK_Reg74: return "MCK_Reg74";
10015 case MCK_GPRnoip: return "MCK_GPRnoip";
10016 case MCK_rGPR: return "MCK_rGPR";
10017 case MCK_Reg124: return "MCK_Reg124";
10018 case MCK_Reg119: return "MCK_Reg119";
10019 case MCK_Reg112: return "MCK_Reg112";
10020 case MCK_Reg83: return "MCK_Reg83";
10021 case MCK_Reg50: return "MCK_Reg50";
10022 case MCK_GPRnopc: return "MCK_GPRnopc";
10023 case MCK_GPRnosp: return "MCK_GPRnosp";
10024 case MCK_GPRwithAPSR_NZCVnosp: return "MCK_GPRwithAPSR_NZCVnosp";
10025 case MCK_GPRwithAPSRnosp: return "MCK_GPRwithAPSRnosp";
10026 case MCK_GPRwithZRnosp: return "MCK_GPRwithZRnosp";
10027 case MCK_QQPR: return "MCK_QQPR";
10028 case MCK_Reg130: return "MCK_Reg130";
10029 case MCK_Reg113: return "MCK_Reg113";
10030 case MCK_Reg84: return "MCK_Reg84";
10031 case MCK_Reg75: return "MCK_Reg75";
10032 case MCK_Reg51: return "MCK_Reg51";
10033 case MCK_DPR_VFP2: return "MCK_DPR_VFP2";
10034 case MCK_GPR: return "MCK_GPR";
10035 case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR";
10036 case MCK_GPRwithZR: return "MCK_GPRwithZR";
10037 case MCK_QPR: return "MCK_QPR";
10038 case MCK_SPR_8: return "MCK_SPR_8";
10039 case MCK_DTripleSpc: return "MCK_DTripleSpc";
10040 case MCK_DQuad: return "MCK_DQuad";
10041 case MCK_DPairSpc: return "MCK_DPairSpc";
10042 case MCK_DTriple: return "MCK_DTriple";
10043 case MCK_DPair: return "MCK_DPair";
10044 case MCK_DPR: return "MCK_DPR";
10045 case MCK_HPR: return "MCK_HPR";
10046 case MCK_FPWithVPR: return "MCK_FPWithVPR";
10047 case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm";
10048 case MCK_AM3Offset: return "MCK_AM3Offset";
10049 case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget";
10050 case MCK_AddrMode3: return "MCK_AddrMode3";
10051 case MCK_AddrMode5: return "MCK_AddrMode5";
10052 case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16";
10053 case MCK_AlignedMemory16: return "MCK_AlignedMemory16";
10054 case MCK_AlignedMemory32: return "MCK_AlignedMemory32";
10055 case MCK_AlignedMemory64: return "MCK_AlignedMemory64";
10056 case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128";
10057 case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256";
10058 case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone";
10059 case MCK_AlignedMemory: return "MCK_AlignedMemory";
10060 case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16";
10061 case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32";
10062 case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64";
10063 case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128";
10064 case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone";
10065 case MCK_AdrLabel: return "MCK_AdrLabel";
10066 case MCK_BankedReg: return "MCK_BankedReg";
10067 case MCK_Bitfield: return "MCK_Bitfield";
10068 case MCK_CCOut: return "MCK_CCOut";
10069 case MCK_CondCode: return "MCK_CondCode";
10070 case MCK_CoprocNum: return "MCK_CoprocNum";
10071 case MCK_CoprocOption: return "MCK_CoprocOption";
10072 case MCK_CoprocReg: return "MCK_CoprocReg";
10073 case MCK_DPRRegList: return "MCK_DPRRegList";
10074 case MCK_FPDRegListWithVPR: return "MCK_FPDRegListWithVPR";
10075 case MCK_FPImm: return "MCK_FPImm";
10076 case MCK_FPSRegListWithVPR: return "MCK_FPSRegListWithVPR";
10077 case MCK_Imm0_15: return "MCK_Imm0_15";
10078 case MCK_Imm0_1: return "MCK_Imm0_1";
10079 case MCK_Imm0_239: return "MCK_Imm0_239";
10080 case MCK_Imm0_255: return "MCK_Imm0_255";
10081 case MCK_Imm0_255Expr: return "MCK_Imm0_255Expr";
10082 case MCK_Imm0_31: return "MCK_Imm0_31";
10083 case MCK_Imm0_32: return "MCK_Imm0_32";
10084 case MCK_Imm0_3: return "MCK_Imm0_3";
10085 case MCK_Imm0_63: return "MCK_Imm0_63";
10086 case MCK_Imm0_65535: return "MCK_Imm0_65535";
10087 case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr";
10088 case MCK_Imm0_7: return "MCK_Imm0_7";
10089 case MCK_Imm16: return "MCK_Imm16";
10090 case MCK_Imm1_15: return "MCK_Imm1_15";
10091 case MCK_Imm1_16: return "MCK_Imm1_16";
10092 case MCK_Imm1_31: return "MCK_Imm1_31";
10093 case MCK_Imm1_32: return "MCK_Imm1_32";
10094 case MCK_Imm1_7: return "MCK_Imm1_7";
10095 case MCK_Imm24bit: return "MCK_Imm24bit";
10096 case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr";
10097 case MCK_Imm32: return "MCK_Imm32";
10098 case MCK_Imm8: return "MCK_Imm8";
10099 case MCK_Imm8_255: return "MCK_Imm8_255";
10100 case MCK_Imm: return "MCK_Imm";
10101 case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt";
10102 case MCK_MSRMask: return "MCK_MSRMask";
10103 case MCK_MVEShiftImm1_15: return "MCK_MVEShiftImm1_15";
10104 case MCK_MVEShiftImm1_7: return "MCK_MVEShiftImm1_7";
10105 case MCK_VIDUP_imm: return "MCK_VIDUP_imm";
10106 case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt";
10107 case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset";
10108 case MCK_MemImm12Offset: return "MCK_MemImm12Offset";
10109 case MCK_MemImm7Shift0Offset: return "MCK_MemImm7Shift0Offset";
10110 case MCK_MemImm7Shift0OffsetWB: return "MCK_MemImm7Shift0OffsetWB";
10111 case MCK_MemImm7Shift1Offset: return "MCK_MemImm7Shift1Offset";
10112 case MCK_MemImm7Shift1OffsetWB: return "MCK_MemImm7Shift1OffsetWB";
10113 case MCK_MemImm7Shift2Offset: return "MCK_MemImm7Shift2Offset";
10114 case MCK_MemImm7Shift2OffsetWB: return "MCK_MemImm7Shift2OffsetWB";
10115 case MCK_MemImm7s4Offset: return "MCK_MemImm7s4Offset";
10116 case MCK_MemImm8Offset: return "MCK_MemImm8Offset";
10117 case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset";
10118 case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset";
10119 case MCK_MemNoOffset: return "MCK_MemNoOffset";
10120 case MCK_MemNoOffsetT2: return "MCK_MemNoOffsetT2";
10121 case MCK_MemNoOffsetT2NoSp: return "MCK_MemNoOffsetT2NoSp";
10122 case MCK_MemNoOffsetT: return "MCK_MemNoOffsetT";
10123 case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset";
10124 case MCK_MemRegOffset: return "MCK_MemRegOffset";
10125 case MCK_MemRegQS2Offset: return "MCK_MemRegQS2Offset";
10126 case MCK_MemRegQS3Offset: return "MCK_MemRegQS3Offset";
10127 case MCK_MemRegRQS0Offset: return "MCK_MemRegRQS0Offset";
10128 case MCK_MemRegRQS1Offset: return "MCK_MemRegRQS1Offset";
10129 case MCK_MemRegRQS2Offset: return "MCK_MemRegRQS2Offset";
10130 case MCK_MemRegRQS3Offset: return "MCK_MemRegRQS3Offset";
10131 case MCK_ModImm: return "MCK_ModImm";
10132 case MCK_ModImmNeg: return "MCK_ModImmNeg";
10133 case MCK_ModImmNot: return "MCK_ModImmNot";
10134 case MCK_MveSaturate: return "MCK_MveSaturate";
10135 case MCK_PKHASRImm: return "MCK_PKHASRImm";
10136 case MCK_PKHLSLImm: return "MCK_PKHLSLImm";
10137 case MCK_PostIdxImm8: return "MCK_PostIdxImm8";
10138 case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4";
10139 case MCK_PostIdxReg: return "MCK_PostIdxReg";
10140 case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted";
10141 case MCK_ProcIFlags: return "MCK_ProcIFlags";
10142 case MCK_RegList: return "MCK_RegList";
10143 case MCK_RegListWithAPSR: return "MCK_RegListWithAPSR";
10144 case MCK_RotImm: return "MCK_RotImm";
10145 case MCK_SPRRegList: return "MCK_SPRRegList";
10146 case MCK_SetEndImm: return "MCK_SetEndImm";
10147 case MCK_RegShiftedImm: return "MCK_RegShiftedImm";
10148 case MCK_RegShiftedReg: return "MCK_RegShiftedReg";
10149 case MCK_ShifterImm: return "MCK_ShifterImm";
10150 case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget";
10151 case MCK_ThumbMemPC: return "MCK_ThumbMemPC";
10152 case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7";
10153 case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255";
10154 case MCK_ImmThumbSR: return "MCK_ImmThumbSR";
10155 case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt";
10156 case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2";
10157 case MCK_VPTPredN: return "MCK_VPTPredN";
10158 case MCK_VPTPredR: return "MCK_VPTPredR";
10159 case MCK_VecListTwoMQ: return "MCK_VecListTwoMQ";
10160 case MCK_VecListFourMQ: return "MCK_VecListFourMQ";
10161 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes";
10162 case MCK_VecListDPair: return "MCK_VecListDPair";
10163 case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes";
10164 case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced";
10165 case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes";
10166 case MCK_VecListFourD: return "MCK_VecListFourD";
10167 case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed";
10168 case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed";
10169 case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed";
10170 case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes";
10171 case MCK_VecListFourQ: return "MCK_VecListFourQ";
10172 case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed";
10173 case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed";
10174 case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes";
10175 case MCK_VecListOneD: return "MCK_VecListOneD";
10176 case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed";
10177 case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed";
10178 case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed";
10179 case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes";
10180 case MCK_VecListThreeD: return "MCK_VecListThreeD";
10181 case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed";
10182 case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed";
10183 case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed";
10184 case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes";
10185 case MCK_VecListThreeQ: return "MCK_VecListThreeQ";
10186 case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed";
10187 case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed";
10188 case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed";
10189 case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed";
10190 case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed";
10191 case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed";
10192 case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed";
10193 case MCK_VectorIndex16: return "MCK_VectorIndex16";
10194 case MCK_VectorIndex32: return "MCK_VectorIndex32";
10195 case MCK_VectorIndex64: return "MCK_VectorIndex64";
10196 case MCK_VectorIndex8: return "MCK_VectorIndex8";
10197 case MCK_MemTBB: return "MCK_MemTBB";
10198 case MCK_MemTBH: return "MCK_MemTBH";
10199 case MCK_MVEVectorIndex4: return "MCK_MVEVectorIndex4";
10200 case MCK_MVEVectorIndex8: return "MCK_MVEVectorIndex8";
10201 case MCK_MVEVectorIndex16: return "MCK_MVEVectorIndex16";
10202 case MCK_MVEVcvtImm32: return "MCK_MVEVcvtImm32";
10203 case MCK_MVEVcvtImm16: return "MCK_MVEVcvtImm16";
10204 case MCK_TMemImm7Shift2Offset: return "MCK_TMemImm7Shift2Offset";
10205 case MCK_TMemImm7Shift0Offset: return "MCK_TMemImm7Shift0Offset";
10206 case MCK_TMemImm7Shift1Offset: return "MCK_TMemImm7Shift1Offset";
10207 case MCK_Imm3b: return "MCK_Imm3b";
10208 case MCK_Imm4b: return "MCK_Imm4b";
10209 case MCK_Imm6b: return "MCK_Imm6b";
10210 case MCK_Imm7b: return "MCK_Imm7b";
10211 case MCK_Imm9b: return "MCK_Imm9b";
10212 case MCK_Imm11b: return "MCK_Imm11b";
10213 case MCK_Imm12b: return "MCK_Imm12b";
10214 case MCK_Imm13b: return "MCK_Imm13b";
10215 case MCK_MVEPairVectorIndex0: return "MCK_MVEPairVectorIndex0";
10216 case MCK_MVEPairVectorIndex2: return "MCK_MVEPairVectorIndex2";
10217 case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven";
10218 case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd";
10219 case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate";
10220 case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate";
10221 case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate";
10222 case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate";
10223 case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate";
10224 case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate";
10225 case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate";
10226 case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate";
10227 case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate";
10228 case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm";
10229 case MCK_FBits16: return "MCK_FBits16";
10230 case MCK_FBits32: return "MCK_FBits32";
10231 case MCK_Imm0_4095: return "MCK_Imm0_4095";
10232 case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg";
10233 case MCK_ITMask: return "MCK_ITMask";
10234 case MCK_ITCondCode: return "MCK_ITCondCode";
10235 case MCK_LELabel: return "MCK_LELabel";
10236 case MCK_MVELongShift: return "MCK_MVELongShift";
10237 case MCK_NEONi16splat: return "MCK_NEONi16splat";
10238 case MCK_NEONi32splat: return "MCK_NEONi32splat";
10239 case MCK_NEONi64splat: return "MCK_NEONi64splat";
10240 case MCK_NEONi8splat: return "MCK_NEONi8splat";
10241 case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot";
10242 case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot";
10243 case MCK_NEONi32vmov: return "MCK_NEONi32vmov";
10244 case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg";
10245 case MCK_CondCodeNoAL: return "MCK_CondCodeNoAL";
10246 case MCK_CondCodeNoALInv: return "MCK_CondCodeNoALInv";
10247 case MCK_CondCodeRestrictedFP: return "MCK_CondCodeRestrictedFP";
10248 case MCK_CondCodeRestrictedI: return "MCK_CondCodeRestrictedI";
10249 case MCK_CondCodeRestrictedS: return "MCK_CondCodeRestrictedS";
10250 case MCK_CondCodeRestrictedU: return "MCK_CondCodeRestrictedU";
10251 case MCK_ShrImm16: return "MCK_ShrImm16";
10252 case MCK_ShrImm32: return "MCK_ShrImm32";
10253 case MCK_ShrImm64: return "MCK_ShrImm64";
10254 case MCK_ShrImm8: return "MCK_ShrImm8";
10255 case MCK_T2SOImm: return "MCK_T2SOImm";
10256 case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg";
10257 case MCK_T2SOImmNot: return "MCK_T2SOImmNot";
10258 case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset";
10259 case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset";
10260 case MCK_Imm7s4: return "MCK_Imm7s4";
10261 case MCK_Imm7Shift0: return "MCK_Imm7Shift0";
10262 case MCK_Imm7Shift1: return "MCK_Imm7Shift1";
10263 case MCK_Imm7Shift2: return "MCK_Imm7Shift2";
10264 case MCK_Imm8s4: return "MCK_Imm8s4";
10265 case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12";
10266 case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1";
10267 case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2";
10268 case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4";
10269 case MCK_MemThumbRR: return "MCK_MemThumbRR";
10270 case MCK_MemThumbSPI: return "MCK_MemThumbSPI";
10271 case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4";
10272 case MCK_Imm0_508s4: return "MCK_Imm0_508s4";
10273 case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg";
10274 case MCK_WLSLabel: return "MCK_WLSLabel";
10275 case NumMatchClassKinds: return "NumMatchClassKinds";
10276 }
10277 llvm_unreachable("unhandled MatchClassKind!");
10278}
10279
10280#endif // NDEBUG
10281FeatureBitset ARMAsmParser::
10282ComputeAvailableFeatures(const FeatureBitset &FB) const {
10283 FeatureBitset Features;
10284 if (FB[ARM::HasV4TOps])
10285 Features.set(Feature_HasV4TBit);
10286 if (FB[ARM::HasV5TOps])
10287 Features.set(Feature_HasV5TBit);
10288 if (FB[ARM::HasV5TEOps])
10289 Features.set(Feature_HasV5TEBit);
10290 if (FB[ARM::HasV6Ops])
10291 Features.set(Feature_HasV6Bit);
10292 if (FB[ARM::HasV6MOps])
10293 Features.set(Feature_HasV6MBit);
10294 if (FB[ARM::HasV8MBaselineOps])
10295 Features.set(Feature_HasV8MBaselineBit);
10296 if (FB[ARM::HasV8MMainlineOps])
10297 Features.set(Feature_HasV8MMainlineBit);
10298 if (FB[ARM::HasV8_1MMainlineOps])
10299 Features.set(Feature_HasV8_1MMainlineBit);
10300 if (FB[ARM::HasMVEIntegerOps])
10301 Features.set(Feature_HasMVEIntBit);
10302 if (FB[ARM::HasMVEFloatOps])
10303 Features.set(Feature_HasMVEFloatBit);
10304 if (FB[ARM::HasCDEOps])
10305 Features.set(Feature_HasCDEBit);
10306 if (FB[ARM::FeatureFPRegs])
10307 Features.set(Feature_HasFPRegsBit);
10308 if (FB[ARM::FeatureFPRegs16])
10309 Features.set(Feature_HasFPRegs16Bit);
10310 if (!FB[ARM::FeatureFPRegs16])
10311 Features.set(Feature_HasNoFPRegs16Bit);
10312 if (FB[ARM::FeatureFPRegs64])
10313 Features.set(Feature_HasFPRegs64Bit);
10314 if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps])
10315 Features.set(Feature_HasFPRegsV8_1MBit);
10316 if (FB[ARM::HasV6T2Ops])
10317 Features.set(Feature_HasV6T2Bit);
10318 if (FB[ARM::HasV6KOps])
10319 Features.set(Feature_HasV6KBit);
10320 if (FB[ARM::HasV7Ops])
10321 Features.set(Feature_HasV7Bit);
10322 if (FB[ARM::HasV8Ops])
10323 Features.set(Feature_HasV8Bit);
10324 if (!FB[ARM::HasV8Ops])
10325 Features.set(Feature_PreV8Bit);
10326 if (FB[ARM::HasV8_1aOps])
10327 Features.set(Feature_HasV8_1aBit);
10328 if (FB[ARM::HasV8_2aOps])
10329 Features.set(Feature_HasV8_2aBit);
10330 if (FB[ARM::HasV8_3aOps])
10331 Features.set(Feature_HasV8_3aBit);
10332 if (FB[ARM::HasV8_4aOps])
10333 Features.set(Feature_HasV8_4aBit);
10334 if (FB[ARM::HasV8_5aOps])
10335 Features.set(Feature_HasV8_5aBit);
10336 if (FB[ARM::HasV8_6aOps])
10337 Features.set(Feature_HasV8_6aBit);
10338 if (FB[ARM::HasV8_7aOps])
10339 Features.set(Feature_HasV8_7aBit);
10340 if (FB[ARM::FeatureVFP2_SP])
10341 Features.set(Feature_HasVFP2Bit);
10342 if (FB[ARM::FeatureVFP3_D16_SP])
10343 Features.set(Feature_HasVFP3Bit);
10344 if (FB[ARM::FeatureVFP4_D16_SP])
10345 Features.set(Feature_HasVFP4Bit);
10346 if (FB[ARM::FeatureFP64])
10347 Features.set(Feature_HasDPVFPBit);
10348 if (FB[ARM::FeatureFPARMv8_D16_SP])
10349 Features.set(Feature_HasFPARMv8Bit);
10350 if (FB[ARM::FeatureNEON])
10351 Features.set(Feature_HasNEONBit);
10352 if (FB[ARM::FeatureSHA2])
10353 Features.set(Feature_HasSHA2Bit);
10354 if (FB[ARM::FeatureAES])
10355 Features.set(Feature_HasAESBit);
10356 if (FB[ARM::FeatureCrypto])
10357 Features.set(Feature_HasCryptoBit);
10358 if (FB[ARM::FeatureDotProd])
10359 Features.set(Feature_HasDotProdBit);
10360 if (FB[ARM::FeatureCRC])
10361 Features.set(Feature_HasCRCBit);
10362 if (FB[ARM::FeatureRAS])
10363 Features.set(Feature_HasRASBit);
10364 if (FB[ARM::FeatureLOB])
10365 Features.set(Feature_HasLOBBit);
10366 if (FB[ARM::FeaturePACBTI])
10367 Features.set(Feature_HasPACBTIBit);
10368 if (FB[ARM::FeatureFP16])
10369 Features.set(Feature_HasFP16Bit);
10370 if (FB[ARM::FeatureFullFP16])
10371 Features.set(Feature_HasFullFP16Bit);
10372 if (FB[ARM::FeatureFP16FML])
10373 Features.set(Feature_HasFP16FMLBit);
10374 if (FB[ARM::FeatureBF16])
10375 Features.set(Feature_HasBF16Bit);
10376 if (FB[ARM::FeatureMatMulInt8])
10377 Features.set(Feature_HasMatMulInt8Bit);
10378 if (FB[ARM::FeatureHWDivThumb])
10379 Features.set(Feature_HasDivideInThumbBit);
10380 if (FB[ARM::FeatureHWDivARM])
10381 Features.set(Feature_HasDivideInARMBit);
10382 if (FB[ARM::FeatureDSP])
10383 Features.set(Feature_HasDSPBit);
10384 if (FB[ARM::FeatureDB])
10385 Features.set(Feature_HasDBBit);
10386 if (FB[ARM::FeatureDFB])
10387 Features.set(Feature_HasDFBBit);
10388 if (FB[ARM::FeatureV7Clrex])
10389 Features.set(Feature_HasV7ClrexBit);
10390 if (FB[ARM::FeatureAcquireRelease])
10391 Features.set(Feature_HasAcquireReleaseBit);
10392 if (FB[ARM::FeatureMP])
10393 Features.set(Feature_HasMPBit);
10394 if (FB[ARM::FeatureVirtualization])
10395 Features.set(Feature_HasVirtualizationBit);
10396 if (FB[ARM::FeatureTrustZone])
10397 Features.set(Feature_HasTrustZoneBit);
10398 if (FB[ARM::Feature8MSecExt])
10399 Features.set(Feature_Has8MSecExtBit);
10400 if (FB[ARM::ModeThumb])
10401 Features.set(Feature_IsThumbBit);
10402 if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2])
10403 Features.set(Feature_IsThumb2Bit);
10404 if (FB[ARM::FeatureMClass])
10405 Features.set(Feature_IsMClassBit);
10406 if (!FB[ARM::FeatureMClass])
10407 Features.set(Feature_IsNotMClassBit);
10408 if (!FB[ARM::ModeThumb])
10409 Features.set(Feature_IsARMBit);
10410 if (FB[ARM::FeatureNaClTrap])
10411 Features.set(Feature_UseNaClTrapBit);
10412 if (!FB[ARM::FeatureNoNegativeImmediates])
10413 Features.set(Feature_UseNegativeImmediatesBit);
10414 if (FB[ARM::FeatureSB])
10415 Features.set(Feature_HasSBBit);
10416 if (FB[ARM::FeatureCLRBHB])
10417 Features.set(Feature_HasCLRBHBBit);
10418 return Features;
10419}
10420
10421static const char MnemonicTable[] =
10422 "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a"
10423 "esmc\003and\003asr\004asrl\003aut\004autg\001b\002bf\003bfc\006bfcsel\003"
10424 "bfi\003bfl\004bflx\003bfx\003bic\004bkpt\002bl\003blx\005blxns\003bti\002"
10425 "bx\005bxaut\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\004cinc\004cin"
10426 "v\006clrbhb\005clrex\004clrm\003clz\003cmn\003cmp\004cneg\003cps\006crc"
10427 "32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006crc32w\004csdb\004cse"
10428 "l\004cset\005csetm\005csinc\005csinv\005csneg\003cx1\004cx1a\004cx1d\005"
10429 "cx1da\003cx2\004cx2a\004cx2d\005cx2da\003cx3\004cx3a\004cx3d\005cx3da\003"
10430 "dbg\005dcps1\005dcps2\005dcps3\003dfb\003dls\005dlstp\003dmb\003dsb\003"
10431 "eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007"
10432 "fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007"
10433 "fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\004lctp\003"
10434 "lda\004ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ld"
10435 "c2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005"
10436 "ldrbt\004ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005"
10437 "ldrsb\006ldrsbt\005ldrsh\006ldrsht\004ldrt\002le\004letp\003lsl\004lsll"
10438 "\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003mov\004"
10439 "movs\004movt\004movw\003mrc\004mrc2\004mrrc\005mrrc2\003mrs\003msr\003m"
10440 "ul\003mvn\003neg\003nop\003orn\003orr\003pac\006pacbti\004pacg\005pkhbt"
10441 "\005pkhtb\003pld\004pldw\003pli\003pop\005pssbb\004push\004qadd\006qadd"
10442 "16\005qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub"
10443 "8\004rbit\003rev\005rev16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003"
10444 "ror\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\002sb\003sbc\004sbf"
10445 "x\004sdiv\003sel\006setend\006setpan\003sev\004sevl\002sg\005sha1c\005s"
10446 "ha1h\005sha1m\005sha1p\007sha1su0\007sha1su1\007sha256h\010sha256h2\tsh"
10447 "a256su0\tsha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006"
10448 "shsub8\003smc\006smlabb\006smlabt\005smlad\006smladx\005smlal\007smlalb"
10449 "b\007smlalbt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006sm"
10450 "latt\006smlawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smm"
10451 "la\006smmlar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006"
10452 "smulbb\006smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005sm"
10453 "usd\006smusdx\006sqrshr\007sqrshrl\005sqshl\006sqshll\005srsda\005srsdb"
10454 "\005srshr\006srshrl\005srsia\005srsib\004ssat\006ssat16\004ssax\004ssbb"
10455 "\006ssub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005s"
10456 "tlex\006stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005"
10457 "stmib\003str\004strb\005strbt\004strd\005strex\006strexb\006strexd\006s"
10458 "trexh\004strh\005strht\004strt\003sub\004subs\004subw\003svc\003swp\004"
10459 "swpb\005sxtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003tbb\003t"
10460 "bh\003teq\004trap\003tsb\003tst\002tt\003tta\004ttat\003ttt\006uadd16\005"
10461 "uadd8\004uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005u"
10462 "hsax\007uhsub16\006uhsub8\005umaal\005umlal\005umull\007uqadd16\006uqad"
10463 "d8\005uqasx\006uqrshl\007uqrshll\005uqsax\005uqshl\006uqshll\007uqsub16"
10464 "\006uqsub8\005urshr\006urshrl\005usad8\006usada8\004usat\006usat16\004u"
10465 "sax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004uxtb\006uxtb16\004"
10466 "uxth\004vaba\005vabal\005vabav\004vabd\005vabdl\004vabs\005vacge\005vac"
10467 "gt\005vacle\005vaclt\004vadc\005vadci\004vadd\006vaddhn\005vaddl\006vad"
10468 "dlv\007vaddlva\005vaddv\006vaddva\005vaddw\004vand\004vbic\004vbif\004v"
10469 "bit\005vbrsr\004vbsl\005vcadd\004vceq\004vcge\004vcgt\004vcle\004vcls\004"
10470 "vclt\004vclz\005vcmla\004vcmp\005vcmpe\005vcmul\004vcnt\004vctp\004vcvt"
10471 "\005vcvta\005vcvtb\005vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vcx1"
10472 "\005vcx1a\004vcx2\005vcx2a\004vcx3\005vcx3a\005vddup\004vdiv\004vdot\004"
10473 "vdup\006vdwdup\004veor\004vext\004vfma\005vfmab\005vfmal\005vfmas\005vf"
10474 "mat\004vfms\005vfmsl\005vfnma\005vfnms\005vhadd\006vhcadd\005vhsub\005v"
10475 "idup\004vins\006viwdup\005vjcvt\004vld1\004vld2\005vld20\005vld21\004vl"
10476 "d3\004vld4\005vld40\005vld41\005vld42\005vld43\006vldmdb\006vldmia\004v"
10477 "ldr\005vldrb\005vldrd\005vldrh\005vldrw\005vlldm\005vlstm\004vmax\005vm"
10478 "axa\006vmaxav\006vmaxnm\007vmaxnma\010vmaxnmav\007vmaxnmv\005vmaxv\004v"
10479 "min\005vmina\006vminav\006vminnm\007vminnma\010vminnmav\007vminnmv\005v"
10480 "minv\004vmla\007vmladav\010vmladava\tvmladavax\010vmladavx\005vmlal\010"
10481 "vmlaldav\tvmlaldava\nvmlaldavax\tvmlaldavx\006vmlalv\007vmlalva\005vmla"
10482 "s\005vmlav\006vmlava\004vmls\007vmlsdav\010vmlsdava\tvmlsdavax\010vmlsd"
10483 "avx\005vmlsl\010vmlsldav\tvmlsldava\nvmlsldavax\tvmlsldavx\005vmmla\004"
10484 "vmov\005vmovl\006vmovlb\006vmovlt\005vmovn\006vmovnb\006vmovnt\005vmovx"
10485 "\004vmrs\004vmsr\004vmul\005vmulh\005vmull\006vmullb\006vmullt\004vmvn\004"
10486 "vneg\005vnmla\005vnmls\005vnmul\004vorn\004vorr\006vpadal\005vpadd\006v"
10487 "paddl\005vpmax\005vpmin\005vpnot\004vpop\005vpsel\004vpst\003vpt\005vpu"
10488 "sh\005vqabs\005vqadd\010vqdmladh\tvqdmladhx\007vqdmlah\007vqdmlal\010vq"
10489 "dmlash\010vqdmlsdh\tvqdmlsdhx\007vqdmlsl\007vqdmulh\007vqdmull\010vqdmu"
10490 "llb\010vqdmullt\006vqmovn\007vqmovnb\007vqmovnt\007vqmovun\010vqmovunb\010"
10491 "vqmovunt\005vqneg\tvqrdmladh\nvqrdmladhx\010vqrdmlah\tvqrdmlash\tvqrdml"
10492 "sdh\nvqrdmlsdhx\010vqrdmlsh\010vqrdmulh\006vqrshl\007vqrshrn\010vqrshrn"
10493 "b\010vqrshrnt\010vqrshrun\tvqrshrunb\tvqrshrunt\005vqshl\006vqshlu\006v"
10494 "qshrn\007vqshrnb\007vqshrnt\007vqshrun\010vqshrunb\010vqshrunt\005vqsub"
10495 "\007vraddhn\006vrecpe\006vrecps\006vrev16\006vrev32\006vrev64\006vrhadd"
10496 "\006vrinta\006vrintm\006vrintn\006vrintp\006vrintr\006vrintx\006vrintz\n"
10497 "vrmlaldavh\013vrmlaldavha\014vrmlaldavhax\013vrmlaldavhx\010vrmlalvh\tv"
10498 "rmlalvha\nvrmlsldavh\013vrmlsldavha\014vrmlsldavhax\013vrmlsldavhx\006v"
10499 "rmulh\005vrshl\005vrshr\006vrshrn\007vrshrnb\007vrshrnt\007vrsqrte\007v"
10500 "rsqrts\005vrsra\007vrsubhn\004vsbc\005vsbci\007vscclrm\005vsdot\006vsel"
10501 "eq\006vselge\006vselgt\006vselvs\004vshl\005vshlc\005vshll\006vshllb\006"
10502 "vshllt\004vshr\005vshrn\006vshrnb\006vshrnt\004vsli\006vsmmla\005vsqrt\004"
10503 "vsra\004vsri\004vst1\004vst2\005vst20\005vst21\004vst3\004vst4\005vst40"
10504 "\005vst41\005vst42\005vst43\006vstmdb\006vstmia\004vstr\005vstrb\005vst"
10505 "rd\005vstrh\005vstrw\004vsub\006vsubhn\005vsubl\005vsubw\006vsudot\004v"
10506 "swp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\006vummla\006vusdot\007vus"
10507 "mmla\004vuzp\004vzip\003wfe\003wfi\003wls\005wlstp\005yield";
10508
10509// Feature bitsets.
10510enum : uint8_t {
10511 AMFBS_None,
10512 AMFBS_Has8MSecExt,
10513 AMFBS_HasBF16,
10514 AMFBS_HasCDE,
10515 AMFBS_HasDB,
10516 AMFBS_HasDFB,
10517 AMFBS_HasDotProd,
10518 AMFBS_HasFP16,
10519 AMFBS_HasFPARMv8,
10520 AMFBS_HasFPRegs,
10521 AMFBS_HasFPRegs16,
10522 AMFBS_HasFPRegs64,
10523 AMFBS_HasFPRegsV8_1M,
10524 AMFBS_HasFullFP16,
10525 AMFBS_HasMVEFloat,
10526 AMFBS_HasMVEInt,
10527 AMFBS_HasMatMulInt8,
10528 AMFBS_HasNEON,
10529 AMFBS_HasV8_1MMainline,
10530 AMFBS_HasVFP2,
10531 AMFBS_HasVFP3,
10532 AMFBS_HasVFP4,
10533 AMFBS_IsARM,
10534 AMFBS_IsThumb,
10535 AMFBS_IsThumb2,
10536 AMFBS_HasBF16_HasNEON,
10537 AMFBS_HasCDE_HasFPRegs,
10538 AMFBS_HasCDE_HasMVEInt,
10539 AMFBS_HasDB_IsThumb2,
10540 AMFBS_HasDSP_IsThumb2,
10541 AMFBS_HasFPARMv8_HasDPVFP,
10542 AMFBS_HasFPARMv8_HasNEON,
10543 AMFBS_HasFPARMv8_HasV8_3a,
10544 AMFBS_HasFPRegs_HasV8_1MMainline,
10545 AMFBS_HasMVEInt_IsThumb,
10546 AMFBS_HasNEON_HasFP16,
10547 AMFBS_HasNEON_HasFP16FML,
10548 AMFBS_HasNEON_HasFullFP16,
10549 AMFBS_HasNEON_HasV8_1a,
10550 AMFBS_HasNEON_HasV8_3a,
10551 AMFBS_HasNEON_HasVFP4,
10552 AMFBS_HasV7_IsMClass,
10553 AMFBS_HasV8_HasAES,
10554 AMFBS_HasV8_HasNEON,
10555 AMFBS_HasV8_HasSHA2,
10556 AMFBS_HasV8MMainline_Has8MSecExt,
10557 AMFBS_HasV8_1MMainline_Has8MSecExt,
10558 AMFBS_HasV8_1MMainline_HasFPRegs,
10559 AMFBS_HasV8_1MMainline_HasMVEInt,
10560 AMFBS_HasVFP2_HasDPVFP,
10561 AMFBS_HasVFP3_HasDPVFP,
10562 AMFBS_HasVFP4_HasDPVFP,
10563 AMFBS_IsARM_HasAcquireRelease,
10564 AMFBS_IsARM_HasCRC,
10565 AMFBS_IsARM_HasDB,
10566 AMFBS_IsARM_HasDFB,
10567 AMFBS_IsARM_HasDivideInARM,
10568 AMFBS_IsARM_HasRAS,
10569 AMFBS_IsARM_HasSB,
10570 AMFBS_IsARM_HasTrustZone,
10571 AMFBS_IsARM_HasV4T,
10572 AMFBS_IsARM_HasV5T,
10573 AMFBS_IsARM_HasV5TE,
10574 AMFBS_IsARM_HasV6,
10575 AMFBS_IsARM_HasV6K,
10576 AMFBS_IsARM_HasV6T2,
10577 AMFBS_IsARM_HasV7,
10578 AMFBS_IsARM_HasV8,
10579 AMFBS_IsARM_HasV8_4a,
10580 AMFBS_IsARM_HasVirtualization,
10581 AMFBS_IsARM_PreV8,
10582 AMFBS_IsARM_UseNaClTrap,
10583 AMFBS_IsARM_UseNegativeImmediates,
10584 AMFBS_IsThumb_Has8MSecExt,
10585 AMFBS_IsThumb_HasAcquireRelease,
10586 AMFBS_IsThumb_HasDB,
10587 AMFBS_IsThumb_HasV5T,
10588 AMFBS_IsThumb_HasV6,
10589 AMFBS_IsThumb_HasV6M,
10590 AMFBS_IsThumb_HasV7Clrex,
10591 AMFBS_IsThumb_HasV8,
10592 AMFBS_IsThumb_HasV8MBaseline,
10593 AMFBS_IsThumb_HasV8_4a,
10594 AMFBS_IsThumb_HasVirtualization,
10595 AMFBS_IsThumb_IsMClass,
10596 AMFBS_IsThumb_IsNotMClass,
10597 AMFBS_IsThumb_UseNegativeImmediates,
10598 AMFBS_IsThumb2_HasCRC,
10599 AMFBS_IsThumb2_HasDSP,
10600 AMFBS_IsThumb2_HasRAS,
10601 AMFBS_IsThumb2_HasSB,
10602 AMFBS_IsThumb2_HasTrustZone,
10603 AMFBS_IsThumb2_HasV7,
10604 AMFBS_IsThumb2_HasV8,
10605 AMFBS_IsThumb2_HasVirtualization,
10606 AMFBS_IsThumb2_IsNotMClass,
10607 AMFBS_IsThumb2_PreV8,
10608 AMFBS_IsThumb2_UseNegativeImmediates,
10609 AMFBS_PreV8_IsThumb2,
10610 AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline,
10611 AMFBS_HasFPARMv8_HasNEON_HasFullFP16,
10612 AMFBS_HasNEON_HasV8_3a_HasFullFP16,
10613 AMFBS_HasV8_HasNEON_HasFullFP16,
10614 AMFBS_IsARM_HasAcquireRelease_HasV7Clrex,
10615 AMFBS_IsARM_HasV7_HasMP,
10616 AMFBS_IsARM_HasV8_HasCLRBHB,
10617 AMFBS_IsARM_HasV8_HasV8_1a,
10618 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex,
10619 AMFBS_IsThumb_HasV5T_IsNotMClass,
10620 AMFBS_IsThumb2_HasV7_HasMP,
10621 AMFBS_IsThumb2_HasV8_HasCLRBHB,
10622 AMFBS_IsThumb2_HasV8_HasV8_1a,
10623 AMFBS_IsThumb2_HasV8_1MMainline_HasLOB,
10624 AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI,
10625 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass,
10626};
10627
10628static constexpr FeatureBitset FeatureBitsets[] = {
10629 {}, // AMFBS_None
10630 {Feature_Has8MSecExtBit, },
10631 {Feature_HasBF16Bit, },
10632 {Feature_HasCDEBit, },
10633 {Feature_HasDBBit, },
10634 {Feature_HasDFBBit, },
10635 {Feature_HasDotProdBit, },
10636 {Feature_HasFP16Bit, },
10637 {Feature_HasFPARMv8Bit, },
10638 {Feature_HasFPRegsBit, },
10639 {Feature_HasFPRegs16Bit, },
10640 {Feature_HasFPRegs64Bit, },
10641 {Feature_HasFPRegsV8_1MBit, },
10642 {Feature_HasFullFP16Bit, },
10643 {Feature_HasMVEFloatBit, },
10644 {Feature_HasMVEIntBit, },
10645 {Feature_HasMatMulInt8Bit, },
10646 {Feature_HasNEONBit, },
10647 {Feature_HasV8_1MMainlineBit, },
10648 {Feature_HasVFP2Bit, },
10649 {Feature_HasVFP3Bit, },
10650 {Feature_HasVFP4Bit, },
10651 {Feature_IsARMBit, },
10652 {Feature_IsThumbBit, },
10653 {Feature_IsThumb2Bit, },
10654 {Feature_HasBF16Bit, Feature_HasNEONBit, },
10655 {Feature_HasCDEBit, Feature_HasFPRegsBit, },
10656 {Feature_HasCDEBit, Feature_HasMVEIntBit, },
10657 {Feature_HasDBBit, Feature_IsThumb2Bit, },
10658 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
10659 {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, },
10660 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
10661 {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, },
10662 {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, },
10663 {Feature_HasMVEIntBit, Feature_IsThumbBit, },
10664 {Feature_HasNEONBit, Feature_HasFP16Bit, },
10665 {Feature_HasNEONBit, Feature_HasFP16FMLBit, },
10666 {Feature_HasNEONBit, Feature_HasFullFP16Bit, },
10667 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
10668 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
10669 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
10670 {Feature_HasV7Bit, Feature_IsMClassBit, },
10671 {Feature_HasV8Bit, Feature_HasAESBit, },
10672 {Feature_HasV8Bit, Feature_HasNEONBit, },
10673 {Feature_HasV8Bit, Feature_HasSHA2Bit, },
10674 {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, },
10675 {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, },
10676 {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, },
10677 {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, },
10678 {Feature_HasVFP2Bit, Feature_HasDPVFPBit, },
10679 {Feature_HasVFP3Bit, Feature_HasDPVFPBit, },
10680 {Feature_HasVFP4Bit, Feature_HasDPVFPBit, },
10681 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, },
10682 {Feature_IsARMBit, Feature_HasCRCBit, },
10683 {Feature_IsARMBit, Feature_HasDBBit, },
10684 {Feature_IsARMBit, Feature_HasDFBBit, },
10685 {Feature_IsARMBit, Feature_HasDivideInARMBit, },
10686 {Feature_IsARMBit, Feature_HasRASBit, },
10687 {Feature_IsARMBit, Feature_HasSBBit, },
10688 {Feature_IsARMBit, Feature_HasTrustZoneBit, },
10689 {Feature_IsARMBit, Feature_HasV4TBit, },
10690 {Feature_IsARMBit, Feature_HasV5TBit, },
10691 {Feature_IsARMBit, Feature_HasV5TEBit, },
10692 {Feature_IsARMBit, Feature_HasV6Bit, },
10693 {Feature_IsARMBit, Feature_HasV6KBit, },
10694 {Feature_IsARMBit, Feature_HasV6T2Bit, },
10695 {Feature_IsARMBit, Feature_HasV7Bit, },
10696 {Feature_IsARMBit, Feature_HasV8Bit, },
10697 {Feature_IsARMBit, Feature_HasV8_4aBit, },
10698 {Feature_IsARMBit, Feature_HasVirtualizationBit, },
10699 {Feature_IsARMBit, Feature_PreV8Bit, },
10700 {Feature_IsARMBit, Feature_UseNaClTrapBit, },
10701 {Feature_IsARMBit, Feature_UseNegativeImmediatesBit, },
10702 {Feature_IsThumbBit, Feature_Has8MSecExtBit, },
10703 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, },
10704 {Feature_IsThumbBit, Feature_HasDBBit, },
10705 {Feature_IsThumbBit, Feature_HasV5TBit, },
10706 {Feature_IsThumbBit, Feature_HasV6Bit, },
10707 {Feature_IsThumbBit, Feature_HasV6MBit, },
10708 {Feature_IsThumbBit, Feature_HasV7ClrexBit, },
10709 {Feature_IsThumbBit, Feature_HasV8Bit, },
10710 {Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
10711 {Feature_IsThumbBit, Feature_HasV8_4aBit, },
10712 {Feature_IsThumbBit, Feature_HasVirtualizationBit, },
10713 {Feature_IsThumbBit, Feature_IsMClassBit, },
10714 {Feature_IsThumbBit, Feature_IsNotMClassBit, },
10715 {Feature_IsThumbBit, Feature_UseNegativeImmediatesBit, },
10716 {Feature_IsThumb2Bit, Feature_HasCRCBit, },
10717 {Feature_IsThumb2Bit, Feature_HasDSPBit, },
10718 {Feature_IsThumb2Bit, Feature_HasRASBit, },
10719 {Feature_IsThumb2Bit, Feature_HasSBBit, },
10720 {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, },
10721 {Feature_IsThumb2Bit, Feature_HasV7Bit, },
10722 {Feature_IsThumb2Bit, Feature_HasV8Bit, },
10723 {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, },
10724 {Feature_IsThumb2Bit, Feature_IsNotMClassBit, },
10725 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
10726 {Feature_IsThumb2Bit, Feature_UseNegativeImmediatesBit, },
10727 {Feature_PreV8Bit, Feature_IsThumb2Bit, },
10728 {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
10729 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, },
10730 {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, },
10731 {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, },
10732 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, },
10733 {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, },
10734 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCLRBHBBit, },
10735 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, },
10736 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, },
10737 {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, },
10738 {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, },
10739 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCLRBHBBit, },
10740 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, },
10741 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, },
10742 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, },
10743 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, },
10744};
10745
10746namespace {
10747 struct MatchEntry {
10748 uint16_t Mnemonic;
10749 uint16_t Opcode;
10750 uint16_t ConvertFn;
10751 uint8_t RequiredFeaturesIdx;
10752 uint16_t Classes[18];
10753 StringRef getMnemonic() const {
10754 return StringRef(MnemonicTable + Mnemonic + 1,
10755 MnemonicTable[Mnemonic]);
10756 }
10757 };
10758
10759 // Predicate for searching for an opcode.
10760 struct LessOpcode {
10761 bool operator()(const MatchEntry &LHS, StringRef RHS) {
10762 return LHS.getMnemonic() < RHS;
10763 }
10764 bool operator()(StringRef LHS, const MatchEntry &RHS) {
10765 return LHS < RHS.getMnemonic();
10766 }
10767 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
10768 return LHS.getMnemonic() < RHS.getMnemonic();
10769 }
10770 };
10771} // end anonymous namespace
10772
10773static const MatchEntry MatchTable0[] = {
10774 { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, AMFBS_IsThumb, { }, },
10775 { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10776 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10777 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10778 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10779 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10780 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10781 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10782 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10783 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10784 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10785 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10786 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10787 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10788 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10789 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10790 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10791 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10792 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10793 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10794 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
10795 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10796 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10797 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10798 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10799 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10800 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10801 { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, },
10802 { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
10803 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
10804 { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10805 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10806 { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255Expr }, },
10807 { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
10808 { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
10809 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
10810 { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, },
10811 { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, },
10812 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
10813 { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
10814 { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
10815 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
10816 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10817 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
10818 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, },
10819 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, },
10820 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, },
10821 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, },
10822 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10823 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10824 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10825 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
10826 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10827 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10828 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10829 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
10830 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10831 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10832 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
10833 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10834 { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, },
10835 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
10836 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
10837 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, },
10838 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImmNeg }, },
10839 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNeg }, },
10840 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
10841 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10842 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10843 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
10844 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10845 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10846 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
10847 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
10848 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10849 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10850 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
10851 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10852 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10853 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
10854 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10855 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10856 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
10857 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10858 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10859 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
10860 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
10861 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
10862 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10863 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
10864 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, },
10865 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
10866 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10867 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_4095Neg }, },
10868 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
10869 { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, },
10870 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10871 { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, },
10872 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, },
10873 { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10874 { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10875 { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10876 { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10877 { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10878 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10879 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10880 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10881 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10882 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10883 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10884 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10885 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10886 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10887 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10888 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10889 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10890 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
10891 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10892 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10893 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10894 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10895 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10896 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10897 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10898 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10899 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10900 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10901 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10902 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10903 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10904 { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10905 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
10906 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
10907 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10908 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
10909 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10910 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
10911 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10912 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
10913 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10914 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10915 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10916 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
10917 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10918 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10919 { 58 /* asrl */, ARM::MVE_ASRLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, },
10920 { 58 /* asrl */, ARM::MVE_ASRLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
10921 { 63 /* aut */, ARM::t2AUT, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
10922 { 63 /* aut */, ARM::t2HINT, Convert__imm_95_45__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
10923 { 67 /* autg */, ARM::t2AUTG, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_GPRnopc, MCK_GPRnopc }, },
10924 { 72 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm }, },
10925 { 72 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
10926 { 72 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10927 { 72 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
10928 { 72 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
10929 { 74 /* bf */, ARM::t2BFi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, },
10930 { 77 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, },
10931 { 77 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, },
10932 { 81 /* bfcsel */, ARM::t2BFic, Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_CondCodeNoAL }, },
10933 { 88 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, },
10934 { 88 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, },
10935 { 92 /* bfl */, ARM::t2BFLi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, },
10936 { 96 /* bflx */, ARM::t2BFLr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, },
10937 { 101 /* bfx */, ARM::t2BFr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, },
10938 { 105 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10939 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10940 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10941 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10942 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10943 { 105 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10944 { 105 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10945 { 105 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10946 { 105 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10947 { 105 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10948 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10949 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10950 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10951 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
10952 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10953 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10954 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10955 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10956 { 105 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10957 { 105 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10958 { 105 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10959 { 105 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10960 { 105 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10961 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10962 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10963 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10964 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10965 { 109 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, AMFBS_IsThumb, { }, },
10966 { 109 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, },
10967 { 109 /* bkpt */, ARM::BKPT, Convert__imm_95_0, AMFBS_IsARM, { }, },
10968 { 109 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
10969 { 114 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, AMFBS_IsARM, { MCK_ARMBranchTarget }, },
10970 { 114 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10971 { 114 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
10972 { 114 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
10973 { 117 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_HasV5T, { MCK_CondCode, MCK_GPR }, },
10974 { 117 /* blx */, ARM::BLX, Convert__Reg1_0, AMFBS_IsARM_HasV5T, { MCK_GPR }, },
10975 { 117 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, AMFBS_IsARM_HasV5T, { MCK_ThumbBranchTarget }, },
10976 { 117 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR }, },
10977 { 117 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, AMFBS_IsThumb_HasV5T_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, },
10978 { 121 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
10979 { 127 /* bti */, ARM::t2BTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { }, },
10980 { 127 /* bti */, ARM::t2HINT, Convert__imm_95_15__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, },
10981 { 131 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR }, },
10982 { 131 /* bx */, ARM::BX, Convert__Reg1_0, AMFBS_IsARM_HasV4T, { MCK_GPR }, },
10983 { 131 /* bx */, ARM::BX_RET, Convert__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPRlr }, },
10984 { 131 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPR }, },
10985 { 134 /* bxaut */, ARM::t2BXAUT, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_rGPR, MCK_GPRnopc }, },
10986 { 140 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, },
10987 { 140 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR }, },
10988 { 144 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPR }, },
10989 { 149 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
10990 { 154 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
10991 { 158 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10992 { 158 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10993 { 162 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10994 { 162 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10995 { 167 /* cinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10996 { 172 /* cinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10997 { 177 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8_HasCLRBHB, { MCK_CondCode }, },
10998 { 177 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8_HasCLRBHB, { MCK_CondCode }, },
10999 { 177 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, },
11000 { 177 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11001 { 184 /* clrex */, ARM::CLREX, Convert_NoOperands, AMFBS_IsARM_HasV6K, { }, },
11002 { 184 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, AMFBS_IsThumb_HasV7Clrex, { MCK_CondCode }, },
11003 { 190 /* clrm */, ARM::t2CLRM, Convert__CondCode2_0__RegListWithAPSR1_1, AMFBS_HasV8_1MMainline, { MCK_CondCode, MCK_RegListWithAPSR }, },
11004 { 195 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11005 { 195 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11006 { 199 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11007 { 199 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
11008 { 199 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
11009 { 199 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
11010 { 199 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
11011 { 199 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11012 { 199 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
11013 { 199 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11014 { 199 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11015 { 199 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11016 { 199 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
11017 { 199 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
11018 { 199 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
11019 { 203 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11020 { 203 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
11021 { 203 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11022 { 203 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
11023 { 203 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
11024 { 203 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
11025 { 203 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11026 { 203 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
11027 { 203 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11028 { 203 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11029 { 203 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11030 { 203 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
11031 { 203 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
11032 { 203 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
11033 { 207 /* cneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
11034 { 212 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsThumb, { MCK_Imm, MCK_ProcIFlags }, },
11035 { 212 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm0_31 }, },
11036 { 212 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11037 { 212 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, },
11038 { 212 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags }, },
11039 { 212 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, },
11040 { 212 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, },
11041 { 212 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, },
11042 { 212 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, AMFBS_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, },
11043 { 216 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11044 { 216 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11045 { 223 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11046 { 223 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11047 { 231 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11048 { 231 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11049 { 239 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11050 { 239 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11051 { 247 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11052 { 247 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11053 { 254 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11054 { 254 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11055 { 261 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
11056 { 261 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, },
11057 { 261 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11058 { 266 /* csel */, ARM::t2CSEL, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
11059 { 271 /* cset */, ARM::t2CSINC, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, },
11060 { 276 /* csetm */, ARM::t2CSINV, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, },
11061 { 282 /* csinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
11062 { 288 /* csinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
11063 { 294 /* csneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
11064 { 300 /* cx1 */, ARM::CDE_CX1, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, },
11065 { 304 /* cx1a */, ARM::CDE_CX1A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, },
11066 { 309 /* cx1d */, ARM::CDE_CX1D, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, },
11067 { 314 /* cx1da */, ARM::CDE_CX1DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, },
11068 { 320 /* cx2 */, ARM::CDE_CX2, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
11069 { 324 /* cx2a */, ARM::CDE_CX2A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
11070 { 329 /* cx2d */, ARM::CDE_CX2D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
11071 { 334 /* cx2da */, ARM::CDE_CX2DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
11072 { 340 /* cx3 */, ARM::CDE_CX3, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
11073 { 344 /* cx3a */, ARM::CDE_CX3A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
11074 { 349 /* cx3d */, ARM::CDE_CX3D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
11075 { 354 /* cx3da */, ARM::CDE_CX3DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
11076 { 360 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasV7, { MCK_CondCode, MCK_Imm0_15 }, },
11077 { 360 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, },
11078 { 360 /* dbg */, ARM::t2DBG, Convert__Imm0_151_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_15 }, },
11079 { 364 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11080 { 370 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11081 { 376 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11082 { 382 /* dfb */, ARM::DSB, Convert__imm_95_12, AMFBS_IsARM_HasDFB, { }, },
11083 { 382 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, AMFBS_HasDFB, { MCK_CondCode }, },
11084 { 386 /* dls */, ARM::t2DLS, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR }, },
11085 { 390 /* dlstp */, ARM::MVE_DLSTP_16, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR }, },
11086 { 390 /* dlstp */, ARM::MVE_DLSTP_32, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR }, },
11087 { 390 /* dlstp */, ARM::MVE_DLSTP_64, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR }, },
11088 { 390 /* dlstp */, ARM::MVE_DLSTP_8, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR }, },
11089 { 396 /* dmb */, ARM::DMB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
11090 { 396 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
11091 { 396 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, },
11092 { 396 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
11093 { 396 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
11094 { 396 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, },
11095 { 400 /* dsb */, ARM::DSB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
11096 { 400 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
11097 { 400 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, },
11098 { 400 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
11099 { 400 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
11100 { 400 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, },
11101 { 404 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11102 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11103 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11104 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11105 { 404 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11106 { 404 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11107 { 404 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11108 { 404 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11109 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11110 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11111 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11112 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11113 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11114 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11115 { 404 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11116 { 404 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11117 { 404 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11118 { 404 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11119 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11120 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11121 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11122 { 408 /* eret */, ARM::ERET, Convert__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode }, },
11123 { 408 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2_HasVirtualization, { MCK_CondCode }, },
11124 { 413 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsARM_HasRAS, { MCK_CondCode }, },
11125 { 413 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode }, },
11126 { 413 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode, MCK__DOT_w }, },
11127 { 417 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11128 { 423 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
11129 { 429 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR }, },
11130 { 436 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR }, },
11131 { 443 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, },
11132 { 451 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, },
11133 { 459 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
11134 { 467 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
11135 { 467 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
11136 { 475 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
11137 { 481 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
11138 { 487 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode }, },
11139 { 494 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
11140 { 502 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
11141 { 502 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
11142 { 510 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11143 { 516 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
11144 { 522 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, },
11145 { 522 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_Imm0_239 }, },
11146 { 522 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, },
11147 { 522 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, },
11148 { 527 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, AMFBS_IsThumb_HasV8, { MCK_Imm0_63 }, },
11149 { 527 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, AMFBS_IsARM_HasV8, { MCK_Imm0_65535 }, },
11150 { 531 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, AMFBS_IsARM_HasVirtualization, { MCK_Imm0_65535 }, },
11151 { 531 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, AMFBS_IsThumb2, { MCK_Imm0_65535 }, },
11152 { 531 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, AMFBS_IsThumb2_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, },
11153 { 535 /* isb */, ARM::ISB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
11154 { 535 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
11155 { 535 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_InstSyncBarrierOpt }, },
11156 { 535 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
11157 { 535 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, },
11158 { 535 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_InstSyncBarrierOpt }, },
11159 { 539 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, },
11160 { 539 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsARM, { MCK_ITMask, MCK_ITCondCode }, },
11161 { 542 /* lctp */, ARM::MVE_LCTP, Convert__CondCode2_0, AMFBS_HasMVEInt, { MCK_CondCode }, },
11162 { 547 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11163 { 547 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11164 { 551 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11165 { 551 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11166 { 556 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11167 { 556 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11168 { 562 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11169 { 562 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11170 { 569 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
11171 { 569 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11172 { 576 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11173 { 576 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11174 { 583 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11175 { 583 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11176 { 588 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11177 { 588 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11178 { 588 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11179 { 588 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11180 { 588 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11181 { 588 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11182 { 588 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11183 { 588 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11184 { 592 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11185 { 592 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11186 { 592 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11187 { 592 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11188 { 592 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11189 { 592 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11190 { 592 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11191 { 592 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11192 { 597 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11193 { 597 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11194 { 597 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11195 { 597 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11196 { 597 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11197 { 597 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11198 { 597 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11199 { 597 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11200 { 603 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11201 { 603 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11202 { 603 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11203 { 603 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11204 { 603 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11205 { 603 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11206 { 603 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11207 { 603 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11208 { 608 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, },
11209 { 608 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
11210 { 608 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11211 { 608 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11212 { 608 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11213 { 608 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11214 { 608 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11215 { 608 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11216 { 608 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11217 { 608 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11218 { 612 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11219 { 612 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11220 { 612 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11221 { 612 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11222 { 618 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11223 { 618 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11224 { 618 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11225 { 618 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11226 { 618 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11227 { 618 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11228 { 618 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11229 { 618 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11230 { 624 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11231 { 624 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11232 { 624 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11233 { 624 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11234 { 630 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, },
11235 { 630 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
11236 { 630 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11237 { 630 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
11238 { 630 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, },
11239 { 630 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, },
11240 { 630 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
11241 { 630 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
11242 { 630 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
11243 { 630 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
11244 { 630 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
11245 { 630 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
11246 { 630 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
11247 { 630 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, },
11248 { 630 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, },
11249 { 630 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, },
11250 { 630 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
11251 { 630 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
11252 { 630 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, },
11253 { 630 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11254 { 630 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11255 { 630 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11256 { 630 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11257 { 630 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11258 { 630 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11259 { 630 /* ldr */, ARM::t2LDR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11260 { 630 /* ldr */, ARM::t2LDR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11261 { 634 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
11262 { 634 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11263 { 634 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
11264 { 634 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11265 { 634 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11266 { 634 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
11267 { 634 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
11268 { 634 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
11269 { 634 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11270 { 634 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
11271 { 634 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
11272 { 634 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
11273 { 634 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11274 { 634 /* ldrb */, ARM::t2LDRB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11275 { 634 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11276 { 634 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11277 { 634 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11278 { 634 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11279 { 634 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11280 { 634 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11281 { 634 /* ldrb */, ARM::t2LDRB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11282 { 634 /* ldrb */, ARM::t2LDRB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11283 { 639 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11284 { 639 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11285 { 639 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11286 { 639 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11287 { 645 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
11288 { 645 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
11289 { 645 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
11290 { 645 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11291 { 645 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11292 { 645 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11293 { 650 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
11294 { 650 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11295 { 656 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11296 { 656 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11297 { 663 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
11298 { 663 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11299 { 670 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11300 { 670 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11301 { 677 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
11302 { 677 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11303 { 677 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
11304 { 677 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11305 { 677 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11306 { 677 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
11307 { 677 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11308 { 677 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
11309 { 677 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
11310 { 677 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
11311 { 677 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
11312 { 677 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11313 { 677 /* ldrh */, ARM::t2LDRH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11314 { 677 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11315 { 677 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11316 { 677 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11317 { 677 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11318 { 677 /* ldrh */, ARM::t2LDRH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11319 { 677 /* ldrh */, ARM::t2LDRH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11320 { 682 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11321 { 682 /* ldrht */, ARM::LDRHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11322 { 682 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
11323 { 682 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
11324 { 688 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11325 { 688 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
11326 { 688 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11327 { 688 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11328 { 688 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
11329 { 688 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11330 { 688 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
11331 { 688 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
11332 { 688 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
11333 { 688 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
11334 { 688 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11335 { 688 /* ldrsb */, ARM::t2LDRSB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11336 { 688 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11337 { 688 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11338 { 688 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11339 { 688 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11340 { 688 /* ldrsb */, ARM::t2LDRSB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11341 { 688 /* ldrsb */, ARM::t2LDRSB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11342 { 694 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11343 { 694 /* ldrsbt */, ARM::LDRSBTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11344 { 694 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
11345 { 694 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
11346 { 701 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11347 { 701 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
11348 { 701 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11349 { 701 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11350 { 701 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
11351 { 701 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11352 { 701 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
11353 { 701 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
11354 { 701 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
11355 { 701 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
11356 { 701 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
11357 { 701 /* ldrsh */, ARM::t2LDRSH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11358 { 701 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11359 { 701 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11360 { 701 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11361 { 701 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11362 { 701 /* ldrsh */, ARM::t2LDRSH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11363 { 701 /* ldrsh */, ARM::t2LDRSH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11364 { 707 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11365 { 707 /* ldrsht */, ARM::LDRSHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11366 { 707 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
11367 { 707 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
11368 { 714 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11369 { 714 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11370 { 714 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11371 { 714 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11372 { 719 /* le */, ARM::t2LE, Convert__LELabel1_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_LELabel }, },
11373 { 719 /* le */, ARM::t2LEUpdate, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_LELabel }, },
11374 { 722 /* letp */, ARM::MVE_LETP, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_HasMVEInt, { MCK_GPRlr, MCK_LELabel }, },
11375 { 727 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11376 { 727 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, },
11377 { 727 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, },
11378 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11379 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
11380 { 727 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11381 { 727 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
11382 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11383 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
11384 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11385 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11386 { 727 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, },
11387 { 727 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11388 { 727 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
11389 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11390 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11391 { 727 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, },
11392 { 731 /* lsll */, ARM::MVE_LSLLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, },
11393 { 731 /* lsll */, ARM::MVE_LSLLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11394 { 736 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11395 { 736 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
11396 { 736 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
11397 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11398 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
11399 { 736 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11400 { 736 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
11401 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11402 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
11403 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11404 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
11405 { 736 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11406 { 736 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
11407 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11408 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
11409 { 740 /* lsrl */, ARM::MVE_LSRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11410 { 745 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11411 { 745 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11412 { 745 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11413 { 745 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11414 { 749 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11415 { 749 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11416 { 749 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11417 { 749 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11418 { 754 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11419 { 754 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11420 { 759 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11421 { 759 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11422 { 765 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11423 { 765 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11424 { 765 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11425 { 769 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11426 { 769 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11427 { 773 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11428 { 773 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255Expr }, },
11429 { 773 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
11430 { 773 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, },
11431 { 773 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11432 { 773 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
11433 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11434 { 773 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11435 { 773 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
11436 { 773 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, },
11437 { 773 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
11438 { 773 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11439 { 773 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11440 { 773 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11441 { 773 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11442 { 773 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11443 { 773 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
11444 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11445 { 773 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
11446 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11447 { 773 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
11448 { 777 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb, { MCK_tGPR, MCK_tGPR }, },
11449 { 777 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0, AMFBS_IsThumb, { MCK_tGPR, MCK_Imm0_255Expr }, },
11450 { 777 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
11451 { 777 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11452 { 777 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
11453 { 777 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11454 { 777 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11455 { 777 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_PC, MCK_GPRlr }, },
11456 { 777 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11457 { 777 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
11458 { 777 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11459 { 777 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
11460 { 782 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
11461 { 782 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, },
11462 { 787 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
11463 { 787 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
11464 { 792 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11465 { 792 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11466 { 792 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11467 { 792 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11468 { 796 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11469 { 796 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11470 { 796 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11471 { 796 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11472 { 801 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11473 { 801 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11474 { 806 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11475 { 806 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11476 { 812 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, },
11477 { 812 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, },
11478 { 812 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, },
11479 { 812 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, },
11480 { 812 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, },
11481 { 812 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, },
11482 { 812 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, },
11483 { 812 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, },
11484 { 812 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, },
11485 { 816 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, },
11486 { 816 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, },
11487 { 816 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
11488 { 816 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
11489 { 816 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, },
11490 { 816 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, },
11491 { 820 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11492 { 820 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
11493 { 820 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11494 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11495 { 820 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11496 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11497 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11498 { 824 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11499 { 824 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11500 { 824 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
11501 { 824 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11502 { 824 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11503 { 824 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11504 { 824 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11505 { 824 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11506 { 824 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11507 { 824 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11508 { 824 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11509 { 824 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11510 { 824 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11511 { 828 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11512 { 828 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11513 { 828 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11514 { 832 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__reg0, AMFBS_IsThumb, { }, },
11515 { 832 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
11516 { 832 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
11517 { 832 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, AMFBS_IsARM, { MCK_CondCode }, },
11518 { 832 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11519 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11520 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11521 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11522 { 836 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11523 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11524 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11525 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11526 { 836 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11527 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11528 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11529 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11530 { 840 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11531 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11532 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11533 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11534 { 840 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11535 { 840 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11536 { 840 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11537 { 840 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11538 { 840 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11539 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11540 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11541 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11542 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11543 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11544 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11545 { 840 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11546 { 840 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11547 { 840 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11548 { 840 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11549 { 840 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11550 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11551 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11552 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11553 { 844 /* pac */, ARM::t2PAC, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11554 { 844 /* pac */, ARM::t2HINT, Convert__imm_95_29__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11555 { 848 /* pacbti */, ARM::t2PACBTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11556 { 848 /* pacbti */, ARM::t2HINT, Convert__imm_95_13__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11557 { 855 /* pacg */, ARM::t2PACG, Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_GPRnopc }, },
11558 { 860 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11559 { 860 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11560 { 860 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, },
11561 { 860 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, },
11562 { 866 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11563 { 866 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11564 { 866 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, },
11565 { 866 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, },
11566 { 872 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, AMFBS_IsARM, { MCK_MemImm12Offset }, },
11567 { 872 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, AMFBS_IsARM, { MCK_MemRegOffset }, },
11568 { 872 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm }, },
11569 { 872 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11570 { 872 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, },
11571 { 872 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, },
11572 { 872 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, },
11573 { 872 /* pld */, ARM::t2PLDpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
11574 { 872 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11575 { 872 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11576 { 872 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11577 { 872 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, },
11578 { 876 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemImm12Offset }, },
11579 { 876 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemRegOffset }, },
11580 { 876 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11581 { 876 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, },
11582 { 876 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, },
11583 { 876 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11584 { 876 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11585 { 876 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11586 { 881 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7, { MCK_MemImm12Offset }, },
11587 { 881 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7, { MCK_MemRegOffset }, },
11588 { 881 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_Imm }, },
11589 { 881 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11590 { 881 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, },
11591 { 881 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, },
11592 { 881 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, },
11593 { 881 /* pli */, ARM::t2PLIpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
11594 { 881 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11595 { 881 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11596 { 881 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11597 { 881 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, },
11598 { 885 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, },
11599 { 885 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, },
11600 { 885 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
11601 { 885 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
11602 { 889 /* pssbb */, ARM::t2DSB, Convert__imm_95_4__imm_95_14__reg0, AMFBS_HasDB_IsThumb2, { }, },
11603 { 889 /* pssbb */, ARM::DSB, Convert__imm_95_4, AMFBS_IsARM_HasDB, { }, },
11604 { 895 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, },
11605 { 895 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, },
11606 { 895 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
11607 { 895 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
11608 { 900 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11609 { 900 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11610 { 905 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11611 { 905 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11612 { 912 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11613 { 912 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11614 { 918 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11615 { 918 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11616 { 923 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11617 { 923 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11618 { 929 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11619 { 929 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11620 { 935 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11621 { 935 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11622 { 940 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11623 { 940 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11624 { 945 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11625 { 945 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11626 { 952 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11627 { 952 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11628 { 958 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11629 { 958 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11630 { 963 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11631 { 963 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11632 { 963 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11633 { 963 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11634 { 967 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11635 { 967 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11636 { 967 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11637 { 967 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11638 { 973 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11639 { 973 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11640 { 973 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11641 { 973 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11642 { 979 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11643 { 979 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11644 { 985 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11645 { 985 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11646 { 985 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
11647 { 985 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11648 { 991 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11649 { 991 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11650 { 991 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
11651 { 991 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11652 { 997 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11653 { 997 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11654 { 1003 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11655 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11656 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
11657 { 1003 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11658 { 1003 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
11659 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11660 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
11661 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11662 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11663 { 1003 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11664 { 1003 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
11665 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11666 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11667 { 1007 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11668 { 1007 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11669 { 1011 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__HASH_0 }, },
11670 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11671 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11672 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11673 { 1011 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11674 { 1011 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11675 { 1011 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11676 { 1011 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11677 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11678 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11679 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11680 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11681 { 1011 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11682 { 1011 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11683 { 1011 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11684 { 1011 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11685 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11686 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11687 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11688 { 1015 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11689 { 1015 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11690 { 1015 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11691 { 1015 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11692 { 1015 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11693 { 1015 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11694 { 1015 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11695 { 1015 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11696 { 1019 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11697 { 1019 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11698 { 1026 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11699 { 1026 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11700 { 1032 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11701 { 1032 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11702 { 1037 /* sb */, ARM::SB, Convert_NoOperands, AMFBS_IsARM_HasSB, { }, },
11703 { 1037 /* sb */, ARM::t2SB, Convert_NoOperands, AMFBS_IsThumb2_HasSB, { }, },
11704 { 1040 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11705 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11706 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11707 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11708 { 1040 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11709 { 1040 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11710 { 1040 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11711 { 1040 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11712 { 1040 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
11713 { 1040 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11714 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11715 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11716 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11717 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11718 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11719 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11720 { 1040 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11721 { 1040 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
11722 { 1040 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11723 { 1040 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11724 { 1040 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
11725 { 1040 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11726 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11727 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11728 { 1044 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
11729 { 1044 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
11730 { 1049 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11731 { 1049 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11732 { 1054 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11733 { 1054 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11734 { 1058 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, AMFBS_IsThumb_IsNotMClass, { MCK_SetEndImm }, },
11735 { 1058 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, AMFBS_IsARM, { MCK_SetEndImm }, },
11736 { 1065 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, AMFBS_IsThumb2_HasV8_HasV8_1a, { MCK_Imm0_1 }, },
11737 { 1065 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, AMFBS_IsARM_HasV8_HasV8_1a, { MCK_Imm0_1 }, },
11738 { 1072 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
11739 { 1072 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
11740 { 1072 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11741 { 1076 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11742 { 1076 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, },
11743 { 1076 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode, MCK__DOT_w }, },
11744 { 1081 /* sg */, ARM::t2SG, Convert__CondCode2_0, AMFBS_Has8MSecExt, { MCK_CondCode }, },
11745 { 1084 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11746 { 1090 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11747 { 1096 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11748 { 1102 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11749 { 1108 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11750 { 1116 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11751 { 1124 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11752 { 1132 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11753 { 1141 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11754 { 1151 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11755 { 1161 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11756 { 1161 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11757 { 1169 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11758 { 1169 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11759 { 1176 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11760 { 1176 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11761 { 1182 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11762 { 1182 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11763 { 1188 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11764 { 1188 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11765 { 1196 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11766 { 1196 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11767 { 1203 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
11768 { 1203 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
11769 { 1207 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11770 { 1207 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11771 { 1214 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11772 { 1214 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11773 { 1221 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11774 { 1221 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11775 { 1227 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11776 { 1227 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11777 { 1234 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11778 { 1234 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11779 { 1234 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11780 { 1240 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11781 { 1240 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11782 { 1248 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11783 { 1248 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11784 { 1256 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11785 { 1256 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11786 { 1263 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11787 { 1263 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11788 { 1271 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11789 { 1271 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11790 { 1279 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11791 { 1279 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11792 { 1287 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11793 { 1287 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11794 { 1294 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11795 { 1294 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11796 { 1301 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11797 { 1301 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11798 { 1308 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11799 { 1308 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11800 { 1315 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11801 { 1315 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11802 { 1321 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11803 { 1321 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11804 { 1328 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11805 { 1328 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11806 { 1335 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11807 { 1335 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11808 { 1343 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11809 { 1343 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11810 { 1349 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11811 { 1349 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11812 { 1356 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11813 { 1356 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11814 { 1362 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11815 { 1362 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11816 { 1369 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11817 { 1369 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11818 { 1375 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11819 { 1375 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11820 { 1382 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11821 { 1382 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11822 { 1388 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11823 { 1388 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11824 { 1395 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11825 { 1395 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11826 { 1402 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11827 { 1402 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11828 { 1409 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11829 { 1409 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11830 { 1409 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11831 { 1415 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11832 { 1415 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11833 { 1422 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11834 { 1422 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11835 { 1429 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11836 { 1429 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11837 { 1436 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11838 { 1436 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11839 { 1443 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11840 { 1443 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11841 { 1449 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11842 { 1449 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11843 { 1456 /* sqrshr */, ARM::MVE_SQRSHR, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11844 { 1463 /* sqrshrl */, ARM::MVE_SQRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, },
11845 { 1471 /* sqshl */, ARM::MVE_SQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11846 { 1477 /* sqshll */, ARM::MVE_SQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11847 { 1484 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11848 { 1484 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11849 { 1484 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11850 { 1484 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11851 { 1490 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11852 { 1490 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11853 { 1490 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
11854 { 1490 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11855 { 1490 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11856 { 1490 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11857 { 1490 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11858 { 1490 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11859 { 1496 /* srshr */, ARM::MVE_SRSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11860 { 1502 /* srshrl */, ARM::MVE_SRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11861 { 1509 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11862 { 1509 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11863 { 1509 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
11864 { 1509 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11865 { 1509 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11866 { 1509 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11867 { 1509 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11868 { 1509 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11869 { 1515 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11870 { 1515 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11871 { 1515 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11872 { 1515 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11873 { 1521 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, },
11874 { 1521 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, },
11875 { 1521 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, },
11876 { 1521 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, },
11877 { 1526 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, },
11878 { 1526 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, },
11879 { 1533 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11880 { 1533 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11881 { 1538 /* ssbb */, ARM::t2DSB, Convert__imm_95_0__imm_95_14__reg0, AMFBS_HasDB_IsThumb2, { }, },
11882 { 1538 /* ssbb */, ARM::DSB, Convert__imm_95_0, AMFBS_IsARM_HasDB, { }, },
11883 { 1543 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11884 { 1543 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11885 { 1550 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11886 { 1550 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11887 { 1556 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11888 { 1556 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11889 { 1556 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11890 { 1556 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11891 { 1556 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11892 { 1556 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11893 { 1556 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11894 { 1556 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11895 { 1560 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11896 { 1560 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11897 { 1560 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11898 { 1560 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11899 { 1560 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11900 { 1560 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11901 { 1560 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11902 { 1560 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11903 { 1565 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11904 { 1565 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11905 { 1565 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11906 { 1565 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11907 { 1565 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11908 { 1565 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11909 { 1565 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11910 { 1565 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11911 { 1571 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11912 { 1571 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11913 { 1571 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11914 { 1571 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11915 { 1571 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11916 { 1571 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11917 { 1571 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11918 { 1571 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11919 { 1576 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11920 { 1576 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11921 { 1580 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11922 { 1580 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11923 { 1585 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11924 { 1585 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11925 { 1591 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11926 { 1591 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11927 { 1598 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
11928 { 1598 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11929 { 1605 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11930 { 1605 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11931 { 1612 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11932 { 1612 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11933 { 1617 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
11934 { 1617 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11935 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11936 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11937 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11938 { 1617 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11939 { 1617 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11940 { 1617 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11941 { 1617 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11942 { 1617 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11943 { 1621 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11944 { 1621 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11945 { 1621 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11946 { 1621 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11947 { 1627 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11948 { 1627 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11949 { 1627 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11950 { 1627 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11951 { 1627 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11952 { 1627 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11953 { 1627 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11954 { 1627 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11955 { 1633 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11956 { 1633 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11957 { 1633 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11958 { 1633 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11959 { 1639 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
11960 { 1639 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11961 { 1639 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
11962 { 1639 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
11963 { 1639 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
11964 { 1639 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
11965 { 1639 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
11966 { 1639 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
11967 { 1639 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
11968 { 1639 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
11969 { 1639 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11970 { 1639 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, },
11971 { 1639 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11972 { 1639 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11973 { 1639 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11974 { 1639 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11975 { 1639 /* str */, ARM::t2STR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11976 { 1639 /* str */, ARM::t2STR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11977 { 1643 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
11978 { 1643 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11979 { 1643 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
11980 { 1643 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11981 { 1643 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11982 { 1643 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
11983 { 1643 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
11984 { 1643 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
11985 { 1643 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
11986 { 1643 /* strb */, ARM::t2STRB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11987 { 1643 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11988 { 1643 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11989 { 1643 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11990 { 1643 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11991 { 1643 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11992 { 1643 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11993 { 1643 /* strb */, ARM::t2STRB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11994 { 1643 /* strb */, ARM::t2STRB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11995 { 1648 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11996 { 1648 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11997 { 1648 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11998 { 1648 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11999 { 1654 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
12000 { 1654 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
12001 { 1654 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
12002 { 1654 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
12003 { 1654 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
12004 { 1654 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
12005 { 1659 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
12006 { 1659 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
12007 { 1665 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
12008 { 1665 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
12009 { 1672 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
12010 { 1672 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
12011 { 1679 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
12012 { 1679 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
12013 { 1686 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
12014 { 1686 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
12015 { 1686 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
12016 { 1686 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
12017 { 1686 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
12018 { 1686 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
12019 { 1686 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
12020 { 1686 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
12021 { 1686 /* strh */, ARM::t2STRH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
12022 { 1686 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
12023 { 1686 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
12024 { 1686 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
12025 { 1686 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
12026 { 1686 /* strh */, ARM::t2STRH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
12027 { 1686 /* strh */, ARM::t2STRH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
12028 { 1691 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
12029 { 1691 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
12030 { 1691 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, },
12031 { 1697 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
12032 { 1697 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
12033 { 1697 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
12034 { 1697 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
12035 { 1702 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
12036 { 1702 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
12037 { 1702 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
12038 { 1702 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
12039 { 1702 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
12040 { 1702 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
12041 { 1702 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
12042 { 1702 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
12043 { 1702 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
12044 { 1702 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
12045 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, },
12046 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
12047 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
12048 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
12049 { 1702 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
12050 { 1702 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
12051 { 1702 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
12052 { 1702 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
12053 { 1702 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
12054 { 1702 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
12055 { 1702 /* sub */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
12056 { 1702 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
12057 { 1702 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
12058 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, },
12059 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
12060 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
12061 { 1702 /* sub */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
12062 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
12063 { 1702 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
12064 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
12065 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
12066 { 1702 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
12067 { 1702 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
12068 { 1702 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
12069 { 1702 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
12070 { 1702 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
12071 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
12072 { 1702 /* sub */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
12073 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
12074 { 1702 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
12075 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
12076 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
12077 { 1706 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_GPRlr, MCK_Imm0_255 }, },
12078 { 1711 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
12079 { 1711 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
12080 { 1711 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
12081 { 1711 /* subw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
12082 { 1711 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
12083 { 1711 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
12084 { 1716 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, },
12085 { 1716 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_Imm24bit }, },
12086 { 1720 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
12087 { 1724 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
12088 { 1729 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12089 { 1729 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
12090 { 1729 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12091 { 1729 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
12092 { 1735 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12093 { 1735 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
12094 { 1735 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12095 { 1735 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
12096 { 1743 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12097 { 1743 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
12098 { 1743 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12099 { 1743 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
12100 { 1749 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
12101 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12102 { 1749 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
12103 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
12104 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12105 { 1749 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
12106 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12107 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12108 { 1754 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
12109 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12110 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12111 { 1754 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
12112 { 1761 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
12113 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12114 { 1761 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
12115 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
12116 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12117 { 1761 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
12118 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12119 { 1766 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBB }, },
12120 { 1770 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBH }, },
12121 { 1774 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12122 { 1774 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
12123 { 1774 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
12124 { 1774 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
12125 { 1774 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
12126 { 1774 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
12127 { 1774 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
12128 { 1774 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
12129 { 1774 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
12130 { 1774 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
12131 { 1778 /* trap */, ARM::tTRAP, Convert_NoOperands, AMFBS_IsThumb, { }, },
12132 { 1778 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, AMFBS_IsARM_UseNaClTrap, { }, },
12133 { 1778 /* trap */, ARM::TRAP, Convert_NoOperands, AMFBS_IsARM, { }, },
12134 { 1783 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, AMFBS_IsARM_HasV8_4a, { MCK_TraceSyncBarrierOpt }, },
12135 { 1783 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, },
12136 { 1787 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
12137 { 1787 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12138 { 1787 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
12139 { 1787 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
12140 { 1787 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
12141 { 1787 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
12142 { 1787 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
12143 { 1787 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
12144 { 1787 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
12145 { 1787 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
12146 { 1787 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
12147 { 1791 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
12148 { 1794 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
12149 { 1798 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
12150 { 1803 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
12151 { 1807 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12152 { 1807 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12153 { 1814 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12154 { 1814 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12155 { 1820 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12156 { 1820 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12157 { 1825 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
12158 { 1825 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
12159 { 1830 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, },
12160 { 1830 /* udf */, ARM::UDF, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
12161 { 1830 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, },
12162 { 1834 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12163 { 1834 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
12164 { 1839 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12165 { 1839 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12166 { 1847 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12167 { 1847 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12168 { 1854 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12169 { 1854 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12170 { 1860 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12171 { 1860 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12172 { 1866 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12173 { 1866 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12174 { 1874 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12175 { 1874 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12176 { 1881 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12177 { 1881 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
12178 { 1887 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12179 { 1887 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
12180 { 1887 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
12181 { 1893 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12182 { 1893 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
12183 { 1893 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
12184 { 1899 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12185 { 1899 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12186 { 1907 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12187 { 1907 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12188 { 1914 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12189 { 1914 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12190 { 1920 /* uqrshl */, ARM::MVE_UQRSHL, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12191 { 1927 /* uqrshll */, ARM::MVE_UQRSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, },
12192 { 1935 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12193 { 1935 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12194 { 1941 /* uqshl */, ARM::MVE_UQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
12195 { 1947 /* uqshll */, ARM::MVE_UQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
12196 { 1954 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12197 { 1954 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12198 { 1962 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12199 { 1962 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12200 { 1969 /* urshr */, ARM::MVE_URSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
12201 { 1975 /* urshrl */, ARM::MVE_URSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
12202 { 1982 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12203 { 1982 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
12204 { 1988 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12205 { 1988 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
12206 { 1995 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, },
12207 { 1995 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, },
12208 { 1995 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, },
12209 { 1995 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, },
12210 { 2000 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, },
12211 { 2000 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, },
12212 { 2007 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12213 { 2007 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12214 { 2012 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12215 { 2012 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12216 { 2019 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12217 { 2019 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
12218 { 2025 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12219 { 2025 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
12220 { 2025 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12221 { 2025 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
12222 { 2031 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12223 { 2031 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
12224 { 2031 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12225 { 2031 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
12226 { 2039 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
12227 { 2039 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
12228 { 2039 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12229 { 2039 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
12230 { 2045 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
12231 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12232 { 2045 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
12233 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
12234 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12235 { 2045 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
12236 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12237 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12238 { 2050 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
12239 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12240 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12241 { 2050 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
12242 { 2057 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
12243 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
12244 { 2057 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
12245 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
12246 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12247 { 2057 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
12248 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
12249 { 2062 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12250 { 2062 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12251 { 2062 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12252 { 2062 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12253 { 2062 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12254 { 2062 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12255 { 2062 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12256 { 2062 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12257 { 2062 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12258 { 2062 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12259 { 2062 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12260 { 2062 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12261 { 2067 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12262 { 2067 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12263 { 2067 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12264 { 2067 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12265 { 2067 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12266 { 2067 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12267 { 2073 /* vabav */, ARM::MVE_VABAVs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
12268 { 2073 /* vabav */, ARM::MVE_VABAVs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
12269 { 2073 /* vabav */, ARM::MVE_VABAVs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
12270 { 2073 /* vabav */, ARM::MVE_VABAVu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
12271 { 2073 /* vabav */, ARM::MVE_VABAVu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
12272 { 2073 /* vabav */, ARM::MVE_VABAVu8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
12273 { 2079 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12274 { 2079 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12275 { 2079 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12276 { 2079 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12277 { 2079 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12278 { 2079 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12279 { 2079 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12280 { 2079 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12281 { 2079 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12282 { 2079 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12283 { 2079 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12284 { 2079 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12285 { 2079 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12286 { 2079 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12287 { 2079 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12288 { 2079 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12289 { 2079 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12290 { 2079 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12291 { 2079 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12292 { 2079 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12293 { 2079 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12294 { 2079 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12295 { 2079 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12296 { 2079 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12297 { 2079 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12298 { 2079 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12299 { 2079 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12300 { 2079 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12301 { 2079 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12302 { 2079 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12303 { 2079 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12304 { 2079 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12305 { 2079 /* vabd */, ARM::MVE_VABDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12306 { 2079 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12307 { 2079 /* vabd */, ARM::MVE_VABDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12308 { 2079 /* vabd */, ARM::MVE_VABDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12309 { 2079 /* vabd */, ARM::MVE_VABDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12310 { 2079 /* vabd */, ARM::MVE_VABDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12311 { 2079 /* vabd */, ARM::MVE_VABDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12312 { 2079 /* vabd */, ARM::MVE_VABDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12313 { 2084 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12314 { 2084 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12315 { 2084 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12316 { 2084 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12317 { 2084 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12318 { 2084 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12319 { 2090 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12320 { 2090 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12321 { 2090 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12322 { 2090 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12323 { 2090 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12324 { 2090 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12325 { 2090 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12326 { 2090 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12327 { 2090 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12328 { 2090 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12329 { 2090 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12330 { 2090 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12331 { 2090 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12332 { 2090 /* vabs */, ARM::MVE_VABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12333 { 2090 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12334 { 2090 /* vabs */, ARM::MVE_VABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
12335 { 2090 /* vabs */, ARM::MVE_VABSf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12336 { 2090 /* vabs */, ARM::MVE_VABSf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12337 { 2095 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12338 { 2095 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12339 { 2095 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12340 { 2095 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12341 { 2095 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12342 { 2095 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12343 { 2095 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12344 { 2095 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12345 { 2101 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12346 { 2101 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12347 { 2101 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12348 { 2101 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12349 { 2101 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12350 { 2101 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12351 { 2101 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12352 { 2101 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12353 { 2107 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12354 { 2107 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12355 { 2107 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12356 { 2107 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12357 { 2107 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12358 { 2107 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12359 { 2107 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12360 { 2107 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12361 { 2113 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12362 { 2113 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12363 { 2113 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12364 { 2113 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12365 { 2113 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12366 { 2113 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12367 { 2113 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12368 { 2113 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12369 { 2119 /* vadc */, ARM::MVE_VADC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12370 { 2124 /* vadci */, ARM::MVE_VADCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12371 { 2130 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12372 { 2130 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12373 { 2130 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12374 { 2130 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12375 { 2130 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12376 { 2130 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12377 { 2130 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12378 { 2130 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12379 { 2130 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
12380 { 2130 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
12381 { 2130 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12382 { 2130 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12383 { 2130 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12384 { 2130 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12385 { 2130 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12386 { 2130 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12387 { 2130 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12388 { 2130 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12389 { 2130 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12390 { 2130 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12391 { 2130 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12392 { 2130 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12393 { 2130 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12394 { 2130 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12395 { 2130 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12396 { 2130 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12397 { 2130 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12398 { 2130 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12399 { 2130 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12400 { 2130 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12401 { 2130 /* vadd */, ARM::MVE_VADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12402 { 2130 /* vadd */, ARM::MVE_VADD_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12403 { 2130 /* vadd */, ARM::MVE_VADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12404 { 2130 /* vadd */, ARM::MVE_VADD_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12405 { 2130 /* vadd */, ARM::MVE_VADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12406 { 2130 /* vadd */, ARM::MVE_VADD_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12407 { 2130 /* vadd */, ARM::MVE_VADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12408 { 2130 /* vadd */, ARM::MVE_VADD_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12409 { 2130 /* vadd */, ARM::MVE_VADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12410 { 2130 /* vadd */, ARM::MVE_VADD_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12411 { 2135 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
12412 { 2135 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
12413 { 2135 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
12414 { 2142 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12415 { 2142 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12416 { 2142 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12417 { 2142 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12418 { 2142 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12419 { 2142 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12420 { 2148 /* vaddlv */, ARM::MVE_VADDLVs32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12421 { 2148 /* vaddlv */, ARM::MVE_VADDLVu32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12422 { 2155 /* vaddlva */, ARM::MVE_VADDLVs32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12423 { 2155 /* vaddlva */, ARM::MVE_VADDLVu32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12424 { 2163 /* vaddv */, ARM::MVE_VADDVs16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, },
12425 { 2163 /* vaddv */, ARM::MVE_VADDVs32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
12426 { 2163 /* vaddv */, ARM::MVE_VADDVs8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, },
12427 { 2163 /* vaddv */, ARM::MVE_VADDVu16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, },
12428 { 2163 /* vaddv */, ARM::MVE_VADDVu32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, },
12429 { 2163 /* vaddv */, ARM::MVE_VADDVu8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, },
12430 { 2169 /* vaddva */, ARM::MVE_VADDVs16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, },
12431 { 2169 /* vaddva */, ARM::MVE_VADDVs32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
12432 { 2169 /* vaddva */, ARM::MVE_VADDVs8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, },
12433 { 2169 /* vaddva */, ARM::MVE_VADDVu16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, },
12434 { 2169 /* vaddva */, ARM::MVE_VADDVu32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, },
12435 { 2169 /* vaddva */, ARM::MVE_VADDVu8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, },
12436 { 2176 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
12437 { 2176 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
12438 { 2176 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
12439 { 2176 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
12440 { 2176 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
12441 { 2176 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
12442 { 2176 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
12443 { 2176 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
12444 { 2176 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
12445 { 2176 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
12446 { 2176 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
12447 { 2176 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
12448 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
12449 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
12450 { 2182 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, },
12451 { 2182 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, },
12452 { 2182 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, },
12453 { 2182 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, },
12454 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
12455 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
12456 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
12457 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
12458 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
12459 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
12460 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12461 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12462 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12463 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12464 { 2182 /* vand */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, },
12465 { 2182 /* vand */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, },
12466 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12467 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12468 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12469 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12470 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12471 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12472 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12473 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12474 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12475 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12476 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12477 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12478 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12479 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12480 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12481 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12482 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12483 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12484 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12485 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12486 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
12487 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
12488 { 2187 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
12489 { 2187 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
12490 { 2187 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
12491 { 2187 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
12492 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12493 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12494 { 2187 /* vbic */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
12495 { 2187 /* vbic */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, },
12496 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12497 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12498 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12499 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12500 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12501 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12502 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12503 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12504 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12505 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12506 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12507 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12508 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12509 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12510 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12511 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12512 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12513 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12514 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12515 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12516 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12517 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12518 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12519 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12520 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12521 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12522 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12523 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12524 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12525 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12526 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12527 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12528 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12529 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12530 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12531 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12532 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12533 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12534 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12535 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12536 { 2202 /* vbrsr */, ARM::MVE_VBRSR16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12537 { 2202 /* vbrsr */, ARM::MVE_VBRSR32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12538 { 2202 /* vbrsr */, ARM::MVE_VBRSR8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12539 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12540 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12541 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12542 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12543 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12544 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12545 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12546 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12547 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12548 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12549 { 2213 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
12550 { 2213 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
12551 { 2213 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
12552 { 2213 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
12553 { 2213 /* vcadd */, ARM::MVE_VCADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12554 { 2213 /* vcadd */, ARM::MVE_VCADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12555 { 2213 /* vcadd */, ARM::MVE_VCADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12556 { 2213 /* vcadd */, ARM::MVE_VCADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12557 { 2213 /* vcadd */, ARM::MVE_VCADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12558 { 2219 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12559 { 2219 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12560 { 2219 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12561 { 2219 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12562 { 2219 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__HASH_0 }, },
12563 { 2219 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12564 { 2219 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__HASH_0 }, },
12565 { 2219 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12566 { 2219 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__HASH_0 }, },
12567 { 2219 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12568 { 2219 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__HASH_0 }, },
12569 { 2219 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12570 { 2219 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__HASH_0 }, },
12571 { 2219 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12572 { 2219 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__HASH_0 }, },
12573 { 2219 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12574 { 2219 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12575 { 2219 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12576 { 2219 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12577 { 2219 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12578 { 2219 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12579 { 2219 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12580 { 2219 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12581 { 2219 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12582 { 2219 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12583 { 2219 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12584 { 2219 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12585 { 2219 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12586 { 2219 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12587 { 2219 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12588 { 2219 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12589 { 2219 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12590 { 2219 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12591 { 2219 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12592 { 2219 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12593 { 2219 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12594 { 2219 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12595 { 2219 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12596 { 2219 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12597 { 2219 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12598 { 2224 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12599 { 2224 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12600 { 2224 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12601 { 2224 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12602 { 2224 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12603 { 2224 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12604 { 2224 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12605 { 2224 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12606 { 2224 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12607 { 2224 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12608 { 2224 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12609 { 2224 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12610 { 2224 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12611 { 2224 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12612 { 2224 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12613 { 2224 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12614 { 2224 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12615 { 2224 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12616 { 2224 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12617 { 2224 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12618 { 2224 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12619 { 2224 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12620 { 2224 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12621 { 2224 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12622 { 2224 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12623 { 2224 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12624 { 2224 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12625 { 2224 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12626 { 2224 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12627 { 2224 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12628 { 2224 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12629 { 2224 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12630 { 2224 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12631 { 2224 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12632 { 2224 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12633 { 2224 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12634 { 2224 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12635 { 2224 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12636 { 2224 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12637 { 2224 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12638 { 2224 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12639 { 2224 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12640 { 2224 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12641 { 2224 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12642 { 2224 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12643 { 2224 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12644 { 2224 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12645 { 2224 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12646 { 2224 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12647 { 2224 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12648 { 2224 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12649 { 2224 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12650 { 2229 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12651 { 2229 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12652 { 2229 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12653 { 2229 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12654 { 2229 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12655 { 2229 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12656 { 2229 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12657 { 2229 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12658 { 2229 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12659 { 2229 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12660 { 2229 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12661 { 2229 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12662 { 2229 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12663 { 2229 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12664 { 2229 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12665 { 2229 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12666 { 2229 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12667 { 2229 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12668 { 2229 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12669 { 2229 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12670 { 2229 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12671 { 2229 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12672 { 2229 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12673 { 2229 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12674 { 2229 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12675 { 2229 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12676 { 2229 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12677 { 2229 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12678 { 2229 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12679 { 2229 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12680 { 2229 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12681 { 2229 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12682 { 2229 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12683 { 2229 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12684 { 2229 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12685 { 2229 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12686 { 2229 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12687 { 2229 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12688 { 2229 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12689 { 2229 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12690 { 2229 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12691 { 2229 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12692 { 2229 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12693 { 2229 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12694 { 2229 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12695 { 2229 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12696 { 2229 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12697 { 2229 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12698 { 2229 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12699 { 2229 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12700 { 2229 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12701 { 2229 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12702 { 2234 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12703 { 2234 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12704 { 2234 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12705 { 2234 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12706 { 2234 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12707 { 2234 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12708 { 2234 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12709 { 2234 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12710 { 2234 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12711 { 2234 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12712 { 2234 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12713 { 2234 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12714 { 2234 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12715 { 2234 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12716 { 2234 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12717 { 2234 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12718 { 2234 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12719 { 2234 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12720 { 2234 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12721 { 2234 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12722 { 2234 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12723 { 2234 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12724 { 2234 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12725 { 2234 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12726 { 2234 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12727 { 2234 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12728 { 2234 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12729 { 2234 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12730 { 2234 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12731 { 2234 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12732 { 2234 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12733 { 2234 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12734 { 2234 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12735 { 2234 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12736 { 2234 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12737 { 2234 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12738 { 2239 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12739 { 2239 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12740 { 2239 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12741 { 2239 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12742 { 2239 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12743 { 2239 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12744 { 2239 /* vcls */, ARM::MVE_VCLSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12745 { 2239 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12746 { 2239 /* vcls */, ARM::MVE_VCLSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
12747 { 2244 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12748 { 2244 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12749 { 2244 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12750 { 2244 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12751 { 2244 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12752 { 2244 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12753 { 2244 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12754 { 2244 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12755 { 2244 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12756 { 2244 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12757 { 2244 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12758 { 2244 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12759 { 2244 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12760 { 2244 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12761 { 2244 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12762 { 2244 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12763 { 2244 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12764 { 2244 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12765 { 2244 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12766 { 2244 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12767 { 2244 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12768 { 2244 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12769 { 2244 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12770 { 2244 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12771 { 2244 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12772 { 2244 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12773 { 2244 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12774 { 2244 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12775 { 2244 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12776 { 2244 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12777 { 2244 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12778 { 2244 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12779 { 2244 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12780 { 2244 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12781 { 2244 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12782 { 2244 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12783 { 2249 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12784 { 2249 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12785 { 2249 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12786 { 2249 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12787 { 2249 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12788 { 2249 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12789 { 2249 /* vclz */, ARM::MVE_VCLZs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
12790 { 2249 /* vclz */, ARM::MVE_VCLZs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
12791 { 2249 /* vclz */, ARM::MVE_VCLZs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR }, },
12792 { 2254 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
12793 { 2254 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
12794 { 2254 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
12795 { 2254 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
12796 { 2254 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
12797 { 2254 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
12798 { 2254 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
12799 { 2254 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
12800 { 2254 /* vcmla */, ARM::MVE_VCMLAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12801 { 2254 /* vcmla */, ARM::MVE_VCMLAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12802 { 2260 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12803 { 2260 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12804 { 2260 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, },
12805 { 2260 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12806 { 2260 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12807 { 2260 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12808 { 2260 /* vcmp */, ARM::MVE_VCMPs16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12809 { 2260 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12810 { 2260 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12811 { 2260 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12812 { 2260 /* vcmp */, ARM::MVE_VCMPs8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12813 { 2260 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12814 { 2260 /* vcmp */, ARM::MVE_VCMPu16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12815 { 2260 /* vcmp */, ARM::MVE_VCMPu16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12816 { 2260 /* vcmp */, ARM::MVE_VCMPu32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12817 { 2260 /* vcmp */, ARM::MVE_VCMPu32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12818 { 2260 /* vcmp */, ARM::MVE_VCMPu8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12819 { 2260 /* vcmp */, ARM::MVE_VCMPu8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12820 { 2260 /* vcmp */, ARM::MVE_VCMPf32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
12821 { 2260 /* vcmp */, ARM::MVE_VCMPf32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
12822 { 2260 /* vcmp */, ARM::MVE_VCMPi16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12823 { 2260 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12824 { 2260 /* vcmp */, ARM::MVE_VCMPi32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12825 { 2260 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12826 { 2260 /* vcmp */, ARM::MVE_VCMPi8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12827 { 2260 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12828 { 2260 /* vcmp */, ARM::MVE_VCMPf16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
12829 { 2260 /* vcmp */, ARM::MVE_VCMPf16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
12830 { 2265 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12831 { 2265 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12832 { 2265 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, },
12833 { 2265 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12834 { 2265 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12835 { 2265 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12836 { 2271 /* vcmul */, ARM::MVE_VCMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12837 { 2271 /* vcmul */, ARM::MVE_VCMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12838 { 2277 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12839 { 2277 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12840 { 2282 /* vctp */, ARM::MVE_VCTP16, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_rGPR }, },
12841 { 2282 /* vctp */, ARM::MVE_VCTP32, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_rGPR }, },
12842 { 2282 /* vctp */, ARM::MVE_VCTP64, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_rGPR }, },
12843 { 2282 /* vctp */, ARM::MVE_VCTP8, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_rGPR }, },
12844 { 2287 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12845 { 2287 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12846 { 2287 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12847 { 2287 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12848 { 2287 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12849 { 2287 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12850 { 2287 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12851 { 2287 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12852 { 2287 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12853 { 2287 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12854 { 2287 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12855 { 2287 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12856 { 2287 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12857 { 2287 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12858 { 2287 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12859 { 2287 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12860 { 2287 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12861 { 2287 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12862 { 2287 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12863 { 2287 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12864 { 2287 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12865 { 2287 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, },
12866 { 2287 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, },
12867 { 2287 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, },
12868 { 2287 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, },
12869 { 2287 /* vcvt */, ARM::BF16_VCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasBF16_HasNEON, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
12870 { 2287 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12871 { 2287 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12872 { 2287 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12873 { 2287 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12874 { 2287 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12875 { 2287 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12876 { 2287 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
12877 { 2287 /* vcvt */, ARM::MVE_VCVTs16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12878 { 2287 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12879 { 2287 /* vcvt */, ARM::MVE_VCVTu16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12880 { 2287 /* vcvt */, ARM::MVE_VCVTu32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12881 { 2287 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12882 { 2287 /* vcvt */, ARM::MVE_VCVTf32u32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
12883 { 2287 /* vcvt */, ARM::MVE_VCVTf16s16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12884 { 2287 /* vcvt */, ARM::MVE_VCVTf16u16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
12885 { 2287 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12886 { 2287 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12887 { 2287 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12888 { 2287 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12889 { 2287 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12890 { 2287 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12891 { 2287 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12892 { 2287 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12893 { 2287 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12894 { 2287 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12895 { 2287 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12896 { 2287 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12897 { 2287 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12898 { 2287 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12899 { 2287 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12900 { 2287 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12901 { 2287 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12902 { 2287 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12903 { 2287 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12904 { 2287 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12905 { 2287 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12906 { 2287 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12907 { 2287 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12908 { 2287 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12909 { 2287 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12910 { 2287 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12911 { 2287 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12912 { 2287 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12913 { 2287 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12914 { 2287 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12915 { 2287 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12916 { 2287 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12917 { 2287 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12918 { 2287 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12919 { 2287 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12920 { 2287 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12921 { 2287 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12922 { 2287 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12923 { 2287 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12924 { 2287 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12925 { 2287 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12926 { 2287 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12927 { 2287 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12928 { 2287 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12929 { 2287 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12930 { 2287 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12931 { 2287 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12932 { 2287 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12933 { 2287 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12934 { 2287 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12935 { 2287 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12936 { 2287 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12937 { 2287 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12938 { 2287 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12939 { 2287 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12940 { 2287 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12941 { 2287 /* vcvt */, ARM::MVE_VCVTs16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12942 { 2287 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12943 { 2287 /* vcvt */, ARM::MVE_VCVTu16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12944 { 2287 /* vcvt */, ARM::MVE_VCVTu32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12945 { 2287 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12946 { 2287 /* vcvt */, ARM::MVE_VCVTf32u32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12947 { 2287 /* vcvt */, ARM::MVE_VCVTf16s16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12948 { 2287 /* vcvt */, ARM::MVE_VCVTf16u16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12949 { 2292 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12950 { 2292 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12951 { 2292 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12952 { 2292 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12953 { 2292 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12954 { 2292 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12955 { 2292 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12956 { 2292 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12957 { 2292 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12958 { 2292 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12959 { 2292 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12960 { 2292 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12961 { 2292 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12962 { 2292 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12963 { 2292 /* vcvta */, ARM::MVE_VCVTs16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12964 { 2292 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12965 { 2292 /* vcvta */, ARM::MVE_VCVTu16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12966 { 2292 /* vcvta */, ARM::MVE_VCVTu32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12967 { 2298 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12968 { 2298 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12969 { 2298 /* vcvtb */, ARM::BF16_VCVTB, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12970 { 2298 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12971 { 2298 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12972 { 2298 /* vcvtb */, ARM::MVE_VCVTf16f32bh, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12973 { 2298 /* vcvtb */, ARM::MVE_VCVTf32f16bh, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12974 { 2304 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12975 { 2304 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12976 { 2304 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12977 { 2304 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12978 { 2304 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12979 { 2304 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12980 { 2304 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12981 { 2304 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12982 { 2304 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12983 { 2304 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12984 { 2304 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12985 { 2304 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12986 { 2304 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12987 { 2304 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12988 { 2304 /* vcvtm */, ARM::MVE_VCVTs16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12989 { 2304 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12990 { 2304 /* vcvtm */, ARM::MVE_VCVTu16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12991 { 2304 /* vcvtm */, ARM::MVE_VCVTu32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12992 { 2310 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12993 { 2310 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12994 { 2310 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12995 { 2310 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12996 { 2310 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12997 { 2310 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12998 { 2310 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12999 { 2310 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13000 { 2310 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13001 { 2310 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13002 { 2310 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13003 { 2310 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13004 { 2310 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13005 { 2310 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13006 { 2310 /* vcvtn */, ARM::MVE_VCVTs16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13007 { 2310 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13008 { 2310 /* vcvtn */, ARM::MVE_VCVTu16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13009 { 2310 /* vcvtn */, ARM::MVE_VCVTu32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13010 { 2316 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13011 { 2316 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13012 { 2316 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13013 { 2316 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13014 { 2316 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13015 { 2316 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13016 { 2316 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13017 { 2316 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13018 { 2316 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13019 { 2316 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13020 { 2316 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13021 { 2316 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13022 { 2316 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13023 { 2316 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13024 { 2316 /* vcvtp */, ARM::MVE_VCVTs16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13025 { 2316 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13026 { 2316 /* vcvtp */, ARM::MVE_VCVTu16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13027 { 2316 /* vcvtp */, ARM::MVE_VCVTu32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13028 { 2322 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13029 { 2322 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13030 { 2322 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13031 { 2322 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13032 { 2322 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13033 { 2322 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13034 { 2328 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13035 { 2328 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
13036 { 2328 /* vcvtt */, ARM::BF16_VCVTT, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13037 { 2328 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13038 { 2328 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13039 { 2328 /* vcvtt */, ARM::MVE_VCVTf16f32th, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13040 { 2328 /* vcvtt */, ARM::MVE_VCVTf32f16th, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13041 { 2334 /* vcx1 */, ARM::CDE_VCX1_fpdp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, },
13042 { 2334 /* vcx1 */, ARM::CDE_VCX1_fpsp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, },
13043 { 2334 /* vcx1 */, ARM::CDE_VCX1_vec, Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, },
13044 { 2339 /* vcx1a */, ARM::CDE_VCX1A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, },
13045 { 2339 /* vcx1a */, ARM::CDE_VCX1A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, },
13046 { 2339 /* vcx1a */, ARM::CDE_VCX1A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, },
13047 { 2345 /* vcx2 */, ARM::CDE_VCX2_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, },
13048 { 2345 /* vcx2 */, ARM::CDE_VCX2_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, },
13049 { 2345 /* vcx2 */, ARM::CDE_VCX2_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, },
13050 { 2350 /* vcx2a */, ARM::CDE_VCX2A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, },
13051 { 2350 /* vcx2a */, ARM::CDE_VCX2A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, },
13052 { 2350 /* vcx2a */, ARM::CDE_VCX2A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, },
13053 { 2356 /* vcx3 */, ARM::CDE_VCX3_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, },
13054 { 2356 /* vcx3 */, ARM::CDE_VCX3_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, },
13055 { 2356 /* vcx3 */, ARM::CDE_VCX3_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, },
13056 { 2361 /* vcx3a */, ARM::CDE_VCX3A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, },
13057 { 2361 /* vcx3a */, ARM::CDE_VCX3A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, },
13058 { 2361 /* vcx3a */, ARM::CDE_VCX3A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, },
13059 { 2367 /* vddup */, ARM::MVE_VDDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
13060 { 2367 /* vddup */, ARM::MVE_VDDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
13061 { 2367 /* vddup */, ARM::MVE_VDDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
13062 { 2373 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13063 { 2373 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13064 { 2373 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13065 { 2373 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13066 { 2373 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13067 { 2373 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13068 { 2378 /* vdot */, ARM::BF16VDOTS_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13069 { 2378 /* vdot */, ARM::BF16VDOTS_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13070 { 2378 /* vdot */, ARM::BF16VDOTI_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13071 { 2378 /* vdot */, ARM::BF16VDOTI_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13072 { 2383 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, },
13073 { 2383 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, },
13074 { 2383 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, },
13075 { 2383 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, },
13076 { 2383 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, },
13077 { 2383 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, },
13078 { 2383 /* vdup */, ARM::MVE_VDUP16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_rGPR }, },
13079 { 2383 /* vdup */, ARM::MVE_VDUP32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_rGPR }, },
13080 { 2383 /* vdup */, ARM::MVE_VDUP8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_rGPR }, },
13081 { 2383 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, },
13082 { 2383 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, },
13083 { 2383 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, },
13084 { 2383 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, },
13085 { 2383 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, },
13086 { 2383 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, },
13087 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
13088 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
13089 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
13090 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13091 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13092 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13093 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13094 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13095 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13096 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13097 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13098 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13099 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13100 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
13101 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
13102 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13103 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13104 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13105 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13106 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13107 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
13108 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13109 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13110 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13111 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13112 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13113 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13114 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13115 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13116 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13117 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13118 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13119 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13120 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13121 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13122 { 2400 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, },
13123 { 2400 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
13124 { 2400 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, },
13125 { 2400 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
13126 { 2400 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, },
13127 { 2400 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
13128 { 2400 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
13129 { 2400 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, },
13130 { 2400 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
13131 { 2400 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, },
13132 { 2400 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
13133 { 2400 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, },
13134 { 2400 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
13135 { 2400 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
13136 { 2405 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13137 { 2405 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13138 { 2405 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13139 { 2405 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13140 { 2405 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13141 { 2405 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13142 { 2405 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13143 { 2405 /* vfma */, ARM::MVE_VFMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13144 { 2405 /* vfma */, ARM::MVE_VFMA_qr_f32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13145 { 2405 /* vfma */, ARM::MVE_VFMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13146 { 2405 /* vfma */, ARM::MVE_VFMA_qr_f16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13147 { 2410 /* vfmab */, ARM::VBF16MALBQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13148 { 2410 /* vfmab */, ARM::VBF16MALBQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13149 { 2416 /* vfmal */, ARM::VFMALQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13150 { 2416 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
13151 { 2416 /* vfmal */, ARM::VFMALQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13152 { 2416 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
13153 { 2422 /* vfmas */, ARM::MVE_VFMA_qr_Sf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13154 { 2422 /* vfmas */, ARM::MVE_VFMA_qr_Sf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13155 { 2428 /* vfmat */, ARM::VBF16MALTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13156 { 2428 /* vfmat */, ARM::VBF16MALTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13157 { 2434 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13158 { 2434 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13159 { 2434 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13160 { 2434 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13161 { 2434 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13162 { 2434 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13163 { 2434 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13164 { 2434 /* vfms */, ARM::MVE_VFMSf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13165 { 2434 /* vfms */, ARM::MVE_VFMSf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13166 { 2439 /* vfmsl */, ARM::VFMSLQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13167 { 2439 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
13168 { 2439 /* vfmsl */, ARM::VFMSLQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13169 { 2439 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
13170 { 2445 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13171 { 2445 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13172 { 2445 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13173 { 2451 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13174 { 2451 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13175 { 2451 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13176 { 2457 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13177 { 2457 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13178 { 2457 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13179 { 2457 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13180 { 2457 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13181 { 2457 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13182 { 2457 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13183 { 2457 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13184 { 2457 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13185 { 2457 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13186 { 2457 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13187 { 2457 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13188 { 2457 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13189 { 2457 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13190 { 2457 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13191 { 2457 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13192 { 2457 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13193 { 2457 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13194 { 2457 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13195 { 2457 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13196 { 2457 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13197 { 2457 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13198 { 2457 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13199 { 2457 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13200 { 2457 /* vhadd */, ARM::MVE_VHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13201 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13202 { 2457 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13203 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13204 { 2457 /* vhadd */, ARM::MVE_VHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13205 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13206 { 2457 /* vhadd */, ARM::MVE_VHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13207 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13208 { 2457 /* vhadd */, ARM::MVE_VHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13209 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13210 { 2457 /* vhadd */, ARM::MVE_VHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13211 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13212 { 2463 /* vhcadd */, ARM::MVE_VHCADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
13213 { 2463 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
13214 { 2463 /* vhcadd */, ARM::MVE_VHCADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
13215 { 2470 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13216 { 2470 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13217 { 2470 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13218 { 2470 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13219 { 2470 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13220 { 2470 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13221 { 2470 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13222 { 2470 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13223 { 2470 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13224 { 2470 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13225 { 2470 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13226 { 2470 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13227 { 2470 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13228 { 2470 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13229 { 2470 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13230 { 2470 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13231 { 2470 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13232 { 2470 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13233 { 2470 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13234 { 2470 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13235 { 2470 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13236 { 2470 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13237 { 2470 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13238 { 2470 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13239 { 2470 /* vhsub */, ARM::MVE_VHSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13240 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13241 { 2470 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13242 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13243 { 2470 /* vhsub */, ARM::MVE_VHSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13244 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13245 { 2470 /* vhsub */, ARM::MVE_VHSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13246 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13247 { 2470 /* vhsub */, ARM::MVE_VHSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13248 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13249 { 2470 /* vhsub */, ARM::MVE_VHSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13250 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13251 { 2476 /* vidup */, ARM::MVE_VIDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
13252 { 2476 /* vidup */, ARM::MVE_VIDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
13253 { 2476 /* vidup */, ARM::MVE_VIDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
13254 { 2482 /* vins */, ARM::VINSH, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13255 { 2487 /* viwdup */, ARM::MVE_VIWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
13256 { 2487 /* viwdup */, ARM::MVE_VIWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
13257 { 2487 /* viwdup */, ARM::MVE_VIWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
13258 { 2494 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
13259 { 2500 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
13260 { 2500 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13261 { 2500 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13262 { 2500 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, },
13263 { 2500 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
13264 { 2500 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
13265 { 2500 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13266 { 2500 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
13267 { 2500 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13268 { 2500 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13269 { 2500 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, },
13270 { 2500 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
13271 { 2500 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
13272 { 2500 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13273 { 2500 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13274 { 2500 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13275 { 2500 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
13276 { 2500 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13277 { 2500 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, },
13278 { 2500 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13279 { 2500 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13280 { 2500 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, },
13281 { 2500 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
13282 { 2500 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
13283 { 2500 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13284 { 2500 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
13285 { 2500 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
13286 { 2500 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13287 { 2500 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13288 { 2500 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13289 { 2500 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13290 { 2500 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
13291 { 2500 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
13292 { 2500 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13293 { 2500 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
13294 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
13295 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
13296 { 2500 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13297 { 2500 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13298 { 2500 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13299 { 2500 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13300 { 2500 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13301 { 2500 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13302 { 2500 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13303 { 2500 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13304 { 2500 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13305 { 2500 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13306 { 2500 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13307 { 2500 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
13308 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
13309 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
13310 { 2500 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13311 { 2500 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13312 { 2500 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13313 { 2500 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13314 { 2500 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13315 { 2500 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13316 { 2500 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13317 { 2500 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
13318 { 2500 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13319 { 2500 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13320 { 2500 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13321 { 2500 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13322 { 2500 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13323 { 2500 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13324 { 2500 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13325 { 2500 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13326 { 2500 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13327 { 2500 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13328 { 2500 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13329 { 2500 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
13330 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13331 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13332 { 2500 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13333 { 2500 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13334 { 2500 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13335 { 2500 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13336 { 2500 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13337 { 2500 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
13338 { 2500 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13339 { 2500 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13340 { 2505 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
13341 { 2505 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13342 { 2505 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, },
13343 { 2505 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
13344 { 2505 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13345 { 2505 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
13346 { 2505 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
13347 { 2505 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, },
13348 { 2505 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13349 { 2505 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, },
13350 { 2505 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
13351 { 2505 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13352 { 2505 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
13353 { 2505 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
13354 { 2505 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
13355 { 2505 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
13356 { 2505 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, },
13357 { 2505 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
13358 { 2505 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13359 { 2505 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
13360 { 2505 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13361 { 2505 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13362 { 2505 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13363 { 2505 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13364 { 2505 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13365 { 2505 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13366 { 2505 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13367 { 2505 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
13368 { 2505 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13369 { 2505 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13370 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
13371 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
13372 { 2505 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
13373 { 2505 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
13374 { 2505 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13375 { 2505 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13376 { 2505 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13377 { 2505 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13378 { 2505 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13379 { 2505 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13380 { 2505 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13381 { 2505 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
13382 { 2505 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13383 { 2505 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13384 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13385 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13386 { 2505 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13387 { 2505 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13388 { 2505 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
13389 { 2505 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
13390 { 2505 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13391 { 2505 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13392 { 2505 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
13393 { 2505 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
13394 { 2505 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13395 { 2505 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
13396 { 2505 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13397 { 2505 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13398 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
13399 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
13400 { 2510 /* vld20 */, ARM::MVE_VLD20_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13401 { 2510 /* vld20 */, ARM::MVE_VLD20_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13402 { 2510 /* vld20 */, ARM::MVE_VLD20_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13403 { 2510 /* vld20 */, ARM::MVE_VLD20_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13404 { 2510 /* vld20 */, ARM::MVE_VLD20_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13405 { 2510 /* vld20 */, ARM::MVE_VLD20_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13406 { 2516 /* vld21 */, ARM::MVE_VLD21_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13407 { 2516 /* vld21 */, ARM::MVE_VLD21_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13408 { 2516 /* vld21 */, ARM::MVE_VLD21_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13409 { 2516 /* vld21 */, ARM::MVE_VLD21_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13410 { 2516 /* vld21 */, ARM::MVE_VLD21_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13411 { 2516 /* vld21 */, ARM::MVE_VLD21_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13412 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
13413 { 2522 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13414 { 2522 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
13415 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
13416 { 2522 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
13417 { 2522 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
13418 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
13419 { 2522 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13420 { 2522 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
13421 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
13422 { 2522 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
13423 { 2522 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
13424 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
13425 { 2522 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13426 { 2522 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
13427 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
13428 { 2522 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
13429 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13430 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13431 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13432 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13433 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13434 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13435 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13436 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13437 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13438 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
13439 { 2522 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13440 { 2522 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13441 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13442 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13443 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13444 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13445 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13446 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13447 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13448 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13449 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13450 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
13451 { 2522 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13452 { 2522 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13453 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13454 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13455 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13456 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13457 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13458 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13459 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13460 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13461 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13462 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
13463 { 2522 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13464 { 2522 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13465 { 2522 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13466 { 2522 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13467 { 2522 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13468 { 2522 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13469 { 2522 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13470 { 2522 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13471 { 2522 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13472 { 2522 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13473 { 2522 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13474 { 2522 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13475 { 2522 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13476 { 2522 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13477 { 2522 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13478 { 2522 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13479 { 2522 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13480 { 2522 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13481 { 2522 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13482 { 2522 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13483 { 2522 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13484 { 2522 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13485 { 2522 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13486 { 2522 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13487 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, },
13488 { 2527 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13489 { 2527 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
13490 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, },
13491 { 2527 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
13492 { 2527 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
13493 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, },
13494 { 2527 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13495 { 2527 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
13496 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, },
13497 { 2527 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
13498 { 2527 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
13499 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, },
13500 { 2527 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13501 { 2527 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
13502 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, },
13503 { 2527 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
13504 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13505 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13506 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13507 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13508 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13509 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13510 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13511 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13512 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13513 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13514 { 2527 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13515 { 2527 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13516 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
13517 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
13518 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13519 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13520 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13521 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
13522 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
13523 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
13524 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13525 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13526 { 2527 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13527 { 2527 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
13528 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13529 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13530 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13531 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13532 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
13533 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
13534 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13535 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13536 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13537 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13538 { 2527 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13539 { 2527 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13540 { 2527 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13541 { 2527 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13542 { 2527 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13543 { 2527 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13544 { 2527 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13545 { 2527 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13546 { 2527 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13547 { 2527 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13548 { 2527 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13549 { 2527 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13550 { 2527 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13551 { 2527 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13552 { 2527 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13553 { 2527 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13554 { 2527 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13555 { 2527 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13556 { 2527 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13557 { 2527 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13558 { 2527 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13559 { 2527 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13560 { 2527 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13561 { 2527 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13562 { 2532 /* vld40 */, ARM::MVE_VLD40_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13563 { 2532 /* vld40 */, ARM::MVE_VLD40_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13564 { 2532 /* vld40 */, ARM::MVE_VLD40_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13565 { 2532 /* vld40 */, ARM::MVE_VLD40_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13566 { 2532 /* vld40 */, ARM::MVE_VLD40_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13567 { 2532 /* vld40 */, ARM::MVE_VLD40_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13568 { 2538 /* vld41 */, ARM::MVE_VLD41_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13569 { 2538 /* vld41 */, ARM::MVE_VLD41_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13570 { 2538 /* vld41 */, ARM::MVE_VLD41_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13571 { 2538 /* vld41 */, ARM::MVE_VLD41_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13572 { 2538 /* vld41 */, ARM::MVE_VLD41_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13573 { 2538 /* vld41 */, ARM::MVE_VLD41_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13574 { 2544 /* vld42 */, ARM::MVE_VLD42_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13575 { 2544 /* vld42 */, ARM::MVE_VLD42_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13576 { 2544 /* vld42 */, ARM::MVE_VLD42_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13577 { 2544 /* vld42 */, ARM::MVE_VLD42_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13578 { 2544 /* vld42 */, ARM::MVE_VLD42_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13579 { 2544 /* vld42 */, ARM::MVE_VLD42_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13580 { 2550 /* vld43 */, ARM::MVE_VLD43_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13581 { 2550 /* vld43 */, ARM::MVE_VLD43_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13582 { 2550 /* vld43 */, ARM::MVE_VLD43_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13583 { 2550 /* vld43 */, ARM::MVE_VLD43_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13584 { 2550 /* vld43 */, ARM::MVE_VLD43_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13585 { 2550 /* vld43 */, ARM::MVE_VLD43_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13586 { 2556 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
13587 { 2556 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
13588 { 2563 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
13589 { 2563 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
13590 { 2563 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
13591 { 2563 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
13592 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, },
13593 { 2570 /* vldr */, ARM::VLDR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, },
13594 { 2570 /* vldr */, ARM::VLDR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, },
13595 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, },
13596 { 2570 /* vldr */, ARM::VLDR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, },
13597 { 2570 /* vldr */, ARM::VLDR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, },
13598 { 2570 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
13599 { 2570 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
13600 { 2570 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
13601 { 2570 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
13602 { 2570 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
13603 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13604 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13605 { 2570 /* vldr */, ARM::VLDR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13606 { 2570 /* vldr */, ARM::VLDR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13607 { 2570 /* vldr */, ARM::VLDR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13608 { 2570 /* vldr */, ARM::VLDR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13609 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13610 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13611 { 2570 /* vldr */, ARM::VLDR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13612 { 2570 /* vldr */, ARM::VLDR_P0_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13613 { 2570 /* vldr */, ARM::VLDR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13614 { 2570 /* vldr */, ARM::VLDR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13615 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13616 { 2575 /* vldrb */, ARM::MVE_VLDRBS16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13617 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13618 { 2575 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13619 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13620 { 2575 /* vldrb */, ARM::MVE_VLDRBU16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13621 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13622 { 2575 /* vldrb */, ARM::MVE_VLDRBU32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13623 { 2575 /* vldrb */, ARM::MVE_VLDRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0Offset }, },
13624 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13625 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13626 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13627 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13628 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13629 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13630 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13631 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13632 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13633 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
13634 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, },
13635 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset }, },
13636 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13637 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS3Offset }, },
13638 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
13639 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13640 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13641 { 2587 /* vldrh */, ARM::MVE_VLDRHS32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
13642 { 2587 /* vldrh */, ARM::MVE_VLDRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1Offset }, },
13643 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13644 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13645 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13646 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13647 { 2587 /* vldrh */, ARM::MVE_VLDRHU32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
13648 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
13649 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
13650 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
13651 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, },
13652 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
13653 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
13654 { 2593 /* vldrw */, ARM::MVE_VLDRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2Offset }, },
13655 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset }, },
13656 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13657 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS2Offset }, },
13658 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
13659 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, },
13660 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
13661 { 2599 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0__imm_95_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
13662 { 2599 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13663 { 2599 /* vlldm */, ARM::VLLDM_T2, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13664 { 2605 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0__imm_95_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
13665 { 2605 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13666 { 2605 /* vlstm */, ARM::VLSTM_T2, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13667 { 2611 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13668 { 2611 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13669 { 2611 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13670 { 2611 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13671 { 2611 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13672 { 2611 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13673 { 2611 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13674 { 2611 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13675 { 2611 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13676 { 2611 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13677 { 2611 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13678 { 2611 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13679 { 2611 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13680 { 2611 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13681 { 2611 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13682 { 2611 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13683 { 2611 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13684 { 2611 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13685 { 2611 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13686 { 2611 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13687 { 2611 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13688 { 2611 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13689 { 2611 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13690 { 2611 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13691 { 2611 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13692 { 2611 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13693 { 2611 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13694 { 2611 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13695 { 2611 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13696 { 2611 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13697 { 2611 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13698 { 2611 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13699 { 2611 /* vmax */, ARM::MVE_VMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13700 { 2611 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13701 { 2611 /* vmax */, ARM::MVE_VMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13702 { 2611 /* vmax */, ARM::MVE_VMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13703 { 2611 /* vmax */, ARM::MVE_VMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13704 { 2611 /* vmax */, ARM::MVE_VMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13705 { 2616 /* vmaxa */, ARM::MVE_VMAXAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13706 { 2616 /* vmaxa */, ARM::MVE_VMAXAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13707 { 2616 /* vmaxa */, ARM::MVE_VMAXAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13708 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13709 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13710 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13711 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13712 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13713 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13714 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13715 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13716 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13717 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13718 { 2629 /* vmaxnm */, ARM::MVE_VMAXNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13719 { 2629 /* vmaxnm */, ARM::MVE_VMAXNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13720 { 2636 /* vmaxnma */, ARM::MVE_VMAXNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13721 { 2636 /* vmaxnma */, ARM::MVE_VMAXNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13722 { 2644 /* vmaxnmav */, ARM::MVE_VMAXNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13723 { 2644 /* vmaxnmav */, ARM::MVE_VMAXNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13724 { 2653 /* vmaxnmv */, ARM::MVE_VMAXNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13725 { 2653 /* vmaxnmv */, ARM::MVE_VMAXNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13726 { 2661 /* vmaxv */, ARM::MVE_VMAXVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13727 { 2661 /* vmaxv */, ARM::MVE_VMAXVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13728 { 2661 /* vmaxv */, ARM::MVE_VMAXVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13729 { 2661 /* vmaxv */, ARM::MVE_VMAXVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, },
13730 { 2661 /* vmaxv */, ARM::MVE_VMAXVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, },
13731 { 2661 /* vmaxv */, ARM::MVE_VMAXVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, },
13732 { 2667 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13733 { 2667 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13734 { 2667 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13735 { 2667 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13736 { 2667 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13737 { 2667 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13738 { 2667 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13739 { 2667 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13740 { 2667 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13741 { 2667 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13742 { 2667 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13743 { 2667 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13744 { 2667 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13745 { 2667 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13746 { 2667 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13747 { 2667 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13748 { 2667 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13749 { 2667 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13750 { 2667 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13751 { 2667 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13752 { 2667 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13753 { 2667 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13754 { 2667 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13755 { 2667 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13756 { 2667 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13757 { 2667 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13758 { 2667 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13759 { 2667 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13760 { 2667 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13761 { 2667 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13762 { 2667 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13763 { 2667 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13764 { 2667 /* vmin */, ARM::MVE_VMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13765 { 2667 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13766 { 2667 /* vmin */, ARM::MVE_VMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13767 { 2667 /* vmin */, ARM::MVE_VMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13768 { 2667 /* vmin */, ARM::MVE_VMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13769 { 2667 /* vmin */, ARM::MVE_VMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13770 { 2672 /* vmina */, ARM::MVE_VMINAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13771 { 2672 /* vmina */, ARM::MVE_VMINAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13772 { 2672 /* vmina */, ARM::MVE_VMINAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13773 { 2678 /* vminav */, ARM::MVE_VMINAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13774 { 2678 /* vminav */, ARM::MVE_VMINAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13775 { 2678 /* vminav */, ARM::MVE_VMINAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13776 { 2685 /* vminnm */, ARM::NEON_VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13777 { 2685 /* vminnm */, ARM::NEON_VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13778 { 2685 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13779 { 2685 /* vminnm */, ARM::VFP_VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13780 { 2685 /* vminnm */, ARM::NEON_VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13781 { 2685 /* vminnm */, ARM::NEON_VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13782 { 2685 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13783 { 2685 /* vminnm */, ARM::MVE_VMINNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13784 { 2685 /* vminnm */, ARM::MVE_VMINNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13785 { 2692 /* vminnma */, ARM::MVE_VMINNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13786 { 2692 /* vminnma */, ARM::MVE_VMINNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13787 { 2700 /* vminnmav */, ARM::MVE_VMINNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13788 { 2700 /* vminnmav */, ARM::MVE_VMINNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13789 { 2709 /* vminnmv */, ARM::MVE_VMINNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13790 { 2709 /* vminnmv */, ARM::MVE_VMINNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13791 { 2717 /* vminv */, ARM::MVE_VMINVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13792 { 2717 /* vminv */, ARM::MVE_VMINVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13793 { 2717 /* vminv */, ARM::MVE_VMINVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13794 { 2717 /* vminv */, ARM::MVE_VMINVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, },
13795 { 2717 /* vminv */, ARM::MVE_VMINVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, },
13796 { 2717 /* vminv */, ARM::MVE_VMINVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, },
13797 { 2723 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13798 { 2723 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13799 { 2723 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13800 { 2723 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13801 { 2723 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13802 { 2723 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13803 { 2723 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13804 { 2723 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13805 { 2723 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13806 { 2723 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13807 { 2723 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13808 { 2723 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13809 { 2723 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13810 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13811 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13812 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13813 { 2723 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13814 { 2723 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13815 { 2723 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13816 { 2723 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13817 { 2723 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13818 { 2723 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13819 { 2723 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13820 { 2723 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13821 { 2728 /* vmladav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13822 { 2728 /* vmladav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13823 { 2728 /* vmladav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13824 { 2728 /* vmladav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13825 { 2728 /* vmladav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13826 { 2728 /* vmladav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13827 { 2736 /* vmladava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13828 { 2736 /* vmladava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13829 { 2736 /* vmladava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13830 { 2736 /* vmladava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13831 { 2736 /* vmladava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13832 { 2736 /* vmladava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13833 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13834 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13835 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13836 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13837 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13838 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13839 { 2764 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13840 { 2764 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13841 { 2764 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13842 { 2764 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13843 { 2764 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13844 { 2764 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13845 { 2764 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13846 { 2764 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13847 { 2764 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13848 { 2764 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13849 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13850 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13851 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13852 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13853 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13854 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13855 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13856 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13857 { 2789 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13858 { 2789 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13859 { 2800 /* vmlaldavx */, ARM::MVE_VMLALDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13860 { 2800 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13861 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13862 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13863 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13864 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13865 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13866 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13867 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13868 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13869 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13870 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13871 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13872 { 2831 /* vmlav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13873 { 2831 /* vmlav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13874 { 2831 /* vmlav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13875 { 2831 /* vmlav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13876 { 2831 /* vmlav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13877 { 2831 /* vmlav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13878 { 2837 /* vmlava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13879 { 2837 /* vmlava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13880 { 2837 /* vmlava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13881 { 2837 /* vmlava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13882 { 2837 /* vmlava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13883 { 2837 /* vmlava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13884 { 2844 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13885 { 2844 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13886 { 2844 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13887 { 2844 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13888 { 2844 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13889 { 2844 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13890 { 2844 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13891 { 2844 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13892 { 2844 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13893 { 2844 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13894 { 2844 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13895 { 2844 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13896 { 2844 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13897 { 2844 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13898 { 2844 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13899 { 2844 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13900 { 2844 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13901 { 2844 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13902 { 2844 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13903 { 2844 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13904 { 2844 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13905 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13906 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13907 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13908 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13909 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13910 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13911 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13912 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13913 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13914 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13915 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13916 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13917 { 2885 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13918 { 2885 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13919 { 2885 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13920 { 2885 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13921 { 2885 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13922 { 2885 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13923 { 2885 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13924 { 2885 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13925 { 2885 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13926 { 2885 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13927 { 2891 /* vmlsldav */, ARM::MVE_VMLSLDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13928 { 2891 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13929 { 2900 /* vmlsldava */, ARM::MVE_VMLSLDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13930 { 2900 /* vmlsldava */, ARM::MVE_VMLSLDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13931 { 2910 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13932 { 2910 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13933 { 2921 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13934 { 2921 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13935 { 2931 /* vmmla */, ARM::VMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13936 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_HPR }, },
13937 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13938 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13939 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_GPR }, },
13940 { 2937 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
13941 { 2937 /* vmov */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13942 { 2937 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, },
13943 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, },
13944 { 2937 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, },
13945 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, },
13946 { 2937 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13947 { 2937 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, },
13948 { 2937 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs64, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13949 { 2937 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, },
13950 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, },
13951 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13952 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, },
13953 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13954 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, },
13955 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
13956 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
13957 { 2937 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
13958 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, },
13959 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
13960 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
13961 { 2937 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
13962 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, },
13963 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
13964 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
13965 { 2937 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, },
13966 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, },
13967 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
13968 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
13969 { 2937 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, },
13970 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, },
13971 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, },
13972 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, },
13973 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13974 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13975 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, },
13976 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, },
13977 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13978 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13979 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, },
13980 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13981 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13982 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, },
13983 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13984 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13985 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, },
13986 { 2937 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_rGPR, MCK_HPR }, },
13987 { 2937 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_rGPR }, },
13988 { 2937 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, },
13989 { 2937 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, },
13990 { 2937 /* vmov */, ARM::VGETLNi32, Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
13991 { 2937 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, },
13992 { 2937 /* vmov */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
13993 { 2937 /* vmov */, ARM::MVE_VMOVimmf32, Convert__Reg1_2__FPImm1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_FPImm }, },
13994 { 2937 /* vmov */, ARM::MVE_VMOVimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13995 { 2937 /* vmov */, ARM::MVE_VMOVimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13996 { 2937 /* vmov */, ARM::MVE_VMOVimmi64, Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i64, MCK_MQPR, MCK_NEONi64splat }, },
13997 { 2937 /* vmov */, ARM::MVE_VMOVimmi8, Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_NEONi8splat }, },
13998 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_s16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, },
13999 { 2937 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
14000 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_s8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, },
14001 { 2937 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
14002 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_u16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, },
14003 { 2937 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
14004 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_u8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, },
14005 { 2937 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
14006 { 2937 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, },
14007 { 2937 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, },
14008 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_16, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_16, MCK_MQPR, MCK_MVEVectorIndex8, MCK_rGPR }, },
14009 { 2937 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, },
14010 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_32, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_MQPR, MCK_MVEVectorIndex4, MCK_rGPR }, },
14011 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_32, Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex4 }, },
14012 { 2937 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
14013 { 2937 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
14014 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_8, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_8, MCK_MQPR, MCK_MVEVectorIndex16, MCK_rGPR }, },
14015 { 2937 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, },
14016 { 2937 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, },
14017 { 2937 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, },
14018 { 2937 /* vmov */, ARM::MVE_VMOV_q_rr, Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0, MCK_rGPR, MCK_rGPR }, },
14019 { 2937 /* vmov */, ARM::MVE_VMOV_rr_q, ConvertCustom_cvtMVEVMOVQtoDReg, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0 }, },
14020 { 2942 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
14021 { 2942 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
14022 { 2942 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
14023 { 2942 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
14024 { 2942 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
14025 { 2942 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
14026 { 2948 /* vmovlb */, ARM::MVE_VMOVLs16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14027 { 2948 /* vmovlb */, ARM::MVE_VMOVLs8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14028 { 2948 /* vmovlb */, ARM::MVE_VMOVLu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
14029 { 2948 /* vmovlb */, ARM::MVE_VMOVLu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
14030 { 2955 /* vmovlt */, ARM::MVE_VMOVLs16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14031 { 2955 /* vmovlt */, ARM::MVE_VMOVLs8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14032 { 2955 /* vmovlt */, ARM::MVE_VMOVLu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
14033 { 2955 /* vmovlt */, ARM::MVE_VMOVLu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
14034 { 2962 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, },
14035 { 2962 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, },
14036 { 2962 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, },
14037 { 2968 /* vmovnb */, ARM::MVE_VMOVNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
14038 { 2968 /* vmovnb */, ARM::MVE_VMOVNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
14039 { 2975 /* vmovnt */, ARM::MVE_VMOVNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
14040 { 2975 /* vmovnt */, ARM::MVE_VMOVNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
14041 { 2982 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14042 { 2988 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, },
14043 { 2988 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, },
14044 { 2988 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, },
14045 { 2988 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, },
14046 { 2988 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, },
14047 { 2988 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, },
14048 { 2988 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, },
14049 { 2988 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, },
14050 { 2988 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, },
14051 { 2988 /* vmrs */, ARM::VMRS_FPCXTNS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTRegs }, },
14052 { 2988 /* vmrs */, ARM::VMRS_FPCXTS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTS }, },
14053 { 2988 /* vmrs */, ARM::VMRS_FPSCR_NZCVQC, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_FPSCR_NZCVQC }, },
14054 { 2988 /* vmrs */, ARM::VMRS_P0, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_P0 }, },
14055 { 2988 /* vmrs */, ARM::VMRS_VPR, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_VCCR }, },
14056 { 2993 /* vmsr */, ARM::VMSR_FPCXTNS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_GPR }, },
14057 { 2993 /* vmsr */, ARM::VMSR_FPCXTS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_GPR }, },
14058 { 2993 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, },
14059 { 2993 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, },
14060 { 2993 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, },
14061 { 2993 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, },
14062 { 2993 /* vmsr */, ARM::VMSR_FPSCR_NZCVQC, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_GPR }, },
14063 { 2993 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, },
14064 { 2993 /* vmsr */, ARM::VMSR_P0, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_GPR }, },
14065 { 2993 /* vmsr */, ARM::VMSR_VPR, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_GPR }, },
14066 { 2998 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14067 { 2998 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14068 { 2998 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14069 { 2998 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14070 { 2998 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
14071 { 2998 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
14072 { 2998 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
14073 { 2998 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
14074 { 2998 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
14075 { 2998 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
14076 { 2998 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, },
14077 { 2998 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, },
14078 { 2998 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14079 { 2998 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14080 { 2998 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14081 { 2998 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14082 { 2998 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14083 { 2998 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14084 { 2998 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14085 { 2998 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14086 { 2998 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14087 { 2998 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14088 { 2998 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14089 { 2998 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14090 { 2998 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14091 { 2998 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14092 { 2998 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14093 { 2998 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14094 { 2998 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14095 { 2998 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14096 { 2998 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14097 { 2998 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14098 { 2998 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14099 { 2998 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14100 { 2998 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14101 { 2998 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14102 { 2998 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14103 { 2998 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14104 { 2998 /* vmul */, ARM::MVE_VMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14105 { 2998 /* vmul */, ARM::MVE_VMUL_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14106 { 2998 /* vmul */, ARM::MVE_VMULi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14107 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14108 { 2998 /* vmul */, ARM::MVE_VMULi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14109 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14110 { 2998 /* vmul */, ARM::MVE_VMULi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14111 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14112 { 2998 /* vmul */, ARM::MVE_VMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14113 { 2998 /* vmul */, ARM::MVE_VMUL_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14114 { 2998 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14115 { 2998 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14116 { 2998 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14117 { 2998 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14118 { 2998 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14119 { 2998 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14120 { 2998 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14121 { 2998 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14122 { 3003 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14123 { 3003 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14124 { 3003 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14125 { 3003 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14126 { 3003 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14127 { 3003 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14128 { 3009 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasAES, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, },
14129 { 3009 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14130 { 3009 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14131 { 3009 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
14132 { 3009 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14133 { 3009 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14134 { 3009 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
14135 { 3009 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, },
14136 { 3009 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14137 { 3009 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14138 { 3009 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14139 { 3009 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14140 { 3015 /* vmullb */, ARM::MVE_VMULLBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14141 { 3015 /* vmullb */, ARM::MVE_VMULLBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14142 { 3015 /* vmullb */, ARM::MVE_VMULLBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14143 { 3015 /* vmullb */, ARM::MVE_VMULLBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14144 { 3015 /* vmullb */, ARM::MVE_VMULLBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14145 { 3015 /* vmullb */, ARM::MVE_VMULLBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14146 { 3015 /* vmullb */, ARM::MVE_VMULLBp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14147 { 3015 /* vmullb */, ARM::MVE_VMULLBp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14148 { 3022 /* vmullt */, ARM::MVE_VMULLTs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14149 { 3022 /* vmullt */, ARM::MVE_VMULLTs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14150 { 3022 /* vmullt */, ARM::MVE_VMULLTs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14151 { 3022 /* vmullt */, ARM::MVE_VMULLTu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14152 { 3022 /* vmullt */, ARM::MVE_VMULLTu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14153 { 3022 /* vmullt */, ARM::MVE_VMULLTu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14154 { 3022 /* vmullt */, ARM::MVE_VMULLTp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14155 { 3022 /* vmullt */, ARM::MVE_VMULLTp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14156 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
14157 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
14158 { 3029 /* vmvn */, ARM::MVE_VMVN, Convert__Reg1_1__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
14159 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, },
14160 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
14161 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, },
14162 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
14163 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, },
14164 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
14165 { 3029 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
14166 { 3029 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
14167 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, },
14168 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
14169 { 3029 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
14170 { 3029 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
14171 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, },
14172 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
14173 { 3029 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
14174 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, },
14175 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
14176 { 3029 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
14177 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14178 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14179 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
14180 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
14181 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
14182 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
14183 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14184 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14185 { 3029 /* vmvn */, ARM::MVE_VMVNimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
14186 { 3029 /* vmvn */, ARM::MVE_VMVNimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
14187 { 3034 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14188 { 3034 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14189 { 3034 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14190 { 3034 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14191 { 3034 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14192 { 3034 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14193 { 3034 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14194 { 3034 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14195 { 3034 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14196 { 3034 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14197 { 3034 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14198 { 3034 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14199 { 3034 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14200 { 3034 /* vneg */, ARM::MVE_VNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14201 { 3034 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14202 { 3034 /* vneg */, ARM::MVE_VNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14203 { 3034 /* vneg */, ARM::MVE_VNEGf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14204 { 3034 /* vneg */, ARM::MVE_VNEGf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14205 { 3039 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14206 { 3039 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14207 { 3039 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14208 { 3045 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14209 { 3045 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14210 { 3045 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14211 { 3051 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14212 { 3051 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14213 { 3051 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14214 { 3051 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14215 { 3051 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14216 { 3051 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14217 { 3057 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
14218 { 3057 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
14219 { 3057 /* vorn */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, },
14220 { 3057 /* vorn */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, },
14221 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14222 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14223 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14224 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14225 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14226 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14227 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14228 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14229 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14230 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14231 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14232 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14233 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
14234 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
14235 { 3062 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
14236 { 3062 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
14237 { 3062 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
14238 { 3062 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
14239 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14240 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14241 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
14242 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
14243 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
14244 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
14245 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14246 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14247 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
14248 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
14249 { 3062 /* vorr */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
14250 { 3062 /* vorr */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, },
14251 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14252 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14253 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14254 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14255 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14256 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14257 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14258 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14259 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14260 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14261 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14262 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14263 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14264 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14265 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14266 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14267 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14268 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14269 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14270 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14271 { 3067 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14272 { 3067 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14273 { 3067 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14274 { 3067 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14275 { 3067 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14276 { 3067 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14277 { 3067 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14278 { 3067 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14279 { 3067 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14280 { 3067 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14281 { 3067 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14282 { 3067 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14283 { 3074 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14284 { 3074 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
14285 { 3074 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
14286 { 3074 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
14287 { 3074 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14288 { 3074 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14289 { 3074 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14290 { 3074 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14291 { 3074 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14292 { 3074 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14293 { 3080 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14294 { 3080 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14295 { 3080 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14296 { 3080 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14297 { 3080 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14298 { 3080 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14299 { 3080 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14300 { 3080 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14301 { 3080 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14302 { 3080 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14303 { 3080 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14304 { 3080 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14305 { 3087 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14306 { 3087 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14307 { 3087 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14308 { 3087 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14309 { 3087 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14310 { 3087 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14311 { 3087 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14312 { 3087 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14313 { 3087 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14314 { 3087 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14315 { 3087 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14316 { 3087 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14317 { 3087 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14318 { 3087 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14319 { 3087 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14320 { 3087 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14321 { 3093 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14322 { 3093 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14323 { 3093 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14324 { 3093 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14325 { 3093 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14326 { 3093 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14327 { 3093 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14328 { 3093 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14329 { 3093 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14330 { 3093 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14331 { 3093 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14332 { 3093 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14333 { 3093 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14334 { 3093 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14335 { 3093 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14336 { 3093 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14337 { 3099 /* vpnot */, ARM::MVE_VPNOT, Convert__imm_95_0__imm_95_0__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN }, },
14338 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, },
14339 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, },
14340 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
14341 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
14342 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
14343 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
14344 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
14345 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
14346 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
14347 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
14348 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14349 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14350 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14351 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14352 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14353 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14354 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14355 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14356 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14357 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14358 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14359 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14360 { 3116 /* vpst */, ARM::MVE_VPST, Convert__ITMask1_0, AMFBS_HasMVEInt, { MCK_ITMask }, },
14361 { 3121 /* vpt */, ARM::MVE_VPTv8s16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
14362 { 3121 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
14363 { 3121 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
14364 { 3121 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
14365 { 3121 /* vpt */, ARM::MVE_VPTv16s8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
14366 { 3121 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
14367 { 3121 /* vpt */, ARM::MVE_VPTv8u16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
14368 { 3121 /* vpt */, ARM::MVE_VPTv8u16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
14369 { 3121 /* vpt */, ARM::MVE_VPTv4u32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
14370 { 3121 /* vpt */, ARM::MVE_VPTv4u32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
14371 { 3121 /* vpt */, ARM::MVE_VPTv16u8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
14372 { 3121 /* vpt */, ARM::MVE_VPTv16u8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
14373 { 3121 /* vpt */, ARM::MVE_VPTv4f32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
14374 { 3121 /* vpt */, ARM::MVE_VPTv4f32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
14375 { 3121 /* vpt */, ARM::MVE_VPTv8i16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
14376 { 3121 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
14377 { 3121 /* vpt */, ARM::MVE_VPTv4i32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
14378 { 3121 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
14379 { 3121 /* vpt */, ARM::MVE_VPTv16i8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
14380 { 3121 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
14381 { 3121 /* vpt */, ARM::MVE_VPTv8f16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
14382 { 3121 /* vpt */, ARM::MVE_VPTv8f16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
14383 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, },
14384 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, },
14385 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
14386 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
14387 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
14388 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
14389 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
14390 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
14391 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
14392 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
14393 { 3131 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14394 { 3131 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14395 { 3131 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14396 { 3131 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14397 { 3131 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14398 { 3131 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14399 { 3131 /* vqabs */, ARM::MVE_VQABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14400 { 3131 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14401 { 3131 /* vqabs */, ARM::MVE_VQABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14402 { 3137 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14403 { 3137 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14404 { 3137 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14405 { 3137 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14406 { 3137 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14407 { 3137 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14408 { 3137 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14409 { 3137 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14410 { 3137 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14411 { 3137 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14412 { 3137 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14413 { 3137 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14414 { 3137 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14415 { 3137 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14416 { 3137 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14417 { 3137 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14418 { 3137 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14419 { 3137 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14420 { 3137 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14421 { 3137 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14422 { 3137 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14423 { 3137 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14424 { 3137 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14425 { 3137 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14426 { 3137 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14427 { 3137 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14428 { 3137 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14429 { 3137 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14430 { 3137 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14431 { 3137 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14432 { 3137 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14433 { 3137 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14434 { 3137 /* vqadd */, ARM::MVE_VQADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14435 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14436 { 3137 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14437 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14438 { 3137 /* vqadd */, ARM::MVE_VQADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14439 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14440 { 3137 /* vqadd */, ARM::MVE_VQADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14441 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14442 { 3137 /* vqadd */, ARM::MVE_VQADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14443 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14444 { 3137 /* vqadd */, ARM::MVE_VQADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14445 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14446 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14447 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14448 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14449 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14450 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14451 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14452 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14453 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14454 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14455 { 3170 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14456 { 3170 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14457 { 3170 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14458 { 3170 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14459 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14460 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14461 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14462 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14463 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14464 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14465 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14466 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14467 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14468 { 3206 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14469 { 3206 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14470 { 3206 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14471 { 3206 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14472 { 3214 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14473 { 3214 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14474 { 3214 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14475 { 3214 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14476 { 3214 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14477 { 3214 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14478 { 3214 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14479 { 3214 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14480 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14481 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14482 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14483 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14484 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14485 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14486 { 3214 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14487 { 3214 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14488 { 3214 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14489 { 3214 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14490 { 3222 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14491 { 3222 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14492 { 3222 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14493 { 3222 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14494 { 3230 /* vqdmullb */, ARM::MVE_VQDMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14495 { 3230 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14496 { 3230 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14497 { 3230 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14498 { 3239 /* vqdmullt */, ARM::MVE_VQDMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14499 { 3239 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14500 { 3239 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14501 { 3239 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14502 { 3248 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
14503 { 3248 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
14504 { 3248 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
14505 { 3248 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, },
14506 { 3248 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, },
14507 { 3248 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, },
14508 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14509 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14510 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNu16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
14511 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNu32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
14512 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14513 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14514 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNu16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
14515 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNu32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
14516 { 3271 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
14517 { 3271 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
14518 { 3271 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
14519 { 3279 /* vqmovunb */, ARM::MVE_VQMOVUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14520 { 3279 /* vqmovunb */, ARM::MVE_VQMOVUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14521 { 3288 /* vqmovunt */, ARM::MVE_VQMOVUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14522 { 3288 /* vqmovunt */, ARM::MVE_VQMOVUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14523 { 3297 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14524 { 3297 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14525 { 3297 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14526 { 3297 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14527 { 3297 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14528 { 3297 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14529 { 3297 /* vqneg */, ARM::MVE_VQNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14530 { 3297 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14531 { 3297 /* vqneg */, ARM::MVE_VQNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14532 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14533 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14534 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14535 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14536 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14537 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14538 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14539 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14540 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14541 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14542 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14543 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14544 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14545 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14546 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14547 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14548 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14549 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14550 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14551 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14552 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14553 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14554 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14555 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14556 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14557 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14558 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14559 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14560 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14561 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14562 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14563 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14564 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14565 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14566 { 3373 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14567 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14568 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14569 { 3373 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14570 { 3373 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14571 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14572 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14573 { 3373 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14574 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14575 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14576 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14577 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14578 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14579 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14580 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14581 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14582 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14583 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14584 { 3382 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14585 { 3382 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14586 { 3382 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14587 { 3382 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14588 { 3382 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14589 { 3382 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14590 { 3382 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14591 { 3382 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14592 { 3382 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14593 { 3382 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14594 { 3382 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14595 { 3382 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14596 { 3382 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14597 { 3382 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14598 { 3382 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14599 { 3382 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14600 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14601 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14602 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14603 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14604 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14605 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14606 { 3382 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14607 { 3382 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14608 { 3382 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14609 { 3382 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14610 { 3382 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14611 { 3382 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14612 { 3382 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14613 { 3382 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14614 { 3382 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14615 { 3382 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14616 { 3382 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14617 { 3382 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14618 { 3382 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14619 { 3382 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14620 { 3382 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14621 { 3382 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14622 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14623 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14624 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14625 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14626 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14627 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14628 { 3389 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14629 { 3389 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14630 { 3389 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14631 { 3389 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14632 { 3389 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14633 { 3389 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14634 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14635 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14636 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14637 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14638 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14639 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14640 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14641 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14642 { 3415 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14643 { 3415 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14644 { 3415 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14645 { 3424 /* vqrshrunb */, ARM::MVE_VQRSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14646 { 3424 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14647 { 3434 /* vqrshrunt */, ARM::MVE_VQRSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14648 { 3434 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14649 { 3444 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14650 { 3444 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
14651 { 3444 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14652 { 3444 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
14653 { 3444 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14654 { 3444 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14655 { 3444 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14656 { 3444 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14657 { 3444 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14658 { 3444 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
14659 { 3444 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14660 { 3444 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
14661 { 3444 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14662 { 3444 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
14663 { 3444 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14664 { 3444 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
14665 { 3444 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14666 { 3444 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, },
14667 { 3444 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14668 { 3444 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, },
14669 { 3444 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14670 { 3444 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, },
14671 { 3444 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14672 { 3444 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, },
14673 { 3444 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14674 { 3444 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, },
14675 { 3444 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14676 { 3444 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, },
14677 { 3444 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14678 { 3444 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, },
14679 { 3444 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14680 { 3444 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, },
14681 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14682 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14683 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14684 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14685 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14686 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14687 { 3444 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14688 { 3444 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14689 { 3444 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14690 { 3444 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14691 { 3444 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14692 { 3444 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14693 { 3444 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14694 { 3444 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14695 { 3444 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14696 { 3444 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14697 { 3444 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14698 { 3444 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14699 { 3444 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14700 { 3444 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14701 { 3444 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14702 { 3444 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14703 { 3444 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14704 { 3444 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14705 { 3444 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14706 { 3444 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14707 { 3444 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14708 { 3444 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14709 { 3444 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14710 { 3444 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14711 { 3444 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14712 { 3444 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14713 { 3444 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14714 { 3444 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14715 { 3444 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14716 { 3444 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14717 { 3444 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14718 { 3444 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14719 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14720 { 3444 /* vqshl */, ARM::MVE_VQSHLimms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14721 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14722 { 3444 /* vqshl */, ARM::MVE_VQSHLimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14723 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14724 { 3444 /* vqshl */, ARM::MVE_VQSHLimms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14725 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14726 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14727 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14728 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14729 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14730 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14731 { 3450 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
14732 { 3450 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
14733 { 3450 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14734 { 3450 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14735 { 3450 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
14736 { 3450 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
14737 { 3450 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
14738 { 3450 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
14739 { 3450 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14740 { 3450 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14741 { 3450 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14742 { 3450 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14743 { 3450 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14744 { 3450 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14745 { 3450 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14746 { 3450 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14747 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14748 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14749 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14750 { 3457 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14751 { 3457 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14752 { 3457 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14753 { 3457 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14754 { 3457 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14755 { 3457 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14756 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14757 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14758 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14759 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14760 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14761 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14762 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14763 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14764 { 3480 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14765 { 3480 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14766 { 3480 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14767 { 3488 /* vqshrunb */, ARM::MVE_VQSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14768 { 3488 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14769 { 3497 /* vqshrunt */, ARM::MVE_VQSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14770 { 3497 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14771 { 3506 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14772 { 3506 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14773 { 3506 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14774 { 3506 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14775 { 3506 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14776 { 3506 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14777 { 3506 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14778 { 3506 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14779 { 3506 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14780 { 3506 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14781 { 3506 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14782 { 3506 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14783 { 3506 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14784 { 3506 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14785 { 3506 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14786 { 3506 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14787 { 3506 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14788 { 3506 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14789 { 3506 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14790 { 3506 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14791 { 3506 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14792 { 3506 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14793 { 3506 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14794 { 3506 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14795 { 3506 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14796 { 3506 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14797 { 3506 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14798 { 3506 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14799 { 3506 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14800 { 3506 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14801 { 3506 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14802 { 3506 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14803 { 3506 /* vqsub */, ARM::MVE_VQSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14804 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14805 { 3506 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14806 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14807 { 3506 /* vqsub */, ARM::MVE_VQSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14808 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14809 { 3506 /* vqsub */, ARM::MVE_VQSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14810 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14811 { 3506 /* vqsub */, ARM::MVE_VQSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14812 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14813 { 3506 /* vqsub */, ARM::MVE_VQSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14814 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14815 { 3512 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
14816 { 3512 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
14817 { 3512 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
14818 { 3520 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14819 { 3520 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14820 { 3520 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14821 { 3520 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14822 { 3520 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14823 { 3520 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14824 { 3527 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14825 { 3527 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14826 { 3527 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14827 { 3527 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14828 { 3527 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14829 { 3527 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14830 { 3527 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14831 { 3527 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14832 { 3534 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14833 { 3534 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14834 { 3534 /* vrev16 */, ARM::MVE_VREV16_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14835 { 3541 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14836 { 3541 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14837 { 3541 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14838 { 3541 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14839 { 3541 /* vrev32 */, ARM::MVE_VREV32_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14840 { 3541 /* vrev32 */, ARM::MVE_VREV32_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14841 { 3548 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14842 { 3548 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14843 { 3548 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
14844 { 3548 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
14845 { 3548 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14846 { 3548 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14847 { 3548 /* vrev64 */, ARM::MVE_VREV64_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14848 { 3548 /* vrev64 */, ARM::MVE_VREV64_32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR }, },
14849 { 3548 /* vrev64 */, ARM::MVE_VREV64_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14850 { 3555 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14851 { 3555 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14852 { 3555 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14853 { 3555 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14854 { 3555 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14855 { 3555 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14856 { 3555 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14857 { 3555 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14858 { 3555 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14859 { 3555 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14860 { 3555 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14861 { 3555 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14862 { 3555 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14863 { 3555 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14864 { 3555 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14865 { 3555 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14866 { 3555 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14867 { 3555 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14868 { 3555 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14869 { 3555 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14870 { 3555 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14871 { 3555 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14872 { 3555 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14873 { 3555 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14874 { 3555 /* vrhadd */, ARM::MVE_VRHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14875 { 3555 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14876 { 3555 /* vrhadd */, ARM::MVE_VRHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14877 { 3555 /* vrhadd */, ARM::MVE_VRHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14878 { 3555 /* vrhadd */, ARM::MVE_VRHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14879 { 3555 /* vrhadd */, ARM::MVE_VRHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14880 { 3562 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14881 { 3562 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14882 { 3562 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14883 { 3562 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14884 { 3562 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14885 { 3562 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14886 { 3562 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14887 { 3562 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14888 { 3562 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14889 { 3562 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14890 { 3562 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14891 { 3562 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14892 { 3562 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14893 { 3562 /* vrinta */, ARM::VRINTAH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14894 { 3562 /* vrinta */, ARM::MVE_VRINTf32A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14895 { 3562 /* vrinta */, ARM::MVE_VRINTf16A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14896 { 3569 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14897 { 3569 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14898 { 3569 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14899 { 3569 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14900 { 3569 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14901 { 3569 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14902 { 3569 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14903 { 3569 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14904 { 3569 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14905 { 3569 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14906 { 3569 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14907 { 3569 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14908 { 3569 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14909 { 3569 /* vrintm */, ARM::VRINTMH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14910 { 3569 /* vrintm */, ARM::MVE_VRINTf32M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14911 { 3569 /* vrintm */, ARM::MVE_VRINTf16M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14912 { 3576 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14913 { 3576 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14914 { 3576 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14915 { 3576 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14916 { 3576 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14917 { 3576 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14918 { 3576 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14919 { 3576 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14920 { 3576 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14921 { 3576 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14922 { 3576 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14923 { 3576 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14924 { 3576 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14925 { 3576 /* vrintn */, ARM::VRINTNH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14926 { 3576 /* vrintn */, ARM::MVE_VRINTf32N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14927 { 3576 /* vrintn */, ARM::MVE_VRINTf16N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14928 { 3583 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14929 { 3583 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14930 { 3583 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14931 { 3583 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14932 { 3583 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14933 { 3583 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14934 { 3583 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14935 { 3583 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14936 { 3583 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14937 { 3583 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14938 { 3583 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14939 { 3583 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14940 { 3583 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14941 { 3583 /* vrintp */, ARM::VRINTPH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14942 { 3583 /* vrintp */, ARM::MVE_VRINTf32P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14943 { 3583 /* vrintp */, ARM::MVE_VRINTf16P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14944 { 3590 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14945 { 3590 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14946 { 3590 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14947 { 3590 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14948 { 3590 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14949 { 3590 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14950 { 3597 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14951 { 3597 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14952 { 3597 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14953 { 3597 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14954 { 3597 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14955 { 3597 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14956 { 3597 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14957 { 3597 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14958 { 3597 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14959 { 3597 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14960 { 3597 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14961 { 3597 /* vrintx */, ARM::MVE_VRINTf32X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14962 { 3597 /* vrintx */, ARM::MVE_VRINTf16X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14963 { 3597 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14964 { 3597 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14965 { 3597 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14966 { 3604 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14967 { 3604 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14968 { 3604 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14969 { 3604 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14970 { 3604 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14971 { 3604 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14972 { 3604 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14973 { 3604 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14974 { 3604 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14975 { 3604 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14976 { 3604 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14977 { 3604 /* vrintz */, ARM::MVE_VRINTf32Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14978 { 3604 /* vrintz */, ARM::MVE_VRINTf16Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14979 { 3604 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14980 { 3604 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14981 { 3604 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14982 { 3611 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14983 { 3611 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14984 { 3622 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14985 { 3622 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14986 { 3634 /* vrmlaldavhax */, ARM::MVE_VRMLALDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14987 { 3647 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14988 { 3659 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14989 { 3659 /* vrmlalvh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14990 { 3668 /* vrmlalvha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14991 { 3668 /* vrmlalvha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14992 { 3678 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14993 { 3689 /* vrmlsldavha */, ARM::MVE_VRMLSLDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14994 { 3701 /* vrmlsldavhax */, ARM::MVE_VRMLSLDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14995 { 3714 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14996 { 3726 /* vrmulh */, ARM::MVE_VRMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14997 { 3726 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14998 { 3726 /* vrmulh */, ARM::MVE_VRMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14999 { 3726 /* vrmulh */, ARM::MVE_VRMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15000 { 3726 /* vrmulh */, ARM::MVE_VRMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15001 { 3726 /* vrmulh */, ARM::MVE_VRMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15002 { 3733 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
15003 { 3733 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
15004 { 3733 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
15005 { 3733 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
15006 { 3733 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
15007 { 3733 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
15008 { 3733 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
15009 { 3733 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
15010 { 3733 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
15011 { 3733 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
15012 { 3733 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
15013 { 3733 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
15014 { 3733 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
15015 { 3733 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
15016 { 3733 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
15017 { 3733 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
15018 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
15019 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
15020 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
15021 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
15022 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
15023 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
15024 { 3733 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15025 { 3733 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15026 { 3733 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15027 { 3733 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15028 { 3733 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15029 { 3733 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15030 { 3733 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15031 { 3733 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15032 { 3733 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15033 { 3733 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15034 { 3733 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15035 { 3733 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15036 { 3733 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15037 { 3733 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15038 { 3733 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15039 { 3733 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15040 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15041 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15042 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15043 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15044 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15045 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15046 { 3739 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
15047 { 3739 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
15048 { 3739 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
15049 { 3739 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
15050 { 3739 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
15051 { 3739 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
15052 { 3739 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
15053 { 3739 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
15054 { 3739 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
15055 { 3739 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
15056 { 3739 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
15057 { 3739 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
15058 { 3739 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
15059 { 3739 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
15060 { 3739 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
15061 { 3739 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
15062 { 3739 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15063 { 3739 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15064 { 3739 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15065 { 3739 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15066 { 3739 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15067 { 3739 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15068 { 3739 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15069 { 3739 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15070 { 3739 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15071 { 3739 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15072 { 3739 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15073 { 3739 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15074 { 3739 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15075 { 3739 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15076 { 3739 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15077 { 3739 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15078 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15079 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
15080 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15081 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15082 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
15083 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15084 { 3745 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
15085 { 3745 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
15086 { 3745 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
15087 { 3752 /* vrshrnb */, ARM::MVE_VRSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15088 { 3752 /* vrshrnb */, ARM::MVE_VRSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15089 { 3760 /* vrshrnt */, ARM::MVE_VRSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15090 { 3760 /* vrshrnt */, ARM::MVE_VRSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15091 { 3768 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
15092 { 3768 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
15093 { 3768 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
15094 { 3768 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
15095 { 3768 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
15096 { 3768 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
15097 { 3776 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
15098 { 3776 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
15099 { 3776 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
15100 { 3776 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
15101 { 3776 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15102 { 3776 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15103 { 3776 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15104 { 3776 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15105 { 3784 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
15106 { 3784 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
15107 { 3784 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
15108 { 3784 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
15109 { 3784 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
15110 { 3784 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
15111 { 3784 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
15112 { 3784 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
15113 { 3784 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
15114 { 3784 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
15115 { 3784 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
15116 { 3784 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
15117 { 3784 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
15118 { 3784 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
15119 { 3784 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
15120 { 3784 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
15121 { 3784 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15122 { 3784 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15123 { 3784 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15124 { 3784 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15125 { 3784 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15126 { 3784 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15127 { 3784 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15128 { 3784 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15129 { 3784 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15130 { 3784 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15131 { 3784 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15132 { 3784 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15133 { 3784 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15134 { 3784 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15135 { 3784 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15136 { 3784 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15137 { 3790 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
15138 { 3790 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
15139 { 3790 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
15140 { 3798 /* vsbc */, ARM::MVE_VSBC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15141 { 3803 /* vsbci */, ARM::MVE_VSBCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15142 { 3809 /* vscclrm */, ARM::VSCCLRMD, Convert__CondCode2_0__FPDRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPDRegListWithVPR }, },
15143 { 3809 /* vscclrm */, ARM::VSCCLRMS, Convert__CondCode2_0__FPSRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPSRegListWithVPR }, },
15144 { 3817 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15145 { 3817 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15146 { 3817 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15147 { 3817 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15148 { 3823 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15149 { 3823 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15150 { 3823 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15151 { 3830 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15152 { 3830 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15153 { 3830 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15154 { 3837 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15155 { 3837 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15156 { 3837 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15157 { 3844 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15158 { 3844 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15159 { 3844 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15160 { 3851 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
15161 { 3851 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
15162 { 3851 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
15163 { 3851 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
15164 { 3851 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
15165 { 3851 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
15166 { 3851 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
15167 { 3851 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
15168 { 3851 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
15169 { 3851 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
15170 { 3851 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
15171 { 3851 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
15172 { 3851 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
15173 { 3851 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
15174 { 3851 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
15175 { 3851 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
15176 { 3851 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, },
15177 { 3851 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, },
15178 { 3851 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, },
15179 { 3851 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, },
15180 { 3851 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, },
15181 { 3851 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, },
15182 { 3851 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, },
15183 { 3851 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, },
15184 { 3851 /* vshl */, ARM::MVE_VSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
15185 { 3851 /* vshl */, ARM::MVE_VSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
15186 { 3851 /* vshl */, ARM::MVE_VSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
15187 { 3851 /* vshl */, ARM::MVE_VSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
15188 { 3851 /* vshl */, ARM::MVE_VSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
15189 { 3851 /* vshl */, ARM::MVE_VSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
15190 { 3851 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15191 { 3851 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15192 { 3851 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15193 { 3851 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15194 { 3851 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15195 { 3851 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15196 { 3851 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15197 { 3851 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15198 { 3851 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15199 { 3851 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15200 { 3851 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15201 { 3851 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15202 { 3851 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15203 { 3851 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15204 { 3851 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15205 { 3851 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15206 { 3851 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, },
15207 { 3851 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, },
15208 { 3851 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, },
15209 { 3851 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, },
15210 { 3851 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, },
15211 { 3851 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, },
15212 { 3851 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, },
15213 { 3851 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, },
15214 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15215 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15216 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15217 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15218 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15219 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15220 { 3851 /* vshl */, ARM::MVE_VSHL_immi16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
15221 { 3851 /* vshl */, ARM::MVE_VSHL_immi32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
15222 { 3851 /* vshl */, ARM::MVE_VSHL_immi8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
15223 { 3856 /* vshlc */, ARM::MVE_VSHLC, Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_rGPR, MCK_MVELongShift }, },
15224 { 3862 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
15225 { 3862 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
15226 { 3862 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
15227 { 3862 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
15228 { 3862 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
15229 { 3862 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
15230 { 3862 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, },
15231 { 3862 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, },
15232 { 3862 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, },
15233 { 3868 /* vshllb */, ARM::MVE_VSHLL_lws16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
15234 { 3868 /* vshllb */, ARM::MVE_VSHLL_imms16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
15235 { 3868 /* vshllb */, ARM::MVE_VSHLL_lws8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
15236 { 3868 /* vshllb */, ARM::MVE_VSHLL_imms8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
15237 { 3868 /* vshllb */, ARM::MVE_VSHLL_lwu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
15238 { 3868 /* vshllb */, ARM::MVE_VSHLL_immu16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
15239 { 3868 /* vshllb */, ARM::MVE_VSHLL_lwu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
15240 { 3868 /* vshllb */, ARM::MVE_VSHLL_immu8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
15241 { 3875 /* vshllt */, ARM::MVE_VSHLL_lws16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
15242 { 3875 /* vshllt */, ARM::MVE_VSHLL_imms16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
15243 { 3875 /* vshllt */, ARM::MVE_VSHLL_lws8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
15244 { 3875 /* vshllt */, ARM::MVE_VSHLL_imms8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
15245 { 3875 /* vshllt */, ARM::MVE_VSHLL_lwu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
15246 { 3875 /* vshllt */, ARM::MVE_VSHLL_immu16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
15247 { 3875 /* vshllt */, ARM::MVE_VSHLL_lwu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
15248 { 3875 /* vshllt */, ARM::MVE_VSHLL_immu8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
15249 { 3882 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
15250 { 3882 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
15251 { 3882 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
15252 { 3882 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
15253 { 3882 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
15254 { 3882 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
15255 { 3882 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
15256 { 3882 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
15257 { 3882 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
15258 { 3882 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
15259 { 3882 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
15260 { 3882 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
15261 { 3882 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
15262 { 3882 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
15263 { 3882 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
15264 { 3882 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
15265 { 3882 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15266 { 3882 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15267 { 3882 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15268 { 3882 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15269 { 3882 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15270 { 3882 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15271 { 3882 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15272 { 3882 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15273 { 3882 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15274 { 3882 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15275 { 3882 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15276 { 3882 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15277 { 3882 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15278 { 3882 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15279 { 3882 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15280 { 3882 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15281 { 3882 /* vshr */, ARM::MVE_VSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15282 { 3882 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
15283 { 3882 /* vshr */, ARM::MVE_VSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15284 { 3882 /* vshr */, ARM::MVE_VSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15285 { 3882 /* vshr */, ARM::MVE_VSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
15286 { 3882 /* vshr */, ARM::MVE_VSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15287 { 3887 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
15288 { 3887 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
15289 { 3887 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
15290 { 3893 /* vshrnb */, ARM::MVE_VSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15291 { 3893 /* vshrnb */, ARM::MVE_VSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15292 { 3900 /* vshrnt */, ARM::MVE_VSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15293 { 3900 /* vshrnt */, ARM::MVE_VSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15294 { 3907 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, },
15295 { 3907 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, },
15296 { 3907 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, },
15297 { 3907 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, },
15298 { 3907 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, },
15299 { 3907 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, },
15300 { 3907 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, },
15301 { 3907 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, },
15302 { 3907 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, },
15303 { 3907 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, },
15304 { 3907 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, },
15305 { 3907 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, },
15306 { 3907 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, },
15307 { 3907 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, },
15308 { 3907 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, },
15309 { 3907 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, },
15310 { 3907 /* vsli */, ARM::MVE_VSLIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
15311 { 3907 /* vsli */, ARM::MVE_VSLIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
15312 { 3907 /* vsli */, ARM::MVE_VSLIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
15313 { 3912 /* vsmmla */, ARM::VSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15314 { 3919 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
15315 { 3919 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
15316 { 3919 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
15317 { 3919 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
15318 { 3919 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
15319 { 3925 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
15320 { 3925 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
15321 { 3925 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
15322 { 3925 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
15323 { 3925 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
15324 { 3925 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
15325 { 3925 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
15326 { 3925 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
15327 { 3925 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
15328 { 3925 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
15329 { 3925 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
15330 { 3925 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
15331 { 3925 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
15332 { 3925 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
15333 { 3925 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
15334 { 3925 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
15335 { 3925 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15336 { 3925 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15337 { 3925 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15338 { 3925 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15339 { 3925 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15340 { 3925 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15341 { 3925 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15342 { 3925 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15343 { 3925 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15344 { 3925 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15345 { 3925 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15346 { 3925 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15347 { 3925 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15348 { 3925 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15349 { 3925 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15350 { 3925 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15351 { 3930 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, },
15352 { 3930 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, },
15353 { 3930 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, },
15354 { 3930 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, },
15355 { 3930 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, },
15356 { 3930 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, },
15357 { 3930 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, },
15358 { 3930 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, },
15359 { 3930 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
15360 { 3930 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
15361 { 3930 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
15362 { 3930 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
15363 { 3930 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
15364 { 3930 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
15365 { 3930 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
15366 { 3930 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
15367 { 3930 /* vsri */, ARM::MVE_VSRIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
15368 { 3930 /* vsri */, ARM::MVE_VSRIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
15369 { 3930 /* vsri */, ARM::MVE_VSRIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
15370 { 3935 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15371 { 3935 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15372 { 3935 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15373 { 3935 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
15374 { 3935 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15375 { 3935 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15376 { 3935 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15377 { 3935 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15378 { 3935 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
15379 { 3935 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15380 { 3935 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15381 { 3935 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15382 { 3935 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15383 { 3935 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15384 { 3935 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15385 { 3935 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15386 { 3935 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15387 { 3935 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
15388 { 3935 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15389 { 3935 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15390 { 3935 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15391 { 3935 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15392 { 3935 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15393 { 3935 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15394 { 3935 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15395 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
15396 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
15397 { 3935 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15398 { 3935 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15399 { 3935 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15400 { 3935 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15401 { 3935 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15402 { 3935 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15403 { 3935 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15404 { 3935 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15405 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15406 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15407 { 3935 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15408 { 3935 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15409 { 3935 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15410 { 3935 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15411 { 3935 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15412 { 3935 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15413 { 3935 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15414 { 3935 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15415 { 3935 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15416 { 3935 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15417 { 3935 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15418 { 3935 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15419 { 3935 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15420 { 3935 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15421 { 3935 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15422 { 3935 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15423 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15424 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15425 { 3935 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15426 { 3935 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15427 { 3935 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
15428 { 3935 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
15429 { 3935 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15430 { 3935 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
15431 { 3935 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15432 { 3935 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, },
15433 { 3940 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15434 { 3940 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
15435 { 3940 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15436 { 3940 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
15437 { 3940 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
15438 { 3940 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15439 { 3940 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
15440 { 3940 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15441 { 3940 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
15442 { 3940 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
15443 { 3940 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15444 { 3940 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
15445 { 3940 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15446 { 3940 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
15447 { 3940 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15448 { 3940 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15449 { 3940 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15450 { 3940 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
15451 { 3940 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15452 { 3940 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15453 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15454 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15455 { 3940 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15456 { 3940 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15457 { 3940 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15458 { 3940 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15459 { 3940 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15460 { 3940 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
15461 { 3940 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15462 { 3940 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15463 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15464 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15465 { 3940 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15466 { 3940 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15467 { 3940 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15468 { 3940 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15469 { 3940 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15470 { 3940 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
15471 { 3940 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15472 { 3940 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15473 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
15474 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
15475 { 3945 /* vst20 */, ARM::MVE_VST20_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15476 { 3945 /* vst20 */, ARM::MVE_VST20_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15477 { 3945 /* vst20 */, ARM::MVE_VST20_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15478 { 3945 /* vst20 */, ARM::MVE_VST20_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15479 { 3945 /* vst20 */, ARM::MVE_VST20_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15480 { 3945 /* vst20 */, ARM::MVE_VST20_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15481 { 3951 /* vst21 */, ARM::MVE_VST21_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15482 { 3951 /* vst21 */, ARM::MVE_VST21_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15483 { 3951 /* vst21 */, ARM::MVE_VST21_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15484 { 3951 /* vst21 */, ARM::MVE_VST21_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15485 { 3951 /* vst21 */, ARM::MVE_VST21_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15486 { 3951 /* vst21 */, ARM::MVE_VST21_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15487 { 3957 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15488 { 3957 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
15489 { 3957 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
15490 { 3957 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
15491 { 3957 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15492 { 3957 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
15493 { 3957 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
15494 { 3957 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
15495 { 3957 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15496 { 3957 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
15497 { 3957 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
15498 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15499 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15500 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15501 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15502 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15503 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
15504 { 3957 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15505 { 3957 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15506 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15507 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15508 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15509 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15510 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15511 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
15512 { 3957 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15513 { 3957 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15514 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15515 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15516 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15517 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15518 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15519 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
15520 { 3957 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15521 { 3957 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15522 { 3957 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15523 { 3957 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15524 { 3957 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15525 { 3957 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15526 { 3957 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15527 { 3957 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15528 { 3957 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15529 { 3957 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15530 { 3957 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15531 { 3957 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15532 { 3962 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15533 { 3962 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
15534 { 3962 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15535 { 3962 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
15536 { 3962 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15537 { 3962 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
15538 { 3962 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15539 { 3962 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
15540 { 3962 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15541 { 3962 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
15542 { 3962 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15543 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15544 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15545 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15546 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15547 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15548 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15549 { 3962 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15550 { 3962 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15551 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15552 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15553 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15554 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
15555 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15556 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15557 { 3962 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15558 { 3962 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
15559 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15560 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15561 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15562 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15563 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15564 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15565 { 3962 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15566 { 3962 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15567 { 3962 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15568 { 3962 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15569 { 3962 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15570 { 3962 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15571 { 3962 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15572 { 3962 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15573 { 3962 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15574 { 3962 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15575 { 3962 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15576 { 3962 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15577 { 3967 /* vst40 */, ARM::MVE_VST40_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15578 { 3967 /* vst40 */, ARM::MVE_VST40_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15579 { 3967 /* vst40 */, ARM::MVE_VST40_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15580 { 3967 /* vst40 */, ARM::MVE_VST40_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15581 { 3967 /* vst40 */, ARM::MVE_VST40_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15582 { 3967 /* vst40 */, ARM::MVE_VST40_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15583 { 3973 /* vst41 */, ARM::MVE_VST41_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15584 { 3973 /* vst41 */, ARM::MVE_VST41_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15585 { 3973 /* vst41 */, ARM::MVE_VST41_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15586 { 3973 /* vst41 */, ARM::MVE_VST41_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15587 { 3973 /* vst41 */, ARM::MVE_VST41_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15588 { 3973 /* vst41 */, ARM::MVE_VST41_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15589 { 3979 /* vst42 */, ARM::MVE_VST42_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15590 { 3979 /* vst42 */, ARM::MVE_VST42_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15591 { 3979 /* vst42 */, ARM::MVE_VST42_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15592 { 3979 /* vst42 */, ARM::MVE_VST42_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15593 { 3979 /* vst42 */, ARM::MVE_VST42_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15594 { 3979 /* vst42 */, ARM::MVE_VST42_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15595 { 3985 /* vst43 */, ARM::MVE_VST43_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15596 { 3985 /* vst43 */, ARM::MVE_VST43_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15597 { 3985 /* vst43 */, ARM::MVE_VST43_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15598 { 3985 /* vst43 */, ARM::MVE_VST43_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15599 { 3985 /* vst43 */, ARM::MVE_VST43_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15600 { 3985 /* vst43 */, ARM::MVE_VST43_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15601 { 3991 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
15602 { 3991 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
15603 { 3998 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
15604 { 3998 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
15605 { 3998 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
15606 { 3998 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
15607 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, },
15608 { 4005 /* vstr */, ARM::VSTR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, },
15609 { 4005 /* vstr */, ARM::VSTR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, },
15610 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, },
15611 { 4005 /* vstr */, ARM::VSTR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, },
15612 { 4005 /* vstr */, ARM::VSTR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, },
15613 { 4005 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
15614 { 4005 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
15615 { 4005 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
15616 { 4005 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
15617 { 4005 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
15618 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15619 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15620 { 4005 /* vstr */, ARM::VSTR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15621 { 4005 /* vstr */, ARM::VSTR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15622 { 4005 /* vstr */, ARM::VSTR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15623 { 4005 /* vstr */, ARM::VSTR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15624 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15625 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15626 { 4005 /* vstr */, ARM::VSTR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15627 { 4005 /* vstr */, ARM::VSTR_P0_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15628 { 4005 /* vstr */, ARM::VSTR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15629 { 4005 /* vstr */, ARM::VSTR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15630 { 4010 /* vstrb */, ARM::MVE_VSTRB16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15631 { 4010 /* vstrb */, ARM::MVE_VSTRB16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
15632 { 4010 /* vstrb */, ARM::MVE_VSTRB32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15633 { 4010 /* vstrb */, ARM::MVE_VSTRB32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
15634 { 4010 /* vstrb */, ARM::MVE_VSTRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0Offset }, },
15635 { 4010 /* vstrb */, ARM::MVE_VSTRB8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15636 { 4010 /* vstrb */, ARM::MVE_VSTRB16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
15637 { 4010 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
15638 { 4010 /* vstrb */, ARM::MVE_VSTRB32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
15639 { 4010 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
15640 { 4010 /* vstrb */, ARM::MVE_VSTRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
15641 { 4010 /* vstrb */, ARM::MVE_VSTRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, },
15642 { 4016 /* vstrd */, ARM::MVE_VSTRD64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset }, },
15643 { 4016 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15644 { 4016 /* vstrd */, ARM::MVE_VSTRD64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS3Offset }, },
15645 { 4016 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
15646 { 4022 /* vstrh */, ARM::MVE_VSTRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1Offset }, },
15647 { 4022 /* vstrh */, ARM::MVE_VSTRH16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15648 { 4022 /* vstrh */, ARM::MVE_VSTRH16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS1Offset }, },
15649 { 4022 /* vstrh */, ARM::MVE_VSTRH32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15650 { 4022 /* vstrh */, ARM::MVE_VSTRH32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
15651 { 4022 /* vstrh */, ARM::MVE_VSTRH32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
15652 { 4022 /* vstrh */, ARM::MVE_VSTRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
15653 { 4022 /* vstrh */, ARM::MVE_VSTRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, },
15654 { 4022 /* vstrh */, ARM::MVE_VSTRH32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
15655 { 4022 /* vstrh */, ARM::MVE_VSTRH32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
15656 { 4028 /* vstrw */, ARM::MVE_VSTRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2Offset }, },
15657 { 4028 /* vstrw */, ARM::MVE_VSTRW32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset }, },
15658 { 4028 /* vstrw */, ARM::MVE_VSTRW32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15659 { 4028 /* vstrw */, ARM::MVE_VSTRW32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS2Offset }, },
15660 { 4028 /* vstrw */, ARM::MVE_VSTRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
15661 { 4028 /* vstrw */, ARM::MVE_VSTRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, },
15662 { 4028 /* vstrw */, ARM::MVE_VSTRW32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
15663 { 4034 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
15664 { 4034 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
15665 { 4034 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
15666 { 4034 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
15667 { 4034 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
15668 { 4034 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
15669 { 4034 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
15670 { 4034 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
15671 { 4034 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
15672 { 4034 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
15673 { 4034 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
15674 { 4034 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
15675 { 4034 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
15676 { 4034 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
15677 { 4034 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
15678 { 4034 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15679 { 4034 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15680 { 4034 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15681 { 4034 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15682 { 4034 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15683 { 4034 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15684 { 4034 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15685 { 4034 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15686 { 4034 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15687 { 4034 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15688 { 4034 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15689 { 4034 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15690 { 4034 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15691 { 4034 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15692 { 4034 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15693 { 4034 /* vsub */, ARM::MVE_VSUBf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15694 { 4034 /* vsub */, ARM::MVE_VSUB_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15695 { 4034 /* vsub */, ARM::MVE_VSUBi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15696 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15697 { 4034 /* vsub */, ARM::MVE_VSUBi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15698 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15699 { 4034 /* vsub */, ARM::MVE_VSUBi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15700 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15701 { 4034 /* vsub */, ARM::MVE_VSUBf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15702 { 4034 /* vsub */, ARM::MVE_VSUB_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15703 { 4039 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
15704 { 4039 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
15705 { 4039 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
15706 { 4046 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
15707 { 4046 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
15708 { 4046 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
15709 { 4046 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
15710 { 4046 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
15711 { 4046 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
15712 { 4052 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
15713 { 4052 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
15714 { 4052 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
15715 { 4052 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
15716 { 4052 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
15717 { 4052 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
15718 { 4052 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
15719 { 4052 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
15720 { 4052 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
15721 { 4052 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
15722 { 4052 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
15723 { 4052 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
15724 { 4058 /* vsudot */, ARM::VSUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15725 { 4058 /* vsudot */, ARM::VSUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15726 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
15727 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
15728 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15729 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15730 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15731 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15732 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
15733 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
15734 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15735 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15736 { 4070 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
15737 { 4070 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
15738 { 4070 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
15739 { 4070 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
15740 { 4075 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
15741 { 4075 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
15742 { 4075 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
15743 { 4075 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
15744 { 4080 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15745 { 4080 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15746 { 4080 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15747 { 4080 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15748 { 4080 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15749 { 4080 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15750 { 4085 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15751 { 4085 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15752 { 4085 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15753 { 4085 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15754 { 4085 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15755 { 4085 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15756 { 4085 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15757 { 4085 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15758 { 4085 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15759 { 4085 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15760 { 4085 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15761 { 4085 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15762 { 4090 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15763 { 4090 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15764 { 4090 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15765 { 4090 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15766 { 4096 /* vummla */, ARM::VUMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15767 { 4103 /* vusdot */, ARM::VUSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15768 { 4103 /* vusdot */, ARM::VUSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15769 { 4103 /* vusdot */, ARM::VUSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15770 { 4103 /* vusdot */, ARM::VUSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15771 { 4110 /* vusmmla */, ARM::VUSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15772 { 4118 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15773 { 4118 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15774 { 4118 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15775 { 4118 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15776 { 4118 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15777 { 4118 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15778 { 4123 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15779 { 4123 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15780 { 4123 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15781 { 4123 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15782 { 4123 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15783 { 4123 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15784 { 4128 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15785 { 4128 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15786 { 4128 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15787 { 4132 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15788 { 4132 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15789 { 4132 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15790 { 4136 /* wls */, ARM::t2WLS, Convert__Reg1_0__Reg1_1__WLSLabel1_2, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15791 { 4140 /* wlstp */, ARM::MVE_WLSTP_16, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15792 { 4140 /* wlstp */, ARM::MVE_WLSTP_32, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15793 { 4140 /* wlstp */, ARM::MVE_WLSTP_64, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15794 { 4140 /* wlstp */, ARM::MVE_WLSTP_8, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15795 { 4146 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15796 { 4146 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15797 { 4146 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15798};
15799
15800#include "llvm/Support/Debug.h"
15801#include "llvm/Support/Format.h"
15802
15803unsigned ARMAsmParser::
15804MatchInstructionImpl(const OperandVector &Operands,
15805 MCInst &Inst,
15806 SmallVectorImpl<NearMissInfo> *NearMisses,
15807 bool matchingInlineAsm, unsigned VariantID) {
15808 // Get the current feature set.
15809 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
15810
15811 // Get the instruction mnemonic, which is the first token.
15812 StringRef Mnemonic = ((ARMOperand &)*Operands[0]).getToken();
15813
15814 // Process all MnemonicAliases to remap the mnemonic.
15815 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
15816
15817 SmallBitVector OptionalOperandsMask(18);
15818 // Find the appropriate table for this asm variant.
15819 const MatchEntry *Start, *End;
15820 switch (VariantID) {
15821 default: llvm_unreachable("invalid variant!");
15822 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
15823 }
15824 // Search the table.
15825 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
15826
15827 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
15828 std::distance(MnemonicRange.first, MnemonicRange.second) <<
15829 " encodings with mnemonic '" << Mnemonic << "'\n");
15830
15831 // Return a more specific error code if no mnemonics match.
15832 if (MnemonicRange.first == MnemonicRange.second)
15833 return Match_MnemonicFail;
15834
15835 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
15836 it != ie; ++it) {
15837 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
15838 bool HasRequiredFeatures =
15839 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
15840 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
15841 << MII.getName(it->Opcode) << "\n");
15842 // Some state to record ways in which this instruction did not match.
15843 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();
15844 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();
15845 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();
15846 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();
15847 bool MultipleInvalidOperands = false;
15848 // equal_range guarantees that instruction mnemonic matches.
15849 assert(Mnemonic == it->getMnemonic());
15850 OptionalOperandsMask.reset(0, 18);
15851 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 18; ++FormalIdx) {
15852 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
15853 DEBUG_WITH_TYPE("asm-matcher",
15854 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
15855 << " against actual operand at index " << ActualIdx);
15856 if (ActualIdx < Operands.size())
15857 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
15858 Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
15859 else
15860 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
15861 if (ActualIdx >= Operands.size()) {
15862 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
15863 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
15864 if (!ThisOperandValid) {
15865 if (!OperandNearMiss) {
15866 // Record info about match failure for later use.
15867 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n");
15868 OperandNearMiss =
15869 NearMissInfo::getTooFewOperands(Formal, it->Opcode);
15870 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {
15871 // If more than one operand is invalid, give up on this match entry.
15872 DEBUG_WITH_TYPE(
15873 "asm-matcher",
15874 dbgs() << "second invalid operand, giving up on this opcode\n");
15875 MultipleInvalidOperands = true;
15876 break;
15877 }
15878 } else {
15879 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n");
15880 if (isSubclass(Formal, OptionalMatchClass)) {
15881 OptionalOperandsMask.set(FormalIdx);
15882 }
15883 }
15884 continue;
15885 }
15886 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
15887 unsigned Diag = validateOperandClass(Actual, Formal);
15888 if (Diag == Match_Success) {
15889 DEBUG_WITH_TYPE("asm-matcher",
15890 dbgs() << "match success using generic matcher\n");
15891 ++ActualIdx;
15892 continue;
15893 }
15894 // If the generic handler indicates an invalid operand
15895 // failure, check for a special case.
15896 if (Diag != Match_Success) {
15897 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
15898 if (TargetDiag == Match_Success) {
15899 DEBUG_WITH_TYPE("asm-matcher",
15900 dbgs() << "match success using target matcher\n");
15901 ++ActualIdx;
15902 continue;
15903 }
15904 // If the target matcher returned a specific error code use
15905 // that, else use the one from the generic matcher.
15906 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
15907 Diag = TargetDiag;
15908 }
15909 // If current formal operand wasn't matched and it is optional
15910 // then try to match next formal operand
15911 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
15912 OptionalOperandsMask.set(FormalIdx);
15913 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
15914 continue;
15915 }
15916 if (!OperandNearMiss) {
15917 // If this is the first invalid operand we have seen, record some
15918 // information about it.
15919 DEBUG_WITH_TYPE(
15920 "asm-matcher",
15921 dbgs()
15922 << "operand match failed, recording near-miss with diag code "
15923 << Diag << "\n");
15924 OperandNearMiss =
15925 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);
15926 ++ActualIdx;
15927 } else {
15928 // If more than one operand is invalid, give up on this match entry.
15929 DEBUG_WITH_TYPE(
15930 "asm-matcher",
15931 dbgs() << "second operand mismatch, skipping this opcode\n");
15932 MultipleInvalidOperands = true;
15933 break;
15934 }
15935 }
15936
15937 if (MultipleInvalidOperands) {
15938 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15939 "operand mismatches, ignoring "
15940 "this opcode\n");
15941 continue;
15942 }
15943 if (!HasRequiredFeatures) {
15944 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
15945 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
15946 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
15947 if (NewMissingFeatures[I])
15948 dbgs() << ' ' << I;
15949 dbgs() << "\n");
15950 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);
15951 }
15952
15953 Inst.clear();
15954
15955 Inst.setOpcode(it->Opcode);
15956 // We have a potential match but have not rendered the operands.
15957 // Check the target predicate to handle any context sensitive
15958 // constraints.
15959 // For example, Ties that are referenced multiple times must be
15960 // checked here to ensure the input is the same for each match
15961 // constraints. If we leave it any later the ties will have been
15962 // canonicalized
15963 unsigned MatchResult;
15964 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
15965 Inst.clear();
15966 DEBUG_WITH_TYPE(
15967 "asm-matcher",
15968 dbgs() << "Early target match predicate failed with diag code "
15969 << MatchResult << "\n");
15970 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
15971 }
15972
15973 // If we did not successfully match the operands, then we can't convert to
15974 // an MCInst, so bail out on this instruction variant now.
15975 if (OperandNearMiss) {
15976 // If the operand mismatch was the only problem, reprrt it as a near-miss.
15977 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {
15978 DEBUG_WITH_TYPE(
15979 "asm-matcher",
15980 dbgs()
15981 << "Opcode result: one mismatched operand, adding near-miss\n");
15982 NearMisses->push_back(OperandNearMiss);
15983 } else {
15984 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15985 "types of mismatch, so not "
15986 "reporting near-miss\n");
15987 }
15988 continue;
15989 }
15990
15991 unsigned DefaultsOffset[19] = { 0 };
15992 assert(OptionalOperandsMask.size() == 18);
15993 for (unsigned i = 0, NumDefaults = 0; i < 18; ++i) {
15994 DefaultsOffset[i + 1] = NumDefaults;
15995 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
15996 }
15997
15998 if (matchingInlineAsm) {
15999 convertToMapAndConstraints(it->ConvertFn, Operands);
16000 return Match_Success;
16001 }
16002
16003 // We have selected a definite instruction, convert the parsed
16004 // operands into the appropriate MCInst.
16005 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
16006 OptionalOperandsMask, DefaultsOffset);
16007
16008 // We have a potential match. Check the target predicate to
16009 // handle any context sensitive constraints.
16010 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
16011 DEBUG_WITH_TYPE("asm-matcher",
16012 dbgs() << "Target match predicate failed with diag code "
16013 << MatchResult << "\n");
16014 Inst.clear();
16015 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
16016 }
16017
16018 int NumNearMisses = ((int)(bool)OperandNearMiss +
16019 (int)(bool)FeaturesNearMiss +
16020 (int)(bool)EarlyPredicateNearMiss +
16021 (int)(bool)LatePredicateNearMiss);
16022 if (NumNearMisses == 1) {
16023 // We had exactly one type of near-miss, so add that to the list.
16024 assert(!OperandNearMiss && "OperandNearMiss was handled earlier");
16025 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of "
16026 "mismatch, so reporting a "
16027 "near-miss\n");
16028 if (NearMisses && FeaturesNearMiss)
16029 NearMisses->push_back(FeaturesNearMiss);
16030 else if (NearMisses && EarlyPredicateNearMiss)
16031 NearMisses->push_back(EarlyPredicateNearMiss);
16032 else if (NearMisses && LatePredicateNearMiss)
16033 NearMisses->push_back(LatePredicateNearMiss);
16034
16035 continue;
16036 } else if (NumNearMisses > 1) {
16037 // This instruction missed in more than one way, so ignore it.
16038 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
16039 "types of mismatch, so not "
16040 "reporting near-miss\n");
16041 continue;
16042 }
16043 std::string Info;
16044 if (!getParser().getTargetParser().getTargetOptions().MCNoDeprecatedWarn &&
16045 MII.getDeprecatedInfo(Inst, getSTI(), Info)) {
16046 SMLoc Loc = ((ARMOperand &)*Operands[0]).getStartLoc();
16047 getParser().Warning(Loc, Info, std::nullopt);
16048 }
16049 DEBUG_WITH_TYPE(
16050 "asm-matcher",
16051 dbgs() << "Opcode result: complete match, selecting this opcode\n");
16052 return Match_Success;
16053 }
16054
16055 // No instruction variants matched exactly.
16056 return Match_NearMisses;
16057}
16058
16059namespace {
16060 struct OperandMatchEntry {
16061 uint16_t Mnemonic;
16062 uint8_t OperandMask;
16063 uint16_t Class;
16064 uint8_t RequiredFeaturesIdx;
16065
16066 StringRef getMnemonic() const {
16067 return StringRef(MnemonicTable + Mnemonic + 1,
16068 MnemonicTable[Mnemonic]);
16069 }
16070 };
16071
16072 // Predicate for searching for an opcode.
16073 struct LessOpcodeOperand {
16074 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
16075 return LHS.getMnemonic() < RHS;
16076 }
16077 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
16078 return LHS < RHS.getMnemonic();
16079 }
16080 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
16081 return LHS.getMnemonic() < RHS.getMnemonic();
16082 }
16083 };
16084} // end anonymous namespace
16085
16086static const OperandMatchEntry OperandMatchTable[891] = {
16087 /* Operand List Mnemonic, Mask, Operand Class, Features */
16088 { 10 /* adc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16089 { 10 /* adc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16090 { 14 /* add */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16091 { 14 /* add */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16092 { 50 /* and */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16093 { 50 /* and */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16094 { 77 /* bfc */, 6 /* 1, 2 */, MCK_Bitfield, AMFBS_IsThumb2 },
16095 { 77 /* bfc */, 6 /* 1, 2 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 },
16096 { 81 /* bfcsel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB },
16097 { 88 /* bfi */, 12 /* 2, 3 */, MCK_Bitfield, AMFBS_IsThumb2 },
16098 { 88 /* bfi */, 12 /* 2, 3 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 },
16099 { 105 /* bic */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16100 { 105 /* bic */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16101 { 158 /* cdp */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16102 { 158 /* cdp */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16103 { 158 /* cdp */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
16104 { 158 /* cdp */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
16105 { 162 /* cdp2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16106 { 162 /* cdp2 */, 28 /* 2, 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16107 { 162 /* cdp2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
16108 { 162 /* cdp2 */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
16109 { 167 /* cinc */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
16110 { 172 /* cinv */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
16111 { 199 /* cmn */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16112 { 203 /* cmp */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16113 { 207 /* cneg */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
16114 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb },
16115 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
16116 { 212 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
16117 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
16118 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
16119 { 212 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2 },
16120 { 266 /* csel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
16121 { 271 /* cset */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
16122 { 276 /* csetm */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
16123 { 282 /* csinc */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
16124 { 288 /* csinv */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
16125 { 294 /* csneg */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
16126 { 300 /* cx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
16127 { 304 /* cx1a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
16128 { 309 /* cx1d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
16129 { 314 /* cx1da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
16130 { 320 /* cx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
16131 { 324 /* cx2a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
16132 { 329 /* cx2d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
16133 { 334 /* cx2da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
16134 { 340 /* cx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
16135 { 344 /* cx3a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
16136 { 349 /* cx3d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
16137 { 354 /* cx3da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
16138 { 396 /* dmb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB },
16139 { 396 /* dmb */, 3 /* 0, 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB },
16140 { 396 /* dmb */, 6 /* 1, 2 */, MCK_MemBarrierOpt, AMFBS_HasDB },
16141 { 400 /* dsb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB },
16142 { 400 /* dsb */, 3 /* 0, 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB },
16143 { 400 /* dsb */, 6 /* 1, 2 */, MCK_MemBarrierOpt, AMFBS_HasDB },
16144 { 404 /* eor */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16145 { 404 /* eor */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16146 { 443 /* fconstd */, 6 /* 1, 2 */, MCK_FPImm, AMFBS_HasVFP3 },
16147 { 451 /* fconsts */, 6 /* 1, 2 */, MCK_FPImm, AMFBS_HasVFP3 },
16148 { 535 /* isb */, 1 /* 0 */, MCK_InstSyncBarrierOpt, AMFBS_IsARM_HasDB },
16149 { 535 /* isb */, 3 /* 0, 1 */, MCK_InstSyncBarrierOpt, AMFBS_IsThumb_HasDB },
16150 { 535 /* isb */, 6 /* 1, 2 */, MCK_InstSyncBarrierOpt, AMFBS_HasDB },
16151 { 539 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsThumb2 },
16152 { 539 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsARM },
16153 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16154 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16155 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16156 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16157 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16158 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16159 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16160 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16161 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16162 { 588 /* ldc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
16163 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16164 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16165 { 588 /* ldc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
16166 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16167 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16168 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16169 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16170 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16171 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16172 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16173 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16174 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16175 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16176 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16177 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16178 { 592 /* ldc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
16179 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16180 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16181 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16182 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16183 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16184 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16185 { 592 /* ldc2 */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
16186 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16187 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16188 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16189 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16190 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16191 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16192 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16193 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16194 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16195 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16196 { 597 /* ldc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
16197 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16198 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16199 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16200 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16201 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16202 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16203 { 597 /* ldc2l */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
16204 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16205 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16206 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16207 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16208 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16209 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16210 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16211 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16212 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16213 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16214 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16215 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16216 { 603 /* ldcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
16217 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16218 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16219 { 603 /* ldcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
16220 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16221 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16222 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16223 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16224 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16225 { 630 /* ldr */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16226 { 634 /* ldrb */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16227 { 639 /* ldrbt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16228 { 645 /* ldrd */, 24 /* 3, 4 */, MCK_AM3Offset, AMFBS_IsARM },
16229 { 677 /* ldrh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
16230 { 682 /* ldrht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
16231 { 688 /* ldrsb */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
16232 { 694 /* ldrsbt */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
16233 { 701 /* ldrsh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
16234 { 707 /* ldrsht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
16235 { 714 /* ldrt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16236 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16237 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
16238 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16239 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16240 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16241 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
16242 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16243 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16244 { 749 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
16245 { 749 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
16246 { 749 /* mcr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16247 { 749 /* mcr2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16248 { 749 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16249 { 749 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16250 { 749 /* mcr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
16251 { 749 /* mcr2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
16252 { 754 /* mcrr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16253 { 754 /* mcrr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
16254 { 754 /* mcrr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16255 { 754 /* mcrr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16256 { 759 /* mcrr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16257 { 759 /* mcrr2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16258 { 759 /* mcrr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
16259 { 759 /* mcrr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
16260 { 773 /* mov */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16261 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16262 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
16263 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16264 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16265 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16266 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
16267 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16268 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16269 { 796 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
16270 { 796 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
16271 { 796 /* mrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16272 { 796 /* mrc2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16273 { 796 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16274 { 796 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16275 { 796 /* mrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
16276 { 796 /* mrc2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
16277 { 801 /* mrrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16278 { 801 /* mrrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
16279 { 801 /* mrrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16280 { 801 /* mrrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16281 { 806 /* mrrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16282 { 806 /* mrrc2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16283 { 806 /* mrrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
16284 { 806 /* mrrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
16285 { 812 /* mrs */, 6 /* 1, 2 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization },
16286 { 812 /* mrs */, 6 /* 1, 2 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass },
16287 { 812 /* mrs */, 6 /* 1, 2 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization },
16288 { 816 /* msr */, 3 /* 0, 1 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization },
16289 { 816 /* msr */, 3 /* 0, 1 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization },
16290 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsThumb2_IsNotMClass },
16291 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass },
16292 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsARM },
16293 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsARM },
16294 { 816 /* msr */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16295 { 824 /* mvn */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16296 { 840 /* orr */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16297 { 840 /* orr */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16298 { 860 /* pkhbt */, 24 /* 3, 4 */, MCK_PKHLSLImm, AMFBS_HasDSP_IsThumb2 },
16299 { 860 /* pkhbt */, 24 /* 3, 4 */, MCK_PKHLSLImm, AMFBS_IsARM_HasV6 },
16300 { 866 /* pkhtb */, 24 /* 3, 4 */, MCK_PKHASRImm, AMFBS_HasDSP_IsThumb2 },
16301 { 866 /* pkhtb */, 24 /* 3, 4 */, MCK_PKHASRImm, AMFBS_IsARM_HasV6 },
16302 { 1011 /* rsb */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16303 { 1011 /* rsb */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16304 { 1015 /* rsc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16305 { 1015 /* rsc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16306 { 1040 /* sbc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16307 { 1040 /* sbc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16308 { 1058 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsThumb_IsNotMClass },
16309 { 1058 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsARM },
16310 { 1521 /* ssat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsThumb2 },
16311 { 1521 /* ssat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 },
16312 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16313 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16314 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16315 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16316 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16317 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16318 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16319 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16320 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16321 { 1556 /* stc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
16322 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16323 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16324 { 1556 /* stc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
16325 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16326 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16327 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16328 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16329 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16330 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16331 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16332 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16333 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16334 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16335 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16336 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16337 { 1560 /* stc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
16338 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16339 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16340 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16341 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16342 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16343 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16344 { 1560 /* stc2 */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
16345 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16346 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16347 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16348 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16349 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16350 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16351 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16352 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16353 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16354 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16355 { 1565 /* stc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
16356 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16357 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16358 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16359 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16360 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16361 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16362 { 1565 /* stc2l */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
16363 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16364 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16365 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16366 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16367 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16368 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16369 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16370 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16371 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16372 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16373 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16374 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16375 { 1571 /* stcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
16376 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16377 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16378 { 1571 /* stcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
16379 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16380 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16381 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16382 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16383 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16384 { 1639 /* str */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16385 { 1643 /* strb */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16386 { 1648 /* strbt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16387 { 1654 /* strd */, 24 /* 3, 4 */, MCK_AM3Offset, AMFBS_IsARM },
16388 { 1686 /* strh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
16389 { 1691 /* strht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
16390 { 1697 /* strt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16391 { 1702 /* sub */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16392 { 1702 /* sub */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16393 { 1729 /* sxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16394 { 1729 /* sxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16395 { 1735 /* sxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16396 { 1735 /* sxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16397 { 1743 /* sxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16398 { 1743 /* sxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16399 { 1749 /* sxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16400 { 1749 /* sxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16401 { 1749 /* sxtb */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16402 { 1754 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16403 { 1754 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16404 { 1754 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16405 { 1761 /* sxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16406 { 1761 /* sxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16407 { 1761 /* sxth */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16408 { 1774 /* teq */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16409 { 1783 /* tsb */, 1 /* 0 */, MCK_TraceSyncBarrierOpt, AMFBS_IsARM_HasV8_4a },
16410 { 1783 /* tsb */, 3 /* 0, 1 */, MCK_TraceSyncBarrierOpt, AMFBS_IsThumb_HasV8_4a },
16411 { 1787 /* tst */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16412 { 1995 /* usat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsThumb2 },
16413 { 1995 /* usat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 },
16414 { 2025 /* uxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16415 { 2025 /* uxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16416 { 2031 /* uxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16417 { 2031 /* uxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16418 { 2039 /* uxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16419 { 2039 /* uxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16420 { 2045 /* uxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16421 { 2045 /* uxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16422 { 2045 /* uxtb */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16423 { 2050 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16424 { 2050 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16425 { 2050 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16426 { 2057 /* uxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16427 { 2057 /* uxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16428 { 2057 /* uxth */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16429 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16430 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16431 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16432 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16433 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16434 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16435 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16436 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16437 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16438 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16439 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16440 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16441 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16442 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16443 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16444 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16445 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16446 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16447 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16448 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16449 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16450 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16451 { 2334 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16452 { 2334 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16453 { 2334 /* vcx1 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16454 { 2339 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16455 { 2339 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16456 { 2339 /* vcx1a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16457 { 2345 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16458 { 2345 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16459 { 2345 /* vcx2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16460 { 2350 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16461 { 2350 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16462 { 2350 /* vcx2a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16463 { 2356 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16464 { 2356 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16465 { 2356 /* vcx3 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16466 { 2361 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16467 { 2361 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16468 { 2361 /* vcx3a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16469 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16470 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16471 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16472 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16473 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16474 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16475 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16476 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16477 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16478 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16479 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16480 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16481 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16482 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16483 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16484 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16485 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16486 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16487 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16488 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16489 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16490 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16491 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16492 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16493 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16494 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16495 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16496 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16497 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16498 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16499 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16500 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16501 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16502 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16503 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16504 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16505 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16506 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16507 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16508 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16509 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16510 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16511 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16512 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16513 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16514 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16515 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16516 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16517 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16518 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16519 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16520 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16521 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16522 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16523 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16524 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16525 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16526 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16527 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16528 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16529 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16530 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16531 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16532 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16533 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16534 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16535 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16536 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16537 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16538 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16539 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16540 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16541 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16542 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16543 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16544 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16545 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16546 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16547 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16548 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16549 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16550 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16551 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16552 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16553 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16554 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16555 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16556 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16557 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16558 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16559 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16560 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16561 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16562 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16563 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16564 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16565 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16566 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16567 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16568 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16569 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16570 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16571 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16572 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16573 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16574 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16575 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16576 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16577 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16578 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16579 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16580 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16581 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16582 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16583 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16584 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16585 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16586 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16587 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16588 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16589 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16590 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16591 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16592 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16593 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16594 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16595 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16596 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16597 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16598 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16599 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16600 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16601 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16602 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16603 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16604 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16605 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16606 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16607 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16608 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16609 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16610 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16611 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16612 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16613 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16614 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16615 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16616 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16617 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16618 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16619 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16620 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16621 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16622 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16623 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16624 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16625 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16626 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16627 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16628 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16629 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16630 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16631 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16632 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16633 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16634 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16635 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16636 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16637 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16638 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16639 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16640 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16641 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16642 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16643 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16644 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16645 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16646 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16647 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16648 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16649 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16650 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16651 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16652 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16653 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16654 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16655 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16656 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16657 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16658 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16659 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16660 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16661 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16662 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16663 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16664 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16665 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16666 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16667 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16668 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16669 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16670 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16671 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16672 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16673 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16674 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16675 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16676 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16677 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16678 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16679 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16680 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16681 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16682 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16683 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16684 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16685 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16686 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16687 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16688 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16689 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16690 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16691 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16692 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16693 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16694 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16695 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16696 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16697 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16698 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16699 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16700 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16701 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16702 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16703 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16704 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16705 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16706 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16707 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16708 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16709 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16710 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16711 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16712 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16713 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16714 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16715 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16716 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16717 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16718 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16719 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16720 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16721 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16722 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16723 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16724 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16725 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16726 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16727 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16728 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16729 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16730 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16731 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16732 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16733 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16734 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16735 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16736 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16737 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16738 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16739 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16740 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16741 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16742 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasNEON },
16743 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasNEON },
16744 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasVFP3 },
16745 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasVFP3_HasDPVFP },
16746 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasFullFP16 },
16747 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasMVEInt },
16748 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16749 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16750 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16751 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16752 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16753 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16754 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16755 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16756 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16757 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16758 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16759 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16760 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16761 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16762 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16763 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16764 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16765 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16766 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16767 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16768 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16769 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16770 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16771 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16772 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16773 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16774 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16775 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16776 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16777 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16778 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16779 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16780 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16781 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16782 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16783 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16784 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16785 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16786 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16787 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16788 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16789 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16790 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16791 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16792 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16793 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16794 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16795 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16796 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16797 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16798 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16799 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16800 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16801 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16802 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16803 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16804 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16805 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16806 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16807 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16808 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16809 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16810 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16811 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16812 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16813 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16814 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16815 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16816 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16817 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16818 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16819 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16820 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16821 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16822 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16823 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16824 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16825 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16826 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16827 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16828 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16829 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16830 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16831 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16832 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16833 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16834 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16835 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16836 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16837 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16838 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16839 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16840 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16841 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16842 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16843 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16844 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16845 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16846 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16847 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16848 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16849 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16850 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16851 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16852 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16853 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16854 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16855 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16856 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16857 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16858 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16859 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16860 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16861 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16862 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16863 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16864 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16865 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16866 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16867 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16868 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16869 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16870 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16871 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16872 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16873 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16874 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16875 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16876 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16877 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16878 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16879 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16880 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16881 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16882 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16883 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16884 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16885 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16886 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16887 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16888 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16889 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16890 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16891 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16892 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16893 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16894 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16895 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16896 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16897 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16898 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16899 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16900 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16901 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16902 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16903 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16904 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16905 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16906 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16907 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16908 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16909 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16910 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16911 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16912 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16913 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16914 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16915 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16916 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16917 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16918 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16919 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16920 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16921 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16922 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16923 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16924 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16925 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16926 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16927 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16928 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16929 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16930 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16931 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16932 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16933 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16934 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16935 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16936 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16937 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16938 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16939 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16940 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16941 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16942 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16943 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16944 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16945 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16946 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16947 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16948 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16949 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16950 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16951 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16952 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16953 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16954 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16955 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16956 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16957 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16958 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16959 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16960 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16961 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16962 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16963 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16964 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16965 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16966 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16967 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16968 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16969 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16970 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16971 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListDPair, AMFBS_HasNEON },
16972 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListFourD, AMFBS_HasNEON },
16973 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListOneD, AMFBS_HasNEON },
16974 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListThreeD, AMFBS_HasNEON },
16975 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListDPair, AMFBS_HasNEON },
16976 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListFourD, AMFBS_HasNEON },
16977 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListOneD, AMFBS_HasNEON },
16978 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListThreeD, AMFBS_HasNEON },
16979};
16980
16981ParseStatus ARMAsmParser::
16982tryCustomParseOperand(OperandVector &Operands,
16983 unsigned MCK) {
16984
16985 switch(MCK) {
16986 case MCK_AM3Offset:
16987 return parseAM3Offset(Operands);
16988 case MCK_BankedReg:
16989 return parseBankedRegOperand(Operands);
16990 case MCK_Bitfield:
16991 return parseBitfield(Operands);
16992 case MCK_CoprocNum:
16993 return parseCoprocNumOperand(Operands);
16994 case MCK_CoprocOption:
16995 return parseCoprocOptionOperand(Operands);
16996 case MCK_CoprocReg:
16997 return parseCoprocRegOperand(Operands);
16998 case MCK_FPImm:
16999 return parseFPImm(Operands);
17000 case MCK_InstSyncBarrierOpt:
17001 return parseInstSyncBarrierOptOperand(Operands);
17002 case MCK_MSRMask:
17003 return parseMSRMaskOperand(Operands);
17004 case MCK_MemBarrierOpt:
17005 return parseMemBarrierOptOperand(Operands);
17006 case MCK_ModImm:
17007 return parseModImm(Operands);
17008 case MCK_PKHASRImm:
17009 return parsePKHASRImm(Operands);
17010 case MCK_PKHLSLImm:
17011 return parsePKHLSLImm(Operands);
17012 case MCK_PostIdxReg:
17013 return parsePostIdxReg(Operands);
17014 case MCK_PostIdxRegShifted:
17015 return parsePostIdxReg(Operands);
17016 case MCK_ProcIFlags:
17017 return parseProcIFlagsOperand(Operands);
17018 case MCK_RotImm:
17019 return parseRotImm(Operands);
17020 case MCK_SetEndImm:
17021 return parseSetEndImm(Operands);
17022 case MCK_ShifterImm:
17023 return parseShifterImm(Operands);
17024 case MCK_TraceSyncBarrierOpt:
17025 return parseTraceSyncBarrierOptOperand(Operands);
17026 case MCK_VecListTwoMQ:
17027 return parseVectorList(Operands);
17028 case MCK_VecListFourMQ:
17029 return parseVectorList(Operands);
17030 case MCK_VecListDPairAllLanes:
17031 return parseVectorList(Operands);
17032 case MCK_VecListDPair:
17033 return parseVectorList(Operands);
17034 case MCK_VecListDPairSpacedAllLanes:
17035 return parseVectorList(Operands);
17036 case MCK_VecListDPairSpaced:
17037 return parseVectorList(Operands);
17038 case MCK_VecListFourDAllLanes:
17039 return parseVectorList(Operands);
17040 case MCK_VecListFourD:
17041 return parseVectorList(Operands);
17042 case MCK_VecListFourDByteIndexed:
17043 return parseVectorList(Operands);
17044 case MCK_VecListFourDHWordIndexed:
17045 return parseVectorList(Operands);
17046 case MCK_VecListFourDWordIndexed:
17047 return parseVectorList(Operands);
17048 case MCK_VecListFourQAllLanes:
17049 return parseVectorList(Operands);
17050 case MCK_VecListFourQ:
17051 return parseVectorList(Operands);
17052 case MCK_VecListFourQHWordIndexed:
17053 return parseVectorList(Operands);
17054 case MCK_VecListFourQWordIndexed:
17055 return parseVectorList(Operands);
17056 case MCK_VecListOneDAllLanes:
17057 return parseVectorList(Operands);
17058 case MCK_VecListOneD:
17059 return parseVectorList(Operands);
17060 case MCK_VecListOneDByteIndexed:
17061 return parseVectorList(Operands);
17062 case MCK_VecListOneDHWordIndexed:
17063 return parseVectorList(Operands);
17064 case MCK_VecListOneDWordIndexed:
17065 return parseVectorList(Operands);
17066 case MCK_VecListThreeDAllLanes:
17067 return parseVectorList(Operands);
17068 case MCK_VecListThreeD:
17069 return parseVectorList(Operands);
17070 case MCK_VecListThreeDByteIndexed:
17071 return parseVectorList(Operands);
17072 case MCK_VecListThreeDHWordIndexed:
17073 return parseVectorList(Operands);
17074 case MCK_VecListThreeDWordIndexed:
17075 return parseVectorList(Operands);
17076 case MCK_VecListThreeQAllLanes:
17077 return parseVectorList(Operands);
17078 case MCK_VecListThreeQ:
17079 return parseVectorList(Operands);
17080 case MCK_VecListThreeQHWordIndexed:
17081 return parseVectorList(Operands);
17082 case MCK_VecListThreeQWordIndexed:
17083 return parseVectorList(Operands);
17084 case MCK_VecListTwoDByteIndexed:
17085 return parseVectorList(Operands);
17086 case MCK_VecListTwoDHWordIndexed:
17087 return parseVectorList(Operands);
17088 case MCK_VecListTwoDWordIndexed:
17089 return parseVectorList(Operands);
17090 case MCK_VecListTwoQHWordIndexed:
17091 return parseVectorList(Operands);
17092 case MCK_VecListTwoQWordIndexed:
17093 return parseVectorList(Operands);
17094 case MCK_ITCondCode:
17095 return parseITCondCode(Operands);
17096 case MCK_CondCodeNoAL:
17097 return parseITCondCode(Operands);
17098 case MCK_CondCodeNoALInv:
17099 return parseITCondCode(Operands);
17100 case MCK_CondCodeRestrictedFP:
17101 return parseITCondCode(Operands);
17102 case MCK_CondCodeRestrictedI:
17103 return parseITCondCode(Operands);
17104 case MCK_CondCodeRestrictedS:
17105 return parseITCondCode(Operands);
17106 case MCK_CondCodeRestrictedU:
17107 return parseITCondCode(Operands);
17108 default:
17109 return ParseStatus::NoMatch;
17110 }
17111 return ParseStatus::NoMatch;
17112}
17113
17114ParseStatus ARMAsmParser::
17115MatchOperandParserImpl(OperandVector &Operands,
17116 StringRef Mnemonic,
17117 bool ParseForAllFeatures) {
17118 // Get the current feature set.
17119 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
17120
17121 // Get the next operand index.
17122 unsigned NextOpNum = Operands.size() - 1;
17123 // Search the table.
17124 auto MnemonicRange =
17125 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
17126 Mnemonic, LessOpcodeOperand());
17127
17128 if (MnemonicRange.first == MnemonicRange.second)
17129 return ParseStatus::NoMatch;
17130
17131 for (const OperandMatchEntry *it = MnemonicRange.first,
17132 *ie = MnemonicRange.second; it != ie; ++it) {
17133 // equal_range guarantees that instruction mnemonic matches.
17134 assert(Mnemonic == it->getMnemonic());
17135
17136 // check if the available features match
17137 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
17138 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
17139 continue;
17140
17141 // check if the operand in question has a custom parser.
17142 if (!(it->OperandMask & (1 << NextOpNum)))
17143 continue;
17144
17145 // call custom parse method to handle the operand
17146 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
17147 if (!Result.isNoMatch())
17148 return Result;
17149 }
17150
17151 // Okay, we had no match.
17152 return ParseStatus::NoMatch;
17153}
17154
17155#endif // GET_MATCHER_IMPLEMENTATION
17156
17157
17158#ifdef GET_MNEMONIC_SPELL_CHECKER
17159#undef GET_MNEMONIC_SPELL_CHECKER
17160
17161static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
17162 const unsigned MaxEditDist = 2;
17163 std::vector<StringRef> Candidates;
17164 StringRef Prev = "";
17165
17166 // Find the appropriate table for this asm variant.
17167 const MatchEntry *Start, *End;
17168 switch (VariantID) {
17169 default: llvm_unreachable("invalid variant!");
17170 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
17171 }
17172
17173 for (auto I = Start; I < End; I++) {
17174 // Ignore unsupported instructions.
17175 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
17176 if ((FBS & RequiredFeatures) != RequiredFeatures)
17177 continue;
17178
17179 StringRef T = I->getMnemonic();
17180 // Avoid recomputing the edit distance for the same string.
17181 if (T == Prev)
17182 continue;
17183
17184 Prev = T;
17185 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
17186 if (Dist <= MaxEditDist)
17187 Candidates.push_back(T);
17188 }
17189
17190 if (Candidates.empty())
17191 return "";
17192
17193 std::string Res = ", did you mean: ";
17194 unsigned i = 0;
17195 for (; i < Candidates.size() - 1; i++)
17196 Res += Candidates[i].str() + ", ";
17197 return Res + Candidates[i].str() + "?";
17198}
17199
17200#endif // GET_MNEMONIC_SPELL_CHECKER
17201
17202
17203#ifdef GET_MNEMONIC_CHECKER
17204#undef GET_MNEMONIC_CHECKER
17205
17206static bool ARMCheckMnemonic(StringRef Mnemonic,
17207 const FeatureBitset &AvailableFeatures,
17208 unsigned VariantID) {
17209 // Process all MnemonicAliases to remap the mnemonic.
17210 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
17211
17212 // Find the appropriate table for this asm variant.
17213 const MatchEntry *Start, *End;
17214 switch (VariantID) {
17215 default: llvm_unreachable("invalid variant!");
17216 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
17217 }
17218
17219 // Search the table.
17220 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
17221
17222 if (MnemonicRange.first == MnemonicRange.second)
17223 return false;
17224
17225 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
17226 it != ie; ++it) {
17227 const FeatureBitset &RequiredFeatures =
17228 FeatureBitsets[it->RequiredFeaturesIdx];
17229 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
17230 return true;
17231 }
17232 return false;
17233}
17234
17235#endif // GET_MNEMONIC_CHECKER
17236
17237