1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47
48
49bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
50 MVT LocVT, CCValAssign::LocInfo LocInfo,
51 ISD::ArgFlagsTy ArgFlags, CCState &State) {
52
53 if (ArgFlags.isByVal()) {
54 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
55 return false;
56 }
57
58 if (ArgFlags.isNest()) {
59 if (unsigned Reg = State.AllocateReg(Reg: ARM::R12)) {
60 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
61 return false;
62 }
63 }
64
65 if (LocVT == MVT::v1i64 ||
66 LocVT == MVT::v2i32 ||
67 LocVT == MVT::v4i16 ||
68 LocVT == MVT::v4f16 ||
69 LocVT == MVT::v4bf16 ||
70 LocVT == MVT::v8i8 ||
71 LocVT == MVT::v2f32) {
72 LocVT = MVT::f64;
73 LocInfo = CCValAssign::BCvt;
74 }
75
76 if (LocVT == MVT::v2i64 ||
77 LocVT == MVT::v4i32 ||
78 LocVT == MVT::v8i16 ||
79 LocVT == MVT::v8f16 ||
80 LocVT == MVT::v8bf16 ||
81 LocVT == MVT::v16i8 ||
82 LocVT == MVT::v4f32) {
83 LocVT = MVT::v2f64;
84 LocInfo = CCValAssign::BCvt;
85 }
86
87 if (ArgFlags.isSwiftSelf()) {
88 if (LocVT == MVT::i32) {
89 if (unsigned Reg = State.AllocateReg(Reg: ARM::R10)) {
90 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
91 return false;
92 }
93 }
94 }
95
96 if (ArgFlags.isSwiftError()) {
97 if (LocVT == MVT::i32) {
98 if (unsigned Reg = State.AllocateReg(Reg: ARM::R8)) {
99 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
100 return false;
101 }
102 }
103 }
104
105 if (LocVT == MVT::f64 ||
106 LocVT == MVT::v2f64) {
107 if (CC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
108 return false;
109 }
110
111 if (LocVT == MVT::f32) {
112 LocVT = MVT::i32;
113 LocInfo = CCValAssign::BCvt;
114 }
115
116 if (LocVT == MVT::f16 ||
117 LocVT == MVT::bf16) {
118 if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
119 return false;
120 }
121
122 if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
123 return false;
124
125 return true; // CC didn't match.
126}
127
128
129static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
130 MVT LocVT, CCValAssign::LocInfo LocInfo,
131 ISD::ArgFlagsTy ArgFlags, CCState &State) {
132
133 if (LocVT == MVT::i1 ||
134 LocVT == MVT::i8 ||
135 LocVT == MVT::i16) {
136 LocVT = MVT::i32;
137 if (ArgFlags.isSExt())
138 LocInfo = CCValAssign::SExt;
139 else if (ArgFlags.isZExt())
140 LocInfo = CCValAssign::ZExt;
141 else
142 LocInfo = CCValAssign::AExt;
143 }
144
145 if (LocVT == MVT::i32) {
146 if (ArgFlags.getNonZeroOrigAlign() == 8) {
147 static const MCPhysReg RegList1[] = {
148 ARM::R0, ARM::R2
149 };
150 static const MCPhysReg RegList2[] = {
151 ARM::R0, ARM::R1
152 };
153 if (unsigned Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
154 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
155 return false;
156 }
157 }
158 }
159
160 if (LocVT == MVT::i32) {
161 if (ArgFlags.getNonZeroOrigAlign() != Align(8)) {
162 static const MCPhysReg RegList3[] = {
163 ARM::R0, ARM::R1, ARM::R2, ARM::R3
164 };
165 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
166 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
167 return false;
168 }
169 }
170 }
171
172 if (LocVT == MVT::i32) {
173 if (ArgFlags.getNonZeroOrigAlign() == 8) {
174 static const MCPhysReg ShadowRegList4[] = {
175 ARM::R0, ARM::R1, ARM::R2, ARM::R3
176 };
177 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(8), ShadowRegs: ShadowRegList4);
178 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
179 return false;
180 }
181 }
182
183 if (LocVT == MVT::i32) {
184 static const MCPhysReg ShadowRegList6[] = {
185 ARM::R0, ARM::R1, ARM::R2, ARM::R3
186 };
187 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList6);
188 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
189 return false;
190 }
191
192 if (LocVT == MVT::f16 ||
193 LocVT == MVT::bf16 ||
194 LocVT == MVT::f32) {
195 static const MCPhysReg ShadowRegList8[] = {
196 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
197 };
198 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList8);
199 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
200 return false;
201 }
202
203 if (LocVT == MVT::f64) {
204 static const MCPhysReg ShadowRegList10[] = {
205 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
206 };
207 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8), ShadowRegs: ShadowRegList10);
208 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
209 return false;
210 }
211
212 if (LocVT == MVT::v2f64) {
213 if (ArgFlags.getNonZeroOrigAlign() == 16) {
214 static const MCPhysReg ShadowRegList12[] = {
215 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
216 };
217 int64_t Offset13 = State.AllocateStack(Size: 16, Alignment: Align(16), ShadowRegs: ShadowRegList12);
218 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
219 return false;
220 }
221 }
222
223 if (LocVT == MVT::v2f64) {
224 static const MCPhysReg ShadowRegList14[] = {
225 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
226 };
227 int64_t Offset15 = State.AllocateStack(Size: 16, Alignment: Align(8), ShadowRegs: ShadowRegList14);
228 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
229 return false;
230 }
231
232 return true; // CC didn't match.
233}
234
235
236bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
237 MVT LocVT, CCValAssign::LocInfo LocInfo,
238 ISD::ArgFlagsTy ArgFlags, CCState &State) {
239
240 if (ArgFlags.isByVal()) {
241 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
242 return false;
243 }
244
245 if (LocVT == MVT::v1i64 ||
246 LocVT == MVT::v2i32 ||
247 LocVT == MVT::v4i16 ||
248 LocVT == MVT::v4f16 ||
249 LocVT == MVT::v4bf16 ||
250 LocVT == MVT::v8i8 ||
251 LocVT == MVT::v2f32) {
252 LocVT = MVT::f64;
253 LocInfo = CCValAssign::BCvt;
254 }
255
256 if (LocVT == MVT::v2i64 ||
257 LocVT == MVT::v4i32 ||
258 LocVT == MVT::v8i16 ||
259 LocVT == MVT::v8f16 ||
260 LocVT == MVT::v8bf16 ||
261 LocVT == MVT::v16i8 ||
262 LocVT == MVT::v4f32) {
263 LocVT = MVT::v2f64;
264 LocInfo = CCValAssign::BCvt;
265 }
266
267 if (ArgFlags.isSwiftSelf()) {
268 if (LocVT == MVT::i32) {
269 if (unsigned Reg = State.AllocateReg(Reg: ARM::R10)) {
270 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
271 return false;
272 }
273 }
274 }
275
276 if (ArgFlags.isSwiftError()) {
277 if (LocVT == MVT::i32) {
278 if (unsigned Reg = State.AllocateReg(Reg: ARM::R8)) {
279 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
280 return false;
281 }
282 }
283 }
284
285 if (ArgFlags.isInConsecutiveRegs()) {
286 if (CC_ARM_AAPCS_Custom_Aggregate(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
287 return false;
288 }
289
290 if (LocVT == MVT::v2f64) {
291 static const MCPhysReg RegList1[] = {
292 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
293 };
294 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
295 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
296 return false;
297 }
298 }
299
300 if (LocVT == MVT::f64) {
301 static const MCPhysReg RegList2[] = {
302 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
303 };
304 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
305 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
306 return false;
307 }
308 }
309
310 if (LocVT == MVT::f32) {
311 static const MCPhysReg RegList3[] = {
312 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
313 };
314 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
315 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
316 return false;
317 }
318 }
319
320 if (LocVT == MVT::f16 ||
321 LocVT == MVT::bf16) {
322 if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
323 return false;
324 }
325
326 if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
327 return false;
328
329 return true; // CC didn't match.
330}
331
332
333bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
334 MVT LocVT, CCValAssign::LocInfo LocInfo,
335 ISD::ArgFlagsTy ArgFlags, CCState &State) {
336
337 if (ArgFlags.isByVal()) {
338 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
339 return false;
340 }
341
342 if (LocVT == MVT::i1 ||
343 LocVT == MVT::i8 ||
344 LocVT == MVT::i16) {
345 LocVT = MVT::i32;
346 if (ArgFlags.isSExt())
347 LocInfo = CCValAssign::SExt;
348 else if (ArgFlags.isZExt())
349 LocInfo = CCValAssign::ZExt;
350 else
351 LocInfo = CCValAssign::AExt;
352 }
353
354 if (ArgFlags.isSwiftSelf()) {
355 if (LocVT == MVT::i32) {
356 if (unsigned Reg = State.AllocateReg(Reg: ARM::R10)) {
357 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
358 return false;
359 }
360 }
361 }
362
363 if (ArgFlags.isSwiftError()) {
364 if (LocVT == MVT::i32) {
365 if (unsigned Reg = State.AllocateReg(Reg: ARM::R8)) {
366 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
367 return false;
368 }
369 }
370 }
371
372 if (LocVT == MVT::v1i64 ||
373 LocVT == MVT::v2i32 ||
374 LocVT == MVT::v4i16 ||
375 LocVT == MVT::v4f16 ||
376 LocVT == MVT::v4bf16 ||
377 LocVT == MVT::v8i8 ||
378 LocVT == MVT::v2f32) {
379 LocVT = MVT::f64;
380 LocInfo = CCValAssign::BCvt;
381 }
382
383 if (LocVT == MVT::v2i64 ||
384 LocVT == MVT::v4i32 ||
385 LocVT == MVT::v8i16 ||
386 LocVT == MVT::v8f16 ||
387 LocVT == MVT::v8bf16 ||
388 LocVT == MVT::v16i8 ||
389 LocVT == MVT::v4f32) {
390 LocVT = MVT::v2f64;
391 LocInfo = CCValAssign::BCvt;
392 }
393
394 if (LocVT == MVT::f64 ||
395 LocVT == MVT::v2f64) {
396 if (CC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
397 return false;
398 }
399
400 if (LocVT == MVT::f32) {
401 LocVT = MVT::i32;
402 LocInfo = CCValAssign::BCvt;
403 }
404
405 if (LocVT == MVT::i32) {
406 static const MCPhysReg RegList1[] = {
407 ARM::R0, ARM::R1, ARM::R2, ARM::R3
408 };
409 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
410 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
411 return false;
412 }
413 }
414
415 if (LocVT == MVT::i32) {
416 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
417 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
418 return false;
419 }
420
421 if (LocVT == MVT::f64) {
422 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(4));
423 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
424 return false;
425 }
426
427 if (LocVT == MVT::v2f64) {
428 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(4));
429 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
430 return false;
431 }
432
433 return true; // CC didn't match.
434}
435
436
437bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
438 MVT LocVT, CCValAssign::LocInfo LocInfo,
439 ISD::ArgFlagsTy ArgFlags, CCState &State) {
440
441 if (LocVT == MVT::v1i64 ||
442 LocVT == MVT::v2i32 ||
443 LocVT == MVT::v4i16 ||
444 LocVT == MVT::v4f16 ||
445 LocVT == MVT::v4bf16 ||
446 LocVT == MVT::v8i8 ||
447 LocVT == MVT::v2f32) {
448 LocVT = MVT::f64;
449 LocInfo = CCValAssign::BCvt;
450 }
451
452 if (LocVT == MVT::v2i64 ||
453 LocVT == MVT::v4i32 ||
454 LocVT == MVT::v8i16 ||
455 LocVT == MVT::v8f16 ||
456 LocVT == MVT::v8bf16 ||
457 LocVT == MVT::v16i8 ||
458 LocVT == MVT::v4f32) {
459 LocVT = MVT::v2f64;
460 LocInfo = CCValAssign::BCvt;
461 }
462
463 if (LocVT == MVT::v2f64) {
464 static const MCPhysReg RegList1[] = {
465 ARM::Q4, ARM::Q5
466 };
467 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
468 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
469 return false;
470 }
471 }
472
473 if (LocVT == MVT::f64) {
474 static const MCPhysReg RegList2[] = {
475 ARM::D8, ARM::D9, ARM::D10, ARM::D11
476 };
477 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
478 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
479 return false;
480 }
481 }
482
483 if (LocVT == MVT::f32) {
484 static const MCPhysReg RegList3[] = {
485 ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23
486 };
487 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
488 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
489 return false;
490 }
491 }
492
493 if (LocVT == MVT::i8 ||
494 LocVT == MVT::i16) {
495 LocVT = MVT::i32;
496 if (ArgFlags.isSExt())
497 LocInfo = CCValAssign::SExt;
498 else if (ArgFlags.isZExt())
499 LocInfo = CCValAssign::ZExt;
500 else
501 LocInfo = CCValAssign::AExt;
502 }
503
504 if (LocVT == MVT::i32) {
505 static const MCPhysReg RegList4[] = {
506 ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11
507 };
508 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
509 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
510 return false;
511 }
512 }
513
514 return true; // CC didn't match.
515}
516
517
518bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
519 MVT LocVT, CCValAssign::LocInfo LocInfo,
520 ISD::ArgFlagsTy ArgFlags, CCState &State) {
521
522 if (LocVT == MVT::i32) {
523 if (unsigned Reg = State.AllocateReg(Reg: ARM::R0)) {
524 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
525 return false;
526 }
527 }
528
529 return true; // CC didn't match.
530}
531
532
533bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
534 MVT LocVT, CCValAssign::LocInfo LocInfo,
535 ISD::ArgFlagsTy ArgFlags, CCState &State) {
536
537 if (LocVT == MVT::v1i64 ||
538 LocVT == MVT::v2i32 ||
539 LocVT == MVT::v4i16 ||
540 LocVT == MVT::v4f16 ||
541 LocVT == MVT::v4bf16 ||
542 LocVT == MVT::v8i8 ||
543 LocVT == MVT::v2f32) {
544 LocVT = MVT::f64;
545 LocInfo = CCValAssign::BCvt;
546 }
547
548 if (LocVT == MVT::v2i64 ||
549 LocVT == MVT::v4i32 ||
550 LocVT == MVT::v8i16 ||
551 LocVT == MVT::v8f16 ||
552 LocVT == MVT::v8bf16 ||
553 LocVT == MVT::v16i8 ||
554 LocVT == MVT::v4f32) {
555 LocVT = MVT::v2f64;
556 LocInfo = CCValAssign::BCvt;
557 }
558
559 if (LocVT == MVT::v2f64) {
560 static const MCPhysReg RegList1[] = {
561 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
562 };
563 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
564 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
565 return false;
566 }
567 }
568
569 if (LocVT == MVT::f64) {
570 static const MCPhysReg RegList2[] = {
571 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
572 };
573 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
574 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
575 return false;
576 }
577 }
578
579 if (LocVT == MVT::f32) {
580 static const MCPhysReg RegList3[] = {
581 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
582 };
583 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
584 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
585 return false;
586 }
587 }
588
589 if (LocVT == MVT::f32) {
590 static const MCPhysReg ShadowRegList4[] = {
591 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
592 };
593 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList4);
594 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
595 return false;
596 }
597
598 if (LocVT == MVT::f64) {
599 static const MCPhysReg ShadowRegList6[] = {
600 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
601 };
602 int64_t Offset7 = State.AllocateStack(Size: 8, Alignment: Align(4), ShadowRegs: ShadowRegList6);
603 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
604 return false;
605 }
606
607 if (LocVT == MVT::v2f64) {
608 static const MCPhysReg ShadowRegList8[] = {
609 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
610 };
611 int64_t Offset9 = State.AllocateStack(Size: 16, Alignment: Align(4), ShadowRegs: ShadowRegList8);
612 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
613 return false;
614 }
615
616 if (!CC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
617 return false;
618
619 return true; // CC didn't match.
620}
621
622
623bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
624 MVT LocVT, CCValAssign::LocInfo LocInfo,
625 ISD::ArgFlagsTy ArgFlags, CCState &State) {
626
627 if (LocVT == MVT::v1i64 ||
628 LocVT == MVT::v2i32 ||
629 LocVT == MVT::v4i16 ||
630 LocVT == MVT::v4f16 ||
631 LocVT == MVT::v4bf16 ||
632 LocVT == MVT::v8i8 ||
633 LocVT == MVT::v2f32) {
634 LocVT = MVT::f64;
635 LocInfo = CCValAssign::BCvt;
636 }
637
638 if (LocVT == MVT::v2i64 ||
639 LocVT == MVT::v4i32 ||
640 LocVT == MVT::v8i16 ||
641 LocVT == MVT::v8f16 ||
642 LocVT == MVT::v8bf16 ||
643 LocVT == MVT::v16i8 ||
644 LocVT == MVT::v4f32) {
645 LocVT = MVT::v2f64;
646 LocInfo = CCValAssign::BCvt;
647 }
648
649 if (ArgFlags.isSwiftSelf()) {
650 if (LocVT == MVT::i32) {
651 if (unsigned Reg = State.AllocateReg(Reg: ARM::R10)) {
652 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
653 return false;
654 }
655 }
656 }
657
658 if (ArgFlags.isSwiftError()) {
659 if (LocVT == MVT::i32) {
660 if (unsigned Reg = State.AllocateReg(Reg: ARM::R8)) {
661 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
662 return false;
663 }
664 }
665 }
666
667 if (LocVT == MVT::f64 ||
668 LocVT == MVT::v2f64) {
669 if (RetCC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
670 return false;
671 }
672
673 if (LocVT == MVT::f32) {
674 LocVT = MVT::i32;
675 LocInfo = CCValAssign::BCvt;
676 }
677
678 if (LocVT == MVT::f16 ||
679 LocVT == MVT::bf16) {
680 if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
681 return false;
682 }
683
684 if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
685 return false;
686
687 return true; // CC didn't match.
688}
689
690
691static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
692 MVT LocVT, CCValAssign::LocInfo LocInfo,
693 ISD::ArgFlagsTy ArgFlags, CCState &State) {
694
695 if (LocVT == MVT::i1 ||
696 LocVT == MVT::i8 ||
697 LocVT == MVT::i16) {
698 LocVT = MVT::i32;
699 if (ArgFlags.isSExt())
700 LocInfo = CCValAssign::SExt;
701 else if (ArgFlags.isZExt())
702 LocInfo = CCValAssign::ZExt;
703 else
704 LocInfo = CCValAssign::AExt;
705 }
706
707 if (LocVT == MVT::i32) {
708 static const MCPhysReg RegList1[] = {
709 ARM::R0, ARM::R1, ARM::R2, ARM::R3
710 };
711 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
712 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
713 return false;
714 }
715 }
716
717 if (LocVT == MVT::i64) {
718 static const MCPhysReg RegList2[] = {
719 ARM::R0, ARM::R2
720 };
721 static const MCPhysReg RegList3[] = {
722 ARM::R1, ARM::R3
723 };
724 if (unsigned Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
725 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
726 return false;
727 }
728 }
729
730 return true; // CC didn't match.
731}
732
733
734bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
735 MVT LocVT, CCValAssign::LocInfo LocInfo,
736 ISD::ArgFlagsTy ArgFlags, CCState &State) {
737
738 if (LocVT == MVT::v1i64 ||
739 LocVT == MVT::v2i32 ||
740 LocVT == MVT::v4i16 ||
741 LocVT == MVT::v4f16 ||
742 LocVT == MVT::v4bf16 ||
743 LocVT == MVT::v8i8 ||
744 LocVT == MVT::v2f32) {
745 LocVT = MVT::f64;
746 LocInfo = CCValAssign::BCvt;
747 }
748
749 if (LocVT == MVT::v2i64 ||
750 LocVT == MVT::v4i32 ||
751 LocVT == MVT::v8i16 ||
752 LocVT == MVT::v8f16 ||
753 LocVT == MVT::v8bf16 ||
754 LocVT == MVT::v16i8 ||
755 LocVT == MVT::v4f32) {
756 LocVT = MVT::v2f64;
757 LocInfo = CCValAssign::BCvt;
758 }
759
760 if (ArgFlags.isSwiftSelf()) {
761 if (LocVT == MVT::i32) {
762 if (unsigned Reg = State.AllocateReg(Reg: ARM::R10)) {
763 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
764 return false;
765 }
766 }
767 }
768
769 if (ArgFlags.isSwiftError()) {
770 if (LocVT == MVT::i32) {
771 if (unsigned Reg = State.AllocateReg(Reg: ARM::R8)) {
772 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
773 return false;
774 }
775 }
776 }
777
778 if (LocVT == MVT::v2f64) {
779 static const MCPhysReg RegList1[] = {
780 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
781 };
782 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
783 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
784 return false;
785 }
786 }
787
788 if (LocVT == MVT::f64) {
789 static const MCPhysReg RegList2[] = {
790 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
791 };
792 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
793 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
794 return false;
795 }
796 }
797
798 if (LocVT == MVT::f32) {
799 static const MCPhysReg RegList3[] = {
800 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
801 };
802 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
803 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
804 return false;
805 }
806 }
807
808 if (LocVT == MVT::f16 ||
809 LocVT == MVT::bf16) {
810 if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
811 return false;
812 }
813
814 if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
815 return false;
816
817 return true; // CC didn't match.
818}
819
820
821bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT,
822 MVT LocVT, CCValAssign::LocInfo LocInfo,
823 ISD::ArgFlagsTy ArgFlags, CCState &State) {
824
825 if (LocVT == MVT::i1 ||
826 LocVT == MVT::i8 ||
827 LocVT == MVT::i16) {
828 LocVT = MVT::i32;
829 if (ArgFlags.isSExt())
830 LocInfo = CCValAssign::SExt;
831 else if (ArgFlags.isZExt())
832 LocInfo = CCValAssign::ZExt;
833 else
834 LocInfo = CCValAssign::AExt;
835 }
836
837 if (LocVT == MVT::f32) {
838 LocVT = MVT::i32;
839 LocInfo = CCValAssign::BCvt;
840 }
841
842 if (ArgFlags.isSwiftSelf()) {
843 if (LocVT == MVT::i32) {
844 if (unsigned Reg = State.AllocateReg(Reg: ARM::R10)) {
845 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
846 return false;
847 }
848 }
849 }
850
851 if (ArgFlags.isSwiftError()) {
852 if (LocVT == MVT::i32) {
853 if (unsigned Reg = State.AllocateReg(Reg: ARM::R8)) {
854 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
855 return false;
856 }
857 }
858 }
859
860 if (LocVT == MVT::v1i64 ||
861 LocVT == MVT::v2i32 ||
862 LocVT == MVT::v4i16 ||
863 LocVT == MVT::v4f16 ||
864 LocVT == MVT::v4bf16 ||
865 LocVT == MVT::v8i8 ||
866 LocVT == MVT::v2f32) {
867 LocVT = MVT::f64;
868 LocInfo = CCValAssign::BCvt;
869 }
870
871 if (LocVT == MVT::v2i64 ||
872 LocVT == MVT::v4i32 ||
873 LocVT == MVT::v8i16 ||
874 LocVT == MVT::v8f16 ||
875 LocVT == MVT::v8bf16 ||
876 LocVT == MVT::v16i8 ||
877 LocVT == MVT::v4f32) {
878 LocVT = MVT::v2f64;
879 LocInfo = CCValAssign::BCvt;
880 }
881
882 if (LocVT == MVT::f64 ||
883 LocVT == MVT::v2f64) {
884 if (RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
885 return false;
886 }
887
888 if (LocVT == MVT::i32) {
889 static const MCPhysReg RegList1[] = {
890 ARM::R0, ARM::R1, ARM::R2, ARM::R3
891 };
892 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
893 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
894 return false;
895 }
896 }
897
898 if (LocVT == MVT::i64) {
899 static const MCPhysReg RegList2[] = {
900 ARM::R0, ARM::R2
901 };
902 static const MCPhysReg RegList3[] = {
903 ARM::R1, ARM::R3
904 };
905 if (unsigned Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
906 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
907 return false;
908 }
909 }
910
911 return true; // CC didn't match.
912}
913
914
915bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
916 MVT LocVT, CCValAssign::LocInfo LocInfo,
917 ISD::ArgFlagsTy ArgFlags, CCState &State) {
918
919 if (LocVT == MVT::v1i64 ||
920 LocVT == MVT::v2i32 ||
921 LocVT == MVT::v4i16 ||
922 LocVT == MVT::v4f16 ||
923 LocVT == MVT::v4bf16 ||
924 LocVT == MVT::v8i8 ||
925 LocVT == MVT::v2f32) {
926 LocVT = MVT::f64;
927 LocInfo = CCValAssign::BCvt;
928 }
929
930 if (LocVT == MVT::v2i64 ||
931 LocVT == MVT::v4i32 ||
932 LocVT == MVT::v8i16 ||
933 LocVT == MVT::v8f16 ||
934 LocVT == MVT::v8bf16 ||
935 LocVT == MVT::v16i8 ||
936 LocVT == MVT::v4f32) {
937 LocVT = MVT::v2f64;
938 LocInfo = CCValAssign::BCvt;
939 }
940
941 if (LocVT == MVT::v2f64) {
942 static const MCPhysReg RegList1[] = {
943 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
944 };
945 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
946 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
947 return false;
948 }
949 }
950
951 if (LocVT == MVT::f64) {
952 static const MCPhysReg RegList2[] = {
953 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
954 };
955 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
956 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
957 return false;
958 }
959 }
960
961 if (LocVT == MVT::f32) {
962 static const MCPhysReg RegList3[] = {
963 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
964 };
965 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
966 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
967 return false;
968 }
969 }
970
971 if (!RetCC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
972 return false;
973
974 return true; // CC didn't match.
975}
976
977#else
978
979const MCRegister CC_ARM_AAPCS_ArgRegs[] = { ARM::R12 };
980const MCRegister CC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
981const MCRegister CC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
982const MCRegister CC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
983const MCRegister CC_ARM_APCS_GHC_ArgRegs[] = { ARM::D10, ARM::D11, ARM::D8, ARM::D9, ARM::Q4, ARM::Q5, ARM::R10, ARM::R11, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23 };
984const MCRegister CC_ARM_Win32_CFGuard_Check_ArgRegs[] = { ARM::R0 };
985const MCRegister FastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
986const MCRegister RetCC_ARM_AAPCS_ArgRegs[] = { 0 };
987const MCRegister RetCC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
988const MCRegister RetCC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
989const MCRegister RetCC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
990const MCRegister RetFastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
991
992// Registers used by Swift.
993const MCRegister CC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
994const MCRegister CC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
995const MCRegister CC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
996const MCRegister RetCC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
997const MCRegister RetCC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
998const MCRegister RetCC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
999
1000#endif // CC_REGISTER_LIST
1001