1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(0),
782 UINT64_C(0),
783 UINT64_C(0),
784 UINT64_C(0),
785 UINT64_C(0),
786 UINT64_C(0),
787 UINT64_C(0),
788 UINT64_C(0),
789 UINT64_C(0),
790 UINT64_C(44040192), // ADCri
791 UINT64_C(10485760), // ADCrr
792 UINT64_C(10485760), // ADCrsi
793 UINT64_C(10485776), // ADCrsr
794 UINT64_C(41943040), // ADDri
795 UINT64_C(8388608), // ADDrr
796 UINT64_C(8388608), // ADDrsi
797 UINT64_C(8388624), // ADDrsr
798 UINT64_C(34537472), // ADR
799 UINT64_C(4088398656), // AESD
800 UINT64_C(4088398592), // AESE
801 UINT64_C(4088398784), // AESIMC
802 UINT64_C(4088398720), // AESMC
803 UINT64_C(33554432), // ANDri
804 UINT64_C(0), // ANDrr
805 UINT64_C(0), // ANDrsi
806 UINT64_C(16), // ANDrsr
807 UINT64_C(4261416192), // BF16VDOTI_VDOTD
808 UINT64_C(4261416256), // BF16VDOTI_VDOTQ
809 UINT64_C(4227861760), // BF16VDOTS_VDOTD
810 UINT64_C(4227861824), // BF16VDOTS_VDOTQ
811 UINT64_C(4088792640), // BF16_VCVT
812 UINT64_C(246614336), // BF16_VCVTB
813 UINT64_C(246614464), // BF16_VCVTT
814 UINT64_C(130023455), // BFC
815 UINT64_C(130023440), // BFI
816 UINT64_C(62914560), // BICri
817 UINT64_C(29360128), // BICrr
818 UINT64_C(29360128), // BICrsi
819 UINT64_C(29360144), // BICrsr
820 UINT64_C(3776970864), // BKPT
821 UINT64_C(3942645760), // BL
822 UINT64_C(3778019120), // BLX
823 UINT64_C(19922736), // BLX_pred
824 UINT64_C(4194304000), // BLXi
825 UINT64_C(184549376), // BL_pred
826 UINT64_C(3778019088), // BX
827 UINT64_C(19922720), // BXJ
828 UINT64_C(19922718), // BX_RET
829 UINT64_C(19922704), // BX_pred
830 UINT64_C(167772160), // Bcc
831 UINT64_C(3992977408), // CDE_CX1
832 UINT64_C(4261412864), // CDE_CX1A
833 UINT64_C(3992977472), // CDE_CX1D
834 UINT64_C(4261412928), // CDE_CX1DA
835 UINT64_C(3997171712), // CDE_CX2
836 UINT64_C(4265607168), // CDE_CX2A
837 UINT64_C(3997171776), // CDE_CX2D
838 UINT64_C(4265607232), // CDE_CX2DA
839 UINT64_C(4001366016), // CDE_CX3
840 UINT64_C(4269801472), // CDE_CX3A
841 UINT64_C(4001366080), // CDE_CX3D
842 UINT64_C(4269801536), // CDE_CX3DA
843 UINT64_C(4246732800), // CDE_VCX1A_fpdp
844 UINT64_C(4229955584), // CDE_VCX1A_fpsp
845 UINT64_C(4229955648), // CDE_VCX1A_vec
846 UINT64_C(3978297344), // CDE_VCX1_fpdp
847 UINT64_C(3961520128), // CDE_VCX1_fpsp
848 UINT64_C(3961520192), // CDE_VCX1_vec
849 UINT64_C(4247781376), // CDE_VCX2A_fpdp
850 UINT64_C(4231004160), // CDE_VCX2A_fpsp
851 UINT64_C(4231004224), // CDE_VCX2A_vec
852 UINT64_C(3979345920), // CDE_VCX2_fpdp
853 UINT64_C(3962568704), // CDE_VCX2_fpsp
854 UINT64_C(3962568768), // CDE_VCX2_vec
855 UINT64_C(4253024256), // CDE_VCX3A_fpdp
856 UINT64_C(4236247040), // CDE_VCX3A_fpsp
857 UINT64_C(4236247104), // CDE_VCX3A_vec
858 UINT64_C(3984588800), // CDE_VCX3_fpdp
859 UINT64_C(3967811584), // CDE_VCX3_fpsp
860 UINT64_C(3967811648), // CDE_VCX3_vec
861 UINT64_C(234881024), // CDP
862 UINT64_C(4261412864), // CDP2
863 UINT64_C(4118802463), // CLREX
864 UINT64_C(24055568), // CLZ
865 UINT64_C(57671680), // CMNri
866 UINT64_C(24117248), // CMNzrr
867 UINT64_C(24117248), // CMNzrsi
868 UINT64_C(24117264), // CMNzrsr
869 UINT64_C(55574528), // CMPri
870 UINT64_C(22020096), // CMPrr
871 UINT64_C(22020096), // CMPrsi
872 UINT64_C(22020112), // CMPrsr
873 UINT64_C(4043440128), // CPS1p
874 UINT64_C(4043309056), // CPS2p
875 UINT64_C(4043440128), // CPS3p
876 UINT64_C(3774873664), // CRC32B
877 UINT64_C(3774874176), // CRC32CB
878 UINT64_C(3776971328), // CRC32CH
879 UINT64_C(3779068480), // CRC32CW
880 UINT64_C(3776970816), // CRC32H
881 UINT64_C(3779067968), // CRC32W
882 UINT64_C(52490480), // DBG
883 UINT64_C(4118802512), // DMB
884 UINT64_C(4118802496), // DSB
885 UINT64_C(35651584), // EORri
886 UINT64_C(2097152), // EORrr
887 UINT64_C(2097152), // EORrsi
888 UINT64_C(2097168), // EORrsr
889 UINT64_C(23068782), // ERET
890 UINT64_C(246418176), // FCONSTD
891 UINT64_C(246417664), // FCONSTH
892 UINT64_C(246417920), // FCONSTS
893 UINT64_C(221252353), // FLDMXDB_UPD
894 UINT64_C(210766593), // FLDMXIA
895 UINT64_C(212863745), // FLDMXIA_UPD
896 UINT64_C(250739216), // FMSTAT
897 UINT64_C(220203777), // FSTMXDB_UPD
898 UINT64_C(209718017), // FSTMXIA
899 UINT64_C(211815169), // FSTMXIA_UPD
900 UINT64_C(52490240), // HINT
901 UINT64_C(3774873712), // HLT
902 UINT64_C(3779068016), // HVC
903 UINT64_C(4118802528), // ISB
904 UINT64_C(26217631), // LDA
905 UINT64_C(30411935), // LDAB
906 UINT64_C(26218143), // LDAEX
907 UINT64_C(30412447), // LDAEXB
908 UINT64_C(28315295), // LDAEXD
909 UINT64_C(32509599), // LDAEXH
910 UINT64_C(32509087), // LDAH
911 UINT64_C(4249878528), // LDC2L_OFFSET
912 UINT64_C(4241489920), // LDC2L_OPTION
913 UINT64_C(4235198464), // LDC2L_POST
914 UINT64_C(4251975680), // LDC2L_PRE
915 UINT64_C(4245684224), // LDC2_OFFSET
916 UINT64_C(4237295616), // LDC2_OPTION
917 UINT64_C(4231004160), // LDC2_POST
918 UINT64_C(4247781376), // LDC2_PRE
919 UINT64_C(223346688), // LDCL_OFFSET
920 UINT64_C(214958080), // LDCL_OPTION
921 UINT64_C(208666624), // LDCL_POST
922 UINT64_C(225443840), // LDCL_PRE
923 UINT64_C(219152384), // LDC_OFFSET
924 UINT64_C(210763776), // LDC_OPTION
925 UINT64_C(204472320), // LDC_POST
926 UINT64_C(221249536), // LDC_PRE
927 UINT64_C(135266304), // LDMDA
928 UINT64_C(137363456), // LDMDA_UPD
929 UINT64_C(152043520), // LDMDB
930 UINT64_C(154140672), // LDMDB_UPD
931 UINT64_C(143654912), // LDMIA
932 UINT64_C(145752064), // LDMIA_UPD
933 UINT64_C(160432128), // LDMIB
934 UINT64_C(162529280), // LDMIB_UPD
935 UINT64_C(74448896), // LDRBT_POST_IMM
936 UINT64_C(108003328), // LDRBT_POST_REG
937 UINT64_C(72351744), // LDRB_POST_IMM
938 UINT64_C(105906176), // LDRB_POST_REG
939 UINT64_C(91226112), // LDRB_PRE_IMM
940 UINT64_C(124780544), // LDRB_PRE_REG
941 UINT64_C(89128960), // LDRBi12
942 UINT64_C(122683392), // LDRBrs
943 UINT64_C(16777424), // LDRD
944 UINT64_C(208), // LDRD_POST
945 UINT64_C(18874576), // LDRD_PRE
946 UINT64_C(26218399), // LDREX
947 UINT64_C(30412703), // LDREXB
948 UINT64_C(28315551), // LDREXD
949 UINT64_C(32509855), // LDREXH
950 UINT64_C(17825968), // LDRH
951 UINT64_C(7340208), // LDRHTi
952 UINT64_C(3145904), // LDRHTr
953 UINT64_C(1048752), // LDRH_POST
954 UINT64_C(19923120), // LDRH_PRE
955 UINT64_C(17826000), // LDRSB
956 UINT64_C(7340240), // LDRSBTi
957 UINT64_C(3145936), // LDRSBTr
958 UINT64_C(1048784), // LDRSB_POST
959 UINT64_C(19923152), // LDRSB_PRE
960 UINT64_C(17826032), // LDRSH
961 UINT64_C(7340272), // LDRSHTi
962 UINT64_C(3145968), // LDRSHTr
963 UINT64_C(1048816), // LDRSH_POST
964 UINT64_C(19923184), // LDRSH_PRE
965 UINT64_C(70254592), // LDRT_POST_IMM
966 UINT64_C(103809024), // LDRT_POST_REG
967 UINT64_C(68157440), // LDR_POST_IMM
968 UINT64_C(101711872), // LDR_POST_REG
969 UINT64_C(87031808), // LDR_PRE_IMM
970 UINT64_C(120586240), // LDR_PRE_REG
971 UINT64_C(85917696), // LDRcp
972 UINT64_C(84934656), // LDRi12
973 UINT64_C(118489088), // LDRrs
974 UINT64_C(234881040), // MCR
975 UINT64_C(4261412880), // MCR2
976 UINT64_C(205520896), // MCRR
977 UINT64_C(4232052736), // MCRR2
978 UINT64_C(2097296), // MLA
979 UINT64_C(6291600), // MLS
980 UINT64_C(27324430), // MOVPCLR
981 UINT64_C(54525952), // MOVTi16
982 UINT64_C(60817408), // MOVi
983 UINT64_C(50331648), // MOVi16
984 UINT64_C(27262976), // MOVr
985 UINT64_C(27262976), // MOVr_TC
986 UINT64_C(27262976), // MOVsi
987 UINT64_C(27262992), // MOVsr
988 UINT64_C(235929616), // MRC
989 UINT64_C(4262461456), // MRC2
990 UINT64_C(206569472), // MRRC
991 UINT64_C(4233101312), // MRRC2
992 UINT64_C(17760256), // MRS
993 UINT64_C(16777728), // MRSbanked
994 UINT64_C(21954560), // MRSsys
995 UINT64_C(18935808), // MSR
996 UINT64_C(18936320), // MSRbanked
997 UINT64_C(52490240), // MSRi
998 UINT64_C(144), // MUL
999 UINT64_C(3931111727), // MVE_ASRLi
1000 UINT64_C(3931111725), // MVE_ASRLr
1001 UINT64_C(4027637761), // MVE_DLSTP_16
1002 UINT64_C(4028686337), // MVE_DLSTP_32
1003 UINT64_C(4029734913), // MVE_DLSTP_64
1004 UINT64_C(4026589185), // MVE_DLSTP_8
1005 UINT64_C(4027572225), // MVE_LCTP
1006 UINT64_C(4028612609), // MVE_LETP
1007 UINT64_C(3931111695), // MVE_LSLLi
1008 UINT64_C(3931111693), // MVE_LSLLr
1009 UINT64_C(3931111711), // MVE_LSRL
1010 UINT64_C(3931115309), // MVE_SQRSHR
1011 UINT64_C(3931177261), // MVE_SQRSHRL
1012 UINT64_C(3931115327), // MVE_SQSHL
1013 UINT64_C(3931177279), // MVE_SQSHLL
1014 UINT64_C(3931115311), // MVE_SRSHR
1015 UINT64_C(3931177263), // MVE_SRSHRL
1016 UINT64_C(3931115277), // MVE_UQRSHL
1017 UINT64_C(3931177229), // MVE_UQRSHLL
1018 UINT64_C(3931115279), // MVE_UQSHL
1019 UINT64_C(3931177231), // MVE_UQSHLL
1020 UINT64_C(3931115295), // MVE_URSHR
1021 UINT64_C(3931177247), // MVE_URSHRL
1022 UINT64_C(4002418433), // MVE_VABAVs16
1023 UINT64_C(4003467009), // MVE_VABAVs32
1024 UINT64_C(4001369857), // MVE_VABAVs8
1025 UINT64_C(4270853889), // MVE_VABAVu16
1026 UINT64_C(4271902465), // MVE_VABAVu32
1027 UINT64_C(4269805313), // MVE_VABAVu8
1028 UINT64_C(4281339200), // MVE_VABDf16
1029 UINT64_C(4280290624), // MVE_VABDf32
1030 UINT64_C(4010805056), // MVE_VABDs16
1031 UINT64_C(4011853632), // MVE_VABDs32
1032 UINT64_C(4009756480), // MVE_VABDs8
1033 UINT64_C(4279240512), // MVE_VABDu16
1034 UINT64_C(4280289088), // MVE_VABDu32
1035 UINT64_C(4278191936), // MVE_VABDu8
1036 UINT64_C(4290053952), // MVE_VABSf16
1037 UINT64_C(4290316096), // MVE_VABSf32
1038 UINT64_C(4290052928), // MVE_VABSs16
1039 UINT64_C(4290315072), // MVE_VABSs32
1040 UINT64_C(4289790784), // MVE_VABSs8
1041 UINT64_C(3996126976), // MVE_VADC
1042 UINT64_C(3996131072), // MVE_VADCI
1043 UINT64_C(4001959712), // MVE_VADDLVs32acc
1044 UINT64_C(4001959680), // MVE_VADDLVs32no_acc
1045 UINT64_C(4270395168), // MVE_VADDLVu32acc
1046 UINT64_C(4270395136), // MVE_VADDLVu32no_acc
1047 UINT64_C(4009037600), // MVE_VADDVs16acc
1048 UINT64_C(4009037568), // MVE_VADDVs16no_acc
1049 UINT64_C(4009299744), // MVE_VADDVs32acc
1050 UINT64_C(4009299712), // MVE_VADDVs32no_acc
1051 UINT64_C(4008775456), // MVE_VADDVs8acc
1052 UINT64_C(4008775424), // MVE_VADDVs8no_acc
1053 UINT64_C(4277473056), // MVE_VADDVu16acc
1054 UINT64_C(4277473024), // MVE_VADDVu16no_acc
1055 UINT64_C(4277735200), // MVE_VADDVu32acc
1056 UINT64_C(4277735168), // MVE_VADDVu32no_acc
1057 UINT64_C(4277210912), // MVE_VADDVu8acc
1058 UINT64_C(4277210880), // MVE_VADDVu8no_acc
1059 UINT64_C(4264562496), // MVE_VADD_qr_f16
1060 UINT64_C(3996127040), // MVE_VADD_qr_f32
1061 UINT64_C(3994095424), // MVE_VADD_qr_i16
1062 UINT64_C(3995144000), // MVE_VADD_qr_i32
1063 UINT64_C(3993046848), // MVE_VADD_qr_i8
1064 UINT64_C(4010806592), // MVE_VADDf16
1065 UINT64_C(4009758016), // MVE_VADDf32
1066 UINT64_C(4010805312), // MVE_VADDi16
1067 UINT64_C(4011853888), // MVE_VADDi32
1068 UINT64_C(4009756736), // MVE_VADDi8
1069 UINT64_C(4009754960), // MVE_VAND
1070 UINT64_C(4010803536), // MVE_VBIC
1071 UINT64_C(4018145648), // MVE_VBICimmi16
1072 UINT64_C(4018143600), // MVE_VBICimmi32
1073 UINT64_C(4262534752), // MVE_VBRSR16
1074 UINT64_C(4263583328), // MVE_VBRSR32
1075 UINT64_C(4261486176), // MVE_VBRSR8
1076 UINT64_C(4236249152), // MVE_VCADDf16
1077 UINT64_C(4237297728), // MVE_VCADDf32
1078 UINT64_C(4262465280), // MVE_VCADDi16
1079 UINT64_C(4263513856), // MVE_VCADDi32
1080 UINT64_C(4261416704), // MVE_VCADDi8
1081 UINT64_C(4289987648), // MVE_VCLSs16
1082 UINT64_C(4290249792), // MVE_VCLSs32
1083 UINT64_C(4289725504), // MVE_VCLSs8
1084 UINT64_C(4289987776), // MVE_VCLZs16
1085 UINT64_C(4290249920), // MVE_VCLZs32
1086 UINT64_C(4289725632), // MVE_VCLZs8
1087 UINT64_C(4229957696), // MVE_VCMLAf16
1088 UINT64_C(4231006272), // MVE_VCMLAf32
1089 UINT64_C(4264627968), // MVE_VCMPf16
1090 UINT64_C(4264628032), // MVE_VCMPf16r
1091 UINT64_C(3996192512), // MVE_VCMPf32
1092 UINT64_C(3996192576), // MVE_VCMPf32r
1093 UINT64_C(4262530816), // MVE_VCMPi16
1094 UINT64_C(4262530880), // MVE_VCMPi16r
1095 UINT64_C(4263579392), // MVE_VCMPi32
1096 UINT64_C(4263579456), // MVE_VCMPi32r
1097 UINT64_C(4261482240), // MVE_VCMPi8
1098 UINT64_C(4261482304), // MVE_VCMPi8r
1099 UINT64_C(4262534912), // MVE_VCMPs16
1100 UINT64_C(4262534976), // MVE_VCMPs16r
1101 UINT64_C(4263583488), // MVE_VCMPs32
1102 UINT64_C(4263583552), // MVE_VCMPs32r
1103 UINT64_C(4261486336), // MVE_VCMPs8
1104 UINT64_C(4261486400), // MVE_VCMPs8r
1105 UINT64_C(4262530817), // MVE_VCMPu16
1106 UINT64_C(4262530912), // MVE_VCMPu16r
1107 UINT64_C(4263579393), // MVE_VCMPu32
1108 UINT64_C(4263579488), // MVE_VCMPu32r
1109 UINT64_C(4261482241), // MVE_VCMPu8
1110 UINT64_C(4261482336), // MVE_VCMPu8r
1111 UINT64_C(3996126720), // MVE_VCMULf16
1112 UINT64_C(4264562176), // MVE_VCMULf32
1113 UINT64_C(4027639809), // MVE_VCTP16
1114 UINT64_C(4028688385), // MVE_VCTP32
1115 UINT64_C(4029736961), // MVE_VCTP64
1116 UINT64_C(4026591233), // MVE_VCTP8
1117 UINT64_C(3997109761), // MVE_VCVTf16f32bh
1118 UINT64_C(3997113857), // MVE_VCVTf16f32th
1119 UINT64_C(4021292112), // MVE_VCVTf16s16_fix
1120 UINT64_C(4290184768), // MVE_VCVTf16s16n
1121 UINT64_C(4289727568), // MVE_VCVTf16u16_fix
1122 UINT64_C(4290184896), // MVE_VCVTf16u16n
1123 UINT64_C(4265545217), // MVE_VCVTf32f16bh
1124 UINT64_C(4265549313), // MVE_VCVTf32f16th
1125 UINT64_C(4020244048), // MVE_VCVTf32s32_fix
1126 UINT64_C(4290446912), // MVE_VCVTf32s32n
1127 UINT64_C(4288679504), // MVE_VCVTf32u32_fix
1128 UINT64_C(4290447040), // MVE_VCVTf32u32n
1129 UINT64_C(4021292368), // MVE_VCVTs16f16_fix
1130 UINT64_C(4290183232), // MVE_VCVTs16f16a
1131 UINT64_C(4290184000), // MVE_VCVTs16f16m
1132 UINT64_C(4290183488), // MVE_VCVTs16f16n
1133 UINT64_C(4290183744), // MVE_VCVTs16f16p
1134 UINT64_C(4290185024), // MVE_VCVTs16f16z
1135 UINT64_C(4020244304), // MVE_VCVTs32f32_fix
1136 UINT64_C(4290445376), // MVE_VCVTs32f32a
1137 UINT64_C(4290446144), // MVE_VCVTs32f32m
1138 UINT64_C(4290445632), // MVE_VCVTs32f32n
1139 UINT64_C(4290445888), // MVE_VCVTs32f32p
1140 UINT64_C(4290447168), // MVE_VCVTs32f32z
1141 UINT64_C(4289727824), // MVE_VCVTu16f16_fix
1142 UINT64_C(4290183360), // MVE_VCVTu16f16a
1143 UINT64_C(4290184128), // MVE_VCVTu16f16m
1144 UINT64_C(4290183616), // MVE_VCVTu16f16n
1145 UINT64_C(4290183872), // MVE_VCVTu16f16p
1146 UINT64_C(4290185152), // MVE_VCVTu16f16z
1147 UINT64_C(4288679760), // MVE_VCVTu32f32_fix
1148 UINT64_C(4290445504), // MVE_VCVTu32f32a
1149 UINT64_C(4290446272), // MVE_VCVTu32f32m
1150 UINT64_C(4290445760), // MVE_VCVTu32f32n
1151 UINT64_C(4290446016), // MVE_VCVTu32f32p
1152 UINT64_C(4290447296), // MVE_VCVTu32f32z
1153 UINT64_C(3994099566), // MVE_VDDUPu16
1154 UINT64_C(3995148142), // MVE_VDDUPu32
1155 UINT64_C(3993050990), // MVE_VDDUPu8
1156 UINT64_C(4003466032), // MVE_VDUP16
1157 UINT64_C(4003466000), // MVE_VDUP32
1158 UINT64_C(4007660304), // MVE_VDUP8
1159 UINT64_C(3994099552), // MVE_VDWDUPu16
1160 UINT64_C(3995148128), // MVE_VDWDUPu32
1161 UINT64_C(3993050976), // MVE_VDWDUPu8
1162 UINT64_C(4278190416), // MVE_VEOR
1163 UINT64_C(4264631872), // MVE_VFMA_qr_Sf16
1164 UINT64_C(3996196416), // MVE_VFMA_qr_Sf32
1165 UINT64_C(4264627776), // MVE_VFMA_qr_f16
1166 UINT64_C(3996192320), // MVE_VFMA_qr_f32
1167 UINT64_C(4010806352), // MVE_VFMAf16
1168 UINT64_C(4009757776), // MVE_VFMAf32
1169 UINT64_C(4012903504), // MVE_VFMSf16
1170 UINT64_C(4011854928), // MVE_VFMSf32
1171 UINT64_C(3994029888), // MVE_VHADD_qr_s16
1172 UINT64_C(3995078464), // MVE_VHADD_qr_s32
1173 UINT64_C(3992981312), // MVE_VHADD_qr_s8
1174 UINT64_C(4262465344), // MVE_VHADD_qr_u16
1175 UINT64_C(4263513920), // MVE_VHADD_qr_u32
1176 UINT64_C(4261416768), // MVE_VHADD_qr_u8
1177 UINT64_C(4010803264), // MVE_VHADDs16
1178 UINT64_C(4011851840), // MVE_VHADDs32
1179 UINT64_C(4009754688), // MVE_VHADDs8
1180 UINT64_C(4279238720), // MVE_VHADDu16
1181 UINT64_C(4280287296), // MVE_VHADDu32
1182 UINT64_C(4278190144), // MVE_VHADDu8
1183 UINT64_C(3994029824), // MVE_VHCADDs16
1184 UINT64_C(3995078400), // MVE_VHCADDs32
1185 UINT64_C(3992981248), // MVE_VHCADDs8
1186 UINT64_C(3994033984), // MVE_VHSUB_qr_s16
1187 UINT64_C(3995082560), // MVE_VHSUB_qr_s32
1188 UINT64_C(3992985408), // MVE_VHSUB_qr_s8
1189 UINT64_C(4262469440), // MVE_VHSUB_qr_u16
1190 UINT64_C(4263518016), // MVE_VHSUB_qr_u32
1191 UINT64_C(4261420864), // MVE_VHSUB_qr_u8
1192 UINT64_C(4010803776), // MVE_VHSUBs16
1193 UINT64_C(4011852352), // MVE_VHSUBs32
1194 UINT64_C(4009755200), // MVE_VHSUBs8
1195 UINT64_C(4279239232), // MVE_VHSUBu16
1196 UINT64_C(4280287808), // MVE_VHSUBu32
1197 UINT64_C(4278190656), // MVE_VHSUBu8
1198 UINT64_C(3994095470), // MVE_VIDUPu16
1199 UINT64_C(3995144046), // MVE_VIDUPu32
1200 UINT64_C(3993046894), // MVE_VIDUPu8
1201 UINT64_C(3994095456), // MVE_VIWDUPu16
1202 UINT64_C(3995144032), // MVE_VIWDUPu32
1203 UINT64_C(3993046880), // MVE_VIWDUPu8
1204 UINT64_C(4237303424), // MVE_VLD20_16
1205 UINT64_C(4239400576), // MVE_VLD20_16_wb
1206 UINT64_C(4237303552), // MVE_VLD20_32
1207 UINT64_C(4239400704), // MVE_VLD20_32_wb
1208 UINT64_C(4237303296), // MVE_VLD20_8
1209 UINT64_C(4239400448), // MVE_VLD20_8_wb
1210 UINT64_C(4237303456), // MVE_VLD21_16
1211 UINT64_C(4239400608), // MVE_VLD21_16_wb
1212 UINT64_C(4237303584), // MVE_VLD21_32
1213 UINT64_C(4239400736), // MVE_VLD21_32_wb
1214 UINT64_C(4237303328), // MVE_VLD21_8
1215 UINT64_C(4239400480), // MVE_VLD21_8_wb
1216 UINT64_C(4237303425), // MVE_VLD40_16
1217 UINT64_C(4239400577), // MVE_VLD40_16_wb
1218 UINT64_C(4237303553), // MVE_VLD40_32
1219 UINT64_C(4239400705), // MVE_VLD40_32_wb
1220 UINT64_C(4237303297), // MVE_VLD40_8
1221 UINT64_C(4239400449), // MVE_VLD40_8_wb
1222 UINT64_C(4237303457), // MVE_VLD41_16
1223 UINT64_C(4239400609), // MVE_VLD41_16_wb
1224 UINT64_C(4237303585), // MVE_VLD41_32
1225 UINT64_C(4239400737), // MVE_VLD41_32_wb
1226 UINT64_C(4237303329), // MVE_VLD41_8
1227 UINT64_C(4239400481), // MVE_VLD41_8_wb
1228 UINT64_C(4237303489), // MVE_VLD42_16
1229 UINT64_C(4239400641), // MVE_VLD42_16_wb
1230 UINT64_C(4237303617), // MVE_VLD42_32
1231 UINT64_C(4239400769), // MVE_VLD42_32_wb
1232 UINT64_C(4237303361), // MVE_VLD42_8
1233 UINT64_C(4239400513), // MVE_VLD42_8_wb
1234 UINT64_C(4237303521), // MVE_VLD43_16
1235 UINT64_C(4239400673), // MVE_VLD43_16_wb
1236 UINT64_C(4237303649), // MVE_VLD43_32
1237 UINT64_C(4239400801), // MVE_VLD43_32_wb
1238 UINT64_C(4237303393), // MVE_VLD43_8
1239 UINT64_C(4239400545), // MVE_VLD43_8_wb
1240 UINT64_C(3977252480), // MVE_VLDRBS16
1241 UINT64_C(3962572416), // MVE_VLDRBS16_post
1242 UINT64_C(3979349632), // MVE_VLDRBS16_pre
1243 UINT64_C(3968863872), // MVE_VLDRBS16_rq
1244 UINT64_C(3977252608), // MVE_VLDRBS32
1245 UINT64_C(3962572544), // MVE_VLDRBS32_post
1246 UINT64_C(3979349760), // MVE_VLDRBS32_pre
1247 UINT64_C(3968864000), // MVE_VLDRBS32_rq
1248 UINT64_C(4245687936), // MVE_VLDRBU16
1249 UINT64_C(4231007872), // MVE_VLDRBU16_post
1250 UINT64_C(4247785088), // MVE_VLDRBU16_pre
1251 UINT64_C(4237299328), // MVE_VLDRBU16_rq
1252 UINT64_C(4245688064), // MVE_VLDRBU32
1253 UINT64_C(4231008000), // MVE_VLDRBU32_post
1254 UINT64_C(4247785216), // MVE_VLDRBU32_pre
1255 UINT64_C(4237299456), // MVE_VLDRBU32_rq
1256 UINT64_C(3977256448), // MVE_VLDRBU8
1257 UINT64_C(3962576384), // MVE_VLDRBU8_post
1258 UINT64_C(3979353600), // MVE_VLDRBU8_pre
1259 UINT64_C(4237299200), // MVE_VLDRBU8_rq
1260 UINT64_C(4245692160), // MVE_VLDRDU64_qi
1261 UINT64_C(4247789312), // MVE_VLDRDU64_qi_pre
1262 UINT64_C(4237299665), // MVE_VLDRDU64_rq
1263 UINT64_C(4237299664), // MVE_VLDRDU64_rq_u
1264 UINT64_C(3977776896), // MVE_VLDRHS32
1265 UINT64_C(3963096832), // MVE_VLDRHS32_post
1266 UINT64_C(3979874048), // MVE_VLDRHS32_pre
1267 UINT64_C(3968864017), // MVE_VLDRHS32_rq
1268 UINT64_C(3968864016), // MVE_VLDRHS32_rq_u
1269 UINT64_C(3977256576), // MVE_VLDRHU16
1270 UINT64_C(3962576512), // MVE_VLDRHU16_post
1271 UINT64_C(3979353728), // MVE_VLDRHU16_pre
1272 UINT64_C(4237299345), // MVE_VLDRHU16_rq
1273 UINT64_C(4237299344), // MVE_VLDRHU16_rq_u
1274 UINT64_C(4246212352), // MVE_VLDRHU32
1275 UINT64_C(4231532288), // MVE_VLDRHU32_post
1276 UINT64_C(4248309504), // MVE_VLDRHU32_pre
1277 UINT64_C(4237299473), // MVE_VLDRHU32_rq
1278 UINT64_C(4237299472), // MVE_VLDRHU32_rq_u
1279 UINT64_C(3977256704), // MVE_VLDRWU32
1280 UINT64_C(3962576640), // MVE_VLDRWU32_post
1281 UINT64_C(3979353856), // MVE_VLDRWU32_pre
1282 UINT64_C(4245691904), // MVE_VLDRWU32_qi
1283 UINT64_C(4247789056), // MVE_VLDRWU32_qi_pre
1284 UINT64_C(4237299521), // MVE_VLDRWU32_rq
1285 UINT64_C(4237299520), // MVE_VLDRWU32_rq_u
1286 UINT64_C(4007923456), // MVE_VMAXAVs16
1287 UINT64_C(4008185600), // MVE_VMAXAVs32
1288 UINT64_C(4007661312), // MVE_VMAXAVs8
1289 UINT64_C(3996585601), // MVE_VMAXAs16
1290 UINT64_C(3996847745), // MVE_VMAXAs32
1291 UINT64_C(3996323457), // MVE_VMAXAs8
1292 UINT64_C(4276883200), // MVE_VMAXNMAVf16
1293 UINT64_C(4008447744), // MVE_VMAXNMAVf32
1294 UINT64_C(4265545345), // MVE_VMAXNMAf16
1295 UINT64_C(3997109889), // MVE_VMAXNMAf32
1296 UINT64_C(4277014272), // MVE_VMAXNMVf16
1297 UINT64_C(4008578816), // MVE_VMAXNMVf32
1298 UINT64_C(4279242576), // MVE_VMAXNMf16
1299 UINT64_C(4278194000), // MVE_VMAXNMf32
1300 UINT64_C(4008054528), // MVE_VMAXVs16
1301 UINT64_C(4008316672), // MVE_VMAXVs32
1302 UINT64_C(4007792384), // MVE_VMAXVs8
1303 UINT64_C(4276489984), // MVE_VMAXVu16
1304 UINT64_C(4276752128), // MVE_VMAXVu32
1305 UINT64_C(4276227840), // MVE_VMAXVu8
1306 UINT64_C(4010804800), // MVE_VMAXs16
1307 UINT64_C(4011853376), // MVE_VMAXs32
1308 UINT64_C(4009756224), // MVE_VMAXs8
1309 UINT64_C(4279240256), // MVE_VMAXu16
1310 UINT64_C(4280288832), // MVE_VMAXu32
1311 UINT64_C(4278191680), // MVE_VMAXu8
1312 UINT64_C(4007923584), // MVE_VMINAVs16
1313 UINT64_C(4008185728), // MVE_VMINAVs32
1314 UINT64_C(4007661440), // MVE_VMINAVs8
1315 UINT64_C(3996589697), // MVE_VMINAs16
1316 UINT64_C(3996851841), // MVE_VMINAs32
1317 UINT64_C(3996327553), // MVE_VMINAs8
1318 UINT64_C(4276883328), // MVE_VMINNMAVf16
1319 UINT64_C(4008447872), // MVE_VMINNMAVf32
1320 UINT64_C(4265549441), // MVE_VMINNMAf16
1321 UINT64_C(3997113985), // MVE_VMINNMAf32
1322 UINT64_C(4277014400), // MVE_VMINNMVf16
1323 UINT64_C(4008578944), // MVE_VMINNMVf32
1324 UINT64_C(4281339728), // MVE_VMINNMf16
1325 UINT64_C(4280291152), // MVE_VMINNMf32
1326 UINT64_C(4008054656), // MVE_VMINVs16
1327 UINT64_C(4008316800), // MVE_VMINVs32
1328 UINT64_C(4007792512), // MVE_VMINVs8
1329 UINT64_C(4276490112), // MVE_VMINVu16
1330 UINT64_C(4276752256), // MVE_VMINVu32
1331 UINT64_C(4276227968), // MVE_VMINVu8
1332 UINT64_C(4010804816), // MVE_VMINs16
1333 UINT64_C(4011853392), // MVE_VMINs32
1334 UINT64_C(4009756240), // MVE_VMINs8
1335 UINT64_C(4279240272), // MVE_VMINu16
1336 UINT64_C(4280288848), // MVE_VMINu32
1337 UINT64_C(4278191696), // MVE_VMINu8
1338 UINT64_C(4008709664), // MVE_VMLADAVas16
1339 UINT64_C(4008775200), // MVE_VMLADAVas32
1340 UINT64_C(4008709920), // MVE_VMLADAVas8
1341 UINT64_C(4277145120), // MVE_VMLADAVau16
1342 UINT64_C(4277210656), // MVE_VMLADAVau32
1343 UINT64_C(4277145376), // MVE_VMLADAVau8
1344 UINT64_C(4008713760), // MVE_VMLADAVaxs16
1345 UINT64_C(4008779296), // MVE_VMLADAVaxs32
1346 UINT64_C(4008714016), // MVE_VMLADAVaxs8
1347 UINT64_C(4008709632), // MVE_VMLADAVs16
1348 UINT64_C(4008775168), // MVE_VMLADAVs32
1349 UINT64_C(4008709888), // MVE_VMLADAVs8
1350 UINT64_C(4277145088), // MVE_VMLADAVu16
1351 UINT64_C(4277210624), // MVE_VMLADAVu32
1352 UINT64_C(4277145344), // MVE_VMLADAVu8
1353 UINT64_C(4008713728), // MVE_VMLADAVxs16
1354 UINT64_C(4008779264), // MVE_VMLADAVxs32
1355 UINT64_C(4008713984), // MVE_VMLADAVxs8
1356 UINT64_C(4001369632), // MVE_VMLALDAVas16
1357 UINT64_C(4001435168), // MVE_VMLALDAVas32
1358 UINT64_C(4269805088), // MVE_VMLALDAVau16
1359 UINT64_C(4269870624), // MVE_VMLALDAVau32
1360 UINT64_C(4001373728), // MVE_VMLALDAVaxs16
1361 UINT64_C(4001439264), // MVE_VMLALDAVaxs32
1362 UINT64_C(4001369600), // MVE_VMLALDAVs16
1363 UINT64_C(4001435136), // MVE_VMLALDAVs32
1364 UINT64_C(4269805056), // MVE_VMLALDAVu16
1365 UINT64_C(4269870592), // MVE_VMLALDAVu32
1366 UINT64_C(4001373696), // MVE_VMLALDAVxs16
1367 UINT64_C(4001439232), // MVE_VMLALDAVxs32
1368 UINT64_C(3994099264), // MVE_VMLAS_qr_i16
1369 UINT64_C(3995147840), // MVE_VMLAS_qr_i32
1370 UINT64_C(3993050688), // MVE_VMLAS_qr_i8
1371 UINT64_C(3994095168), // MVE_VMLA_qr_i16
1372 UINT64_C(3995143744), // MVE_VMLA_qr_i32
1373 UINT64_C(3993046592), // MVE_VMLA_qr_i8
1374 UINT64_C(4008709665), // MVE_VMLSDAVas16
1375 UINT64_C(4008775201), // MVE_VMLSDAVas32
1376 UINT64_C(4277145121), // MVE_VMLSDAVas8
1377 UINT64_C(4008713761), // MVE_VMLSDAVaxs16
1378 UINT64_C(4008779297), // MVE_VMLSDAVaxs32
1379 UINT64_C(4277149217), // MVE_VMLSDAVaxs8
1380 UINT64_C(4008709633), // MVE_VMLSDAVs16
1381 UINT64_C(4008775169), // MVE_VMLSDAVs32
1382 UINT64_C(4277145089), // MVE_VMLSDAVs8
1383 UINT64_C(4008713729), // MVE_VMLSDAVxs16
1384 UINT64_C(4008779265), // MVE_VMLSDAVxs32
1385 UINT64_C(4277149185), // MVE_VMLSDAVxs8
1386 UINT64_C(4001369633), // MVE_VMLSLDAVas16
1387 UINT64_C(4001435169), // MVE_VMLSLDAVas32
1388 UINT64_C(4001373729), // MVE_VMLSLDAVaxs16
1389 UINT64_C(4001439265), // MVE_VMLSLDAVaxs32
1390 UINT64_C(4001369601), // MVE_VMLSLDAVs16
1391 UINT64_C(4001435137), // MVE_VMLSLDAVs32
1392 UINT64_C(4001373697), // MVE_VMLSLDAVxs16
1393 UINT64_C(4001439233), // MVE_VMLSLDAVxs32
1394 UINT64_C(4004515648), // MVE_VMOVLs16bh
1395 UINT64_C(4004519744), // MVE_VMOVLs16th
1396 UINT64_C(4003991360), // MVE_VMOVLs8bh
1397 UINT64_C(4003995456), // MVE_VMOVLs8th
1398 UINT64_C(4272951104), // MVE_VMOVLu16bh
1399 UINT64_C(4272955200), // MVE_VMOVLu16th
1400 UINT64_C(4272426816), // MVE_VMOVLu8bh
1401 UINT64_C(4272430912), // MVE_VMOVLu8th
1402 UINT64_C(4264627841), // MVE_VMOVNi16bh
1403 UINT64_C(4264631937), // MVE_VMOVNi16th
1404 UINT64_C(4264889985), // MVE_VMOVNi32bh
1405 UINT64_C(4264894081), // MVE_VMOVNi32th
1406 UINT64_C(3994028816), // MVE_VMOV_from_lane_32
1407 UINT64_C(3994028848), // MVE_VMOV_from_lane_s16
1408 UINT64_C(3998223120), // MVE_VMOV_from_lane_s8
1409 UINT64_C(4002417456), // MVE_VMOV_from_lane_u16
1410 UINT64_C(4006611728), // MVE_VMOV_from_lane_u8
1411 UINT64_C(3960475392), // MVE_VMOV_q_rr
1412 UINT64_C(3959426816), // MVE_VMOV_rr_q
1413 UINT64_C(3992980272), // MVE_VMOV_to_lane_16
1414 UINT64_C(3992980240), // MVE_VMOV_to_lane_32
1415 UINT64_C(3997174544), // MVE_VMOV_to_lane_8
1416 UINT64_C(4018147152), // MVE_VMOVimmf32
1417 UINT64_C(4018145360), // MVE_VMOVimmi16
1418 UINT64_C(4018143312), // MVE_VMOVimmi32
1419 UINT64_C(4018146928), // MVE_VMOVimmi64
1420 UINT64_C(4018146896), // MVE_VMOVimmi8
1421 UINT64_C(3994095105), // MVE_VMULHs16
1422 UINT64_C(3995143681), // MVE_VMULHs32
1423 UINT64_C(3993046529), // MVE_VMULHs8
1424 UINT64_C(4262530561), // MVE_VMULHu16
1425 UINT64_C(4263579137), // MVE_VMULHu32
1426 UINT64_C(4261481985), // MVE_VMULHu8
1427 UINT64_C(4264627712), // MVE_VMULLBp16
1428 UINT64_C(3996192256), // MVE_VMULLBp8
1429 UINT64_C(3994095104), // MVE_VMULLBs16
1430 UINT64_C(3995143680), // MVE_VMULLBs32
1431 UINT64_C(3993046528), // MVE_VMULLBs8
1432 UINT64_C(4262530560), // MVE_VMULLBu16
1433 UINT64_C(4263579136), // MVE_VMULLBu32
1434 UINT64_C(4261481984), // MVE_VMULLBu8
1435 UINT64_C(4264631808), // MVE_VMULLTp16
1436 UINT64_C(3996196352), // MVE_VMULLTp8
1437 UINT64_C(3994099200), // MVE_VMULLTs16
1438 UINT64_C(3995147776), // MVE_VMULLTs32
1439 UINT64_C(3993050624), // MVE_VMULLTs8
1440 UINT64_C(4262534656), // MVE_VMULLTu16
1441 UINT64_C(4263583232), // MVE_VMULLTu32
1442 UINT64_C(4261486080), // MVE_VMULLTu8
1443 UINT64_C(4264627808), // MVE_VMUL_qr_f16
1444 UINT64_C(3996192352), // MVE_VMUL_qr_f32
1445 UINT64_C(3994099296), // MVE_VMUL_qr_i16
1446 UINT64_C(3995147872), // MVE_VMUL_qr_i32
1447 UINT64_C(3993050720), // MVE_VMUL_qr_i8
1448 UINT64_C(4279242064), // MVE_VMULf16
1449 UINT64_C(4278193488), // MVE_VMULf32
1450 UINT64_C(4010805584), // MVE_VMULi16
1451 UINT64_C(4011854160), // MVE_VMULi32
1452 UINT64_C(4009757008), // MVE_VMULi8
1453 UINT64_C(4289725888), // MVE_VMVN
1454 UINT64_C(4018145392), // MVE_VMVNimmi16
1455 UINT64_C(4018143344), // MVE_VMVNimmi32
1456 UINT64_C(4290054080), // MVE_VNEGf16
1457 UINT64_C(4290316224), // MVE_VNEGf32
1458 UINT64_C(4290053056), // MVE_VNEGs16
1459 UINT64_C(4290315200), // MVE_VNEGs32
1460 UINT64_C(4289790912), // MVE_VNEGs8
1461 UINT64_C(4012900688), // MVE_VORN
1462 UINT64_C(4011852112), // MVE_VORR
1463 UINT64_C(4018145616), // MVE_VORRimmi16
1464 UINT64_C(4018143568), // MVE_VORRimmi32
1465 UINT64_C(4264628045), // MVE_VPNOT
1466 UINT64_C(4264627969), // MVE_VPSEL
1467 UINT64_C(4264628045), // MVE_VPST
1468 UINT64_C(4261482240), // MVE_VPTv16i8
1469 UINT64_C(4261482304), // MVE_VPTv16i8r
1470 UINT64_C(4261486336), // MVE_VPTv16s8
1471 UINT64_C(4261486400), // MVE_VPTv16s8r
1472 UINT64_C(4261482241), // MVE_VPTv16u8
1473 UINT64_C(4261482336), // MVE_VPTv16u8r
1474 UINT64_C(3996192512), // MVE_VPTv4f32
1475 UINT64_C(3996192576), // MVE_VPTv4f32r
1476 UINT64_C(4263579392), // MVE_VPTv4i32
1477 UINT64_C(4263579456), // MVE_VPTv4i32r
1478 UINT64_C(4263583488), // MVE_VPTv4s32
1479 UINT64_C(4263583552), // MVE_VPTv4s32r
1480 UINT64_C(4263579393), // MVE_VPTv4u32
1481 UINT64_C(4263579488), // MVE_VPTv4u32r
1482 UINT64_C(4264627968), // MVE_VPTv8f16
1483 UINT64_C(4264628032), // MVE_VPTv8f16r
1484 UINT64_C(4262530816), // MVE_VPTv8i16
1485 UINT64_C(4262530880), // MVE_VPTv8i16r
1486 UINT64_C(4262534912), // MVE_VPTv8s16
1487 UINT64_C(4262534976), // MVE_VPTv8s16r
1488 UINT64_C(4262530817), // MVE_VPTv8u16
1489 UINT64_C(4262530912), // MVE_VPTv8u16r
1490 UINT64_C(4289988416), // MVE_VQABSs16
1491 UINT64_C(4290250560), // MVE_VQABSs32
1492 UINT64_C(4289726272), // MVE_VQABSs8
1493 UINT64_C(3994029920), // MVE_VQADD_qr_s16
1494 UINT64_C(3995078496), // MVE_VQADD_qr_s32
1495 UINT64_C(3992981344), // MVE_VQADD_qr_s8
1496 UINT64_C(4262465376), // MVE_VQADD_qr_u16
1497 UINT64_C(4263513952), // MVE_VQADD_qr_u32
1498 UINT64_C(4261416800), // MVE_VQADD_qr_u8
1499 UINT64_C(4010803280), // MVE_VQADDs16
1500 UINT64_C(4011851856), // MVE_VQADDs32
1501 UINT64_C(4009754704), // MVE_VQADDs8
1502 UINT64_C(4279238736), // MVE_VQADDu16
1503 UINT64_C(4280287312), // MVE_VQADDu32
1504 UINT64_C(4278190160), // MVE_VQADDu8
1505 UINT64_C(3994033664), // MVE_VQDMLADHXs16
1506 UINT64_C(3995082240), // MVE_VQDMLADHXs32
1507 UINT64_C(3992985088), // MVE_VQDMLADHXs8
1508 UINT64_C(3994029568), // MVE_VQDMLADHs16
1509 UINT64_C(3995078144), // MVE_VQDMLADHs32
1510 UINT64_C(3992980992), // MVE_VQDMLADHs8
1511 UINT64_C(3994029664), // MVE_VQDMLAH_qrs16
1512 UINT64_C(3995078240), // MVE_VQDMLAH_qrs32
1513 UINT64_C(3992981088), // MVE_VQDMLAH_qrs8
1514 UINT64_C(3994033760), // MVE_VQDMLASH_qrs16
1515 UINT64_C(3995082336), // MVE_VQDMLASH_qrs32
1516 UINT64_C(3992985184), // MVE_VQDMLASH_qrs8
1517 UINT64_C(4262469120), // MVE_VQDMLSDHXs16
1518 UINT64_C(4263517696), // MVE_VQDMLSDHXs32
1519 UINT64_C(4261420544), // MVE_VQDMLSDHXs8
1520 UINT64_C(4262465024), // MVE_VQDMLSDHs16
1521 UINT64_C(4263513600), // MVE_VQDMLSDHs32
1522 UINT64_C(4261416448), // MVE_VQDMLSDHs8
1523 UINT64_C(3994095200), // MVE_VQDMULH_qr_s16
1524 UINT64_C(3995143776), // MVE_VQDMULH_qr_s32
1525 UINT64_C(3993046624), // MVE_VQDMULH_qr_s8
1526 UINT64_C(4010806080), // MVE_VQDMULHi16
1527 UINT64_C(4011854656), // MVE_VQDMULHi32
1528 UINT64_C(4009757504), // MVE_VQDMULHi8
1529 UINT64_C(3996127072), // MVE_VQDMULL_qr_s16bh
1530 UINT64_C(3996131168), // MVE_VQDMULL_qr_s16th
1531 UINT64_C(4264562528), // MVE_VQDMULL_qr_s32bh
1532 UINT64_C(4264566624), // MVE_VQDMULL_qr_s32th
1533 UINT64_C(3996126977), // MVE_VQDMULLs16bh
1534 UINT64_C(3996131073), // MVE_VQDMULLs16th
1535 UINT64_C(4264562433), // MVE_VQDMULLs32bh
1536 UINT64_C(4264566529), // MVE_VQDMULLs32th
1537 UINT64_C(3996323329), // MVE_VQMOVNs16bh
1538 UINT64_C(3996327425), // MVE_VQMOVNs16th
1539 UINT64_C(3996585473), // MVE_VQMOVNs32bh
1540 UINT64_C(3996589569), // MVE_VQMOVNs32th
1541 UINT64_C(4264758785), // MVE_VQMOVNu16bh
1542 UINT64_C(4264762881), // MVE_VQMOVNu16th
1543 UINT64_C(4265020929), // MVE_VQMOVNu32bh
1544 UINT64_C(4265025025), // MVE_VQMOVNu32th
1545 UINT64_C(3996192385), // MVE_VQMOVUNs16bh
1546 UINT64_C(3996196481), // MVE_VQMOVUNs16th
1547 UINT64_C(3996454529), // MVE_VQMOVUNs32bh
1548 UINT64_C(3996458625), // MVE_VQMOVUNs32th
1549 UINT64_C(4289988544), // MVE_VQNEGs16
1550 UINT64_C(4290250688), // MVE_VQNEGs32
1551 UINT64_C(4289726400), // MVE_VQNEGs8
1552 UINT64_C(3994033665), // MVE_VQRDMLADHXs16
1553 UINT64_C(3995082241), // MVE_VQRDMLADHXs32
1554 UINT64_C(3992985089), // MVE_VQRDMLADHXs8
1555 UINT64_C(3994029569), // MVE_VQRDMLADHs16
1556 UINT64_C(3995078145), // MVE_VQRDMLADHs32
1557 UINT64_C(3992980993), // MVE_VQRDMLADHs8
1558 UINT64_C(3994029632), // MVE_VQRDMLAH_qrs16
1559 UINT64_C(3995078208), // MVE_VQRDMLAH_qrs32
1560 UINT64_C(3992981056), // MVE_VQRDMLAH_qrs8
1561 UINT64_C(3994033728), // MVE_VQRDMLASH_qrs16
1562 UINT64_C(3995082304), // MVE_VQRDMLASH_qrs32
1563 UINT64_C(3992985152), // MVE_VQRDMLASH_qrs8
1564 UINT64_C(4262469121), // MVE_VQRDMLSDHXs16
1565 UINT64_C(4263517697), // MVE_VQRDMLSDHXs32
1566 UINT64_C(4261420545), // MVE_VQRDMLSDHXs8
1567 UINT64_C(4262465025), // MVE_VQRDMLSDHs16
1568 UINT64_C(4263513601), // MVE_VQRDMLSDHs32
1569 UINT64_C(4261416449), // MVE_VQRDMLSDHs8
1570 UINT64_C(4262530656), // MVE_VQRDMULH_qr_s16
1571 UINT64_C(4263579232), // MVE_VQRDMULH_qr_s32
1572 UINT64_C(4261482080), // MVE_VQRDMULH_qr_s8
1573 UINT64_C(4279241536), // MVE_VQRDMULHi16
1574 UINT64_C(4280290112), // MVE_VQRDMULHi32
1575 UINT64_C(4278192960), // MVE_VQRDMULHi8
1576 UINT64_C(4010804560), // MVE_VQRSHL_by_vecs16
1577 UINT64_C(4011853136), // MVE_VQRSHL_by_vecs32
1578 UINT64_C(4009755984), // MVE_VQRSHL_by_vecs8
1579 UINT64_C(4279240016), // MVE_VQRSHL_by_vecu16
1580 UINT64_C(4280288592), // MVE_VQRSHL_by_vecu32
1581 UINT64_C(4278191440), // MVE_VQRSHL_by_vecu8
1582 UINT64_C(3996589792), // MVE_VQRSHL_qrs16
1583 UINT64_C(3996851936), // MVE_VQRSHL_qrs32
1584 UINT64_C(3996327648), // MVE_VQRSHL_qrs8
1585 UINT64_C(4265025248), // MVE_VQRSHL_qru16
1586 UINT64_C(4265287392), // MVE_VQRSHL_qru32
1587 UINT64_C(4264763104), // MVE_VQRSHL_qru8
1588 UINT64_C(4001894209), // MVE_VQRSHRNbhs16
1589 UINT64_C(4002418497), // MVE_VQRSHRNbhs32
1590 UINT64_C(4270329665), // MVE_VQRSHRNbhu16
1591 UINT64_C(4270853953), // MVE_VQRSHRNbhu32
1592 UINT64_C(4001898305), // MVE_VQRSHRNths16
1593 UINT64_C(4002422593), // MVE_VQRSHRNths32
1594 UINT64_C(4270333761), // MVE_VQRSHRNthu16
1595 UINT64_C(4270858049), // MVE_VQRSHRNthu32
1596 UINT64_C(4270329792), // MVE_VQRSHRUNs16bh
1597 UINT64_C(4270333888), // MVE_VQRSHRUNs16th
1598 UINT64_C(4270854080), // MVE_VQRSHRUNs32bh
1599 UINT64_C(4270858176), // MVE_VQRSHRUNs32th
1600 UINT64_C(4287628880), // MVE_VQSHLU_imms16
1601 UINT64_C(4288677456), // MVE_VQSHLU_imms32
1602 UINT64_C(4287104592), // MVE_VQSHLU_imms8
1603 UINT64_C(4010804304), // MVE_VQSHL_by_vecs16
1604 UINT64_C(4011852880), // MVE_VQSHL_by_vecs32
1605 UINT64_C(4009755728), // MVE_VQSHL_by_vecs8
1606 UINT64_C(4279239760), // MVE_VQSHL_by_vecu16
1607 UINT64_C(4280288336), // MVE_VQSHL_by_vecu32
1608 UINT64_C(4278191184), // MVE_VQSHL_by_vecu8
1609 UINT64_C(3996458720), // MVE_VQSHL_qrs16
1610 UINT64_C(3996720864), // MVE_VQSHL_qrs32
1611 UINT64_C(3996196576), // MVE_VQSHL_qrs8
1612 UINT64_C(4264894176), // MVE_VQSHL_qru16
1613 UINT64_C(4265156320), // MVE_VQSHL_qru32
1614 UINT64_C(4264632032), // MVE_VQSHL_qru8
1615 UINT64_C(4019193680), // MVE_VQSHLimms16
1616 UINT64_C(4020242256), // MVE_VQSHLimms32
1617 UINT64_C(4018669392), // MVE_VQSHLimms8
1618 UINT64_C(4287629136), // MVE_VQSHLimmu16
1619 UINT64_C(4288677712), // MVE_VQSHLimmu32
1620 UINT64_C(4287104848), // MVE_VQSHLimmu8
1621 UINT64_C(4001894208), // MVE_VQSHRNbhs16
1622 UINT64_C(4002418496), // MVE_VQSHRNbhs32
1623 UINT64_C(4270329664), // MVE_VQSHRNbhu16
1624 UINT64_C(4270853952), // MVE_VQSHRNbhu32
1625 UINT64_C(4001898304), // MVE_VQSHRNths16
1626 UINT64_C(4002422592), // MVE_VQSHRNths32
1627 UINT64_C(4270333760), // MVE_VQSHRNthu16
1628 UINT64_C(4270858048), // MVE_VQSHRNthu32
1629 UINT64_C(4001894336), // MVE_VQSHRUNs16bh
1630 UINT64_C(4001898432), // MVE_VQSHRUNs16th
1631 UINT64_C(4002418624), // MVE_VQSHRUNs32bh
1632 UINT64_C(4002422720), // MVE_VQSHRUNs32th
1633 UINT64_C(3994034016), // MVE_VQSUB_qr_s16
1634 UINT64_C(3995082592), // MVE_VQSUB_qr_s32
1635 UINT64_C(3992985440), // MVE_VQSUB_qr_s8
1636 UINT64_C(4262469472), // MVE_VQSUB_qr_u16
1637 UINT64_C(4263518048), // MVE_VQSUB_qr_u32
1638 UINT64_C(4261420896), // MVE_VQSUB_qr_u8
1639 UINT64_C(4010803792), // MVE_VQSUBs16
1640 UINT64_C(4011852368), // MVE_VQSUBs32
1641 UINT64_C(4009755216), // MVE_VQSUBs8
1642 UINT64_C(4279239248), // MVE_VQSUBu16
1643 UINT64_C(4280287824), // MVE_VQSUBu32
1644 UINT64_C(4278190672), // MVE_VQSUBu8
1645 UINT64_C(4289724736), // MVE_VREV16_8
1646 UINT64_C(4289986752), // MVE_VREV32_16
1647 UINT64_C(4289724608), // MVE_VREV32_8
1648 UINT64_C(4289986624), // MVE_VREV64_16
1649 UINT64_C(4290248768), // MVE_VREV64_32
1650 UINT64_C(4289724480), // MVE_VREV64_8
1651 UINT64_C(4010803520), // MVE_VRHADDs16
1652 UINT64_C(4011852096), // MVE_VRHADDs32
1653 UINT64_C(4009754944), // MVE_VRHADDs8
1654 UINT64_C(4279238976), // MVE_VRHADDu16
1655 UINT64_C(4280287552), // MVE_VRHADDu32
1656 UINT64_C(4278190400), // MVE_VRHADDu8
1657 UINT64_C(4290118976), // MVE_VRINTf16A
1658 UINT64_C(4290119360), // MVE_VRINTf16M
1659 UINT64_C(4290118720), // MVE_VRINTf16N
1660 UINT64_C(4290119616), // MVE_VRINTf16P
1661 UINT64_C(4290118848), // MVE_VRINTf16X
1662 UINT64_C(4290119104), // MVE_VRINTf16Z
1663 UINT64_C(4290381120), // MVE_VRINTf32A
1664 UINT64_C(4290381504), // MVE_VRINTf32M
1665 UINT64_C(4290380864), // MVE_VRINTf32N
1666 UINT64_C(4290381760), // MVE_VRINTf32P
1667 UINT64_C(4290380992), // MVE_VRINTf32X
1668 UINT64_C(4290381248), // MVE_VRINTf32Z
1669 UINT64_C(4001369888), // MVE_VRMLALDAVHas32
1670 UINT64_C(4269805344), // MVE_VRMLALDAVHau32
1671 UINT64_C(4001373984), // MVE_VRMLALDAVHaxs32
1672 UINT64_C(4001369856), // MVE_VRMLALDAVHs32
1673 UINT64_C(4269805312), // MVE_VRMLALDAVHu32
1674 UINT64_C(4001373952), // MVE_VRMLALDAVHxs32
1675 UINT64_C(4269805089), // MVE_VRMLSLDAVHas32
1676 UINT64_C(4269809185), // MVE_VRMLSLDAVHaxs32
1677 UINT64_C(4269805057), // MVE_VRMLSLDAVHs32
1678 UINT64_C(4269809153), // MVE_VRMLSLDAVHxs32
1679 UINT64_C(3994099201), // MVE_VRMULHs16
1680 UINT64_C(3995147777), // MVE_VRMULHs32
1681 UINT64_C(3993050625), // MVE_VRMULHs8
1682 UINT64_C(4262534657), // MVE_VRMULHu16
1683 UINT64_C(4263583233), // MVE_VRMULHu32
1684 UINT64_C(4261486081), // MVE_VRMULHu8
1685 UINT64_C(4010804544), // MVE_VRSHL_by_vecs16
1686 UINT64_C(4011853120), // MVE_VRSHL_by_vecs32
1687 UINT64_C(4009755968), // MVE_VRSHL_by_vecs8
1688 UINT64_C(4279240000), // MVE_VRSHL_by_vecu16
1689 UINT64_C(4280288576), // MVE_VRSHL_by_vecu32
1690 UINT64_C(4278191424), // MVE_VRSHL_by_vecu8
1691 UINT64_C(3996589664), // MVE_VRSHL_qrs16
1692 UINT64_C(3996851808), // MVE_VRSHL_qrs32
1693 UINT64_C(3996327520), // MVE_VRSHL_qrs8
1694 UINT64_C(4265025120), // MVE_VRSHL_qru16
1695 UINT64_C(4265287264), // MVE_VRSHL_qru32
1696 UINT64_C(4264762976), // MVE_VRSHL_qru8
1697 UINT64_C(4270329793), // MVE_VRSHRNi16bh
1698 UINT64_C(4270333889), // MVE_VRSHRNi16th
1699 UINT64_C(4270854081), // MVE_VRSHRNi32bh
1700 UINT64_C(4270858177), // MVE_VRSHRNi32th
1701 UINT64_C(4019192400), // MVE_VRSHR_imms16
1702 UINT64_C(4020240976), // MVE_VRSHR_imms32
1703 UINT64_C(4018668112), // MVE_VRSHR_imms8
1704 UINT64_C(4287627856), // MVE_VRSHR_immu16
1705 UINT64_C(4288676432), // MVE_VRSHR_immu32
1706 UINT64_C(4287103568), // MVE_VRSHR_immu8
1707 UINT64_C(4264562432), // MVE_VSBC
1708 UINT64_C(4264566528), // MVE_VSBCI
1709 UINT64_C(4003467200), // MVE_VSHLC
1710 UINT64_C(4004515648), // MVE_VSHLL_imms16bh
1711 UINT64_C(4004519744), // MVE_VSHLL_imms16th
1712 UINT64_C(4003991360), // MVE_VSHLL_imms8bh
1713 UINT64_C(4003995456), // MVE_VSHLL_imms8th
1714 UINT64_C(4272951104), // MVE_VSHLL_immu16bh
1715 UINT64_C(4272955200), // MVE_VSHLL_immu16th
1716 UINT64_C(4272426816), // MVE_VSHLL_immu8bh
1717 UINT64_C(4272430912), // MVE_VSHLL_immu8th
1718 UINT64_C(3996454401), // MVE_VSHLL_lws16bh
1719 UINT64_C(3996458497), // MVE_VSHLL_lws16th
1720 UINT64_C(3996192257), // MVE_VSHLL_lws8bh
1721 UINT64_C(3996196353), // MVE_VSHLL_lws8th
1722 UINT64_C(4264889857), // MVE_VSHLL_lwu16bh
1723 UINT64_C(4264893953), // MVE_VSHLL_lwu16th
1724 UINT64_C(4264627713), // MVE_VSHLL_lwu8bh
1725 UINT64_C(4264631809), // MVE_VSHLL_lwu8th
1726 UINT64_C(4010804288), // MVE_VSHL_by_vecs16
1727 UINT64_C(4011852864), // MVE_VSHL_by_vecs32
1728 UINT64_C(4009755712), // MVE_VSHL_by_vecs8
1729 UINT64_C(4279239744), // MVE_VSHL_by_vecu16
1730 UINT64_C(4280288320), // MVE_VSHL_by_vecu32
1731 UINT64_C(4278191168), // MVE_VSHL_by_vecu8
1732 UINT64_C(4019193168), // MVE_VSHL_immi16
1733 UINT64_C(4020241744), // MVE_VSHL_immi32
1734 UINT64_C(4018668880), // MVE_VSHL_immi8
1735 UINT64_C(3996458592), // MVE_VSHL_qrs16
1736 UINT64_C(3996720736), // MVE_VSHL_qrs32
1737 UINT64_C(3996196448), // MVE_VSHL_qrs8
1738 UINT64_C(4264894048), // MVE_VSHL_qru16
1739 UINT64_C(4265156192), // MVE_VSHL_qru32
1740 UINT64_C(4264631904), // MVE_VSHL_qru8
1741 UINT64_C(4001894337), // MVE_VSHRNi16bh
1742 UINT64_C(4001898433), // MVE_VSHRNi16th
1743 UINT64_C(4002418625), // MVE_VSHRNi32bh
1744 UINT64_C(4002422721), // MVE_VSHRNi32th
1745 UINT64_C(4019191888), // MVE_VSHR_imms16
1746 UINT64_C(4020240464), // MVE_VSHR_imms32
1747 UINT64_C(4018667600), // MVE_VSHR_imms8
1748 UINT64_C(4287627344), // MVE_VSHR_immu16
1749 UINT64_C(4288675920), // MVE_VSHR_immu32
1750 UINT64_C(4287103056), // MVE_VSHR_immu8
1751 UINT64_C(4287628624), // MVE_VSLIimm16
1752 UINT64_C(4288677200), // MVE_VSLIimm32
1753 UINT64_C(4287104336), // MVE_VSLIimm8
1754 UINT64_C(4287628368), // MVE_VSRIimm16
1755 UINT64_C(4288676944), // MVE_VSRIimm32
1756 UINT64_C(4287104080), // MVE_VSRIimm8
1757 UINT64_C(4236254848), // MVE_VST20_16
1758 UINT64_C(4238352000), // MVE_VST20_16_wb
1759 UINT64_C(4236254976), // MVE_VST20_32
1760 UINT64_C(4238352128), // MVE_VST20_32_wb
1761 UINT64_C(4236254720), // MVE_VST20_8
1762 UINT64_C(4238351872), // MVE_VST20_8_wb
1763 UINT64_C(4236254880), // MVE_VST21_16
1764 UINT64_C(4238352032), // MVE_VST21_16_wb
1765 UINT64_C(4236255008), // MVE_VST21_32
1766 UINT64_C(4238352160), // MVE_VST21_32_wb
1767 UINT64_C(4236254752), // MVE_VST21_8
1768 UINT64_C(4238351904), // MVE_VST21_8_wb
1769 UINT64_C(4236254849), // MVE_VST40_16
1770 UINT64_C(4238352001), // MVE_VST40_16_wb
1771 UINT64_C(4236254977), // MVE_VST40_32
1772 UINT64_C(4238352129), // MVE_VST40_32_wb
1773 UINT64_C(4236254721), // MVE_VST40_8
1774 UINT64_C(4238351873), // MVE_VST40_8_wb
1775 UINT64_C(4236254881), // MVE_VST41_16
1776 UINT64_C(4238352033), // MVE_VST41_16_wb
1777 UINT64_C(4236255009), // MVE_VST41_32
1778 UINT64_C(4238352161), // MVE_VST41_32_wb
1779 UINT64_C(4236254753), // MVE_VST41_8
1780 UINT64_C(4238351905), // MVE_VST41_8_wb
1781 UINT64_C(4236254913), // MVE_VST42_16
1782 UINT64_C(4238352065), // MVE_VST42_16_wb
1783 UINT64_C(4236255041), // MVE_VST42_32
1784 UINT64_C(4238352193), // MVE_VST42_32_wb
1785 UINT64_C(4236254785), // MVE_VST42_8
1786 UINT64_C(4238351937), // MVE_VST42_8_wb
1787 UINT64_C(4236254945), // MVE_VST43_16
1788 UINT64_C(4238352097), // MVE_VST43_16_wb
1789 UINT64_C(4236255073), // MVE_VST43_32
1790 UINT64_C(4238352225), // MVE_VST43_32_wb
1791 UINT64_C(4236254817), // MVE_VST43_8
1792 UINT64_C(4238351969), // MVE_VST43_8_wb
1793 UINT64_C(3976203904), // MVE_VSTRB16
1794 UINT64_C(3961523840), // MVE_VSTRB16_post
1795 UINT64_C(3978301056), // MVE_VSTRB16_pre
1796 UINT64_C(3967815296), // MVE_VSTRB16_rq
1797 UINT64_C(3976204032), // MVE_VSTRB32
1798 UINT64_C(3961523968), // MVE_VSTRB32_post
1799 UINT64_C(3978301184), // MVE_VSTRB32_pre
1800 UINT64_C(3967815424), // MVE_VSTRB32_rq
1801 UINT64_C(3967815168), // MVE_VSTRB8_rq
1802 UINT64_C(3976207872), // MVE_VSTRBU8
1803 UINT64_C(3961527808), // MVE_VSTRBU8_post
1804 UINT64_C(3978305024), // MVE_VSTRBU8_pre
1805 UINT64_C(4244643584), // MVE_VSTRD64_qi
1806 UINT64_C(4246740736), // MVE_VSTRD64_qi_pre
1807 UINT64_C(3967815633), // MVE_VSTRD64_rq
1808 UINT64_C(3967815632), // MVE_VSTRD64_rq_u
1809 UINT64_C(3967815313), // MVE_VSTRH16_rq
1810 UINT64_C(3967815312), // MVE_VSTRH16_rq_u
1811 UINT64_C(3976728320), // MVE_VSTRH32
1812 UINT64_C(3962048256), // MVE_VSTRH32_post
1813 UINT64_C(3978825472), // MVE_VSTRH32_pre
1814 UINT64_C(3967815441), // MVE_VSTRH32_rq
1815 UINT64_C(3967815440), // MVE_VSTRH32_rq_u
1816 UINT64_C(3976208000), // MVE_VSTRHU16
1817 UINT64_C(3961527936), // MVE_VSTRHU16_post
1818 UINT64_C(3978305152), // MVE_VSTRHU16_pre
1819 UINT64_C(4244643328), // MVE_VSTRW32_qi
1820 UINT64_C(4246740480), // MVE_VSTRW32_qi_pre
1821 UINT64_C(3967815489), // MVE_VSTRW32_rq
1822 UINT64_C(3967815488), // MVE_VSTRW32_rq_u
1823 UINT64_C(3976208128), // MVE_VSTRWU32
1824 UINT64_C(3961528064), // MVE_VSTRWU32_post
1825 UINT64_C(3978305280), // MVE_VSTRWU32_pre
1826 UINT64_C(4264566592), // MVE_VSUB_qr_f16
1827 UINT64_C(3996131136), // MVE_VSUB_qr_f32
1828 UINT64_C(3994099520), // MVE_VSUB_qr_i16
1829 UINT64_C(3995148096), // MVE_VSUB_qr_i32
1830 UINT64_C(3993050944), // MVE_VSUB_qr_i8
1831 UINT64_C(4012903744), // MVE_VSUBf16
1832 UINT64_C(4011855168), // MVE_VSUBf32
1833 UINT64_C(4279240768), // MVE_VSUBi16
1834 UINT64_C(4280289344), // MVE_VSUBi32
1835 UINT64_C(4278192192), // MVE_VSUBi8
1836 UINT64_C(4027629569), // MVE_WLSTP_16
1837 UINT64_C(4028678145), // MVE_WLSTP_32
1838 UINT64_C(4029726721), // MVE_WLSTP_64
1839 UINT64_C(4026580993), // MVE_WLSTP_8
1840 UINT64_C(65011712), // MVNi
1841 UINT64_C(31457280), // MVNr
1842 UINT64_C(31457280), // MVNsi
1843 UINT64_C(31457296), // MVNsr
1844 UINT64_C(4076867344), // NEON_VMAXNMNDf
1845 UINT64_C(4077915920), // NEON_VMAXNMNDh
1846 UINT64_C(4076867408), // NEON_VMAXNMNQf
1847 UINT64_C(4077915984), // NEON_VMAXNMNQh
1848 UINT64_C(4078964496), // NEON_VMINNMNDf
1849 UINT64_C(4080013072), // NEON_VMINNMNDh
1850 UINT64_C(4078964560), // NEON_VMINNMNQf
1851 UINT64_C(4080013136), // NEON_VMINNMNQh
1852 UINT64_C(58720256), // ORRri
1853 UINT64_C(25165824), // ORRrr
1854 UINT64_C(25165824), // ORRrsi
1855 UINT64_C(25165840), // ORRrsr
1856 UINT64_C(109051920), // PKHBT
1857 UINT64_C(109051984), // PKHTB
1858 UINT64_C(4111527936), // PLDWi12
1859 UINT64_C(4145082368), // PLDWrs
1860 UINT64_C(4115722240), // PLDi12
1861 UINT64_C(4149276672), // PLDrs
1862 UINT64_C(4098945024), // PLIi12
1863 UINT64_C(4132499456), // PLIrs
1864 UINT64_C(16777296), // QADD
1865 UINT64_C(102764304), // QADD16
1866 UINT64_C(102764432), // QADD8
1867 UINT64_C(102764336), // QASX
1868 UINT64_C(20971600), // QDADD
1869 UINT64_C(23068752), // QDSUB
1870 UINT64_C(102764368), // QSAX
1871 UINT64_C(18874448), // QSUB
1872 UINT64_C(102764400), // QSUB16
1873 UINT64_C(102764528), // QSUB8
1874 UINT64_C(117378864), // RBIT
1875 UINT64_C(113184560), // REV
1876 UINT64_C(113184688), // REV16
1877 UINT64_C(117378992), // REVSH
1878 UINT64_C(4161800704), // RFEDA
1879 UINT64_C(4163897856), // RFEDA_UPD
1880 UINT64_C(4178577920), // RFEDB
1881 UINT64_C(4180675072), // RFEDB_UPD
1882 UINT64_C(4170189312), // RFEIA
1883 UINT64_C(4172286464), // RFEIA_UPD
1884 UINT64_C(4186966528), // RFEIB
1885 UINT64_C(4189063680), // RFEIB_UPD
1886 UINT64_C(39845888), // RSBri
1887 UINT64_C(6291456), // RSBrr
1888 UINT64_C(6291456), // RSBrsi
1889 UINT64_C(6291472), // RSBrsr
1890 UINT64_C(48234496), // RSCri
1891 UINT64_C(14680064), // RSCrr
1892 UINT64_C(14680064), // RSCrsi
1893 UINT64_C(14680080), // RSCrsr
1894 UINT64_C(101715728), // SADD16
1895 UINT64_C(101715856), // SADD8
1896 UINT64_C(101715760), // SASX
1897 UINT64_C(4118802544), // SB
1898 UINT64_C(46137344), // SBCri
1899 UINT64_C(12582912), // SBCrr
1900 UINT64_C(12582912), // SBCrsi
1901 UINT64_C(12582928), // SBCrsr
1902 UINT64_C(127926352), // SBFX
1903 UINT64_C(118550544), // SDIV
1904 UINT64_C(109055920), // SEL
1905 UINT64_C(4043374592), // SETEND
1906 UINT64_C(4044357632), // SETPAN
1907 UINT64_C(4060089408), // SHA1C
1908 UINT64_C(4088988352), // SHA1H
1909 UINT64_C(4062186560), // SHA1M
1910 UINT64_C(4061137984), // SHA1P
1911 UINT64_C(4063235136), // SHA1SU0
1912 UINT64_C(4089054080), // SHA1SU1
1913 UINT64_C(4076866624), // SHA256H
1914 UINT64_C(4077915200), // SHA256H2
1915 UINT64_C(4089054144), // SHA256SU0
1916 UINT64_C(4078963776), // SHA256SU1
1917 UINT64_C(103812880), // SHADD16
1918 UINT64_C(103813008), // SHADD8
1919 UINT64_C(103812912), // SHASX
1920 UINT64_C(103812944), // SHSAX
1921 UINT64_C(103812976), // SHSUB16
1922 UINT64_C(103813104), // SHSUB8
1923 UINT64_C(23068784), // SMC
1924 UINT64_C(16777344), // SMLABB
1925 UINT64_C(16777408), // SMLABT
1926 UINT64_C(117440528), // SMLAD
1927 UINT64_C(117440560), // SMLADX
1928 UINT64_C(14680208), // SMLAL
1929 UINT64_C(20971648), // SMLALBB
1930 UINT64_C(20971712), // SMLALBT
1931 UINT64_C(121634832), // SMLALD
1932 UINT64_C(121634864), // SMLALDX
1933 UINT64_C(20971680), // SMLALTB
1934 UINT64_C(20971744), // SMLALTT
1935 UINT64_C(16777376), // SMLATB
1936 UINT64_C(16777440), // SMLATT
1937 UINT64_C(18874496), // SMLAWB
1938 UINT64_C(18874560), // SMLAWT
1939 UINT64_C(117440592), // SMLSD
1940 UINT64_C(117440624), // SMLSDX
1941 UINT64_C(121634896), // SMLSLD
1942 UINT64_C(121634928), // SMLSLDX
1943 UINT64_C(122683408), // SMMLA
1944 UINT64_C(122683440), // SMMLAR
1945 UINT64_C(122683600), // SMMLS
1946 UINT64_C(122683632), // SMMLSR
1947 UINT64_C(122744848), // SMMUL
1948 UINT64_C(122744880), // SMMULR
1949 UINT64_C(117501968), // SMUAD
1950 UINT64_C(117502000), // SMUADX
1951 UINT64_C(23068800), // SMULBB
1952 UINT64_C(23068864), // SMULBT
1953 UINT64_C(12583056), // SMULL
1954 UINT64_C(23068832), // SMULTB
1955 UINT64_C(23068896), // SMULTT
1956 UINT64_C(18874528), // SMULWB
1957 UINT64_C(18874592), // SMULWT
1958 UINT64_C(117502032), // SMUSD
1959 UINT64_C(117502064), // SMUSDX
1960 UINT64_C(4165797120), // SRSDA
1961 UINT64_C(4167894272), // SRSDA_UPD
1962 UINT64_C(4182574336), // SRSDB
1963 UINT64_C(4184671488), // SRSDB_UPD
1964 UINT64_C(4174185728), // SRSIA
1965 UINT64_C(4176282880), // SRSIA_UPD
1966 UINT64_C(4190962944), // SRSIB
1967 UINT64_C(4193060096), // SRSIB_UPD
1968 UINT64_C(111149072), // SSAT
1969 UINT64_C(111152944), // SSAT16
1970 UINT64_C(101715792), // SSAX
1971 UINT64_C(101715824), // SSUB16
1972 UINT64_C(101715952), // SSUB8
1973 UINT64_C(4248829952), // STC2L_OFFSET
1974 UINT64_C(4240441344), // STC2L_OPTION
1975 UINT64_C(4234149888), // STC2L_POST
1976 UINT64_C(4250927104), // STC2L_PRE
1977 UINT64_C(4244635648), // STC2_OFFSET
1978 UINT64_C(4236247040), // STC2_OPTION
1979 UINT64_C(4229955584), // STC2_POST
1980 UINT64_C(4246732800), // STC2_PRE
1981 UINT64_C(222298112), // STCL_OFFSET
1982 UINT64_C(213909504), // STCL_OPTION
1983 UINT64_C(207618048), // STCL_POST
1984 UINT64_C(224395264), // STCL_PRE
1985 UINT64_C(218103808), // STC_OFFSET
1986 UINT64_C(209715200), // STC_OPTION
1987 UINT64_C(203423744), // STC_POST
1988 UINT64_C(220200960), // STC_PRE
1989 UINT64_C(25230480), // STL
1990 UINT64_C(29424784), // STLB
1991 UINT64_C(25169552), // STLEX
1992 UINT64_C(29363856), // STLEXB
1993 UINT64_C(27266704), // STLEXD
1994 UINT64_C(31461008), // STLEXH
1995 UINT64_C(31521936), // STLH
1996 UINT64_C(134217728), // STMDA
1997 UINT64_C(136314880), // STMDA_UPD
1998 UINT64_C(150994944), // STMDB
1999 UINT64_C(153092096), // STMDB_UPD
2000 UINT64_C(142606336), // STMIA
2001 UINT64_C(144703488), // STMIA_UPD
2002 UINT64_C(159383552), // STMIB
2003 UINT64_C(161480704), // STMIB_UPD
2004 UINT64_C(73400320), // STRBT_POST_IMM
2005 UINT64_C(106954752), // STRBT_POST_REG
2006 UINT64_C(71303168), // STRB_POST_IMM
2007 UINT64_C(104857600), // STRB_POST_REG
2008 UINT64_C(90177536), // STRB_PRE_IMM
2009 UINT64_C(123731968), // STRB_PRE_REG
2010 UINT64_C(88080384), // STRBi12
2011 UINT64_C(121634816), // STRBrs
2012 UINT64_C(16777456), // STRD
2013 UINT64_C(240), // STRD_POST
2014 UINT64_C(18874608), // STRD_PRE
2015 UINT64_C(25169808), // STREX
2016 UINT64_C(29364112), // STREXB
2017 UINT64_C(27266960), // STREXD
2018 UINT64_C(31461264), // STREXH
2019 UINT64_C(16777392), // STRH
2020 UINT64_C(6291632), // STRHTi
2021 UINT64_C(2097328), // STRHTr
2022 UINT64_C(176), // STRH_POST
2023 UINT64_C(18874544), // STRH_PRE
2024 UINT64_C(69206016), // STRT_POST_IMM
2025 UINT64_C(102760448), // STRT_POST_REG
2026 UINT64_C(67108864), // STR_POST_IMM
2027 UINT64_C(100663296), // STR_POST_REG
2028 UINT64_C(85983232), // STR_PRE_IMM
2029 UINT64_C(119537664), // STR_PRE_REG
2030 UINT64_C(83886080), // STRi12
2031 UINT64_C(117440512), // STRrs
2032 UINT64_C(37748736), // SUBri
2033 UINT64_C(4194304), // SUBrr
2034 UINT64_C(4194304), // SUBrsi
2035 UINT64_C(4194320), // SUBrsr
2036 UINT64_C(251658240), // SVC
2037 UINT64_C(16777360), // SWP
2038 UINT64_C(20971664), // SWPB
2039 UINT64_C(111149168), // SXTAB
2040 UINT64_C(109052016), // SXTAB16
2041 UINT64_C(112197744), // SXTAH
2042 UINT64_C(112132208), // SXTB
2043 UINT64_C(110035056), // SXTB16
2044 UINT64_C(113180784), // SXTH
2045 UINT64_C(53477376), // TEQri
2046 UINT64_C(19922944), // TEQrr
2047 UINT64_C(19922944), // TEQrsi
2048 UINT64_C(19922960), // TEQrsr
2049 UINT64_C(3892305662), // TRAP
2050 UINT64_C(3892240112), // TRAPNaCl
2051 UINT64_C(3810586642), // TSB
2052 UINT64_C(51380224), // TSTri
2053 UINT64_C(17825792), // TSTrr
2054 UINT64_C(17825792), // TSTrsi
2055 UINT64_C(17825808), // TSTrsr
2056 UINT64_C(105910032), // UADD16
2057 UINT64_C(105910160), // UADD8
2058 UINT64_C(105910064), // UASX
2059 UINT64_C(132120656), // UBFX
2060 UINT64_C(3891265776), // UDF
2061 UINT64_C(120647696), // UDIV
2062 UINT64_C(108007184), // UHADD16
2063 UINT64_C(108007312), // UHADD8
2064 UINT64_C(108007216), // UHASX
2065 UINT64_C(108007248), // UHSAX
2066 UINT64_C(108007280), // UHSUB16
2067 UINT64_C(108007408), // UHSUB8
2068 UINT64_C(4194448), // UMAAL
2069 UINT64_C(10485904), // UMLAL
2070 UINT64_C(8388752), // UMULL
2071 UINT64_C(106958608), // UQADD16
2072 UINT64_C(106958736), // UQADD8
2073 UINT64_C(106958640), // UQASX
2074 UINT64_C(106958672), // UQSAX
2075 UINT64_C(106958704), // UQSUB16
2076 UINT64_C(106958832), // UQSUB8
2077 UINT64_C(125890576), // USAD8
2078 UINT64_C(125829136), // USADA8
2079 UINT64_C(115343376), // USAT
2080 UINT64_C(115347248), // USAT16
2081 UINT64_C(105910096), // USAX
2082 UINT64_C(105910128), // USUB16
2083 UINT64_C(105910256), // USUB8
2084 UINT64_C(115343472), // UXTAB
2085 UINT64_C(113246320), // UXTAB16
2086 UINT64_C(116392048), // UXTAH
2087 UINT64_C(116326512), // UXTB
2088 UINT64_C(114229360), // UXTB16
2089 UINT64_C(117375088), // UXTH
2090 UINT64_C(4070573312), // VABALsv2i64
2091 UINT64_C(4069524736), // VABALsv4i32
2092 UINT64_C(4068476160), // VABALsv8i16
2093 UINT64_C(4087350528), // VABALuv2i64
2094 UINT64_C(4086301952), // VABALuv4i32
2095 UINT64_C(4085253376), // VABALuv8i16
2096 UINT64_C(4060088144), // VABAsv16i8
2097 UINT64_C(4062185232), // VABAsv2i32
2098 UINT64_C(4061136656), // VABAsv4i16
2099 UINT64_C(4062185296), // VABAsv4i32
2100 UINT64_C(4061136720), // VABAsv8i16
2101 UINT64_C(4060088080), // VABAsv8i8
2102 UINT64_C(4076865360), // VABAuv16i8
2103 UINT64_C(4078962448), // VABAuv2i32
2104 UINT64_C(4077913872), // VABAuv4i16
2105 UINT64_C(4078962512), // VABAuv4i32
2106 UINT64_C(4077913936), // VABAuv8i16
2107 UINT64_C(4076865296), // VABAuv8i8
2108 UINT64_C(4070573824), // VABDLsv2i64
2109 UINT64_C(4069525248), // VABDLsv4i32
2110 UINT64_C(4068476672), // VABDLsv8i16
2111 UINT64_C(4087351040), // VABDLuv2i64
2112 UINT64_C(4086302464), // VABDLuv4i32
2113 UINT64_C(4085253888), // VABDLuv8i16
2114 UINT64_C(4078963968), // VABDfd
2115 UINT64_C(4078964032), // VABDfq
2116 UINT64_C(4080012544), // VABDhd
2117 UINT64_C(4080012608), // VABDhq
2118 UINT64_C(4060088128), // VABDsv16i8
2119 UINT64_C(4062185216), // VABDsv2i32
2120 UINT64_C(4061136640), // VABDsv4i16
2121 UINT64_C(4062185280), // VABDsv4i32
2122 UINT64_C(4061136704), // VABDsv8i16
2123 UINT64_C(4060088064), // VABDsv8i8
2124 UINT64_C(4076865344), // VABDuv16i8
2125 UINT64_C(4078962432), // VABDuv2i32
2126 UINT64_C(4077913856), // VABDuv4i16
2127 UINT64_C(4078962496), // VABDuv4i32
2128 UINT64_C(4077913920), // VABDuv8i16
2129 UINT64_C(4076865280), // VABDuv8i8
2130 UINT64_C(246418368), // VABSD
2131 UINT64_C(246417856), // VABSH
2132 UINT64_C(246418112), // VABSS
2133 UINT64_C(4088989440), // VABSfd
2134 UINT64_C(4088989504), // VABSfq
2135 UINT64_C(4088727296), // VABShd
2136 UINT64_C(4088727360), // VABShq
2137 UINT64_C(4088464192), // VABSv16i8
2138 UINT64_C(4088988416), // VABSv2i32
2139 UINT64_C(4088726272), // VABSv4i16
2140 UINT64_C(4088988480), // VABSv4i32
2141 UINT64_C(4088726336), // VABSv8i16
2142 UINT64_C(4088464128), // VABSv8i8
2143 UINT64_C(4076867088), // VACGEfd
2144 UINT64_C(4076867152), // VACGEfq
2145 UINT64_C(4077915664), // VACGEhd
2146 UINT64_C(4077915728), // VACGEhq
2147 UINT64_C(4078964240), // VACGTfd
2148 UINT64_C(4078964304), // VACGTfq
2149 UINT64_C(4080012816), // VACGThd
2150 UINT64_C(4080012880), // VACGThq
2151 UINT64_C(238029568), // VADDD
2152 UINT64_C(238029056), // VADDH
2153 UINT64_C(4070573056), // VADDHNv2i32
2154 UINT64_C(4069524480), // VADDHNv4i16
2155 UINT64_C(4068475904), // VADDHNv8i8
2156 UINT64_C(4070572032), // VADDLsv2i64
2157 UINT64_C(4069523456), // VADDLsv4i32
2158 UINT64_C(4068474880), // VADDLsv8i16
2159 UINT64_C(4087349248), // VADDLuv2i64
2160 UINT64_C(4086300672), // VADDLuv4i32
2161 UINT64_C(4085252096), // VADDLuv8i16
2162 UINT64_C(238029312), // VADDS
2163 UINT64_C(4070572288), // VADDWsv2i64
2164 UINT64_C(4069523712), // VADDWsv4i32
2165 UINT64_C(4068475136), // VADDWsv8i16
2166 UINT64_C(4087349504), // VADDWuv2i64
2167 UINT64_C(4086300928), // VADDWuv4i32
2168 UINT64_C(4085252352), // VADDWuv8i16
2169 UINT64_C(4060089600), // VADDfd
2170 UINT64_C(4060089664), // VADDfq
2171 UINT64_C(4061138176), // VADDhd
2172 UINT64_C(4061138240), // VADDhq
2173 UINT64_C(4060088384), // VADDv16i8
2174 UINT64_C(4063234048), // VADDv1i64
2175 UINT64_C(4062185472), // VADDv2i32
2176 UINT64_C(4063234112), // VADDv2i64
2177 UINT64_C(4061136896), // VADDv4i16
2178 UINT64_C(4062185536), // VADDv4i32
2179 UINT64_C(4061136960), // VADDv8i16
2180 UINT64_C(4060088320), // VADDv8i8
2181 UINT64_C(4060086544), // VANDd
2182 UINT64_C(4060086608), // VANDq
2183 UINT64_C(4231006224), // VBF16MALBQ
2184 UINT64_C(4264560656), // VBF16MALBQI
2185 UINT64_C(4231006288), // VBF16MALTQ
2186 UINT64_C(4264560720), // VBF16MALTQI
2187 UINT64_C(4061135120), // VBICd
2188 UINT64_C(4068475184), // VBICiv2i32
2189 UINT64_C(4068477232), // VBICiv4i16
2190 UINT64_C(4068475248), // VBICiv4i32
2191 UINT64_C(4068477296), // VBICiv8i16
2192 UINT64_C(4061135184), // VBICq
2193 UINT64_C(4080009488), // VBIFd
2194 UINT64_C(4080009552), // VBIFq
2195 UINT64_C(4078960912), // VBITd
2196 UINT64_C(4078960976), // VBITq
2197 UINT64_C(4077912336), // VBSLd
2198 UINT64_C(4077912400), // VBSLq
2199 UINT64_C(0), // VBSPd
2200 UINT64_C(0), // VBSPq
2201 UINT64_C(4237297664), // VCADDv2f32
2202 UINT64_C(4236249088), // VCADDv4f16
2203 UINT64_C(4237297728), // VCADDv4f32
2204 UINT64_C(4236249152), // VCADDv8f16
2205 UINT64_C(4060089856), // VCEQfd
2206 UINT64_C(4060089920), // VCEQfq
2207 UINT64_C(4061138432), // VCEQhd
2208 UINT64_C(4061138496), // VCEQhq
2209 UINT64_C(4076865616), // VCEQv16i8
2210 UINT64_C(4078962704), // VCEQv2i32
2211 UINT64_C(4077914128), // VCEQv4i16
2212 UINT64_C(4078962768), // VCEQv4i32
2213 UINT64_C(4077914192), // VCEQv8i16
2214 UINT64_C(4076865552), // VCEQv8i8
2215 UINT64_C(4088463680), // VCEQzv16i8
2216 UINT64_C(4088988928), // VCEQzv2f32
2217 UINT64_C(4088987904), // VCEQzv2i32
2218 UINT64_C(4088726784), // VCEQzv4f16
2219 UINT64_C(4088988992), // VCEQzv4f32
2220 UINT64_C(4088725760), // VCEQzv4i16
2221 UINT64_C(4088987968), // VCEQzv4i32
2222 UINT64_C(4088726848), // VCEQzv8f16
2223 UINT64_C(4088725824), // VCEQzv8i16
2224 UINT64_C(4088463616), // VCEQzv8i8
2225 UINT64_C(4076867072), // VCGEfd
2226 UINT64_C(4076867136), // VCGEfq
2227 UINT64_C(4077915648), // VCGEhd
2228 UINT64_C(4077915712), // VCGEhq
2229 UINT64_C(4060087120), // VCGEsv16i8
2230 UINT64_C(4062184208), // VCGEsv2i32
2231 UINT64_C(4061135632), // VCGEsv4i16
2232 UINT64_C(4062184272), // VCGEsv4i32
2233 UINT64_C(4061135696), // VCGEsv8i16
2234 UINT64_C(4060087056), // VCGEsv8i8
2235 UINT64_C(4076864336), // VCGEuv16i8
2236 UINT64_C(4078961424), // VCGEuv2i32
2237 UINT64_C(4077912848), // VCGEuv4i16
2238 UINT64_C(4078961488), // VCGEuv4i32
2239 UINT64_C(4077912912), // VCGEuv8i16
2240 UINT64_C(4076864272), // VCGEuv8i8
2241 UINT64_C(4088463552), // VCGEzv16i8
2242 UINT64_C(4088988800), // VCGEzv2f32
2243 UINT64_C(4088987776), // VCGEzv2i32
2244 UINT64_C(4088726656), // VCGEzv4f16
2245 UINT64_C(4088988864), // VCGEzv4f32
2246 UINT64_C(4088725632), // VCGEzv4i16
2247 UINT64_C(4088987840), // VCGEzv4i32
2248 UINT64_C(4088726720), // VCGEzv8f16
2249 UINT64_C(4088725696), // VCGEzv8i16
2250 UINT64_C(4088463488), // VCGEzv8i8
2251 UINT64_C(4078964224), // VCGTfd
2252 UINT64_C(4078964288), // VCGTfq
2253 UINT64_C(4080012800), // VCGThd
2254 UINT64_C(4080012864), // VCGThq
2255 UINT64_C(4060087104), // VCGTsv16i8
2256 UINT64_C(4062184192), // VCGTsv2i32
2257 UINT64_C(4061135616), // VCGTsv4i16
2258 UINT64_C(4062184256), // VCGTsv4i32
2259 UINT64_C(4061135680), // VCGTsv8i16
2260 UINT64_C(4060087040), // VCGTsv8i8
2261 UINT64_C(4076864320), // VCGTuv16i8
2262 UINT64_C(4078961408), // VCGTuv2i32
2263 UINT64_C(4077912832), // VCGTuv4i16
2264 UINT64_C(4078961472), // VCGTuv4i32
2265 UINT64_C(4077912896), // VCGTuv8i16
2266 UINT64_C(4076864256), // VCGTuv8i8
2267 UINT64_C(4088463424), // VCGTzv16i8
2268 UINT64_C(4088988672), // VCGTzv2f32
2269 UINT64_C(4088987648), // VCGTzv2i32
2270 UINT64_C(4088726528), // VCGTzv4f16
2271 UINT64_C(4088988736), // VCGTzv4f32
2272 UINT64_C(4088725504), // VCGTzv4i16
2273 UINT64_C(4088987712), // VCGTzv4i32
2274 UINT64_C(4088726592), // VCGTzv8f16
2275 UINT64_C(4088725568), // VCGTzv8i16
2276 UINT64_C(4088463360), // VCGTzv8i8
2277 UINT64_C(4088463808), // VCLEzv16i8
2278 UINT64_C(4088989056), // VCLEzv2f32
2279 UINT64_C(4088988032), // VCLEzv2i32
2280 UINT64_C(4088726912), // VCLEzv4f16
2281 UINT64_C(4088989120), // VCLEzv4f32
2282 UINT64_C(4088725888), // VCLEzv4i16
2283 UINT64_C(4088988096), // VCLEzv4i32
2284 UINT64_C(4088726976), // VCLEzv8f16
2285 UINT64_C(4088725952), // VCLEzv8i16
2286 UINT64_C(4088463744), // VCLEzv8i8
2287 UINT64_C(4088398912), // VCLSv16i8
2288 UINT64_C(4088923136), // VCLSv2i32
2289 UINT64_C(4088660992), // VCLSv4i16
2290 UINT64_C(4088923200), // VCLSv4i32
2291 UINT64_C(4088661056), // VCLSv8i16
2292 UINT64_C(4088398848), // VCLSv8i8
2293 UINT64_C(4088463936), // VCLTzv16i8
2294 UINT64_C(4088989184), // VCLTzv2f32
2295 UINT64_C(4088988160), // VCLTzv2i32
2296 UINT64_C(4088727040), // VCLTzv4f16
2297 UINT64_C(4088989248), // VCLTzv4f32
2298 UINT64_C(4088726016), // VCLTzv4i16
2299 UINT64_C(4088988224), // VCLTzv4i32
2300 UINT64_C(4088727104), // VCLTzv8f16
2301 UINT64_C(4088726080), // VCLTzv8i16
2302 UINT64_C(4088463872), // VCLTzv8i8
2303 UINT64_C(4088399040), // VCLZv16i8
2304 UINT64_C(4088923264), // VCLZv2i32
2305 UINT64_C(4088661120), // VCLZv4i16
2306 UINT64_C(4088923328), // VCLZv4i32
2307 UINT64_C(4088661184), // VCLZv8i16
2308 UINT64_C(4088398976), // VCLZv8i8
2309 UINT64_C(4231006208), // VCMLAv2f32
2310 UINT64_C(4269803520), // VCMLAv2f32_indexed
2311 UINT64_C(4229957632), // VCMLAv4f16
2312 UINT64_C(4261414912), // VCMLAv4f16_indexed
2313 UINT64_C(4231006272), // VCMLAv4f32
2314 UINT64_C(4269803584), // VCMLAv4f32_indexed
2315 UINT64_C(4229957696), // VCMLAv8f16
2316 UINT64_C(4261414976), // VCMLAv8f16_indexed
2317 UINT64_C(246680384), // VCMPD
2318 UINT64_C(246680512), // VCMPED
2319 UINT64_C(246680000), // VCMPEH
2320 UINT64_C(246680256), // VCMPES
2321 UINT64_C(246746048), // VCMPEZD
2322 UINT64_C(246745536), // VCMPEZH
2323 UINT64_C(246745792), // VCMPEZS
2324 UINT64_C(246679872), // VCMPH
2325 UINT64_C(246680128), // VCMPS
2326 UINT64_C(246745920), // VCMPZD
2327 UINT64_C(246745408), // VCMPZH
2328 UINT64_C(246745664), // VCMPZS
2329 UINT64_C(4088399104), // VCNTd
2330 UINT64_C(4088399168), // VCNTq
2331 UINT64_C(4089118720), // VCVTANSDf
2332 UINT64_C(4088856576), // VCVTANSDh
2333 UINT64_C(4089118784), // VCVTANSQf
2334 UINT64_C(4088856640), // VCVTANSQh
2335 UINT64_C(4089118848), // VCVTANUDf
2336 UINT64_C(4088856704), // VCVTANUDh
2337 UINT64_C(4089118912), // VCVTANUQf
2338 UINT64_C(4088856768), // VCVTANUQh
2339 UINT64_C(4273736640), // VCVTASD
2340 UINT64_C(4273736128), // VCVTASH
2341 UINT64_C(4273736384), // VCVTASS
2342 UINT64_C(4273736512), // VCVTAUD
2343 UINT64_C(4273736000), // VCVTAUH
2344 UINT64_C(4273736256), // VCVTAUS
2345 UINT64_C(246614848), // VCVTBDH
2346 UINT64_C(246549312), // VCVTBHD
2347 UINT64_C(246549056), // VCVTBHS
2348 UINT64_C(246614592), // VCVTBSH
2349 UINT64_C(246876864), // VCVTDS
2350 UINT64_C(4089119488), // VCVTMNSDf
2351 UINT64_C(4088857344), // VCVTMNSDh
2352 UINT64_C(4089119552), // VCVTMNSQf
2353 UINT64_C(4088857408), // VCVTMNSQh
2354 UINT64_C(4089119616), // VCVTMNUDf
2355 UINT64_C(4088857472), // VCVTMNUDh
2356 UINT64_C(4089119680), // VCVTMNUQf
2357 UINT64_C(4088857536), // VCVTMNUQh
2358 UINT64_C(4273933248), // VCVTMSD
2359 UINT64_C(4273932736), // VCVTMSH
2360 UINT64_C(4273932992), // VCVTMSS
2361 UINT64_C(4273933120), // VCVTMUD
2362 UINT64_C(4273932608), // VCVTMUH
2363 UINT64_C(4273932864), // VCVTMUS
2364 UINT64_C(4089118976), // VCVTNNSDf
2365 UINT64_C(4088856832), // VCVTNNSDh
2366 UINT64_C(4089119040), // VCVTNNSQf
2367 UINT64_C(4088856896), // VCVTNNSQh
2368 UINT64_C(4089119104), // VCVTNNUDf
2369 UINT64_C(4088856960), // VCVTNNUDh
2370 UINT64_C(4089119168), // VCVTNNUQf
2371 UINT64_C(4088857024), // VCVTNNUQh
2372 UINT64_C(4273802176), // VCVTNSD
2373 UINT64_C(4273801664), // VCVTNSH
2374 UINT64_C(4273801920), // VCVTNSS
2375 UINT64_C(4273802048), // VCVTNUD
2376 UINT64_C(4273801536), // VCVTNUH
2377 UINT64_C(4273801792), // VCVTNUS
2378 UINT64_C(4089119232), // VCVTPNSDf
2379 UINT64_C(4088857088), // VCVTPNSDh
2380 UINT64_C(4089119296), // VCVTPNSQf
2381 UINT64_C(4088857152), // VCVTPNSQh
2382 UINT64_C(4089119360), // VCVTPNUDf
2383 UINT64_C(4088857216), // VCVTPNUDh
2384 UINT64_C(4089119424), // VCVTPNUQf
2385 UINT64_C(4088857280), // VCVTPNUQh
2386 UINT64_C(4273867712), // VCVTPSD
2387 UINT64_C(4273867200), // VCVTPSH
2388 UINT64_C(4273867456), // VCVTPSS
2389 UINT64_C(4273867584), // VCVTPUD
2390 UINT64_C(4273867072), // VCVTPUH
2391 UINT64_C(4273867328), // VCVTPUS
2392 UINT64_C(246877120), // VCVTSD
2393 UINT64_C(246614976), // VCVTTDH
2394 UINT64_C(246549440), // VCVTTHD
2395 UINT64_C(246549184), // VCVTTHS
2396 UINT64_C(246614720), // VCVTTSH
2397 UINT64_C(4088792576), // VCVTf2h
2398 UINT64_C(4089120512), // VCVTf2sd
2399 UINT64_C(4089120576), // VCVTf2sq
2400 UINT64_C(4089120640), // VCVTf2ud
2401 UINT64_C(4089120704), // VCVTf2uq
2402 UINT64_C(4068478736), // VCVTf2xsd
2403 UINT64_C(4068478800), // VCVTf2xsq
2404 UINT64_C(4085255952), // VCVTf2xud
2405 UINT64_C(4085256016), // VCVTf2xuq
2406 UINT64_C(4088792832), // VCVTh2f
2407 UINT64_C(4088858368), // VCVTh2sd
2408 UINT64_C(4088858432), // VCVTh2sq
2409 UINT64_C(4088858496), // VCVTh2ud
2410 UINT64_C(4088858560), // VCVTh2uq
2411 UINT64_C(4068478224), // VCVTh2xsd
2412 UINT64_C(4068478288), // VCVTh2xsq
2413 UINT64_C(4085255440), // VCVTh2xud
2414 UINT64_C(4085255504), // VCVTh2xuq
2415 UINT64_C(4089120256), // VCVTs2fd
2416 UINT64_C(4089120320), // VCVTs2fq
2417 UINT64_C(4088858112), // VCVTs2hd
2418 UINT64_C(4088858176), // VCVTs2hq
2419 UINT64_C(4089120384), // VCVTu2fd
2420 UINT64_C(4089120448), // VCVTu2fq
2421 UINT64_C(4088858240), // VCVTu2hd
2422 UINT64_C(4088858304), // VCVTu2hq
2423 UINT64_C(4068478480), // VCVTxs2fd
2424 UINT64_C(4068478544), // VCVTxs2fq
2425 UINT64_C(4068477968), // VCVTxs2hd
2426 UINT64_C(4068478032), // VCVTxs2hq
2427 UINT64_C(4085255696), // VCVTxu2fd
2428 UINT64_C(4085255760), // VCVTxu2fq
2429 UINT64_C(4085255184), // VCVTxu2hd
2430 UINT64_C(4085255248), // VCVTxu2hq
2431 UINT64_C(243272448), // VDIVD
2432 UINT64_C(243271936), // VDIVH
2433 UINT64_C(243272192), // VDIVS
2434 UINT64_C(243272496), // VDUP16d
2435 UINT64_C(245369648), // VDUP16q
2436 UINT64_C(243272464), // VDUP32d
2437 UINT64_C(245369616), // VDUP32q
2438 UINT64_C(247466768), // VDUP8d
2439 UINT64_C(249563920), // VDUP8q
2440 UINT64_C(4088531968), // VDUPLN16d
2441 UINT64_C(4088532032), // VDUPLN16q
2442 UINT64_C(4088663040), // VDUPLN32d
2443 UINT64_C(4088663104), // VDUPLN32q
2444 UINT64_C(4088466432), // VDUPLN8d
2445 UINT64_C(4088466496), // VDUPLN8q
2446 UINT64_C(4076863760), // VEORd
2447 UINT64_C(4076863824), // VEORq
2448 UINT64_C(4071620608), // VEXTd16
2449 UINT64_C(4071620608), // VEXTd32
2450 UINT64_C(4071620608), // VEXTd8
2451 UINT64_C(4071620672), // VEXTq16
2452 UINT64_C(4071620672), // VEXTq32
2453 UINT64_C(4071620672), // VEXTq64
2454 UINT64_C(4071620672), // VEXTq8
2455 UINT64_C(245369600), // VFMAD
2456 UINT64_C(245369088), // VFMAH
2457 UINT64_C(4229957648), // VFMALD
2458 UINT64_C(4261414928), // VFMALDI
2459 UINT64_C(4229957712), // VFMALQ
2460 UINT64_C(4261414992), // VFMALQI
2461 UINT64_C(245369344), // VFMAS
2462 UINT64_C(4060089360), // VFMAfd
2463 UINT64_C(4060089424), // VFMAfq
2464 UINT64_C(4061137936), // VFMAhd
2465 UINT64_C(4061138000), // VFMAhq
2466 UINT64_C(245369664), // VFMSD
2467 UINT64_C(245369152), // VFMSH
2468 UINT64_C(4238346256), // VFMSLD
2469 UINT64_C(4262463504), // VFMSLDI
2470 UINT64_C(4238346320), // VFMSLQ
2471 UINT64_C(4262463568), // VFMSLQI
2472 UINT64_C(245369408), // VFMSS
2473 UINT64_C(4062186512), // VFMSfd
2474 UINT64_C(4062186576), // VFMSfq
2475 UINT64_C(4063235088), // VFMShd
2476 UINT64_C(4063235152), // VFMShq
2477 UINT64_C(244321088), // VFNMAD
2478 UINT64_C(244320576), // VFNMAH
2479 UINT64_C(244320832), // VFNMAS
2480 UINT64_C(244321024), // VFNMSD
2481 UINT64_C(244320512), // VFNMSH
2482 UINT64_C(244320768), // VFNMSS
2483 UINT64_C(4269804288), // VFP_VMAXNMD
2484 UINT64_C(4269803776), // VFP_VMAXNMH
2485 UINT64_C(4269804032), // VFP_VMAXNMS
2486 UINT64_C(4269804352), // VFP_VMINNMD
2487 UINT64_C(4269803840), // VFP_VMINNMH
2488 UINT64_C(4269804096), // VFP_VMINNMS
2489 UINT64_C(235932432), // VGETLNi32
2490 UINT64_C(235932464), // VGETLNs16
2491 UINT64_C(240126736), // VGETLNs8
2492 UINT64_C(244321072), // VGETLNu16
2493 UINT64_C(248515344), // VGETLNu8
2494 UINT64_C(4060086336), // VHADDsv16i8
2495 UINT64_C(4062183424), // VHADDsv2i32
2496 UINT64_C(4061134848), // VHADDsv4i16
2497 UINT64_C(4062183488), // VHADDsv4i32
2498 UINT64_C(4061134912), // VHADDsv8i16
2499 UINT64_C(4060086272), // VHADDsv8i8
2500 UINT64_C(4076863552), // VHADDuv16i8
2501 UINT64_C(4078960640), // VHADDuv2i32
2502 UINT64_C(4077912064), // VHADDuv4i16
2503 UINT64_C(4078960704), // VHADDuv4i32
2504 UINT64_C(4077912128), // VHADDuv8i16
2505 UINT64_C(4076863488), // VHADDuv8i8
2506 UINT64_C(4060086848), // VHSUBsv16i8
2507 UINT64_C(4062183936), // VHSUBsv2i32
2508 UINT64_C(4061135360), // VHSUBsv4i16
2509 UINT64_C(4062184000), // VHSUBsv4i32
2510 UINT64_C(4061135424), // VHSUBsv8i16
2511 UINT64_C(4060086784), // VHSUBsv8i8
2512 UINT64_C(4076864064), // VHSUBuv16i8
2513 UINT64_C(4078961152), // VHSUBuv2i32
2514 UINT64_C(4077912576), // VHSUBuv4i16
2515 UINT64_C(4078961216), // VHSUBuv4i32
2516 UINT64_C(4077912640), // VHSUBuv8i16
2517 UINT64_C(4076864000), // VHSUBuv8i8
2518 UINT64_C(4272949952), // VINSH
2519 UINT64_C(247008192), // VJCVT
2520 UINT64_C(4104129615), // VLD1DUPd16
2521 UINT64_C(4104129613), // VLD1DUPd16wb_fixed
2522 UINT64_C(4104129600), // VLD1DUPd16wb_register
2523 UINT64_C(4104129679), // VLD1DUPd32
2524 UINT64_C(4104129677), // VLD1DUPd32wb_fixed
2525 UINT64_C(4104129664), // VLD1DUPd32wb_register
2526 UINT64_C(4104129551), // VLD1DUPd8
2527 UINT64_C(4104129549), // VLD1DUPd8wb_fixed
2528 UINT64_C(4104129536), // VLD1DUPd8wb_register
2529 UINT64_C(4104129647), // VLD1DUPq16
2530 UINT64_C(4104129645), // VLD1DUPq16wb_fixed
2531 UINT64_C(4104129632), // VLD1DUPq16wb_register
2532 UINT64_C(4104129711), // VLD1DUPq32
2533 UINT64_C(4104129709), // VLD1DUPq32wb_fixed
2534 UINT64_C(4104129696), // VLD1DUPq32wb_register
2535 UINT64_C(4104129583), // VLD1DUPq8
2536 UINT64_C(4104129581), // VLD1DUPq8wb_fixed
2537 UINT64_C(4104129568), // VLD1DUPq8wb_register
2538 UINT64_C(4104127503), // VLD1LNd16
2539 UINT64_C(4104127488), // VLD1LNd16_UPD
2540 UINT64_C(4104128527), // VLD1LNd32
2541 UINT64_C(4104128512), // VLD1LNd32_UPD
2542 UINT64_C(4104126479), // VLD1LNd8
2543 UINT64_C(4104126464), // VLD1LNd8_UPD
2544 UINT64_C(0), // VLD1LNq16Pseudo
2545 UINT64_C(0), // VLD1LNq16Pseudo_UPD
2546 UINT64_C(0), // VLD1LNq32Pseudo
2547 UINT64_C(0), // VLD1LNq32Pseudo_UPD
2548 UINT64_C(0), // VLD1LNq8Pseudo
2549 UINT64_C(0), // VLD1LNq8Pseudo_UPD
2550 UINT64_C(4095739727), // VLD1d16
2551 UINT64_C(4095738447), // VLD1d16Q
2552 UINT64_C(0), // VLD1d16QPseudo
2553 UINT64_C(0), // VLD1d16QPseudoWB_fixed
2554 UINT64_C(0), // VLD1d16QPseudoWB_register
2555 UINT64_C(4095738445), // VLD1d16Qwb_fixed
2556 UINT64_C(4095738432), // VLD1d16Qwb_register
2557 UINT64_C(4095739471), // VLD1d16T
2558 UINT64_C(0), // VLD1d16TPseudo
2559 UINT64_C(0), // VLD1d16TPseudoWB_fixed
2560 UINT64_C(0), // VLD1d16TPseudoWB_register
2561 UINT64_C(4095739469), // VLD1d16Twb_fixed
2562 UINT64_C(4095739456), // VLD1d16Twb_register
2563 UINT64_C(4095739725), // VLD1d16wb_fixed
2564 UINT64_C(4095739712), // VLD1d16wb_register
2565 UINT64_C(4095739791), // VLD1d32
2566 UINT64_C(4095738511), // VLD1d32Q
2567 UINT64_C(0), // VLD1d32QPseudo
2568 UINT64_C(0), // VLD1d32QPseudoWB_fixed
2569 UINT64_C(0), // VLD1d32QPseudoWB_register
2570 UINT64_C(4095738509), // VLD1d32Qwb_fixed
2571 UINT64_C(4095738496), // VLD1d32Qwb_register
2572 UINT64_C(4095739535), // VLD1d32T
2573 UINT64_C(0), // VLD1d32TPseudo
2574 UINT64_C(0), // VLD1d32TPseudoWB_fixed
2575 UINT64_C(0), // VLD1d32TPseudoWB_register
2576 UINT64_C(4095739533), // VLD1d32Twb_fixed
2577 UINT64_C(4095739520), // VLD1d32Twb_register
2578 UINT64_C(4095739789), // VLD1d32wb_fixed
2579 UINT64_C(4095739776), // VLD1d32wb_register
2580 UINT64_C(4095739855), // VLD1d64
2581 UINT64_C(4095738575), // VLD1d64Q
2582 UINT64_C(0), // VLD1d64QPseudo
2583 UINT64_C(0), // VLD1d64QPseudoWB_fixed
2584 UINT64_C(0), // VLD1d64QPseudoWB_register
2585 UINT64_C(4095738573), // VLD1d64Qwb_fixed
2586 UINT64_C(4095738560), // VLD1d64Qwb_register
2587 UINT64_C(4095739599), // VLD1d64T
2588 UINT64_C(0), // VLD1d64TPseudo
2589 UINT64_C(0), // VLD1d64TPseudoWB_fixed
2590 UINT64_C(0), // VLD1d64TPseudoWB_register
2591 UINT64_C(4095739597), // VLD1d64Twb_fixed
2592 UINT64_C(4095739584), // VLD1d64Twb_register
2593 UINT64_C(4095739853), // VLD1d64wb_fixed
2594 UINT64_C(4095739840), // VLD1d64wb_register
2595 UINT64_C(4095739663), // VLD1d8
2596 UINT64_C(4095738383), // VLD1d8Q
2597 UINT64_C(0), // VLD1d8QPseudo
2598 UINT64_C(0), // VLD1d8QPseudoWB_fixed
2599 UINT64_C(0), // VLD1d8QPseudoWB_register
2600 UINT64_C(4095738381), // VLD1d8Qwb_fixed
2601 UINT64_C(4095738368), // VLD1d8Qwb_register
2602 UINT64_C(4095739407), // VLD1d8T
2603 UINT64_C(0), // VLD1d8TPseudo
2604 UINT64_C(0), // VLD1d8TPseudoWB_fixed
2605 UINT64_C(0), // VLD1d8TPseudoWB_register
2606 UINT64_C(4095739405), // VLD1d8Twb_fixed
2607 UINT64_C(4095739392), // VLD1d8Twb_register
2608 UINT64_C(4095739661), // VLD1d8wb_fixed
2609 UINT64_C(4095739648), // VLD1d8wb_register
2610 UINT64_C(4095740495), // VLD1q16
2611 UINT64_C(0), // VLD1q16HighQPseudo
2612 UINT64_C(0), // VLD1q16HighQPseudo_UPD
2613 UINT64_C(0), // VLD1q16HighTPseudo
2614 UINT64_C(0), // VLD1q16HighTPseudo_UPD
2615 UINT64_C(0), // VLD1q16LowQPseudo_UPD
2616 UINT64_C(0), // VLD1q16LowTPseudo_UPD
2617 UINT64_C(4095740493), // VLD1q16wb_fixed
2618 UINT64_C(4095740480), // VLD1q16wb_register
2619 UINT64_C(4095740559), // VLD1q32
2620 UINT64_C(0), // VLD1q32HighQPseudo
2621 UINT64_C(0), // VLD1q32HighQPseudo_UPD
2622 UINT64_C(0), // VLD1q32HighTPseudo
2623 UINT64_C(0), // VLD1q32HighTPseudo_UPD
2624 UINT64_C(0), // VLD1q32LowQPseudo_UPD
2625 UINT64_C(0), // VLD1q32LowTPseudo_UPD
2626 UINT64_C(4095740557), // VLD1q32wb_fixed
2627 UINT64_C(4095740544), // VLD1q32wb_register
2628 UINT64_C(4095740623), // VLD1q64
2629 UINT64_C(0), // VLD1q64HighQPseudo
2630 UINT64_C(0), // VLD1q64HighQPseudo_UPD
2631 UINT64_C(0), // VLD1q64HighTPseudo
2632 UINT64_C(0), // VLD1q64HighTPseudo_UPD
2633 UINT64_C(0), // VLD1q64LowQPseudo_UPD
2634 UINT64_C(0), // VLD1q64LowTPseudo_UPD
2635 UINT64_C(4095740621), // VLD1q64wb_fixed
2636 UINT64_C(4095740608), // VLD1q64wb_register
2637 UINT64_C(4095740431), // VLD1q8
2638 UINT64_C(0), // VLD1q8HighQPseudo
2639 UINT64_C(0), // VLD1q8HighQPseudo_UPD
2640 UINT64_C(0), // VLD1q8HighTPseudo
2641 UINT64_C(0), // VLD1q8HighTPseudo_UPD
2642 UINT64_C(0), // VLD1q8LowQPseudo_UPD
2643 UINT64_C(0), // VLD1q8LowTPseudo_UPD
2644 UINT64_C(4095740429), // VLD1q8wb_fixed
2645 UINT64_C(4095740416), // VLD1q8wb_register
2646 UINT64_C(4104129871), // VLD2DUPd16
2647 UINT64_C(4104129869), // VLD2DUPd16wb_fixed
2648 UINT64_C(4104129856), // VLD2DUPd16wb_register
2649 UINT64_C(4104129903), // VLD2DUPd16x2
2650 UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed
2651 UINT64_C(4104129888), // VLD2DUPd16x2wb_register
2652 UINT64_C(4104129935), // VLD2DUPd32
2653 UINT64_C(4104129933), // VLD2DUPd32wb_fixed
2654 UINT64_C(4104129920), // VLD2DUPd32wb_register
2655 UINT64_C(4104129967), // VLD2DUPd32x2
2656 UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed
2657 UINT64_C(4104129952), // VLD2DUPd32x2wb_register
2658 UINT64_C(4104129807), // VLD2DUPd8
2659 UINT64_C(4104129805), // VLD2DUPd8wb_fixed
2660 UINT64_C(4104129792), // VLD2DUPd8wb_register
2661 UINT64_C(4104129839), // VLD2DUPd8x2
2662 UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed
2663 UINT64_C(4104129824), // VLD2DUPd8x2wb_register
2664 UINT64_C(0), // VLD2DUPq16EvenPseudo
2665 UINT64_C(0), // VLD2DUPq16OddPseudo
2666 UINT64_C(0), // VLD2DUPq16OddPseudoWB_fixed
2667 UINT64_C(0), // VLD2DUPq16OddPseudoWB_register
2668 UINT64_C(0), // VLD2DUPq32EvenPseudo
2669 UINT64_C(0), // VLD2DUPq32OddPseudo
2670 UINT64_C(0), // VLD2DUPq32OddPseudoWB_fixed
2671 UINT64_C(0), // VLD2DUPq32OddPseudoWB_register
2672 UINT64_C(0), // VLD2DUPq8EvenPseudo
2673 UINT64_C(0), // VLD2DUPq8OddPseudo
2674 UINT64_C(0), // VLD2DUPq8OddPseudoWB_fixed
2675 UINT64_C(0), // VLD2DUPq8OddPseudoWB_register
2676 UINT64_C(4104127759), // VLD2LNd16
2677 UINT64_C(0), // VLD2LNd16Pseudo
2678 UINT64_C(0), // VLD2LNd16Pseudo_UPD
2679 UINT64_C(4104127744), // VLD2LNd16_UPD
2680 UINT64_C(4104128783), // VLD2LNd32
2681 UINT64_C(0), // VLD2LNd32Pseudo
2682 UINT64_C(0), // VLD2LNd32Pseudo_UPD
2683 UINT64_C(4104128768), // VLD2LNd32_UPD
2684 UINT64_C(4104126735), // VLD2LNd8
2685 UINT64_C(0), // VLD2LNd8Pseudo
2686 UINT64_C(0), // VLD2LNd8Pseudo_UPD
2687 UINT64_C(4104126720), // VLD2LNd8_UPD
2688 UINT64_C(4104127791), // VLD2LNq16
2689 UINT64_C(0), // VLD2LNq16Pseudo
2690 UINT64_C(0), // VLD2LNq16Pseudo_UPD
2691 UINT64_C(4104127776), // VLD2LNq16_UPD
2692 UINT64_C(4104128847), // VLD2LNq32
2693 UINT64_C(0), // VLD2LNq32Pseudo
2694 UINT64_C(0), // VLD2LNq32Pseudo_UPD
2695 UINT64_C(4104128832), // VLD2LNq32_UPD
2696 UINT64_C(4095740239), // VLD2b16
2697 UINT64_C(4095740237), // VLD2b16wb_fixed
2698 UINT64_C(4095740224), // VLD2b16wb_register
2699 UINT64_C(4095740303), // VLD2b32
2700 UINT64_C(4095740301), // VLD2b32wb_fixed
2701 UINT64_C(4095740288), // VLD2b32wb_register
2702 UINT64_C(4095740175), // VLD2b8
2703 UINT64_C(4095740173), // VLD2b8wb_fixed
2704 UINT64_C(4095740160), // VLD2b8wb_register
2705 UINT64_C(4095739983), // VLD2d16
2706 UINT64_C(4095739981), // VLD2d16wb_fixed
2707 UINT64_C(4095739968), // VLD2d16wb_register
2708 UINT64_C(4095740047), // VLD2d32
2709 UINT64_C(4095740045), // VLD2d32wb_fixed
2710 UINT64_C(4095740032), // VLD2d32wb_register
2711 UINT64_C(4095739919), // VLD2d8
2712 UINT64_C(4095739917), // VLD2d8wb_fixed
2713 UINT64_C(4095739904), // VLD2d8wb_register
2714 UINT64_C(4095738703), // VLD2q16
2715 UINT64_C(0), // VLD2q16Pseudo
2716 UINT64_C(0), // VLD2q16PseudoWB_fixed
2717 UINT64_C(0), // VLD2q16PseudoWB_register
2718 UINT64_C(4095738701), // VLD2q16wb_fixed
2719 UINT64_C(4095738688), // VLD2q16wb_register
2720 UINT64_C(4095738767), // VLD2q32
2721 UINT64_C(0), // VLD2q32Pseudo
2722 UINT64_C(0), // VLD2q32PseudoWB_fixed
2723 UINT64_C(0), // VLD2q32PseudoWB_register
2724 UINT64_C(4095738765), // VLD2q32wb_fixed
2725 UINT64_C(4095738752), // VLD2q32wb_register
2726 UINT64_C(4095738639), // VLD2q8
2727 UINT64_C(0), // VLD2q8Pseudo
2728 UINT64_C(0), // VLD2q8PseudoWB_fixed
2729 UINT64_C(0), // VLD2q8PseudoWB_register
2730 UINT64_C(4095738637), // VLD2q8wb_fixed
2731 UINT64_C(4095738624), // VLD2q8wb_register
2732 UINT64_C(4104130127), // VLD3DUPd16
2733 UINT64_C(0), // VLD3DUPd16Pseudo
2734 UINT64_C(0), // VLD3DUPd16Pseudo_UPD
2735 UINT64_C(4104130112), // VLD3DUPd16_UPD
2736 UINT64_C(4104130191), // VLD3DUPd32
2737 UINT64_C(0), // VLD3DUPd32Pseudo
2738 UINT64_C(0), // VLD3DUPd32Pseudo_UPD
2739 UINT64_C(4104130176), // VLD3DUPd32_UPD
2740 UINT64_C(4104130063), // VLD3DUPd8
2741 UINT64_C(0), // VLD3DUPd8Pseudo
2742 UINT64_C(0), // VLD3DUPd8Pseudo_UPD
2743 UINT64_C(4104130048), // VLD3DUPd8_UPD
2744 UINT64_C(4104130159), // VLD3DUPq16
2745 UINT64_C(0), // VLD3DUPq16EvenPseudo
2746 UINT64_C(0), // VLD3DUPq16OddPseudo
2747 UINT64_C(0), // VLD3DUPq16OddPseudo_UPD
2748 UINT64_C(4104130144), // VLD3DUPq16_UPD
2749 UINT64_C(4104130223), // VLD3DUPq32
2750 UINT64_C(0), // VLD3DUPq32EvenPseudo
2751 UINT64_C(0), // VLD3DUPq32OddPseudo
2752 UINT64_C(0), // VLD3DUPq32OddPseudo_UPD
2753 UINT64_C(4104130208), // VLD3DUPq32_UPD
2754 UINT64_C(4104130095), // VLD3DUPq8
2755 UINT64_C(0), // VLD3DUPq8EvenPseudo
2756 UINT64_C(0), // VLD3DUPq8OddPseudo
2757 UINT64_C(0), // VLD3DUPq8OddPseudo_UPD
2758 UINT64_C(4104130080), // VLD3DUPq8_UPD
2759 UINT64_C(4104128015), // VLD3LNd16
2760 UINT64_C(0), // VLD3LNd16Pseudo
2761 UINT64_C(0), // VLD3LNd16Pseudo_UPD
2762 UINT64_C(4104128000), // VLD3LNd16_UPD
2763 UINT64_C(4104129039), // VLD3LNd32
2764 UINT64_C(0), // VLD3LNd32Pseudo
2765 UINT64_C(0), // VLD3LNd32Pseudo_UPD
2766 UINT64_C(4104129024), // VLD3LNd32_UPD
2767 UINT64_C(4104126991), // VLD3LNd8
2768 UINT64_C(0), // VLD3LNd8Pseudo
2769 UINT64_C(0), // VLD3LNd8Pseudo_UPD
2770 UINT64_C(4104126976), // VLD3LNd8_UPD
2771 UINT64_C(4104128047), // VLD3LNq16
2772 UINT64_C(0), // VLD3LNq16Pseudo
2773 UINT64_C(0), // VLD3LNq16Pseudo_UPD
2774 UINT64_C(4104128032), // VLD3LNq16_UPD
2775 UINT64_C(4104129103), // VLD3LNq32
2776 UINT64_C(0), // VLD3LNq32Pseudo
2777 UINT64_C(0), // VLD3LNq32Pseudo_UPD
2778 UINT64_C(4104129088), // VLD3LNq32_UPD
2779 UINT64_C(4095738959), // VLD3d16
2780 UINT64_C(0), // VLD3d16Pseudo
2781 UINT64_C(0), // VLD3d16Pseudo_UPD
2782 UINT64_C(4095738944), // VLD3d16_UPD
2783 UINT64_C(4095739023), // VLD3d32
2784 UINT64_C(0), // VLD3d32Pseudo
2785 UINT64_C(0), // VLD3d32Pseudo_UPD
2786 UINT64_C(4095739008), // VLD3d32_UPD
2787 UINT64_C(4095738895), // VLD3d8
2788 UINT64_C(0), // VLD3d8Pseudo
2789 UINT64_C(0), // VLD3d8Pseudo_UPD
2790 UINT64_C(4095738880), // VLD3d8_UPD
2791 UINT64_C(4095739215), // VLD3q16
2792 UINT64_C(0), // VLD3q16Pseudo_UPD
2793 UINT64_C(4095739200), // VLD3q16_UPD
2794 UINT64_C(0), // VLD3q16oddPseudo
2795 UINT64_C(0), // VLD3q16oddPseudo_UPD
2796 UINT64_C(4095739279), // VLD3q32
2797 UINT64_C(0), // VLD3q32Pseudo_UPD
2798 UINT64_C(4095739264), // VLD3q32_UPD
2799 UINT64_C(0), // VLD3q32oddPseudo
2800 UINT64_C(0), // VLD3q32oddPseudo_UPD
2801 UINT64_C(4095739151), // VLD3q8
2802 UINT64_C(0), // VLD3q8Pseudo_UPD
2803 UINT64_C(4095739136), // VLD3q8_UPD
2804 UINT64_C(0), // VLD3q8oddPseudo
2805 UINT64_C(0), // VLD3q8oddPseudo_UPD
2806 UINT64_C(4104130383), // VLD4DUPd16
2807 UINT64_C(0), // VLD4DUPd16Pseudo
2808 UINT64_C(0), // VLD4DUPd16Pseudo_UPD
2809 UINT64_C(4104130368), // VLD4DUPd16_UPD
2810 UINT64_C(4104130447), // VLD4DUPd32
2811 UINT64_C(0), // VLD4DUPd32Pseudo
2812 UINT64_C(0), // VLD4DUPd32Pseudo_UPD
2813 UINT64_C(4104130432), // VLD4DUPd32_UPD
2814 UINT64_C(4104130319), // VLD4DUPd8
2815 UINT64_C(0), // VLD4DUPd8Pseudo
2816 UINT64_C(0), // VLD4DUPd8Pseudo_UPD
2817 UINT64_C(4104130304), // VLD4DUPd8_UPD
2818 UINT64_C(4104130415), // VLD4DUPq16
2819 UINT64_C(0), // VLD4DUPq16EvenPseudo
2820 UINT64_C(0), // VLD4DUPq16OddPseudo
2821 UINT64_C(0), // VLD4DUPq16OddPseudo_UPD
2822 UINT64_C(4104130400), // VLD4DUPq16_UPD
2823 UINT64_C(4104130479), // VLD4DUPq32
2824 UINT64_C(0), // VLD4DUPq32EvenPseudo
2825 UINT64_C(0), // VLD4DUPq32OddPseudo
2826 UINT64_C(0), // VLD4DUPq32OddPseudo_UPD
2827 UINT64_C(4104130464), // VLD4DUPq32_UPD
2828 UINT64_C(4104130351), // VLD4DUPq8
2829 UINT64_C(0), // VLD4DUPq8EvenPseudo
2830 UINT64_C(0), // VLD4DUPq8OddPseudo
2831 UINT64_C(0), // VLD4DUPq8OddPseudo_UPD
2832 UINT64_C(4104130336), // VLD4DUPq8_UPD
2833 UINT64_C(4104128271), // VLD4LNd16
2834 UINT64_C(0), // VLD4LNd16Pseudo
2835 UINT64_C(0), // VLD4LNd16Pseudo_UPD
2836 UINT64_C(4104128256), // VLD4LNd16_UPD
2837 UINT64_C(4104129295), // VLD4LNd32
2838 UINT64_C(0), // VLD4LNd32Pseudo
2839 UINT64_C(0), // VLD4LNd32Pseudo_UPD
2840 UINT64_C(4104129280), // VLD4LNd32_UPD
2841 UINT64_C(4104127247), // VLD4LNd8
2842 UINT64_C(0), // VLD4LNd8Pseudo
2843 UINT64_C(0), // VLD4LNd8Pseudo_UPD
2844 UINT64_C(4104127232), // VLD4LNd8_UPD
2845 UINT64_C(4104128303), // VLD4LNq16
2846 UINT64_C(0), // VLD4LNq16Pseudo
2847 UINT64_C(0), // VLD4LNq16Pseudo_UPD
2848 UINT64_C(4104128288), // VLD4LNq16_UPD
2849 UINT64_C(4104129359), // VLD4LNq32
2850 UINT64_C(0), // VLD4LNq32Pseudo
2851 UINT64_C(0), // VLD4LNq32Pseudo_UPD
2852 UINT64_C(4104129344), // VLD4LNq32_UPD
2853 UINT64_C(4095737935), // VLD4d16
2854 UINT64_C(0), // VLD4d16Pseudo
2855 UINT64_C(0), // VLD4d16Pseudo_UPD
2856 UINT64_C(4095737920), // VLD4d16_UPD
2857 UINT64_C(4095737999), // VLD4d32
2858 UINT64_C(0), // VLD4d32Pseudo
2859 UINT64_C(0), // VLD4d32Pseudo_UPD
2860 UINT64_C(4095737984), // VLD4d32_UPD
2861 UINT64_C(4095737871), // VLD4d8
2862 UINT64_C(0), // VLD4d8Pseudo
2863 UINT64_C(0), // VLD4d8Pseudo_UPD
2864 UINT64_C(4095737856), // VLD4d8_UPD
2865 UINT64_C(4095738191), // VLD4q16
2866 UINT64_C(0), // VLD4q16Pseudo_UPD
2867 UINT64_C(4095738176), // VLD4q16_UPD
2868 UINT64_C(0), // VLD4q16oddPseudo
2869 UINT64_C(0), // VLD4q16oddPseudo_UPD
2870 UINT64_C(4095738255), // VLD4q32
2871 UINT64_C(0), // VLD4q32Pseudo_UPD
2872 UINT64_C(4095738240), // VLD4q32_UPD
2873 UINT64_C(0), // VLD4q32oddPseudo
2874 UINT64_C(0), // VLD4q32oddPseudo_UPD
2875 UINT64_C(4095738127), // VLD4q8
2876 UINT64_C(0), // VLD4q8Pseudo_UPD
2877 UINT64_C(4095738112), // VLD4q8_UPD
2878 UINT64_C(0), // VLD4q8oddPseudo
2879 UINT64_C(0), // VLD4q8oddPseudo_UPD
2880 UINT64_C(221252352), // VLDMDDB_UPD
2881 UINT64_C(210766592), // VLDMDIA
2882 UINT64_C(212863744), // VLDMDIA_UPD
2883 UINT64_C(0), // VLDMQIA
2884 UINT64_C(221252096), // VLDMSDB_UPD
2885 UINT64_C(210766336), // VLDMSIA
2886 UINT64_C(212863488), // VLDMSIA_UPD
2887 UINT64_C(219155200), // VLDRD
2888 UINT64_C(219154688), // VLDRH
2889 UINT64_C(219154944), // VLDRS
2890 UINT64_C(223399808), // VLDR_FPCXTNS_off
2891 UINT64_C(208719744), // VLDR_FPCXTNS_post
2892 UINT64_C(225496960), // VLDR_FPCXTNS_pre
2893 UINT64_C(223408000), // VLDR_FPCXTS_off
2894 UINT64_C(208727936), // VLDR_FPCXTS_post
2895 UINT64_C(225505152), // VLDR_FPCXTS_pre
2896 UINT64_C(219172736), // VLDR_FPSCR_NZCVQC_off
2897 UINT64_C(204492672), // VLDR_FPSCR_NZCVQC_post
2898 UINT64_C(221269888), // VLDR_FPSCR_NZCVQC_pre
2899 UINT64_C(219164544), // VLDR_FPSCR_off
2900 UINT64_C(204484480), // VLDR_FPSCR_post
2901 UINT64_C(221261696), // VLDR_FPSCR_pre
2902 UINT64_C(223391616), // VLDR_P0_off
2903 UINT64_C(208711552), // VLDR_P0_post
2904 UINT64_C(225488768), // VLDR_P0_pre
2905 UINT64_C(223383424), // VLDR_VPR_off
2906 UINT64_C(208703360), // VLDR_VPR_post
2907 UINT64_C(225480576), // VLDR_VPR_pre
2908 UINT64_C(3962571264), // VLLDM
2909 UINT64_C(3962571392), // VLLDM_T2
2910 UINT64_C(3961522688), // VLSTM
2911 UINT64_C(3961522816), // VLSTM_T2
2912 UINT64_C(4060090112), // VMAXfd
2913 UINT64_C(4060090176), // VMAXfq
2914 UINT64_C(4061138688), // VMAXhd
2915 UINT64_C(4061138752), // VMAXhq
2916 UINT64_C(4060087872), // VMAXsv16i8
2917 UINT64_C(4062184960), // VMAXsv2i32
2918 UINT64_C(4061136384), // VMAXsv4i16
2919 UINT64_C(4062185024), // VMAXsv4i32
2920 UINT64_C(4061136448), // VMAXsv8i16
2921 UINT64_C(4060087808), // VMAXsv8i8
2922 UINT64_C(4076865088), // VMAXuv16i8
2923 UINT64_C(4078962176), // VMAXuv2i32
2924 UINT64_C(4077913600), // VMAXuv4i16
2925 UINT64_C(4078962240), // VMAXuv4i32
2926 UINT64_C(4077913664), // VMAXuv8i16
2927 UINT64_C(4076865024), // VMAXuv8i8
2928 UINT64_C(4062187264), // VMINfd
2929 UINT64_C(4062187328), // VMINfq
2930 UINT64_C(4063235840), // VMINhd
2931 UINT64_C(4063235904), // VMINhq
2932 UINT64_C(4060087888), // VMINsv16i8
2933 UINT64_C(4062184976), // VMINsv2i32
2934 UINT64_C(4061136400), // VMINsv4i16
2935 UINT64_C(4062185040), // VMINsv4i32
2936 UINT64_C(4061136464), // VMINsv8i16
2937 UINT64_C(4060087824), // VMINsv8i8
2938 UINT64_C(4076865104), // VMINuv16i8
2939 UINT64_C(4078962192), // VMINuv2i32
2940 UINT64_C(4077913616), // VMINuv4i16
2941 UINT64_C(4078962256), // VMINuv4i32
2942 UINT64_C(4077913680), // VMINuv8i16
2943 UINT64_C(4076865040), // VMINuv8i8
2944 UINT64_C(234883840), // VMLAD
2945 UINT64_C(234883328), // VMLAH
2946 UINT64_C(4070572608), // VMLALslsv2i32
2947 UINT64_C(4069524032), // VMLALslsv4i16
2948 UINT64_C(4087349824), // VMLALsluv2i32
2949 UINT64_C(4086301248), // VMLALsluv4i16
2950 UINT64_C(4070574080), // VMLALsv2i64
2951 UINT64_C(4069525504), // VMLALsv4i32
2952 UINT64_C(4068476928), // VMLALsv8i16
2953 UINT64_C(4087351296), // VMLALuv2i64
2954 UINT64_C(4086302720), // VMLALuv4i32
2955 UINT64_C(4085254144), // VMLALuv8i16
2956 UINT64_C(234883584), // VMLAS
2957 UINT64_C(4060089616), // VMLAfd
2958 UINT64_C(4060089680), // VMLAfq
2959 UINT64_C(4061138192), // VMLAhd
2960 UINT64_C(4061138256), // VMLAhq
2961 UINT64_C(4070572352), // VMLAslfd
2962 UINT64_C(4087349568), // VMLAslfq
2963 UINT64_C(4069523776), // VMLAslhd
2964 UINT64_C(4086300992), // VMLAslhq
2965 UINT64_C(4070572096), // VMLAslv2i32
2966 UINT64_C(4069523520), // VMLAslv4i16
2967 UINT64_C(4087349312), // VMLAslv4i32
2968 UINT64_C(4086300736), // VMLAslv8i16
2969 UINT64_C(4060088640), // VMLAv16i8
2970 UINT64_C(4062185728), // VMLAv2i32
2971 UINT64_C(4061137152), // VMLAv4i16
2972 UINT64_C(4062185792), // VMLAv4i32
2973 UINT64_C(4061137216), // VMLAv8i16
2974 UINT64_C(4060088576), // VMLAv8i8
2975 UINT64_C(234883904), // VMLSD
2976 UINT64_C(234883392), // VMLSH
2977 UINT64_C(4070573632), // VMLSLslsv2i32
2978 UINT64_C(4069525056), // VMLSLslsv4i16
2979 UINT64_C(4087350848), // VMLSLsluv2i32
2980 UINT64_C(4086302272), // VMLSLsluv4i16
2981 UINT64_C(4070574592), // VMLSLsv2i64
2982 UINT64_C(4069526016), // VMLSLsv4i32
2983 UINT64_C(4068477440), // VMLSLsv8i16
2984 UINT64_C(4087351808), // VMLSLuv2i64
2985 UINT64_C(4086303232), // VMLSLuv4i32
2986 UINT64_C(4085254656), // VMLSLuv8i16
2987 UINT64_C(234883648), // VMLSS
2988 UINT64_C(4062186768), // VMLSfd
2989 UINT64_C(4062186832), // VMLSfq
2990 UINT64_C(4063235344), // VMLShd
2991 UINT64_C(4063235408), // VMLShq
2992 UINT64_C(4070573376), // VMLSslfd
2993 UINT64_C(4087350592), // VMLSslfq
2994 UINT64_C(4069524800), // VMLSslhd
2995 UINT64_C(4086302016), // VMLSslhq
2996 UINT64_C(4070573120), // VMLSslv2i32
2997 UINT64_C(4069524544), // VMLSslv4i16
2998 UINT64_C(4087350336), // VMLSslv4i32
2999 UINT64_C(4086301760), // VMLSslv8i16
3000 UINT64_C(4076865856), // VMLSv16i8
3001 UINT64_C(4078962944), // VMLSv2i32
3002 UINT64_C(4077914368), // VMLSv4i16
3003 UINT64_C(4078963008), // VMLSv4i32
3004 UINT64_C(4077914432), // VMLSv8i16
3005 UINT64_C(4076865792), // VMLSv8i8
3006 UINT64_C(4227861568), // VMMLA
3007 UINT64_C(246418240), // VMOVD
3008 UINT64_C(205523728), // VMOVDRR
3009 UINT64_C(4272949824), // VMOVH
3010 UINT64_C(234883344), // VMOVHR
3011 UINT64_C(4070574608), // VMOVLsv2i64
3012 UINT64_C(4069526032), // VMOVLsv4i32
3013 UINT64_C(4069001744), // VMOVLsv8i16
3014 UINT64_C(4087351824), // VMOVLuv2i64
3015 UINT64_C(4086303248), // VMOVLuv4i32
3016 UINT64_C(4085778960), // VMOVLuv8i16
3017 UINT64_C(4089053696), // VMOVNv2i32
3018 UINT64_C(4088791552), // VMOVNv4i16
3019 UINT64_C(4088529408), // VMOVNv8i8
3020 UINT64_C(235931920), // VMOVRH
3021 UINT64_C(206572304), // VMOVRRD
3022 UINT64_C(206572048), // VMOVRRS
3023 UINT64_C(235932176), // VMOVRS
3024 UINT64_C(246417984), // VMOVS
3025 UINT64_C(234883600), // VMOVSR
3026 UINT64_C(205523472), // VMOVSRR
3027 UINT64_C(4068478544), // VMOVv16i8
3028 UINT64_C(4068478512), // VMOVv1i64
3029 UINT64_C(4068478736), // VMOVv2f32
3030 UINT64_C(4068474896), // VMOVv2i32
3031 UINT64_C(4068478576), // VMOVv2i64
3032 UINT64_C(4068478800), // VMOVv4f32
3033 UINT64_C(4068476944), // VMOVv4i16
3034 UINT64_C(4068474960), // VMOVv4i32
3035 UINT64_C(4068477008), // VMOVv8i16
3036 UINT64_C(4068478480), // VMOVv8i8
3037 UINT64_C(250677776), // VMRS
3038 UINT64_C(251529744), // VMRS_FPCXTNS
3039 UINT64_C(251595280), // VMRS_FPCXTS
3040 UINT64_C(251136528), // VMRS_FPEXC
3041 UINT64_C(251202064), // VMRS_FPINST
3042 UINT64_C(251267600), // VMRS_FPINST2
3043 UINT64_C(250743312), // VMRS_FPSCR_NZCVQC
3044 UINT64_C(250612240), // VMRS_FPSID
3045 UINT64_C(251070992), // VMRS_MVFR0
3046 UINT64_C(251005456), // VMRS_MVFR1
3047 UINT64_C(250939920), // VMRS_MVFR2
3048 UINT64_C(251464208), // VMRS_P0
3049 UINT64_C(251398672), // VMRS_VPR
3050 UINT64_C(249629200), // VMSR
3051 UINT64_C(250481168), // VMSR_FPCXTNS
3052 UINT64_C(250546704), // VMSR_FPCXTS
3053 UINT64_C(250087952), // VMSR_FPEXC
3054 UINT64_C(250153488), // VMSR_FPINST
3055 UINT64_C(250219024), // VMSR_FPINST2
3056 UINT64_C(249694736), // VMSR_FPSCR_NZCVQC
3057 UINT64_C(249563664), // VMSR_FPSID
3058 UINT64_C(250415632), // VMSR_P0
3059 UINT64_C(250350096), // VMSR_VPR
3060 UINT64_C(236980992), // VMULD
3061 UINT64_C(236980480), // VMULH
3062 UINT64_C(4070575616), // VMULLp64
3063 UINT64_C(4068478464), // VMULLp8
3064 UINT64_C(4070574656), // VMULLslsv2i32
3065 UINT64_C(4069526080), // VMULLslsv4i16
3066 UINT64_C(4087351872), // VMULLsluv2i32
3067 UINT64_C(4086303296), // VMULLsluv4i16
3068 UINT64_C(4070575104), // VMULLsv2i64
3069 UINT64_C(4069526528), // VMULLsv4i32
3070 UINT64_C(4068477952), // VMULLsv8i16
3071 UINT64_C(4087352320), // VMULLuv2i64
3072 UINT64_C(4086303744), // VMULLuv4i32
3073 UINT64_C(4085255168), // VMULLuv8i16
3074 UINT64_C(236980736), // VMULS
3075 UINT64_C(4076866832), // VMULfd
3076 UINT64_C(4076866896), // VMULfq
3077 UINT64_C(4077915408), // VMULhd
3078 UINT64_C(4077915472), // VMULhq
3079 UINT64_C(4076865808), // VMULpd
3080 UINT64_C(4076865872), // VMULpq
3081 UINT64_C(4070574400), // VMULslfd
3082 UINT64_C(4087351616), // VMULslfq
3083 UINT64_C(4069525824), // VMULslhd
3084 UINT64_C(4086303040), // VMULslhq
3085 UINT64_C(4070574144), // VMULslv2i32
3086 UINT64_C(4069525568), // VMULslv4i16
3087 UINT64_C(4087351360), // VMULslv4i32
3088 UINT64_C(4086302784), // VMULslv8i16
3089 UINT64_C(4060088656), // VMULv16i8
3090 UINT64_C(4062185744), // VMULv2i32
3091 UINT64_C(4061137168), // VMULv4i16
3092 UINT64_C(4062185808), // VMULv4i32
3093 UINT64_C(4061137232), // VMULv8i16
3094 UINT64_C(4060088592), // VMULv8i8
3095 UINT64_C(4088399232), // VMVNd
3096 UINT64_C(4088399296), // VMVNq
3097 UINT64_C(4068474928), // VMVNv2i32
3098 UINT64_C(4068476976), // VMVNv4i16
3099 UINT64_C(4068474992), // VMVNv4i32
3100 UINT64_C(4068477040), // VMVNv8i16
3101 UINT64_C(246483776), // VNEGD
3102 UINT64_C(246483264), // VNEGH
3103 UINT64_C(246483520), // VNEGS
3104 UINT64_C(4088989632), // VNEGf32q
3105 UINT64_C(4088989568), // VNEGfd
3106 UINT64_C(4088727424), // VNEGhd
3107 UINT64_C(4088727488), // VNEGhq
3108 UINT64_C(4088726400), // VNEGs16d
3109 UINT64_C(4088726464), // VNEGs16q
3110 UINT64_C(4088988544), // VNEGs32d
3111 UINT64_C(4088988608), // VNEGs32q
3112 UINT64_C(4088464256), // VNEGs8d
3113 UINT64_C(4088464320), // VNEGs8q
3114 UINT64_C(235932480), // VNMLAD
3115 UINT64_C(235931968), // VNMLAH
3116 UINT64_C(235932224), // VNMLAS
3117 UINT64_C(235932416), // VNMLSD
3118 UINT64_C(235931904), // VNMLSH
3119 UINT64_C(235932160), // VNMLSS
3120 UINT64_C(236981056), // VNMULD
3121 UINT64_C(236980544), // VNMULH
3122 UINT64_C(236980800), // VNMULS
3123 UINT64_C(4063232272), // VORNd
3124 UINT64_C(4063232336), // VORNq
3125 UINT64_C(4062183696), // VORRd
3126 UINT64_C(4068475152), // VORRiv2i32
3127 UINT64_C(4068477200), // VORRiv4i16
3128 UINT64_C(4068475216), // VORRiv4i32
3129 UINT64_C(4068477264), // VORRiv8i16
3130 UINT64_C(4062183760), // VORRq
3131 UINT64_C(4088399424), // VPADALsv16i8
3132 UINT64_C(4088923648), // VPADALsv2i32
3133 UINT64_C(4088661504), // VPADALsv4i16
3134 UINT64_C(4088923712), // VPADALsv4i32
3135 UINT64_C(4088661568), // VPADALsv8i16
3136 UINT64_C(4088399360), // VPADALsv8i8
3137 UINT64_C(4088399552), // VPADALuv16i8
3138 UINT64_C(4088923776), // VPADALuv2i32
3139 UINT64_C(4088661632), // VPADALuv4i16
3140 UINT64_C(4088923840), // VPADALuv4i32
3141 UINT64_C(4088661696), // VPADALuv8i16
3142 UINT64_C(4088399488), // VPADALuv8i8
3143 UINT64_C(4088398400), // VPADDLsv16i8
3144 UINT64_C(4088922624), // VPADDLsv2i32
3145 UINT64_C(4088660480), // VPADDLsv4i16
3146 UINT64_C(4088922688), // VPADDLsv4i32
3147 UINT64_C(4088660544), // VPADDLsv8i16
3148 UINT64_C(4088398336), // VPADDLsv8i8
3149 UINT64_C(4088398528), // VPADDLuv16i8
3150 UINT64_C(4088922752), // VPADDLuv2i32
3151 UINT64_C(4088660608), // VPADDLuv4i16
3152 UINT64_C(4088922816), // VPADDLuv4i32
3153 UINT64_C(4088660672), // VPADDLuv8i16
3154 UINT64_C(4088398464), // VPADDLuv8i8
3155 UINT64_C(4076866816), // VPADDf
3156 UINT64_C(4077915392), // VPADDh
3157 UINT64_C(4061137680), // VPADDi16
3158 UINT64_C(4062186256), // VPADDi32
3159 UINT64_C(4060089104), // VPADDi8
3160 UINT64_C(4076867328), // VPMAXf
3161 UINT64_C(4077915904), // VPMAXh
3162 UINT64_C(4061137408), // VPMAXs16
3163 UINT64_C(4062185984), // VPMAXs32
3164 UINT64_C(4060088832), // VPMAXs8
3165 UINT64_C(4077914624), // VPMAXu16
3166 UINT64_C(4078963200), // VPMAXu32
3167 UINT64_C(4076866048), // VPMAXu8
3168 UINT64_C(4078964480), // VPMINf
3169 UINT64_C(4080013056), // VPMINh
3170 UINT64_C(4061137424), // VPMINs16
3171 UINT64_C(4062186000), // VPMINs32
3172 UINT64_C(4060088848), // VPMINs8
3173 UINT64_C(4077914640), // VPMINu16
3174 UINT64_C(4078963216), // VPMINu32
3175 UINT64_C(4076866064), // VPMINu8
3176 UINT64_C(4088399680), // VQABSv16i8
3177 UINT64_C(4088923904), // VQABSv2i32
3178 UINT64_C(4088661760), // VQABSv4i16
3179 UINT64_C(4088923968), // VQABSv4i32
3180 UINT64_C(4088661824), // VQABSv8i16
3181 UINT64_C(4088399616), // VQABSv8i8
3182 UINT64_C(4060086352), // VQADDsv16i8
3183 UINT64_C(4063232016), // VQADDsv1i64
3184 UINT64_C(4062183440), // VQADDsv2i32
3185 UINT64_C(4063232080), // VQADDsv2i64
3186 UINT64_C(4061134864), // VQADDsv4i16
3187 UINT64_C(4062183504), // VQADDsv4i32
3188 UINT64_C(4061134928), // VQADDsv8i16
3189 UINT64_C(4060086288), // VQADDsv8i8
3190 UINT64_C(4076863568), // VQADDuv16i8
3191 UINT64_C(4080009232), // VQADDuv1i64
3192 UINT64_C(4078960656), // VQADDuv2i32
3193 UINT64_C(4080009296), // VQADDuv2i64
3194 UINT64_C(4077912080), // VQADDuv4i16
3195 UINT64_C(4078960720), // VQADDuv4i32
3196 UINT64_C(4077912144), // VQADDuv8i16
3197 UINT64_C(4076863504), // VQADDuv8i8
3198 UINT64_C(4070572864), // VQDMLALslv2i32
3199 UINT64_C(4069524288), // VQDMLALslv4i16
3200 UINT64_C(4070574336), // VQDMLALv2i64
3201 UINT64_C(4069525760), // VQDMLALv4i32
3202 UINT64_C(4070573888), // VQDMLSLslv2i32
3203 UINT64_C(4069525312), // VQDMLSLslv4i16
3204 UINT64_C(4070574848), // VQDMLSLv2i64
3205 UINT64_C(4069526272), // VQDMLSLv4i32
3206 UINT64_C(4070575168), // VQDMULHslv2i32
3207 UINT64_C(4069526592), // VQDMULHslv4i16
3208 UINT64_C(4087352384), // VQDMULHslv4i32
3209 UINT64_C(4086303808), // VQDMULHslv8i16
3210 UINT64_C(4062186240), // VQDMULHv2i32
3211 UINT64_C(4061137664), // VQDMULHv4i16
3212 UINT64_C(4062186304), // VQDMULHv4i32
3213 UINT64_C(4061137728), // VQDMULHv8i16
3214 UINT64_C(4070574912), // VQDMULLslv2i32
3215 UINT64_C(4069526336), // VQDMULLslv4i16
3216 UINT64_C(4070575360), // VQDMULLv2i64
3217 UINT64_C(4069526784), // VQDMULLv4i32
3218 UINT64_C(4089053760), // VQMOVNsuv2i32
3219 UINT64_C(4088791616), // VQMOVNsuv4i16
3220 UINT64_C(4088529472), // VQMOVNsuv8i8
3221 UINT64_C(4089053824), // VQMOVNsv2i32
3222 UINT64_C(4088791680), // VQMOVNsv4i16
3223 UINT64_C(4088529536), // VQMOVNsv8i8
3224 UINT64_C(4089053888), // VQMOVNuv2i32
3225 UINT64_C(4088791744), // VQMOVNuv4i16
3226 UINT64_C(4088529600), // VQMOVNuv8i8
3227 UINT64_C(4088399808), // VQNEGv16i8
3228 UINT64_C(4088924032), // VQNEGv2i32
3229 UINT64_C(4088661888), // VQNEGv4i16
3230 UINT64_C(4088924096), // VQNEGv4i32
3231 UINT64_C(4088661952), // VQNEGv8i16
3232 UINT64_C(4088399744), // VQNEGv8i8
3233 UINT64_C(4070575680), // VQRDMLAHslv2i32
3234 UINT64_C(4069527104), // VQRDMLAHslv4i16
3235 UINT64_C(4087352896), // VQRDMLAHslv4i32
3236 UINT64_C(4086304320), // VQRDMLAHslv8i16
3237 UINT64_C(4078963472), // VQRDMLAHv2i32
3238 UINT64_C(4077914896), // VQRDMLAHv4i16
3239 UINT64_C(4078963536), // VQRDMLAHv4i32
3240 UINT64_C(4077914960), // VQRDMLAHv8i16
3241 UINT64_C(4070575936), // VQRDMLSHslv2i32
3242 UINT64_C(4069527360), // VQRDMLSHslv4i16
3243 UINT64_C(4087353152), // VQRDMLSHslv4i32
3244 UINT64_C(4086304576), // VQRDMLSHslv8i16
3245 UINT64_C(4078963728), // VQRDMLSHv2i32
3246 UINT64_C(4077915152), // VQRDMLSHv4i16
3247 UINT64_C(4078963792), // VQRDMLSHv4i32
3248 UINT64_C(4077915216), // VQRDMLSHv8i16
3249 UINT64_C(4070575424), // VQRDMULHslv2i32
3250 UINT64_C(4069526848), // VQRDMULHslv4i16
3251 UINT64_C(4087352640), // VQRDMULHslv4i32
3252 UINT64_C(4086304064), // VQRDMULHslv8i16
3253 UINT64_C(4078963456), // VQRDMULHv2i32
3254 UINT64_C(4077914880), // VQRDMULHv4i16
3255 UINT64_C(4078963520), // VQRDMULHv4i32
3256 UINT64_C(4077914944), // VQRDMULHv8i16
3257 UINT64_C(4060087632), // VQRSHLsv16i8
3258 UINT64_C(4063233296), // VQRSHLsv1i64
3259 UINT64_C(4062184720), // VQRSHLsv2i32
3260 UINT64_C(4063233360), // VQRSHLsv2i64
3261 UINT64_C(4061136144), // VQRSHLsv4i16
3262 UINT64_C(4062184784), // VQRSHLsv4i32
3263 UINT64_C(4061136208), // VQRSHLsv8i16
3264 UINT64_C(4060087568), // VQRSHLsv8i8
3265 UINT64_C(4076864848), // VQRSHLuv16i8
3266 UINT64_C(4080010512), // VQRSHLuv1i64
3267 UINT64_C(4078961936), // VQRSHLuv2i32
3268 UINT64_C(4080010576), // VQRSHLuv2i64
3269 UINT64_C(4077913360), // VQRSHLuv4i16
3270 UINT64_C(4078962000), // VQRSHLuv4i32
3271 UINT64_C(4077913424), // VQRSHLuv8i16
3272 UINT64_C(4076864784), // VQRSHLuv8i8
3273 UINT64_C(4070574416), // VQRSHRNsv2i32
3274 UINT64_C(4069525840), // VQRSHRNsv4i16
3275 UINT64_C(4069001552), // VQRSHRNsv8i8
3276 UINT64_C(4087351632), // VQRSHRNuv2i32
3277 UINT64_C(4086303056), // VQRSHRNuv4i16
3278 UINT64_C(4085778768), // VQRSHRNuv8i8
3279 UINT64_C(4087351376), // VQRSHRUNv2i32
3280 UINT64_C(4086302800), // VQRSHRUNv4i16
3281 UINT64_C(4085778512), // VQRSHRUNv8i8
3282 UINT64_C(4069001040), // VQSHLsiv16i8
3283 UINT64_C(4068476816), // VQSHLsiv1i64
3284 UINT64_C(4070573840), // VQSHLsiv2i32
3285 UINT64_C(4068476880), // VQSHLsiv2i64
3286 UINT64_C(4069525264), // VQSHLsiv4i16
3287 UINT64_C(4070573904), // VQSHLsiv4i32
3288 UINT64_C(4069525328), // VQSHLsiv8i16
3289 UINT64_C(4069000976), // VQSHLsiv8i8
3290 UINT64_C(4085778000), // VQSHLsuv16i8
3291 UINT64_C(4085253776), // VQSHLsuv1i64
3292 UINT64_C(4087350800), // VQSHLsuv2i32
3293 UINT64_C(4085253840), // VQSHLsuv2i64
3294 UINT64_C(4086302224), // VQSHLsuv4i16
3295 UINT64_C(4087350864), // VQSHLsuv4i32
3296 UINT64_C(4086302288), // VQSHLsuv8i16
3297 UINT64_C(4085777936), // VQSHLsuv8i8
3298 UINT64_C(4060087376), // VQSHLsv16i8
3299 UINT64_C(4063233040), // VQSHLsv1i64
3300 UINT64_C(4062184464), // VQSHLsv2i32
3301 UINT64_C(4063233104), // VQSHLsv2i64
3302 UINT64_C(4061135888), // VQSHLsv4i16
3303 UINT64_C(4062184528), // VQSHLsv4i32
3304 UINT64_C(4061135952), // VQSHLsv8i16
3305 UINT64_C(4060087312), // VQSHLsv8i8
3306 UINT64_C(4085778256), // VQSHLuiv16i8
3307 UINT64_C(4085254032), // VQSHLuiv1i64
3308 UINT64_C(4087351056), // VQSHLuiv2i32
3309 UINT64_C(4085254096), // VQSHLuiv2i64
3310 UINT64_C(4086302480), // VQSHLuiv4i16
3311 UINT64_C(4087351120), // VQSHLuiv4i32
3312 UINT64_C(4086302544), // VQSHLuiv8i16
3313 UINT64_C(4085778192), // VQSHLuiv8i8
3314 UINT64_C(4076864592), // VQSHLuv16i8
3315 UINT64_C(4080010256), // VQSHLuv1i64
3316 UINT64_C(4078961680), // VQSHLuv2i32
3317 UINT64_C(4080010320), // VQSHLuv2i64
3318 UINT64_C(4077913104), // VQSHLuv4i16
3319 UINT64_C(4078961744), // VQSHLuv4i32
3320 UINT64_C(4077913168), // VQSHLuv8i16
3321 UINT64_C(4076864528), // VQSHLuv8i8
3322 UINT64_C(4070574352), // VQSHRNsv2i32
3323 UINT64_C(4069525776), // VQSHRNsv4i16
3324 UINT64_C(4069001488), // VQSHRNsv8i8
3325 UINT64_C(4087351568), // VQSHRNuv2i32
3326 UINT64_C(4086302992), // VQSHRNuv4i16
3327 UINT64_C(4085778704), // VQSHRNuv8i8
3328 UINT64_C(4087351312), // VQSHRUNv2i32
3329 UINT64_C(4086302736), // VQSHRUNv4i16
3330 UINT64_C(4085778448), // VQSHRUNv8i8
3331 UINT64_C(4060086864), // VQSUBsv16i8
3332 UINT64_C(4063232528), // VQSUBsv1i64
3333 UINT64_C(4062183952), // VQSUBsv2i32
3334 UINT64_C(4063232592), // VQSUBsv2i64
3335 UINT64_C(4061135376), // VQSUBsv4i16
3336 UINT64_C(4062184016), // VQSUBsv4i32
3337 UINT64_C(4061135440), // VQSUBsv8i16
3338 UINT64_C(4060086800), // VQSUBsv8i8
3339 UINT64_C(4076864080), // VQSUBuv16i8
3340 UINT64_C(4080009744), // VQSUBuv1i64
3341 UINT64_C(4078961168), // VQSUBuv2i32
3342 UINT64_C(4080009808), // VQSUBuv2i64
3343 UINT64_C(4077912592), // VQSUBuv4i16
3344 UINT64_C(4078961232), // VQSUBuv4i32
3345 UINT64_C(4077912656), // VQSUBuv8i16
3346 UINT64_C(4076864016), // VQSUBuv8i8
3347 UINT64_C(4087350272), // VRADDHNv2i32
3348 UINT64_C(4086301696), // VRADDHNv4i16
3349 UINT64_C(4085253120), // VRADDHNv8i8
3350 UINT64_C(4089119744), // VRECPEd
3351 UINT64_C(4089120000), // VRECPEfd
3352 UINT64_C(4089120064), // VRECPEfq
3353 UINT64_C(4088857856), // VRECPEhd
3354 UINT64_C(4088857920), // VRECPEhq
3355 UINT64_C(4089119808), // VRECPEq
3356 UINT64_C(4060090128), // VRECPSfd
3357 UINT64_C(4060090192), // VRECPSfq
3358 UINT64_C(4061138704), // VRECPShd
3359 UINT64_C(4061138768), // VRECPShq
3360 UINT64_C(4088398080), // VREV16d8
3361 UINT64_C(4088398144), // VREV16q8
3362 UINT64_C(4088660096), // VREV32d16
3363 UINT64_C(4088397952), // VREV32d8
3364 UINT64_C(4088660160), // VREV32q16
3365 UINT64_C(4088398016), // VREV32q8
3366 UINT64_C(4088659968), // VREV64d16
3367 UINT64_C(4088922112), // VREV64d32
3368 UINT64_C(4088397824), // VREV64d8
3369 UINT64_C(4088660032), // VREV64q16
3370 UINT64_C(4088922176), // VREV64q32
3371 UINT64_C(4088397888), // VREV64q8
3372 UINT64_C(4060086592), // VRHADDsv16i8
3373 UINT64_C(4062183680), // VRHADDsv2i32
3374 UINT64_C(4061135104), // VRHADDsv4i16
3375 UINT64_C(4062183744), // VRHADDsv4i32
3376 UINT64_C(4061135168), // VRHADDsv8i16
3377 UINT64_C(4060086528), // VRHADDsv8i8
3378 UINT64_C(4076863808), // VRHADDuv16i8
3379 UINT64_C(4078960896), // VRHADDuv2i32
3380 UINT64_C(4077912320), // VRHADDuv4i16
3381 UINT64_C(4078960960), // VRHADDuv4i32
3382 UINT64_C(4077912384), // VRHADDuv8i16
3383 UINT64_C(4076863744), // VRHADDuv8i8
3384 UINT64_C(4273474368), // VRINTAD
3385 UINT64_C(4273473856), // VRINTAH
3386 UINT64_C(4089054464), // VRINTANDf
3387 UINT64_C(4088792320), // VRINTANDh
3388 UINT64_C(4089054528), // VRINTANQf
3389 UINT64_C(4088792384), // VRINTANQh
3390 UINT64_C(4273474112), // VRINTAS
3391 UINT64_C(4273670976), // VRINTMD
3392 UINT64_C(4273670464), // VRINTMH
3393 UINT64_C(4089054848), // VRINTMNDf
3394 UINT64_C(4088792704), // VRINTMNDh
3395 UINT64_C(4089054912), // VRINTMNQf
3396 UINT64_C(4088792768), // VRINTMNQh
3397 UINT64_C(4273670720), // VRINTMS
3398 UINT64_C(4273539904), // VRINTND
3399 UINT64_C(4273539392), // VRINTNH
3400 UINT64_C(4089054208), // VRINTNNDf
3401 UINT64_C(4088792064), // VRINTNNDh
3402 UINT64_C(4089054272), // VRINTNNQf
3403 UINT64_C(4088792128), // VRINTNNQh
3404 UINT64_C(4273539648), // VRINTNS
3405 UINT64_C(4273605440), // VRINTPD
3406 UINT64_C(4273604928), // VRINTPH
3407 UINT64_C(4089055104), // VRINTPNDf
3408 UINT64_C(4088792960), // VRINTPNDh
3409 UINT64_C(4089055168), // VRINTPNQf
3410 UINT64_C(4088793024), // VRINTPNQh
3411 UINT64_C(4273605184), // VRINTPS
3412 UINT64_C(246811456), // VRINTRD
3413 UINT64_C(246810944), // VRINTRH
3414 UINT64_C(246811200), // VRINTRS
3415 UINT64_C(246876992), // VRINTXD
3416 UINT64_C(246876480), // VRINTXH
3417 UINT64_C(4089054336), // VRINTXNDf
3418 UINT64_C(4088792192), // VRINTXNDh
3419 UINT64_C(4089054400), // VRINTXNQf
3420 UINT64_C(4088792256), // VRINTXNQh
3421 UINT64_C(246876736), // VRINTXS
3422 UINT64_C(246811584), // VRINTZD
3423 UINT64_C(246811072), // VRINTZH
3424 UINT64_C(4089054592), // VRINTZNDf
3425 UINT64_C(4088792448), // VRINTZNDh
3426 UINT64_C(4089054656), // VRINTZNQf
3427 UINT64_C(4088792512), // VRINTZNQh
3428 UINT64_C(246811328), // VRINTZS
3429 UINT64_C(4060087616), // VRSHLsv16i8
3430 UINT64_C(4063233280), // VRSHLsv1i64
3431 UINT64_C(4062184704), // VRSHLsv2i32
3432 UINT64_C(4063233344), // VRSHLsv2i64
3433 UINT64_C(4061136128), // VRSHLsv4i16
3434 UINT64_C(4062184768), // VRSHLsv4i32
3435 UINT64_C(4061136192), // VRSHLsv8i16
3436 UINT64_C(4060087552), // VRSHLsv8i8
3437 UINT64_C(4076864832), // VRSHLuv16i8
3438 UINT64_C(4080010496), // VRSHLuv1i64
3439 UINT64_C(4078961920), // VRSHLuv2i32
3440 UINT64_C(4080010560), // VRSHLuv2i64
3441 UINT64_C(4077913344), // VRSHLuv4i16
3442 UINT64_C(4078961984), // VRSHLuv4i32
3443 UINT64_C(4077913408), // VRSHLuv8i16
3444 UINT64_C(4076864768), // VRSHLuv8i8
3445 UINT64_C(4070574160), // VRSHRNv2i32
3446 UINT64_C(4069525584), // VRSHRNv4i16
3447 UINT64_C(4069001296), // VRSHRNv8i8
3448 UINT64_C(4068999760), // VRSHRsv16i8
3449 UINT64_C(4068475536), // VRSHRsv1i64
3450 UINT64_C(4070572560), // VRSHRsv2i32
3451 UINT64_C(4068475600), // VRSHRsv2i64
3452 UINT64_C(4069523984), // VRSHRsv4i16
3453 UINT64_C(4070572624), // VRSHRsv4i32
3454 UINT64_C(4069524048), // VRSHRsv8i16
3455 UINT64_C(4068999696), // VRSHRsv8i8
3456 UINT64_C(4085776976), // VRSHRuv16i8
3457 UINT64_C(4085252752), // VRSHRuv1i64
3458 UINT64_C(4087349776), // VRSHRuv2i32
3459 UINT64_C(4085252816), // VRSHRuv2i64
3460 UINT64_C(4086301200), // VRSHRuv4i16
3461 UINT64_C(4087349840), // VRSHRuv4i32
3462 UINT64_C(4086301264), // VRSHRuv8i16
3463 UINT64_C(4085776912), // VRSHRuv8i8
3464 UINT64_C(4089119872), // VRSQRTEd
3465 UINT64_C(4089120128), // VRSQRTEfd
3466 UINT64_C(4089120192), // VRSQRTEfq
3467 UINT64_C(4088857984), // VRSQRTEhd
3468 UINT64_C(4088858048), // VRSQRTEhq
3469 UINT64_C(4089119936), // VRSQRTEq
3470 UINT64_C(4062187280), // VRSQRTSfd
3471 UINT64_C(4062187344), // VRSQRTSfq
3472 UINT64_C(4063235856), // VRSQRTShd
3473 UINT64_C(4063235920), // VRSQRTShq
3474 UINT64_C(4069000016), // VRSRAsv16i8
3475 UINT64_C(4068475792), // VRSRAsv1i64
3476 UINT64_C(4070572816), // VRSRAsv2i32
3477 UINT64_C(4068475856), // VRSRAsv2i64
3478 UINT64_C(4069524240), // VRSRAsv4i16
3479 UINT64_C(4070572880), // VRSRAsv4i32
3480 UINT64_C(4069524304), // VRSRAsv8i16
3481 UINT64_C(4068999952), // VRSRAsv8i8
3482 UINT64_C(4085777232), // VRSRAuv16i8
3483 UINT64_C(4085253008), // VRSRAuv1i64
3484 UINT64_C(4087350032), // VRSRAuv2i32
3485 UINT64_C(4085253072), // VRSRAuv2i64
3486 UINT64_C(4086301456), // VRSRAuv4i16
3487 UINT64_C(4087350096), // VRSRAuv4i32
3488 UINT64_C(4086301520), // VRSRAuv8i16
3489 UINT64_C(4085777168), // VRSRAuv8i8
3490 UINT64_C(4087350784), // VRSUBHNv2i32
3491 UINT64_C(4086302208), // VRSUBHNv4i16
3492 UINT64_C(4085253632), // VRSUBHNv8i8
3493 UINT64_C(3969846016), // VSCCLRMD
3494 UINT64_C(3969845760), // VSCCLRMS
3495 UINT64_C(4229958912), // VSDOTD
3496 UINT64_C(4263513344), // VSDOTDI
3497 UINT64_C(4229958976), // VSDOTQ
3498 UINT64_C(4263513408), // VSDOTQI
3499 UINT64_C(4261415680), // VSELEQD
3500 UINT64_C(4261415168), // VSELEQH
3501 UINT64_C(4261415424), // VSELEQS
3502 UINT64_C(4263512832), // VSELGED
3503 UINT64_C(4263512320), // VSELGEH
3504 UINT64_C(4263512576), // VSELGES
3505 UINT64_C(4264561408), // VSELGTD
3506 UINT64_C(4264560896), // VSELGTH
3507 UINT64_C(4264561152), // VSELGTS
3508 UINT64_C(4262464256), // VSELVSD
3509 UINT64_C(4262463744), // VSELVSH
3510 UINT64_C(4262464000), // VSELVSS
3511 UINT64_C(234883888), // VSETLNi16
3512 UINT64_C(234883856), // VSETLNi32
3513 UINT64_C(239078160), // VSETLNi8
3514 UINT64_C(4088791808), // VSHLLi16
3515 UINT64_C(4089053952), // VSHLLi32
3516 UINT64_C(4088529664), // VSHLLi8
3517 UINT64_C(4070574608), // VSHLLsv2i64
3518 UINT64_C(4069526032), // VSHLLsv4i32
3519 UINT64_C(4069001744), // VSHLLsv8i16
3520 UINT64_C(4087351824), // VSHLLuv2i64
3521 UINT64_C(4086303248), // VSHLLuv4i32
3522 UINT64_C(4085778960), // VSHLLuv8i16
3523 UINT64_C(4069000528), // VSHLiv16i8
3524 UINT64_C(4068476304), // VSHLiv1i64
3525 UINT64_C(4070573328), // VSHLiv2i32
3526 UINT64_C(4068476368), // VSHLiv2i64
3527 UINT64_C(4069524752), // VSHLiv4i16
3528 UINT64_C(4070573392), // VSHLiv4i32
3529 UINT64_C(4069524816), // VSHLiv8i16
3530 UINT64_C(4069000464), // VSHLiv8i8
3531 UINT64_C(4060087360), // VSHLsv16i8
3532 UINT64_C(4063233024), // VSHLsv1i64
3533 UINT64_C(4062184448), // VSHLsv2i32
3534 UINT64_C(4063233088), // VSHLsv2i64
3535 UINT64_C(4061135872), // VSHLsv4i16
3536 UINT64_C(4062184512), // VSHLsv4i32
3537 UINT64_C(4061135936), // VSHLsv8i16
3538 UINT64_C(4060087296), // VSHLsv8i8
3539 UINT64_C(4076864576), // VSHLuv16i8
3540 UINT64_C(4080010240), // VSHLuv1i64
3541 UINT64_C(4078961664), // VSHLuv2i32
3542 UINT64_C(4080010304), // VSHLuv2i64
3543 UINT64_C(4077913088), // VSHLuv4i16
3544 UINT64_C(4078961728), // VSHLuv4i32
3545 UINT64_C(4077913152), // VSHLuv8i16
3546 UINT64_C(4076864512), // VSHLuv8i8
3547 UINT64_C(4070574096), // VSHRNv2i32
3548 UINT64_C(4069525520), // VSHRNv4i16
3549 UINT64_C(4069001232), // VSHRNv8i8
3550 UINT64_C(4068999248), // VSHRsv16i8
3551 UINT64_C(4068475024), // VSHRsv1i64
3552 UINT64_C(4070572048), // VSHRsv2i32
3553 UINT64_C(4068475088), // VSHRsv2i64
3554 UINT64_C(4069523472), // VSHRsv4i16
3555 UINT64_C(4070572112), // VSHRsv4i32
3556 UINT64_C(4069523536), // VSHRsv8i16
3557 UINT64_C(4068999184), // VSHRsv8i8
3558 UINT64_C(4085776464), // VSHRuv16i8
3559 UINT64_C(4085252240), // VSHRuv1i64
3560 UINT64_C(4087349264), // VSHRuv2i32
3561 UINT64_C(4085252304), // VSHRuv2i64
3562 UINT64_C(4086300688), // VSHRuv4i16
3563 UINT64_C(4087349328), // VSHRuv4i32
3564 UINT64_C(4086300752), // VSHRuv8i16
3565 UINT64_C(4085776400), // VSHRuv8i8
3566 UINT64_C(247073600), // VSHTOD
3567 UINT64_C(247073088), // VSHTOH
3568 UINT64_C(247073344), // VSHTOS
3569 UINT64_C(246942656), // VSITOD
3570 UINT64_C(246942144), // VSITOH
3571 UINT64_C(246942400), // VSITOS
3572 UINT64_C(4085777744), // VSLIv16i8
3573 UINT64_C(4085253520), // VSLIv1i64
3574 UINT64_C(4087350544), // VSLIv2i32
3575 UINT64_C(4085253584), // VSLIv2i64
3576 UINT64_C(4086301968), // VSLIv4i16
3577 UINT64_C(4087350608), // VSLIv4i32
3578 UINT64_C(4086302032), // VSLIv8i16
3579 UINT64_C(4085777680), // VSLIv8i8
3580 UINT64_C(247073728), // VSLTOD
3581 UINT64_C(247073216), // VSLTOH
3582 UINT64_C(247073472), // VSLTOS
3583 UINT64_C(4229958720), // VSMMLA
3584 UINT64_C(246483904), // VSQRTD
3585 UINT64_C(246483392), // VSQRTH
3586 UINT64_C(246483648), // VSQRTS
3587 UINT64_C(4068999504), // VSRAsv16i8
3588 UINT64_C(4068475280), // VSRAsv1i64
3589 UINT64_C(4070572304), // VSRAsv2i32
3590 UINT64_C(4068475344), // VSRAsv2i64
3591 UINT64_C(4069523728), // VSRAsv4i16
3592 UINT64_C(4070572368), // VSRAsv4i32
3593 UINT64_C(4069523792), // VSRAsv8i16
3594 UINT64_C(4068999440), // VSRAsv8i8
3595 UINT64_C(4085776720), // VSRAuv16i8
3596 UINT64_C(4085252496), // VSRAuv1i64
3597 UINT64_C(4087349520), // VSRAuv2i32
3598 UINT64_C(4085252560), // VSRAuv2i64
3599 UINT64_C(4086300944), // VSRAuv4i16
3600 UINT64_C(4087349584), // VSRAuv4i32
3601 UINT64_C(4086301008), // VSRAuv8i16
3602 UINT64_C(4085776656), // VSRAuv8i8
3603 UINT64_C(4085777488), // VSRIv16i8
3604 UINT64_C(4085253264), // VSRIv1i64
3605 UINT64_C(4087350288), // VSRIv2i32
3606 UINT64_C(4085253328), // VSRIv2i64
3607 UINT64_C(4086301712), // VSRIv4i16
3608 UINT64_C(4087350352), // VSRIv4i32
3609 UINT64_C(4086301776), // VSRIv8i16
3610 UINT64_C(4085777424), // VSRIv8i8
3611 UINT64_C(4102030351), // VST1LNd16
3612 UINT64_C(4102030336), // VST1LNd16_UPD
3613 UINT64_C(4102031375), // VST1LNd32
3614 UINT64_C(4102031360), // VST1LNd32_UPD
3615 UINT64_C(4102029327), // VST1LNd8
3616 UINT64_C(4102029312), // VST1LNd8_UPD
3617 UINT64_C(0), // VST1LNq16Pseudo
3618 UINT64_C(0), // VST1LNq16Pseudo_UPD
3619 UINT64_C(0), // VST1LNq32Pseudo
3620 UINT64_C(0), // VST1LNq32Pseudo_UPD
3621 UINT64_C(0), // VST1LNq8Pseudo
3622 UINT64_C(0), // VST1LNq8Pseudo_UPD
3623 UINT64_C(4093642575), // VST1d16
3624 UINT64_C(4093641295), // VST1d16Q
3625 UINT64_C(0), // VST1d16QPseudo
3626 UINT64_C(0), // VST1d16QPseudoWB_fixed
3627 UINT64_C(0), // VST1d16QPseudoWB_register
3628 UINT64_C(4093641293), // VST1d16Qwb_fixed
3629 UINT64_C(4093641280), // VST1d16Qwb_register
3630 UINT64_C(4093642319), // VST1d16T
3631 UINT64_C(0), // VST1d16TPseudo
3632 UINT64_C(0), // VST1d16TPseudoWB_fixed
3633 UINT64_C(0), // VST1d16TPseudoWB_register
3634 UINT64_C(4093642317), // VST1d16Twb_fixed
3635 UINT64_C(4093642304), // VST1d16Twb_register
3636 UINT64_C(4093642573), // VST1d16wb_fixed
3637 UINT64_C(4093642560), // VST1d16wb_register
3638 UINT64_C(4093642639), // VST1d32
3639 UINT64_C(4093641359), // VST1d32Q
3640 UINT64_C(0), // VST1d32QPseudo
3641 UINT64_C(0), // VST1d32QPseudoWB_fixed
3642 UINT64_C(0), // VST1d32QPseudoWB_register
3643 UINT64_C(4093641357), // VST1d32Qwb_fixed
3644 UINT64_C(4093641344), // VST1d32Qwb_register
3645 UINT64_C(4093642383), // VST1d32T
3646 UINT64_C(0), // VST1d32TPseudo
3647 UINT64_C(0), // VST1d32TPseudoWB_fixed
3648 UINT64_C(0), // VST1d32TPseudoWB_register
3649 UINT64_C(4093642381), // VST1d32Twb_fixed
3650 UINT64_C(4093642368), // VST1d32Twb_register
3651 UINT64_C(4093642637), // VST1d32wb_fixed
3652 UINT64_C(4093642624), // VST1d32wb_register
3653 UINT64_C(4093642703), // VST1d64
3654 UINT64_C(4093641423), // VST1d64Q
3655 UINT64_C(0), // VST1d64QPseudo
3656 UINT64_C(0), // VST1d64QPseudoWB_fixed
3657 UINT64_C(0), // VST1d64QPseudoWB_register
3658 UINT64_C(4093641421), // VST1d64Qwb_fixed
3659 UINT64_C(4093641408), // VST1d64Qwb_register
3660 UINT64_C(4093642447), // VST1d64T
3661 UINT64_C(0), // VST1d64TPseudo
3662 UINT64_C(0), // VST1d64TPseudoWB_fixed
3663 UINT64_C(0), // VST1d64TPseudoWB_register
3664 UINT64_C(4093642445), // VST1d64Twb_fixed
3665 UINT64_C(4093642432), // VST1d64Twb_register
3666 UINT64_C(4093642701), // VST1d64wb_fixed
3667 UINT64_C(4093642688), // VST1d64wb_register
3668 UINT64_C(4093642511), // VST1d8
3669 UINT64_C(4093641231), // VST1d8Q
3670 UINT64_C(0), // VST1d8QPseudo
3671 UINT64_C(0), // VST1d8QPseudoWB_fixed
3672 UINT64_C(0), // VST1d8QPseudoWB_register
3673 UINT64_C(4093641229), // VST1d8Qwb_fixed
3674 UINT64_C(4093641216), // VST1d8Qwb_register
3675 UINT64_C(4093642255), // VST1d8T
3676 UINT64_C(0), // VST1d8TPseudo
3677 UINT64_C(0), // VST1d8TPseudoWB_fixed
3678 UINT64_C(0), // VST1d8TPseudoWB_register
3679 UINT64_C(4093642253), // VST1d8Twb_fixed
3680 UINT64_C(4093642240), // VST1d8Twb_register
3681 UINT64_C(4093642509), // VST1d8wb_fixed
3682 UINT64_C(4093642496), // VST1d8wb_register
3683 UINT64_C(4093643343), // VST1q16
3684 UINT64_C(0), // VST1q16HighQPseudo
3685 UINT64_C(0), // VST1q16HighQPseudo_UPD
3686 UINT64_C(0), // VST1q16HighTPseudo
3687 UINT64_C(0), // VST1q16HighTPseudo_UPD
3688 UINT64_C(0), // VST1q16LowQPseudo_UPD
3689 UINT64_C(0), // VST1q16LowTPseudo_UPD
3690 UINT64_C(4093643341), // VST1q16wb_fixed
3691 UINT64_C(4093643328), // VST1q16wb_register
3692 UINT64_C(4093643407), // VST1q32
3693 UINT64_C(0), // VST1q32HighQPseudo
3694 UINT64_C(0), // VST1q32HighQPseudo_UPD
3695 UINT64_C(0), // VST1q32HighTPseudo
3696 UINT64_C(0), // VST1q32HighTPseudo_UPD
3697 UINT64_C(0), // VST1q32LowQPseudo_UPD
3698 UINT64_C(0), // VST1q32LowTPseudo_UPD
3699 UINT64_C(4093643405), // VST1q32wb_fixed
3700 UINT64_C(4093643392), // VST1q32wb_register
3701 UINT64_C(4093643471), // VST1q64
3702 UINT64_C(0), // VST1q64HighQPseudo
3703 UINT64_C(0), // VST1q64HighQPseudo_UPD
3704 UINT64_C(0), // VST1q64HighTPseudo
3705 UINT64_C(0), // VST1q64HighTPseudo_UPD
3706 UINT64_C(0), // VST1q64LowQPseudo_UPD
3707 UINT64_C(0), // VST1q64LowTPseudo_UPD
3708 UINT64_C(4093643469), // VST1q64wb_fixed
3709 UINT64_C(4093643456), // VST1q64wb_register
3710 UINT64_C(4093643279), // VST1q8
3711 UINT64_C(0), // VST1q8HighQPseudo
3712 UINT64_C(0), // VST1q8HighQPseudo_UPD
3713 UINT64_C(0), // VST1q8HighTPseudo
3714 UINT64_C(0), // VST1q8HighTPseudo_UPD
3715 UINT64_C(0), // VST1q8LowQPseudo_UPD
3716 UINT64_C(0), // VST1q8LowTPseudo_UPD
3717 UINT64_C(4093643277), // VST1q8wb_fixed
3718 UINT64_C(4093643264), // VST1q8wb_register
3719 UINT64_C(4102030607), // VST2LNd16
3720 UINT64_C(0), // VST2LNd16Pseudo
3721 UINT64_C(0), // VST2LNd16Pseudo_UPD
3722 UINT64_C(4102030592), // VST2LNd16_UPD
3723 UINT64_C(4102031631), // VST2LNd32
3724 UINT64_C(0), // VST2LNd32Pseudo
3725 UINT64_C(0), // VST2LNd32Pseudo_UPD
3726 UINT64_C(4102031616), // VST2LNd32_UPD
3727 UINT64_C(4102029583), // VST2LNd8
3728 UINT64_C(0), // VST2LNd8Pseudo
3729 UINT64_C(0), // VST2LNd8Pseudo_UPD
3730 UINT64_C(4102029568), // VST2LNd8_UPD
3731 UINT64_C(4102030639), // VST2LNq16
3732 UINT64_C(0), // VST2LNq16Pseudo
3733 UINT64_C(0), // VST2LNq16Pseudo_UPD
3734 UINT64_C(4102030624), // VST2LNq16_UPD
3735 UINT64_C(4102031695), // VST2LNq32
3736 UINT64_C(0), // VST2LNq32Pseudo
3737 UINT64_C(0), // VST2LNq32Pseudo_UPD
3738 UINT64_C(4102031680), // VST2LNq32_UPD
3739 UINT64_C(4093643087), // VST2b16
3740 UINT64_C(4093643085), // VST2b16wb_fixed
3741 UINT64_C(4093643072), // VST2b16wb_register
3742 UINT64_C(4093643151), // VST2b32
3743 UINT64_C(4093643149), // VST2b32wb_fixed
3744 UINT64_C(4093643136), // VST2b32wb_register
3745 UINT64_C(4093643023), // VST2b8
3746 UINT64_C(4093643021), // VST2b8wb_fixed
3747 UINT64_C(4093643008), // VST2b8wb_register
3748 UINT64_C(4093642831), // VST2d16
3749 UINT64_C(4093642829), // VST2d16wb_fixed
3750 UINT64_C(4093642816), // VST2d16wb_register
3751 UINT64_C(4093642895), // VST2d32
3752 UINT64_C(4093642893), // VST2d32wb_fixed
3753 UINT64_C(4093642880), // VST2d32wb_register
3754 UINT64_C(4093642767), // VST2d8
3755 UINT64_C(4093642765), // VST2d8wb_fixed
3756 UINT64_C(4093642752), // VST2d8wb_register
3757 UINT64_C(4093641551), // VST2q16
3758 UINT64_C(0), // VST2q16Pseudo
3759 UINT64_C(0), // VST2q16PseudoWB_fixed
3760 UINT64_C(0), // VST2q16PseudoWB_register
3761 UINT64_C(4093641549), // VST2q16wb_fixed
3762 UINT64_C(4093641536), // VST2q16wb_register
3763 UINT64_C(4093641615), // VST2q32
3764 UINT64_C(0), // VST2q32Pseudo
3765 UINT64_C(0), // VST2q32PseudoWB_fixed
3766 UINT64_C(0), // VST2q32PseudoWB_register
3767 UINT64_C(4093641613), // VST2q32wb_fixed
3768 UINT64_C(4093641600), // VST2q32wb_register
3769 UINT64_C(4093641487), // VST2q8
3770 UINT64_C(0), // VST2q8Pseudo
3771 UINT64_C(0), // VST2q8PseudoWB_fixed
3772 UINT64_C(0), // VST2q8PseudoWB_register
3773 UINT64_C(4093641485), // VST2q8wb_fixed
3774 UINT64_C(4093641472), // VST2q8wb_register
3775 UINT64_C(4102030863), // VST3LNd16
3776 UINT64_C(0), // VST3LNd16Pseudo
3777 UINT64_C(0), // VST3LNd16Pseudo_UPD
3778 UINT64_C(4102030848), // VST3LNd16_UPD
3779 UINT64_C(4102031887), // VST3LNd32
3780 UINT64_C(0), // VST3LNd32Pseudo
3781 UINT64_C(0), // VST3LNd32Pseudo_UPD
3782 UINT64_C(4102031872), // VST3LNd32_UPD
3783 UINT64_C(4102029839), // VST3LNd8
3784 UINT64_C(0), // VST3LNd8Pseudo
3785 UINT64_C(0), // VST3LNd8Pseudo_UPD
3786 UINT64_C(4102029824), // VST3LNd8_UPD
3787 UINT64_C(4102030895), // VST3LNq16
3788 UINT64_C(0), // VST3LNq16Pseudo
3789 UINT64_C(0), // VST3LNq16Pseudo_UPD
3790 UINT64_C(4102030880), // VST3LNq16_UPD
3791 UINT64_C(4102031951), // VST3LNq32
3792 UINT64_C(0), // VST3LNq32Pseudo
3793 UINT64_C(0), // VST3LNq32Pseudo_UPD
3794 UINT64_C(4102031936), // VST3LNq32_UPD
3795 UINT64_C(4093641807), // VST3d16
3796 UINT64_C(0), // VST3d16Pseudo
3797 UINT64_C(0), // VST3d16Pseudo_UPD
3798 UINT64_C(4093641792), // VST3d16_UPD
3799 UINT64_C(4093641871), // VST3d32
3800 UINT64_C(0), // VST3d32Pseudo
3801 UINT64_C(0), // VST3d32Pseudo_UPD
3802 UINT64_C(4093641856), // VST3d32_UPD
3803 UINT64_C(4093641743), // VST3d8
3804 UINT64_C(0), // VST3d8Pseudo
3805 UINT64_C(0), // VST3d8Pseudo_UPD
3806 UINT64_C(4093641728), // VST3d8_UPD
3807 UINT64_C(4093642063), // VST3q16
3808 UINT64_C(0), // VST3q16Pseudo_UPD
3809 UINT64_C(4093642048), // VST3q16_UPD
3810 UINT64_C(0), // VST3q16oddPseudo
3811 UINT64_C(0), // VST3q16oddPseudo_UPD
3812 UINT64_C(4093642127), // VST3q32
3813 UINT64_C(0), // VST3q32Pseudo_UPD
3814 UINT64_C(4093642112), // VST3q32_UPD
3815 UINT64_C(0), // VST3q32oddPseudo
3816 UINT64_C(0), // VST3q32oddPseudo_UPD
3817 UINT64_C(4093641999), // VST3q8
3818 UINT64_C(0), // VST3q8Pseudo_UPD
3819 UINT64_C(4093641984), // VST3q8_UPD
3820 UINT64_C(0), // VST3q8oddPseudo
3821 UINT64_C(0), // VST3q8oddPseudo_UPD
3822 UINT64_C(4102031119), // VST4LNd16
3823 UINT64_C(0), // VST4LNd16Pseudo
3824 UINT64_C(0), // VST4LNd16Pseudo_UPD
3825 UINT64_C(4102031104), // VST4LNd16_UPD
3826 UINT64_C(4102032143), // VST4LNd32
3827 UINT64_C(0), // VST4LNd32Pseudo
3828 UINT64_C(0), // VST4LNd32Pseudo_UPD
3829 UINT64_C(4102032128), // VST4LNd32_UPD
3830 UINT64_C(4102030095), // VST4LNd8
3831 UINT64_C(0), // VST4LNd8Pseudo
3832 UINT64_C(0), // VST4LNd8Pseudo_UPD
3833 UINT64_C(4102030080), // VST4LNd8_UPD
3834 UINT64_C(4102031151), // VST4LNq16
3835 UINT64_C(0), // VST4LNq16Pseudo
3836 UINT64_C(0), // VST4LNq16Pseudo_UPD
3837 UINT64_C(4102031136), // VST4LNq16_UPD
3838 UINT64_C(4102032207), // VST4LNq32
3839 UINT64_C(0), // VST4LNq32Pseudo
3840 UINT64_C(0), // VST4LNq32Pseudo_UPD
3841 UINT64_C(4102032192), // VST4LNq32_UPD
3842 UINT64_C(4093640783), // VST4d16
3843 UINT64_C(0), // VST4d16Pseudo
3844 UINT64_C(0), // VST4d16Pseudo_UPD
3845 UINT64_C(4093640768), // VST4d16_UPD
3846 UINT64_C(4093640847), // VST4d32
3847 UINT64_C(0), // VST4d32Pseudo
3848 UINT64_C(0), // VST4d32Pseudo_UPD
3849 UINT64_C(4093640832), // VST4d32_UPD
3850 UINT64_C(4093640719), // VST4d8
3851 UINT64_C(0), // VST4d8Pseudo
3852 UINT64_C(0), // VST4d8Pseudo_UPD
3853 UINT64_C(4093640704), // VST4d8_UPD
3854 UINT64_C(4093641039), // VST4q16
3855 UINT64_C(0), // VST4q16Pseudo_UPD
3856 UINT64_C(4093641024), // VST4q16_UPD
3857 UINT64_C(0), // VST4q16oddPseudo
3858 UINT64_C(0), // VST4q16oddPseudo_UPD
3859 UINT64_C(4093641103), // VST4q32
3860 UINT64_C(0), // VST4q32Pseudo_UPD
3861 UINT64_C(4093641088), // VST4q32_UPD
3862 UINT64_C(0), // VST4q32oddPseudo
3863 UINT64_C(0), // VST4q32oddPseudo_UPD
3864 UINT64_C(4093640975), // VST4q8
3865 UINT64_C(0), // VST4q8Pseudo_UPD
3866 UINT64_C(4093640960), // VST4q8_UPD
3867 UINT64_C(0), // VST4q8oddPseudo
3868 UINT64_C(0), // VST4q8oddPseudo_UPD
3869 UINT64_C(220203776), // VSTMDDB_UPD
3870 UINT64_C(209718016), // VSTMDIA
3871 UINT64_C(211815168), // VSTMDIA_UPD
3872 UINT64_C(0), // VSTMQIA
3873 UINT64_C(220203520), // VSTMSDB_UPD
3874 UINT64_C(209717760), // VSTMSIA
3875 UINT64_C(211814912), // VSTMSIA_UPD
3876 UINT64_C(218106624), // VSTRD
3877 UINT64_C(218106112), // VSTRH
3878 UINT64_C(218106368), // VSTRS
3879 UINT64_C(222351232), // VSTR_FPCXTNS_off
3880 UINT64_C(207671168), // VSTR_FPCXTNS_post
3881 UINT64_C(224448384), // VSTR_FPCXTNS_pre
3882 UINT64_C(222359424), // VSTR_FPCXTS_off
3883 UINT64_C(207679360), // VSTR_FPCXTS_post
3884 UINT64_C(224456576), // VSTR_FPCXTS_pre
3885 UINT64_C(218124160), // VSTR_FPSCR_NZCVQC_off
3886 UINT64_C(203444096), // VSTR_FPSCR_NZCVQC_post
3887 UINT64_C(220221312), // VSTR_FPSCR_NZCVQC_pre
3888 UINT64_C(218115968), // VSTR_FPSCR_off
3889 UINT64_C(203435904), // VSTR_FPSCR_post
3890 UINT64_C(220213120), // VSTR_FPSCR_pre
3891 UINT64_C(222343040), // VSTR_P0_off
3892 UINT64_C(207662976), // VSTR_P0_post
3893 UINT64_C(224440192), // VSTR_P0_pre
3894 UINT64_C(222334848), // VSTR_VPR_off
3895 UINT64_C(207654784), // VSTR_VPR_post
3896 UINT64_C(224432000), // VSTR_VPR_pre
3897 UINT64_C(238029632), // VSUBD
3898 UINT64_C(238029120), // VSUBH
3899 UINT64_C(4070573568), // VSUBHNv2i32
3900 UINT64_C(4069524992), // VSUBHNv4i16
3901 UINT64_C(4068476416), // VSUBHNv8i8
3902 UINT64_C(4070572544), // VSUBLsv2i64
3903 UINT64_C(4069523968), // VSUBLsv4i32
3904 UINT64_C(4068475392), // VSUBLsv8i16
3905 UINT64_C(4087349760), // VSUBLuv2i64
3906 UINT64_C(4086301184), // VSUBLuv4i32
3907 UINT64_C(4085252608), // VSUBLuv8i16
3908 UINT64_C(238029376), // VSUBS
3909 UINT64_C(4070572800), // VSUBWsv2i64
3910 UINT64_C(4069524224), // VSUBWsv4i32
3911 UINT64_C(4068475648), // VSUBWsv8i16
3912 UINT64_C(4087350016), // VSUBWuv2i64
3913 UINT64_C(4086301440), // VSUBWuv4i32
3914 UINT64_C(4085252864), // VSUBWuv8i16
3915 UINT64_C(4062186752), // VSUBfd
3916 UINT64_C(4062186816), // VSUBfq
3917 UINT64_C(4063235328), // VSUBhd
3918 UINT64_C(4063235392), // VSUBhq
3919 UINT64_C(4076865600), // VSUBv16i8
3920 UINT64_C(4080011264), // VSUBv1i64
3921 UINT64_C(4078962688), // VSUBv2i32
3922 UINT64_C(4080011328), // VSUBv2i64
3923 UINT64_C(4077914112), // VSUBv4i16
3924 UINT64_C(4078962752), // VSUBv4i32
3925 UINT64_C(4077914176), // VSUBv8i16
3926 UINT64_C(4076865536), // VSUBv8i8
3927 UINT64_C(4269804816), // VSUDOTDI
3928 UINT64_C(4269804880), // VSUDOTQI
3929 UINT64_C(4088528896), // VSWPd
3930 UINT64_C(4088528960), // VSWPq
3931 UINT64_C(4088399872), // VTBL1
3932 UINT64_C(4088400128), // VTBL2
3933 UINT64_C(4088400384), // VTBL3
3934 UINT64_C(0), // VTBL3Pseudo
3935 UINT64_C(4088400640), // VTBL4
3936 UINT64_C(0), // VTBL4Pseudo
3937 UINT64_C(4088399936), // VTBX1
3938 UINT64_C(4088400192), // VTBX2
3939 UINT64_C(4088400448), // VTBX3
3940 UINT64_C(0), // VTBX3Pseudo
3941 UINT64_C(4088400704), // VTBX4
3942 UINT64_C(0), // VTBX4Pseudo
3943 UINT64_C(247335744), // VTOSHD
3944 UINT64_C(247335232), // VTOSHH
3945 UINT64_C(247335488), // VTOSHS
3946 UINT64_C(247270208), // VTOSIRD
3947 UINT64_C(247269696), // VTOSIRH
3948 UINT64_C(247269952), // VTOSIRS
3949 UINT64_C(247270336), // VTOSIZD
3950 UINT64_C(247269824), // VTOSIZH
3951 UINT64_C(247270080), // VTOSIZS
3952 UINT64_C(247335872), // VTOSLD
3953 UINT64_C(247335360), // VTOSLH
3954 UINT64_C(247335616), // VTOSLS
3955 UINT64_C(247401280), // VTOUHD
3956 UINT64_C(247400768), // VTOUHH
3957 UINT64_C(247401024), // VTOUHS
3958 UINT64_C(247204672), // VTOUIRD
3959 UINT64_C(247204160), // VTOUIRH
3960 UINT64_C(247204416), // VTOUIRS
3961 UINT64_C(247204800), // VTOUIZD
3962 UINT64_C(247204288), // VTOUIZH
3963 UINT64_C(247204544), // VTOUIZS
3964 UINT64_C(247401408), // VTOULD
3965 UINT64_C(247400896), // VTOULH
3966 UINT64_C(247401152), // VTOULS
3967 UINT64_C(4088791168), // VTRNd16
3968 UINT64_C(4089053312), // VTRNd32
3969 UINT64_C(4088529024), // VTRNd8
3970 UINT64_C(4088791232), // VTRNq16
3971 UINT64_C(4089053376), // VTRNq32
3972 UINT64_C(4088529088), // VTRNq8
3973 UINT64_C(4060088400), // VTSTv16i8
3974 UINT64_C(4062185488), // VTSTv2i32
3975 UINT64_C(4061136912), // VTSTv4i16
3976 UINT64_C(4062185552), // VTSTv4i32
3977 UINT64_C(4061136976), // VTSTv8i16
3978 UINT64_C(4060088336), // VTSTv8i8
3979 UINT64_C(4229958928), // VUDOTD
3980 UINT64_C(4263513360), // VUDOTDI
3981 UINT64_C(4229958992), // VUDOTQ
3982 UINT64_C(4263513424), // VUDOTQI
3983 UINT64_C(247139136), // VUHTOD
3984 UINT64_C(247138624), // VUHTOH
3985 UINT64_C(247138880), // VUHTOS
3986 UINT64_C(246942528), // VUITOD
3987 UINT64_C(246942016), // VUITOH
3988 UINT64_C(246942272), // VUITOS
3989 UINT64_C(247139264), // VULTOD
3990 UINT64_C(247138752), // VULTOH
3991 UINT64_C(247139008), // VULTOS
3992 UINT64_C(4229958736), // VUMMLA
3993 UINT64_C(4238347520), // VUSDOTD
3994 UINT64_C(4269804800), // VUSDOTDI
3995 UINT64_C(4238347584), // VUSDOTQ
3996 UINT64_C(4269804864), // VUSDOTQI
3997 UINT64_C(4238347328), // VUSMMLA
3998 UINT64_C(4088791296), // VUZPd16
3999 UINT64_C(4088529152), // VUZPd8
4000 UINT64_C(4088791360), // VUZPq16
4001 UINT64_C(4089053504), // VUZPq32
4002 UINT64_C(4088529216), // VUZPq8
4003 UINT64_C(4088791424), // VZIPd16
4004 UINT64_C(4088529280), // VZIPd8
4005 UINT64_C(4088791488), // VZIPq16
4006 UINT64_C(4089053632), // VZIPq32
4007 UINT64_C(4088529344), // VZIPq8
4008 UINT64_C(139460608), // sysLDMDA
4009 UINT64_C(141557760), // sysLDMDA_UPD
4010 UINT64_C(156237824), // sysLDMDB
4011 UINT64_C(158334976), // sysLDMDB_UPD
4012 UINT64_C(147849216), // sysLDMIA
4013 UINT64_C(149946368), // sysLDMIA_UPD
4014 UINT64_C(164626432), // sysLDMIB
4015 UINT64_C(166723584), // sysLDMIB_UPD
4016 UINT64_C(138412032), // sysSTMDA
4017 UINT64_C(140509184), // sysSTMDA_UPD
4018 UINT64_C(155189248), // sysSTMDB
4019 UINT64_C(157286400), // sysSTMDB_UPD
4020 UINT64_C(146800640), // sysSTMIA
4021 UINT64_C(148897792), // sysSTMIA_UPD
4022 UINT64_C(163577856), // sysSTMIB
4023 UINT64_C(165675008), // sysSTMIB_UPD
4024 UINT64_C(4047503360), // t2ADCri
4025 UINT64_C(3946840064), // t2ADCrr
4026 UINT64_C(3946840064), // t2ADCrs
4027 UINT64_C(4043309056), // t2ADDri
4028 UINT64_C(4060086272), // t2ADDri12
4029 UINT64_C(3942645760), // t2ADDrr
4030 UINT64_C(3942645760), // t2ADDrs
4031 UINT64_C(4044164352), // t2ADDspImm
4032 UINT64_C(4060941568), // t2ADDspImm12
4033 UINT64_C(4061069312), // t2ADR
4034 UINT64_C(4026531840), // t2ANDri
4035 UINT64_C(3925868544), // t2ANDrr
4036 UINT64_C(3925868544), // t2ANDrs
4037 UINT64_C(3931045920), // t2ASRri
4038 UINT64_C(4198559744), // t2ASRrr
4039 UINT64_C(4088365101), // t2AUT
4040 UINT64_C(4216327936), // t2AUTG
4041 UINT64_C(4026568704), // t2B
4042 UINT64_C(4084137984), // t2BFC
4043 UINT64_C(4083154944), // t2BFI
4044 UINT64_C(4026580993), // t2BFLi
4045 UINT64_C(4033929217), // t2BFLr
4046 UINT64_C(4030783489), // t2BFi
4047 UINT64_C(4026589185), // t2BFic
4048 UINT64_C(4032880641), // t2BFr
4049 UINT64_C(4028628992), // t2BICri
4050 UINT64_C(3927965696), // t2BICrr
4051 UINT64_C(3927965696), // t2BICrs
4052 UINT64_C(4088365071), // t2BTI
4053 UINT64_C(4216327952), // t2BXAUT
4054 UINT64_C(4089483008), // t2BXJ
4055 UINT64_C(4026564608), // t2Bcc
4056 UINT64_C(3992977408), // t2CDP
4057 UINT64_C(4261412864), // t2CDP2
4058 UINT64_C(4089417519), // t2CLREX
4059 UINT64_C(3902734336), // t2CLRM
4060 UINT64_C(4205899904), // t2CLZ
4061 UINT64_C(4044361472), // t2CMNri
4062 UINT64_C(3943698176), // t2CMNzrr
4063 UINT64_C(3943698176), // t2CMNzrs
4064 UINT64_C(4054847232), // t2CMPri
4065 UINT64_C(3954183936), // t2CMPrr
4066 UINT64_C(3954183936), // t2CMPrs
4067 UINT64_C(4088365312), // t2CPS1p
4068 UINT64_C(4088365056), // t2CPS2p
4069 UINT64_C(4088365312), // t2CPS3p
4070 UINT64_C(4206948480), // t2CRC32B
4071 UINT64_C(4207997056), // t2CRC32CB
4072 UINT64_C(4207997072), // t2CRC32CH
4073 UINT64_C(4207997088), // t2CRC32CW
4074 UINT64_C(4206948496), // t2CRC32H
4075 UINT64_C(4206948512), // t2CRC32W
4076 UINT64_C(3931144192), // t2CSEL
4077 UINT64_C(3931148288), // t2CSINC
4078 UINT64_C(3931152384), // t2CSINV
4079 UINT64_C(3931156480), // t2CSNEG
4080 UINT64_C(4088365296), // t2DBG
4081 UINT64_C(4153376769), // t2DCPS1
4082 UINT64_C(4153376770), // t2DCPS2
4083 UINT64_C(4153376771), // t2DCPS3
4084 UINT64_C(4030783489), // t2DLS
4085 UINT64_C(4089417552), // t2DMB
4086 UINT64_C(4089417536), // t2DSB
4087 UINT64_C(4034920448), // t2EORri
4088 UINT64_C(3934257152), // t2EORrr
4089 UINT64_C(3934257152), // t2EORrs
4090 UINT64_C(4088365056), // t2HINT
4091 UINT64_C(4158685184), // t2HVC
4092 UINT64_C(4089417568), // t2ISB
4093 UINT64_C(48896), // t2IT
4094 UINT64_C(0), // t2Int_eh_sjlj_setjmp
4095 UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp
4096 UINT64_C(3905949615), // t2LDA
4097 UINT64_C(3905949583), // t2LDAB
4098 UINT64_C(3905949679), // t2LDAEX
4099 UINT64_C(3905949647), // t2LDAEXB
4100 UINT64_C(3905945855), // t2LDAEXD
4101 UINT64_C(3905949663), // t2LDAEXH
4102 UINT64_C(3905949599), // t2LDAH
4103 UINT64_C(4249878528), // t2LDC2L_OFFSET
4104 UINT64_C(4241489920), // t2LDC2L_OPTION
4105 UINT64_C(4235198464), // t2LDC2L_POST
4106 UINT64_C(4251975680), // t2LDC2L_PRE
4107 UINT64_C(4245684224), // t2LDC2_OFFSET
4108 UINT64_C(4237295616), // t2LDC2_OPTION
4109 UINT64_C(4231004160), // t2LDC2_POST
4110 UINT64_C(4247781376), // t2LDC2_PRE
4111 UINT64_C(3981443072), // t2LDCL_OFFSET
4112 UINT64_C(3973054464), // t2LDCL_OPTION
4113 UINT64_C(3966763008), // t2LDCL_POST
4114 UINT64_C(3983540224), // t2LDCL_PRE
4115 UINT64_C(3977248768), // t2LDC_OFFSET
4116 UINT64_C(3968860160), // t2LDC_OPTION
4117 UINT64_C(3962568704), // t2LDC_POST
4118 UINT64_C(3979345920), // t2LDC_PRE
4119 UINT64_C(3910139904), // t2LDMDB
4120 UINT64_C(3912237056), // t2LDMDB_UPD
4121 UINT64_C(3901751296), // t2LDMIA
4122 UINT64_C(3903848448), // t2LDMIA_UPD
4123 UINT64_C(4161801728), // t2LDRBT
4124 UINT64_C(4161800448), // t2LDRB_POST
4125 UINT64_C(4161801472), // t2LDRB_PRE
4126 UINT64_C(4170186752), // t2LDRBi12
4127 UINT64_C(4161801216), // t2LDRBi8
4128 UINT64_C(4162781184), // t2LDRBpci
4129 UINT64_C(4161798144), // t2LDRBs
4130 UINT64_C(3899654144), // t2LDRD_POST
4131 UINT64_C(3916431360), // t2LDRD_PRE
4132 UINT64_C(3914334208), // t2LDRDi8
4133 UINT64_C(3897560832), // t2LDREX
4134 UINT64_C(3905949519), // t2LDREXB
4135 UINT64_C(3905945727), // t2LDREXD
4136 UINT64_C(3905949535), // t2LDREXH
4137 UINT64_C(4163898880), // t2LDRHT
4138 UINT64_C(4163897600), // t2LDRH_POST
4139 UINT64_C(4163898624), // t2LDRH_PRE
4140 UINT64_C(4172283904), // t2LDRHi12
4141 UINT64_C(4163898368), // t2LDRHi8
4142 UINT64_C(4164878336), // t2LDRHpci
4143 UINT64_C(4163895296), // t2LDRHs
4144 UINT64_C(4178578944), // t2LDRSBT
4145 UINT64_C(4178577664), // t2LDRSB_POST
4146 UINT64_C(4178578688), // t2LDRSB_PRE
4147 UINT64_C(4186963968), // t2LDRSBi12
4148 UINT64_C(4178578432), // t2LDRSBi8
4149 UINT64_C(4179558400), // t2LDRSBpci
4150 UINT64_C(4178575360), // t2LDRSBs
4151 UINT64_C(4180676096), // t2LDRSHT
4152 UINT64_C(4180674816), // t2LDRSH_POST
4153 UINT64_C(4180675840), // t2LDRSH_PRE
4154 UINT64_C(4189061120), // t2LDRSHi12
4155 UINT64_C(4180675584), // t2LDRSHi8
4156 UINT64_C(4181655552), // t2LDRSHpci
4157 UINT64_C(4180672512), // t2LDRSHs
4158 UINT64_C(4165996032), // t2LDRT
4159 UINT64_C(4165994752), // t2LDR_POST
4160 UINT64_C(4165995776), // t2LDR_PRE
4161 UINT64_C(4174381056), // t2LDRi12
4162 UINT64_C(4165995520), // t2LDRi8
4163 UINT64_C(4166975488), // t2LDRpci
4164 UINT64_C(4165992448), // t2LDRs
4165 UINT64_C(4029661185), // t2LE
4166 UINT64_C(4027564033), // t2LEUpdate
4167 UINT64_C(3931045888), // t2LSLri
4168 UINT64_C(4194365440), // t2LSLrr
4169 UINT64_C(3931045904), // t2LSRri
4170 UINT64_C(4196462592), // t2LSRrr
4171 UINT64_C(3992977424), // t2MCR
4172 UINT64_C(4261412880), // t2MCR2
4173 UINT64_C(3963617280), // t2MCRR
4174 UINT64_C(4232052736), // t2MCRR2
4175 UINT64_C(4211081216), // t2MLA
4176 UINT64_C(4211081232), // t2MLS
4177 UINT64_C(4072669184), // t2MOVTi16
4178 UINT64_C(4031709184), // t2MOVi
4179 UINT64_C(4064280576), // t2MOVi16
4180 UINT64_C(3931045888), // t2MOVr
4181 UINT64_C(3932094560), // t2MOVsra_glue
4182 UINT64_C(3932094544), // t2MOVsrl_glue
4183 UINT64_C(3994026000), // t2MRC
4184 UINT64_C(4262461456), // t2MRC2
4185 UINT64_C(3964665856), // t2MRRC
4186 UINT64_C(4233101312), // t2MRRC2
4187 UINT64_C(4092559360), // t2MRS_AR
4188 UINT64_C(4092559360), // t2MRS_M
4189 UINT64_C(4091576352), // t2MRSbanked
4190 UINT64_C(4093607936), // t2MRSsys_AR
4191 UINT64_C(4085284864), // t2MSR_AR
4192 UINT64_C(4085284864), // t2MSR_M
4193 UINT64_C(4085284896), // t2MSRbanked
4194 UINT64_C(4211142656), // t2MUL
4195 UINT64_C(4033806336), // t2MVNi
4196 UINT64_C(3933143040), // t2MVNr
4197 UINT64_C(3933143040), // t2MVNs
4198 UINT64_C(4032823296), // t2ORNri
4199 UINT64_C(3932160000), // t2ORNrr
4200 UINT64_C(3932160000), // t2ORNrs
4201 UINT64_C(4030726144), // t2ORRri
4202 UINT64_C(3930062848), // t2ORRrr
4203 UINT64_C(3930062848), // t2ORRrs
4204 UINT64_C(4088365085), // t2PAC
4205 UINT64_C(4088365069), // t2PACBTI
4206 UINT64_C(4217434112), // t2PACG
4207 UINT64_C(3938451456), // t2PKHBT
4208 UINT64_C(3938451488), // t2PKHTB
4209 UINT64_C(4172345344), // t2PLDWi12
4210 UINT64_C(4163959808), // t2PLDWi8
4211 UINT64_C(4163956736), // t2PLDWs
4212 UINT64_C(4170248192), // t2PLDi12
4213 UINT64_C(4161862656), // t2PLDi8
4214 UINT64_C(4162842624), // t2PLDpci
4215 UINT64_C(4161859584), // t2PLDs
4216 UINT64_C(4187025408), // t2PLIi12
4217 UINT64_C(4178639872), // t2PLIi8
4218 UINT64_C(4179619840), // t2PLIpci
4219 UINT64_C(4178636800), // t2PLIs
4220 UINT64_C(4202754176), // t2QADD
4221 UINT64_C(4203802640), // t2QADD16
4222 UINT64_C(4202754064), // t2QADD8
4223 UINT64_C(4204851216), // t2QASX
4224 UINT64_C(4202754192), // t2QDADD
4225 UINT64_C(4202754224), // t2QDSUB
4226 UINT64_C(4209045520), // t2QSAX
4227 UINT64_C(4202754208), // t2QSUB
4228 UINT64_C(4207996944), // t2QSUB16
4229 UINT64_C(4206948368), // t2QSUB8
4230 UINT64_C(4203802784), // t2RBIT
4231 UINT64_C(4203802752), // t2REV
4232 UINT64_C(4203802768), // t2REV16
4233 UINT64_C(4203802800), // t2REVSH
4234 UINT64_C(3893411840), // t2RFEDB
4235 UINT64_C(3895508992), // t2RFEDBW
4236 UINT64_C(3918577664), // t2RFEIA
4237 UINT64_C(3920674816), // t2RFEIAW
4238 UINT64_C(3931045936), // t2RORri
4239 UINT64_C(4200656896), // t2RORrr
4240 UINT64_C(3931045936), // t2RRX
4241 UINT64_C(4055891968), // t2RSBri
4242 UINT64_C(3955228672), // t2RSBrr
4243 UINT64_C(3955228672), // t2RSBrs
4244 UINT64_C(4203802624), // t2SADD16
4245 UINT64_C(4202754048), // t2SADD8
4246 UINT64_C(4204851200), // t2SASX
4247 UINT64_C(4089417584), // t2SB
4248 UINT64_C(4049600512), // t2SBCri
4249 UINT64_C(3948937216), // t2SBCrr
4250 UINT64_C(3948937216), // t2SBCrs
4251 UINT64_C(4081057792), // t2SBFX
4252 UINT64_C(4220580080), // t2SDIV
4253 UINT64_C(4204851328), // t2SEL
4254 UINT64_C(46608), // t2SETPAN
4255 UINT64_C(3917474175), // t2SG
4256 UINT64_C(4203802656), // t2SHADD16
4257 UINT64_C(4202754080), // t2SHADD8
4258 UINT64_C(4204851232), // t2SHASX
4259 UINT64_C(4209045536), // t2SHSAX
4260 UINT64_C(4207996960), // t2SHSUB16
4261 UINT64_C(4206948384), // t2SHSUB8
4262 UINT64_C(4159733760), // t2SMC
4263 UINT64_C(4212129792), // t2SMLABB
4264 UINT64_C(4212129808), // t2SMLABT
4265 UINT64_C(4213178368), // t2SMLAD
4266 UINT64_C(4213178384), // t2SMLADX
4267 UINT64_C(4223664128), // t2SMLAL
4268 UINT64_C(4223664256), // t2SMLALBB
4269 UINT64_C(4223664272), // t2SMLALBT
4270 UINT64_C(4223664320), // t2SMLALD
4271 UINT64_C(4223664336), // t2SMLALDX
4272 UINT64_C(4223664288), // t2SMLALTB
4273 UINT64_C(4223664304), // t2SMLALTT
4274 UINT64_C(4212129824), // t2SMLATB
4275 UINT64_C(4212129840), // t2SMLATT
4276 UINT64_C(4214226944), // t2SMLAWB
4277 UINT64_C(4214226960), // t2SMLAWT
4278 UINT64_C(4215275520), // t2SMLSD
4279 UINT64_C(4215275536), // t2SMLSDX
4280 UINT64_C(4224712896), // t2SMLSLD
4281 UINT64_C(4224712912), // t2SMLSLDX
4282 UINT64_C(4216324096), // t2SMMLA
4283 UINT64_C(4216324112), // t2SMMLAR
4284 UINT64_C(4217372672), // t2SMMLS
4285 UINT64_C(4217372688), // t2SMMLSR
4286 UINT64_C(4216385536), // t2SMMUL
4287 UINT64_C(4216385552), // t2SMMULR
4288 UINT64_C(4213239808), // t2SMUAD
4289 UINT64_C(4213239824), // t2SMUADX
4290 UINT64_C(4212191232), // t2SMULBB
4291 UINT64_C(4212191248), // t2SMULBT
4292 UINT64_C(4219469824), // t2SMULL
4293 UINT64_C(4212191264), // t2SMULTB
4294 UINT64_C(4212191280), // t2SMULTT
4295 UINT64_C(4214288384), // t2SMULWB
4296 UINT64_C(4214288400), // t2SMULWT
4297 UINT64_C(4215336960), // t2SMUSD
4298 UINT64_C(4215336976), // t2SMUSDX
4299 UINT64_C(3893215232), // t2SRSDB
4300 UINT64_C(3895312384), // t2SRSDB_UPD
4301 UINT64_C(3918381056), // t2SRSIA
4302 UINT64_C(3920478208), // t2SRSIA_UPD
4303 UINT64_C(4076863488), // t2SSAT
4304 UINT64_C(4078960640), // t2SSAT16
4305 UINT64_C(4209045504), // t2SSAX
4306 UINT64_C(4207996928), // t2SSUB16
4307 UINT64_C(4206948352), // t2SSUB8
4308 UINT64_C(4248829952), // t2STC2L_OFFSET
4309 UINT64_C(4240441344), // t2STC2L_OPTION
4310 UINT64_C(4234149888), // t2STC2L_POST
4311 UINT64_C(4250927104), // t2STC2L_PRE
4312 UINT64_C(4244635648), // t2STC2_OFFSET
4313 UINT64_C(4236247040), // t2STC2_OPTION
4314 UINT64_C(4229955584), // t2STC2_POST
4315 UINT64_C(4246732800), // t2STC2_PRE
4316 UINT64_C(3980394496), // t2STCL_OFFSET
4317 UINT64_C(3972005888), // t2STCL_OPTION
4318 UINT64_C(3965714432), // t2STCL_POST
4319 UINT64_C(3982491648), // t2STCL_PRE
4320 UINT64_C(3976200192), // t2STC_OFFSET
4321 UINT64_C(3967811584), // t2STC_OPTION
4322 UINT64_C(3961520128), // t2STC_POST
4323 UINT64_C(3978297344), // t2STC_PRE
4324 UINT64_C(3904901039), // t2STL
4325 UINT64_C(3904901007), // t2STLB
4326 UINT64_C(3904901088), // t2STLEX
4327 UINT64_C(3904901056), // t2STLEXB
4328 UINT64_C(3904897264), // t2STLEXD
4329 UINT64_C(3904901072), // t2STLEXH
4330 UINT64_C(3904901023), // t2STLH
4331 UINT64_C(3909091328), // t2STMDB
4332 UINT64_C(3911188480), // t2STMDB_UPD
4333 UINT64_C(3900702720), // t2STMIA
4334 UINT64_C(3902799872), // t2STMIA_UPD
4335 UINT64_C(4160753152), // t2STRBT
4336 UINT64_C(4160751872), // t2STRB_POST
4337 UINT64_C(4160752896), // t2STRB_PRE
4338 UINT64_C(4169138176), // t2STRBi12
4339 UINT64_C(4160752640), // t2STRBi8
4340 UINT64_C(4160749568), // t2STRBs
4341 UINT64_C(3898605568), // t2STRD_POST
4342 UINT64_C(3915382784), // t2STRD_PRE
4343 UINT64_C(3913285632), // t2STRDi8
4344 UINT64_C(3896508416), // t2STREX
4345 UINT64_C(3904900928), // t2STREXB
4346 UINT64_C(3904897136), // t2STREXD
4347 UINT64_C(3904900944), // t2STREXH
4348 UINT64_C(4162850304), // t2STRHT
4349 UINT64_C(4162849024), // t2STRH_POST
4350 UINT64_C(4162850048), // t2STRH_PRE
4351 UINT64_C(4171235328), // t2STRHi12
4352 UINT64_C(4162849792), // t2STRHi8
4353 UINT64_C(4162846720), // t2STRHs
4354 UINT64_C(4164947456), // t2STRT
4355 UINT64_C(4164946176), // t2STR_POST
4356 UINT64_C(4164947200), // t2STR_PRE
4357 UINT64_C(4173332480), // t2STRi12
4358 UINT64_C(4164946944), // t2STRi8
4359 UINT64_C(4164943872), // t2STRs
4360 UINT64_C(4091449088), // t2SUBS_PC_LR
4361 UINT64_C(4053794816), // t2SUBri
4362 UINT64_C(4070572032), // t2SUBri12
4363 UINT64_C(3953131520), // t2SUBrr
4364 UINT64_C(3953131520), // t2SUBrs
4365 UINT64_C(4054650112), // t2SUBspImm
4366 UINT64_C(4071427328), // t2SUBspImm12
4367 UINT64_C(4198559872), // t2SXTAB
4368 UINT64_C(4196462720), // t2SXTAB16
4369 UINT64_C(4194365568), // t2SXTAH
4370 UINT64_C(4199542912), // t2SXTB
4371 UINT64_C(4197445760), // t2SXTB16
4372 UINT64_C(4195348608), // t2SXTH
4373 UINT64_C(3906007040), // t2TBB
4374 UINT64_C(3906007056), // t2TBH
4375 UINT64_C(4035972864), // t2TEQri
4376 UINT64_C(3935309568), // t2TEQrr
4377 UINT64_C(3935309568), // t2TEQrs
4378 UINT64_C(4088365074), // t2TSB
4379 UINT64_C(4027584256), // t2TSTri
4380 UINT64_C(3926920960), // t2TSTrr
4381 UINT64_C(3926920960), // t2TSTrs
4382 UINT64_C(3896569856), // t2TT
4383 UINT64_C(3896569984), // t2TTA
4384 UINT64_C(3896570048), // t2TTAT
4385 UINT64_C(3896569920), // t2TTT
4386 UINT64_C(4203802688), // t2UADD16
4387 UINT64_C(4202754112), // t2UADD8
4388 UINT64_C(4204851264), // t2UASX
4389 UINT64_C(4089446400), // t2UBFX
4390 UINT64_C(4159741952), // t2UDF
4391 UINT64_C(4222677232), // t2UDIV
4392 UINT64_C(4203802720), // t2UHADD16
4393 UINT64_C(4202754144), // t2UHADD8
4394 UINT64_C(4204851296), // t2UHASX
4395 UINT64_C(4209045600), // t2UHSAX
4396 UINT64_C(4207997024), // t2UHSUB16
4397 UINT64_C(4206948448), // t2UHSUB8
4398 UINT64_C(4225761376), // t2UMAAL
4399 UINT64_C(4225761280), // t2UMLAL
4400 UINT64_C(4221566976), // t2UMULL
4401 UINT64_C(4203802704), // t2UQADD16
4402 UINT64_C(4202754128), // t2UQADD8
4403 UINT64_C(4204851280), // t2UQASX
4404 UINT64_C(4209045584), // t2UQSAX
4405 UINT64_C(4207997008), // t2UQSUB16
4406 UINT64_C(4206948432), // t2UQSUB8
4407 UINT64_C(4218482688), // t2USAD8
4408 UINT64_C(4218421248), // t2USADA8
4409 UINT64_C(4085252096), // t2USAT
4410 UINT64_C(4087349248), // t2USAT16
4411 UINT64_C(4209045568), // t2USAX
4412 UINT64_C(4207996992), // t2USUB16
4413 UINT64_C(4206948416), // t2USUB8
4414 UINT64_C(4199608448), // t2UXTAB
4415 UINT64_C(4197511296), // t2UXTAB16
4416 UINT64_C(4195414144), // t2UXTAH
4417 UINT64_C(4200591488), // t2UXTB
4418 UINT64_C(4198494336), // t2UXTB16
4419 UINT64_C(4196397184), // t2UXTH
4420 UINT64_C(4030775297), // t2WLS
4421 UINT64_C(16704), // tADC
4422 UINT64_C(17408), // tADDhirr
4423 UINT64_C(7168), // tADDi3
4424 UINT64_C(12288), // tADDi8
4425 UINT64_C(17512), // tADDrSP
4426 UINT64_C(43008), // tADDrSPi
4427 UINT64_C(6144), // tADDrr
4428 UINT64_C(45056), // tADDspi
4429 UINT64_C(17541), // tADDspr
4430 UINT64_C(40960), // tADR
4431 UINT64_C(16384), // tAND
4432 UINT64_C(4096), // tASRri
4433 UINT64_C(16640), // tASRrr
4434 UINT64_C(57344), // tB
4435 UINT64_C(17280), // tBIC
4436 UINT64_C(48640), // tBKPT
4437 UINT64_C(4026585088), // tBL
4438 UINT64_C(18308), // tBLXNSr
4439 UINT64_C(4026580992), // tBLXi
4440 UINT64_C(18304), // tBLXr
4441 UINT64_C(18176), // tBX
4442 UINT64_C(18180), // tBXNS
4443 UINT64_C(53248), // tBcc
4444 UINT64_C(47360), // tCBNZ
4445 UINT64_C(45312), // tCBZ
4446 UINT64_C(17088), // tCMNz
4447 UINT64_C(17664), // tCMPhir
4448 UINT64_C(10240), // tCMPi8
4449 UINT64_C(17024), // tCMPr
4450 UINT64_C(46688), // tCPS
4451 UINT64_C(16448), // tEOR
4452 UINT64_C(48896), // tHINT
4453 UINT64_C(47744), // tHLT
4454 UINT64_C(0), // tInt_WIN_eh_sjlj_longjmp
4455 UINT64_C(0), // tInt_eh_sjlj_longjmp
4456 UINT64_C(0), // tInt_eh_sjlj_setjmp
4457 UINT64_C(51200), // tLDMIA
4458 UINT64_C(30720), // tLDRBi
4459 UINT64_C(23552), // tLDRBr
4460 UINT64_C(34816), // tLDRHi
4461 UINT64_C(23040), // tLDRHr
4462 UINT64_C(22016), // tLDRSB
4463 UINT64_C(24064), // tLDRSH
4464 UINT64_C(26624), // tLDRi
4465 UINT64_C(18432), // tLDRpci
4466 UINT64_C(22528), // tLDRr
4467 UINT64_C(38912), // tLDRspi
4468 UINT64_C(0), // tLSLri
4469 UINT64_C(16512), // tLSLrr
4470 UINT64_C(2048), // tLSRri
4471 UINT64_C(16576), // tLSRrr
4472 UINT64_C(0), // tMOVSr
4473 UINT64_C(8192), // tMOVi8
4474 UINT64_C(17920), // tMOVr
4475 UINT64_C(17216), // tMUL
4476 UINT64_C(17344), // tMVN
4477 UINT64_C(17152), // tORR
4478 UINT64_C(17528), // tPICADD
4479 UINT64_C(48128), // tPOP
4480 UINT64_C(46080), // tPUSH
4481 UINT64_C(47616), // tREV
4482 UINT64_C(47680), // tREV16
4483 UINT64_C(47808), // tREVSH
4484 UINT64_C(16832), // tROR
4485 UINT64_C(16960), // tRSB
4486 UINT64_C(16768), // tSBC
4487 UINT64_C(46672), // tSETEND
4488 UINT64_C(49152), // tSTMIA_UPD
4489 UINT64_C(28672), // tSTRBi
4490 UINT64_C(21504), // tSTRBr
4491 UINT64_C(32768), // tSTRHi
4492 UINT64_C(20992), // tSTRHr
4493 UINT64_C(24576), // tSTRi
4494 UINT64_C(20480), // tSTRr
4495 UINT64_C(36864), // tSTRspi
4496 UINT64_C(7680), // tSUBi3
4497 UINT64_C(14336), // tSUBi8
4498 UINT64_C(6656), // tSUBrr
4499 UINT64_C(45184), // tSUBspi
4500 UINT64_C(57088), // tSVC
4501 UINT64_C(45632), // tSXTB
4502 UINT64_C(45568), // tSXTH
4503 UINT64_C(57086), // tTRAP
4504 UINT64_C(16896), // tTST
4505 UINT64_C(56832), // tUDF
4506 UINT64_C(45760), // tUXTB
4507 UINT64_C(45696), // tUXTH
4508 UINT64_C(57081), // t__brkdiv0
4509 UINT64_C(0)
4510 };
4511 const unsigned opcode = MI.getOpcode();
4512 uint64_t Value = InstBits[opcode];
4513 uint64_t op = 0;
4514 (void)op; // suppress warning
4515 switch (opcode) {
4516 case ARM::CLREX:
4517 case ARM::MVE_LCTP:
4518 case ARM::MVE_VPNOT:
4519 case ARM::SB:
4520 case ARM::TRAP:
4521 case ARM::TRAPNaCl:
4522 case ARM::TSB:
4523 case ARM::VBSPd:
4524 case ARM::VBSPq:
4525 case ARM::VLD1LNq8Pseudo:
4526 case ARM::VLD1LNq8Pseudo_UPD:
4527 case ARM::VLD1LNq16Pseudo:
4528 case ARM::VLD1LNq16Pseudo_UPD:
4529 case ARM::VLD1LNq32Pseudo:
4530 case ARM::VLD1LNq32Pseudo_UPD:
4531 case ARM::VLD1d8QPseudo:
4532 case ARM::VLD1d8QPseudoWB_fixed:
4533 case ARM::VLD1d8QPseudoWB_register:
4534 case ARM::VLD1d8TPseudo:
4535 case ARM::VLD1d8TPseudoWB_fixed:
4536 case ARM::VLD1d8TPseudoWB_register:
4537 case ARM::VLD1d16QPseudo:
4538 case ARM::VLD1d16QPseudoWB_fixed:
4539 case ARM::VLD1d16QPseudoWB_register:
4540 case ARM::VLD1d16TPseudo:
4541 case ARM::VLD1d16TPseudoWB_fixed:
4542 case ARM::VLD1d16TPseudoWB_register:
4543 case ARM::VLD1d32QPseudo:
4544 case ARM::VLD1d32QPseudoWB_fixed:
4545 case ARM::VLD1d32QPseudoWB_register:
4546 case ARM::VLD1d32TPseudo:
4547 case ARM::VLD1d32TPseudoWB_fixed:
4548 case ARM::VLD1d32TPseudoWB_register:
4549 case ARM::VLD1d64QPseudo:
4550 case ARM::VLD1d64QPseudoWB_fixed:
4551 case ARM::VLD1d64QPseudoWB_register:
4552 case ARM::VLD1d64TPseudo:
4553 case ARM::VLD1d64TPseudoWB_fixed:
4554 case ARM::VLD1d64TPseudoWB_register:
4555 case ARM::VLD1q8HighQPseudo:
4556 case ARM::VLD1q8HighQPseudo_UPD:
4557 case ARM::VLD1q8HighTPseudo:
4558 case ARM::VLD1q8HighTPseudo_UPD:
4559 case ARM::VLD1q8LowQPseudo_UPD:
4560 case ARM::VLD1q8LowTPseudo_UPD:
4561 case ARM::VLD1q16HighQPseudo:
4562 case ARM::VLD1q16HighQPseudo_UPD:
4563 case ARM::VLD1q16HighTPseudo:
4564 case ARM::VLD1q16HighTPseudo_UPD:
4565 case ARM::VLD1q16LowQPseudo_UPD:
4566 case ARM::VLD1q16LowTPseudo_UPD:
4567 case ARM::VLD1q32HighQPseudo:
4568 case ARM::VLD1q32HighQPseudo_UPD:
4569 case ARM::VLD1q32HighTPseudo:
4570 case ARM::VLD1q32HighTPseudo_UPD:
4571 case ARM::VLD1q32LowQPseudo_UPD:
4572 case ARM::VLD1q32LowTPseudo_UPD:
4573 case ARM::VLD1q64HighQPseudo:
4574 case ARM::VLD1q64HighQPseudo_UPD:
4575 case ARM::VLD1q64HighTPseudo:
4576 case ARM::VLD1q64HighTPseudo_UPD:
4577 case ARM::VLD1q64LowQPseudo_UPD:
4578 case ARM::VLD1q64LowTPseudo_UPD:
4579 case ARM::VLD2DUPq8EvenPseudo:
4580 case ARM::VLD2DUPq8OddPseudo:
4581 case ARM::VLD2DUPq8OddPseudoWB_fixed:
4582 case ARM::VLD2DUPq8OddPseudoWB_register:
4583 case ARM::VLD2DUPq16EvenPseudo:
4584 case ARM::VLD2DUPq16OddPseudo:
4585 case ARM::VLD2DUPq16OddPseudoWB_fixed:
4586 case ARM::VLD2DUPq16OddPseudoWB_register:
4587 case ARM::VLD2DUPq32EvenPseudo:
4588 case ARM::VLD2DUPq32OddPseudo:
4589 case ARM::VLD2DUPq32OddPseudoWB_fixed:
4590 case ARM::VLD2DUPq32OddPseudoWB_register:
4591 case ARM::VLD2LNd8Pseudo:
4592 case ARM::VLD2LNd8Pseudo_UPD:
4593 case ARM::VLD2LNd16Pseudo:
4594 case ARM::VLD2LNd16Pseudo_UPD:
4595 case ARM::VLD2LNd32Pseudo:
4596 case ARM::VLD2LNd32Pseudo_UPD:
4597 case ARM::VLD2LNq16Pseudo:
4598 case ARM::VLD2LNq16Pseudo_UPD:
4599 case ARM::VLD2LNq32Pseudo:
4600 case ARM::VLD2LNq32Pseudo_UPD:
4601 case ARM::VLD2q8Pseudo:
4602 case ARM::VLD2q8PseudoWB_fixed:
4603 case ARM::VLD2q8PseudoWB_register:
4604 case ARM::VLD2q16Pseudo:
4605 case ARM::VLD2q16PseudoWB_fixed:
4606 case ARM::VLD2q16PseudoWB_register:
4607 case ARM::VLD2q32Pseudo:
4608 case ARM::VLD2q32PseudoWB_fixed:
4609 case ARM::VLD2q32PseudoWB_register:
4610 case ARM::VLD3DUPd8Pseudo:
4611 case ARM::VLD3DUPd8Pseudo_UPD:
4612 case ARM::VLD3DUPd16Pseudo:
4613 case ARM::VLD3DUPd16Pseudo_UPD:
4614 case ARM::VLD3DUPd32Pseudo:
4615 case ARM::VLD3DUPd32Pseudo_UPD:
4616 case ARM::VLD3DUPq8EvenPseudo:
4617 case ARM::VLD3DUPq8OddPseudo:
4618 case ARM::VLD3DUPq8OddPseudo_UPD:
4619 case ARM::VLD3DUPq16EvenPseudo:
4620 case ARM::VLD3DUPq16OddPseudo:
4621 case ARM::VLD3DUPq16OddPseudo_UPD:
4622 case ARM::VLD3DUPq32EvenPseudo:
4623 case ARM::VLD3DUPq32OddPseudo:
4624 case ARM::VLD3DUPq32OddPseudo_UPD:
4625 case ARM::VLD3LNd8Pseudo:
4626 case ARM::VLD3LNd8Pseudo_UPD:
4627 case ARM::VLD3LNd16Pseudo:
4628 case ARM::VLD3LNd16Pseudo_UPD:
4629 case ARM::VLD3LNd32Pseudo:
4630 case ARM::VLD3LNd32Pseudo_UPD:
4631 case ARM::VLD3LNq16Pseudo:
4632 case ARM::VLD3LNq16Pseudo_UPD:
4633 case ARM::VLD3LNq32Pseudo:
4634 case ARM::VLD3LNq32Pseudo_UPD:
4635 case ARM::VLD3d8Pseudo:
4636 case ARM::VLD3d8Pseudo_UPD:
4637 case ARM::VLD3d16Pseudo:
4638 case ARM::VLD3d16Pseudo_UPD:
4639 case ARM::VLD3d32Pseudo:
4640 case ARM::VLD3d32Pseudo_UPD:
4641 case ARM::VLD3q8Pseudo_UPD:
4642 case ARM::VLD3q8oddPseudo:
4643 case ARM::VLD3q8oddPseudo_UPD:
4644 case ARM::VLD3q16Pseudo_UPD:
4645 case ARM::VLD3q16oddPseudo:
4646 case ARM::VLD3q16oddPseudo_UPD:
4647 case ARM::VLD3q32Pseudo_UPD:
4648 case ARM::VLD3q32oddPseudo:
4649 case ARM::VLD3q32oddPseudo_UPD:
4650 case ARM::VLD4DUPd8Pseudo:
4651 case ARM::VLD4DUPd8Pseudo_UPD:
4652 case ARM::VLD4DUPd16Pseudo:
4653 case ARM::VLD4DUPd16Pseudo_UPD:
4654 case ARM::VLD4DUPd32Pseudo:
4655 case ARM::VLD4DUPd32Pseudo_UPD:
4656 case ARM::VLD4DUPq8EvenPseudo:
4657 case ARM::VLD4DUPq8OddPseudo:
4658 case ARM::VLD4DUPq8OddPseudo_UPD:
4659 case ARM::VLD4DUPq16EvenPseudo:
4660 case ARM::VLD4DUPq16OddPseudo:
4661 case ARM::VLD4DUPq16OddPseudo_UPD:
4662 case ARM::VLD4DUPq32EvenPseudo:
4663 case ARM::VLD4DUPq32OddPseudo:
4664 case ARM::VLD4DUPq32OddPseudo_UPD:
4665 case ARM::VLD4LNd8Pseudo:
4666 case ARM::VLD4LNd8Pseudo_UPD:
4667 case ARM::VLD4LNd16Pseudo:
4668 case ARM::VLD4LNd16Pseudo_UPD:
4669 case ARM::VLD4LNd32Pseudo:
4670 case ARM::VLD4LNd32Pseudo_UPD:
4671 case ARM::VLD4LNq16Pseudo:
4672 case ARM::VLD4LNq16Pseudo_UPD:
4673 case ARM::VLD4LNq32Pseudo:
4674 case ARM::VLD4LNq32Pseudo_UPD:
4675 case ARM::VLD4d8Pseudo:
4676 case ARM::VLD4d8Pseudo_UPD:
4677 case ARM::VLD4d16Pseudo:
4678 case ARM::VLD4d16Pseudo_UPD:
4679 case ARM::VLD4d32Pseudo:
4680 case ARM::VLD4d32Pseudo_UPD:
4681 case ARM::VLD4q8Pseudo_UPD:
4682 case ARM::VLD4q8oddPseudo:
4683 case ARM::VLD4q8oddPseudo_UPD:
4684 case ARM::VLD4q16Pseudo_UPD:
4685 case ARM::VLD4q16oddPseudo:
4686 case ARM::VLD4q16oddPseudo_UPD:
4687 case ARM::VLD4q32Pseudo_UPD:
4688 case ARM::VLD4q32oddPseudo:
4689 case ARM::VLD4q32oddPseudo_UPD:
4690 case ARM::VLDMQIA:
4691 case ARM::VST1LNq8Pseudo:
4692 case ARM::VST1LNq8Pseudo_UPD:
4693 case ARM::VST1LNq16Pseudo:
4694 case ARM::VST1LNq16Pseudo_UPD:
4695 case ARM::VST1LNq32Pseudo:
4696 case ARM::VST1LNq32Pseudo_UPD:
4697 case ARM::VST1d8QPseudo:
4698 case ARM::VST1d8QPseudoWB_fixed:
4699 case ARM::VST1d8QPseudoWB_register:
4700 case ARM::VST1d8TPseudo:
4701 case ARM::VST1d8TPseudoWB_fixed:
4702 case ARM::VST1d8TPseudoWB_register:
4703 case ARM::VST1d16QPseudo:
4704 case ARM::VST1d16QPseudoWB_fixed:
4705 case ARM::VST1d16QPseudoWB_register:
4706 case ARM::VST1d16TPseudo:
4707 case ARM::VST1d16TPseudoWB_fixed:
4708 case ARM::VST1d16TPseudoWB_register:
4709 case ARM::VST1d32QPseudo:
4710 case ARM::VST1d32QPseudoWB_fixed:
4711 case ARM::VST1d32QPseudoWB_register:
4712 case ARM::VST1d32TPseudo:
4713 case ARM::VST1d32TPseudoWB_fixed:
4714 case ARM::VST1d32TPseudoWB_register:
4715 case ARM::VST1d64QPseudo:
4716 case ARM::VST1d64QPseudoWB_fixed:
4717 case ARM::VST1d64QPseudoWB_register:
4718 case ARM::VST1d64TPseudo:
4719 case ARM::VST1d64TPseudoWB_fixed:
4720 case ARM::VST1d64TPseudoWB_register:
4721 case ARM::VST1q8HighQPseudo:
4722 case ARM::VST1q8HighQPseudo_UPD:
4723 case ARM::VST1q8HighTPseudo:
4724 case ARM::VST1q8HighTPseudo_UPD:
4725 case ARM::VST1q8LowQPseudo_UPD:
4726 case ARM::VST1q8LowTPseudo_UPD:
4727 case ARM::VST1q16HighQPseudo:
4728 case ARM::VST1q16HighQPseudo_UPD:
4729 case ARM::VST1q16HighTPseudo:
4730 case ARM::VST1q16HighTPseudo_UPD:
4731 case ARM::VST1q16LowQPseudo_UPD:
4732 case ARM::VST1q16LowTPseudo_UPD:
4733 case ARM::VST1q32HighQPseudo:
4734 case ARM::VST1q32HighQPseudo_UPD:
4735 case ARM::VST1q32HighTPseudo:
4736 case ARM::VST1q32HighTPseudo_UPD:
4737 case ARM::VST1q32LowQPseudo_UPD:
4738 case ARM::VST1q32LowTPseudo_UPD:
4739 case ARM::VST1q64HighQPseudo:
4740 case ARM::VST1q64HighQPseudo_UPD:
4741 case ARM::VST1q64HighTPseudo:
4742 case ARM::VST1q64HighTPseudo_UPD:
4743 case ARM::VST1q64LowQPseudo_UPD:
4744 case ARM::VST1q64LowTPseudo_UPD:
4745 case ARM::VST2LNd8Pseudo:
4746 case ARM::VST2LNd8Pseudo_UPD:
4747 case ARM::VST2LNd16Pseudo:
4748 case ARM::VST2LNd16Pseudo_UPD:
4749 case ARM::VST2LNd32Pseudo:
4750 case ARM::VST2LNd32Pseudo_UPD:
4751 case ARM::VST2LNq16Pseudo:
4752 case ARM::VST2LNq16Pseudo_UPD:
4753 case ARM::VST2LNq32Pseudo:
4754 case ARM::VST2LNq32Pseudo_UPD:
4755 case ARM::VST2q8Pseudo:
4756 case ARM::VST2q8PseudoWB_fixed:
4757 case ARM::VST2q8PseudoWB_register:
4758 case ARM::VST2q16Pseudo:
4759 case ARM::VST2q16PseudoWB_fixed:
4760 case ARM::VST2q16PseudoWB_register:
4761 case ARM::VST2q32Pseudo:
4762 case ARM::VST2q32PseudoWB_fixed:
4763 case ARM::VST2q32PseudoWB_register:
4764 case ARM::VST3LNd8Pseudo:
4765 case ARM::VST3LNd8Pseudo_UPD:
4766 case ARM::VST3LNd16Pseudo:
4767 case ARM::VST3LNd16Pseudo_UPD:
4768 case ARM::VST3LNd32Pseudo:
4769 case ARM::VST3LNd32Pseudo_UPD:
4770 case ARM::VST3LNq16Pseudo:
4771 case ARM::VST3LNq16Pseudo_UPD:
4772 case ARM::VST3LNq32Pseudo:
4773 case ARM::VST3LNq32Pseudo_UPD:
4774 case ARM::VST3d8Pseudo:
4775 case ARM::VST3d8Pseudo_UPD:
4776 case ARM::VST3d16Pseudo:
4777 case ARM::VST3d16Pseudo_UPD:
4778 case ARM::VST3d32Pseudo:
4779 case ARM::VST3d32Pseudo_UPD:
4780 case ARM::VST3q8Pseudo_UPD:
4781 case ARM::VST3q8oddPseudo:
4782 case ARM::VST3q8oddPseudo_UPD:
4783 case ARM::VST3q16Pseudo_UPD:
4784 case ARM::VST3q16oddPseudo:
4785 case ARM::VST3q16oddPseudo_UPD:
4786 case ARM::VST3q32Pseudo_UPD:
4787 case ARM::VST3q32oddPseudo:
4788 case ARM::VST3q32oddPseudo_UPD:
4789 case ARM::VST4LNd8Pseudo:
4790 case ARM::VST4LNd8Pseudo_UPD:
4791 case ARM::VST4LNd16Pseudo:
4792 case ARM::VST4LNd16Pseudo_UPD:
4793 case ARM::VST4LNd32Pseudo:
4794 case ARM::VST4LNd32Pseudo_UPD:
4795 case ARM::VST4LNq16Pseudo:
4796 case ARM::VST4LNq16Pseudo_UPD:
4797 case ARM::VST4LNq32Pseudo:
4798 case ARM::VST4LNq32Pseudo_UPD:
4799 case ARM::VST4d8Pseudo:
4800 case ARM::VST4d8Pseudo_UPD:
4801 case ARM::VST4d16Pseudo:
4802 case ARM::VST4d16Pseudo_UPD:
4803 case ARM::VST4d32Pseudo:
4804 case ARM::VST4d32Pseudo_UPD:
4805 case ARM::VST4q8Pseudo_UPD:
4806 case ARM::VST4q8oddPseudo:
4807 case ARM::VST4q8oddPseudo_UPD:
4808 case ARM::VST4q16Pseudo_UPD:
4809 case ARM::VST4q16oddPseudo:
4810 case ARM::VST4q16oddPseudo_UPD:
4811 case ARM::VST4q32Pseudo_UPD:
4812 case ARM::VST4q32oddPseudo:
4813 case ARM::VST4q32oddPseudo_UPD:
4814 case ARM::VSTMQIA:
4815 case ARM::VTBL3Pseudo:
4816 case ARM::VTBL4Pseudo:
4817 case ARM::VTBX3Pseudo:
4818 case ARM::VTBX4Pseudo:
4819 case ARM::t2AUT:
4820 case ARM::t2BTI:
4821 case ARM::t2CLREX:
4822 case ARM::t2DCPS1:
4823 case ARM::t2DCPS2:
4824 case ARM::t2DCPS3:
4825 case ARM::t2Int_eh_sjlj_setjmp:
4826 case ARM::t2Int_eh_sjlj_setjmp_nofp:
4827 case ARM::t2PAC:
4828 case ARM::t2PACBTI:
4829 case ARM::t2SB:
4830 case ARM::t2SG:
4831 case ARM::t2TSB:
4832 case ARM::tInt_WIN_eh_sjlj_longjmp:
4833 case ARM::tInt_eh_sjlj_longjmp:
4834 case ARM::tInt_eh_sjlj_setjmp:
4835 case ARM::tTRAP:
4836 case ARM::t__brkdiv0: {
4837 break;
4838 }
4839 case ARM::VRINTAD:
4840 case ARM::VRINTMD:
4841 case ARM::VRINTND:
4842 case ARM::VRINTPD: {
4843 // op: Dd
4844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4845 Value |= (op & UINT64_C(16)) << 18;
4846 Value |= (op & UINT64_C(15)) << 12;
4847 // op: Dm
4848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4849 Value |= (op & UINT64_C(16)) << 1;
4850 Value |= (op & UINT64_C(15));
4851 break;
4852 }
4853 case ARM::VFP_VMAXNMD:
4854 case ARM::VFP_VMINNMD:
4855 case ARM::VSELEQD:
4856 case ARM::VSELGED:
4857 case ARM::VSELGTD:
4858 case ARM::VSELVSD: {
4859 // op: Dd
4860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4861 Value |= (op & UINT64_C(16)) << 18;
4862 Value |= (op & UINT64_C(15)) << 12;
4863 // op: Dn
4864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4865 Value |= (op & UINT64_C(15)) << 16;
4866 Value |= (op & UINT64_C(16)) << 3;
4867 // op: Dm
4868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4869 Value |= (op & UINT64_C(16)) << 1;
4870 Value |= (op & UINT64_C(15));
4871 break;
4872 }
4873 case ARM::MVE_VPST: {
4874 // op: Mk
4875 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
4876 Value |= (op & UINT64_C(8)) << 19;
4877 Value |= (op & UINT64_C(7)) << 13;
4878 break;
4879 }
4880 case ARM::MVE_VDUP8:
4881 case ARM::MVE_VDUP16:
4882 case ARM::MVE_VDUP32: {
4883 // op: Qd
4884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4885 Value |= (op & UINT64_C(7)) << 17;
4886 Value |= (op & UINT64_C(8)) << 4;
4887 // op: Rt
4888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4889 op &= UINT64_C(15);
4890 op <<= 12;
4891 Value |= op;
4892 break;
4893 }
4894 case ARM::MVE_VMOV_to_lane_32: {
4895 // op: Qd
4896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4897 Value |= (op & UINT64_C(7)) << 17;
4898 Value |= (op & UINT64_C(8)) << 4;
4899 // op: Rt
4900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4901 op &= UINT64_C(15);
4902 op <<= 12;
4903 Value |= op;
4904 // op: Idx
4905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4906 Value |= (op & UINT64_C(1)) << 21;
4907 Value |= (op & UINT64_C(2)) << 15;
4908 break;
4909 }
4910 case ARM::MVE_VMOV_to_lane_16: {
4911 // op: Qd
4912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4913 Value |= (op & UINT64_C(7)) << 17;
4914 Value |= (op & UINT64_C(8)) << 4;
4915 // op: Rt
4916 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4917 op &= UINT64_C(15);
4918 op <<= 12;
4919 Value |= op;
4920 // op: Idx
4921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4922 Value |= (op & UINT64_C(2)) << 20;
4923 Value |= (op & UINT64_C(4)) << 14;
4924 Value |= (op & UINT64_C(1)) << 6;
4925 break;
4926 }
4927 case ARM::MVE_VMOV_to_lane_8: {
4928 // op: Qd
4929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4930 Value |= (op & UINT64_C(7)) << 17;
4931 Value |= (op & UINT64_C(8)) << 4;
4932 // op: Rt
4933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4934 op &= UINT64_C(15);
4935 op <<= 12;
4936 Value |= op;
4937 // op: Idx
4938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4939 Value |= (op & UINT64_C(4)) << 19;
4940 Value |= (op & UINT64_C(8)) << 13;
4941 Value |= (op & UINT64_C(3)) << 5;
4942 break;
4943 }
4944 case ARM::MVE_VABSs8:
4945 case ARM::MVE_VABSs16:
4946 case ARM::MVE_VABSs32:
4947 case ARM::MVE_VCLSs8:
4948 case ARM::MVE_VCLSs16:
4949 case ARM::MVE_VCLSs32:
4950 case ARM::MVE_VCLZs8:
4951 case ARM::MVE_VCLZs16:
4952 case ARM::MVE_VCLZs32:
4953 case ARM::MVE_VCVTf32f16bh:
4954 case ARM::MVE_VCVTf32f16th:
4955 case ARM::MVE_VMOVLs8bh:
4956 case ARM::MVE_VMOVLs8th:
4957 case ARM::MVE_VMOVLs16bh:
4958 case ARM::MVE_VMOVLs16th:
4959 case ARM::MVE_VMOVLu8bh:
4960 case ARM::MVE_VMOVLu8th:
4961 case ARM::MVE_VMOVLu16bh:
4962 case ARM::MVE_VMOVLu16th:
4963 case ARM::MVE_VMVN:
4964 case ARM::MVE_VNEGs8:
4965 case ARM::MVE_VNEGs16:
4966 case ARM::MVE_VNEGs32:
4967 case ARM::MVE_VQABSs8:
4968 case ARM::MVE_VQABSs16:
4969 case ARM::MVE_VQABSs32:
4970 case ARM::MVE_VQNEGs8:
4971 case ARM::MVE_VQNEGs16:
4972 case ARM::MVE_VQNEGs32:
4973 case ARM::MVE_VREV16_8:
4974 case ARM::MVE_VREV32_8:
4975 case ARM::MVE_VREV32_16:
4976 case ARM::MVE_VREV64_8:
4977 case ARM::MVE_VREV64_16:
4978 case ARM::MVE_VREV64_32:
4979 case ARM::MVE_VSHLL_lws8bh:
4980 case ARM::MVE_VSHLL_lws8th:
4981 case ARM::MVE_VSHLL_lws16bh:
4982 case ARM::MVE_VSHLL_lws16th:
4983 case ARM::MVE_VSHLL_lwu8bh:
4984 case ARM::MVE_VSHLL_lwu8th:
4985 case ARM::MVE_VSHLL_lwu16bh:
4986 case ARM::MVE_VSHLL_lwu16th: {
4987 // op: Qd
4988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4989 Value |= (op & UINT64_C(8)) << 19;
4990 Value |= (op & UINT64_C(7)) << 13;
4991 // op: Qm
4992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4993 Value |= (op & UINT64_C(8)) << 2;
4994 Value |= (op & UINT64_C(7)) << 1;
4995 break;
4996 }
4997 case ARM::MVE_VQRSHL_by_vecs8:
4998 case ARM::MVE_VQRSHL_by_vecs16:
4999 case ARM::MVE_VQRSHL_by_vecs32:
5000 case ARM::MVE_VQRSHL_by_vecu8:
5001 case ARM::MVE_VQRSHL_by_vecu16:
5002 case ARM::MVE_VQRSHL_by_vecu32:
5003 case ARM::MVE_VQSHL_by_vecs8:
5004 case ARM::MVE_VQSHL_by_vecs16:
5005 case ARM::MVE_VQSHL_by_vecs32:
5006 case ARM::MVE_VQSHL_by_vecu8:
5007 case ARM::MVE_VQSHL_by_vecu16:
5008 case ARM::MVE_VQSHL_by_vecu32:
5009 case ARM::MVE_VRSHL_by_vecs8:
5010 case ARM::MVE_VRSHL_by_vecs16:
5011 case ARM::MVE_VRSHL_by_vecs32:
5012 case ARM::MVE_VRSHL_by_vecu8:
5013 case ARM::MVE_VRSHL_by_vecu16:
5014 case ARM::MVE_VRSHL_by_vecu32:
5015 case ARM::MVE_VSHL_by_vecs8:
5016 case ARM::MVE_VSHL_by_vecs16:
5017 case ARM::MVE_VSHL_by_vecs32:
5018 case ARM::MVE_VSHL_by_vecu8:
5019 case ARM::MVE_VSHL_by_vecu16:
5020 case ARM::MVE_VSHL_by_vecu32: {
5021 // op: Qd
5022 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5023 Value |= (op & UINT64_C(8)) << 19;
5024 Value |= (op & UINT64_C(7)) << 13;
5025 // op: Qm
5026 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5027 Value |= (op & UINT64_C(8)) << 2;
5028 Value |= (op & UINT64_C(7)) << 1;
5029 // op: Qn
5030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5031 Value |= (op & UINT64_C(7)) << 17;
5032 Value |= (op & UINT64_C(8)) << 4;
5033 break;
5034 }
5035 case ARM::MVE_VSHLL_imms16bh:
5036 case ARM::MVE_VSHLL_imms16th:
5037 case ARM::MVE_VSHLL_immu16bh:
5038 case ARM::MVE_VSHLL_immu16th: {
5039 // op: Qd
5040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5041 Value |= (op & UINT64_C(8)) << 19;
5042 Value |= (op & UINT64_C(7)) << 13;
5043 // op: Qm
5044 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5045 Value |= (op & UINT64_C(8)) << 2;
5046 Value |= (op & UINT64_C(7)) << 1;
5047 // op: imm
5048 op = getMVEShiftImmOpValue(MI, OpIdx: 2, Fixups, STI);
5049 op &= UINT64_C(15);
5050 op <<= 16;
5051 Value |= op;
5052 break;
5053 }
5054 case ARM::MVE_VSHLL_imms8bh:
5055 case ARM::MVE_VSHLL_imms8th:
5056 case ARM::MVE_VSHLL_immu8bh:
5057 case ARM::MVE_VSHLL_immu8th: {
5058 // op: Qd
5059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5060 Value |= (op & UINT64_C(8)) << 19;
5061 Value |= (op & UINT64_C(7)) << 13;
5062 // op: Qm
5063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5064 Value |= (op & UINT64_C(8)) << 2;
5065 Value |= (op & UINT64_C(7)) << 1;
5066 // op: imm
5067 op = getMVEShiftImmOpValue(MI, OpIdx: 2, Fixups, STI);
5068 op &= UINT64_C(7);
5069 op <<= 16;
5070 Value |= op;
5071 break;
5072 }
5073 case ARM::MVE_VQSHLU_imms16:
5074 case ARM::MVE_VQSHLimms16:
5075 case ARM::MVE_VQSHLimmu16:
5076 case ARM::MVE_VSHL_immi16: {
5077 // op: Qd
5078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5079 Value |= (op & UINT64_C(8)) << 19;
5080 Value |= (op & UINT64_C(7)) << 13;
5081 // op: Qm
5082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5083 Value |= (op & UINT64_C(8)) << 2;
5084 Value |= (op & UINT64_C(7)) << 1;
5085 // op: imm
5086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5087 op &= UINT64_C(15);
5088 op <<= 16;
5089 Value |= op;
5090 break;
5091 }
5092 case ARM::MVE_VQSHLU_imms32:
5093 case ARM::MVE_VQSHLimms32:
5094 case ARM::MVE_VQSHLimmu32:
5095 case ARM::MVE_VSHL_immi32: {
5096 // op: Qd
5097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5098 Value |= (op & UINT64_C(8)) << 19;
5099 Value |= (op & UINT64_C(7)) << 13;
5100 // op: Qm
5101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5102 Value |= (op & UINT64_C(8)) << 2;
5103 Value |= (op & UINT64_C(7)) << 1;
5104 // op: imm
5105 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5106 op &= UINT64_C(31);
5107 op <<= 16;
5108 Value |= op;
5109 break;
5110 }
5111 case ARM::MVE_VQSHLU_imms8:
5112 case ARM::MVE_VQSHLimms8:
5113 case ARM::MVE_VQSHLimmu8:
5114 case ARM::MVE_VSHL_immi8: {
5115 // op: Qd
5116 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5117 Value |= (op & UINT64_C(8)) << 19;
5118 Value |= (op & UINT64_C(7)) << 13;
5119 // op: Qm
5120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5121 Value |= (op & UINT64_C(8)) << 2;
5122 Value |= (op & UINT64_C(7)) << 1;
5123 // op: imm
5124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5125 op &= UINT64_C(7);
5126 op <<= 16;
5127 Value |= op;
5128 break;
5129 }
5130 case ARM::MVE_VRSHR_imms16:
5131 case ARM::MVE_VRSHR_immu16:
5132 case ARM::MVE_VSHR_imms16:
5133 case ARM::MVE_VSHR_immu16: {
5134 // op: Qd
5135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5136 Value |= (op & UINT64_C(8)) << 19;
5137 Value |= (op & UINT64_C(7)) << 13;
5138 // op: Qm
5139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5140 Value |= (op & UINT64_C(8)) << 2;
5141 Value |= (op & UINT64_C(7)) << 1;
5142 // op: imm
5143 op = getShiftRight16Imm(MI, Op: 2, Fixups, STI);
5144 op &= UINT64_C(15);
5145 op <<= 16;
5146 Value |= op;
5147 break;
5148 }
5149 case ARM::MVE_VRSHR_imms32:
5150 case ARM::MVE_VRSHR_immu32:
5151 case ARM::MVE_VSHR_imms32:
5152 case ARM::MVE_VSHR_immu32: {
5153 // op: Qd
5154 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5155 Value |= (op & UINT64_C(8)) << 19;
5156 Value |= (op & UINT64_C(7)) << 13;
5157 // op: Qm
5158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5159 Value |= (op & UINT64_C(8)) << 2;
5160 Value |= (op & UINT64_C(7)) << 1;
5161 // op: imm
5162 op = getShiftRight32Imm(MI, Op: 2, Fixups, STI);
5163 op &= UINT64_C(31);
5164 op <<= 16;
5165 Value |= op;
5166 break;
5167 }
5168 case ARM::MVE_VRSHR_imms8:
5169 case ARM::MVE_VRSHR_immu8:
5170 case ARM::MVE_VSHR_imms8:
5171 case ARM::MVE_VSHR_immu8: {
5172 // op: Qd
5173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5174 Value |= (op & UINT64_C(8)) << 19;
5175 Value |= (op & UINT64_C(7)) << 13;
5176 // op: Qm
5177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5178 Value |= (op & UINT64_C(8)) << 2;
5179 Value |= (op & UINT64_C(7)) << 1;
5180 // op: imm
5181 op = getShiftRight8Imm(MI, Op: 2, Fixups, STI);
5182 op &= UINT64_C(7);
5183 op <<= 16;
5184 Value |= op;
5185 break;
5186 }
5187 case ARM::MVE_VCVTf16f32bh:
5188 case ARM::MVE_VCVTf16f32th:
5189 case ARM::MVE_VMAXAs8:
5190 case ARM::MVE_VMAXAs16:
5191 case ARM::MVE_VMAXAs32:
5192 case ARM::MVE_VMAXNMAf16:
5193 case ARM::MVE_VMAXNMAf32:
5194 case ARM::MVE_VMINAs8:
5195 case ARM::MVE_VMINAs16:
5196 case ARM::MVE_VMINAs32:
5197 case ARM::MVE_VMINNMAf16:
5198 case ARM::MVE_VMINNMAf32:
5199 case ARM::MVE_VMOVNi16bh:
5200 case ARM::MVE_VMOVNi16th:
5201 case ARM::MVE_VMOVNi32bh:
5202 case ARM::MVE_VMOVNi32th:
5203 case ARM::MVE_VQMOVNs16bh:
5204 case ARM::MVE_VQMOVNs16th:
5205 case ARM::MVE_VQMOVNs32bh:
5206 case ARM::MVE_VQMOVNs32th:
5207 case ARM::MVE_VQMOVNu16bh:
5208 case ARM::MVE_VQMOVNu16th:
5209 case ARM::MVE_VQMOVNu32bh:
5210 case ARM::MVE_VQMOVNu32th:
5211 case ARM::MVE_VQMOVUNs16bh:
5212 case ARM::MVE_VQMOVUNs16th:
5213 case ARM::MVE_VQMOVUNs32bh:
5214 case ARM::MVE_VQMOVUNs32th: {
5215 // op: Qd
5216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5217 Value |= (op & UINT64_C(8)) << 19;
5218 Value |= (op & UINT64_C(7)) << 13;
5219 // op: Qm
5220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5221 Value |= (op & UINT64_C(8)) << 2;
5222 Value |= (op & UINT64_C(7)) << 1;
5223 break;
5224 }
5225 case ARM::MVE_VAND:
5226 case ARM::MVE_VBIC:
5227 case ARM::MVE_VEOR:
5228 case ARM::MVE_VMULHs8:
5229 case ARM::MVE_VMULHs16:
5230 case ARM::MVE_VMULHs32:
5231 case ARM::MVE_VMULHu8:
5232 case ARM::MVE_VMULHu16:
5233 case ARM::MVE_VMULHu32:
5234 case ARM::MVE_VMULLBp8:
5235 case ARM::MVE_VMULLBp16:
5236 case ARM::MVE_VMULLBs8:
5237 case ARM::MVE_VMULLBs16:
5238 case ARM::MVE_VMULLBs32:
5239 case ARM::MVE_VMULLBu8:
5240 case ARM::MVE_VMULLBu16:
5241 case ARM::MVE_VMULLBu32:
5242 case ARM::MVE_VMULLTp8:
5243 case ARM::MVE_VMULLTp16:
5244 case ARM::MVE_VMULLTs8:
5245 case ARM::MVE_VMULLTs16:
5246 case ARM::MVE_VMULLTs32:
5247 case ARM::MVE_VMULLTu8:
5248 case ARM::MVE_VMULLTu16:
5249 case ARM::MVE_VMULLTu32:
5250 case ARM::MVE_VORN:
5251 case ARM::MVE_VORR:
5252 case ARM::MVE_VQDMULLs16bh:
5253 case ARM::MVE_VQDMULLs16th:
5254 case ARM::MVE_VQDMULLs32bh:
5255 case ARM::MVE_VQDMULLs32th:
5256 case ARM::MVE_VRMULHs8:
5257 case ARM::MVE_VRMULHs16:
5258 case ARM::MVE_VRMULHs32:
5259 case ARM::MVE_VRMULHu8:
5260 case ARM::MVE_VRMULHu16:
5261 case ARM::MVE_VRMULHu32: {
5262 // op: Qd
5263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5264 Value |= (op & UINT64_C(8)) << 19;
5265 Value |= (op & UINT64_C(7)) << 13;
5266 // op: Qm
5267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5268 Value |= (op & UINT64_C(8)) << 2;
5269 Value |= (op & UINT64_C(7)) << 1;
5270 // op: Qn
5271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5272 Value |= (op & UINT64_C(7)) << 17;
5273 Value |= (op & UINT64_C(8)) << 4;
5274 break;
5275 }
5276 case ARM::MVE_VCMULf16:
5277 case ARM::MVE_VCMULf32: {
5278 // op: Qd
5279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5280 Value |= (op & UINT64_C(8)) << 19;
5281 Value |= (op & UINT64_C(7)) << 13;
5282 // op: Qm
5283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5284 Value |= (op & UINT64_C(8)) << 2;
5285 Value |= (op & UINT64_C(7)) << 1;
5286 // op: Qn
5287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5288 Value |= (op & UINT64_C(7)) << 17;
5289 Value |= (op & UINT64_C(8)) << 4;
5290 // op: rot
5291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5292 Value |= (op & UINT64_C(2)) << 11;
5293 Value |= (op & UINT64_C(1));
5294 break;
5295 }
5296 case ARM::MVE_VCADDi8:
5297 case ARM::MVE_VCADDi16:
5298 case ARM::MVE_VCADDi32:
5299 case ARM::MVE_VHCADDs8:
5300 case ARM::MVE_VHCADDs16:
5301 case ARM::MVE_VHCADDs32: {
5302 // op: Qd
5303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5304 Value |= (op & UINT64_C(8)) << 19;
5305 Value |= (op & UINT64_C(7)) << 13;
5306 // op: Qm
5307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5308 Value |= (op & UINT64_C(8)) << 2;
5309 Value |= (op & UINT64_C(7)) << 1;
5310 // op: Qn
5311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5312 Value |= (op & UINT64_C(7)) << 17;
5313 Value |= (op & UINT64_C(8)) << 4;
5314 // op: rot
5315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5316 op &= UINT64_C(1);
5317 op <<= 12;
5318 Value |= op;
5319 break;
5320 }
5321 case ARM::MVE_VSLIimm16: {
5322 // op: Qd
5323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5324 Value |= (op & UINT64_C(8)) << 19;
5325 Value |= (op & UINT64_C(7)) << 13;
5326 // op: Qm
5327 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5328 Value |= (op & UINT64_C(8)) << 2;
5329 Value |= (op & UINT64_C(7)) << 1;
5330 // op: imm
5331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5332 op &= UINT64_C(15);
5333 op <<= 16;
5334 Value |= op;
5335 break;
5336 }
5337 case ARM::MVE_VSLIimm32: {
5338 // op: Qd
5339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5340 Value |= (op & UINT64_C(8)) << 19;
5341 Value |= (op & UINT64_C(7)) << 13;
5342 // op: Qm
5343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5344 Value |= (op & UINT64_C(8)) << 2;
5345 Value |= (op & UINT64_C(7)) << 1;
5346 // op: imm
5347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5348 op &= UINT64_C(31);
5349 op <<= 16;
5350 Value |= op;
5351 break;
5352 }
5353 case ARM::MVE_VSLIimm8: {
5354 // op: Qd
5355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5356 Value |= (op & UINT64_C(8)) << 19;
5357 Value |= (op & UINT64_C(7)) << 13;
5358 // op: Qm
5359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5360 Value |= (op & UINT64_C(8)) << 2;
5361 Value |= (op & UINT64_C(7)) << 1;
5362 // op: imm
5363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5364 op &= UINT64_C(7);
5365 op <<= 16;
5366 Value |= op;
5367 break;
5368 }
5369 case ARM::MVE_VQRSHRNbhs32:
5370 case ARM::MVE_VQRSHRNbhu32:
5371 case ARM::MVE_VQRSHRNths32:
5372 case ARM::MVE_VQRSHRNthu32:
5373 case ARM::MVE_VQRSHRUNs32bh:
5374 case ARM::MVE_VQRSHRUNs32th:
5375 case ARM::MVE_VQSHRNbhs32:
5376 case ARM::MVE_VQSHRNbhu32:
5377 case ARM::MVE_VQSHRNths32:
5378 case ARM::MVE_VQSHRNthu32:
5379 case ARM::MVE_VQSHRUNs32bh:
5380 case ARM::MVE_VQSHRUNs32th:
5381 case ARM::MVE_VRSHRNi32bh:
5382 case ARM::MVE_VRSHRNi32th:
5383 case ARM::MVE_VSHRNi32bh:
5384 case ARM::MVE_VSHRNi32th:
5385 case ARM::MVE_VSRIimm16: {
5386 // op: Qd
5387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5388 Value |= (op & UINT64_C(8)) << 19;
5389 Value |= (op & UINT64_C(7)) << 13;
5390 // op: Qm
5391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5392 Value |= (op & UINT64_C(8)) << 2;
5393 Value |= (op & UINT64_C(7)) << 1;
5394 // op: imm
5395 op = getShiftRight16Imm(MI, Op: 3, Fixups, STI);
5396 op &= UINT64_C(15);
5397 op <<= 16;
5398 Value |= op;
5399 break;
5400 }
5401 case ARM::MVE_VSRIimm32: {
5402 // op: Qd
5403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5404 Value |= (op & UINT64_C(8)) << 19;
5405 Value |= (op & UINT64_C(7)) << 13;
5406 // op: Qm
5407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5408 Value |= (op & UINT64_C(8)) << 2;
5409 Value |= (op & UINT64_C(7)) << 1;
5410 // op: imm
5411 op = getShiftRight32Imm(MI, Op: 3, Fixups, STI);
5412 op &= UINT64_C(31);
5413 op <<= 16;
5414 Value |= op;
5415 break;
5416 }
5417 case ARM::MVE_VQRSHRNbhs16:
5418 case ARM::MVE_VQRSHRNbhu16:
5419 case ARM::MVE_VQRSHRNths16:
5420 case ARM::MVE_VQRSHRNthu16:
5421 case ARM::MVE_VQRSHRUNs16bh:
5422 case ARM::MVE_VQRSHRUNs16th:
5423 case ARM::MVE_VQSHRNbhs16:
5424 case ARM::MVE_VQSHRNbhu16:
5425 case ARM::MVE_VQSHRNths16:
5426 case ARM::MVE_VQSHRNthu16:
5427 case ARM::MVE_VQSHRUNs16bh:
5428 case ARM::MVE_VQSHRUNs16th:
5429 case ARM::MVE_VRSHRNi16bh:
5430 case ARM::MVE_VRSHRNi16th:
5431 case ARM::MVE_VSHRNi16bh:
5432 case ARM::MVE_VSHRNi16th:
5433 case ARM::MVE_VSRIimm8: {
5434 // op: Qd
5435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5436 Value |= (op & UINT64_C(8)) << 19;
5437 Value |= (op & UINT64_C(7)) << 13;
5438 // op: Qm
5439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5440 Value |= (op & UINT64_C(8)) << 2;
5441 Value |= (op & UINT64_C(7)) << 1;
5442 // op: imm
5443 op = getShiftRight8Imm(MI, Op: 3, Fixups, STI);
5444 op &= UINT64_C(7);
5445 op <<= 16;
5446 Value |= op;
5447 break;
5448 }
5449 case ARM::MVE_VADC:
5450 case ARM::MVE_VADCI:
5451 case ARM::MVE_VQDMLADHXs8:
5452 case ARM::MVE_VQDMLADHXs16:
5453 case ARM::MVE_VQDMLADHXs32:
5454 case ARM::MVE_VQDMLADHs8:
5455 case ARM::MVE_VQDMLADHs16:
5456 case ARM::MVE_VQDMLADHs32:
5457 case ARM::MVE_VQDMLSDHXs8:
5458 case ARM::MVE_VQDMLSDHXs16:
5459 case ARM::MVE_VQDMLSDHXs32:
5460 case ARM::MVE_VQDMLSDHs8:
5461 case ARM::MVE_VQDMLSDHs16:
5462 case ARM::MVE_VQDMLSDHs32:
5463 case ARM::MVE_VQRDMLADHXs8:
5464 case ARM::MVE_VQRDMLADHXs16:
5465 case ARM::MVE_VQRDMLADHXs32:
5466 case ARM::MVE_VQRDMLADHs8:
5467 case ARM::MVE_VQRDMLADHs16:
5468 case ARM::MVE_VQRDMLADHs32:
5469 case ARM::MVE_VQRDMLSDHXs8:
5470 case ARM::MVE_VQRDMLSDHXs16:
5471 case ARM::MVE_VQRDMLSDHXs32:
5472 case ARM::MVE_VQRDMLSDHs8:
5473 case ARM::MVE_VQRDMLSDHs16:
5474 case ARM::MVE_VQRDMLSDHs32:
5475 case ARM::MVE_VSBC:
5476 case ARM::MVE_VSBCI: {
5477 // op: Qd
5478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5479 Value |= (op & UINT64_C(8)) << 19;
5480 Value |= (op & UINT64_C(7)) << 13;
5481 // op: Qm
5482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5483 Value |= (op & UINT64_C(8)) << 2;
5484 Value |= (op & UINT64_C(7)) << 1;
5485 // op: Qn
5486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5487 Value |= (op & UINT64_C(7)) << 17;
5488 Value |= (op & UINT64_C(8)) << 4;
5489 break;
5490 }
5491 case ARM::MVE_VABDs8:
5492 case ARM::MVE_VABDs16:
5493 case ARM::MVE_VABDs32:
5494 case ARM::MVE_VABDu8:
5495 case ARM::MVE_VABDu16:
5496 case ARM::MVE_VABDu32:
5497 case ARM::MVE_VADDi8:
5498 case ARM::MVE_VADDi16:
5499 case ARM::MVE_VADDi32:
5500 case ARM::MVE_VHADDs8:
5501 case ARM::MVE_VHADDs16:
5502 case ARM::MVE_VHADDs32:
5503 case ARM::MVE_VHADDu8:
5504 case ARM::MVE_VHADDu16:
5505 case ARM::MVE_VHADDu32:
5506 case ARM::MVE_VHSUBs8:
5507 case ARM::MVE_VHSUBs16:
5508 case ARM::MVE_VHSUBs32:
5509 case ARM::MVE_VHSUBu8:
5510 case ARM::MVE_VHSUBu16:
5511 case ARM::MVE_VHSUBu32:
5512 case ARM::MVE_VMAXNMf16:
5513 case ARM::MVE_VMAXNMf32:
5514 case ARM::MVE_VMAXs8:
5515 case ARM::MVE_VMAXs16:
5516 case ARM::MVE_VMAXs32:
5517 case ARM::MVE_VMAXu8:
5518 case ARM::MVE_VMAXu16:
5519 case ARM::MVE_VMAXu32:
5520 case ARM::MVE_VMINNMf16:
5521 case ARM::MVE_VMINNMf32:
5522 case ARM::MVE_VMINs8:
5523 case ARM::MVE_VMINs16:
5524 case ARM::MVE_VMINs32:
5525 case ARM::MVE_VMINu8:
5526 case ARM::MVE_VMINu16:
5527 case ARM::MVE_VMINu32:
5528 case ARM::MVE_VMULi8:
5529 case ARM::MVE_VMULi16:
5530 case ARM::MVE_VMULi32:
5531 case ARM::MVE_VQADDs8:
5532 case ARM::MVE_VQADDs16:
5533 case ARM::MVE_VQADDs32:
5534 case ARM::MVE_VQADDu8:
5535 case ARM::MVE_VQADDu16:
5536 case ARM::MVE_VQADDu32:
5537 case ARM::MVE_VQDMULHi8:
5538 case ARM::MVE_VQDMULHi16:
5539 case ARM::MVE_VQDMULHi32:
5540 case ARM::MVE_VQRDMULHi8:
5541 case ARM::MVE_VQRDMULHi16:
5542 case ARM::MVE_VQRDMULHi32:
5543 case ARM::MVE_VQSUBs8:
5544 case ARM::MVE_VQSUBs16:
5545 case ARM::MVE_VQSUBs32:
5546 case ARM::MVE_VQSUBu8:
5547 case ARM::MVE_VQSUBu16:
5548 case ARM::MVE_VQSUBu32:
5549 case ARM::MVE_VRHADDs8:
5550 case ARM::MVE_VRHADDs16:
5551 case ARM::MVE_VRHADDs32:
5552 case ARM::MVE_VRHADDu8:
5553 case ARM::MVE_VRHADDu16:
5554 case ARM::MVE_VRHADDu32:
5555 case ARM::MVE_VSUBi8:
5556 case ARM::MVE_VSUBi16:
5557 case ARM::MVE_VSUBi32: {
5558 // op: Qd
5559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5560 Value |= (op & UINT64_C(8)) << 19;
5561 Value |= (op & UINT64_C(7)) << 13;
5562 // op: Qn
5563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5564 Value |= (op & UINT64_C(7)) << 17;
5565 Value |= (op & UINT64_C(8)) << 4;
5566 // op: Qm
5567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5568 Value |= (op & UINT64_C(8)) << 2;
5569 Value |= (op & UINT64_C(7)) << 1;
5570 break;
5571 }
5572 case ARM::MVE_VADD_qr_f16:
5573 case ARM::MVE_VADD_qr_f32:
5574 case ARM::MVE_VADD_qr_i8:
5575 case ARM::MVE_VADD_qr_i16:
5576 case ARM::MVE_VADD_qr_i32:
5577 case ARM::MVE_VBRSR8:
5578 case ARM::MVE_VBRSR16:
5579 case ARM::MVE_VBRSR32:
5580 case ARM::MVE_VHADD_qr_s8:
5581 case ARM::MVE_VHADD_qr_s16:
5582 case ARM::MVE_VHADD_qr_s32:
5583 case ARM::MVE_VHADD_qr_u8:
5584 case ARM::MVE_VHADD_qr_u16:
5585 case ARM::MVE_VHADD_qr_u32:
5586 case ARM::MVE_VHSUB_qr_s8:
5587 case ARM::MVE_VHSUB_qr_s16:
5588 case ARM::MVE_VHSUB_qr_s32:
5589 case ARM::MVE_VHSUB_qr_u8:
5590 case ARM::MVE_VHSUB_qr_u16:
5591 case ARM::MVE_VHSUB_qr_u32:
5592 case ARM::MVE_VMUL_qr_f16:
5593 case ARM::MVE_VMUL_qr_f32:
5594 case ARM::MVE_VMUL_qr_i8:
5595 case ARM::MVE_VMUL_qr_i16:
5596 case ARM::MVE_VMUL_qr_i32:
5597 case ARM::MVE_VQADD_qr_s8:
5598 case ARM::MVE_VQADD_qr_s16:
5599 case ARM::MVE_VQADD_qr_s32:
5600 case ARM::MVE_VQADD_qr_u8:
5601 case ARM::MVE_VQADD_qr_u16:
5602 case ARM::MVE_VQADD_qr_u32:
5603 case ARM::MVE_VQDMULH_qr_s8:
5604 case ARM::MVE_VQDMULH_qr_s16:
5605 case ARM::MVE_VQDMULH_qr_s32:
5606 case ARM::MVE_VQDMULL_qr_s16bh:
5607 case ARM::MVE_VQDMULL_qr_s16th:
5608 case ARM::MVE_VQDMULL_qr_s32bh:
5609 case ARM::MVE_VQDMULL_qr_s32th:
5610 case ARM::MVE_VQRDMULH_qr_s8:
5611 case ARM::MVE_VQRDMULH_qr_s16:
5612 case ARM::MVE_VQRDMULH_qr_s32:
5613 case ARM::MVE_VQSUB_qr_s8:
5614 case ARM::MVE_VQSUB_qr_s16:
5615 case ARM::MVE_VQSUB_qr_s32:
5616 case ARM::MVE_VQSUB_qr_u8:
5617 case ARM::MVE_VQSUB_qr_u16:
5618 case ARM::MVE_VQSUB_qr_u32:
5619 case ARM::MVE_VSUB_qr_f16:
5620 case ARM::MVE_VSUB_qr_f32:
5621 case ARM::MVE_VSUB_qr_i8:
5622 case ARM::MVE_VSUB_qr_i16:
5623 case ARM::MVE_VSUB_qr_i32: {
5624 // op: Qd
5625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5626 Value |= (op & UINT64_C(8)) << 19;
5627 Value |= (op & UINT64_C(7)) << 13;
5628 // op: Qn
5629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5630 Value |= (op & UINT64_C(7)) << 17;
5631 Value |= (op & UINT64_C(8)) << 4;
5632 // op: Rm
5633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5634 op &= UINT64_C(15);
5635 Value |= op;
5636 break;
5637 }
5638 case ARM::MVE_VFMA_qr_Sf16:
5639 case ARM::MVE_VFMA_qr_Sf32:
5640 case ARM::MVE_VFMA_qr_f16:
5641 case ARM::MVE_VFMA_qr_f32:
5642 case ARM::MVE_VMLAS_qr_i8:
5643 case ARM::MVE_VMLAS_qr_i16:
5644 case ARM::MVE_VMLAS_qr_i32:
5645 case ARM::MVE_VMLA_qr_i8:
5646 case ARM::MVE_VMLA_qr_i16:
5647 case ARM::MVE_VMLA_qr_i32:
5648 case ARM::MVE_VQDMLAH_qrs8:
5649 case ARM::MVE_VQDMLAH_qrs16:
5650 case ARM::MVE_VQDMLAH_qrs32:
5651 case ARM::MVE_VQDMLASH_qrs8:
5652 case ARM::MVE_VQDMLASH_qrs16:
5653 case ARM::MVE_VQDMLASH_qrs32:
5654 case ARM::MVE_VQRDMLAH_qrs8:
5655 case ARM::MVE_VQRDMLAH_qrs16:
5656 case ARM::MVE_VQRDMLAH_qrs32:
5657 case ARM::MVE_VQRDMLASH_qrs8:
5658 case ARM::MVE_VQRDMLASH_qrs16:
5659 case ARM::MVE_VQRDMLASH_qrs32: {
5660 // op: Qd
5661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5662 Value |= (op & UINT64_C(8)) << 19;
5663 Value |= (op & UINT64_C(7)) << 13;
5664 // op: Qn
5665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5666 Value |= (op & UINT64_C(7)) << 17;
5667 Value |= (op & UINT64_C(8)) << 4;
5668 // op: Rm
5669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5670 op &= UINT64_C(15);
5671 Value |= op;
5672 break;
5673 }
5674 case ARM::MVE_VQRSHL_qrs8:
5675 case ARM::MVE_VQRSHL_qrs16:
5676 case ARM::MVE_VQRSHL_qrs32:
5677 case ARM::MVE_VQRSHL_qru8:
5678 case ARM::MVE_VQRSHL_qru16:
5679 case ARM::MVE_VQRSHL_qru32:
5680 case ARM::MVE_VQSHL_qrs8:
5681 case ARM::MVE_VQSHL_qrs16:
5682 case ARM::MVE_VQSHL_qrs32:
5683 case ARM::MVE_VQSHL_qru8:
5684 case ARM::MVE_VQSHL_qru16:
5685 case ARM::MVE_VQSHL_qru32:
5686 case ARM::MVE_VRSHL_qrs8:
5687 case ARM::MVE_VRSHL_qrs16:
5688 case ARM::MVE_VRSHL_qrs32:
5689 case ARM::MVE_VRSHL_qru8:
5690 case ARM::MVE_VRSHL_qru16:
5691 case ARM::MVE_VRSHL_qru32:
5692 case ARM::MVE_VSHL_qrs8:
5693 case ARM::MVE_VSHL_qrs16:
5694 case ARM::MVE_VSHL_qrs32:
5695 case ARM::MVE_VSHL_qru8:
5696 case ARM::MVE_VSHL_qru16:
5697 case ARM::MVE_VSHL_qru32: {
5698 // op: Qd
5699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5700 Value |= (op & UINT64_C(8)) << 19;
5701 Value |= (op & UINT64_C(7)) << 13;
5702 // op: Rm
5703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5704 op &= UINT64_C(15);
5705 Value |= op;
5706 break;
5707 }
5708 case ARM::MVE_VDWDUPu8:
5709 case ARM::MVE_VDWDUPu16:
5710 case ARM::MVE_VDWDUPu32:
5711 case ARM::MVE_VIWDUPu8:
5712 case ARM::MVE_VIWDUPu16:
5713 case ARM::MVE_VIWDUPu32: {
5714 // op: Qd
5715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5716 Value |= (op & UINT64_C(8)) << 19;
5717 Value |= (op & UINT64_C(7)) << 13;
5718 // op: Rm
5719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5720 op &= UINT64_C(14);
5721 Value |= op;
5722 // op: Rn
5723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5724 op &= UINT64_C(14);
5725 op <<= 16;
5726 Value |= op;
5727 // op: imm
5728 op = getPowerTwoOpValue(MI, OpIdx: 4, Fixups, STI);
5729 Value |= (op & UINT64_C(2)) << 6;
5730 Value |= (op & UINT64_C(1));
5731 break;
5732 }
5733 case ARM::MVE_VDDUPu8:
5734 case ARM::MVE_VDDUPu16:
5735 case ARM::MVE_VDDUPu32:
5736 case ARM::MVE_VIDUPu8:
5737 case ARM::MVE_VIDUPu16:
5738 case ARM::MVE_VIDUPu32: {
5739 // op: Qd
5740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5741 Value |= (op & UINT64_C(8)) << 19;
5742 Value |= (op & UINT64_C(7)) << 13;
5743 // op: Rn
5744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5745 op &= UINT64_C(14);
5746 op <<= 16;
5747 Value |= op;
5748 // op: imm
5749 op = getPowerTwoOpValue(MI, OpIdx: 3, Fixups, STI);
5750 Value |= (op & UINT64_C(2)) << 6;
5751 Value |= (op & UINT64_C(1));
5752 break;
5753 }
5754 case ARM::MVE_VLDRWU32_qi:
5755 case ARM::MVE_VSTRW32_qi: {
5756 // op: Qd
5757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5758 op &= UINT64_C(7);
5759 op <<= 13;
5760 Value |= op;
5761 // op: addr
5762 op = getMveAddrModeQOpValue<2>(MI, OpIdx: 1, Fixups, STI);
5763 Value |= (op & UINT64_C(128)) << 16;
5764 Value |= (op & UINT64_C(1792)) << 9;
5765 Value |= (op & UINT64_C(127));
5766 break;
5767 }
5768 case ARM::MVE_VLDRDU64_qi:
5769 case ARM::MVE_VSTRD64_qi: {
5770 // op: Qd
5771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5772 op &= UINT64_C(7);
5773 op <<= 13;
5774 Value |= op;
5775 // op: addr
5776 op = getMveAddrModeQOpValue<3>(MI, OpIdx: 1, Fixups, STI);
5777 Value |= (op & UINT64_C(128)) << 16;
5778 Value |= (op & UINT64_C(1792)) << 9;
5779 Value |= (op & UINT64_C(127));
5780 break;
5781 }
5782 case ARM::MVE_VLDRBS16_rq:
5783 case ARM::MVE_VLDRBS32_rq:
5784 case ARM::MVE_VLDRBU8_rq:
5785 case ARM::MVE_VLDRBU16_rq:
5786 case ARM::MVE_VLDRBU32_rq:
5787 case ARM::MVE_VLDRDU64_rq:
5788 case ARM::MVE_VLDRDU64_rq_u:
5789 case ARM::MVE_VLDRHS32_rq:
5790 case ARM::MVE_VLDRHS32_rq_u:
5791 case ARM::MVE_VLDRHU16_rq:
5792 case ARM::MVE_VLDRHU16_rq_u:
5793 case ARM::MVE_VLDRHU32_rq:
5794 case ARM::MVE_VLDRHU32_rq_u:
5795 case ARM::MVE_VLDRWU32_rq:
5796 case ARM::MVE_VLDRWU32_rq_u:
5797 case ARM::MVE_VSTRB8_rq:
5798 case ARM::MVE_VSTRB16_rq:
5799 case ARM::MVE_VSTRB32_rq:
5800 case ARM::MVE_VSTRD64_rq:
5801 case ARM::MVE_VSTRD64_rq_u:
5802 case ARM::MVE_VSTRH16_rq:
5803 case ARM::MVE_VSTRH16_rq_u:
5804 case ARM::MVE_VSTRH32_rq:
5805 case ARM::MVE_VSTRH32_rq_u:
5806 case ARM::MVE_VSTRW32_rq:
5807 case ARM::MVE_VSTRW32_rq_u: {
5808 // op: Qd
5809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5810 op &= UINT64_C(7);
5811 op <<= 13;
5812 Value |= op;
5813 // op: addr
5814 op = getMveAddrModeRQOpValue(MI, OpIdx: 1, Fixups, STI);
5815 Value |= (op & UINT64_C(120)) << 13;
5816 Value |= (op & UINT64_C(7)) << 1;
5817 break;
5818 }
5819 case ARM::MVE_VLDRBS16:
5820 case ARM::MVE_VLDRBS32:
5821 case ARM::MVE_VLDRBU16:
5822 case ARM::MVE_VLDRBU32:
5823 case ARM::MVE_VSTRB16:
5824 case ARM::MVE_VSTRB32: {
5825 // op: Qd
5826 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5827 op &= UINT64_C(7);
5828 op <<= 13;
5829 Value |= op;
5830 // op: addr
5831 op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 1, Fixups, STI);
5832 Value |= (op & UINT64_C(128)) << 16;
5833 Value |= (op & UINT64_C(1792)) << 8;
5834 Value |= (op & UINT64_C(127));
5835 break;
5836 }
5837 case ARM::MVE_VLDRBU8:
5838 case ARM::MVE_VSTRBU8: {
5839 // op: Qd
5840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5841 op &= UINT64_C(7);
5842 op <<= 13;
5843 Value |= op;
5844 // op: addr
5845 op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 1, Fixups, STI);
5846 Value |= (op & UINT64_C(128)) << 16;
5847 Value |= (op & UINT64_C(3840)) << 8;
5848 Value |= (op & UINT64_C(127));
5849 break;
5850 }
5851 case ARM::MVE_VLDRHS32:
5852 case ARM::MVE_VLDRHU32:
5853 case ARM::MVE_VSTRH32: {
5854 // op: Qd
5855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5856 op &= UINT64_C(7);
5857 op <<= 13;
5858 Value |= op;
5859 // op: addr
5860 op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 1, Fixups, STI);
5861 Value |= (op & UINT64_C(128)) << 16;
5862 Value |= (op & UINT64_C(1792)) << 8;
5863 Value |= (op & UINT64_C(127));
5864 break;
5865 }
5866 case ARM::MVE_VLDRHU16:
5867 case ARM::MVE_VSTRHU16: {
5868 // op: Qd
5869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5870 op &= UINT64_C(7);
5871 op <<= 13;
5872 Value |= op;
5873 // op: addr
5874 op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 1, Fixups, STI);
5875 Value |= (op & UINT64_C(128)) << 16;
5876 Value |= (op & UINT64_C(3840)) << 8;
5877 Value |= (op & UINT64_C(127));
5878 break;
5879 }
5880 case ARM::MVE_VLDRWU32:
5881 case ARM::MVE_VSTRWU32: {
5882 // op: Qd
5883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5884 op &= UINT64_C(7);
5885 op <<= 13;
5886 Value |= op;
5887 // op: addr
5888 op = getT2AddrModeImmOpValue<7,2>(MI, OpNum: 1, Fixups, STI);
5889 Value |= (op & UINT64_C(128)) << 16;
5890 Value |= (op & UINT64_C(3840)) << 8;
5891 Value |= (op & UINT64_C(127));
5892 break;
5893 }
5894 case ARM::MVE_VMOV_from_lane_32: {
5895 // op: Qd
5896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5897 Value |= (op & UINT64_C(7)) << 17;
5898 Value |= (op & UINT64_C(8)) << 4;
5899 // op: Rt
5900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5901 op &= UINT64_C(15);
5902 op <<= 12;
5903 Value |= op;
5904 // op: Idx
5905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5906 Value |= (op & UINT64_C(1)) << 21;
5907 Value |= (op & UINT64_C(2)) << 15;
5908 break;
5909 }
5910 case ARM::MVE_VMOV_from_lane_s16:
5911 case ARM::MVE_VMOV_from_lane_u16: {
5912 // op: Qd
5913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5914 Value |= (op & UINT64_C(7)) << 17;
5915 Value |= (op & UINT64_C(8)) << 4;
5916 // op: Rt
5917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5918 op &= UINT64_C(15);
5919 op <<= 12;
5920 Value |= op;
5921 // op: Idx
5922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5923 Value |= (op & UINT64_C(2)) << 20;
5924 Value |= (op & UINT64_C(4)) << 14;
5925 Value |= (op & UINT64_C(1)) << 6;
5926 break;
5927 }
5928 case ARM::MVE_VMOV_from_lane_s8:
5929 case ARM::MVE_VMOV_from_lane_u8: {
5930 // op: Qd
5931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5932 Value |= (op & UINT64_C(7)) << 17;
5933 Value |= (op & UINT64_C(8)) << 4;
5934 // op: Rt
5935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5936 op &= UINT64_C(15);
5937 op <<= 12;
5938 Value |= op;
5939 // op: Idx
5940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5941 Value |= (op & UINT64_C(4)) << 19;
5942 Value |= (op & UINT64_C(8)) << 13;
5943 Value |= (op & UINT64_C(3)) << 5;
5944 break;
5945 }
5946 case ARM::MVE_VLDRWU32_qi_pre:
5947 case ARM::MVE_VSTRW32_qi_pre: {
5948 // op: Qd
5949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5950 op &= UINT64_C(7);
5951 op <<= 13;
5952 Value |= op;
5953 // op: addr
5954 op = getMveAddrModeQOpValue<2>(MI, OpIdx: 2, Fixups, STI);
5955 Value |= (op & UINT64_C(128)) << 16;
5956 Value |= (op & UINT64_C(1792)) << 9;
5957 Value |= (op & UINT64_C(127));
5958 break;
5959 }
5960 case ARM::MVE_VLDRDU64_qi_pre:
5961 case ARM::MVE_VSTRD64_qi_pre: {
5962 // op: Qd
5963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5964 op &= UINT64_C(7);
5965 op <<= 13;
5966 Value |= op;
5967 // op: addr
5968 op = getMveAddrModeQOpValue<3>(MI, OpIdx: 2, Fixups, STI);
5969 Value |= (op & UINT64_C(128)) << 16;
5970 Value |= (op & UINT64_C(1792)) << 9;
5971 Value |= (op & UINT64_C(127));
5972 break;
5973 }
5974 case ARM::MVE_VLDRBS16_pre:
5975 case ARM::MVE_VLDRBS32_pre:
5976 case ARM::MVE_VLDRBU16_pre:
5977 case ARM::MVE_VLDRBU32_pre:
5978 case ARM::MVE_VSTRB16_pre:
5979 case ARM::MVE_VSTRB32_pre: {
5980 // op: Qd
5981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5982 op &= UINT64_C(7);
5983 op <<= 13;
5984 Value |= op;
5985 // op: addr
5986 op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 2, Fixups, STI);
5987 Value |= (op & UINT64_C(128)) << 16;
5988 Value |= (op & UINT64_C(1792)) << 8;
5989 Value |= (op & UINT64_C(127));
5990 break;
5991 }
5992 case ARM::MVE_VLDRBU8_pre:
5993 case ARM::MVE_VSTRBU8_pre: {
5994 // op: Qd
5995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5996 op &= UINT64_C(7);
5997 op <<= 13;
5998 Value |= op;
5999 // op: addr
6000 op = getT2AddrModeImmOpValue<7,0>(MI, OpNum: 2, Fixups, STI);
6001 Value |= (op & UINT64_C(128)) << 16;
6002 Value |= (op & UINT64_C(3840)) << 8;
6003 Value |= (op & UINT64_C(127));
6004 break;
6005 }
6006 case ARM::MVE_VLDRHS32_pre:
6007 case ARM::MVE_VLDRHU32_pre:
6008 case ARM::MVE_VSTRH32_pre: {
6009 // op: Qd
6010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6011 op &= UINT64_C(7);
6012 op <<= 13;
6013 Value |= op;
6014 // op: addr
6015 op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 2, Fixups, STI);
6016 Value |= (op & UINT64_C(128)) << 16;
6017 Value |= (op & UINT64_C(1792)) << 8;
6018 Value |= (op & UINT64_C(127));
6019 break;
6020 }
6021 case ARM::MVE_VLDRHU16_pre:
6022 case ARM::MVE_VSTRHU16_pre: {
6023 // op: Qd
6024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6025 op &= UINT64_C(7);
6026 op <<= 13;
6027 Value |= op;
6028 // op: addr
6029 op = getT2AddrModeImmOpValue<7,1>(MI, OpNum: 2, Fixups, STI);
6030 Value |= (op & UINT64_C(128)) << 16;
6031 Value |= (op & UINT64_C(3840)) << 8;
6032 Value |= (op & UINT64_C(127));
6033 break;
6034 }
6035 case ARM::MVE_VLDRWU32_pre:
6036 case ARM::MVE_VSTRWU32_pre: {
6037 // op: Qd
6038 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6039 op &= UINT64_C(7);
6040 op <<= 13;
6041 Value |= op;
6042 // op: addr
6043 op = getT2AddrModeImmOpValue<7,2>(MI, OpNum: 2, Fixups, STI);
6044 Value |= (op & UINT64_C(128)) << 16;
6045 Value |= (op & UINT64_C(3840)) << 8;
6046 Value |= (op & UINT64_C(127));
6047 break;
6048 }
6049 case ARM::MVE_VLDRBU8_post:
6050 case ARM::MVE_VSTRBU8_post: {
6051 // op: Qd
6052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6053 op &= UINT64_C(7);
6054 op <<= 13;
6055 Value |= op;
6056 // op: addr
6057 op = getT2ScaledImmOpValue<7,0>(MI, OpIdx: 3, Fixups, STI);
6058 Value |= (op & UINT64_C(128)) << 16;
6059 Value |= (op & UINT64_C(127));
6060 // op: Rn
6061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6062 op &= UINT64_C(15);
6063 op <<= 16;
6064 Value |= op;
6065 break;
6066 }
6067 case ARM::MVE_VLDRBS16_post:
6068 case ARM::MVE_VLDRBS32_post:
6069 case ARM::MVE_VLDRBU16_post:
6070 case ARM::MVE_VLDRBU32_post:
6071 case ARM::MVE_VSTRB16_post:
6072 case ARM::MVE_VSTRB32_post: {
6073 // op: Qd
6074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6075 op &= UINT64_C(7);
6076 op <<= 13;
6077 Value |= op;
6078 // op: addr
6079 op = getT2ScaledImmOpValue<7,0>(MI, OpIdx: 3, Fixups, STI);
6080 Value |= (op & UINT64_C(128)) << 16;
6081 Value |= (op & UINT64_C(127));
6082 // op: Rn
6083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6084 op &= UINT64_C(7);
6085 op <<= 16;
6086 Value |= op;
6087 break;
6088 }
6089 case ARM::MVE_VLDRHU16_post:
6090 case ARM::MVE_VSTRHU16_post: {
6091 // op: Qd
6092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6093 op &= UINT64_C(7);
6094 op <<= 13;
6095 Value |= op;
6096 // op: addr
6097 op = getT2ScaledImmOpValue<7,1>(MI, OpIdx: 3, Fixups, STI);
6098 Value |= (op & UINT64_C(128)) << 16;
6099 Value |= (op & UINT64_C(127));
6100 // op: Rn
6101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6102 op &= UINT64_C(15);
6103 op <<= 16;
6104 Value |= op;
6105 break;
6106 }
6107 case ARM::MVE_VLDRHS32_post:
6108 case ARM::MVE_VLDRHU32_post:
6109 case ARM::MVE_VSTRH32_post: {
6110 // op: Qd
6111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6112 op &= UINT64_C(7);
6113 op <<= 13;
6114 Value |= op;
6115 // op: addr
6116 op = getT2ScaledImmOpValue<7,1>(MI, OpIdx: 3, Fixups, STI);
6117 Value |= (op & UINT64_C(128)) << 16;
6118 Value |= (op & UINT64_C(127));
6119 // op: Rn
6120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6121 op &= UINT64_C(7);
6122 op <<= 16;
6123 Value |= op;
6124 break;
6125 }
6126 case ARM::MVE_VLDRWU32_post:
6127 case ARM::MVE_VSTRWU32_post: {
6128 // op: Qd
6129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6130 op &= UINT64_C(7);
6131 op <<= 13;
6132 Value |= op;
6133 // op: addr
6134 op = getT2ScaledImmOpValue<7,2>(MI, OpIdx: 3, Fixups, STI);
6135 Value |= (op & UINT64_C(128)) << 16;
6136 Value |= (op & UINT64_C(127));
6137 // op: Rn
6138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6139 op &= UINT64_C(15);
6140 op <<= 16;
6141 Value |= op;
6142 break;
6143 }
6144 case ARM::MVE_VABSf16:
6145 case ARM::MVE_VABSf32:
6146 case ARM::MVE_VCVTf16s16n:
6147 case ARM::MVE_VCVTf16u16n:
6148 case ARM::MVE_VCVTf32s32n:
6149 case ARM::MVE_VCVTf32u32n:
6150 case ARM::MVE_VCVTs16f16a:
6151 case ARM::MVE_VCVTs16f16m:
6152 case ARM::MVE_VCVTs16f16n:
6153 case ARM::MVE_VCVTs16f16p:
6154 case ARM::MVE_VCVTs16f16z:
6155 case ARM::MVE_VCVTs32f32a:
6156 case ARM::MVE_VCVTs32f32m:
6157 case ARM::MVE_VCVTs32f32n:
6158 case ARM::MVE_VCVTs32f32p:
6159 case ARM::MVE_VCVTs32f32z:
6160 case ARM::MVE_VCVTu16f16a:
6161 case ARM::MVE_VCVTu16f16m:
6162 case ARM::MVE_VCVTu16f16n:
6163 case ARM::MVE_VCVTu16f16p:
6164 case ARM::MVE_VCVTu16f16z:
6165 case ARM::MVE_VCVTu32f32a:
6166 case ARM::MVE_VCVTu32f32m:
6167 case ARM::MVE_VCVTu32f32n:
6168 case ARM::MVE_VCVTu32f32p:
6169 case ARM::MVE_VCVTu32f32z:
6170 case ARM::MVE_VNEGf16:
6171 case ARM::MVE_VNEGf32:
6172 case ARM::MVE_VRINTf16A:
6173 case ARM::MVE_VRINTf16M:
6174 case ARM::MVE_VRINTf16N:
6175 case ARM::MVE_VRINTf16P:
6176 case ARM::MVE_VRINTf16X:
6177 case ARM::MVE_VRINTf16Z:
6178 case ARM::MVE_VRINTf32A:
6179 case ARM::MVE_VRINTf32M:
6180 case ARM::MVE_VRINTf32N:
6181 case ARM::MVE_VRINTf32P:
6182 case ARM::MVE_VRINTf32X:
6183 case ARM::MVE_VRINTf32Z: {
6184 // op: Qm
6185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6186 Value |= (op & UINT64_C(8)) << 2;
6187 Value |= (op & UINT64_C(7)) << 1;
6188 // op: Qd
6189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6190 Value |= (op & UINT64_C(8)) << 19;
6191 Value |= (op & UINT64_C(7)) << 13;
6192 break;
6193 }
6194 case ARM::MVE_VCVTf16s16_fix:
6195 case ARM::MVE_VCVTf16u16_fix:
6196 case ARM::MVE_VCVTs16f16_fix:
6197 case ARM::MVE_VCVTu16f16_fix: {
6198 // op: Qm
6199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6200 Value |= (op & UINT64_C(8)) << 2;
6201 Value |= (op & UINT64_C(7)) << 1;
6202 // op: Qd
6203 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6204 Value |= (op & UINT64_C(8)) << 19;
6205 Value |= (op & UINT64_C(7)) << 13;
6206 // op: imm6
6207 op = getNEONVcvtImm32OpValue(MI, Op: 2, Fixups, STI);
6208 op &= UINT64_C(15);
6209 op <<= 16;
6210 Value |= op;
6211 break;
6212 }
6213 case ARM::MVE_VCVTf32s32_fix:
6214 case ARM::MVE_VCVTf32u32_fix:
6215 case ARM::MVE_VCVTs32f32_fix:
6216 case ARM::MVE_VCVTu32f32_fix: {
6217 // op: Qm
6218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6219 Value |= (op & UINT64_C(8)) << 2;
6220 Value |= (op & UINT64_C(7)) << 1;
6221 // op: Qd
6222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6223 Value |= (op & UINT64_C(8)) << 19;
6224 Value |= (op & UINT64_C(7)) << 13;
6225 // op: imm6
6226 op = getNEONVcvtImm32OpValue(MI, Op: 2, Fixups, STI);
6227 op &= UINT64_C(31);
6228 op <<= 16;
6229 Value |= op;
6230 break;
6231 }
6232 case ARM::MVE_VADDVs8no_acc:
6233 case ARM::MVE_VADDVs16no_acc:
6234 case ARM::MVE_VADDVs32no_acc:
6235 case ARM::MVE_VADDVu8no_acc:
6236 case ARM::MVE_VADDVu16no_acc:
6237 case ARM::MVE_VADDVu32no_acc: {
6238 // op: Qm
6239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6240 op &= UINT64_C(7);
6241 op <<= 1;
6242 Value |= op;
6243 // op: Rda
6244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6245 op &= UINT64_C(14);
6246 op <<= 12;
6247 Value |= op;
6248 break;
6249 }
6250 case ARM::MVE_VABDf16:
6251 case ARM::MVE_VABDf32:
6252 case ARM::MVE_VADDf16:
6253 case ARM::MVE_VADDf32:
6254 case ARM::MVE_VMULf16:
6255 case ARM::MVE_VMULf32:
6256 case ARM::MVE_VSUBf16:
6257 case ARM::MVE_VSUBf32: {
6258 // op: Qm
6259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6260 Value |= (op & UINT64_C(8)) << 2;
6261 Value |= (op & UINT64_C(7)) << 1;
6262 // op: Qd
6263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6264 Value |= (op & UINT64_C(8)) << 19;
6265 Value |= (op & UINT64_C(7)) << 13;
6266 // op: Qn
6267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6268 Value |= (op & UINT64_C(7)) << 17;
6269 Value |= (op & UINT64_C(8)) << 4;
6270 break;
6271 }
6272 case ARM::MVE_VCADDf16:
6273 case ARM::MVE_VCADDf32: {
6274 // op: Qm
6275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6276 Value |= (op & UINT64_C(8)) << 2;
6277 Value |= (op & UINT64_C(7)) << 1;
6278 // op: Qd
6279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6280 Value |= (op & UINT64_C(8)) << 19;
6281 Value |= (op & UINT64_C(7)) << 13;
6282 // op: Qn
6283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6284 Value |= (op & UINT64_C(7)) << 17;
6285 Value |= (op & UINT64_C(8)) << 4;
6286 // op: rot
6287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6288 op &= UINT64_C(1);
6289 op <<= 24;
6290 Value |= op;
6291 break;
6292 }
6293 case ARM::MVE_VADDVs8acc:
6294 case ARM::MVE_VADDVs16acc:
6295 case ARM::MVE_VADDVs32acc:
6296 case ARM::MVE_VADDVu8acc:
6297 case ARM::MVE_VADDVu16acc:
6298 case ARM::MVE_VADDVu32acc: {
6299 // op: Qm
6300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6301 op &= UINT64_C(7);
6302 op <<= 1;
6303 Value |= op;
6304 // op: Rda
6305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6306 op &= UINT64_C(14);
6307 op <<= 12;
6308 Value |= op;
6309 break;
6310 }
6311 case ARM::MVE_VMAXAVs8:
6312 case ARM::MVE_VMAXAVs16:
6313 case ARM::MVE_VMAXAVs32:
6314 case ARM::MVE_VMAXNMAVf16:
6315 case ARM::MVE_VMAXNMAVf32:
6316 case ARM::MVE_VMAXNMVf16:
6317 case ARM::MVE_VMAXNMVf32:
6318 case ARM::MVE_VMAXVs8:
6319 case ARM::MVE_VMAXVs16:
6320 case ARM::MVE_VMAXVs32:
6321 case ARM::MVE_VMAXVu8:
6322 case ARM::MVE_VMAXVu16:
6323 case ARM::MVE_VMAXVu32:
6324 case ARM::MVE_VMINAVs8:
6325 case ARM::MVE_VMINAVs16:
6326 case ARM::MVE_VMINAVs32:
6327 case ARM::MVE_VMINNMAVf16:
6328 case ARM::MVE_VMINNMAVf32:
6329 case ARM::MVE_VMINNMVf16:
6330 case ARM::MVE_VMINNMVf32:
6331 case ARM::MVE_VMINVs8:
6332 case ARM::MVE_VMINVs16:
6333 case ARM::MVE_VMINVs32:
6334 case ARM::MVE_VMINVu8:
6335 case ARM::MVE_VMINVu16:
6336 case ARM::MVE_VMINVu32: {
6337 // op: Qm
6338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6339 op &= UINT64_C(7);
6340 op <<= 1;
6341 Value |= op;
6342 // op: RdaDest
6343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6344 op &= UINT64_C(15);
6345 op <<= 12;
6346 Value |= op;
6347 break;
6348 }
6349 case ARM::MVE_VADDLVs32no_acc:
6350 case ARM::MVE_VADDLVu32no_acc: {
6351 // op: Qm
6352 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6353 op &= UINT64_C(7);
6354 op <<= 1;
6355 Value |= op;
6356 // op: RdaLo
6357 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6358 op &= UINT64_C(14);
6359 op <<= 12;
6360 Value |= op;
6361 // op: RdaHi
6362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6363 op &= UINT64_C(14);
6364 op <<= 19;
6365 Value |= op;
6366 break;
6367 }
6368 case ARM::MVE_VFMAf16:
6369 case ARM::MVE_VFMAf32:
6370 case ARM::MVE_VFMSf16:
6371 case ARM::MVE_VFMSf32: {
6372 // op: Qm
6373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6374 Value |= (op & UINT64_C(8)) << 2;
6375 Value |= (op & UINT64_C(7)) << 1;
6376 // op: Qd
6377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6378 Value |= (op & UINT64_C(8)) << 19;
6379 Value |= (op & UINT64_C(7)) << 13;
6380 // op: Qn
6381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6382 Value |= (op & UINT64_C(7)) << 17;
6383 Value |= (op & UINT64_C(8)) << 4;
6384 break;
6385 }
6386 case ARM::MVE_VCMLAf16:
6387 case ARM::MVE_VCMLAf32: {
6388 // op: Qm
6389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6390 Value |= (op & UINT64_C(8)) << 2;
6391 Value |= (op & UINT64_C(7)) << 1;
6392 // op: Qd
6393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6394 Value |= (op & UINT64_C(8)) << 19;
6395 Value |= (op & UINT64_C(7)) << 13;
6396 // op: Qn
6397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6398 Value |= (op & UINT64_C(7)) << 17;
6399 Value |= (op & UINT64_C(8)) << 4;
6400 // op: rot
6401 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6402 op &= UINT64_C(3);
6403 op <<= 23;
6404 Value |= op;
6405 break;
6406 }
6407 case ARM::MVE_VABAVs8:
6408 case ARM::MVE_VABAVs16:
6409 case ARM::MVE_VABAVs32:
6410 case ARM::MVE_VABAVu8:
6411 case ARM::MVE_VABAVu16:
6412 case ARM::MVE_VABAVu32: {
6413 // op: Qm
6414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6415 Value |= (op & UINT64_C(8)) << 2;
6416 Value |= (op & UINT64_C(7)) << 1;
6417 // op: Qn
6418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6419 Value |= (op & UINT64_C(7)) << 17;
6420 Value |= (op & UINT64_C(8)) << 4;
6421 // op: Rda
6422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6423 op &= UINT64_C(15);
6424 op <<= 12;
6425 Value |= op;
6426 break;
6427 }
6428 case ARM::MVE_VADDLVs32acc:
6429 case ARM::MVE_VADDLVu32acc: {
6430 // op: Qm
6431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6432 op &= UINT64_C(7);
6433 op <<= 1;
6434 Value |= op;
6435 // op: RdaLo
6436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6437 op &= UINT64_C(14);
6438 op <<= 12;
6439 Value |= op;
6440 // op: RdaHi
6441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6442 op &= UINT64_C(14);
6443 op <<= 19;
6444 Value |= op;
6445 break;
6446 }
6447 case ARM::MVE_VPSEL: {
6448 // op: Qn
6449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6450 Value |= (op & UINT64_C(7)) << 17;
6451 Value |= (op & UINT64_C(8)) << 4;
6452 // op: Qd
6453 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6454 Value |= (op & UINT64_C(8)) << 19;
6455 Value |= (op & UINT64_C(7)) << 13;
6456 // op: Qm
6457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6458 Value |= (op & UINT64_C(8)) << 2;
6459 Value |= (op & UINT64_C(7)) << 1;
6460 break;
6461 }
6462 case ARM::t2AUTG:
6463 case ARM::t2BXAUT: {
6464 // op: Ra
6465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6466 op &= UINT64_C(15);
6467 op <<= 12;
6468 Value |= op;
6469 // op: Rn
6470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6471 op &= UINT64_C(15);
6472 op <<= 16;
6473 Value |= op;
6474 // op: Rm
6475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6476 op &= UINT64_C(15);
6477 Value |= op;
6478 break;
6479 }
6480 case ARM::tMOVr: {
6481 // op: Rd
6482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6483 Value |= (op & UINT64_C(8)) << 4;
6484 Value |= (op & UINT64_C(7));
6485 // op: Rm
6486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6487 op &= UINT64_C(15);
6488 op <<= 3;
6489 Value |= op;
6490 break;
6491 }
6492 case ARM::t2STLEX: {
6493 // op: Rd
6494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6495 op &= UINT64_C(15);
6496 Value |= op;
6497 // op: Rt
6498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6499 op &= UINT64_C(15);
6500 op <<= 12;
6501 Value |= op;
6502 // op: addr
6503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6504 op &= UINT64_C(15);
6505 op <<= 16;
6506 Value |= op;
6507 break;
6508 }
6509 case ARM::t2STLEXB:
6510 case ARM::t2STLEXH:
6511 case ARM::t2STREXB:
6512 case ARM::t2STREXH: {
6513 // op: Rd
6514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6515 op &= UINT64_C(15);
6516 Value |= op;
6517 // op: addr
6518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6519 op &= UINT64_C(15);
6520 op <<= 16;
6521 Value |= op;
6522 // op: Rt
6523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6524 op &= UINT64_C(15);
6525 op <<= 12;
6526 Value |= op;
6527 break;
6528 }
6529 case ARM::t2STLEXD:
6530 case ARM::t2STREXD: {
6531 // op: Rd
6532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6533 op &= UINT64_C(15);
6534 Value |= op;
6535 // op: addr
6536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6537 op &= UINT64_C(15);
6538 op <<= 16;
6539 Value |= op;
6540 // op: Rt
6541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6542 op &= UINT64_C(15);
6543 op <<= 12;
6544 Value |= op;
6545 // op: Rt2
6546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6547 op &= UINT64_C(15);
6548 op <<= 8;
6549 Value |= op;
6550 break;
6551 }
6552 case ARM::CRC32B:
6553 case ARM::CRC32CB:
6554 case ARM::CRC32CH:
6555 case ARM::CRC32CW:
6556 case ARM::CRC32H:
6557 case ARM::CRC32W: {
6558 // op: Rd
6559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6560 op &= UINT64_C(15);
6561 op <<= 12;
6562 Value |= op;
6563 // op: Rn
6564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6565 op &= UINT64_C(15);
6566 op <<= 16;
6567 Value |= op;
6568 // op: Rm
6569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6570 op &= UINT64_C(15);
6571 Value |= op;
6572 break;
6573 }
6574 case ARM::t2MRS_AR:
6575 case ARM::t2MRSsys_AR: {
6576 // op: Rd
6577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6578 op &= UINT64_C(15);
6579 op <<= 8;
6580 Value |= op;
6581 break;
6582 }
6583 case ARM::t2CLZ:
6584 case ARM::t2RBIT:
6585 case ARM::t2REV:
6586 case ARM::t2REV16:
6587 case ARM::t2REVSH: {
6588 // op: Rd
6589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6590 op &= UINT64_C(15);
6591 op <<= 8;
6592 Value |= op;
6593 // op: Rm
6594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6595 Value |= (op & UINT64_C(15)) << 16;
6596 Value |= (op & UINT64_C(15));
6597 break;
6598 }
6599 case ARM::t2MOVsra_glue:
6600 case ARM::t2MOVsrl_glue: {
6601 // op: Rd
6602 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6603 op &= UINT64_C(15);
6604 op <<= 8;
6605 Value |= op;
6606 // op: Rm
6607 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6608 op &= UINT64_C(15);
6609 Value |= op;
6610 break;
6611 }
6612 case ARM::t2SXTB:
6613 case ARM::t2SXTB16:
6614 case ARM::t2SXTH:
6615 case ARM::t2UXTB:
6616 case ARM::t2UXTB16:
6617 case ARM::t2UXTH: {
6618 // op: Rd
6619 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6620 op &= UINT64_C(15);
6621 op <<= 8;
6622 Value |= op;
6623 // op: Rm
6624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6625 op &= UINT64_C(15);
6626 Value |= op;
6627 // op: rot
6628 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6629 op &= UINT64_C(3);
6630 op <<= 4;
6631 Value |= op;
6632 break;
6633 }
6634 case ARM::t2CSEL:
6635 case ARM::t2CSINC:
6636 case ARM::t2CSINV:
6637 case ARM::t2CSNEG: {
6638 // op: Rd
6639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6640 op &= UINT64_C(15);
6641 op <<= 8;
6642 Value |= op;
6643 // op: Rm
6644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6645 op &= UINT64_C(15);
6646 Value |= op;
6647 // op: Rn
6648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6649 op &= UINT64_C(15);
6650 op <<= 16;
6651 Value |= op;
6652 // op: fcond
6653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6654 op &= UINT64_C(15);
6655 op <<= 4;
6656 Value |= op;
6657 break;
6658 }
6659 case ARM::t2CRC32B:
6660 case ARM::t2CRC32CB:
6661 case ARM::t2CRC32CH:
6662 case ARM::t2CRC32CW:
6663 case ARM::t2CRC32H:
6664 case ARM::t2CRC32W:
6665 case ARM::t2MUL:
6666 case ARM::t2QADD8:
6667 case ARM::t2QADD16:
6668 case ARM::t2QASX:
6669 case ARM::t2QSAX:
6670 case ARM::t2QSUB8:
6671 case ARM::t2QSUB16:
6672 case ARM::t2SADD8:
6673 case ARM::t2SADD16:
6674 case ARM::t2SASX:
6675 case ARM::t2SDIV:
6676 case ARM::t2SEL:
6677 case ARM::t2SHADD8:
6678 case ARM::t2SHADD16:
6679 case ARM::t2SHASX:
6680 case ARM::t2SHSAX:
6681 case ARM::t2SHSUB8:
6682 case ARM::t2SHSUB16:
6683 case ARM::t2SMMUL:
6684 case ARM::t2SMMULR:
6685 case ARM::t2SMUAD:
6686 case ARM::t2SMUADX:
6687 case ARM::t2SMULBB:
6688 case ARM::t2SMULBT:
6689 case ARM::t2SMULTB:
6690 case ARM::t2SMULTT:
6691 case ARM::t2SMULWB:
6692 case ARM::t2SMULWT:
6693 case ARM::t2SMUSD:
6694 case ARM::t2SMUSDX:
6695 case ARM::t2SSAX:
6696 case ARM::t2SSUB8:
6697 case ARM::t2SSUB16:
6698 case ARM::t2UADD8:
6699 case ARM::t2UADD16:
6700 case ARM::t2UASX:
6701 case ARM::t2UDIV:
6702 case ARM::t2UHADD8:
6703 case ARM::t2UHADD16:
6704 case ARM::t2UHASX:
6705 case ARM::t2UHSAX:
6706 case ARM::t2UHSUB8:
6707 case ARM::t2UHSUB16:
6708 case ARM::t2UQADD8:
6709 case ARM::t2UQADD16:
6710 case ARM::t2UQASX:
6711 case ARM::t2UQSAX:
6712 case ARM::t2UQSUB8:
6713 case ARM::t2UQSUB16:
6714 case ARM::t2USAD8:
6715 case ARM::t2USAX:
6716 case ARM::t2USUB8:
6717 case ARM::t2USUB16: {
6718 // op: Rd
6719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6720 op &= UINT64_C(15);
6721 op <<= 8;
6722 Value |= op;
6723 // op: Rn
6724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6725 op &= UINT64_C(15);
6726 op <<= 16;
6727 Value |= op;
6728 // op: Rm
6729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6730 op &= UINT64_C(15);
6731 Value |= op;
6732 break;
6733 }
6734 case ARM::t2MLA:
6735 case ARM::t2MLS:
6736 case ARM::t2SMLABB:
6737 case ARM::t2SMLABT:
6738 case ARM::t2SMLAD:
6739 case ARM::t2SMLADX:
6740 case ARM::t2SMLATB:
6741 case ARM::t2SMLATT:
6742 case ARM::t2SMLAWB:
6743 case ARM::t2SMLAWT:
6744 case ARM::t2SMLSD:
6745 case ARM::t2SMLSDX:
6746 case ARM::t2SMMLA:
6747 case ARM::t2SMMLAR:
6748 case ARM::t2SMMLS:
6749 case ARM::t2SMMLSR:
6750 case ARM::t2USADA8: {
6751 // op: Rd
6752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6753 op &= UINT64_C(15);
6754 op <<= 8;
6755 Value |= op;
6756 // op: Rn
6757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6758 op &= UINT64_C(15);
6759 op <<= 16;
6760 Value |= op;
6761 // op: Rm
6762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6763 op &= UINT64_C(15);
6764 Value |= op;
6765 // op: Ra
6766 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6767 op &= UINT64_C(15);
6768 op <<= 12;
6769 Value |= op;
6770 break;
6771 }
6772 case ARM::t2SXTAB:
6773 case ARM::t2SXTAB16:
6774 case ARM::t2SXTAH:
6775 case ARM::t2UXTAB:
6776 case ARM::t2UXTAB16:
6777 case ARM::t2UXTAH: {
6778 // op: Rd
6779 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6780 op &= UINT64_C(15);
6781 op <<= 8;
6782 Value |= op;
6783 // op: Rn
6784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6785 op &= UINT64_C(15);
6786 op <<= 16;
6787 Value |= op;
6788 // op: Rm
6789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6790 op &= UINT64_C(15);
6791 Value |= op;
6792 // op: rot
6793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6794 op &= UINT64_C(3);
6795 op <<= 4;
6796 Value |= op;
6797 break;
6798 }
6799 case ARM::t2PKHBT:
6800 case ARM::t2PKHTB: {
6801 // op: Rd
6802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6803 op &= UINT64_C(15);
6804 op <<= 8;
6805 Value |= op;
6806 // op: Rn
6807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6808 op &= UINT64_C(15);
6809 op <<= 16;
6810 Value |= op;
6811 // op: Rm
6812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6813 op &= UINT64_C(15);
6814 Value |= op;
6815 // op: sh
6816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6817 Value |= (op & UINT64_C(28)) << 10;
6818 Value |= (op & UINT64_C(3)) << 6;
6819 break;
6820 }
6821 case ARM::t2ADDri12:
6822 case ARM::t2SUBri12: {
6823 // op: Rd
6824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6825 op &= UINT64_C(15);
6826 op <<= 8;
6827 Value |= op;
6828 // op: Rn
6829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6830 op &= UINT64_C(15);
6831 op <<= 16;
6832 Value |= op;
6833 // op: imm
6834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6835 Value |= (op & UINT64_C(2048)) << 15;
6836 Value |= (op & UINT64_C(1792)) << 4;
6837 Value |= (op & UINT64_C(255));
6838 break;
6839 }
6840 case ARM::t2QADD:
6841 case ARM::t2QDADD:
6842 case ARM::t2QDSUB:
6843 case ARM::t2QSUB: {
6844 // op: Rd
6845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6846 op &= UINT64_C(15);
6847 op <<= 8;
6848 Value |= op;
6849 // op: Rn
6850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6851 op &= UINT64_C(15);
6852 op <<= 16;
6853 Value |= op;
6854 // op: Rm
6855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6856 op &= UINT64_C(15);
6857 Value |= op;
6858 break;
6859 }
6860 case ARM::t2BFI: {
6861 // op: Rd
6862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6863 op &= UINT64_C(15);
6864 op <<= 8;
6865 Value |= op;
6866 // op: Rn
6867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6868 op &= UINT64_C(15);
6869 op <<= 16;
6870 Value |= op;
6871 // op: imm
6872 op = getBitfieldInvertedMaskOpValue(MI, Op: 3, Fixups, STI);
6873 Value |= (op & UINT64_C(28)) << 10;
6874 Value |= (op & UINT64_C(3)) << 6;
6875 Value |= (op & UINT64_C(992)) >> 5;
6876 break;
6877 }
6878 case ARM::t2SSAT16:
6879 case ARM::t2USAT16: {
6880 // op: Rd
6881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6882 op &= UINT64_C(15);
6883 op <<= 8;
6884 Value |= op;
6885 // op: Rn
6886 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6887 op &= UINT64_C(15);
6888 op <<= 16;
6889 Value |= op;
6890 // op: sat_imm
6891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6892 op &= UINT64_C(15);
6893 Value |= op;
6894 break;
6895 }
6896 case ARM::t2SSAT:
6897 case ARM::t2USAT: {
6898 // op: Rd
6899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6900 op &= UINT64_C(15);
6901 op <<= 8;
6902 Value |= op;
6903 // op: Rn
6904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6905 op &= UINT64_C(15);
6906 op <<= 16;
6907 Value |= op;
6908 // op: sat_imm
6909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6910 op &= UINT64_C(31);
6911 Value |= op;
6912 // op: sh
6913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6914 Value |= (op & UINT64_C(32)) << 16;
6915 Value |= (op & UINT64_C(28)) << 10;
6916 Value |= (op & UINT64_C(3)) << 6;
6917 break;
6918 }
6919 case ARM::t2PACG: {
6920 // op: Rd
6921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6922 op &= UINT64_C(15);
6923 op <<= 8;
6924 Value |= op;
6925 // op: Rn
6926 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6927 op &= UINT64_C(15);
6928 op <<= 16;
6929 Value |= op;
6930 // op: Rm
6931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6932 op &= UINT64_C(15);
6933 Value |= op;
6934 break;
6935 }
6936 case ARM::t2STREX: {
6937 // op: Rd
6938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6939 op &= UINT64_C(15);
6940 op <<= 8;
6941 Value |= op;
6942 // op: Rt
6943 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6944 op &= UINT64_C(15);
6945 op <<= 12;
6946 Value |= op;
6947 // op: addr
6948 op = getT2AddrModeImm0_1020s4OpValue(MI, OpIdx: 2, Fixups, STI);
6949 Value |= (op & UINT64_C(3840)) << 8;
6950 Value |= (op & UINT64_C(255));
6951 break;
6952 }
6953 case ARM::t2MRS_M: {
6954 // op: Rd
6955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6956 op &= UINT64_C(15);
6957 op <<= 8;
6958 Value |= op;
6959 // op: SYSm
6960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6961 op &= UINT64_C(255);
6962 Value |= op;
6963 break;
6964 }
6965 case ARM::t2ADR: {
6966 // op: Rd
6967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6968 op &= UINT64_C(15);
6969 op <<= 8;
6970 Value |= op;
6971 // op: addr
6972 op = getT2AdrLabelOpValue(MI, OpIdx: 1, Fixups, STI);
6973 Value |= (op & UINT64_C(2048)) << 15;
6974 Value |= (op & UINT64_C(4096)) << 11;
6975 Value |= (op & UINT64_C(4096)) << 9;
6976 Value |= (op & UINT64_C(1792)) << 4;
6977 Value |= (op & UINT64_C(255));
6978 break;
6979 }
6980 case ARM::t2BFC: {
6981 // op: Rd
6982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6983 op &= UINT64_C(15);
6984 op <<= 8;
6985 Value |= op;
6986 // op: imm
6987 op = getBitfieldInvertedMaskOpValue(MI, Op: 2, Fixups, STI);
6988 Value |= (op & UINT64_C(28)) << 10;
6989 Value |= (op & UINT64_C(3)) << 6;
6990 Value |= (op & UINT64_C(992)) >> 5;
6991 break;
6992 }
6993 case ARM::t2MOVi16: {
6994 // op: Rd
6995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6996 op &= UINT64_C(15);
6997 op <<= 8;
6998 Value |= op;
6999 // op: imm
7000 op = getHiLoImmOpValue(MI, OpIdx: 1, Fixups, STI);
7001 Value |= (op & UINT64_C(2048)) << 15;
7002 Value |= (op & UINT64_C(61440)) << 4;
7003 Value |= (op & UINT64_C(1792)) << 4;
7004 Value |= (op & UINT64_C(255));
7005 break;
7006 }
7007 case ARM::t2MOVTi16: {
7008 // op: Rd
7009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7010 op &= UINT64_C(15);
7011 op <<= 8;
7012 Value |= op;
7013 // op: imm
7014 op = getHiLoImmOpValue(MI, OpIdx: 2, Fixups, STI);
7015 Value |= (op & UINT64_C(2048)) << 15;
7016 Value |= (op & UINT64_C(61440)) << 4;
7017 Value |= (op & UINT64_C(1792)) << 4;
7018 Value |= (op & UINT64_C(255));
7019 break;
7020 }
7021 case ARM::t2SBFX:
7022 case ARM::t2UBFX: {
7023 // op: Rd
7024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7025 op &= UINT64_C(15);
7026 op <<= 8;
7027 Value |= op;
7028 // op: msb
7029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7030 op &= UINT64_C(31);
7031 Value |= op;
7032 // op: lsb
7033 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7034 Value |= (op & UINT64_C(28)) << 10;
7035 Value |= (op & UINT64_C(3)) << 6;
7036 // op: Rn
7037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7038 op &= UINT64_C(15);
7039 op <<= 16;
7040 Value |= op;
7041 break;
7042 }
7043 case ARM::tMOVSr: {
7044 // op: Rd
7045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7046 op &= UINT64_C(7);
7047 Value |= op;
7048 // op: Rm
7049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7050 op &= UINT64_C(7);
7051 op <<= 3;
7052 Value |= op;
7053 break;
7054 }
7055 case ARM::tADDi3:
7056 case ARM::tSUBi3: {
7057 // op: Rd
7058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7059 op &= UINT64_C(7);
7060 Value |= op;
7061 // op: Rm
7062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7063 op &= UINT64_C(7);
7064 op <<= 3;
7065 Value |= op;
7066 // op: imm3
7067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7068 op &= UINT64_C(7);
7069 op <<= 6;
7070 Value |= op;
7071 break;
7072 }
7073 case ARM::tASRri:
7074 case ARM::tLSLri:
7075 case ARM::tLSRri: {
7076 // op: Rd
7077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7078 op &= UINT64_C(7);
7079 Value |= op;
7080 // op: Rm
7081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7082 op &= UINT64_C(7);
7083 op <<= 3;
7084 Value |= op;
7085 // op: imm5
7086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7087 op &= UINT64_C(31);
7088 op <<= 6;
7089 Value |= op;
7090 break;
7091 }
7092 case ARM::tMUL:
7093 case ARM::tMVN:
7094 case ARM::tRSB: {
7095 // op: Rd
7096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7097 op &= UINT64_C(7);
7098 Value |= op;
7099 // op: Rn
7100 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7101 op &= UINT64_C(7);
7102 op <<= 3;
7103 Value |= op;
7104 break;
7105 }
7106 case ARM::tADR: {
7107 // op: Rd
7108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7109 op &= UINT64_C(7);
7110 op <<= 8;
7111 Value |= op;
7112 // op: addr
7113 op = getThumbAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI);
7114 op &= UINT64_C(255);
7115 Value |= op;
7116 break;
7117 }
7118 case ARM::tMOVi8: {
7119 // op: Rd
7120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7121 op &= UINT64_C(7);
7122 op <<= 8;
7123 Value |= op;
7124 // op: imm8
7125 op = getHiLoImmOpValue(MI, OpIdx: 2, Fixups, STI);
7126 op &= UINT64_C(255);
7127 Value |= op;
7128 break;
7129 }
7130 case ARM::t2SMLALD:
7131 case ARM::t2SMLALDX:
7132 case ARM::t2SMLSLD:
7133 case ARM::t2SMLSLDX: {
7134 // op: Rd
7135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7136 op &= UINT64_C(15);
7137 op <<= 8;
7138 Value |= op;
7139 // op: Rn
7140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7141 op &= UINT64_C(15);
7142 op <<= 16;
7143 Value |= op;
7144 // op: Rm
7145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7146 op &= UINT64_C(15);
7147 Value |= op;
7148 // op: Ra
7149 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7150 op &= UINT64_C(15);
7151 op <<= 12;
7152 Value |= op;
7153 break;
7154 }
7155 case ARM::t2SMLAL:
7156 case ARM::t2SMLALBB:
7157 case ARM::t2SMLALBT:
7158 case ARM::t2SMLALTB:
7159 case ARM::t2SMLALTT:
7160 case ARM::t2SMULL:
7161 case ARM::t2UMAAL:
7162 case ARM::t2UMLAL:
7163 case ARM::t2UMULL: {
7164 // op: RdLo
7165 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7166 op &= UINT64_C(15);
7167 op <<= 12;
7168 Value |= op;
7169 // op: RdHi
7170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7171 op &= UINT64_C(15);
7172 op <<= 8;
7173 Value |= op;
7174 // op: Rn
7175 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7176 op &= UINT64_C(15);
7177 op <<= 16;
7178 Value |= op;
7179 // op: Rm
7180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7181 op &= UINT64_C(15);
7182 Value |= op;
7183 break;
7184 }
7185 case ARM::MVE_VMLADAVs8:
7186 case ARM::MVE_VMLADAVs16:
7187 case ARM::MVE_VMLADAVs32:
7188 case ARM::MVE_VMLADAVu8:
7189 case ARM::MVE_VMLADAVu16:
7190 case ARM::MVE_VMLADAVu32:
7191 case ARM::MVE_VMLADAVxs8:
7192 case ARM::MVE_VMLADAVxs16:
7193 case ARM::MVE_VMLADAVxs32:
7194 case ARM::MVE_VMLSDAVs8:
7195 case ARM::MVE_VMLSDAVs16:
7196 case ARM::MVE_VMLSDAVs32:
7197 case ARM::MVE_VMLSDAVxs8:
7198 case ARM::MVE_VMLSDAVxs16:
7199 case ARM::MVE_VMLSDAVxs32: {
7200 // op: RdaDest
7201 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7202 op &= UINT64_C(14);
7203 op <<= 12;
7204 Value |= op;
7205 // op: Qm
7206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7207 op &= UINT64_C(7);
7208 op <<= 1;
7209 Value |= op;
7210 // op: Qn
7211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7212 op &= UINT64_C(7);
7213 op <<= 17;
7214 Value |= op;
7215 break;
7216 }
7217 case ARM::MVE_VMLADAVas8:
7218 case ARM::MVE_VMLADAVas16:
7219 case ARM::MVE_VMLADAVas32:
7220 case ARM::MVE_VMLADAVau8:
7221 case ARM::MVE_VMLADAVau16:
7222 case ARM::MVE_VMLADAVau32:
7223 case ARM::MVE_VMLADAVaxs8:
7224 case ARM::MVE_VMLADAVaxs16:
7225 case ARM::MVE_VMLADAVaxs32:
7226 case ARM::MVE_VMLSDAVas8:
7227 case ARM::MVE_VMLSDAVas16:
7228 case ARM::MVE_VMLSDAVas32:
7229 case ARM::MVE_VMLSDAVaxs8:
7230 case ARM::MVE_VMLSDAVaxs16:
7231 case ARM::MVE_VMLSDAVaxs32: {
7232 // op: RdaDest
7233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7234 op &= UINT64_C(14);
7235 op <<= 12;
7236 Value |= op;
7237 // op: Qm
7238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7239 op &= UINT64_C(7);
7240 op <<= 1;
7241 Value |= op;
7242 // op: Qn
7243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7244 op &= UINT64_C(7);
7245 op <<= 17;
7246 Value |= op;
7247 break;
7248 }
7249 case ARM::MVE_SQRSHR:
7250 case ARM::MVE_UQRSHL: {
7251 // op: RdaDest
7252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7253 op &= UINT64_C(15);
7254 op <<= 16;
7255 Value |= op;
7256 // op: Rm
7257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7258 op &= UINT64_C(15);
7259 op <<= 12;
7260 Value |= op;
7261 break;
7262 }
7263 case ARM::MVE_SQSHL:
7264 case ARM::MVE_SRSHR:
7265 case ARM::MVE_UQSHL:
7266 case ARM::MVE_URSHR: {
7267 // op: RdaDest
7268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7269 op &= UINT64_C(15);
7270 op <<= 16;
7271 Value |= op;
7272 // op: imm
7273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7274 Value |= (op & UINT64_C(28)) << 10;
7275 Value |= (op & UINT64_C(3)) << 6;
7276 break;
7277 }
7278 case ARM::MVE_ASRLr:
7279 case ARM::MVE_LSLLr: {
7280 // op: RdaLo
7281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7282 op &= UINT64_C(14);
7283 op <<= 16;
7284 Value |= op;
7285 // op: RdaHi
7286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7287 op &= UINT64_C(14);
7288 op <<= 8;
7289 Value |= op;
7290 // op: Rm
7291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7292 op &= UINT64_C(15);
7293 op <<= 12;
7294 Value |= op;
7295 break;
7296 }
7297 case ARM::MVE_SQRSHRL:
7298 case ARM::MVE_UQRSHLL: {
7299 // op: RdaLo
7300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7301 op &= UINT64_C(14);
7302 op <<= 16;
7303 Value |= op;
7304 // op: RdaHi
7305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7306 op &= UINT64_C(14);
7307 op <<= 8;
7308 Value |= op;
7309 // op: Rm
7310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7311 op &= UINT64_C(15);
7312 op <<= 12;
7313 Value |= op;
7314 // op: sat
7315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
7316 op &= UINT64_C(1);
7317 op <<= 7;
7318 Value |= op;
7319 break;
7320 }
7321 case ARM::MVE_ASRLi:
7322 case ARM::MVE_LSLLi:
7323 case ARM::MVE_LSRL:
7324 case ARM::MVE_SQSHLL:
7325 case ARM::MVE_SRSHRL:
7326 case ARM::MVE_UQSHLL:
7327 case ARM::MVE_URSHRL: {
7328 // op: RdaLo
7329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7330 op &= UINT64_C(14);
7331 op <<= 16;
7332 Value |= op;
7333 // op: RdaHi
7334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7335 op &= UINT64_C(14);
7336 op <<= 8;
7337 Value |= op;
7338 // op: imm
7339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7340 Value |= (op & UINT64_C(28)) << 10;
7341 Value |= (op & UINT64_C(3)) << 6;
7342 break;
7343 }
7344 case ARM::MVE_VMLALDAVs16:
7345 case ARM::MVE_VMLALDAVs32:
7346 case ARM::MVE_VMLALDAVu16:
7347 case ARM::MVE_VMLALDAVu32:
7348 case ARM::MVE_VMLALDAVxs16:
7349 case ARM::MVE_VMLALDAVxs32:
7350 case ARM::MVE_VMLSLDAVs16:
7351 case ARM::MVE_VMLSLDAVs32:
7352 case ARM::MVE_VMLSLDAVxs16:
7353 case ARM::MVE_VMLSLDAVxs32:
7354 case ARM::MVE_VRMLALDAVHs32:
7355 case ARM::MVE_VRMLALDAVHu32:
7356 case ARM::MVE_VRMLALDAVHxs32:
7357 case ARM::MVE_VRMLSLDAVHs32:
7358 case ARM::MVE_VRMLSLDAVHxs32: {
7359 // op: RdaLoDest
7360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7361 op &= UINT64_C(14);
7362 op <<= 12;
7363 Value |= op;
7364 // op: RdaHiDest
7365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7366 op &= UINT64_C(14);
7367 op <<= 19;
7368 Value |= op;
7369 // op: Qm
7370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7371 op &= UINT64_C(7);
7372 op <<= 1;
7373 Value |= op;
7374 // op: Qn
7375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7376 op &= UINT64_C(7);
7377 op <<= 17;
7378 Value |= op;
7379 break;
7380 }
7381 case ARM::MVE_VMLALDAVas16:
7382 case ARM::MVE_VMLALDAVas32:
7383 case ARM::MVE_VMLALDAVau16:
7384 case ARM::MVE_VMLALDAVau32:
7385 case ARM::MVE_VMLALDAVaxs16:
7386 case ARM::MVE_VMLALDAVaxs32:
7387 case ARM::MVE_VMLSLDAVas16:
7388 case ARM::MVE_VMLSLDAVas32:
7389 case ARM::MVE_VMLSLDAVaxs16:
7390 case ARM::MVE_VMLSLDAVaxs32:
7391 case ARM::MVE_VRMLALDAVHas32:
7392 case ARM::MVE_VRMLALDAVHau32:
7393 case ARM::MVE_VRMLALDAVHaxs32:
7394 case ARM::MVE_VRMLSLDAVHas32:
7395 case ARM::MVE_VRMLSLDAVHaxs32: {
7396 // op: RdaLoDest
7397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7398 op &= UINT64_C(14);
7399 op <<= 12;
7400 Value |= op;
7401 // op: RdaHiDest
7402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7403 op &= UINT64_C(14);
7404 op <<= 19;
7405 Value |= op;
7406 // op: Qm
7407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
7408 op &= UINT64_C(7);
7409 op <<= 1;
7410 Value |= op;
7411 // op: Qn
7412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7413 op &= UINT64_C(7);
7414 op <<= 17;
7415 Value |= op;
7416 break;
7417 }
7418 case ARM::tADDrSP: {
7419 // op: Rdn
7420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7421 Value |= (op & UINT64_C(8)) << 4;
7422 Value |= (op & UINT64_C(7));
7423 break;
7424 }
7425 case ARM::tADDhirr: {
7426 // op: Rdn
7427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7428 Value |= (op & UINT64_C(8)) << 4;
7429 Value |= (op & UINT64_C(7));
7430 // op: Rm
7431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7432 op &= UINT64_C(15);
7433 op <<= 3;
7434 Value |= op;
7435 break;
7436 }
7437 case ARM::tADC:
7438 case ARM::tAND:
7439 case ARM::tASRrr:
7440 case ARM::tBIC:
7441 case ARM::tEOR:
7442 case ARM::tLSLrr:
7443 case ARM::tLSRrr:
7444 case ARM::tORR:
7445 case ARM::tROR:
7446 case ARM::tSBC: {
7447 // op: Rdn
7448 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7449 op &= UINT64_C(7);
7450 Value |= op;
7451 // op: Rm
7452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7453 op &= UINT64_C(7);
7454 op <<= 3;
7455 Value |= op;
7456 break;
7457 }
7458 case ARM::tADDi8: {
7459 // op: Rdn
7460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7461 op &= UINT64_C(7);
7462 op <<= 8;
7463 Value |= op;
7464 // op: imm8
7465 op = getHiLoImmOpValue(MI, OpIdx: 3, Fixups, STI);
7466 op &= UINT64_C(255);
7467 Value |= op;
7468 break;
7469 }
7470 case ARM::tSUBi8: {
7471 // op: Rdn
7472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7473 op &= UINT64_C(7);
7474 op <<= 8;
7475 Value |= op;
7476 // op: imm8
7477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7478 op &= UINT64_C(255);
7479 Value |= op;
7480 break;
7481 }
7482 case ARM::tBX:
7483 case ARM::tBXNS: {
7484 // op: Rm
7485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7486 op &= UINT64_C(15);
7487 op <<= 3;
7488 Value |= op;
7489 break;
7490 }
7491 case ARM::tCMPhir: {
7492 // op: Rm
7493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7494 op &= UINT64_C(15);
7495 op <<= 3;
7496 Value |= op;
7497 // op: Rn
7498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7499 Value |= (op & UINT64_C(8)) << 4;
7500 Value |= (op & UINT64_C(7));
7501 break;
7502 }
7503 case ARM::tREV:
7504 case ARM::tREV16:
7505 case ARM::tREVSH:
7506 case ARM::tSXTB:
7507 case ARM::tSXTH:
7508 case ARM::tUXTB:
7509 case ARM::tUXTH: {
7510 // op: Rm
7511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7512 op &= UINT64_C(7);
7513 op <<= 3;
7514 Value |= op;
7515 // op: Rd
7516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7517 op &= UINT64_C(7);
7518 Value |= op;
7519 break;
7520 }
7521 case ARM::tCMNz:
7522 case ARM::tCMPr:
7523 case ARM::tTST: {
7524 // op: Rm
7525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7526 op &= UINT64_C(7);
7527 op <<= 3;
7528 Value |= op;
7529 // op: Rn
7530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7531 op &= UINT64_C(7);
7532 Value |= op;
7533 break;
7534 }
7535 case ARM::tADDspr: {
7536 // op: Rm
7537 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7538 op &= UINT64_C(15);
7539 op <<= 3;
7540 Value |= op;
7541 break;
7542 }
7543 case ARM::tADDrr:
7544 case ARM::tSUBrr: {
7545 // op: Rm
7546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7547 op &= UINT64_C(7);
7548 op <<= 6;
7549 Value |= op;
7550 // op: Rn
7551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7552 op &= UINT64_C(7);
7553 op <<= 3;
7554 Value |= op;
7555 // op: Rd
7556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7557 op &= UINT64_C(7);
7558 Value |= op;
7559 break;
7560 }
7561 case ARM::RFEDA:
7562 case ARM::RFEDA_UPD:
7563 case ARM::RFEDB:
7564 case ARM::RFEDB_UPD:
7565 case ARM::RFEIA:
7566 case ARM::RFEIA_UPD:
7567 case ARM::RFEIB:
7568 case ARM::RFEIB_UPD:
7569 case ARM::VLLDM:
7570 case ARM::VLLDM_T2:
7571 case ARM::VLSTM:
7572 case ARM::VLSTM_T2:
7573 case ARM::t2RFEDB:
7574 case ARM::t2RFEDBW:
7575 case ARM::t2RFEIA:
7576 case ARM::t2RFEIAW: {
7577 // op: Rn
7578 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7579 op &= UINT64_C(15);
7580 op <<= 16;
7581 Value |= op;
7582 break;
7583 }
7584 case ARM::t2CMNzrr:
7585 case ARM::t2CMPrr:
7586 case ARM::t2TBB:
7587 case ARM::t2TBH:
7588 case ARM::t2TEQrr:
7589 case ARM::t2TSTrr: {
7590 // op: Rn
7591 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7592 op &= UINT64_C(15);
7593 op <<= 16;
7594 Value |= op;
7595 // op: Rm
7596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7597 op &= UINT64_C(15);
7598 Value |= op;
7599 break;
7600 }
7601 case ARM::t2CMNzrs:
7602 case ARM::t2CMPrs:
7603 case ARM::t2TEQrs:
7604 case ARM::t2TSTrs: {
7605 // op: Rn
7606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7607 op &= UINT64_C(15);
7608 op <<= 16;
7609 Value |= op;
7610 // op: ShiftedRm
7611 op = getT2SORegOpValue(MI, OpIdx: 1, Fixups, STI);
7612 Value |= (op & UINT64_C(3584)) << 3;
7613 Value |= (op & UINT64_C(480)) >> 1;
7614 Value |= (op & UINT64_C(15));
7615 break;
7616 }
7617 case ARM::t2CMNri:
7618 case ARM::t2CMPri:
7619 case ARM::t2TEQri:
7620 case ARM::t2TSTri: {
7621 // op: Rn
7622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7623 op &= UINT64_C(15);
7624 op <<= 16;
7625 Value |= op;
7626 // op: imm
7627 op = getT2SOImmOpValue(MI, Op: 1, Fixups, STI);
7628 Value |= (op & UINT64_C(2048)) << 15;
7629 Value |= (op & UINT64_C(1792)) << 4;
7630 Value |= (op & UINT64_C(255));
7631 break;
7632 }
7633 case ARM::t2STMDB:
7634 case ARM::t2STMIA: {
7635 // op: Rn
7636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7637 op &= UINT64_C(15);
7638 op <<= 16;
7639 Value |= op;
7640 // op: regs
7641 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
7642 Value |= (op & UINT64_C(16384));
7643 Value |= (op & UINT64_C(8191));
7644 break;
7645 }
7646 case ARM::t2LDMDB:
7647 case ARM::t2LDMIA: {
7648 // op: Rn
7649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7650 op &= UINT64_C(15);
7651 op <<= 16;
7652 Value |= op;
7653 // op: regs
7654 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
7655 op &= UINT64_C(65535);
7656 Value |= op;
7657 break;
7658 }
7659 case ARM::tCMPi8: {
7660 // op: Rn
7661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7662 op &= UINT64_C(7);
7663 op <<= 8;
7664 Value |= op;
7665 // op: imm8
7666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7667 op &= UINT64_C(255);
7668 Value |= op;
7669 break;
7670 }
7671 case ARM::tLDMIA: {
7672 // op: Rn
7673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7674 op &= UINT64_C(7);
7675 op <<= 8;
7676 Value |= op;
7677 // op: regs
7678 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
7679 op &= UINT64_C(255);
7680 Value |= op;
7681 break;
7682 }
7683 case ARM::MVE_DLSTP_8:
7684 case ARM::MVE_DLSTP_16:
7685 case ARM::MVE_DLSTP_32:
7686 case ARM::MVE_DLSTP_64:
7687 case ARM::MVE_VCTP8:
7688 case ARM::MVE_VCTP16:
7689 case ARM::MVE_VCTP32:
7690 case ARM::MVE_VCTP64:
7691 case ARM::t2DLS: {
7692 // op: Rn
7693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7694 op &= UINT64_C(15);
7695 op <<= 16;
7696 Value |= op;
7697 break;
7698 }
7699 case ARM::t2TT:
7700 case ARM::t2TTA:
7701 case ARM::t2TTAT:
7702 case ARM::t2TTT: {
7703 // op: Rn
7704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7705 op &= UINT64_C(15);
7706 op <<= 16;
7707 Value |= op;
7708 // op: Rt
7709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7710 op &= UINT64_C(15);
7711 op <<= 8;
7712 Value |= op;
7713 break;
7714 }
7715 case ARM::MVE_WLSTP_8:
7716 case ARM::MVE_WLSTP_16:
7717 case ARM::MVE_WLSTP_32:
7718 case ARM::MVE_WLSTP_64:
7719 case ARM::t2WLS: {
7720 // op: Rn
7721 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7722 op &= UINT64_C(15);
7723 op <<= 16;
7724 Value |= op;
7725 // op: label
7726 op = getBFTargetOpValue<false, ARM::fixup_wls>(MI, OpIdx: 2, Fixups, STI);
7727 Value |= (op & UINT64_C(1)) << 11;
7728 Value |= (op & UINT64_C(2046));
7729 break;
7730 }
7731 case ARM::t2STMDB_UPD:
7732 case ARM::t2STMIA_UPD: {
7733 // op: Rn
7734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7735 op &= UINT64_C(15);
7736 op <<= 16;
7737 Value |= op;
7738 // op: regs
7739 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
7740 Value |= (op & UINT64_C(16384));
7741 Value |= (op & UINT64_C(8191));
7742 break;
7743 }
7744 case ARM::t2LDMDB_UPD:
7745 case ARM::t2LDMIA_UPD: {
7746 // op: Rn
7747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7748 op &= UINT64_C(15);
7749 op <<= 16;
7750 Value |= op;
7751 // op: regs
7752 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
7753 op &= UINT64_C(65535);
7754 Value |= op;
7755 break;
7756 }
7757 case ARM::tSTMIA_UPD: {
7758 // op: Rn
7759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7760 op &= UINT64_C(7);
7761 op <<= 8;
7762 Value |= op;
7763 // op: regs
7764 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
7765 op &= UINT64_C(255);
7766 Value |= op;
7767 break;
7768 }
7769 case ARM::MVE_VMOV_rr_q: {
7770 // op: Rt
7771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7772 op &= UINT64_C(15);
7773 Value |= op;
7774 // op: Rt2
7775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7776 op &= UINT64_C(15);
7777 op <<= 16;
7778 Value |= op;
7779 // op: Qd
7780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7781 Value |= (op & UINT64_C(8)) << 19;
7782 Value |= (op & UINT64_C(7)) << 13;
7783 // op: idx2
7784 op = getMVEPairVectorIndexOpValue<0>(MI, OpIdx: 4, Fixups, STI);
7785 op &= UINT64_C(1);
7786 op <<= 4;
7787 Value |= op;
7788 break;
7789 }
7790 case ARM::t2LDRB_POST:
7791 case ARM::t2LDRH_POST:
7792 case ARM::t2LDRSB_POST:
7793 case ARM::t2LDRSH_POST:
7794 case ARM::t2LDR_POST: {
7795 // op: Rt
7796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7797 op &= UINT64_C(15);
7798 op <<= 12;
7799 Value |= op;
7800 // op: Rn
7801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7802 op &= UINT64_C(15);
7803 op <<= 16;
7804 Value |= op;
7805 // op: offset
7806 op = getT2AddrModeImm8OffsetOpValue(MI, OpNum: 3, Fixups, STI);
7807 Value |= (op & UINT64_C(256)) << 1;
7808 Value |= (op & UINT64_C(255));
7809 break;
7810 }
7811 case ARM::MRRC2:
7812 case ARM::t2MRRC:
7813 case ARM::t2MRRC2: {
7814 // op: Rt
7815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7816 op &= UINT64_C(15);
7817 op <<= 12;
7818 Value |= op;
7819 // op: Rt2
7820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7821 op &= UINT64_C(15);
7822 op <<= 16;
7823 Value |= op;
7824 // op: cop
7825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7826 op &= UINT64_C(15);
7827 op <<= 8;
7828 Value |= op;
7829 // op: opc1
7830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7831 op &= UINT64_C(15);
7832 op <<= 4;
7833 Value |= op;
7834 // op: CRm
7835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7836 op &= UINT64_C(15);
7837 Value |= op;
7838 break;
7839 }
7840 case ARM::t2LDRD_POST: {
7841 // op: Rt
7842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7843 op &= UINT64_C(15);
7844 op <<= 12;
7845 Value |= op;
7846 // op: Rt2
7847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7848 op &= UINT64_C(15);
7849 op <<= 8;
7850 Value |= op;
7851 // op: addr
7852 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7853 op &= UINT64_C(15);
7854 op <<= 16;
7855 Value |= op;
7856 // op: imm
7857 op = getT2ScaledImmOpValue<8,2>(MI, OpIdx: 4, Fixups, STI);
7858 Value |= (op & UINT64_C(256)) << 15;
7859 Value |= (op & UINT64_C(255));
7860 break;
7861 }
7862 case ARM::t2LDRDi8:
7863 case ARM::t2STRDi8: {
7864 // op: Rt
7865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7866 op &= UINT64_C(15);
7867 op <<= 12;
7868 Value |= op;
7869 // op: Rt2
7870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7871 op &= UINT64_C(15);
7872 op <<= 8;
7873 Value |= op;
7874 // op: addr
7875 op = getT2AddrModeImm8s4OpValue(MI, OpIdx: 2, Fixups, STI);
7876 Value |= (op & UINT64_C(256)) << 15;
7877 Value |= (op & UINT64_C(7680)) << 7;
7878 Value |= (op & UINT64_C(255));
7879 break;
7880 }
7881 case ARM::t2LDRD_PRE: {
7882 // op: Rt
7883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7884 op &= UINT64_C(15);
7885 op <<= 12;
7886 Value |= op;
7887 // op: Rt2
7888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7889 op &= UINT64_C(15);
7890 op <<= 8;
7891 Value |= op;
7892 // op: addr
7893 op = getT2AddrModeImm8s4OpValue(MI, OpIdx: 3, Fixups, STI);
7894 Value |= (op & UINT64_C(256)) << 15;
7895 Value |= (op & UINT64_C(7680)) << 7;
7896 Value |= (op & UINT64_C(255));
7897 break;
7898 }
7899 case ARM::t2LDRBi12:
7900 case ARM::t2LDRHi12:
7901 case ARM::t2LDRSBi12:
7902 case ARM::t2LDRSHi12:
7903 case ARM::t2LDRi12:
7904 case ARM::t2STRBi12:
7905 case ARM::t2STRHi12:
7906 case ARM::t2STRi12: {
7907 // op: Rt
7908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7909 op &= UINT64_C(15);
7910 op <<= 12;
7911 Value |= op;
7912 // op: addr
7913 op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI);
7914 Value |= (op & UINT64_C(122880)) << 3;
7915 Value |= (op & UINT64_C(4095));
7916 break;
7917 }
7918 case ARM::t2LDRBpci:
7919 case ARM::t2LDRHpci:
7920 case ARM::t2LDRSBpci:
7921 case ARM::t2LDRSHpci:
7922 case ARM::t2LDRpci: {
7923 // op: Rt
7924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7925 op &= UINT64_C(15);
7926 op <<= 12;
7927 Value |= op;
7928 // op: addr
7929 op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI);
7930 Value |= (op & UINT64_C(4096)) << 11;
7931 Value |= (op & UINT64_C(4095));
7932 break;
7933 }
7934 case ARM::t2LDA:
7935 case ARM::t2LDAB:
7936 case ARM::t2LDAEX:
7937 case ARM::t2LDAH:
7938 case ARM::t2STL:
7939 case ARM::t2STLB:
7940 case ARM::t2STLH: {
7941 // op: Rt
7942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7943 op &= UINT64_C(15);
7944 op <<= 12;
7945 Value |= op;
7946 // op: addr
7947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7948 op &= UINT64_C(15);
7949 op <<= 16;
7950 Value |= op;
7951 break;
7952 }
7953 case ARM::t2LDREX: {
7954 // op: Rt
7955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7956 op &= UINT64_C(15);
7957 op <<= 12;
7958 Value |= op;
7959 // op: addr
7960 op = getT2AddrModeImm0_1020s4OpValue(MI, OpIdx: 1, Fixups, STI);
7961 Value |= (op & UINT64_C(3840)) << 8;
7962 Value |= (op & UINT64_C(255));
7963 break;
7964 }
7965 case ARM::t2LDRBT:
7966 case ARM::t2LDRHT:
7967 case ARM::t2LDRSBT:
7968 case ARM::t2LDRSHT:
7969 case ARM::t2LDRT:
7970 case ARM::t2STRBT:
7971 case ARM::t2STRHT:
7972 case ARM::t2STRT: {
7973 // op: Rt
7974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7975 op &= UINT64_C(15);
7976 op <<= 12;
7977 Value |= op;
7978 // op: addr
7979 op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 1, Fixups, STI);
7980 Value |= (op & UINT64_C(7680)) << 7;
7981 Value |= (op & UINT64_C(255));
7982 break;
7983 }
7984 case ARM::t2LDRBi8:
7985 case ARM::t2LDRHi8:
7986 case ARM::t2LDRSBi8:
7987 case ARM::t2LDRSHi8:
7988 case ARM::t2LDRi8:
7989 case ARM::t2STRBi8:
7990 case ARM::t2STRHi8:
7991 case ARM::t2STRi8: {
7992 // op: Rt
7993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7994 op &= UINT64_C(15);
7995 op <<= 12;
7996 Value |= op;
7997 // op: addr
7998 op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 1, Fixups, STI);
7999 Value |= (op & UINT64_C(7680)) << 7;
8000 Value |= (op & UINT64_C(256)) << 1;
8001 Value |= (op & UINT64_C(255));
8002 break;
8003 }
8004 case ARM::t2LDRB_PRE:
8005 case ARM::t2LDRH_PRE:
8006 case ARM::t2LDRSB_PRE:
8007 case ARM::t2LDRSH_PRE:
8008 case ARM::t2LDR_PRE: {
8009 // op: Rt
8010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8011 op &= UINT64_C(15);
8012 op <<= 12;
8013 Value |= op;
8014 // op: addr
8015 op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 2, Fixups, STI);
8016 Value |= (op & UINT64_C(7680)) << 7;
8017 Value |= (op & UINT64_C(256)) << 1;
8018 Value |= (op & UINT64_C(255));
8019 break;
8020 }
8021 case ARM::t2LDRBs:
8022 case ARM::t2LDRHs:
8023 case ARM::t2LDRSBs:
8024 case ARM::t2LDRSHs:
8025 case ARM::t2LDRs:
8026 case ARM::t2STRBs:
8027 case ARM::t2STRHs:
8028 case ARM::t2STRs: {
8029 // op: Rt
8030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8031 op &= UINT64_C(15);
8032 op <<= 12;
8033 Value |= op;
8034 // op: addr
8035 op = getT2AddrModeSORegOpValue(MI, OpNum: 1, Fixups, STI);
8036 Value |= (op & UINT64_C(960)) << 10;
8037 Value |= (op & UINT64_C(3)) << 4;
8038 Value |= (op & UINT64_C(60)) >> 2;
8039 break;
8040 }
8041 case ARM::MRC2:
8042 case ARM::t2MRC:
8043 case ARM::t2MRC2: {
8044 // op: Rt
8045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8046 op &= UINT64_C(15);
8047 op <<= 12;
8048 Value |= op;
8049 // op: cop
8050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8051 op &= UINT64_C(15);
8052 op <<= 8;
8053 Value |= op;
8054 // op: opc1
8055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8056 op &= UINT64_C(7);
8057 op <<= 21;
8058 Value |= op;
8059 // op: opc2
8060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
8061 op &= UINT64_C(7);
8062 op <<= 5;
8063 Value |= op;
8064 // op: CRm
8065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8066 op &= UINT64_C(15);
8067 Value |= op;
8068 // op: CRn
8069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8070 op &= UINT64_C(15);
8071 op <<= 16;
8072 Value |= op;
8073 break;
8074 }
8075 case ARM::tLDRBi:
8076 case ARM::tLDRHi:
8077 case ARM::tLDRi:
8078 case ARM::tSTRBi:
8079 case ARM::tSTRHi:
8080 case ARM::tSTRi: {
8081 // op: Rt
8082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8083 op &= UINT64_C(7);
8084 Value |= op;
8085 // op: addr
8086 op = getAddrModeISOpValue(MI, OpIdx: 1, Fixups, STI);
8087 op &= UINT64_C(255);
8088 op <<= 3;
8089 Value |= op;
8090 break;
8091 }
8092 case ARM::tLDRBr:
8093 case ARM::tLDRHr:
8094 case ARM::tLDRSB:
8095 case ARM::tLDRSH:
8096 case ARM::tLDRr:
8097 case ARM::tSTRBr:
8098 case ARM::tSTRHr:
8099 case ARM::tSTRr: {
8100 // op: Rt
8101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8102 op &= UINT64_C(7);
8103 Value |= op;
8104 // op: addr
8105 op = getThumbAddrModeRegRegOpValue(MI, OpIdx: 1, Fixups, STI);
8106 op &= UINT64_C(63);
8107 op <<= 3;
8108 Value |= op;
8109 break;
8110 }
8111 case ARM::tLDRpci: {
8112 // op: Rt
8113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8114 op &= UINT64_C(7);
8115 op <<= 8;
8116 Value |= op;
8117 // op: addr
8118 op = getAddrModePCOpValue(MI, OpIdx: 1, Fixups, STI);
8119 op &= UINT64_C(255);
8120 Value |= op;
8121 break;
8122 }
8123 case ARM::tLDRspi:
8124 case ARM::tSTRspi: {
8125 // op: Rt
8126 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8127 op &= UINT64_C(7);
8128 op <<= 8;
8129 Value |= op;
8130 // op: addr
8131 op = getAddrModeThumbSPOpValue(MI, OpIdx: 1, Fixups, STI);
8132 op &= UINT64_C(255);
8133 Value |= op;
8134 break;
8135 }
8136 case ARM::t2STRB_POST:
8137 case ARM::t2STRH_POST:
8138 case ARM::t2STR_POST: {
8139 // op: Rt
8140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8141 op &= UINT64_C(15);
8142 op <<= 12;
8143 Value |= op;
8144 // op: Rn
8145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8146 op &= UINT64_C(15);
8147 op <<= 16;
8148 Value |= op;
8149 // op: offset
8150 op = getT2AddrModeImm8OffsetOpValue(MI, OpNum: 3, Fixups, STI);
8151 Value |= (op & UINT64_C(256)) << 1;
8152 Value |= (op & UINT64_C(255));
8153 break;
8154 }
8155 case ARM::t2STRD_POST: {
8156 // op: Rt
8157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8158 op &= UINT64_C(15);
8159 op <<= 12;
8160 Value |= op;
8161 // op: Rt2
8162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8163 op &= UINT64_C(15);
8164 op <<= 8;
8165 Value |= op;
8166 // op: addr
8167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8168 op &= UINT64_C(15);
8169 op <<= 16;
8170 Value |= op;
8171 // op: imm
8172 op = getT2ScaledImmOpValue<8,2>(MI, OpIdx: 4, Fixups, STI);
8173 Value |= (op & UINT64_C(256)) << 15;
8174 Value |= (op & UINT64_C(255));
8175 break;
8176 }
8177 case ARM::t2STRD_PRE: {
8178 // op: Rt
8179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8180 op &= UINT64_C(15);
8181 op <<= 12;
8182 Value |= op;
8183 // op: Rt2
8184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8185 op &= UINT64_C(15);
8186 op <<= 8;
8187 Value |= op;
8188 // op: addr
8189 op = getT2AddrModeImm8s4OpValue(MI, OpIdx: 3, Fixups, STI);
8190 Value |= (op & UINT64_C(256)) << 15;
8191 Value |= (op & UINT64_C(7680)) << 7;
8192 Value |= (op & UINT64_C(255));
8193 break;
8194 }
8195 case ARM::t2STRB_PRE:
8196 case ARM::t2STRH_PRE:
8197 case ARM::t2STR_PRE: {
8198 // op: Rt
8199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8200 op &= UINT64_C(15);
8201 op <<= 12;
8202 Value |= op;
8203 // op: addr
8204 op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 2, Fixups, STI);
8205 Value |= (op & UINT64_C(7680)) << 7;
8206 Value |= (op & UINT64_C(256)) << 1;
8207 Value |= (op & UINT64_C(255));
8208 break;
8209 }
8210 case ARM::MVE_VMOV_q_rr: {
8211 // op: Rt
8212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8213 op &= UINT64_C(15);
8214 Value |= op;
8215 // op: Rt2
8216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8217 op &= UINT64_C(15);
8218 op <<= 16;
8219 Value |= op;
8220 // op: Qd
8221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8222 Value |= (op & UINT64_C(8)) << 19;
8223 Value |= (op & UINT64_C(7)) << 13;
8224 // op: idx2
8225 op = getMVEPairVectorIndexOpValue<0>(MI, OpIdx: 5, Fixups, STI);
8226 op &= UINT64_C(1);
8227 op <<= 4;
8228 Value |= op;
8229 break;
8230 }
8231 case ARM::MCRR2:
8232 case ARM::t2MCRR:
8233 case ARM::t2MCRR2: {
8234 // op: Rt
8235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8236 op &= UINT64_C(15);
8237 op <<= 12;
8238 Value |= op;
8239 // op: Rt2
8240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8241 op &= UINT64_C(15);
8242 op <<= 16;
8243 Value |= op;
8244 // op: cop
8245 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8246 op &= UINT64_C(15);
8247 op <<= 8;
8248 Value |= op;
8249 // op: opc1
8250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8251 op &= UINT64_C(15);
8252 op <<= 4;
8253 Value |= op;
8254 // op: CRm
8255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8256 op &= UINT64_C(15);
8257 Value |= op;
8258 break;
8259 }
8260 case ARM::MCR2:
8261 case ARM::t2MCR:
8262 case ARM::t2MCR2: {
8263 // op: Rt
8264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8265 op &= UINT64_C(15);
8266 op <<= 12;
8267 Value |= op;
8268 // op: cop
8269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8270 op &= UINT64_C(15);
8271 op <<= 8;
8272 Value |= op;
8273 // op: opc1
8274 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8275 op &= UINT64_C(7);
8276 op <<= 21;
8277 Value |= op;
8278 // op: opc2
8279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
8280 op &= UINT64_C(7);
8281 op <<= 5;
8282 Value |= op;
8283 // op: CRm
8284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8285 op &= UINT64_C(15);
8286 Value |= op;
8287 // op: CRn
8288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8289 op &= UINT64_C(15);
8290 op <<= 16;
8291 Value |= op;
8292 break;
8293 }
8294 case ARM::t2MSR_M: {
8295 // op: SYSm
8296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8297 Value |= (op & UINT64_C(3072));
8298 Value |= (op & UINT64_C(255));
8299 // op: Rn
8300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8301 op &= UINT64_C(15);
8302 op <<= 16;
8303 Value |= op;
8304 break;
8305 }
8306 case ARM::VCVTASD:
8307 case ARM::VCVTAUD:
8308 case ARM::VCVTMSD:
8309 case ARM::VCVTMUD:
8310 case ARM::VCVTNSD:
8311 case ARM::VCVTNUD:
8312 case ARM::VCVTPSD:
8313 case ARM::VCVTPUD: {
8314 // op: Sd
8315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8316 Value |= (op & UINT64_C(1)) << 22;
8317 Value |= (op & UINT64_C(30)) << 11;
8318 // op: Dm
8319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8320 Value |= (op & UINT64_C(16)) << 1;
8321 Value |= (op & UINT64_C(15));
8322 break;
8323 }
8324 case ARM::VCVTASH:
8325 case ARM::VCVTASS:
8326 case ARM::VCVTAUH:
8327 case ARM::VCVTAUS:
8328 case ARM::VCVTMSH:
8329 case ARM::VCVTMSS:
8330 case ARM::VCVTMUH:
8331 case ARM::VCVTMUS:
8332 case ARM::VCVTNSH:
8333 case ARM::VCVTNSS:
8334 case ARM::VCVTNUH:
8335 case ARM::VCVTNUS:
8336 case ARM::VCVTPSH:
8337 case ARM::VCVTPSS:
8338 case ARM::VCVTPUH:
8339 case ARM::VCVTPUS:
8340 case ARM::VMOVH:
8341 case ARM::VRINTAH:
8342 case ARM::VRINTAS:
8343 case ARM::VRINTMH:
8344 case ARM::VRINTMS:
8345 case ARM::VRINTNH:
8346 case ARM::VRINTNS:
8347 case ARM::VRINTPH:
8348 case ARM::VRINTPS: {
8349 // op: Sd
8350 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8351 Value |= (op & UINT64_C(1)) << 22;
8352 Value |= (op & UINT64_C(30)) << 11;
8353 // op: Sm
8354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8355 Value |= (op & UINT64_C(1)) << 5;
8356 Value |= (op & UINT64_C(30)) >> 1;
8357 break;
8358 }
8359 case ARM::VINSH: {
8360 // op: Sd
8361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8362 Value |= (op & UINT64_C(1)) << 22;
8363 Value |= (op & UINT64_C(30)) << 11;
8364 // op: Sm
8365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8366 Value |= (op & UINT64_C(1)) << 5;
8367 Value |= (op & UINT64_C(30)) >> 1;
8368 break;
8369 }
8370 case ARM::VFP_VMAXNMH:
8371 case ARM::VFP_VMAXNMS:
8372 case ARM::VFP_VMINNMH:
8373 case ARM::VFP_VMINNMS:
8374 case ARM::VSELEQH:
8375 case ARM::VSELEQS:
8376 case ARM::VSELGEH:
8377 case ARM::VSELGES:
8378 case ARM::VSELGTH:
8379 case ARM::VSELGTS:
8380 case ARM::VSELVSH:
8381 case ARM::VSELVSS: {
8382 // op: Sd
8383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8384 Value |= (op & UINT64_C(1)) << 22;
8385 Value |= (op & UINT64_C(30)) << 11;
8386 // op: Sn
8387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8388 Value |= (op & UINT64_C(30)) << 15;
8389 Value |= (op & UINT64_C(1)) << 7;
8390 // op: Sm
8391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8392 Value |= (op & UINT64_C(1)) << 5;
8393 Value |= (op & UINT64_C(30)) >> 1;
8394 break;
8395 }
8396 case ARM::VDUP8d:
8397 case ARM::VDUP8q:
8398 case ARM::VDUP16d:
8399 case ARM::VDUP16q:
8400 case ARM::VDUP32d:
8401 case ARM::VDUP32q: {
8402 // op: V
8403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8404 Value |= (op & UINT64_C(15)) << 16;
8405 Value |= (op & UINT64_C(16)) << 3;
8406 // op: R
8407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8408 op &= UINT64_C(15);
8409 op <<= 12;
8410 Value |= op;
8411 // op: p
8412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8413 op &= UINT64_C(15);
8414 op <<= 28;
8415 Value |= op;
8416 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8417 break;
8418 }
8419 case ARM::VSETLNi16: {
8420 // op: V
8421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8422 Value |= (op & UINT64_C(15)) << 16;
8423 Value |= (op & UINT64_C(16)) << 3;
8424 // op: R
8425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8426 op &= UINT64_C(15);
8427 op <<= 12;
8428 Value |= op;
8429 // op: p
8430 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8431 op &= UINT64_C(15);
8432 op <<= 28;
8433 Value |= op;
8434 // op: lane
8435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8436 Value |= (op & UINT64_C(2)) << 20;
8437 Value |= (op & UINT64_C(1)) << 6;
8438 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8439 break;
8440 }
8441 case ARM::VSETLNi8: {
8442 // op: V
8443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8444 Value |= (op & UINT64_C(15)) << 16;
8445 Value |= (op & UINT64_C(16)) << 3;
8446 // op: R
8447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8448 op &= UINT64_C(15);
8449 op <<= 12;
8450 Value |= op;
8451 // op: p
8452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8453 op &= UINT64_C(15);
8454 op <<= 28;
8455 Value |= op;
8456 // op: lane
8457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8458 Value |= (op & UINT64_C(4)) << 19;
8459 Value |= (op & UINT64_C(3)) << 5;
8460 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8461 break;
8462 }
8463 case ARM::VSETLNi32: {
8464 // op: V
8465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8466 Value |= (op & UINT64_C(15)) << 16;
8467 Value |= (op & UINT64_C(16)) << 3;
8468 // op: R
8469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8470 op &= UINT64_C(15);
8471 op <<= 12;
8472 Value |= op;
8473 // op: p
8474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8475 op &= UINT64_C(15);
8476 op <<= 28;
8477 Value |= op;
8478 // op: lane
8479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8480 op &= UINT64_C(1);
8481 op <<= 21;
8482 Value |= op;
8483 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8484 break;
8485 }
8486 case ARM::VGETLNs16:
8487 case ARM::VGETLNu16: {
8488 // op: V
8489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8490 Value |= (op & UINT64_C(15)) << 16;
8491 Value |= (op & UINT64_C(16)) << 3;
8492 // op: R
8493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8494 op &= UINT64_C(15);
8495 op <<= 12;
8496 Value |= op;
8497 // op: p
8498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8499 op &= UINT64_C(15);
8500 op <<= 28;
8501 Value |= op;
8502 // op: lane
8503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8504 Value |= (op & UINT64_C(2)) << 20;
8505 Value |= (op & UINT64_C(1)) << 6;
8506 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8507 break;
8508 }
8509 case ARM::VGETLNs8:
8510 case ARM::VGETLNu8: {
8511 // op: V
8512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8513 Value |= (op & UINT64_C(15)) << 16;
8514 Value |= (op & UINT64_C(16)) << 3;
8515 // op: R
8516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8517 op &= UINT64_C(15);
8518 op <<= 12;
8519 Value |= op;
8520 // op: p
8521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8522 op &= UINT64_C(15);
8523 op <<= 28;
8524 Value |= op;
8525 // op: lane
8526 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8527 Value |= (op & UINT64_C(4)) << 19;
8528 Value |= (op & UINT64_C(3)) << 5;
8529 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8530 break;
8531 }
8532 case ARM::VGETLNi32: {
8533 // op: V
8534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8535 Value |= (op & UINT64_C(15)) << 16;
8536 Value |= (op & UINT64_C(16)) << 3;
8537 // op: R
8538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8539 op &= UINT64_C(15);
8540 op <<= 12;
8541 Value |= op;
8542 // op: p
8543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8544 op &= UINT64_C(15);
8545 op <<= 28;
8546 Value |= op;
8547 // op: lane
8548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8549 op &= UINT64_C(1);
8550 op <<= 21;
8551 Value |= op;
8552 Value = NEONThumb2DupPostEncoder(MI, EncodedValue: Value, STI);
8553 break;
8554 }
8555 case ARM::MVE_VST20_8:
8556 case ARM::MVE_VST20_16:
8557 case ARM::MVE_VST20_32:
8558 case ARM::MVE_VST21_8:
8559 case ARM::MVE_VST21_16:
8560 case ARM::MVE_VST21_32:
8561 case ARM::MVE_VST40_8:
8562 case ARM::MVE_VST40_16:
8563 case ARM::MVE_VST40_32:
8564 case ARM::MVE_VST41_8:
8565 case ARM::MVE_VST41_16:
8566 case ARM::MVE_VST41_32:
8567 case ARM::MVE_VST42_8:
8568 case ARM::MVE_VST42_16:
8569 case ARM::MVE_VST42_32:
8570 case ARM::MVE_VST43_8:
8571 case ARM::MVE_VST43_16:
8572 case ARM::MVE_VST43_32: {
8573 // op: VQd
8574 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8575 op &= UINT64_C(7);
8576 op <<= 13;
8577 Value |= op;
8578 // op: Rn
8579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8580 op &= UINT64_C(15);
8581 op <<= 16;
8582 Value |= op;
8583 break;
8584 }
8585 case ARM::MVE_VLD20_8:
8586 case ARM::MVE_VLD20_16:
8587 case ARM::MVE_VLD20_32:
8588 case ARM::MVE_VLD21_8:
8589 case ARM::MVE_VLD21_16:
8590 case ARM::MVE_VLD21_32:
8591 case ARM::MVE_VLD40_8:
8592 case ARM::MVE_VLD40_16:
8593 case ARM::MVE_VLD40_32:
8594 case ARM::MVE_VLD41_8:
8595 case ARM::MVE_VLD41_16:
8596 case ARM::MVE_VLD41_32:
8597 case ARM::MVE_VLD42_8:
8598 case ARM::MVE_VLD42_16:
8599 case ARM::MVE_VLD42_32:
8600 case ARM::MVE_VLD43_8:
8601 case ARM::MVE_VLD43_16:
8602 case ARM::MVE_VLD43_32: {
8603 // op: VQd
8604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8605 op &= UINT64_C(7);
8606 op <<= 13;
8607 Value |= op;
8608 // op: Rn
8609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8610 op &= UINT64_C(15);
8611 op <<= 16;
8612 Value |= op;
8613 break;
8614 }
8615 case ARM::MVE_VLD20_8_wb:
8616 case ARM::MVE_VLD20_16_wb:
8617 case ARM::MVE_VLD20_32_wb:
8618 case ARM::MVE_VLD21_8_wb:
8619 case ARM::MVE_VLD21_16_wb:
8620 case ARM::MVE_VLD21_32_wb:
8621 case ARM::MVE_VLD40_8_wb:
8622 case ARM::MVE_VLD40_16_wb:
8623 case ARM::MVE_VLD40_32_wb:
8624 case ARM::MVE_VLD41_8_wb:
8625 case ARM::MVE_VLD41_16_wb:
8626 case ARM::MVE_VLD41_32_wb:
8627 case ARM::MVE_VLD42_8_wb:
8628 case ARM::MVE_VLD42_16_wb:
8629 case ARM::MVE_VLD42_32_wb:
8630 case ARM::MVE_VLD43_8_wb:
8631 case ARM::MVE_VLD43_16_wb:
8632 case ARM::MVE_VLD43_32_wb: {
8633 // op: VQd
8634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8635 op &= UINT64_C(7);
8636 op <<= 13;
8637 Value |= op;
8638 // op: Rn
8639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8640 op &= UINT64_C(15);
8641 op <<= 16;
8642 Value |= op;
8643 break;
8644 }
8645 case ARM::MVE_VST20_8_wb:
8646 case ARM::MVE_VST20_16_wb:
8647 case ARM::MVE_VST20_32_wb:
8648 case ARM::MVE_VST21_8_wb:
8649 case ARM::MVE_VST21_16_wb:
8650 case ARM::MVE_VST21_32_wb:
8651 case ARM::MVE_VST40_8_wb:
8652 case ARM::MVE_VST40_16_wb:
8653 case ARM::MVE_VST40_32_wb:
8654 case ARM::MVE_VST41_8_wb:
8655 case ARM::MVE_VST41_16_wb:
8656 case ARM::MVE_VST41_32_wb:
8657 case ARM::MVE_VST42_8_wb:
8658 case ARM::MVE_VST42_16_wb:
8659 case ARM::MVE_VST42_32_wb:
8660 case ARM::MVE_VST43_8_wb:
8661 case ARM::MVE_VST43_16_wb:
8662 case ARM::MVE_VST43_32_wb: {
8663 // op: VQd
8664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8665 op &= UINT64_C(7);
8666 op <<= 13;
8667 Value |= op;
8668 // op: Rn
8669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8670 op &= UINT64_C(15);
8671 op <<= 16;
8672 Value |= op;
8673 break;
8674 }
8675 case ARM::VLD1d8:
8676 case ARM::VLD1d8T:
8677 case ARM::VLD1d16:
8678 case ARM::VLD1d16T:
8679 case ARM::VLD1d32:
8680 case ARM::VLD1d32T:
8681 case ARM::VLD1d64:
8682 case ARM::VLD1d64T: {
8683 // op: Vd
8684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8685 Value |= (op & UINT64_C(16)) << 18;
8686 Value |= (op & UINT64_C(15)) << 12;
8687 // op: Rn
8688 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
8689 Value |= (op & UINT64_C(15)) << 16;
8690 Value |= (op & UINT64_C(16));
8691 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8692 break;
8693 }
8694 case ARM::VLD1LNd16: {
8695 // op: Vd
8696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8697 Value |= (op & UINT64_C(16)) << 18;
8698 Value |= (op & UINT64_C(15)) << 12;
8699 // op: Rn
8700 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
8701 Value |= (op & UINT64_C(15)) << 16;
8702 Value |= (op & UINT64_C(48));
8703 // op: lane
8704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8705 op &= UINT64_C(3);
8706 op <<= 6;
8707 Value |= op;
8708 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8709 break;
8710 }
8711 case ARM::VLD1d8Q:
8712 case ARM::VLD1d16Q:
8713 case ARM::VLD1d32Q:
8714 case ARM::VLD1d64Q:
8715 case ARM::VLD1q8:
8716 case ARM::VLD1q16:
8717 case ARM::VLD1q32:
8718 case ARM::VLD1q64:
8719 case ARM::VLD2b8:
8720 case ARM::VLD2b16:
8721 case ARM::VLD2b32:
8722 case ARM::VLD2d8:
8723 case ARM::VLD2d16:
8724 case ARM::VLD2d32:
8725 case ARM::VLD2q8:
8726 case ARM::VLD2q16:
8727 case ARM::VLD2q32: {
8728 // op: Vd
8729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8730 Value |= (op & UINT64_C(16)) << 18;
8731 Value |= (op & UINT64_C(15)) << 12;
8732 // op: Rn
8733 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
8734 Value |= (op & UINT64_C(15)) << 16;
8735 Value |= (op & UINT64_C(48));
8736 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8737 break;
8738 }
8739 case ARM::VLD1LNd8: {
8740 // op: Vd
8741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8742 Value |= (op & UINT64_C(16)) << 18;
8743 Value |= (op & UINT64_C(15)) << 12;
8744 // op: Rn
8745 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
8746 op &= UINT64_C(15);
8747 op <<= 16;
8748 Value |= op;
8749 // op: lane
8750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8751 op &= UINT64_C(7);
8752 op <<= 5;
8753 Value |= op;
8754 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8755 break;
8756 }
8757 case ARM::VLD1LNd32_UPD: {
8758 // op: Vd
8759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8760 Value |= (op & UINT64_C(16)) << 18;
8761 Value |= (op & UINT64_C(15)) << 12;
8762 // op: Rn
8763 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8764 Value |= (op & UINT64_C(15)) << 16;
8765 Value |= (op & UINT64_C(16)) << 1;
8766 Value |= (op & UINT64_C(16));
8767 // op: Rm
8768 op = getAddrMode6OffsetOpValue(MI, Op: 4, Fixups, STI);
8769 op &= UINT64_C(15);
8770 Value |= op;
8771 // op: lane
8772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
8773 op &= UINT64_C(1);
8774 op <<= 7;
8775 Value |= op;
8776 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8777 break;
8778 }
8779 case ARM::VLD1LNd16_UPD: {
8780 // op: Vd
8781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8782 Value |= (op & UINT64_C(16)) << 18;
8783 Value |= (op & UINT64_C(15)) << 12;
8784 // op: Rn
8785 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8786 Value |= (op & UINT64_C(15)) << 16;
8787 Value |= (op & UINT64_C(16));
8788 // op: Rm
8789 op = getAddrMode6OffsetOpValue(MI, Op: 4, Fixups, STI);
8790 op &= UINT64_C(15);
8791 Value |= op;
8792 // op: lane
8793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
8794 op &= UINT64_C(3);
8795 op <<= 6;
8796 Value |= op;
8797 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8798 break;
8799 }
8800 case ARM::VLD1d8Twb_register:
8801 case ARM::VLD1d8wb_register:
8802 case ARM::VLD1d16Twb_register:
8803 case ARM::VLD1d16wb_register:
8804 case ARM::VLD1d32Twb_register:
8805 case ARM::VLD1d32wb_register:
8806 case ARM::VLD1d64Twb_register:
8807 case ARM::VLD1d64wb_register: {
8808 // op: Vd
8809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8810 Value |= (op & UINT64_C(16)) << 18;
8811 Value |= (op & UINT64_C(15)) << 12;
8812 // op: Rn
8813 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8814 Value |= (op & UINT64_C(15)) << 16;
8815 Value |= (op & UINT64_C(16));
8816 // op: Rm
8817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8818 op &= UINT64_C(15);
8819 Value |= op;
8820 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8821 break;
8822 }
8823 case ARM::VLD2LNd32:
8824 case ARM::VLD2LNq32: {
8825 // op: Vd
8826 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8827 Value |= (op & UINT64_C(16)) << 18;
8828 Value |= (op & UINT64_C(15)) << 12;
8829 // op: Rn
8830 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8831 Value |= (op & UINT64_C(15)) << 16;
8832 Value |= (op & UINT64_C(16));
8833 // op: lane
8834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
8835 op &= UINT64_C(1);
8836 op <<= 7;
8837 Value |= op;
8838 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8839 break;
8840 }
8841 case ARM::VLD2LNd16:
8842 case ARM::VLD2LNq16: {
8843 // op: Vd
8844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8845 Value |= (op & UINT64_C(16)) << 18;
8846 Value |= (op & UINT64_C(15)) << 12;
8847 // op: Rn
8848 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8849 Value |= (op & UINT64_C(15)) << 16;
8850 Value |= (op & UINT64_C(16));
8851 // op: lane
8852 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
8853 op &= UINT64_C(3);
8854 op <<= 6;
8855 Value |= op;
8856 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8857 break;
8858 }
8859 case ARM::VLD2LNd8: {
8860 // op: Vd
8861 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8862 Value |= (op & UINT64_C(16)) << 18;
8863 Value |= (op & UINT64_C(15)) << 12;
8864 // op: Rn
8865 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8866 Value |= (op & UINT64_C(15)) << 16;
8867 Value |= (op & UINT64_C(16));
8868 // op: lane
8869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
8870 op &= UINT64_C(7);
8871 op <<= 5;
8872 Value |= op;
8873 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8874 break;
8875 }
8876 case ARM::VLD1d8Twb_fixed:
8877 case ARM::VLD1d8wb_fixed:
8878 case ARM::VLD1d16Twb_fixed:
8879 case ARM::VLD1d16wb_fixed:
8880 case ARM::VLD1d32Twb_fixed:
8881 case ARM::VLD1d32wb_fixed:
8882 case ARM::VLD1d64Twb_fixed:
8883 case ARM::VLD1d64wb_fixed: {
8884 // op: Vd
8885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8886 Value |= (op & UINT64_C(16)) << 18;
8887 Value |= (op & UINT64_C(15)) << 12;
8888 // op: Rn
8889 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8890 Value |= (op & UINT64_C(15)) << 16;
8891 Value |= (op & UINT64_C(16));
8892 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8893 break;
8894 }
8895 case ARM::VLD1d8Qwb_register:
8896 case ARM::VLD1d16Qwb_register:
8897 case ARM::VLD1d32Qwb_register:
8898 case ARM::VLD1d64Qwb_register:
8899 case ARM::VLD1q8wb_register:
8900 case ARM::VLD1q16wb_register:
8901 case ARM::VLD1q32wb_register:
8902 case ARM::VLD1q64wb_register:
8903 case ARM::VLD2b8wb_register:
8904 case ARM::VLD2b16wb_register:
8905 case ARM::VLD2b32wb_register:
8906 case ARM::VLD2d8wb_register:
8907 case ARM::VLD2d16wb_register:
8908 case ARM::VLD2d32wb_register:
8909 case ARM::VLD2q8wb_register:
8910 case ARM::VLD2q16wb_register:
8911 case ARM::VLD2q32wb_register: {
8912 // op: Vd
8913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8914 Value |= (op & UINT64_C(16)) << 18;
8915 Value |= (op & UINT64_C(15)) << 12;
8916 // op: Rn
8917 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8918 Value |= (op & UINT64_C(15)) << 16;
8919 Value |= (op & UINT64_C(48));
8920 // op: Rm
8921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8922 op &= UINT64_C(15);
8923 Value |= op;
8924 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8925 break;
8926 }
8927 case ARM::VLD1d8Qwb_fixed:
8928 case ARM::VLD1d16Qwb_fixed:
8929 case ARM::VLD1d32Qwb_fixed:
8930 case ARM::VLD1d64Qwb_fixed:
8931 case ARM::VLD1q8wb_fixed:
8932 case ARM::VLD1q16wb_fixed:
8933 case ARM::VLD1q32wb_fixed:
8934 case ARM::VLD1q64wb_fixed:
8935 case ARM::VLD2b8wb_fixed:
8936 case ARM::VLD2b16wb_fixed:
8937 case ARM::VLD2b32wb_fixed:
8938 case ARM::VLD2d8wb_fixed:
8939 case ARM::VLD2d16wb_fixed:
8940 case ARM::VLD2d32wb_fixed:
8941 case ARM::VLD2q8wb_fixed:
8942 case ARM::VLD2q16wb_fixed:
8943 case ARM::VLD2q32wb_fixed: {
8944 // op: Vd
8945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8946 Value |= (op & UINT64_C(16)) << 18;
8947 Value |= (op & UINT64_C(15)) << 12;
8948 // op: Rn
8949 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8950 Value |= (op & UINT64_C(15)) << 16;
8951 Value |= (op & UINT64_C(48));
8952 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8953 break;
8954 }
8955 case ARM::VLD1LNd8_UPD: {
8956 // op: Vd
8957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8958 Value |= (op & UINT64_C(16)) << 18;
8959 Value |= (op & UINT64_C(15)) << 12;
8960 // op: Rn
8961 op = getAddrMode6AddressOpValue(MI, Op: 2, Fixups, STI);
8962 op &= UINT64_C(15);
8963 op <<= 16;
8964 Value |= op;
8965 // op: Rm
8966 op = getAddrMode6OffsetOpValue(MI, Op: 4, Fixups, STI);
8967 op &= UINT64_C(15);
8968 Value |= op;
8969 // op: lane
8970 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
8971 op &= UINT64_C(7);
8972 op <<= 5;
8973 Value |= op;
8974 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8975 break;
8976 }
8977 case ARM::VLD2LNd32_UPD:
8978 case ARM::VLD2LNq32_UPD: {
8979 // op: Vd
8980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8981 Value |= (op & UINT64_C(16)) << 18;
8982 Value |= (op & UINT64_C(15)) << 12;
8983 // op: Rn
8984 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
8985 Value |= (op & UINT64_C(15)) << 16;
8986 Value |= (op & UINT64_C(16));
8987 // op: Rm
8988 op = getAddrMode6OffsetOpValue(MI, Op: 5, Fixups, STI);
8989 op &= UINT64_C(15);
8990 Value |= op;
8991 // op: lane
8992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
8993 op &= UINT64_C(1);
8994 op <<= 7;
8995 Value |= op;
8996 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
8997 break;
8998 }
8999 case ARM::VLD2LNd16_UPD:
9000 case ARM::VLD2LNq16_UPD: {
9001 // op: Vd
9002 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9003 Value |= (op & UINT64_C(16)) << 18;
9004 Value |= (op & UINT64_C(15)) << 12;
9005 // op: Rn
9006 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
9007 Value |= (op & UINT64_C(15)) << 16;
9008 Value |= (op & UINT64_C(16));
9009 // op: Rm
9010 op = getAddrMode6OffsetOpValue(MI, Op: 5, Fixups, STI);
9011 op &= UINT64_C(15);
9012 Value |= op;
9013 // op: lane
9014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
9015 op &= UINT64_C(3);
9016 op <<= 6;
9017 Value |= op;
9018 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9019 break;
9020 }
9021 case ARM::VLD2LNd8_UPD: {
9022 // op: Vd
9023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9024 Value |= (op & UINT64_C(16)) << 18;
9025 Value |= (op & UINT64_C(15)) << 12;
9026 // op: Rn
9027 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
9028 Value |= (op & UINT64_C(15)) << 16;
9029 Value |= (op & UINT64_C(16));
9030 // op: Rm
9031 op = getAddrMode6OffsetOpValue(MI, Op: 5, Fixups, STI);
9032 op &= UINT64_C(15);
9033 Value |= op;
9034 // op: lane
9035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
9036 op &= UINT64_C(7);
9037 op <<= 5;
9038 Value |= op;
9039 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9040 break;
9041 }
9042 case ARM::VLD3d8:
9043 case ARM::VLD3d16:
9044 case ARM::VLD3d32:
9045 case ARM::VLD3q8:
9046 case ARM::VLD3q16:
9047 case ARM::VLD3q32: {
9048 // op: Vd
9049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9050 Value |= (op & UINT64_C(16)) << 18;
9051 Value |= (op & UINT64_C(15)) << 12;
9052 // op: Rn
9053 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
9054 Value |= (op & UINT64_C(15)) << 16;
9055 Value |= (op & UINT64_C(16));
9056 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9057 break;
9058 }
9059 case ARM::VLD3LNd32:
9060 case ARM::VLD3LNq32: {
9061 // op: Vd
9062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9063 Value |= (op & UINT64_C(16)) << 18;
9064 Value |= (op & UINT64_C(15)) << 12;
9065 // op: Rn
9066 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
9067 op &= UINT64_C(15);
9068 op <<= 16;
9069 Value |= op;
9070 // op: lane
9071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
9072 op &= UINT64_C(1);
9073 op <<= 7;
9074 Value |= op;
9075 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9076 break;
9077 }
9078 case ARM::VLD3LNd16:
9079 case ARM::VLD3LNq16: {
9080 // op: Vd
9081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9082 Value |= (op & UINT64_C(16)) << 18;
9083 Value |= (op & UINT64_C(15)) << 12;
9084 // op: Rn
9085 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
9086 op &= UINT64_C(15);
9087 op <<= 16;
9088 Value |= op;
9089 // op: lane
9090 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
9091 op &= UINT64_C(3);
9092 op <<= 6;
9093 Value |= op;
9094 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9095 break;
9096 }
9097 case ARM::VLD3LNd8: {
9098 // op: Vd
9099 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9100 Value |= (op & UINT64_C(16)) << 18;
9101 Value |= (op & UINT64_C(15)) << 12;
9102 // op: Rn
9103 op = getAddrMode6AddressOpValue(MI, Op: 3, Fixups, STI);
9104 op &= UINT64_C(15);
9105 op <<= 16;
9106 Value |= op;
9107 // op: lane
9108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
9109 op &= UINT64_C(7);
9110 op <<= 5;
9111 Value |= op;
9112 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9113 break;
9114 }
9115 case ARM::VLD3d8_UPD:
9116 case ARM::VLD3d16_UPD:
9117 case ARM::VLD3d32_UPD:
9118 case ARM::VLD3q8_UPD:
9119 case ARM::VLD3q16_UPD:
9120 case ARM::VLD3q32_UPD: {
9121 // op: Vd
9122 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9123 Value |= (op & UINT64_C(16)) << 18;
9124 Value |= (op & UINT64_C(15)) << 12;
9125 // op: Rn
9126 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9127 Value |= (op & UINT64_C(15)) << 16;
9128 Value |= (op & UINT64_C(16));
9129 // op: Rm
9130 op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI);
9131 op &= UINT64_C(15);
9132 Value |= op;
9133 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9134 break;
9135 }
9136 case ARM::VLD4LNd16:
9137 case ARM::VLD4LNq16: {
9138 // op: Vd
9139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9140 Value |= (op & UINT64_C(16)) << 18;
9141 Value |= (op & UINT64_C(15)) << 12;
9142 // op: Rn
9143 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9144 Value |= (op & UINT64_C(15)) << 16;
9145 Value |= (op & UINT64_C(16));
9146 // op: lane
9147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI);
9148 op &= UINT64_C(3);
9149 op <<= 6;
9150 Value |= op;
9151 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9152 break;
9153 }
9154 case ARM::VLD4LNd8: {
9155 // op: Vd
9156 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9157 Value |= (op & UINT64_C(16)) << 18;
9158 Value |= (op & UINT64_C(15)) << 12;
9159 // op: Rn
9160 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9161 Value |= (op & UINT64_C(15)) << 16;
9162 Value |= (op & UINT64_C(16));
9163 // op: lane
9164 op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI);
9165 op &= UINT64_C(7);
9166 op <<= 5;
9167 Value |= op;
9168 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9169 break;
9170 }
9171 case ARM::VLD4LNd32:
9172 case ARM::VLD4LNq32: {
9173 // op: Vd
9174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9175 Value |= (op & UINT64_C(16)) << 18;
9176 Value |= (op & UINT64_C(15)) << 12;
9177 // op: Rn
9178 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9179 Value |= (op & UINT64_C(15)) << 16;
9180 Value |= (op & UINT64_C(48));
9181 // op: lane
9182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI);
9183 op &= UINT64_C(1);
9184 op <<= 7;
9185 Value |= op;
9186 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9187 break;
9188 }
9189 case ARM::VLD4d8:
9190 case ARM::VLD4d16:
9191 case ARM::VLD4d32:
9192 case ARM::VLD4q8:
9193 case ARM::VLD4q16:
9194 case ARM::VLD4q32: {
9195 // op: Vd
9196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9197 Value |= (op & UINT64_C(16)) << 18;
9198 Value |= (op & UINT64_C(15)) << 12;
9199 // op: Rn
9200 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9201 Value |= (op & UINT64_C(15)) << 16;
9202 Value |= (op & UINT64_C(48));
9203 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9204 break;
9205 }
9206 case ARM::VLD3LNd32_UPD:
9207 case ARM::VLD3LNq32_UPD: {
9208 // op: Vd
9209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9210 Value |= (op & UINT64_C(16)) << 18;
9211 Value |= (op & UINT64_C(15)) << 12;
9212 // op: Rn
9213 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9214 op &= UINT64_C(15);
9215 op <<= 16;
9216 Value |= op;
9217 // op: Rm
9218 op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI);
9219 op &= UINT64_C(15);
9220 Value |= op;
9221 // op: lane
9222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI);
9223 op &= UINT64_C(1);
9224 op <<= 7;
9225 Value |= op;
9226 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9227 break;
9228 }
9229 case ARM::VLD3LNd16_UPD:
9230 case ARM::VLD3LNq16_UPD: {
9231 // op: Vd
9232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9233 Value |= (op & UINT64_C(16)) << 18;
9234 Value |= (op & UINT64_C(15)) << 12;
9235 // op: Rn
9236 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9237 op &= UINT64_C(15);
9238 op <<= 16;
9239 Value |= op;
9240 // op: Rm
9241 op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI);
9242 op &= UINT64_C(15);
9243 Value |= op;
9244 // op: lane
9245 op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI);
9246 op &= UINT64_C(3);
9247 op <<= 6;
9248 Value |= op;
9249 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9250 break;
9251 }
9252 case ARM::VLD3LNd8_UPD: {
9253 // op: Vd
9254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9255 Value |= (op & UINT64_C(16)) << 18;
9256 Value |= (op & UINT64_C(15)) << 12;
9257 // op: Rn
9258 op = getAddrMode6AddressOpValue(MI, Op: 4, Fixups, STI);
9259 op &= UINT64_C(15);
9260 op <<= 16;
9261 Value |= op;
9262 // op: Rm
9263 op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI);
9264 op &= UINT64_C(15);
9265 Value |= op;
9266 // op: lane
9267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 10), Fixups, STI);
9268 op &= UINT64_C(7);
9269 op <<= 5;
9270 Value |= op;
9271 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9272 break;
9273 }
9274 case ARM::VLD4LNd16_UPD:
9275 case ARM::VLD4LNq16_UPD: {
9276 // op: Vd
9277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9278 Value |= (op & UINT64_C(16)) << 18;
9279 Value |= (op & UINT64_C(15)) << 12;
9280 // op: Rn
9281 op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI);
9282 Value |= (op & UINT64_C(15)) << 16;
9283 Value |= (op & UINT64_C(16));
9284 // op: Rm
9285 op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI);
9286 op &= UINT64_C(15);
9287 Value |= op;
9288 // op: lane
9289 op = getMachineOpValue(MI, MO: MI.getOperand(i: 12), Fixups, STI);
9290 op &= UINT64_C(3);
9291 op <<= 6;
9292 Value |= op;
9293 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9294 break;
9295 }
9296 case ARM::VLD4LNd8_UPD: {
9297 // op: Vd
9298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9299 Value |= (op & UINT64_C(16)) << 18;
9300 Value |= (op & UINT64_C(15)) << 12;
9301 // op: Rn
9302 op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI);
9303 Value |= (op & UINT64_C(15)) << 16;
9304 Value |= (op & UINT64_C(16));
9305 // op: Rm
9306 op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI);
9307 op &= UINT64_C(15);
9308 Value |= op;
9309 // op: lane
9310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 12), Fixups, STI);
9311 op &= UINT64_C(7);
9312 op <<= 5;
9313 Value |= op;
9314 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9315 break;
9316 }
9317 case ARM::VLD4LNd32_UPD:
9318 case ARM::VLD4LNq32_UPD: {
9319 // op: Vd
9320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9321 Value |= (op & UINT64_C(16)) << 18;
9322 Value |= (op & UINT64_C(15)) << 12;
9323 // op: Rn
9324 op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI);
9325 Value |= (op & UINT64_C(15)) << 16;
9326 Value |= (op & UINT64_C(48));
9327 // op: Rm
9328 op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI);
9329 op &= UINT64_C(15);
9330 Value |= op;
9331 // op: lane
9332 op = getMachineOpValue(MI, MO: MI.getOperand(i: 12), Fixups, STI);
9333 op &= UINT64_C(1);
9334 op <<= 7;
9335 Value |= op;
9336 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9337 break;
9338 }
9339 case ARM::VLD4d8_UPD:
9340 case ARM::VLD4d16_UPD:
9341 case ARM::VLD4d32_UPD:
9342 case ARM::VLD4q8_UPD:
9343 case ARM::VLD4q16_UPD:
9344 case ARM::VLD4q32_UPD: {
9345 // op: Vd
9346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9347 Value |= (op & UINT64_C(16)) << 18;
9348 Value |= (op & UINT64_C(15)) << 12;
9349 // op: Rn
9350 op = getAddrMode6AddressOpValue(MI, Op: 5, Fixups, STI);
9351 Value |= (op & UINT64_C(15)) << 16;
9352 Value |= (op & UINT64_C(48));
9353 // op: Rm
9354 op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI);
9355 op &= UINT64_C(15);
9356 Value |= op;
9357 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9358 break;
9359 }
9360 case ARM::VLD1DUPd8:
9361 case ARM::VLD1DUPd16:
9362 case ARM::VLD1DUPd32:
9363 case ARM::VLD1DUPq8:
9364 case ARM::VLD1DUPq16:
9365 case ARM::VLD1DUPq32:
9366 case ARM::VLD2DUPd8:
9367 case ARM::VLD2DUPd8x2:
9368 case ARM::VLD2DUPd16:
9369 case ARM::VLD2DUPd16x2:
9370 case ARM::VLD2DUPd32:
9371 case ARM::VLD2DUPd32x2: {
9372 // op: Vd
9373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9374 Value |= (op & UINT64_C(16)) << 18;
9375 Value |= (op & UINT64_C(15)) << 12;
9376 // op: Rn
9377 op = getAddrMode6DupAddressOpValue(MI, Op: 1, Fixups, STI);
9378 Value |= (op & UINT64_C(15)) << 16;
9379 Value |= (op & UINT64_C(16));
9380 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9381 break;
9382 }
9383 case ARM::VLD1DUPd8wb_register:
9384 case ARM::VLD1DUPd16wb_register:
9385 case ARM::VLD1DUPd32wb_register:
9386 case ARM::VLD1DUPq8wb_register:
9387 case ARM::VLD1DUPq16wb_register:
9388 case ARM::VLD1DUPq32wb_register:
9389 case ARM::VLD2DUPd8wb_register:
9390 case ARM::VLD2DUPd8x2wb_register:
9391 case ARM::VLD2DUPd16wb_register:
9392 case ARM::VLD2DUPd16x2wb_register:
9393 case ARM::VLD2DUPd32wb_register:
9394 case ARM::VLD2DUPd32x2wb_register: {
9395 // op: Vd
9396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9397 Value |= (op & UINT64_C(16)) << 18;
9398 Value |= (op & UINT64_C(15)) << 12;
9399 // op: Rn
9400 op = getAddrMode6DupAddressOpValue(MI, Op: 2, Fixups, STI);
9401 Value |= (op & UINT64_C(15)) << 16;
9402 Value |= (op & UINT64_C(16));
9403 // op: Rm
9404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9405 op &= UINT64_C(15);
9406 Value |= op;
9407 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9408 break;
9409 }
9410 case ARM::VLD1DUPd8wb_fixed:
9411 case ARM::VLD1DUPd16wb_fixed:
9412 case ARM::VLD1DUPd32wb_fixed:
9413 case ARM::VLD1DUPq8wb_fixed:
9414 case ARM::VLD1DUPq16wb_fixed:
9415 case ARM::VLD1DUPq32wb_fixed:
9416 case ARM::VLD2DUPd8wb_fixed:
9417 case ARM::VLD2DUPd8x2wb_fixed:
9418 case ARM::VLD2DUPd16wb_fixed:
9419 case ARM::VLD2DUPd16x2wb_fixed:
9420 case ARM::VLD2DUPd32wb_fixed:
9421 case ARM::VLD2DUPd32x2wb_fixed: {
9422 // op: Vd
9423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9424 Value |= (op & UINT64_C(16)) << 18;
9425 Value |= (op & UINT64_C(15)) << 12;
9426 // op: Rn
9427 op = getAddrMode6DupAddressOpValue(MI, Op: 2, Fixups, STI);
9428 Value |= (op & UINT64_C(15)) << 16;
9429 Value |= (op & UINT64_C(16));
9430 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9431 break;
9432 }
9433 case ARM::VLD3DUPd8:
9434 case ARM::VLD3DUPd16:
9435 case ARM::VLD3DUPd32:
9436 case ARM::VLD3DUPq8:
9437 case ARM::VLD3DUPq16:
9438 case ARM::VLD3DUPq32: {
9439 // op: Vd
9440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9441 Value |= (op & UINT64_C(16)) << 18;
9442 Value |= (op & UINT64_C(15)) << 12;
9443 // op: Rn
9444 op = getAddrMode6DupAddressOpValue(MI, Op: 3, Fixups, STI);
9445 op &= UINT64_C(15);
9446 op <<= 16;
9447 Value |= op;
9448 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9449 break;
9450 }
9451 case ARM::VLD4DUPd8:
9452 case ARM::VLD4DUPd16:
9453 case ARM::VLD4DUPq8:
9454 case ARM::VLD4DUPq16: {
9455 // op: Vd
9456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9457 Value |= (op & UINT64_C(16)) << 18;
9458 Value |= (op & UINT64_C(15)) << 12;
9459 // op: Rn
9460 op = getAddrMode6DupAddressOpValue(MI, Op: 4, Fixups, STI);
9461 Value |= (op & UINT64_C(15)) << 16;
9462 Value |= (op & UINT64_C(16));
9463 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9464 break;
9465 }
9466 case ARM::VLD4DUPd32:
9467 case ARM::VLD4DUPq32: {
9468 // op: Vd
9469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9470 Value |= (op & UINT64_C(16)) << 18;
9471 Value |= (op & UINT64_C(15)) << 12;
9472 // op: Rn
9473 op = getAddrMode6DupAddressOpValue(MI, Op: 4, Fixups, STI);
9474 Value |= (op & UINT64_C(15)) << 16;
9475 Value |= (op & UINT64_C(32)) << 1;
9476 Value |= (op & UINT64_C(16));
9477 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9478 break;
9479 }
9480 case ARM::VLD3DUPd8_UPD:
9481 case ARM::VLD3DUPd16_UPD:
9482 case ARM::VLD3DUPd32_UPD:
9483 case ARM::VLD3DUPq8_UPD:
9484 case ARM::VLD3DUPq16_UPD:
9485 case ARM::VLD3DUPq32_UPD: {
9486 // op: Vd
9487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9488 Value |= (op & UINT64_C(16)) << 18;
9489 Value |= (op & UINT64_C(15)) << 12;
9490 // op: Rn
9491 op = getAddrMode6DupAddressOpValue(MI, Op: 4, Fixups, STI);
9492 op &= UINT64_C(15);
9493 op <<= 16;
9494 Value |= op;
9495 // op: Rm
9496 op = getAddrMode6OffsetOpValue(MI, Op: 6, Fixups, STI);
9497 op &= UINT64_C(15);
9498 Value |= op;
9499 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9500 break;
9501 }
9502 case ARM::VLD4DUPd8_UPD:
9503 case ARM::VLD4DUPd16_UPD:
9504 case ARM::VLD4DUPq8_UPD:
9505 case ARM::VLD4DUPq16_UPD: {
9506 // op: Vd
9507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9508 Value |= (op & UINT64_C(16)) << 18;
9509 Value |= (op & UINT64_C(15)) << 12;
9510 // op: Rn
9511 op = getAddrMode6DupAddressOpValue(MI, Op: 5, Fixups, STI);
9512 Value |= (op & UINT64_C(15)) << 16;
9513 Value |= (op & UINT64_C(16));
9514 // op: Rm
9515 op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI);
9516 op &= UINT64_C(15);
9517 Value |= op;
9518 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9519 break;
9520 }
9521 case ARM::VLD4DUPd32_UPD:
9522 case ARM::VLD4DUPq32_UPD: {
9523 // op: Vd
9524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9525 Value |= (op & UINT64_C(16)) << 18;
9526 Value |= (op & UINT64_C(15)) << 12;
9527 // op: Rn
9528 op = getAddrMode6DupAddressOpValue(MI, Op: 5, Fixups, STI);
9529 Value |= (op & UINT64_C(15)) << 16;
9530 Value |= (op & UINT64_C(32)) << 1;
9531 Value |= (op & UINT64_C(16));
9532 // op: Rm
9533 op = getAddrMode6OffsetOpValue(MI, Op: 7, Fixups, STI);
9534 op &= UINT64_C(15);
9535 Value |= op;
9536 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9537 break;
9538 }
9539 case ARM::VLD1LNd32: {
9540 // op: Vd
9541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9542 Value |= (op & UINT64_C(16)) << 18;
9543 Value |= (op & UINT64_C(15)) << 12;
9544 // op: Rn
9545 op = getAddrMode6OneLane32AddressOpValue(MI, Op: 1, Fixups, STI);
9546 Value |= (op & UINT64_C(15)) << 16;
9547 Value |= (op & UINT64_C(48));
9548 // op: lane
9549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9550 op &= UINT64_C(1);
9551 op <<= 7;
9552 Value |= op;
9553 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
9554 break;
9555 }
9556 case ARM::VMOVv1i64:
9557 case ARM::VMOVv2f32:
9558 case ARM::VMOVv2i64:
9559 case ARM::VMOVv4f32:
9560 case ARM::VMOVv8i8:
9561 case ARM::VMOVv16i8: {
9562 // op: Vd
9563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9564 Value |= (op & UINT64_C(16)) << 18;
9565 Value |= (op & UINT64_C(15)) << 12;
9566 // op: SIMM
9567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9568 Value |= (op & UINT64_C(128)) << 17;
9569 Value |= (op & UINT64_C(112)) << 12;
9570 Value |= (op & UINT64_C(15));
9571 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9572 break;
9573 }
9574 case ARM::VBICiv2i32:
9575 case ARM::VBICiv4i32:
9576 case ARM::VORRiv2i32:
9577 case ARM::VORRiv4i32: {
9578 // op: Vd
9579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9580 Value |= (op & UINT64_C(16)) << 18;
9581 Value |= (op & UINT64_C(15)) << 12;
9582 // op: SIMM
9583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9584 Value |= (op & UINT64_C(128)) << 17;
9585 Value |= (op & UINT64_C(112)) << 12;
9586 Value |= (op & UINT64_C(1536));
9587 Value |= (op & UINT64_C(15));
9588 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9589 break;
9590 }
9591 case ARM::VMOVv2i32:
9592 case ARM::VMOVv4i32:
9593 case ARM::VMVNv2i32:
9594 case ARM::VMVNv4i32: {
9595 // op: Vd
9596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9597 Value |= (op & UINT64_C(16)) << 18;
9598 Value |= (op & UINT64_C(15)) << 12;
9599 // op: SIMM
9600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9601 Value |= (op & UINT64_C(128)) << 17;
9602 Value |= (op & UINT64_C(112)) << 12;
9603 Value |= (op & UINT64_C(3840));
9604 Value |= (op & UINT64_C(15));
9605 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9606 break;
9607 }
9608 case ARM::VBICiv4i16:
9609 case ARM::VBICiv8i16:
9610 case ARM::VMOVv4i16:
9611 case ARM::VMOVv8i16:
9612 case ARM::VMVNv4i16:
9613 case ARM::VMVNv8i16:
9614 case ARM::VORRiv4i16:
9615 case ARM::VORRiv8i16: {
9616 // op: Vd
9617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9618 Value |= (op & UINT64_C(16)) << 18;
9619 Value |= (op & UINT64_C(15)) << 12;
9620 // op: SIMM
9621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9622 Value |= (op & UINT64_C(128)) << 17;
9623 Value |= (op & UINT64_C(112)) << 12;
9624 Value |= (op & UINT64_C(512));
9625 Value |= (op & UINT64_C(15));
9626 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9627 break;
9628 }
9629 case ARM::VQSHLsiv4i16:
9630 case ARM::VQSHLsiv8i16:
9631 case ARM::VQSHLsuv4i16:
9632 case ARM::VQSHLsuv8i16:
9633 case ARM::VQSHLuiv4i16:
9634 case ARM::VQSHLuiv8i16:
9635 case ARM::VSHLLsv4i32:
9636 case ARM::VSHLLuv4i32:
9637 case ARM::VSHLiv4i16:
9638 case ARM::VSHLiv8i16: {
9639 // op: Vd
9640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9641 Value |= (op & UINT64_C(16)) << 18;
9642 Value |= (op & UINT64_C(15)) << 12;
9643 // op: Vm
9644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9645 Value |= (op & UINT64_C(16)) << 1;
9646 Value |= (op & UINT64_C(15));
9647 // op: SIMM
9648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9649 op &= UINT64_C(15);
9650 op <<= 16;
9651 Value |= op;
9652 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9653 break;
9654 }
9655 case ARM::VQSHLsiv2i32:
9656 case ARM::VQSHLsiv4i32:
9657 case ARM::VQSHLsuv2i32:
9658 case ARM::VQSHLsuv4i32:
9659 case ARM::VQSHLuiv2i32:
9660 case ARM::VQSHLuiv4i32:
9661 case ARM::VSHLLsv2i64:
9662 case ARM::VSHLLuv2i64:
9663 case ARM::VSHLiv2i32:
9664 case ARM::VSHLiv4i32: {
9665 // op: Vd
9666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9667 Value |= (op & UINT64_C(16)) << 18;
9668 Value |= (op & UINT64_C(15)) << 12;
9669 // op: Vm
9670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9671 Value |= (op & UINT64_C(16)) << 1;
9672 Value |= (op & UINT64_C(15));
9673 // op: SIMM
9674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9675 op &= UINT64_C(31);
9676 op <<= 16;
9677 Value |= op;
9678 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9679 break;
9680 }
9681 case ARM::VQSHLsiv1i64:
9682 case ARM::VQSHLsiv2i64:
9683 case ARM::VQSHLsuv1i64:
9684 case ARM::VQSHLsuv2i64:
9685 case ARM::VQSHLuiv1i64:
9686 case ARM::VQSHLuiv2i64:
9687 case ARM::VSHLiv1i64:
9688 case ARM::VSHLiv2i64: {
9689 // op: Vd
9690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9691 Value |= (op & UINT64_C(16)) << 18;
9692 Value |= (op & UINT64_C(15)) << 12;
9693 // op: Vm
9694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9695 Value |= (op & UINT64_C(16)) << 1;
9696 Value |= (op & UINT64_C(15));
9697 // op: SIMM
9698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9699 op &= UINT64_C(63);
9700 op <<= 16;
9701 Value |= op;
9702 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9703 break;
9704 }
9705 case ARM::VQSHLsiv8i8:
9706 case ARM::VQSHLsiv16i8:
9707 case ARM::VQSHLsuv8i8:
9708 case ARM::VQSHLsuv16i8:
9709 case ARM::VQSHLuiv8i8:
9710 case ARM::VQSHLuiv16i8:
9711 case ARM::VSHLLsv8i16:
9712 case ARM::VSHLLuv8i16:
9713 case ARM::VSHLiv8i8:
9714 case ARM::VSHLiv16i8: {
9715 // op: Vd
9716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9717 Value |= (op & UINT64_C(16)) << 18;
9718 Value |= (op & UINT64_C(15)) << 12;
9719 // op: Vm
9720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9721 Value |= (op & UINT64_C(16)) << 1;
9722 Value |= (op & UINT64_C(15));
9723 // op: SIMM
9724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9725 op &= UINT64_C(7);
9726 op <<= 16;
9727 Value |= op;
9728 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9729 break;
9730 }
9731 case ARM::VCVTf2xsd:
9732 case ARM::VCVTf2xsq:
9733 case ARM::VCVTf2xud:
9734 case ARM::VCVTf2xuq:
9735 case ARM::VCVTh2xsd:
9736 case ARM::VCVTh2xsq:
9737 case ARM::VCVTh2xud:
9738 case ARM::VCVTh2xuq:
9739 case ARM::VCVTxs2fd:
9740 case ARM::VCVTxs2fq:
9741 case ARM::VCVTxs2hd:
9742 case ARM::VCVTxs2hq:
9743 case ARM::VCVTxu2fd:
9744 case ARM::VCVTxu2fq:
9745 case ARM::VCVTxu2hd:
9746 case ARM::VCVTxu2hq: {
9747 // op: Vd
9748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9749 Value |= (op & UINT64_C(16)) << 18;
9750 Value |= (op & UINT64_C(15)) << 12;
9751 // op: Vm
9752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9753 Value |= (op & UINT64_C(16)) << 1;
9754 Value |= (op & UINT64_C(15));
9755 // op: SIMM
9756 op = getNEONVcvtImm32OpValue(MI, Op: 2, Fixups, STI);
9757 op &= UINT64_C(63);
9758 op <<= 16;
9759 Value |= op;
9760 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9761 break;
9762 }
9763 case ARM::VQRSHRNsv4i16:
9764 case ARM::VQRSHRNuv4i16:
9765 case ARM::VQRSHRUNv4i16:
9766 case ARM::VQSHRNsv4i16:
9767 case ARM::VQSHRNuv4i16:
9768 case ARM::VQSHRUNv4i16:
9769 case ARM::VRSHRNv4i16:
9770 case ARM::VRSHRsv4i16:
9771 case ARM::VRSHRsv8i16:
9772 case ARM::VRSHRuv4i16:
9773 case ARM::VRSHRuv8i16:
9774 case ARM::VSHRNv4i16:
9775 case ARM::VSHRsv4i16:
9776 case ARM::VSHRsv8i16:
9777 case ARM::VSHRuv4i16:
9778 case ARM::VSHRuv8i16: {
9779 // op: Vd
9780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9781 Value |= (op & UINT64_C(16)) << 18;
9782 Value |= (op & UINT64_C(15)) << 12;
9783 // op: Vm
9784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9785 Value |= (op & UINT64_C(16)) << 1;
9786 Value |= (op & UINT64_C(15));
9787 // op: SIMM
9788 op = getShiftRight16Imm(MI, Op: 2, Fixups, STI);
9789 op &= UINT64_C(15);
9790 op <<= 16;
9791 Value |= op;
9792 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9793 break;
9794 }
9795 case ARM::VQRSHRNsv2i32:
9796 case ARM::VQRSHRNuv2i32:
9797 case ARM::VQRSHRUNv2i32:
9798 case ARM::VQSHRNsv2i32:
9799 case ARM::VQSHRNuv2i32:
9800 case ARM::VQSHRUNv2i32:
9801 case ARM::VRSHRNv2i32:
9802 case ARM::VRSHRsv2i32:
9803 case ARM::VRSHRsv4i32:
9804 case ARM::VRSHRuv2i32:
9805 case ARM::VRSHRuv4i32:
9806 case ARM::VSHRNv2i32:
9807 case ARM::VSHRsv2i32:
9808 case ARM::VSHRsv4i32:
9809 case ARM::VSHRuv2i32:
9810 case ARM::VSHRuv4i32: {
9811 // op: Vd
9812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9813 Value |= (op & UINT64_C(16)) << 18;
9814 Value |= (op & UINT64_C(15)) << 12;
9815 // op: Vm
9816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9817 Value |= (op & UINT64_C(16)) << 1;
9818 Value |= (op & UINT64_C(15));
9819 // op: SIMM
9820 op = getShiftRight32Imm(MI, Op: 2, Fixups, STI);
9821 op &= UINT64_C(31);
9822 op <<= 16;
9823 Value |= op;
9824 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9825 break;
9826 }
9827 case ARM::VRSHRsv1i64:
9828 case ARM::VRSHRsv2i64:
9829 case ARM::VRSHRuv1i64:
9830 case ARM::VRSHRuv2i64:
9831 case ARM::VSHRsv1i64:
9832 case ARM::VSHRsv2i64:
9833 case ARM::VSHRuv1i64:
9834 case ARM::VSHRuv2i64: {
9835 // op: Vd
9836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9837 Value |= (op & UINT64_C(16)) << 18;
9838 Value |= (op & UINT64_C(15)) << 12;
9839 // op: Vm
9840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9841 Value |= (op & UINT64_C(16)) << 1;
9842 Value |= (op & UINT64_C(15));
9843 // op: SIMM
9844 op = getShiftRight64Imm(MI, Op: 2, Fixups, STI);
9845 op &= UINT64_C(63);
9846 op <<= 16;
9847 Value |= op;
9848 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9849 break;
9850 }
9851 case ARM::VQRSHRNsv8i8:
9852 case ARM::VQRSHRNuv8i8:
9853 case ARM::VQRSHRUNv8i8:
9854 case ARM::VQSHRNsv8i8:
9855 case ARM::VQSHRNuv8i8:
9856 case ARM::VQSHRUNv8i8:
9857 case ARM::VRSHRNv8i8:
9858 case ARM::VRSHRsv8i8:
9859 case ARM::VRSHRsv16i8:
9860 case ARM::VRSHRuv8i8:
9861 case ARM::VRSHRuv16i8:
9862 case ARM::VSHRNv8i8:
9863 case ARM::VSHRsv8i8:
9864 case ARM::VSHRsv16i8:
9865 case ARM::VSHRuv8i8:
9866 case ARM::VSHRuv16i8: {
9867 // op: Vd
9868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9869 Value |= (op & UINT64_C(16)) << 18;
9870 Value |= (op & UINT64_C(15)) << 12;
9871 // op: Vm
9872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9873 Value |= (op & UINT64_C(16)) << 1;
9874 Value |= (op & UINT64_C(15));
9875 // op: SIMM
9876 op = getShiftRight8Imm(MI, Op: 2, Fixups, STI);
9877 op &= UINT64_C(7);
9878 op <<= 16;
9879 Value |= op;
9880 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9881 break;
9882 }
9883 case ARM::VDUPLN32d:
9884 case ARM::VDUPLN32q: {
9885 // op: Vd
9886 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9887 Value |= (op & UINT64_C(16)) << 18;
9888 Value |= (op & UINT64_C(15)) << 12;
9889 // op: Vm
9890 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9891 Value |= (op & UINT64_C(16)) << 1;
9892 Value |= (op & UINT64_C(15));
9893 // op: lane
9894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9895 op &= UINT64_C(1);
9896 op <<= 19;
9897 Value |= op;
9898 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9899 break;
9900 }
9901 case ARM::VDUPLN16d:
9902 case ARM::VDUPLN16q: {
9903 // op: Vd
9904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9905 Value |= (op & UINT64_C(16)) << 18;
9906 Value |= (op & UINT64_C(15)) << 12;
9907 // op: Vm
9908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9909 Value |= (op & UINT64_C(16)) << 1;
9910 Value |= (op & UINT64_C(15));
9911 // op: lane
9912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9913 op &= UINT64_C(3);
9914 op <<= 18;
9915 Value |= op;
9916 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9917 break;
9918 }
9919 case ARM::VDUPLN8d:
9920 case ARM::VDUPLN8q: {
9921 // op: Vd
9922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9923 Value |= (op & UINT64_C(16)) << 18;
9924 Value |= (op & UINT64_C(15)) << 12;
9925 // op: Vm
9926 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9927 Value |= (op & UINT64_C(16)) << 1;
9928 Value |= (op & UINT64_C(15));
9929 // op: lane
9930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9931 op &= UINT64_C(7);
9932 op <<= 17;
9933 Value |= op;
9934 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
9935 break;
9936 }
9937 case ARM::AESIMC:
9938 case ARM::AESMC:
9939 case ARM::BF16_VCVT:
9940 case ARM::SHA1H:
9941 case ARM::VABSfd:
9942 case ARM::VABSfq:
9943 case ARM::VABShd:
9944 case ARM::VABShq:
9945 case ARM::VABSv2i32:
9946 case ARM::VABSv4i16:
9947 case ARM::VABSv4i32:
9948 case ARM::VABSv8i8:
9949 case ARM::VABSv8i16:
9950 case ARM::VABSv16i8:
9951 case ARM::VCEQzv2f32:
9952 case ARM::VCEQzv2i32:
9953 case ARM::VCEQzv4f16:
9954 case ARM::VCEQzv4f32:
9955 case ARM::VCEQzv4i16:
9956 case ARM::VCEQzv4i32:
9957 case ARM::VCEQzv8f16:
9958 case ARM::VCEQzv8i8:
9959 case ARM::VCEQzv8i16:
9960 case ARM::VCEQzv16i8:
9961 case ARM::VCGEzv2f32:
9962 case ARM::VCGEzv2i32:
9963 case ARM::VCGEzv4f16:
9964 case ARM::VCGEzv4f32:
9965 case ARM::VCGEzv4i16:
9966 case ARM::VCGEzv4i32:
9967 case ARM::VCGEzv8f16:
9968 case ARM::VCGEzv8i8:
9969 case ARM::VCGEzv8i16:
9970 case ARM::VCGEzv16i8:
9971 case ARM::VCGTzv2f32:
9972 case ARM::VCGTzv2i32:
9973 case ARM::VCGTzv4f16:
9974 case ARM::VCGTzv4f32:
9975 case ARM::VCGTzv4i16:
9976 case ARM::VCGTzv4i32:
9977 case ARM::VCGTzv8f16:
9978 case ARM::VCGTzv8i8:
9979 case ARM::VCGTzv8i16:
9980 case ARM::VCGTzv16i8:
9981 case ARM::VCLEzv2f32:
9982 case ARM::VCLEzv2i32:
9983 case ARM::VCLEzv4f16:
9984 case ARM::VCLEzv4f32:
9985 case ARM::VCLEzv4i16:
9986 case ARM::VCLEzv4i32:
9987 case ARM::VCLEzv8f16:
9988 case ARM::VCLEzv8i8:
9989 case ARM::VCLEzv8i16:
9990 case ARM::VCLEzv16i8:
9991 case ARM::VCLSv2i32:
9992 case ARM::VCLSv4i16:
9993 case ARM::VCLSv4i32:
9994 case ARM::VCLSv8i8:
9995 case ARM::VCLSv8i16:
9996 case ARM::VCLSv16i8:
9997 case ARM::VCLTzv2f32:
9998 case ARM::VCLTzv2i32:
9999 case ARM::VCLTzv4f16:
10000 case ARM::VCLTzv4f32:
10001 case ARM::VCLTzv4i16:
10002 case ARM::VCLTzv4i32:
10003 case ARM::VCLTzv8f16:
10004 case ARM::VCLTzv8i8:
10005 case ARM::VCLTzv8i16:
10006 case ARM::VCLTzv16i8:
10007 case ARM::VCLZv2i32:
10008 case ARM::VCLZv4i16:
10009 case ARM::VCLZv4i32:
10010 case ARM::VCLZv8i8:
10011 case ARM::VCLZv8i16:
10012 case ARM::VCLZv16i8:
10013 case ARM::VCNTd:
10014 case ARM::VCNTq:
10015 case ARM::VCVTf2h:
10016 case ARM::VCVTf2sd:
10017 case ARM::VCVTf2sq:
10018 case ARM::VCVTf2ud:
10019 case ARM::VCVTf2uq:
10020 case ARM::VCVTh2f:
10021 case ARM::VCVTh2sd:
10022 case ARM::VCVTh2sq:
10023 case ARM::VCVTh2ud:
10024 case ARM::VCVTh2uq:
10025 case ARM::VCVTs2fd:
10026 case ARM::VCVTs2fq:
10027 case ARM::VCVTs2hd:
10028 case ARM::VCVTs2hq:
10029 case ARM::VCVTu2fd:
10030 case ARM::VCVTu2fq:
10031 case ARM::VCVTu2hd:
10032 case ARM::VCVTu2hq:
10033 case ARM::VMOVLsv2i64:
10034 case ARM::VMOVLsv4i32:
10035 case ARM::VMOVLsv8i16:
10036 case ARM::VMOVLuv2i64:
10037 case ARM::VMOVLuv4i32:
10038 case ARM::VMOVLuv8i16:
10039 case ARM::VMOVNv2i32:
10040 case ARM::VMOVNv4i16:
10041 case ARM::VMOVNv8i8:
10042 case ARM::VMVNd:
10043 case ARM::VMVNq:
10044 case ARM::VNEGf32q:
10045 case ARM::VNEGfd:
10046 case ARM::VNEGhd:
10047 case ARM::VNEGhq:
10048 case ARM::VNEGs8d:
10049 case ARM::VNEGs8q:
10050 case ARM::VNEGs16d:
10051 case ARM::VNEGs16q:
10052 case ARM::VNEGs32d:
10053 case ARM::VNEGs32q:
10054 case ARM::VPADDLsv2i32:
10055 case ARM::VPADDLsv4i16:
10056 case ARM::VPADDLsv4i32:
10057 case ARM::VPADDLsv8i8:
10058 case ARM::VPADDLsv8i16:
10059 case ARM::VPADDLsv16i8:
10060 case ARM::VPADDLuv2i32:
10061 case ARM::VPADDLuv4i16:
10062 case ARM::VPADDLuv4i32:
10063 case ARM::VPADDLuv8i8:
10064 case ARM::VPADDLuv8i16:
10065 case ARM::VPADDLuv16i8:
10066 case ARM::VQABSv2i32:
10067 case ARM::VQABSv4i16:
10068 case ARM::VQABSv4i32:
10069 case ARM::VQABSv8i8:
10070 case ARM::VQABSv8i16:
10071 case ARM::VQABSv16i8:
10072 case ARM::VQMOVNsuv2i32:
10073 case ARM::VQMOVNsuv4i16:
10074 case ARM::VQMOVNsuv8i8:
10075 case ARM::VQMOVNsv2i32:
10076 case ARM::VQMOVNsv4i16:
10077 case ARM::VQMOVNsv8i8:
10078 case ARM::VQMOVNuv2i32:
10079 case ARM::VQMOVNuv4i16:
10080 case ARM::VQMOVNuv8i8:
10081 case ARM::VQNEGv2i32:
10082 case ARM::VQNEGv4i16:
10083 case ARM::VQNEGv4i32:
10084 case ARM::VQNEGv8i8:
10085 case ARM::VQNEGv8i16:
10086 case ARM::VQNEGv16i8:
10087 case ARM::VRECPEd:
10088 case ARM::VRECPEfd:
10089 case ARM::VRECPEfq:
10090 case ARM::VRECPEhd:
10091 case ARM::VRECPEhq:
10092 case ARM::VRECPEq:
10093 case ARM::VREV16d8:
10094 case ARM::VREV16q8:
10095 case ARM::VREV32d8:
10096 case ARM::VREV32d16:
10097 case ARM::VREV32q8:
10098 case ARM::VREV32q16:
10099 case ARM::VREV64d8:
10100 case ARM::VREV64d16:
10101 case ARM::VREV64d32:
10102 case ARM::VREV64q8:
10103 case ARM::VREV64q16:
10104 case ARM::VREV64q32:
10105 case ARM::VRSQRTEd:
10106 case ARM::VRSQRTEfd:
10107 case ARM::VRSQRTEfq:
10108 case ARM::VRSQRTEhd:
10109 case ARM::VRSQRTEhq:
10110 case ARM::VRSQRTEq:
10111 case ARM::VSHLLi8:
10112 case ARM::VSHLLi16:
10113 case ARM::VSHLLi32:
10114 case ARM::VSWPd:
10115 case ARM::VSWPq:
10116 case ARM::VTRNd8:
10117 case ARM::VTRNd16:
10118 case ARM::VTRNd32:
10119 case ARM::VTRNq8:
10120 case ARM::VTRNq16:
10121 case ARM::VTRNq32:
10122 case ARM::VUZPd8:
10123 case ARM::VUZPd16:
10124 case ARM::VUZPq8:
10125 case ARM::VUZPq16:
10126 case ARM::VUZPq32:
10127 case ARM::VZIPd8:
10128 case ARM::VZIPd16:
10129 case ARM::VZIPq8:
10130 case ARM::VZIPq16:
10131 case ARM::VZIPq32: {
10132 // op: Vd
10133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10134 Value |= (op & UINT64_C(16)) << 18;
10135 Value |= (op & UINT64_C(15)) << 12;
10136 // op: Vm
10137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10138 Value |= (op & UINT64_C(16)) << 1;
10139 Value |= (op & UINT64_C(15));
10140 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10141 break;
10142 }
10143 case ARM::VCVTANSDf:
10144 case ARM::VCVTANSDh:
10145 case ARM::VCVTANSQf:
10146 case ARM::VCVTANSQh:
10147 case ARM::VCVTANUDf:
10148 case ARM::VCVTANUDh:
10149 case ARM::VCVTANUQf:
10150 case ARM::VCVTANUQh:
10151 case ARM::VCVTMNSDf:
10152 case ARM::VCVTMNSDh:
10153 case ARM::VCVTMNSQf:
10154 case ARM::VCVTMNSQh:
10155 case ARM::VCVTMNUDf:
10156 case ARM::VCVTMNUDh:
10157 case ARM::VCVTMNUQf:
10158 case ARM::VCVTMNUQh:
10159 case ARM::VCVTNNSDf:
10160 case ARM::VCVTNNSDh:
10161 case ARM::VCVTNNSQf:
10162 case ARM::VCVTNNSQh:
10163 case ARM::VCVTNNUDf:
10164 case ARM::VCVTNNUDh:
10165 case ARM::VCVTNNUQf:
10166 case ARM::VCVTNNUQh:
10167 case ARM::VCVTPNSDf:
10168 case ARM::VCVTPNSDh:
10169 case ARM::VCVTPNSQf:
10170 case ARM::VCVTPNSQh:
10171 case ARM::VCVTPNUDf:
10172 case ARM::VCVTPNUDh:
10173 case ARM::VCVTPNUQf:
10174 case ARM::VCVTPNUQh:
10175 case ARM::VRINTANDf:
10176 case ARM::VRINTANDh:
10177 case ARM::VRINTANQf:
10178 case ARM::VRINTANQh:
10179 case ARM::VRINTMNDf:
10180 case ARM::VRINTMNDh:
10181 case ARM::VRINTMNQf:
10182 case ARM::VRINTMNQh:
10183 case ARM::VRINTNNDf:
10184 case ARM::VRINTNNDh:
10185 case ARM::VRINTNNQf:
10186 case ARM::VRINTNNQh:
10187 case ARM::VRINTPNDf:
10188 case ARM::VRINTPNDh:
10189 case ARM::VRINTPNQf:
10190 case ARM::VRINTPNQh:
10191 case ARM::VRINTXNDf:
10192 case ARM::VRINTXNDh:
10193 case ARM::VRINTXNQf:
10194 case ARM::VRINTXNQh:
10195 case ARM::VRINTZNDf:
10196 case ARM::VRINTZNDh:
10197 case ARM::VRINTZNQf:
10198 case ARM::VRINTZNQh: {
10199 // op: Vd
10200 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10201 Value |= (op & UINT64_C(16)) << 18;
10202 Value |= (op & UINT64_C(15)) << 12;
10203 // op: Vm
10204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10205 Value |= (op & UINT64_C(16)) << 1;
10206 Value |= (op & UINT64_C(15));
10207 Value = NEONThumb2V8PostEncoder(MI, EncodedValue: Value, STI);
10208 break;
10209 }
10210 case ARM::VSLIv4i16:
10211 case ARM::VSLIv8i16: {
10212 // op: Vd
10213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10214 Value |= (op & UINT64_C(16)) << 18;
10215 Value |= (op & UINT64_C(15)) << 12;
10216 // op: Vm
10217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10218 Value |= (op & UINT64_C(16)) << 1;
10219 Value |= (op & UINT64_C(15));
10220 // op: SIMM
10221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10222 op &= UINT64_C(15);
10223 op <<= 16;
10224 Value |= op;
10225 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10226 break;
10227 }
10228 case ARM::VSLIv2i32:
10229 case ARM::VSLIv4i32: {
10230 // op: Vd
10231 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10232 Value |= (op & UINT64_C(16)) << 18;
10233 Value |= (op & UINT64_C(15)) << 12;
10234 // op: Vm
10235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10236 Value |= (op & UINT64_C(16)) << 1;
10237 Value |= (op & UINT64_C(15));
10238 // op: SIMM
10239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10240 op &= UINT64_C(31);
10241 op <<= 16;
10242 Value |= op;
10243 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10244 break;
10245 }
10246 case ARM::VSLIv1i64:
10247 case ARM::VSLIv2i64: {
10248 // op: Vd
10249 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10250 Value |= (op & UINT64_C(16)) << 18;
10251 Value |= (op & UINT64_C(15)) << 12;
10252 // op: Vm
10253 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10254 Value |= (op & UINT64_C(16)) << 1;
10255 Value |= (op & UINT64_C(15));
10256 // op: SIMM
10257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10258 op &= UINT64_C(63);
10259 op <<= 16;
10260 Value |= op;
10261 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10262 break;
10263 }
10264 case ARM::VSLIv8i8:
10265 case ARM::VSLIv16i8: {
10266 // op: Vd
10267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10268 Value |= (op & UINT64_C(16)) << 18;
10269 Value |= (op & UINT64_C(15)) << 12;
10270 // op: Vm
10271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10272 Value |= (op & UINT64_C(16)) << 1;
10273 Value |= (op & UINT64_C(15));
10274 // op: SIMM
10275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10276 op &= UINT64_C(7);
10277 op <<= 16;
10278 Value |= op;
10279 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10280 break;
10281 }
10282 case ARM::VRSRAsv4i16:
10283 case ARM::VRSRAsv8i16:
10284 case ARM::VRSRAuv4i16:
10285 case ARM::VRSRAuv8i16:
10286 case ARM::VSRAsv4i16:
10287 case ARM::VSRAsv8i16:
10288 case ARM::VSRAuv4i16:
10289 case ARM::VSRAuv8i16:
10290 case ARM::VSRIv4i16:
10291 case ARM::VSRIv8i16: {
10292 // op: Vd
10293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10294 Value |= (op & UINT64_C(16)) << 18;
10295 Value |= (op & UINT64_C(15)) << 12;
10296 // op: Vm
10297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10298 Value |= (op & UINT64_C(16)) << 1;
10299 Value |= (op & UINT64_C(15));
10300 // op: SIMM
10301 op = getShiftRight16Imm(MI, Op: 3, Fixups, STI);
10302 op &= UINT64_C(15);
10303 op <<= 16;
10304 Value |= op;
10305 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10306 break;
10307 }
10308 case ARM::VRSRAsv2i32:
10309 case ARM::VRSRAsv4i32:
10310 case ARM::VRSRAuv2i32:
10311 case ARM::VRSRAuv4i32:
10312 case ARM::VSRAsv2i32:
10313 case ARM::VSRAsv4i32:
10314 case ARM::VSRAuv2i32:
10315 case ARM::VSRAuv4i32:
10316 case ARM::VSRIv2i32:
10317 case ARM::VSRIv4i32: {
10318 // op: Vd
10319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10320 Value |= (op & UINT64_C(16)) << 18;
10321 Value |= (op & UINT64_C(15)) << 12;
10322 // op: Vm
10323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10324 Value |= (op & UINT64_C(16)) << 1;
10325 Value |= (op & UINT64_C(15));
10326 // op: SIMM
10327 op = getShiftRight32Imm(MI, Op: 3, Fixups, STI);
10328 op &= UINT64_C(31);
10329 op <<= 16;
10330 Value |= op;
10331 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10332 break;
10333 }
10334 case ARM::VRSRAsv1i64:
10335 case ARM::VRSRAsv2i64:
10336 case ARM::VRSRAuv1i64:
10337 case ARM::VRSRAuv2i64:
10338 case ARM::VSRAsv1i64:
10339 case ARM::VSRAsv2i64:
10340 case ARM::VSRAuv1i64:
10341 case ARM::VSRAuv2i64:
10342 case ARM::VSRIv1i64:
10343 case ARM::VSRIv2i64: {
10344 // op: Vd
10345 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10346 Value |= (op & UINT64_C(16)) << 18;
10347 Value |= (op & UINT64_C(15)) << 12;
10348 // op: Vm
10349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10350 Value |= (op & UINT64_C(16)) << 1;
10351 Value |= (op & UINT64_C(15));
10352 // op: SIMM
10353 op = getShiftRight64Imm(MI, Op: 3, Fixups, STI);
10354 op &= UINT64_C(63);
10355 op <<= 16;
10356 Value |= op;
10357 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10358 break;
10359 }
10360 case ARM::VRSRAsv8i8:
10361 case ARM::VRSRAsv16i8:
10362 case ARM::VRSRAuv8i8:
10363 case ARM::VRSRAuv16i8:
10364 case ARM::VSRAsv8i8:
10365 case ARM::VSRAsv16i8:
10366 case ARM::VSRAuv8i8:
10367 case ARM::VSRAuv16i8:
10368 case ARM::VSRIv8i8:
10369 case ARM::VSRIv16i8: {
10370 // op: Vd
10371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10372 Value |= (op & UINT64_C(16)) << 18;
10373 Value |= (op & UINT64_C(15)) << 12;
10374 // op: Vm
10375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10376 Value |= (op & UINT64_C(16)) << 1;
10377 Value |= (op & UINT64_C(15));
10378 // op: SIMM
10379 op = getShiftRight8Imm(MI, Op: 3, Fixups, STI);
10380 op &= UINT64_C(7);
10381 op <<= 16;
10382 Value |= op;
10383 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10384 break;
10385 }
10386 case ARM::AESD:
10387 case ARM::AESE:
10388 case ARM::SHA1SU1:
10389 case ARM::SHA256SU0:
10390 case ARM::VPADALsv2i32:
10391 case ARM::VPADALsv4i16:
10392 case ARM::VPADALsv4i32:
10393 case ARM::VPADALsv8i8:
10394 case ARM::VPADALsv8i16:
10395 case ARM::VPADALsv16i8:
10396 case ARM::VPADALuv2i32:
10397 case ARM::VPADALuv4i16:
10398 case ARM::VPADALuv4i32:
10399 case ARM::VPADALuv8i8:
10400 case ARM::VPADALuv8i16:
10401 case ARM::VPADALuv16i8: {
10402 // op: Vd
10403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10404 Value |= (op & UINT64_C(16)) << 18;
10405 Value |= (op & UINT64_C(15)) << 12;
10406 // op: Vm
10407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10408 Value |= (op & UINT64_C(16)) << 1;
10409 Value |= (op & UINT64_C(15));
10410 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10411 break;
10412 }
10413 case ARM::VFMALQ:
10414 case ARM::VFMSLQ: {
10415 // op: Vd
10416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10417 Value |= (op & UINT64_C(16)) << 18;
10418 Value |= (op & UINT64_C(15)) << 12;
10419 // op: Vn
10420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10421 Value |= (op & UINT64_C(15)) << 16;
10422 Value |= (op & UINT64_C(16)) << 3;
10423 // op: Vm
10424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10425 Value |= (op & UINT64_C(16)) << 1;
10426 Value |= (op & UINT64_C(15));
10427 break;
10428 }
10429 case ARM::VEXTd32: {
10430 // op: Vd
10431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10432 Value |= (op & UINT64_C(16)) << 18;
10433 Value |= (op & UINT64_C(15)) << 12;
10434 // op: Vn
10435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10436 Value |= (op & UINT64_C(15)) << 16;
10437 Value |= (op & UINT64_C(16)) << 3;
10438 // op: Vm
10439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10440 Value |= (op & UINT64_C(16)) << 1;
10441 Value |= (op & UINT64_C(15));
10442 // op: index
10443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10444 op &= UINT64_C(1);
10445 op <<= 10;
10446 Value |= op;
10447 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10448 break;
10449 }
10450 case ARM::VEXTq64: {
10451 // op: Vd
10452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10453 Value |= (op & UINT64_C(16)) << 18;
10454 Value |= (op & UINT64_C(15)) << 12;
10455 // op: Vn
10456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10457 Value |= (op & UINT64_C(15)) << 16;
10458 Value |= (op & UINT64_C(16)) << 3;
10459 // op: Vm
10460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10461 Value |= (op & UINT64_C(16)) << 1;
10462 Value |= (op & UINT64_C(15));
10463 // op: index
10464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10465 op &= UINT64_C(1);
10466 op <<= 11;
10467 Value |= op;
10468 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10469 break;
10470 }
10471 case ARM::VEXTq8: {
10472 // op: Vd
10473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10474 Value |= (op & UINT64_C(16)) << 18;
10475 Value |= (op & UINT64_C(15)) << 12;
10476 // op: Vn
10477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10478 Value |= (op & UINT64_C(15)) << 16;
10479 Value |= (op & UINT64_C(16)) << 3;
10480 // op: Vm
10481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10482 Value |= (op & UINT64_C(16)) << 1;
10483 Value |= (op & UINT64_C(15));
10484 // op: index
10485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10486 op &= UINT64_C(15);
10487 op <<= 8;
10488 Value |= op;
10489 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10490 break;
10491 }
10492 case ARM::VEXTq32: {
10493 // op: Vd
10494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10495 Value |= (op & UINT64_C(16)) << 18;
10496 Value |= (op & UINT64_C(15)) << 12;
10497 // op: Vn
10498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10499 Value |= (op & UINT64_C(15)) << 16;
10500 Value |= (op & UINT64_C(16)) << 3;
10501 // op: Vm
10502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10503 Value |= (op & UINT64_C(16)) << 1;
10504 Value |= (op & UINT64_C(15));
10505 // op: index
10506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10507 op &= UINT64_C(3);
10508 op <<= 10;
10509 Value |= op;
10510 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10511 break;
10512 }
10513 case ARM::VEXTd16: {
10514 // op: Vd
10515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10516 Value |= (op & UINT64_C(16)) << 18;
10517 Value |= (op & UINT64_C(15)) << 12;
10518 // op: Vn
10519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10520 Value |= (op & UINT64_C(15)) << 16;
10521 Value |= (op & UINT64_C(16)) << 3;
10522 // op: Vm
10523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10524 Value |= (op & UINT64_C(16)) << 1;
10525 Value |= (op & UINT64_C(15));
10526 // op: index
10527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10528 op &= UINT64_C(3);
10529 op <<= 9;
10530 Value |= op;
10531 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10532 break;
10533 }
10534 case ARM::VEXTd8: {
10535 // op: Vd
10536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10537 Value |= (op & UINT64_C(16)) << 18;
10538 Value |= (op & UINT64_C(15)) << 12;
10539 // op: Vn
10540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10541 Value |= (op & UINT64_C(15)) << 16;
10542 Value |= (op & UINT64_C(16)) << 3;
10543 // op: Vm
10544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10545 Value |= (op & UINT64_C(16)) << 1;
10546 Value |= (op & UINT64_C(15));
10547 // op: index
10548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10549 op &= UINT64_C(7);
10550 op <<= 8;
10551 Value |= op;
10552 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10553 break;
10554 }
10555 case ARM::VEXTq16: {
10556 // op: Vd
10557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10558 Value |= (op & UINT64_C(16)) << 18;
10559 Value |= (op & UINT64_C(15)) << 12;
10560 // op: Vn
10561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10562 Value |= (op & UINT64_C(15)) << 16;
10563 Value |= (op & UINT64_C(16)) << 3;
10564 // op: Vm
10565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10566 Value |= (op & UINT64_C(16)) << 1;
10567 Value |= (op & UINT64_C(15));
10568 // op: index
10569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10570 op &= UINT64_C(7);
10571 op <<= 9;
10572 Value |= op;
10573 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10574 break;
10575 }
10576 case ARM::VCADDv2f32:
10577 case ARM::VCADDv4f16:
10578 case ARM::VCADDv4f32:
10579 case ARM::VCADDv8f16: {
10580 // op: Vd
10581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10582 Value |= (op & UINT64_C(16)) << 18;
10583 Value |= (op & UINT64_C(15)) << 12;
10584 // op: Vn
10585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10586 Value |= (op & UINT64_C(15)) << 16;
10587 Value |= (op & UINT64_C(16)) << 3;
10588 // op: Vm
10589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10590 Value |= (op & UINT64_C(16)) << 1;
10591 Value |= (op & UINT64_C(15));
10592 // op: rot
10593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10594 op &= UINT64_C(1);
10595 op <<= 24;
10596 Value |= op;
10597 break;
10598 }
10599 case ARM::VABDLsv2i64:
10600 case ARM::VABDLsv4i32:
10601 case ARM::VABDLsv8i16:
10602 case ARM::VABDLuv2i64:
10603 case ARM::VABDLuv4i32:
10604 case ARM::VABDLuv8i16:
10605 case ARM::VABDfd:
10606 case ARM::VABDfq:
10607 case ARM::VABDhd:
10608 case ARM::VABDhq:
10609 case ARM::VABDsv2i32:
10610 case ARM::VABDsv4i16:
10611 case ARM::VABDsv4i32:
10612 case ARM::VABDsv8i8:
10613 case ARM::VABDsv8i16:
10614 case ARM::VABDsv16i8:
10615 case ARM::VABDuv2i32:
10616 case ARM::VABDuv4i16:
10617 case ARM::VABDuv4i32:
10618 case ARM::VABDuv8i8:
10619 case ARM::VABDuv8i16:
10620 case ARM::VABDuv16i8:
10621 case ARM::VACGEfd:
10622 case ARM::VACGEfq:
10623 case ARM::VACGEhd:
10624 case ARM::VACGEhq:
10625 case ARM::VACGTfd:
10626 case ARM::VACGTfq:
10627 case ARM::VACGThd:
10628 case ARM::VACGThq:
10629 case ARM::VADDHNv2i32:
10630 case ARM::VADDHNv4i16:
10631 case ARM::VADDHNv8i8:
10632 case ARM::VADDLsv2i64:
10633 case ARM::VADDLsv4i32:
10634 case ARM::VADDLsv8i16:
10635 case ARM::VADDLuv2i64:
10636 case ARM::VADDLuv4i32:
10637 case ARM::VADDLuv8i16:
10638 case ARM::VADDWsv2i64:
10639 case ARM::VADDWsv4i32:
10640 case ARM::VADDWsv8i16:
10641 case ARM::VADDWuv2i64:
10642 case ARM::VADDWuv4i32:
10643 case ARM::VADDWuv8i16:
10644 case ARM::VADDfd:
10645 case ARM::VADDfq:
10646 case ARM::VADDhd:
10647 case ARM::VADDhq:
10648 case ARM::VADDv1i64:
10649 case ARM::VADDv2i32:
10650 case ARM::VADDv2i64:
10651 case ARM::VADDv4i16:
10652 case ARM::VADDv4i32:
10653 case ARM::VADDv8i8:
10654 case ARM::VADDv8i16:
10655 case ARM::VADDv16i8:
10656 case ARM::VANDd:
10657 case ARM::VANDq:
10658 case ARM::VBICd:
10659 case ARM::VBICq:
10660 case ARM::VCEQfd:
10661 case ARM::VCEQfq:
10662 case ARM::VCEQhd:
10663 case ARM::VCEQhq:
10664 case ARM::VCEQv2i32:
10665 case ARM::VCEQv4i16:
10666 case ARM::VCEQv4i32:
10667 case ARM::VCEQv8i8:
10668 case ARM::VCEQv8i16:
10669 case ARM::VCEQv16i8:
10670 case ARM::VCGEfd:
10671 case ARM::VCGEfq:
10672 case ARM::VCGEhd:
10673 case ARM::VCGEhq:
10674 case ARM::VCGEsv2i32:
10675 case ARM::VCGEsv4i16:
10676 case ARM::VCGEsv4i32:
10677 case ARM::VCGEsv8i8:
10678 case ARM::VCGEsv8i16:
10679 case ARM::VCGEsv16i8:
10680 case ARM::VCGEuv2i32:
10681 case ARM::VCGEuv4i16:
10682 case ARM::VCGEuv4i32:
10683 case ARM::VCGEuv8i8:
10684 case ARM::VCGEuv8i16:
10685 case ARM::VCGEuv16i8:
10686 case ARM::VCGTfd:
10687 case ARM::VCGTfq:
10688 case ARM::VCGThd:
10689 case ARM::VCGThq:
10690 case ARM::VCGTsv2i32:
10691 case ARM::VCGTsv4i16:
10692 case ARM::VCGTsv4i32:
10693 case ARM::VCGTsv8i8:
10694 case ARM::VCGTsv8i16:
10695 case ARM::VCGTsv16i8:
10696 case ARM::VCGTuv2i32:
10697 case ARM::VCGTuv4i16:
10698 case ARM::VCGTuv4i32:
10699 case ARM::VCGTuv8i8:
10700 case ARM::VCGTuv8i16:
10701 case ARM::VCGTuv16i8:
10702 case ARM::VEORd:
10703 case ARM::VEORq:
10704 case ARM::VHADDsv2i32:
10705 case ARM::VHADDsv4i16:
10706 case ARM::VHADDsv4i32:
10707 case ARM::VHADDsv8i8:
10708 case ARM::VHADDsv8i16:
10709 case ARM::VHADDsv16i8:
10710 case ARM::VHADDuv2i32:
10711 case ARM::VHADDuv4i16:
10712 case ARM::VHADDuv4i32:
10713 case ARM::VHADDuv8i8:
10714 case ARM::VHADDuv8i16:
10715 case ARM::VHADDuv16i8:
10716 case ARM::VHSUBsv2i32:
10717 case ARM::VHSUBsv4i16:
10718 case ARM::VHSUBsv4i32:
10719 case ARM::VHSUBsv8i8:
10720 case ARM::VHSUBsv8i16:
10721 case ARM::VHSUBsv16i8:
10722 case ARM::VHSUBuv2i32:
10723 case ARM::VHSUBuv4i16:
10724 case ARM::VHSUBuv4i32:
10725 case ARM::VHSUBuv8i8:
10726 case ARM::VHSUBuv8i16:
10727 case ARM::VHSUBuv16i8:
10728 case ARM::VMAXfd:
10729 case ARM::VMAXfq:
10730 case ARM::VMAXhd:
10731 case ARM::VMAXhq:
10732 case ARM::VMAXsv2i32:
10733 case ARM::VMAXsv4i16:
10734 case ARM::VMAXsv4i32:
10735 case ARM::VMAXsv8i8:
10736 case ARM::VMAXsv8i16:
10737 case ARM::VMAXsv16i8:
10738 case ARM::VMAXuv2i32:
10739 case ARM::VMAXuv4i16:
10740 case ARM::VMAXuv4i32:
10741 case ARM::VMAXuv8i8:
10742 case ARM::VMAXuv8i16:
10743 case ARM::VMAXuv16i8:
10744 case ARM::VMINfd:
10745 case ARM::VMINfq:
10746 case ARM::VMINhd:
10747 case ARM::VMINhq:
10748 case ARM::VMINsv2i32:
10749 case ARM::VMINsv4i16:
10750 case ARM::VMINsv4i32:
10751 case ARM::VMINsv8i8:
10752 case ARM::VMINsv8i16:
10753 case ARM::VMINsv16i8:
10754 case ARM::VMINuv2i32:
10755 case ARM::VMINuv4i16:
10756 case ARM::VMINuv4i32:
10757 case ARM::VMINuv8i8:
10758 case ARM::VMINuv8i16:
10759 case ARM::VMINuv16i8:
10760 case ARM::VMULLp8:
10761 case ARM::VMULLp64:
10762 case ARM::VMULLsv2i64:
10763 case ARM::VMULLsv4i32:
10764 case ARM::VMULLsv8i16:
10765 case ARM::VMULLuv2i64:
10766 case ARM::VMULLuv4i32:
10767 case ARM::VMULLuv8i16:
10768 case ARM::VMULfd:
10769 case ARM::VMULfq:
10770 case ARM::VMULhd:
10771 case ARM::VMULhq:
10772 case ARM::VMULpd:
10773 case ARM::VMULpq:
10774 case ARM::VMULv2i32:
10775 case ARM::VMULv4i16:
10776 case ARM::VMULv4i32:
10777 case ARM::VMULv8i8:
10778 case ARM::VMULv8i16:
10779 case ARM::VMULv16i8:
10780 case ARM::VORNd:
10781 case ARM::VORNq:
10782 case ARM::VORRd:
10783 case ARM::VORRq:
10784 case ARM::VPADDf:
10785 case ARM::VPADDh:
10786 case ARM::VPADDi8:
10787 case ARM::VPADDi16:
10788 case ARM::VPADDi32:
10789 case ARM::VPMAXf:
10790 case ARM::VPMAXh:
10791 case ARM::VPMAXs8:
10792 case ARM::VPMAXs16:
10793 case ARM::VPMAXs32:
10794 case ARM::VPMAXu8:
10795 case ARM::VPMAXu16:
10796 case ARM::VPMAXu32:
10797 case ARM::VPMINf:
10798 case ARM::VPMINh:
10799 case ARM::VPMINs8:
10800 case ARM::VPMINs16:
10801 case ARM::VPMINs32:
10802 case ARM::VPMINu8:
10803 case ARM::VPMINu16:
10804 case ARM::VPMINu32:
10805 case ARM::VQADDsv1i64:
10806 case ARM::VQADDsv2i32:
10807 case ARM::VQADDsv2i64:
10808 case ARM::VQADDsv4i16:
10809 case ARM::VQADDsv4i32:
10810 case ARM::VQADDsv8i8:
10811 case ARM::VQADDsv8i16:
10812 case ARM::VQADDsv16i8:
10813 case ARM::VQADDuv1i64:
10814 case ARM::VQADDuv2i32:
10815 case ARM::VQADDuv2i64:
10816 case ARM::VQADDuv4i16:
10817 case ARM::VQADDuv4i32:
10818 case ARM::VQADDuv8i8:
10819 case ARM::VQADDuv8i16:
10820 case ARM::VQADDuv16i8:
10821 case ARM::VQDMULHv2i32:
10822 case ARM::VQDMULHv4i16:
10823 case ARM::VQDMULHv4i32:
10824 case ARM::VQDMULHv8i16:
10825 case ARM::VQDMULLv2i64:
10826 case ARM::VQDMULLv4i32:
10827 case ARM::VQRDMULHv2i32:
10828 case ARM::VQRDMULHv4i16:
10829 case ARM::VQRDMULHv4i32:
10830 case ARM::VQRDMULHv8i16:
10831 case ARM::VQSUBsv1i64:
10832 case ARM::VQSUBsv2i32:
10833 case ARM::VQSUBsv2i64:
10834 case ARM::VQSUBsv4i16:
10835 case ARM::VQSUBsv4i32:
10836 case ARM::VQSUBsv8i8:
10837 case ARM::VQSUBsv8i16:
10838 case ARM::VQSUBsv16i8:
10839 case ARM::VQSUBuv1i64:
10840 case ARM::VQSUBuv2i32:
10841 case ARM::VQSUBuv2i64:
10842 case ARM::VQSUBuv4i16:
10843 case ARM::VQSUBuv4i32:
10844 case ARM::VQSUBuv8i8:
10845 case ARM::VQSUBuv8i16:
10846 case ARM::VQSUBuv16i8:
10847 case ARM::VRADDHNv2i32:
10848 case ARM::VRADDHNv4i16:
10849 case ARM::VRADDHNv8i8:
10850 case ARM::VRECPSfd:
10851 case ARM::VRECPSfq:
10852 case ARM::VRECPShd:
10853 case ARM::VRECPShq:
10854 case ARM::VRHADDsv2i32:
10855 case ARM::VRHADDsv4i16:
10856 case ARM::VRHADDsv4i32:
10857 case ARM::VRHADDsv8i8:
10858 case ARM::VRHADDsv8i16:
10859 case ARM::VRHADDsv16i8:
10860 case ARM::VRHADDuv2i32:
10861 case ARM::VRHADDuv4i16:
10862 case ARM::VRHADDuv4i32:
10863 case ARM::VRHADDuv8i8:
10864 case ARM::VRHADDuv8i16:
10865 case ARM::VRHADDuv16i8:
10866 case ARM::VRSQRTSfd:
10867 case ARM::VRSQRTSfq:
10868 case ARM::VRSQRTShd:
10869 case ARM::VRSQRTShq:
10870 case ARM::VRSUBHNv2i32:
10871 case ARM::VRSUBHNv4i16:
10872 case ARM::VRSUBHNv8i8:
10873 case ARM::VSUBHNv2i32:
10874 case ARM::VSUBHNv4i16:
10875 case ARM::VSUBHNv8i8:
10876 case ARM::VSUBLsv2i64:
10877 case ARM::VSUBLsv4i32:
10878 case ARM::VSUBLsv8i16:
10879 case ARM::VSUBLuv2i64:
10880 case ARM::VSUBLuv4i32:
10881 case ARM::VSUBLuv8i16:
10882 case ARM::VSUBWsv2i64:
10883 case ARM::VSUBWsv4i32:
10884 case ARM::VSUBWsv8i16:
10885 case ARM::VSUBWuv2i64:
10886 case ARM::VSUBWuv4i32:
10887 case ARM::VSUBWuv8i16:
10888 case ARM::VSUBfd:
10889 case ARM::VSUBfq:
10890 case ARM::VSUBhd:
10891 case ARM::VSUBhq:
10892 case ARM::VSUBv1i64:
10893 case ARM::VSUBv2i32:
10894 case ARM::VSUBv2i64:
10895 case ARM::VSUBv4i16:
10896 case ARM::VSUBv4i32:
10897 case ARM::VSUBv8i8:
10898 case ARM::VSUBv8i16:
10899 case ARM::VSUBv16i8:
10900 case ARM::VTBL1:
10901 case ARM::VTBL2:
10902 case ARM::VTBL3:
10903 case ARM::VTBL4:
10904 case ARM::VTSTv2i32:
10905 case ARM::VTSTv4i16:
10906 case ARM::VTSTv4i32:
10907 case ARM::VTSTv8i8:
10908 case ARM::VTSTv8i16:
10909 case ARM::VTSTv16i8: {
10910 // op: Vd
10911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10912 Value |= (op & UINT64_C(16)) << 18;
10913 Value |= (op & UINT64_C(15)) << 12;
10914 // op: Vn
10915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10916 Value |= (op & UINT64_C(15)) << 16;
10917 Value |= (op & UINT64_C(16)) << 3;
10918 // op: Vm
10919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10920 Value |= (op & UINT64_C(16)) << 1;
10921 Value |= (op & UINT64_C(15));
10922 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10923 break;
10924 }
10925 case ARM::NEON_VMAXNMNDf:
10926 case ARM::NEON_VMAXNMNDh:
10927 case ARM::NEON_VMAXNMNQf:
10928 case ARM::NEON_VMAXNMNQh:
10929 case ARM::NEON_VMINNMNDf:
10930 case ARM::NEON_VMINNMNDh:
10931 case ARM::NEON_VMINNMNQf:
10932 case ARM::NEON_VMINNMNQh: {
10933 // op: Vd
10934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10935 Value |= (op & UINT64_C(16)) << 18;
10936 Value |= (op & UINT64_C(15)) << 12;
10937 // op: Vn
10938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10939 Value |= (op & UINT64_C(15)) << 16;
10940 Value |= (op & UINT64_C(16)) << 3;
10941 // op: Vm
10942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10943 Value |= (op & UINT64_C(16)) << 1;
10944 Value |= (op & UINT64_C(15));
10945 Value = NEONThumb2V8PostEncoder(MI, EncodedValue: Value, STI);
10946 break;
10947 }
10948 case ARM::VMULLslsv2i32:
10949 case ARM::VMULLsluv2i32:
10950 case ARM::VMULslfd:
10951 case ARM::VMULslfq:
10952 case ARM::VMULslv2i32:
10953 case ARM::VMULslv4i32:
10954 case ARM::VQDMULHslv2i32:
10955 case ARM::VQDMULHslv4i32:
10956 case ARM::VQDMULLslv2i32:
10957 case ARM::VQRDMULHslv2i32:
10958 case ARM::VQRDMULHslv4i32: {
10959 // op: Vd
10960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10961 Value |= (op & UINT64_C(16)) << 18;
10962 Value |= (op & UINT64_C(15)) << 12;
10963 // op: Vn
10964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10965 Value |= (op & UINT64_C(15)) << 16;
10966 Value |= (op & UINT64_C(16)) << 3;
10967 // op: Vm
10968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10969 op &= UINT64_C(15);
10970 Value |= op;
10971 // op: lane
10972 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10973 op &= UINT64_C(1);
10974 op <<= 5;
10975 Value |= op;
10976 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
10977 break;
10978 }
10979 case ARM::VFMALQI:
10980 case ARM::VFMSLQI: {
10981 // op: Vd
10982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10983 Value |= (op & UINT64_C(16)) << 18;
10984 Value |= (op & UINT64_C(15)) << 12;
10985 // op: Vn
10986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10987 Value |= (op & UINT64_C(15)) << 16;
10988 Value |= (op & UINT64_C(16)) << 3;
10989 // op: Vm
10990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10991 op &= UINT64_C(7);
10992 Value |= op;
10993 // op: idx
10994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10995 Value |= (op & UINT64_C(2)) << 4;
10996 Value |= (op & UINT64_C(1)) << 3;
10997 break;
10998 }
10999 case ARM::VMULLslsv4i16:
11000 case ARM::VMULLsluv4i16:
11001 case ARM::VMULslhd:
11002 case ARM::VMULslhq:
11003 case ARM::VMULslv4i16:
11004 case ARM::VMULslv8i16:
11005 case ARM::VQDMULHslv4i16:
11006 case ARM::VQDMULHslv8i16:
11007 case ARM::VQDMULLslv4i16:
11008 case ARM::VQRDMULHslv4i16:
11009 case ARM::VQRDMULHslv8i16: {
11010 // op: Vd
11011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11012 Value |= (op & UINT64_C(16)) << 18;
11013 Value |= (op & UINT64_C(15)) << 12;
11014 // op: Vn
11015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11016 Value |= (op & UINT64_C(15)) << 16;
11017 Value |= (op & UINT64_C(16)) << 3;
11018 // op: Vm
11019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11020 op &= UINT64_C(7);
11021 Value |= op;
11022 // op: lane
11023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11024 Value |= (op & UINT64_C(2)) << 4;
11025 Value |= (op & UINT64_C(1)) << 3;
11026 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
11027 break;
11028 }
11029 case ARM::VFMALDI:
11030 case ARM::VFMSLDI: {
11031 // op: Vd
11032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11033 Value |= (op & UINT64_C(16)) << 18;
11034 Value |= (op & UINT64_C(15)) << 12;
11035 // op: Vn
11036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11037 Value |= (op & UINT64_C(30)) << 15;
11038 Value |= (op & UINT64_C(1)) << 7;
11039 // op: Vm
11040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11041 Value |= (op & UINT64_C(1)) << 5;
11042 Value |= (op & UINT64_C(14)) >> 1;
11043 // op: idx
11044 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11045 op &= UINT64_C(1);
11046 op <<= 3;
11047 Value |= op;
11048 break;
11049 }
11050 case ARM::VFMALD:
11051 case ARM::VFMSLD: {
11052 // op: Vd
11053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11054 Value |= (op & UINT64_C(16)) << 18;
11055 Value |= (op & UINT64_C(15)) << 12;
11056 // op: Vn
11057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11058 Value |= (op & UINT64_C(30)) << 15;
11059 Value |= (op & UINT64_C(1)) << 7;
11060 // op: Vm
11061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11062 Value |= (op & UINT64_C(1)) << 5;
11063 Value |= (op & UINT64_C(30)) >> 1;
11064 break;
11065 }
11066 case ARM::VQRSHLsv1i64:
11067 case ARM::VQRSHLsv2i32:
11068 case ARM::VQRSHLsv2i64:
11069 case ARM::VQRSHLsv4i16:
11070 case ARM::VQRSHLsv4i32:
11071 case ARM::VQRSHLsv8i8:
11072 case ARM::VQRSHLsv8i16:
11073 case ARM::VQRSHLsv16i8:
11074 case ARM::VQRSHLuv1i64:
11075 case ARM::VQRSHLuv2i32:
11076 case ARM::VQRSHLuv2i64:
11077 case ARM::VQRSHLuv4i16:
11078 case ARM::VQRSHLuv4i32:
11079 case ARM::VQRSHLuv8i8:
11080 case ARM::VQRSHLuv8i16:
11081 case ARM::VQRSHLuv16i8:
11082 case ARM::VQSHLsv1i64:
11083 case ARM::VQSHLsv2i32:
11084 case ARM::VQSHLsv2i64:
11085 case ARM::VQSHLsv4i16:
11086 case ARM::VQSHLsv4i32:
11087 case ARM::VQSHLsv8i8:
11088 case ARM::VQSHLsv8i16:
11089 case ARM::VQSHLsv16i8:
11090 case ARM::VQSHLuv1i64:
11091 case ARM::VQSHLuv2i32:
11092 case ARM::VQSHLuv2i64:
11093 case ARM::VQSHLuv4i16:
11094 case ARM::VQSHLuv4i32:
11095 case ARM::VQSHLuv8i8:
11096 case ARM::VQSHLuv8i16:
11097 case ARM::VQSHLuv16i8:
11098 case ARM::VRSHLsv1i64:
11099 case ARM::VRSHLsv2i32:
11100 case ARM::VRSHLsv2i64:
11101 case ARM::VRSHLsv4i16:
11102 case ARM::VRSHLsv4i32:
11103 case ARM::VRSHLsv8i8:
11104 case ARM::VRSHLsv8i16:
11105 case ARM::VRSHLsv16i8:
11106 case ARM::VRSHLuv1i64:
11107 case ARM::VRSHLuv2i32:
11108 case ARM::VRSHLuv2i64:
11109 case ARM::VRSHLuv4i16:
11110 case ARM::VRSHLuv4i32:
11111 case ARM::VRSHLuv8i8:
11112 case ARM::VRSHLuv8i16:
11113 case ARM::VRSHLuv16i8:
11114 case ARM::VSHLsv1i64:
11115 case ARM::VSHLsv2i32:
11116 case ARM::VSHLsv2i64:
11117 case ARM::VSHLsv4i16:
11118 case ARM::VSHLsv4i32:
11119 case ARM::VSHLsv8i8:
11120 case ARM::VSHLsv8i16:
11121 case ARM::VSHLsv16i8:
11122 case ARM::VSHLuv1i64:
11123 case ARM::VSHLuv2i32:
11124 case ARM::VSHLuv2i64:
11125 case ARM::VSHLuv4i16:
11126 case ARM::VSHLuv4i32:
11127 case ARM::VSHLuv8i8:
11128 case ARM::VSHLuv8i16:
11129 case ARM::VSHLuv16i8: {
11130 // op: Vd
11131 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11132 Value |= (op & UINT64_C(16)) << 18;
11133 Value |= (op & UINT64_C(15)) << 12;
11134 // op: Vn
11135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11136 Value |= (op & UINT64_C(15)) << 16;
11137 Value |= (op & UINT64_C(16)) << 3;
11138 // op: Vm
11139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11140 Value |= (op & UINT64_C(16)) << 1;
11141 Value |= (op & UINT64_C(15));
11142 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
11143 break;
11144 }
11145 case ARM::VCMLAv2f32:
11146 case ARM::VCMLAv4f16:
11147 case ARM::VCMLAv4f32:
11148 case ARM::VCMLAv8f16: {
11149 // op: Vd
11150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11151 Value |= (op & UINT64_C(16)) << 18;
11152 Value |= (op & UINT64_C(15)) << 12;
11153 // op: Vn
11154 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11155 Value |= (op & UINT64_C(15)) << 16;
11156 Value |= (op & UINT64_C(16)) << 3;
11157 // op: Vm
11158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11159 Value |= (op & UINT64_C(16)) << 1;
11160 Value |= (op & UINT64_C(15));
11161 // op: rot
11162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11163 op &= UINT64_C(3);
11164 op <<= 23;
11165 Value |= op;
11166 break;
11167 }
11168 case ARM::VCMLAv2f32_indexed:
11169 case ARM::VCMLAv4f32_indexed: {
11170 // op: Vd
11171 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11172 Value |= (op & UINT64_C(16)) << 18;
11173 Value |= (op & UINT64_C(15)) << 12;
11174 // op: Vn
11175 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11176 Value |= (op & UINT64_C(15)) << 16;
11177 Value |= (op & UINT64_C(16)) << 3;
11178 // op: Vm
11179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11180 Value |= (op & UINT64_C(16)) << 1;
11181 Value |= (op & UINT64_C(15));
11182 // op: rot
11183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
11184 op &= UINT64_C(3);
11185 op <<= 20;
11186 Value |= op;
11187 break;
11188 }
11189 case ARM::SHA1C:
11190 case ARM::SHA1M:
11191 case ARM::SHA1P:
11192 case ARM::SHA1SU0:
11193 case ARM::SHA256H:
11194 case ARM::SHA256H2:
11195 case ARM::SHA256SU1:
11196 case ARM::VABALsv2i64:
11197 case ARM::VABALsv4i32:
11198 case ARM::VABALsv8i16:
11199 case ARM::VABALuv2i64:
11200 case ARM::VABALuv4i32:
11201 case ARM::VABALuv8i16:
11202 case ARM::VABAsv2i32:
11203 case ARM::VABAsv4i16:
11204 case ARM::VABAsv4i32:
11205 case ARM::VABAsv8i8:
11206 case ARM::VABAsv8i16:
11207 case ARM::VABAsv16i8:
11208 case ARM::VABAuv2i32:
11209 case ARM::VABAuv4i16:
11210 case ARM::VABAuv4i32:
11211 case ARM::VABAuv8i8:
11212 case ARM::VABAuv8i16:
11213 case ARM::VABAuv16i8:
11214 case ARM::VBIFd:
11215 case ARM::VBIFq:
11216 case ARM::VBITd:
11217 case ARM::VBITq:
11218 case ARM::VBSLd:
11219 case ARM::VBSLq:
11220 case ARM::VFMAfd:
11221 case ARM::VFMAfq:
11222 case ARM::VFMAhd:
11223 case ARM::VFMAhq:
11224 case ARM::VFMSfd:
11225 case ARM::VFMSfq:
11226 case ARM::VFMShd:
11227 case ARM::VFMShq:
11228 case ARM::VMLALsv2i64:
11229 case ARM::VMLALsv4i32:
11230 case ARM::VMLALsv8i16:
11231 case ARM::VMLALuv2i64:
11232 case ARM::VMLALuv4i32:
11233 case ARM::VMLALuv8i16:
11234 case ARM::VMLAfd:
11235 case ARM::VMLAfq:
11236 case ARM::VMLAhd:
11237 case ARM::VMLAhq:
11238 case ARM::VMLAv2i32:
11239 case ARM::VMLAv4i16:
11240 case ARM::VMLAv4i32:
11241 case ARM::VMLAv8i8:
11242 case ARM::VMLAv8i16:
11243 case ARM::VMLAv16i8:
11244 case ARM::VMLSLsv2i64:
11245 case ARM::VMLSLsv4i32:
11246 case ARM::VMLSLsv8i16:
11247 case ARM::VMLSLuv2i64:
11248 case ARM::VMLSLuv4i32:
11249 case ARM::VMLSLuv8i16:
11250 case ARM::VMLSfd:
11251 case ARM::VMLSfq:
11252 case ARM::VMLShd:
11253 case ARM::VMLShq:
11254 case ARM::VMLSv2i32:
11255 case ARM::VMLSv4i16:
11256 case ARM::VMLSv4i32:
11257 case ARM::VMLSv8i8:
11258 case ARM::VMLSv8i16:
11259 case ARM::VMLSv16i8:
11260 case ARM::VQDMLALv2i64:
11261 case ARM::VQDMLALv4i32:
11262 case ARM::VQDMLSLv2i64:
11263 case ARM::VQDMLSLv4i32:
11264 case ARM::VQRDMLAHv2i32:
11265 case ARM::VQRDMLAHv4i16:
11266 case ARM::VQRDMLAHv4i32:
11267 case ARM::VQRDMLAHv8i16:
11268 case ARM::VQRDMLSHv2i32:
11269 case ARM::VQRDMLSHv4i16:
11270 case ARM::VQRDMLSHv4i32:
11271 case ARM::VQRDMLSHv8i16:
11272 case ARM::VTBX1:
11273 case ARM::VTBX2:
11274 case ARM::VTBX3:
11275 case ARM::VTBX4: {
11276 // op: Vd
11277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11278 Value |= (op & UINT64_C(16)) << 18;
11279 Value |= (op & UINT64_C(15)) << 12;
11280 // op: Vn
11281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11282 Value |= (op & UINT64_C(15)) << 16;
11283 Value |= (op & UINT64_C(16)) << 3;
11284 // op: Vm
11285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11286 Value |= (op & UINT64_C(16)) << 1;
11287 Value |= (op & UINT64_C(15));
11288 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
11289 break;
11290 }
11291 case ARM::VMLALslsv2i32:
11292 case ARM::VMLALsluv2i32:
11293 case ARM::VMLAslfd:
11294 case ARM::VMLAslfq:
11295 case ARM::VMLAslv2i32:
11296 case ARM::VMLAslv4i32:
11297 case ARM::VMLSLslsv2i32:
11298 case ARM::VMLSLsluv2i32:
11299 case ARM::VMLSslfd:
11300 case ARM::VMLSslfq:
11301 case ARM::VMLSslv2i32:
11302 case ARM::VMLSslv4i32:
11303 case ARM::VQDMLALslv2i32:
11304 case ARM::VQDMLSLslv2i32:
11305 case ARM::VQRDMLAHslv2i32:
11306 case ARM::VQRDMLAHslv4i32:
11307 case ARM::VQRDMLSHslv2i32:
11308 case ARM::VQRDMLSHslv4i32: {
11309 // op: Vd
11310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11311 Value |= (op & UINT64_C(16)) << 18;
11312 Value |= (op & UINT64_C(15)) << 12;
11313 // op: Vn
11314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11315 Value |= (op & UINT64_C(15)) << 16;
11316 Value |= (op & UINT64_C(16)) << 3;
11317 // op: Vm
11318 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11319 op &= UINT64_C(15);
11320 Value |= op;
11321 // op: lane
11322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11323 op &= UINT64_C(1);
11324 op <<= 5;
11325 Value |= op;
11326 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
11327 break;
11328 }
11329 case ARM::VCMLAv4f16_indexed:
11330 case ARM::VCMLAv8f16_indexed: {
11331 // op: Vd
11332 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11333 Value |= (op & UINT64_C(16)) << 18;
11334 Value |= (op & UINT64_C(15)) << 12;
11335 // op: Vn
11336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11337 Value |= (op & UINT64_C(15)) << 16;
11338 Value |= (op & UINT64_C(16)) << 3;
11339 // op: Vm
11340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11341 op &= UINT64_C(15);
11342 Value |= op;
11343 // op: rot
11344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
11345 op &= UINT64_C(3);
11346 op <<= 20;
11347 Value |= op;
11348 // op: lane
11349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11350 op &= UINT64_C(1);
11351 op <<= 5;
11352 Value |= op;
11353 break;
11354 }
11355 case ARM::VMLALslsv4i16:
11356 case ARM::VMLALsluv4i16:
11357 case ARM::VMLAslhd:
11358 case ARM::VMLAslhq:
11359 case ARM::VMLAslv4i16:
11360 case ARM::VMLAslv8i16:
11361 case ARM::VMLSLslsv4i16:
11362 case ARM::VMLSLsluv4i16:
11363 case ARM::VMLSslhd:
11364 case ARM::VMLSslhq:
11365 case ARM::VMLSslv4i16:
11366 case ARM::VMLSslv8i16:
11367 case ARM::VQDMLALslv4i16:
11368 case ARM::VQDMLSLslv4i16:
11369 case ARM::VQRDMLAHslv4i16:
11370 case ARM::VQRDMLAHslv8i16:
11371 case ARM::VQRDMLSHslv4i16:
11372 case ARM::VQRDMLSHslv8i16: {
11373 // op: Vd
11374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11375 Value |= (op & UINT64_C(16)) << 18;
11376 Value |= (op & UINT64_C(15)) << 12;
11377 // op: Vn
11378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11379 Value |= (op & UINT64_C(15)) << 16;
11380 Value |= (op & UINT64_C(16)) << 3;
11381 // op: Vm
11382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11383 op &= UINT64_C(7);
11384 Value |= op;
11385 // op: lane
11386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11387 Value |= (op & UINT64_C(2)) << 4;
11388 Value |= (op & UINT64_C(1)) << 3;
11389 Value = NEONThumb2DataIPostEncoder(MI, EncodedValue: Value, STI);
11390 break;
11391 }
11392 case ARM::BF16VDOTS_VDOTD:
11393 case ARM::BF16VDOTS_VDOTQ:
11394 case ARM::VBF16MALBQ:
11395 case ARM::VBF16MALTQ:
11396 case ARM::VMMLA:
11397 case ARM::VSDOTD:
11398 case ARM::VSDOTQ:
11399 case ARM::VSMMLA:
11400 case ARM::VUDOTD:
11401 case ARM::VUDOTQ:
11402 case ARM::VUMMLA:
11403 case ARM::VUSDOTD:
11404 case ARM::VUSDOTQ:
11405 case ARM::VUSMMLA: {
11406 // op: Vd
11407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11408 Value |= (op & UINT64_C(16)) << 18;
11409 Value |= (op & UINT64_C(15)) << 12;
11410 // op: Vn
11411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11412 Value |= (op & UINT64_C(15)) << 16;
11413 Value |= (op & UINT64_C(16)) << 3;
11414 // op: Vm
11415 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11416 Value |= (op & UINT64_C(16)) << 1;
11417 Value |= (op & UINT64_C(15));
11418 break;
11419 }
11420 case ARM::BF16VDOTI_VDOTD:
11421 case ARM::BF16VDOTI_VDOTQ:
11422 case ARM::VSDOTDI:
11423 case ARM::VSDOTQI:
11424 case ARM::VSUDOTDI:
11425 case ARM::VSUDOTQI:
11426 case ARM::VUDOTDI:
11427 case ARM::VUDOTQI:
11428 case ARM::VUSDOTDI:
11429 case ARM::VUSDOTQI: {
11430 // op: Vd
11431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11432 Value |= (op & UINT64_C(16)) << 18;
11433 Value |= (op & UINT64_C(15)) << 12;
11434 // op: Vn
11435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11436 Value |= (op & UINT64_C(15)) << 16;
11437 Value |= (op & UINT64_C(16)) << 3;
11438 // op: Vm
11439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11440 op &= UINT64_C(15);
11441 Value |= op;
11442 // op: lane
11443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11444 op &= UINT64_C(1);
11445 op <<= 5;
11446 Value |= op;
11447 break;
11448 }
11449 case ARM::VBF16MALBQI:
11450 case ARM::VBF16MALTQI: {
11451 // op: Vd
11452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11453 Value |= (op & UINT64_C(16)) << 18;
11454 Value |= (op & UINT64_C(15)) << 12;
11455 // op: Vn
11456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11457 Value |= (op & UINT64_C(15)) << 16;
11458 Value |= (op & UINT64_C(16)) << 3;
11459 // op: Vm
11460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11461 op &= UINT64_C(7);
11462 Value |= op;
11463 // op: idx
11464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11465 Value |= (op & UINT64_C(2)) << 4;
11466 Value |= (op & UINT64_C(1)) << 3;
11467 break;
11468 }
11469 case ARM::VST1LNd16: {
11470 // op: Vd
11471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11472 Value |= (op & UINT64_C(16)) << 18;
11473 Value |= (op & UINT64_C(15)) << 12;
11474 // op: Rn
11475 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11476 Value |= (op & UINT64_C(15)) << 16;
11477 Value |= (op & UINT64_C(16));
11478 // op: lane
11479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11480 op &= UINT64_C(3);
11481 op <<= 6;
11482 Value |= op;
11483 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11484 break;
11485 }
11486 case ARM::VST2LNd32:
11487 case ARM::VST2LNq32: {
11488 // op: Vd
11489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11490 Value |= (op & UINT64_C(16)) << 18;
11491 Value |= (op & UINT64_C(15)) << 12;
11492 // op: Rn
11493 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11494 Value |= (op & UINT64_C(15)) << 16;
11495 Value |= (op & UINT64_C(16));
11496 // op: lane
11497 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11498 op &= UINT64_C(1);
11499 op <<= 7;
11500 Value |= op;
11501 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11502 break;
11503 }
11504 case ARM::VST2LNd16:
11505 case ARM::VST2LNq16: {
11506 // op: Vd
11507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11508 Value |= (op & UINT64_C(16)) << 18;
11509 Value |= (op & UINT64_C(15)) << 12;
11510 // op: Rn
11511 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11512 Value |= (op & UINT64_C(15)) << 16;
11513 Value |= (op & UINT64_C(16));
11514 // op: lane
11515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11516 op &= UINT64_C(3);
11517 op <<= 6;
11518 Value |= op;
11519 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11520 break;
11521 }
11522 case ARM::VST2LNd8: {
11523 // op: Vd
11524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11525 Value |= (op & UINT64_C(16)) << 18;
11526 Value |= (op & UINT64_C(15)) << 12;
11527 // op: Rn
11528 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11529 Value |= (op & UINT64_C(15)) << 16;
11530 Value |= (op & UINT64_C(16));
11531 // op: lane
11532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11533 op &= UINT64_C(7);
11534 op <<= 5;
11535 Value |= op;
11536 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11537 break;
11538 }
11539 case ARM::VST4LNd16:
11540 case ARM::VST4LNq16: {
11541 // op: Vd
11542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11543 Value |= (op & UINT64_C(16)) << 18;
11544 Value |= (op & UINT64_C(15)) << 12;
11545 // op: Rn
11546 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11547 Value |= (op & UINT64_C(15)) << 16;
11548 Value |= (op & UINT64_C(16));
11549 // op: lane
11550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
11551 op &= UINT64_C(3);
11552 op <<= 6;
11553 Value |= op;
11554 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11555 break;
11556 }
11557 case ARM::VST4LNd8: {
11558 // op: Vd
11559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11560 Value |= (op & UINT64_C(16)) << 18;
11561 Value |= (op & UINT64_C(15)) << 12;
11562 // op: Rn
11563 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11564 Value |= (op & UINT64_C(15)) << 16;
11565 Value |= (op & UINT64_C(16));
11566 // op: lane
11567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
11568 op &= UINT64_C(7);
11569 op <<= 5;
11570 Value |= op;
11571 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11572 break;
11573 }
11574 case ARM::VST1d8:
11575 case ARM::VST1d8T:
11576 case ARM::VST1d16:
11577 case ARM::VST1d16T:
11578 case ARM::VST1d32:
11579 case ARM::VST1d32T:
11580 case ARM::VST1d64:
11581 case ARM::VST1d64T:
11582 case ARM::VST3d8:
11583 case ARM::VST3d16:
11584 case ARM::VST3d32:
11585 case ARM::VST3q8:
11586 case ARM::VST3q16:
11587 case ARM::VST3q32: {
11588 // op: Vd
11589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11590 Value |= (op & UINT64_C(16)) << 18;
11591 Value |= (op & UINT64_C(15)) << 12;
11592 // op: Rn
11593 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11594 Value |= (op & UINT64_C(15)) << 16;
11595 Value |= (op & UINT64_C(16));
11596 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11597 break;
11598 }
11599 case ARM::VST4LNd32:
11600 case ARM::VST4LNq32: {
11601 // op: Vd
11602 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11603 Value |= (op & UINT64_C(16)) << 18;
11604 Value |= (op & UINT64_C(15)) << 12;
11605 // op: Rn
11606 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11607 Value |= (op & UINT64_C(15)) << 16;
11608 Value |= (op & UINT64_C(48));
11609 // op: lane
11610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
11611 op &= UINT64_C(1);
11612 op <<= 7;
11613 Value |= op;
11614 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11615 break;
11616 }
11617 case ARM::VST1d8Q:
11618 case ARM::VST1d16Q:
11619 case ARM::VST1d32Q:
11620 case ARM::VST1d64Q:
11621 case ARM::VST1q8:
11622 case ARM::VST1q16:
11623 case ARM::VST1q32:
11624 case ARM::VST1q64:
11625 case ARM::VST2b8:
11626 case ARM::VST2b16:
11627 case ARM::VST2b32:
11628 case ARM::VST2d8:
11629 case ARM::VST2d16:
11630 case ARM::VST2d32:
11631 case ARM::VST2q8:
11632 case ARM::VST2q16:
11633 case ARM::VST2q32:
11634 case ARM::VST4d8:
11635 case ARM::VST4d16:
11636 case ARM::VST4d32:
11637 case ARM::VST4q8:
11638 case ARM::VST4q16:
11639 case ARM::VST4q32: {
11640 // op: Vd
11641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11642 Value |= (op & UINT64_C(16)) << 18;
11643 Value |= (op & UINT64_C(15)) << 12;
11644 // op: Rn
11645 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11646 Value |= (op & UINT64_C(15)) << 16;
11647 Value |= (op & UINT64_C(48));
11648 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11649 break;
11650 }
11651 case ARM::VST1LNd8: {
11652 // op: Vd
11653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11654 Value |= (op & UINT64_C(16)) << 18;
11655 Value |= (op & UINT64_C(15)) << 12;
11656 // op: Rn
11657 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11658 op &= UINT64_C(15);
11659 op <<= 16;
11660 Value |= op;
11661 // op: lane
11662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11663 op &= UINT64_C(7);
11664 op <<= 5;
11665 Value |= op;
11666 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11667 break;
11668 }
11669 case ARM::VST3LNd32:
11670 case ARM::VST3LNq32: {
11671 // op: Vd
11672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11673 Value |= (op & UINT64_C(16)) << 18;
11674 Value |= (op & UINT64_C(15)) << 12;
11675 // op: Rn
11676 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11677 op &= UINT64_C(15);
11678 op <<= 16;
11679 Value |= op;
11680 // op: lane
11681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
11682 op &= UINT64_C(1);
11683 op <<= 7;
11684 Value |= op;
11685 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11686 break;
11687 }
11688 case ARM::VST3LNd16:
11689 case ARM::VST3LNq16: {
11690 // op: Vd
11691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11692 Value |= (op & UINT64_C(16)) << 18;
11693 Value |= (op & UINT64_C(15)) << 12;
11694 // op: Rn
11695 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11696 op &= UINT64_C(15);
11697 op <<= 16;
11698 Value |= op;
11699 // op: lane
11700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
11701 op &= UINT64_C(3);
11702 op <<= 6;
11703 Value |= op;
11704 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11705 break;
11706 }
11707 case ARM::VST3LNd8: {
11708 // op: Vd
11709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11710 Value |= (op & UINT64_C(16)) << 18;
11711 Value |= (op & UINT64_C(15)) << 12;
11712 // op: Rn
11713 op = getAddrMode6AddressOpValue(MI, Op: 0, Fixups, STI);
11714 op &= UINT64_C(15);
11715 op <<= 16;
11716 Value |= op;
11717 // op: lane
11718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
11719 op &= UINT64_C(7);
11720 op <<= 5;
11721 Value |= op;
11722 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11723 break;
11724 }
11725 case ARM::VST1LNd32: {
11726 // op: Vd
11727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11728 Value |= (op & UINT64_C(16)) << 18;
11729 Value |= (op & UINT64_C(15)) << 12;
11730 // op: Rn
11731 op = getAddrMode6OneLane32AddressOpValue(MI, Op: 0, Fixups, STI);
11732 Value |= (op & UINT64_C(15)) << 16;
11733 Value |= (op & UINT64_C(48));
11734 // op: lane
11735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11736 op &= UINT64_C(1);
11737 op <<= 7;
11738 Value |= op;
11739 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11740 break;
11741 }
11742 case ARM::VST1d8wb_fixed:
11743 case ARM::VST1d16wb_fixed:
11744 case ARM::VST1d32wb_fixed:
11745 case ARM::VST1d64wb_fixed: {
11746 // op: Vd
11747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11748 Value |= (op & UINT64_C(16)) << 18;
11749 Value |= (op & UINT64_C(15)) << 12;
11750 // op: Rn
11751 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11752 Value |= (op & UINT64_C(15)) << 16;
11753 Value |= (op & UINT64_C(16));
11754 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11755 break;
11756 }
11757 case ARM::VST1d8Qwb_fixed:
11758 case ARM::VST1d8Twb_fixed:
11759 case ARM::VST1d16Qwb_fixed:
11760 case ARM::VST1d16Twb_fixed:
11761 case ARM::VST1d32Qwb_fixed:
11762 case ARM::VST1d32Twb_fixed:
11763 case ARM::VST1d64Qwb_fixed:
11764 case ARM::VST1d64Twb_fixed:
11765 case ARM::VST1q8wb_fixed:
11766 case ARM::VST1q16wb_fixed:
11767 case ARM::VST1q32wb_fixed:
11768 case ARM::VST1q64wb_fixed:
11769 case ARM::VST2b8wb_fixed:
11770 case ARM::VST2b16wb_fixed:
11771 case ARM::VST2b32wb_fixed:
11772 case ARM::VST2d8wb_fixed:
11773 case ARM::VST2d16wb_fixed:
11774 case ARM::VST2d32wb_fixed:
11775 case ARM::VST2q8wb_fixed:
11776 case ARM::VST2q16wb_fixed:
11777 case ARM::VST2q32wb_fixed: {
11778 // op: Vd
11779 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11780 Value |= (op & UINT64_C(16)) << 18;
11781 Value |= (op & UINT64_C(15)) << 12;
11782 // op: Rn
11783 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11784 Value |= (op & UINT64_C(15)) << 16;
11785 Value |= (op & UINT64_C(48));
11786 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11787 break;
11788 }
11789 case ARM::VST1LNd16_UPD: {
11790 // op: Vd
11791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11792 Value |= (op & UINT64_C(16)) << 18;
11793 Value |= (op & UINT64_C(15)) << 12;
11794 // op: Rn
11795 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11796 Value |= (op & UINT64_C(15)) << 16;
11797 Value |= (op & UINT64_C(16));
11798 // op: Rm
11799 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11800 op &= UINT64_C(15);
11801 Value |= op;
11802 // op: lane
11803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
11804 op &= UINT64_C(3);
11805 op <<= 6;
11806 Value |= op;
11807 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11808 break;
11809 }
11810 case ARM::VST2LNd32_UPD:
11811 case ARM::VST2LNq32_UPD: {
11812 // op: Vd
11813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11814 Value |= (op & UINT64_C(16)) << 18;
11815 Value |= (op & UINT64_C(15)) << 12;
11816 // op: Rn
11817 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11818 Value |= (op & UINT64_C(15)) << 16;
11819 Value |= (op & UINT64_C(16));
11820 // op: Rm
11821 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11822 op &= UINT64_C(15);
11823 Value |= op;
11824 // op: lane
11825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
11826 op &= UINT64_C(1);
11827 op <<= 7;
11828 Value |= op;
11829 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11830 break;
11831 }
11832 case ARM::VST2LNd16_UPD:
11833 case ARM::VST2LNq16_UPD: {
11834 // op: Vd
11835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11836 Value |= (op & UINT64_C(16)) << 18;
11837 Value |= (op & UINT64_C(15)) << 12;
11838 // op: Rn
11839 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11840 Value |= (op & UINT64_C(15)) << 16;
11841 Value |= (op & UINT64_C(16));
11842 // op: Rm
11843 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11844 op &= UINT64_C(15);
11845 Value |= op;
11846 // op: lane
11847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
11848 op &= UINT64_C(3);
11849 op <<= 6;
11850 Value |= op;
11851 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11852 break;
11853 }
11854 case ARM::VST2LNd8_UPD: {
11855 // op: Vd
11856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11857 Value |= (op & UINT64_C(16)) << 18;
11858 Value |= (op & UINT64_C(15)) << 12;
11859 // op: Rn
11860 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11861 Value |= (op & UINT64_C(15)) << 16;
11862 Value |= (op & UINT64_C(16));
11863 // op: Rm
11864 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11865 op &= UINT64_C(15);
11866 Value |= op;
11867 // op: lane
11868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
11869 op &= UINT64_C(7);
11870 op <<= 5;
11871 Value |= op;
11872 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11873 break;
11874 }
11875 case ARM::VST4LNd16_UPD:
11876 case ARM::VST4LNq16_UPD: {
11877 // op: Vd
11878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11879 Value |= (op & UINT64_C(16)) << 18;
11880 Value |= (op & UINT64_C(15)) << 12;
11881 // op: Rn
11882 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11883 Value |= (op & UINT64_C(15)) << 16;
11884 Value |= (op & UINT64_C(16));
11885 // op: Rm
11886 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11887 op &= UINT64_C(15);
11888 Value |= op;
11889 // op: lane
11890 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
11891 op &= UINT64_C(3);
11892 op <<= 6;
11893 Value |= op;
11894 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11895 break;
11896 }
11897 case ARM::VST4LNd8_UPD: {
11898 // op: Vd
11899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11900 Value |= (op & UINT64_C(16)) << 18;
11901 Value |= (op & UINT64_C(15)) << 12;
11902 // op: Rn
11903 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11904 Value |= (op & UINT64_C(15)) << 16;
11905 Value |= (op & UINT64_C(16));
11906 // op: Rm
11907 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11908 op &= UINT64_C(15);
11909 Value |= op;
11910 // op: lane
11911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
11912 op &= UINT64_C(7);
11913 op <<= 5;
11914 Value |= op;
11915 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11916 break;
11917 }
11918 case ARM::VST3d8_UPD:
11919 case ARM::VST3d16_UPD:
11920 case ARM::VST3d32_UPD:
11921 case ARM::VST3q8_UPD:
11922 case ARM::VST3q16_UPD:
11923 case ARM::VST3q32_UPD: {
11924 // op: Vd
11925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11926 Value |= (op & UINT64_C(16)) << 18;
11927 Value |= (op & UINT64_C(15)) << 12;
11928 // op: Rn
11929 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11930 Value |= (op & UINT64_C(15)) << 16;
11931 Value |= (op & UINT64_C(16));
11932 // op: Rm
11933 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11934 op &= UINT64_C(15);
11935 Value |= op;
11936 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11937 break;
11938 }
11939 case ARM::VST1d8wb_register:
11940 case ARM::VST1d16wb_register:
11941 case ARM::VST1d32wb_register:
11942 case ARM::VST1d64wb_register: {
11943 // op: Vd
11944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11945 Value |= (op & UINT64_C(16)) << 18;
11946 Value |= (op & UINT64_C(15)) << 12;
11947 // op: Rn
11948 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11949 Value |= (op & UINT64_C(15)) << 16;
11950 Value |= (op & UINT64_C(16));
11951 // op: Rm
11952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11953 op &= UINT64_C(15);
11954 Value |= op;
11955 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11956 break;
11957 }
11958 case ARM::VST4LNd32_UPD:
11959 case ARM::VST4LNq32_UPD: {
11960 // op: Vd
11961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11962 Value |= (op & UINT64_C(16)) << 18;
11963 Value |= (op & UINT64_C(15)) << 12;
11964 // op: Rn
11965 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11966 Value |= (op & UINT64_C(15)) << 16;
11967 Value |= (op & UINT64_C(48));
11968 // op: Rm
11969 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11970 op &= UINT64_C(15);
11971 Value |= op;
11972 // op: lane
11973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 8), Fixups, STI);
11974 op &= UINT64_C(1);
11975 op <<= 7;
11976 Value |= op;
11977 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11978 break;
11979 }
11980 case ARM::VST4d8_UPD:
11981 case ARM::VST4d16_UPD:
11982 case ARM::VST4d32_UPD:
11983 case ARM::VST4q8_UPD:
11984 case ARM::VST4q16_UPD:
11985 case ARM::VST4q32_UPD: {
11986 // op: Vd
11987 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11988 Value |= (op & UINT64_C(16)) << 18;
11989 Value |= (op & UINT64_C(15)) << 12;
11990 // op: Rn
11991 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
11992 Value |= (op & UINT64_C(15)) << 16;
11993 Value |= (op & UINT64_C(48));
11994 // op: Rm
11995 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
11996 op &= UINT64_C(15);
11997 Value |= op;
11998 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
11999 break;
12000 }
12001 case ARM::VST1d8Qwb_register:
12002 case ARM::VST1d8Twb_register:
12003 case ARM::VST1d16Qwb_register:
12004 case ARM::VST1d16Twb_register:
12005 case ARM::VST1d32Qwb_register:
12006 case ARM::VST1d32Twb_register:
12007 case ARM::VST1d64Qwb_register:
12008 case ARM::VST1d64Twb_register:
12009 case ARM::VST1q8wb_register:
12010 case ARM::VST1q16wb_register:
12011 case ARM::VST1q32wb_register:
12012 case ARM::VST1q64wb_register:
12013 case ARM::VST2b8wb_register:
12014 case ARM::VST2b16wb_register:
12015 case ARM::VST2b32wb_register:
12016 case ARM::VST2d8wb_register:
12017 case ARM::VST2d16wb_register:
12018 case ARM::VST2d32wb_register:
12019 case ARM::VST2q8wb_register:
12020 case ARM::VST2q16wb_register:
12021 case ARM::VST2q32wb_register: {
12022 // op: Vd
12023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12024 Value |= (op & UINT64_C(16)) << 18;
12025 Value |= (op & UINT64_C(15)) << 12;
12026 // op: Rn
12027 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
12028 Value |= (op & UINT64_C(15)) << 16;
12029 Value |= (op & UINT64_C(48));
12030 // op: Rm
12031 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12032 op &= UINT64_C(15);
12033 Value |= op;
12034 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
12035 break;
12036 }
12037 case ARM::VST1LNd8_UPD: {
12038 // op: Vd
12039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12040 Value |= (op & UINT64_C(16)) << 18;
12041 Value |= (op & UINT64_C(15)) << 12;
12042 // op: Rn
12043 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
12044 op &= UINT64_C(15);
12045 op <<= 16;
12046 Value |= op;
12047 // op: Rm
12048 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
12049 op &= UINT64_C(15);
12050 Value |= op;
12051 // op: lane
12052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
12053 op &= UINT64_C(7);
12054 op <<= 5;
12055 Value |= op;
12056 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
12057 break;
12058 }
12059 case ARM::VST3LNd32_UPD:
12060 case ARM::VST3LNq32_UPD: {
12061 // op: Vd
12062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12063 Value |= (op & UINT64_C(16)) << 18;
12064 Value |= (op & UINT64_C(15)) << 12;
12065 // op: Rn
12066 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
12067 op &= UINT64_C(15);
12068 op <<= 16;
12069 Value |= op;
12070 // op: Rm
12071 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
12072 op &= UINT64_C(15);
12073 Value |= op;
12074 // op: lane
12075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 7), Fixups, STI);
12076 op &= UINT64_C(1);
12077 op <<= 7;
12078 Value |= op;
12079 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
12080 break;
12081 }
12082 case ARM::VST3LNd16_UPD:
12083 case ARM::VST3LNq16_UPD: {
12084 // op: Vd
12085 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12086 Value |= (op & UINT64_C(16)) << 18;
12087 Value |= (op & UINT64_C(15)) << 12;
12088 // op: Rn
12089 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
12090 op &= UINT64_C(15);
12091 op <<= 16;
12092 Value |= op;
12093 // op: Rm
12094 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
12095 op &= UINT64_C(15);
12096 Value |= op;
12097 // op: lane
12098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 7), Fixups, STI);
12099 op &= UINT64_C(3);
12100 op <<= 6;
12101 Value |= op;
12102 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
12103 break;
12104 }
12105 case ARM::VST3LNd8_UPD: {
12106 // op: Vd
12107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12108 Value |= (op & UINT64_C(16)) << 18;
12109 Value |= (op & UINT64_C(15)) << 12;
12110 // op: Rn
12111 op = getAddrMode6AddressOpValue(MI, Op: 1, Fixups, STI);
12112 op &= UINT64_C(15);
12113 op <<= 16;
12114 Value |= op;
12115 // op: Rm
12116 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
12117 op &= UINT64_C(15);
12118 Value |= op;
12119 // op: lane
12120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 7), Fixups, STI);
12121 op &= UINT64_C(7);
12122 op <<= 5;
12123 Value |= op;
12124 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
12125 break;
12126 }
12127 case ARM::VST1LNd32_UPD: {
12128 // op: Vd
12129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12130 Value |= (op & UINT64_C(16)) << 18;
12131 Value |= (op & UINT64_C(15)) << 12;
12132 // op: Rn
12133 op = getAddrMode6OneLane32AddressOpValue(MI, Op: 1, Fixups, STI);
12134 Value |= (op & UINT64_C(15)) << 16;
12135 Value |= (op & UINT64_C(48));
12136 // op: Rm
12137 op = getAddrMode6OffsetOpValue(MI, Op: 3, Fixups, STI);
12138 op &= UINT64_C(15);
12139 Value |= op;
12140 // op: lane
12141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
12142 op &= UINT64_C(1);
12143 op <<= 7;
12144 Value |= op;
12145 Value = NEONThumb2LoadStorePostEncoder(MI, EncodedValue: Value, STI);
12146 break;
12147 }
12148 case ARM::LDC2L_OFFSET:
12149 case ARM::LDC2L_PRE:
12150 case ARM::LDC2_OFFSET:
12151 case ARM::LDC2_PRE:
12152 case ARM::STC2L_OFFSET:
12153 case ARM::STC2L_PRE:
12154 case ARM::STC2_OFFSET:
12155 case ARM::STC2_PRE:
12156 case ARM::t2LDC2L_OFFSET:
12157 case ARM::t2LDC2L_PRE:
12158 case ARM::t2LDC2_OFFSET:
12159 case ARM::t2LDC2_PRE:
12160 case ARM::t2LDCL_OFFSET:
12161 case ARM::t2LDCL_PRE:
12162 case ARM::t2LDC_OFFSET:
12163 case ARM::t2LDC_PRE:
12164 case ARM::t2STC2L_OFFSET:
12165 case ARM::t2STC2L_PRE:
12166 case ARM::t2STC2_OFFSET:
12167 case ARM::t2STC2_PRE:
12168 case ARM::t2STCL_OFFSET:
12169 case ARM::t2STCL_PRE:
12170 case ARM::t2STC_OFFSET:
12171 case ARM::t2STC_PRE: {
12172 // op: addr
12173 op = getAddrMode5OpValue(MI, OpIdx: 2, Fixups, STI);
12174 Value |= (op & UINT64_C(256)) << 15;
12175 Value |= (op & UINT64_C(7680)) << 7;
12176 Value |= (op & UINT64_C(255));
12177 // op: cop
12178 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12179 op &= UINT64_C(15);
12180 op <<= 8;
12181 Value |= op;
12182 // op: CRd
12183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12184 op &= UINT64_C(15);
12185 op <<= 12;
12186 Value |= op;
12187 break;
12188 }
12189 case ARM::t2PLDWi12:
12190 case ARM::t2PLDi12:
12191 case ARM::t2PLIi12: {
12192 // op: addr
12193 op = getAddrModeImm12OpValue(MI, OpIdx: 0, Fixups, STI);
12194 Value |= (op & UINT64_C(122880)) << 3;
12195 Value |= (op & UINT64_C(4095));
12196 break;
12197 }
12198 case ARM::PLDWi12:
12199 case ARM::PLDi12:
12200 case ARM::PLIi12: {
12201 // op: addr
12202 op = getAddrModeImm12OpValue(MI, OpIdx: 0, Fixups, STI);
12203 Value |= (op & UINT64_C(4096)) << 11;
12204 Value |= (op & UINT64_C(122880)) << 3;
12205 Value |= (op & UINT64_C(4095));
12206 break;
12207 }
12208 case ARM::t2PLDpci:
12209 case ARM::t2PLIpci: {
12210 // op: addr
12211 op = getAddrModeImm12OpValue(MI, OpIdx: 0, Fixups, STI);
12212 Value |= (op & UINT64_C(4096)) << 11;
12213 Value |= (op & UINT64_C(4095));
12214 break;
12215 }
12216 case ARM::t2LDAEXB:
12217 case ARM::t2LDAEXH:
12218 case ARM::t2LDREXB:
12219 case ARM::t2LDREXH: {
12220 // op: addr
12221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12222 op &= UINT64_C(15);
12223 op <<= 16;
12224 Value |= op;
12225 // op: Rt
12226 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12227 op &= UINT64_C(15);
12228 op <<= 12;
12229 Value |= op;
12230 break;
12231 }
12232 case ARM::t2LDAEXD:
12233 case ARM::t2LDREXD: {
12234 // op: addr
12235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12236 op &= UINT64_C(15);
12237 op <<= 16;
12238 Value |= op;
12239 // op: Rt
12240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12241 op &= UINT64_C(15);
12242 op <<= 12;
12243 Value |= op;
12244 // op: Rt2
12245 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12246 op &= UINT64_C(15);
12247 op <<= 8;
12248 Value |= op;
12249 break;
12250 }
12251 case ARM::t2PLDWi8:
12252 case ARM::t2PLDi8:
12253 case ARM::t2PLIi8: {
12254 // op: addr
12255 op = getT2AddrModeImmOpValue<8,0>(MI, OpNum: 0, Fixups, STI);
12256 Value |= (op & UINT64_C(7680)) << 7;
12257 Value |= (op & UINT64_C(255));
12258 break;
12259 }
12260 case ARM::t2PLDWs:
12261 case ARM::t2PLDs:
12262 case ARM::t2PLIs: {
12263 // op: addr
12264 op = getT2AddrModeSORegOpValue(MI, OpNum: 0, Fixups, STI);
12265 Value |= (op & UINT64_C(960)) << 10;
12266 Value |= (op & UINT64_C(3)) << 4;
12267 Value |= (op & UINT64_C(60)) >> 2;
12268 break;
12269 }
12270 case ARM::t2BFLr:
12271 case ARM::t2BFr: {
12272 // op: b_label
12273 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI);
12274 op &= UINT64_C(15);
12275 op <<= 23;
12276 Value |= op;
12277 // op: Rn
12278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12279 op &= UINT64_C(15);
12280 op <<= 16;
12281 Value |= op;
12282 break;
12283 }
12284 case ARM::t2BFi: {
12285 // op: b_label
12286 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI);
12287 op &= UINT64_C(15);
12288 op <<= 23;
12289 Value |= op;
12290 // op: label
12291 op = getBFTargetOpValue<false, ARM::fixup_bf_target>(MI, OpIdx: 1, Fixups, STI);
12292 Value |= (op & UINT64_C(63488)) << 5;
12293 Value |= (op & UINT64_C(1)) << 11;
12294 Value |= (op & UINT64_C(2046));
12295 break;
12296 }
12297 case ARM::t2BFLi: {
12298 // op: b_label
12299 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI);
12300 op &= UINT64_C(15);
12301 op <<= 23;
12302 Value |= op;
12303 // op: label
12304 op = getBFTargetOpValue<false, ARM::fixup_bfl_target>(MI, OpIdx: 1, Fixups, STI);
12305 Value |= (op & UINT64_C(260096)) << 5;
12306 Value |= (op & UINT64_C(1)) << 11;
12307 Value |= (op & UINT64_C(2046));
12308 break;
12309 }
12310 case ARM::t2MSRbanked: {
12311 // op: banked
12312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12313 Value |= (op & UINT64_C(32)) << 15;
12314 Value |= (op & UINT64_C(15)) << 8;
12315 Value |= (op & UINT64_C(16));
12316 // op: Rn
12317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12318 op &= UINT64_C(15);
12319 op <<= 16;
12320 Value |= op;
12321 break;
12322 }
12323 case ARM::t2MRSbanked: {
12324 // op: banked
12325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12326 Value |= (op & UINT64_C(32)) << 15;
12327 Value |= (op & UINT64_C(15)) << 16;
12328 Value |= (op & UINT64_C(16));
12329 // op: Rd
12330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12331 op &= UINT64_C(15);
12332 op <<= 8;
12333 Value |= op;
12334 break;
12335 }
12336 case ARM::t2BFic: {
12337 // op: bcond
12338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12339 op &= UINT64_C(15);
12340 op <<= 18;
12341 Value |= op;
12342 // op: label
12343 op = getBFTargetOpValue<false, ARM::fixup_bfc_target>(MI, OpIdx: 1, Fixups, STI);
12344 Value |= (op & UINT64_C(2048)) << 5;
12345 Value |= (op & UINT64_C(1)) << 11;
12346 Value |= (op & UINT64_C(2046));
12347 // op: ba_label
12348 op = getBFAfterTargetOpValue(MI, OpIdx: 2, Fixups, STI);
12349 op &= UINT64_C(1);
12350 op <<= 17;
12351 Value |= op;
12352 // op: b_label
12353 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, OpIdx: 0, Fixups, STI);
12354 op &= UINT64_C(15);
12355 op <<= 23;
12356 Value |= op;
12357 break;
12358 }
12359 case ARM::t2IT: {
12360 // op: cc
12361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12362 op &= UINT64_C(15);
12363 op <<= 4;
12364 Value |= op;
12365 // op: mask
12366 op = getITMaskOpValue(MI, OpIdx: 1, Fixups, STI);
12367 op &= UINT64_C(15);
12368 Value |= op;
12369 break;
12370 }
12371 case ARM::CDE_VCX1_fpsp: {
12372 // op: coproc
12373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12374 op &= UINT64_C(7);
12375 op <<= 8;
12376 Value |= op;
12377 // op: imm
12378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12379 Value |= (op & UINT64_C(1920)) << 9;
12380 Value |= (op & UINT64_C(64)) << 1;
12381 Value |= (op & UINT64_C(63));
12382 // op: Vd
12383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12384 Value |= (op & UINT64_C(1)) << 22;
12385 Value |= (op & UINT64_C(30)) << 11;
12386 break;
12387 }
12388 case ARM::CDE_VCX1_fpdp: {
12389 // op: coproc
12390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12391 op &= UINT64_C(7);
12392 op <<= 8;
12393 Value |= op;
12394 // op: imm
12395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12396 Value |= (op & UINT64_C(1920)) << 9;
12397 Value |= (op & UINT64_C(64)) << 1;
12398 Value |= (op & UINT64_C(63));
12399 // op: Vd
12400 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12401 Value |= (op & UINT64_C(16)) << 18;
12402 Value |= (op & UINT64_C(15)) << 12;
12403 break;
12404 }
12405 case ARM::CDE_VCX1_vec: {
12406 // op: coproc
12407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12408 op &= UINT64_C(7);
12409 op <<= 8;
12410 Value |= op;
12411 // op: imm
12412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12413 Value |= (op & UINT64_C(2048)) << 13;
12414 Value |= (op & UINT64_C(1920)) << 9;
12415 Value |= (op & UINT64_C(64)) << 1;
12416 Value |= (op & UINT64_C(63));
12417 // op: Qd
12418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12419 op &= UINT64_C(7);
12420 op <<= 13;
12421 Value |= op;
12422 break;
12423 }
12424 case ARM::CDE_CX1:
12425 case ARM::CDE_CX1D: {
12426 // op: coproc
12427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12428 op &= UINT64_C(7);
12429 op <<= 8;
12430 Value |= op;
12431 // op: imm
12432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12433 Value |= (op & UINT64_C(8064)) << 9;
12434 Value |= (op & UINT64_C(64)) << 1;
12435 Value |= (op & UINT64_C(63));
12436 // op: Rd
12437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12438 op &= UINT64_C(15);
12439 op <<= 12;
12440 Value |= op;
12441 break;
12442 }
12443 case ARM::CDE_VCX1A_fpsp: {
12444 // op: coproc
12445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12446 op &= UINT64_C(7);
12447 op <<= 8;
12448 Value |= op;
12449 // op: imm
12450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12451 Value |= (op & UINT64_C(1920)) << 9;
12452 Value |= (op & UINT64_C(64)) << 1;
12453 Value |= (op & UINT64_C(63));
12454 // op: Vd
12455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12456 Value |= (op & UINT64_C(1)) << 22;
12457 Value |= (op & UINT64_C(30)) << 11;
12458 break;
12459 }
12460 case ARM::CDE_VCX1A_fpdp: {
12461 // op: coproc
12462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12463 op &= UINT64_C(7);
12464 op <<= 8;
12465 Value |= op;
12466 // op: imm
12467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12468 Value |= (op & UINT64_C(1920)) << 9;
12469 Value |= (op & UINT64_C(64)) << 1;
12470 Value |= (op & UINT64_C(63));
12471 // op: Vd
12472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12473 Value |= (op & UINT64_C(16)) << 18;
12474 Value |= (op & UINT64_C(15)) << 12;
12475 break;
12476 }
12477 case ARM::CDE_VCX1A_vec: {
12478 // op: coproc
12479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12480 op &= UINT64_C(7);
12481 op <<= 8;
12482 Value |= op;
12483 // op: imm
12484 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12485 Value |= (op & UINT64_C(2048)) << 13;
12486 Value |= (op & UINT64_C(1920)) << 9;
12487 Value |= (op & UINT64_C(64)) << 1;
12488 Value |= (op & UINT64_C(63));
12489 // op: Qd
12490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12491 op &= UINT64_C(7);
12492 op <<= 13;
12493 Value |= op;
12494 break;
12495 }
12496 case ARM::CDE_CX2:
12497 case ARM::CDE_CX2D: {
12498 // op: coproc
12499 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12500 op &= UINT64_C(7);
12501 op <<= 8;
12502 Value |= op;
12503 // op: imm
12504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12505 Value |= (op & UINT64_C(384)) << 13;
12506 Value |= (op & UINT64_C(64)) << 1;
12507 Value |= (op & UINT64_C(63));
12508 // op: Rd
12509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12510 op &= UINT64_C(15);
12511 op <<= 12;
12512 Value |= op;
12513 // op: Rn
12514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12515 op &= UINT64_C(15);
12516 op <<= 16;
12517 Value |= op;
12518 break;
12519 }
12520 case ARM::CDE_VCX2_fpsp: {
12521 // op: coproc
12522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12523 op &= UINT64_C(7);
12524 op <<= 8;
12525 Value |= op;
12526 // op: imm
12527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12528 Value |= (op & UINT64_C(60)) << 14;
12529 Value |= (op & UINT64_C(2)) << 6;
12530 Value |= (op & UINT64_C(1)) << 4;
12531 // op: Vd
12532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12533 Value |= (op & UINT64_C(1)) << 22;
12534 Value |= (op & UINT64_C(30)) << 11;
12535 // op: Vm
12536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12537 Value |= (op & UINT64_C(1)) << 5;
12538 Value |= (op & UINT64_C(30)) >> 1;
12539 break;
12540 }
12541 case ARM::CDE_VCX2_fpdp: {
12542 // op: coproc
12543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12544 op &= UINT64_C(7);
12545 op <<= 8;
12546 Value |= op;
12547 // op: imm
12548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12549 Value |= (op & UINT64_C(60)) << 14;
12550 Value |= (op & UINT64_C(2)) << 6;
12551 Value |= (op & UINT64_C(1)) << 4;
12552 // op: Vd
12553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12554 Value |= (op & UINT64_C(16)) << 18;
12555 Value |= (op & UINT64_C(15)) << 12;
12556 // op: Vm
12557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12558 Value |= (op & UINT64_C(16)) << 1;
12559 Value |= (op & UINT64_C(15));
12560 break;
12561 }
12562 case ARM::CDE_VCX2_vec: {
12563 // op: coproc
12564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12565 op &= UINT64_C(7);
12566 op <<= 8;
12567 Value |= op;
12568 // op: imm
12569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12570 Value |= (op & UINT64_C(64)) << 18;
12571 Value |= (op & UINT64_C(60)) << 14;
12572 Value |= (op & UINT64_C(2)) << 6;
12573 Value |= (op & UINT64_C(1)) << 4;
12574 // op: Qd
12575 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12576 op &= UINT64_C(7);
12577 op <<= 13;
12578 Value |= op;
12579 // op: Qm
12580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12581 op &= UINT64_C(7);
12582 op <<= 1;
12583 Value |= op;
12584 break;
12585 }
12586 case ARM::CDE_CX1A:
12587 case ARM::CDE_CX1DA: {
12588 // op: coproc
12589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12590 op &= UINT64_C(7);
12591 op <<= 8;
12592 Value |= op;
12593 // op: imm
12594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12595 Value |= (op & UINT64_C(8064)) << 9;
12596 Value |= (op & UINT64_C(64)) << 1;
12597 Value |= (op & UINT64_C(63));
12598 // op: Rd
12599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12600 op &= UINT64_C(15);
12601 op <<= 12;
12602 Value |= op;
12603 break;
12604 }
12605 case ARM::CDE_CX2A:
12606 case ARM::CDE_CX2DA: {
12607 // op: coproc
12608 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12609 op &= UINT64_C(7);
12610 op <<= 8;
12611 Value |= op;
12612 // op: imm
12613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12614 Value |= (op & UINT64_C(384)) << 13;
12615 Value |= (op & UINT64_C(64)) << 1;
12616 Value |= (op & UINT64_C(63));
12617 // op: Rd
12618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12619 op &= UINT64_C(15);
12620 op <<= 12;
12621 Value |= op;
12622 // op: Rn
12623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12624 op &= UINT64_C(15);
12625 op <<= 16;
12626 Value |= op;
12627 break;
12628 }
12629 case ARM::CDE_CX3:
12630 case ARM::CDE_CX3D: {
12631 // op: coproc
12632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12633 op &= UINT64_C(7);
12634 op <<= 8;
12635 Value |= op;
12636 // op: imm
12637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12638 Value |= (op & UINT64_C(56)) << 17;
12639 Value |= (op & UINT64_C(4)) << 5;
12640 Value |= (op & UINT64_C(3)) << 4;
12641 // op: Rd
12642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12643 op &= UINT64_C(15);
12644 Value |= op;
12645 // op: Rn
12646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12647 op &= UINT64_C(15);
12648 op <<= 16;
12649 Value |= op;
12650 // op: Rm
12651 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12652 op &= UINT64_C(15);
12653 op <<= 12;
12654 Value |= op;
12655 break;
12656 }
12657 case ARM::CDE_VCX3_fpsp: {
12658 // op: coproc
12659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12660 op &= UINT64_C(7);
12661 op <<= 8;
12662 Value |= op;
12663 // op: imm
12664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12665 Value |= (op & UINT64_C(6)) << 19;
12666 Value |= (op & UINT64_C(1)) << 4;
12667 // op: Vd
12668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12669 Value |= (op & UINT64_C(1)) << 22;
12670 Value |= (op & UINT64_C(30)) << 11;
12671 // op: Vm
12672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12673 Value |= (op & UINT64_C(1)) << 5;
12674 Value |= (op & UINT64_C(30)) >> 1;
12675 // op: Vn
12676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12677 Value |= (op & UINT64_C(30)) << 15;
12678 Value |= (op & UINT64_C(1)) << 7;
12679 break;
12680 }
12681 case ARM::CDE_VCX3_fpdp: {
12682 // op: coproc
12683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12684 op &= UINT64_C(7);
12685 op <<= 8;
12686 Value |= op;
12687 // op: imm
12688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12689 Value |= (op & UINT64_C(6)) << 19;
12690 Value |= (op & UINT64_C(1)) << 4;
12691 // op: Vd
12692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12693 Value |= (op & UINT64_C(16)) << 18;
12694 Value |= (op & UINT64_C(15)) << 12;
12695 // op: Vm
12696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12697 Value |= (op & UINT64_C(16)) << 1;
12698 Value |= (op & UINT64_C(15));
12699 // op: Vn
12700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12701 Value |= (op & UINT64_C(15)) << 16;
12702 Value |= (op & UINT64_C(16)) << 3;
12703 break;
12704 }
12705 case ARM::CDE_VCX2A_fpsp: {
12706 // op: coproc
12707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12708 op &= UINT64_C(7);
12709 op <<= 8;
12710 Value |= op;
12711 // op: imm
12712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12713 Value |= (op & UINT64_C(60)) << 14;
12714 Value |= (op & UINT64_C(2)) << 6;
12715 Value |= (op & UINT64_C(1)) << 4;
12716 // op: Vd
12717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12718 Value |= (op & UINT64_C(1)) << 22;
12719 Value |= (op & UINT64_C(30)) << 11;
12720 // op: Vm
12721 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12722 Value |= (op & UINT64_C(1)) << 5;
12723 Value |= (op & UINT64_C(30)) >> 1;
12724 break;
12725 }
12726 case ARM::CDE_VCX2A_fpdp: {
12727 // op: coproc
12728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12729 op &= UINT64_C(7);
12730 op <<= 8;
12731 Value |= op;
12732 // op: imm
12733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12734 Value |= (op & UINT64_C(60)) << 14;
12735 Value |= (op & UINT64_C(2)) << 6;
12736 Value |= (op & UINT64_C(1)) << 4;
12737 // op: Vd
12738 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12739 Value |= (op & UINT64_C(16)) << 18;
12740 Value |= (op & UINT64_C(15)) << 12;
12741 // op: Vm
12742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12743 Value |= (op & UINT64_C(16)) << 1;
12744 Value |= (op & UINT64_C(15));
12745 break;
12746 }
12747 case ARM::CDE_VCX2A_vec: {
12748 // op: coproc
12749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12750 op &= UINT64_C(7);
12751 op <<= 8;
12752 Value |= op;
12753 // op: imm
12754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12755 Value |= (op & UINT64_C(64)) << 18;
12756 Value |= (op & UINT64_C(60)) << 14;
12757 Value |= (op & UINT64_C(2)) << 6;
12758 Value |= (op & UINT64_C(1)) << 4;
12759 // op: Qd
12760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12761 op &= UINT64_C(7);
12762 op <<= 13;
12763 Value |= op;
12764 // op: Qm
12765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12766 op &= UINT64_C(7);
12767 op <<= 1;
12768 Value |= op;
12769 break;
12770 }
12771 case ARM::CDE_VCX3_vec: {
12772 // op: coproc
12773 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12774 op &= UINT64_C(7);
12775 op <<= 8;
12776 Value |= op;
12777 // op: imm
12778 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12779 Value |= (op & UINT64_C(8)) << 21;
12780 Value |= (op & UINT64_C(6)) << 19;
12781 Value |= (op & UINT64_C(1)) << 4;
12782 // op: Qd
12783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12784 op &= UINT64_C(7);
12785 op <<= 13;
12786 Value |= op;
12787 // op: Qm
12788 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12789 op &= UINT64_C(7);
12790 op <<= 1;
12791 Value |= op;
12792 // op: Qn
12793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12794 op &= UINT64_C(7);
12795 op <<= 17;
12796 Value |= op;
12797 break;
12798 }
12799 case ARM::CDE_CX3A:
12800 case ARM::CDE_CX3DA: {
12801 // op: coproc
12802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12803 op &= UINT64_C(7);
12804 op <<= 8;
12805 Value |= op;
12806 // op: imm
12807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
12808 Value |= (op & UINT64_C(56)) << 17;
12809 Value |= (op & UINT64_C(4)) << 5;
12810 Value |= (op & UINT64_C(3)) << 4;
12811 // op: Rd
12812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12813 op &= UINT64_C(15);
12814 Value |= op;
12815 // op: Rn
12816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12817 op &= UINT64_C(15);
12818 op <<= 16;
12819 Value |= op;
12820 // op: Rm
12821 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12822 op &= UINT64_C(15);
12823 op <<= 12;
12824 Value |= op;
12825 break;
12826 }
12827 case ARM::CDE_VCX3A_fpsp: {
12828 // op: coproc
12829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12830 op &= UINT64_C(7);
12831 op <<= 8;
12832 Value |= op;
12833 // op: imm
12834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
12835 Value |= (op & UINT64_C(6)) << 19;
12836 Value |= (op & UINT64_C(1)) << 4;
12837 // op: Vd
12838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12839 Value |= (op & UINT64_C(1)) << 22;
12840 Value |= (op & UINT64_C(30)) << 11;
12841 // op: Vm
12842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12843 Value |= (op & UINT64_C(1)) << 5;
12844 Value |= (op & UINT64_C(30)) >> 1;
12845 // op: Vn
12846 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12847 Value |= (op & UINT64_C(30)) << 15;
12848 Value |= (op & UINT64_C(1)) << 7;
12849 break;
12850 }
12851 case ARM::CDE_VCX3A_fpdp: {
12852 // op: coproc
12853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12854 op &= UINT64_C(7);
12855 op <<= 8;
12856 Value |= op;
12857 // op: imm
12858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
12859 Value |= (op & UINT64_C(6)) << 19;
12860 Value |= (op & UINT64_C(1)) << 4;
12861 // op: Vd
12862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12863 Value |= (op & UINT64_C(16)) << 18;
12864 Value |= (op & UINT64_C(15)) << 12;
12865 // op: Vm
12866 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12867 Value |= (op & UINT64_C(16)) << 1;
12868 Value |= (op & UINT64_C(15));
12869 // op: Vn
12870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12871 Value |= (op & UINT64_C(15)) << 16;
12872 Value |= (op & UINT64_C(16)) << 3;
12873 break;
12874 }
12875 case ARM::CDE_VCX3A_vec: {
12876 // op: coproc
12877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12878 op &= UINT64_C(7);
12879 op <<= 8;
12880 Value |= op;
12881 // op: imm
12882 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
12883 Value |= (op & UINT64_C(8)) << 21;
12884 Value |= (op & UINT64_C(6)) << 19;
12885 Value |= (op & UINT64_C(1)) << 4;
12886 // op: Qd
12887 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12888 op &= UINT64_C(7);
12889 op <<= 13;
12890 Value |= op;
12891 // op: Qm
12892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12893 op &= UINT64_C(7);
12894 op <<= 1;
12895 Value |= op;
12896 // op: Qn
12897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12898 op &= UINT64_C(7);
12899 op <<= 17;
12900 Value |= op;
12901 break;
12902 }
12903 case ARM::BX: {
12904 // op: dst
12905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12906 op &= UINT64_C(15);
12907 Value |= op;
12908 break;
12909 }
12910 case ARM::tPICADD: {
12911 // op: dst
12912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12913 op &= UINT64_C(7);
12914 Value |= op;
12915 break;
12916 }
12917 case ARM::tADDrSPi: {
12918 // op: dst
12919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12920 op &= UINT64_C(7);
12921 op <<= 8;
12922 Value |= op;
12923 // op: imm
12924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12925 op &= UINT64_C(255);
12926 Value |= op;
12927 break;
12928 }
12929 case ARM::tSETEND: {
12930 // op: end
12931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12932 op &= UINT64_C(1);
12933 op <<= 3;
12934 Value |= op;
12935 break;
12936 }
12937 case ARM::SETEND: {
12938 // op: end
12939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12940 op &= UINT64_C(1);
12941 op <<= 9;
12942 Value |= op;
12943 break;
12944 }
12945 case ARM::MVE_VPTv4s32r:
12946 case ARM::MVE_VPTv8s16r:
12947 case ARM::MVE_VPTv16s8r: {
12948 // op: fc
12949 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
12950 Value |= (op & UINT64_C(1)) << 7;
12951 Value |= (op & UINT64_C(2)) << 4;
12952 // op: Mk
12953 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
12954 Value |= (op & UINT64_C(8)) << 19;
12955 Value |= (op & UINT64_C(7)) << 13;
12956 // op: Qn
12957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12958 op &= UINT64_C(7);
12959 op <<= 17;
12960 Value |= op;
12961 // op: Rm
12962 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12963 op &= UINT64_C(15);
12964 Value |= op;
12965 break;
12966 }
12967 case ARM::MVE_VCMPs8r:
12968 case ARM::MVE_VCMPs16r:
12969 case ARM::MVE_VCMPs32r: {
12970 // op: fc
12971 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
12972 Value |= (op & UINT64_C(1)) << 7;
12973 Value |= (op & UINT64_C(2)) << 4;
12974 // op: Qn
12975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12976 op &= UINT64_C(7);
12977 op <<= 17;
12978 Value |= op;
12979 // op: Rm
12980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12981 op &= UINT64_C(15);
12982 Value |= op;
12983 break;
12984 }
12985 case ARM::MVE_VPTv4s32:
12986 case ARM::MVE_VPTv8s16:
12987 case ARM::MVE_VPTv16s8: {
12988 // op: fc
12989 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
12990 Value |= (op & UINT64_C(1)) << 7;
12991 Value |= (op & UINT64_C(2)) >> 1;
12992 // op: Mk
12993 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
12994 Value |= (op & UINT64_C(8)) << 19;
12995 Value |= (op & UINT64_C(7)) << 13;
12996 // op: Qn
12997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12998 op &= UINT64_C(7);
12999 op <<= 17;
13000 Value |= op;
13001 // op: Qm
13002 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13003 Value |= (op & UINT64_C(8)) << 2;
13004 Value |= (op & UINT64_C(7)) << 1;
13005 break;
13006 }
13007 case ARM::MVE_VCMPs8:
13008 case ARM::MVE_VCMPs16:
13009 case ARM::MVE_VCMPs32: {
13010 // op: fc
13011 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13012 Value |= (op & UINT64_C(1)) << 7;
13013 Value |= (op & UINT64_C(2)) >> 1;
13014 // op: Qn
13015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13016 op &= UINT64_C(7);
13017 op <<= 17;
13018 Value |= op;
13019 // op: Qm
13020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13021 Value |= (op & UINT64_C(8)) << 2;
13022 Value |= (op & UINT64_C(7)) << 1;
13023 break;
13024 }
13025 case ARM::MVE_VPTv4f32r:
13026 case ARM::MVE_VPTv8f16r: {
13027 // op: fc
13028 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13029 Value |= (op & UINT64_C(4)) << 10;
13030 Value |= (op & UINT64_C(1)) << 7;
13031 Value |= (op & UINT64_C(2)) << 4;
13032 // op: Mk
13033 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
13034 Value |= (op & UINT64_C(8)) << 19;
13035 Value |= (op & UINT64_C(7)) << 13;
13036 // op: Qn
13037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13038 op &= UINT64_C(7);
13039 op <<= 17;
13040 Value |= op;
13041 // op: Rm
13042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13043 op &= UINT64_C(15);
13044 Value |= op;
13045 break;
13046 }
13047 case ARM::MVE_VCMPf16r:
13048 case ARM::MVE_VCMPf32r: {
13049 // op: fc
13050 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13051 Value |= (op & UINT64_C(4)) << 10;
13052 Value |= (op & UINT64_C(1)) << 7;
13053 Value |= (op & UINT64_C(2)) << 4;
13054 // op: Qn
13055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13056 op &= UINT64_C(7);
13057 op <<= 17;
13058 Value |= op;
13059 // op: Rm
13060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13061 op &= UINT64_C(15);
13062 Value |= op;
13063 break;
13064 }
13065 case ARM::MVE_VPTv4f32:
13066 case ARM::MVE_VPTv8f16: {
13067 // op: fc
13068 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13069 Value |= (op & UINT64_C(4)) << 10;
13070 Value |= (op & UINT64_C(1)) << 7;
13071 Value |= (op & UINT64_C(2)) >> 1;
13072 // op: Mk
13073 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
13074 Value |= (op & UINT64_C(8)) << 19;
13075 Value |= (op & UINT64_C(7)) << 13;
13076 // op: Qn
13077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13078 op &= UINT64_C(7);
13079 op <<= 17;
13080 Value |= op;
13081 // op: Qm
13082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13083 Value |= (op & UINT64_C(8)) << 2;
13084 Value |= (op & UINT64_C(7)) << 1;
13085 break;
13086 }
13087 case ARM::MVE_VCMPf16:
13088 case ARM::MVE_VCMPf32: {
13089 // op: fc
13090 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13091 Value |= (op & UINT64_C(4)) << 10;
13092 Value |= (op & UINT64_C(1)) << 7;
13093 Value |= (op & UINT64_C(2)) >> 1;
13094 // op: Qn
13095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13096 op &= UINT64_C(7);
13097 op <<= 17;
13098 Value |= op;
13099 // op: Qm
13100 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13101 Value |= (op & UINT64_C(8)) << 2;
13102 Value |= (op & UINT64_C(7)) << 1;
13103 break;
13104 }
13105 case ARM::MVE_VPTv4i32:
13106 case ARM::MVE_VPTv4u32:
13107 case ARM::MVE_VPTv8i16:
13108 case ARM::MVE_VPTv8u16:
13109 case ARM::MVE_VPTv16i8:
13110 case ARM::MVE_VPTv16u8: {
13111 // op: fc
13112 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13113 op &= UINT64_C(1);
13114 op <<= 7;
13115 Value |= op;
13116 // op: Mk
13117 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
13118 Value |= (op & UINT64_C(8)) << 19;
13119 Value |= (op & UINT64_C(7)) << 13;
13120 // op: Qn
13121 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13122 op &= UINT64_C(7);
13123 op <<= 17;
13124 Value |= op;
13125 // op: Qm
13126 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13127 Value |= (op & UINT64_C(8)) << 2;
13128 Value |= (op & UINT64_C(7)) << 1;
13129 break;
13130 }
13131 case ARM::MVE_VPTv4i32r:
13132 case ARM::MVE_VPTv4u32r:
13133 case ARM::MVE_VPTv8i16r:
13134 case ARM::MVE_VPTv8u16r:
13135 case ARM::MVE_VPTv16i8r:
13136 case ARM::MVE_VPTv16u8r: {
13137 // op: fc
13138 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13139 op &= UINT64_C(1);
13140 op <<= 7;
13141 Value |= op;
13142 // op: Mk
13143 op = getVPTMaskOpValue(MI, OpIdx: 0, Fixups, STI);
13144 Value |= (op & UINT64_C(8)) << 19;
13145 Value |= (op & UINT64_C(7)) << 13;
13146 // op: Qn
13147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13148 op &= UINT64_C(7);
13149 op <<= 17;
13150 Value |= op;
13151 // op: Rm
13152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13153 op &= UINT64_C(15);
13154 Value |= op;
13155 break;
13156 }
13157 case ARM::MVE_VCMPi8:
13158 case ARM::MVE_VCMPi16:
13159 case ARM::MVE_VCMPi32:
13160 case ARM::MVE_VCMPu8:
13161 case ARM::MVE_VCMPu16:
13162 case ARM::MVE_VCMPu32: {
13163 // op: fc
13164 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13165 op &= UINT64_C(1);
13166 op <<= 7;
13167 Value |= op;
13168 // op: Qn
13169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13170 op &= UINT64_C(7);
13171 op <<= 17;
13172 Value |= op;
13173 // op: Qm
13174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13175 Value |= (op & UINT64_C(8)) << 2;
13176 Value |= (op & UINT64_C(7)) << 1;
13177 break;
13178 }
13179 case ARM::MVE_VCMPi8r:
13180 case ARM::MVE_VCMPi16r:
13181 case ARM::MVE_VCMPi32r:
13182 case ARM::MVE_VCMPu8r:
13183 case ARM::MVE_VCMPu16r:
13184 case ARM::MVE_VCMPu32r: {
13185 // op: fc
13186 op = getRestrictedCondCodeOpValue(MI, OpIdx: 3, Fixups, STI);
13187 op &= UINT64_C(1);
13188 op <<= 7;
13189 Value |= op;
13190 // op: Qn
13191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13192 op &= UINT64_C(7);
13193 op <<= 17;
13194 Value |= op;
13195 // op: Rm
13196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13197 op &= UINT64_C(15);
13198 Value |= op;
13199 break;
13200 }
13201 case ARM::BL: {
13202 // op: func
13203 op = getARMBLTargetOpValue(MI, OpIdx: 0, Fixups, STI);
13204 op &= UINT64_C(16777215);
13205 Value |= op;
13206 break;
13207 }
13208 case ARM::BLX: {
13209 // op: func
13210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13211 op &= UINT64_C(15);
13212 Value |= op;
13213 break;
13214 }
13215 case ARM::t2BXJ: {
13216 // op: func
13217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13218 op &= UINT64_C(15);
13219 op <<= 16;
13220 Value |= op;
13221 break;
13222 }
13223 case ARM::tBLXNSr:
13224 case ARM::tBLXr: {
13225 // op: func
13226 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13227 op &= UINT64_C(15);
13228 op <<= 3;
13229 Value |= op;
13230 break;
13231 }
13232 case ARM::tBL: {
13233 // op: func
13234 op = getThumbBLTargetOpValue(MI, OpIdx: 2, Fixups, STI);
13235 Value |= (op & UINT64_C(8388608)) << 3;
13236 Value |= (op & UINT64_C(2095104)) << 5;
13237 Value |= (op & UINT64_C(4194304)) >> 9;
13238 Value |= (op & UINT64_C(2097152)) >> 10;
13239 Value |= (op & UINT64_C(2047));
13240 break;
13241 }
13242 case ARM::tBLXi: {
13243 // op: func
13244 op = getThumbBLXTargetOpValue(MI, OpIdx: 2, Fixups, STI);
13245 Value |= (op & UINT64_C(8388608)) << 3;
13246 Value |= (op & UINT64_C(2095104)) << 5;
13247 Value |= (op & UINT64_C(4194304)) >> 9;
13248 Value |= (op & UINT64_C(2097152)) >> 10;
13249 Value |= (op & UINT64_C(2046));
13250 break;
13251 }
13252 case ARM::HVC: {
13253 // op: imm
13254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13255 Value |= (op & UINT64_C(65520)) << 4;
13256 Value |= (op & UINT64_C(15));
13257 break;
13258 }
13259 case ARM::t2SETPAN: {
13260 // op: imm
13261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13262 op &= UINT64_C(1);
13263 op <<= 3;
13264 Value |= op;
13265 break;
13266 }
13267 case ARM::SETPAN: {
13268 // op: imm
13269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13270 op &= UINT64_C(1);
13271 op <<= 9;
13272 Value |= op;
13273 break;
13274 }
13275 case ARM::tHINT: {
13276 // op: imm
13277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13278 op &= UINT64_C(15);
13279 op <<= 4;
13280 Value |= op;
13281 break;
13282 }
13283 case ARM::t2HINT:
13284 case ARM::t2SUBS_PC_LR:
13285 case ARM::tSVC: {
13286 // op: imm
13287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13288 op &= UINT64_C(255);
13289 Value |= op;
13290 break;
13291 }
13292 case ARM::MVE_VMOVimmf32:
13293 case ARM::MVE_VMOVimmi8:
13294 case ARM::MVE_VMOVimmi64: {
13295 // op: imm
13296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13297 Value |= (op & UINT64_C(128)) << 21;
13298 Value |= (op & UINT64_C(112)) << 12;
13299 Value |= (op & UINT64_C(15));
13300 // op: Qd
13301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13302 Value |= (op & UINT64_C(8)) << 19;
13303 Value |= (op & UINT64_C(7)) << 13;
13304 break;
13305 }
13306 case ARM::MVE_VMOVimmi32:
13307 case ARM::MVE_VMVNimmi32: {
13308 // op: imm
13309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13310 Value |= (op & UINT64_C(128)) << 21;
13311 Value |= (op & UINT64_C(112)) << 12;
13312 Value |= (op & UINT64_C(3840));
13313 Value |= (op & UINT64_C(15));
13314 // op: Qd
13315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13316 Value |= (op & UINT64_C(8)) << 19;
13317 Value |= (op & UINT64_C(7)) << 13;
13318 break;
13319 }
13320 case ARM::MVE_VMOVimmi16:
13321 case ARM::MVE_VMVNimmi16: {
13322 // op: imm
13323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13324 Value |= (op & UINT64_C(128)) << 21;
13325 Value |= (op & UINT64_C(112)) << 12;
13326 Value |= (op & UINT64_C(512));
13327 Value |= (op & UINT64_C(15));
13328 // op: Qd
13329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13330 Value |= (op & UINT64_C(8)) << 19;
13331 Value |= (op & UINT64_C(7)) << 13;
13332 break;
13333 }
13334 case ARM::MVE_VBICimmi32:
13335 case ARM::MVE_VORRimmi32: {
13336 // op: imm
13337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13338 Value |= (op & UINT64_C(128)) << 21;
13339 Value |= (op & UINT64_C(112)) << 12;
13340 Value |= (op & UINT64_C(1536));
13341 Value |= (op & UINT64_C(15));
13342 // op: Qd
13343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13344 Value |= (op & UINT64_C(8)) << 19;
13345 Value |= (op & UINT64_C(7)) << 13;
13346 break;
13347 }
13348 case ARM::MVE_VBICimmi16:
13349 case ARM::MVE_VORRimmi16: {
13350 // op: imm
13351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13352 Value |= (op & UINT64_C(128)) << 21;
13353 Value |= (op & UINT64_C(112)) << 12;
13354 Value |= (op & UINT64_C(512));
13355 Value |= (op & UINT64_C(15));
13356 // op: Qd
13357 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13358 Value |= (op & UINT64_C(8)) << 19;
13359 Value |= (op & UINT64_C(7)) << 13;
13360 break;
13361 }
13362 case ARM::t2ADDspImm12:
13363 case ARM::t2SUBspImm12: {
13364 // op: imm
13365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13366 Value |= (op & UINT64_C(2048)) << 15;
13367 Value |= (op & UINT64_C(1792)) << 4;
13368 Value |= (op & UINT64_C(255));
13369 break;
13370 }
13371 case ARM::tADDspi:
13372 case ARM::tSUBspi: {
13373 // op: imm
13374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13375 op &= UINT64_C(127);
13376 Value |= op;
13377 break;
13378 }
13379 case ARM::MVE_VSHLC: {
13380 // op: imm
13381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13382 op &= UINT64_C(31);
13383 op <<= 16;
13384 Value |= op;
13385 // op: Qd
13386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13387 Value |= (op & UINT64_C(8)) << 19;
13388 Value |= (op & UINT64_C(7)) << 13;
13389 // op: RdmDest
13390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13391 op &= UINT64_C(15);
13392 Value |= op;
13393 break;
13394 }
13395 case ARM::t2HVC:
13396 case ARM::t2UDF: {
13397 // op: imm16
13398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13399 Value |= (op & UINT64_C(61440)) << 4;
13400 Value |= (op & UINT64_C(4095));
13401 break;
13402 }
13403 case ARM::UDF: {
13404 // op: imm16
13405 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13406 Value |= (op & UINT64_C(65520)) << 4;
13407 Value |= (op & UINT64_C(15));
13408 break;
13409 }
13410 case ARM::tUDF: {
13411 // op: imm8
13412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13413 op &= UINT64_C(255);
13414 Value |= op;
13415 break;
13416 }
13417 case ARM::tCPS: {
13418 // op: imod
13419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13420 op &= UINT64_C(1);
13421 op <<= 4;
13422 Value |= op;
13423 // op: iflags
13424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13425 op &= UINT64_C(7);
13426 Value |= op;
13427 break;
13428 }
13429 case ARM::CPS2p: {
13430 // op: imod
13431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13432 op &= UINT64_C(3);
13433 op <<= 18;
13434 Value |= op;
13435 // op: iflags
13436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13437 op &= UINT64_C(7);
13438 op <<= 6;
13439 Value |= op;
13440 break;
13441 }
13442 case ARM::CPS3p: {
13443 // op: imod
13444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13445 op &= UINT64_C(3);
13446 op <<= 18;
13447 Value |= op;
13448 // op: iflags
13449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13450 op &= UINT64_C(7);
13451 op <<= 6;
13452 Value |= op;
13453 // op: mode
13454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13455 op &= UINT64_C(31);
13456 Value |= op;
13457 break;
13458 }
13459 case ARM::t2CPS2p: {
13460 // op: imod
13461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13462 op &= UINT64_C(3);
13463 op <<= 9;
13464 Value |= op;
13465 // op: iflags
13466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13467 op &= UINT64_C(7);
13468 op <<= 5;
13469 Value |= op;
13470 break;
13471 }
13472 case ARM::t2CPS3p: {
13473 // op: imod
13474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13475 op &= UINT64_C(3);
13476 op <<= 9;
13477 Value |= op;
13478 // op: iflags
13479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13480 op &= UINT64_C(7);
13481 op <<= 5;
13482 Value |= op;
13483 // op: mode
13484 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13485 op &= UINT64_C(31);
13486 Value |= op;
13487 break;
13488 }
13489 case ARM::t2LE: {
13490 // op: label
13491 op = getBFTargetOpValue<true, ARM::fixup_le>(MI, OpIdx: 0, Fixups, STI);
13492 Value |= (op & UINT64_C(1)) << 11;
13493 Value |= (op & UINT64_C(2046));
13494 break;
13495 }
13496 case ARM::MVE_LETP:
13497 case ARM::t2LEUpdate: {
13498 // op: label
13499 op = getBFTargetOpValue<true, ARM::fixup_le>(MI, OpIdx: 2, Fixups, STI);
13500 Value |= (op & UINT64_C(1)) << 11;
13501 Value |= (op & UINT64_C(2046));
13502 break;
13503 }
13504 case ARM::t2MSR_AR: {
13505 // op: mask
13506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13507 Value |= (op & UINT64_C(16)) << 16;
13508 Value |= (op & UINT64_C(15)) << 8;
13509 // op: Rn
13510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13511 op &= UINT64_C(15);
13512 op <<= 16;
13513 Value |= op;
13514 break;
13515 }
13516 case ARM::CPS1p:
13517 case ARM::SRSDA:
13518 case ARM::SRSDA_UPD:
13519 case ARM::SRSDB:
13520 case ARM::SRSDB_UPD:
13521 case ARM::SRSIA:
13522 case ARM::SRSIA_UPD:
13523 case ARM::SRSIB:
13524 case ARM::SRSIB_UPD:
13525 case ARM::t2CPS1p:
13526 case ARM::t2SRSDB:
13527 case ARM::t2SRSDB_UPD:
13528 case ARM::t2SRSIA:
13529 case ARM::t2SRSIA_UPD: {
13530 // op: mode
13531 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13532 op &= UINT64_C(31);
13533 Value |= op;
13534 break;
13535 }
13536 case ARM::LDC2L_POST:
13537 case ARM::LDC2_POST:
13538 case ARM::STC2L_POST:
13539 case ARM::STC2_POST:
13540 case ARM::t2LDC2L_POST:
13541 case ARM::t2LDC2_POST:
13542 case ARM::t2LDCL_POST:
13543 case ARM::t2LDC_POST:
13544 case ARM::t2STC2L_POST:
13545 case ARM::t2STC2_POST:
13546 case ARM::t2STCL_POST:
13547 case ARM::t2STC_POST: {
13548 // op: offset
13549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13550 Value |= (op & UINT64_C(256)) << 15;
13551 Value |= (op & UINT64_C(255));
13552 // op: addr
13553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13554 op &= UINT64_C(15);
13555 op <<= 16;
13556 Value |= op;
13557 // op: cop
13558 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13559 op &= UINT64_C(15);
13560 op <<= 8;
13561 Value |= op;
13562 // op: CRd
13563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13564 op &= UINT64_C(15);
13565 op <<= 12;
13566 Value |= op;
13567 break;
13568 }
13569 case ARM::CDP2:
13570 case ARM::t2CDP:
13571 case ARM::t2CDP2: {
13572 // op: opc1
13573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13574 op &= UINT64_C(15);
13575 op <<= 20;
13576 Value |= op;
13577 // op: CRn
13578 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13579 op &= UINT64_C(15);
13580 op <<= 16;
13581 Value |= op;
13582 // op: CRd
13583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13584 op &= UINT64_C(15);
13585 op <<= 12;
13586 Value |= op;
13587 // op: cop
13588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13589 op &= UINT64_C(15);
13590 op <<= 8;
13591 Value |= op;
13592 // op: opc2
13593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
13594 op &= UINT64_C(7);
13595 op <<= 5;
13596 Value |= op;
13597 // op: CRm
13598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13599 op &= UINT64_C(15);
13600 Value |= op;
13601 break;
13602 }
13603 case ARM::DMB:
13604 case ARM::DSB:
13605 case ARM::ISB:
13606 case ARM::t2DBG:
13607 case ARM::t2DMB:
13608 case ARM::t2DSB:
13609 case ARM::t2ISB: {
13610 // op: opt
13611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13612 op &= UINT64_C(15);
13613 Value |= op;
13614 break;
13615 }
13616 case ARM::t2SMC: {
13617 // op: opt
13618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13619 op &= UINT64_C(15);
13620 op <<= 16;
13621 Value |= op;
13622 break;
13623 }
13624 case ARM::LDC2L_OPTION:
13625 case ARM::LDC2_OPTION:
13626 case ARM::STC2L_OPTION:
13627 case ARM::STC2_OPTION:
13628 case ARM::t2LDC2L_OPTION:
13629 case ARM::t2LDC2_OPTION:
13630 case ARM::t2LDCL_OPTION:
13631 case ARM::t2LDC_OPTION:
13632 case ARM::t2STC2L_OPTION:
13633 case ARM::t2STC2_OPTION:
13634 case ARM::t2STCL_OPTION:
13635 case ARM::t2STC_OPTION: {
13636 // op: option
13637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13638 op &= UINT64_C(255);
13639 Value |= op;
13640 // op: addr
13641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13642 op &= UINT64_C(15);
13643 op <<= 16;
13644 Value |= op;
13645 // op: cop
13646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13647 op &= UINT64_C(15);
13648 op <<= 8;
13649 Value |= op;
13650 // op: CRd
13651 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13652 op &= UINT64_C(15);
13653 op <<= 12;
13654 Value |= op;
13655 break;
13656 }
13657 case ARM::BX_RET:
13658 case ARM::ERET:
13659 case ARM::MOVPCLR: {
13660 // op: p
13661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13662 op &= UINT64_C(15);
13663 op <<= 28;
13664 Value |= op;
13665 break;
13666 }
13667 case ARM::FMSTAT: {
13668 // op: p
13669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13670 op &= UINT64_C(15);
13671 op <<= 28;
13672 Value |= op;
13673 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13674 break;
13675 }
13676 case ARM::t2Bcc: {
13677 // op: p
13678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13679 op &= UINT64_C(15);
13680 op <<= 22;
13681 Value |= op;
13682 // op: target
13683 op = getBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI);
13684 Value |= (op & UINT64_C(1048576)) << 6;
13685 Value |= (op & UINT64_C(258048)) << 4;
13686 Value |= (op & UINT64_C(262144)) >> 5;
13687 Value |= (op & UINT64_C(524288)) >> 8;
13688 Value |= (op & UINT64_C(4094)) >> 1;
13689 break;
13690 }
13691 case ARM::VCMPEZD:
13692 case ARM::VCMPZD: {
13693 // op: p
13694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13695 op &= UINT64_C(15);
13696 op <<= 28;
13697 Value |= op;
13698 // op: Dd
13699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13700 Value |= (op & UINT64_C(16)) << 18;
13701 Value |= (op & UINT64_C(15)) << 12;
13702 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13703 break;
13704 }
13705 case ARM::MRS:
13706 case ARM::MRSsys: {
13707 // op: p
13708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13709 op &= UINT64_C(15);
13710 op <<= 28;
13711 Value |= op;
13712 // op: Rd
13713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13714 op &= UINT64_C(15);
13715 op <<= 12;
13716 Value |= op;
13717 break;
13718 }
13719 case ARM::VLDMSIA:
13720 case ARM::VSTMSIA: {
13721 // op: p
13722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13723 op &= UINT64_C(15);
13724 op <<= 28;
13725 Value |= op;
13726 // op: Rn
13727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13728 op &= UINT64_C(15);
13729 op <<= 16;
13730 Value |= op;
13731 // op: regs
13732 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
13733 Value |= (op & UINT64_C(256)) << 14;
13734 Value |= (op & UINT64_C(7680)) << 3;
13735 Value |= (op & UINT64_C(255));
13736 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13737 break;
13738 }
13739 case ARM::FLDMXIA:
13740 case ARM::FSTMXIA: {
13741 // op: p
13742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13743 op &= UINT64_C(15);
13744 op <<= 28;
13745 Value |= op;
13746 // op: Rn
13747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13748 op &= UINT64_C(15);
13749 op <<= 16;
13750 Value |= op;
13751 // op: regs
13752 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
13753 Value |= (op & UINT64_C(3840)) << 4;
13754 Value |= (op & UINT64_C(254));
13755 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13756 break;
13757 }
13758 case ARM::VLDMDIA:
13759 case ARM::VSTMDIA: {
13760 // op: p
13761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13762 op &= UINT64_C(15);
13763 op <<= 28;
13764 Value |= op;
13765 // op: Rn
13766 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13767 op &= UINT64_C(15);
13768 op <<= 16;
13769 Value |= op;
13770 // op: regs
13771 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
13772 Value |= (op & UINT64_C(4096)) << 10;
13773 Value |= (op & UINT64_C(3840)) << 4;
13774 Value |= (op & UINT64_C(254));
13775 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13776 break;
13777 }
13778 case ARM::VMRS:
13779 case ARM::VMRS_FPCXTNS:
13780 case ARM::VMRS_FPCXTS:
13781 case ARM::VMRS_FPEXC:
13782 case ARM::VMRS_FPINST:
13783 case ARM::VMRS_FPINST2:
13784 case ARM::VMRS_FPSID:
13785 case ARM::VMRS_MVFR0:
13786 case ARM::VMRS_MVFR1:
13787 case ARM::VMRS_MVFR2:
13788 case ARM::VMRS_VPR:
13789 case ARM::VMSR:
13790 case ARM::VMSR_FPCXTNS:
13791 case ARM::VMSR_FPCXTS:
13792 case ARM::VMSR_FPEXC:
13793 case ARM::VMSR_FPINST:
13794 case ARM::VMSR_FPINST2:
13795 case ARM::VMSR_FPSID:
13796 case ARM::VMSR_VPR: {
13797 // op: p
13798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13799 op &= UINT64_C(15);
13800 op <<= 28;
13801 Value |= op;
13802 // op: Rt
13803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13804 op &= UINT64_C(15);
13805 op <<= 12;
13806 Value |= op;
13807 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13808 break;
13809 }
13810 case ARM::VCMPEZH:
13811 case ARM::VCMPEZS:
13812 case ARM::VCMPZH:
13813 case ARM::VCMPZS: {
13814 // op: p
13815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13816 op &= UINT64_C(15);
13817 op <<= 28;
13818 Value |= op;
13819 // op: Sd
13820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13821 Value |= (op & UINT64_C(1)) << 22;
13822 Value |= (op & UINT64_C(30)) << 11;
13823 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13824 break;
13825 }
13826 case ARM::BX_pred: {
13827 // op: p
13828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13829 op &= UINT64_C(15);
13830 op <<= 28;
13831 Value |= op;
13832 // op: dst
13833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13834 op &= UINT64_C(15);
13835 Value |= op;
13836 break;
13837 }
13838 case ARM::BL_pred: {
13839 // op: p
13840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13841 op &= UINT64_C(15);
13842 op <<= 28;
13843 Value |= op;
13844 // op: func
13845 op = getARMBLTargetOpValue(MI, OpIdx: 0, Fixups, STI);
13846 op &= UINT64_C(16777215);
13847 Value |= op;
13848 break;
13849 }
13850 case ARM::BLX_pred:
13851 case ARM::BXJ: {
13852 // op: p
13853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13854 op &= UINT64_C(15);
13855 op <<= 28;
13856 Value |= op;
13857 // op: func
13858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13859 op &= UINT64_C(15);
13860 Value |= op;
13861 break;
13862 }
13863 case ARM::HINT: {
13864 // op: p
13865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13866 op &= UINT64_C(15);
13867 op <<= 28;
13868 Value |= op;
13869 // op: imm
13870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13871 op &= UINT64_C(255);
13872 Value |= op;
13873 break;
13874 }
13875 case ARM::DBG:
13876 case ARM::SMC: {
13877 // op: p
13878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13879 op &= UINT64_C(15);
13880 op <<= 28;
13881 Value |= op;
13882 // op: opt
13883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13884 op &= UINT64_C(15);
13885 Value |= op;
13886 break;
13887 }
13888 case ARM::LDMDA:
13889 case ARM::LDMDB:
13890 case ARM::LDMIA:
13891 case ARM::LDMIB:
13892 case ARM::STMDA:
13893 case ARM::STMDB:
13894 case ARM::STMIA:
13895 case ARM::STMIB:
13896 case ARM::sysLDMDA:
13897 case ARM::sysLDMDB:
13898 case ARM::sysLDMIA:
13899 case ARM::sysLDMIB:
13900 case ARM::sysSTMDA:
13901 case ARM::sysSTMDB:
13902 case ARM::sysSTMIA:
13903 case ARM::sysSTMIB: {
13904 // op: p
13905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13906 op &= UINT64_C(15);
13907 op <<= 28;
13908 Value |= op;
13909 // op: regs
13910 op = getRegisterListOpValue(MI, Op: 3, Fixups, STI);
13911 op &= UINT64_C(65535);
13912 Value |= op;
13913 // op: Rn
13914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13915 op &= UINT64_C(15);
13916 op <<= 16;
13917 Value |= op;
13918 break;
13919 }
13920 case ARM::SVC: {
13921 // op: p
13922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13923 op &= UINT64_C(15);
13924 op <<= 28;
13925 Value |= op;
13926 // op: svc
13927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13928 op &= UINT64_C(16777215);
13929 Value |= op;
13930 break;
13931 }
13932 case ARM::Bcc: {
13933 // op: p
13934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13935 op &= UINT64_C(15);
13936 op <<= 28;
13937 Value |= op;
13938 // op: target
13939 op = getARMBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI);
13940 op &= UINT64_C(16777215);
13941 Value |= op;
13942 break;
13943 }
13944 case ARM::tBcc: {
13945 // op: p
13946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13947 op &= UINT64_C(15);
13948 op <<= 8;
13949 Value |= op;
13950 // op: target
13951 op = getThumbBCCTargetOpValue(MI, OpIdx: 0, Fixups, STI);
13952 op &= UINT64_C(255);
13953 Value |= op;
13954 break;
13955 }
13956 case ARM::VABSD:
13957 case ARM::VCMPD:
13958 case ARM::VCMPED:
13959 case ARM::VMOVD:
13960 case ARM::VNEGD:
13961 case ARM::VRINTRD:
13962 case ARM::VRINTXD:
13963 case ARM::VRINTZD:
13964 case ARM::VSQRTD: {
13965 // op: p
13966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13967 op &= UINT64_C(15);
13968 op <<= 28;
13969 Value |= op;
13970 // op: Dd
13971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13972 Value |= (op & UINT64_C(16)) << 18;
13973 Value |= (op & UINT64_C(15)) << 12;
13974 // op: Dm
13975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13976 Value |= (op & UINT64_C(16)) << 1;
13977 Value |= (op & UINT64_C(15));
13978 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13979 break;
13980 }
13981 case ARM::VCVTBHD:
13982 case ARM::VCVTTHD:
13983 case ARM::VSITOD:
13984 case ARM::VUITOD: {
13985 // op: p
13986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13987 op &= UINT64_C(15);
13988 op <<= 28;
13989 Value |= op;
13990 // op: Dd
13991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13992 Value |= (op & UINT64_C(16)) << 18;
13993 Value |= (op & UINT64_C(15)) << 12;
13994 // op: Sm
13995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13996 Value |= (op & UINT64_C(1)) << 5;
13997 Value |= (op & UINT64_C(30)) >> 1;
13998 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
13999 break;
14000 }
14001 case ARM::FCONSTD: {
14002 // op: p
14003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14004 op &= UINT64_C(15);
14005 op <<= 28;
14006 Value |= op;
14007 // op: Dd
14008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14009 Value |= (op & UINT64_C(16)) << 18;
14010 Value |= (op & UINT64_C(15)) << 12;
14011 // op: imm
14012 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14013 Value |= (op & UINT64_C(240)) << 12;
14014 Value |= (op & UINT64_C(15));
14015 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14016 break;
14017 }
14018 case ARM::CLZ:
14019 case ARM::RBIT:
14020 case ARM::REV:
14021 case ARM::REV16:
14022 case ARM::REVSH: {
14023 // op: p
14024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14025 op &= UINT64_C(15);
14026 op <<= 28;
14027 Value |= op;
14028 // op: Rd
14029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14030 op &= UINT64_C(15);
14031 op <<= 12;
14032 Value |= op;
14033 // op: Rm
14034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14035 op &= UINT64_C(15);
14036 Value |= op;
14037 break;
14038 }
14039 case ARM::MOVi16: {
14040 // op: p
14041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14042 op &= UINT64_C(15);
14043 op <<= 28;
14044 Value |= op;
14045 // op: Rd
14046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14047 op &= UINT64_C(15);
14048 op <<= 12;
14049 Value |= op;
14050 // op: imm
14051 op = getHiLoImmOpValue(MI, OpIdx: 1, Fixups, STI);
14052 Value |= (op & UINT64_C(61440)) << 4;
14053 Value |= (op & UINT64_C(4095));
14054 break;
14055 }
14056 case ARM::ADR: {
14057 // op: p
14058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14059 op &= UINT64_C(15);
14060 op <<= 28;
14061 Value |= op;
14062 // op: Rd
14063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14064 op &= UINT64_C(15);
14065 op <<= 12;
14066 Value |= op;
14067 // op: label
14068 op = getAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI);
14069 Value |= (op & UINT64_C(12288)) << 10;
14070 Value |= (op & UINT64_C(4095));
14071 break;
14072 }
14073 case ARM::CMNzrr:
14074 case ARM::CMPrr:
14075 case ARM::TEQrr:
14076 case ARM::TSTrr: {
14077 // op: p
14078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14079 op &= UINT64_C(15);
14080 op <<= 28;
14081 Value |= op;
14082 // op: Rn
14083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14084 op &= UINT64_C(15);
14085 op <<= 16;
14086 Value |= op;
14087 // op: Rm
14088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14089 op &= UINT64_C(15);
14090 Value |= op;
14091 break;
14092 }
14093 case ARM::CMNri:
14094 case ARM::CMPri:
14095 case ARM::TEQri:
14096 case ARM::TSTri: {
14097 // op: p
14098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14099 op &= UINT64_C(15);
14100 op <<= 28;
14101 Value |= op;
14102 // op: Rn
14103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14104 op &= UINT64_C(15);
14105 op <<= 16;
14106 Value |= op;
14107 // op: imm
14108 op = getModImmOpValue(MI, Op: 1, Fixups, ST: STI);
14109 op &= UINT64_C(4095);
14110 Value |= op;
14111 break;
14112 }
14113 case ARM::VLDMSDB_UPD:
14114 case ARM::VLDMSIA_UPD:
14115 case ARM::VSTMSDB_UPD:
14116 case ARM::VSTMSIA_UPD: {
14117 // op: p
14118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14119 op &= UINT64_C(15);
14120 op <<= 28;
14121 Value |= op;
14122 // op: Rn
14123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14124 op &= UINT64_C(15);
14125 op <<= 16;
14126 Value |= op;
14127 // op: regs
14128 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
14129 Value |= (op & UINT64_C(256)) << 14;
14130 Value |= (op & UINT64_C(7680)) << 3;
14131 Value |= (op & UINT64_C(255));
14132 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14133 break;
14134 }
14135 case ARM::FLDMXDB_UPD:
14136 case ARM::FLDMXIA_UPD:
14137 case ARM::FSTMXDB_UPD:
14138 case ARM::FSTMXIA_UPD: {
14139 // op: p
14140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14141 op &= UINT64_C(15);
14142 op <<= 28;
14143 Value |= op;
14144 // op: Rn
14145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14146 op &= UINT64_C(15);
14147 op <<= 16;
14148 Value |= op;
14149 // op: regs
14150 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
14151 Value |= (op & UINT64_C(3840)) << 4;
14152 Value |= (op & UINT64_C(254));
14153 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14154 break;
14155 }
14156 case ARM::VLDMDDB_UPD:
14157 case ARM::VLDMDIA_UPD:
14158 case ARM::VSTMDDB_UPD:
14159 case ARM::VSTMDIA_UPD: {
14160 // op: p
14161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14162 op &= UINT64_C(15);
14163 op <<= 28;
14164 Value |= op;
14165 // op: Rn
14166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14167 op &= UINT64_C(15);
14168 op <<= 16;
14169 Value |= op;
14170 // op: regs
14171 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
14172 Value |= (op & UINT64_C(4096)) << 10;
14173 Value |= (op & UINT64_C(3840)) << 4;
14174 Value |= (op & UINT64_C(254));
14175 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14176 break;
14177 }
14178 case ARM::STL:
14179 case ARM::STLB:
14180 case ARM::STLH: {
14181 // op: p
14182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14183 op &= UINT64_C(15);
14184 op <<= 28;
14185 Value |= op;
14186 // op: Rt
14187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14188 op &= UINT64_C(15);
14189 Value |= op;
14190 // op: addr
14191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14192 op &= UINT64_C(15);
14193 op <<= 16;
14194 Value |= op;
14195 break;
14196 }
14197 case ARM::VMOVRH:
14198 case ARM::VMOVRS: {
14199 // op: p
14200 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14201 op &= UINT64_C(15);
14202 op <<= 28;
14203 Value |= op;
14204 // op: Rt
14205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14206 op &= UINT64_C(15);
14207 op <<= 12;
14208 Value |= op;
14209 // op: Sn
14210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14211 Value |= (op & UINT64_C(30)) << 15;
14212 Value |= (op & UINT64_C(1)) << 7;
14213 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14214 break;
14215 }
14216 case ARM::LDA:
14217 case ARM::LDAB:
14218 case ARM::LDAEX:
14219 case ARM::LDAEXB:
14220 case ARM::LDAEXD:
14221 case ARM::LDAEXH:
14222 case ARM::LDAH:
14223 case ARM::LDREX:
14224 case ARM::LDREXB:
14225 case ARM::LDREXD:
14226 case ARM::LDREXH: {
14227 // op: p
14228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14229 op &= UINT64_C(15);
14230 op <<= 28;
14231 Value |= op;
14232 // op: Rt
14233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14234 op &= UINT64_C(15);
14235 op <<= 12;
14236 Value |= op;
14237 // op: addr
14238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14239 op &= UINT64_C(15);
14240 op <<= 16;
14241 Value |= op;
14242 break;
14243 }
14244 case ARM::VMRS_FPSCR_NZCVQC:
14245 case ARM::VMRS_P0: {
14246 // op: p
14247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14248 op &= UINT64_C(15);
14249 op <<= 28;
14250 Value |= op;
14251 // op: Rt
14252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14253 op &= UINT64_C(15);
14254 op <<= 12;
14255 Value |= op;
14256 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14257 break;
14258 }
14259 case ARM::VMSR_FPSCR_NZCVQC:
14260 case ARM::VMSR_P0: {
14261 // op: p
14262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14263 op &= UINT64_C(15);
14264 op <<= 28;
14265 Value |= op;
14266 // op: Rt
14267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14268 op &= UINT64_C(15);
14269 op <<= 12;
14270 Value |= op;
14271 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14272 break;
14273 }
14274 case ARM::VCVTSD:
14275 case ARM::VJCVT:
14276 case ARM::VTOSIRD:
14277 case ARM::VTOSIZD:
14278 case ARM::VTOUIRD:
14279 case ARM::VTOUIZD: {
14280 // op: p
14281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14282 op &= UINT64_C(15);
14283 op <<= 28;
14284 Value |= op;
14285 // op: Sd
14286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14287 Value |= (op & UINT64_C(1)) << 22;
14288 Value |= (op & UINT64_C(30)) << 11;
14289 // op: Dm
14290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14291 Value |= (op & UINT64_C(16)) << 1;
14292 Value |= (op & UINT64_C(15));
14293 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14294 break;
14295 }
14296 case ARM::VABSH:
14297 case ARM::VABSS:
14298 case ARM::VCMPEH:
14299 case ARM::VCMPES:
14300 case ARM::VCMPH:
14301 case ARM::VCMPS:
14302 case ARM::VCVTBHS:
14303 case ARM::VCVTTHS:
14304 case ARM::VMOVS:
14305 case ARM::VNEGH:
14306 case ARM::VNEGS:
14307 case ARM::VRINTRH:
14308 case ARM::VRINTRS:
14309 case ARM::VRINTXH:
14310 case ARM::VRINTXS:
14311 case ARM::VRINTZH:
14312 case ARM::VRINTZS:
14313 case ARM::VSITOH:
14314 case ARM::VSITOS:
14315 case ARM::VSQRTH:
14316 case ARM::VSQRTS:
14317 case ARM::VTOSIRH:
14318 case ARM::VTOSIRS:
14319 case ARM::VTOSIZH:
14320 case ARM::VTOSIZS:
14321 case ARM::VTOUIRH:
14322 case ARM::VTOUIRS:
14323 case ARM::VTOUIZH:
14324 case ARM::VTOUIZS:
14325 case ARM::VUITOH:
14326 case ARM::VUITOS: {
14327 // op: p
14328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14329 op &= UINT64_C(15);
14330 op <<= 28;
14331 Value |= op;
14332 // op: Sd
14333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14334 Value |= (op & UINT64_C(1)) << 22;
14335 Value |= (op & UINT64_C(30)) << 11;
14336 // op: Sm
14337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14338 Value |= (op & UINT64_C(1)) << 5;
14339 Value |= (op & UINT64_C(30)) >> 1;
14340 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14341 break;
14342 }
14343 case ARM::FCONSTH:
14344 case ARM::FCONSTS: {
14345 // op: p
14346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14347 op &= UINT64_C(15);
14348 op <<= 28;
14349 Value |= op;
14350 // op: Sd
14351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14352 Value |= (op & UINT64_C(1)) << 22;
14353 Value |= (op & UINT64_C(30)) << 11;
14354 // op: imm
14355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14356 Value |= (op & UINT64_C(240)) << 12;
14357 Value |= (op & UINT64_C(15));
14358 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14359 break;
14360 }
14361 case ARM::VCVTDS: {
14362 // op: p
14363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14364 op &= UINT64_C(15);
14365 op <<= 28;
14366 Value |= op;
14367 // op: Sm
14368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14369 Value |= (op & UINT64_C(1)) << 5;
14370 Value |= (op & UINT64_C(30)) >> 1;
14371 // op: Dd
14372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14373 Value |= (op & UINT64_C(16)) << 18;
14374 Value |= (op & UINT64_C(15)) << 12;
14375 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14376 break;
14377 }
14378 case ARM::VMOVHR:
14379 case ARM::VMOVSR: {
14380 // op: p
14381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14382 op &= UINT64_C(15);
14383 op <<= 28;
14384 Value |= op;
14385 // op: Sn
14386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14387 Value |= (op & UINT64_C(30)) << 15;
14388 Value |= (op & UINT64_C(1)) << 7;
14389 // op: Rt
14390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14391 op &= UINT64_C(15);
14392 op <<= 12;
14393 Value |= op;
14394 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14395 break;
14396 }
14397 case ARM::VLDR_FPCXTNS_off:
14398 case ARM::VLDR_FPCXTS_off:
14399 case ARM::VLDR_FPSCR_NZCVQC_off:
14400 case ARM::VLDR_FPSCR_off:
14401 case ARM::VLDR_VPR_off:
14402 case ARM::VSTR_FPCXTNS_off:
14403 case ARM::VSTR_FPCXTS_off:
14404 case ARM::VSTR_FPSCR_NZCVQC_off:
14405 case ARM::VSTR_FPSCR_off:
14406 case ARM::VSTR_VPR_off: {
14407 // op: p
14408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14409 op &= UINT64_C(15);
14410 op <<= 28;
14411 Value |= op;
14412 // op: addr
14413 op = getT2AddrModeImm7s4OpValue(MI, OpIdx: 0, Fixups, STI);
14414 Value |= (op & UINT64_C(128)) << 16;
14415 Value |= (op & UINT64_C(3840)) << 8;
14416 Value |= (op & UINT64_C(127));
14417 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14418 break;
14419 }
14420 case ARM::MSRbanked: {
14421 // op: p
14422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14423 op &= UINT64_C(15);
14424 op <<= 28;
14425 Value |= op;
14426 // op: banked
14427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14428 Value |= (op & UINT64_C(32)) << 17;
14429 Value |= (op & UINT64_C(15)) << 16;
14430 Value |= (op & UINT64_C(16)) << 4;
14431 // op: Rn
14432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14433 op &= UINT64_C(15);
14434 Value |= op;
14435 break;
14436 }
14437 case ARM::MRSbanked: {
14438 // op: p
14439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14440 op &= UINT64_C(15);
14441 op <<= 28;
14442 Value |= op;
14443 // op: banked
14444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14445 Value |= (op & UINT64_C(32)) << 17;
14446 Value |= (op & UINT64_C(15)) << 16;
14447 Value |= (op & UINT64_C(16)) << 4;
14448 // op: Rd
14449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14450 op &= UINT64_C(15);
14451 op <<= 12;
14452 Value |= op;
14453 break;
14454 }
14455 case ARM::MSR: {
14456 // op: p
14457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14458 op &= UINT64_C(15);
14459 op <<= 28;
14460 Value |= op;
14461 // op: mask
14462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14463 Value |= (op & UINT64_C(16)) << 18;
14464 Value |= (op & UINT64_C(15)) << 16;
14465 // op: Rn
14466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14467 op &= UINT64_C(15);
14468 Value |= op;
14469 break;
14470 }
14471 case ARM::MSRi: {
14472 // op: p
14473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14474 op &= UINT64_C(15);
14475 op <<= 28;
14476 Value |= op;
14477 // op: mask
14478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14479 Value |= (op & UINT64_C(16)) << 18;
14480 Value |= (op & UINT64_C(15)) << 16;
14481 // op: imm
14482 op = getModImmOpValue(MI, Op: 1, Fixups, ST: STI);
14483 op &= UINT64_C(4095);
14484 Value |= op;
14485 break;
14486 }
14487 case ARM::LDMDA_UPD:
14488 case ARM::LDMDB_UPD:
14489 case ARM::LDMIA_UPD:
14490 case ARM::LDMIB_UPD:
14491 case ARM::STMDA_UPD:
14492 case ARM::STMDB_UPD:
14493 case ARM::STMIA_UPD:
14494 case ARM::STMIB_UPD:
14495 case ARM::sysLDMDA_UPD:
14496 case ARM::sysLDMDB_UPD:
14497 case ARM::sysLDMIA_UPD:
14498 case ARM::sysLDMIB_UPD:
14499 case ARM::sysSTMDA_UPD:
14500 case ARM::sysSTMDB_UPD:
14501 case ARM::sysSTMIA_UPD:
14502 case ARM::sysSTMIB_UPD: {
14503 // op: p
14504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14505 op &= UINT64_C(15);
14506 op <<= 28;
14507 Value |= op;
14508 // op: regs
14509 op = getRegisterListOpValue(MI, Op: 4, Fixups, STI);
14510 op &= UINT64_C(65535);
14511 Value |= op;
14512 // op: Rn
14513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14514 op &= UINT64_C(15);
14515 op <<= 16;
14516 Value |= op;
14517 break;
14518 }
14519 case ARM::MOVr:
14520 case ARM::MOVr_TC:
14521 case ARM::MVNr: {
14522 // op: p
14523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14524 op &= UINT64_C(15);
14525 op <<= 28;
14526 Value |= op;
14527 // op: s
14528 op = getCCOutOpValue(MI, Op: 4, Fixups, STI);
14529 op &= UINT64_C(1);
14530 op <<= 20;
14531 Value |= op;
14532 // op: Rd
14533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14534 op &= UINT64_C(15);
14535 op <<= 12;
14536 Value |= op;
14537 // op: Rm
14538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14539 op &= UINT64_C(15);
14540 Value |= op;
14541 break;
14542 }
14543 case ARM::MOVi:
14544 case ARM::MVNi: {
14545 // op: p
14546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14547 op &= UINT64_C(15);
14548 op <<= 28;
14549 Value |= op;
14550 // op: s
14551 op = getCCOutOpValue(MI, Op: 4, Fixups, STI);
14552 op &= UINT64_C(1);
14553 op <<= 20;
14554 Value |= op;
14555 // op: Rd
14556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14557 op &= UINT64_C(15);
14558 op <<= 12;
14559 Value |= op;
14560 // op: imm
14561 op = getModImmOpValue(MI, Op: 1, Fixups, ST: STI);
14562 op &= UINT64_C(4095);
14563 Value |= op;
14564 break;
14565 }
14566 case ARM::VADDD:
14567 case ARM::VDIVD:
14568 case ARM::VMULD:
14569 case ARM::VNMULD:
14570 case ARM::VSUBD: {
14571 // op: p
14572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14573 op &= UINT64_C(15);
14574 op <<= 28;
14575 Value |= op;
14576 // op: Dd
14577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14578 Value |= (op & UINT64_C(16)) << 18;
14579 Value |= (op & UINT64_C(15)) << 12;
14580 // op: Dn
14581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14582 Value |= (op & UINT64_C(15)) << 16;
14583 Value |= (op & UINT64_C(16)) << 3;
14584 // op: Dm
14585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14586 Value |= (op & UINT64_C(16)) << 1;
14587 Value |= (op & UINT64_C(15));
14588 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14589 break;
14590 }
14591 case ARM::VLDRD:
14592 case ARM::VSTRD: {
14593 // op: p
14594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14595 op &= UINT64_C(15);
14596 op <<= 28;
14597 Value |= op;
14598 // op: Dd
14599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14600 Value |= (op & UINT64_C(16)) << 18;
14601 Value |= (op & UINT64_C(15)) << 12;
14602 // op: addr
14603 op = getAddrMode5OpValue(MI, OpIdx: 1, Fixups, STI);
14604 Value |= (op & UINT64_C(256)) << 15;
14605 Value |= (op & UINT64_C(7680)) << 7;
14606 Value |= (op & UINT64_C(255));
14607 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14608 break;
14609 }
14610 case ARM::VMOVDRR: {
14611 // op: p
14612 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14613 op &= UINT64_C(15);
14614 op <<= 28;
14615 Value |= op;
14616 // op: Dm
14617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14618 Value |= (op & UINT64_C(16)) << 1;
14619 Value |= (op & UINT64_C(15));
14620 // op: Rt
14621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14622 op &= UINT64_C(15);
14623 op <<= 12;
14624 Value |= op;
14625 // op: Rt2
14626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14627 op &= UINT64_C(15);
14628 op <<= 16;
14629 Value |= op;
14630 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14631 break;
14632 }
14633 case ARM::VMOVRRD: {
14634 // op: p
14635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14636 op &= UINT64_C(15);
14637 op <<= 28;
14638 Value |= op;
14639 // op: Dm
14640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14641 Value |= (op & UINT64_C(16)) << 1;
14642 Value |= (op & UINT64_C(15));
14643 // op: Rt
14644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14645 op &= UINT64_C(15);
14646 op <<= 12;
14647 Value |= op;
14648 // op: Rt2
14649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14650 op &= UINT64_C(15);
14651 op <<= 16;
14652 Value |= op;
14653 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14654 break;
14655 }
14656 case ARM::VCVTBDH:
14657 case ARM::VCVTTDH: {
14658 // op: p
14659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14660 op &= UINT64_C(15);
14661 op <<= 28;
14662 Value |= op;
14663 // op: Dm
14664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14665 Value |= (op & UINT64_C(16)) << 1;
14666 Value |= (op & UINT64_C(15));
14667 // op: Sd
14668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14669 Value |= (op & UINT64_C(1)) << 22;
14670 Value |= (op & UINT64_C(30)) << 11;
14671 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
14672 break;
14673 }
14674 case ARM::SXTB:
14675 case ARM::SXTB16:
14676 case ARM::SXTH:
14677 case ARM::UXTB:
14678 case ARM::UXTB16:
14679 case ARM::UXTH: {
14680 // op: p
14681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14682 op &= UINT64_C(15);
14683 op <<= 28;
14684 Value |= op;
14685 // op: Rd
14686 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14687 op &= UINT64_C(15);
14688 op <<= 12;
14689 Value |= op;
14690 // op: Rm
14691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14692 op &= UINT64_C(15);
14693 Value |= op;
14694 // op: rot
14695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14696 op &= UINT64_C(3);
14697 op <<= 10;
14698 Value |= op;
14699 break;
14700 }
14701 case ARM::SEL: {
14702 // op: p
14703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14704 op &= UINT64_C(15);
14705 op <<= 28;
14706 Value |= op;
14707 // op: Rd
14708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14709 op &= UINT64_C(15);
14710 op <<= 12;
14711 Value |= op;
14712 // op: Rn
14713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14714 op &= UINT64_C(15);
14715 op <<= 16;
14716 Value |= op;
14717 // op: Rm
14718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14719 op &= UINT64_C(15);
14720 Value |= op;
14721 break;
14722 }
14723 case ARM::BFC: {
14724 // op: p
14725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14726 op &= UINT64_C(15);
14727 op <<= 28;
14728 Value |= op;
14729 // op: Rd
14730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14731 op &= UINT64_C(15);
14732 op <<= 12;
14733 Value |= op;
14734 // op: imm
14735 op = getBitfieldInvertedMaskOpValue(MI, Op: 2, Fixups, STI);
14736 Value |= (op & UINT64_C(992)) << 11;
14737 Value |= (op & UINT64_C(31)) << 7;
14738 break;
14739 }
14740 case ARM::MOVTi16: {
14741 // op: p
14742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14743 op &= UINT64_C(15);
14744 op <<= 28;
14745 Value |= op;
14746 // op: Rd
14747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14748 op &= UINT64_C(15);
14749 op <<= 12;
14750 Value |= op;
14751 // op: imm
14752 op = getHiLoImmOpValue(MI, OpIdx: 2, Fixups, STI);
14753 Value |= (op & UINT64_C(61440)) << 4;
14754 Value |= (op & UINT64_C(4095));
14755 break;
14756 }
14757 case ARM::SSAT16:
14758 case ARM::USAT16: {
14759 // op: p
14760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14761 op &= UINT64_C(15);
14762 op <<= 28;
14763 Value |= op;
14764 // op: Rd
14765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14766 op &= UINT64_C(15);
14767 op <<= 12;
14768 Value |= op;
14769 // op: sat_imm
14770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14771 op &= UINT64_C(15);
14772 op <<= 16;
14773 Value |= op;
14774 // op: Rn
14775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14776 op &= UINT64_C(15);
14777 Value |= op;
14778 break;
14779 }
14780 case ARM::SDIV:
14781 case ARM::SMMUL:
14782 case ARM::SMMULR:
14783 case ARM::UDIV:
14784 case ARM::USAD8: {
14785 // op: p
14786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14787 op &= UINT64_C(15);
14788 op <<= 28;
14789 Value |= op;
14790 // op: Rd
14791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14792 op &= UINT64_C(15);
14793 op <<= 16;
14794 Value |= op;
14795 // op: Rn
14796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14797 op &= UINT64_C(15);
14798 Value |= op;
14799 // op: Rm
14800 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14801 op &= UINT64_C(15);
14802 op <<= 8;
14803 Value |= op;
14804 break;
14805 }
14806 case ARM::CMNzrsi:
14807 case ARM::CMPrsi:
14808 case ARM::TEQrsi:
14809 case ARM::TSTrsi: {
14810 // op: p
14811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14812 op &= UINT64_C(15);
14813 op <<= 28;
14814 Value |= op;
14815 // op: Rn
14816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14817 op &= UINT64_C(15);
14818 op <<= 16;
14819 Value |= op;
14820 // op: shift
14821 op = getSORegImmOpValue(MI, OpIdx: 1, Fixups, STI);
14822 Value |= (op & UINT64_C(4064));
14823 Value |= (op & UINT64_C(15));
14824 break;
14825 }
14826 case ARM::SMUAD:
14827 case ARM::SMUADX:
14828 case ARM::SMULBB:
14829 case ARM::SMULBT:
14830 case ARM::SMULTB:
14831 case ARM::SMULTT:
14832 case ARM::SMULWB:
14833 case ARM::SMULWT:
14834 case ARM::SMUSD:
14835 case ARM::SMUSDX: {
14836 // op: p
14837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14838 op &= UINT64_C(15);
14839 op <<= 28;
14840 Value |= op;
14841 // op: Rn
14842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14843 op &= UINT64_C(15);
14844 Value |= op;
14845 // op: Rm
14846 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14847 op &= UINT64_C(15);
14848 op <<= 8;
14849 Value |= op;
14850 // op: Rd
14851 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14852 op &= UINT64_C(15);
14853 op <<= 16;
14854 Value |= op;
14855 break;
14856 }
14857 case ARM::QADD8:
14858 case ARM::QADD16:
14859 case ARM::QASX:
14860 case ARM::QSAX:
14861 case ARM::QSUB8:
14862 case ARM::QSUB16:
14863 case ARM::SADD8:
14864 case ARM::SADD16:
14865 case ARM::SASX:
14866 case ARM::SHADD8:
14867 case ARM::SHADD16:
14868 case ARM::SHASX:
14869 case ARM::SHSAX:
14870 case ARM::SHSUB8:
14871 case ARM::SHSUB16:
14872 case ARM::SSAX:
14873 case ARM::SSUB8:
14874 case ARM::SSUB16:
14875 case ARM::UADD8:
14876 case ARM::UADD16:
14877 case ARM::UASX:
14878 case ARM::UHADD8:
14879 case ARM::UHADD16:
14880 case ARM::UHASX:
14881 case ARM::UHSAX:
14882 case ARM::UHSUB8:
14883 case ARM::UHSUB16:
14884 case ARM::UQADD8:
14885 case ARM::UQADD16:
14886 case ARM::UQASX:
14887 case ARM::UQSAX:
14888 case ARM::UQSUB8:
14889 case ARM::UQSUB16:
14890 case ARM::USAX:
14891 case ARM::USUB8:
14892 case ARM::USUB16: {
14893 // op: p
14894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14895 op &= UINT64_C(15);
14896 op <<= 28;
14897 Value |= op;
14898 // op: Rn
14899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14900 op &= UINT64_C(15);
14901 op <<= 16;
14902 Value |= op;
14903 // op: Rd
14904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14905 op &= UINT64_C(15);
14906 op <<= 12;
14907 Value |= op;
14908 // op: Rm
14909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14910 op &= UINT64_C(15);
14911 Value |= op;
14912 break;
14913 }
14914 case ARM::QADD:
14915 case ARM::QDADD:
14916 case ARM::QDSUB:
14917 case ARM::QSUB: {
14918 // op: p
14919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14920 op &= UINT64_C(15);
14921 op <<= 28;
14922 Value |= op;
14923 // op: Rn
14924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14925 op &= UINT64_C(15);
14926 op <<= 16;
14927 Value |= op;
14928 // op: Rd
14929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14930 op &= UINT64_C(15);
14931 op <<= 12;
14932 Value |= op;
14933 // op: Rm
14934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14935 op &= UINT64_C(15);
14936 Value |= op;
14937 break;
14938 }
14939 case ARM::SWP:
14940 case ARM::SWPB: {
14941 // op: p
14942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14943 op &= UINT64_C(15);
14944 op <<= 28;
14945 Value |= op;
14946 // op: Rt
14947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14948 op &= UINT64_C(15);
14949 op <<= 12;
14950 Value |= op;
14951 // op: Rt2
14952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14953 op &= UINT64_C(15);
14954 Value |= op;
14955 // op: addr
14956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14957 op &= UINT64_C(15);
14958 op <<= 16;
14959 Value |= op;
14960 break;
14961 }
14962 case ARM::LDRBi12:
14963 case ARM::LDRi12:
14964 case ARM::STRBi12:
14965 case ARM::STRi12: {
14966 // op: p
14967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14968 op &= UINT64_C(15);
14969 op <<= 28;
14970 Value |= op;
14971 // op: Rt
14972 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14973 op &= UINT64_C(15);
14974 op <<= 12;
14975 Value |= op;
14976 // op: addr
14977 op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI);
14978 Value |= (op & UINT64_C(4096)) << 11;
14979 Value |= (op & UINT64_C(122880)) << 3;
14980 Value |= (op & UINT64_C(4095));
14981 break;
14982 }
14983 case ARM::LDRcp: {
14984 // op: p
14985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14986 op &= UINT64_C(15);
14987 op <<= 28;
14988 Value |= op;
14989 // op: Rt
14990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14991 op &= UINT64_C(15);
14992 op <<= 12;
14993 Value |= op;
14994 // op: addr
14995 op = getAddrModeImm12OpValue(MI, OpIdx: 1, Fixups, STI);
14996 Value |= (op & UINT64_C(4096)) << 11;
14997 Value |= (op & UINT64_C(4095));
14998 break;
14999 }
15000 case ARM::STLEX:
15001 case ARM::STLEXB:
15002 case ARM::STLEXD:
15003 case ARM::STLEXH:
15004 case ARM::STREX:
15005 case ARM::STREXB:
15006 case ARM::STREXD:
15007 case ARM::STREXH: {
15008 // op: p
15009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15010 op &= UINT64_C(15);
15011 op <<= 28;
15012 Value |= op;
15013 // op: Rt
15014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15015 op &= UINT64_C(15);
15016 Value |= op;
15017 // op: addr
15018 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15019 op &= UINT64_C(15);
15020 op <<= 16;
15021 Value |= op;
15022 // op: Rd
15023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15024 op &= UINT64_C(15);
15025 op <<= 12;
15026 Value |= op;
15027 break;
15028 }
15029 case ARM::BF16_VCVTB:
15030 case ARM::BF16_VCVTT:
15031 case ARM::VCVTBSH:
15032 case ARM::VCVTTSH: {
15033 // op: p
15034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15035 op &= UINT64_C(15);
15036 op <<= 28;
15037 Value |= op;
15038 // op: Sd
15039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15040 Value |= (op & UINT64_C(1)) << 22;
15041 Value |= (op & UINT64_C(30)) << 11;
15042 // op: Sm
15043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15044 Value |= (op & UINT64_C(1)) << 5;
15045 Value |= (op & UINT64_C(30)) >> 1;
15046 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15047 break;
15048 }
15049 case ARM::VADDH:
15050 case ARM::VADDS:
15051 case ARM::VDIVH:
15052 case ARM::VDIVS:
15053 case ARM::VMULH:
15054 case ARM::VMULS:
15055 case ARM::VNMULH:
15056 case ARM::VNMULS:
15057 case ARM::VSUBH:
15058 case ARM::VSUBS: {
15059 // op: p
15060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15061 op &= UINT64_C(15);
15062 op <<= 28;
15063 Value |= op;
15064 // op: Sd
15065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15066 Value |= (op & UINT64_C(1)) << 22;
15067 Value |= (op & UINT64_C(30)) << 11;
15068 // op: Sn
15069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15070 Value |= (op & UINT64_C(30)) << 15;
15071 Value |= (op & UINT64_C(1)) << 7;
15072 // op: Sm
15073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15074 Value |= (op & UINT64_C(1)) << 5;
15075 Value |= (op & UINT64_C(30)) >> 1;
15076 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15077 break;
15078 }
15079 case ARM::VLDRH:
15080 case ARM::VSTRH: {
15081 // op: p
15082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15083 op &= UINT64_C(15);
15084 op <<= 28;
15085 Value |= op;
15086 // op: Sd
15087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15088 Value |= (op & UINT64_C(1)) << 22;
15089 Value |= (op & UINT64_C(30)) << 11;
15090 // op: addr
15091 op = getAddrMode5FP16OpValue(MI, OpIdx: 1, Fixups, STI);
15092 Value |= (op & UINT64_C(256)) << 15;
15093 Value |= (op & UINT64_C(7680)) << 7;
15094 Value |= (op & UINT64_C(255));
15095 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15096 break;
15097 }
15098 case ARM::VLDRS:
15099 case ARM::VSTRS: {
15100 // op: p
15101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15102 op &= UINT64_C(15);
15103 op <<= 28;
15104 Value |= op;
15105 // op: Sd
15106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15107 Value |= (op & UINT64_C(1)) << 22;
15108 Value |= (op & UINT64_C(30)) << 11;
15109 // op: addr
15110 op = getAddrMode5OpValue(MI, OpIdx: 1, Fixups, STI);
15111 Value |= (op & UINT64_C(256)) << 15;
15112 Value |= (op & UINT64_C(7680)) << 7;
15113 Value |= (op & UINT64_C(255));
15114 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15115 break;
15116 }
15117 case ARM::VLDR_FPCXTNS_pre:
15118 case ARM::VLDR_FPCXTS_pre:
15119 case ARM::VLDR_FPSCR_NZCVQC_pre:
15120 case ARM::VLDR_FPSCR_pre:
15121 case ARM::VLDR_P0_off:
15122 case ARM::VLDR_VPR_pre:
15123 case ARM::VSTR_FPCXTNS_pre:
15124 case ARM::VSTR_FPCXTS_pre:
15125 case ARM::VSTR_FPSCR_NZCVQC_pre:
15126 case ARM::VSTR_FPSCR_pre:
15127 case ARM::VSTR_P0_off:
15128 case ARM::VSTR_VPR_pre: {
15129 // op: p
15130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15131 op &= UINT64_C(15);
15132 op <<= 28;
15133 Value |= op;
15134 // op: addr
15135 op = getT2AddrModeImm7s4OpValue(MI, OpIdx: 1, Fixups, STI);
15136 Value |= (op & UINT64_C(128)) << 16;
15137 Value |= (op & UINT64_C(3840)) << 8;
15138 Value |= (op & UINT64_C(127));
15139 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15140 break;
15141 }
15142 case ARM::VLDR_FPCXTNS_post:
15143 case ARM::VLDR_FPCXTS_post:
15144 case ARM::VLDR_FPSCR_NZCVQC_post:
15145 case ARM::VLDR_FPSCR_post:
15146 case ARM::VLDR_VPR_post:
15147 case ARM::VSTR_FPCXTNS_post:
15148 case ARM::VSTR_FPCXTS_post:
15149 case ARM::VSTR_FPSCR_NZCVQC_post:
15150 case ARM::VSTR_FPSCR_post:
15151 case ARM::VSTR_VPR_post: {
15152 // op: p
15153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15154 op &= UINT64_C(15);
15155 op <<= 28;
15156 Value |= op;
15157 // op: addr
15158 op = getT2ScaledImmOpValue<7,2>(MI, OpIdx: 2, Fixups, STI);
15159 Value |= (op & UINT64_C(128)) << 16;
15160 Value |= (op & UINT64_C(127));
15161 // op: Rn
15162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15163 op &= UINT64_C(15);
15164 op <<= 16;
15165 Value |= op;
15166 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15167 break;
15168 }
15169 case ARM::VSHTOH:
15170 case ARM::VSHTOS:
15171 case ARM::VSLTOH:
15172 case ARM::VSLTOS:
15173 case ARM::VTOSHH:
15174 case ARM::VTOSHS:
15175 case ARM::VTOSLH:
15176 case ARM::VTOSLS:
15177 case ARM::VTOUHH:
15178 case ARM::VTOUHS:
15179 case ARM::VTOULH:
15180 case ARM::VTOULS:
15181 case ARM::VUHTOH:
15182 case ARM::VUHTOS:
15183 case ARM::VULTOH:
15184 case ARM::VULTOS: {
15185 // op: p
15186 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15187 op &= UINT64_C(15);
15188 op <<= 28;
15189 Value |= op;
15190 // op: fbits
15191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15192 Value |= (op & UINT64_C(1)) << 5;
15193 Value |= (op & UINT64_C(30)) >> 1;
15194 // op: dst
15195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15196 Value |= (op & UINT64_C(1)) << 22;
15197 Value |= (op & UINT64_C(30)) << 11;
15198 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15199 break;
15200 }
15201 case ARM::VSHTOD:
15202 case ARM::VSLTOD:
15203 case ARM::VTOSHD:
15204 case ARM::VTOSLD:
15205 case ARM::VTOUHD:
15206 case ARM::VTOULD:
15207 case ARM::VUHTOD:
15208 case ARM::VULTOD: {
15209 // op: p
15210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15211 op &= UINT64_C(15);
15212 op <<= 28;
15213 Value |= op;
15214 // op: fbits
15215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15216 Value |= (op & UINT64_C(1)) << 5;
15217 Value |= (op & UINT64_C(30)) >> 1;
15218 // op: dst
15219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15220 Value |= (op & UINT64_C(16)) << 18;
15221 Value |= (op & UINT64_C(15)) << 12;
15222 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15223 break;
15224 }
15225 case ARM::ADCrr:
15226 case ARM::ADDrr:
15227 case ARM::ANDrr:
15228 case ARM::BICrr:
15229 case ARM::EORrr:
15230 case ARM::ORRrr:
15231 case ARM::RSBrr:
15232 case ARM::RSCrr:
15233 case ARM::SBCrr:
15234 case ARM::SUBrr: {
15235 // op: p
15236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15237 op &= UINT64_C(15);
15238 op <<= 28;
15239 Value |= op;
15240 // op: s
15241 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
15242 op &= UINT64_C(1);
15243 op <<= 20;
15244 Value |= op;
15245 // op: Rd
15246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15247 op &= UINT64_C(15);
15248 op <<= 12;
15249 Value |= op;
15250 // op: Rn
15251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15252 op &= UINT64_C(15);
15253 op <<= 16;
15254 Value |= op;
15255 // op: Rm
15256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15257 op &= UINT64_C(15);
15258 Value |= op;
15259 break;
15260 }
15261 case ARM::ADCri:
15262 case ARM::ADDri:
15263 case ARM::ANDri:
15264 case ARM::BICri:
15265 case ARM::EORri:
15266 case ARM::ORRri:
15267 case ARM::RSBri:
15268 case ARM::RSCri:
15269 case ARM::SBCri:
15270 case ARM::SUBri: {
15271 // op: p
15272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15273 op &= UINT64_C(15);
15274 op <<= 28;
15275 Value |= op;
15276 // op: s
15277 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
15278 op &= UINT64_C(1);
15279 op <<= 20;
15280 Value |= op;
15281 // op: Rd
15282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15283 op &= UINT64_C(15);
15284 op <<= 12;
15285 Value |= op;
15286 // op: Rn
15287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15288 op &= UINT64_C(15);
15289 op <<= 16;
15290 Value |= op;
15291 // op: imm
15292 op = getModImmOpValue(MI, Op: 2, Fixups, ST: STI);
15293 op &= UINT64_C(4095);
15294 Value |= op;
15295 break;
15296 }
15297 case ARM::MVNsi: {
15298 // op: p
15299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15300 op &= UINT64_C(15);
15301 op <<= 28;
15302 Value |= op;
15303 // op: s
15304 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
15305 op &= UINT64_C(1);
15306 op <<= 20;
15307 Value |= op;
15308 // op: Rd
15309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15310 op &= UINT64_C(15);
15311 op <<= 12;
15312 Value |= op;
15313 // op: shift
15314 op = getSORegImmOpValue(MI, OpIdx: 1, Fixups, STI);
15315 Value |= (op & UINT64_C(4064));
15316 Value |= (op & UINT64_C(15));
15317 break;
15318 }
15319 case ARM::MOVsi: {
15320 // op: p
15321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15322 op &= UINT64_C(15);
15323 op <<= 28;
15324 Value |= op;
15325 // op: s
15326 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
15327 op &= UINT64_C(1);
15328 op <<= 20;
15329 Value |= op;
15330 // op: Rd
15331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15332 op &= UINT64_C(15);
15333 op <<= 12;
15334 Value |= op;
15335 // op: src
15336 op = getSORegImmOpValue(MI, OpIdx: 1, Fixups, STI);
15337 Value |= (op & UINT64_C(4064));
15338 Value |= (op & UINT64_C(15));
15339 break;
15340 }
15341 case ARM::MUL: {
15342 // op: p
15343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15344 op &= UINT64_C(15);
15345 op <<= 28;
15346 Value |= op;
15347 // op: s
15348 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
15349 op &= UINT64_C(1);
15350 op <<= 20;
15351 Value |= op;
15352 // op: Rd
15353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15354 op &= UINT64_C(15);
15355 op <<= 16;
15356 Value |= op;
15357 // op: Rm
15358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15359 op &= UINT64_C(15);
15360 op <<= 8;
15361 Value |= op;
15362 // op: Rn
15363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15364 op &= UINT64_C(15);
15365 Value |= op;
15366 break;
15367 }
15368 case ARM::VFMAD:
15369 case ARM::VFMSD:
15370 case ARM::VFNMAD:
15371 case ARM::VFNMSD:
15372 case ARM::VMLAD:
15373 case ARM::VMLSD:
15374 case ARM::VNMLAD:
15375 case ARM::VNMLSD: {
15376 // op: p
15377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15378 op &= UINT64_C(15);
15379 op <<= 28;
15380 Value |= op;
15381 // op: Dd
15382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15383 Value |= (op & UINT64_C(16)) << 18;
15384 Value |= (op & UINT64_C(15)) << 12;
15385 // op: Dn
15386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15387 Value |= (op & UINT64_C(15)) << 16;
15388 Value |= (op & UINT64_C(16)) << 3;
15389 // op: Dm
15390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15391 Value |= (op & UINT64_C(16)) << 1;
15392 Value |= (op & UINT64_C(15));
15393 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15394 break;
15395 }
15396 case ARM::SXTAB:
15397 case ARM::SXTAB16:
15398 case ARM::SXTAH:
15399 case ARM::UXTAB:
15400 case ARM::UXTAB16:
15401 case ARM::UXTAH: {
15402 // op: p
15403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15404 op &= UINT64_C(15);
15405 op <<= 28;
15406 Value |= op;
15407 // op: Rd
15408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15409 op &= UINT64_C(15);
15410 op <<= 12;
15411 Value |= op;
15412 // op: Rm
15413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15414 op &= UINT64_C(15);
15415 Value |= op;
15416 // op: Rn
15417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15418 op &= UINT64_C(15);
15419 op <<= 16;
15420 Value |= op;
15421 // op: rot
15422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15423 op &= UINT64_C(3);
15424 op <<= 10;
15425 Value |= op;
15426 break;
15427 }
15428 case ARM::SBFX:
15429 case ARM::UBFX: {
15430 // op: p
15431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15432 op &= UINT64_C(15);
15433 op <<= 28;
15434 Value |= op;
15435 // op: Rd
15436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15437 op &= UINT64_C(15);
15438 op <<= 12;
15439 Value |= op;
15440 // op: Rn
15441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15442 op &= UINT64_C(15);
15443 Value |= op;
15444 // op: lsb
15445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15446 op &= UINT64_C(31);
15447 op <<= 7;
15448 Value |= op;
15449 // op: width
15450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15451 op &= UINT64_C(31);
15452 op <<= 16;
15453 Value |= op;
15454 break;
15455 }
15456 case ARM::PKHBT:
15457 case ARM::PKHTB: {
15458 // op: p
15459 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15460 op &= UINT64_C(15);
15461 op <<= 28;
15462 Value |= op;
15463 // op: Rd
15464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15465 op &= UINT64_C(15);
15466 op <<= 12;
15467 Value |= op;
15468 // op: Rn
15469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15470 op &= UINT64_C(15);
15471 op <<= 16;
15472 Value |= op;
15473 // op: Rm
15474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15475 op &= UINT64_C(15);
15476 Value |= op;
15477 // op: sh
15478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15479 op &= UINT64_C(31);
15480 op <<= 7;
15481 Value |= op;
15482 break;
15483 }
15484 case ARM::BFI: {
15485 // op: p
15486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15487 op &= UINT64_C(15);
15488 op <<= 28;
15489 Value |= op;
15490 // op: Rd
15491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15492 op &= UINT64_C(15);
15493 op <<= 12;
15494 Value |= op;
15495 // op: Rn
15496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15497 op &= UINT64_C(15);
15498 Value |= op;
15499 // op: imm
15500 op = getBitfieldInvertedMaskOpValue(MI, Op: 3, Fixups, STI);
15501 Value |= (op & UINT64_C(992)) << 11;
15502 Value |= (op & UINT64_C(31)) << 7;
15503 break;
15504 }
15505 case ARM::SSAT:
15506 case ARM::USAT: {
15507 // op: p
15508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15509 op &= UINT64_C(15);
15510 op <<= 28;
15511 Value |= op;
15512 // op: Rd
15513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15514 op &= UINT64_C(15);
15515 op <<= 12;
15516 Value |= op;
15517 // op: sat_imm
15518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15519 op &= UINT64_C(31);
15520 op <<= 16;
15521 Value |= op;
15522 // op: Rn
15523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15524 op &= UINT64_C(15);
15525 Value |= op;
15526 // op: sh
15527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15528 Value |= (op & UINT64_C(31)) << 7;
15529 Value |= (op & UINT64_C(32)) << 1;
15530 break;
15531 }
15532 case ARM::MLS: {
15533 // op: p
15534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15535 op &= UINT64_C(15);
15536 op <<= 28;
15537 Value |= op;
15538 // op: Rd
15539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15540 op &= UINT64_C(15);
15541 op <<= 16;
15542 Value |= op;
15543 // op: Rm
15544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15545 op &= UINT64_C(15);
15546 op <<= 8;
15547 Value |= op;
15548 // op: Rn
15549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15550 op &= UINT64_C(15);
15551 Value |= op;
15552 // op: Ra
15553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15554 op &= UINT64_C(15);
15555 op <<= 12;
15556 Value |= op;
15557 break;
15558 }
15559 case ARM::SMMLA:
15560 case ARM::SMMLAR:
15561 case ARM::SMMLS:
15562 case ARM::SMMLSR:
15563 case ARM::USADA8: {
15564 // op: p
15565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15566 op &= UINT64_C(15);
15567 op <<= 28;
15568 Value |= op;
15569 // op: Rd
15570 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15571 op &= UINT64_C(15);
15572 op <<= 16;
15573 Value |= op;
15574 // op: Rn
15575 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15576 op &= UINT64_C(15);
15577 Value |= op;
15578 // op: Rm
15579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15580 op &= UINT64_C(15);
15581 op <<= 8;
15582 Value |= op;
15583 // op: Ra
15584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15585 op &= UINT64_C(15);
15586 op <<= 12;
15587 Value |= op;
15588 break;
15589 }
15590 case ARM::CMNzrsr:
15591 case ARM::CMPrsr:
15592 case ARM::TEQrsr:
15593 case ARM::TSTrsr: {
15594 // op: p
15595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15596 op &= UINT64_C(15);
15597 op <<= 28;
15598 Value |= op;
15599 // op: Rn
15600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15601 op &= UINT64_C(15);
15602 op <<= 16;
15603 Value |= op;
15604 // op: shift
15605 op = getSORegRegOpValue(MI, OpIdx: 1, Fixups, STI);
15606 Value |= (op & UINT64_C(3840));
15607 Value |= (op & UINT64_C(96));
15608 Value |= (op & UINT64_C(15));
15609 break;
15610 }
15611 case ARM::SMLAD:
15612 case ARM::SMLADX:
15613 case ARM::SMLSD:
15614 case ARM::SMLSDX: {
15615 // op: p
15616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15617 op &= UINT64_C(15);
15618 op <<= 28;
15619 Value |= op;
15620 // op: Rn
15621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15622 op &= UINT64_C(15);
15623 Value |= op;
15624 // op: Rm
15625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15626 op &= UINT64_C(15);
15627 op <<= 8;
15628 Value |= op;
15629 // op: Ra
15630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15631 op &= UINT64_C(15);
15632 op <<= 12;
15633 Value |= op;
15634 // op: Rd
15635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15636 op &= UINT64_C(15);
15637 op <<= 16;
15638 Value |= op;
15639 break;
15640 }
15641 case ARM::SMLABB:
15642 case ARM::SMLABT:
15643 case ARM::SMLATB:
15644 case ARM::SMLATT:
15645 case ARM::SMLAWB:
15646 case ARM::SMLAWT: {
15647 // op: p
15648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15649 op &= UINT64_C(15);
15650 op <<= 28;
15651 Value |= op;
15652 // op: Rn
15653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15654 op &= UINT64_C(15);
15655 Value |= op;
15656 // op: Rm
15657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15658 op &= UINT64_C(15);
15659 op <<= 8;
15660 Value |= op;
15661 // op: Rd
15662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15663 op &= UINT64_C(15);
15664 op <<= 16;
15665 Value |= op;
15666 // op: Ra
15667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15668 op &= UINT64_C(15);
15669 op <<= 12;
15670 Value |= op;
15671 break;
15672 }
15673 case ARM::LDRB_PRE_IMM:
15674 case ARM::LDR_PRE_IMM: {
15675 // op: p
15676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15677 op &= UINT64_C(15);
15678 op <<= 28;
15679 Value |= op;
15680 // op: Rt
15681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15682 op &= UINT64_C(15);
15683 op <<= 12;
15684 Value |= op;
15685 // op: addr
15686 op = getAddrModeImm12OpValue(MI, OpIdx: 2, Fixups, STI);
15687 Value |= (op & UINT64_C(4096)) << 11;
15688 Value |= (op & UINT64_C(122880)) << 3;
15689 Value |= (op & UINT64_C(4095));
15690 break;
15691 }
15692 case ARM::LDRBrs:
15693 case ARM::LDRrs:
15694 case ARM::STRBrs:
15695 case ARM::STRrs: {
15696 // op: p
15697 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15698 op &= UINT64_C(15);
15699 op <<= 28;
15700 Value |= op;
15701 // op: Rt
15702 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15703 op &= UINT64_C(15);
15704 op <<= 12;
15705 Value |= op;
15706 // op: shift
15707 op = getLdStSORegOpValue(MI, OpIdx: 1, Fixups, STI);
15708 Value |= (op & UINT64_C(4096)) << 11;
15709 Value |= (op & UINT64_C(122880)) << 3;
15710 Value |= (op & UINT64_C(4064));
15711 Value |= (op & UINT64_C(15));
15712 break;
15713 }
15714 case ARM::STRB_PRE_IMM:
15715 case ARM::STR_PRE_IMM: {
15716 // op: p
15717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15718 op &= UINT64_C(15);
15719 op <<= 28;
15720 Value |= op;
15721 // op: Rt
15722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15723 op &= UINT64_C(15);
15724 op <<= 12;
15725 Value |= op;
15726 // op: addr
15727 op = getAddrModeImm12OpValue(MI, OpIdx: 2, Fixups, STI);
15728 Value |= (op & UINT64_C(4096)) << 11;
15729 Value |= (op & UINT64_C(122880)) << 3;
15730 Value |= (op & UINT64_C(4095));
15731 break;
15732 }
15733 case ARM::VFMAH:
15734 case ARM::VFMAS:
15735 case ARM::VFMSH:
15736 case ARM::VFMSS:
15737 case ARM::VFNMAH:
15738 case ARM::VFNMAS:
15739 case ARM::VFNMSH:
15740 case ARM::VFNMSS:
15741 case ARM::VMLAH:
15742 case ARM::VMLAS:
15743 case ARM::VMLSH:
15744 case ARM::VMLSS:
15745 case ARM::VNMLAH:
15746 case ARM::VNMLAS:
15747 case ARM::VNMLSH:
15748 case ARM::VNMLSS: {
15749 // op: p
15750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15751 op &= UINT64_C(15);
15752 op <<= 28;
15753 Value |= op;
15754 // op: Sd
15755 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15756 Value |= (op & UINT64_C(1)) << 22;
15757 Value |= (op & UINT64_C(30)) << 11;
15758 // op: Sn
15759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15760 Value |= (op & UINT64_C(30)) << 15;
15761 Value |= (op & UINT64_C(1)) << 7;
15762 // op: Sm
15763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15764 Value |= (op & UINT64_C(1)) << 5;
15765 Value |= (op & UINT64_C(30)) >> 1;
15766 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15767 break;
15768 }
15769 case ARM::LDRH:
15770 case ARM::LDRSB:
15771 case ARM::LDRSH:
15772 case ARM::STRH: {
15773 // op: p
15774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15775 op &= UINT64_C(15);
15776 op <<= 28;
15777 Value |= op;
15778 // op: addr
15779 op = getAddrMode3OpValue(MI, OpIdx: 1, Fixups, STI);
15780 Value |= (op & UINT64_C(256)) << 15;
15781 Value |= (op & UINT64_C(8192)) << 9;
15782 Value |= (op & UINT64_C(7680)) << 7;
15783 Value |= (op & UINT64_C(240)) << 4;
15784 Value |= (op & UINT64_C(15));
15785 // op: Rt
15786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15787 op &= UINT64_C(15);
15788 op <<= 12;
15789 Value |= op;
15790 break;
15791 }
15792 case ARM::LDCL_OFFSET:
15793 case ARM::LDCL_PRE:
15794 case ARM::LDC_OFFSET:
15795 case ARM::LDC_PRE:
15796 case ARM::STCL_OFFSET:
15797 case ARM::STCL_PRE:
15798 case ARM::STC_OFFSET:
15799 case ARM::STC_PRE: {
15800 // op: p
15801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15802 op &= UINT64_C(15);
15803 op <<= 28;
15804 Value |= op;
15805 // op: addr
15806 op = getAddrMode5OpValue(MI, OpIdx: 2, Fixups, STI);
15807 Value |= (op & UINT64_C(256)) << 15;
15808 Value |= (op & UINT64_C(7680)) << 7;
15809 Value |= (op & UINT64_C(255));
15810 // op: cop
15811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15812 op &= UINT64_C(15);
15813 op <<= 8;
15814 Value |= op;
15815 // op: CRd
15816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15817 op &= UINT64_C(15);
15818 op <<= 12;
15819 Value |= op;
15820 break;
15821 }
15822 case ARM::LDRHTi:
15823 case ARM::LDRSBTi:
15824 case ARM::LDRSHTi: {
15825 // op: p
15826 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15827 op &= UINT64_C(15);
15828 op <<= 28;
15829 Value |= op;
15830 // op: addr
15831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15832 op &= UINT64_C(15);
15833 op <<= 16;
15834 Value |= op;
15835 // op: Rt
15836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15837 op &= UINT64_C(15);
15838 op <<= 12;
15839 Value |= op;
15840 // op: offset
15841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15842 Value |= (op & UINT64_C(256)) << 15;
15843 Value |= (op & UINT64_C(240)) << 4;
15844 Value |= (op & UINT64_C(15));
15845 break;
15846 }
15847 case ARM::STRHTi: {
15848 // op: p
15849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15850 op &= UINT64_C(15);
15851 op <<= 28;
15852 Value |= op;
15853 // op: addr
15854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15855 op &= UINT64_C(15);
15856 op <<= 16;
15857 Value |= op;
15858 // op: Rt
15859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15860 op &= UINT64_C(15);
15861 op <<= 12;
15862 Value |= op;
15863 // op: offset
15864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15865 Value |= (op & UINT64_C(256)) << 15;
15866 Value |= (op & UINT64_C(240)) << 4;
15867 Value |= (op & UINT64_C(15));
15868 break;
15869 }
15870 case ARM::VLDR_P0_pre:
15871 case ARM::VSTR_P0_pre: {
15872 // op: p
15873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15874 op &= UINT64_C(15);
15875 op <<= 28;
15876 Value |= op;
15877 // op: addr
15878 op = getT2AddrModeImm7s4OpValue(MI, OpIdx: 2, Fixups, STI);
15879 Value |= (op & UINT64_C(128)) << 16;
15880 Value |= (op & UINT64_C(3840)) << 8;
15881 Value |= (op & UINT64_C(127));
15882 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15883 break;
15884 }
15885 case ARM::VLDR_P0_post:
15886 case ARM::VSTR_P0_post: {
15887 // op: p
15888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15889 op &= UINT64_C(15);
15890 op <<= 28;
15891 Value |= op;
15892 // op: addr
15893 op = getT2ScaledImmOpValue<7,2>(MI, OpIdx: 3, Fixups, STI);
15894 Value |= (op & UINT64_C(128)) << 16;
15895 Value |= (op & UINT64_C(127));
15896 // op: Rn
15897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15898 op &= UINT64_C(15);
15899 op <<= 16;
15900 Value |= op;
15901 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15902 break;
15903 }
15904 case ARM::VMOVSRR: {
15905 // op: p
15906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15907 op &= UINT64_C(15);
15908 op <<= 28;
15909 Value |= op;
15910 // op: dst1
15911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15912 Value |= (op & UINT64_C(1)) << 5;
15913 Value |= (op & UINT64_C(30)) >> 1;
15914 // op: src1
15915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15916 op &= UINT64_C(15);
15917 op <<= 12;
15918 Value |= op;
15919 // op: src2
15920 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15921 op &= UINT64_C(15);
15922 op <<= 16;
15923 Value |= op;
15924 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
15925 break;
15926 }
15927 case ARM::LDCL_POST:
15928 case ARM::LDC_POST:
15929 case ARM::STCL_POST:
15930 case ARM::STC_POST: {
15931 // op: p
15932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15933 op &= UINT64_C(15);
15934 op <<= 28;
15935 Value |= op;
15936 // op: offset
15937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15938 Value |= (op & UINT64_C(256)) << 15;
15939 Value |= (op & UINT64_C(255));
15940 // op: addr
15941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15942 op &= UINT64_C(15);
15943 op <<= 16;
15944 Value |= op;
15945 // op: cop
15946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15947 op &= UINT64_C(15);
15948 op <<= 8;
15949 Value |= op;
15950 // op: CRd
15951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15952 op &= UINT64_C(15);
15953 op <<= 12;
15954 Value |= op;
15955 break;
15956 }
15957 case ARM::LDCL_OPTION:
15958 case ARM::LDC_OPTION:
15959 case ARM::STCL_OPTION:
15960 case ARM::STC_OPTION: {
15961 // op: p
15962 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15963 op &= UINT64_C(15);
15964 op <<= 28;
15965 Value |= op;
15966 // op: option
15967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15968 op &= UINT64_C(255);
15969 Value |= op;
15970 // op: addr
15971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15972 op &= UINT64_C(15);
15973 op <<= 16;
15974 Value |= op;
15975 // op: cop
15976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15977 op &= UINT64_C(15);
15978 op <<= 8;
15979 Value |= op;
15980 // op: CRd
15981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15982 op &= UINT64_C(15);
15983 op <<= 12;
15984 Value |= op;
15985 break;
15986 }
15987 case ARM::ADCrsi:
15988 case ARM::ADDrsi:
15989 case ARM::ANDrsi:
15990 case ARM::BICrsi:
15991 case ARM::EORrsi:
15992 case ARM::ORRrsi:
15993 case ARM::RSBrsi:
15994 case ARM::RSCrsi:
15995 case ARM::SBCrsi:
15996 case ARM::SUBrsi: {
15997 // op: p
15998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15999 op &= UINT64_C(15);
16000 op <<= 28;
16001 Value |= op;
16002 // op: s
16003 op = getCCOutOpValue(MI, Op: 6, Fixups, STI);
16004 op &= UINT64_C(1);
16005 op <<= 20;
16006 Value |= op;
16007 // op: Rd
16008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16009 op &= UINT64_C(15);
16010 op <<= 12;
16011 Value |= op;
16012 // op: Rn
16013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16014 op &= UINT64_C(15);
16015 op <<= 16;
16016 Value |= op;
16017 // op: shift
16018 op = getSORegImmOpValue(MI, OpIdx: 2, Fixups, STI);
16019 Value |= (op & UINT64_C(4064));
16020 Value |= (op & UINT64_C(15));
16021 break;
16022 }
16023 case ARM::MVNsr: {
16024 // op: p
16025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16026 op &= UINT64_C(15);
16027 op <<= 28;
16028 Value |= op;
16029 // op: s
16030 op = getCCOutOpValue(MI, Op: 6, Fixups, STI);
16031 op &= UINT64_C(1);
16032 op <<= 20;
16033 Value |= op;
16034 // op: Rd
16035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16036 op &= UINT64_C(15);
16037 op <<= 12;
16038 Value |= op;
16039 // op: shift
16040 op = getSORegRegOpValue(MI, OpIdx: 1, Fixups, STI);
16041 Value |= (op & UINT64_C(3840));
16042 Value |= (op & UINT64_C(96));
16043 Value |= (op & UINT64_C(15));
16044 break;
16045 }
16046 case ARM::MOVsr: {
16047 // op: p
16048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16049 op &= UINT64_C(15);
16050 op <<= 28;
16051 Value |= op;
16052 // op: s
16053 op = getCCOutOpValue(MI, Op: 6, Fixups, STI);
16054 op &= UINT64_C(1);
16055 op <<= 20;
16056 Value |= op;
16057 // op: Rd
16058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16059 op &= UINT64_C(15);
16060 op <<= 12;
16061 Value |= op;
16062 // op: src
16063 op = getSORegRegOpValue(MI, OpIdx: 1, Fixups, STI);
16064 Value |= (op & UINT64_C(3840));
16065 Value |= (op & UINT64_C(96));
16066 Value |= (op & UINT64_C(15));
16067 break;
16068 }
16069 case ARM::MLA: {
16070 // op: p
16071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16072 op &= UINT64_C(15);
16073 op <<= 28;
16074 Value |= op;
16075 // op: s
16076 op = getCCOutOpValue(MI, Op: 6, Fixups, STI);
16077 op &= UINT64_C(1);
16078 op <<= 20;
16079 Value |= op;
16080 // op: Rd
16081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16082 op &= UINT64_C(15);
16083 op <<= 16;
16084 Value |= op;
16085 // op: Rm
16086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16087 op &= UINT64_C(15);
16088 op <<= 8;
16089 Value |= op;
16090 // op: Rn
16091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16092 op &= UINT64_C(15);
16093 Value |= op;
16094 // op: Ra
16095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16096 op &= UINT64_C(15);
16097 op <<= 12;
16098 Value |= op;
16099 break;
16100 }
16101 case ARM::SMULL:
16102 case ARM::UMULL: {
16103 // op: p
16104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16105 op &= UINT64_C(15);
16106 op <<= 28;
16107 Value |= op;
16108 // op: s
16109 op = getCCOutOpValue(MI, Op: 6, Fixups, STI);
16110 op &= UINT64_C(1);
16111 op <<= 20;
16112 Value |= op;
16113 // op: RdLo
16114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16115 op &= UINT64_C(15);
16116 op <<= 12;
16117 Value |= op;
16118 // op: RdHi
16119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16120 op &= UINT64_C(15);
16121 op <<= 16;
16122 Value |= op;
16123 // op: Rm
16124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16125 op &= UINT64_C(15);
16126 op <<= 8;
16127 Value |= op;
16128 // op: Rn
16129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16130 op &= UINT64_C(15);
16131 Value |= op;
16132 break;
16133 }
16134 case ARM::VMOVRRS: {
16135 // op: p
16136 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16137 op &= UINT64_C(15);
16138 op <<= 28;
16139 Value |= op;
16140 // op: src1
16141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16142 Value |= (op & UINT64_C(1)) << 5;
16143 Value |= (op & UINT64_C(30)) >> 1;
16144 // op: Rt
16145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16146 op &= UINT64_C(15);
16147 op <<= 12;
16148 Value |= op;
16149 // op: Rt2
16150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16151 op &= UINT64_C(15);
16152 op <<= 16;
16153 Value |= op;
16154 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
16155 break;
16156 }
16157 case ARM::MRRC: {
16158 // op: p
16159 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16160 op &= UINT64_C(15);
16161 op <<= 28;
16162 Value |= op;
16163 // op: Rt
16164 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16165 op &= UINT64_C(15);
16166 op <<= 12;
16167 Value |= op;
16168 // op: Rt2
16169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16170 op &= UINT64_C(15);
16171 op <<= 16;
16172 Value |= op;
16173 // op: cop
16174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16175 op &= UINT64_C(15);
16176 op <<= 8;
16177 Value |= op;
16178 // op: opc1
16179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16180 op &= UINT64_C(15);
16181 op <<= 4;
16182 Value |= op;
16183 // op: CRm
16184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16185 op &= UINT64_C(15);
16186 Value |= op;
16187 break;
16188 }
16189 case ARM::LDRH_PRE:
16190 case ARM::LDRSB_PRE:
16191 case ARM::LDRSH_PRE: {
16192 // op: p
16193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16194 op &= UINT64_C(15);
16195 op <<= 28;
16196 Value |= op;
16197 // op: Rt
16198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16199 op &= UINT64_C(15);
16200 op <<= 12;
16201 Value |= op;
16202 // op: addr
16203 op = getAddrMode3OpValue(MI, OpIdx: 2, Fixups, STI);
16204 Value |= (op & UINT64_C(256)) << 15;
16205 Value |= (op & UINT64_C(8192)) << 9;
16206 Value |= (op & UINT64_C(7680)) << 7;
16207 Value |= (op & UINT64_C(240)) << 4;
16208 Value |= (op & UINT64_C(15));
16209 break;
16210 }
16211 case ARM::LDRB_PRE_REG:
16212 case ARM::LDR_PRE_REG: {
16213 // op: p
16214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16215 op &= UINT64_C(15);
16216 op <<= 28;
16217 Value |= op;
16218 // op: Rt
16219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16220 op &= UINT64_C(15);
16221 op <<= 12;
16222 Value |= op;
16223 // op: addr
16224 op = getLdStSORegOpValue(MI, OpIdx: 2, Fixups, STI);
16225 Value |= (op & UINT64_C(4096)) << 11;
16226 Value |= (op & UINT64_C(122880)) << 3;
16227 Value |= (op & UINT64_C(4064));
16228 Value |= (op & UINT64_C(15));
16229 break;
16230 }
16231 case ARM::LDRBT_POST_REG:
16232 case ARM::LDRB_POST_REG:
16233 case ARM::LDRT_POST_REG:
16234 case ARM::LDR_POST_REG: {
16235 // op: p
16236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16237 op &= UINT64_C(15);
16238 op <<= 28;
16239 Value |= op;
16240 // op: Rt
16241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16242 op &= UINT64_C(15);
16243 op <<= 12;
16244 Value |= op;
16245 // op: offset
16246 op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI);
16247 Value |= (op & UINT64_C(4096)) << 11;
16248 Value |= (op & UINT64_C(4064));
16249 Value |= (op & UINT64_C(15));
16250 // op: addr
16251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16252 op &= UINT64_C(15);
16253 op <<= 16;
16254 Value |= op;
16255 break;
16256 }
16257 case ARM::LDRBT_POST_IMM:
16258 case ARM::LDRB_POST_IMM:
16259 case ARM::LDRT_POST_IMM:
16260 case ARM::LDR_POST_IMM: {
16261 // op: p
16262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16263 op &= UINT64_C(15);
16264 op <<= 28;
16265 Value |= op;
16266 // op: Rt
16267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16268 op &= UINT64_C(15);
16269 op <<= 12;
16270 Value |= op;
16271 // op: offset
16272 op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI);
16273 Value |= (op & UINT64_C(4096)) << 11;
16274 Value |= (op & UINT64_C(4095));
16275 // op: addr
16276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16277 op &= UINT64_C(15);
16278 op <<= 16;
16279 Value |= op;
16280 break;
16281 }
16282 case ARM::LDRH_POST:
16283 case ARM::LDRSB_POST:
16284 case ARM::LDRSH_POST: {
16285 // op: p
16286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16287 op &= UINT64_C(15);
16288 op <<= 28;
16289 Value |= op;
16290 // op: Rt
16291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16292 op &= UINT64_C(15);
16293 op <<= 12;
16294 Value |= op;
16295 // op: offset
16296 op = getAddrMode3OffsetOpValue(MI, OpIdx: 3, Fixups, STI);
16297 Value |= (op & UINT64_C(256)) << 15;
16298 Value |= (op & UINT64_C(512)) << 13;
16299 Value |= (op & UINT64_C(240)) << 4;
16300 Value |= (op & UINT64_C(15));
16301 // op: addr
16302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16303 op &= UINT64_C(15);
16304 op <<= 16;
16305 Value |= op;
16306 break;
16307 }
16308 case ARM::STRH_PRE: {
16309 // op: p
16310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16311 op &= UINT64_C(15);
16312 op <<= 28;
16313 Value |= op;
16314 // op: Rt
16315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16316 op &= UINT64_C(15);
16317 op <<= 12;
16318 Value |= op;
16319 // op: addr
16320 op = getAddrMode3OpValue(MI, OpIdx: 2, Fixups, STI);
16321 Value |= (op & UINT64_C(256)) << 15;
16322 Value |= (op & UINT64_C(8192)) << 9;
16323 Value |= (op & UINT64_C(7680)) << 7;
16324 Value |= (op & UINT64_C(240)) << 4;
16325 Value |= (op & UINT64_C(15));
16326 break;
16327 }
16328 case ARM::STRB_PRE_REG:
16329 case ARM::STR_PRE_REG: {
16330 // op: p
16331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16332 op &= UINT64_C(15);
16333 op <<= 28;
16334 Value |= op;
16335 // op: Rt
16336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16337 op &= UINT64_C(15);
16338 op <<= 12;
16339 Value |= op;
16340 // op: addr
16341 op = getLdStSORegOpValue(MI, OpIdx: 2, Fixups, STI);
16342 Value |= (op & UINT64_C(4096)) << 11;
16343 Value |= (op & UINT64_C(122880)) << 3;
16344 Value |= (op & UINT64_C(4064));
16345 Value |= (op & UINT64_C(15));
16346 break;
16347 }
16348 case ARM::STRBT_POST_REG:
16349 case ARM::STRB_POST_REG:
16350 case ARM::STRT_POST_REG:
16351 case ARM::STR_POST_REG: {
16352 // op: p
16353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16354 op &= UINT64_C(15);
16355 op <<= 28;
16356 Value |= op;
16357 // op: Rt
16358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16359 op &= UINT64_C(15);
16360 op <<= 12;
16361 Value |= op;
16362 // op: offset
16363 op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI);
16364 Value |= (op & UINT64_C(4096)) << 11;
16365 Value |= (op & UINT64_C(4064));
16366 Value |= (op & UINT64_C(15));
16367 // op: addr
16368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16369 op &= UINT64_C(15);
16370 op <<= 16;
16371 Value |= op;
16372 break;
16373 }
16374 case ARM::STRBT_POST_IMM:
16375 case ARM::STRB_POST_IMM:
16376 case ARM::STRT_POST_IMM:
16377 case ARM::STR_POST_IMM: {
16378 // op: p
16379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16380 op &= UINT64_C(15);
16381 op <<= 28;
16382 Value |= op;
16383 // op: Rt
16384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16385 op &= UINT64_C(15);
16386 op <<= 12;
16387 Value |= op;
16388 // op: offset
16389 op = getAddrMode2OffsetOpValue(MI, OpIdx: 3, Fixups, STI);
16390 Value |= (op & UINT64_C(4096)) << 11;
16391 Value |= (op & UINT64_C(4095));
16392 // op: addr
16393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16394 op &= UINT64_C(15);
16395 op <<= 16;
16396 Value |= op;
16397 break;
16398 }
16399 case ARM::STRH_POST: {
16400 // op: p
16401 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16402 op &= UINT64_C(15);
16403 op <<= 28;
16404 Value |= op;
16405 // op: Rt
16406 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16407 op &= UINT64_C(15);
16408 op <<= 12;
16409 Value |= op;
16410 // op: offset
16411 op = getAddrMode3OffsetOpValue(MI, OpIdx: 3, Fixups, STI);
16412 Value |= (op & UINT64_C(256)) << 15;
16413 Value |= (op & UINT64_C(512)) << 13;
16414 Value |= (op & UINT64_C(240)) << 4;
16415 Value |= (op & UINT64_C(15));
16416 // op: addr
16417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16418 op &= UINT64_C(15);
16419 op <<= 16;
16420 Value |= op;
16421 break;
16422 }
16423 case ARM::MCRR: {
16424 // op: p
16425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16426 op &= UINT64_C(15);
16427 op <<= 28;
16428 Value |= op;
16429 // op: Rt
16430 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16431 op &= UINT64_C(15);
16432 op <<= 12;
16433 Value |= op;
16434 // op: Rt2
16435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16436 op &= UINT64_C(15);
16437 op <<= 16;
16438 Value |= op;
16439 // op: cop
16440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16441 op &= UINT64_C(15);
16442 op <<= 8;
16443 Value |= op;
16444 // op: opc1
16445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16446 op &= UINT64_C(15);
16447 op <<= 4;
16448 Value |= op;
16449 // op: CRm
16450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16451 op &= UINT64_C(15);
16452 Value |= op;
16453 break;
16454 }
16455 case ARM::LDRD:
16456 case ARM::STRD: {
16457 // op: p
16458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16459 op &= UINT64_C(15);
16460 op <<= 28;
16461 Value |= op;
16462 // op: addr
16463 op = getAddrMode3OpValue(MI, OpIdx: 2, Fixups, STI);
16464 Value |= (op & UINT64_C(256)) << 15;
16465 Value |= (op & UINT64_C(8192)) << 9;
16466 Value |= (op & UINT64_C(7680)) << 7;
16467 Value |= (op & UINT64_C(240)) << 4;
16468 Value |= (op & UINT64_C(15));
16469 // op: Rt
16470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16471 op &= UINT64_C(15);
16472 op <<= 12;
16473 Value |= op;
16474 break;
16475 }
16476 case ARM::LDRHTr:
16477 case ARM::LDRSBTr:
16478 case ARM::LDRSHTr: {
16479 // op: p
16480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16481 op &= UINT64_C(15);
16482 op <<= 28;
16483 Value |= op;
16484 // op: addr
16485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16486 op &= UINT64_C(15);
16487 op <<= 16;
16488 Value |= op;
16489 // op: Rt
16490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16491 op &= UINT64_C(15);
16492 op <<= 12;
16493 Value |= op;
16494 // op: Rm
16495 op = getPostIdxRegOpValue(MI, OpIdx: 3, Fixups, STI);
16496 Value |= (op & UINT64_C(16)) << 19;
16497 Value |= (op & UINT64_C(15));
16498 break;
16499 }
16500 case ARM::STRHTr: {
16501 // op: p
16502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16503 op &= UINT64_C(15);
16504 op <<= 28;
16505 Value |= op;
16506 // op: addr
16507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16508 op &= UINT64_C(15);
16509 op <<= 16;
16510 Value |= op;
16511 // op: Rt
16512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16513 op &= UINT64_C(15);
16514 op <<= 12;
16515 Value |= op;
16516 // op: Rm
16517 op = getPostIdxRegOpValue(MI, OpIdx: 3, Fixups, STI);
16518 Value |= (op & UINT64_C(16)) << 19;
16519 Value |= (op & UINT64_C(15));
16520 break;
16521 }
16522 case ARM::ADCrsr:
16523 case ARM::ADDrsr:
16524 case ARM::ANDrsr:
16525 case ARM::BICrsr:
16526 case ARM::EORrsr:
16527 case ARM::ORRrsr:
16528 case ARM::RSBrsr:
16529 case ARM::RSCrsr:
16530 case ARM::SBCrsr:
16531 case ARM::SUBrsr: {
16532 // op: p
16533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16534 op &= UINT64_C(15);
16535 op <<= 28;
16536 Value |= op;
16537 // op: s
16538 op = getCCOutOpValue(MI, Op: 7, Fixups, STI);
16539 op &= UINT64_C(1);
16540 op <<= 20;
16541 Value |= op;
16542 // op: Rd
16543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16544 op &= UINT64_C(15);
16545 op <<= 12;
16546 Value |= op;
16547 // op: Rn
16548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16549 op &= UINT64_C(15);
16550 op <<= 16;
16551 Value |= op;
16552 // op: shift
16553 op = getSORegRegOpValue(MI, OpIdx: 2, Fixups, STI);
16554 Value |= (op & UINT64_C(3840));
16555 Value |= (op & UINT64_C(96));
16556 Value |= (op & UINT64_C(15));
16557 break;
16558 }
16559 case ARM::UMAAL: {
16560 // op: p
16561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16562 op &= UINT64_C(15);
16563 op <<= 28;
16564 Value |= op;
16565 // op: RdLo
16566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16567 op &= UINT64_C(15);
16568 op <<= 12;
16569 Value |= op;
16570 // op: RdHi
16571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16572 op &= UINT64_C(15);
16573 op <<= 16;
16574 Value |= op;
16575 // op: Rm
16576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16577 op &= UINT64_C(15);
16578 op <<= 8;
16579 Value |= op;
16580 // op: Rn
16581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16582 op &= UINT64_C(15);
16583 Value |= op;
16584 break;
16585 }
16586 case ARM::SMLALBB:
16587 case ARM::SMLALBT:
16588 case ARM::SMLALD:
16589 case ARM::SMLALDX:
16590 case ARM::SMLALTB:
16591 case ARM::SMLALTT:
16592 case ARM::SMLSLD:
16593 case ARM::SMLSLDX: {
16594 // op: p
16595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16596 op &= UINT64_C(15);
16597 op <<= 28;
16598 Value |= op;
16599 // op: Rn
16600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16601 op &= UINT64_C(15);
16602 Value |= op;
16603 // op: Rm
16604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16605 op &= UINT64_C(15);
16606 op <<= 8;
16607 Value |= op;
16608 // op: RdLo
16609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16610 op &= UINT64_C(15);
16611 op <<= 12;
16612 Value |= op;
16613 // op: RdHi
16614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16615 op &= UINT64_C(15);
16616 op <<= 16;
16617 Value |= op;
16618 break;
16619 }
16620 case ARM::LDRD_PRE: {
16621 // op: p
16622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16623 op &= UINT64_C(15);
16624 op <<= 28;
16625 Value |= op;
16626 // op: Rt
16627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16628 op &= UINT64_C(15);
16629 op <<= 12;
16630 Value |= op;
16631 // op: addr
16632 op = getAddrMode3OpValue(MI, OpIdx: 3, Fixups, STI);
16633 Value |= (op & UINT64_C(256)) << 15;
16634 Value |= (op & UINT64_C(8192)) << 9;
16635 Value |= (op & UINT64_C(7680)) << 7;
16636 Value |= (op & UINT64_C(240)) << 4;
16637 Value |= (op & UINT64_C(15));
16638 break;
16639 }
16640 case ARM::MRC: {
16641 // op: p
16642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16643 op &= UINT64_C(15);
16644 op <<= 28;
16645 Value |= op;
16646 // op: Rt
16647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16648 op &= UINT64_C(15);
16649 op <<= 12;
16650 Value |= op;
16651 // op: cop
16652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16653 op &= UINT64_C(15);
16654 op <<= 8;
16655 Value |= op;
16656 // op: opc1
16657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16658 op &= UINT64_C(7);
16659 op <<= 21;
16660 Value |= op;
16661 // op: opc2
16662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16663 op &= UINT64_C(7);
16664 op <<= 5;
16665 Value |= op;
16666 // op: CRm
16667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16668 op &= UINT64_C(15);
16669 Value |= op;
16670 // op: CRn
16671 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16672 op &= UINT64_C(15);
16673 op <<= 16;
16674 Value |= op;
16675 break;
16676 }
16677 case ARM::LDRD_POST: {
16678 // op: p
16679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16680 op &= UINT64_C(15);
16681 op <<= 28;
16682 Value |= op;
16683 // op: Rt
16684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16685 op &= UINT64_C(15);
16686 op <<= 12;
16687 Value |= op;
16688 // op: offset
16689 op = getAddrMode3OffsetOpValue(MI, OpIdx: 4, Fixups, STI);
16690 Value |= (op & UINT64_C(256)) << 15;
16691 Value |= (op & UINT64_C(512)) << 13;
16692 Value |= (op & UINT64_C(240)) << 4;
16693 Value |= (op & UINT64_C(15));
16694 // op: addr
16695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16696 op &= UINT64_C(15);
16697 op <<= 16;
16698 Value |= op;
16699 break;
16700 }
16701 case ARM::STRD_PRE: {
16702 // op: p
16703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16704 op &= UINT64_C(15);
16705 op <<= 28;
16706 Value |= op;
16707 // op: Rt
16708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16709 op &= UINT64_C(15);
16710 op <<= 12;
16711 Value |= op;
16712 // op: addr
16713 op = getAddrMode3OpValue(MI, OpIdx: 3, Fixups, STI);
16714 Value |= (op & UINT64_C(256)) << 15;
16715 Value |= (op & UINT64_C(8192)) << 9;
16716 Value |= (op & UINT64_C(7680)) << 7;
16717 Value |= (op & UINT64_C(240)) << 4;
16718 Value |= (op & UINT64_C(15));
16719 break;
16720 }
16721 case ARM::STRD_POST: {
16722 // op: p
16723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16724 op &= UINT64_C(15);
16725 op <<= 28;
16726 Value |= op;
16727 // op: Rt
16728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16729 op &= UINT64_C(15);
16730 op <<= 12;
16731 Value |= op;
16732 // op: offset
16733 op = getAddrMode3OffsetOpValue(MI, OpIdx: 4, Fixups, STI);
16734 Value |= (op & UINT64_C(256)) << 15;
16735 Value |= (op & UINT64_C(512)) << 13;
16736 Value |= (op & UINT64_C(240)) << 4;
16737 Value |= (op & UINT64_C(15));
16738 // op: addr
16739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16740 op &= UINT64_C(15);
16741 op <<= 16;
16742 Value |= op;
16743 break;
16744 }
16745 case ARM::MCR: {
16746 // op: p
16747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16748 op &= UINT64_C(15);
16749 op <<= 28;
16750 Value |= op;
16751 // op: Rt
16752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16753 op &= UINT64_C(15);
16754 op <<= 12;
16755 Value |= op;
16756 // op: cop
16757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16758 op &= UINT64_C(15);
16759 op <<= 8;
16760 Value |= op;
16761 // op: opc1
16762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16763 op &= UINT64_C(7);
16764 op <<= 21;
16765 Value |= op;
16766 // op: opc2
16767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16768 op &= UINT64_C(7);
16769 op <<= 5;
16770 Value |= op;
16771 // op: CRm
16772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16773 op &= UINT64_C(15);
16774 Value |= op;
16775 // op: CRn
16776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16777 op &= UINT64_C(15);
16778 op <<= 16;
16779 Value |= op;
16780 break;
16781 }
16782 case ARM::CDP: {
16783 // op: p
16784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16785 op &= UINT64_C(15);
16786 op <<= 28;
16787 Value |= op;
16788 // op: opc1
16789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16790 op &= UINT64_C(15);
16791 op <<= 20;
16792 Value |= op;
16793 // op: CRn
16794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16795 op &= UINT64_C(15);
16796 op <<= 16;
16797 Value |= op;
16798 // op: CRd
16799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16800 op &= UINT64_C(15);
16801 op <<= 12;
16802 Value |= op;
16803 // op: cop
16804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16805 op &= UINT64_C(15);
16806 op <<= 8;
16807 Value |= op;
16808 // op: opc2
16809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16810 op &= UINT64_C(7);
16811 op <<= 5;
16812 Value |= op;
16813 // op: CRm
16814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16815 op &= UINT64_C(15);
16816 Value |= op;
16817 break;
16818 }
16819 case ARM::SMLAL:
16820 case ARM::UMLAL: {
16821 // op: p
16822 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
16823 op &= UINT64_C(15);
16824 op <<= 28;
16825 Value |= op;
16826 // op: s
16827 op = getCCOutOpValue(MI, Op: 8, Fixups, STI);
16828 op &= UINT64_C(1);
16829 op <<= 20;
16830 Value |= op;
16831 // op: RdLo
16832 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16833 op &= UINT64_C(15);
16834 op <<= 12;
16835 Value |= op;
16836 // op: RdHi
16837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16838 op &= UINT64_C(15);
16839 op <<= 16;
16840 Value |= op;
16841 // op: Rm
16842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16843 op &= UINT64_C(15);
16844 op <<= 8;
16845 Value |= op;
16846 // op: Rn
16847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16848 op &= UINT64_C(15);
16849 Value |= op;
16850 break;
16851 }
16852 case ARM::tPUSH: {
16853 // op: regs
16854 op = getRegisterListOpValue(MI, Op: 2, Fixups, STI);
16855 Value |= (op & UINT64_C(16384)) >> 6;
16856 Value |= (op & UINT64_C(255));
16857 break;
16858 }
16859 case ARM::VSCCLRMS: {
16860 // op: regs
16861 op = getRegisterListOpValue(MI, Op: 2, Fixups, STI);
16862 Value |= (op & UINT64_C(256)) << 14;
16863 Value |= (op & UINT64_C(7680)) << 3;
16864 Value |= (op & UINT64_C(255));
16865 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
16866 break;
16867 }
16868 case ARM::tPOP: {
16869 // op: regs
16870 op = getRegisterListOpValue(MI, Op: 2, Fixups, STI);
16871 Value |= (op & UINT64_C(32768)) >> 7;
16872 Value |= (op & UINT64_C(255));
16873 break;
16874 }
16875 case ARM::VSCCLRMD: {
16876 // op: regs
16877 op = getRegisterListOpValue(MI, Op: 2, Fixups, STI);
16878 Value |= (op & UINT64_C(4096)) << 10;
16879 Value |= (op & UINT64_C(3840)) << 4;
16880 Value |= (op & UINT64_C(254));
16881 Value = VFPThumb2PostEncoder(MI, EncodedValue: Value, STI);
16882 break;
16883 }
16884 case ARM::t2CLRM: {
16885 // op: regs
16886 op = getRegisterListOpValue(MI, Op: 2, Fixups, STI);
16887 Value |= (op & UINT64_C(49152));
16888 Value |= (op & UINT64_C(8191));
16889 break;
16890 }
16891 case ARM::t2MOVr:
16892 case ARM::t2MVNr:
16893 case ARM::t2RRX: {
16894 // op: s
16895 op = getCCOutOpValue(MI, Op: 4, Fixups, STI);
16896 op &= UINT64_C(1);
16897 op <<= 20;
16898 Value |= op;
16899 // op: Rd
16900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16901 op &= UINT64_C(15);
16902 op <<= 8;
16903 Value |= op;
16904 // op: Rm
16905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16906 op &= UINT64_C(15);
16907 Value |= op;
16908 break;
16909 }
16910 case ARM::t2MOVi:
16911 case ARM::t2MVNi: {
16912 // op: s
16913 op = getCCOutOpValue(MI, Op: 4, Fixups, STI);
16914 op &= UINT64_C(1);
16915 op <<= 20;
16916 Value |= op;
16917 // op: Rd
16918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16919 op &= UINT64_C(15);
16920 op <<= 8;
16921 Value |= op;
16922 // op: imm
16923 op = getT2SOImmOpValue(MI, Op: 1, Fixups, STI);
16924 Value |= (op & UINT64_C(2048)) << 15;
16925 Value |= (op & UINT64_C(1792)) << 4;
16926 Value |= (op & UINT64_C(255));
16927 break;
16928 }
16929 case ARM::t2ASRri:
16930 case ARM::t2LSLri:
16931 case ARM::t2LSRri:
16932 case ARM::t2RORri: {
16933 // op: s
16934 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
16935 op &= UINT64_C(1);
16936 op <<= 20;
16937 Value |= op;
16938 // op: Rd
16939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16940 op &= UINT64_C(15);
16941 op <<= 8;
16942 Value |= op;
16943 // op: Rm
16944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16945 op &= UINT64_C(15);
16946 Value |= op;
16947 // op: imm
16948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16949 Value |= (op & UINT64_C(28)) << 10;
16950 Value |= (op & UINT64_C(3)) << 6;
16951 break;
16952 }
16953 case ARM::t2ADCrr:
16954 case ARM::t2ADDrr:
16955 case ARM::t2ANDrr:
16956 case ARM::t2ASRrr:
16957 case ARM::t2BICrr:
16958 case ARM::t2EORrr:
16959 case ARM::t2LSLrr:
16960 case ARM::t2LSRrr:
16961 case ARM::t2ORNrr:
16962 case ARM::t2ORRrr:
16963 case ARM::t2RORrr:
16964 case ARM::t2RSBrr:
16965 case ARM::t2SBCrr:
16966 case ARM::t2SUBrr: {
16967 // op: s
16968 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
16969 op &= UINT64_C(1);
16970 op <<= 20;
16971 Value |= op;
16972 // op: Rd
16973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16974 op &= UINT64_C(15);
16975 op <<= 8;
16976 Value |= op;
16977 // op: Rn
16978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16979 op &= UINT64_C(15);
16980 op <<= 16;
16981 Value |= op;
16982 // op: Rm
16983 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16984 op &= UINT64_C(15);
16985 Value |= op;
16986 break;
16987 }
16988 case ARM::t2ADCri:
16989 case ARM::t2ADDri:
16990 case ARM::t2ANDri:
16991 case ARM::t2BICri:
16992 case ARM::t2EORri:
16993 case ARM::t2ORNri:
16994 case ARM::t2ORRri:
16995 case ARM::t2RSBri:
16996 case ARM::t2SBCri:
16997 case ARM::t2SUBri: {
16998 // op: s
16999 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
17000 op &= UINT64_C(1);
17001 op <<= 20;
17002 Value |= op;
17003 // op: Rd
17004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17005 op &= UINT64_C(15);
17006 op <<= 8;
17007 Value |= op;
17008 // op: Rn
17009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17010 op &= UINT64_C(15);
17011 op <<= 16;
17012 Value |= op;
17013 // op: imm
17014 op = getT2SOImmOpValue(MI, Op: 2, Fixups, STI);
17015 Value |= (op & UINT64_C(2048)) << 15;
17016 Value |= (op & UINT64_C(1792)) << 4;
17017 Value |= (op & UINT64_C(255));
17018 break;
17019 }
17020 case ARM::t2MVNs: {
17021 // op: s
17022 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
17023 op &= UINT64_C(1);
17024 op <<= 20;
17025 Value |= op;
17026 // op: Rd
17027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17028 op &= UINT64_C(15);
17029 op <<= 8;
17030 Value |= op;
17031 // op: ShiftedRm
17032 op = getT2SORegOpValue(MI, OpIdx: 1, Fixups, STI);
17033 Value |= (op & UINT64_C(3584)) << 3;
17034 Value |= (op & UINT64_C(480)) >> 1;
17035 Value |= (op & UINT64_C(15));
17036 break;
17037 }
17038 case ARM::t2ADDspImm:
17039 case ARM::t2SUBspImm: {
17040 // op: s
17041 op = getCCOutOpValue(MI, Op: 5, Fixups, STI);
17042 op &= UINT64_C(1);
17043 op <<= 20;
17044 Value |= op;
17045 // op: imm
17046 op = getT2SOImmOpValue(MI, Op: 2, Fixups, STI);
17047 Value |= (op & UINT64_C(2048)) << 15;
17048 Value |= (op & UINT64_C(1792)) << 4;
17049 Value |= (op & UINT64_C(255));
17050 break;
17051 }
17052 case ARM::t2ADCrs:
17053 case ARM::t2ADDrs:
17054 case ARM::t2ANDrs:
17055 case ARM::t2BICrs:
17056 case ARM::t2EORrs:
17057 case ARM::t2ORNrs:
17058 case ARM::t2ORRrs:
17059 case ARM::t2RSBrs:
17060 case ARM::t2SBCrs:
17061 case ARM::t2SUBrs: {
17062 // op: s
17063 op = getCCOutOpValue(MI, Op: 6, Fixups, STI);
17064 op &= UINT64_C(1);
17065 op <<= 20;
17066 Value |= op;
17067 // op: Rd
17068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17069 op &= UINT64_C(15);
17070 op <<= 8;
17071 Value |= op;
17072 // op: Rn
17073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17074 op &= UINT64_C(15);
17075 op <<= 16;
17076 Value |= op;
17077 // op: ShiftedRm
17078 op = getT2SORegOpValue(MI, OpIdx: 2, Fixups, STI);
17079 Value |= (op & UINT64_C(3584)) << 3;
17080 Value |= (op & UINT64_C(480)) >> 1;
17081 Value |= (op & UINT64_C(15));
17082 break;
17083 }
17084 case ARM::PLDWrs:
17085 case ARM::PLDrs:
17086 case ARM::PLIrs: {
17087 // op: shift
17088 op = getLdStSORegOpValue(MI, OpIdx: 0, Fixups, STI);
17089 Value |= (op & UINT64_C(4096)) << 11;
17090 Value |= (op & UINT64_C(122880)) << 3;
17091 Value |= (op & UINT64_C(4064));
17092 Value |= (op & UINT64_C(15));
17093 break;
17094 }
17095 case ARM::BLXi: {
17096 // op: target
17097 op = getARMBLXTargetOpValue(MI, OpIdx: 0, Fixups, STI);
17098 Value |= (op & UINT64_C(1)) << 24;
17099 Value |= (op & UINT64_C(33554430)) >> 1;
17100 break;
17101 }
17102 case ARM::tB: {
17103 // op: target
17104 op = getThumbBRTargetOpValue(MI, OpIdx: 0, Fixups, STI);
17105 op &= UINT64_C(2047);
17106 Value |= op;
17107 break;
17108 }
17109 case ARM::t2B: {
17110 // op: target
17111 op = getThumbBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI);
17112 Value |= (op & UINT64_C(8388608)) << 3;
17113 Value |= (op & UINT64_C(2095104)) << 5;
17114 Value |= (op & UINT64_C(4194304)) >> 9;
17115 Value |= (op & UINT64_C(2097152)) >> 10;
17116 Value |= (op & UINT64_C(2047));
17117 break;
17118 }
17119 case ARM::tCBNZ:
17120 case ARM::tCBZ: {
17121 // op: target
17122 op = getThumbCBTargetOpValue(MI, OpIdx: 1, Fixups, STI);
17123 Value |= (op & UINT64_C(32)) << 4;
17124 Value |= (op & UINT64_C(31)) << 3;
17125 // op: Rn
17126 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17127 op &= UINT64_C(7);
17128 Value |= op;
17129 break;
17130 }
17131 case ARM::BKPT:
17132 case ARM::HLT: {
17133 // op: val
17134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17135 Value |= (op & UINT64_C(65520)) << 4;
17136 Value |= (op & UINT64_C(15));
17137 break;
17138 }
17139 case ARM::tBKPT: {
17140 // op: val
17141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17142 op &= UINT64_C(255);
17143 Value |= op;
17144 break;
17145 }
17146 case ARM::tHLT: {
17147 // op: val
17148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17149 op &= UINT64_C(63);
17150 Value |= op;
17151 break;
17152 }
17153 default:
17154 std::string msg;
17155 raw_string_ostream Msg(msg);
17156 Msg << "Not supported instr: " << MI;
17157 report_fatal_error(reason: Msg.str().c_str());
17158 }
17159 return Value;
17160}
17161
17162#ifdef GET_OPERAND_BIT_OFFSET
17163#undef GET_OPERAND_BIT_OFFSET
17164
17165uint32_t ARMMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
17166 unsigned OpNum,
17167 const MCSubtargetInfo &STI) const {
17168 switch (MI.getOpcode()) {
17169 case ARM::CLREX:
17170 case ARM::MVE_LCTP:
17171 case ARM::MVE_VPNOT:
17172 case ARM::SB:
17173 case ARM::TRAP:
17174 case ARM::TRAPNaCl:
17175 case ARM::TSB:
17176 case ARM::VBSPd:
17177 case ARM::VBSPq:
17178 case ARM::VLD1LNq8Pseudo:
17179 case ARM::VLD1LNq8Pseudo_UPD:
17180 case ARM::VLD1LNq16Pseudo:
17181 case ARM::VLD1LNq16Pseudo_UPD:
17182 case ARM::VLD1LNq32Pseudo:
17183 case ARM::VLD1LNq32Pseudo_UPD:
17184 case ARM::VLD1d8QPseudo:
17185 case ARM::VLD1d8QPseudoWB_fixed:
17186 case ARM::VLD1d8QPseudoWB_register:
17187 case ARM::VLD1d8TPseudo:
17188 case ARM::VLD1d8TPseudoWB_fixed:
17189 case ARM::VLD1d8TPseudoWB_register:
17190 case ARM::VLD1d16QPseudo:
17191 case ARM::VLD1d16QPseudoWB_fixed:
17192 case ARM::VLD1d16QPseudoWB_register:
17193 case ARM::VLD1d16TPseudo:
17194 case ARM::VLD1d16TPseudoWB_fixed:
17195 case ARM::VLD1d16TPseudoWB_register:
17196 case ARM::VLD1d32QPseudo:
17197 case ARM::VLD1d32QPseudoWB_fixed:
17198 case ARM::VLD1d32QPseudoWB_register:
17199 case ARM::VLD1d32TPseudo:
17200 case ARM::VLD1d32TPseudoWB_fixed:
17201 case ARM::VLD1d32TPseudoWB_register:
17202 case ARM::VLD1d64QPseudo:
17203 case ARM::VLD1d64QPseudoWB_fixed:
17204 case ARM::VLD1d64QPseudoWB_register:
17205 case ARM::VLD1d64TPseudo:
17206 case ARM::VLD1d64TPseudoWB_fixed:
17207 case ARM::VLD1d64TPseudoWB_register:
17208 case ARM::VLD1q8HighQPseudo:
17209 case ARM::VLD1q8HighQPseudo_UPD:
17210 case ARM::VLD1q8HighTPseudo:
17211 case ARM::VLD1q8HighTPseudo_UPD:
17212 case ARM::VLD1q8LowQPseudo_UPD:
17213 case ARM::VLD1q8LowTPseudo_UPD:
17214 case ARM::VLD1q16HighQPseudo:
17215 case ARM::VLD1q16HighQPseudo_UPD:
17216 case ARM::VLD1q16HighTPseudo:
17217 case ARM::VLD1q16HighTPseudo_UPD:
17218 case ARM::VLD1q16LowQPseudo_UPD:
17219 case ARM::VLD1q16LowTPseudo_UPD:
17220 case ARM::VLD1q32HighQPseudo:
17221 case ARM::VLD1q32HighQPseudo_UPD:
17222 case ARM::VLD1q32HighTPseudo:
17223 case ARM::VLD1q32HighTPseudo_UPD:
17224 case ARM::VLD1q32LowQPseudo_UPD:
17225 case ARM::VLD1q32LowTPseudo_UPD:
17226 case ARM::VLD1q64HighQPseudo:
17227 case ARM::VLD1q64HighQPseudo_UPD:
17228 case ARM::VLD1q64HighTPseudo:
17229 case ARM::VLD1q64HighTPseudo_UPD:
17230 case ARM::VLD1q64LowQPseudo_UPD:
17231 case ARM::VLD1q64LowTPseudo_UPD:
17232 case ARM::VLD2DUPq8EvenPseudo:
17233 case ARM::VLD2DUPq8OddPseudo:
17234 case ARM::VLD2DUPq8OddPseudoWB_fixed:
17235 case ARM::VLD2DUPq8OddPseudoWB_register:
17236 case ARM::VLD2DUPq16EvenPseudo:
17237 case ARM::VLD2DUPq16OddPseudo:
17238 case ARM::VLD2DUPq16OddPseudoWB_fixed:
17239 case ARM::VLD2DUPq16OddPseudoWB_register:
17240 case ARM::VLD2DUPq32EvenPseudo:
17241 case ARM::VLD2DUPq32OddPseudo:
17242 case ARM::VLD2DUPq32OddPseudoWB_fixed:
17243 case ARM::VLD2DUPq32OddPseudoWB_register:
17244 case ARM::VLD2LNd8Pseudo:
17245 case ARM::VLD2LNd8Pseudo_UPD:
17246 case ARM::VLD2LNd16Pseudo:
17247 case ARM::VLD2LNd16Pseudo_UPD:
17248 case ARM::VLD2LNd32Pseudo:
17249 case ARM::VLD2LNd32Pseudo_UPD:
17250 case ARM::VLD2LNq16Pseudo:
17251 case ARM::VLD2LNq16Pseudo_UPD:
17252 case ARM::VLD2LNq32Pseudo:
17253 case ARM::VLD2LNq32Pseudo_UPD:
17254 case ARM::VLD2q8Pseudo:
17255 case ARM::VLD2q8PseudoWB_fixed:
17256 case ARM::VLD2q8PseudoWB_register:
17257 case ARM::VLD2q16Pseudo:
17258 case ARM::VLD2q16PseudoWB_fixed:
17259 case ARM::VLD2q16PseudoWB_register:
17260 case ARM::VLD2q32Pseudo:
17261 case ARM::VLD2q32PseudoWB_fixed:
17262 case ARM::VLD2q32PseudoWB_register:
17263 case ARM::VLD3DUPd8Pseudo:
17264 case ARM::VLD3DUPd8Pseudo_UPD:
17265 case ARM::VLD3DUPd16Pseudo:
17266 case ARM::VLD3DUPd16Pseudo_UPD:
17267 case ARM::VLD3DUPd32Pseudo:
17268 case ARM::VLD3DUPd32Pseudo_UPD:
17269 case ARM::VLD3DUPq8EvenPseudo:
17270 case ARM::VLD3DUPq8OddPseudo:
17271 case ARM::VLD3DUPq8OddPseudo_UPD:
17272 case ARM::VLD3DUPq16EvenPseudo:
17273 case ARM::VLD3DUPq16OddPseudo:
17274 case ARM::VLD3DUPq16OddPseudo_UPD:
17275 case ARM::VLD3DUPq32EvenPseudo:
17276 case ARM::VLD3DUPq32OddPseudo:
17277 case ARM::VLD3DUPq32OddPseudo_UPD:
17278 case ARM::VLD3LNd8Pseudo:
17279 case ARM::VLD3LNd8Pseudo_UPD:
17280 case ARM::VLD3LNd16Pseudo:
17281 case ARM::VLD3LNd16Pseudo_UPD:
17282 case ARM::VLD3LNd32Pseudo:
17283 case ARM::VLD3LNd32Pseudo_UPD:
17284 case ARM::VLD3LNq16Pseudo:
17285 case ARM::VLD3LNq16Pseudo_UPD:
17286 case ARM::VLD3LNq32Pseudo:
17287 case ARM::VLD3LNq32Pseudo_UPD:
17288 case ARM::VLD3d8Pseudo:
17289 case ARM::VLD3d8Pseudo_UPD:
17290 case ARM::VLD3d16Pseudo:
17291 case ARM::VLD3d16Pseudo_UPD:
17292 case ARM::VLD3d32Pseudo:
17293 case ARM::VLD3d32Pseudo_UPD:
17294 case ARM::VLD3q8Pseudo_UPD:
17295 case ARM::VLD3q8oddPseudo:
17296 case ARM::VLD3q8oddPseudo_UPD:
17297 case ARM::VLD3q16Pseudo_UPD:
17298 case ARM::VLD3q16oddPseudo:
17299 case ARM::VLD3q16oddPseudo_UPD:
17300 case ARM::VLD3q32Pseudo_UPD:
17301 case ARM::VLD3q32oddPseudo:
17302 case ARM::VLD3q32oddPseudo_UPD:
17303 case ARM::VLD4DUPd8Pseudo:
17304 case ARM::VLD4DUPd8Pseudo_UPD:
17305 case ARM::VLD4DUPd16Pseudo:
17306 case ARM::VLD4DUPd16Pseudo_UPD:
17307 case ARM::VLD4DUPd32Pseudo:
17308 case ARM::VLD4DUPd32Pseudo_UPD:
17309 case ARM::VLD4DUPq8EvenPseudo:
17310 case ARM::VLD4DUPq8OddPseudo:
17311 case ARM::VLD4DUPq8OddPseudo_UPD:
17312 case ARM::VLD4DUPq16EvenPseudo:
17313 case ARM::VLD4DUPq16OddPseudo:
17314 case ARM::VLD4DUPq16OddPseudo_UPD:
17315 case ARM::VLD4DUPq32EvenPseudo:
17316 case ARM::VLD4DUPq32OddPseudo:
17317 case ARM::VLD4DUPq32OddPseudo_UPD:
17318 case ARM::VLD4LNd8Pseudo:
17319 case ARM::VLD4LNd8Pseudo_UPD:
17320 case ARM::VLD4LNd16Pseudo:
17321 case ARM::VLD4LNd16Pseudo_UPD:
17322 case ARM::VLD4LNd32Pseudo:
17323 case ARM::VLD4LNd32Pseudo_UPD:
17324 case ARM::VLD4LNq16Pseudo:
17325 case ARM::VLD4LNq16Pseudo_UPD:
17326 case ARM::VLD4LNq32Pseudo:
17327 case ARM::VLD4LNq32Pseudo_UPD:
17328 case ARM::VLD4d8Pseudo:
17329 case ARM::VLD4d8Pseudo_UPD:
17330 case ARM::VLD4d16Pseudo:
17331 case ARM::VLD4d16Pseudo_UPD:
17332 case ARM::VLD4d32Pseudo:
17333 case ARM::VLD4d32Pseudo_UPD:
17334 case ARM::VLD4q8Pseudo_UPD:
17335 case ARM::VLD4q8oddPseudo:
17336 case ARM::VLD4q8oddPseudo_UPD:
17337 case ARM::VLD4q16Pseudo_UPD:
17338 case ARM::VLD4q16oddPseudo:
17339 case ARM::VLD4q16oddPseudo_UPD:
17340 case ARM::VLD4q32Pseudo_UPD:
17341 case ARM::VLD4q32oddPseudo:
17342 case ARM::VLD4q32oddPseudo_UPD:
17343 case ARM::VLDMQIA:
17344 case ARM::VST1LNq8Pseudo:
17345 case ARM::VST1LNq8Pseudo_UPD:
17346 case ARM::VST1LNq16Pseudo:
17347 case ARM::VST1LNq16Pseudo_UPD:
17348 case ARM::VST1LNq32Pseudo:
17349 case ARM::VST1LNq32Pseudo_UPD:
17350 case ARM::VST1d8QPseudo:
17351 case ARM::VST1d8QPseudoWB_fixed:
17352 case ARM::VST1d8QPseudoWB_register:
17353 case ARM::VST1d8TPseudo:
17354 case ARM::VST1d8TPseudoWB_fixed:
17355 case ARM::VST1d8TPseudoWB_register:
17356 case ARM::VST1d16QPseudo:
17357 case ARM::VST1d16QPseudoWB_fixed:
17358 case ARM::VST1d16QPseudoWB_register:
17359 case ARM::VST1d16TPseudo:
17360 case ARM::VST1d16TPseudoWB_fixed:
17361 case ARM::VST1d16TPseudoWB_register:
17362 case ARM::VST1d32QPseudo:
17363 case ARM::VST1d32QPseudoWB_fixed:
17364 case ARM::VST1d32QPseudoWB_register:
17365 case ARM::VST1d32TPseudo:
17366 case ARM::VST1d32TPseudoWB_fixed:
17367 case ARM::VST1d32TPseudoWB_register:
17368 case ARM::VST1d64QPseudo:
17369 case ARM::VST1d64QPseudoWB_fixed:
17370 case ARM::VST1d64QPseudoWB_register:
17371 case ARM::VST1d64TPseudo:
17372 case ARM::VST1d64TPseudoWB_fixed:
17373 case ARM::VST1d64TPseudoWB_register:
17374 case ARM::VST1q8HighQPseudo:
17375 case ARM::VST1q8HighQPseudo_UPD:
17376 case ARM::VST1q8HighTPseudo:
17377 case ARM::VST1q8HighTPseudo_UPD:
17378 case ARM::VST1q8LowQPseudo_UPD:
17379 case ARM::VST1q8LowTPseudo_UPD:
17380 case ARM::VST1q16HighQPseudo:
17381 case ARM::VST1q16HighQPseudo_UPD:
17382 case ARM::VST1q16HighTPseudo:
17383 case ARM::VST1q16HighTPseudo_UPD:
17384 case ARM::VST1q16LowQPseudo_UPD:
17385 case ARM::VST1q16LowTPseudo_UPD:
17386 case ARM::VST1q32HighQPseudo:
17387 case ARM::VST1q32HighQPseudo_UPD:
17388 case ARM::VST1q32HighTPseudo:
17389 case ARM::VST1q32HighTPseudo_UPD:
17390 case ARM::VST1q32LowQPseudo_UPD:
17391 case ARM::VST1q32LowTPseudo_UPD:
17392 case ARM::VST1q64HighQPseudo:
17393 case ARM::VST1q64HighQPseudo_UPD:
17394 case ARM::VST1q64HighTPseudo:
17395 case ARM::VST1q64HighTPseudo_UPD:
17396 case ARM::VST1q64LowQPseudo_UPD:
17397 case ARM::VST1q64LowTPseudo_UPD:
17398 case ARM::VST2LNd8Pseudo:
17399 case ARM::VST2LNd8Pseudo_UPD:
17400 case ARM::VST2LNd16Pseudo:
17401 case ARM::VST2LNd16Pseudo_UPD:
17402 case ARM::VST2LNd32Pseudo:
17403 case ARM::VST2LNd32Pseudo_UPD:
17404 case ARM::VST2LNq16Pseudo:
17405 case ARM::VST2LNq16Pseudo_UPD:
17406 case ARM::VST2LNq32Pseudo:
17407 case ARM::VST2LNq32Pseudo_UPD:
17408 case ARM::VST2q8Pseudo:
17409 case ARM::VST2q8PseudoWB_fixed:
17410 case ARM::VST2q8PseudoWB_register:
17411 case ARM::VST2q16Pseudo:
17412 case ARM::VST2q16PseudoWB_fixed:
17413 case ARM::VST2q16PseudoWB_register:
17414 case ARM::VST2q32Pseudo:
17415 case ARM::VST2q32PseudoWB_fixed:
17416 case ARM::VST2q32PseudoWB_register:
17417 case ARM::VST3LNd8Pseudo:
17418 case ARM::VST3LNd8Pseudo_UPD:
17419 case ARM::VST3LNd16Pseudo:
17420 case ARM::VST3LNd16Pseudo_UPD:
17421 case ARM::VST3LNd32Pseudo:
17422 case ARM::VST3LNd32Pseudo_UPD:
17423 case ARM::VST3LNq16Pseudo:
17424 case ARM::VST3LNq16Pseudo_UPD:
17425 case ARM::VST3LNq32Pseudo:
17426 case ARM::VST3LNq32Pseudo_UPD:
17427 case ARM::VST3d8Pseudo:
17428 case ARM::VST3d8Pseudo_UPD:
17429 case ARM::VST3d16Pseudo:
17430 case ARM::VST3d16Pseudo_UPD:
17431 case ARM::VST3d32Pseudo:
17432 case ARM::VST3d32Pseudo_UPD:
17433 case ARM::VST3q8Pseudo_UPD:
17434 case ARM::VST3q8oddPseudo:
17435 case ARM::VST3q8oddPseudo_UPD:
17436 case ARM::VST3q16Pseudo_UPD:
17437 case ARM::VST3q16oddPseudo:
17438 case ARM::VST3q16oddPseudo_UPD:
17439 case ARM::VST3q32Pseudo_UPD:
17440 case ARM::VST3q32oddPseudo:
17441 case ARM::VST3q32oddPseudo_UPD:
17442 case ARM::VST4LNd8Pseudo:
17443 case ARM::VST4LNd8Pseudo_UPD:
17444 case ARM::VST4LNd16Pseudo:
17445 case ARM::VST4LNd16Pseudo_UPD:
17446 case ARM::VST4LNd32Pseudo:
17447 case ARM::VST4LNd32Pseudo_UPD:
17448 case ARM::VST4LNq16Pseudo:
17449 case ARM::VST4LNq16Pseudo_UPD:
17450 case ARM::VST4LNq32Pseudo:
17451 case ARM::VST4LNq32Pseudo_UPD:
17452 case ARM::VST4d8Pseudo:
17453 case ARM::VST4d8Pseudo_UPD:
17454 case ARM::VST4d16Pseudo:
17455 case ARM::VST4d16Pseudo_UPD:
17456 case ARM::VST4d32Pseudo:
17457 case ARM::VST4d32Pseudo_UPD:
17458 case ARM::VST4q8Pseudo_UPD:
17459 case ARM::VST4q8oddPseudo:
17460 case ARM::VST4q8oddPseudo_UPD:
17461 case ARM::VST4q16Pseudo_UPD:
17462 case ARM::VST4q16oddPseudo:
17463 case ARM::VST4q16oddPseudo_UPD:
17464 case ARM::VST4q32Pseudo_UPD:
17465 case ARM::VST4q32oddPseudo:
17466 case ARM::VST4q32oddPseudo_UPD:
17467 case ARM::VSTMQIA:
17468 case ARM::VTBL3Pseudo:
17469 case ARM::VTBL4Pseudo:
17470 case ARM::VTBX3Pseudo:
17471 case ARM::VTBX4Pseudo:
17472 case ARM::t2AUT:
17473 case ARM::t2BTI:
17474 case ARM::t2CLREX:
17475 case ARM::t2DCPS1:
17476 case ARM::t2DCPS2:
17477 case ARM::t2DCPS3:
17478 case ARM::t2Int_eh_sjlj_setjmp:
17479 case ARM::t2Int_eh_sjlj_setjmp_nofp:
17480 case ARM::t2PAC:
17481 case ARM::t2PACBTI:
17482 case ARM::t2SB:
17483 case ARM::t2SG:
17484 case ARM::t2TSB:
17485 case ARM::tInt_WIN_eh_sjlj_longjmp:
17486 case ARM::tInt_eh_sjlj_longjmp:
17487 case ARM::tInt_eh_sjlj_setjmp:
17488 case ARM::tTRAP:
17489 case ARM::t__brkdiv0: {
17490 break;
17491 }
17492 case ARM::VRINTAD:
17493 case ARM::VRINTMD:
17494 case ARM::VRINTND:
17495 case ARM::VRINTPD: {
17496 switch (OpNum) {
17497 case 0:
17498 // op: Dd
17499 return 12;
17500 case 1:
17501 // op: Dm
17502 return 0;
17503 }
17504 break;
17505 }
17506 case ARM::VFP_VMAXNMD:
17507 case ARM::VFP_VMINNMD:
17508 case ARM::VSELEQD:
17509 case ARM::VSELGED:
17510 case ARM::VSELGTD:
17511 case ARM::VSELVSD: {
17512 switch (OpNum) {
17513 case 0:
17514 // op: Dd
17515 return 12;
17516 case 1:
17517 // op: Dn
17518 return 7;
17519 case 2:
17520 // op: Dm
17521 return 0;
17522 }
17523 break;
17524 }
17525 case ARM::MVE_VPST: {
17526 switch (OpNum) {
17527 case 0:
17528 // op: Mk
17529 return 13;
17530 }
17531 break;
17532 }
17533 case ARM::MVE_VQRSHL_by_vecs8:
17534 case ARM::MVE_VQRSHL_by_vecs16:
17535 case ARM::MVE_VQRSHL_by_vecs32:
17536 case ARM::MVE_VQRSHL_by_vecu8:
17537 case ARM::MVE_VQRSHL_by_vecu16:
17538 case ARM::MVE_VQRSHL_by_vecu32:
17539 case ARM::MVE_VQSHL_by_vecs8:
17540 case ARM::MVE_VQSHL_by_vecs16:
17541 case ARM::MVE_VQSHL_by_vecs32:
17542 case ARM::MVE_VQSHL_by_vecu8:
17543 case ARM::MVE_VQSHL_by_vecu16:
17544 case ARM::MVE_VQSHL_by_vecu32:
17545 case ARM::MVE_VRSHL_by_vecs8:
17546 case ARM::MVE_VRSHL_by_vecs16:
17547 case ARM::MVE_VRSHL_by_vecs32:
17548 case ARM::MVE_VRSHL_by_vecu8:
17549 case ARM::MVE_VRSHL_by_vecu16:
17550 case ARM::MVE_VRSHL_by_vecu32:
17551 case ARM::MVE_VSHL_by_vecs8:
17552 case ARM::MVE_VSHL_by_vecs16:
17553 case ARM::MVE_VSHL_by_vecs32:
17554 case ARM::MVE_VSHL_by_vecu8:
17555 case ARM::MVE_VSHL_by_vecu16:
17556 case ARM::MVE_VSHL_by_vecu32: {
17557 switch (OpNum) {
17558 case 0:
17559 // op: Qd
17560 return 13;
17561 case 1:
17562 // op: Qm
17563 return 1;
17564 case 2:
17565 // op: Qn
17566 return 7;
17567 }
17568 break;
17569 }
17570 case ARM::MVE_VQSHLU_imms8:
17571 case ARM::MVE_VQSHLU_imms16:
17572 case ARM::MVE_VQSHLU_imms32:
17573 case ARM::MVE_VQSHLimms8:
17574 case ARM::MVE_VQSHLimms16:
17575 case ARM::MVE_VQSHLimms32:
17576 case ARM::MVE_VQSHLimmu8:
17577 case ARM::MVE_VQSHLimmu16:
17578 case ARM::MVE_VQSHLimmu32:
17579 case ARM::MVE_VRSHR_imms8:
17580 case ARM::MVE_VRSHR_imms16:
17581 case ARM::MVE_VRSHR_imms32:
17582 case ARM::MVE_VRSHR_immu8:
17583 case ARM::MVE_VRSHR_immu16:
17584 case ARM::MVE_VRSHR_immu32:
17585 case ARM::MVE_VSHLL_imms8bh:
17586 case ARM::MVE_VSHLL_imms8th:
17587 case ARM::MVE_VSHLL_imms16bh:
17588 case ARM::MVE_VSHLL_imms16th:
17589 case ARM::MVE_VSHLL_immu8bh:
17590 case ARM::MVE_VSHLL_immu8th:
17591 case ARM::MVE_VSHLL_immu16bh:
17592 case ARM::MVE_VSHLL_immu16th:
17593 case ARM::MVE_VSHL_immi8:
17594 case ARM::MVE_VSHL_immi16:
17595 case ARM::MVE_VSHL_immi32:
17596 case ARM::MVE_VSHR_imms8:
17597 case ARM::MVE_VSHR_imms16:
17598 case ARM::MVE_VSHR_imms32:
17599 case ARM::MVE_VSHR_immu8:
17600 case ARM::MVE_VSHR_immu16:
17601 case ARM::MVE_VSHR_immu32: {
17602 switch (OpNum) {
17603 case 0:
17604 // op: Qd
17605 return 13;
17606 case 1:
17607 // op: Qm
17608 return 1;
17609 case 2:
17610 // op: imm
17611 return 16;
17612 }
17613 break;
17614 }
17615 case ARM::MVE_VABSs8:
17616 case ARM::MVE_VABSs16:
17617 case ARM::MVE_VABSs32:
17618 case ARM::MVE_VCLSs8:
17619 case ARM::MVE_VCLSs16:
17620 case ARM::MVE_VCLSs32:
17621 case ARM::MVE_VCLZs8:
17622 case ARM::MVE_VCLZs16:
17623 case ARM::MVE_VCLZs32:
17624 case ARM::MVE_VCVTf32f16bh:
17625 case ARM::MVE_VCVTf32f16th:
17626 case ARM::MVE_VMOVLs8bh:
17627 case ARM::MVE_VMOVLs8th:
17628 case ARM::MVE_VMOVLs16bh:
17629 case ARM::MVE_VMOVLs16th:
17630 case ARM::MVE_VMOVLu8bh:
17631 case ARM::MVE_VMOVLu8th:
17632 case ARM::MVE_VMOVLu16bh:
17633 case ARM::MVE_VMOVLu16th:
17634 case ARM::MVE_VMVN:
17635 case ARM::MVE_VNEGs8:
17636 case ARM::MVE_VNEGs16:
17637 case ARM::MVE_VNEGs32:
17638 case ARM::MVE_VQABSs8:
17639 case ARM::MVE_VQABSs16:
17640 case ARM::MVE_VQABSs32:
17641 case ARM::MVE_VQNEGs8:
17642 case ARM::MVE_VQNEGs16:
17643 case ARM::MVE_VQNEGs32:
17644 case ARM::MVE_VREV16_8:
17645 case ARM::MVE_VREV32_8:
17646 case ARM::MVE_VREV32_16:
17647 case ARM::MVE_VREV64_8:
17648 case ARM::MVE_VREV64_16:
17649 case ARM::MVE_VREV64_32:
17650 case ARM::MVE_VSHLL_lws8bh:
17651 case ARM::MVE_VSHLL_lws8th:
17652 case ARM::MVE_VSHLL_lws16bh:
17653 case ARM::MVE_VSHLL_lws16th:
17654 case ARM::MVE_VSHLL_lwu8bh:
17655 case ARM::MVE_VSHLL_lwu8th:
17656 case ARM::MVE_VSHLL_lwu16bh:
17657 case ARM::MVE_VSHLL_lwu16th: {
17658 switch (OpNum) {
17659 case 0:
17660 // op: Qd
17661 return 13;
17662 case 1:
17663 // op: Qm
17664 return 1;
17665 }
17666 break;
17667 }
17668 case ARM::MVE_VABDs8:
17669 case ARM::MVE_VABDs16:
17670 case ARM::MVE_VABDs32:
17671 case ARM::MVE_VABDu8:
17672 case ARM::MVE_VABDu16:
17673 case ARM::MVE_VABDu32:
17674 case ARM::MVE_VADDi8:
17675 case ARM::MVE_VADDi16:
17676 case ARM::MVE_VADDi32:
17677 case ARM::MVE_VHADDs8:
17678 case ARM::MVE_VHADDs16:
17679 case ARM::MVE_VHADDs32:
17680 case ARM::MVE_VHADDu8:
17681 case ARM::MVE_VHADDu16:
17682 case ARM::MVE_VHADDu32:
17683 case ARM::MVE_VHSUBs8:
17684 case ARM::MVE_VHSUBs16:
17685 case ARM::MVE_VHSUBs32:
17686 case ARM::MVE_VHSUBu8:
17687 case ARM::MVE_VHSUBu16:
17688 case ARM::MVE_VHSUBu32:
17689 case ARM::MVE_VMAXNMf16:
17690 case ARM::MVE_VMAXNMf32:
17691 case ARM::MVE_VMAXs8:
17692 case ARM::MVE_VMAXs16:
17693 case ARM::MVE_VMAXs32:
17694 case ARM::MVE_VMAXu8:
17695 case ARM::MVE_VMAXu16:
17696 case ARM::MVE_VMAXu32:
17697 case ARM::MVE_VMINNMf16:
17698 case ARM::MVE_VMINNMf32:
17699 case ARM::MVE_VMINs8:
17700 case ARM::MVE_VMINs16:
17701 case ARM::MVE_VMINs32:
17702 case ARM::MVE_VMINu8:
17703 case ARM::MVE_VMINu16:
17704 case ARM::MVE_VMINu32:
17705 case ARM::MVE_VMULi8:
17706 case ARM::MVE_VMULi16:
17707 case ARM::MVE_VMULi32:
17708 case ARM::MVE_VQADDs8:
17709 case ARM::MVE_VQADDs16:
17710 case ARM::MVE_VQADDs32:
17711 case ARM::MVE_VQADDu8:
17712 case ARM::MVE_VQADDu16:
17713 case ARM::MVE_VQADDu32:
17714 case ARM::MVE_VQDMULHi8:
17715 case ARM::MVE_VQDMULHi16:
17716 case ARM::MVE_VQDMULHi32:
17717 case ARM::MVE_VQRDMULHi8:
17718 case ARM::MVE_VQRDMULHi16:
17719 case ARM::MVE_VQRDMULHi32:
17720 case ARM::MVE_VQSUBs8:
17721 case ARM::MVE_VQSUBs16:
17722 case ARM::MVE_VQSUBs32:
17723 case ARM::MVE_VQSUBu8:
17724 case ARM::MVE_VQSUBu16:
17725 case ARM::MVE_VQSUBu32:
17726 case ARM::MVE_VRHADDs8:
17727 case ARM::MVE_VRHADDs16:
17728 case ARM::MVE_VRHADDs32:
17729 case ARM::MVE_VRHADDu8:
17730 case ARM::MVE_VRHADDu16:
17731 case ARM::MVE_VRHADDu32:
17732 case ARM::MVE_VSUBi8:
17733 case ARM::MVE_VSUBi16:
17734 case ARM::MVE_VSUBi32: {
17735 switch (OpNum) {
17736 case 0:
17737 // op: Qd
17738 return 13;
17739 case 1:
17740 // op: Qn
17741 return 7;
17742 case 2:
17743 // op: Qm
17744 return 1;
17745 }
17746 break;
17747 }
17748 case ARM::MVE_VADD_qr_f16:
17749 case ARM::MVE_VADD_qr_f32:
17750 case ARM::MVE_VADD_qr_i8:
17751 case ARM::MVE_VADD_qr_i16:
17752 case ARM::MVE_VADD_qr_i32:
17753 case ARM::MVE_VBRSR8:
17754 case ARM::MVE_VBRSR16:
17755 case ARM::MVE_VBRSR32:
17756 case ARM::MVE_VHADD_qr_s8:
17757 case ARM::MVE_VHADD_qr_s16:
17758 case ARM::MVE_VHADD_qr_s32:
17759 case ARM::MVE_VHADD_qr_u8:
17760 case ARM::MVE_VHADD_qr_u16:
17761 case ARM::MVE_VHADD_qr_u32:
17762 case ARM::MVE_VHSUB_qr_s8:
17763 case ARM::MVE_VHSUB_qr_s16:
17764 case ARM::MVE_VHSUB_qr_s32:
17765 case ARM::MVE_VHSUB_qr_u8:
17766 case ARM::MVE_VHSUB_qr_u16:
17767 case ARM::MVE_VHSUB_qr_u32:
17768 case ARM::MVE_VMUL_qr_f16:
17769 case ARM::MVE_VMUL_qr_f32:
17770 case ARM::MVE_VMUL_qr_i8:
17771 case ARM::MVE_VMUL_qr_i16:
17772 case ARM::MVE_VMUL_qr_i32:
17773 case ARM::MVE_VQADD_qr_s8:
17774 case ARM::MVE_VQADD_qr_s16:
17775 case ARM::MVE_VQADD_qr_s32:
17776 case ARM::MVE_VQADD_qr_u8:
17777 case ARM::MVE_VQADD_qr_u16:
17778 case ARM::MVE_VQADD_qr_u32:
17779 case ARM::MVE_VQDMULH_qr_s8:
17780 case ARM::MVE_VQDMULH_qr_s16:
17781 case ARM::MVE_VQDMULH_qr_s32:
17782 case ARM::MVE_VQDMULL_qr_s16bh:
17783 case ARM::MVE_VQDMULL_qr_s16th:
17784 case ARM::MVE_VQDMULL_qr_s32bh:
17785 case ARM::MVE_VQDMULL_qr_s32th:
17786 case ARM::MVE_VQRDMULH_qr_s8:
17787 case ARM::MVE_VQRDMULH_qr_s16:
17788 case ARM::MVE_VQRDMULH_qr_s32:
17789 case ARM::MVE_VQSUB_qr_s8:
17790 case ARM::MVE_VQSUB_qr_s16:
17791 case ARM::MVE_VQSUB_qr_s32:
17792 case ARM::MVE_VQSUB_qr_u8:
17793 case ARM::MVE_VQSUB_qr_u16:
17794 case ARM::MVE_VQSUB_qr_u32:
17795 case ARM::MVE_VSUB_qr_f16:
17796 case ARM::MVE_VSUB_qr_f32:
17797 case ARM::MVE_VSUB_qr_i8:
17798 case ARM::MVE_VSUB_qr_i16:
17799 case ARM::MVE_VSUB_qr_i32: {
17800 switch (OpNum) {
17801 case 0:
17802 // op: Qd
17803 return 13;
17804 case 1:
17805 // op: Qn
17806 return 7;
17807 case 2:
17808 // op: Rm
17809 return 0;
17810 }
17811 break;
17812 }
17813 case ARM::MVE_VDDUPu8:
17814 case ARM::MVE_VDDUPu16:
17815 case ARM::MVE_VDDUPu32:
17816 case ARM::MVE_VIDUPu8:
17817 case ARM::MVE_VIDUPu16:
17818 case ARM::MVE_VIDUPu32: {
17819 switch (OpNum) {
17820 case 0:
17821 // op: Qd
17822 return 13;
17823 case 1:
17824 // op: Rn
17825 return 17;
17826 case 3:
17827 // op: imm
17828 return 0;
17829 }
17830 break;
17831 }
17832 case ARM::MVE_VLDRBS16:
17833 case ARM::MVE_VLDRBS32:
17834 case ARM::MVE_VLDRBU8:
17835 case ARM::MVE_VLDRBU16:
17836 case ARM::MVE_VLDRBU32:
17837 case ARM::MVE_VLDRDU64_qi:
17838 case ARM::MVE_VLDRHS32:
17839 case ARM::MVE_VLDRHU16:
17840 case ARM::MVE_VLDRHU32:
17841 case ARM::MVE_VLDRWU32:
17842 case ARM::MVE_VLDRWU32_qi:
17843 case ARM::MVE_VSTRB16:
17844 case ARM::MVE_VSTRB32:
17845 case ARM::MVE_VSTRBU8:
17846 case ARM::MVE_VSTRD64_qi:
17847 case ARM::MVE_VSTRH32:
17848 case ARM::MVE_VSTRHU16:
17849 case ARM::MVE_VSTRW32_qi:
17850 case ARM::MVE_VSTRWU32: {
17851 switch (OpNum) {
17852 case 0:
17853 // op: Qd
17854 return 13;
17855 case 1:
17856 // op: addr
17857 return 0;
17858 }
17859 break;
17860 }
17861 case ARM::MVE_VLDRBS16_rq:
17862 case ARM::MVE_VLDRBS32_rq:
17863 case ARM::MVE_VLDRBU8_rq:
17864 case ARM::MVE_VLDRBU16_rq:
17865 case ARM::MVE_VLDRBU32_rq:
17866 case ARM::MVE_VLDRDU64_rq:
17867 case ARM::MVE_VLDRDU64_rq_u:
17868 case ARM::MVE_VLDRHS32_rq:
17869 case ARM::MVE_VLDRHS32_rq_u:
17870 case ARM::MVE_VLDRHU16_rq:
17871 case ARM::MVE_VLDRHU16_rq_u:
17872 case ARM::MVE_VLDRHU32_rq:
17873 case ARM::MVE_VLDRHU32_rq_u:
17874 case ARM::MVE_VLDRWU32_rq:
17875 case ARM::MVE_VLDRWU32_rq_u:
17876 case ARM::MVE_VSTRB8_rq:
17877 case ARM::MVE_VSTRB16_rq:
17878 case ARM::MVE_VSTRB32_rq:
17879 case ARM::MVE_VSTRD64_rq:
17880 case ARM::MVE_VSTRD64_rq_u:
17881 case ARM::MVE_VSTRH16_rq:
17882 case ARM::MVE_VSTRH16_rq_u:
17883 case ARM::MVE_VSTRH32_rq:
17884 case ARM::MVE_VSTRH32_rq_u:
17885 case ARM::MVE_VSTRW32_rq:
17886 case ARM::MVE_VSTRW32_rq_u: {
17887 switch (OpNum) {
17888 case 0:
17889 // op: Qd
17890 return 13;
17891 case 1:
17892 // op: addr
17893 return 1;
17894 }
17895 break;
17896 }
17897 case ARM::MVE_VCMULf16:
17898 case ARM::MVE_VCMULf32: {
17899 switch (OpNum) {
17900 case 0:
17901 // op: Qd
17902 return 13;
17903 case 2:
17904 // op: Qm
17905 return 1;
17906 case 1:
17907 // op: Qn
17908 return 7;
17909 case 3:
17910 // op: rot
17911 return 0;
17912 }
17913 break;
17914 }
17915 case ARM::MVE_VCADDi8:
17916 case ARM::MVE_VCADDi16:
17917 case ARM::MVE_VCADDi32:
17918 case ARM::MVE_VHCADDs8:
17919 case ARM::MVE_VHCADDs16:
17920 case ARM::MVE_VHCADDs32: {
17921 switch (OpNum) {
17922 case 0:
17923 // op: Qd
17924 return 13;
17925 case 2:
17926 // op: Qm
17927 return 1;
17928 case 1:
17929 // op: Qn
17930 return 7;
17931 case 3:
17932 // op: rot
17933 return 12;
17934 }
17935 break;
17936 }
17937 case ARM::MVE_VAND:
17938 case ARM::MVE_VBIC:
17939 case ARM::MVE_VEOR:
17940 case ARM::MVE_VMULHs8:
17941 case ARM::MVE_VMULHs16:
17942 case ARM::MVE_VMULHs32:
17943 case ARM::MVE_VMULHu8:
17944 case ARM::MVE_VMULHu16:
17945 case ARM::MVE_VMULHu32:
17946 case ARM::MVE_VMULLBp8:
17947 case ARM::MVE_VMULLBp16:
17948 case ARM::MVE_VMULLBs8:
17949 case ARM::MVE_VMULLBs16:
17950 case ARM::MVE_VMULLBs32:
17951 case ARM::MVE_VMULLBu8:
17952 case ARM::MVE_VMULLBu16:
17953 case ARM::MVE_VMULLBu32:
17954 case ARM::MVE_VMULLTp8:
17955 case ARM::MVE_VMULLTp16:
17956 case ARM::MVE_VMULLTs8:
17957 case ARM::MVE_VMULLTs16:
17958 case ARM::MVE_VMULLTs32:
17959 case ARM::MVE_VMULLTu8:
17960 case ARM::MVE_VMULLTu16:
17961 case ARM::MVE_VMULLTu32:
17962 case ARM::MVE_VORN:
17963 case ARM::MVE_VORR:
17964 case ARM::MVE_VQDMULLs16bh:
17965 case ARM::MVE_VQDMULLs16th:
17966 case ARM::MVE_VQDMULLs32bh:
17967 case ARM::MVE_VQDMULLs32th:
17968 case ARM::MVE_VRMULHs8:
17969 case ARM::MVE_VRMULHs16:
17970 case ARM::MVE_VRMULHs32:
17971 case ARM::MVE_VRMULHu8:
17972 case ARM::MVE_VRMULHu16:
17973 case ARM::MVE_VRMULHu32: {
17974 switch (OpNum) {
17975 case 0:
17976 // op: Qd
17977 return 13;
17978 case 2:
17979 // op: Qm
17980 return 1;
17981 case 1:
17982 // op: Qn
17983 return 7;
17984 }
17985 break;
17986 }
17987 case ARM::MVE_VQRSHRNbhs16:
17988 case ARM::MVE_VQRSHRNbhs32:
17989 case ARM::MVE_VQRSHRNbhu16:
17990 case ARM::MVE_VQRSHRNbhu32:
17991 case ARM::MVE_VQRSHRNths16:
17992 case ARM::MVE_VQRSHRNths32:
17993 case ARM::MVE_VQRSHRNthu16:
17994 case ARM::MVE_VQRSHRNthu32:
17995 case ARM::MVE_VQRSHRUNs16bh:
17996 case ARM::MVE_VQRSHRUNs16th:
17997 case ARM::MVE_VQRSHRUNs32bh:
17998 case ARM::MVE_VQRSHRUNs32th:
17999 case ARM::MVE_VQSHRNbhs16:
18000 case ARM::MVE_VQSHRNbhs32:
18001 case ARM::MVE_VQSHRNbhu16:
18002 case ARM::MVE_VQSHRNbhu32:
18003 case ARM::MVE_VQSHRNths16:
18004 case ARM::MVE_VQSHRNths32:
18005 case ARM::MVE_VQSHRNthu16:
18006 case ARM::MVE_VQSHRNthu32:
18007 case ARM::MVE_VQSHRUNs16bh:
18008 case ARM::MVE_VQSHRUNs16th:
18009 case ARM::MVE_VQSHRUNs32bh:
18010 case ARM::MVE_VQSHRUNs32th:
18011 case ARM::MVE_VRSHRNi16bh:
18012 case ARM::MVE_VRSHRNi16th:
18013 case ARM::MVE_VRSHRNi32bh:
18014 case ARM::MVE_VRSHRNi32th:
18015 case ARM::MVE_VSHRNi16bh:
18016 case ARM::MVE_VSHRNi16th:
18017 case ARM::MVE_VSHRNi32bh:
18018 case ARM::MVE_VSHRNi32th:
18019 case ARM::MVE_VSLIimm8:
18020 case ARM::MVE_VSLIimm16:
18021 case ARM::MVE_VSLIimm32:
18022 case ARM::MVE_VSRIimm8:
18023 case ARM::MVE_VSRIimm16:
18024 case ARM::MVE_VSRIimm32: {
18025 switch (OpNum) {
18026 case 0:
18027 // op: Qd
18028 return 13;
18029 case 2:
18030 // op: Qm
18031 return 1;
18032 case 3:
18033 // op: imm
18034 return 16;
18035 }
18036 break;
18037 }
18038 case ARM::MVE_VCVTf16f32bh:
18039 case ARM::MVE_VCVTf16f32th:
18040 case ARM::MVE_VMAXAs8:
18041 case ARM::MVE_VMAXAs16:
18042 case ARM::MVE_VMAXAs32:
18043 case ARM::MVE_VMAXNMAf16:
18044 case ARM::MVE_VMAXNMAf32:
18045 case ARM::MVE_VMINAs8:
18046 case ARM::MVE_VMINAs16:
18047 case ARM::MVE_VMINAs32:
18048 case ARM::MVE_VMINNMAf16:
18049 case ARM::MVE_VMINNMAf32:
18050 case ARM::MVE_VMOVNi16bh:
18051 case ARM::MVE_VMOVNi16th:
18052 case ARM::MVE_VMOVNi32bh:
18053 case ARM::MVE_VMOVNi32th:
18054 case ARM::MVE_VQMOVNs16bh:
18055 case ARM::MVE_VQMOVNs16th:
18056 case ARM::MVE_VQMOVNs32bh:
18057 case ARM::MVE_VQMOVNs32th:
18058 case ARM::MVE_VQMOVNu16bh:
18059 case ARM::MVE_VQMOVNu16th:
18060 case ARM::MVE_VQMOVNu32bh:
18061 case ARM::MVE_VQMOVNu32th:
18062 case ARM::MVE_VQMOVUNs16bh:
18063 case ARM::MVE_VQMOVUNs16th:
18064 case ARM::MVE_VQMOVUNs32bh:
18065 case ARM::MVE_VQMOVUNs32th: {
18066 switch (OpNum) {
18067 case 0:
18068 // op: Qd
18069 return 13;
18070 case 2:
18071 // op: Qm
18072 return 1;
18073 }
18074 break;
18075 }
18076 case ARM::MVE_VFMA_qr_Sf16:
18077 case ARM::MVE_VFMA_qr_Sf32:
18078 case ARM::MVE_VFMA_qr_f16:
18079 case ARM::MVE_VFMA_qr_f32:
18080 case ARM::MVE_VMLAS_qr_i8:
18081 case ARM::MVE_VMLAS_qr_i16:
18082 case ARM::MVE_VMLAS_qr_i32:
18083 case ARM::MVE_VMLA_qr_i8:
18084 case ARM::MVE_VMLA_qr_i16:
18085 case ARM::MVE_VMLA_qr_i32:
18086 case ARM::MVE_VQDMLAH_qrs8:
18087 case ARM::MVE_VQDMLAH_qrs16:
18088 case ARM::MVE_VQDMLAH_qrs32:
18089 case ARM::MVE_VQDMLASH_qrs8:
18090 case ARM::MVE_VQDMLASH_qrs16:
18091 case ARM::MVE_VQDMLASH_qrs32:
18092 case ARM::MVE_VQRDMLAH_qrs8:
18093 case ARM::MVE_VQRDMLAH_qrs16:
18094 case ARM::MVE_VQRDMLAH_qrs32:
18095 case ARM::MVE_VQRDMLASH_qrs8:
18096 case ARM::MVE_VQRDMLASH_qrs16:
18097 case ARM::MVE_VQRDMLASH_qrs32: {
18098 switch (OpNum) {
18099 case 0:
18100 // op: Qd
18101 return 13;
18102 case 2:
18103 // op: Qn
18104 return 7;
18105 case 3:
18106 // op: Rm
18107 return 0;
18108 }
18109 break;
18110 }
18111 case ARM::MVE_VQRSHL_qrs8:
18112 case ARM::MVE_VQRSHL_qrs16:
18113 case ARM::MVE_VQRSHL_qrs32:
18114 case ARM::MVE_VQRSHL_qru8:
18115 case ARM::MVE_VQRSHL_qru16:
18116 case ARM::MVE_VQRSHL_qru32:
18117 case ARM::MVE_VQSHL_qrs8:
18118 case ARM::MVE_VQSHL_qrs16:
18119 case ARM::MVE_VQSHL_qrs32:
18120 case ARM::MVE_VQSHL_qru8:
18121 case ARM::MVE_VQSHL_qru16:
18122 case ARM::MVE_VQSHL_qru32:
18123 case ARM::MVE_VRSHL_qrs8:
18124 case ARM::MVE_VRSHL_qrs16:
18125 case ARM::MVE_VRSHL_qrs32:
18126 case ARM::MVE_VRSHL_qru8:
18127 case ARM::MVE_VRSHL_qru16:
18128 case ARM::MVE_VRSHL_qru32:
18129 case ARM::MVE_VSHL_qrs8:
18130 case ARM::MVE_VSHL_qrs16:
18131 case ARM::MVE_VSHL_qrs32:
18132 case ARM::MVE_VSHL_qru8:
18133 case ARM::MVE_VSHL_qru16:
18134 case ARM::MVE_VSHL_qru32: {
18135 switch (OpNum) {
18136 case 0:
18137 // op: Qd
18138 return 13;
18139 case 2:
18140 // op: Rm
18141 return 0;
18142 }
18143 break;
18144 }
18145 case ARM::MVE_VADC:
18146 case ARM::MVE_VADCI:
18147 case ARM::MVE_VQDMLADHXs8:
18148 case ARM::MVE_VQDMLADHXs16:
18149 case ARM::MVE_VQDMLADHXs32:
18150 case ARM::MVE_VQDMLADHs8:
18151 case ARM::MVE_VQDMLADHs16:
18152 case ARM::MVE_VQDMLADHs32:
18153 case ARM::MVE_VQDMLSDHXs8:
18154 case ARM::MVE_VQDMLSDHXs16:
18155 case ARM::MVE_VQDMLSDHXs32:
18156 case ARM::MVE_VQDMLSDHs8:
18157 case ARM::MVE_VQDMLSDHs16:
18158 case ARM::MVE_VQDMLSDHs32:
18159 case ARM::MVE_VQRDMLADHXs8:
18160 case ARM::MVE_VQRDMLADHXs16:
18161 case ARM::MVE_VQRDMLADHXs32:
18162 case ARM::MVE_VQRDMLADHs8:
18163 case ARM::MVE_VQRDMLADHs16:
18164 case ARM::MVE_VQRDMLADHs32:
18165 case ARM::MVE_VQRDMLSDHXs8:
18166 case ARM::MVE_VQRDMLSDHXs16:
18167 case ARM::MVE_VQRDMLSDHXs32:
18168 case ARM::MVE_VQRDMLSDHs8:
18169 case ARM::MVE_VQRDMLSDHs16:
18170 case ARM::MVE_VQRDMLSDHs32:
18171 case ARM::MVE_VSBC:
18172 case ARM::MVE_VSBCI: {
18173 switch (OpNum) {
18174 case 0:
18175 // op: Qd
18176 return 13;
18177 case 3:
18178 // op: Qm
18179 return 1;
18180 case 2:
18181 // op: Qn
18182 return 7;
18183 }
18184 break;
18185 }
18186 case ARM::MVE_VDWDUPu8:
18187 case ARM::MVE_VDWDUPu16:
18188 case ARM::MVE_VDWDUPu32:
18189 case ARM::MVE_VIWDUPu8:
18190 case ARM::MVE_VIWDUPu16:
18191 case ARM::MVE_VIWDUPu32: {
18192 switch (OpNum) {
18193 case 0:
18194 // op: Qd
18195 return 13;
18196 case 3:
18197 // op: Rm
18198 return 1;
18199 case 1:
18200 // op: Rn
18201 return 17;
18202 case 4:
18203 // op: imm
18204 return 0;
18205 }
18206 break;
18207 }
18208 case ARM::MVE_VDUP8:
18209 case ARM::MVE_VDUP16:
18210 case ARM::MVE_VDUP32: {
18211 switch (OpNum) {
18212 case 0:
18213 // op: Qd
18214 return 7;
18215 case 1:
18216 // op: Rt
18217 return 12;
18218 }
18219 break;
18220 }
18221 case ARM::MVE_VMOV_to_lane_32: {
18222 switch (OpNum) {
18223 case 0:
18224 // op: Qd
18225 return 7;
18226 case 2:
18227 // op: Rt
18228 return 12;
18229 case 3:
18230 // op: Idx
18231 return 16;
18232 }
18233 break;
18234 }
18235 case ARM::MVE_VMOV_to_lane_8: {
18236 switch (OpNum) {
18237 case 0:
18238 // op: Qd
18239 return 7;
18240 case 2:
18241 // op: Rt
18242 return 12;
18243 case 3:
18244 // op: Idx
18245 return 5;
18246 }
18247 break;
18248 }
18249 case ARM::MVE_VMOV_to_lane_16: {
18250 switch (OpNum) {
18251 case 0:
18252 // op: Qd
18253 return 7;
18254 case 2:
18255 // op: Rt
18256 return 12;
18257 case 3:
18258 // op: Idx
18259 return 6;
18260 }
18261 break;
18262 }
18263 case ARM::tMOVSr:
18264 case ARM::tMOVr: {
18265 switch (OpNum) {
18266 case 0:
18267 // op: Rd
18268 return 0;
18269 case 1:
18270 // op: Rm
18271 return 3;
18272 }
18273 break;
18274 }
18275 case ARM::t2STLEX: {
18276 switch (OpNum) {
18277 case 0:
18278 // op: Rd
18279 return 0;
18280 case 1:
18281 // op: Rt
18282 return 12;
18283 case 2:
18284 // op: addr
18285 return 16;
18286 }
18287 break;
18288 }
18289 case ARM::tADDi3:
18290 case ARM::tSUBi3: {
18291 switch (OpNum) {
18292 case 0:
18293 // op: Rd
18294 return 0;
18295 case 2:
18296 // op: Rm
18297 return 3;
18298 case 3:
18299 // op: imm3
18300 return 6;
18301 }
18302 break;
18303 }
18304 case ARM::tASRri:
18305 case ARM::tLSLri:
18306 case ARM::tLSRri: {
18307 switch (OpNum) {
18308 case 0:
18309 // op: Rd
18310 return 0;
18311 case 2:
18312 // op: Rm
18313 return 3;
18314 case 3:
18315 // op: imm5
18316 return 6;
18317 }
18318 break;
18319 }
18320 case ARM::tMUL:
18321 case ARM::tMVN:
18322 case ARM::tRSB: {
18323 switch (OpNum) {
18324 case 0:
18325 // op: Rd
18326 return 0;
18327 case 2:
18328 // op: Rn
18329 return 3;
18330 }
18331 break;
18332 }
18333 case ARM::t2STLEXB:
18334 case ARM::t2STLEXH:
18335 case ARM::t2STREXB:
18336 case ARM::t2STREXH: {
18337 switch (OpNum) {
18338 case 0:
18339 // op: Rd
18340 return 0;
18341 case 2:
18342 // op: addr
18343 return 16;
18344 case 1:
18345 // op: Rt
18346 return 12;
18347 }
18348 break;
18349 }
18350 case ARM::t2STLEXD:
18351 case ARM::t2STREXD: {
18352 switch (OpNum) {
18353 case 0:
18354 // op: Rd
18355 return 0;
18356 case 3:
18357 // op: addr
18358 return 16;
18359 case 1:
18360 // op: Rt
18361 return 12;
18362 case 2:
18363 // op: Rt2
18364 return 8;
18365 }
18366 break;
18367 }
18368 case ARM::CRC32B:
18369 case ARM::CRC32CB:
18370 case ARM::CRC32CH:
18371 case ARM::CRC32CW:
18372 case ARM::CRC32H:
18373 case ARM::CRC32W: {
18374 switch (OpNum) {
18375 case 0:
18376 // op: Rd
18377 return 12;
18378 case 1:
18379 // op: Rn
18380 return 16;
18381 case 2:
18382 // op: Rm
18383 return 0;
18384 }
18385 break;
18386 }
18387 case ARM::t2SXTB:
18388 case ARM::t2SXTB16:
18389 case ARM::t2SXTH:
18390 case ARM::t2UXTB:
18391 case ARM::t2UXTB16:
18392 case ARM::t2UXTH: {
18393 switch (OpNum) {
18394 case 0:
18395 // op: Rd
18396 return 8;
18397 case 1:
18398 // op: Rm
18399 return 0;
18400 case 2:
18401 // op: rot
18402 return 4;
18403 }
18404 break;
18405 }
18406 case ARM::t2CLZ:
18407 case ARM::t2MOVsra_glue:
18408 case ARM::t2MOVsrl_glue:
18409 case ARM::t2RBIT:
18410 case ARM::t2REV:
18411 case ARM::t2REV16:
18412 case ARM::t2REVSH: {
18413 switch (OpNum) {
18414 case 0:
18415 // op: Rd
18416 return 8;
18417 case 1:
18418 // op: Rm
18419 return 0;
18420 }
18421 break;
18422 }
18423 case ARM::t2MLA:
18424 case ARM::t2MLS:
18425 case ARM::t2SMLABB:
18426 case ARM::t2SMLABT:
18427 case ARM::t2SMLAD:
18428 case ARM::t2SMLADX:
18429 case ARM::t2SMLATB:
18430 case ARM::t2SMLATT:
18431 case ARM::t2SMLAWB:
18432 case ARM::t2SMLAWT:
18433 case ARM::t2SMLSD:
18434 case ARM::t2SMLSDX:
18435 case ARM::t2SMMLA:
18436 case ARM::t2SMMLAR:
18437 case ARM::t2SMMLS:
18438 case ARM::t2SMMLSR:
18439 case ARM::t2USADA8: {
18440 switch (OpNum) {
18441 case 0:
18442 // op: Rd
18443 return 8;
18444 case 1:
18445 // op: Rn
18446 return 16;
18447 case 2:
18448 // op: Rm
18449 return 0;
18450 case 3:
18451 // op: Ra
18452 return 12;
18453 }
18454 break;
18455 }
18456 case ARM::t2SXTAB:
18457 case ARM::t2SXTAB16:
18458 case ARM::t2SXTAH:
18459 case ARM::t2UXTAB:
18460 case ARM::t2UXTAB16:
18461 case ARM::t2UXTAH: {
18462 switch (OpNum) {
18463 case 0:
18464 // op: Rd
18465 return 8;
18466 case 1:
18467 // op: Rn
18468 return 16;
18469 case 2:
18470 // op: Rm
18471 return 0;
18472 case 3:
18473 // op: rot
18474 return 4;
18475 }
18476 break;
18477 }
18478 case ARM::t2PKHBT:
18479 case ARM::t2PKHTB: {
18480 switch (OpNum) {
18481 case 0:
18482 // op: Rd
18483 return 8;
18484 case 1:
18485 // op: Rn
18486 return 16;
18487 case 2:
18488 // op: Rm
18489 return 0;
18490 case 3:
18491 // op: sh
18492 return 6;
18493 }
18494 break;
18495 }
18496 case ARM::t2CRC32B:
18497 case ARM::t2CRC32CB:
18498 case ARM::t2CRC32CH:
18499 case ARM::t2CRC32CW:
18500 case ARM::t2CRC32H:
18501 case ARM::t2CRC32W:
18502 case ARM::t2MUL:
18503 case ARM::t2QADD8:
18504 case ARM::t2QADD16:
18505 case ARM::t2QASX:
18506 case ARM::t2QSAX:
18507 case ARM::t2QSUB8:
18508 case ARM::t2QSUB16:
18509 case ARM::t2SADD8:
18510 case ARM::t2SADD16:
18511 case ARM::t2SASX:
18512 case ARM::t2SDIV:
18513 case ARM::t2SEL:
18514 case ARM::t2SHADD8:
18515 case ARM::t2SHADD16:
18516 case ARM::t2SHASX:
18517 case ARM::t2SHSAX:
18518 case ARM::t2SHSUB8:
18519 case ARM::t2SHSUB16:
18520 case ARM::t2SMMUL:
18521 case ARM::t2SMMULR:
18522 case ARM::t2SMUAD:
18523 case ARM::t2SMUADX:
18524 case ARM::t2SMULBB:
18525 case ARM::t2SMULBT:
18526 case ARM::t2SMULTB:
18527 case ARM::t2SMULTT:
18528 case ARM::t2SMULWB:
18529 case ARM::t2SMULWT:
18530 case ARM::t2SMUSD:
18531 case ARM::t2SMUSDX:
18532 case ARM::t2SSAX:
18533 case ARM::t2SSUB8:
18534 case ARM::t2SSUB16:
18535 case ARM::t2UADD8:
18536 case ARM::t2UADD16:
18537 case ARM::t2UASX:
18538 case ARM::t2UDIV:
18539 case ARM::t2UHADD8:
18540 case ARM::t2UHADD16:
18541 case ARM::t2UHASX:
18542 case ARM::t2UHSAX:
18543 case ARM::t2UHSUB8:
18544 case ARM::t2UHSUB16:
18545 case ARM::t2UQADD8:
18546 case ARM::t2UQADD16:
18547 case ARM::t2UQASX:
18548 case ARM::t2UQSAX:
18549 case ARM::t2UQSUB8:
18550 case ARM::t2UQSUB16:
18551 case ARM::t2USAD8:
18552 case ARM::t2USAX:
18553 case ARM::t2USUB8:
18554 case ARM::t2USUB16: {
18555 switch (OpNum) {
18556 case 0:
18557 // op: Rd
18558 return 8;
18559 case 1:
18560 // op: Rn
18561 return 16;
18562 case 2:
18563 // op: Rm
18564 return 0;
18565 }
18566 break;
18567 }
18568 case ARM::t2ADDri12:
18569 case ARM::t2SUBri12: {
18570 switch (OpNum) {
18571 case 0:
18572 // op: Rd
18573 return 8;
18574 case 1:
18575 // op: Rn
18576 return 16;
18577 case 2:
18578 // op: imm
18579 return 0;
18580 }
18581 break;
18582 }
18583 case ARM::t2STREX: {
18584 switch (OpNum) {
18585 case 0:
18586 // op: Rd
18587 return 8;
18588 case 1:
18589 // op: Rt
18590 return 12;
18591 case 2:
18592 // op: addr
18593 return 0;
18594 }
18595 break;
18596 }
18597 case ARM::t2MRS_M: {
18598 switch (OpNum) {
18599 case 0:
18600 // op: Rd
18601 return 8;
18602 case 1:
18603 // op: SYSm
18604 return 0;
18605 }
18606 break;
18607 }
18608 case ARM::t2ADR:
18609 case ARM::tADR: {
18610 switch (OpNum) {
18611 case 0:
18612 // op: Rd
18613 return 8;
18614 case 1:
18615 // op: addr
18616 return 0;
18617 }
18618 break;
18619 }
18620 case ARM::t2MOVi16: {
18621 switch (OpNum) {
18622 case 0:
18623 // op: Rd
18624 return 8;
18625 case 1:
18626 // op: imm
18627 return 0;
18628 }
18629 break;
18630 }
18631 case ARM::t2CSEL:
18632 case ARM::t2CSINC:
18633 case ARM::t2CSINV:
18634 case ARM::t2CSNEG: {
18635 switch (OpNum) {
18636 case 0:
18637 // op: Rd
18638 return 8;
18639 case 2:
18640 // op: Rm
18641 return 0;
18642 case 1:
18643 // op: Rn
18644 return 16;
18645 case 3:
18646 // op: fcond
18647 return 4;
18648 }
18649 break;
18650 }
18651 case ARM::t2QADD:
18652 case ARM::t2QDADD:
18653 case ARM::t2QDSUB:
18654 case ARM::t2QSUB: {
18655 switch (OpNum) {
18656 case 0:
18657 // op: Rd
18658 return 8;
18659 case 2:
18660 // op: Rn
18661 return 16;
18662 case 1:
18663 // op: Rm
18664 return 0;
18665 }
18666 break;
18667 }
18668 case ARM::t2SSAT:
18669 case ARM::t2USAT: {
18670 switch (OpNum) {
18671 case 0:
18672 // op: Rd
18673 return 8;
18674 case 2:
18675 // op: Rn
18676 return 16;
18677 case 1:
18678 // op: sat_imm
18679 return 0;
18680 case 3:
18681 // op: sh
18682 return 6;
18683 }
18684 break;
18685 }
18686 case ARM::t2SSAT16:
18687 case ARM::t2USAT16: {
18688 switch (OpNum) {
18689 case 0:
18690 // op: Rd
18691 return 8;
18692 case 2:
18693 // op: Rn
18694 return 16;
18695 case 1:
18696 // op: sat_imm
18697 return 0;
18698 }
18699 break;
18700 }
18701 case ARM::t2BFI: {
18702 switch (OpNum) {
18703 case 0:
18704 // op: Rd
18705 return 8;
18706 case 2:
18707 // op: Rn
18708 return 16;
18709 case 3:
18710 // op: imm
18711 return 0;
18712 }
18713 break;
18714 }
18715 case ARM::t2BFC:
18716 case ARM::t2MOVTi16: {
18717 switch (OpNum) {
18718 case 0:
18719 // op: Rd
18720 return 8;
18721 case 2:
18722 // op: imm
18723 return 0;
18724 }
18725 break;
18726 }
18727 case ARM::tMOVi8: {
18728 switch (OpNum) {
18729 case 0:
18730 // op: Rd
18731 return 8;
18732 case 2:
18733 // op: imm8
18734 return 0;
18735 }
18736 break;
18737 }
18738 case ARM::t2PACG: {
18739 switch (OpNum) {
18740 case 0:
18741 // op: Rd
18742 return 8;
18743 case 3:
18744 // op: Rn
18745 return 16;
18746 case 4:
18747 // op: Rm
18748 return 0;
18749 }
18750 break;
18751 }
18752 case ARM::t2SBFX:
18753 case ARM::t2UBFX: {
18754 switch (OpNum) {
18755 case 0:
18756 // op: Rd
18757 return 8;
18758 case 3:
18759 // op: msb
18760 return 0;
18761 case 2:
18762 // op: lsb
18763 return 6;
18764 case 1:
18765 // op: Rn
18766 return 16;
18767 }
18768 break;
18769 }
18770 case ARM::t2MRS_AR:
18771 case ARM::t2MRSsys_AR: {
18772 switch (OpNum) {
18773 case 0:
18774 // op: Rd
18775 return 8;
18776 }
18777 break;
18778 }
18779 case ARM::t2SMLAL:
18780 case ARM::t2SMLALBB:
18781 case ARM::t2SMLALBT:
18782 case ARM::t2SMLALTB:
18783 case ARM::t2SMLALTT:
18784 case ARM::t2SMULL:
18785 case ARM::t2UMAAL:
18786 case ARM::t2UMLAL:
18787 case ARM::t2UMULL: {
18788 switch (OpNum) {
18789 case 0:
18790 // op: RdLo
18791 return 12;
18792 case 1:
18793 // op: RdHi
18794 return 8;
18795 case 2:
18796 // op: Rn
18797 return 16;
18798 case 3:
18799 // op: Rm
18800 return 0;
18801 }
18802 break;
18803 }
18804 case ARM::MVE_VMLADAVs8:
18805 case ARM::MVE_VMLADAVs16:
18806 case ARM::MVE_VMLADAVs32:
18807 case ARM::MVE_VMLADAVu8:
18808 case ARM::MVE_VMLADAVu16:
18809 case ARM::MVE_VMLADAVu32:
18810 case ARM::MVE_VMLADAVxs8:
18811 case ARM::MVE_VMLADAVxs16:
18812 case ARM::MVE_VMLADAVxs32:
18813 case ARM::MVE_VMLSDAVs8:
18814 case ARM::MVE_VMLSDAVs16:
18815 case ARM::MVE_VMLSDAVs32:
18816 case ARM::MVE_VMLSDAVxs8:
18817 case ARM::MVE_VMLSDAVxs16:
18818 case ARM::MVE_VMLSDAVxs32: {
18819 switch (OpNum) {
18820 case 0:
18821 // op: RdaDest
18822 return 13;
18823 case 2:
18824 // op: Qm
18825 return 1;
18826 case 1:
18827 // op: Qn
18828 return 17;
18829 }
18830 break;
18831 }
18832 case ARM::MVE_VMLADAVas8:
18833 case ARM::MVE_VMLADAVas16:
18834 case ARM::MVE_VMLADAVas32:
18835 case ARM::MVE_VMLADAVau8:
18836 case ARM::MVE_VMLADAVau16:
18837 case ARM::MVE_VMLADAVau32:
18838 case ARM::MVE_VMLADAVaxs8:
18839 case ARM::MVE_VMLADAVaxs16:
18840 case ARM::MVE_VMLADAVaxs32:
18841 case ARM::MVE_VMLSDAVas8:
18842 case ARM::MVE_VMLSDAVas16:
18843 case ARM::MVE_VMLSDAVas32:
18844 case ARM::MVE_VMLSDAVaxs8:
18845 case ARM::MVE_VMLSDAVaxs16:
18846 case ARM::MVE_VMLSDAVaxs32: {
18847 switch (OpNum) {
18848 case 0:
18849 // op: RdaDest
18850 return 13;
18851 case 3:
18852 // op: Qm
18853 return 1;
18854 case 2:
18855 // op: Qn
18856 return 17;
18857 }
18858 break;
18859 }
18860 case ARM::MVE_SQRSHR:
18861 case ARM::MVE_UQRSHL: {
18862 switch (OpNum) {
18863 case 0:
18864 // op: RdaDest
18865 return 16;
18866 case 2:
18867 // op: Rm
18868 return 12;
18869 }
18870 break;
18871 }
18872 case ARM::MVE_SQSHL:
18873 case ARM::MVE_SRSHR:
18874 case ARM::MVE_UQSHL:
18875 case ARM::MVE_URSHR: {
18876 switch (OpNum) {
18877 case 0:
18878 // op: RdaDest
18879 return 16;
18880 case 2:
18881 // op: imm
18882 return 6;
18883 }
18884 break;
18885 }
18886 case ARM::MVE_SQRSHRL:
18887 case ARM::MVE_UQRSHLL: {
18888 switch (OpNum) {
18889 case 0:
18890 // op: RdaLo
18891 return 17;
18892 case 1:
18893 // op: RdaHi
18894 return 9;
18895 case 4:
18896 // op: Rm
18897 return 12;
18898 case 5:
18899 // op: sat
18900 return 7;
18901 }
18902 break;
18903 }
18904 case ARM::MVE_ASRLr:
18905 case ARM::MVE_LSLLr: {
18906 switch (OpNum) {
18907 case 0:
18908 // op: RdaLo
18909 return 17;
18910 case 1:
18911 // op: RdaHi
18912 return 9;
18913 case 4:
18914 // op: Rm
18915 return 12;
18916 }
18917 break;
18918 }
18919 case ARM::MVE_ASRLi:
18920 case ARM::MVE_LSLLi:
18921 case ARM::MVE_LSRL:
18922 case ARM::MVE_SQSHLL:
18923 case ARM::MVE_SRSHRL:
18924 case ARM::MVE_UQSHLL:
18925 case ARM::MVE_URSHRL: {
18926 switch (OpNum) {
18927 case 0:
18928 // op: RdaLo
18929 return 17;
18930 case 1:
18931 // op: RdaHi
18932 return 9;
18933 case 4:
18934 // op: imm
18935 return 6;
18936 }
18937 break;
18938 }
18939 case ARM::MVE_VMLALDAVs16:
18940 case ARM::MVE_VMLALDAVs32:
18941 case ARM::MVE_VMLALDAVu16:
18942 case ARM::MVE_VMLALDAVu32:
18943 case ARM::MVE_VMLALDAVxs16:
18944 case ARM::MVE_VMLALDAVxs32:
18945 case ARM::MVE_VMLSLDAVs16:
18946 case ARM::MVE_VMLSLDAVs32:
18947 case ARM::MVE_VMLSLDAVxs16:
18948 case ARM::MVE_VMLSLDAVxs32:
18949 case ARM::MVE_VRMLALDAVHs32:
18950 case ARM::MVE_VRMLALDAVHu32:
18951 case ARM::MVE_VRMLALDAVHxs32:
18952 case ARM::MVE_VRMLSLDAVHs32:
18953 case ARM::MVE_VRMLSLDAVHxs32: {
18954 switch (OpNum) {
18955 case 0:
18956 // op: RdaLoDest
18957 return 13;
18958 case 1:
18959 // op: RdaHiDest
18960 return 20;
18961 case 3:
18962 // op: Qm
18963 return 1;
18964 case 2:
18965 // op: Qn
18966 return 17;
18967 }
18968 break;
18969 }
18970 case ARM::MVE_VMLALDAVas16:
18971 case ARM::MVE_VMLALDAVas32:
18972 case ARM::MVE_VMLALDAVau16:
18973 case ARM::MVE_VMLALDAVau32:
18974 case ARM::MVE_VMLALDAVaxs16:
18975 case ARM::MVE_VMLALDAVaxs32:
18976 case ARM::MVE_VMLSLDAVas16:
18977 case ARM::MVE_VMLSLDAVas32:
18978 case ARM::MVE_VMLSLDAVaxs16:
18979 case ARM::MVE_VMLSLDAVaxs32:
18980 case ARM::MVE_VRMLALDAVHas32:
18981 case ARM::MVE_VRMLALDAVHau32:
18982 case ARM::MVE_VRMLALDAVHaxs32:
18983 case ARM::MVE_VRMLSLDAVHas32:
18984 case ARM::MVE_VRMLSLDAVHaxs32: {
18985 switch (OpNum) {
18986 case 0:
18987 // op: RdaLoDest
18988 return 13;
18989 case 1:
18990 // op: RdaHiDest
18991 return 20;
18992 case 5:
18993 // op: Qm
18994 return 1;
18995 case 4:
18996 // op: Qn
18997 return 17;
18998 }
18999 break;
19000 }
19001 case ARM::tADDhirr: {
19002 switch (OpNum) {
19003 case 0:
19004 // op: Rdn
19005 return 0;
19006 case 2:
19007 // op: Rm
19008 return 3;
19009 }
19010 break;
19011 }
19012 case ARM::tADC:
19013 case ARM::tAND:
19014 case ARM::tASRrr:
19015 case ARM::tBIC:
19016 case ARM::tEOR:
19017 case ARM::tLSLrr:
19018 case ARM::tLSRrr:
19019 case ARM::tORR:
19020 case ARM::tROR:
19021 case ARM::tSBC: {
19022 switch (OpNum) {
19023 case 0:
19024 // op: Rdn
19025 return 0;
19026 case 3:
19027 // op: Rm
19028 return 3;
19029 }
19030 break;
19031 }
19032 case ARM::tADDrSP: {
19033 switch (OpNum) {
19034 case 0:
19035 // op: Rdn
19036 return 0;
19037 }
19038 break;
19039 }
19040 case ARM::tADDi8:
19041 case ARM::tSUBi8: {
19042 switch (OpNum) {
19043 case 0:
19044 // op: Rdn
19045 return 8;
19046 case 3:
19047 // op: imm8
19048 return 0;
19049 }
19050 break;
19051 }
19052 case ARM::tBX:
19053 case ARM::tBXNS: {
19054 switch (OpNum) {
19055 case 0:
19056 // op: Rm
19057 return 3;
19058 }
19059 break;
19060 }
19061 case ARM::t2CMNzrr:
19062 case ARM::t2CMPrr:
19063 case ARM::t2TBB:
19064 case ARM::t2TBH:
19065 case ARM::t2TEQrr:
19066 case ARM::t2TSTrr: {
19067 switch (OpNum) {
19068 case 0:
19069 // op: Rn
19070 return 16;
19071 case 1:
19072 // op: Rm
19073 return 0;
19074 }
19075 break;
19076 }
19077 case ARM::t2CMNzrs:
19078 case ARM::t2CMPrs:
19079 case ARM::t2TEQrs:
19080 case ARM::t2TSTrs: {
19081 switch (OpNum) {
19082 case 0:
19083 // op: Rn
19084 return 16;
19085 case 1:
19086 // op: ShiftedRm
19087 return 0;
19088 }
19089 break;
19090 }
19091 case ARM::t2CMNri:
19092 case ARM::t2CMPri:
19093 case ARM::t2TEQri:
19094 case ARM::t2TSTri: {
19095 switch (OpNum) {
19096 case 0:
19097 // op: Rn
19098 return 16;
19099 case 1:
19100 // op: imm
19101 return 0;
19102 }
19103 break;
19104 }
19105 case ARM::t2LDMDB:
19106 case ARM::t2LDMIA:
19107 case ARM::t2STMDB:
19108 case ARM::t2STMIA: {
19109 switch (OpNum) {
19110 case 0:
19111 // op: Rn
19112 return 16;
19113 case 3:
19114 // op: regs
19115 return 0;
19116 }
19117 break;
19118 }
19119 case ARM::RFEDA:
19120 case ARM::RFEDA_UPD:
19121 case ARM::RFEDB:
19122 case ARM::RFEDB_UPD:
19123 case ARM::RFEIA:
19124 case ARM::RFEIA_UPD:
19125 case ARM::RFEIB:
19126 case ARM::RFEIB_UPD:
19127 case ARM::VLLDM:
19128 case ARM::VLLDM_T2:
19129 case ARM::VLSTM:
19130 case ARM::VLSTM_T2:
19131 case ARM::t2RFEDB:
19132 case ARM::t2RFEDBW:
19133 case ARM::t2RFEIA:
19134 case ARM::t2RFEIAW: {
19135 switch (OpNum) {
19136 case 0:
19137 // op: Rn
19138 return 16;
19139 }
19140 break;
19141 }
19142 case ARM::tCMPi8: {
19143 switch (OpNum) {
19144 case 0:
19145 // op: Rn
19146 return 8;
19147 case 1:
19148 // op: imm8
19149 return 0;
19150 }
19151 break;
19152 }
19153 case ARM::tLDMIA: {
19154 switch (OpNum) {
19155 case 0:
19156 // op: Rn
19157 return 8;
19158 case 3:
19159 // op: regs
19160 return 0;
19161 }
19162 break;
19163 }
19164 case ARM::MVE_VMOV_rr_q: {
19165 switch (OpNum) {
19166 case 0:
19167 // op: Rt
19168 return 0;
19169 case 1:
19170 // op: Rt2
19171 return 16;
19172 case 2:
19173 // op: Qd
19174 return 13;
19175 case 4:
19176 // op: idx2
19177 return 4;
19178 }
19179 break;
19180 }
19181 case ARM::tLDRBi:
19182 case ARM::tLDRBr:
19183 case ARM::tLDRHi:
19184 case ARM::tLDRHr:
19185 case ARM::tLDRSB:
19186 case ARM::tLDRSH:
19187 case ARM::tLDRi:
19188 case ARM::tLDRr:
19189 case ARM::tSTRBi:
19190 case ARM::tSTRBr:
19191 case ARM::tSTRHi:
19192 case ARM::tSTRHr:
19193 case ARM::tSTRi:
19194 case ARM::tSTRr: {
19195 switch (OpNum) {
19196 case 0:
19197 // op: Rt
19198 return 0;
19199 case 1:
19200 // op: addr
19201 return 3;
19202 }
19203 break;
19204 }
19205 case ARM::MRRC2:
19206 case ARM::t2MRRC:
19207 case ARM::t2MRRC2: {
19208 switch (OpNum) {
19209 case 0:
19210 // op: Rt
19211 return 12;
19212 case 1:
19213 // op: Rt2
19214 return 16;
19215 case 2:
19216 // op: cop
19217 return 8;
19218 case 3:
19219 // op: opc1
19220 return 4;
19221 case 4:
19222 // op: CRm
19223 return 0;
19224 }
19225 break;
19226 }
19227 case ARM::t2LDRDi8:
19228 case ARM::t2STRDi8: {
19229 switch (OpNum) {
19230 case 0:
19231 // op: Rt
19232 return 12;
19233 case 1:
19234 // op: Rt2
19235 return 8;
19236 case 2:
19237 // op: addr
19238 return 0;
19239 }
19240 break;
19241 }
19242 case ARM::t2LDRD_PRE: {
19243 switch (OpNum) {
19244 case 0:
19245 // op: Rt
19246 return 12;
19247 case 1:
19248 // op: Rt2
19249 return 8;
19250 case 3:
19251 // op: addr
19252 return 0;
19253 }
19254 break;
19255 }
19256 case ARM::t2LDRD_POST: {
19257 switch (OpNum) {
19258 case 0:
19259 // op: Rt
19260 return 12;
19261 case 1:
19262 // op: Rt2
19263 return 8;
19264 case 3:
19265 // op: addr
19266 return 16;
19267 case 4:
19268 // op: imm
19269 return 0;
19270 }
19271 break;
19272 }
19273 case ARM::t2LDRBT:
19274 case ARM::t2LDRBi8:
19275 case ARM::t2LDRBi12:
19276 case ARM::t2LDRBpci:
19277 case ARM::t2LDRBs:
19278 case ARM::t2LDREX:
19279 case ARM::t2LDRHT:
19280 case ARM::t2LDRHi8:
19281 case ARM::t2LDRHi12:
19282 case ARM::t2LDRHpci:
19283 case ARM::t2LDRHs:
19284 case ARM::t2LDRSBT:
19285 case ARM::t2LDRSBi8:
19286 case ARM::t2LDRSBi12:
19287 case ARM::t2LDRSBpci:
19288 case ARM::t2LDRSBs:
19289 case ARM::t2LDRSHT:
19290 case ARM::t2LDRSHi8:
19291 case ARM::t2LDRSHi12:
19292 case ARM::t2LDRSHpci:
19293 case ARM::t2LDRSHs:
19294 case ARM::t2LDRT:
19295 case ARM::t2LDRi8:
19296 case ARM::t2LDRi12:
19297 case ARM::t2LDRpci:
19298 case ARM::t2LDRs:
19299 case ARM::t2STRBT:
19300 case ARM::t2STRBi8:
19301 case ARM::t2STRBi12:
19302 case ARM::t2STRBs:
19303 case ARM::t2STRHT:
19304 case ARM::t2STRHi8:
19305 case ARM::t2STRHi12:
19306 case ARM::t2STRHs:
19307 case ARM::t2STRT:
19308 case ARM::t2STRi8:
19309 case ARM::t2STRi12:
19310 case ARM::t2STRs: {
19311 switch (OpNum) {
19312 case 0:
19313 // op: Rt
19314 return 12;
19315 case 1:
19316 // op: addr
19317 return 0;
19318 }
19319 break;
19320 }
19321 case ARM::t2LDA:
19322 case ARM::t2LDAB:
19323 case ARM::t2LDAEX:
19324 case ARM::t2LDAH:
19325 case ARM::t2STL:
19326 case ARM::t2STLB:
19327 case ARM::t2STLH: {
19328 switch (OpNum) {
19329 case 0:
19330 // op: Rt
19331 return 12;
19332 case 1:
19333 // op: addr
19334 return 16;
19335 }
19336 break;
19337 }
19338 case ARM::MRC2:
19339 case ARM::t2MRC:
19340 case ARM::t2MRC2: {
19341 switch (OpNum) {
19342 case 0:
19343 // op: Rt
19344 return 12;
19345 case 1:
19346 // op: cop
19347 return 8;
19348 case 2:
19349 // op: opc1
19350 return 21;
19351 case 5:
19352 // op: opc2
19353 return 5;
19354 case 4:
19355 // op: CRm
19356 return 0;
19357 case 3:
19358 // op: CRn
19359 return 16;
19360 }
19361 break;
19362 }
19363 case ARM::t2LDRB_POST:
19364 case ARM::t2LDRH_POST:
19365 case ARM::t2LDRSB_POST:
19366 case ARM::t2LDRSH_POST:
19367 case ARM::t2LDR_POST: {
19368 switch (OpNum) {
19369 case 0:
19370 // op: Rt
19371 return 12;
19372 case 2:
19373 // op: Rn
19374 return 16;
19375 case 3:
19376 // op: offset
19377 return 0;
19378 }
19379 break;
19380 }
19381 case ARM::t2LDRB_PRE:
19382 case ARM::t2LDRH_PRE:
19383 case ARM::t2LDRSB_PRE:
19384 case ARM::t2LDRSH_PRE:
19385 case ARM::t2LDR_PRE: {
19386 switch (OpNum) {
19387 case 0:
19388 // op: Rt
19389 return 12;
19390 case 2:
19391 // op: addr
19392 return 0;
19393 }
19394 break;
19395 }
19396 case ARM::tLDRpci:
19397 case ARM::tLDRspi:
19398 case ARM::tSTRspi: {
19399 switch (OpNum) {
19400 case 0:
19401 // op: Rt
19402 return 8;
19403 case 1:
19404 // op: addr
19405 return 0;
19406 }
19407 break;
19408 }
19409 case ARM::t2MSR_M: {
19410 switch (OpNum) {
19411 case 0:
19412 // op: SYSm
19413 return 0;
19414 case 1:
19415 // op: Rn
19416 return 16;
19417 }
19418 break;
19419 }
19420 case ARM::VCVTASD:
19421 case ARM::VCVTAUD:
19422 case ARM::VCVTMSD:
19423 case ARM::VCVTMUD:
19424 case ARM::VCVTNSD:
19425 case ARM::VCVTNUD:
19426 case ARM::VCVTPSD:
19427 case ARM::VCVTPUD: {
19428 switch (OpNum) {
19429 case 0:
19430 // op: Sd
19431 return 12;
19432 case 1:
19433 // op: Dm
19434 return 0;
19435 }
19436 break;
19437 }
19438 case ARM::VCVTASH:
19439 case ARM::VCVTASS:
19440 case ARM::VCVTAUH:
19441 case ARM::VCVTAUS:
19442 case ARM::VCVTMSH:
19443 case ARM::VCVTMSS:
19444 case ARM::VCVTMUH:
19445 case ARM::VCVTMUS:
19446 case ARM::VCVTNSH:
19447 case ARM::VCVTNSS:
19448 case ARM::VCVTNUH:
19449 case ARM::VCVTNUS:
19450 case ARM::VCVTPSH:
19451 case ARM::VCVTPSS:
19452 case ARM::VCVTPUH:
19453 case ARM::VCVTPUS:
19454 case ARM::VMOVH:
19455 case ARM::VRINTAH:
19456 case ARM::VRINTAS:
19457 case ARM::VRINTMH:
19458 case ARM::VRINTMS:
19459 case ARM::VRINTNH:
19460 case ARM::VRINTNS:
19461 case ARM::VRINTPH:
19462 case ARM::VRINTPS: {
19463 switch (OpNum) {
19464 case 0:
19465 // op: Sd
19466 return 12;
19467 case 1:
19468 // op: Sm
19469 return 0;
19470 }
19471 break;
19472 }
19473 case ARM::VFP_VMAXNMH:
19474 case ARM::VFP_VMAXNMS:
19475 case ARM::VFP_VMINNMH:
19476 case ARM::VFP_VMINNMS:
19477 case ARM::VSELEQH:
19478 case ARM::VSELEQS:
19479 case ARM::VSELGEH:
19480 case ARM::VSELGES:
19481 case ARM::VSELGTH:
19482 case ARM::VSELGTS:
19483 case ARM::VSELVSH:
19484 case ARM::VSELVSS: {
19485 switch (OpNum) {
19486 case 0:
19487 // op: Sd
19488 return 12;
19489 case 1:
19490 // op: Sn
19491 return 7;
19492 case 2:
19493 // op: Sm
19494 return 0;
19495 }
19496 break;
19497 }
19498 case ARM::VINSH: {
19499 switch (OpNum) {
19500 case 0:
19501 // op: Sd
19502 return 12;
19503 case 2:
19504 // op: Sm
19505 return 0;
19506 }
19507 break;
19508 }
19509 case ARM::VDUP8d:
19510 case ARM::VDUP8q:
19511 case ARM::VDUP16d:
19512 case ARM::VDUP16q:
19513 case ARM::VDUP32d:
19514 case ARM::VDUP32q: {
19515 switch (OpNum) {
19516 case 0:
19517 // op: V
19518 return 7;
19519 case 1:
19520 // op: R
19521 return 12;
19522 case 2:
19523 // op: p
19524 return 28;
19525 }
19526 break;
19527 }
19528 case ARM::VSETLNi32: {
19529 switch (OpNum) {
19530 case 0:
19531 // op: V
19532 return 7;
19533 case 2:
19534 // op: R
19535 return 12;
19536 case 4:
19537 // op: p
19538 return 28;
19539 case 3:
19540 // op: lane
19541 return 21;
19542 }
19543 break;
19544 }
19545 case ARM::VSETLNi8: {
19546 switch (OpNum) {
19547 case 0:
19548 // op: V
19549 return 7;
19550 case 2:
19551 // op: R
19552 return 12;
19553 case 4:
19554 // op: p
19555 return 28;
19556 case 3:
19557 // op: lane
19558 return 5;
19559 }
19560 break;
19561 }
19562 case ARM::VSETLNi16: {
19563 switch (OpNum) {
19564 case 0:
19565 // op: V
19566 return 7;
19567 case 2:
19568 // op: R
19569 return 12;
19570 case 4:
19571 // op: p
19572 return 28;
19573 case 3:
19574 // op: lane
19575 return 6;
19576 }
19577 break;
19578 }
19579 case ARM::MVE_VST20_8:
19580 case ARM::MVE_VST20_16:
19581 case ARM::MVE_VST20_32:
19582 case ARM::MVE_VST21_8:
19583 case ARM::MVE_VST21_16:
19584 case ARM::MVE_VST21_32:
19585 case ARM::MVE_VST40_8:
19586 case ARM::MVE_VST40_16:
19587 case ARM::MVE_VST40_32:
19588 case ARM::MVE_VST41_8:
19589 case ARM::MVE_VST41_16:
19590 case ARM::MVE_VST41_32:
19591 case ARM::MVE_VST42_8:
19592 case ARM::MVE_VST42_16:
19593 case ARM::MVE_VST42_32:
19594 case ARM::MVE_VST43_8:
19595 case ARM::MVE_VST43_16:
19596 case ARM::MVE_VST43_32: {
19597 switch (OpNum) {
19598 case 0:
19599 // op: VQd
19600 return 13;
19601 case 1:
19602 // op: Rn
19603 return 16;
19604 }
19605 break;
19606 }
19607 case ARM::MVE_VLD20_8:
19608 case ARM::MVE_VLD20_16:
19609 case ARM::MVE_VLD20_32:
19610 case ARM::MVE_VLD21_8:
19611 case ARM::MVE_VLD21_16:
19612 case ARM::MVE_VLD21_32:
19613 case ARM::MVE_VLD40_8:
19614 case ARM::MVE_VLD40_16:
19615 case ARM::MVE_VLD40_32:
19616 case ARM::MVE_VLD41_8:
19617 case ARM::MVE_VLD41_16:
19618 case ARM::MVE_VLD41_32:
19619 case ARM::MVE_VLD42_8:
19620 case ARM::MVE_VLD42_16:
19621 case ARM::MVE_VLD42_32:
19622 case ARM::MVE_VLD43_8:
19623 case ARM::MVE_VLD43_16:
19624 case ARM::MVE_VLD43_32: {
19625 switch (OpNum) {
19626 case 0:
19627 // op: VQd
19628 return 13;
19629 case 2:
19630 // op: Rn
19631 return 16;
19632 }
19633 break;
19634 }
19635 case ARM::MVE_VLD20_8_wb:
19636 case ARM::MVE_VLD20_16_wb:
19637 case ARM::MVE_VLD20_32_wb:
19638 case ARM::MVE_VLD21_8_wb:
19639 case ARM::MVE_VLD21_16_wb:
19640 case ARM::MVE_VLD21_32_wb:
19641 case ARM::MVE_VLD40_8_wb:
19642 case ARM::MVE_VLD40_16_wb:
19643 case ARM::MVE_VLD40_32_wb:
19644 case ARM::MVE_VLD41_8_wb:
19645 case ARM::MVE_VLD41_16_wb:
19646 case ARM::MVE_VLD41_32_wb:
19647 case ARM::MVE_VLD42_8_wb:
19648 case ARM::MVE_VLD42_16_wb:
19649 case ARM::MVE_VLD42_32_wb:
19650 case ARM::MVE_VLD43_8_wb:
19651 case ARM::MVE_VLD43_16_wb:
19652 case ARM::MVE_VLD43_32_wb: {
19653 switch (OpNum) {
19654 case 0:
19655 // op: VQd
19656 return 13;
19657 case 3:
19658 // op: Rn
19659 return 16;
19660 }
19661 break;
19662 }
19663 case ARM::VLD1LNd8: {
19664 switch (OpNum) {
19665 case 0:
19666 // op: Vd
19667 return 12;
19668 case 1:
19669 // op: Rn
19670 return 16;
19671 case 4:
19672 // op: lane
19673 return 5;
19674 }
19675 break;
19676 }
19677 case ARM::VLD1LNd16: {
19678 switch (OpNum) {
19679 case 0:
19680 // op: Vd
19681 return 12;
19682 case 1:
19683 // op: Rn
19684 return 4;
19685 case 4:
19686 // op: lane
19687 return 6;
19688 }
19689 break;
19690 }
19691 case ARM::VLD1LNd32: {
19692 switch (OpNum) {
19693 case 0:
19694 // op: Vd
19695 return 12;
19696 case 1:
19697 // op: Rn
19698 return 4;
19699 case 4:
19700 // op: lane
19701 return 7;
19702 }
19703 break;
19704 }
19705 case ARM::VLD1DUPd8:
19706 case ARM::VLD1DUPd16:
19707 case ARM::VLD1DUPd32:
19708 case ARM::VLD1DUPq8:
19709 case ARM::VLD1DUPq16:
19710 case ARM::VLD1DUPq32:
19711 case ARM::VLD1d8:
19712 case ARM::VLD1d8Q:
19713 case ARM::VLD1d8T:
19714 case ARM::VLD1d16:
19715 case ARM::VLD1d16Q:
19716 case ARM::VLD1d16T:
19717 case ARM::VLD1d32:
19718 case ARM::VLD1d32Q:
19719 case ARM::VLD1d32T:
19720 case ARM::VLD1d64:
19721 case ARM::VLD1d64Q:
19722 case ARM::VLD1d64T:
19723 case ARM::VLD1q8:
19724 case ARM::VLD1q16:
19725 case ARM::VLD1q32:
19726 case ARM::VLD1q64:
19727 case ARM::VLD2DUPd8:
19728 case ARM::VLD2DUPd8x2:
19729 case ARM::VLD2DUPd16:
19730 case ARM::VLD2DUPd16x2:
19731 case ARM::VLD2DUPd32:
19732 case ARM::VLD2DUPd32x2:
19733 case ARM::VLD2b8:
19734 case ARM::VLD2b16:
19735 case ARM::VLD2b32:
19736 case ARM::VLD2d8:
19737 case ARM::VLD2d16:
19738 case ARM::VLD2d32:
19739 case ARM::VLD2q8:
19740 case ARM::VLD2q16:
19741 case ARM::VLD2q32: {
19742 switch (OpNum) {
19743 case 0:
19744 // op: Vd
19745 return 12;
19746 case 1:
19747 // op: Rn
19748 return 4;
19749 }
19750 break;
19751 }
19752 case ARM::VBICiv2i32:
19753 case ARM::VBICiv4i16:
19754 case ARM::VBICiv4i32:
19755 case ARM::VBICiv8i16:
19756 case ARM::VMOVv1i64:
19757 case ARM::VMOVv2f32:
19758 case ARM::VMOVv2i32:
19759 case ARM::VMOVv2i64:
19760 case ARM::VMOVv4f32:
19761 case ARM::VMOVv4i16:
19762 case ARM::VMOVv4i32:
19763 case ARM::VMOVv8i8:
19764 case ARM::VMOVv8i16:
19765 case ARM::VMOVv16i8:
19766 case ARM::VMVNv2i32:
19767 case ARM::VMVNv4i16:
19768 case ARM::VMVNv4i32:
19769 case ARM::VMVNv8i16:
19770 case ARM::VORRiv2i32:
19771 case ARM::VORRiv4i16:
19772 case ARM::VORRiv4i32:
19773 case ARM::VORRiv8i16: {
19774 switch (OpNum) {
19775 case 0:
19776 // op: Vd
19777 return 12;
19778 case 1:
19779 // op: SIMM
19780 return 0;
19781 }
19782 break;
19783 }
19784 case ARM::VCVTf2xsd:
19785 case ARM::VCVTf2xsq:
19786 case ARM::VCVTf2xud:
19787 case ARM::VCVTf2xuq:
19788 case ARM::VCVTh2xsd:
19789 case ARM::VCVTh2xsq:
19790 case ARM::VCVTh2xud:
19791 case ARM::VCVTh2xuq:
19792 case ARM::VCVTxs2fd:
19793 case ARM::VCVTxs2fq:
19794 case ARM::VCVTxs2hd:
19795 case ARM::VCVTxs2hq:
19796 case ARM::VCVTxu2fd:
19797 case ARM::VCVTxu2fq:
19798 case ARM::VCVTxu2hd:
19799 case ARM::VCVTxu2hq:
19800 case ARM::VQRSHRNsv2i32:
19801 case ARM::VQRSHRNsv4i16:
19802 case ARM::VQRSHRNsv8i8:
19803 case ARM::VQRSHRNuv2i32:
19804 case ARM::VQRSHRNuv4i16:
19805 case ARM::VQRSHRNuv8i8:
19806 case ARM::VQRSHRUNv2i32:
19807 case ARM::VQRSHRUNv4i16:
19808 case ARM::VQRSHRUNv8i8:
19809 case ARM::VQSHLsiv1i64:
19810 case ARM::VQSHLsiv2i32:
19811 case ARM::VQSHLsiv2i64:
19812 case ARM::VQSHLsiv4i16:
19813 case ARM::VQSHLsiv4i32:
19814 case ARM::VQSHLsiv8i8:
19815 case ARM::VQSHLsiv8i16:
19816 case ARM::VQSHLsiv16i8:
19817 case ARM::VQSHLsuv1i64:
19818 case ARM::VQSHLsuv2i32:
19819 case ARM::VQSHLsuv2i64:
19820 case ARM::VQSHLsuv4i16:
19821 case ARM::VQSHLsuv4i32:
19822 case ARM::VQSHLsuv8i8:
19823 case ARM::VQSHLsuv8i16:
19824 case ARM::VQSHLsuv16i8:
19825 case ARM::VQSHLuiv1i64:
19826 case ARM::VQSHLuiv2i32:
19827 case ARM::VQSHLuiv2i64:
19828 case ARM::VQSHLuiv4i16:
19829 case ARM::VQSHLuiv4i32:
19830 case ARM::VQSHLuiv8i8:
19831 case ARM::VQSHLuiv8i16:
19832 case ARM::VQSHLuiv16i8:
19833 case ARM::VQSHRNsv2i32:
19834 case ARM::VQSHRNsv4i16:
19835 case ARM::VQSHRNsv8i8:
19836 case ARM::VQSHRNuv2i32:
19837 case ARM::VQSHRNuv4i16:
19838 case ARM::VQSHRNuv8i8:
19839 case ARM::VQSHRUNv2i32:
19840 case ARM::VQSHRUNv4i16:
19841 case ARM::VQSHRUNv8i8:
19842 case ARM::VRSHRNv2i32:
19843 case ARM::VRSHRNv4i16:
19844 case ARM::VRSHRNv8i8:
19845 case ARM::VRSHRsv1i64:
19846 case ARM::VRSHRsv2i32:
19847 case ARM::VRSHRsv2i64:
19848 case ARM::VRSHRsv4i16:
19849 case ARM::VRSHRsv4i32:
19850 case ARM::VRSHRsv8i8:
19851 case ARM::VRSHRsv8i16:
19852 case ARM::VRSHRsv16i8:
19853 case ARM::VRSHRuv1i64:
19854 case ARM::VRSHRuv2i32:
19855 case ARM::VRSHRuv2i64:
19856 case ARM::VRSHRuv4i16:
19857 case ARM::VRSHRuv4i32:
19858 case ARM::VRSHRuv8i8:
19859 case ARM::VRSHRuv8i16:
19860 case ARM::VRSHRuv16i8:
19861 case ARM::VSHLLsv2i64:
19862 case ARM::VSHLLsv4i32:
19863 case ARM::VSHLLsv8i16:
19864 case ARM::VSHLLuv2i64:
19865 case ARM::VSHLLuv4i32:
19866 case ARM::VSHLLuv8i16:
19867 case ARM::VSHLiv1i64:
19868 case ARM::VSHLiv2i32:
19869 case ARM::VSHLiv2i64:
19870 case ARM::VSHLiv4i16:
19871 case ARM::VSHLiv4i32:
19872 case ARM::VSHLiv8i8:
19873 case ARM::VSHLiv8i16:
19874 case ARM::VSHLiv16i8:
19875 case ARM::VSHRNv2i32:
19876 case ARM::VSHRNv4i16:
19877 case ARM::VSHRNv8i8:
19878 case ARM::VSHRsv1i64:
19879 case ARM::VSHRsv2i32:
19880 case ARM::VSHRsv2i64:
19881 case ARM::VSHRsv4i16:
19882 case ARM::VSHRsv4i32:
19883 case ARM::VSHRsv8i8:
19884 case ARM::VSHRsv8i16:
19885 case ARM::VSHRsv16i8:
19886 case ARM::VSHRuv1i64:
19887 case ARM::VSHRuv2i32:
19888 case ARM::VSHRuv2i64:
19889 case ARM::VSHRuv4i16:
19890 case ARM::VSHRuv4i32:
19891 case ARM::VSHRuv8i8:
19892 case ARM::VSHRuv8i16:
19893 case ARM::VSHRuv16i8: {
19894 switch (OpNum) {
19895 case 0:
19896 // op: Vd
19897 return 12;
19898 case 1:
19899 // op: Vm
19900 return 0;
19901 case 2:
19902 // op: SIMM
19903 return 16;
19904 }
19905 break;
19906 }
19907 case ARM::VDUPLN8d:
19908 case ARM::VDUPLN8q: {
19909 switch (OpNum) {
19910 case 0:
19911 // op: Vd
19912 return 12;
19913 case 1:
19914 // op: Vm
19915 return 0;
19916 case 2:
19917 // op: lane
19918 return 17;
19919 }
19920 break;
19921 }
19922 case ARM::VDUPLN16d:
19923 case ARM::VDUPLN16q: {
19924 switch (OpNum) {
19925 case 0:
19926 // op: Vd
19927 return 12;
19928 case 1:
19929 // op: Vm
19930 return 0;
19931 case 2:
19932 // op: lane
19933 return 18;
19934 }
19935 break;
19936 }
19937 case ARM::VDUPLN32d:
19938 case ARM::VDUPLN32q: {
19939 switch (OpNum) {
19940 case 0:
19941 // op: Vd
19942 return 12;
19943 case 1:
19944 // op: Vm
19945 return 0;
19946 case 2:
19947 // op: lane
19948 return 19;
19949 }
19950 break;
19951 }
19952 case ARM::AESIMC:
19953 case ARM::AESMC:
19954 case ARM::BF16_VCVT:
19955 case ARM::SHA1H:
19956 case ARM::VABSfd:
19957 case ARM::VABSfq:
19958 case ARM::VABShd:
19959 case ARM::VABShq:
19960 case ARM::VABSv2i32:
19961 case ARM::VABSv4i16:
19962 case ARM::VABSv4i32:
19963 case ARM::VABSv8i8:
19964 case ARM::VABSv8i16:
19965 case ARM::VABSv16i8:
19966 case ARM::VCEQzv2f32:
19967 case ARM::VCEQzv2i32:
19968 case ARM::VCEQzv4f16:
19969 case ARM::VCEQzv4f32:
19970 case ARM::VCEQzv4i16:
19971 case ARM::VCEQzv4i32:
19972 case ARM::VCEQzv8f16:
19973 case ARM::VCEQzv8i8:
19974 case ARM::VCEQzv8i16:
19975 case ARM::VCEQzv16i8:
19976 case ARM::VCGEzv2f32:
19977 case ARM::VCGEzv2i32:
19978 case ARM::VCGEzv4f16:
19979 case ARM::VCGEzv4f32:
19980 case ARM::VCGEzv4i16:
19981 case ARM::VCGEzv4i32:
19982 case ARM::VCGEzv8f16:
19983 case ARM::VCGEzv8i8:
19984 case ARM::VCGEzv8i16:
19985 case ARM::VCGEzv16i8:
19986 case ARM::VCGTzv2f32:
19987 case ARM::VCGTzv2i32:
19988 case ARM::VCGTzv4f16:
19989 case ARM::VCGTzv4f32:
19990 case ARM::VCGTzv4i16:
19991 case ARM::VCGTzv4i32:
19992 case ARM::VCGTzv8f16:
19993 case ARM::VCGTzv8i8:
19994 case ARM::VCGTzv8i16:
19995 case ARM::VCGTzv16i8:
19996 case ARM::VCLEzv2f32:
19997 case ARM::VCLEzv2i32:
19998 case ARM::VCLEzv4f16:
19999 case ARM::VCLEzv4f32:
20000 case ARM::VCLEzv4i16:
20001 case ARM::VCLEzv4i32:
20002 case ARM::VCLEzv8f16:
20003 case ARM::VCLEzv8i8:
20004 case ARM::VCLEzv8i16:
20005 case ARM::VCLEzv16i8:
20006 case ARM::VCLSv2i32:
20007 case ARM::VCLSv4i16:
20008 case ARM::VCLSv4i32:
20009 case ARM::VCLSv8i8:
20010 case ARM::VCLSv8i16:
20011 case ARM::VCLSv16i8:
20012 case ARM::VCLTzv2f32:
20013 case ARM::VCLTzv2i32:
20014 case ARM::VCLTzv4f16:
20015 case ARM::VCLTzv4f32:
20016 case ARM::VCLTzv4i16:
20017 case ARM::VCLTzv4i32:
20018 case ARM::VCLTzv8f16:
20019 case ARM::VCLTzv8i8:
20020 case ARM::VCLTzv8i16:
20021 case ARM::VCLTzv16i8:
20022 case ARM::VCLZv2i32:
20023 case ARM::VCLZv4i16:
20024 case ARM::VCLZv4i32:
20025 case ARM::VCLZv8i8:
20026 case ARM::VCLZv8i16:
20027 case ARM::VCLZv16i8:
20028 case ARM::VCNTd:
20029 case ARM::VCNTq:
20030 case ARM::VCVTANSDf:
20031 case ARM::VCVTANSDh:
20032 case ARM::VCVTANSQf:
20033 case ARM::VCVTANSQh:
20034 case ARM::VCVTANUDf:
20035 case ARM::VCVTANUDh:
20036 case ARM::VCVTANUQf:
20037 case ARM::VCVTANUQh:
20038 case ARM::VCVTMNSDf:
20039 case ARM::VCVTMNSDh:
20040 case ARM::VCVTMNSQf:
20041 case ARM::VCVTMNSQh:
20042 case ARM::VCVTMNUDf:
20043 case ARM::VCVTMNUDh:
20044 case ARM::VCVTMNUQf:
20045 case ARM::VCVTMNUQh:
20046 case ARM::VCVTNNSDf:
20047 case ARM::VCVTNNSDh:
20048 case ARM::VCVTNNSQf:
20049 case ARM::VCVTNNSQh:
20050 case ARM::VCVTNNUDf:
20051 case ARM::VCVTNNUDh:
20052 case ARM::VCVTNNUQf:
20053 case ARM::VCVTNNUQh:
20054 case ARM::VCVTPNSDf:
20055 case ARM::VCVTPNSDh:
20056 case ARM::VCVTPNSQf:
20057 case ARM::VCVTPNSQh:
20058 case ARM::VCVTPNUDf:
20059 case ARM::VCVTPNUDh:
20060 case ARM::VCVTPNUQf:
20061 case ARM::VCVTPNUQh:
20062 case ARM::VCVTf2h:
20063 case ARM::VCVTf2sd:
20064 case ARM::VCVTf2sq:
20065 case ARM::VCVTf2ud:
20066 case ARM::VCVTf2uq:
20067 case ARM::VCVTh2f:
20068 case ARM::VCVTh2sd:
20069 case ARM::VCVTh2sq:
20070 case ARM::VCVTh2ud:
20071 case ARM::VCVTh2uq:
20072 case ARM::VCVTs2fd:
20073 case ARM::VCVTs2fq:
20074 case ARM::VCVTs2hd:
20075 case ARM::VCVTs2hq:
20076 case ARM::VCVTu2fd:
20077 case ARM::VCVTu2fq:
20078 case ARM::VCVTu2hd:
20079 case ARM::VCVTu2hq:
20080 case ARM::VMOVLsv2i64:
20081 case ARM::VMOVLsv4i32:
20082 case ARM::VMOVLsv8i16:
20083 case ARM::VMOVLuv2i64:
20084 case ARM::VMOVLuv4i32:
20085 case ARM::VMOVLuv8i16:
20086 case ARM::VMOVNv2i32:
20087 case ARM::VMOVNv4i16:
20088 case ARM::VMOVNv8i8:
20089 case ARM::VMVNd:
20090 case ARM::VMVNq:
20091 case ARM::VNEGf32q:
20092 case ARM::VNEGfd:
20093 case ARM::VNEGhd:
20094 case ARM::VNEGhq:
20095 case ARM::VNEGs8d:
20096 case ARM::VNEGs8q:
20097 case ARM::VNEGs16d:
20098 case ARM::VNEGs16q:
20099 case ARM::VNEGs32d:
20100 case ARM::VNEGs32q:
20101 case ARM::VPADDLsv2i32:
20102 case ARM::VPADDLsv4i16:
20103 case ARM::VPADDLsv4i32:
20104 case ARM::VPADDLsv8i8:
20105 case ARM::VPADDLsv8i16:
20106 case ARM::VPADDLsv16i8:
20107 case ARM::VPADDLuv2i32:
20108 case ARM::VPADDLuv4i16:
20109 case ARM::VPADDLuv4i32:
20110 case ARM::VPADDLuv8i8:
20111 case ARM::VPADDLuv8i16:
20112 case ARM::VPADDLuv16i8:
20113 case ARM::VQABSv2i32:
20114 case ARM::VQABSv4i16:
20115 case ARM::VQABSv4i32:
20116 case ARM::VQABSv8i8:
20117 case ARM::VQABSv8i16:
20118 case ARM::VQABSv16i8:
20119 case ARM::VQMOVNsuv2i32:
20120 case ARM::VQMOVNsuv4i16:
20121 case ARM::VQMOVNsuv8i8:
20122 case ARM::VQMOVNsv2i32:
20123 case ARM::VQMOVNsv4i16:
20124 case ARM::VQMOVNsv8i8:
20125 case ARM::VQMOVNuv2i32:
20126 case ARM::VQMOVNuv4i16:
20127 case ARM::VQMOVNuv8i8:
20128 case ARM::VQNEGv2i32:
20129 case ARM::VQNEGv4i16:
20130 case ARM::VQNEGv4i32:
20131 case ARM::VQNEGv8i8:
20132 case ARM::VQNEGv8i16:
20133 case ARM::VQNEGv16i8:
20134 case ARM::VRECPEd:
20135 case ARM::VRECPEfd:
20136 case ARM::VRECPEfq:
20137 case ARM::VRECPEhd:
20138 case ARM::VRECPEhq:
20139 case ARM::VRECPEq:
20140 case ARM::VREV16d8:
20141 case ARM::VREV16q8:
20142 case ARM::VREV32d8:
20143 case ARM::VREV32d16:
20144 case ARM::VREV32q8:
20145 case ARM::VREV32q16:
20146 case ARM::VREV64d8:
20147 case ARM::VREV64d16:
20148 case ARM::VREV64d32:
20149 case ARM::VREV64q8:
20150 case ARM::VREV64q16:
20151 case ARM::VREV64q32:
20152 case ARM::VRINTANDf:
20153 case ARM::VRINTANDh:
20154 case ARM::VRINTANQf:
20155 case ARM::VRINTANQh:
20156 case ARM::VRINTMNDf:
20157 case ARM::VRINTMNDh:
20158 case ARM::VRINTMNQf:
20159 case ARM::VRINTMNQh:
20160 case ARM::VRINTNNDf:
20161 case ARM::VRINTNNDh:
20162 case ARM::VRINTNNQf:
20163 case ARM::VRINTNNQh:
20164 case ARM::VRINTPNDf:
20165 case ARM::VRINTPNDh:
20166 case ARM::VRINTPNQf:
20167 case ARM::VRINTPNQh:
20168 case ARM::VRINTXNDf:
20169 case ARM::VRINTXNDh:
20170 case ARM::VRINTXNQf:
20171 case ARM::VRINTXNQh:
20172 case ARM::VRINTZNDf:
20173 case ARM::VRINTZNDh:
20174 case ARM::VRINTZNQf:
20175 case ARM::VRINTZNQh:
20176 case ARM::VRSQRTEd:
20177 case ARM::VRSQRTEfd:
20178 case ARM::VRSQRTEfq:
20179 case ARM::VRSQRTEhd:
20180 case ARM::VRSQRTEhq:
20181 case ARM::VRSQRTEq:
20182 case ARM::VSHLLi8:
20183 case ARM::VSHLLi16:
20184 case ARM::VSHLLi32:
20185 case ARM::VSWPd:
20186 case ARM::VSWPq:
20187 case ARM::VTRNd8:
20188 case ARM::VTRNd16:
20189 case ARM::VTRNd32:
20190 case ARM::VTRNq8:
20191 case ARM::VTRNq16:
20192 case ARM::VTRNq32:
20193 case ARM::VUZPd8:
20194 case ARM::VUZPd16:
20195 case ARM::VUZPq8:
20196 case ARM::VUZPq16:
20197 case ARM::VUZPq32:
20198 case ARM::VZIPd8:
20199 case ARM::VZIPd16:
20200 case ARM::VZIPq8:
20201 case ARM::VZIPq16:
20202 case ARM::VZIPq32: {
20203 switch (OpNum) {
20204 case 0:
20205 // op: Vd
20206 return 12;
20207 case 1:
20208 // op: Vm
20209 return 0;
20210 }
20211 break;
20212 }
20213 case ARM::VFMALDI:
20214 case ARM::VFMALQI:
20215 case ARM::VFMSLDI:
20216 case ARM::VFMSLQI: {
20217 switch (OpNum) {
20218 case 0:
20219 // op: Vd
20220 return 12;
20221 case 1:
20222 // op: Vn
20223 return 7;
20224 case 2:
20225 // op: Vm
20226 return 0;
20227 case 3:
20228 // op: idx
20229 return 3;
20230 }
20231 break;
20232 }
20233 case ARM::VEXTd32:
20234 case ARM::VEXTq32: {
20235 switch (OpNum) {
20236 case 0:
20237 // op: Vd
20238 return 12;
20239 case 1:
20240 // op: Vn
20241 return 7;
20242 case 2:
20243 // op: Vm
20244 return 0;
20245 case 3:
20246 // op: index
20247 return 10;
20248 }
20249 break;
20250 }
20251 case ARM::VEXTq64: {
20252 switch (OpNum) {
20253 case 0:
20254 // op: Vd
20255 return 12;
20256 case 1:
20257 // op: Vn
20258 return 7;
20259 case 2:
20260 // op: Vm
20261 return 0;
20262 case 3:
20263 // op: index
20264 return 11;
20265 }
20266 break;
20267 }
20268 case ARM::VEXTd8:
20269 case ARM::VEXTq8: {
20270 switch (OpNum) {
20271 case 0:
20272 // op: Vd
20273 return 12;
20274 case 1:
20275 // op: Vn
20276 return 7;
20277 case 2:
20278 // op: Vm
20279 return 0;
20280 case 3:
20281 // op: index
20282 return 8;
20283 }
20284 break;
20285 }
20286 case ARM::VEXTd16:
20287 case ARM::VEXTq16: {
20288 switch (OpNum) {
20289 case 0:
20290 // op: Vd
20291 return 12;
20292 case 1:
20293 // op: Vn
20294 return 7;
20295 case 2:
20296 // op: Vm
20297 return 0;
20298 case 3:
20299 // op: index
20300 return 9;
20301 }
20302 break;
20303 }
20304 case ARM::VMULLslsv4i16:
20305 case ARM::VMULLsluv4i16:
20306 case ARM::VMULslhd:
20307 case ARM::VMULslhq:
20308 case ARM::VMULslv4i16:
20309 case ARM::VMULslv8i16:
20310 case ARM::VQDMULHslv4i16:
20311 case ARM::VQDMULHslv8i16:
20312 case ARM::VQDMULLslv4i16:
20313 case ARM::VQRDMULHslv4i16:
20314 case ARM::VQRDMULHslv8i16: {
20315 switch (OpNum) {
20316 case 0:
20317 // op: Vd
20318 return 12;
20319 case 1:
20320 // op: Vn
20321 return 7;
20322 case 2:
20323 // op: Vm
20324 return 0;
20325 case 3:
20326 // op: lane
20327 return 3;
20328 }
20329 break;
20330 }
20331 case ARM::VMULLslsv2i32:
20332 case ARM::VMULLsluv2i32:
20333 case ARM::VMULslfd:
20334 case ARM::VMULslfq:
20335 case ARM::VMULslv2i32:
20336 case ARM::VMULslv4i32:
20337 case ARM::VQDMULHslv2i32:
20338 case ARM::VQDMULHslv4i32:
20339 case ARM::VQDMULLslv2i32:
20340 case ARM::VQRDMULHslv2i32:
20341 case ARM::VQRDMULHslv4i32: {
20342 switch (OpNum) {
20343 case 0:
20344 // op: Vd
20345 return 12;
20346 case 1:
20347 // op: Vn
20348 return 7;
20349 case 2:
20350 // op: Vm
20351 return 0;
20352 case 3:
20353 // op: lane
20354 return 5;
20355 }
20356 break;
20357 }
20358 case ARM::VCADDv2f32:
20359 case ARM::VCADDv4f16:
20360 case ARM::VCADDv4f32:
20361 case ARM::VCADDv8f16: {
20362 switch (OpNum) {
20363 case 0:
20364 // op: Vd
20365 return 12;
20366 case 1:
20367 // op: Vn
20368 return 7;
20369 case 2:
20370 // op: Vm
20371 return 0;
20372 case 3:
20373 // op: rot
20374 return 24;
20375 }
20376 break;
20377 }
20378 case ARM::NEON_VMAXNMNDf:
20379 case ARM::NEON_VMAXNMNDh:
20380 case ARM::NEON_VMAXNMNQf:
20381 case ARM::NEON_VMAXNMNQh:
20382 case ARM::NEON_VMINNMNDf:
20383 case ARM::NEON_VMINNMNDh:
20384 case ARM::NEON_VMINNMNQf:
20385 case ARM::NEON_VMINNMNQh:
20386 case ARM::VABDLsv2i64:
20387 case ARM::VABDLsv4i32:
20388 case ARM::VABDLsv8i16:
20389 case ARM::VABDLuv2i64:
20390 case ARM::VABDLuv4i32:
20391 case ARM::VABDLuv8i16:
20392 case ARM::VABDfd:
20393 case ARM::VABDfq:
20394 case ARM::VABDhd:
20395 case ARM::VABDhq:
20396 case ARM::VABDsv2i32:
20397 case ARM::VABDsv4i16:
20398 case ARM::VABDsv4i32:
20399 case ARM::VABDsv8i8:
20400 case ARM::VABDsv8i16:
20401 case ARM::VABDsv16i8:
20402 case ARM::VABDuv2i32:
20403 case ARM::VABDuv4i16:
20404 case ARM::VABDuv4i32:
20405 case ARM::VABDuv8i8:
20406 case ARM::VABDuv8i16:
20407 case ARM::VABDuv16i8:
20408 case ARM::VACGEfd:
20409 case ARM::VACGEfq:
20410 case ARM::VACGEhd:
20411 case ARM::VACGEhq:
20412 case ARM::VACGTfd:
20413 case ARM::VACGTfq:
20414 case ARM::VACGThd:
20415 case ARM::VACGThq:
20416 case ARM::VADDHNv2i32:
20417 case ARM::VADDHNv4i16:
20418 case ARM::VADDHNv8i8:
20419 case ARM::VADDLsv2i64:
20420 case ARM::VADDLsv4i32:
20421 case ARM::VADDLsv8i16:
20422 case ARM::VADDLuv2i64:
20423 case ARM::VADDLuv4i32:
20424 case ARM::VADDLuv8i16:
20425 case ARM::VADDWsv2i64:
20426 case ARM::VADDWsv4i32:
20427 case ARM::VADDWsv8i16:
20428 case ARM::VADDWuv2i64:
20429 case ARM::VADDWuv4i32:
20430 case ARM::VADDWuv8i16:
20431 case ARM::VADDfd:
20432 case ARM::VADDfq:
20433 case ARM::VADDhd:
20434 case ARM::VADDhq:
20435 case ARM::VADDv1i64:
20436 case ARM::VADDv2i32:
20437 case ARM::VADDv2i64:
20438 case ARM::VADDv4i16:
20439 case ARM::VADDv4i32:
20440 case ARM::VADDv8i8:
20441 case ARM::VADDv8i16:
20442 case ARM::VADDv16i8:
20443 case ARM::VANDd:
20444 case ARM::VANDq:
20445 case ARM::VBICd:
20446 case ARM::VBICq:
20447 case ARM::VCEQfd:
20448 case ARM::VCEQfq:
20449 case ARM::VCEQhd:
20450 case ARM::VCEQhq:
20451 case ARM::VCEQv2i32:
20452 case ARM::VCEQv4i16:
20453 case ARM::VCEQv4i32:
20454 case ARM::VCEQv8i8:
20455 case ARM::VCEQv8i16:
20456 case ARM::VCEQv16i8:
20457 case ARM::VCGEfd:
20458 case ARM::VCGEfq:
20459 case ARM::VCGEhd:
20460 case ARM::VCGEhq:
20461 case ARM::VCGEsv2i32:
20462 case ARM::VCGEsv4i16:
20463 case ARM::VCGEsv4i32:
20464 case ARM::VCGEsv8i8:
20465 case ARM::VCGEsv8i16:
20466 case ARM::VCGEsv16i8:
20467 case ARM::VCGEuv2i32:
20468 case ARM::VCGEuv4i16:
20469 case ARM::VCGEuv4i32:
20470 case ARM::VCGEuv8i8:
20471 case ARM::VCGEuv8i16:
20472 case ARM::VCGEuv16i8:
20473 case ARM::VCGTfd:
20474 case ARM::VCGTfq:
20475 case ARM::VCGThd:
20476 case ARM::VCGThq:
20477 case ARM::VCGTsv2i32:
20478 case ARM::VCGTsv4i16:
20479 case ARM::VCGTsv4i32:
20480 case ARM::VCGTsv8i8:
20481 case ARM::VCGTsv8i16:
20482 case ARM::VCGTsv16i8:
20483 case ARM::VCGTuv2i32:
20484 case ARM::VCGTuv4i16:
20485 case ARM::VCGTuv4i32:
20486 case ARM::VCGTuv8i8:
20487 case ARM::VCGTuv8i16:
20488 case ARM::VCGTuv16i8:
20489 case ARM::VEORd:
20490 case ARM::VEORq:
20491 case ARM::VFMALD:
20492 case ARM::VFMALQ:
20493 case ARM::VFMSLD:
20494 case ARM::VFMSLQ:
20495 case ARM::VHADDsv2i32:
20496 case ARM::VHADDsv4i16:
20497 case ARM::VHADDsv4i32:
20498 case ARM::VHADDsv8i8:
20499 case ARM::VHADDsv8i16:
20500 case ARM::VHADDsv16i8:
20501 case ARM::VHADDuv2i32:
20502 case ARM::VHADDuv4i16:
20503 case ARM::VHADDuv4i32:
20504 case ARM::VHADDuv8i8:
20505 case ARM::VHADDuv8i16:
20506 case ARM::VHADDuv16i8:
20507 case ARM::VHSUBsv2i32:
20508 case ARM::VHSUBsv4i16:
20509 case ARM::VHSUBsv4i32:
20510 case ARM::VHSUBsv8i8:
20511 case ARM::VHSUBsv8i16:
20512 case ARM::VHSUBsv16i8:
20513 case ARM::VHSUBuv2i32:
20514 case ARM::VHSUBuv4i16:
20515 case ARM::VHSUBuv4i32:
20516 case ARM::VHSUBuv8i8:
20517 case ARM::VHSUBuv8i16:
20518 case ARM::VHSUBuv16i8:
20519 case ARM::VMAXfd:
20520 case ARM::VMAXfq:
20521 case ARM::VMAXhd:
20522 case ARM::VMAXhq:
20523 case ARM::VMAXsv2i32:
20524 case ARM::VMAXsv4i16:
20525 case ARM::VMAXsv4i32:
20526 case ARM::VMAXsv8i8:
20527 case ARM::VMAXsv8i16:
20528 case ARM::VMAXsv16i8:
20529 case ARM::VMAXuv2i32:
20530 case ARM::VMAXuv4i16:
20531 case ARM::VMAXuv4i32:
20532 case ARM::VMAXuv8i8:
20533 case ARM::VMAXuv8i16:
20534 case ARM::VMAXuv16i8:
20535 case ARM::VMINfd:
20536 case ARM::VMINfq:
20537 case ARM::VMINhd:
20538 case ARM::VMINhq:
20539 case ARM::VMINsv2i32:
20540 case ARM::VMINsv4i16:
20541 case ARM::VMINsv4i32:
20542 case ARM::VMINsv8i8:
20543 case ARM::VMINsv8i16:
20544 case ARM::VMINsv16i8:
20545 case ARM::VMINuv2i32:
20546 case ARM::VMINuv4i16:
20547 case ARM::VMINuv4i32:
20548 case ARM::VMINuv8i8:
20549 case ARM::VMINuv8i16:
20550 case ARM::VMINuv16i8:
20551 case ARM::VMULLp8:
20552 case ARM::VMULLp64:
20553 case ARM::VMULLsv2i64:
20554 case ARM::VMULLsv4i32:
20555 case ARM::VMULLsv8i16:
20556 case ARM::VMULLuv2i64:
20557 case ARM::VMULLuv4i32:
20558 case ARM::VMULLuv8i16:
20559 case ARM::VMULfd:
20560 case ARM::VMULfq:
20561 case ARM::VMULhd:
20562 case ARM::VMULhq:
20563 case ARM::VMULpd:
20564 case ARM::VMULpq:
20565 case ARM::VMULv2i32:
20566 case ARM::VMULv4i16:
20567 case ARM::VMULv4i32:
20568 case ARM::VMULv8i8:
20569 case ARM::VMULv8i16:
20570 case ARM::VMULv16i8:
20571 case ARM::VORNd:
20572 case ARM::VORNq:
20573 case ARM::VORRd:
20574 case ARM::VORRq:
20575 case ARM::VPADDf:
20576 case ARM::VPADDh:
20577 case ARM::VPADDi8:
20578 case ARM::VPADDi16:
20579 case ARM::VPADDi32:
20580 case ARM::VPMAXf:
20581 case ARM::VPMAXh:
20582 case ARM::VPMAXs8:
20583 case ARM::VPMAXs16:
20584 case ARM::VPMAXs32:
20585 case ARM::VPMAXu8:
20586 case ARM::VPMAXu16:
20587 case ARM::VPMAXu32:
20588 case ARM::VPMINf:
20589 case ARM::VPMINh:
20590 case ARM::VPMINs8:
20591 case ARM::VPMINs16:
20592 case ARM::VPMINs32:
20593 case ARM::VPMINu8:
20594 case ARM::VPMINu16:
20595 case ARM::VPMINu32:
20596 case ARM::VQADDsv1i64:
20597 case ARM::VQADDsv2i32:
20598 case ARM::VQADDsv2i64:
20599 case ARM::VQADDsv4i16:
20600 case ARM::VQADDsv4i32:
20601 case ARM::VQADDsv8i8:
20602 case ARM::VQADDsv8i16:
20603 case ARM::VQADDsv16i8:
20604 case ARM::VQADDuv1i64:
20605 case ARM::VQADDuv2i32:
20606 case ARM::VQADDuv2i64:
20607 case ARM::VQADDuv4i16:
20608 case ARM::VQADDuv4i32:
20609 case ARM::VQADDuv8i8:
20610 case ARM::VQADDuv8i16:
20611 case ARM::VQADDuv16i8:
20612 case ARM::VQDMULHv2i32:
20613 case ARM::VQDMULHv4i16:
20614 case ARM::VQDMULHv4i32:
20615 case ARM::VQDMULHv8i16:
20616 case ARM::VQDMULLv2i64:
20617 case ARM::VQDMULLv4i32:
20618 case ARM::VQRDMULHv2i32:
20619 case ARM::VQRDMULHv4i16:
20620 case ARM::VQRDMULHv4i32:
20621 case ARM::VQRDMULHv8i16:
20622 case ARM::VQSUBsv1i64:
20623 case ARM::VQSUBsv2i32:
20624 case ARM::VQSUBsv2i64:
20625 case ARM::VQSUBsv4i16:
20626 case ARM::VQSUBsv4i32:
20627 case ARM::VQSUBsv8i8:
20628 case ARM::VQSUBsv8i16:
20629 case ARM::VQSUBsv16i8:
20630 case ARM::VQSUBuv1i64:
20631 case ARM::VQSUBuv2i32:
20632 case ARM::VQSUBuv2i64:
20633 case ARM::VQSUBuv4i16:
20634 case ARM::VQSUBuv4i32:
20635 case ARM::VQSUBuv8i8:
20636 case ARM::VQSUBuv8i16:
20637 case ARM::VQSUBuv16i8:
20638 case ARM::VRADDHNv2i32:
20639 case ARM::VRADDHNv4i16:
20640 case ARM::VRADDHNv8i8:
20641 case ARM::VRECPSfd:
20642 case ARM::VRECPSfq:
20643 case ARM::VRECPShd:
20644 case ARM::VRECPShq:
20645 case ARM::VRHADDsv2i32:
20646 case ARM::VRHADDsv4i16:
20647 case ARM::VRHADDsv4i32:
20648 case ARM::VRHADDsv8i8:
20649 case ARM::VRHADDsv8i16:
20650 case ARM::VRHADDsv16i8:
20651 case ARM::VRHADDuv2i32:
20652 case ARM::VRHADDuv4i16:
20653 case ARM::VRHADDuv4i32:
20654 case ARM::VRHADDuv8i8:
20655 case ARM::VRHADDuv8i16:
20656 case ARM::VRHADDuv16i8:
20657 case ARM::VRSQRTSfd:
20658 case ARM::VRSQRTSfq:
20659 case ARM::VRSQRTShd:
20660 case ARM::VRSQRTShq:
20661 case ARM::VRSUBHNv2i32:
20662 case ARM::VRSUBHNv4i16:
20663 case ARM::VRSUBHNv8i8:
20664 case ARM::VSUBHNv2i32:
20665 case ARM::VSUBHNv4i16:
20666 case ARM::VSUBHNv8i8:
20667 case ARM::VSUBLsv2i64:
20668 case ARM::VSUBLsv4i32:
20669 case ARM::VSUBLsv8i16:
20670 case ARM::VSUBLuv2i64:
20671 case ARM::VSUBLuv4i32:
20672 case ARM::VSUBLuv8i16:
20673 case ARM::VSUBWsv2i64:
20674 case ARM::VSUBWsv4i32:
20675 case ARM::VSUBWsv8i16:
20676 case ARM::VSUBWuv2i64:
20677 case ARM::VSUBWuv4i32:
20678 case ARM::VSUBWuv8i16:
20679 case ARM::VSUBfd:
20680 case ARM::VSUBfq:
20681 case ARM::VSUBhd:
20682 case ARM::VSUBhq:
20683 case ARM::VSUBv1i64:
20684 case ARM::VSUBv2i32:
20685 case ARM::VSUBv2i64:
20686 case ARM::VSUBv4i16:
20687 case ARM::VSUBv4i32:
20688 case ARM::VSUBv8i8:
20689 case ARM::VSUBv8i16:
20690 case ARM::VSUBv16i8:
20691 case ARM::VTBL1:
20692 case ARM::VTBL2:
20693 case ARM::VTBL3:
20694 case ARM::VTBL4:
20695 case ARM::VTSTv2i32:
20696 case ARM::VTSTv4i16:
20697 case ARM::VTSTv4i32:
20698 case ARM::VTSTv8i8:
20699 case ARM::VTSTv8i16:
20700 case ARM::VTSTv16i8: {
20701 switch (OpNum) {
20702 case 0:
20703 // op: Vd
20704 return 12;
20705 case 1:
20706 // op: Vn
20707 return 7;
20708 case 2:
20709 // op: Vm
20710 return 0;
20711 }
20712 break;
20713 }
20714 case ARM::VLD1LNd8_UPD: {
20715 switch (OpNum) {
20716 case 0:
20717 // op: Vd
20718 return 12;
20719 case 2:
20720 // op: Rn
20721 return 16;
20722 case 4:
20723 // op: Rm
20724 return 0;
20725 case 6:
20726 // op: lane
20727 return 5;
20728 }
20729 break;
20730 }
20731 case ARM::VLD1LNd16_UPD: {
20732 switch (OpNum) {
20733 case 0:
20734 // op: Vd
20735 return 12;
20736 case 2:
20737 // op: Rn
20738 return 4;
20739 case 4:
20740 // op: Rm
20741 return 0;
20742 case 6:
20743 // op: lane
20744 return 6;
20745 }
20746 break;
20747 }
20748 case ARM::VLD1LNd32_UPD: {
20749 switch (OpNum) {
20750 case 0:
20751 // op: Vd
20752 return 12;
20753 case 2:
20754 // op: Rn
20755 return 4;
20756 case 4:
20757 // op: Rm
20758 return 0;
20759 case 6:
20760 // op: lane
20761 return 7;
20762 }
20763 break;
20764 }
20765 case ARM::VLD1DUPd8wb_register:
20766 case ARM::VLD1DUPd16wb_register:
20767 case ARM::VLD1DUPd32wb_register:
20768 case ARM::VLD1DUPq8wb_register:
20769 case ARM::VLD1DUPq16wb_register:
20770 case ARM::VLD1DUPq32wb_register:
20771 case ARM::VLD1d8Qwb_register:
20772 case ARM::VLD1d8Twb_register:
20773 case ARM::VLD1d8wb_register:
20774 case ARM::VLD1d16Qwb_register:
20775 case ARM::VLD1d16Twb_register:
20776 case ARM::VLD1d16wb_register:
20777 case ARM::VLD1d32Qwb_register:
20778 case ARM::VLD1d32Twb_register:
20779 case ARM::VLD1d32wb_register:
20780 case ARM::VLD1d64Qwb_register:
20781 case ARM::VLD1d64Twb_register:
20782 case ARM::VLD1d64wb_register:
20783 case ARM::VLD1q8wb_register:
20784 case ARM::VLD1q16wb_register:
20785 case ARM::VLD1q32wb_register:
20786 case ARM::VLD1q64wb_register:
20787 case ARM::VLD2DUPd8wb_register:
20788 case ARM::VLD2DUPd8x2wb_register:
20789 case ARM::VLD2DUPd16wb_register:
20790 case ARM::VLD2DUPd16x2wb_register:
20791 case ARM::VLD2DUPd32wb_register:
20792 case ARM::VLD2DUPd32x2wb_register:
20793 case ARM::VLD2b8wb_register:
20794 case ARM::VLD2b16wb_register:
20795 case ARM::VLD2b32wb_register:
20796 case ARM::VLD2d8wb_register:
20797 case ARM::VLD2d16wb_register:
20798 case ARM::VLD2d32wb_register:
20799 case ARM::VLD2q8wb_register:
20800 case ARM::VLD2q16wb_register:
20801 case ARM::VLD2q32wb_register: {
20802 switch (OpNum) {
20803 case 0:
20804 // op: Vd
20805 return 12;
20806 case 2:
20807 // op: Rn
20808 return 4;
20809 case 4:
20810 // op: Rm
20811 return 0;
20812 }
20813 break;
20814 }
20815 case ARM::VLD2LNd8: {
20816 switch (OpNum) {
20817 case 0:
20818 // op: Vd
20819 return 12;
20820 case 2:
20821 // op: Rn
20822 return 4;
20823 case 6:
20824 // op: lane
20825 return 5;
20826 }
20827 break;
20828 }
20829 case ARM::VLD2LNd16:
20830 case ARM::VLD2LNq16: {
20831 switch (OpNum) {
20832 case 0:
20833 // op: Vd
20834 return 12;
20835 case 2:
20836 // op: Rn
20837 return 4;
20838 case 6:
20839 // op: lane
20840 return 6;
20841 }
20842 break;
20843 }
20844 case ARM::VLD2LNd32:
20845 case ARM::VLD2LNq32: {
20846 switch (OpNum) {
20847 case 0:
20848 // op: Vd
20849 return 12;
20850 case 2:
20851 // op: Rn
20852 return 4;
20853 case 6:
20854 // op: lane
20855 return 7;
20856 }
20857 break;
20858 }
20859 case ARM::VLD1DUPd8wb_fixed:
20860 case ARM::VLD1DUPd16wb_fixed:
20861 case ARM::VLD1DUPd32wb_fixed:
20862 case ARM::VLD1DUPq8wb_fixed:
20863 case ARM::VLD1DUPq16wb_fixed:
20864 case ARM::VLD1DUPq32wb_fixed:
20865 case ARM::VLD1d8Qwb_fixed:
20866 case ARM::VLD1d8Twb_fixed:
20867 case ARM::VLD1d8wb_fixed:
20868 case ARM::VLD1d16Qwb_fixed:
20869 case ARM::VLD1d16Twb_fixed:
20870 case ARM::VLD1d16wb_fixed:
20871 case ARM::VLD1d32Qwb_fixed:
20872 case ARM::VLD1d32Twb_fixed:
20873 case ARM::VLD1d32wb_fixed:
20874 case ARM::VLD1d64Qwb_fixed:
20875 case ARM::VLD1d64Twb_fixed:
20876 case ARM::VLD1d64wb_fixed:
20877 case ARM::VLD1q8wb_fixed:
20878 case ARM::VLD1q16wb_fixed:
20879 case ARM::VLD1q32wb_fixed:
20880 case ARM::VLD1q64wb_fixed:
20881 case ARM::VLD2DUPd8wb_fixed:
20882 case ARM::VLD2DUPd8x2wb_fixed:
20883 case ARM::VLD2DUPd16wb_fixed:
20884 case ARM::VLD2DUPd16x2wb_fixed:
20885 case ARM::VLD2DUPd32wb_fixed:
20886 case ARM::VLD2DUPd32x2wb_fixed:
20887 case ARM::VLD2b8wb_fixed:
20888 case ARM::VLD2b16wb_fixed:
20889 case ARM::VLD2b32wb_fixed:
20890 case ARM::VLD2d8wb_fixed:
20891 case ARM::VLD2d16wb_fixed:
20892 case ARM::VLD2d32wb_fixed:
20893 case ARM::VLD2q8wb_fixed:
20894 case ARM::VLD2q16wb_fixed:
20895 case ARM::VLD2q32wb_fixed: {
20896 switch (OpNum) {
20897 case 0:
20898 // op: Vd
20899 return 12;
20900 case 2:
20901 // op: Rn
20902 return 4;
20903 }
20904 break;
20905 }
20906 case ARM::VRSRAsv1i64:
20907 case ARM::VRSRAsv2i32:
20908 case ARM::VRSRAsv2i64:
20909 case ARM::VRSRAsv4i16:
20910 case ARM::VRSRAsv4i32:
20911 case ARM::VRSRAsv8i8:
20912 case ARM::VRSRAsv8i16:
20913 case ARM::VRSRAsv16i8:
20914 case ARM::VRSRAuv1i64:
20915 case ARM::VRSRAuv2i32:
20916 case ARM::VRSRAuv2i64:
20917 case ARM::VRSRAuv4i16:
20918 case ARM::VRSRAuv4i32:
20919 case ARM::VRSRAuv8i8:
20920 case ARM::VRSRAuv8i16:
20921 case ARM::VRSRAuv16i8:
20922 case ARM::VSLIv1i64:
20923 case ARM::VSLIv2i32:
20924 case ARM::VSLIv2i64:
20925 case ARM::VSLIv4i16:
20926 case ARM::VSLIv4i32:
20927 case ARM::VSLIv8i8:
20928 case ARM::VSLIv8i16:
20929 case ARM::VSLIv16i8:
20930 case ARM::VSRAsv1i64:
20931 case ARM::VSRAsv2i32:
20932 case ARM::VSRAsv2i64:
20933 case ARM::VSRAsv4i16:
20934 case ARM::VSRAsv4i32:
20935 case ARM::VSRAsv8i8:
20936 case ARM::VSRAsv8i16:
20937 case ARM::VSRAsv16i8:
20938 case ARM::VSRAuv1i64:
20939 case ARM::VSRAuv2i32:
20940 case ARM::VSRAuv2i64:
20941 case ARM::VSRAuv4i16:
20942 case ARM::VSRAuv4i32:
20943 case ARM::VSRAuv8i8:
20944 case ARM::VSRAuv8i16:
20945 case ARM::VSRAuv16i8:
20946 case ARM::VSRIv1i64:
20947 case ARM::VSRIv2i32:
20948 case ARM::VSRIv2i64:
20949 case ARM::VSRIv4i16:
20950 case ARM::VSRIv4i32:
20951 case ARM::VSRIv8i8:
20952 case ARM::VSRIv8i16:
20953 case ARM::VSRIv16i8: {
20954 switch (OpNum) {
20955 case 0:
20956 // op: Vd
20957 return 12;
20958 case 2:
20959 // op: Vm
20960 return 0;
20961 case 3:
20962 // op: SIMM
20963 return 16;
20964 }
20965 break;
20966 }
20967 case ARM::AESD:
20968 case ARM::AESE:
20969 case ARM::SHA1SU1:
20970 case ARM::SHA256SU0:
20971 case ARM::VPADALsv2i32:
20972 case ARM::VPADALsv4i16:
20973 case ARM::VPADALsv4i32:
20974 case ARM::VPADALsv8i8:
20975 case ARM::VPADALsv8i16:
20976 case ARM::VPADALsv16i8:
20977 case ARM::VPADALuv2i32:
20978 case ARM::VPADALuv4i16:
20979 case ARM::VPADALuv4i32:
20980 case ARM::VPADALuv8i8:
20981 case ARM::VPADALuv8i16:
20982 case ARM::VPADALuv16i8: {
20983 switch (OpNum) {
20984 case 0:
20985 // op: Vd
20986 return 12;
20987 case 2:
20988 // op: Vm
20989 return 0;
20990 }
20991 break;
20992 }
20993 case ARM::VQRSHLsv1i64:
20994 case ARM::VQRSHLsv2i32:
20995 case ARM::VQRSHLsv2i64:
20996 case ARM::VQRSHLsv4i16:
20997 case ARM::VQRSHLsv4i32:
20998 case ARM::VQRSHLsv8i8:
20999 case ARM::VQRSHLsv8i16:
21000 case ARM::VQRSHLsv16i8:
21001 case ARM::VQRSHLuv1i64:
21002 case ARM::VQRSHLuv2i32:
21003 case ARM::VQRSHLuv2i64:
21004 case ARM::VQRSHLuv4i16:
21005 case ARM::VQRSHLuv4i32:
21006 case ARM::VQRSHLuv8i8:
21007 case ARM::VQRSHLuv8i16:
21008 case ARM::VQRSHLuv16i8:
21009 case ARM::VQSHLsv1i64:
21010 case ARM::VQSHLsv2i32:
21011 case ARM::VQSHLsv2i64:
21012 case ARM::VQSHLsv4i16:
21013 case ARM::VQSHLsv4i32:
21014 case ARM::VQSHLsv8i8:
21015 case ARM::VQSHLsv8i16:
21016 case ARM::VQSHLsv16i8:
21017 case ARM::VQSHLuv1i64:
21018 case ARM::VQSHLuv2i32:
21019 case ARM::VQSHLuv2i64:
21020 case ARM::VQSHLuv4i16:
21021 case ARM::VQSHLuv4i32:
21022 case ARM::VQSHLuv8i8:
21023 case ARM::VQSHLuv8i16:
21024 case ARM::VQSHLuv16i8:
21025 case ARM::VRSHLsv1i64:
21026 case ARM::VRSHLsv2i32:
21027 case ARM::VRSHLsv2i64:
21028 case ARM::VRSHLsv4i16:
21029 case ARM::VRSHLsv4i32:
21030 case ARM::VRSHLsv8i8:
21031 case ARM::VRSHLsv8i16:
21032 case ARM::VRSHLsv16i8:
21033 case ARM::VRSHLuv1i64:
21034 case ARM::VRSHLuv2i32:
21035 case ARM::VRSHLuv2i64:
21036 case ARM::VRSHLuv4i16:
21037 case ARM::VRSHLuv4i32:
21038 case ARM::VRSHLuv8i8:
21039 case ARM::VRSHLuv8i16:
21040 case ARM::VRSHLuv16i8:
21041 case ARM::VSHLsv1i64:
21042 case ARM::VSHLsv2i32:
21043 case ARM::VSHLsv2i64:
21044 case ARM::VSHLsv4i16:
21045 case ARM::VSHLsv4i32:
21046 case ARM::VSHLsv8i8:
21047 case ARM::VSHLsv8i16:
21048 case ARM::VSHLsv16i8:
21049 case ARM::VSHLuv1i64:
21050 case ARM::VSHLuv2i32:
21051 case ARM::VSHLuv2i64:
21052 case ARM::VSHLuv4i16:
21053 case ARM::VSHLuv4i32:
21054 case ARM::VSHLuv8i8:
21055 case ARM::VSHLuv8i16:
21056 case ARM::VSHLuv16i8: {
21057 switch (OpNum) {
21058 case 0:
21059 // op: Vd
21060 return 12;
21061 case 2:
21062 // op: Vn
21063 return 7;
21064 case 1:
21065 // op: Vm
21066 return 0;
21067 }
21068 break;
21069 }
21070 case ARM::VMLALslsv4i16:
21071 case ARM::VMLALsluv4i16:
21072 case ARM::VMLAslhd:
21073 case ARM::VMLAslhq:
21074 case ARM::VMLAslv4i16:
21075 case ARM::VMLAslv8i16:
21076 case ARM::VMLSLslsv4i16:
21077 case ARM::VMLSLsluv4i16:
21078 case ARM::VMLSslhd:
21079 case ARM::VMLSslhq:
21080 case ARM::VMLSslv4i16:
21081 case ARM::VMLSslv8i16:
21082 case ARM::VQDMLALslv4i16:
21083 case ARM::VQDMLSLslv4i16:
21084 case ARM::VQRDMLAHslv4i16:
21085 case ARM::VQRDMLAHslv8i16:
21086 case ARM::VQRDMLSHslv4i16:
21087 case ARM::VQRDMLSHslv8i16: {
21088 switch (OpNum) {
21089 case 0:
21090 // op: Vd
21091 return 12;
21092 case 2:
21093 // op: Vn
21094 return 7;
21095 case 3:
21096 // op: Vm
21097 return 0;
21098 case 4:
21099 // op: lane
21100 return 3;
21101 }
21102 break;
21103 }
21104 case ARM::VMLALslsv2i32:
21105 case ARM::VMLALsluv2i32:
21106 case ARM::VMLAslfd:
21107 case ARM::VMLAslfq:
21108 case ARM::VMLAslv2i32:
21109 case ARM::VMLAslv4i32:
21110 case ARM::VMLSLslsv2i32:
21111 case ARM::VMLSLsluv2i32:
21112 case ARM::VMLSslfd:
21113 case ARM::VMLSslfq:
21114 case ARM::VMLSslv2i32:
21115 case ARM::VMLSslv4i32:
21116 case ARM::VQDMLALslv2i32:
21117 case ARM::VQDMLSLslv2i32:
21118 case ARM::VQRDMLAHslv2i32:
21119 case ARM::VQRDMLAHslv4i32:
21120 case ARM::VQRDMLSHslv2i32:
21121 case ARM::VQRDMLSHslv4i32: {
21122 switch (OpNum) {
21123 case 0:
21124 // op: Vd
21125 return 12;
21126 case 2:
21127 // op: Vn
21128 return 7;
21129 case 3:
21130 // op: Vm
21131 return 0;
21132 case 4:
21133 // op: lane
21134 return 5;
21135 }
21136 break;
21137 }
21138 case ARM::VCMLAv2f32:
21139 case ARM::VCMLAv4f16:
21140 case ARM::VCMLAv4f32:
21141 case ARM::VCMLAv8f16: {
21142 switch (OpNum) {
21143 case 0:
21144 // op: Vd
21145 return 12;
21146 case 2:
21147 // op: Vn
21148 return 7;
21149 case 3:
21150 // op: Vm
21151 return 0;
21152 case 4:
21153 // op: rot
21154 return 23;
21155 }
21156 break;
21157 }
21158 case ARM::VCMLAv4f16_indexed:
21159 case ARM::VCMLAv8f16_indexed: {
21160 switch (OpNum) {
21161 case 0:
21162 // op: Vd
21163 return 12;
21164 case 2:
21165 // op: Vn
21166 return 7;
21167 case 3:
21168 // op: Vm
21169 return 0;
21170 case 5:
21171 // op: rot
21172 return 20;
21173 case 4:
21174 // op: lane
21175 return 5;
21176 }
21177 break;
21178 }
21179 case ARM::VCMLAv2f32_indexed:
21180 case ARM::VCMLAv4f32_indexed: {
21181 switch (OpNum) {
21182 case 0:
21183 // op: Vd
21184 return 12;
21185 case 2:
21186 // op: Vn
21187 return 7;
21188 case 3:
21189 // op: Vm
21190 return 0;
21191 case 5:
21192 // op: rot
21193 return 20;
21194 }
21195 break;
21196 }
21197 case ARM::SHA1C:
21198 case ARM::SHA1M:
21199 case ARM::SHA1P:
21200 case ARM::SHA1SU0:
21201 case ARM::SHA256H:
21202 case ARM::SHA256H2:
21203 case ARM::SHA256SU1:
21204 case ARM::VABALsv2i64:
21205 case ARM::VABALsv4i32:
21206 case ARM::VABALsv8i16:
21207 case ARM::VABALuv2i64:
21208 case ARM::VABALuv4i32:
21209 case ARM::VABALuv8i16:
21210 case ARM::VABAsv2i32:
21211 case ARM::VABAsv4i16:
21212 case ARM::VABAsv4i32:
21213 case ARM::VABAsv8i8:
21214 case ARM::VABAsv8i16:
21215 case ARM::VABAsv16i8:
21216 case ARM::VABAuv2i32:
21217 case ARM::VABAuv4i16:
21218 case ARM::VABAuv4i32:
21219 case ARM::VABAuv8i8:
21220 case ARM::VABAuv8i16:
21221 case ARM::VABAuv16i8:
21222 case ARM::VBIFd:
21223 case ARM::VBIFq:
21224 case ARM::VBITd:
21225 case ARM::VBITq:
21226 case ARM::VBSLd:
21227 case ARM::VBSLq:
21228 case ARM::VFMAfd:
21229 case ARM::VFMAfq:
21230 case ARM::VFMAhd:
21231 case ARM::VFMAhq:
21232 case ARM::VFMSfd:
21233 case ARM::VFMSfq:
21234 case ARM::VFMShd:
21235 case ARM::VFMShq:
21236 case ARM::VMLALsv2i64:
21237 case ARM::VMLALsv4i32:
21238 case ARM::VMLALsv8i16:
21239 case ARM::VMLALuv2i64:
21240 case ARM::VMLALuv4i32:
21241 case ARM::VMLALuv8i16:
21242 case ARM::VMLAfd:
21243 case ARM::VMLAfq:
21244 case ARM::VMLAhd:
21245 case ARM::VMLAhq:
21246 case ARM::VMLAv2i32:
21247 case ARM::VMLAv4i16:
21248 case ARM::VMLAv4i32:
21249 case ARM::VMLAv8i8:
21250 case ARM::VMLAv8i16:
21251 case ARM::VMLAv16i8:
21252 case ARM::VMLSLsv2i64:
21253 case ARM::VMLSLsv4i32:
21254 case ARM::VMLSLsv8i16:
21255 case ARM::VMLSLuv2i64:
21256 case ARM::VMLSLuv4i32:
21257 case ARM::VMLSLuv8i16:
21258 case ARM::VMLSfd:
21259 case ARM::VMLSfq:
21260 case ARM::VMLShd:
21261 case ARM::VMLShq:
21262 case ARM::VMLSv2i32:
21263 case ARM::VMLSv4i16:
21264 case ARM::VMLSv4i32:
21265 case ARM::VMLSv8i8:
21266 case ARM::VMLSv8i16:
21267 case ARM::VMLSv16i8:
21268 case ARM::VQDMLALv2i64:
21269 case ARM::VQDMLALv4i32:
21270 case ARM::VQDMLSLv2i64:
21271 case ARM::VQDMLSLv4i32:
21272 case ARM::VQRDMLAHv2i32:
21273 case ARM::VQRDMLAHv4i16:
21274 case ARM::VQRDMLAHv4i32:
21275 case ARM::VQRDMLAHv8i16:
21276 case ARM::VQRDMLSHv2i32:
21277 case ARM::VQRDMLSHv4i16:
21278 case ARM::VQRDMLSHv4i32:
21279 case ARM::VQRDMLSHv8i16:
21280 case ARM::VTBX1:
21281 case ARM::VTBX2:
21282 case ARM::VTBX3:
21283 case ARM::VTBX4: {
21284 switch (OpNum) {
21285 case 0:
21286 // op: Vd
21287 return 12;
21288 case 2:
21289 // op: Vn
21290 return 7;
21291 case 3:
21292 // op: Vm
21293 return 0;
21294 }
21295 break;
21296 }
21297 case ARM::VLD3LNd8: {
21298 switch (OpNum) {
21299 case 0:
21300 // op: Vd
21301 return 12;
21302 case 3:
21303 // op: Rn
21304 return 16;
21305 case 8:
21306 // op: lane
21307 return 5;
21308 }
21309 break;
21310 }
21311 case ARM::VLD3LNd16:
21312 case ARM::VLD3LNq16: {
21313 switch (OpNum) {
21314 case 0:
21315 // op: Vd
21316 return 12;
21317 case 3:
21318 // op: Rn
21319 return 16;
21320 case 8:
21321 // op: lane
21322 return 6;
21323 }
21324 break;
21325 }
21326 case ARM::VLD3LNd32:
21327 case ARM::VLD3LNq32: {
21328 switch (OpNum) {
21329 case 0:
21330 // op: Vd
21331 return 12;
21332 case 3:
21333 // op: Rn
21334 return 16;
21335 case 8:
21336 // op: lane
21337 return 7;
21338 }
21339 break;
21340 }
21341 case ARM::VLD3DUPd8:
21342 case ARM::VLD3DUPd16:
21343 case ARM::VLD3DUPd32:
21344 case ARM::VLD3DUPq8:
21345 case ARM::VLD3DUPq16:
21346 case ARM::VLD3DUPq32: {
21347 switch (OpNum) {
21348 case 0:
21349 // op: Vd
21350 return 12;
21351 case 3:
21352 // op: Rn
21353 return 16;
21354 }
21355 break;
21356 }
21357 case ARM::VLD2LNd8_UPD: {
21358 switch (OpNum) {
21359 case 0:
21360 // op: Vd
21361 return 12;
21362 case 3:
21363 // op: Rn
21364 return 4;
21365 case 5:
21366 // op: Rm
21367 return 0;
21368 case 8:
21369 // op: lane
21370 return 5;
21371 }
21372 break;
21373 }
21374 case ARM::VLD2LNd16_UPD:
21375 case ARM::VLD2LNq16_UPD: {
21376 switch (OpNum) {
21377 case 0:
21378 // op: Vd
21379 return 12;
21380 case 3:
21381 // op: Rn
21382 return 4;
21383 case 5:
21384 // op: Rm
21385 return 0;
21386 case 8:
21387 // op: lane
21388 return 6;
21389 }
21390 break;
21391 }
21392 case ARM::VLD2LNd32_UPD:
21393 case ARM::VLD2LNq32_UPD: {
21394 switch (OpNum) {
21395 case 0:
21396 // op: Vd
21397 return 12;
21398 case 3:
21399 // op: Rn
21400 return 4;
21401 case 5:
21402 // op: Rm
21403 return 0;
21404 case 8:
21405 // op: lane
21406 return 7;
21407 }
21408 break;
21409 }
21410 case ARM::VLD3d8:
21411 case ARM::VLD3d16:
21412 case ARM::VLD3d32:
21413 case ARM::VLD3q8:
21414 case ARM::VLD3q16:
21415 case ARM::VLD3q32: {
21416 switch (OpNum) {
21417 case 0:
21418 // op: Vd
21419 return 12;
21420 case 3:
21421 // op: Rn
21422 return 4;
21423 }
21424 break;
21425 }
21426 case ARM::VLD3LNd8_UPD: {
21427 switch (OpNum) {
21428 case 0:
21429 // op: Vd
21430 return 12;
21431 case 4:
21432 // op: Rn
21433 return 16;
21434 case 6:
21435 // op: Rm
21436 return 0;
21437 case 10:
21438 // op: lane
21439 return 5;
21440 }
21441 break;
21442 }
21443 case ARM::VLD3LNd16_UPD:
21444 case ARM::VLD3LNq16_UPD: {
21445 switch (OpNum) {
21446 case 0:
21447 // op: Vd
21448 return 12;
21449 case 4:
21450 // op: Rn
21451 return 16;
21452 case 6:
21453 // op: Rm
21454 return 0;
21455 case 10:
21456 // op: lane
21457 return 6;
21458 }
21459 break;
21460 }
21461 case ARM::VLD3LNd32_UPD:
21462 case ARM::VLD3LNq32_UPD: {
21463 switch (OpNum) {
21464 case 0:
21465 // op: Vd
21466 return 12;
21467 case 4:
21468 // op: Rn
21469 return 16;
21470 case 6:
21471 // op: Rm
21472 return 0;
21473 case 10:
21474 // op: lane
21475 return 7;
21476 }
21477 break;
21478 }
21479 case ARM::VLD3DUPd8_UPD:
21480 case ARM::VLD3DUPd16_UPD:
21481 case ARM::VLD3DUPd32_UPD:
21482 case ARM::VLD3DUPq8_UPD:
21483 case ARM::VLD3DUPq16_UPD:
21484 case ARM::VLD3DUPq32_UPD: {
21485 switch (OpNum) {
21486 case 0:
21487 // op: Vd
21488 return 12;
21489 case 4:
21490 // op: Rn
21491 return 16;
21492 case 6:
21493 // op: Rm
21494 return 0;
21495 }
21496 break;
21497 }
21498 case ARM::VLD4LNd8: {
21499 switch (OpNum) {
21500 case 0:
21501 // op: Vd
21502 return 12;
21503 case 4:
21504 // op: Rn
21505 return 4;
21506 case 10:
21507 // op: lane
21508 return 5;
21509 }
21510 break;
21511 }
21512 case ARM::VLD4LNd16:
21513 case ARM::VLD4LNq16: {
21514 switch (OpNum) {
21515 case 0:
21516 // op: Vd
21517 return 12;
21518 case 4:
21519 // op: Rn
21520 return 4;
21521 case 10:
21522 // op: lane
21523 return 6;
21524 }
21525 break;
21526 }
21527 case ARM::VLD4LNd32:
21528 case ARM::VLD4LNq32: {
21529 switch (OpNum) {
21530 case 0:
21531 // op: Vd
21532 return 12;
21533 case 4:
21534 // op: Rn
21535 return 4;
21536 case 10:
21537 // op: lane
21538 return 7;
21539 }
21540 break;
21541 }
21542 case ARM::VLD3d8_UPD:
21543 case ARM::VLD3d16_UPD:
21544 case ARM::VLD3d32_UPD:
21545 case ARM::VLD3q8_UPD:
21546 case ARM::VLD3q16_UPD:
21547 case ARM::VLD3q32_UPD: {
21548 switch (OpNum) {
21549 case 0:
21550 // op: Vd
21551 return 12;
21552 case 4:
21553 // op: Rn
21554 return 4;
21555 case 6:
21556 // op: Rm
21557 return 0;
21558 }
21559 break;
21560 }
21561 case ARM::VLD4DUPd8:
21562 case ARM::VLD4DUPd16:
21563 case ARM::VLD4DUPd32:
21564 case ARM::VLD4DUPq8:
21565 case ARM::VLD4DUPq16:
21566 case ARM::VLD4DUPq32:
21567 case ARM::VLD4d8:
21568 case ARM::VLD4d16:
21569 case ARM::VLD4d32:
21570 case ARM::VLD4q8:
21571 case ARM::VLD4q16:
21572 case ARM::VLD4q32: {
21573 switch (OpNum) {
21574 case 0:
21575 // op: Vd
21576 return 12;
21577 case 4:
21578 // op: Rn
21579 return 4;
21580 }
21581 break;
21582 }
21583 case ARM::VLD4LNd8_UPD: {
21584 switch (OpNum) {
21585 case 0:
21586 // op: Vd
21587 return 12;
21588 case 5:
21589 // op: Rn
21590 return 4;
21591 case 7:
21592 // op: Rm
21593 return 0;
21594 case 12:
21595 // op: lane
21596 return 5;
21597 }
21598 break;
21599 }
21600 case ARM::VLD4LNd16_UPD:
21601 case ARM::VLD4LNq16_UPD: {
21602 switch (OpNum) {
21603 case 0:
21604 // op: Vd
21605 return 12;
21606 case 5:
21607 // op: Rn
21608 return 4;
21609 case 7:
21610 // op: Rm
21611 return 0;
21612 case 12:
21613 // op: lane
21614 return 6;
21615 }
21616 break;
21617 }
21618 case ARM::VLD4LNd32_UPD:
21619 case ARM::VLD4LNq32_UPD: {
21620 switch (OpNum) {
21621 case 0:
21622 // op: Vd
21623 return 12;
21624 case 5:
21625 // op: Rn
21626 return 4;
21627 case 7:
21628 // op: Rm
21629 return 0;
21630 case 12:
21631 // op: lane
21632 return 7;
21633 }
21634 break;
21635 }
21636 case ARM::VLD4DUPd8_UPD:
21637 case ARM::VLD4DUPd16_UPD:
21638 case ARM::VLD4DUPd32_UPD:
21639 case ARM::VLD4DUPq8_UPD:
21640 case ARM::VLD4DUPq16_UPD:
21641 case ARM::VLD4DUPq32_UPD:
21642 case ARM::VLD4d8_UPD:
21643 case ARM::VLD4d16_UPD:
21644 case ARM::VLD4d32_UPD:
21645 case ARM::VLD4q8_UPD:
21646 case ARM::VLD4q16_UPD:
21647 case ARM::VLD4q32_UPD: {
21648 switch (OpNum) {
21649 case 0:
21650 // op: Vd
21651 return 12;
21652 case 5:
21653 // op: Rn
21654 return 4;
21655 case 7:
21656 // op: Rm
21657 return 0;
21658 }
21659 break;
21660 }
21661 case ARM::PLDWi12:
21662 case ARM::PLDi12:
21663 case ARM::PLIi12:
21664 case ARM::t2PLDWi8:
21665 case ARM::t2PLDWi12:
21666 case ARM::t2PLDWs:
21667 case ARM::t2PLDi8:
21668 case ARM::t2PLDi12:
21669 case ARM::t2PLDpci:
21670 case ARM::t2PLDs:
21671 case ARM::t2PLIi8:
21672 case ARM::t2PLIi12:
21673 case ARM::t2PLIpci:
21674 case ARM::t2PLIs: {
21675 switch (OpNum) {
21676 case 0:
21677 // op: addr
21678 return 0;
21679 }
21680 break;
21681 }
21682 case ARM::t2BFLr:
21683 case ARM::t2BFr: {
21684 switch (OpNum) {
21685 case 0:
21686 // op: b_label
21687 return 23;
21688 case 1:
21689 // op: Rn
21690 return 16;
21691 }
21692 break;
21693 }
21694 case ARM::t2BFLi:
21695 case ARM::t2BFi: {
21696 switch (OpNum) {
21697 case 0:
21698 // op: b_label
21699 return 23;
21700 case 1:
21701 // op: label
21702 return 1;
21703 }
21704 break;
21705 }
21706 case ARM::t2MSRbanked: {
21707 switch (OpNum) {
21708 case 0:
21709 // op: banked
21710 return 4;
21711 case 1:
21712 // op: Rn
21713 return 16;
21714 }
21715 break;
21716 }
21717 case ARM::t2IT: {
21718 switch (OpNum) {
21719 case 0:
21720 // op: cc
21721 return 4;
21722 case 1:
21723 // op: mask
21724 return 0;
21725 }
21726 break;
21727 }
21728 case ARM::BX:
21729 case ARM::tPICADD: {
21730 switch (OpNum) {
21731 case 0:
21732 // op: dst
21733 return 0;
21734 }
21735 break;
21736 }
21737 case ARM::tADDrSPi: {
21738 switch (OpNum) {
21739 case 0:
21740 // op: dst
21741 return 8;
21742 case 2:
21743 // op: imm
21744 return 0;
21745 }
21746 break;
21747 }
21748 case ARM::tSETEND: {
21749 switch (OpNum) {
21750 case 0:
21751 // op: end
21752 return 3;
21753 }
21754 break;
21755 }
21756 case ARM::SETEND: {
21757 switch (OpNum) {
21758 case 0:
21759 // op: end
21760 return 9;
21761 }
21762 break;
21763 }
21764 case ARM::BL:
21765 case ARM::BLX: {
21766 switch (OpNum) {
21767 case 0:
21768 // op: func
21769 return 0;
21770 }
21771 break;
21772 }
21773 case ARM::t2BXJ: {
21774 switch (OpNum) {
21775 case 0:
21776 // op: func
21777 return 16;
21778 }
21779 break;
21780 }
21781 case ARM::HVC:
21782 case ARM::t2HINT:
21783 case ARM::t2SUBS_PC_LR:
21784 case ARM::tSVC: {
21785 switch (OpNum) {
21786 case 0:
21787 // op: imm
21788 return 0;
21789 }
21790 break;
21791 }
21792 case ARM::t2SETPAN: {
21793 switch (OpNum) {
21794 case 0:
21795 // op: imm
21796 return 3;
21797 }
21798 break;
21799 }
21800 case ARM::tHINT: {
21801 switch (OpNum) {
21802 case 0:
21803 // op: imm
21804 return 4;
21805 }
21806 break;
21807 }
21808 case ARM::SETPAN: {
21809 switch (OpNum) {
21810 case 0:
21811 // op: imm
21812 return 9;
21813 }
21814 break;
21815 }
21816 case ARM::UDF:
21817 case ARM::t2HVC:
21818 case ARM::t2UDF: {
21819 switch (OpNum) {
21820 case 0:
21821 // op: imm16
21822 return 0;
21823 }
21824 break;
21825 }
21826 case ARM::tUDF: {
21827 switch (OpNum) {
21828 case 0:
21829 // op: imm8
21830 return 0;
21831 }
21832 break;
21833 }
21834 case ARM::CPS3p: {
21835 switch (OpNum) {
21836 case 0:
21837 // op: imod
21838 return 18;
21839 case 1:
21840 // op: iflags
21841 return 6;
21842 case 2:
21843 // op: mode
21844 return 0;
21845 }
21846 break;
21847 }
21848 case ARM::CPS2p: {
21849 switch (OpNum) {
21850 case 0:
21851 // op: imod
21852 return 18;
21853 case 1:
21854 // op: iflags
21855 return 6;
21856 }
21857 break;
21858 }
21859 case ARM::tCPS: {
21860 switch (OpNum) {
21861 case 0:
21862 // op: imod
21863 return 4;
21864 case 1:
21865 // op: iflags
21866 return 0;
21867 }
21868 break;
21869 }
21870 case ARM::t2CPS3p: {
21871 switch (OpNum) {
21872 case 0:
21873 // op: imod
21874 return 9;
21875 case 1:
21876 // op: iflags
21877 return 5;
21878 case 2:
21879 // op: mode
21880 return 0;
21881 }
21882 break;
21883 }
21884 case ARM::t2CPS2p: {
21885 switch (OpNum) {
21886 case 0:
21887 // op: imod
21888 return 9;
21889 case 1:
21890 // op: iflags
21891 return 5;
21892 }
21893 break;
21894 }
21895 case ARM::t2LE: {
21896 switch (OpNum) {
21897 case 0:
21898 // op: label
21899 return 1;
21900 }
21901 break;
21902 }
21903 case ARM::t2MSR_AR: {
21904 switch (OpNum) {
21905 case 0:
21906 // op: mask
21907 return 8;
21908 case 1:
21909 // op: Rn
21910 return 16;
21911 }
21912 break;
21913 }
21914 case ARM::CPS1p:
21915 case ARM::SRSDA:
21916 case ARM::SRSDA_UPD:
21917 case ARM::SRSDB:
21918 case ARM::SRSDB_UPD:
21919 case ARM::SRSIA:
21920 case ARM::SRSIA_UPD:
21921 case ARM::SRSIB:
21922 case ARM::SRSIB_UPD:
21923 case ARM::t2CPS1p:
21924 case ARM::t2SRSDB:
21925 case ARM::t2SRSDB_UPD:
21926 case ARM::t2SRSIA:
21927 case ARM::t2SRSIA_UPD: {
21928 switch (OpNum) {
21929 case 0:
21930 // op: mode
21931 return 0;
21932 }
21933 break;
21934 }
21935 case ARM::DMB:
21936 case ARM::DSB:
21937 case ARM::ISB:
21938 case ARM::t2DBG:
21939 case ARM::t2DMB:
21940 case ARM::t2DSB:
21941 case ARM::t2ISB: {
21942 switch (OpNum) {
21943 case 0:
21944 // op: opt
21945 return 0;
21946 }
21947 break;
21948 }
21949 case ARM::t2SMC: {
21950 switch (OpNum) {
21951 case 0:
21952 // op: opt
21953 return 16;
21954 }
21955 break;
21956 }
21957 case ARM::BX_RET:
21958 case ARM::ERET:
21959 case ARM::FMSTAT:
21960 case ARM::MOVPCLR: {
21961 switch (OpNum) {
21962 case 0:
21963 // op: p
21964 return 28;
21965 }
21966 break;
21967 }
21968 case ARM::PLDWrs:
21969 case ARM::PLDrs:
21970 case ARM::PLIrs: {
21971 switch (OpNum) {
21972 case 0:
21973 // op: shift
21974 return 0;
21975 }
21976 break;
21977 }
21978 case ARM::BLXi:
21979 case ARM::t2B:
21980 case ARM::tB: {
21981 switch (OpNum) {
21982 case 0:
21983 // op: target
21984 return 0;
21985 }
21986 break;
21987 }
21988 case ARM::BKPT:
21989 case ARM::HLT:
21990 case ARM::tBKPT:
21991 case ARM::tHLT: {
21992 switch (OpNum) {
21993 case 0:
21994 // op: val
21995 return 0;
21996 }
21997 break;
21998 }
21999 case ARM::MVE_VLDRBS16_pre:
22000 case ARM::MVE_VLDRBS32_pre:
22001 case ARM::MVE_VLDRBU8_pre:
22002 case ARM::MVE_VLDRBU16_pre:
22003 case ARM::MVE_VLDRBU32_pre:
22004 case ARM::MVE_VLDRDU64_qi_pre:
22005 case ARM::MVE_VLDRHS32_pre:
22006 case ARM::MVE_VLDRHU16_pre:
22007 case ARM::MVE_VLDRHU32_pre:
22008 case ARM::MVE_VLDRWU32_pre:
22009 case ARM::MVE_VLDRWU32_qi_pre:
22010 case ARM::MVE_VSTRB16_pre:
22011 case ARM::MVE_VSTRB32_pre:
22012 case ARM::MVE_VSTRBU8_pre:
22013 case ARM::MVE_VSTRD64_qi_pre:
22014 case ARM::MVE_VSTRH32_pre:
22015 case ARM::MVE_VSTRHU16_pre:
22016 case ARM::MVE_VSTRW32_qi_pre:
22017 case ARM::MVE_VSTRWU32_pre: {
22018 switch (OpNum) {
22019 case 1:
22020 // op: Qd
22021 return 13;
22022 case 2:
22023 // op: addr
22024 return 0;
22025 }
22026 break;
22027 }
22028 case ARM::MVE_VLDRBS16_post:
22029 case ARM::MVE_VLDRBS32_post:
22030 case ARM::MVE_VLDRBU8_post:
22031 case ARM::MVE_VLDRBU16_post:
22032 case ARM::MVE_VLDRBU32_post:
22033 case ARM::MVE_VLDRHS32_post:
22034 case ARM::MVE_VLDRHU16_post:
22035 case ARM::MVE_VLDRHU32_post:
22036 case ARM::MVE_VLDRWU32_post:
22037 case ARM::MVE_VSTRB16_post:
22038 case ARM::MVE_VSTRB32_post:
22039 case ARM::MVE_VSTRBU8_post:
22040 case ARM::MVE_VSTRH32_post:
22041 case ARM::MVE_VSTRHU16_post:
22042 case ARM::MVE_VSTRWU32_post: {
22043 switch (OpNum) {
22044 case 1:
22045 // op: Qd
22046 return 13;
22047 case 3:
22048 // op: addr
22049 return 0;
22050 case 2:
22051 // op: Rn
22052 return 16;
22053 }
22054 break;
22055 }
22056 case ARM::MVE_VMOV_from_lane_32: {
22057 switch (OpNum) {
22058 case 1:
22059 // op: Qd
22060 return 7;
22061 case 0:
22062 // op: Rt
22063 return 12;
22064 case 2:
22065 // op: Idx
22066 return 16;
22067 }
22068 break;
22069 }
22070 case ARM::MVE_VMOV_from_lane_s8:
22071 case ARM::MVE_VMOV_from_lane_u8: {
22072 switch (OpNum) {
22073 case 1:
22074 // op: Qd
22075 return 7;
22076 case 0:
22077 // op: Rt
22078 return 12;
22079 case 2:
22080 // op: Idx
22081 return 5;
22082 }
22083 break;
22084 }
22085 case ARM::MVE_VMOV_from_lane_s16:
22086 case ARM::MVE_VMOV_from_lane_u16: {
22087 switch (OpNum) {
22088 case 1:
22089 // op: Qd
22090 return 7;
22091 case 0:
22092 // op: Rt
22093 return 12;
22094 case 2:
22095 // op: Idx
22096 return 6;
22097 }
22098 break;
22099 }
22100 case ARM::MVE_VCVTf16s16_fix:
22101 case ARM::MVE_VCVTf16u16_fix:
22102 case ARM::MVE_VCVTf32s32_fix:
22103 case ARM::MVE_VCVTf32u32_fix:
22104 case ARM::MVE_VCVTs16f16_fix:
22105 case ARM::MVE_VCVTs32f32_fix:
22106 case ARM::MVE_VCVTu16f16_fix:
22107 case ARM::MVE_VCVTu32f32_fix: {
22108 switch (OpNum) {
22109 case 1:
22110 // op: Qm
22111 return 1;
22112 case 0:
22113 // op: Qd
22114 return 13;
22115 case 2:
22116 // op: imm6
22117 return 16;
22118 }
22119 break;
22120 }
22121 case ARM::MVE_VABSf16:
22122 case ARM::MVE_VABSf32:
22123 case ARM::MVE_VCVTf16s16n:
22124 case ARM::MVE_VCVTf16u16n:
22125 case ARM::MVE_VCVTf32s32n:
22126 case ARM::MVE_VCVTf32u32n:
22127 case ARM::MVE_VCVTs16f16a:
22128 case ARM::MVE_VCVTs16f16m:
22129 case ARM::MVE_VCVTs16f16n:
22130 case ARM::MVE_VCVTs16f16p:
22131 case ARM::MVE_VCVTs16f16z:
22132 case ARM::MVE_VCVTs32f32a:
22133 case ARM::MVE_VCVTs32f32m:
22134 case ARM::MVE_VCVTs32f32n:
22135 case ARM::MVE_VCVTs32f32p:
22136 case ARM::MVE_VCVTs32f32z:
22137 case ARM::MVE_VCVTu16f16a:
22138 case ARM::MVE_VCVTu16f16m:
22139 case ARM::MVE_VCVTu16f16n:
22140 case ARM::MVE_VCVTu16f16p:
22141 case ARM::MVE_VCVTu16f16z:
22142 case ARM::MVE_VCVTu32f32a:
22143 case ARM::MVE_VCVTu32f32m:
22144 case ARM::MVE_VCVTu32f32n:
22145 case ARM::MVE_VCVTu32f32p:
22146 case ARM::MVE_VCVTu32f32z:
22147 case ARM::MVE_VNEGf16:
22148 case ARM::MVE_VNEGf32:
22149 case ARM::MVE_VRINTf16A:
22150 case ARM::MVE_VRINTf16M:
22151 case ARM::MVE_VRINTf16N:
22152 case ARM::MVE_VRINTf16P:
22153 case ARM::MVE_VRINTf16X:
22154 case ARM::MVE_VRINTf16Z:
22155 case ARM::MVE_VRINTf32A:
22156 case ARM::MVE_VRINTf32M:
22157 case ARM::MVE_VRINTf32N:
22158 case ARM::MVE_VRINTf32P:
22159 case ARM::MVE_VRINTf32X:
22160 case ARM::MVE_VRINTf32Z: {
22161 switch (OpNum) {
22162 case 1:
22163 // op: Qm
22164 return 1;
22165 case 0:
22166 // op: Qd
22167 return 13;
22168 }
22169 break;
22170 }
22171 case ARM::MVE_VADDVs8no_acc:
22172 case ARM::MVE_VADDVs16no_acc:
22173 case ARM::MVE_VADDVs32no_acc:
22174 case ARM::MVE_VADDVu8no_acc:
22175 case ARM::MVE_VADDVu16no_acc:
22176 case ARM::MVE_VADDVu32no_acc: {
22177 switch (OpNum) {
22178 case 1:
22179 // op: Qm
22180 return 1;
22181 case 0:
22182 // op: Rda
22183 return 13;
22184 }
22185 break;
22186 }
22187 case ARM::MVE_VPSEL: {
22188 switch (OpNum) {
22189 case 1:
22190 // op: Qn
22191 return 7;
22192 case 0:
22193 // op: Qd
22194 return 13;
22195 case 2:
22196 // op: Qm
22197 return 1;
22198 }
22199 break;
22200 }
22201 case ARM::t2SMLALD:
22202 case ARM::t2SMLALDX:
22203 case ARM::t2SMLSLD:
22204 case ARM::t2SMLSLDX: {
22205 switch (OpNum) {
22206 case 1:
22207 // op: Rd
22208 return 8;
22209 case 2:
22210 // op: Rn
22211 return 16;
22212 case 3:
22213 // op: Rm
22214 return 0;
22215 case 0:
22216 // op: Ra
22217 return 12;
22218 }
22219 break;
22220 }
22221 case ARM::tREV:
22222 case ARM::tREV16:
22223 case ARM::tREVSH:
22224 case ARM::tSXTB:
22225 case ARM::tSXTH:
22226 case ARM::tUXTB:
22227 case ARM::tUXTH: {
22228 switch (OpNum) {
22229 case 1:
22230 // op: Rm
22231 return 3;
22232 case 0:
22233 // op: Rd
22234 return 0;
22235 }
22236 break;
22237 }
22238 case ARM::tCMNz:
22239 case ARM::tCMPhir:
22240 case ARM::tCMPr:
22241 case ARM::tTST: {
22242 switch (OpNum) {
22243 case 1:
22244 // op: Rm
22245 return 3;
22246 case 0:
22247 // op: Rn
22248 return 0;
22249 }
22250 break;
22251 }
22252 case ARM::t2TT:
22253 case ARM::t2TTA:
22254 case ARM::t2TTAT:
22255 case ARM::t2TTT: {
22256 switch (OpNum) {
22257 case 1:
22258 // op: Rn
22259 return 16;
22260 case 0:
22261 // op: Rt
22262 return 8;
22263 }
22264 break;
22265 }
22266 case ARM::MVE_WLSTP_8:
22267 case ARM::MVE_WLSTP_16:
22268 case ARM::MVE_WLSTP_32:
22269 case ARM::MVE_WLSTP_64:
22270 case ARM::t2WLS: {
22271 switch (OpNum) {
22272 case 1:
22273 // op: Rn
22274 return 16;
22275 case 2:
22276 // op: label
22277 return 1;
22278 }
22279 break;
22280 }
22281 case ARM::t2LDMDB_UPD:
22282 case ARM::t2LDMIA_UPD:
22283 case ARM::t2STMDB_UPD:
22284 case ARM::t2STMIA_UPD: {
22285 switch (OpNum) {
22286 case 1:
22287 // op: Rn
22288 return 16;
22289 case 4:
22290 // op: regs
22291 return 0;
22292 }
22293 break;
22294 }
22295 case ARM::MVE_DLSTP_8:
22296 case ARM::MVE_DLSTP_16:
22297 case ARM::MVE_DLSTP_32:
22298 case ARM::MVE_DLSTP_64:
22299 case ARM::MVE_VCTP8:
22300 case ARM::MVE_VCTP16:
22301 case ARM::MVE_VCTP32:
22302 case ARM::MVE_VCTP64:
22303 case ARM::t2DLS: {
22304 switch (OpNum) {
22305 case 1:
22306 // op: Rn
22307 return 16;
22308 }
22309 break;
22310 }
22311 case ARM::tSTMIA_UPD: {
22312 switch (OpNum) {
22313 case 1:
22314 // op: Rn
22315 return 8;
22316 case 4:
22317 // op: regs
22318 return 0;
22319 }
22320 break;
22321 }
22322 case ARM::t2STRB_POST:
22323 case ARM::t2STRH_POST:
22324 case ARM::t2STR_POST: {
22325 switch (OpNum) {
22326 case 1:
22327 // op: Rt
22328 return 12;
22329 case 2:
22330 // op: Rn
22331 return 16;
22332 case 3:
22333 // op: offset
22334 return 0;
22335 }
22336 break;
22337 }
22338 case ARM::t2STRD_PRE: {
22339 switch (OpNum) {
22340 case 1:
22341 // op: Rt
22342 return 12;
22343 case 2:
22344 // op: Rt2
22345 return 8;
22346 case 3:
22347 // op: addr
22348 return 0;
22349 }
22350 break;
22351 }
22352 case ARM::t2STRD_POST: {
22353 switch (OpNum) {
22354 case 1:
22355 // op: Rt
22356 return 12;
22357 case 2:
22358 // op: Rt2
22359 return 8;
22360 case 3:
22361 // op: addr
22362 return 16;
22363 case 4:
22364 // op: imm
22365 return 0;
22366 }
22367 break;
22368 }
22369 case ARM::t2STRB_PRE:
22370 case ARM::t2STRH_PRE:
22371 case ARM::t2STR_PRE: {
22372 switch (OpNum) {
22373 case 1:
22374 // op: Rt
22375 return 12;
22376 case 2:
22377 // op: addr
22378 return 0;
22379 }
22380 break;
22381 }
22382 case ARM::VGETLNi32: {
22383 switch (OpNum) {
22384 case 1:
22385 // op: V
22386 return 7;
22387 case 0:
22388 // op: R
22389 return 12;
22390 case 3:
22391 // op: p
22392 return 28;
22393 case 2:
22394 // op: lane
22395 return 21;
22396 }
22397 break;
22398 }
22399 case ARM::VGETLNs8:
22400 case ARM::VGETLNu8: {
22401 switch (OpNum) {
22402 case 1:
22403 // op: V
22404 return 7;
22405 case 0:
22406 // op: R
22407 return 12;
22408 case 3:
22409 // op: p
22410 return 28;
22411 case 2:
22412 // op: lane
22413 return 5;
22414 }
22415 break;
22416 }
22417 case ARM::VGETLNs16:
22418 case ARM::VGETLNu16: {
22419 switch (OpNum) {
22420 case 1:
22421 // op: V
22422 return 7;
22423 case 0:
22424 // op: R
22425 return 12;
22426 case 3:
22427 // op: p
22428 return 28;
22429 case 2:
22430 // op: lane
22431 return 6;
22432 }
22433 break;
22434 }
22435 case ARM::MVE_VST20_8_wb:
22436 case ARM::MVE_VST20_16_wb:
22437 case ARM::MVE_VST20_32_wb:
22438 case ARM::MVE_VST21_8_wb:
22439 case ARM::MVE_VST21_16_wb:
22440 case ARM::MVE_VST21_32_wb:
22441 case ARM::MVE_VST40_8_wb:
22442 case ARM::MVE_VST40_16_wb:
22443 case ARM::MVE_VST40_32_wb:
22444 case ARM::MVE_VST41_8_wb:
22445 case ARM::MVE_VST41_16_wb:
22446 case ARM::MVE_VST41_32_wb:
22447 case ARM::MVE_VST42_8_wb:
22448 case ARM::MVE_VST42_16_wb:
22449 case ARM::MVE_VST42_32_wb:
22450 case ARM::MVE_VST43_8_wb:
22451 case ARM::MVE_VST43_16_wb:
22452 case ARM::MVE_VST43_32_wb: {
22453 switch (OpNum) {
22454 case 1:
22455 // op: VQd
22456 return 13;
22457 case 2:
22458 // op: Rn
22459 return 16;
22460 }
22461 break;
22462 }
22463 case ARM::VBF16MALBQI:
22464 case ARM::VBF16MALTQI: {
22465 switch (OpNum) {
22466 case 1:
22467 // op: Vd
22468 return 12;
22469 case 2:
22470 // op: Vn
22471 return 7;
22472 case 3:
22473 // op: Vm
22474 return 0;
22475 case 4:
22476 // op: idx
22477 return 3;
22478 }
22479 break;
22480 }
22481 case ARM::BF16VDOTI_VDOTD:
22482 case ARM::BF16VDOTI_VDOTQ:
22483 case ARM::VSDOTDI:
22484 case ARM::VSDOTQI:
22485 case ARM::VSUDOTDI:
22486 case ARM::VSUDOTQI:
22487 case ARM::VUDOTDI:
22488 case ARM::VUDOTQI:
22489 case ARM::VUSDOTDI:
22490 case ARM::VUSDOTQI: {
22491 switch (OpNum) {
22492 case 1:
22493 // op: Vd
22494 return 12;
22495 case 2:
22496 // op: Vn
22497 return 7;
22498 case 3:
22499 // op: Vm
22500 return 0;
22501 case 4:
22502 // op: lane
22503 return 5;
22504 }
22505 break;
22506 }
22507 case ARM::BF16VDOTS_VDOTD:
22508 case ARM::BF16VDOTS_VDOTQ:
22509 case ARM::VBF16MALBQ:
22510 case ARM::VBF16MALTQ:
22511 case ARM::VMMLA:
22512 case ARM::VSDOTD:
22513 case ARM::VSDOTQ:
22514 case ARM::VSMMLA:
22515 case ARM::VUDOTD:
22516 case ARM::VUDOTQ:
22517 case ARM::VUMMLA:
22518 case ARM::VUSDOTD:
22519 case ARM::VUSDOTQ:
22520 case ARM::VUSMMLA: {
22521 switch (OpNum) {
22522 case 1:
22523 // op: Vd
22524 return 12;
22525 case 2:
22526 // op: Vn
22527 return 7;
22528 case 3:
22529 // op: Vm
22530 return 0;
22531 }
22532 break;
22533 }
22534 case ARM::t2LDAEXB:
22535 case ARM::t2LDAEXH:
22536 case ARM::t2LDREXB:
22537 case ARM::t2LDREXH: {
22538 switch (OpNum) {
22539 case 1:
22540 // op: addr
22541 return 16;
22542 case 0:
22543 // op: Rt
22544 return 12;
22545 }
22546 break;
22547 }
22548 case ARM::t2MRSbanked: {
22549 switch (OpNum) {
22550 case 1:
22551 // op: banked
22552 return 4;
22553 case 0:
22554 // op: Rd
22555 return 8;
22556 }
22557 break;
22558 }
22559 case ARM::CDE_VCX1_vec: {
22560 switch (OpNum) {
22561 case 1:
22562 // op: coproc
22563 return 8;
22564 case 2:
22565 // op: imm
22566 return 0;
22567 case 0:
22568 // op: Qd
22569 return 13;
22570 }
22571 break;
22572 }
22573 case ARM::CDE_CX1:
22574 case ARM::CDE_CX1D: {
22575 switch (OpNum) {
22576 case 1:
22577 // op: coproc
22578 return 8;
22579 case 2:
22580 // op: imm
22581 return 0;
22582 case 0:
22583 // op: Rd
22584 return 12;
22585 }
22586 break;
22587 }
22588 case ARM::CDE_VCX1_fpdp:
22589 case ARM::CDE_VCX1_fpsp: {
22590 switch (OpNum) {
22591 case 1:
22592 // op: coproc
22593 return 8;
22594 case 2:
22595 // op: imm
22596 return 0;
22597 case 0:
22598 // op: Vd
22599 return 12;
22600 }
22601 break;
22602 }
22603 case ARM::CDE_VCX1A_vec: {
22604 switch (OpNum) {
22605 case 1:
22606 // op: coproc
22607 return 8;
22608 case 3:
22609 // op: imm
22610 return 0;
22611 case 0:
22612 // op: Qd
22613 return 13;
22614 }
22615 break;
22616 }
22617 case ARM::CDE_CX2:
22618 case ARM::CDE_CX2D: {
22619 switch (OpNum) {
22620 case 1:
22621 // op: coproc
22622 return 8;
22623 case 3:
22624 // op: imm
22625 return 0;
22626 case 0:
22627 // op: Rd
22628 return 12;
22629 case 2:
22630 // op: Rn
22631 return 16;
22632 }
22633 break;
22634 }
22635 case ARM::CDE_CX1A:
22636 case ARM::CDE_CX1DA: {
22637 switch (OpNum) {
22638 case 1:
22639 // op: coproc
22640 return 8;
22641 case 3:
22642 // op: imm
22643 return 0;
22644 case 0:
22645 // op: Rd
22646 return 12;
22647 }
22648 break;
22649 }
22650 case ARM::CDE_VCX1A_fpdp:
22651 case ARM::CDE_VCX1A_fpsp: {
22652 switch (OpNum) {
22653 case 1:
22654 // op: coproc
22655 return 8;
22656 case 3:
22657 // op: imm
22658 return 0;
22659 case 0:
22660 // op: Vd
22661 return 12;
22662 }
22663 break;
22664 }
22665 case ARM::CDE_VCX2_vec: {
22666 switch (OpNum) {
22667 case 1:
22668 // op: coproc
22669 return 8;
22670 case 3:
22671 // op: imm
22672 return 4;
22673 case 0:
22674 // op: Qd
22675 return 13;
22676 case 2:
22677 // op: Qm
22678 return 1;
22679 }
22680 break;
22681 }
22682 case ARM::CDE_VCX2_fpdp:
22683 case ARM::CDE_VCX2_fpsp: {
22684 switch (OpNum) {
22685 case 1:
22686 // op: coproc
22687 return 8;
22688 case 3:
22689 // op: imm
22690 return 4;
22691 case 0:
22692 // op: Vd
22693 return 12;
22694 case 2:
22695 // op: Vm
22696 return 0;
22697 }
22698 break;
22699 }
22700 case ARM::CDE_CX2A:
22701 case ARM::CDE_CX2DA: {
22702 switch (OpNum) {
22703 case 1:
22704 // op: coproc
22705 return 8;
22706 case 4:
22707 // op: imm
22708 return 0;
22709 case 0:
22710 // op: Rd
22711 return 12;
22712 case 3:
22713 // op: Rn
22714 return 16;
22715 }
22716 break;
22717 }
22718 case ARM::CDE_VCX3_vec: {
22719 switch (OpNum) {
22720 case 1:
22721 // op: coproc
22722 return 8;
22723 case 4:
22724 // op: imm
22725 return 4;
22726 case 0:
22727 // op: Qd
22728 return 13;
22729 case 3:
22730 // op: Qm
22731 return 1;
22732 case 2:
22733 // op: Qn
22734 return 17;
22735 }
22736 break;
22737 }
22738 case ARM::CDE_VCX2A_vec: {
22739 switch (OpNum) {
22740 case 1:
22741 // op: coproc
22742 return 8;
22743 case 4:
22744 // op: imm
22745 return 4;
22746 case 0:
22747 // op: Qd
22748 return 13;
22749 case 3:
22750 // op: Qm
22751 return 1;
22752 }
22753 break;
22754 }
22755 case ARM::CDE_CX3:
22756 case ARM::CDE_CX3D: {
22757 switch (OpNum) {
22758 case 1:
22759 // op: coproc
22760 return 8;
22761 case 4:
22762 // op: imm
22763 return 4;
22764 case 0:
22765 // op: Rd
22766 return 0;
22767 case 2:
22768 // op: Rn
22769 return 16;
22770 case 3:
22771 // op: Rm
22772 return 12;
22773 }
22774 break;
22775 }
22776 case ARM::CDE_VCX3_fpdp:
22777 case ARM::CDE_VCX3_fpsp: {
22778 switch (OpNum) {
22779 case 1:
22780 // op: coproc
22781 return 8;
22782 case 4:
22783 // op: imm
22784 return 4;
22785 case 0:
22786 // op: Vd
22787 return 12;
22788 case 3:
22789 // op: Vm
22790 return 0;
22791 case 2:
22792 // op: Vn
22793 return 7;
22794 }
22795 break;
22796 }
22797 case ARM::CDE_VCX2A_fpdp:
22798 case ARM::CDE_VCX2A_fpsp: {
22799 switch (OpNum) {
22800 case 1:
22801 // op: coproc
22802 return 8;
22803 case 4:
22804 // op: imm
22805 return 4;
22806 case 0:
22807 // op: Vd
22808 return 12;
22809 case 3:
22810 // op: Vm
22811 return 0;
22812 }
22813 break;
22814 }
22815 case ARM::CDE_VCX3A_vec: {
22816 switch (OpNum) {
22817 case 1:
22818 // op: coproc
22819 return 8;
22820 case 5:
22821 // op: imm
22822 return 4;
22823 case 0:
22824 // op: Qd
22825 return 13;
22826 case 4:
22827 // op: Qm
22828 return 1;
22829 case 3:
22830 // op: Qn
22831 return 17;
22832 }
22833 break;
22834 }
22835 case ARM::CDE_CX3A:
22836 case ARM::CDE_CX3DA: {
22837 switch (OpNum) {
22838 case 1:
22839 // op: coproc
22840 return 8;
22841 case 5:
22842 // op: imm
22843 return 4;
22844 case 0:
22845 // op: Rd
22846 return 0;
22847 case 3:
22848 // op: Rn
22849 return 16;
22850 case 4:
22851 // op: Rm
22852 return 12;
22853 }
22854 break;
22855 }
22856 case ARM::CDE_VCX3A_fpdp:
22857 case ARM::CDE_VCX3A_fpsp: {
22858 switch (OpNum) {
22859 case 1:
22860 // op: coproc
22861 return 8;
22862 case 5:
22863 // op: imm
22864 return 4;
22865 case 0:
22866 // op: Vd
22867 return 12;
22868 case 4:
22869 // op: Vm
22870 return 0;
22871 case 3:
22872 // op: Vn
22873 return 7;
22874 }
22875 break;
22876 }
22877 case ARM::MVE_VMOVimmf32:
22878 case ARM::MVE_VMOVimmi8:
22879 case ARM::MVE_VMOVimmi16:
22880 case ARM::MVE_VMOVimmi32:
22881 case ARM::MVE_VMOVimmi64:
22882 case ARM::MVE_VMVNimmi16:
22883 case ARM::MVE_VMVNimmi32: {
22884 switch (OpNum) {
22885 case 1:
22886 // op: imm
22887 return 0;
22888 case 0:
22889 // op: Qd
22890 return 13;
22891 }
22892 break;
22893 }
22894 case ARM::CDP2:
22895 case ARM::t2CDP:
22896 case ARM::t2CDP2: {
22897 switch (OpNum) {
22898 case 1:
22899 // op: opc1
22900 return 20;
22901 case 3:
22902 // op: CRn
22903 return 16;
22904 case 2:
22905 // op: CRd
22906 return 12;
22907 case 0:
22908 // op: cop
22909 return 8;
22910 case 5:
22911 // op: opc2
22912 return 5;
22913 case 4:
22914 // op: CRm
22915 return 0;
22916 }
22917 break;
22918 }
22919 case ARM::t2Bcc: {
22920 switch (OpNum) {
22921 case 1:
22922 // op: p
22923 return 22;
22924 case 0:
22925 // op: target
22926 return 0;
22927 }
22928 break;
22929 }
22930 case ARM::VCMPEZD:
22931 case ARM::VCMPZD: {
22932 switch (OpNum) {
22933 case 1:
22934 // op: p
22935 return 28;
22936 case 0:
22937 // op: Dd
22938 return 12;
22939 }
22940 break;
22941 }
22942 case ARM::MRS:
22943 case ARM::MRSsys: {
22944 switch (OpNum) {
22945 case 1:
22946 // op: p
22947 return 28;
22948 case 0:
22949 // op: Rd
22950 return 12;
22951 }
22952 break;
22953 }
22954 case ARM::VLDMSIA:
22955 case ARM::VSTMSIA: {
22956 switch (OpNum) {
22957 case 1:
22958 // op: p
22959 return 28;
22960 case 0:
22961 // op: Rn
22962 return 16;
22963 case 3:
22964 // op: regs
22965 return 0;
22966 }
22967 break;
22968 }
22969 case ARM::FLDMXIA:
22970 case ARM::FSTMXIA:
22971 case ARM::VLDMDIA:
22972 case ARM::VSTMDIA: {
22973 switch (OpNum) {
22974 case 1:
22975 // op: p
22976 return 28;
22977 case 0:
22978 // op: Rn
22979 return 16;
22980 case 3:
22981 // op: regs
22982 return 1;
22983 }
22984 break;
22985 }
22986 case ARM::VMRS:
22987 case ARM::VMRS_FPCXTNS:
22988 case ARM::VMRS_FPCXTS:
22989 case ARM::VMRS_FPEXC:
22990 case ARM::VMRS_FPINST:
22991 case ARM::VMRS_FPINST2:
22992 case ARM::VMRS_FPSID:
22993 case ARM::VMRS_MVFR0:
22994 case ARM::VMRS_MVFR1:
22995 case ARM::VMRS_MVFR2:
22996 case ARM::VMRS_VPR:
22997 case ARM::VMSR:
22998 case ARM::VMSR_FPCXTNS:
22999 case ARM::VMSR_FPCXTS:
23000 case ARM::VMSR_FPEXC:
23001 case ARM::VMSR_FPINST:
23002 case ARM::VMSR_FPINST2:
23003 case ARM::VMSR_FPSID:
23004 case ARM::VMSR_VPR: {
23005 switch (OpNum) {
23006 case 1:
23007 // op: p
23008 return 28;
23009 case 0:
23010 // op: Rt
23011 return 12;
23012 }
23013 break;
23014 }
23015 case ARM::VCMPEZH:
23016 case ARM::VCMPEZS:
23017 case ARM::VCMPZH:
23018 case ARM::VCMPZS: {
23019 switch (OpNum) {
23020 case 1:
23021 // op: p
23022 return 28;
23023 case 0:
23024 // op: Sd
23025 return 12;
23026 }
23027 break;
23028 }
23029 case ARM::BX_pred: {
23030 switch (OpNum) {
23031 case 1:
23032 // op: p
23033 return 28;
23034 case 0:
23035 // op: dst
23036 return 0;
23037 }
23038 break;
23039 }
23040 case ARM::BLX_pred:
23041 case ARM::BL_pred:
23042 case ARM::BXJ: {
23043 switch (OpNum) {
23044 case 1:
23045 // op: p
23046 return 28;
23047 case 0:
23048 // op: func
23049 return 0;
23050 }
23051 break;
23052 }
23053 case ARM::HINT: {
23054 switch (OpNum) {
23055 case 1:
23056 // op: p
23057 return 28;
23058 case 0:
23059 // op: imm
23060 return 0;
23061 }
23062 break;
23063 }
23064 case ARM::DBG:
23065 case ARM::SMC: {
23066 switch (OpNum) {
23067 case 1:
23068 // op: p
23069 return 28;
23070 case 0:
23071 // op: opt
23072 return 0;
23073 }
23074 break;
23075 }
23076 case ARM::SVC: {
23077 switch (OpNum) {
23078 case 1:
23079 // op: p
23080 return 28;
23081 case 0:
23082 // op: svc
23083 return 0;
23084 }
23085 break;
23086 }
23087 case ARM::Bcc: {
23088 switch (OpNum) {
23089 case 1:
23090 // op: p
23091 return 28;
23092 case 0:
23093 // op: target
23094 return 0;
23095 }
23096 break;
23097 }
23098 case ARM::LDMDA:
23099 case ARM::LDMDB:
23100 case ARM::LDMIA:
23101 case ARM::LDMIB:
23102 case ARM::STMDA:
23103 case ARM::STMDB:
23104 case ARM::STMIA:
23105 case ARM::STMIB:
23106 case ARM::sysLDMDA:
23107 case ARM::sysLDMDB:
23108 case ARM::sysLDMIA:
23109 case ARM::sysLDMIB:
23110 case ARM::sysSTMDA:
23111 case ARM::sysSTMDB:
23112 case ARM::sysSTMIA:
23113 case ARM::sysSTMIB: {
23114 switch (OpNum) {
23115 case 1:
23116 // op: p
23117 return 28;
23118 case 3:
23119 // op: regs
23120 return 0;
23121 case 0:
23122 // op: Rn
23123 return 16;
23124 }
23125 break;
23126 }
23127 case ARM::tBcc: {
23128 switch (OpNum) {
23129 case 1:
23130 // op: p
23131 return 8;
23132 case 0:
23133 // op: target
23134 return 0;
23135 }
23136 break;
23137 }
23138 case ARM::tCBNZ:
23139 case ARM::tCBZ: {
23140 switch (OpNum) {
23141 case 1:
23142 // op: target
23143 return 3;
23144 case 0:
23145 // op: Rn
23146 return 0;
23147 }
23148 break;
23149 }
23150 case ARM::MVE_VCADDf16:
23151 case ARM::MVE_VCADDf32: {
23152 switch (OpNum) {
23153 case 2:
23154 // op: Qm
23155 return 1;
23156 case 0:
23157 // op: Qd
23158 return 13;
23159 case 1:
23160 // op: Qn
23161 return 7;
23162 case 3:
23163 // op: rot
23164 return 24;
23165 }
23166 break;
23167 }
23168 case ARM::MVE_VABDf16:
23169 case ARM::MVE_VABDf32:
23170 case ARM::MVE_VADDf16:
23171 case ARM::MVE_VADDf32:
23172 case ARM::MVE_VMULf16:
23173 case ARM::MVE_VMULf32:
23174 case ARM::MVE_VSUBf16:
23175 case ARM::MVE_VSUBf32: {
23176 switch (OpNum) {
23177 case 2:
23178 // op: Qm
23179 return 1;
23180 case 0:
23181 // op: Qd
23182 return 13;
23183 case 1:
23184 // op: Qn
23185 return 7;
23186 }
23187 break;
23188 }
23189 case ARM::MVE_VADDVs8acc:
23190 case ARM::MVE_VADDVs16acc:
23191 case ARM::MVE_VADDVs32acc:
23192 case ARM::MVE_VADDVu8acc:
23193 case ARM::MVE_VADDVu16acc:
23194 case ARM::MVE_VADDVu32acc: {
23195 switch (OpNum) {
23196 case 2:
23197 // op: Qm
23198 return 1;
23199 case 0:
23200 // op: Rda
23201 return 13;
23202 }
23203 break;
23204 }
23205 case ARM::MVE_VMAXAVs8:
23206 case ARM::MVE_VMAXAVs16:
23207 case ARM::MVE_VMAXAVs32:
23208 case ARM::MVE_VMAXNMAVf16:
23209 case ARM::MVE_VMAXNMAVf32:
23210 case ARM::MVE_VMAXNMVf16:
23211 case ARM::MVE_VMAXNMVf32:
23212 case ARM::MVE_VMAXVs8:
23213 case ARM::MVE_VMAXVs16:
23214 case ARM::MVE_VMAXVs32:
23215 case ARM::MVE_VMAXVu8:
23216 case ARM::MVE_VMAXVu16:
23217 case ARM::MVE_VMAXVu32:
23218 case ARM::MVE_VMINAVs8:
23219 case ARM::MVE_VMINAVs16:
23220 case ARM::MVE_VMINAVs32:
23221 case ARM::MVE_VMINNMAVf16:
23222 case ARM::MVE_VMINNMAVf32:
23223 case ARM::MVE_VMINNMVf16:
23224 case ARM::MVE_VMINNMVf32:
23225 case ARM::MVE_VMINVs8:
23226 case ARM::MVE_VMINVs16:
23227 case ARM::MVE_VMINVs32:
23228 case ARM::MVE_VMINVu8:
23229 case ARM::MVE_VMINVu16:
23230 case ARM::MVE_VMINVu32: {
23231 switch (OpNum) {
23232 case 2:
23233 // op: Qm
23234 return 1;
23235 case 0:
23236 // op: RdaDest
23237 return 12;
23238 }
23239 break;
23240 }
23241 case ARM::MVE_VADDLVs32no_acc:
23242 case ARM::MVE_VADDLVu32no_acc: {
23243 switch (OpNum) {
23244 case 2:
23245 // op: Qm
23246 return 1;
23247 case 0:
23248 // op: RdaLo
23249 return 13;
23250 case 1:
23251 // op: RdaHi
23252 return 20;
23253 }
23254 break;
23255 }
23256 case ARM::t2AUTG:
23257 case ARM::t2BXAUT: {
23258 switch (OpNum) {
23259 case 2:
23260 // op: Ra
23261 return 12;
23262 case 3:
23263 // op: Rn
23264 return 16;
23265 case 4:
23266 // op: Rm
23267 return 0;
23268 }
23269 break;
23270 }
23271 case ARM::tADDspr: {
23272 switch (OpNum) {
23273 case 2:
23274 // op: Rm
23275 return 3;
23276 }
23277 break;
23278 }
23279 case ARM::MVE_VMOV_q_rr: {
23280 switch (OpNum) {
23281 case 2:
23282 // op: Rt
23283 return 0;
23284 case 3:
23285 // op: Rt2
23286 return 16;
23287 case 0:
23288 // op: Qd
23289 return 13;
23290 case 5:
23291 // op: idx2
23292 return 4;
23293 }
23294 break;
23295 }
23296 case ARM::MCR2:
23297 case ARM::t2MCR:
23298 case ARM::t2MCR2: {
23299 switch (OpNum) {
23300 case 2:
23301 // op: Rt
23302 return 12;
23303 case 0:
23304 // op: cop
23305 return 8;
23306 case 1:
23307 // op: opc1
23308 return 21;
23309 case 5:
23310 // op: opc2
23311 return 5;
23312 case 4:
23313 // op: CRm
23314 return 0;
23315 case 3:
23316 // op: CRn
23317 return 16;
23318 }
23319 break;
23320 }
23321 case ARM::MCRR2:
23322 case ARM::t2MCRR:
23323 case ARM::t2MCRR2: {
23324 switch (OpNum) {
23325 case 2:
23326 // op: Rt
23327 return 12;
23328 case 3:
23329 // op: Rt2
23330 return 16;
23331 case 0:
23332 // op: cop
23333 return 8;
23334 case 1:
23335 // op: opc1
23336 return 4;
23337 case 4:
23338 // op: CRm
23339 return 0;
23340 }
23341 break;
23342 }
23343 case ARM::VST1LNd8: {
23344 switch (OpNum) {
23345 case 2:
23346 // op: Vd
23347 return 12;
23348 case 0:
23349 // op: Rn
23350 return 16;
23351 case 3:
23352 // op: lane
23353 return 5;
23354 }
23355 break;
23356 }
23357 case ARM::VST3LNd8: {
23358 switch (OpNum) {
23359 case 2:
23360 // op: Vd
23361 return 12;
23362 case 0:
23363 // op: Rn
23364 return 16;
23365 case 5:
23366 // op: lane
23367 return 5;
23368 }
23369 break;
23370 }
23371 case ARM::VST3LNd16:
23372 case ARM::VST3LNq16: {
23373 switch (OpNum) {
23374 case 2:
23375 // op: Vd
23376 return 12;
23377 case 0:
23378 // op: Rn
23379 return 16;
23380 case 5:
23381 // op: lane
23382 return 6;
23383 }
23384 break;
23385 }
23386 case ARM::VST3LNd32:
23387 case ARM::VST3LNq32: {
23388 switch (OpNum) {
23389 case 2:
23390 // op: Vd
23391 return 12;
23392 case 0:
23393 // op: Rn
23394 return 16;
23395 case 5:
23396 // op: lane
23397 return 7;
23398 }
23399 break;
23400 }
23401 case ARM::VST1LNd16: {
23402 switch (OpNum) {
23403 case 2:
23404 // op: Vd
23405 return 12;
23406 case 0:
23407 // op: Rn
23408 return 4;
23409 case 3:
23410 // op: lane
23411 return 6;
23412 }
23413 break;
23414 }
23415 case ARM::VST1LNd32: {
23416 switch (OpNum) {
23417 case 2:
23418 // op: Vd
23419 return 12;
23420 case 0:
23421 // op: Rn
23422 return 4;
23423 case 3:
23424 // op: lane
23425 return 7;
23426 }
23427 break;
23428 }
23429 case ARM::VST2LNd8: {
23430 switch (OpNum) {
23431 case 2:
23432 // op: Vd
23433 return 12;
23434 case 0:
23435 // op: Rn
23436 return 4;
23437 case 4:
23438 // op: lane
23439 return 5;
23440 }
23441 break;
23442 }
23443 case ARM::VST2LNd16:
23444 case ARM::VST2LNq16: {
23445 switch (OpNum) {
23446 case 2:
23447 // op: Vd
23448 return 12;
23449 case 0:
23450 // op: Rn
23451 return 4;
23452 case 4:
23453 // op: lane
23454 return 6;
23455 }
23456 break;
23457 }
23458 case ARM::VST2LNd32:
23459 case ARM::VST2LNq32: {
23460 switch (OpNum) {
23461 case 2:
23462 // op: Vd
23463 return 12;
23464 case 0:
23465 // op: Rn
23466 return 4;
23467 case 4:
23468 // op: lane
23469 return 7;
23470 }
23471 break;
23472 }
23473 case ARM::VST4LNd8: {
23474 switch (OpNum) {
23475 case 2:
23476 // op: Vd
23477 return 12;
23478 case 0:
23479 // op: Rn
23480 return 4;
23481 case 6:
23482 // op: lane
23483 return 5;
23484 }
23485 break;
23486 }
23487 case ARM::VST4LNd16:
23488 case ARM::VST4LNq16: {
23489 switch (OpNum) {
23490 case 2:
23491 // op: Vd
23492 return 12;
23493 case 0:
23494 // op: Rn
23495 return 4;
23496 case 6:
23497 // op: lane
23498 return 6;
23499 }
23500 break;
23501 }
23502 case ARM::VST4LNd32:
23503 case ARM::VST4LNq32: {
23504 switch (OpNum) {
23505 case 2:
23506 // op: Vd
23507 return 12;
23508 case 0:
23509 // op: Rn
23510 return 4;
23511 case 6:
23512 // op: lane
23513 return 7;
23514 }
23515 break;
23516 }
23517 case ARM::VST1d8:
23518 case ARM::VST1d8Q:
23519 case ARM::VST1d8T:
23520 case ARM::VST1d16:
23521 case ARM::VST1d16Q:
23522 case ARM::VST1d16T:
23523 case ARM::VST1d32:
23524 case ARM::VST1d32Q:
23525 case ARM::VST1d32T:
23526 case ARM::VST1d64:
23527 case ARM::VST1d64Q:
23528 case ARM::VST1d64T:
23529 case ARM::VST1q8:
23530 case ARM::VST1q16:
23531 case ARM::VST1q32:
23532 case ARM::VST1q64:
23533 case ARM::VST2b8:
23534 case ARM::VST2b16:
23535 case ARM::VST2b32:
23536 case ARM::VST2d8:
23537 case ARM::VST2d16:
23538 case ARM::VST2d32:
23539 case ARM::VST2q8:
23540 case ARM::VST2q16:
23541 case ARM::VST2q32:
23542 case ARM::VST3d8:
23543 case ARM::VST3d16:
23544 case ARM::VST3d32:
23545 case ARM::VST3q8:
23546 case ARM::VST3q16:
23547 case ARM::VST3q32:
23548 case ARM::VST4d8:
23549 case ARM::VST4d16:
23550 case ARM::VST4d32:
23551 case ARM::VST4q8:
23552 case ARM::VST4q16:
23553 case ARM::VST4q32: {
23554 switch (OpNum) {
23555 case 2:
23556 // op: Vd
23557 return 12;
23558 case 0:
23559 // op: Rn
23560 return 4;
23561 }
23562 break;
23563 }
23564 case ARM::LDC2L_OFFSET:
23565 case ARM::LDC2L_PRE:
23566 case ARM::LDC2_OFFSET:
23567 case ARM::LDC2_PRE:
23568 case ARM::STC2L_OFFSET:
23569 case ARM::STC2L_PRE:
23570 case ARM::STC2_OFFSET:
23571 case ARM::STC2_PRE:
23572 case ARM::t2LDC2L_OFFSET:
23573 case ARM::t2LDC2L_PRE:
23574 case ARM::t2LDC2_OFFSET:
23575 case ARM::t2LDC2_PRE:
23576 case ARM::t2LDCL_OFFSET:
23577 case ARM::t2LDCL_PRE:
23578 case ARM::t2LDC_OFFSET:
23579 case ARM::t2LDC_PRE:
23580 case ARM::t2STC2L_OFFSET:
23581 case ARM::t2STC2L_PRE:
23582 case ARM::t2STC2_OFFSET:
23583 case ARM::t2STC2_PRE:
23584 case ARM::t2STCL_OFFSET:
23585 case ARM::t2STCL_PRE:
23586 case ARM::t2STC_OFFSET:
23587 case ARM::t2STC_PRE: {
23588 switch (OpNum) {
23589 case 2:
23590 // op: addr
23591 return 0;
23592 case 0:
23593 // op: cop
23594 return 8;
23595 case 1:
23596 // op: CRd
23597 return 12;
23598 }
23599 break;
23600 }
23601 case ARM::t2LDAEXD:
23602 case ARM::t2LDREXD: {
23603 switch (OpNum) {
23604 case 2:
23605 // op: addr
23606 return 16;
23607 case 0:
23608 // op: Rt
23609 return 12;
23610 case 1:
23611 // op: Rt2
23612 return 8;
23613 }
23614 break;
23615 }
23616 case ARM::tBL: {
23617 switch (OpNum) {
23618 case 2:
23619 // op: func
23620 return 0;
23621 }
23622 break;
23623 }
23624 case ARM::tBLXi: {
23625 switch (OpNum) {
23626 case 2:
23627 // op: func
23628 return 1;
23629 }
23630 break;
23631 }
23632 case ARM::tBLXNSr:
23633 case ARM::tBLXr: {
23634 switch (OpNum) {
23635 case 2:
23636 // op: func
23637 return 3;
23638 }
23639 break;
23640 }
23641 case ARM::MVE_VBICimmi16:
23642 case ARM::MVE_VBICimmi32:
23643 case ARM::MVE_VORRimmi16:
23644 case ARM::MVE_VORRimmi32: {
23645 switch (OpNum) {
23646 case 2:
23647 // op: imm
23648 return 0;
23649 case 0:
23650 // op: Qd
23651 return 13;
23652 }
23653 break;
23654 }
23655 case ARM::t2ADDspImm12:
23656 case ARM::t2SUBspImm12:
23657 case ARM::tADDspi:
23658 case ARM::tSUBspi: {
23659 switch (OpNum) {
23660 case 2:
23661 // op: imm
23662 return 0;
23663 }
23664 break;
23665 }
23666 case ARM::MVE_LETP:
23667 case ARM::t2LEUpdate: {
23668 switch (OpNum) {
23669 case 2:
23670 // op: label
23671 return 1;
23672 }
23673 break;
23674 }
23675 case ARM::VABSD:
23676 case ARM::VCMPD:
23677 case ARM::VCMPED:
23678 case ARM::VMOVD:
23679 case ARM::VNEGD:
23680 case ARM::VRINTRD:
23681 case ARM::VRINTXD:
23682 case ARM::VRINTZD:
23683 case ARM::VSQRTD: {
23684 switch (OpNum) {
23685 case 2:
23686 // op: p
23687 return 28;
23688 case 0:
23689 // op: Dd
23690 return 12;
23691 case 1:
23692 // op: Dm
23693 return 0;
23694 }
23695 break;
23696 }
23697 case ARM::VCVTBHD:
23698 case ARM::VCVTTHD:
23699 case ARM::VSITOD:
23700 case ARM::VUITOD: {
23701 switch (OpNum) {
23702 case 2:
23703 // op: p
23704 return 28;
23705 case 0:
23706 // op: Dd
23707 return 12;
23708 case 1:
23709 // op: Sm
23710 return 0;
23711 }
23712 break;
23713 }
23714 case ARM::FCONSTD: {
23715 switch (OpNum) {
23716 case 2:
23717 // op: p
23718 return 28;
23719 case 0:
23720 // op: Dd
23721 return 12;
23722 case 1:
23723 // op: imm
23724 return 0;
23725 }
23726 break;
23727 }
23728 case ARM::CLZ:
23729 case ARM::RBIT:
23730 case ARM::REV:
23731 case ARM::REV16:
23732 case ARM::REVSH: {
23733 switch (OpNum) {
23734 case 2:
23735 // op: p
23736 return 28;
23737 case 0:
23738 // op: Rd
23739 return 12;
23740 case 1:
23741 // op: Rm
23742 return 0;
23743 }
23744 break;
23745 }
23746 case ARM::MOVi16: {
23747 switch (OpNum) {
23748 case 2:
23749 // op: p
23750 return 28;
23751 case 0:
23752 // op: Rd
23753 return 12;
23754 case 1:
23755 // op: imm
23756 return 0;
23757 }
23758 break;
23759 }
23760 case ARM::ADR: {
23761 switch (OpNum) {
23762 case 2:
23763 // op: p
23764 return 28;
23765 case 0:
23766 // op: Rd
23767 return 12;
23768 case 1:
23769 // op: label
23770 return 0;
23771 }
23772 break;
23773 }
23774 case ARM::CMNzrr:
23775 case ARM::CMPrr:
23776 case ARM::TEQrr:
23777 case ARM::TSTrr: {
23778 switch (OpNum) {
23779 case 2:
23780 // op: p
23781 return 28;
23782 case 0:
23783 // op: Rn
23784 return 16;
23785 case 1:
23786 // op: Rm
23787 return 0;
23788 }
23789 break;
23790 }
23791 case ARM::CMNri:
23792 case ARM::CMPri:
23793 case ARM::TEQri:
23794 case ARM::TSTri: {
23795 switch (OpNum) {
23796 case 2:
23797 // op: p
23798 return 28;
23799 case 0:
23800 // op: Rn
23801 return 16;
23802 case 1:
23803 // op: imm
23804 return 0;
23805 }
23806 break;
23807 }
23808 case ARM::STL:
23809 case ARM::STLB:
23810 case ARM::STLH: {
23811 switch (OpNum) {
23812 case 2:
23813 // op: p
23814 return 28;
23815 case 0:
23816 // op: Rt
23817 return 0;
23818 case 1:
23819 // op: addr
23820 return 16;
23821 }
23822 break;
23823 }
23824 case ARM::VMOVRH:
23825 case ARM::VMOVRS: {
23826 switch (OpNum) {
23827 case 2:
23828 // op: p
23829 return 28;
23830 case 0:
23831 // op: Rt
23832 return 12;
23833 case 1:
23834 // op: Sn
23835 return 7;
23836 }
23837 break;
23838 }
23839 case ARM::LDA:
23840 case ARM::LDAB:
23841 case ARM::LDAEX:
23842 case ARM::LDAEXB:
23843 case ARM::LDAEXD:
23844 case ARM::LDAEXH:
23845 case ARM::LDAH:
23846 case ARM::LDREX:
23847 case ARM::LDREXB:
23848 case ARM::LDREXD:
23849 case ARM::LDREXH: {
23850 switch (OpNum) {
23851 case 2:
23852 // op: p
23853 return 28;
23854 case 0:
23855 // op: Rt
23856 return 12;
23857 case 1:
23858 // op: addr
23859 return 16;
23860 }
23861 break;
23862 }
23863 case ARM::VMRS_FPSCR_NZCVQC:
23864 case ARM::VMRS_P0: {
23865 switch (OpNum) {
23866 case 2:
23867 // op: p
23868 return 28;
23869 case 0:
23870 // op: Rt
23871 return 12;
23872 }
23873 break;
23874 }
23875 case ARM::VCVTSD:
23876 case ARM::VJCVT:
23877 case ARM::VTOSIRD:
23878 case ARM::VTOSIZD:
23879 case ARM::VTOUIRD:
23880 case ARM::VTOUIZD: {
23881 switch (OpNum) {
23882 case 2:
23883 // op: p
23884 return 28;
23885 case 0:
23886 // op: Sd
23887 return 12;
23888 case 1:
23889 // op: Dm
23890 return 0;
23891 }
23892 break;
23893 }
23894 case ARM::VABSH:
23895 case ARM::VABSS:
23896 case ARM::VCMPEH:
23897 case ARM::VCMPES:
23898 case ARM::VCMPH:
23899 case ARM::VCMPS:
23900 case ARM::VCVTBHS:
23901 case ARM::VCVTTHS:
23902 case ARM::VMOVS:
23903 case ARM::VNEGH:
23904 case ARM::VNEGS:
23905 case ARM::VRINTRH:
23906 case ARM::VRINTRS:
23907 case ARM::VRINTXH:
23908 case ARM::VRINTXS:
23909 case ARM::VRINTZH:
23910 case ARM::VRINTZS:
23911 case ARM::VSITOH:
23912 case ARM::VSITOS:
23913 case ARM::VSQRTH:
23914 case ARM::VSQRTS:
23915 case ARM::VTOSIRH:
23916 case ARM::VTOSIRS:
23917 case ARM::VTOSIZH:
23918 case ARM::VTOSIZS:
23919 case ARM::VTOUIRH:
23920 case ARM::VTOUIRS:
23921 case ARM::VTOUIZH:
23922 case ARM::VTOUIZS:
23923 case ARM::VUITOH:
23924 case ARM::VUITOS: {
23925 switch (OpNum) {
23926 case 2:
23927 // op: p
23928 return 28;
23929 case 0:
23930 // op: Sd
23931 return 12;
23932 case 1:
23933 // op: Sm
23934 return 0;
23935 }
23936 break;
23937 }
23938 case ARM::FCONSTH:
23939 case ARM::FCONSTS: {
23940 switch (OpNum) {
23941 case 2:
23942 // op: p
23943 return 28;
23944 case 0:
23945 // op: Sd
23946 return 12;
23947 case 1:
23948 // op: imm
23949 return 0;
23950 }
23951 break;
23952 }
23953 case ARM::VMOVHR:
23954 case ARM::VMOVSR: {
23955 switch (OpNum) {
23956 case 2:
23957 // op: p
23958 return 28;
23959 case 0:
23960 // op: Sn
23961 return 7;
23962 case 1:
23963 // op: Rt
23964 return 12;
23965 }
23966 break;
23967 }
23968 case ARM::VLDR_FPCXTNS_off:
23969 case ARM::VLDR_FPCXTS_off:
23970 case ARM::VLDR_FPSCR_NZCVQC_off:
23971 case ARM::VLDR_FPSCR_off:
23972 case ARM::VLDR_VPR_off:
23973 case ARM::VSTR_FPCXTNS_off:
23974 case ARM::VSTR_FPCXTS_off:
23975 case ARM::VSTR_FPSCR_NZCVQC_off:
23976 case ARM::VSTR_FPSCR_off:
23977 case ARM::VSTR_VPR_off: {
23978 switch (OpNum) {
23979 case 2:
23980 // op: p
23981 return 28;
23982 case 0:
23983 // op: addr
23984 return 0;
23985 }
23986 break;
23987 }
23988 case ARM::MSRbanked: {
23989 switch (OpNum) {
23990 case 2:
23991 // op: p
23992 return 28;
23993 case 0:
23994 // op: banked
23995 return 8;
23996 case 1:
23997 // op: Rn
23998 return 0;
23999 }
24000 break;
24001 }
24002 case ARM::MSR: {
24003 switch (OpNum) {
24004 case 2:
24005 // op: p
24006 return 28;
24007 case 0:
24008 // op: mask
24009 return 16;
24010 case 1:
24011 // op: Rn
24012 return 0;
24013 }
24014 break;
24015 }
24016 case ARM::MSRi: {
24017 switch (OpNum) {
24018 case 2:
24019 // op: p
24020 return 28;
24021 case 0:
24022 // op: mask
24023 return 16;
24024 case 1:
24025 // op: imm
24026 return 0;
24027 }
24028 break;
24029 }
24030 case ARM::VLDMSDB_UPD:
24031 case ARM::VLDMSIA_UPD:
24032 case ARM::VSTMSDB_UPD:
24033 case ARM::VSTMSIA_UPD: {
24034 switch (OpNum) {
24035 case 2:
24036 // op: p
24037 return 28;
24038 case 1:
24039 // op: Rn
24040 return 16;
24041 case 4:
24042 // op: regs
24043 return 0;
24044 }
24045 break;
24046 }
24047 case ARM::FLDMXDB_UPD:
24048 case ARM::FLDMXIA_UPD:
24049 case ARM::FSTMXDB_UPD:
24050 case ARM::FSTMXIA_UPD:
24051 case ARM::VLDMDDB_UPD:
24052 case ARM::VLDMDIA_UPD:
24053 case ARM::VSTMDDB_UPD:
24054 case ARM::VSTMDIA_UPD: {
24055 switch (OpNum) {
24056 case 2:
24057 // op: p
24058 return 28;
24059 case 1:
24060 // op: Rn
24061 return 16;
24062 case 4:
24063 // op: regs
24064 return 1;
24065 }
24066 break;
24067 }
24068 case ARM::VMSR_FPSCR_NZCVQC:
24069 case ARM::VMSR_P0: {
24070 switch (OpNum) {
24071 case 2:
24072 // op: p
24073 return 28;
24074 case 1:
24075 // op: Rt
24076 return 12;
24077 }
24078 break;
24079 }
24080 case ARM::VCVTDS: {
24081 switch (OpNum) {
24082 case 2:
24083 // op: p
24084 return 28;
24085 case 1:
24086 // op: Sm
24087 return 0;
24088 case 0:
24089 // op: Dd
24090 return 12;
24091 }
24092 break;
24093 }
24094 case ARM::MRSbanked: {
24095 switch (OpNum) {
24096 case 2:
24097 // op: p
24098 return 28;
24099 case 1:
24100 // op: banked
24101 return 8;
24102 case 0:
24103 // op: Rd
24104 return 12;
24105 }
24106 break;
24107 }
24108 case ARM::LDMDA_UPD:
24109 case ARM::LDMDB_UPD:
24110 case ARM::LDMIA_UPD:
24111 case ARM::LDMIB_UPD:
24112 case ARM::STMDA_UPD:
24113 case ARM::STMDB_UPD:
24114 case ARM::STMIA_UPD:
24115 case ARM::STMIB_UPD:
24116 case ARM::sysLDMDA_UPD:
24117 case ARM::sysLDMDB_UPD:
24118 case ARM::sysLDMIA_UPD:
24119 case ARM::sysLDMIB_UPD:
24120 case ARM::sysSTMDA_UPD:
24121 case ARM::sysSTMDB_UPD:
24122 case ARM::sysSTMIA_UPD:
24123 case ARM::sysSTMIB_UPD: {
24124 switch (OpNum) {
24125 case 2:
24126 // op: p
24127 return 28;
24128 case 4:
24129 // op: regs
24130 return 0;
24131 case 1:
24132 // op: Rn
24133 return 16;
24134 }
24135 break;
24136 }
24137 case ARM::MOVr:
24138 case ARM::MOVr_TC:
24139 case ARM::MVNr: {
24140 switch (OpNum) {
24141 case 2:
24142 // op: p
24143 return 28;
24144 case 4:
24145 // op: s
24146 return 20;
24147 case 0:
24148 // op: Rd
24149 return 12;
24150 case 1:
24151 // op: Rm
24152 return 0;
24153 }
24154 break;
24155 }
24156 case ARM::MOVi:
24157 case ARM::MVNi: {
24158 switch (OpNum) {
24159 case 2:
24160 // op: p
24161 return 28;
24162 case 4:
24163 // op: s
24164 return 20;
24165 case 0:
24166 // op: Rd
24167 return 12;
24168 case 1:
24169 // op: imm
24170 return 0;
24171 }
24172 break;
24173 }
24174 case ARM::VSCCLRMS:
24175 case ARM::t2CLRM:
24176 case ARM::tPOP:
24177 case ARM::tPUSH: {
24178 switch (OpNum) {
24179 case 2:
24180 // op: regs
24181 return 0;
24182 }
24183 break;
24184 }
24185 case ARM::VSCCLRMD: {
24186 switch (OpNum) {
24187 case 2:
24188 // op: regs
24189 return 1;
24190 }
24191 break;
24192 }
24193 case ARM::MVE_VCMLAf16:
24194 case ARM::MVE_VCMLAf32: {
24195 switch (OpNum) {
24196 case 3:
24197 // op: Qm
24198 return 1;
24199 case 0:
24200 // op: Qd
24201 return 13;
24202 case 2:
24203 // op: Qn
24204 return 7;
24205 case 4:
24206 // op: rot
24207 return 23;
24208 }
24209 break;
24210 }
24211 case ARM::MVE_VFMAf16:
24212 case ARM::MVE_VFMAf32:
24213 case ARM::MVE_VFMSf16:
24214 case ARM::MVE_VFMSf32: {
24215 switch (OpNum) {
24216 case 3:
24217 // op: Qm
24218 return 1;
24219 case 0:
24220 // op: Qd
24221 return 13;
24222 case 2:
24223 // op: Qn
24224 return 7;
24225 }
24226 break;
24227 }
24228 case ARM::MVE_VABAVs8:
24229 case ARM::MVE_VABAVs16:
24230 case ARM::MVE_VABAVs32:
24231 case ARM::MVE_VABAVu8:
24232 case ARM::MVE_VABAVu16:
24233 case ARM::MVE_VABAVu32: {
24234 switch (OpNum) {
24235 case 3:
24236 // op: Qm
24237 return 1;
24238 case 2:
24239 // op: Qn
24240 return 7;
24241 case 0:
24242 // op: Rda
24243 return 12;
24244 }
24245 break;
24246 }
24247 case ARM::tADDrr:
24248 case ARM::tSUBrr: {
24249 switch (OpNum) {
24250 case 3:
24251 // op: Rm
24252 return 6;
24253 case 2:
24254 // op: Rn
24255 return 3;
24256 case 0:
24257 // op: Rd
24258 return 0;
24259 }
24260 break;
24261 }
24262 case ARM::VST1d8Qwb_fixed:
24263 case ARM::VST1d8Twb_fixed:
24264 case ARM::VST1d8wb_fixed:
24265 case ARM::VST1d16Qwb_fixed:
24266 case ARM::VST1d16Twb_fixed:
24267 case ARM::VST1d16wb_fixed:
24268 case ARM::VST1d32Qwb_fixed:
24269 case ARM::VST1d32Twb_fixed:
24270 case ARM::VST1d32wb_fixed:
24271 case ARM::VST1d64Qwb_fixed:
24272 case ARM::VST1d64Twb_fixed:
24273 case ARM::VST1d64wb_fixed:
24274 case ARM::VST1q8wb_fixed:
24275 case ARM::VST1q16wb_fixed:
24276 case ARM::VST1q32wb_fixed:
24277 case ARM::VST1q64wb_fixed:
24278 case ARM::VST2b8wb_fixed:
24279 case ARM::VST2b16wb_fixed:
24280 case ARM::VST2b32wb_fixed:
24281 case ARM::VST2d8wb_fixed:
24282 case ARM::VST2d16wb_fixed:
24283 case ARM::VST2d32wb_fixed:
24284 case ARM::VST2q8wb_fixed:
24285 case ARM::VST2q16wb_fixed:
24286 case ARM::VST2q32wb_fixed: {
24287 switch (OpNum) {
24288 case 3:
24289 // op: Vd
24290 return 12;
24291 case 1:
24292 // op: Rn
24293 return 4;
24294 }
24295 break;
24296 }
24297 case ARM::t2BFic: {
24298 switch (OpNum) {
24299 case 3:
24300 // op: bcond
24301 return 18;
24302 case 1:
24303 // op: label
24304 return 1;
24305 case 2:
24306 // op: ba_label
24307 return 17;
24308 case 0:
24309 // op: b_label
24310 return 23;
24311 }
24312 break;
24313 }
24314 case ARM::MVE_VPTv4f32:
24315 case ARM::MVE_VPTv4s32:
24316 case ARM::MVE_VPTv8f16:
24317 case ARM::MVE_VPTv8s16:
24318 case ARM::MVE_VPTv16s8: {
24319 switch (OpNum) {
24320 case 3:
24321 // op: fc
24322 return 0;
24323 case 0:
24324 // op: Mk
24325 return 13;
24326 case 1:
24327 // op: Qn
24328 return 17;
24329 case 2:
24330 // op: Qm
24331 return 1;
24332 }
24333 break;
24334 }
24335 case ARM::MVE_VCMPf16:
24336 case ARM::MVE_VCMPf32:
24337 case ARM::MVE_VCMPs8:
24338 case ARM::MVE_VCMPs16:
24339 case ARM::MVE_VCMPs32: {
24340 switch (OpNum) {
24341 case 3:
24342 // op: fc
24343 return 0;
24344 case 1:
24345 // op: Qn
24346 return 17;
24347 case 2:
24348 // op: Qm
24349 return 1;
24350 }
24351 break;
24352 }
24353 case ARM::MVE_VPTv4f32r:
24354 case ARM::MVE_VPTv4s32r:
24355 case ARM::MVE_VPTv8f16r:
24356 case ARM::MVE_VPTv8s16r:
24357 case ARM::MVE_VPTv16s8r: {
24358 switch (OpNum) {
24359 case 3:
24360 // op: fc
24361 return 5;
24362 case 0:
24363 // op: Mk
24364 return 13;
24365 case 1:
24366 // op: Qn
24367 return 17;
24368 case 2:
24369 // op: Rm
24370 return 0;
24371 }
24372 break;
24373 }
24374 case ARM::MVE_VCMPf16r:
24375 case ARM::MVE_VCMPf32r:
24376 case ARM::MVE_VCMPs8r:
24377 case ARM::MVE_VCMPs16r:
24378 case ARM::MVE_VCMPs32r: {
24379 switch (OpNum) {
24380 case 3:
24381 // op: fc
24382 return 5;
24383 case 1:
24384 // op: Qn
24385 return 17;
24386 case 2:
24387 // op: Rm
24388 return 0;
24389 }
24390 break;
24391 }
24392 case ARM::MVE_VPTv4i32:
24393 case ARM::MVE_VPTv4u32:
24394 case ARM::MVE_VPTv8i16:
24395 case ARM::MVE_VPTv8u16:
24396 case ARM::MVE_VPTv16i8:
24397 case ARM::MVE_VPTv16u8: {
24398 switch (OpNum) {
24399 case 3:
24400 // op: fc
24401 return 7;
24402 case 0:
24403 // op: Mk
24404 return 13;
24405 case 1:
24406 // op: Qn
24407 return 17;
24408 case 2:
24409 // op: Qm
24410 return 1;
24411 }
24412 break;
24413 }
24414 case ARM::MVE_VPTv4i32r:
24415 case ARM::MVE_VPTv4u32r:
24416 case ARM::MVE_VPTv8i16r:
24417 case ARM::MVE_VPTv8u16r:
24418 case ARM::MVE_VPTv16i8r:
24419 case ARM::MVE_VPTv16u8r: {
24420 switch (OpNum) {
24421 case 3:
24422 // op: fc
24423 return 7;
24424 case 0:
24425 // op: Mk
24426 return 13;
24427 case 1:
24428 // op: Qn
24429 return 17;
24430 case 2:
24431 // op: Rm
24432 return 0;
24433 }
24434 break;
24435 }
24436 case ARM::MVE_VCMPi8:
24437 case ARM::MVE_VCMPi16:
24438 case ARM::MVE_VCMPi32:
24439 case ARM::MVE_VCMPu8:
24440 case ARM::MVE_VCMPu16:
24441 case ARM::MVE_VCMPu32: {
24442 switch (OpNum) {
24443 case 3:
24444 // op: fc
24445 return 7;
24446 case 1:
24447 // op: Qn
24448 return 17;
24449 case 2:
24450 // op: Qm
24451 return 1;
24452 }
24453 break;
24454 }
24455 case ARM::MVE_VCMPi8r:
24456 case ARM::MVE_VCMPi16r:
24457 case ARM::MVE_VCMPi32r:
24458 case ARM::MVE_VCMPu8r:
24459 case ARM::MVE_VCMPu16r:
24460 case ARM::MVE_VCMPu32r: {
24461 switch (OpNum) {
24462 case 3:
24463 // op: fc
24464 return 7;
24465 case 1:
24466 // op: Qn
24467 return 17;
24468 case 2:
24469 // op: Rm
24470 return 0;
24471 }
24472 break;
24473 }
24474 case ARM::LDC2L_POST:
24475 case ARM::LDC2_POST:
24476 case ARM::STC2L_POST:
24477 case ARM::STC2_POST:
24478 case ARM::t2LDC2L_POST:
24479 case ARM::t2LDC2_POST:
24480 case ARM::t2LDCL_POST:
24481 case ARM::t2LDC_POST:
24482 case ARM::t2STC2L_POST:
24483 case ARM::t2STC2_POST:
24484 case ARM::t2STCL_POST:
24485 case ARM::t2STC_POST: {
24486 switch (OpNum) {
24487 case 3:
24488 // op: offset
24489 return 0;
24490 case 2:
24491 // op: addr
24492 return 16;
24493 case 0:
24494 // op: cop
24495 return 8;
24496 case 1:
24497 // op: CRd
24498 return 12;
24499 }
24500 break;
24501 }
24502 case ARM::LDC2L_OPTION:
24503 case ARM::LDC2_OPTION:
24504 case ARM::STC2L_OPTION:
24505 case ARM::STC2_OPTION:
24506 case ARM::t2LDC2L_OPTION:
24507 case ARM::t2LDC2_OPTION:
24508 case ARM::t2LDCL_OPTION:
24509 case ARM::t2LDC_OPTION:
24510 case ARM::t2STC2L_OPTION:
24511 case ARM::t2STC2_OPTION:
24512 case ARM::t2STCL_OPTION:
24513 case ARM::t2STC_OPTION: {
24514 switch (OpNum) {
24515 case 3:
24516 // op: option
24517 return 0;
24518 case 2:
24519 // op: addr
24520 return 16;
24521 case 0:
24522 // op: cop
24523 return 8;
24524 case 1:
24525 // op: CRd
24526 return 12;
24527 }
24528 break;
24529 }
24530 case ARM::VADDD:
24531 case ARM::VDIVD:
24532 case ARM::VMULD:
24533 case ARM::VNMULD:
24534 case ARM::VSUBD: {
24535 switch (OpNum) {
24536 case 3:
24537 // op: p
24538 return 28;
24539 case 0:
24540 // op: Dd
24541 return 12;
24542 case 1:
24543 // op: Dn
24544 return 7;
24545 case 2:
24546 // op: Dm
24547 return 0;
24548 }
24549 break;
24550 }
24551 case ARM::VLDRD:
24552 case ARM::VSTRD: {
24553 switch (OpNum) {
24554 case 3:
24555 // op: p
24556 return 28;
24557 case 0:
24558 // op: Dd
24559 return 12;
24560 case 1:
24561 // op: addr
24562 return 0;
24563 }
24564 break;
24565 }
24566 case ARM::VMOVDRR: {
24567 switch (OpNum) {
24568 case 3:
24569 // op: p
24570 return 28;
24571 case 0:
24572 // op: Dm
24573 return 0;
24574 case 1:
24575 // op: Rt
24576 return 12;
24577 case 2:
24578 // op: Rt2
24579 return 16;
24580 }
24581 break;
24582 }
24583 case ARM::SXTB:
24584 case ARM::SXTB16:
24585 case ARM::SXTH:
24586 case ARM::UXTB:
24587 case ARM::UXTB16:
24588 case ARM::UXTH: {
24589 switch (OpNum) {
24590 case 3:
24591 // op: p
24592 return 28;
24593 case 0:
24594 // op: Rd
24595 return 12;
24596 case 1:
24597 // op: Rm
24598 return 0;
24599 case 2:
24600 // op: rot
24601 return 10;
24602 }
24603 break;
24604 }
24605 case ARM::SEL: {
24606 switch (OpNum) {
24607 case 3:
24608 // op: p
24609 return 28;
24610 case 0:
24611 // op: Rd
24612 return 12;
24613 case 1:
24614 // op: Rn
24615 return 16;
24616 case 2:
24617 // op: Rm
24618 return 0;
24619 }
24620 break;
24621 }
24622 case ARM::SSAT16:
24623 case ARM::USAT16: {
24624 switch (OpNum) {
24625 case 3:
24626 // op: p
24627 return 28;
24628 case 0:
24629 // op: Rd
24630 return 12;
24631 case 1:
24632 // op: sat_imm
24633 return 16;
24634 case 2:
24635 // op: Rn
24636 return 0;
24637 }
24638 break;
24639 }
24640 case ARM::MOVTi16: {
24641 switch (OpNum) {
24642 case 3:
24643 // op: p
24644 return 28;
24645 case 0:
24646 // op: Rd
24647 return 12;
24648 case 2:
24649 // op: imm
24650 return 0;
24651 }
24652 break;
24653 }
24654 case ARM::BFC: {
24655 switch (OpNum) {
24656 case 3:
24657 // op: p
24658 return 28;
24659 case 0:
24660 // op: Rd
24661 return 12;
24662 case 2:
24663 // op: imm
24664 return 7;
24665 }
24666 break;
24667 }
24668 case ARM::SDIV:
24669 case ARM::SMMUL:
24670 case ARM::SMMULR:
24671 case ARM::UDIV:
24672 case ARM::USAD8: {
24673 switch (OpNum) {
24674 case 3:
24675 // op: p
24676 return 28;
24677 case 0:
24678 // op: Rd
24679 return 16;
24680 case 1:
24681 // op: Rn
24682 return 0;
24683 case 2:
24684 // op: Rm
24685 return 8;
24686 }
24687 break;
24688 }
24689 case ARM::CMNzrsi:
24690 case ARM::CMPrsi:
24691 case ARM::TEQrsi:
24692 case ARM::TSTrsi: {
24693 switch (OpNum) {
24694 case 3:
24695 // op: p
24696 return 28;
24697 case 0:
24698 // op: Rn
24699 return 16;
24700 case 1:
24701 // op: shift
24702 return 0;
24703 }
24704 break;
24705 }
24706 case ARM::SWP:
24707 case ARM::SWPB: {
24708 switch (OpNum) {
24709 case 3:
24710 // op: p
24711 return 28;
24712 case 0:
24713 // op: Rt
24714 return 12;
24715 case 1:
24716 // op: Rt2
24717 return 0;
24718 case 2:
24719 // op: addr
24720 return 16;
24721 }
24722 break;
24723 }
24724 case ARM::LDRBi12:
24725 case ARM::LDRcp:
24726 case ARM::LDRi12:
24727 case ARM::STRBi12:
24728 case ARM::STRi12: {
24729 switch (OpNum) {
24730 case 3:
24731 // op: p
24732 return 28;
24733 case 0:
24734 // op: Rt
24735 return 12;
24736 case 1:
24737 // op: addr
24738 return 0;
24739 }
24740 break;
24741 }
24742 case ARM::VADDH:
24743 case ARM::VADDS:
24744 case ARM::VDIVH:
24745 case ARM::VDIVS:
24746 case ARM::VMULH:
24747 case ARM::VMULS:
24748 case ARM::VNMULH:
24749 case ARM::VNMULS:
24750 case ARM::VSUBH:
24751 case ARM::VSUBS: {
24752 switch (OpNum) {
24753 case 3:
24754 // op: p
24755 return 28;
24756 case 0:
24757 // op: Sd
24758 return 12;
24759 case 1:
24760 // op: Sn
24761 return 7;
24762 case 2:
24763 // op: Sm
24764 return 0;
24765 }
24766 break;
24767 }
24768 case ARM::VLDRH:
24769 case ARM::VLDRS:
24770 case ARM::VSTRH:
24771 case ARM::VSTRS: {
24772 switch (OpNum) {
24773 case 3:
24774 // op: p
24775 return 28;
24776 case 0:
24777 // op: Sd
24778 return 12;
24779 case 1:
24780 // op: addr
24781 return 0;
24782 }
24783 break;
24784 }
24785 case ARM::BF16_VCVTB:
24786 case ARM::BF16_VCVTT:
24787 case ARM::VCVTBSH:
24788 case ARM::VCVTTSH: {
24789 switch (OpNum) {
24790 case 3:
24791 // op: p
24792 return 28;
24793 case 0:
24794 // op: Sd
24795 return 12;
24796 case 2:
24797 // op: Sm
24798 return 0;
24799 }
24800 break;
24801 }
24802 case ARM::SMUAD:
24803 case ARM::SMUADX:
24804 case ARM::SMULBB:
24805 case ARM::SMULBT:
24806 case ARM::SMULTB:
24807 case ARM::SMULTT:
24808 case ARM::SMULWB:
24809 case ARM::SMULWT:
24810 case ARM::SMUSD:
24811 case ARM::SMUSDX: {
24812 switch (OpNum) {
24813 case 3:
24814 // op: p
24815 return 28;
24816 case 1:
24817 // op: Rn
24818 return 0;
24819 case 2:
24820 // op: Rm
24821 return 8;
24822 case 0:
24823 // op: Rd
24824 return 16;
24825 }
24826 break;
24827 }
24828 case ARM::QADD8:
24829 case ARM::QADD16:
24830 case ARM::QASX:
24831 case ARM::QSAX:
24832 case ARM::QSUB8:
24833 case ARM::QSUB16:
24834 case ARM::SADD8:
24835 case ARM::SADD16:
24836 case ARM::SASX:
24837 case ARM::SHADD8:
24838 case ARM::SHADD16:
24839 case ARM::SHASX:
24840 case ARM::SHSAX:
24841 case ARM::SHSUB8:
24842 case ARM::SHSUB16:
24843 case ARM::SSAX:
24844 case ARM::SSUB8:
24845 case ARM::SSUB16:
24846 case ARM::UADD8:
24847 case ARM::UADD16:
24848 case ARM::UASX:
24849 case ARM::UHADD8:
24850 case ARM::UHADD16:
24851 case ARM::UHASX:
24852 case ARM::UHSAX:
24853 case ARM::UHSUB8:
24854 case ARM::UHSUB16:
24855 case ARM::UQADD8:
24856 case ARM::UQADD16:
24857 case ARM::UQASX:
24858 case ARM::UQSAX:
24859 case ARM::UQSUB8:
24860 case ARM::UQSUB16:
24861 case ARM::USAX:
24862 case ARM::USUB8:
24863 case ARM::USUB16: {
24864 switch (OpNum) {
24865 case 3:
24866 // op: p
24867 return 28;
24868 case 1:
24869 // op: Rn
24870 return 16;
24871 case 0:
24872 // op: Rd
24873 return 12;
24874 case 2:
24875 // op: Rm
24876 return 0;
24877 }
24878 break;
24879 }
24880 case ARM::STLEX:
24881 case ARM::STLEXB:
24882 case ARM::STLEXD:
24883 case ARM::STLEXH:
24884 case ARM::STREX:
24885 case ARM::STREXB:
24886 case ARM::STREXD:
24887 case ARM::STREXH: {
24888 switch (OpNum) {
24889 case 3:
24890 // op: p
24891 return 28;
24892 case 1:
24893 // op: Rt
24894 return 0;
24895 case 2:
24896 // op: addr
24897 return 16;
24898 case 0:
24899 // op: Rd
24900 return 12;
24901 }
24902 break;
24903 }
24904 case ARM::VLDR_FPCXTNS_pre:
24905 case ARM::VLDR_FPCXTS_pre:
24906 case ARM::VLDR_FPSCR_NZCVQC_pre:
24907 case ARM::VLDR_FPSCR_pre:
24908 case ARM::VLDR_P0_off:
24909 case ARM::VLDR_VPR_pre:
24910 case ARM::VSTR_FPCXTNS_pre:
24911 case ARM::VSTR_FPCXTS_pre:
24912 case ARM::VSTR_FPSCR_NZCVQC_pre:
24913 case ARM::VSTR_FPSCR_pre:
24914 case ARM::VSTR_P0_off:
24915 case ARM::VSTR_VPR_pre: {
24916 switch (OpNum) {
24917 case 3:
24918 // op: p
24919 return 28;
24920 case 1:
24921 // op: addr
24922 return 0;
24923 }
24924 break;
24925 }
24926 case ARM::VMOVRRD: {
24927 switch (OpNum) {
24928 case 3:
24929 // op: p
24930 return 28;
24931 case 2:
24932 // op: Dm
24933 return 0;
24934 case 0:
24935 // op: Rt
24936 return 12;
24937 case 1:
24938 // op: Rt2
24939 return 16;
24940 }
24941 break;
24942 }
24943 case ARM::VCVTBDH:
24944 case ARM::VCVTTDH: {
24945 switch (OpNum) {
24946 case 3:
24947 // op: p
24948 return 28;
24949 case 2:
24950 // op: Dm
24951 return 0;
24952 case 0:
24953 // op: Sd
24954 return 12;
24955 }
24956 break;
24957 }
24958 case ARM::QADD:
24959 case ARM::QDADD:
24960 case ARM::QDSUB:
24961 case ARM::QSUB: {
24962 switch (OpNum) {
24963 case 3:
24964 // op: p
24965 return 28;
24966 case 2:
24967 // op: Rn
24968 return 16;
24969 case 0:
24970 // op: Rd
24971 return 12;
24972 case 1:
24973 // op: Rm
24974 return 0;
24975 }
24976 break;
24977 }
24978 case ARM::VLDR_FPCXTNS_post:
24979 case ARM::VLDR_FPCXTS_post:
24980 case ARM::VLDR_FPSCR_NZCVQC_post:
24981 case ARM::VLDR_FPSCR_post:
24982 case ARM::VLDR_VPR_post:
24983 case ARM::VSTR_FPCXTNS_post:
24984 case ARM::VSTR_FPCXTS_post:
24985 case ARM::VSTR_FPSCR_NZCVQC_post:
24986 case ARM::VSTR_FPSCR_post:
24987 case ARM::VSTR_VPR_post: {
24988 switch (OpNum) {
24989 case 3:
24990 // op: p
24991 return 28;
24992 case 2:
24993 // op: addr
24994 return 0;
24995 case 1:
24996 // op: Rn
24997 return 16;
24998 }
24999 break;
25000 }
25001 case ARM::VSHTOD:
25002 case ARM::VSHTOH:
25003 case ARM::VSHTOS:
25004 case ARM::VSLTOD:
25005 case ARM::VSLTOH:
25006 case ARM::VSLTOS:
25007 case ARM::VTOSHD:
25008 case ARM::VTOSHH:
25009 case ARM::VTOSHS:
25010 case ARM::VTOSLD:
25011 case ARM::VTOSLH:
25012 case ARM::VTOSLS:
25013 case ARM::VTOUHD:
25014 case ARM::VTOUHH:
25015 case ARM::VTOUHS:
25016 case ARM::VTOULD:
25017 case ARM::VTOULH:
25018 case ARM::VTOULS:
25019 case ARM::VUHTOD:
25020 case ARM::VUHTOH:
25021 case ARM::VUHTOS:
25022 case ARM::VULTOD:
25023 case ARM::VULTOH:
25024 case ARM::VULTOS: {
25025 switch (OpNum) {
25026 case 3:
25027 // op: p
25028 return 28;
25029 case 2:
25030 // op: fbits
25031 return 0;
25032 case 0:
25033 // op: dst
25034 return 12;
25035 }
25036 break;
25037 }
25038 case ARM::ADCrr:
25039 case ARM::ADDrr:
25040 case ARM::ANDrr:
25041 case ARM::BICrr:
25042 case ARM::EORrr:
25043 case ARM::ORRrr:
25044 case ARM::RSBrr:
25045 case ARM::RSCrr:
25046 case ARM::SBCrr:
25047 case ARM::SUBrr: {
25048 switch (OpNum) {
25049 case 3:
25050 // op: p
25051 return 28;
25052 case 5:
25053 // op: s
25054 return 20;
25055 case 0:
25056 // op: Rd
25057 return 12;
25058 case 1:
25059 // op: Rn
25060 return 16;
25061 case 2:
25062 // op: Rm
25063 return 0;
25064 }
25065 break;
25066 }
25067 case ARM::ADCri:
25068 case ARM::ADDri:
25069 case ARM::ANDri:
25070 case ARM::BICri:
25071 case ARM::EORri:
25072 case ARM::ORRri:
25073 case ARM::RSBri:
25074 case ARM::RSCri:
25075 case ARM::SBCri:
25076 case ARM::SUBri: {
25077 switch (OpNum) {
25078 case 3:
25079 // op: p
25080 return 28;
25081 case 5:
25082 // op: s
25083 return 20;
25084 case 0:
25085 // op: Rd
25086 return 12;
25087 case 1:
25088 // op: Rn
25089 return 16;
25090 case 2:
25091 // op: imm
25092 return 0;
25093 }
25094 break;
25095 }
25096 case ARM::MVNsi: {
25097 switch (OpNum) {
25098 case 3:
25099 // op: p
25100 return 28;
25101 case 5:
25102 // op: s
25103 return 20;
25104 case 0:
25105 // op: Rd
25106 return 12;
25107 case 1:
25108 // op: shift
25109 return 0;
25110 }
25111 break;
25112 }
25113 case ARM::MOVsi: {
25114 switch (OpNum) {
25115 case 3:
25116 // op: p
25117 return 28;
25118 case 5:
25119 // op: s
25120 return 20;
25121 case 0:
25122 // op: Rd
25123 return 12;
25124 case 1:
25125 // op: src
25126 return 0;
25127 }
25128 break;
25129 }
25130 case ARM::MUL: {
25131 switch (OpNum) {
25132 case 3:
25133 // op: p
25134 return 28;
25135 case 5:
25136 // op: s
25137 return 20;
25138 case 0:
25139 // op: Rd
25140 return 16;
25141 case 2:
25142 // op: Rm
25143 return 8;
25144 case 1:
25145 // op: Rn
25146 return 0;
25147 }
25148 break;
25149 }
25150 case ARM::MVE_VADDLVs32acc:
25151 case ARM::MVE_VADDLVu32acc: {
25152 switch (OpNum) {
25153 case 4:
25154 // op: Qm
25155 return 1;
25156 case 0:
25157 // op: RdaLo
25158 return 13;
25159 case 1:
25160 // op: RdaHi
25161 return 20;
25162 }
25163 break;
25164 }
25165 case ARM::VST1LNd8_UPD: {
25166 switch (OpNum) {
25167 case 4:
25168 // op: Vd
25169 return 12;
25170 case 1:
25171 // op: Rn
25172 return 16;
25173 case 3:
25174 // op: Rm
25175 return 0;
25176 case 5:
25177 // op: lane
25178 return 5;
25179 }
25180 break;
25181 }
25182 case ARM::VST3LNd8_UPD: {
25183 switch (OpNum) {
25184 case 4:
25185 // op: Vd
25186 return 12;
25187 case 1:
25188 // op: Rn
25189 return 16;
25190 case 3:
25191 // op: Rm
25192 return 0;
25193 case 7:
25194 // op: lane
25195 return 5;
25196 }
25197 break;
25198 }
25199 case ARM::VST3LNd16_UPD:
25200 case ARM::VST3LNq16_UPD: {
25201 switch (OpNum) {
25202 case 4:
25203 // op: Vd
25204 return 12;
25205 case 1:
25206 // op: Rn
25207 return 16;
25208 case 3:
25209 // op: Rm
25210 return 0;
25211 case 7:
25212 // op: lane
25213 return 6;
25214 }
25215 break;
25216 }
25217 case ARM::VST3LNd32_UPD:
25218 case ARM::VST3LNq32_UPD: {
25219 switch (OpNum) {
25220 case 4:
25221 // op: Vd
25222 return 12;
25223 case 1:
25224 // op: Rn
25225 return 16;
25226 case 3:
25227 // op: Rm
25228 return 0;
25229 case 7:
25230 // op: lane
25231 return 7;
25232 }
25233 break;
25234 }
25235 case ARM::VST1LNd16_UPD: {
25236 switch (OpNum) {
25237 case 4:
25238 // op: Vd
25239 return 12;
25240 case 1:
25241 // op: Rn
25242 return 4;
25243 case 3:
25244 // op: Rm
25245 return 0;
25246 case 5:
25247 // op: lane
25248 return 6;
25249 }
25250 break;
25251 }
25252 case ARM::VST1LNd32_UPD: {
25253 switch (OpNum) {
25254 case 4:
25255 // op: Vd
25256 return 12;
25257 case 1:
25258 // op: Rn
25259 return 4;
25260 case 3:
25261 // op: Rm
25262 return 0;
25263 case 5:
25264 // op: lane
25265 return 7;
25266 }
25267 break;
25268 }
25269 case ARM::VST2LNd8_UPD: {
25270 switch (OpNum) {
25271 case 4:
25272 // op: Vd
25273 return 12;
25274 case 1:
25275 // op: Rn
25276 return 4;
25277 case 3:
25278 // op: Rm
25279 return 0;
25280 case 6:
25281 // op: lane
25282 return 5;
25283 }
25284 break;
25285 }
25286 case ARM::VST2LNd16_UPD:
25287 case ARM::VST2LNq16_UPD: {
25288 switch (OpNum) {
25289 case 4:
25290 // op: Vd
25291 return 12;
25292 case 1:
25293 // op: Rn
25294 return 4;
25295 case 3:
25296 // op: Rm
25297 return 0;
25298 case 6:
25299 // op: lane
25300 return 6;
25301 }
25302 break;
25303 }
25304 case ARM::VST2LNd32_UPD:
25305 case ARM::VST2LNq32_UPD: {
25306 switch (OpNum) {
25307 case 4:
25308 // op: Vd
25309 return 12;
25310 case 1:
25311 // op: Rn
25312 return 4;
25313 case 3:
25314 // op: Rm
25315 return 0;
25316 case 6:
25317 // op: lane
25318 return 7;
25319 }
25320 break;
25321 }
25322 case ARM::VST4LNd8_UPD: {
25323 switch (OpNum) {
25324 case 4:
25325 // op: Vd
25326 return 12;
25327 case 1:
25328 // op: Rn
25329 return 4;
25330 case 3:
25331 // op: Rm
25332 return 0;
25333 case 8:
25334 // op: lane
25335 return 5;
25336 }
25337 break;
25338 }
25339 case ARM::VST4LNd16_UPD:
25340 case ARM::VST4LNq16_UPD: {
25341 switch (OpNum) {
25342 case 4:
25343 // op: Vd
25344 return 12;
25345 case 1:
25346 // op: Rn
25347 return 4;
25348 case 3:
25349 // op: Rm
25350 return 0;
25351 case 8:
25352 // op: lane
25353 return 6;
25354 }
25355 break;
25356 }
25357 case ARM::VST4LNd32_UPD:
25358 case ARM::VST4LNq32_UPD: {
25359 switch (OpNum) {
25360 case 4:
25361 // op: Vd
25362 return 12;
25363 case 1:
25364 // op: Rn
25365 return 4;
25366 case 3:
25367 // op: Rm
25368 return 0;
25369 case 8:
25370 // op: lane
25371 return 7;
25372 }
25373 break;
25374 }
25375 case ARM::VST1d8Qwb_register:
25376 case ARM::VST1d8Twb_register:
25377 case ARM::VST1d8wb_register:
25378 case ARM::VST1d16Qwb_register:
25379 case ARM::VST1d16Twb_register:
25380 case ARM::VST1d16wb_register:
25381 case ARM::VST1d32Qwb_register:
25382 case ARM::VST1d32Twb_register:
25383 case ARM::VST1d32wb_register:
25384 case ARM::VST1d64Qwb_register:
25385 case ARM::VST1d64Twb_register:
25386 case ARM::VST1d64wb_register:
25387 case ARM::VST1q8wb_register:
25388 case ARM::VST1q16wb_register:
25389 case ARM::VST1q32wb_register:
25390 case ARM::VST1q64wb_register:
25391 case ARM::VST2b8wb_register:
25392 case ARM::VST2b16wb_register:
25393 case ARM::VST2b32wb_register:
25394 case ARM::VST2d8wb_register:
25395 case ARM::VST2d16wb_register:
25396 case ARM::VST2d32wb_register:
25397 case ARM::VST2q8wb_register:
25398 case ARM::VST2q16wb_register:
25399 case ARM::VST2q32wb_register:
25400 case ARM::VST3d8_UPD:
25401 case ARM::VST3d16_UPD:
25402 case ARM::VST3d32_UPD:
25403 case ARM::VST3q8_UPD:
25404 case ARM::VST3q16_UPD:
25405 case ARM::VST3q32_UPD:
25406 case ARM::VST4d8_UPD:
25407 case ARM::VST4d16_UPD:
25408 case ARM::VST4d32_UPD:
25409 case ARM::VST4q8_UPD:
25410 case ARM::VST4q16_UPD:
25411 case ARM::VST4q32_UPD: {
25412 switch (OpNum) {
25413 case 4:
25414 // op: Vd
25415 return 12;
25416 case 1:
25417 // op: Rn
25418 return 4;
25419 case 3:
25420 // op: Rm
25421 return 0;
25422 }
25423 break;
25424 }
25425 case ARM::MVE_VSHLC: {
25426 switch (OpNum) {
25427 case 4:
25428 // op: imm
25429 return 16;
25430 case 1:
25431 // op: Qd
25432 return 13;
25433 case 0:
25434 // op: RdmDest
25435 return 0;
25436 }
25437 break;
25438 }
25439 case ARM::VFMAD:
25440 case ARM::VFMSD:
25441 case ARM::VFNMAD:
25442 case ARM::VFNMSD:
25443 case ARM::VMLAD:
25444 case ARM::VMLSD:
25445 case ARM::VNMLAD:
25446 case ARM::VNMLSD: {
25447 switch (OpNum) {
25448 case 4:
25449 // op: p
25450 return 28;
25451 case 0:
25452 // op: Dd
25453 return 12;
25454 case 2:
25455 // op: Dn
25456 return 7;
25457 case 3:
25458 // op: Dm
25459 return 0;
25460 }
25461 break;
25462 }
25463 case ARM::SBFX:
25464 case ARM::UBFX: {
25465 switch (OpNum) {
25466 case 4:
25467 // op: p
25468 return 28;
25469 case 0:
25470 // op: Rd
25471 return 12;
25472 case 1:
25473 // op: Rn
25474 return 0;
25475 case 2:
25476 // op: lsb
25477 return 7;
25478 case 3:
25479 // op: width
25480 return 16;
25481 }
25482 break;
25483 }
25484 case ARM::PKHBT:
25485 case ARM::PKHTB: {
25486 switch (OpNum) {
25487 case 4:
25488 // op: p
25489 return 28;
25490 case 0:
25491 // op: Rd
25492 return 12;
25493 case 1:
25494 // op: Rn
25495 return 16;
25496 case 2:
25497 // op: Rm
25498 return 0;
25499 case 3:
25500 // op: sh
25501 return 7;
25502 }
25503 break;
25504 }
25505 case ARM::SSAT:
25506 case ARM::USAT: {
25507 switch (OpNum) {
25508 case 4:
25509 // op: p
25510 return 28;
25511 case 0:
25512 // op: Rd
25513 return 12;
25514 case 1:
25515 // op: sat_imm
25516 return 16;
25517 case 2:
25518 // op: Rn
25519 return 0;
25520 case 3:
25521 // op: sh
25522 return 6;
25523 }
25524 break;
25525 }
25526 case ARM::SXTAB:
25527 case ARM::SXTAB16:
25528 case ARM::SXTAH:
25529 case ARM::UXTAB:
25530 case ARM::UXTAB16:
25531 case ARM::UXTAH: {
25532 switch (OpNum) {
25533 case 4:
25534 // op: p
25535 return 28;
25536 case 0:
25537 // op: Rd
25538 return 12;
25539 case 2:
25540 // op: Rm
25541 return 0;
25542 case 1:
25543 // op: Rn
25544 return 16;
25545 case 3:
25546 // op: rot
25547 return 10;
25548 }
25549 break;
25550 }
25551 case ARM::BFI: {
25552 switch (OpNum) {
25553 case 4:
25554 // op: p
25555 return 28;
25556 case 0:
25557 // op: Rd
25558 return 12;
25559 case 2:
25560 // op: Rn
25561 return 0;
25562 case 3:
25563 // op: imm
25564 return 7;
25565 }
25566 break;
25567 }
25568 case ARM::SMMLA:
25569 case ARM::SMMLAR:
25570 case ARM::SMMLS:
25571 case ARM::SMMLSR:
25572 case ARM::USADA8: {
25573 switch (OpNum) {
25574 case 4:
25575 // op: p
25576 return 28;
25577 case 0:
25578 // op: Rd
25579 return 16;
25580 case 1:
25581 // op: Rn
25582 return 0;
25583 case 2:
25584 // op: Rm
25585 return 8;
25586 case 3:
25587 // op: Ra
25588 return 12;
25589 }
25590 break;
25591 }
25592 case ARM::MLS: {
25593 switch (OpNum) {
25594 case 4:
25595 // op: p
25596 return 28;
25597 case 0:
25598 // op: Rd
25599 return 16;
25600 case 2:
25601 // op: Rm
25602 return 8;
25603 case 1:
25604 // op: Rn
25605 return 0;
25606 case 3:
25607 // op: Ra
25608 return 12;
25609 }
25610 break;
25611 }
25612 case ARM::CMNzrsr:
25613 case ARM::CMPrsr:
25614 case ARM::TEQrsr:
25615 case ARM::TSTrsr: {
25616 switch (OpNum) {
25617 case 4:
25618 // op: p
25619 return 28;
25620 case 0:
25621 // op: Rn
25622 return 16;
25623 case 1:
25624 // op: shift
25625 return 0;
25626 }
25627 break;
25628 }
25629 case ARM::LDRBrs:
25630 case ARM::LDRrs:
25631 case ARM::STRBrs:
25632 case ARM::STRrs: {
25633 switch (OpNum) {
25634 case 4:
25635 // op: p
25636 return 28;
25637 case 0:
25638 // op: Rt
25639 return 12;
25640 case 1:
25641 // op: shift
25642 return 0;
25643 }
25644 break;
25645 }
25646 case ARM::LDRB_PRE_IMM:
25647 case ARM::LDR_PRE_IMM: {
25648 switch (OpNum) {
25649 case 4:
25650 // op: p
25651 return 28;
25652 case 0:
25653 // op: Rt
25654 return 12;
25655 case 2:
25656 // op: addr
25657 return 0;
25658 }
25659 break;
25660 }
25661 case ARM::VFMAH:
25662 case ARM::VFMAS:
25663 case ARM::VFMSH:
25664 case ARM::VFMSS:
25665 case ARM::VFNMAH:
25666 case ARM::VFNMAS:
25667 case ARM::VFNMSH:
25668 case ARM::VFNMSS:
25669 case ARM::VMLAH:
25670 case ARM::VMLAS:
25671 case ARM::VMLSH:
25672 case ARM::VMLSS:
25673 case ARM::VNMLAH:
25674 case ARM::VNMLAS:
25675 case ARM::VNMLSH:
25676 case ARM::VNMLSS: {
25677 switch (OpNum) {
25678 case 4:
25679 // op: p
25680 return 28;
25681 case 0:
25682 // op: Sd
25683 return 12;
25684 case 2:
25685 // op: Sn
25686 return 7;
25687 case 3:
25688 // op: Sm
25689 return 0;
25690 }
25691 break;
25692 }
25693 case ARM::VMOVSRR: {
25694 switch (OpNum) {
25695 case 4:
25696 // op: p
25697 return 28;
25698 case 0:
25699 // op: dst1
25700 return 0;
25701 case 2:
25702 // op: src1
25703 return 12;
25704 case 3:
25705 // op: src2
25706 return 16;
25707 }
25708 break;
25709 }
25710 case ARM::SMLABB:
25711 case ARM::SMLABT:
25712 case ARM::SMLATB:
25713 case ARM::SMLATT:
25714 case ARM::SMLAWB:
25715 case ARM::SMLAWT: {
25716 switch (OpNum) {
25717 case 4:
25718 // op: p
25719 return 28;
25720 case 1:
25721 // op: Rn
25722 return 0;
25723 case 2:
25724 // op: Rm
25725 return 8;
25726 case 0:
25727 // op: Rd
25728 return 16;
25729 case 3:
25730 // op: Ra
25731 return 12;
25732 }
25733 break;
25734 }
25735 case ARM::SMLAD:
25736 case ARM::SMLADX:
25737 case ARM::SMLSD:
25738 case ARM::SMLSDX: {
25739 switch (OpNum) {
25740 case 4:
25741 // op: p
25742 return 28;
25743 case 1:
25744 // op: Rn
25745 return 0;
25746 case 2:
25747 // op: Rm
25748 return 8;
25749 case 3:
25750 // op: Ra
25751 return 12;
25752 case 0:
25753 // op: Rd
25754 return 16;
25755 }
25756 break;
25757 }
25758 case ARM::STRB_PRE_IMM:
25759 case ARM::STR_PRE_IMM: {
25760 switch (OpNum) {
25761 case 4:
25762 // op: p
25763 return 28;
25764 case 1:
25765 // op: Rt
25766 return 12;
25767 case 2:
25768 // op: addr
25769 return 0;
25770 }
25771 break;
25772 }
25773 case ARM::LDRH:
25774 case ARM::LDRSB:
25775 case ARM::LDRSH:
25776 case ARM::STRH: {
25777 switch (OpNum) {
25778 case 4:
25779 // op: p
25780 return 28;
25781 case 1:
25782 // op: addr
25783 return 0;
25784 case 0:
25785 // op: Rt
25786 return 12;
25787 }
25788 break;
25789 }
25790 case ARM::LDCL_OFFSET:
25791 case ARM::LDCL_PRE:
25792 case ARM::LDC_OFFSET:
25793 case ARM::LDC_PRE:
25794 case ARM::STCL_OFFSET:
25795 case ARM::STCL_PRE:
25796 case ARM::STC_OFFSET:
25797 case ARM::STC_PRE: {
25798 switch (OpNum) {
25799 case 4:
25800 // op: p
25801 return 28;
25802 case 2:
25803 // op: addr
25804 return 0;
25805 case 0:
25806 // op: cop
25807 return 8;
25808 case 1:
25809 // op: CRd
25810 return 12;
25811 }
25812 break;
25813 }
25814 case ARM::VLDR_P0_pre:
25815 case ARM::VSTR_P0_pre: {
25816 switch (OpNum) {
25817 case 4:
25818 // op: p
25819 return 28;
25820 case 2:
25821 // op: addr
25822 return 0;
25823 }
25824 break;
25825 }
25826 case ARM::LDRHTi:
25827 case ARM::LDRSBTi:
25828 case ARM::LDRSHTi: {
25829 switch (OpNum) {
25830 case 4:
25831 // op: p
25832 return 28;
25833 case 2:
25834 // op: addr
25835 return 16;
25836 case 0:
25837 // op: Rt
25838 return 12;
25839 case 3:
25840 // op: offset
25841 return 0;
25842 }
25843 break;
25844 }
25845 case ARM::STRHTi: {
25846 switch (OpNum) {
25847 case 4:
25848 // op: p
25849 return 28;
25850 case 2:
25851 // op: addr
25852 return 16;
25853 case 1:
25854 // op: Rt
25855 return 12;
25856 case 3:
25857 // op: offset
25858 return 0;
25859 }
25860 break;
25861 }
25862 case ARM::VMOVRRS: {
25863 switch (OpNum) {
25864 case 4:
25865 // op: p
25866 return 28;
25867 case 2:
25868 // op: src1
25869 return 0;
25870 case 0:
25871 // op: Rt
25872 return 12;
25873 case 1:
25874 // op: Rt2
25875 return 16;
25876 }
25877 break;
25878 }
25879 case ARM::VLDR_P0_post:
25880 case ARM::VSTR_P0_post: {
25881 switch (OpNum) {
25882 case 4:
25883 // op: p
25884 return 28;
25885 case 3:
25886 // op: addr
25887 return 0;
25888 case 2:
25889 // op: Rn
25890 return 16;
25891 }
25892 break;
25893 }
25894 case ARM::LDCL_POST:
25895 case ARM::LDC_POST:
25896 case ARM::STCL_POST:
25897 case ARM::STC_POST: {
25898 switch (OpNum) {
25899 case 4:
25900 // op: p
25901 return 28;
25902 case 3:
25903 // op: offset
25904 return 0;
25905 case 2:
25906 // op: addr
25907 return 16;
25908 case 0:
25909 // op: cop
25910 return 8;
25911 case 1:
25912 // op: CRd
25913 return 12;
25914 }
25915 break;
25916 }
25917 case ARM::LDCL_OPTION:
25918 case ARM::LDC_OPTION:
25919 case ARM::STCL_OPTION:
25920 case ARM::STC_OPTION: {
25921 switch (OpNum) {
25922 case 4:
25923 // op: p
25924 return 28;
25925 case 3:
25926 // op: option
25927 return 0;
25928 case 2:
25929 // op: addr
25930 return 16;
25931 case 0:
25932 // op: cop
25933 return 8;
25934 case 1:
25935 // op: CRd
25936 return 12;
25937 }
25938 break;
25939 }
25940 case ARM::ADCrsi:
25941 case ARM::ADDrsi:
25942 case ARM::ANDrsi:
25943 case ARM::BICrsi:
25944 case ARM::EORrsi:
25945 case ARM::ORRrsi:
25946 case ARM::RSBrsi:
25947 case ARM::RSCrsi:
25948 case ARM::SBCrsi:
25949 case ARM::SUBrsi: {
25950 switch (OpNum) {
25951 case 4:
25952 // op: p
25953 return 28;
25954 case 6:
25955 // op: s
25956 return 20;
25957 case 0:
25958 // op: Rd
25959 return 12;
25960 case 1:
25961 // op: Rn
25962 return 16;
25963 case 2:
25964 // op: shift
25965 return 0;
25966 }
25967 break;
25968 }
25969 case ARM::MVNsr: {
25970 switch (OpNum) {
25971 case 4:
25972 // op: p
25973 return 28;
25974 case 6:
25975 // op: s
25976 return 20;
25977 case 0:
25978 // op: Rd
25979 return 12;
25980 case 1:
25981 // op: shift
25982 return 0;
25983 }
25984 break;
25985 }
25986 case ARM::MOVsr: {
25987 switch (OpNum) {
25988 case 4:
25989 // op: p
25990 return 28;
25991 case 6:
25992 // op: s
25993 return 20;
25994 case 0:
25995 // op: Rd
25996 return 12;
25997 case 1:
25998 // op: src
25999 return 0;
26000 }
26001 break;
26002 }
26003 case ARM::MLA: {
26004 switch (OpNum) {
26005 case 4:
26006 // op: p
26007 return 28;
26008 case 6:
26009 // op: s
26010 return 20;
26011 case 0:
26012 // op: Rd
26013 return 16;
26014 case 2:
26015 // op: Rm
26016 return 8;
26017 case 1:
26018 // op: Rn
26019 return 0;
26020 case 3:
26021 // op: Ra
26022 return 12;
26023 }
26024 break;
26025 }
26026 case ARM::SMULL:
26027 case ARM::UMULL: {
26028 switch (OpNum) {
26029 case 4:
26030 // op: p
26031 return 28;
26032 case 6:
26033 // op: s
26034 return 20;
26035 case 0:
26036 // op: RdLo
26037 return 12;
26038 case 1:
26039 // op: RdHi
26040 return 16;
26041 case 3:
26042 // op: Rm
26043 return 8;
26044 case 2:
26045 // op: Rn
26046 return 0;
26047 }
26048 break;
26049 }
26050 case ARM::t2MOVr:
26051 case ARM::t2MVNr:
26052 case ARM::t2RRX: {
26053 switch (OpNum) {
26054 case 4:
26055 // op: s
26056 return 20;
26057 case 0:
26058 // op: Rd
26059 return 8;
26060 case 1:
26061 // op: Rm
26062 return 0;
26063 }
26064 break;
26065 }
26066 case ARM::t2MOVi:
26067 case ARM::t2MVNi: {
26068 switch (OpNum) {
26069 case 4:
26070 // op: s
26071 return 20;
26072 case 0:
26073 // op: Rd
26074 return 8;
26075 case 1:
26076 // op: imm
26077 return 0;
26078 }
26079 break;
26080 }
26081 case ARM::MRRC: {
26082 switch (OpNum) {
26083 case 5:
26084 // op: p
26085 return 28;
26086 case 0:
26087 // op: Rt
26088 return 12;
26089 case 1:
26090 // op: Rt2
26091 return 16;
26092 case 2:
26093 // op: cop
26094 return 8;
26095 case 3:
26096 // op: opc1
26097 return 4;
26098 case 4:
26099 // op: CRm
26100 return 0;
26101 }
26102 break;
26103 }
26104 case ARM::LDRB_PRE_REG:
26105 case ARM::LDRH_PRE:
26106 case ARM::LDRSB_PRE:
26107 case ARM::LDRSH_PRE:
26108 case ARM::LDR_PRE_REG: {
26109 switch (OpNum) {
26110 case 5:
26111 // op: p
26112 return 28;
26113 case 0:
26114 // op: Rt
26115 return 12;
26116 case 2:
26117 // op: addr
26118 return 0;
26119 }
26120 break;
26121 }
26122 case ARM::LDRBT_POST_IMM:
26123 case ARM::LDRBT_POST_REG:
26124 case ARM::LDRB_POST_IMM:
26125 case ARM::LDRB_POST_REG:
26126 case ARM::LDRH_POST:
26127 case ARM::LDRSB_POST:
26128 case ARM::LDRSH_POST:
26129 case ARM::LDRT_POST_IMM:
26130 case ARM::LDRT_POST_REG:
26131 case ARM::LDR_POST_IMM:
26132 case ARM::LDR_POST_REG: {
26133 switch (OpNum) {
26134 case 5:
26135 // op: p
26136 return 28;
26137 case 0:
26138 // op: Rt
26139 return 12;
26140 case 3:
26141 // op: offset
26142 return 0;
26143 case 2:
26144 // op: addr
26145 return 16;
26146 }
26147 break;
26148 }
26149 case ARM::STRB_PRE_REG:
26150 case ARM::STRH_PRE:
26151 case ARM::STR_PRE_REG: {
26152 switch (OpNum) {
26153 case 5:
26154 // op: p
26155 return 28;
26156 case 1:
26157 // op: Rt
26158 return 12;
26159 case 2:
26160 // op: addr
26161 return 0;
26162 }
26163 break;
26164 }
26165 case ARM::STRBT_POST_IMM:
26166 case ARM::STRBT_POST_REG:
26167 case ARM::STRB_POST_IMM:
26168 case ARM::STRB_POST_REG:
26169 case ARM::STRH_POST:
26170 case ARM::STRT_POST_IMM:
26171 case ARM::STRT_POST_REG:
26172 case ARM::STR_POST_IMM:
26173 case ARM::STR_POST_REG: {
26174 switch (OpNum) {
26175 case 5:
26176 // op: p
26177 return 28;
26178 case 1:
26179 // op: Rt
26180 return 12;
26181 case 3:
26182 // op: offset
26183 return 0;
26184 case 2:
26185 // op: addr
26186 return 16;
26187 }
26188 break;
26189 }
26190 case ARM::MCRR: {
26191 switch (OpNum) {
26192 case 5:
26193 // op: p
26194 return 28;
26195 case 2:
26196 // op: Rt
26197 return 12;
26198 case 3:
26199 // op: Rt2
26200 return 16;
26201 case 0:
26202 // op: cop
26203 return 8;
26204 case 1:
26205 // op: opc1
26206 return 4;
26207 case 4:
26208 // op: CRm
26209 return 0;
26210 }
26211 break;
26212 }
26213 case ARM::LDRD:
26214 case ARM::STRD: {
26215 switch (OpNum) {
26216 case 5:
26217 // op: p
26218 return 28;
26219 case 2:
26220 // op: addr
26221 return 0;
26222 case 0:
26223 // op: Rt
26224 return 12;
26225 }
26226 break;
26227 }
26228 case ARM::LDRHTr:
26229 case ARM::LDRSBTr:
26230 case ARM::LDRSHTr: {
26231 switch (OpNum) {
26232 case 5:
26233 // op: p
26234 return 28;
26235 case 2:
26236 // op: addr
26237 return 16;
26238 case 0:
26239 // op: Rt
26240 return 12;
26241 case 3:
26242 // op: Rm
26243 return 0;
26244 }
26245 break;
26246 }
26247 case ARM::STRHTr: {
26248 switch (OpNum) {
26249 case 5:
26250 // op: p
26251 return 28;
26252 case 2:
26253 // op: addr
26254 return 16;
26255 case 1:
26256 // op: Rt
26257 return 12;
26258 case 3:
26259 // op: Rm
26260 return 0;
26261 }
26262 break;
26263 }
26264 case ARM::ADCrsr:
26265 case ARM::ADDrsr:
26266 case ARM::ANDrsr:
26267 case ARM::BICrsr:
26268 case ARM::EORrsr:
26269 case ARM::ORRrsr:
26270 case ARM::RSBrsr:
26271 case ARM::RSCrsr:
26272 case ARM::SBCrsr:
26273 case ARM::SUBrsr: {
26274 switch (OpNum) {
26275 case 5:
26276 // op: p
26277 return 28;
26278 case 7:
26279 // op: s
26280 return 20;
26281 case 0:
26282 // op: Rd
26283 return 12;
26284 case 1:
26285 // op: Rn
26286 return 16;
26287 case 2:
26288 // op: shift
26289 return 0;
26290 }
26291 break;
26292 }
26293 case ARM::t2ASRri:
26294 case ARM::t2LSLri:
26295 case ARM::t2LSRri:
26296 case ARM::t2RORri: {
26297 switch (OpNum) {
26298 case 5:
26299 // op: s
26300 return 20;
26301 case 0:
26302 // op: Rd
26303 return 8;
26304 case 1:
26305 // op: Rm
26306 return 0;
26307 case 2:
26308 // op: imm
26309 return 6;
26310 }
26311 break;
26312 }
26313 case ARM::t2ADCrr:
26314 case ARM::t2ADDrr:
26315 case ARM::t2ANDrr:
26316 case ARM::t2ASRrr:
26317 case ARM::t2BICrr:
26318 case ARM::t2EORrr:
26319 case ARM::t2LSLrr:
26320 case ARM::t2LSRrr:
26321 case ARM::t2ORNrr:
26322 case ARM::t2ORRrr:
26323 case ARM::t2RORrr:
26324 case ARM::t2RSBrr:
26325 case ARM::t2SBCrr:
26326 case ARM::t2SUBrr: {
26327 switch (OpNum) {
26328 case 5:
26329 // op: s
26330 return 20;
26331 case 0:
26332 // op: Rd
26333 return 8;
26334 case 1:
26335 // op: Rn
26336 return 16;
26337 case 2:
26338 // op: Rm
26339 return 0;
26340 }
26341 break;
26342 }
26343 case ARM::t2ADCri:
26344 case ARM::t2ADDri:
26345 case ARM::t2ANDri:
26346 case ARM::t2BICri:
26347 case ARM::t2EORri:
26348 case ARM::t2ORNri:
26349 case ARM::t2ORRri:
26350 case ARM::t2RSBri:
26351 case ARM::t2SBCri:
26352 case ARM::t2SUBri: {
26353 switch (OpNum) {
26354 case 5:
26355 // op: s
26356 return 20;
26357 case 0:
26358 // op: Rd
26359 return 8;
26360 case 1:
26361 // op: Rn
26362 return 16;
26363 case 2:
26364 // op: imm
26365 return 0;
26366 }
26367 break;
26368 }
26369 case ARM::t2MVNs: {
26370 switch (OpNum) {
26371 case 5:
26372 // op: s
26373 return 20;
26374 case 0:
26375 // op: Rd
26376 return 8;
26377 case 1:
26378 // op: ShiftedRm
26379 return 0;
26380 }
26381 break;
26382 }
26383 case ARM::t2ADDspImm:
26384 case ARM::t2SUBspImm: {
26385 switch (OpNum) {
26386 case 5:
26387 // op: s
26388 return 20;
26389 case 2:
26390 // op: imm
26391 return 0;
26392 }
26393 break;
26394 }
26395 case ARM::UMAAL: {
26396 switch (OpNum) {
26397 case 6:
26398 // op: p
26399 return 28;
26400 case 0:
26401 // op: RdLo
26402 return 12;
26403 case 1:
26404 // op: RdHi
26405 return 16;
26406 case 3:
26407 // op: Rm
26408 return 8;
26409 case 2:
26410 // op: Rn
26411 return 0;
26412 }
26413 break;
26414 }
26415 case ARM::MRC: {
26416 switch (OpNum) {
26417 case 6:
26418 // op: p
26419 return 28;
26420 case 0:
26421 // op: Rt
26422 return 12;
26423 case 1:
26424 // op: cop
26425 return 8;
26426 case 2:
26427 // op: opc1
26428 return 21;
26429 case 5:
26430 // op: opc2
26431 return 5;
26432 case 4:
26433 // op: CRm
26434 return 0;
26435 case 3:
26436 // op: CRn
26437 return 16;
26438 }
26439 break;
26440 }
26441 case ARM::LDRD_PRE: {
26442 switch (OpNum) {
26443 case 6:
26444 // op: p
26445 return 28;
26446 case 0:
26447 // op: Rt
26448 return 12;
26449 case 3:
26450 // op: addr
26451 return 0;
26452 }
26453 break;
26454 }
26455 case ARM::LDRD_POST: {
26456 switch (OpNum) {
26457 case 6:
26458 // op: p
26459 return 28;
26460 case 0:
26461 // op: Rt
26462 return 12;
26463 case 4:
26464 // op: offset
26465 return 0;
26466 case 3:
26467 // op: addr
26468 return 16;
26469 }
26470 break;
26471 }
26472 case ARM::STRD_PRE: {
26473 switch (OpNum) {
26474 case 6:
26475 // op: p
26476 return 28;
26477 case 1:
26478 // op: Rt
26479 return 12;
26480 case 3:
26481 // op: addr
26482 return 0;
26483 }
26484 break;
26485 }
26486 case ARM::STRD_POST: {
26487 switch (OpNum) {
26488 case 6:
26489 // op: p
26490 return 28;
26491 case 1:
26492 // op: Rt
26493 return 12;
26494 case 4:
26495 // op: offset
26496 return 0;
26497 case 3:
26498 // op: addr
26499 return 16;
26500 }
26501 break;
26502 }
26503 case ARM::CDP: {
26504 switch (OpNum) {
26505 case 6:
26506 // op: p
26507 return 28;
26508 case 1:
26509 // op: opc1
26510 return 20;
26511 case 3:
26512 // op: CRn
26513 return 16;
26514 case 2:
26515 // op: CRd
26516 return 12;
26517 case 0:
26518 // op: cop
26519 return 8;
26520 case 5:
26521 // op: opc2
26522 return 5;
26523 case 4:
26524 // op: CRm
26525 return 0;
26526 }
26527 break;
26528 }
26529 case ARM::SMLALBB:
26530 case ARM::SMLALBT:
26531 case ARM::SMLALD:
26532 case ARM::SMLALDX:
26533 case ARM::SMLALTB:
26534 case ARM::SMLALTT:
26535 case ARM::SMLSLD:
26536 case ARM::SMLSLDX: {
26537 switch (OpNum) {
26538 case 6:
26539 // op: p
26540 return 28;
26541 case 2:
26542 // op: Rn
26543 return 0;
26544 case 3:
26545 // op: Rm
26546 return 8;
26547 case 0:
26548 // op: RdLo
26549 return 12;
26550 case 1:
26551 // op: RdHi
26552 return 16;
26553 }
26554 break;
26555 }
26556 case ARM::MCR: {
26557 switch (OpNum) {
26558 case 6:
26559 // op: p
26560 return 28;
26561 case 2:
26562 // op: Rt
26563 return 12;
26564 case 0:
26565 // op: cop
26566 return 8;
26567 case 1:
26568 // op: opc1
26569 return 21;
26570 case 5:
26571 // op: opc2
26572 return 5;
26573 case 4:
26574 // op: CRm
26575 return 0;
26576 case 3:
26577 // op: CRn
26578 return 16;
26579 }
26580 break;
26581 }
26582 case ARM::SMLAL:
26583 case ARM::UMLAL: {
26584 switch (OpNum) {
26585 case 6:
26586 // op: p
26587 return 28;
26588 case 8:
26589 // op: s
26590 return 20;
26591 case 0:
26592 // op: RdLo
26593 return 12;
26594 case 1:
26595 // op: RdHi
26596 return 16;
26597 case 3:
26598 // op: Rm
26599 return 8;
26600 case 2:
26601 // op: Rn
26602 return 0;
26603 }
26604 break;
26605 }
26606 case ARM::t2ADCrs:
26607 case ARM::t2ADDrs:
26608 case ARM::t2ANDrs:
26609 case ARM::t2BICrs:
26610 case ARM::t2EORrs:
26611 case ARM::t2ORNrs:
26612 case ARM::t2ORRrs:
26613 case ARM::t2RSBrs:
26614 case ARM::t2SBCrs:
26615 case ARM::t2SUBrs: {
26616 switch (OpNum) {
26617 case 6:
26618 // op: s
26619 return 20;
26620 case 0:
26621 // op: Rd
26622 return 8;
26623 case 1:
26624 // op: Rn
26625 return 16;
26626 case 2:
26627 // op: ShiftedRm
26628 return 0;
26629 }
26630 break;
26631 }
26632 }
26633 std::string msg;
26634 raw_string_ostream Msg(msg);
26635 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
26636 report_fatal_error(Msg.str().c_str());
26637}
26638
26639#endif // GET_OPERAND_BIT_OFFSET
26640
26641