1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t AVRMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(7168), // ADCRdRr
404 UINT64_C(3072), // ADDRdRr
405 UINT64_C(38400), // ADIWRdK
406 UINT64_C(28672), // ANDIRdK
407 UINT64_C(8192), // ANDRdRr
408 UINT64_C(37893), // ASRRd
409 UINT64_C(38024), // BCLRs
410 UINT64_C(63488), // BLD
411 UINT64_C(62464), // BRBCsk
412 UINT64_C(61440), // BRBSsk
413 UINT64_C(38296), // BREAK
414 UINT64_C(61441), // BREQk
415 UINT64_C(62468), // BRGEk
416 UINT64_C(61440), // BRLOk
417 UINT64_C(61444), // BRLTk
418 UINT64_C(61442), // BRMIk
419 UINT64_C(62465), // BRNEk
420 UINT64_C(62466), // BRPLk
421 UINT64_C(62464), // BRSHk
422 UINT64_C(37896), // BSETs
423 UINT64_C(64000), // BST
424 UINT64_C(2483945472), // CALLk
425 UINT64_C(38912), // CBIAb
426 UINT64_C(37888), // COMRd
427 UINT64_C(1024), // CPCRdRr
428 UINT64_C(12288), // CPIRdK
429 UINT64_C(5120), // CPRdRr
430 UINT64_C(4096), // CPSE
431 UINT64_C(37898), // DECRd
432 UINT64_C(37899), // DESK
433 UINT64_C(38169), // EICALL
434 UINT64_C(37913), // EIJMP
435 UINT64_C(38360), // ELPM
436 UINT64_C(36870), // ELPMRdZ
437 UINT64_C(36871), // ELPMRdZPi
438 UINT64_C(9216), // EORRdRr
439 UINT64_C(776), // FMUL
440 UINT64_C(896), // FMULS
441 UINT64_C(904), // FMULSU
442 UINT64_C(38153), // ICALL
443 UINT64_C(37897), // IJMP
444 UINT64_C(37891), // INCRd
445 UINT64_C(45056), // INRdA
446 UINT64_C(2483814400), // JMPk
447 UINT64_C(37382), // LACZRd
448 UINT64_C(37381), // LASZRd
449 UINT64_C(37383), // LATZRd
450 UINT64_C(32768), // LDDRdPtrQ
451 UINT64_C(57344), // LDIRdK
452 UINT64_C(32768), // LDRdPtr
453 UINT64_C(32770), // LDRdPtrPd
454 UINT64_C(32769), // LDRdPtrPi
455 UINT64_C(2415919104), // LDSRdK
456 UINT64_C(40960), // LDSRdKTiny
457 UINT64_C(38344), // LPM
458 UINT64_C(36868), // LPMRdZ
459 UINT64_C(36869), // LPMRdZPi
460 UINT64_C(37894), // LSRRd
461 UINT64_C(11264), // MOVRdRr
462 UINT64_C(256), // MOVWRdRr
463 UINT64_C(39936), // MULRdRr
464 UINT64_C(512), // MULSRdRr
465 UINT64_C(768), // MULSURdRr
466 UINT64_C(37889), // NEGRd
467 UINT64_C(0), // NOP
468 UINT64_C(24576), // ORIRdK
469 UINT64_C(10240), // ORRdRr
470 UINT64_C(47104), // OUTARr
471 UINT64_C(36879), // POPRd
472 UINT64_C(37391), // PUSHRr
473 UINT64_C(53248), // RCALLk
474 UINT64_C(38152), // RET
475 UINT64_C(38168), // RETI
476 UINT64_C(49152), // RJMPk
477 UINT64_C(37895), // RORRd
478 UINT64_C(16384), // SBCIRdK
479 UINT64_C(2048), // SBCRdRr
480 UINT64_C(39424), // SBIAb
481 UINT64_C(39168), // SBICAb
482 UINT64_C(39680), // SBISAb
483 UINT64_C(38656), // SBIWRdK
484 UINT64_C(64512), // SBRCRrB
485 UINT64_C(65024), // SBRSRrB
486 UINT64_C(38280), // SLEEP
487 UINT64_C(38376), // SPM
488 UINT64_C(38392), // SPMZPi
489 UINT64_C(33280), // STDPtrQRr
490 UINT64_C(33282), // STPtrPdRr
491 UINT64_C(33281), // STPtrPiRr
492 UINT64_C(33280), // STPtrRr
493 UINT64_C(2449473536), // STSKRr
494 UINT64_C(43008), // STSKRrTiny
495 UINT64_C(20480), // SUBIRdK
496 UINT64_C(6144), // SUBRdRr
497 UINT64_C(37890), // SWAPRd
498 UINT64_C(38312), // WDR
499 UINT64_C(37380), // XCHZRd
500 UINT64_C(0)
501 };
502 const unsigned opcode = MI.getOpcode();
503 uint64_t Value = InstBits[opcode];
504 uint64_t op = 0;
505 (void)op; // suppress warning
506 switch (opcode) {
507 case AVR::BREAK:
508 case AVR::EICALL:
509 case AVR::EIJMP:
510 case AVR::ELPM:
511 case AVR::ICALL:
512 case AVR::IJMP:
513 case AVR::LPM:
514 case AVR::NOP:
515 case AVR::RET:
516 case AVR::RETI:
517 case AVR::SLEEP:
518 case AVR::SPM:
519 case AVR::SPMZPi:
520 case AVR::WDR: {
521 break;
522 }
523 case AVR::OUTARr: {
524 // op: A
525 op = encodeImm<AVR::fixup_port6, 0>(MI, OpNo: 0, Fixups, STI);
526 Value |= (op & UINT64_C(48)) << 5;
527 Value |= (op & UINT64_C(15));
528 // op: rr
529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
530 op &= UINT64_C(31);
531 op <<= 4;
532 Value |= op;
533 break;
534 }
535 case AVR::CBIAb:
536 case AVR::SBIAb:
537 case AVR::SBICAb:
538 case AVR::SBISAb: {
539 // op: addr
540 op = encodeImm<AVR::fixup_port5, 0>(MI, OpNo: 0, Fixups, STI);
541 op &= UINT64_C(31);
542 op <<= 3;
543 Value |= op;
544 // op: b
545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
546 op &= UINT64_C(7);
547 Value |= op;
548 break;
549 }
550 case AVR::CALLk:
551 case AVR::JMPk: {
552 // op: k
553 op = encodeCallTarget(MI, OpNo: 0, Fixups, STI);
554 Value |= (op & UINT64_C(4063232)) << 3;
555 Value |= (op & UINT64_C(131071));
556 break;
557 }
558 case AVR::RCALLk:
559 case AVR::RJMPk: {
560 // op: k
561 op = encodeRelCondBrTarget<AVR::fixup_13_pcrel>(MI, OpNo: 0, Fixups, STI);
562 op &= UINT64_C(4095);
563 Value |= op;
564 break;
565 }
566 case AVR::BREQk:
567 case AVR::BRGEk:
568 case AVR::BRLOk:
569 case AVR::BRLTk:
570 case AVR::BRMIk:
571 case AVR::BRNEk:
572 case AVR::BRPLk:
573 case AVR::BRSHk: {
574 // op: k
575 op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, OpNo: 0, Fixups, STI);
576 op &= UINT64_C(127);
577 op <<= 3;
578 Value |= op;
579 break;
580 }
581 case AVR::BRBCsk:
582 case AVR::BRBSsk: {
583 // op: k
584 op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, OpNo: 1, Fixups, STI);
585 op &= UINT64_C(127);
586 op <<= 3;
587 Value |= op;
588 // op: s
589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
590 op &= UINT64_C(7);
591 Value |= op;
592 break;
593 }
594 case AVR::DESK: {
595 // op: k
596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
597 op &= UINT64_C(15);
598 op <<= 4;
599 Value |= op;
600 break;
601 }
602 case AVR::STDPtrQRr: {
603 // op: memri
604 op = encodeMemri(MI, OpNo: 0, Fixups, STI);
605 Value |= (op & UINT64_C(32)) << 8;
606 Value |= (op & UINT64_C(24)) << 7;
607 Value |= (op & UINT64_C(64)) >> 3;
608 Value |= (op & UINT64_C(7));
609 // op: reg
610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
611 op &= UINT64_C(31);
612 op <<= 4;
613 Value |= op;
614 break;
615 }
616 case AVR::LDDRdPtrQ: {
617 // op: memri
618 op = encodeMemri(MI, OpNo: 1, Fixups, STI);
619 Value |= (op & UINT64_C(32)) << 8;
620 Value |= (op & UINT64_C(24)) << 7;
621 Value |= (op & UINT64_C(64)) >> 3;
622 Value |= (op & UINT64_C(7));
623 // op: reg
624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
625 op &= UINT64_C(31);
626 op <<= 4;
627 Value |= op;
628 break;
629 }
630 case AVR::STPtrRr: {
631 // op: ptrreg
632 op = encodeLDSTPtrReg(MI, OpNo: 0, Fixups, STI);
633 op &= UINT64_C(3);
634 op <<= 2;
635 Value |= op;
636 // op: reg
637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
638 op &= UINT64_C(31);
639 op <<= 4;
640 Value |= op;
641 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
642 break;
643 }
644 case AVR::LDRdPtr: {
645 // op: ptrreg
646 op = encodeLDSTPtrReg(MI, OpNo: 1, Fixups, STI);
647 op &= UINT64_C(3);
648 op <<= 2;
649 Value |= op;
650 // op: reg
651 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
652 op &= UINT64_C(31);
653 op <<= 4;
654 Value |= op;
655 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
656 break;
657 }
658 case AVR::STPtrPdRr:
659 case AVR::STPtrPiRr: {
660 // op: ptrreg
661 op = encodeLDSTPtrReg(MI, OpNo: 1, Fixups, STI);
662 op &= UINT64_C(3);
663 op <<= 2;
664 Value |= op;
665 // op: reg
666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
667 op &= UINT64_C(31);
668 op <<= 4;
669 Value |= op;
670 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
671 break;
672 }
673 case AVR::LDRdPtrPd:
674 case AVR::LDRdPtrPi: {
675 // op: ptrreg
676 op = encodeLDSTPtrReg(MI, OpNo: 2, Fixups, STI);
677 op &= UINT64_C(3);
678 op <<= 2;
679 Value |= op;
680 // op: reg
681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
682 op &= UINT64_C(31);
683 op <<= 4;
684 Value |= op;
685 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
686 break;
687 }
688 case AVR::CPIRdK:
689 case AVR::LDIRdK: {
690 // op: rd
691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
692 op &= UINT64_C(15);
693 op <<= 4;
694 Value |= op;
695 // op: k
696 op = encodeImm<AVR::fixup_ldi, 0>(MI, OpNo: 1, Fixups, STI);
697 Value |= (op & UINT64_C(240)) << 4;
698 Value |= (op & UINT64_C(15));
699 break;
700 }
701 case AVR::ANDIRdK:
702 case AVR::ORIRdK:
703 case AVR::SBCIRdK:
704 case AVR::SUBIRdK: {
705 // op: rd
706 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
707 op &= UINT64_C(15);
708 op <<= 4;
709 Value |= op;
710 // op: k
711 op = encodeImm<AVR::fixup_ldi, 0>(MI, OpNo: 2, Fixups, STI);
712 Value |= (op & UINT64_C(240)) << 4;
713 Value |= (op & UINT64_C(15));
714 break;
715 }
716 case AVR::LDSRdKTiny: {
717 // op: rd
718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
719 op &= UINT64_C(15);
720 op <<= 4;
721 Value |= op;
722 // op: k
723 op = encodeImm<AVR::fixup_lds_sts_16, 0>(MI, OpNo: 1, Fixups, STI);
724 Value |= (op & UINT64_C(112)) << 4;
725 Value |= (op & UINT64_C(15));
726 break;
727 }
728 case AVR::MULSRdRr:
729 case AVR::MULSURdRr: {
730 // op: rd
731 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
732 op &= UINT64_C(15);
733 op <<= 4;
734 Value |= op;
735 // op: rr
736 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
737 op &= UINT64_C(15);
738 Value |= op;
739 break;
740 }
741 case AVR::MOVWRdRr: {
742 // op: rd
743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
744 op &= UINT64_C(30);
745 op <<= 3;
746 Value |= op;
747 // op: rr
748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
749 op &= UINT64_C(30);
750 op >>= 1;
751 Value |= op;
752 break;
753 }
754 case AVR::LDSRdK: {
755 // op: rd
756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
757 op &= UINT64_C(31);
758 op <<= 20;
759 Value |= op;
760 // op: k
761 op = encodeImm<AVR::fixup_16, 2>(MI, OpNo: 1, Fixups, STI);
762 op &= UINT64_C(65535);
763 Value |= op;
764 break;
765 }
766 case AVR::ASRRd:
767 case AVR::COMRd:
768 case AVR::DECRd:
769 case AVR::ELPMRdZ:
770 case AVR::ELPMRdZPi:
771 case AVR::INCRd:
772 case AVR::LACZRd:
773 case AVR::LASZRd:
774 case AVR::LATZRd:
775 case AVR::LPMRdZ:
776 case AVR::LPMRdZPi:
777 case AVR::LSRRd:
778 case AVR::NEGRd:
779 case AVR::POPRd:
780 case AVR::PUSHRr:
781 case AVR::RORRd:
782 case AVR::SWAPRd:
783 case AVR::XCHZRd: {
784 // op: rd
785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
786 op &= UINT64_C(31);
787 op <<= 4;
788 Value |= op;
789 break;
790 }
791 case AVR::INRdA: {
792 // op: rd
793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
794 op &= UINT64_C(31);
795 op <<= 4;
796 Value |= op;
797 // op: A
798 op = encodeImm<AVR::fixup_port6, 0>(MI, OpNo: 1, Fixups, STI);
799 Value |= (op & UINT64_C(48)) << 5;
800 Value |= (op & UINT64_C(15));
801 break;
802 }
803 case AVR::BST:
804 case AVR::SBRCRrB:
805 case AVR::SBRSRrB: {
806 // op: rd
807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
808 op &= UINT64_C(31);
809 op <<= 4;
810 Value |= op;
811 // op: b
812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
813 op &= UINT64_C(7);
814 Value |= op;
815 break;
816 }
817 case AVR::BLD: {
818 // op: rd
819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
820 op &= UINT64_C(31);
821 op <<= 4;
822 Value |= op;
823 // op: b
824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
825 op &= UINT64_C(7);
826 Value |= op;
827 break;
828 }
829 case AVR::CPCRdRr:
830 case AVR::CPRdRr:
831 case AVR::CPSE:
832 case AVR::MOVRdRr:
833 case AVR::MULRdRr: {
834 // op: rd
835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
836 op &= UINT64_C(31);
837 op <<= 4;
838 Value |= op;
839 // op: rr
840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
841 Value |= (op & UINT64_C(16)) << 5;
842 Value |= (op & UINT64_C(15));
843 break;
844 }
845 case AVR::ADCRdRr:
846 case AVR::ADDRdRr:
847 case AVR::ANDRdRr:
848 case AVR::EORRdRr:
849 case AVR::ORRdRr:
850 case AVR::SBCRdRr:
851 case AVR::SUBRdRr: {
852 // op: rd
853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
854 op &= UINT64_C(31);
855 op <<= 4;
856 Value |= op;
857 // op: rr
858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
859 Value |= (op & UINT64_C(16)) << 5;
860 Value |= (op & UINT64_C(15));
861 break;
862 }
863 case AVR::ADIWRdK:
864 case AVR::SBIWRdK: {
865 // op: rd
866 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
867 op &= UINT64_C(6);
868 op <<= 3;
869 Value |= op;
870 // op: k
871 op = encodeImm<AVR::fixup_6_adiw, 0>(MI, OpNo: 2, Fixups, STI);
872 Value |= (op & UINT64_C(48)) << 2;
873 Value |= (op & UINT64_C(15));
874 break;
875 }
876 case AVR::FMUL:
877 case AVR::FMULS:
878 case AVR::FMULSU: {
879 // op: rd
880 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
881 op &= UINT64_C(7);
882 op <<= 4;
883 Value |= op;
884 // op: rr
885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
886 op &= UINT64_C(7);
887 Value |= op;
888 break;
889 }
890 case AVR::STSKRrTiny: {
891 // op: rd
892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
893 op &= UINT64_C(15);
894 op <<= 4;
895 Value |= op;
896 // op: k
897 op = encodeImm<AVR::fixup_lds_sts_16, 0>(MI, OpNo: 0, Fixups, STI);
898 Value |= (op & UINT64_C(112)) << 4;
899 Value |= (op & UINT64_C(15));
900 break;
901 }
902 case AVR::STSKRr: {
903 // op: rd
904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
905 op &= UINT64_C(31);
906 op <<= 20;
907 Value |= op;
908 // op: k
909 op = encodeImm<AVR::fixup_16, 2>(MI, OpNo: 0, Fixups, STI);
910 op &= UINT64_C(65535);
911 Value |= op;
912 break;
913 }
914 case AVR::BCLRs:
915 case AVR::BSETs: {
916 // op: s
917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
918 op &= UINT64_C(7);
919 op <<= 4;
920 Value |= op;
921 break;
922 }
923 default:
924 std::string msg;
925 raw_string_ostream Msg(msg);
926 Msg << "Not supported instr: " << MI;
927 report_fatal_error(reason: Msg.str().c_str());
928 }
929 return Value;
930}
931
932#ifdef GET_OPERAND_BIT_OFFSET
933#undef GET_OPERAND_BIT_OFFSET
934
935uint32_t AVRMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
936 unsigned OpNum,
937 const MCSubtargetInfo &STI) const {
938 switch (MI.getOpcode()) {
939 case AVR::BREAK:
940 case AVR::EICALL:
941 case AVR::EIJMP:
942 case AVR::ELPM:
943 case AVR::ICALL:
944 case AVR::IJMP:
945 case AVR::LPM:
946 case AVR::NOP:
947 case AVR::RET:
948 case AVR::RETI:
949 case AVR::SLEEP:
950 case AVR::SPM:
951 case AVR::SPMZPi:
952 case AVR::WDR: {
953 break;
954 }
955 case AVR::OUTARr: {
956 switch (OpNum) {
957 case 0:
958 // op: A
959 return 0;
960 case 1:
961 // op: rr
962 return 4;
963 }
964 break;
965 }
966 case AVR::CBIAb:
967 case AVR::SBIAb:
968 case AVR::SBICAb:
969 case AVR::SBISAb: {
970 switch (OpNum) {
971 case 0:
972 // op: addr
973 return 3;
974 case 1:
975 // op: b
976 return 0;
977 }
978 break;
979 }
980 case AVR::CALLk:
981 case AVR::JMPk:
982 case AVR::RCALLk:
983 case AVR::RJMPk: {
984 switch (OpNum) {
985 case 0:
986 // op: k
987 return 0;
988 }
989 break;
990 }
991 case AVR::BREQk:
992 case AVR::BRGEk:
993 case AVR::BRLOk:
994 case AVR::BRLTk:
995 case AVR::BRMIk:
996 case AVR::BRNEk:
997 case AVR::BRPLk:
998 case AVR::BRSHk: {
999 switch (OpNum) {
1000 case 0:
1001 // op: k
1002 return 3;
1003 }
1004 break;
1005 }
1006 case AVR::DESK: {
1007 switch (OpNum) {
1008 case 0:
1009 // op: k
1010 return 4;
1011 }
1012 break;
1013 }
1014 case AVR::STDPtrQRr: {
1015 switch (OpNum) {
1016 case 0:
1017 // op: memri
1018 return 0;
1019 case 2:
1020 // op: reg
1021 return 4;
1022 }
1023 break;
1024 }
1025 case AVR::STPtrRr: {
1026 switch (OpNum) {
1027 case 0:
1028 // op: ptrreg
1029 return 2;
1030 case 1:
1031 // op: reg
1032 return 4;
1033 }
1034 break;
1035 }
1036 case AVR::LDSRdK: {
1037 switch (OpNum) {
1038 case 0:
1039 // op: rd
1040 return 20;
1041 case 1:
1042 // op: k
1043 return 0;
1044 }
1045 break;
1046 }
1047 case AVR::INRdA: {
1048 switch (OpNum) {
1049 case 0:
1050 // op: rd
1051 return 4;
1052 case 1:
1053 // op: A
1054 return 0;
1055 }
1056 break;
1057 }
1058 case AVR::BST:
1059 case AVR::SBRCRrB:
1060 case AVR::SBRSRrB: {
1061 switch (OpNum) {
1062 case 0:
1063 // op: rd
1064 return 4;
1065 case 1:
1066 // op: b
1067 return 0;
1068 }
1069 break;
1070 }
1071 case AVR::CPIRdK:
1072 case AVR::LDIRdK:
1073 case AVR::LDSRdKTiny: {
1074 switch (OpNum) {
1075 case 0:
1076 // op: rd
1077 return 4;
1078 case 1:
1079 // op: k
1080 return 0;
1081 }
1082 break;
1083 }
1084 case AVR::CPCRdRr:
1085 case AVR::CPRdRr:
1086 case AVR::CPSE:
1087 case AVR::FMUL:
1088 case AVR::FMULS:
1089 case AVR::FMULSU:
1090 case AVR::MOVRdRr:
1091 case AVR::MOVWRdRr:
1092 case AVR::MULRdRr:
1093 case AVR::MULSRdRr:
1094 case AVR::MULSURdRr: {
1095 switch (OpNum) {
1096 case 0:
1097 // op: rd
1098 return 4;
1099 case 1:
1100 // op: rr
1101 return 0;
1102 }
1103 break;
1104 }
1105 case AVR::BLD: {
1106 switch (OpNum) {
1107 case 0:
1108 // op: rd
1109 return 4;
1110 case 2:
1111 // op: b
1112 return 0;
1113 }
1114 break;
1115 }
1116 case AVR::ADIWRdK:
1117 case AVR::ANDIRdK:
1118 case AVR::ORIRdK:
1119 case AVR::SBCIRdK:
1120 case AVR::SBIWRdK:
1121 case AVR::SUBIRdK: {
1122 switch (OpNum) {
1123 case 0:
1124 // op: rd
1125 return 4;
1126 case 2:
1127 // op: k
1128 return 0;
1129 }
1130 break;
1131 }
1132 case AVR::ADCRdRr:
1133 case AVR::ADDRdRr:
1134 case AVR::ANDRdRr:
1135 case AVR::EORRdRr:
1136 case AVR::ORRdRr:
1137 case AVR::SBCRdRr:
1138 case AVR::SUBRdRr: {
1139 switch (OpNum) {
1140 case 0:
1141 // op: rd
1142 return 4;
1143 case 2:
1144 // op: rr
1145 return 0;
1146 }
1147 break;
1148 }
1149 case AVR::ASRRd:
1150 case AVR::COMRd:
1151 case AVR::DECRd:
1152 case AVR::ELPMRdZ:
1153 case AVR::ELPMRdZPi:
1154 case AVR::INCRd:
1155 case AVR::LACZRd:
1156 case AVR::LASZRd:
1157 case AVR::LATZRd:
1158 case AVR::LPMRdZ:
1159 case AVR::LPMRdZPi:
1160 case AVR::LSRRd:
1161 case AVR::NEGRd:
1162 case AVR::POPRd:
1163 case AVR::PUSHRr:
1164 case AVR::RORRd:
1165 case AVR::SWAPRd:
1166 case AVR::XCHZRd: {
1167 switch (OpNum) {
1168 case 0:
1169 // op: rd
1170 return 4;
1171 }
1172 break;
1173 }
1174 case AVR::BCLRs:
1175 case AVR::BSETs: {
1176 switch (OpNum) {
1177 case 0:
1178 // op: s
1179 return 4;
1180 }
1181 break;
1182 }
1183 case AVR::BRBCsk:
1184 case AVR::BRBSsk: {
1185 switch (OpNum) {
1186 case 1:
1187 // op: k
1188 return 3;
1189 case 0:
1190 // op: s
1191 return 0;
1192 }
1193 break;
1194 }
1195 case AVR::LDDRdPtrQ: {
1196 switch (OpNum) {
1197 case 1:
1198 // op: memri
1199 return 0;
1200 case 0:
1201 // op: reg
1202 return 4;
1203 }
1204 break;
1205 }
1206 case AVR::LDRdPtr: {
1207 switch (OpNum) {
1208 case 1:
1209 // op: ptrreg
1210 return 2;
1211 case 0:
1212 // op: reg
1213 return 4;
1214 }
1215 break;
1216 }
1217 case AVR::STPtrPdRr:
1218 case AVR::STPtrPiRr: {
1219 switch (OpNum) {
1220 case 1:
1221 // op: ptrreg
1222 return 2;
1223 case 2:
1224 // op: reg
1225 return 4;
1226 }
1227 break;
1228 }
1229 case AVR::STSKRr: {
1230 switch (OpNum) {
1231 case 1:
1232 // op: rd
1233 return 20;
1234 case 0:
1235 // op: k
1236 return 0;
1237 }
1238 break;
1239 }
1240 case AVR::STSKRrTiny: {
1241 switch (OpNum) {
1242 case 1:
1243 // op: rd
1244 return 4;
1245 case 0:
1246 // op: k
1247 return 0;
1248 }
1249 break;
1250 }
1251 case AVR::LDRdPtrPd:
1252 case AVR::LDRdPtrPi: {
1253 switch (OpNum) {
1254 case 2:
1255 // op: ptrreg
1256 return 2;
1257 case 0:
1258 // op: reg
1259 return 4;
1260 }
1261 break;
1262 }
1263 }
1264 std::string msg;
1265 raw_string_ostream Msg(msg);
1266 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
1267 report_fatal_error(Msg.str().c_str());
1268}
1269
1270#endif // GET_OPERAND_BIT_OFFSET
1271
1272