HexagonGenMCCodeEmitter.inc source code [llvm_projects/build/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Machine Code Emitter \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	uint64_t HexagonMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10	SmallVectorImpl<MCFixup> &Fixups,
11	const MCSubtargetInfo &STI) const {
12	static const uint64_t InstBits[] = {
13	UINT64_C(`0`),
14	UINT64_C(`0`),
15	UINT64_C(`0`),
16	UINT64_C(`0`),
17	UINT64_C(`0`),
18	UINT64_C(`0`),
19	UINT64_C(`0`),
20	UINT64_C(`0`),
21	UINT64_C(`0`),
22	UINT64_C(`0`),
23	UINT64_C(`0`),
24	UINT64_C(`0`),
25	UINT64_C(`0`),
26	UINT64_C(`0`),
27	UINT64_C(`0`),
28	UINT64_C(`0`),
29	UINT64_C(`0`),
30	UINT64_C(`0`),
31	UINT64_C(`0`),
32	UINT64_C(`0`),
33	UINT64_C(`0`),
34	UINT64_C(`0`),
35	UINT64_C(`0`),
36	UINT64_C(`0`),
37	UINT64_C(`0`),
38	UINT64_C(`0`),
39	UINT64_C(`0`),
40	UINT64_C(`0`),
41	UINT64_C(`0`),
42	UINT64_C(`0`),
43	UINT64_C(`0`),
44	UINT64_C(`0`),
45	UINT64_C(`0`),
46	UINT64_C(`0`),
47	UINT64_C(`0`),
48	UINT64_C(`0`),
49	UINT64_C(`0`),
50	UINT64_C(`0`),
51	UINT64_C(`0`),
52	UINT64_C(`0`),
53	UINT64_C(`0`),
54	UINT64_C(`0`),
55	UINT64_C(`0`),
56	UINT64_C(`0`),
57	UINT64_C(`0`),
58	UINT64_C(`0`),
59	UINT64_C(`0`),
60	UINT64_C(`0`),
61	UINT64_C(`0`),
62	UINT64_C(`0`),
63	UINT64_C(`0`),
64	UINT64_C(`0`),
65	UINT64_C(`0`),
66	UINT64_C(`0`),
67	UINT64_C(`0`),
68	UINT64_C(`0`),
69	UINT64_C(`0`),
70	UINT64_C(`0`),
71	UINT64_C(`0`),
72	UINT64_C(`0`),
73	UINT64_C(`0`),
74	UINT64_C(`0`),
75	UINT64_C(`0`),
76	UINT64_C(`0`),
77	UINT64_C(`0`),
78	UINT64_C(`0`),
79	UINT64_C(`0`),
80	UINT64_C(`0`),
81	UINT64_C(`0`),
82	UINT64_C(`0`),
83	UINT64_C(`0`),
84	UINT64_C(`0`),
85	UINT64_C(`0`),
86	UINT64_C(`0`),
87	UINT64_C(`0`),
88	UINT64_C(`0`),
89	UINT64_C(`0`),
90	UINT64_C(`0`),
91	UINT64_C(`0`),
92	UINT64_C(`0`),
93	UINT64_C(`0`),
94	UINT64_C(`0`),
95	UINT64_C(`0`),
96	UINT64_C(`0`),
97	UINT64_C(`0`),
98	UINT64_C(`0`),
99	UINT64_C(`0`),
100	UINT64_C(`0`),
101	UINT64_C(`0`),
102	UINT64_C(`0`),
103	UINT64_C(`0`),
104	UINT64_C(`0`),
105	UINT64_C(`0`),
106	UINT64_C(`0`),
107	UINT64_C(`0`),
108	UINT64_C(`0`),
109	UINT64_C(`0`),
110	UINT64_C(`0`),
111	UINT64_C(`0`),
112	UINT64_C(`0`),
113	UINT64_C(`0`),
114	UINT64_C(`0`),
115	UINT64_C(`0`),
116	UINT64_C(`0`),
117	UINT64_C(`0`),
118	UINT64_C(`0`),
119	UINT64_C(`0`),
120	UINT64_C(`0`),
121	UINT64_C(`0`),
122	UINT64_C(`0`),
123	UINT64_C(`0`),
124	UINT64_C(`0`),
125	UINT64_C(`0`),
126	UINT64_C(`0`),
127	UINT64_C(`0`),
128	UINT64_C(`0`),
129	UINT64_C(`0`),
130	UINT64_C(`0`),
131	UINT64_C(`0`),
132	UINT64_C(`0`),
133	UINT64_C(`0`),
134	UINT64_C(`0`),
135	UINT64_C(`0`),
136	UINT64_C(`0`),
137	UINT64_C(`0`),
138	UINT64_C(`0`),
139	UINT64_C(`0`),
140	UINT64_C(`0`),
141	UINT64_C(`0`),
142	UINT64_C(`0`),
143	UINT64_C(`0`),
144	UINT64_C(`0`),
145	UINT64_C(`0`),
146	UINT64_C(`0`),
147	UINT64_C(`0`),
148	UINT64_C(`0`),
149	UINT64_C(`0`),
150	UINT64_C(`0`),
151	UINT64_C(`0`),
152	UINT64_C(`0`),
153	UINT64_C(`0`),
154	UINT64_C(`0`),
155	UINT64_C(`0`),
156	UINT64_C(`0`),
157	UINT64_C(`0`),
158	UINT64_C(`0`),
159	UINT64_C(`0`),
160	UINT64_C(`0`),
161	UINT64_C(`0`),
162	UINT64_C(`0`),
163	UINT64_C(`0`),
164	UINT64_C(`0`),
165	UINT64_C(`0`),
166	UINT64_C(`0`),
167	UINT64_C(`0`),
168	UINT64_C(`0`),
169	UINT64_C(`0`),
170	UINT64_C(`0`),
171	UINT64_C(`0`),
172	UINT64_C(`0`),
173	UINT64_C(`0`),
174	UINT64_C(`0`),
175	UINT64_C(`0`),
176	UINT64_C(`0`),
177	UINT64_C(`0`),
178	UINT64_C(`0`),
179	UINT64_C(`0`),
180	UINT64_C(`0`),
181	UINT64_C(`0`),
182	UINT64_C(`0`),
183	UINT64_C(`0`),
184	UINT64_C(`0`),
185	UINT64_C(`0`),
186	UINT64_C(`0`),
187	UINT64_C(`0`),
188	UINT64_C(`0`),
189	UINT64_C(`0`),
190	UINT64_C(`0`),
191	UINT64_C(`0`),
192	UINT64_C(`0`),
193	UINT64_C(`0`),
194	UINT64_C(`0`),
195	UINT64_C(`0`),
196	UINT64_C(`0`),
197	UINT64_C(`0`),
198	UINT64_C(`0`),
199	UINT64_C(`0`),
200	UINT64_C(`0`),
201	UINT64_C(`0`),
202	UINT64_C(`0`),
203	UINT64_C(`0`),
204	UINT64_C(`0`),
205	UINT64_C(`0`),
206	UINT64_C(`0`),
207	UINT64_C(`0`),
208	UINT64_C(`0`),
209	UINT64_C(`0`),
210	UINT64_C(`0`),
211	UINT64_C(`0`),
212	UINT64_C(`0`),
213	UINT64_C(`0`),
214	UINT64_C(`0`),
215	UINT64_C(`0`),
216	UINT64_C(`0`),
217	UINT64_C(`0`),
218	UINT64_C(`0`),
219	UINT64_C(`0`),
220	UINT64_C(`0`),
221	UINT64_C(`0`),
222	UINT64_C(`0`),
223	UINT64_C(`0`),
224	UINT64_C(`0`),
225	UINT64_C(`0`),
226	UINT64_C(`0`),
227	UINT64_C(`0`),
228	UINT64_C(`0`),
229	UINT64_C(`0`),
230	UINT64_C(`0`),
231	UINT64_C(`0`),
232	UINT64_C(`0`),
233	UINT64_C(`0`),
234	UINT64_C(`0`),
235	UINT64_C(`0`),
236	UINT64_C(`0`),
237	UINT64_C(`0`),
238	UINT64_C(`0`),
239	UINT64_C(`0`),
240	UINT64_C(`0`),
241	UINT64_C(`0`),
242	UINT64_C(`0`),
243	UINT64_C(`0`),
244	UINT64_C(`0`),
245	UINT64_C(`0`),
246	UINT64_C(`0`),
247	UINT64_C(`0`),
248	UINT64_C(`0`),
249	UINT64_C(`0`),
250	UINT64_C(`0`),
251	UINT64_C(`0`),
252	UINT64_C(`0`),
253	UINT64_C(`0`),
254	UINT64_C(`0`),
255	UINT64_C(`0`),
256	UINT64_C(`0`),
257	UINT64_C(`0`),
258	UINT64_C(`0`),
259	UINT64_C(`0`),
260	UINT64_C(`0`),
261	UINT64_C(`0`),
262	UINT64_C(`0`),
263	UINT64_C(`0`),
264	UINT64_C(`0`),
265	UINT64_C(`0`),
266	UINT64_C(`0`),
267	UINT64_C(`0`),
268	UINT64_C(`0`),
269	UINT64_C(`0`),
270	UINT64_C(`0`),
271	UINT64_C(`0`),
272	UINT64_C(`0`),
273	UINT64_C(`0`),
274	UINT64_C(`0`),
275	UINT64_C(`0`),
276	UINT64_C(`0`),
277	UINT64_C(`0`),
278	UINT64_C(`0`),
279	UINT64_C(`0`),
280	UINT64_C(`0`),
281	UINT64_C(`0`),
282	UINT64_C(`0`),
283	UINT64_C(`0`),
284	UINT64_C(`0`),
285	UINT64_C(`0`),
286	UINT64_C(`0`),
287	UINT64_C(`0`),
288	UINT64_C(`0`),
289	UINT64_C(`0`),
290	UINT64_C(`0`),
291	UINT64_C(`0`),
292	UINT64_C(`0`),
293	UINT64_C(`0`),
294	UINT64_C(`0`),
295	UINT64_C(`0`),
296	UINT64_C(`0`),
297	UINT64_C(`0`),
298	UINT64_C(`0`),
299	UINT64_C(`0`),
300	UINT64_C(`0`),
301	UINT64_C(`0`),
302	UINT64_C(`0`),
303	UINT64_C(`0`),
304	UINT64_C(`0`),
305	UINT64_C(`0`),
306	UINT64_C(`0`),
307	UINT64_C(`0`),
308	UINT64_C(`0`),
309	UINT64_C(`0`),
310	UINT64_C(`0`),
311	UINT64_C(`0`),
312	UINT64_C(`0`),
313	UINT64_C(`0`),
314	UINT64_C(`0`),
315	UINT64_C(`0`),
316	UINT64_C(`0`),
317	UINT64_C(`0`),
318	UINT64_C(`0`),
319	UINT64_C(`0`),
320	UINT64_C(`0`),
321	UINT64_C(`0`),
322	UINT64_C(`0`),
323	UINT64_C(`0`),
324	UINT64_C(`0`),
325	UINT64_C(`0`),
326	UINT64_C(`0`),
327	UINT64_C(`0`),
328	UINT64_C(`0`),
329	UINT64_C(`0`),
330	UINT64_C(`0`),
331	UINT64_C(`0`),
332	UINT64_C(`0`),
333	UINT64_C(`0`),
334	UINT64_C(`0`),
335	UINT64_C(`0`),
336	UINT64_C(`0`),
337	UINT64_C(`0`),
338	UINT64_C(`0`),
339	UINT64_C(`0`),
340	UINT64_C(`0`),
341	UINT64_C(`0`),
342	UINT64_C(`0`),
343	UINT64_C(`0`),
344	UINT64_C(`0`),
345	UINT64_C(`0`),
346	UINT64_C(`0`),
347	UINT64_C(`0`),
348	UINT64_C(`0`),
349	UINT64_C(`0`),
350	UINT64_C(`0`),
351	UINT64_C(`0`),
352	UINT64_C(`0`),
353	UINT64_C(`0`),
354	UINT64_C(`0`),
355	UINT64_C(`0`),
356	UINT64_C(`0`),
357	UINT64_C(`0`),
358	UINT64_C(`0`),
359	UINT64_C(`0`),
360	UINT64_C(`0`),
361	UINT64_C(`0`),
362	UINT64_C(`0`),
363	UINT64_C(`0`),
364	UINT64_C(`0`),
365	UINT64_C(`0`),
366	UINT64_C(`0`),
367	UINT64_C(`0`),
368	UINT64_C(`0`),
369	UINT64_C(`0`),
370	UINT64_C(`0`),
371	UINT64_C(`0`),
372	UINT64_C(`0`),
373	UINT64_C(`0`),
374	UINT64_C(`0`),
375	UINT64_C(`0`),
376	UINT64_C(`0`),
377	UINT64_C(`0`),
378	UINT64_C(`0`),
379	UINT64_C(`0`),
380	UINT64_C(`0`),
381	UINT64_C(`0`),
382	UINT64_C(`0`),
383	UINT64_C(`0`),
384	UINT64_C(`0`),
385	UINT64_C(`0`),
386	UINT64_C(`0`),
387	UINT64_C(`0`),
388	UINT64_C(`0`),
389	UINT64_C(`0`),
390	UINT64_C(`0`),
391	UINT64_C(`0`),
392	UINT64_C(`0`),
393	UINT64_C(`0`),
394	UINT64_C(`0`),
395	UINT64_C(`0`),
396	UINT64_C(`0`),
397	UINT64_C(`0`),
398	UINT64_C(`0`),
399	UINT64_C(`0`),
400	UINT64_C(`0`),
401	UINT64_C(`0`),
402	UINT64_C(`0`),
403	UINT64_C(`0`),
404	UINT64_C(`0`),
405	UINT64_C(`0`),
406	UINT64_C(`0`),
407	UINT64_C(`0`),
408	UINT64_C(`0`),
409	UINT64_C(`0`),
410	UINT64_C(`0`),
411	UINT64_C(`0`),
412	UINT64_C(`0`),
413	UINT64_C(`0`),
414	UINT64_C(`0`),
415	UINT64_C(`0`),
416	UINT64_C(`0`),
417	UINT64_C(`0`),
418	UINT64_C(`0`),
419	UINT64_C(`0`),
420	UINT64_C(`0`),
421	UINT64_C(`0`),
422	UINT64_C(`0`),
423	UINT64_C(`0`),
424	UINT64_C(`0`),
425	UINT64_C(`0`),
426	UINT64_C(`0`),
427	UINT64_C(`0`),
428	UINT64_C(`0`),
429	UINT64_C(`0`),
430	UINT64_C(`0`),
431	UINT64_C(`0`),
432	UINT64_C(`0`),
433	UINT64_C(`0`),
434	UINT64_C(`0`),
435	UINT64_C(`0`),
436	UINT64_C(`0`),
437	UINT64_C(`0`),
438	UINT64_C(`0`),
439	UINT64_C(`0`),
440	UINT64_C(`0`),
441	UINT64_C(`0`),
442	UINT64_C(`0`),
443	UINT64_C(`0`),
444	UINT64_C(`0`),
445	UINT64_C(`0`),
446	UINT64_C(`0`),
447	UINT64_C(`0`),
448	UINT64_C(`0`),
449	UINT64_C(`0`),
450	UINT64_C(`0`),
451	UINT64_C(`0`),
452	UINT64_C(`0`),
453	UINT64_C(`0`),
454	UINT64_C(`0`),
455	UINT64_C(`0`),
456	UINT64_C(`0`),
457	UINT64_C(`0`),
458	UINT64_C(`0`),
459	UINT64_C(`0`),
460	UINT64_C(`0`),
461	UINT64_C(`0`),
462	UINT64_C(`0`),
463	UINT64_C(`0`),
464	UINT64_C(`0`),
465	UINT64_C(`0`),
466	UINT64_C(`0`),
467	UINT64_C(`0`),
468	UINT64_C(`0`),
469	UINT64_C(`0`),
470	UINT64_C(`0`),
471	UINT64_C(`0`),
472	UINT64_C(`0`),
473	UINT64_C(`0`),
474	UINT64_C(`0`),
475	UINT64_C(`0`),
476	UINT64_C(`0`),
477	UINT64_C(`0`),
478	UINT64_C(`0`),
479	UINT64_C(`0`),
480	UINT64_C(`0`),
481	UINT64_C(`0`),
482	UINT64_C(`0`),
483	UINT64_C(`0`),
484	UINT64_C(`0`),
485	UINT64_C(`0`),
486	UINT64_C(`0`),
487	UINT64_C(`0`),
488	UINT64_C(`0`),
489	UINT64_C(`0`),
490	UINT64_C(`0`),
491	UINT64_C(`0`),
492	UINT64_C(`0`),
493	UINT64_C(`0`),
494	UINT64_C(`0`),
495	UINT64_C(`0`),
496	UINT64_C(`0`),
497	UINT64_C(`0`),
498	UINT64_C(`0`),
499	UINT64_C(`0`),
500	UINT64_C(`0`),
501	UINT64_C(`0`),
502	UINT64_C(`0`),
503	UINT64_C(`0`),
504	UINT64_C(`0`),
505	UINT64_C(`0`),
506	UINT64_C(`0`),
507	UINT64_C(`0`),
508	UINT64_C(`0`),
509	UINT64_C(`0`),
510	UINT64_C(`0`),
511	UINT64_C(`0`),
512	UINT64_C(`0`),
513	UINT64_C(`0`),
514	UINT64_C(`0`),
515	UINT64_C(`0`),
516	UINT64_C(`0`),
517	UINT64_C(`0`),
518	UINT64_C(`0`),
519	UINT64_C(`0`),
520	UINT64_C(`0`),
521	UINT64_C(`0`),
522	UINT64_C(`0`),
523	UINT64_C(`0`),
524	UINT64_C(`0`),
525	UINT64_C(`0`),
526	UINT64_C(`0`),
527	UINT64_C(`0`),
528	UINT64_C(`0`),
529	UINT64_C(`0`),
530	UINT64_C(`0`),
531	UINT64_C(`0`),
532	UINT64_C(`0`),
533	UINT64_C(`0`),
534	UINT64_C(`0`),
535	UINT64_C(`0`),
536	UINT64_C(`0`),
537	UINT64_C(`0`),
538	UINT64_C(`0`),
539	UINT64_C(`0`),
540	UINT64_C(`0`),
541	UINT64_C(`0`),
542	UINT64_C(`0`),
543	UINT64_C(`0`),
544	UINT64_C(`0`),
545	UINT64_C(`0`),
546	UINT64_C(`0`),
547	UINT64_C(`0`),
548	UINT64_C(`0`),
549	UINT64_C(`0`),
550	UINT64_C(`0`),
551	UINT64_C(`0`),
552	UINT64_C(`0`),
553	UINT64_C(`0`),
554	UINT64_C(`0`),
555	UINT64_C(`0`),
556	UINT64_C(`0`),
557	UINT64_C(`0`),
558	UINT64_C(`0`),
559	UINT64_C(`0`),
560	UINT64_C(`0`),
561	UINT64_C(`0`),
562	UINT64_C(`0`),
563	UINT64_C(`0`),
564	UINT64_C(`0`),
565	UINT64_C(`0`),
566	UINT64_C(`0`),
567	UINT64_C(`0`),
568	UINT64_C(`0`),
569	UINT64_C(`0`),
570	UINT64_C(`0`),
571	UINT64_C(`0`),
572	UINT64_C(`0`),
573	UINT64_C(`0`),
574	UINT64_C(`0`),
575	UINT64_C(`0`),
576	UINT64_C(`0`),
577	UINT64_C(`0`),
578	UINT64_C(`0`),
579	UINT64_C(`0`),
580	UINT64_C(`0`),
581	UINT64_C(`0`),
582	UINT64_C(`0`),
583	UINT64_C(`0`),
584	UINT64_C(`0`),
585	UINT64_C(`0`),
586	UINT64_C(`0`),
587	UINT64_C(`0`),
588	UINT64_C(`0`),
589	UINT64_C(`0`),
590	UINT64_C(`0`),
591	UINT64_C(`0`),
592	UINT64_C(`0`),
593	UINT64_C(`0`),
594	UINT64_C(`0`),
595	UINT64_C(`0`),
596	UINT64_C(`0`),
597	UINT64_C(`0`),
598	UINT64_C(`0`),
599	UINT64_C(`0`),
600	UINT64_C(`0`),
601	UINT64_C(`0`),
602	UINT64_C(`0`),
603	UINT64_C(`0`),
604	UINT64_C(`0`),
605	UINT64_C(`0`),
606	UINT64_C(`0`),
607	UINT64_C(`0`),
608	UINT64_C(`0`),
609	UINT64_C(`0`),
610	UINT64_C(`0`),
611	UINT64_C(`0`),
612	UINT64_C(`0`),
613	UINT64_C(`0`),
614	UINT64_C(`0`),
615	UINT64_C(`0`),
616	UINT64_C(`0`),
617	UINT64_C(`0`),
618	UINT64_C(`0`),
619	UINT64_C(`0`),
620	UINT64_C(`0`),
621	UINT64_C(`0`),
622	UINT64_C(`0`),
623	UINT64_C(`0`),
624	UINT64_C(`0`),
625	UINT64_C(`0`),
626	UINT64_C(`0`),
627	UINT64_C(`0`),
628	UINT64_C(`0`),
629	UINT64_C(`0`),
630	UINT64_C(`0`),
631	UINT64_C(`0`),
632	UINT64_C(`0`),
633	UINT64_C(`0`),
634	UINT64_C(`0`),
635	UINT64_C(`0`),
636	UINT64_C(`0`),
637	UINT64_C(`0`),
638	UINT64_C(`0`),
639	UINT64_C(`0`),
640	UINT64_C(`0`),
641	UINT64_C(`0`),
642	UINT64_C(`0`),
643	UINT64_C(`0`),
644	UINT64_C(`0`),
645	UINT64_C(`0`),
646	UINT64_C(`0`),
647	UINT64_C(`0`),
648	UINT64_C(`0`),
649	UINT64_C(`0`),
650	UINT64_C(`0`),
651	UINT64_C(`0`),
652	UINT64_C(`0`),
653	UINT64_C(`0`),
654	UINT64_C(`0`),
655	UINT64_C(`0`),
656	UINT64_C(`0`),
657	UINT64_C(`0`),
658	UINT64_C(`0`),
659	UINT64_C(`0`),
660	UINT64_C(`0`),
661	UINT64_C(`0`),
662	UINT64_C(`0`),
663	UINT64_C(`0`),
664	UINT64_C(`0`),
665	UINT64_C(`0`),
666	UINT64_C(`0`),
667	UINT64_C(`0`),
668	UINT64_C(`0`),
669	UINT64_C(`0`),
670	UINT64_C(`0`),
671	UINT64_C(`0`),
672	UINT64_C(`0`),
673	UINT64_C(`0`),
674	UINT64_C(`0`),
675	UINT64_C(`0`),
676	UINT64_C(`0`),
677	UINT64_C(`0`),
678	UINT64_C(`0`),
679	UINT64_C(`0`),
680	UINT64_C(`0`),
681	UINT64_C(`0`),
682	UINT64_C(`0`),
683	UINT64_C(`0`),
684	UINT64_C(`0`),
685	UINT64_C(`0`),
686	UINT64_C(`0`),
687	UINT64_C(`0`),
688	UINT64_C(`0`),
689	UINT64_C(`0`),
690	UINT64_C(`0`),
691	UINT64_C(`0`),
692	UINT64_C(`0`),
693	UINT64_C(`0`),
694	UINT64_C(`0`),
695	UINT64_C(`0`),
696	UINT64_C(`0`),
697	UINT64_C(`0`),
698	UINT64_C(`0`),
699	UINT64_C(`0`),
700	UINT64_C(`0`),
701	UINT64_C(`0`),
702	UINT64_C(`0`),
703	UINT64_C(`0`),
704	UINT64_C(`0`),
705	UINT64_C(`0`),
706	UINT64_C(`0`),
707	UINT64_C(`0`),
708	UINT64_C(`0`),
709	UINT64_C(`0`),
710	UINT64_C(`0`),
711	UINT64_C(`0`),
712	UINT64_C(`0`),
713	UINT64_C(`0`),
714	UINT64_C(`0`),
715	UINT64_C(`0`),
716	UINT64_C(`0`),
717	UINT64_C(`0`),
718	UINT64_C(`0`),
719	UINT64_C(`0`),
720	UINT64_C(`0`),
721	UINT64_C(`0`),
722	UINT64_C(`0`),
723	UINT64_C(`0`),
724	UINT64_C(`0`),
725	UINT64_C(`0`),
726	UINT64_C(`0`),
727	UINT64_C(`0`),
728	UINT64_C(`0`),
729	UINT64_C(`0`),
730	UINT64_C(`0`),
731	UINT64_C(`0`),
732	UINT64_C(`0`),
733	UINT64_C(`0`),
734	UINT64_C(`0`),
735	UINT64_C(`0`),
736	UINT64_C(`0`),
737	UINT64_C(`0`),
738	UINT64_C(`0`),
739	UINT64_C(`0`),
740	UINT64_C(`0`),
741	UINT64_C(`0`),
742	UINT64_C(`0`),
743	UINT64_C(`0`),
744	UINT64_C(`0`),
745	UINT64_C(`0`),
746	UINT64_C(`0`),
747	UINT64_C(`0`),
748	UINT64_C(`0`),
749	UINT64_C(`0`),
750	UINT64_C(`0`),
751	UINT64_C(`0`),
752	UINT64_C(`0`),
753	UINT64_C(`0`),
754	UINT64_C(`0`),
755	UINT64_C(`0`),
756	UINT64_C(`0`),
757	UINT64_C(`0`),
758	UINT64_C(`0`),
759	UINT64_C(`0`),
760	UINT64_C(`0`),
761	UINT64_C(`0`),
762	UINT64_C(`0`),
763	UINT64_C(`0`),
764	UINT64_C(`0`),
765	UINT64_C(`0`),
766	UINT64_C(`0`),
767	UINT64_C(`0`),
768	UINT64_C(`0`),
769	UINT64_C(`0`),
770	UINT64_C(`0`),
771	UINT64_C(`0`),
772	UINT64_C(`0`),
773	UINT64_C(`0`),
774	UINT64_C(`0`),
775	UINT64_C(`0`),
776	UINT64_C(`0`),
777	UINT64_C(`0`),
778	UINT64_C(`0`),
779	UINT64_C(`0`),
780	UINT64_C(`0`),
781	UINT64_C(`0`),
782	UINT64_C(`0`),
783	UINT64_C(`0`),
784	UINT64_C(`0`),
785	UINT64_C(`0`),
786	UINT64_C(`0`),
787	UINT64_C(`0`),
788	UINT64_C(`0`),
789	UINT64_C(`0`),
790	UINT64_C(`0`),
791	UINT64_C(`0`),
792	UINT64_C(`0`),
793	UINT64_C(`0`),
794	UINT64_C(`0`),
795	UINT64_C(`0`),
796	UINT64_C(`0`),
797	UINT64_C(`0`),
798	UINT64_C(`0`),
799	UINT64_C(`0`),
800	UINT64_C(`0`),
801	UINT64_C(`0`),
802	UINT64_C(`0`),
803	UINT64_C(`0`),
804	UINT64_C(`0`),
805	UINT64_C(`0`),
806	UINT64_C(`0`),
807	UINT64_C(`0`),
808	UINT64_C(`0`),
809	UINT64_C(`0`),
810	UINT64_C(`0`),
811	UINT64_C(`0`),
812	UINT64_C(`0`),
813	UINT64_C(`0`),
814	UINT64_C(`0`),
815	UINT64_C(`0`),
816	UINT64_C(`0`),
817	UINT64_C(`0`),
818	UINT64_C(`0`),
819	UINT64_C(`0`),
820	UINT64_C(`0`),
821	UINT64_C(`0`),
822	UINT64_C(`0`),
823	UINT64_C(`0`),
824	UINT64_C(`0`),
825	UINT64_C(`0`),
826	UINT64_C(`0`),
827	UINT64_C(`0`),
828	UINT64_C(`0`),
829	UINT64_C(`0`),
830	UINT64_C(`0`),
831	UINT64_C(`0`),
832	UINT64_C(`0`),
833	UINT64_C(`0`),
834	UINT64_C(`0`),
835	UINT64_C(`0`),
836	UINT64_C(`0`),
837	UINT64_C(`0`),
838	UINT64_C(`0`),
839	UINT64_C(`0`),
840	UINT64_C(`0`),
841	UINT64_C(`0`),
842	UINT64_C(`0`),
843	UINT64_C(`0`),
844	UINT64_C(`0`),
845	UINT64_C(`0`),
846	UINT64_C(`0`),
847	UINT64_C(`0`),
848	UINT64_C(`0`),
849	UINT64_C(`0`),
850	UINT64_C(`0`),
851	UINT64_C(`0`),
852	UINT64_C(`0`),
853	UINT64_C(`0`),
854	UINT64_C(`0`),
855	UINT64_C(`0`),
856	UINT64_C(`0`),
857	UINT64_C(`0`),
858	UINT64_C(`0`),
859	UINT64_C(`0`),
860	UINT64_C(`0`),
861	UINT64_C(`0`),
862	UINT64_C(`0`),
863	UINT64_C(`0`),
864	UINT64_C(`0`),
865	UINT64_C(`0`),
866	UINT64_C(`0`),
867	UINT64_C(`0`),
868	UINT64_C(`0`),
869	UINT64_C(`0`),
870	UINT64_C(`0`),
871	UINT64_C(`0`),
872	UINT64_C(`0`),
873	UINT64_C(`0`),
874	UINT64_C(`0`),
875	UINT64_C(`0`),
876	UINT64_C(`0`),
877	UINT64_C(`0`),
878	UINT64_C(`0`),
879	UINT64_C(`0`),
880	UINT64_C(`0`),
881	UINT64_C(`0`),
882	UINT64_C(`0`),
883	UINT64_C(`0`),
884	UINT64_C(`0`),
885	UINT64_C(`0`),
886	UINT64_C(`0`),
887	UINT64_C(`0`),
888	UINT64_C(`0`),
889	UINT64_C(`0`),
890	UINT64_C(`0`),
891	UINT64_C(`0`),
892	UINT64_C(`0`),
893	UINT64_C(`0`),
894	UINT64_C(`0`),
895	UINT64_C(`0`),
896	UINT64_C(`0`),
897	UINT64_C(`0`),
898	UINT64_C(`0`),
899	UINT64_C(`0`),
900	UINT64_C(`0`),
901	UINT64_C(`0`),
902	UINT64_C(`0`),
903	UINT64_C(`0`),
904	UINT64_C(`0`),
905	UINT64_C(`0`),
906	UINT64_C(`0`),
907	UINT64_C(`0`),
908	UINT64_C(`0`),
909	UINT64_C(`0`),
910	UINT64_C(`0`),
911	UINT64_C(`0`),
912	UINT64_C(`0`),
913	UINT64_C(`0`),
914	UINT64_C(`0`),
915	UINT64_C(`2357198976`), // A2_abs
916	UINT64_C(`2155872448`), // A2_absp
917	UINT64_C(`2357199008`), // A2_abssat
918	UINT64_C(`4076863488`), // A2_add
919	UINT64_C(`3577741408`), // A2_addh_h16_hh
920	UINT64_C(`3577741376`), // A2_addh_h16_hl
921	UINT64_C(`3577741344`), // A2_addh_h16_lh
922	UINT64_C(`3577741312`), // A2_addh_h16_ll
923	UINT64_C(`3577741536`), // A2_addh_h16_sat_hh
924	UINT64_C(`3577741504`), // A2_addh_h16_sat_hl
925	UINT64_C(`3577741472`), // A2_addh_h16_sat_lh
926	UINT64_C(`3577741440`), // A2_addh_h16_sat_ll
927	UINT64_C(`3573547072`), // A2_addh_l16_hl
928	UINT64_C(`3573547008`), // A2_addh_l16_ll
929	UINT64_C(`3573547200`), // A2_addh_l16_sat_hl
930	UINT64_C(`3573547136`), // A2_addh_l16_sat_ll
931	UINT64_C(`2952790016`), // A2_addi
932	UINT64_C(`3539992800`), // A2_addp
933	UINT64_C(`3546284192`), // A2_addpsat
934	UINT64_C(`4131389440`), // A2_addsat
935	UINT64_C(`3546284256`), // A2_addsph
936	UINT64_C(`3546284224`), // A2_addspl
937	UINT64_C(`4043309056`), // A2_and
938	UINT64_C(`1979711488`), // A2_andir
939	UINT64_C(`3554672640`), // A2_andp
940	UINT64_C(`1879048192`), // A2_aslh
941	UINT64_C(`1881145344`), // A2_asrh
942	UINT64_C(`4085252096`), // A2_combine_hh
943	UINT64_C(`4087349248`), // A2_combine_hl
944	UINT64_C(`4089446400`), // A2_combine_lh
945	UINT64_C(`4091543552`), // A2_combine_ll
946	UINT64_C(`2080374784`), // A2_combineii
947	UINT64_C(`4110417920`), // A2_combinew
948	UINT64_C(`3586129920`), // A2_max
949	UINT64_C(`3552575616`), // A2_maxp
950	UINT64_C(`3586130048`), // A2_maxu
951	UINT64_C(`3552575648`), // A2_maxup
952	UINT64_C(`3584032768`), // A2_min
953	UINT64_C(`3550478528`), // A2_minp
954	UINT64_C(`3584032896`), // A2_minu
955	UINT64_C(`3550478560`), // A2_minup
956	UINT64_C(`2155872416`), // A2_negp
957	UINT64_C(`2357199040`), // A2_negsat
958	UINT64_C(`2130706432`), // A2_nop
959	UINT64_C(`2155872384`), // A2_notp
960	UINT64_C(`4045406208`), // A2_or
961	UINT64_C(`1988100096`), // A2_orir
962	UINT64_C(`3554672704`), // A2_orp
963	UINT64_C(`4211081344`), // A2_paddf
964	UINT64_C(`4211089536`), // A2_paddfnew
965	UINT64_C(`1954545664`), // A2_paddif
966	UINT64_C(`1954553856`), // A2_paddifnew
967	UINT64_C(`1946157056`), // A2_paddit
968	UINT64_C(`1946165248`), // A2_padditnew
969	UINT64_C(`4211081216`), // A2_paddt
970	UINT64_C(`4211089408`), // A2_paddtnew
971	UINT64_C(`4177526912`), // A2_pandf
972	UINT64_C(`4177535104`), // A2_pandfnew
973	UINT64_C(`4177526784`), // A2_pandt
974	UINT64_C(`4177534976`), // A2_pandtnew
975	UINT64_C(`4179624064`), // A2_porf
976	UINT64_C(`4179632256`), // A2_porfnew
977	UINT64_C(`4179623936`), // A2_port
978	UINT64_C(`4179632128`), // A2_portnew
979	UINT64_C(`4213178496`), // A2_psubf
980	UINT64_C(`4213186688`), // A2_psubfnew
981	UINT64_C(`4213178368`), // A2_psubt
982	UINT64_C(`4213186560`), // A2_psubtnew
983	UINT64_C(`4183818368`), // A2_pxorf
984	UINT64_C(`4183826560`), // A2_pxorfnew
985	UINT64_C(`4183818240`), // A2_pxort
986	UINT64_C(`4183826432`), // A2_pxortnew
987	UINT64_C(`2294284320`), // A2_roundsat
988	UINT64_C(`2294284288`), // A2_sat
989	UINT64_C(`2361393376`), // A2_satb
990	UINT64_C(`2361393280`), // A2_sath
991	UINT64_C(`2361393344`), // A2_satub
992	UINT64_C(`2361393312`), // A2_satuh
993	UINT64_C(`4078960640`), // A2_sub
994	UINT64_C(`3579838560`), // A2_subh_h16_hh
995	UINT64_C(`3579838528`), // A2_subh_h16_hl
996	UINT64_C(`3579838496`), // A2_subh_h16_lh
997	UINT64_C(`3579838464`), // A2_subh_h16_ll
998	UINT64_C(`3579838688`), // A2_subh_h16_sat_hh
999	UINT64_C(`3579838656`), // A2_subh_h16_sat_hl
1000	UINT64_C(`3579838624`), // A2_subh_h16_sat_lh
1001	UINT64_C(`3579838592`), // A2_subh_h16_sat_ll
1002	UINT64_C(`3575644224`), // A2_subh_l16_hl
1003	UINT64_C(`3575644160`), // A2_subh_l16_ll
1004	UINT64_C(`3575644352`), // A2_subh_l16_sat_hl
1005	UINT64_C(`3575644288`), // A2_subh_l16_sat_ll
1006	UINT64_C(`3542089952`), // A2_subp
1007	UINT64_C(`1983905792`), // A2_subri
1008	UINT64_C(`4139778048`), // A2_subsat
1009	UINT64_C(`4127195136`), // A2_svaddh
1010	UINT64_C(`4129292288`), // A2_svaddhs
1011	UINT64_C(`4133486592`), // A2_svadduhs
1012	UINT64_C(`4143972352`), // A2_svavgh
1013	UINT64_C(`4146069504`), // A2_svavghs
1014	UINT64_C(`4150263808`), // A2_svnavgh
1015	UINT64_C(`4135583744`), // A2_svsubh
1016	UINT64_C(`4137680896`), // A2_svsubhs
1017	UINT64_C(`4141875200`), // A2_svsubuhs
1018	UINT64_C(`2357199072`), // A2_swiz
1019	UINT64_C(`1889533952`), // A2_sxtb
1020	UINT64_C(`1893728256`), // A2_sxth
1021	UINT64_C(`2218786816`), // A2_sxtw
1022	UINT64_C(`1885339648`), // A2_tfr
1023	UINT64_C(`1778384896`), // A2_tfrcrr
1024	UINT64_C(`1914699776`), // A2_tfrih
1025	UINT64_C(`1897922560`), // A2_tfril
1026	UINT64_C(`1646264320`), // A2_tfrrcr
1027	UINT64_C(`2013265920`), // A2_tfrsi
1028	UINT64_C(`2151678080`), // A2_vabsh
1029	UINT64_C(`2151678112`), // A2_vabshsat
1030	UINT64_C(`2151678144`), // A2_vabsw
1031	UINT64_C(`2151678176`), // A2_vabswsat
1032	UINT64_C(`3539992640`), // A2_vaddh
1033	UINT64_C(`3539992672`), // A2_vaddhs
1034	UINT64_C(`3539992576`), // A2_vaddub
1035	UINT64_C(`3539992608`), // A2_vaddubs
1036	UINT64_C(`3539992704`), // A2_vadduhs
1037	UINT64_C(`3539992736`), // A2_vaddw
1038	UINT64_C(`3539992768`), // A2_vaddws
1039	UINT64_C(`3544186944`), // A2_vavgh
1040	UINT64_C(`3544187008`), // A2_vavghcr
1041	UINT64_C(`3544186976`), // A2_vavghr
1042	UINT64_C(`3544186880`), // A2_vavgub
1043	UINT64_C(`3544186912`), // A2_vavgubr
1044	UINT64_C(`3544187040`), // A2_vavguh
1045	UINT64_C(`3544187072`), // A2_vavguhr
1046	UINT64_C(`3546284128`), // A2_vavguw
1047	UINT64_C(`3546284160`), // A2_vavguwr
1048	UINT64_C(`3546284032`), // A2_vavgw
1049	UINT64_C(`3546284096`), // A2_vavgwcr
1050	UINT64_C(`3546284064`), // A2_vavgwr
1051	UINT64_C(`3523215552`), // A2_vcmpbeq
1052	UINT64_C(`3523215584`), // A2_vcmpbgtu
1053	UINT64_C(`3523215456`), // A2_vcmpheq
1054	UINT64_C(`3523215488`), // A2_vcmphgt
1055	UINT64_C(`3523215520`), // A2_vcmphgtu
1056	UINT64_C(`3523215360`), // A2_vcmpweq
1057	UINT64_C(`3523215392`), // A2_vcmpwgt
1058	UINT64_C(`3523215424`), // A2_vcmpwgtu
1059	UINT64_C(`2155872480`), // A2_vconj
1060	UINT64_C(`3552575680`), // A2_vmaxb
1061	UINT64_C(`3552575520`), // A2_vmaxh
1062	UINT64_C(`3552575488`), // A2_vmaxub
1063	UINT64_C(`3552575552`), // A2_vmaxuh
1064	UINT64_C(`3550478496`), // A2_vmaxuw
1065	UINT64_C(`3552575584`), // A2_vmaxw
1066	UINT64_C(`3552575712`), // A2_vminb
1067	UINT64_C(`3550478368`), // A2_vminh
1068	UINT64_C(`3550478336`), // A2_vminub
1069	UINT64_C(`3550478400`), // A2_vminuh
1070	UINT64_C(`3550478464`), // A2_vminuw
1071	UINT64_C(`3550478432`), // A2_vminw
1072	UINT64_C(`3548381184`), // A2_vnavgh
1073	UINT64_C(`3548381248`), // A2_vnavghcr
1074	UINT64_C(`3548381216`), // A2_vnavghr
1075	UINT64_C(`3548381280`), // A2_vnavgw
1076	UINT64_C(`3548381376`), // A2_vnavgwcr
1077	UINT64_C(`3548381312`), // A2_vnavgwr
1078	UINT64_C(`3896508448`), // A2_vraddub
1079	UINT64_C(`3930062880`), // A2_vraddub_acc
1080	UINT64_C(`3896508480`), // A2_vrsadub
1081	UINT64_C(`3930062912`), // A2_vrsadub_acc
1082	UINT64_C(`3542089792`), // A2_vsubh
1083	UINT64_C(`3542089824`), // A2_vsubhs
1084	UINT64_C(`3542089728`), // A2_vsubub
1085	UINT64_C(`3542089760`), // A2_vsububs
1086	UINT64_C(`3542089856`), // A2_vsubuhs
1087	UINT64_C(`3542089888`), // A2_vsubw
1088	UINT64_C(`3542089920`), // A2_vsubws
1089	UINT64_C(`4049600512`), // A2_xor
1090	UINT64_C(`3554672768`), // A2_xorp
1091	UINT64_C(`1891631104`), // A2_zxth
1092	UINT64_C(`3267362816`), // A4_addp_c
1093	UINT64_C(`4051697664`), // A4_andn
1094	UINT64_C(`3554672672`), // A4_andnp
1095	UINT64_C(`3558866944`), // A4_bitsplit
1096	UINT64_C(`2294284416`), // A4_bitspliti
1097	UINT64_C(`3523223712`), // A4_boundscheck_hi
1098	UINT64_C(`3523223680`), // A4_boundscheck_lo
1099	UINT64_C(`3351249088`), // A4_cmpbeq
1100	UINT64_C(`3707764736`), // A4_cmpbeqi
1101	UINT64_C(`3351248960`), // A4_cmpbgt
1102	UINT64_C(`3709861888`), // A4_cmpbgti
1103	UINT64_C(`3351249120`), // A4_cmpbgtu
1104	UINT64_C(`3711959040`), // A4_cmpbgtui
1105	UINT64_C(`3351248992`), // A4_cmpheq
1106	UINT64_C(`3707764744`), // A4_cmpheqi
1107	UINT64_C(`3351249024`), // A4_cmphgt
1108	UINT64_C(`3709861896`), // A4_cmphgti
1109	UINT64_C(`3351249056`), // A4_cmphgtu
1110	UINT64_C(`3711959048`), // A4_cmphgtui
1111	UINT64_C(`2088763392`), // A4_combineii
1112	UINT64_C(`1931485184`), // A4_combineir
1113	UINT64_C(`1929388032`), // A4_combineri
1114	UINT64_C(`2363490304`), // A4_cround_ri
1115	UINT64_C(`3334471680`), // A4_cround_rr
1116	UINT64_C(`0`), // A4_ext
1117	UINT64_C(`3554672864`), // A4_modwrapu
1118	UINT64_C(`4053794816`), // A4_orn
1119	UINT64_C(`3554672736`), // A4_ornp
1120	UINT64_C(`1879058432`), // A4_paslhf
1121	UINT64_C(`1879059456`), // A4_paslhfnew
1122	UINT64_C(`1879056384`), // A4_paslht
1123	UINT64_C(`1879057408`), // A4_paslhtnew
1124	UINT64_C(`1881155584`), // A4_pasrhf
1125	UINT64_C(`1881156608`), // A4_pasrhfnew
1126	UINT64_C(`1881153536`), // A4_pasrht
1127	UINT64_C(`1881154560`), // A4_pasrhtnew
1128	UINT64_C(`1889544192`), // A4_psxtbf
1129	UINT64_C(`1889545216`), // A4_psxtbfnew
1130	UINT64_C(`1889542144`), // A4_psxtbt
1131	UINT64_C(`1889543168`), // A4_psxtbtnew
1132	UINT64_C(`1893738496`), // A4_psxthf
1133	UINT64_C(`1893739520`), // A4_psxthfnew
1134	UINT64_C(`1893736448`), // A4_psxtht
1135	UINT64_C(`1893737472`), // A4_psxthtnew
1136	UINT64_C(`1887447040`), // A4_pzxtbf
1137	UINT64_C(`1887448064`), // A4_pzxtbfnew
1138	UINT64_C(`1887444992`), // A4_pzxtbt
1139	UINT64_C(`1887446016`), // A4_pzxtbtnew
1140	UINT64_C(`1891641344`), // A4_pzxthf
1141	UINT64_C(`1891642368`), // A4_pzxthfnew
1142	UINT64_C(`1891639296`), // A4_pzxtht
1143	UINT64_C(`1891640320`), // A4_pzxthtnew
1144	UINT64_C(`4081057792`), // A4_rcmpeq
1145	UINT64_C(`1933582336`), // A4_rcmpeqi
1146	UINT64_C(`4083154944`), // A4_rcmpneq
1147	UINT64_C(`1935679488`), // A4_rcmpneqi
1148	UINT64_C(`2363490432`), // A4_round_ri
1149	UINT64_C(`2363490496`), // A4_round_ri_sat
1150	UINT64_C(`3334471808`), // A4_round_rr
1151	UINT64_C(`3334471872`), // A4_round_rr_sat
1152	UINT64_C(`3269459968`), // A4_subp_c
1153	UINT64_C(`1744830464`), // A4_tfrcpp
1154	UINT64_C(`1663041536`), // A4_tfrpcp
1155	UINT64_C(`3523223648`), // A4_tlbmatch
1156	UINT64_C(`3523223552`), // A4_vcmpbeq_any
1157	UINT64_C(`3690987520`), // A4_vcmpbeqi
1158	UINT64_C(`3523223616`), // A4_vcmpbgt
1159	UINT64_C(`3693084672`), // A4_vcmpbgti
1160	UINT64_C(`3695181824`), // A4_vcmpbgtui
1161	UINT64_C(`3690987528`), // A4_vcmpheqi
1162	UINT64_C(`3693084680`), // A4_vcmphgti
1163	UINT64_C(`3695181832`), // A4_vcmphgtui
1164	UINT64_C(`3690987536`), // A4_vcmpweqi
1165	UINT64_C(`3693084688`), // A4_vcmpwgti
1166	UINT64_C(`3695181840`), // A4_vcmpwgtui
1167	UINT64_C(`3407872032`), // A4_vrmaxh
1168	UINT64_C(`3407880224`), // A4_vrmaxuh
1169	UINT64_C(`3407880256`), // A4_vrmaxuw
1170	UINT64_C(`3407872064`), // A4_vrmaxw
1171	UINT64_C(`3407872160`), // A4_vrminh
1172	UINT64_C(`3407880352`), // A4_vrminuh
1173	UINT64_C(`3407880384`), // A4_vrminuw
1174	UINT64_C(`3407872192`), // A4_vrminw
1175	UINT64_C(`3936354304`), // A5_ACS
1176	UINT64_C(`3242197024`), // A5_vaddhubs
1177	UINT64_C(`3523223584`), // A6_vcmpbeq_notany
1178	UINT64_C(`3940548608`), // A6_vminub_RdP
1179	UINT64_C(`2294284448`), // A7_clip
1180	UINT64_C(`2363490368`), // A7_croundd_ri
1181	UINT64_C(`3334471744`), // A7_croundd_rr
1182	UINT64_C(`2294284480`), // A7_vclip
1183	UINT64_C(`1805647872`), // C2_all8
1184	UINT64_C(`1795162112`), // C2_and
1185	UINT64_C(`1801453568`), // C2_andn
1186	UINT64_C(`1803550720`), // C2_any8
1187	UINT64_C(`3347054592`), // C2_bitsclr
1188	UINT64_C(`2239758336`), // C2_bitsclri
1189	UINT64_C(`3342860288`), // C2_bitsset
1190	UINT64_C(`4244635776`), // C2_ccombinewf
1191	UINT64_C(`4244643968`), // C2_ccombinewnewf
1192	UINT64_C(`4244643840`), // C2_ccombinewnewt
1193	UINT64_C(`4244635648`), // C2_ccombinewt
1194	UINT64_C(`2122317824`), // C2_cmoveif
1195	UINT64_C(`2113929216`), // C2_cmoveit
1196	UINT64_C(`2122326016`), // C2_cmovenewif
1197	UINT64_C(`2113937408`), // C2_cmovenewit
1198	UINT64_C(`4060086272`), // C2_cmpeq
1199	UINT64_C(`1962934272`), // C2_cmpeqi
1200	UINT64_C(`3531603968`), // C2_cmpeqp
1201	UINT64_C(`4064280576`), // C2_cmpgt
1202	UINT64_C(`1967128576`), // C2_cmpgti
1203	UINT64_C(`3531604032`), // C2_cmpgtp
1204	UINT64_C(`4066377728`), // C2_cmpgtu
1205	UINT64_C(`1971322880`), // C2_cmpgtui
1206	UINT64_C(`3531604096`), // C2_cmpgtup
1207	UINT64_C(`2248146944`), // C2_mask
1208	UINT64_C(`4093640704`), // C2_mux
1209	UINT64_C(`2046820352`), // C2_muxii
1210	UINT64_C(`1929379840`), // C2_muxir
1211	UINT64_C(`1937768448`), // C2_muxri
1212	UINT64_C(`1807745024`), // C2_not
1213	UINT64_C(`1797259264`), // C2_or
1214	UINT64_C(`1809842176`), // C2_orn
1215	UINT64_C(`2302672896`), // C2_tfrpr
1216	UINT64_C(`2235564032`), // C2_tfrrp
1217	UINT64_C(`2298478592`), // C2_vitpack
1218	UINT64_C(`3506438144`), // C2_vmux
1219	UINT64_C(`1799356416`), // C2_xor
1220	UINT64_C(`1783169024`), // C4_addipc
1221	UINT64_C(`1796210688`), // C4_and_and
1222	UINT64_C(`1804599296`), // C4_and_andn
1223	UINT64_C(`1798307840`), // C4_and_or
1224	UINT64_C(`1806696448`), // C4_and_orn
1225	UINT64_C(`4064280592`), // C4_cmplte
1226	UINT64_C(`1967128592`), // C4_cmpltei
1227	UINT64_C(`4066377744`), // C4_cmplteu
1228	UINT64_C(`1971322896`), // C4_cmplteui
1229	UINT64_C(`4060086288`), // C4_cmpneq
1230	UINT64_C(`1962934288`), // C4_cmpneqi
1231	UINT64_C(`1795170448`), // C4_fastcorner9
1232	UINT64_C(`1796219024`), // C4_fastcorner9_not
1233	UINT64_C(`3349151744`), // C4_nbitsclr
1234	UINT64_C(`2241855488`), // C4_nbitsclri
1235	UINT64_C(`3344957440`), // C4_nbitsset
1236	UINT64_C(`1800404992`), // C4_or_and
1237	UINT64_C(`1808793600`), // C4_or_andn
1238	UINT64_C(`1802502144`), // C4_or_or
1239	UINT64_C(`1810890752`), // C4_or_orn
1240	UINT64_C(`1509949440`), // CALLProfile
1241	UINT64_C(`0`), // CONST32
1242	UINT64_C(`0`), // CONST64
1243	UINT64_C(`0`), // DuplexIClass0
1244	UINT64_C(`8192`), // DuplexIClass1
1245	UINT64_C(`536870912`), // DuplexIClass2
1246	UINT64_C(`536879104`), // DuplexIClass3
1247	UINT64_C(`1073741824`), // DuplexIClass4
1248	UINT64_C(`1073750016`), // DuplexIClass5
1249	UINT64_C(`1610612736`), // DuplexIClass6
1250	UINT64_C(`1610620928`), // DuplexIClass7
1251	UINT64_C(`2147483648`), // DuplexIClass8
1252	UINT64_C(`2147491840`), // DuplexIClass9
1253	UINT64_C(`2684354560`), // DuplexIClassA
1254	UINT64_C(`2684362752`), // DuplexIClassB
1255	UINT64_C(`3221225472`), // DuplexIClassC
1256	UINT64_C(`3221233664`), // DuplexIClassD
1257	UINT64_C(`3758096384`), // DuplexIClassE
1258	UINT64_C(`3758104576`), // DuplexIClassF
1259	UINT64_C(`1384120320`), // EH_RETURN_JMPR
1260	UINT64_C(`2162163808`), // F2_conv_d2df
1261	UINT64_C(`2285895712`), // F2_conv_d2sf
1262	UINT64_C(`2162163712`), // F2_conv_df2d
1263	UINT64_C(`2162163904`), // F2_conv_df2d_chop
1264	UINT64_C(`2281701408`), // F2_conv_df2sf
1265	UINT64_C(`2162163744`), // F2_conv_df2ud
1266	UINT64_C(`2162163936`), // F2_conv_df2ud_chop
1267	UINT64_C(`2287992864`), // F2_conv_df2uw
1268	UINT64_C(`2292187168`), // F2_conv_df2uw_chop
1269	UINT64_C(`2290090016`), // F2_conv_df2w
1270	UINT64_C(`2296381472`), // F2_conv_df2w_chop
1271	UINT64_C(`2222981248`), // F2_conv_sf2d
1272	UINT64_C(`2222981312`), // F2_conv_sf2d_chop
1273	UINT64_C(`2222981120`), // F2_conv_sf2df
1274	UINT64_C(`2222981216`), // F2_conv_sf2ud
1275	UINT64_C(`2222981280`), // F2_conv_sf2ud_chop
1276	UINT64_C(`2338324480`), // F2_conv_sf2uw
1277	UINT64_C(`2338324512`), // F2_conv_sf2uw_chop
1278	UINT64_C(`2340421632`), // F2_conv_sf2w
1279	UINT64_C(`2340421664`), // F2_conv_sf2w_chop
1280	UINT64_C(`2162163776`), // F2_conv_ud2df
1281	UINT64_C(`2283798560`), // F2_conv_ud2sf
1282	UINT64_C(`2222981152`), // F2_conv_uw2df
1283	UINT64_C(`2334130176`), // F2_conv_uw2sf
1284	UINT64_C(`2222981184`), // F2_conv_w2df
1285	UINT64_C(`2336227328`), // F2_conv_w2sf
1286	UINT64_C(`3892314208`), // F2_dfadd
1287	UINT64_C(`3699376144`), // F2_dfclass
1288	UINT64_C(`3537895424`), // F2_dfcmpeq
1289	UINT64_C(`3537895488`), // F2_dfcmpge
1290	UINT64_C(`3537895456`), // F2_dfcmpgt
1291	UINT64_C(`3537895520`), // F2_dfcmpuo
1292	UINT64_C(`3644850176`), // F2_dfimm_n
1293	UINT64_C(`3640655872`), // F2_dfimm_p
1294	UINT64_C(`3894411360`), // F2_dfmax
1295	UINT64_C(`3904897120`), // F2_dfmin
1296	UINT64_C(`3896508512`), // F2_dfmpyfix
1297	UINT64_C(`3934257248`), // F2_dfmpyhh
1298	UINT64_C(`3925868640`), // F2_dfmpylh
1299	UINT64_C(`3902799968`), // F2_dfmpyll
1300	UINT64_C(`3900702816`), // F2_dfsub
1301	UINT64_C(`3942645760`), // F2_sfadd
1302	UINT64_C(`2246049792`), // F2_sfclass
1303	UINT64_C(`3353346144`), // F2_sfcmpeq
1304	UINT64_C(`3353346048`), // F2_sfcmpge
1305	UINT64_C(`3353346176`), // F2_sfcmpgt
1306	UINT64_C(`3353346080`), // F2_sfcmpuo
1307	UINT64_C(`3955228704`), // F2_sffixupd
1308	UINT64_C(`3955228672`), // F2_sffixupn
1309	UINT64_C(`2342518784`), // F2_sffixupr
1310	UINT64_C(`4009754752`), // F2_sffma
1311	UINT64_C(`4009754816`), // F2_sffma_lib
1312	UINT64_C(`4016046208`), // F2_sffma_sc
1313	UINT64_C(`4009754784`), // F2_sffms
1314	UINT64_C(`4009754848`), // F2_sffms_lib
1315	UINT64_C(`3594518528`), // F2_sfimm_n
1316	UINT64_C(`3590324224`), // F2_sfimm_p
1317	UINT64_C(`2346713088`), // F2_sfinvsqrta
1318	UINT64_C(`3951034368`), // F2_sfmax
1319	UINT64_C(`3951034400`), // F2_sfmin
1320	UINT64_C(`3946840064`), // F2_sfmpy
1321	UINT64_C(`3957325952`), // F2_sfrecipa
1322	UINT64_C(`3942645792`), // F2_sfsub
1323	UINT64_C(`1746927616`), // G4_tfrgcpp
1324	UINT64_C(`1780482048`), // G4_tfrgcrr
1325	UINT64_C(`1660944384`), // G4_tfrgpcp
1326	UINT64_C(`1644167168`), // G4_tfrgrcr
1327	UINT64_C(`35651584`), // HI
1328	UINT64_C(`1509949440`), // J2_call
1329	UINT64_C(`1562378240`), // J2_callf
1330	UINT64_C(`1352663040`), // J2_callr
1331	UINT64_C(`1361051648`), // J2_callrf
1332	UINT64_C(`1354760192`), // J2_callrh
1333	UINT64_C(`1358954496`), // J2_callrt
1334	UINT64_C(`1560281088`), // J2_callt
1335	UINT64_C(`1476395008`), // J2_jump
1336	UINT64_C(`1545601024`), // J2_jumpf
1337	UINT64_C(`1545603072`), // J2_jumpfnew
1338	UINT64_C(`1545607168`), // J2_jumpfnewpt
1339	UINT64_C(`1545605120`), // J2_jumpfpt
1340	UINT64_C(`1384120320`), // J2_jumpr
1341	UINT64_C(`1398800384`), // J2_jumprf
1342	UINT64_C(`1398802432`), // J2_jumprfnew
1343	UINT64_C(`1398806528`), // J2_jumprfnewpt
1344	UINT64_C(`1398804480`), // J2_jumprfpt
1345	UINT64_C(`1631584256`), // J2_jumprgtez
1346	UINT64_C(`1631588352`), // J2_jumprgtezpt
1347	UINT64_C(`1388314624`), // J2_jumprh
1348	UINT64_C(`1639972864`), // J2_jumprltez
1349	UINT64_C(`1639976960`), // J2_jumprltezpt
1350	UINT64_C(`1635778560`), // J2_jumprnz
1351	UINT64_C(`1635782656`), // J2_jumprnzpt
1352	UINT64_C(`1396703232`), // J2_jumprt
1353	UINT64_C(`1396705280`), // J2_jumprtnew
1354	UINT64_C(`1396709376`), // J2_jumprtnewpt
1355	UINT64_C(`1396707328`), // J2_jumprtpt
1356	UINT64_C(`1627389952`), // J2_jumprz
1357	UINT64_C(`1627394048`), // J2_jumprzpt
1358	UINT64_C(`1543503872`), // J2_jumpt
1359	UINT64_C(`1543505920`), // J2_jumptnew
1360	UINT64_C(`1543510016`), // J2_jumptnewpt
1361	UINT64_C(`1543507968`), // J2_jumptpt
1362	UINT64_C(`1761607680`), // J2_loop0i
1363	UINT64_C(`1761607680`), // J2_loop0iext
1364	UINT64_C(`1610612736`), // J2_loop0r
1365	UINT64_C(`1610612736`), // J2_loop0rext
1366	UINT64_C(`1763704832`), // J2_loop1i
1367	UINT64_C(`1763704832`), // J2_loop1iext
1368	UINT64_C(`1612709888`), // J2_loop1r
1369	UINT64_C(`1612709888`), // J2_loop1rext
1370	UINT64_C(`1413480448`), // J2_pause
1371	UINT64_C(`1772093440`), // J2_ploop1si
1372	UINT64_C(`1621098496`), // J2_ploop1sr
1373	UINT64_C(`1774190592`), // J2_ploop2si
1374	UINT64_C(`1623195648`), // J2_ploop2sr
1375	UINT64_C(`1776287744`), // J2_ploop3si
1376	UINT64_C(`1625292800`), // J2_ploop3sr
1377	UINT64_C(`1474297856`), // J2_rte
1378	UINT64_C(`1409286144`), // J2_trap0
1379	UINT64_C(`1417674752`), // J2_trap1
1380	UINT64_C(`1474301952`), // J2_unpause
1381	UINT64_C(`541065216`), // J4_cmpeq_f_jumpnv_nt
1382	UINT64_C(`541073408`), // J4_cmpeq_f_jumpnv_t
1383	UINT64_C(`339738624`), // J4_cmpeq_fp0_jump_nt
1384	UINT64_C(`339746816`), // J4_cmpeq_fp0_jump_t
1385	UINT64_C(`339742720`), // J4_cmpeq_fp1_jump_nt
1386	UINT64_C(`339750912`), // J4_cmpeq_fp1_jump_t
1387	UINT64_C(`536870912`), // J4_cmpeq_t_jumpnv_nt
1388	UINT64_C(`536879104`), // J4_cmpeq_t_jumpnv_t
1389	UINT64_C(`335544320`), // J4_cmpeq_tp0_jump_nt
1390	UINT64_C(`335552512`), // J4_cmpeq_tp0_jump_t
1391	UINT64_C(`335548416`), // J4_cmpeq_tp1_jump_nt
1392	UINT64_C(`335556608`), // J4_cmpeq_tp1_jump_t
1393	UINT64_C(`608174080`), // J4_cmpeqi_f_jumpnv_nt
1394	UINT64_C(`608182272`), // J4_cmpeqi_f_jumpnv_t
1395	UINT64_C(`272629760`), // J4_cmpeqi_fp0_jump_nt
1396	UINT64_C(`272637952`), // J4_cmpeqi_fp0_jump_t
1397	UINT64_C(`306184192`), // J4_cmpeqi_fp1_jump_nt
1398	UINT64_C(`306192384`), // J4_cmpeqi_fp1_jump_t
1399	UINT64_C(`603979776`), // J4_cmpeqi_t_jumpnv_nt
1400	UINT64_C(`603987968`), // J4_cmpeqi_t_jumpnv_t
1401	UINT64_C(`268435456`), // J4_cmpeqi_tp0_jump_nt
1402	UINT64_C(`268443648`), // J4_cmpeqi_tp0_jump_t
1403	UINT64_C(`301989888`), // J4_cmpeqi_tp1_jump_nt
1404	UINT64_C(`301998080`), // J4_cmpeqi_tp1_jump_t
1405	UINT64_C(`641728512`), // J4_cmpeqn1_f_jumpnv_nt
1406	UINT64_C(`641736704`), // J4_cmpeqn1_f_jumpnv_t
1407	UINT64_C(`297795584`), // J4_cmpeqn1_fp0_jump_nt
1408	UINT64_C(`297803776`), // J4_cmpeqn1_fp0_jump_t
1409	UINT64_C(`331350016`), // J4_cmpeqn1_fp1_jump_nt
1410	UINT64_C(`331358208`), // J4_cmpeqn1_fp1_jump_t
1411	UINT64_C(`637534208`), // J4_cmpeqn1_t_jumpnv_nt
1412	UINT64_C(`637542400`), // J4_cmpeqn1_t_jumpnv_t
1413	UINT64_C(`293601280`), // J4_cmpeqn1_tp0_jump_nt
1414	UINT64_C(`293609472`), // J4_cmpeqn1_tp0_jump_t
1415	UINT64_C(`327155712`), // J4_cmpeqn1_tp1_jump_nt
1416	UINT64_C(`327163904`), // J4_cmpeqn1_tp1_jump_t
1417	UINT64_C(`549453824`), // J4_cmpgt_f_jumpnv_nt
1418	UINT64_C(`549462016`), // J4_cmpgt_f_jumpnv_t
1419	UINT64_C(`348127232`), // J4_cmpgt_fp0_jump_nt
1420	UINT64_C(`348135424`), // J4_cmpgt_fp0_jump_t
1421	UINT64_C(`348131328`), // J4_cmpgt_fp1_jump_nt
1422	UINT64_C(`348139520`), // J4_cmpgt_fp1_jump_t
1423	UINT64_C(`545259520`), // J4_cmpgt_t_jumpnv_nt
1424	UINT64_C(`545267712`), // J4_cmpgt_t_jumpnv_t
1425	UINT64_C(`343932928`), // J4_cmpgt_tp0_jump_nt
1426	UINT64_C(`343941120`), // J4_cmpgt_tp0_jump_t
1427	UINT64_C(`343937024`), // J4_cmpgt_tp1_jump_nt
1428	UINT64_C(`343945216`), // J4_cmpgt_tp1_jump_t
1429	UINT64_C(`616562688`), // J4_cmpgti_f_jumpnv_nt
1430	UINT64_C(`616570880`), // J4_cmpgti_f_jumpnv_t
1431	UINT64_C(`281018368`), // J4_cmpgti_fp0_jump_nt
1432	UINT64_C(`281026560`), // J4_cmpgti_fp0_jump_t
1433	UINT64_C(`314572800`), // J4_cmpgti_fp1_jump_nt
1434	UINT64_C(`314580992`), // J4_cmpgti_fp1_jump_t
1435	UINT64_C(`612368384`), // J4_cmpgti_t_jumpnv_nt
1436	UINT64_C(`612376576`), // J4_cmpgti_t_jumpnv_t
1437	UINT64_C(`276824064`), // J4_cmpgti_tp0_jump_nt
1438	UINT64_C(`276832256`), // J4_cmpgti_tp0_jump_t
1439	UINT64_C(`310378496`), // J4_cmpgti_tp1_jump_nt
1440	UINT64_C(`310386688`), // J4_cmpgti_tp1_jump_t
1441	UINT64_C(`650117120`), // J4_cmpgtn1_f_jumpnv_nt
1442	UINT64_C(`650125312`), // J4_cmpgtn1_f_jumpnv_t
1443	UINT64_C(`297795840`), // J4_cmpgtn1_fp0_jump_nt
1444	UINT64_C(`297804032`), // J4_cmpgtn1_fp0_jump_t
1445	UINT64_C(`331350272`), // J4_cmpgtn1_fp1_jump_nt
1446	UINT64_C(`331358464`), // J4_cmpgtn1_fp1_jump_t
1447	UINT64_C(`645922816`), // J4_cmpgtn1_t_jumpnv_nt
1448	UINT64_C(`645931008`), // J4_cmpgtn1_t_jumpnv_t
1449	UINT64_C(`293601536`), // J4_cmpgtn1_tp0_jump_nt
1450	UINT64_C(`293609728`), // J4_cmpgtn1_tp0_jump_t
1451	UINT64_C(`327155968`), // J4_cmpgtn1_tp1_jump_nt
1452	UINT64_C(`327164160`), // J4_cmpgtn1_tp1_jump_t
1453	UINT64_C(`557842432`), // J4_cmpgtu_f_jumpnv_nt
1454	UINT64_C(`557850624`), // J4_cmpgtu_f_jumpnv_t
1455	UINT64_C(`356515840`), // J4_cmpgtu_fp0_jump_nt
1456	UINT64_C(`356524032`), // J4_cmpgtu_fp0_jump_t
1457	UINT64_C(`356519936`), // J4_cmpgtu_fp1_jump_nt
1458	UINT64_C(`356528128`), // J4_cmpgtu_fp1_jump_t
1459	UINT64_C(`553648128`), // J4_cmpgtu_t_jumpnv_nt
1460	UINT64_C(`553656320`), // J4_cmpgtu_t_jumpnv_t
1461	UINT64_C(`352321536`), // J4_cmpgtu_tp0_jump_nt
1462	UINT64_C(`352329728`), // J4_cmpgtu_tp0_jump_t
1463	UINT64_C(`352325632`), // J4_cmpgtu_tp1_jump_nt
1464	UINT64_C(`352333824`), // J4_cmpgtu_tp1_jump_t
1465	UINT64_C(`624951296`), // J4_cmpgtui_f_jumpnv_nt
1466	UINT64_C(`624959488`), // J4_cmpgtui_f_jumpnv_t
1467	UINT64_C(`289406976`), // J4_cmpgtui_fp0_jump_nt
1468	UINT64_C(`289415168`), // J4_cmpgtui_fp0_jump_t
1469	UINT64_C(`322961408`), // J4_cmpgtui_fp1_jump_nt
1470	UINT64_C(`322969600`), // J4_cmpgtui_fp1_jump_t
1471	UINT64_C(`620756992`), // J4_cmpgtui_t_jumpnv_nt
1472	UINT64_C(`620765184`), // J4_cmpgtui_t_jumpnv_t
1473	UINT64_C(`285212672`), // J4_cmpgtui_tp0_jump_nt
1474	UINT64_C(`285220864`), // J4_cmpgtui_tp0_jump_t
1475	UINT64_C(`318767104`), // J4_cmpgtui_tp1_jump_nt
1476	UINT64_C(`318775296`), // J4_cmpgtui_tp1_jump_t
1477	UINT64_C(`566231040`), // J4_cmplt_f_jumpnv_nt
1478	UINT64_C(`566239232`), // J4_cmplt_f_jumpnv_t
1479	UINT64_C(`562036736`), // J4_cmplt_t_jumpnv_nt
1480	UINT64_C(`562044928`), // J4_cmplt_t_jumpnv_t
1481	UINT64_C(`574619648`), // J4_cmpltu_f_jumpnv_nt
1482	UINT64_C(`574627840`), // J4_cmpltu_f_jumpnv_t
1483	UINT64_C(`570425344`), // J4_cmpltu_t_jumpnv_nt
1484	UINT64_C(`570433536`), // J4_cmpltu_t_jumpnv_t
1485	UINT64_C(`1386217472`), // J4_hintjumpr
1486	UINT64_C(`369098752`), // J4_jumpseti
1487	UINT64_C(`385875968`), // J4_jumpsetr
1488	UINT64_C(`633339904`), // J4_tstbit0_f_jumpnv_nt
1489	UINT64_C(`633348096`), // J4_tstbit0_f_jumpnv_t
1490	UINT64_C(`297796352`), // J4_tstbit0_fp0_jump_nt
1491	UINT64_C(`297804544`), // J4_tstbit0_fp0_jump_t
1492	UINT64_C(`331350784`), // J4_tstbit0_fp1_jump_nt
1493	UINT64_C(`331358976`), // J4_tstbit0_fp1_jump_t
1494	UINT64_C(`629145600`), // J4_tstbit0_t_jumpnv_nt
1495	UINT64_C(`629153792`), // J4_tstbit0_t_jumpnv_t
1496	UINT64_C(`293602048`), // J4_tstbit0_tp0_jump_nt
1497	UINT64_C(`293610240`), // J4_tstbit0_tp0_jump_t
1498	UINT64_C(`327156480`), // J4_tstbit0_tp1_jump_nt
1499	UINT64_C(`327164672`), // J4_tstbit0_tp1_jump_t
1500	UINT64_C(`2415919104`), // L2_deallocframe
1501	UINT64_C(`2424307712`), // L2_loadalignb_io
1502	UINT64_C(`2659188736`), // L2_loadalignb_pbr
1503	UINT64_C(`2558525440`), // L2_loadalignb_pci
1504	UINT64_C(`2558525952`), // L2_loadalignb_pcr
1505	UINT64_C(`2592079872`), // L2_loadalignb_pi
1506	UINT64_C(`2625634304`), // L2_loadalignb_pr
1507	UINT64_C(`2420113408`), // L2_loadalignh_io
1508	UINT64_C(`2654994432`), // L2_loadalignh_pbr
1509	UINT64_C(`2554331136`), // L2_loadalignh_pci
1510	UINT64_C(`2554331648`), // L2_loadalignh_pcr
1511	UINT64_C(`2587885568`), // L2_loadalignh_pi
1512	UINT64_C(`2621440000`), // L2_loadalignh_pr
1513	UINT64_C(`2418016256`), // L2_loadbsw2_io
1514	UINT64_C(`2652897280`), // L2_loadbsw2_pbr
1515	UINT64_C(`2552233984`), // L2_loadbsw2_pci
1516	UINT64_C(`2552234496`), // L2_loadbsw2_pcr
1517	UINT64_C(`2585788416`), // L2_loadbsw2_pi
1518	UINT64_C(`2619342848`), // L2_loadbsw2_pr
1519	UINT64_C(`2430599168`), // L2_loadbsw4_io
1520	UINT64_C(`2665480192`), // L2_loadbsw4_pbr
1521	UINT64_C(`2564816896`), // L2_loadbsw4_pci
1522	UINT64_C(`2564817408`), // L2_loadbsw4_pcr
1523	UINT64_C(`2598371328`), // L2_loadbsw4_pi
1524	UINT64_C(`2631925760`), // L2_loadbsw4_pr
1525	UINT64_C(`2422210560`), // L2_loadbzw2_io
1526	UINT64_C(`2657091584`), // L2_loadbzw2_pbr
1527	UINT64_C(`2556428288`), // L2_loadbzw2_pci
1528	UINT64_C(`2556428800`), // L2_loadbzw2_pcr
1529	UINT64_C(`2589982720`), // L2_loadbzw2_pi
1530	UINT64_C(`2623537152`), // L2_loadbzw2_pr
1531	UINT64_C(`2426404864`), // L2_loadbzw4_io
1532	UINT64_C(`2661285888`), // L2_loadbzw4_pbr
1533	UINT64_C(`2560622592`), // L2_loadbzw4_pci
1534	UINT64_C(`2560623104`), // L2_loadbzw4_pcr
1535	UINT64_C(`2594177024`), // L2_loadbzw4_pi
1536	UINT64_C(`2627731456`), // L2_loadbzw4_pr
1537	UINT64_C(`2432696320`), // L2_loadrb_io
1538	UINT64_C(`2667577344`), // L2_loadrb_pbr
1539	UINT64_C(`2566914048`), // L2_loadrb_pci
1540	UINT64_C(`2566914560`), // L2_loadrb_pcr
1541	UINT64_C(`2600468480`), // L2_loadrb_pi
1542	UINT64_C(`2634022912`), // L2_loadrb_pr
1543	UINT64_C(`1224736768`), // L2_loadrbgp
1544	UINT64_C(`2445279232`), // L2_loadrd_io
1545	UINT64_C(`2680160256`), // L2_loadrd_pbr
1546	UINT64_C(`2579496960`), // L2_loadrd_pci
1547	UINT64_C(`2579497472`), // L2_loadrd_pcr
1548	UINT64_C(`2613051392`), // L2_loadrd_pi
1549	UINT64_C(`2646605824`), // L2_loadrd_pr
1550	UINT64_C(`1237319680`), // L2_loadrdgp
1551	UINT64_C(`2436890624`), // L2_loadrh_io
1552	UINT64_C(`2671771648`), // L2_loadrh_pbr
1553	UINT64_C(`2571108352`), // L2_loadrh_pci
1554	UINT64_C(`2571108864`), // L2_loadrh_pcr
1555	UINT64_C(`2604662784`), // L2_loadrh_pi
1556	UINT64_C(`2638217216`), // L2_loadrh_pr
1557	UINT64_C(`1228931072`), // L2_loadrhgp
1558	UINT64_C(`2441084928`), // L2_loadri_io
1559	UINT64_C(`2675965952`), // L2_loadri_pbr
1560	UINT64_C(`2575302656`), // L2_loadri_pci
1561	UINT64_C(`2575303168`), // L2_loadri_pcr
1562	UINT64_C(`2608857088`), // L2_loadri_pi
1563	UINT64_C(`2642411520`), // L2_loadri_pr
1564	UINT64_C(`1233125376`), // L2_loadrigp
1565	UINT64_C(`2434793472`), // L2_loadrub_io
1566	UINT64_C(`2669674496`), // L2_loadrub_pbr
1567	UINT64_C(`2569011200`), // L2_loadrub_pci
1568	UINT64_C(`2569011712`), // L2_loadrub_pcr
1569	UINT64_C(`2602565632`), // L2_loadrub_pi
1570	UINT64_C(`2636120064`), // L2_loadrub_pr
1571	UINT64_C(`1226833920`), // L2_loadrubgp
1572	UINT64_C(`2438987776`), // L2_loadruh_io
1573	UINT64_C(`2673868800`), // L2_loadruh_pbr
1574	UINT64_C(`2573205504`), // L2_loadruh_pci
1575	UINT64_C(`2573206016`), // L2_loadruh_pcr
1576	UINT64_C(`2606759936`), // L2_loadruh_pi
1577	UINT64_C(`2640314368`), // L2_loadruh_pr
1578	UINT64_C(`1231028224`), // L2_loadruhgp
1579	UINT64_C(`2449475584`), // L2_loadw_aq
1580	UINT64_C(`2449473536`), // L2_loadw_locked
1581	UINT64_C(`1157627904`), // L2_ploadrbf_io
1582	UINT64_C(`2600478720`), // L2_ploadrbf_pi
1583	UINT64_C(`1191182336`), // L2_ploadrbfnew_io
1584	UINT64_C(`2600482816`), // L2_ploadrbfnew_pi
1585	UINT64_C(`1090519040`), // L2_ploadrbt_io
1586	UINT64_C(`2600476672`), // L2_ploadrbt_pi
1587	UINT64_C(`1124073472`), // L2_ploadrbtnew_io
1588	UINT64_C(`2600480768`), // L2_ploadrbtnew_pi
1589	UINT64_C(`1170210816`), // L2_ploadrdf_io
1590	UINT64_C(`2613061632`), // L2_ploadrdf_pi
1591	UINT64_C(`1203765248`), // L2_ploadrdfnew_io
1592	UINT64_C(`2613065728`), // L2_ploadrdfnew_pi
1593	UINT64_C(`1103101952`), // L2_ploadrdt_io
1594	UINT64_C(`2613059584`), // L2_ploadrdt_pi
1595	UINT64_C(`1136656384`), // L2_ploadrdtnew_io
1596	UINT64_C(`2613063680`), // L2_ploadrdtnew_pi
1597	UINT64_C(`1161822208`), // L2_ploadrhf_io
1598	UINT64_C(`2604673024`), // L2_ploadrhf_pi
1599	UINT64_C(`1195376640`), // L2_ploadrhfnew_io
1600	UINT64_C(`2604677120`), // L2_ploadrhfnew_pi
1601	UINT64_C(`1094713344`), // L2_ploadrht_io
1602	UINT64_C(`2604670976`), // L2_ploadrht_pi
1603	UINT64_C(`1128267776`), // L2_ploadrhtnew_io
1604	UINT64_C(`2604675072`), // L2_ploadrhtnew_pi
1605	UINT64_C(`1166016512`), // L2_ploadrif_io
1606	UINT64_C(`2608867328`), // L2_ploadrif_pi
1607	UINT64_C(`1199570944`), // L2_ploadrifnew_io
1608	UINT64_C(`2608871424`), // L2_ploadrifnew_pi
1609	UINT64_C(`1098907648`), // L2_ploadrit_io
1610	UINT64_C(`2608865280`), // L2_ploadrit_pi
1611	UINT64_C(`1132462080`), // L2_ploadritnew_io
1612	UINT64_C(`2608869376`), // L2_ploadritnew_pi
1613	UINT64_C(`1159725056`), // L2_ploadrubf_io
1614	UINT64_C(`2602575872`), // L2_ploadrubf_pi
1615	UINT64_C(`1193279488`), // L2_ploadrubfnew_io
1616	UINT64_C(`2602579968`), // L2_ploadrubfnew_pi
1617	UINT64_C(`1092616192`), // L2_ploadrubt_io
1618	UINT64_C(`2602573824`), // L2_ploadrubt_pi
1619	UINT64_C(`1126170624`), // L2_ploadrubtnew_io
1620	UINT64_C(`2602577920`), // L2_ploadrubtnew_pi
1621	UINT64_C(`1163919360`), // L2_ploadruhf_io
1622	UINT64_C(`2606770176`), // L2_ploadruhf_pi
1623	UINT64_C(`1197473792`), // L2_ploadruhfnew_io
1624	UINT64_C(`2606774272`), // L2_ploadruhfnew_pi
1625	UINT64_C(`1096810496`), // L2_ploadruht_io
1626	UINT64_C(`2606768128`), // L2_ploadruht_pi
1627	UINT64_C(`1130364928`), // L2_ploadruhtnew_io
1628	UINT64_C(`2606772224`), // L2_ploadruhtnew_pi
1629	UINT64_C(`1040187392`), // L4_add_memopb_io
1630	UINT64_C(`1042284544`), // L4_add_memoph_io
1631	UINT64_C(`1044381696`), // L4_add_memopw_io
1632	UINT64_C(`1040187456`), // L4_and_memopb_io
1633	UINT64_C(`1042284608`), // L4_and_memoph_io
1634	UINT64_C(`1044381760`), // L4_and_memopw_io
1635	UINT64_C(`1056964608`), // L4_iadd_memopb_io
1636	UINT64_C(`1059061760`), // L4_iadd_memoph_io
1637	UINT64_C(`1061158912`), // L4_iadd_memopw_io
1638	UINT64_C(`1056964672`), // L4_iand_memopb_io
1639	UINT64_C(`1059061824`), // L4_iand_memoph_io
1640	UINT64_C(`1061158976`), // L4_iand_memopw_io
1641	UINT64_C(`1056964704`), // L4_ior_memopb_io
1642	UINT64_C(`1059061856`), // L4_ior_memoph_io
1643	UINT64_C(`1061159008`), // L4_ior_memopw_io
1644	UINT64_C(`1056964640`), // L4_isub_memopb_io
1645	UINT64_C(`1059061792`), // L4_isub_memoph_io
1646	UINT64_C(`1061158944`), // L4_isub_memopw_io
1647	UINT64_C(`2592083968`), // L4_loadalignb_ap
1648	UINT64_C(`2625638400`), // L4_loadalignb_ur
1649	UINT64_C(`2587889664`), // L4_loadalignh_ap
1650	UINT64_C(`2621444096`), // L4_loadalignh_ur
1651	UINT64_C(`2585792512`), // L4_loadbsw2_ap
1652	UINT64_C(`2619346944`), // L4_loadbsw2_ur
1653	UINT64_C(`2598375424`), // L4_loadbsw4_ap
1654	UINT64_C(`2631929856`), // L4_loadbsw4_ur
1655	UINT64_C(`2589986816`), // L4_loadbzw2_ap
1656	UINT64_C(`2623541248`), // L4_loadbzw2_ur
1657	UINT64_C(`2594181120`), // L4_loadbzw4_ap
1658	UINT64_C(`2627735552`), // L4_loadbzw4_ur
1659	UINT64_C(`2449479680`), // L4_loadd_aq
1660	UINT64_C(`2449477632`), // L4_loadd_locked
1661	UINT64_C(`2600472576`), // L4_loadrb_ap
1662	UINT64_C(`973078528`), // L4_loadrb_rr
1663	UINT64_C(`2634027008`), // L4_loadrb_ur
1664	UINT64_C(`2613055488`), // L4_loadrd_ap
1665	UINT64_C(`985661440`), // L4_loadrd_rr
1666	UINT64_C(`2646609920`), // L4_loadrd_ur
1667	UINT64_C(`2604666880`), // L4_loadrh_ap
1668	UINT64_C(`977272832`), // L4_loadrh_rr
1669	UINT64_C(`2638221312`), // L4_loadrh_ur
1670	UINT64_C(`2608861184`), // L4_loadri_ap
1671	UINT64_C(`981467136`), // L4_loadri_rr
1672	UINT64_C(`2642415616`), // L4_loadri_ur
1673	UINT64_C(`2602569728`), // L4_loadrub_ap
1674	UINT64_C(`975175680`), // L4_loadrub_rr
1675	UINT64_C(`2636124160`), // L4_loadrub_ur
1676	UINT64_C(`2606764032`), // L4_loadruh_ap
1677	UINT64_C(`979369984`), // L4_loadruh_rr
1678	UINT64_C(`2640318464`), // L4_loadruh_ur
1679	UINT64_C(`2449481728`), // L4_loadw_phys
1680	UINT64_C(`1040187488`), // L4_or_memopb_io
1681	UINT64_C(`1042284640`), // L4_or_memoph_io
1682	UINT64_C(`1044381792`), // L4_or_memopw_io
1683	UINT64_C(`2667587712`), // L4_ploadrbf_abs
1684	UINT64_C(`822083584`), // L4_ploadrbf_rr
1685	UINT64_C(`2667591808`), // L4_ploadrbfnew_abs
1686	UINT64_C(`855638016`), // L4_ploadrbfnew_rr
1687	UINT64_C(`2667585664`), // L4_ploadrbt_abs
1688	UINT64_C(`805306368`), // L4_ploadrbt_rr
1689	UINT64_C(`2667589760`), // L4_ploadrbtnew_abs
1690	UINT64_C(`838860800`), // L4_ploadrbtnew_rr
1691	UINT64_C(`2680170624`), // L4_ploadrdf_abs
1692	UINT64_C(`834666496`), // L4_ploadrdf_rr
1693	UINT64_C(`2680174720`), // L4_ploadrdfnew_abs
1694	UINT64_C(`868220928`), // L4_ploadrdfnew_rr
1695	UINT64_C(`2680168576`), // L4_ploadrdt_abs
1696	UINT64_C(`817889280`), // L4_ploadrdt_rr
1697	UINT64_C(`2680172672`), // L4_ploadrdtnew_abs
1698	UINT64_C(`851443712`), // L4_ploadrdtnew_rr
1699	UINT64_C(`2671782016`), // L4_ploadrhf_abs
1700	UINT64_C(`826277888`), // L4_ploadrhf_rr
1701	UINT64_C(`2671786112`), // L4_ploadrhfnew_abs
1702	UINT64_C(`859832320`), // L4_ploadrhfnew_rr
1703	UINT64_C(`2671779968`), // L4_ploadrht_abs
1704	UINT64_C(`809500672`), // L4_ploadrht_rr
1705	UINT64_C(`2671784064`), // L4_ploadrhtnew_abs
1706	UINT64_C(`843055104`), // L4_ploadrhtnew_rr
1707	UINT64_C(`2675976320`), // L4_ploadrif_abs
1708	UINT64_C(`830472192`), // L4_ploadrif_rr
1709	UINT64_C(`2675980416`), // L4_ploadrifnew_abs
1710	UINT64_C(`864026624`), // L4_ploadrifnew_rr
1711	UINT64_C(`2675974272`), // L4_ploadrit_abs
1712	UINT64_C(`813694976`), // L4_ploadrit_rr
1713	UINT64_C(`2675978368`), // L4_ploadritnew_abs
1714	UINT64_C(`847249408`), // L4_ploadritnew_rr
1715	UINT64_C(`2669684864`), // L4_ploadrubf_abs
1716	UINT64_C(`824180736`), // L4_ploadrubf_rr
1717	UINT64_C(`2669688960`), // L4_ploadrubfnew_abs
1718	UINT64_C(`857735168`), // L4_ploadrubfnew_rr
1719	UINT64_C(`2669682816`), // L4_ploadrubt_abs
1720	UINT64_C(`807403520`), // L4_ploadrubt_rr
1721	UINT64_C(`2669686912`), // L4_ploadrubtnew_abs
1722	UINT64_C(`840957952`), // L4_ploadrubtnew_rr
1723	UINT64_C(`2673879168`), // L4_ploadruhf_abs
1724	UINT64_C(`828375040`), // L4_ploadruhf_rr
1725	UINT64_C(`2673883264`), // L4_ploadruhfnew_abs
1726	UINT64_C(`861929472`), // L4_ploadruhfnew_rr
1727	UINT64_C(`2673877120`), // L4_ploadruht_abs
1728	UINT64_C(`811597824`), // L4_ploadruht_rr
1729	UINT64_C(`2673881216`), // L4_ploadruhtnew_abs
1730	UINT64_C(`845152256`), // L4_ploadruhtnew_rr
1731	UINT64_C(`2516582400`), // L4_return
1732	UINT64_C(`2516594688`), // L4_return_f
1733	UINT64_C(`2516592640`), // L4_return_fnew_pnt
1734	UINT64_C(`2516596736`), // L4_return_fnew_pt
1735	UINT64_C(`2516586496`), // L4_return_t
1736	UINT64_C(`2516584448`), // L4_return_tnew_pnt
1737	UINT64_C(`2516588544`), // L4_return_tnew_pt
1738	UINT64_C(`1040187424`), // L4_sub_memopb_io
1739	UINT64_C(`1042284576`), // L4_sub_memoph_io
1740	UINT64_C(`1044381728`), // L4_sub_memopw_io
1741	UINT64_C(`2449473600`), // L6_memcpy
1742	UINT64_C(`18874368`), // LO
1743	UINT64_C(`4009754656`), // M2_acci
1744	UINT64_C(`3791650816`), // M2_accii
1745	UINT64_C(`3875536928`), // M2_cmaci_s0
1746	UINT64_C(`3875536960`), // M2_cmacr_s0
1747	UINT64_C(`3875537088`), // M2_cmacs_s0
1748	UINT64_C(`3883925696`), // M2_cmacs_s1
1749	UINT64_C(`3879731392`), // M2_cmacsc_s0
1750	UINT64_C(`3888120000`), // M2_cmacsc_s1
1751	UINT64_C(`3841982496`), // M2_cmpyi_s0
1752	UINT64_C(`3841982528`), // M2_cmpyr_s0
1753	UINT64_C(`3978297536`), // M2_cmpyrs_s0
1754	UINT64_C(`3986686144`), // M2_cmpyrs_s1
1755	UINT64_C(`3982491840`), // M2_cmpyrsc_s0
1756	UINT64_C(`3990880448`), // M2_cmpyrsc_s1
1757	UINT64_C(`3841982656`), // M2_cmpys_s0
1758	UINT64_C(`3850371264`), // M2_cmpys_s1
1759	UINT64_C(`3846176960`), // M2_cmpysc_s0
1760	UINT64_C(`3854565568`), // M2_cmpysc_s1
1761	UINT64_C(`3875537120`), // M2_cnacs_s0
1762	UINT64_C(`3883925728`), // M2_cnacs_s1
1763	UINT64_C(`3879731424`), // M2_cnacsc_s0
1764	UINT64_C(`3888120032`), // M2_cnacsc_s1
1765	UINT64_C(`3875536896`), // M2_dpmpyss_acc_s0
1766	UINT64_C(`3877634048`), // M2_dpmpyss_nac_s0
1767	UINT64_C(`3978297376`), // M2_dpmpyss_rnd_s0
1768	UINT64_C(`3841982464`), // M2_dpmpyss_s0
1769	UINT64_C(`3879731200`), // M2_dpmpyuu_acc_s0
1770	UINT64_C(`3881828352`), // M2_dpmpyuu_nac_s0
1771	UINT64_C(`3846176768`), // M2_dpmpyuu_s0
1772	UINT64_C(`3986686080`), // M2_hmmpyh_rs1
1773	UINT64_C(`3986685952`), // M2_hmmpyh_s1
1774	UINT64_C(`3990880384`), // M2_hmmpyl_rs1
1775	UINT64_C(`3986685984`), // M2_hmmpyl_s1
1776	UINT64_C(`4009754624`), // M2_maci
1777	UINT64_C(`3783262208`), // M2_macsin
1778	UINT64_C(`3774873600`), // M2_macsip
1779	UINT64_C(`3927965920`), // M2_mmachs_rs0
1780	UINT64_C(`3936354528`), // M2_mmachs_rs1
1781	UINT64_C(`3925868768`), // M2_mmachs_s0
1782	UINT64_C(`3934257376`), // M2_mmachs_s1
1783	UINT64_C(`3927965856`), // M2_mmacls_rs0
1784	UINT64_C(`3936354464`), // M2_mmacls_rs1
1785	UINT64_C(`3925868704`), // M2_mmacls_s0
1786	UINT64_C(`3934257312`), // M2_mmacls_s1
1787	UINT64_C(`3932160224`), // M2_mmacuhs_rs0
1788	UINT64_C(`3940548832`), // M2_mmacuhs_rs1
1789	UINT64_C(`3930063072`), // M2_mmacuhs_s0
1790	UINT64_C(`3938451680`), // M2_mmacuhs_s1
1791	UINT64_C(`3932160160`), // M2_mmaculs_rs0
1792	UINT64_C(`3940548768`), // M2_mmaculs_rs1
1793	UINT64_C(`3930063008`), // M2_mmaculs_s0
1794	UINT64_C(`3938451616`), // M2_mmaculs_s1
1795	UINT64_C(`3894411488`), // M2_mmpyh_rs0
1796	UINT64_C(`3902800096`), // M2_mmpyh_rs1
1797	UINT64_C(`3892314336`), // M2_mmpyh_s0
1798	UINT64_C(`3900702944`), // M2_mmpyh_s1
1799	UINT64_C(`3894411424`), // M2_mmpyl_rs0
1800	UINT64_C(`3902800032`), // M2_mmpyl_rs1
1801	UINT64_C(`3892314272`), // M2_mmpyl_s0
1802	UINT64_C(`3900702880`), // M2_mmpyl_s1
1803	UINT64_C(`3898605792`), // M2_mmpyuh_rs0
1804	UINT64_C(`3906994400`), // M2_mmpyuh_rs1
1805	UINT64_C(`3896508640`), // M2_mmpyuh_s0
1806	UINT64_C(`3904897248`), // M2_mmpyuh_s1
1807	UINT64_C(`3898605728`), // M2_mmpyul_rs0
1808	UINT64_C(`3906994336`), // M2_mmpyul_rs1
1809	UINT64_C(`3896508576`), // M2_mmpyul_s0
1810	UINT64_C(`3904897184`), // M2_mmpyul_s1
1811	UINT64_C(`4018143232`), // M2_mnaci
1812	UINT64_C(`3992977504`), // M2_mpy_acc_hh_s0
1813	UINT64_C(`4001366112`), // M2_mpy_acc_hh_s1
1814	UINT64_C(`3992977472`), // M2_mpy_acc_hl_s0
1815	UINT64_C(`4001366080`), // M2_mpy_acc_hl_s1
1816	UINT64_C(`3992977440`), // M2_mpy_acc_lh_s0
1817	UINT64_C(`4001366048`), // M2_mpy_acc_lh_s1
1818	UINT64_C(`3992977408`), // M2_mpy_acc_ll_s0
1819	UINT64_C(`4001366016`), // M2_mpy_acc_ll_s1
1820	UINT64_C(`3992977632`), // M2_mpy_acc_sat_hh_s0
1821	UINT64_C(`4001366240`), // M2_mpy_acc_sat_hh_s1
1822	UINT64_C(`3992977600`), // M2_mpy_acc_sat_hl_s0
1823	UINT64_C(`4001366208`), // M2_mpy_acc_sat_hl_s1
1824	UINT64_C(`3992977568`), // M2_mpy_acc_sat_lh_s0
1825	UINT64_C(`4001366176`), // M2_mpy_acc_sat_lh_s1
1826	UINT64_C(`3992977536`), // M2_mpy_acc_sat_ll_s0
1827	UINT64_C(`4001366144`), // M2_mpy_acc_sat_ll_s1
1828	UINT64_C(`3959423072`), // M2_mpy_hh_s0
1829	UINT64_C(`3967811680`), // M2_mpy_hh_s1
1830	UINT64_C(`3959423040`), // M2_mpy_hl_s0
1831	UINT64_C(`3967811648`), // M2_mpy_hl_s1
1832	UINT64_C(`3959423008`), // M2_mpy_lh_s0
1833	UINT64_C(`3967811616`), // M2_mpy_lh_s1
1834	UINT64_C(`3959422976`), // M2_mpy_ll_s0
1835	UINT64_C(`3967811584`), // M2_mpy_ll_s1
1836	UINT64_C(`3995074656`), // M2_mpy_nac_hh_s0
1837	UINT64_C(`4003463264`), // M2_mpy_nac_hh_s1
1838	UINT64_C(`3995074624`), // M2_mpy_nac_hl_s0
1839	UINT64_C(`4003463232`), // M2_mpy_nac_hl_s1
1840	UINT64_C(`3995074592`), // M2_mpy_nac_lh_s0
1841	UINT64_C(`4003463200`), // M2_mpy_nac_lh_s1
1842	UINT64_C(`3995074560`), // M2_mpy_nac_ll_s0
1843	UINT64_C(`4003463168`), // M2_mpy_nac_ll_s1
1844	UINT64_C(`3995074784`), // M2_mpy_nac_sat_hh_s0
1845	UINT64_C(`4003463392`), // M2_mpy_nac_sat_hh_s1
1846	UINT64_C(`3995074752`), // M2_mpy_nac_sat_hl_s0
1847	UINT64_C(`4003463360`), // M2_mpy_nac_sat_hl_s1
1848	UINT64_C(`3995074720`), // M2_mpy_nac_sat_lh_s0
1849	UINT64_C(`4003463328`), // M2_mpy_nac_sat_lh_s1
1850	UINT64_C(`3995074688`), // M2_mpy_nac_sat_ll_s0
1851	UINT64_C(`4003463296`), // M2_mpy_nac_sat_ll_s1
1852	UINT64_C(`3961520224`), // M2_mpy_rnd_hh_s0
1853	UINT64_C(`3969908832`), // M2_mpy_rnd_hh_s1
1854	UINT64_C(`3961520192`), // M2_mpy_rnd_hl_s0
1855	UINT64_C(`3969908800`), // M2_mpy_rnd_hl_s1
1856	UINT64_C(`3961520160`), // M2_mpy_rnd_lh_s0
1857	UINT64_C(`3969908768`), // M2_mpy_rnd_lh_s1
1858	UINT64_C(`3961520128`), // M2_mpy_rnd_ll_s0
1859	UINT64_C(`3969908736`), // M2_mpy_rnd_ll_s1
1860	UINT64_C(`3959423200`), // M2_mpy_sat_hh_s0
1861	UINT64_C(`3967811808`), // M2_mpy_sat_hh_s1
1862	UINT64_C(`3959423168`), // M2_mpy_sat_hl_s0
1863	UINT64_C(`3967811776`), // M2_mpy_sat_hl_s1
1864	UINT64_C(`3959423136`), // M2_mpy_sat_lh_s0
1865	UINT64_C(`3967811744`), // M2_mpy_sat_lh_s1
1866	UINT64_C(`3959423104`), // M2_mpy_sat_ll_s0
1867	UINT64_C(`3967811712`), // M2_mpy_sat_ll_s1
1868	UINT64_C(`3961520352`), // M2_mpy_sat_rnd_hh_s0
1869	UINT64_C(`3969908960`), // M2_mpy_sat_rnd_hh_s1
1870	UINT64_C(`3961520320`), // M2_mpy_sat_rnd_hl_s0
1871	UINT64_C(`3969908928`), // M2_mpy_sat_rnd_hl_s1
1872	UINT64_C(`3961520288`), // M2_mpy_sat_rnd_lh_s0
1873	UINT64_C(`3969908896`), // M2_mpy_sat_rnd_lh_s1
1874	UINT64_C(`3961520256`), // M2_mpy_sat_rnd_ll_s0
1875	UINT64_C(`3969908864`), // M2_mpy_sat_rnd_ll_s1
1876	UINT64_C(`3976200224`), // M2_mpy_up
1877	UINT64_C(`3986686016`), // M2_mpy_up_s1
1878	UINT64_C(`3990880256`), // M2_mpy_up_s1_sat
1879	UINT64_C(`3858759776`), // M2_mpyd_acc_hh_s0
1880	UINT64_C(`3867148384`), // M2_mpyd_acc_hh_s1
1881	UINT64_C(`3858759744`), // M2_mpyd_acc_hl_s0
1882	UINT64_C(`3867148352`), // M2_mpyd_acc_hl_s1
1883	UINT64_C(`3858759712`), // M2_mpyd_acc_lh_s0
1884	UINT64_C(`3867148320`), // M2_mpyd_acc_lh_s1
1885	UINT64_C(`3858759680`), // M2_mpyd_acc_ll_s0
1886	UINT64_C(`3867148288`), // M2_mpyd_acc_ll_s1
1887	UINT64_C(`3825205344`), // M2_mpyd_hh_s0
1888	UINT64_C(`3833593952`), // M2_mpyd_hh_s1
1889	UINT64_C(`3825205312`), // M2_mpyd_hl_s0
1890	UINT64_C(`3833593920`), // M2_mpyd_hl_s1
1891	UINT64_C(`3825205280`), // M2_mpyd_lh_s0
1892	UINT64_C(`3833593888`), // M2_mpyd_lh_s1
1893	UINT64_C(`3825205248`), // M2_mpyd_ll_s0
1894	UINT64_C(`3833593856`), // M2_mpyd_ll_s1
1895	UINT64_C(`3860856928`), // M2_mpyd_nac_hh_s0
1896	UINT64_C(`3869245536`), // M2_mpyd_nac_hh_s1
1897	UINT64_C(`3860856896`), // M2_mpyd_nac_hl_s0
1898	UINT64_C(`3869245504`), // M2_mpyd_nac_hl_s1
1899	UINT64_C(`3860856864`), // M2_mpyd_nac_lh_s0
1900	UINT64_C(`3869245472`), // M2_mpyd_nac_lh_s1
1901	UINT64_C(`3860856832`), // M2_mpyd_nac_ll_s0
1902	UINT64_C(`3869245440`), // M2_mpyd_nac_ll_s1
1903	UINT64_C(`3827302496`), // M2_mpyd_rnd_hh_s0
1904	UINT64_C(`3835691104`), // M2_mpyd_rnd_hh_s1
1905	UINT64_C(`3827302464`), // M2_mpyd_rnd_hl_s0
1906	UINT64_C(`3835691072`), // M2_mpyd_rnd_hl_s1
1907	UINT64_C(`3827302432`), // M2_mpyd_rnd_lh_s0
1908	UINT64_C(`3835691040`), // M2_mpyd_rnd_lh_s1
1909	UINT64_C(`3827302400`), // M2_mpyd_rnd_ll_s0
1910	UINT64_C(`3835691008`), // M2_mpyd_rnd_ll_s1
1911	UINT64_C(`3976200192`), // M2_mpyi
1912	UINT64_C(`3766484992`), // M2_mpysin
1913	UINT64_C(`3758096384`), // M2_mpysip
1914	UINT64_C(`3982491680`), // M2_mpysu_up
1915	UINT64_C(`3997171808`), // M2_mpyu_acc_hh_s0
1916	UINT64_C(`4005560416`), // M2_mpyu_acc_hh_s1
1917	UINT64_C(`3997171776`), // M2_mpyu_acc_hl_s0
1918	UINT64_C(`4005560384`), // M2_mpyu_acc_hl_s1
1919	UINT64_C(`3997171744`), // M2_mpyu_acc_lh_s0
1920	UINT64_C(`4005560352`), // M2_mpyu_acc_lh_s1
1921	UINT64_C(`3997171712`), // M2_mpyu_acc_ll_s0
1922	UINT64_C(`4005560320`), // M2_mpyu_acc_ll_s1
1923	UINT64_C(`3963617376`), // M2_mpyu_hh_s0
1924	UINT64_C(`3972005984`), // M2_mpyu_hh_s1
1925	UINT64_C(`3963617344`), // M2_mpyu_hl_s0
1926	UINT64_C(`3972005952`), // M2_mpyu_hl_s1
1927	UINT64_C(`3963617312`), // M2_mpyu_lh_s0
1928	UINT64_C(`3972005920`), // M2_mpyu_lh_s1
1929	UINT64_C(`3963617280`), // M2_mpyu_ll_s0
1930	UINT64_C(`3972005888`), // M2_mpyu_ll_s1
1931	UINT64_C(`3999268960`), // M2_mpyu_nac_hh_s0
1932	UINT64_C(`4007657568`), // M2_mpyu_nac_hh_s1
1933	UINT64_C(`3999268928`), // M2_mpyu_nac_hl_s0
1934	UINT64_C(`4007657536`), // M2_mpyu_nac_hl_s1
1935	UINT64_C(`3999268896`), // M2_mpyu_nac_lh_s0
1936	UINT64_C(`4007657504`), // M2_mpyu_nac_lh_s1
1937	UINT64_C(`3999268864`), // M2_mpyu_nac_ll_s0
1938	UINT64_C(`4007657472`), // M2_mpyu_nac_ll_s1
1939	UINT64_C(`3980394528`), // M2_mpyu_up
1940	UINT64_C(`3862954080`), // M2_mpyud_acc_hh_s0
1941	UINT64_C(`3871342688`), // M2_mpyud_acc_hh_s1
1942	UINT64_C(`3862954048`), // M2_mpyud_acc_hl_s0
1943	UINT64_C(`3871342656`), // M2_mpyud_acc_hl_s1
1944	UINT64_C(`3862954016`), // M2_mpyud_acc_lh_s0
1945	UINT64_C(`3871342624`), // M2_mpyud_acc_lh_s1
1946	UINT64_C(`3862953984`), // M2_mpyud_acc_ll_s0
1947	UINT64_C(`3871342592`), // M2_mpyud_acc_ll_s1
1948	UINT64_C(`3829399648`), // M2_mpyud_hh_s0
1949	UINT64_C(`3837788256`), // M2_mpyud_hh_s1
1950	UINT64_C(`3829399616`), // M2_mpyud_hl_s0
1951	UINT64_C(`3837788224`), // M2_mpyud_hl_s1
1952	UINT64_C(`3829399584`), // M2_mpyud_lh_s0
1953	UINT64_C(`3837788192`), // M2_mpyud_lh_s1
1954	UINT64_C(`3829399552`), // M2_mpyud_ll_s0
1955	UINT64_C(`3837788160`), // M2_mpyud_ll_s1
1956	UINT64_C(`3865051232`), // M2_mpyud_nac_hh_s0
1957	UINT64_C(`3873439840`), // M2_mpyud_nac_hh_s1
1958	UINT64_C(`3865051200`), // M2_mpyud_nac_hl_s0
1959	UINT64_C(`3873439808`), // M2_mpyud_nac_hl_s1
1960	UINT64_C(`3865051168`), // M2_mpyud_nac_lh_s0
1961	UINT64_C(`3873439776`), // M2_mpyud_nac_lh_s1
1962	UINT64_C(`3865051136`), // M2_mpyud_nac_ll_s0
1963	UINT64_C(`3873439744`), // M2_mpyud_nac_ll_s1
1964	UINT64_C(`4018143264`), // M2_nacci
1965	UINT64_C(`3800039424`), // M2_naccii
1966	UINT64_C(`4009754720`), // M2_subacc
1967	UINT64_C(`3898605568`), // M2_vabsdiffh
1968	UINT64_C(`3894411264`), // M2_vabsdiffw
1969	UINT64_C(`3930062976`), // M2_vcmac_s0_sat_i
1970	UINT64_C(`3927965824`), // M2_vcmac_s0_sat_r
1971	UINT64_C(`3896508608`), // M2_vcmpy_s0_sat_i
1972	UINT64_C(`3894411456`), // M2_vcmpy_s0_sat_r
1973	UINT64_C(`3904897216`), // M2_vcmpy_s1_sat_i
1974	UINT64_C(`3902800064`), // M2_vcmpy_s1_sat_r
1975	UINT64_C(`3925868672`), // M2_vdmacs_s0
1976	UINT64_C(`3934257280`), // M2_vdmacs_s1
1977	UINT64_C(`3909091328`), // M2_vdmpyrs_s0
1978	UINT64_C(`3917479936`), // M2_vdmpyrs_s1
1979	UINT64_C(`3892314240`), // M2_vdmpys_s0
1980	UINT64_C(`3900702848`), // M2_vdmpys_s1
1981	UINT64_C(`3877634080`), // M2_vmac2
1982	UINT64_C(`3927965760`), // M2_vmac2es
1983	UINT64_C(`3925868736`), // M2_vmac2es_s0
1984	UINT64_C(`3934257344`), // M2_vmac2es_s1
1985	UINT64_C(`3875537056`), // M2_vmac2s_s0
1986	UINT64_C(`3883925664`), // M2_vmac2s_s1
1987	UINT64_C(`3881828512`), // M2_vmac2su_s0
1988	UINT64_C(`3890217120`), // M2_vmac2su_s1
1989	UINT64_C(`3892314304`), // M2_vmpy2es_s0
1990	UINT64_C(`3900702912`), // M2_vmpy2es_s1
1991	UINT64_C(`3841982624`), // M2_vmpy2s_s0
1992	UINT64_C(`3978297568`), // M2_vmpy2s_s0pack
1993	UINT64_C(`3850371232`), // M2_vmpy2s_s1
1994	UINT64_C(`3986686176`), // M2_vmpy2s_s1pack
1995	UINT64_C(`3841982688`), // M2_vmpy2su_s0
1996	UINT64_C(`3850371296`), // M2_vmpy2su_s1
1997	UINT64_C(`3911188704`), // M2_vraddh
1998	UINT64_C(`3909091360`), // M2_vradduh
1999	UINT64_C(`3925868544`), // M2_vrcmaci_s0
2000	UINT64_C(`3930062848`), // M2_vrcmaci_s0c
2001	UINT64_C(`3925868576`), // M2_vrcmacr_s0
2002	UINT64_C(`3932160032`), // M2_vrcmacr_s0c
2003	UINT64_C(`3892314112`), // M2_vrcmpyi_s0
2004	UINT64_C(`3896508416`), // M2_vrcmpyi_s0c
2005	UINT64_C(`3892314144`), // M2_vrcmpyr_s0
2006	UINT64_C(`3898605600`), // M2_vrcmpyr_s0c
2007	UINT64_C(`3936354432`), // M2_vrcmpys_acc_s1_h
2008	UINT64_C(`3940548736`), // M2_vrcmpys_acc_s1_l
2009	UINT64_C(`3902800000`), // M2_vrcmpys_s1_h
2010	UINT64_C(`3906994304`), // M2_vrcmpys_s1_l
2011	UINT64_C(`3919577280`), // M2_vrcmpys_s1rp_h
2012	UINT64_C(`3919577312`), // M2_vrcmpys_s1rp_l
2013	UINT64_C(`3925868608`), // M2_vrmac_s0
2014	UINT64_C(`3892314176`), // M2_vrmpy_s0
2015	UINT64_C(`4018143328`), // M2_xor_xacc
2016	UINT64_C(`4013948928`), // M4_and_and
2017	UINT64_C(`4011851808`), // M4_and_andn
2018	UINT64_C(`4013948960`), // M4_and_or
2019	UINT64_C(`4013948992`), // M4_and_xor
2020	UINT64_C(`3305111680`), // M4_cmpyi_wh
2021	UINT64_C(`3305111712`), // M4_cmpyi_whc
2022	UINT64_C(`3305111744`), // M4_cmpyr_wh
2023	UINT64_C(`3305111776`), // M4_cmpyr_whc
2024	UINT64_C(`4016046080`), // M4_mac_up_s1_sat
2025	UINT64_C(`3623878656`), // M4_mpyri_addi
2026	UINT64_C(`3749707776`), // M4_mpyri_addr
2027	UINT64_C(`3741319168`), // M4_mpyri_addr_u2
2028	UINT64_C(`3607101440`), // M4_mpyrr_addi
2029	UINT64_C(`3808428032`), // M4_mpyrr_addr
2030	UINT64_C(`4016046112`), // M4_nac_up_s1_sat
2031	UINT64_C(`4013949024`), // M4_or_and
2032	UINT64_C(`4011851776`), // M4_or_andn
2033	UINT64_C(`4022337536`), // M4_or_or
2034	UINT64_C(`4022337568`), // M4_or_xor
2035	UINT64_C(`3846176992`), // M4_pmpyw
2036	UINT64_C(`3877634272`), // M4_pmpyw_acc
2037	UINT64_C(`3854565600`), // M4_vpmpyh
2038	UINT64_C(`3886022880`), // M4_vpmpyh_acc
2039	UINT64_C(`3927965888`), // M4_vrmpyeh_acc_s0
2040	UINT64_C(`3936354496`), // M4_vrmpyeh_acc_s1
2041	UINT64_C(`3896508544`), // M4_vrmpyeh_s0
2042	UINT64_C(`3904897152`), // M4_vrmpyeh_s1
2043	UINT64_C(`3932160192`), // M4_vrmpyoh_acc_s0
2044	UINT64_C(`3940548800`), // M4_vrmpyoh_acc_s1
2045	UINT64_C(`3894411328`), // M4_vrmpyoh_s0
2046	UINT64_C(`3902799936`), // M4_vrmpyoh_s1
2047	UINT64_C(`4022337600`), // M4_xor_and
2048	UINT64_C(`4011851840`), // M4_xor_andn
2049	UINT64_C(`4022337632`), // M4_xor_or
2050	UINT64_C(`3397386240`), // M4_xor_xacc
2051	UINT64_C(`3927965728`), // M5_vdmacbsu
2052	UINT64_C(`3902799904`), // M5_vdmpybsu
2053	UINT64_C(`3888119840`), // M5_vmacbsu
2054	UINT64_C(`3883925536`), // M5_vmacbuu
2055	UINT64_C(`3846176800`), // M5_vmpybsu
2056	UINT64_C(`3850371104`), // M5_vmpybuu
2057	UINT64_C(`3938451488`), // M5_vrmacbsu
2058	UINT64_C(`3934257184`), // M5_vrmacbuu
2059	UINT64_C(`3904897056`), // M5_vrmpybsu
2060	UINT64_C(`3900702752`), // M5_vrmpybuu
2061	UINT64_C(`3906994176`), // M6_vabsdiffb
2062	UINT64_C(`3902799872`), // M6_vabsdiffub
2063	UINT64_C(`3898605632`), // M7_dcmpyiw
2064	UINT64_C(`3932160064`), // M7_dcmpyiw_acc
2065	UINT64_C(`3906994240`), // M7_dcmpyiwc
2066	UINT64_C(`3930063040`), // M7_dcmpyiwc_acc
2067	UINT64_C(`3900702784`), // M7_dcmpyrw
2068	UINT64_C(`3934257216`), // M7_dcmpyrw_acc
2069	UINT64_C(`3904897088`), // M7_dcmpyrwc
2070	UINT64_C(`3938451520`), // M7_dcmpyrwc_acc
2071	UINT64_C(`3911188480`), // M7_wcmpyiw
2072	UINT64_C(`3919577088`), // M7_wcmpyiw_rnd
2073	UINT64_C(`3909091456`), // M7_wcmpyiwc
2074	UINT64_C(`3917480064`), // M7_wcmpyiwc_rnd
2075	UINT64_C(`3913285632`), // M7_wcmpyrw
2076	UINT64_C(`3921674240`), // M7_wcmpyrw_rnd
2077	UINT64_C(`3915382784`), // M7_wcmpyrwc
2078	UINT64_C(`3923771392`), // M7_wcmpyrwc_rnd
2079	UINT64_C(`1509949440`), // PS_call_stk
2080	UINT64_C(`1352663040`), // PS_callr_nr
2081	UINT64_C(`1384120320`), // PS_jmpret
2082	UINT64_C(`1398800384`), // PS_jmpretf
2083	UINT64_C(`1398802432`), // PS_jmpretfnew
2084	UINT64_C(`1398806528`), // PS_jmpretfnewpt
2085	UINT64_C(`1396703232`), // PS_jmprett
2086	UINT64_C(`1396705280`), // PS_jmprettnew
2087	UINT64_C(`1396709376`), // PS_jmprettnewpt
2088	UINT64_C(`1224736768`), // PS_loadrbabs
2089	UINT64_C(`1237319680`), // PS_loadrdabs
2090	UINT64_C(`1228931072`), // PS_loadrhabs
2091	UINT64_C(`1233125376`), // PS_loadriabs
2092	UINT64_C(`1226833920`), // PS_loadrubabs
2093	UINT64_C(`1231028224`), // PS_loadruhabs
2094	UINT64_C(`1207959552`), // PS_storerbabs
2095	UINT64_C(`1218445312`), // PS_storerbnewabs
2096	UINT64_C(`1220542464`), // PS_storerdabs
2097	UINT64_C(`1214251008`), // PS_storerfabs
2098	UINT64_C(`1212153856`), // PS_storerhabs
2099	UINT64_C(`1218447360`), // PS_storerhnewabs
2100	UINT64_C(`1216348160`), // PS_storeriabs
2101	UINT64_C(`1218449408`), // PS_storerinewabs
2102	UINT64_C(`1417674752`), // PS_trap1
2103	UINT64_C(`2699034636`), // R6_release_at_vi
2104	UINT64_C(`2699034668`), // R6_release_st_vi
2105	UINT64_C(`1509949440`), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4
2106	UINT64_C(`1509949440`), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT
2107	UINT64_C(`1509949440`), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
2108	UINT64_C(`1509949440`), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
2109	UINT64_C(`1476395008`), // RESTORE_DEALLOC_RET_JMP_V4
2110	UINT64_C(`1476395008`), // RESTORE_DEALLOC_RET_JMP_V4_EXT
2111	UINT64_C(`1476395008`), // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
2112	UINT64_C(`1476395008`), // RESTORE_DEALLOC_RET_JMP_V4_PIC
2113	UINT64_C(`3288334336`), // S2_addasl_rrri
2114	UINT64_C(`2692743168`), // S2_allocframe
2115	UINT64_C(`2147483712`), // S2_asl_i_p
2116	UINT64_C(`2181038272`), // S2_asl_i_p_acc
2117	UINT64_C(`2185232448`), // S2_asl_i_p_and
2118	UINT64_C(`2181038144`), // S2_asl_i_p_nac
2119	UINT64_C(`2185232576`), // S2_asl_i_p_or
2120	UINT64_C(`2189426752`), // S2_asl_i_p_xacc
2121	UINT64_C(`2348810304`), // S2_asl_i_r
2122	UINT64_C(`2382364864`), // S2_asl_i_r_acc
2123	UINT64_C(`2386559040`), // S2_asl_i_r_and
2124	UINT64_C(`2382364736`), // S2_asl_i_r_nac
2125	UINT64_C(`2386559168`), // S2_asl_i_r_or
2126	UINT64_C(`2353004608`), // S2_asl_i_r_sat
2127	UINT64_C(`2390753344`), // S2_asl_i_r_xacc
2128	UINT64_C(`2155872320`), // S2_asl_i_vh
2129	UINT64_C(`2151678016`), // S2_asl_i_vw
2130	UINT64_C(`3279945856`), // S2_asl_r_p
2131	UINT64_C(`3418357888`), // S2_asl_r_p_acc
2132	UINT64_C(`3409969280`), // S2_asl_r_p_and
2133	UINT64_C(`3414163584`), // S2_asl_r_p_nac
2134	UINT64_C(`3405774976`), // S2_asl_r_p_or
2135	UINT64_C(`3412066432`), // S2_asl_r_p_xor
2136	UINT64_C(`3326083200`), // S2_asl_r_r
2137	UINT64_C(`3435135104`), // S2_asl_r_r_acc
2138	UINT64_C(`3426746496`), // S2_asl_r_r_and
2139	UINT64_C(`3430940800`), // S2_asl_r_r_nac
2140	UINT64_C(`3422552192`), // S2_asl_r_r_or
2141	UINT64_C(`3321888896`), // S2_asl_r_r_sat
2142	UINT64_C(`3275751552`), // S2_asl_r_vh
2143	UINT64_C(`3271557248`), // S2_asl_r_vw
2144	UINT64_C(`2147483648`), // S2_asr_i_p
2145	UINT64_C(`2181038208`), // S2_asr_i_p_acc
2146	UINT64_C(`2185232384`), // S2_asr_i_p_and
2147	UINT64_C(`2181038080`), // S2_asr_i_p_nac
2148	UINT64_C(`2185232512`), // S2_asr_i_p_or
2149	UINT64_C(`2160066784`), // S2_asr_i_p_rnd
2150	UINT64_C(`2348810240`), // S2_asr_i_r
2151	UINT64_C(`2382364800`), // S2_asr_i_r_acc
2152	UINT64_C(`2386558976`), // S2_asr_i_r_and
2153	UINT64_C(`2382364672`), // S2_asr_i_r_nac
2154	UINT64_C(`2386559104`), // S2_asr_i_r_or
2155	UINT64_C(`2353004544`), // S2_asr_i_r_rnd
2156	UINT64_C(`2294284352`), // S2_asr_i_svw_trun
2157	UINT64_C(`2155872256`), // S2_asr_i_vh
2158	UINT64_C(`2151677952`), // S2_asr_i_vw
2159	UINT64_C(`3279945728`), // S2_asr_r_p
2160	UINT64_C(`3418357760`), // S2_asr_r_p_acc
2161	UINT64_C(`3409969152`), // S2_asr_r_p_and
2162	UINT64_C(`3414163456`), // S2_asr_r_p_nac
2163	UINT64_C(`3405774848`), // S2_asr_r_p_or
2164	UINT64_C(`3412066304`), // S2_asr_r_p_xor
2165	UINT64_C(`3326083072`), // S2_asr_r_r
2166	UINT64_C(`3435134976`), // S2_asr_r_r_acc
2167	UINT64_C(`3426746368`), // S2_asr_r_r_and
2168	UINT64_C(`3430940672`), // S2_asr_r_r_nac
2169	UINT64_C(`3422552064`), // S2_asr_r_r_or
2170	UINT64_C(`3321888768`), // S2_asr_r_r_sat
2171	UINT64_C(`3305111616`), // S2_asr_r_svw_trun
2172	UINT64_C(`3275751424`), // S2_asr_r_vh
2173	UINT64_C(`3271557120`), // S2_asr_r_vw
2174	UINT64_C(`2353004736`), // S2_brev
2175	UINT64_C(`2160066752`), // S2_brevp
2176	UINT64_C(`3250585792`), // S2_cabacdecbin
2177	UINT64_C(`2348810400`), // S2_cl0
2178	UINT64_C(`2285895744`), // S2_cl0p
2179	UINT64_C(`2348810432`), // S2_cl1
2180	UINT64_C(`2285895808`), // S2_cl1p
2181	UINT64_C(`2348810368`), // S2_clb
2182	UINT64_C(`2348810464`), // S2_clbnorm
2183	UINT64_C(`2285895680`), // S2_clbp
2184	UINT64_C(`2361393184`), // S2_clrbit_i
2185	UINT64_C(`3330277440`), // S2_clrbit_r
2186	UINT64_C(`2353004672`), // S2_ct0
2187	UINT64_C(`2296381504`), // S2_ct0p
2188	UINT64_C(`2353004704`), // S2_ct1
2189	UINT64_C(`2296381568`), // S2_ct1p
2190	UINT64_C(`2160066688`), // S2_deinterleave
2191	UINT64_C(`2365587456`), // S2_extractu
2192	UINT64_C(`3372220416`), // S2_extractu_rp
2193	UINT64_C(`2164260864`), // S2_extractup
2194	UINT64_C(`3238002688`), // S2_extractup_rp
2195	UINT64_C(`2399141888`), // S2_insert
2196	UINT64_C(`3355443200`), // S2_insert_rp
2197	UINT64_C(`2197815296`), // S2_insertp
2198	UINT64_C(`3388997632`), // S2_insertp_rp
2199	UINT64_C(`2160066720`), // S2_interleave
2200	UINT64_C(`3246391488`), // S2_lfsp
2201	UINT64_C(`3279945920`), // S2_lsl_r_p
2202	UINT64_C(`3418357952`), // S2_lsl_r_p_acc
2203	UINT64_C(`3409969344`), // S2_lsl_r_p_and
2204	UINT64_C(`3414163648`), // S2_lsl_r_p_nac
2205	UINT64_C(`3405775040`), // S2_lsl_r_p_or
2206	UINT64_C(`3412066496`), // S2_lsl_r_p_xor
2207	UINT64_C(`3326083264`), // S2_lsl_r_r
2208	UINT64_C(`3435135168`), // S2_lsl_r_r_acc
2209	UINT64_C(`3426746560`), // S2_lsl_r_r_and
2210	UINT64_C(`3430940864`), // S2_lsl_r_r_nac
2211	UINT64_C(`3422552256`), // S2_lsl_r_r_or
2212	UINT64_C(`3275751616`), // S2_lsl_r_vh
2213	UINT64_C(`3271557312`), // S2_lsl_r_vw
2214	UINT64_C(`2147483680`), // S2_lsr_i_p
2215	UINT64_C(`2181038240`), // S2_lsr_i_p_acc
2216	UINT64_C(`2185232416`), // S2_lsr_i_p_and
2217	UINT64_C(`2181038112`), // S2_lsr_i_p_nac
2218	UINT64_C(`2185232544`), // S2_lsr_i_p_or
2219	UINT64_C(`2189426720`), // S2_lsr_i_p_xacc
2220	UINT64_C(`2348810272`), // S2_lsr_i_r
2221	UINT64_C(`2382364832`), // S2_lsr_i_r_acc
2222	UINT64_C(`2386559008`), // S2_lsr_i_r_and
2223	UINT64_C(`2382364704`), // S2_lsr_i_r_nac
2224	UINT64_C(`2386559136`), // S2_lsr_i_r_or
2225	UINT64_C(`2390753312`), // S2_lsr_i_r_xacc
2226	UINT64_C(`2155872288`), // S2_lsr_i_vh
2227	UINT64_C(`2151677984`), // S2_lsr_i_vw
2228	UINT64_C(`3279945792`), // S2_lsr_r_p
2229	UINT64_C(`3418357824`), // S2_lsr_r_p_acc
2230	UINT64_C(`3409969216`), // S2_lsr_r_p_and
2231	UINT64_C(`3414163520`), // S2_lsr_r_p_nac
2232	UINT64_C(`3405774912`), // S2_lsr_r_p_or
2233	UINT64_C(`3412066368`), // S2_lsr_r_p_xor
2234	UINT64_C(`3326083136`), // S2_lsr_r_r
2235	UINT64_C(`3435135040`), // S2_lsr_r_r_acc
2236	UINT64_C(`3426746432`), // S2_lsr_r_r_and
2237	UINT64_C(`3430940736`), // S2_lsr_r_r_nac
2238	UINT64_C(`3422552128`), // S2_lsr_r_r_or
2239	UINT64_C(`3275751488`), // S2_lsr_r_vh
2240	UINT64_C(`3271557184`), // S2_lsr_r_vw
2241	UINT64_C(`2365595648`), // S2_mask
2242	UINT64_C(`4118806528`), // S2_packhl
2243	UINT64_C(`3489660928`), // S2_parityp
2244	UINT64_C(`1140850688`), // S2_pstorerbf_io
2245	UINT64_C(`2868912132`), // S2_pstorerbf_pi
2246	UINT64_C(`2868912260`), // S2_pstorerbfnew_pi
2247	UINT64_C(`1151336448`), // S2_pstorerbnewf_io
2248	UINT64_C(`2879397892`), // S2_pstorerbnewf_pi
2249	UINT64_C(`2879398020`), // S2_pstorerbnewfnew_pi
2250	UINT64_C(`1084227584`), // S2_pstorerbnewt_io
2251	UINT64_C(`2879397888`), // S2_pstorerbnewt_pi
2252	UINT64_C(`2879398016`), // S2_pstorerbnewtnew_pi
2253	UINT64_C(`1073741824`), // S2_pstorerbt_io
2254	UINT64_C(`2868912128`), // S2_pstorerbt_pi
2255	UINT64_C(`2868912256`), // S2_pstorerbtnew_pi
2256	UINT64_C(`1153433600`), // S2_pstorerdf_io
2257	UINT64_C(`2881495044`), // S2_pstorerdf_pi
2258	UINT64_C(`2881495172`), // S2_pstorerdfnew_pi
2259	UINT64_C(`1086324736`), // S2_pstorerdt_io
2260	UINT64_C(`2881495040`), // S2_pstorerdt_pi
2261	UINT64_C(`2881495168`), // S2_pstorerdtnew_pi
2262	UINT64_C(`1147142144`), // S2_pstorerff_io
2263	UINT64_C(`2875203588`), // S2_pstorerff_pi
2264	UINT64_C(`2875203716`), // S2_pstorerffnew_pi
2265	UINT64_C(`1080033280`), // S2_pstorerft_io
2266	UINT64_C(`2875203584`), // S2_pstorerft_pi
2267	UINT64_C(`2875203712`), // S2_pstorerftnew_pi
2268	UINT64_C(`1145044992`), // S2_pstorerhf_io
2269	UINT64_C(`2873106436`), // S2_pstorerhf_pi
2270	UINT64_C(`2873106564`), // S2_pstorerhfnew_pi
2271	UINT64_C(`1151338496`), // S2_pstorerhnewf_io
2272	UINT64_C(`2879399940`), // S2_pstorerhnewf_pi
2273	UINT64_C(`2879400068`), // S2_pstorerhnewfnew_pi
2274	UINT64_C(`1084229632`), // S2_pstorerhnewt_io
2275	UINT64_C(`2879399936`), // S2_pstorerhnewt_pi
2276	UINT64_C(`2879400064`), // S2_pstorerhnewtnew_pi
2277	UINT64_C(`1077936128`), // S2_pstorerht_io
2278	UINT64_C(`2873106432`), // S2_pstorerht_pi
2279	UINT64_C(`2873106560`), // S2_pstorerhtnew_pi
2280	UINT64_C(`1149239296`), // S2_pstorerif_io
2281	UINT64_C(`2877300740`), // S2_pstorerif_pi
2282	UINT64_C(`2877300868`), // S2_pstorerifnew_pi
2283	UINT64_C(`1151340544`), // S2_pstorerinewf_io
2284	UINT64_C(`2879401988`), // S2_pstorerinewf_pi
2285	UINT64_C(`2879402116`), // S2_pstorerinewfnew_pi
2286	UINT64_C(`1084231680`), // S2_pstorerinewt_io
2287	UINT64_C(`2879401984`), // S2_pstorerinewt_pi
2288	UINT64_C(`2879402112`), // S2_pstorerinewtnew_pi
2289	UINT64_C(`1082130432`), // S2_pstorerit_io
2290	UINT64_C(`2877300736`), // S2_pstorerit_pi
2291	UINT64_C(`2877300864`), // S2_pstoreritnew_pi
2292	UINT64_C(`2361393152`), // S2_setbit_i
2293	UINT64_C(`3330277376`), // S2_setbit_r
2294	UINT64_C(`3238002752`), // S2_shuffeb
2295	UINT64_C(`3238002880`), // S2_shuffeh
2296	UINT64_C(`3238002816`), // S2_shuffob
2297	UINT64_C(`3246391296`), // S2_shuffoh
2298	UINT64_C(`2701131776`), // S2_storerb_io
2299	UINT64_C(`2936012800`), // S2_storerb_pbr
2300	UINT64_C(`2835349504`), // S2_storerb_pci
2301	UINT64_C(`2835349506`), // S2_storerb_pcr
2302	UINT64_C(`2868903936`), // S2_storerb_pi
2303	UINT64_C(`2902458368`), // S2_storerb_pr
2304	UINT64_C(`1207959552`), // S2_storerbgp
2305	UINT64_C(`2711617536`), // S2_storerbnew_io
2306	UINT64_C(`2946498560`), // S2_storerbnew_pbr
2307	UINT64_C(`2845835264`), // S2_storerbnew_pci
2308	UINT64_C(`2845835266`), // S2_storerbnew_pcr
2309	UINT64_C(`2879389696`), // S2_storerbnew_pi
2310	UINT64_C(`2912944128`), // S2_storerbnew_pr
2311	UINT64_C(`1218445312`), // S2_storerbnewgp
2312	UINT64_C(`2713714688`), // S2_storerd_io
2313	UINT64_C(`2948595712`), // S2_storerd_pbr
2314	UINT64_C(`2847932416`), // S2_storerd_pci
2315	UINT64_C(`2847932418`), // S2_storerd_pcr
2316	UINT64_C(`2881486848`), // S2_storerd_pi
2317	UINT64_C(`2915041280`), // S2_storerd_pr
2318	UINT64_C(`1220542464`), // S2_storerdgp
2319	UINT64_C(`2707423232`), // S2_storerf_io
2320	UINT64_C(`2942304256`), // S2_storerf_pbr
2321	UINT64_C(`2841640960`), // S2_storerf_pci
2322	UINT64_C(`2841640962`), // S2_storerf_pcr
2323	UINT64_C(`2875195392`), // S2_storerf_pi
2324	UINT64_C(`2908749824`), // S2_storerf_pr
2325	UINT64_C(`1214251008`), // S2_storerfgp
2326	UINT64_C(`2705326080`), // S2_storerh_io
2327	UINT64_C(`2940207104`), // S2_storerh_pbr
2328	UINT64_C(`2839543808`), // S2_storerh_pci
2329	UINT64_C(`2839543810`), // S2_storerh_pcr
2330	UINT64_C(`2873098240`), // S2_storerh_pi
2331	UINT64_C(`2906652672`), // S2_storerh_pr
2332	UINT64_C(`1212153856`), // S2_storerhgp
2333	UINT64_C(`2711619584`), // S2_storerhnew_io
2334	UINT64_C(`2946500608`), // S2_storerhnew_pbr
2335	UINT64_C(`2845837312`), // S2_storerhnew_pci
2336	UINT64_C(`2845837314`), // S2_storerhnew_pcr
2337	UINT64_C(`2879391744`), // S2_storerhnew_pi
2338	UINT64_C(`2912946176`), // S2_storerhnew_pr
2339	UINT64_C(`1218447360`), // S2_storerhnewgp
2340	UINT64_C(`2709520384`), // S2_storeri_io
2341	UINT64_C(`2944401408`), // S2_storeri_pbr
2342	UINT64_C(`2843738112`), // S2_storeri_pci
2343	UINT64_C(`2843738114`), // S2_storeri_pcr
2344	UINT64_C(`2877292544`), // S2_storeri_pi
2345	UINT64_C(`2910846976`), // S2_storeri_pr
2346	UINT64_C(`1216348160`), // S2_storerigp
2347	UINT64_C(`2711621632`), // S2_storerinew_io
2348	UINT64_C(`2946502656`), // S2_storerinew_pbr
2349	UINT64_C(`2845839360`), // S2_storerinew_pci
2350	UINT64_C(`2845839362`), // S2_storerinew_pcr
2351	UINT64_C(`2879393792`), // S2_storerinew_pi
2352	UINT64_C(`2912948224`), // S2_storerinew_pr
2353	UINT64_C(`1218449408`), // S2_storerinewgp
2354	UINT64_C(`2694840320`), // S2_storew_locked
2355	UINT64_C(`2694840328`), // S2_storew_rl_at_vi
2356	UINT64_C(`2694840360`), // S2_storew_rl_st_vi
2357	UINT64_C(`2357198848`), // S2_svsathb
2358	UINT64_C(`2357198912`), // S2_svsathub
2359	UINT64_C(`2264924160`), // S2_tableidxb
2360	UINT64_C(`2277507072`), // S2_tableidxd
2361	UINT64_C(`2269118464`), // S2_tableidxh
2362	UINT64_C(`2273312768`), // S2_tableidxw
2363	UINT64_C(`2361393216`), // S2_togglebit_i
2364	UINT64_C(`3330277504`), // S2_togglebit_r
2365	UINT64_C(`2231369728`), // S2_tstbit_i
2366	UINT64_C(`3338665984`), // S2_tstbit_r
2367	UINT64_C(`3221225472`), // S2_valignib
2368	UINT64_C(`3254779904`), // S2_valignrb
2369	UINT64_C(`3284140096`), // S2_vcnegh
2370	UINT64_C(`3284140032`), // S2_vcrotate
2371	UINT64_C(`3407880416`), // S2_vrcnegh
2372	UINT64_C(`2290090112`), // S2_vrndpackwh
2373	UINT64_C(`2290090176`), // S2_vrndpackwhs
2374	UINT64_C(`2281701568`), // S2_vsathb
2375	UINT64_C(`2147483872`), // S2_vsathb_nopack
2376	UINT64_C(`2281701376`), // S2_vsathub
2377	UINT64_C(`2147483776`), // S2_vsathub_nopack
2378	UINT64_C(`2281701440`), // S2_vsatwh
2379	UINT64_C(`2147483840`), // S2_vsatwh_nopack
2380	UINT64_C(`2281701504`), // S2_vsatwuh
2381	UINT64_C(`2147483808`), // S2_vsatwuh_nopack
2382	UINT64_C(`2353004768`), // S2_vsplatrb
2383	UINT64_C(`2218786880`), // S2_vsplatrh
2384	UINT64_C(`3229614080`), // S2_vspliceib
2385	UINT64_C(`3263168512`), // S2_vsplicerb
2386	UINT64_C(`2214592512`), // S2_vsxtbh
2387	UINT64_C(`2214592640`), // S2_vsxthw
2388	UINT64_C(`2290090048`), // S2_vtrunehb
2389	UINT64_C(`3246391360`), // S2_vtrunewh
2390	UINT64_C(`2290089984`), // S2_vtrunohb
2391	UINT64_C(`3246391424`), // S2_vtrunowh
2392	UINT64_C(`2214592576`), // S2_vzxtbh
2393	UINT64_C(`2214592704`), // S2_vzxthw
2394	UINT64_C(`3674210304`), // S4_addaddi
2395	UINT64_C(`3724541956`), // S4_addi_asl_ri
2396	UINT64_C(`3724541972`), // S4_addi_lsr_ri
2397	UINT64_C(`3724541952`), // S4_andi_asl_ri
2398	UINT64_C(`3724541968`), // S4_andi_lsr_ri
2399	UINT64_C(`2350907392`), // S4_clbaddi
2400	UINT64_C(`2287992896`), // S4_clbpaddi
2401	UINT64_C(`2287992832`), // S4_clbpnorm
2402	UINT64_C(`2373976064`), // S4_extract
2403	UINT64_C(`3372220480`), // S4_extract_rp
2404	UINT64_C(`2315255808`), // S4_extractp
2405	UINT64_C(`3250585728`), // S4_extractp_rp
2406	UINT64_C(`3330277568`), // S4_lsli
2407	UINT64_C(`2233466880`), // S4_ntstbit_i
2408	UINT64_C(`3340763136`), // S4_ntstbit_r
2409	UINT64_C(`3657433088`), // S4_or_andi
2410	UINT64_C(`3661627392`), // S4_or_andix
2411	UINT64_C(`3665821696`), // S4_or_ori
2412	UINT64_C(`3724541954`), // S4_ori_asl_ri
2413	UINT64_C(`3724541970`), // S4_ori_lsr_ri
2414	UINT64_C(`3588227072`), // S4_parity
2415	UINT64_C(`2936012932`), // S4_pstorerbf_abs
2416	UINT64_C(`889192448`), // S4_pstorerbf_rr
2417	UINT64_C(`2936021124`), // S4_pstorerbfnew_abs
2418	UINT64_C(`1174405120`), // S4_pstorerbfnew_io
2419	UINT64_C(`922746880`), // S4_pstorerbfnew_rr
2420	UINT64_C(`2946498692`), // S4_pstorerbnewf_abs
2421	UINT64_C(`899678208`), // S4_pstorerbnewf_rr
2422	UINT64_C(`2946506884`), // S4_pstorerbnewfnew_abs
2423	UINT64_C(`1184890880`), // S4_pstorerbnewfnew_io
2424	UINT64_C(`933232640`), // S4_pstorerbnewfnew_rr
2425	UINT64_C(`2946498688`), // S4_pstorerbnewt_abs
2426	UINT64_C(`882900992`), // S4_pstorerbnewt_rr
2427	UINT64_C(`2946506880`), // S4_pstorerbnewtnew_abs
2428	UINT64_C(`1117782016`), // S4_pstorerbnewtnew_io
2429	UINT64_C(`916455424`), // S4_pstorerbnewtnew_rr
2430	UINT64_C(`2936012928`), // S4_pstorerbt_abs
2431	UINT64_C(`872415232`), // S4_pstorerbt_rr
2432	UINT64_C(`2936021120`), // S4_pstorerbtnew_abs
2433	UINT64_C(`1107296256`), // S4_pstorerbtnew_io
2434	UINT64_C(`905969664`), // S4_pstorerbtnew_rr
2435	UINT64_C(`2948595844`), // S4_pstorerdf_abs
2436	UINT64_C(`901775360`), // S4_pstorerdf_rr
2437	UINT64_C(`2948604036`), // S4_pstorerdfnew_abs
2438	UINT64_C(`1186988032`), // S4_pstorerdfnew_io
2439	UINT64_C(`935329792`), // S4_pstorerdfnew_rr
2440	UINT64_C(`2948595840`), // S4_pstorerdt_abs
2441	UINT64_C(`884998144`), // S4_pstorerdt_rr
2442	UINT64_C(`2948604032`), // S4_pstorerdtnew_abs
2443	UINT64_C(`1119879168`), // S4_pstorerdtnew_io
2444	UINT64_C(`918552576`), // S4_pstorerdtnew_rr
2445	UINT64_C(`2942304388`), // S4_pstorerff_abs
2446	UINT64_C(`895483904`), // S4_pstorerff_rr
2447	UINT64_C(`2942312580`), // S4_pstorerffnew_abs
2448	UINT64_C(`1180696576`), // S4_pstorerffnew_io
2449	UINT64_C(`929038336`), // S4_pstorerffnew_rr
2450	UINT64_C(`2942304384`), // S4_pstorerft_abs
2451	UINT64_C(`878706688`), // S4_pstorerft_rr
2452	UINT64_C(`2942312576`), // S4_pstorerftnew_abs
2453	UINT64_C(`1113587712`), // S4_pstorerftnew_io
2454	UINT64_C(`912261120`), // S4_pstorerftnew_rr
2455	UINT64_C(`2940207236`), // S4_pstorerhf_abs
2456	UINT64_C(`893386752`), // S4_pstorerhf_rr
2457	UINT64_C(`2940215428`), // S4_pstorerhfnew_abs
2458	UINT64_C(`1178599424`), // S4_pstorerhfnew_io
2459	UINT64_C(`926941184`), // S4_pstorerhfnew_rr
2460	UINT64_C(`2946500740`), // S4_pstorerhnewf_abs
2461	UINT64_C(`899678216`), // S4_pstorerhnewf_rr
2462	UINT64_C(`2946508932`), // S4_pstorerhnewfnew_abs
2463	UINT64_C(`1184892928`), // S4_pstorerhnewfnew_io
2464	UINT64_C(`933232648`), // S4_pstorerhnewfnew_rr
2465	UINT64_C(`2946500736`), // S4_pstorerhnewt_abs
2466	UINT64_C(`882901000`), // S4_pstorerhnewt_rr
2467	UINT64_C(`2946508928`), // S4_pstorerhnewtnew_abs
2468	UINT64_C(`1117784064`), // S4_pstorerhnewtnew_io
2469	UINT64_C(`916455432`), // S4_pstorerhnewtnew_rr
2470	UINT64_C(`2940207232`), // S4_pstorerht_abs
2471	UINT64_C(`876609536`), // S4_pstorerht_rr
2472	UINT64_C(`2940215424`), // S4_pstorerhtnew_abs
2473	UINT64_C(`1111490560`), // S4_pstorerhtnew_io
2474	UINT64_C(`910163968`), // S4_pstorerhtnew_rr
2475	UINT64_C(`2944401540`), // S4_pstorerif_abs
2476	UINT64_C(`897581056`), // S4_pstorerif_rr
2477	UINT64_C(`2944409732`), // S4_pstorerifnew_abs
2478	UINT64_C(`1182793728`), // S4_pstorerifnew_io
2479	UINT64_C(`931135488`), // S4_pstorerifnew_rr
2480	UINT64_C(`2946502788`), // S4_pstorerinewf_abs
2481	UINT64_C(`899678224`), // S4_pstorerinewf_rr
2482	UINT64_C(`2946510980`), // S4_pstorerinewfnew_abs
2483	UINT64_C(`1184894976`), // S4_pstorerinewfnew_io
2484	UINT64_C(`933232656`), // S4_pstorerinewfnew_rr
2485	UINT64_C(`2946502784`), // S4_pstorerinewt_abs
2486	UINT64_C(`882901008`), // S4_pstorerinewt_rr
2487	UINT64_C(`2946510976`), // S4_pstorerinewtnew_abs
2488	UINT64_C(`1117786112`), // S4_pstorerinewtnew_io
2489	UINT64_C(`916455440`), // S4_pstorerinewtnew_rr
2490	UINT64_C(`2944401536`), // S4_pstorerit_abs
2491	UINT64_C(`880803840`), // S4_pstorerit_rr
2492	UINT64_C(`2944409728`), // S4_pstoreritnew_abs
2493	UINT64_C(`1115684864`), // S4_pstoreritnew_io
2494	UINT64_C(`914358272`), // S4_pstoreritnew_rr
2495	UINT64_C(`2699034624`), // S4_stored_locked
2496	UINT64_C(`2699034632`), // S4_stored_rl_at_vi
2497	UINT64_C(`2699034664`), // S4_stored_rl_st_vi
2498	UINT64_C(`1006632960`), // S4_storeirb_io
2499	UINT64_C(`947912704`), // S4_storeirbf_io
2500	UINT64_C(`964689920`), // S4_storeirbfnew_io
2501	UINT64_C(`939524096`), // S4_storeirbt_io
2502	UINT64_C(`956301312`), // S4_storeirbtnew_io
2503	UINT64_C(`1008730112`), // S4_storeirh_io
2504	UINT64_C(`950009856`), // S4_storeirhf_io
2505	UINT64_C(`966787072`), // S4_storeirhfnew_io
2506	UINT64_C(`941621248`), // S4_storeirht_io
2507	UINT64_C(`958398464`), // S4_storeirhtnew_io
2508	UINT64_C(`1010827264`), // S4_storeiri_io
2509	UINT64_C(`952107008`), // S4_storeirif_io
2510	UINT64_C(`968884224`), // S4_storeirifnew_io
2511	UINT64_C(`943718400`), // S4_storeirit_io
2512	UINT64_C(`960495616`), // S4_storeiritnew_io
2513	UINT64_C(`2868904064`), // S4_storerb_ap
2514	UINT64_C(`989855744`), // S4_storerb_rr
2515	UINT64_C(`2902458496`), // S4_storerb_ur
2516	UINT64_C(`2879389824`), // S4_storerbnew_ap
2517	UINT64_C(`1000341504`), // S4_storerbnew_rr
2518	UINT64_C(`2912944256`), // S4_storerbnew_ur
2519	UINT64_C(`2881486976`), // S4_storerd_ap
2520	UINT64_C(`1002438656`), // S4_storerd_rr
2521	UINT64_C(`2915041408`), // S4_storerd_ur
2522	UINT64_C(`2875195520`), // S4_storerf_ap
2523	UINT64_C(`996147200`), // S4_storerf_rr
2524	UINT64_C(`2908749952`), // S4_storerf_ur
2525	UINT64_C(`2873098368`), // S4_storerh_ap
2526	UINT64_C(`994050048`), // S4_storerh_rr
2527	UINT64_C(`2906652800`), // S4_storerh_ur
2528	UINT64_C(`2879391872`), // S4_storerhnew_ap
2529	UINT64_C(`1000341512`), // S4_storerhnew_rr
2530	UINT64_C(`2912946304`), // S4_storerhnew_ur
2531	UINT64_C(`2877292672`), // S4_storeri_ap
2532	UINT64_C(`998244352`), // S4_storeri_rr
2533	UINT64_C(`2910847104`), // S4_storeri_ur
2534	UINT64_C(`2879393920`), // S4_storerinew_ap
2535	UINT64_C(`1000341520`), // S4_storerinew_rr
2536	UINT64_C(`2912948352`), // S4_storerinew_ur
2537	UINT64_C(`3682598912`), // S4_subaddi
2538	UINT64_C(`3724541958`), // S4_subi_asl_ri
2539	UINT64_C(`3724541974`), // S4_subi_lsr_ri
2540	UINT64_C(`3284140224`), // S4_vrcrotate
2541	UINT64_C(`3416260608`), // S4_vrcrotate_acc
2542	UINT64_C(`3242197120`), // S4_vxaddsubh
2543	UINT64_C(`3250585600`), // S4_vxaddsubhr
2544	UINT64_C(`3242196992`), // S4_vxaddsubw
2545	UINT64_C(`3242197184`), // S4_vxsubaddh
2546	UINT64_C(`3250585664`), // S4_vxsubaddhr
2547	UINT64_C(`3242197056`), // S4_vxsubaddw
2548	UINT64_C(`2287992960`), // S5_asrhub_rnd_sat
2549	UINT64_C(`2287992992`), // S5_asrhub_sat
2550	UINT64_C(`2287992928`), // S5_popcountp
2551	UINT64_C(`2149580800`), // S5_vasrhrnd
2552	UINT64_C(`2147483744`), // S6_rol_i_p
2553	UINT64_C(`2181038304`), // S6_rol_i_p_acc
2554	UINT64_C(`2185232480`), // S6_rol_i_p_and
2555	UINT64_C(`2181038176`), // S6_rol_i_p_nac
2556	UINT64_C(`2185232608`), // S6_rol_i_p_or
2557	UINT64_C(`2189426784`), // S6_rol_i_p_xacc
2558	UINT64_C(`2348810336`), // S6_rol_i_r
2559	UINT64_C(`2382364896`), // S6_rol_i_r_acc
2560	UINT64_C(`2386559072`), // S6_rol_i_r_and
2561	UINT64_C(`2382364768`), // S6_rol_i_r_nac
2562	UINT64_C(`2386559200`), // S6_rol_i_r_or
2563	UINT64_C(`2390753376`), // S6_rol_i_r_xacc
2564	UINT64_C(`2218786944`), // S6_vsplatrbp
2565	UINT64_C(`3246391392`), // S6_vtrunehb_ppp
2566	UINT64_C(`3246391456`), // S6_vtrunohb_ppp
2567	UINT64_C(`0`), // SA1_addi
2568	UINT64_C(`6144`), // SA1_addrx
2569	UINT64_C(`3072`), // SA1_addsp
2570	UINT64_C(`4608`), // SA1_and1
2571	UINT64_C(`6768`), // SA1_clrf
2572	UINT64_C(`6736`), // SA1_clrfnew
2573	UINT64_C(`6752`), // SA1_clrt
2574	UINT64_C(`6720`), // SA1_clrtnew
2575	UINT64_C(`6400`), // SA1_cmpeqi
2576	UINT64_C(`7168`), // SA1_combine0i
2577	UINT64_C(`7176`), // SA1_combine1i
2578	UINT64_C(`7184`), // SA1_combine2i
2579	UINT64_C(`7192`), // SA1_combine3i
2580	UINT64_C(`7432`), // SA1_combinerz
2581	UINT64_C(`7424`), // SA1_combinezr
2582	UINT64_C(`4864`), // SA1_dec
2583	UINT64_C(`4352`), // SA1_inc
2584	UINT64_C(`2048`), // SA1_seti
2585	UINT64_C(`6656`), // SA1_setin1
2586	UINT64_C(`5376`), // SA1_sxtb
2587	UINT64_C(`5120`), // SA1_sxth
2588	UINT64_C(`4096`), // SA1_tfr
2589	UINT64_C(`5888`), // SA1_zxtb
2590	UINT64_C(`5632`), // SA1_zxth
2591	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4
2592	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4STK
2593	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4STK_EXT
2594	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4STK_EXT_PIC
2595	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4STK_PIC
2596	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4_EXT
2597	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4_EXT_PIC
2598	UINT64_C(`1509949440`), // SAVE_REGISTERS_CALL_V4_PIC
2599	UINT64_C(`0`), // SL1_loadri_io
2600	UINT64_C(`4096`), // SL1_loadrub_io
2601	UINT64_C(`7936`), // SL2_deallocframe
2602	UINT64_C(`8128`), // SL2_jumpr31
2603	UINT64_C(`8133`), // SL2_jumpr31_f
2604	UINT64_C(`8135`), // SL2_jumpr31_fnew
2605	UINT64_C(`8132`), // SL2_jumpr31_t
2606	UINT64_C(`8134`), // SL2_jumpr31_tnew
2607	UINT64_C(`4096`), // SL2_loadrb_io
2608	UINT64_C(`7680`), // SL2_loadrd_sp
2609	UINT64_C(`0`), // SL2_loadrh_io
2610	UINT64_C(`7168`), // SL2_loadri_sp
2611	UINT64_C(`2048`), // SL2_loadruh_io
2612	UINT64_C(`8000`), // SL2_return
2613	UINT64_C(`8005`), // SL2_return_f
2614	UINT64_C(`8007`), // SL2_return_fnew
2615	UINT64_C(`8004`), // SL2_return_t
2616	UINT64_C(`8006`), // SL2_return_tnew
2617	UINT64_C(`4096`), // SS1_storeb_io
2618	UINT64_C(`0`), // SS1_storew_io
2619	UINT64_C(`7168`), // SS2_allocframe
2620	UINT64_C(`4608`), // SS2_storebi0
2621	UINT64_C(`4864`), // SS2_storebi1
2622	UINT64_C(`2560`), // SS2_stored_sp
2623	UINT64_C(`0`), // SS2_storeh_io
2624	UINT64_C(`2048`), // SS2_storew_sp
2625	UINT64_C(`4096`), // SS2_storewi0
2626	UINT64_C(`4352`), // SS2_storewi1
2627	UINT64_C(`0`), // TFRI64_V2_ext
2628	UINT64_C(`0`), // TFRI64_V4
2629	UINT64_C(`2449473568`), // V6_extractw
2630	UINT64_C(`432013376`), // V6_lvsplatb
2631	UINT64_C(`432013344`), // V6_lvsplath
2632	UINT64_C(`429916192`), // V6_lvsplatw
2633	UINT64_C(`503513088`), // V6_pred_and
2634	UINT64_C(`503513108`), // V6_pred_and_n
2635	UINT64_C(`503513096`), // V6_pred_not
2636	UINT64_C(`503513092`), // V6_pred_or
2637	UINT64_C(`503513104`), // V6_pred_or_n
2638	UINT64_C(`429916228`), // V6_pred_scalar2
2639	UINT64_C(`429916236`), // V6_pred_scalar2v2
2640	UINT64_C(`503513100`), // V6_pred_xor
2641	UINT64_C(`503513112`), // V6_shuffeqh
2642	UINT64_C(`503513116`), // V6_shuffeqw
2643	UINT64_C(`524296320`), // V6_v6mpyhubs10
2644	UINT64_C(`522199168`), // V6_v6mpyhubs10_vxx
2645	UINT64_C(`524296192`), // V6_v6mpyvubs10
2646	UINT64_C(`522199040`), // V6_v6mpyvubs10_vxx
2647	UINT64_C(`671088864`), // V6_vL32Ub_ai
2648	UINT64_C(`687866080`), // V6_vL32Ub_pi
2649	UINT64_C(`721420512`), // V6_vL32Ub_ppu
2650	UINT64_C(`671088640`), // V6_vL32b_ai
2651	UINT64_C(`671088672`), // V6_vL32b_cur_ai
2652	UINT64_C(`679477408`), // V6_vL32b_cur_npred_ai
2653	UINT64_C(`696254624`), // V6_vL32b_cur_npred_pi
2654	UINT64_C(`729809056`), // V6_vL32b_cur_npred_ppu
2655	UINT64_C(`687865888`), // V6_vL32b_cur_pi
2656	UINT64_C(`721420320`), // V6_vL32b_cur_ppu
2657	UINT64_C(`679477376`), // V6_vL32b_cur_pred_ai
2658	UINT64_C(`696254592`), // V6_vL32b_cur_pred_pi
2659	UINT64_C(`729809024`), // V6_vL32b_cur_pred_ppu
2660	UINT64_C(`679477344`), // V6_vL32b_npred_ai
2661	UINT64_C(`696254560`), // V6_vL32b_npred_pi
2662	UINT64_C(`729808992`), // V6_vL32b_npred_ppu
2663	UINT64_C(`675282944`), // V6_vL32b_nt_ai
2664	UINT64_C(`675282976`), // V6_vL32b_nt_cur_ai
2665	UINT64_C(`683671712`), // V6_vL32b_nt_cur_npred_ai
2666	UINT64_C(`700448928`), // V6_vL32b_nt_cur_npred_pi
2667	UINT64_C(`734003360`), // V6_vL32b_nt_cur_npred_ppu
2668	UINT64_C(`692060192`), // V6_vL32b_nt_cur_pi
2669	UINT64_C(`725614624`), // V6_vL32b_nt_cur_ppu
2670	UINT64_C(`683671680`), // V6_vL32b_nt_cur_pred_ai
2671	UINT64_C(`700448896`), // V6_vL32b_nt_cur_pred_pi
2672	UINT64_C(`734003328`), // V6_vL32b_nt_cur_pred_ppu
2673	UINT64_C(`683671648`), // V6_vL32b_nt_npred_ai
2674	UINT64_C(`700448864`), // V6_vL32b_nt_npred_pi
2675	UINT64_C(`734003296`), // V6_vL32b_nt_npred_ppu
2676	UINT64_C(`692060160`), // V6_vL32b_nt_pi
2677	UINT64_C(`725614592`), // V6_vL32b_nt_ppu
2678	UINT64_C(`683671616`), // V6_vL32b_nt_pred_ai
2679	UINT64_C(`700448832`), // V6_vL32b_nt_pred_pi
2680	UINT64_C(`734003264`), // V6_vL32b_nt_pred_ppu
2681	UINT64_C(`675283008`), // V6_vL32b_nt_tmp_ai
2682	UINT64_C(`683671776`), // V6_vL32b_nt_tmp_npred_ai
2683	UINT64_C(`700448992`), // V6_vL32b_nt_tmp_npred_pi
2684	UINT64_C(`734003424`), // V6_vL32b_nt_tmp_npred_ppu
2685	UINT64_C(`692060224`), // V6_vL32b_nt_tmp_pi
2686	UINT64_C(`725614656`), // V6_vL32b_nt_tmp_ppu
2687	UINT64_C(`683671744`), // V6_vL32b_nt_tmp_pred_ai
2688	UINT64_C(`700448960`), // V6_vL32b_nt_tmp_pred_pi
2689	UINT64_C(`734003392`), // V6_vL32b_nt_tmp_pred_ppu
2690	UINT64_C(`687865856`), // V6_vL32b_pi
2691	UINT64_C(`721420288`), // V6_vL32b_ppu
2692	UINT64_C(`679477312`), // V6_vL32b_pred_ai
2693	UINT64_C(`696254528`), // V6_vL32b_pred_pi
2694	UINT64_C(`729808960`), // V6_vL32b_pred_ppu
2695	UINT64_C(`671088704`), // V6_vL32b_tmp_ai
2696	UINT64_C(`679477472`), // V6_vL32b_tmp_npred_ai
2697	UINT64_C(`696254688`), // V6_vL32b_tmp_npred_pi
2698	UINT64_C(`729809120`), // V6_vL32b_tmp_npred_ppu
2699	UINT64_C(`687865920`), // V6_vL32b_tmp_pi
2700	UINT64_C(`721420352`), // V6_vL32b_tmp_ppu
2701	UINT64_C(`679477440`), // V6_vL32b_tmp_pred_ai
2702	UINT64_C(`696254656`), // V6_vL32b_tmp_pred_pi
2703	UINT64_C(`729809088`), // V6_vL32b_tmp_pred_ppu
2704	UINT64_C(`673186016`), // V6_vS32Ub_ai
2705	UINT64_C(`681574624`), // V6_vS32Ub_npred_ai
2706	UINT64_C(`698351840`), // V6_vS32Ub_npred_pi
2707	UINT64_C(`731906272`), // V6_vS32Ub_npred_ppu
2708	UINT64_C(`689963232`), // V6_vS32Ub_pi
2709	UINT64_C(`723517664`), // V6_vS32Ub_ppu
2710	UINT64_C(`681574592`), // V6_vS32Ub_pred_ai
2711	UINT64_C(`698351808`), // V6_vS32Ub_pred_pi
2712	UINT64_C(`731906240`), // V6_vS32Ub_pred_ppu
2713	UINT64_C(`673185792`), // V6_vS32b_ai
2714	UINT64_C(`673185824`), // V6_vS32b_new_ai
2715	UINT64_C(`681574504`), // V6_vS32b_new_npred_ai
2716	UINT64_C(`698351720`), // V6_vS32b_new_npred_pi
2717	UINT64_C(`731906152`), // V6_vS32b_new_npred_ppu
2718	UINT64_C(`689963040`), // V6_vS32b_new_pi
2719	UINT64_C(`723517472`), // V6_vS32b_new_ppu
2720	UINT64_C(`681574464`), // V6_vS32b_new_pred_ai
2721	UINT64_C(`698351680`), // V6_vS32b_new_pred_pi
2722	UINT64_C(`731906112`), // V6_vS32b_new_pred_ppu
2723	UINT64_C(`681574432`), // V6_vS32b_npred_ai
2724	UINT64_C(`698351648`), // V6_vS32b_npred_pi
2725	UINT64_C(`731906080`), // V6_vS32b_npred_ppu
2726	UINT64_C(`679477280`), // V6_vS32b_nqpred_ai
2727	UINT64_C(`696254496`), // V6_vS32b_nqpred_pi
2728	UINT64_C(`729808928`), // V6_vS32b_nqpred_ppu
2729	UINT64_C(`677380096`), // V6_vS32b_nt_ai
2730	UINT64_C(`677380128`), // V6_vS32b_nt_new_ai
2731	UINT64_C(`685768824`), // V6_vS32b_nt_new_npred_ai
2732	UINT64_C(`702546040`), // V6_vS32b_nt_new_npred_pi
2733	UINT64_C(`736100472`), // V6_vS32b_nt_new_npred_ppu
2734	UINT64_C(`694157344`), // V6_vS32b_nt_new_pi
2735	UINT64_C(`727711776`), // V6_vS32b_nt_new_ppu
2736	UINT64_C(`685768784`), // V6_vS32b_nt_new_pred_ai
2737	UINT64_C(`702546000`), // V6_vS32b_nt_new_pred_pi
2738	UINT64_C(`736100432`), // V6_vS32b_nt_new_pred_ppu
2739	UINT64_C(`685768736`), // V6_vS32b_nt_npred_ai
2740	UINT64_C(`702545952`), // V6_vS32b_nt_npred_pi
2741	UINT64_C(`736100384`), // V6_vS32b_nt_npred_ppu
2742	UINT64_C(`683671584`), // V6_vS32b_nt_nqpred_ai
2743	UINT64_C(`700448800`), // V6_vS32b_nt_nqpred_pi
2744	UINT64_C(`734003232`), // V6_vS32b_nt_nqpred_ppu
2745	UINT64_C(`694157312`), // V6_vS32b_nt_pi
2746	UINT64_C(`727711744`), // V6_vS32b_nt_ppu
2747	UINT64_C(`685768704`), // V6_vS32b_nt_pred_ai
2748	UINT64_C(`702545920`), // V6_vS32b_nt_pred_pi
2749	UINT64_C(`736100352`), // V6_vS32b_nt_pred_ppu
2750	UINT64_C(`683671552`), // V6_vS32b_nt_qpred_ai
2751	UINT64_C(`700448768`), // V6_vS32b_nt_qpred_pi
2752	UINT64_C(`734003200`), // V6_vS32b_nt_qpred_ppu
2753	UINT64_C(`689963008`), // V6_vS32b_pi
2754	UINT64_C(`723517440`), // V6_vS32b_ppu
2755	UINT64_C(`681574400`), // V6_vS32b_pred_ai
2756	UINT64_C(`698351616`), // V6_vS32b_pred_pi
2757	UINT64_C(`731906048`), // V6_vS32b_pred_ppu
2758	UINT64_C(`679477248`), // V6_vS32b_qpred_ai
2759	UINT64_C(`696254464`), // V6_vS32b_qpred_pi
2760	UINT64_C(`729808896`), // V6_vS32b_qpred_ppu
2761	UINT64_C(`673185832`), // V6_vS32b_srls_ai
2762	UINT64_C(`689963048`), // V6_vS32b_srls_pi
2763	UINT64_C(`723517480`), // V6_vS32b_srls_ppu
2764	UINT64_C(`503718016`), // V6_vabs_hf
2765	UINT64_C(`503718048`), // V6_vabs_sf
2766	UINT64_C(`503382144`), // V6_vabsb
2767	UINT64_C(`503382176`), // V6_vabsb_sat
2768	UINT64_C(`482344992`), // V6_vabsdiffh
2769	UINT64_C(`482344960`), // V6_vabsdiffub
2770	UINT64_C(`482345024`), // V6_vabsdiffuh
2771	UINT64_C(`482345056`), // V6_vabsdiffw
2772	UINT64_C(`503316480`), // V6_vabsh
2773	UINT64_C(`503316512`), // V6_vabsh_sat
2774	UINT64_C(`503316544`), // V6_vabsw
2775	UINT64_C(`503316576`), // V6_vabsw_sat
2776	UINT64_C(`526393440`), // V6_vadd_hf
2777	UINT64_C(`530587872`), // V6_vadd_hf_hf
2778	UINT64_C(`526393408`), // V6_vadd_qf16
2779	UINT64_C(`526393472`), // V6_vadd_qf16_mix
2780	UINT64_C(`530587648`), // V6_vadd_qf32
2781	UINT64_C(`530587712`), // V6_vadd_qf32_mix
2782	UINT64_C(`530587680`), // V6_vadd_sf
2783	UINT64_C(`490741952`), // V6_vadd_sf_bf
2784	UINT64_C(`528490624`), // V6_vadd_sf_hf
2785	UINT64_C(`528490688`), // V6_vadd_sf_sf
2786	UINT64_C(`530579648`), // V6_vaddb
2787	UINT64_C(`476053632`), // V6_vaddb_dv
2788	UINT64_C(`503390304`), // V6_vaddbnq
2789	UINT64_C(`503390208`), // V6_vaddbq
2790	UINT64_C(`520093696`), // V6_vaddbsat
2791	UINT64_C(`513802240`), // V6_vaddbsat_dv
2792	UINT64_C(`480256000`), // V6_vaddcarry
2793	UINT64_C(`497033216`), // V6_vaddcarryo
2794	UINT64_C(`494936064`), // V6_vaddcarrysat
2795	UINT64_C(`520101888`), // V6_vaddclbh
2796	UINT64_C(`520101920`), // V6_vaddclbw
2797	UINT64_C(`530579680`), // V6_vaddh
2798	UINT64_C(`476053664`), // V6_vaddh_dv
2799	UINT64_C(`503390336`), // V6_vaddhnq
2800	UINT64_C(`503390240`), // V6_vaddhq
2801	UINT64_C(`473956448`), // V6_vaddhsat
2802	UINT64_C(`478150688`), // V6_vaddhsat_dv
2803	UINT64_C(`480247936`), // V6_vaddhw
2804	UINT64_C(`471867456`), // V6_vaddhw_acc
2805	UINT64_C(`480247872`), // V6_vaddubh
2806	UINT64_C(`473964704`), // V6_vaddubh_acc
2807	UINT64_C(`473956384`), // V6_vaddubsat
2808	UINT64_C(`476053728`), // V6_vaddubsat_dv
2809	UINT64_C(`513802368`), // V6_vaddububb_sat
2810	UINT64_C(`473956416`), // V6_vadduhsat
2811	UINT64_C(`478150656`), // V6_vadduhsat_dv
2812	UINT64_C(`480247904`), // V6_vadduhw
2813	UINT64_C(`473964672`), // V6_vadduhw_acc
2814	UINT64_C(`526385184`), // V6_vadduwsat
2815	UINT64_C(`513802304`), // V6_vadduwsat_dv
2816	UINT64_C(`473956352`), // V6_vaddw
2817	UINT64_C(`476053696`), // V6_vaddw_dv
2818	UINT64_C(`503390368`), // V6_vaddwnq
2819	UINT64_C(`503390272`), // V6_vaddwq
2820	UINT64_C(`473956480`), // V6_vaddwsat
2821	UINT64_C(`478150720`), // V6_vaddwsat_dv
2822	UINT64_C(`452984832`), // V6_valignb
2823	UINT64_C(`505421824`), // V6_valignbi
2824	UINT64_C(`471859360`), // V6_vand
2825	UINT64_C(`429917344`), // V6_vandnqrt
2826	UINT64_C(`425731168`), // V6_vandnqrt_acc
2827	UINT64_C(`429916320`), // V6_vandqrt
2828	UINT64_C(`425730144`), // V6_vandqrt_acc
2829	UINT64_C(`503521312`), // V6_vandvnqv
2830	UINT64_C(`503521280`), // V6_vandvqv
2831	UINT64_C(`429916232`), // V6_vandvrt
2832	UINT64_C(`425730176`), // V6_vandvrt_acc
2833	UINT64_C(`427819008`), // V6_vaslh
2834	UINT64_C(`429924512`), // V6_vaslh_acc
2835	UINT64_C(`530579616`), // V6_vaslhv
2836	UINT64_C(`425722080`), // V6_vaslw
2837	UINT64_C(`425730112`), // V6_vaslw_acc
2838	UINT64_C(`530579584`), // V6_vaslwv
2839	UINT64_C(`446701792`), // V6_vasr_into
2840	UINT64_C(`425722048`), // V6_vasrh
2841	UINT64_C(`427827424`), // V6_vasrh_acc
2842	UINT64_C(`452993024`), // V6_vasrhbrndsat
2843	UINT64_C(`402653184`), // V6_vasrhbsat
2844	UINT64_C(`452985056`), // V6_vasrhubrndsat
2845	UINT64_C(`452985024`), // V6_vasrhubsat
2846	UINT64_C(`530579552`), // V6_vasrhv
2847	UINT64_C(`402653408`), // V6_vasruhubrndsat
2848	UINT64_C(`402661536`), // V6_vasruhubsat
2849	UINT64_C(`402653216`), // V6_vasruwuhrndsat
2850	UINT64_C(`402661504`), // V6_vasruwuhsat
2851	UINT64_C(`486539360`), // V6_vasrvuhubrndsat
2852	UINT64_C(`486539328`), // V6_vasrvuhubsat
2853	UINT64_C(`486539296`), // V6_vasrvwuhrndsat
2854	UINT64_C(`486539264`), // V6_vasrvwuhsat
2855	UINT64_C(`425722016`), // V6_vasrw
2856	UINT64_C(`425730208`), // V6_vasrw_acc
2857	UINT64_C(`452984896`), // V6_vasrwh
2858	UINT64_C(`452984960`), // V6_vasrwhrndsat
2859	UINT64_C(`452984928`), // V6_vasrwhsat
2860	UINT64_C(`402653248`), // V6_vasrwuhrndsat
2861	UINT64_C(`452984992`), // V6_vasrwuhsat
2862	UINT64_C(`530579456`), // V6_vasrwv
2863	UINT64_C(`503521504`), // V6_vassign
2864	UINT64_C(`503717920`), // V6_vassign_fp
2865	UINT64_C(`503382208`), // V6_vassign_tmp
2866	UINT64_C(`520102016`), // V6_vavgb
2867	UINT64_C(`520102048`), // V6_vavgbrnd
2868	UINT64_C(`482345152`), // V6_vavgh
2869	UINT64_C(`484442272`), // V6_vavghrnd
2870	UINT64_C(`482345088`), // V6_vavgub
2871	UINT64_C(`484442208`), // V6_vavgubrnd
2872	UINT64_C(`482345120`), // V6_vavguh
2873	UINT64_C(`484442240`), // V6_vavguhrnd
2874	UINT64_C(`520101952`), // V6_vavguw
2875	UINT64_C(`520101984`), // V6_vavguwrnd
2876	UINT64_C(`482345184`), // V6_vavgw
2877	UINT64_C(`484442304`), // V6_vavgwrnd
2878	UINT64_C(`442499072`), // V6_vccombine
2879	UINT64_C(`503447776`), // V6_vcl0h
2880	UINT64_C(`503447712`), // V6_vcl0w
2881	UINT64_C(`436207616`), // V6_vcmov
2882	UINT64_C(`524288224`), // V6_vcombine
2883	UINT64_C(`513802464`), // V6_vcombine_tmp
2884	UINT64_C(`503652416`), // V6_vconv_h_hf
2885	UINT64_C(`503652480`), // V6_vconv_hf_h
2886	UINT64_C(`503586912`), // V6_vconv_hf_qf16
2887	UINT64_C(`503587008`), // V6_vconv_hf_qf32
2888	UINT64_C(`503586816`), // V6_vconv_sf_qf32
2889	UINT64_C(`503652448`), // V6_vconv_sf_w
2890	UINT64_C(`503652384`), // V6_vconv_w_sf
2891	UINT64_C(`532684992`), // V6_vcvt_b_hf
2892	UINT64_C(`490741856`), // V6_vcvt_bf_sf
2893	UINT64_C(`503717888`), // V6_vcvt_h_hf
2894	UINT64_C(`503586880`), // V6_vcvt_hf_b
2895	UINT64_C(`503587040`), // V6_vcvt_hf_h
2896	UINT64_C(`526393376`), // V6_vcvt_hf_sf
2897	UINT64_C(`503586848`), // V6_vcvt_hf_ub
2898	UINT64_C(`503586976`), // V6_vcvt_hf_uh
2899	UINT64_C(`503586944`), // V6_vcvt_sf_hf
2900	UINT64_C(`532684960`), // V6_vcvt_ub_hf
2901	UINT64_C(`503652352`), // V6_vcvt_uh_hf
2902	UINT64_C(`434118720`), // V6_vdeal
2903	UINT64_C(`503316704`), // V6_vdealb
2904	UINT64_C(`522191072`), // V6_vdealb4w
2905	UINT64_C(`503316672`), // V6_vdealh
2906	UINT64_C(`452993152`), // V6_vdealvdd
2907	UINT64_C(`522190880`), // V6_vdelta
2908	UINT64_C(`530587840`), // V6_vdmpy_sf_hf
2909	UINT64_C(`473964640`), // V6_vdmpy_sf_hf_acc
2910	UINT64_C(`419430592`), // V6_vdmpybus
2911	UINT64_C(`419438784`), // V6_vdmpybus_acc
2912	UINT64_C(`419430624`), // V6_vdmpybus_dv
2913	UINT64_C(`419438816`), // V6_vdmpybus_dv_acc
2914	UINT64_C(`419430464`), // V6_vdmpyhb
2915	UINT64_C(`419438688`), // V6_vdmpyhb_acc
2916	UINT64_C(`421527680`), // V6_vdmpyhb_dv
2917	UINT64_C(`421535872`), // V6_vdmpyhb_dv_acc
2918	UINT64_C(`421527648`), // V6_vdmpyhisat
2919	UINT64_C(`421535808`), // V6_vdmpyhisat_acc
2920	UINT64_C(`421527616`), // V6_vdmpyhsat
2921	UINT64_C(`421535840`), // V6_vdmpyhsat_acc
2922	UINT64_C(`421527584`), // V6_vdmpyhsuisat
2923	UINT64_C(`421535776`), // V6_vdmpyhsuisat_acc
2924	UINT64_C(`421527552`), // V6_vdmpyhsusat
2925	UINT64_C(`421535744`), // V6_vdmpyhsusat_acc
2926	UINT64_C(`469762144`), // V6_vdmpyhvsat
2927	UINT64_C(`469770336`), // V6_vdmpyhvsat_acc
2928	UINT64_C(`419430560`), // V6_vdsaduh
2929	UINT64_C(`425730048`), // V6_vdsaduh_acc
2930	UINT64_C(`528482304`), // V6_veqb
2931	UINT64_C(`478158848`), // V6_veqb_and
2932	UINT64_C(`478158912`), // V6_veqb_or
2933	UINT64_C(`478158976`), // V6_veqb_xor
2934	UINT64_C(`528482308`), // V6_veqh
2935	UINT64_C(`478158852`), // V6_veqh_and
2936	UINT64_C(`478158916`), // V6_veqh_or
2937	UINT64_C(`478158980`), // V6_veqh_xor
2938	UINT64_C(`528482312`), // V6_veqw
2939	UINT64_C(`478158856`), // V6_veqw_and
2940	UINT64_C(`478158920`), // V6_veqw_or
2941	UINT64_C(`478158984`), // V6_veqw_xor
2942	UINT64_C(`476061760`), // V6_vfmax_hf
2943	UINT64_C(`476061792`), // V6_vfmax_sf
2944	UINT64_C(`476061696`), // V6_vfmin_hf
2945	UINT64_C(`476061728`), // V6_vfmin_sf
2946	UINT64_C(`503717952`), // V6_vfneg_hf
2947	UINT64_C(`503717984`), // V6_vfneg_sf
2948	UINT64_C(`788529408`), // V6_vgathermh
2949	UINT64_C(`788530432`), // V6_vgathermhq
2950	UINT64_C(`788529664`), // V6_vgathermhw
2951	UINT64_C(`788530688`), // V6_vgathermhwq
2952	UINT64_C(`788529152`), // V6_vgathermw
2953	UINT64_C(`788530176`), // V6_vgathermwq
2954	UINT64_C(`528482320`), // V6_vgtb
2955	UINT64_C(`478158864`), // V6_vgtb_and
2956	UINT64_C(`478158928`), // V6_vgtb_or
2957	UINT64_C(`478158992`), // V6_vgtb_xor
2958	UINT64_C(`478158968`), // V6_vgtbf
2959	UINT64_C(`478159056`), // V6_vgtbf_and
2960	UINT64_C(`478158904`), // V6_vgtbf_or
2961	UINT64_C(`478159088`), // V6_vgtbf_xor
2962	UINT64_C(`528482324`), // V6_vgth
2963	UINT64_C(`478158868`), // V6_vgth_and
2964	UINT64_C(`478158932`), // V6_vgth_or
2965	UINT64_C(`478158996`), // V6_vgth_xor
2966	UINT64_C(`478158964`), // V6_vgthf
2967	UINT64_C(`478159052`), // V6_vgthf_and
2968	UINT64_C(`478158900`), // V6_vgthf_or
2969	UINT64_C(`478159084`), // V6_vgthf_xor
2970	UINT64_C(`478158960`), // V6_vgtsf
2971	UINT64_C(`478159048`), // V6_vgtsf_and
2972	UINT64_C(`478158896`), // V6_vgtsf_or
2973	UINT64_C(`478159080`), // V6_vgtsf_xor
2974	UINT64_C(`528482336`), // V6_vgtub
2975	UINT64_C(`478158880`), // V6_vgtub_and
2976	UINT64_C(`478158944`), // V6_vgtub_or
2977	UINT64_C(`478159008`), // V6_vgtub_xor
2978	UINT64_C(`528482340`), // V6_vgtuh
2979	UINT64_C(`478158884`), // V6_vgtuh_and
2980	UINT64_C(`478158948`), // V6_vgtuh_or
2981	UINT64_C(`478159012`), // V6_vgtuh_xor
2982	UINT64_C(`528482344`), // V6_vgtuw
2983	UINT64_C(`478158888`), // V6_vgtuw_and
2984	UINT64_C(`478158952`), // V6_vgtuw_or
2985	UINT64_C(`478159016`), // V6_vgtuw_xor
2986	UINT64_C(`528482328`), // V6_vgtw
2987	UINT64_C(`478158872`), // V6_vgtw_and
2988	UINT64_C(`478158936`), // V6_vgtw_or
2989	UINT64_C(`478159000`), // V6_vgtw_xor
2990	UINT64_C(`503324800`), // V6_vhist
2991	UINT64_C(`503455872`), // V6_vhistq
2992	UINT64_C(`429924384`), // V6_vinsertwr
2993	UINT64_C(`452984864`), // V6_vlalignb
2994	UINT64_C(`509616128`), // V6_vlalignbi
2995	UINT64_C(`427819104`), // V6_vlsrb
2996	UINT64_C(`427819072`), // V6_vlsrh
2997	UINT64_C(`530579520`), // V6_vlsrhv
2998	UINT64_C(`427819040`), // V6_vlsrw
2999	UINT64_C(`530579488`), // V6_vlsrwv
3000	UINT64_C(`425721984`), // V6_vlut4
3001	UINT64_C(`452993056`), // V6_vlutvvb
3002	UINT64_C(`402653280`), // V6_vlutvvb_nm
3003	UINT64_C(`452993184`), // V6_vlutvvb_oracc
3004	UINT64_C(`482353152`), // V6_vlutvvb_oracci
3005	UINT64_C(`505413632`), // V6_vlutvvbi
3006	UINT64_C(`452993216`), // V6_vlutvwh
3007	UINT64_C(`402653312`), // V6_vlutvwh_nm
3008	UINT64_C(`452993248`), // V6_vlutvwh_oracc
3009	UINT64_C(`484450304`), // V6_vlutvwh_oracci
3010	UINT64_C(`509607936`), // V6_vlutvwhi
3011	UINT64_C(`490741984`), // V6_vmax_bf
3012	UINT64_C(`532684896`), // V6_vmax_hf
3013	UINT64_C(`532684832`), // V6_vmax_sf
3014	UINT64_C(`522191008`), // V6_vmaxb
3015	UINT64_C(`520093920`), // V6_vmaxh
3016	UINT64_C(`520093856`), // V6_vmaxub
3017	UINT64_C(`520093888`), // V6_vmaxuh
3018	UINT64_C(`522190848`), // V6_vmaxw
3019	UINT64_C(`490741760`), // V6_vmin_bf
3020	UINT64_C(`532684928`), // V6_vmin_hf
3021	UINT64_C(`532684864`), // V6_vmin_sf
3022	UINT64_C(`522190976`), // V6_vminb
3023	UINT64_C(`520093792`), // V6_vminh
3024	UINT64_C(`520093728`), // V6_vminub
3025	UINT64_C(`520093760`), // V6_vminuh
3026	UINT64_C(`520093824`), // V6_vminw
3027	UINT64_C(`421527744`), // V6_vmpabus
3028	UINT64_C(`421535936`), // V6_vmpabus_acc
3029	UINT64_C(`471859296`), // V6_vmpabusv
3030	UINT64_C(`425721952`), // V6_vmpabuu
3031	UINT64_C(`429924480`), // V6_vmpabuu_acc
3032	UINT64_C(`484442336`), // V6_vmpabuuv
3033	UINT64_C(`421527776`), // V6_vmpahb
3034	UINT64_C(`421535968`), // V6_vmpahb_acc
3035	UINT64_C(`427827328`), // V6_vmpahhsat
3036	UINT64_C(`427819168`), // V6_vmpauhb
3037	UINT64_C(`427827264`), // V6_vmpauhb_acc
3038	UINT64_C(`427827360`), // V6_vmpauhuhsat
3039	UINT64_C(`427827392`), // V6_vmpsuhuhsat
3040	UINT64_C(`528490592`), // V6_vmpy_hf_hf
3041	UINT64_C(`473964608`), // V6_vmpy_hf_hf_acc
3042	UINT64_C(`534782048`), // V6_vmpy_qf16
3043	UINT64_C(`534782080`), // V6_vmpy_qf16_hf
3044	UINT64_C(`534782112`), // V6_vmpy_qf16_mix_hf
3045	UINT64_C(`534781952`), // V6_vmpy_qf32
3046	UINT64_C(`534782176`), // V6_vmpy_qf32_hf
3047	UINT64_C(`528490496`), // V6_vmpy_qf32_mix_hf
3048	UINT64_C(`534782144`), // V6_vmpy_qf32_qf16
3049	UINT64_C(`534781984`), // V6_vmpy_qf32_sf
3050	UINT64_C(`490741888`), // V6_vmpy_sf_bf
3051	UINT64_C(`486547456`), // V6_vmpy_sf_bf_acc
3052	UINT64_C(`528490560`), // V6_vmpy_sf_hf
3053	UINT64_C(`473964576`), // V6_vmpy_sf_hf_acc
3054	UINT64_C(`528490528`), // V6_vmpy_sf_sf
3055	UINT64_C(`421527712`), // V6_vmpybus
3056	UINT64_C(`421535904`), // V6_vmpybus_acc
3057	UINT64_C(`469762240`), // V6_vmpybusv
3058	UINT64_C(`469770432`), // V6_vmpybusv_acc
3059	UINT64_C(`469762176`), // V6_vmpybv
3060	UINT64_C(`469770368`), // V6_vmpybv_acc
3061	UINT64_C(`534773920`), // V6_vmpyewuh
3062	UINT64_C(`513802432`), // V6_vmpyewuh_64
3063	UINT64_C(`423624704`), // V6_vmpyh
3064	UINT64_C(`429924544`), // V6_vmpyh_acc
3065	UINT64_C(`423632896`), // V6_vmpyhsat_acc
3066	UINT64_C(`423624768`), // V6_vmpyhsrs
3067	UINT64_C(`423624736`), // V6_vmpyhss
3068	UINT64_C(`471859264`), // V6_vmpyhus
3069	UINT64_C(`471867424`), // V6_vmpyhus_acc
3070	UINT64_C(`469762272`), // V6_vmpyhv
3071	UINT64_C(`469770464`), // V6_vmpyhv_acc
3072	UINT64_C(`471859232`), // V6_vmpyhvsrs
3073	UINT64_C(`526385152`), // V6_vmpyieoh
3074	UINT64_C(`473964544`), // V6_vmpyiewh_acc
3075	UINT64_C(`532676608`), // V6_vmpyiewuh
3076	UINT64_C(`471867552`), // V6_vmpyiewuh_acc
3077	UINT64_C(`471859328`), // V6_vmpyih
3078	UINT64_C(`471867520`), // V6_vmpyih_acc
3079	UINT64_C(`425721856`), // V6_vmpyihb
3080	UINT64_C(`425730080`), // V6_vmpyihb_acc
3081	UINT64_C(`532676640`), // V6_vmpyiowh
3082	UINT64_C(`429916160`), // V6_vmpyiwb
3083	UINT64_C(`423632960`), // V6_vmpyiwb_acc
3084	UINT64_C(`427819232`), // V6_vmpyiwh
3085	UINT64_C(`423632992`), // V6_vmpyiwh_acc
3086	UINT64_C(`427819200`), // V6_vmpyiwub
3087	UINT64_C(`427827232`), // V6_vmpyiwub_acc
3088	UINT64_C(`534773984`), // V6_vmpyowh
3089	UINT64_C(`471867488`), // V6_vmpyowh_64_acc
3090	UINT64_C(`524288000`), // V6_vmpyowh_rnd
3091	UINT64_C(`471867616`), // V6_vmpyowh_rnd_sacc
3092	UINT64_C(`471867584`), // V6_vmpyowh_sacc
3093	UINT64_C(`432013312`), // V6_vmpyub
3094	UINT64_C(`427827200`), // V6_vmpyub_acc
3095	UINT64_C(`469762208`), // V6_vmpyubv
3096	UINT64_C(`469770400`), // V6_vmpyubv_acc
3097	UINT64_C(`423624800`), // V6_vmpyuh
3098	UINT64_C(`423632928`), // V6_vmpyuh_acc
3099	UINT64_C(`425721920`), // V6_vmpyuhe
3100	UINT64_C(`427827296`), // V6_vmpyuhe_acc
3101	UINT64_C(`471859200`), // V6_vmpyuhv
3102	UINT64_C(`471867392`), // V6_vmpyuhv_acc
3103	UINT64_C(`532685024`), // V6_vmpyuhvs
3104	UINT64_C(`518004736`), // V6_vmux
3105	UINT64_C(`520102080`), // V6_vnavgb
3106	UINT64_C(`484442144`), // V6_vnavgh
3107	UINT64_C(`484442112`), // V6_vnavgub
3108	UINT64_C(`484442176`), // V6_vnavgw
3109	UINT64_C(`440401920`), // V6_vnccombine
3110	UINT64_C(`438304768`), // V6_vncmov
3111	UINT64_C(`503513248`), // V6_vnormamth
3112	UINT64_C(`503513216`), // V6_vnormamtw
3113	UINT64_C(`503316608`), // V6_vnot
3114	UINT64_C(`471859392`), // V6_vor
3115	UINT64_C(`532676672`), // V6_vpackeb
3116	UINT64_C(`532676704`), // V6_vpackeh
3117	UINT64_C(`532676800`), // V6_vpackhb_sat
3118	UINT64_C(`532676768`), // V6_vpackhub_sat
3119	UINT64_C(`534773792`), // V6_vpackob
3120	UINT64_C(`534773824`), // V6_vpackoh
3121	UINT64_C(`534773760`), // V6_vpackwh_sat
3122	UINT64_C(`532676832`), // V6_vpackwuh_sat
3123	UINT64_C(`503447744`), // V6_vpopcounth
3124	UINT64_C(`503521344`), // V6_vprefixqb
3125	UINT64_C(`503521600`), // V6_vprefixqh
3126	UINT64_C(`503521856`), // V6_vprefixqw
3127	UINT64_C(`522190944`), // V6_vrdelta
3128	UINT64_C(`432013472`), // V6_vrmpybub_rtt
3129	UINT64_C(`429924352`), // V6_vrmpybub_rtt_acc
3130	UINT64_C(`419430528`), // V6_vrmpybus
3131	UINT64_C(`419438752`), // V6_vrmpybus_acc
3132	UINT64_C(`423624832`), // V6_vrmpybusi
3133	UINT64_C(`423633024`), // V6_vrmpybusi_acc
3134	UINT64_C(`469762112`), // V6_vrmpybusv
3135	UINT64_C(`469770304`), // V6_vrmpybusv_acc
3136	UINT64_C(`469762080`), // V6_vrmpybv
3137	UINT64_C(`469770272`), // V6_vrmpybv_acc
3138	UINT64_C(`419430496`), // V6_vrmpyub
3139	UINT64_C(`419438720`), // V6_vrmpyub_acc
3140	UINT64_C(`432013440`), // V6_vrmpyub_rtt
3141	UINT64_C(`429924576`), // V6_vrmpyub_rtt_acc
3142	UINT64_C(`429916352`), // V6_vrmpyubi
3143	UINT64_C(`425730240`), // V6_vrmpyubi_acc
3144	UINT64_C(`469762048`), // V6_vrmpyubv
3145	UINT64_C(`469770240`), // V6_vrmpyubv_acc
3146	UINT64_C(`434634752`), // V6_vrmpyzbb_rt
3147	UINT64_C(`432021568`), // V6_vrmpyzbb_rt_acc
3148	UINT64_C(`434110464`), // V6_vrmpyzbb_rx
3149	UINT64_C(`432545856`), // V6_vrmpyzbb_rx_acc
3150	UINT64_C(`435683392`), // V6_vrmpyzbub_rt
3151	UINT64_C(`433070112`), // V6_vrmpyzbub_rt_acc
3152	UINT64_C(`435159104`), // V6_vrmpyzbub_rx
3153	UINT64_C(`433594400`), // V6_vrmpyzbub_rx_acc
3154	UINT64_C(`434634784`), // V6_vrmpyzcb_rt
3155	UINT64_C(`432021600`), // V6_vrmpyzcb_rt_acc
3156	UINT64_C(`434110496`), // V6_vrmpyzcb_rx
3157	UINT64_C(`432545888`), // V6_vrmpyzcb_rx_acc
3158	UINT64_C(`434634816`), // V6_vrmpyzcbs_rt
3159	UINT64_C(`432021536`), // V6_vrmpyzcbs_rt_acc
3160	UINT64_C(`434110528`), // V6_vrmpyzcbs_rx
3161	UINT64_C(`432545824`), // V6_vrmpyzcbs_rx_acc
3162	UINT64_C(`435683328`), // V6_vrmpyznb_rt
3163	UINT64_C(`433070144`), // V6_vrmpyznb_rt_acc
3164	UINT64_C(`435159040`), // V6_vrmpyznb_rx
3165	UINT64_C(`433594432`), // V6_vrmpyznb_rx_acc
3166	UINT64_C(`425721888`), // V6_vror
3167	UINT64_C(`444604640`), // V6_vrotr
3168	UINT64_C(`526385344`), // V6_vroundhb
3169	UINT64_C(`526385376`), // V6_vroundhub
3170	UINT64_C(`534773856`), // V6_vrounduhub
3171	UINT64_C(`534773888`), // V6_vrounduwuh
3172	UINT64_C(`526385280`), // V6_vroundwh
3173	UINT64_C(`526385312`), // V6_vroundwuh
3174	UINT64_C(`423624896`), // V6_vrsadubi
3175	UINT64_C(`423633088`), // V6_vrsadubi_acc
3176	UINT64_C(`494936288`), // V6_vsatdw
3177	UINT64_C(`526385216`), // V6_vsathub
3178	UINT64_C(`522191040`), // V6_vsatuwuh
3179	UINT64_C(`526385248`), // V6_vsatwh
3180	UINT64_C(`503447648`), // V6_vsb
3181	UINT64_C(`790626336`), // V6_vscattermh
3182	UINT64_C(`790626464`), // V6_vscattermh_add
3183	UINT64_C(`796917888`), // V6_vscattermhq
3184	UINT64_C(`790626368`), // V6_vscattermhw
3185	UINT64_C(`790626496`), // V6_vscattermhw_add
3186	UINT64_C(`799014912`), // V6_vscattermhwq
3187	UINT64_C(`790626304`), // V6_vscattermw
3188	UINT64_C(`790626432`), // V6_vscattermw_add
3189	UINT64_C(`796917760`), // V6_vscattermwq
3190	UINT64_C(`503447680`), // V6_vsh
3191	UINT64_C(`524288096`), // V6_vshufeh
3192	UINT64_C(`434118688`), // V6_vshuff
3193	UINT64_C(`503447552`), // V6_vshuffb
3194	UINT64_C(`524288032`), // V6_vshuffeb
3195	UINT64_C(`503382240`), // V6_vshuffh
3196	UINT64_C(`524288064`), // V6_vshuffob
3197	UINT64_C(`452993120`), // V6_vshuffvdd
3198	UINT64_C(`524288192`), // V6_vshufoeb
3199	UINT64_C(`524288160`), // V6_vshufoeh
3200	UINT64_C(`524288128`), // V6_vshufoh
3201	UINT64_C(`526393536`), // V6_vsub_hf
3202	UINT64_C(`526393344`), // V6_vsub_hf_hf
3203	UINT64_C(`526393504`), // V6_vsub_qf16
3204	UINT64_C(`526393568`), // V6_vsub_qf16_mix
3205	UINT64_C(`530587744`), // V6_vsub_qf32
3206	UINT64_C(`530587808`), // V6_vsub_qf32_mix
3207	UINT64_C(`530587776`), // V6_vsub_sf
3208	UINT64_C(`490741920`), // V6_vsub_sf_bf
3209	UINT64_C(`528490656`), // V6_vsub_sf_hf
3210	UINT64_C(`528490720`), // V6_vsub_sf_sf
3211	UINT64_C(`473956512`), // V6_vsubb
3212	UINT64_C(`478150752`), // V6_vsubb_dv
3213	UINT64_C(`503455776`), // V6_vsubbnq
3214	UINT64_C(`503390400`), // V6_vsubbq
3215	UINT64_C(`522190912`), // V6_vsubbsat
3216	UINT64_C(`513802272`), // V6_vsubbsat_dv
3217	UINT64_C(`480256128`), // V6_vsubcarry
3218	UINT64_C(`497033344`), // V6_vsubcarryo
3219	UINT64_C(`473956544`), // V6_vsubh
3220	UINT64_C(`478150784`), // V6_vsubh_dv
3221	UINT64_C(`503455808`), // V6_vsubhnq
3222	UINT64_C(`503390432`), // V6_vsubhq
3223	UINT64_C(`476053568`), // V6_vsubhsat
3224	UINT64_C(`480247808`), // V6_vsubhsat_dv
3225	UINT64_C(`480248032`), // V6_vsubhw
3226	UINT64_C(`480247968`), // V6_vsububh
3227	UINT64_C(`476053504`), // V6_vsububsat
3228	UINT64_C(`478150848`), // V6_vsububsat_dv
3229	UINT64_C(`513802400`), // V6_vsubububb_sat
3230	UINT64_C(`476053536`), // V6_vsubuhsat
3231	UINT64_C(`478150880`), // V6_vsubuhsat_dv
3232	UINT64_C(`480248000`), // V6_vsubuhw
3233	UINT64_C(`532676736`), // V6_vsubuwsat
3234	UINT64_C(`513802336`), // V6_vsubuwsat_dv
3235	UINT64_C(`473956576`), // V6_vsubw
3236	UINT64_C(`478150816`), // V6_vsubw_dv
3237	UINT64_C(`503455840`), // V6_vsubwnq
3238	UINT64_C(`503455744`), // V6_vsubwq
3239	UINT64_C(`476053600`), // V6_vsubwsat
3240	UINT64_C(`480247840`), // V6_vsubwsat_dv
3241	UINT64_C(`513810432`), // V6_vswap
3242	UINT64_C(`419430400`), // V6_vtmpyb
3243	UINT64_C(`419438592`), // V6_vtmpyb_acc
3244	UINT64_C(`419430432`), // V6_vtmpybus
3245	UINT64_C(`419438624`), // V6_vtmpybus_acc
3246	UINT64_C(`429916288`), // V6_vtmpyhb
3247	UINT64_C(`419438656`), // V6_vtmpyhb_acc
3248	UINT64_C(`503382080`), // V6_vunpackb
3249	UINT64_C(`503382112`), // V6_vunpackh
3250	UINT64_C(`503324672`), // V6_vunpackob
3251	UINT64_C(`503324704`), // V6_vunpackoh
3252	UINT64_C(`503382016`), // V6_vunpackub
3253	UINT64_C(`503382048`), // V6_vunpackuh
3254	UINT64_C(`503325824`), // V6_vwhist128
3255	UINT64_C(`503326336`), // V6_vwhist128m
3256	UINT64_C(`503456896`), // V6_vwhist128q
3257	UINT64_C(`503457408`), // V6_vwhist128qm
3258	UINT64_C(`503325312`), // V6_vwhist256
3259	UINT64_C(`503325568`), // V6_vwhist256_sat
3260	UINT64_C(`503456384`), // V6_vwhist256q
3261	UINT64_C(`503456640`), // V6_vwhist256q_sat
3262	UINT64_C(`471859424`), // V6_vxor
3263	UINT64_C(`503447584`), // V6_vzb
3264	UINT64_C(`503447616`), // V6_vzh
3265	UINT64_C(`738197504`), // V6_zLd_ai
3266	UINT64_C(`754974720`), // V6_zLd_pi
3267	UINT64_C(`754974721`), // V6_zLd_ppu
3268	UINT64_C(`746586112`), // V6_zLd_pred_ai
3269	UINT64_C(`763363328`), // V6_zLd_pred_pi
3270	UINT64_C(`763363329`), // V6_zLd_pred_ppu
3271	UINT64_C(`429916448`), // V6_zextract
3272	UINT64_C(`2818572288`), // Y2_barrier
3273	UINT64_C(`1814036480`), // Y2_break
3274	UINT64_C(`1677721696`), // Y2_ciad
3275	UINT64_C(`1694498816`), // Y2_crswap0
3276	UINT64_C(`1677721632`), // Y2_cswi
3277	UINT64_C(`2684354560`), // Y2_dccleana
3278	UINT64_C(`2720006144`), // Y2_dccleanidx
3279	UINT64_C(`2688548864`), // Y2_dccleaninva
3280	UINT64_C(`2724200448`), // Y2_dccleaninvidx
3281	UINT64_C(`2483027968`), // Y2_dcfetchbo
3282	UINT64_C(`2686451712`), // Y2_dcinva
3283	UINT64_C(`2722103296`), // Y2_dcinvidx
3284	UINT64_C(`2717908992`), // Y2_dckill
3285	UINT64_C(`2753560576`), // Y2_dctagr
3286	UINT64_C(`2751463424`), // Y2_dctagw
3287	UINT64_C(`2696937472`), // Y2_dczeroa
3288	UINT64_C(`1711276032`), // Y2_getimask
3289	UINT64_C(`1717567488`), // Y2_iassignr
3290	UINT64_C(`1677721664`), // Y2_iassignw
3291	UINT64_C(`1436549120`), // Y2_icdatar
3292	UINT64_C(`1438654464`), // Y2_icdataw
3293	UINT64_C(`1455423488`), // Y2_icinva
3294	UINT64_C(`1455425536`), // Y2_icinvidx
3295	UINT64_C(`1455427584`), // Y2_ickill
3296	UINT64_C(`1440743424`), // Y2_ictagr
3297	UINT64_C(`1438646272`), // Y2_ictagw
3298	UINT64_C(`1472200706`), // Y2_isync
3299	UINT64_C(`1814036576`), // Y2_k0lock
3300	UINT64_C(`1814036608`), // Y2_k0unlock
3301	UINT64_C(`2824863744`), // Y2_l2cleaninvidx
3302	UINT64_C(`2820669440`), // Y2_l2kill
3303	UINT64_C(`1681915936`), // Y2_resume
3304	UINT64_C(`1686110208`), // Y2_setimask
3305	UINT64_C(`1686110240`), // Y2_setprio
3306	UINT64_C(`1684013088`), // Y2_start
3307	UINT64_C(`1684013056`), // Y2_stop
3308	UINT64_C(`1677721600`), // Y2_swi
3309	UINT64_C(`2822766592`), // Y2_syncht
3310	UINT64_C(`1853882368`), // Y2_tfrscrr
3311	UINT64_C(`1728053248`), // Y2_tfrsrcr
3312	UINT64_C(`1814036512`), // Y2_tlblock
3313	UINT64_C(`1820327936`), // Y2_tlbp
3314	UINT64_C(`1816133632`), // Y2_tlbr
3315	UINT64_C(`1814036544`), // Y2_tlbunlock
3316	UINT64_C(`1811939328`), // Y2_tlbw
3317	UINT64_C(`1681915904`), // Y2_wait
3318	UINT64_C(`1696595968`), // Y4_crswap1
3319	UINT64_C(`1837105152`), // Y4_crswap10
3320	UINT64_C(`2785017856`), // Y4_l2fetch
3321	UINT64_C(`2757754880`), // Y4_l2tagr
3322	UINT64_C(`2755657728`), // Y4_l2tagw
3323	UINT64_C(`1684013120`), // Y4_nmi
3324	UINT64_C(`1686110304`), // Y4_siad
3325	UINT64_C(`1862270976`), // Y4_tfrscpp
3326	UINT64_C(`1828716544`), // Y4_tfrspcp
3327	UINT64_C(`1648361472`), // Y4_trace
3328	UINT64_C(`1824522240`), // Y5_ctlbw
3329	UINT64_C(`2787115008`), // Y5_l2cleanidx
3330	UINT64_C(`2793406464`), // Y5_l2fetch
3331	UINT64_C(`2820673536`), // Y5_l2gclean
3332	UINT64_C(`2820675584`), // Y5_l2gcleaninv
3333	UINT64_C(`2820671488`), // Y5_l2gunlock
3334	UINT64_C(`2789212160`), // Y5_l2invidx
3335	UINT64_C(`2699042816`), // Y5_l2locka
3336	UINT64_C(`2791309312`), // Y5_l2unlocka
3337	UINT64_C(`1822425088`), // Y5_tlbasidi
3338	UINT64_C(`1826619392`), // Y5_tlboc
3339	UINT64_C(`1648361504`), // Y6_diag
3340	UINT64_C(`1648361536`), // Y6_diag0
3341	UINT64_C(`1648361568`), // Y6_diag1
3342	UINT64_C(`2785017920`), // Y6_dmlink
3343	UINT64_C(`2818572384`), // Y6_dmpause
3344	UINT64_C(`2818572352`), // Y6_dmpoll
3345	UINT64_C(`2785017984`), // Y6_dmresume
3346	UINT64_C(`2785017888`), // Y6_dmstart
3347	UINT64_C(`2818572320`), // Y6_dmwait
3348	UINT64_C(`2797600768`), // Y6_l2gcleaninvpa
3349	UINT64_C(`2795503616`), // Y6_l2gcleanpa
3350	UINT64_C(`3581935616`), // dep_A2_addsat
3351	UINT64_C(`3581935744`), // dep_A2_subsat
3352	UINT64_C(`3556769792`), // dep_S2_packhl
3353	UINT64_C(`0`), // invalid_decode
3354	UINT64_C(`0`)
3355	};
3356	const unsigned opcode = MI.getOpcode();
3357	uint64_t Value = InstBits[opcode];
3358	uint64_t op = `0`;
3359	(void)op; // suppress warning
3360	switch (opcode) {
3361	case Hexagon::A2_nop:
3362	case Hexagon::CONST32:
3363	case Hexagon::CONST64:
3364	case Hexagon::DuplexIClass0:
3365	case Hexagon::DuplexIClass1:
3366	case Hexagon::DuplexIClass2:
3367	case Hexagon::DuplexIClass3:
3368	case Hexagon::DuplexIClass4:
3369	case Hexagon::DuplexIClass5:
3370	case Hexagon::DuplexIClass6:
3371	case Hexagon::DuplexIClass7:
3372	case Hexagon::DuplexIClass8:
3373	case Hexagon::DuplexIClass9:
3374	case Hexagon::DuplexIClassA:
3375	case Hexagon::DuplexIClassB:
3376	case Hexagon::DuplexIClassC:
3377	case Hexagon::DuplexIClassD:
3378	case Hexagon::DuplexIClassE:
3379	case Hexagon::DuplexIClassF:
3380	case Hexagon::J2_rte:
3381	case Hexagon::J2_unpause:
3382	case Hexagon::SL2_deallocframe:
3383	case Hexagon::SL2_jumpr31:
3384	case Hexagon::SL2_jumpr31_f:
3385	case Hexagon::SL2_jumpr31_fnew:
3386	case Hexagon::SL2_jumpr31_t:
3387	case Hexagon::SL2_jumpr31_tnew:
3388	case Hexagon::SL2_return:
3389	case Hexagon::SL2_return_f:
3390	case Hexagon::SL2_return_fnew:
3391	case Hexagon::SL2_return_t:
3392	case Hexagon::SL2_return_tnew:
3393	case Hexagon::TFRI64_V2_ext:
3394	case Hexagon::TFRI64_V4:
3395	case Hexagon::V6_vhist:
3396	case Hexagon::V6_vwhist128:
3397	case Hexagon::V6_vwhist256:
3398	case Hexagon::V6_vwhist256_sat:
3399	case Hexagon::Y2_barrier:
3400	case Hexagon::Y2_break:
3401	case Hexagon::Y2_dckill:
3402	case Hexagon::Y2_ickill:
3403	case Hexagon::Y2_isync:
3404	case Hexagon::Y2_k0lock:
3405	case Hexagon::Y2_k0unlock:
3406	case Hexagon::Y2_l2kill:
3407	case Hexagon::Y2_syncht:
3408	case Hexagon::Y2_tlblock:
3409	case Hexagon::Y2_tlbunlock:
3410	case Hexagon::Y5_l2gclean:
3411	case Hexagon::Y5_l2gcleaninv:
3412	case Hexagon::Y5_l2gunlock:
3413	case Hexagon::invalid_decode: {
3414	break;
3415	}
3416	case Hexagon::A2_tfrcrr: {
3417	// op: Cs32
3418	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3419	op &= UINT64_C(`31`);
3420	op <<= `16`;
3421	Value \|= op;
3422	// op: Rd32
3423	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3424	op &= UINT64_C(`31`);
3425	Value \|= op;
3426	break;
3427	}
3428	case Hexagon::A4_tfrcpp: {
3429	// op: Css32
3430	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3431	op &= UINT64_C(`31`);
3432	op <<= `16`;
3433	Value \|= op;
3434	// op: Rdd32
3435	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3436	op &= UINT64_C(`31`);
3437	Value \|= op;
3438	break;
3439	}
3440	case Hexagon::G4_tfrgcrr: {
3441	// op: Gs32
3442	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3443	op &= UINT64_C(`31`);
3444	op <<= `16`;
3445	Value \|= op;
3446	// op: Rd32
3447	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3448	op &= UINT64_C(`31`);
3449	Value \|= op;
3450	break;
3451	}
3452	case Hexagon::G4_tfrgcpp: {
3453	// op: Gss32
3454	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3455	op &= UINT64_C(`31`);
3456	op <<= `16`;
3457	Value \|= op;
3458	// op: Rdd32
3459	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3460	op &= UINT64_C(`31`);
3461	Value \|= op;
3462	break;
3463	}
3464	case Hexagon::J4_cmpeqi_f_jumpnv_nt:
3465	case Hexagon::J4_cmpeqi_f_jumpnv_t:
3466	case Hexagon::J4_cmpeqi_t_jumpnv_nt:
3467	case Hexagon::J4_cmpeqi_t_jumpnv_t:
3468	case Hexagon::J4_cmpgti_f_jumpnv_nt:
3469	case Hexagon::J4_cmpgti_f_jumpnv_t:
3470	case Hexagon::J4_cmpgti_t_jumpnv_nt:
3471	case Hexagon::J4_cmpgti_t_jumpnv_t:
3472	case Hexagon::J4_cmpgtui_f_jumpnv_nt:
3473	case Hexagon::J4_cmpgtui_f_jumpnv_t:
3474	case Hexagon::J4_cmpgtui_t_jumpnv_nt:
3475	case Hexagon::J4_cmpgtui_t_jumpnv_t: {
3476	// op: II
3477	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3478	op &= UINT64_C(`31`);
3479	op <<= `8`;
3480	Value \|= op;
3481	// op: Ii
3482	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3483	Value \|= (op & UINT64_C(`1536`)) << `11`;
3484	Value \|= (op & UINT64_C(`508`)) >> `1`;
3485	// op: Ns8
3486	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3487	op &= UINT64_C(`7`);
3488	op <<= `16`;
3489	Value \|= op;
3490	break;
3491	}
3492	case Hexagon::J4_cmpeqi_fp0_jump_nt:
3493	case Hexagon::J4_cmpeqi_fp0_jump_t:
3494	case Hexagon::J4_cmpeqi_fp1_jump_nt:
3495	case Hexagon::J4_cmpeqi_fp1_jump_t:
3496	case Hexagon::J4_cmpeqi_tp0_jump_nt:
3497	case Hexagon::J4_cmpeqi_tp0_jump_t:
3498	case Hexagon::J4_cmpeqi_tp1_jump_nt:
3499	case Hexagon::J4_cmpeqi_tp1_jump_t:
3500	case Hexagon::J4_cmpgti_fp0_jump_nt:
3501	case Hexagon::J4_cmpgti_fp0_jump_t:
3502	case Hexagon::J4_cmpgti_fp1_jump_nt:
3503	case Hexagon::J4_cmpgti_fp1_jump_t:
3504	case Hexagon::J4_cmpgti_tp0_jump_nt:
3505	case Hexagon::J4_cmpgti_tp0_jump_t:
3506	case Hexagon::J4_cmpgti_tp1_jump_nt:
3507	case Hexagon::J4_cmpgti_tp1_jump_t:
3508	case Hexagon::J4_cmpgtui_fp0_jump_nt:
3509	case Hexagon::J4_cmpgtui_fp0_jump_t:
3510	case Hexagon::J4_cmpgtui_fp1_jump_nt:
3511	case Hexagon::J4_cmpgtui_fp1_jump_t:
3512	case Hexagon::J4_cmpgtui_tp0_jump_nt:
3513	case Hexagon::J4_cmpgtui_tp0_jump_t:
3514	case Hexagon::J4_cmpgtui_tp1_jump_nt:
3515	case Hexagon::J4_cmpgtui_tp1_jump_t: {
3516	// op: II
3517	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3518	op &= UINT64_C(`31`);
3519	op <<= `8`;
3520	Value \|= op;
3521	// op: Ii
3522	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3523	Value \|= (op & UINT64_C(`1536`)) << `11`;
3524	Value \|= (op & UINT64_C(`508`)) >> `1`;
3525	// op: Rs16
3526	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3527	op &= UINT64_C(`15`);
3528	op <<= `16`;
3529	Value \|= op;
3530	break;
3531	}
3532	case Hexagon::S4_storerbnew_ap:
3533	case Hexagon::S4_storerhnew_ap:
3534	case Hexagon::S4_storerinew_ap: {
3535	// op: II
3536	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3537	op &= UINT64_C(`63`);
3538	Value \|= op;
3539	// op: Nt8
3540	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3541	op &= UINT64_C(`7`);
3542	op <<= `8`;
3543	Value \|= op;
3544	// op: Re32
3545	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3546	op &= UINT64_C(`31`);
3547	op <<= `16`;
3548	Value \|= op;
3549	break;
3550	}
3551	case Hexagon::S4_storerb_ap:
3552	case Hexagon::S4_storerf_ap:
3553	case Hexagon::S4_storerh_ap:
3554	case Hexagon::S4_storeri_ap: {
3555	// op: II
3556	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3557	op &= UINT64_C(`63`);
3558	Value \|= op;
3559	// op: Rt32
3560	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3561	op &= UINT64_C(`31`);
3562	op <<= `8`;
3563	Value \|= op;
3564	// op: Re32
3565	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3566	op &= UINT64_C(`31`);
3567	op <<= `16`;
3568	Value \|= op;
3569	break;
3570	}
3571	case Hexagon::S4_storerd_ap: {
3572	// op: II
3573	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3574	op &= UINT64_C(`63`);
3575	Value \|= op;
3576	// op: Rtt32
3577	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3578	op &= UINT64_C(`31`);
3579	op <<= `8`;
3580	Value \|= op;
3581	// op: Re32
3582	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3583	op &= UINT64_C(`31`);
3584	op <<= `16`;
3585	Value \|= op;
3586	break;
3587	}
3588	case Hexagon::J4_jumpseti: {
3589	// op: II
3590	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3591	op &= UINT64_C(`63`);
3592	op <<= `8`;
3593	Value \|= op;
3594	// op: Ii
3595	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3596	Value \|= (op & UINT64_C(`1536`)) << `11`;
3597	Value \|= (op & UINT64_C(`508`)) >> `1`;
3598	// op: Rd16
3599	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3600	op &= UINT64_C(`15`);
3601	op <<= `16`;
3602	Value \|= op;
3603	break;
3604	}
3605	case Hexagon::L4_loadbsw2_ap:
3606	case Hexagon::L4_loadbzw2_ap:
3607	case Hexagon::L4_loadrb_ap:
3608	case Hexagon::L4_loadrh_ap:
3609	case Hexagon::L4_loadri_ap:
3610	case Hexagon::L4_loadrub_ap:
3611	case Hexagon::L4_loadruh_ap: {
3612	// op: II
3613	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3614	Value \|= (op & UINT64_C(`60`)) << `6`;
3615	Value \|= (op & UINT64_C(`3`)) << `5`;
3616	// op: Rd32
3617	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3618	op &= UINT64_C(`31`);
3619	Value \|= op;
3620	// op: Re32
3621	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3622	op &= UINT64_C(`31`);
3623	op <<= `16`;
3624	Value \|= op;
3625	break;
3626	}
3627	case Hexagon::L4_loadbsw4_ap:
3628	case Hexagon::L4_loadbzw4_ap:
3629	case Hexagon::L4_loadrd_ap: {
3630	// op: II
3631	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3632	Value \|= (op & UINT64_C(`60`)) << `6`;
3633	Value \|= (op & UINT64_C(`3`)) << `5`;
3634	// op: Rdd32
3635	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3636	op &= UINT64_C(`31`);
3637	Value \|= op;
3638	// op: Re32
3639	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3640	op &= UINT64_C(`31`);
3641	op <<= `16`;
3642	Value \|= op;
3643	break;
3644	}
3645	case Hexagon::L4_loadalignb_ap:
3646	case Hexagon::L4_loadalignh_ap: {
3647	// op: II
3648	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
3649	Value \|= (op & UINT64_C(`60`)) << `6`;
3650	Value \|= (op & UINT64_C(`3`)) << `5`;
3651	// op: Ryy32
3652	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3653	op &= UINT64_C(`31`);
3654	Value \|= op;
3655	// op: Re32
3656	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3657	op &= UINT64_C(`31`);
3658	op <<= `16`;
3659	Value \|= op;
3660	break;
3661	}
3662	case Hexagon::J2_call:
3663	case Hexagon::J2_jump: {
3664	// op: Ii
3665	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3666	Value \|= (op & UINT64_C(`16744448`)) << `1`;
3667	Value \|= (op & UINT64_C(`32764`)) >> `1`;
3668	break;
3669	}
3670	case Hexagon::PS_storerinewabs:
3671	case Hexagon::S2_storerinewgp: {
3672	// op: Ii
3673	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3674	Value \|= (op & UINT64_C(`196608`)) << `9`;
3675	Value \|= (op & UINT64_C(`63488`)) << `5`;
3676	Value \|= (op & UINT64_C(`1024`)) << `3`;
3677	Value \|= (op & UINT64_C(`1020`)) >> `2`;
3678	// op: Nt8
3679	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3680	op &= UINT64_C(`7`);
3681	op <<= `8`;
3682	Value \|= op;
3683	break;
3684	}
3685	case Hexagon::PS_storeriabs:
3686	case Hexagon::S2_storerigp: {
3687	// op: Ii
3688	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3689	Value \|= (op & UINT64_C(`196608`)) << `9`;
3690	Value \|= (op & UINT64_C(`63488`)) << `5`;
3691	Value \|= (op & UINT64_C(`1024`)) << `3`;
3692	Value \|= (op & UINT64_C(`1020`)) >> `2`;
3693	// op: Rt32
3694	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3695	op &= UINT64_C(`31`);
3696	op <<= `8`;
3697	Value \|= op;
3698	break;
3699	}
3700	case Hexagon::J2_trap0:
3701	case Hexagon::PS_trap1: {
3702	// op: Ii
3703	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3704	Value \|= (op & UINT64_C(`248`)) << `5`;
3705	Value \|= (op & UINT64_C(`7`)) << `2`;
3706	break;
3707	}
3708	case Hexagon::PS_storerdabs:
3709	case Hexagon::S2_storerdgp: {
3710	// op: Ii
3711	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3712	Value \|= (op & UINT64_C(`393216`)) << `8`;
3713	Value \|= (op & UINT64_C(`126976`)) << `4`;
3714	Value \|= (op & UINT64_C(`2048`)) << `2`;
3715	Value \|= (op & UINT64_C(`2040`)) >> `3`;
3716	// op: Rtt32
3717	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3718	op &= UINT64_C(`31`);
3719	op <<= `8`;
3720	Value \|= op;
3721	break;
3722	}
3723	case Hexagon::A4_ext: {
3724	// op: Ii
3725	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3726	Value \|= (op & UINT64_C(`4293918720`)) >> `4`;
3727	Value \|= (op & UINT64_C(`1048512`)) >> `6`;
3728	break;
3729	}
3730	case Hexagon::PS_storerbnewabs:
3731	case Hexagon::S2_storerbnewgp: {
3732	// op: Ii
3733	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3734	Value \|= (op & UINT64_C(`49152`)) << `11`;
3735	Value \|= (op & UINT64_C(`15872`)) << `7`;
3736	Value \|= (op & UINT64_C(`256`)) << `5`;
3737	Value \|= (op & UINT64_C(`255`));
3738	// op: Nt8
3739	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3740	op &= UINT64_C(`7`);
3741	op <<= `8`;
3742	Value \|= op;
3743	break;
3744	}
3745	case Hexagon::PS_storerbabs:
3746	case Hexagon::S2_storerbgp: {
3747	// op: Ii
3748	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3749	Value \|= (op & UINT64_C(`49152`)) << `11`;
3750	Value \|= (op & UINT64_C(`15872`)) << `7`;
3751	Value \|= (op & UINT64_C(`256`)) << `5`;
3752	Value \|= (op & UINT64_C(`255`));
3753	// op: Rt32
3754	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3755	op &= UINT64_C(`31`);
3756	op <<= `8`;
3757	Value \|= op;
3758	break;
3759	}
3760	case Hexagon::J2_loop0i:
3761	case Hexagon::J2_loop1i:
3762	case Hexagon::J2_ploop1si:
3763	case Hexagon::J2_ploop2si:
3764	case Hexagon::J2_ploop3si: {
3765	// op: Ii
3766	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3767	Value \|= (op & UINT64_C(`496`)) << `4`;
3768	Value \|= (op & UINT64_C(`12`)) << `1`;
3769	// op: II
3770	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3771	Value \|= (op & UINT64_C(`992`)) << `11`;
3772	Value \|= (op & UINT64_C(`28`)) << `3`;
3773	Value \|= (op & UINT64_C(`3`));
3774	break;
3775	}
3776	case Hexagon::J2_loop0r:
3777	case Hexagon::J2_loop1r:
3778	case Hexagon::J2_ploop1sr:
3779	case Hexagon::J2_ploop2sr:
3780	case Hexagon::J2_ploop3sr: {
3781	// op: Ii
3782	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3783	Value \|= (op & UINT64_C(`496`)) << `4`;
3784	Value \|= (op & UINT64_C(`12`)) << `1`;
3785	// op: Rs32
3786	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3787	op &= UINT64_C(`31`);
3788	op <<= `16`;
3789	Value \|= op;
3790	break;
3791	}
3792	case Hexagon::J2_pause: {
3793	// op: Ii
3794	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3795	Value \|= (op & UINT64_C(`768`)) << `8`;
3796	Value \|= (op & UINT64_C(`248`)) << `5`;
3797	Value \|= (op & UINT64_C(`7`)) << `2`;
3798	break;
3799	}
3800	case Hexagon::PS_storerhnewabs:
3801	case Hexagon::S2_storerhnewgp: {
3802	// op: Ii
3803	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3804	Value \|= (op & UINT64_C(`98304`)) << `10`;
3805	Value \|= (op & UINT64_C(`31744`)) << `6`;
3806	Value \|= (op & UINT64_C(`512`)) << `4`;
3807	Value \|= (op & UINT64_C(`510`)) >> `1`;
3808	// op: Nt8
3809	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3810	op &= UINT64_C(`7`);
3811	op <<= `8`;
3812	Value \|= op;
3813	break;
3814	}
3815	case Hexagon::PS_storerfabs:
3816	case Hexagon::PS_storerhabs:
3817	case Hexagon::S2_storerfgp:
3818	case Hexagon::S2_storerhgp: {
3819	// op: Ii
3820	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3821	Value \|= (op & UINT64_C(`98304`)) << `10`;
3822	Value \|= (op & UINT64_C(`31744`)) << `6`;
3823	Value \|= (op & UINT64_C(`512`)) << `4`;
3824	Value \|= (op & UINT64_C(`510`)) >> `1`;
3825	// op: Rt32
3826	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3827	op &= UINT64_C(`31`);
3828	op <<= `8`;
3829	Value \|= op;
3830	break;
3831	}
3832	case Hexagon::V6_vwhist128m: {
3833	// op: Ii
3834	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3835	op &= UINT64_C(`1`);
3836	op <<= `8`;
3837	Value \|= op;
3838	break;
3839	}
3840	case Hexagon::SS2_storew_sp: {
3841	// op: Ii
3842	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3843	op &= UINT64_C(`124`);
3844	op <<= `2`;
3845	Value \|= op;
3846	// op: Rt16
3847	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3848	op &= UINT64_C(`15`);
3849	Value \|= op;
3850	break;
3851	}
3852	case Hexagon::SS2_allocframe: {
3853	// op: Ii
3854	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3855	op &= UINT64_C(`248`);
3856	op <<= `1`;
3857	Value \|= op;
3858	break;
3859	}
3860	case Hexagon::SS2_stored_sp: {
3861	// op: Ii
3862	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3863	op &= UINT64_C(`504`);
3864	Value \|= op;
3865	// op: Rtt8
3866	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3867	op &= UINT64_C(`7`);
3868	Value \|= op;
3869	break;
3870	}
3871	case Hexagon::S2_storerd_io: {
3872	// op: Ii
3873	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3874	Value \|= (op & UINT64_C(`12288`)) << `13`;
3875	Value \|= (op & UINT64_C(`2048`)) << `2`;
3876	Value \|= (op & UINT64_C(`2040`)) >> `3`;
3877	// op: Rs32
3878	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3879	op &= UINT64_C(`31`);
3880	op <<= `16`;
3881	Value \|= op;
3882	// op: Rtt32
3883	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3884	op &= UINT64_C(`31`);
3885	op <<= `8`;
3886	Value \|= op;
3887	break;
3888	}
3889	case Hexagon::J4_tstbit0_f_jumpnv_nt:
3890	case Hexagon::J4_tstbit0_f_jumpnv_t:
3891	case Hexagon::J4_tstbit0_t_jumpnv_nt:
3892	case Hexagon::J4_tstbit0_t_jumpnv_t: {
3893	// op: Ii
3894	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3895	Value \|= (op & UINT64_C(`1536`)) << `11`;
3896	Value \|= (op & UINT64_C(`508`)) >> `1`;
3897	// op: Ns8
3898	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3899	op &= UINT64_C(`7`);
3900	op <<= `16`;
3901	Value \|= op;
3902	break;
3903	}
3904	case Hexagon::J4_tstbit0_fp0_jump_nt:
3905	case Hexagon::J4_tstbit0_fp0_jump_t:
3906	case Hexagon::J4_tstbit0_fp1_jump_nt:
3907	case Hexagon::J4_tstbit0_fp1_jump_t:
3908	case Hexagon::J4_tstbit0_tp0_jump_nt:
3909	case Hexagon::J4_tstbit0_tp0_jump_t:
3910	case Hexagon::J4_tstbit0_tp1_jump_nt:
3911	case Hexagon::J4_tstbit0_tp1_jump_t: {
3912	// op: Ii
3913	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3914	Value \|= (op & UINT64_C(`1536`)) << `11`;
3915	Value \|= (op & UINT64_C(`508`)) >> `1`;
3916	// op: Rs16
3917	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3918	op &= UINT64_C(`15`);
3919	op <<= `16`;
3920	Value \|= op;
3921	break;
3922	}
3923	case Hexagon::S2_storerbnew_io: {
3924	// op: Ii
3925	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3926	Value \|= (op & UINT64_C(`1536`)) << `16`;
3927	Value \|= (op & UINT64_C(`256`)) << `5`;
3928	Value \|= (op & UINT64_C(`255`));
3929	// op: Rs32
3930	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3931	op &= UINT64_C(`31`);
3932	op <<= `16`;
3933	Value \|= op;
3934	// op: Nt8
3935	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3936	op &= UINT64_C(`7`);
3937	op <<= `8`;
3938	Value \|= op;
3939	break;
3940	}
3941	case Hexagon::S2_storerb_io: {
3942	// op: Ii
3943	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3944	Value \|= (op & UINT64_C(`1536`)) << `16`;
3945	Value \|= (op & UINT64_C(`256`)) << `5`;
3946	Value \|= (op & UINT64_C(`255`));
3947	// op: Rs32
3948	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3949	op &= UINT64_C(`31`);
3950	op <<= `16`;
3951	Value \|= op;
3952	// op: Rt32
3953	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
3954	op &= UINT64_C(`31`);
3955	op <<= `8`;
3956	Value \|= op;
3957	break;
3958	}
3959	case Hexagon::J2_jumprgtez:
3960	case Hexagon::J2_jumprgtezpt:
3961	case Hexagon::J2_jumprltez:
3962	case Hexagon::J2_jumprltezpt:
3963	case Hexagon::J2_jumprnz:
3964	case Hexagon::J2_jumprnzpt:
3965	case Hexagon::J2_jumprz:
3966	case Hexagon::J2_jumprzpt: {
3967	// op: Ii
3968	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3969	Value \|= (op & UINT64_C(`16384`)) << `7`;
3970	Value \|= (op & UINT64_C(`8192`));
3971	Value \|= (op & UINT64_C(`8188`)) >> `1`;
3972	// op: Rs32
3973	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3974	op &= UINT64_C(`31`);
3975	op <<= `16`;
3976	Value \|= op;
3977	break;
3978	}
3979	case Hexagon::L2_loadrigp:
3980	case Hexagon::PS_loadriabs: {
3981	// op: Ii
3982	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3983	Value \|= (op & UINT64_C(`196608`)) << `9`;
3984	Value \|= (op & UINT64_C(`63488`)) << `5`;
3985	Value \|= (op & UINT64_C(`2044`)) << `3`;
3986	// op: Rd32
3987	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
3988	op &= UINT64_C(`31`);
3989	Value \|= op;
3990	break;
3991	}
3992	case Hexagon::S4_storerbnew_ur:
3993	case Hexagon::S4_storerhnew_ur:
3994	case Hexagon::S4_storerinew_ur: {
3995	// op: Ii
3996	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
3997	Value \|= (op & UINT64_C(`2`)) << `12`;
3998	Value \|= (op & UINT64_C(`1`)) << `6`;
3999	// op: II
4000	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4001	op &= UINT64_C(`63`);
4002	Value \|= op;
4003	// op: Ru32
4004	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4005	op &= UINT64_C(`31`);
4006	op <<= `16`;
4007	Value \|= op;
4008	// op: Nt8
4009	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4010	op &= UINT64_C(`7`);
4011	op <<= `8`;
4012	Value \|= op;
4013	break;
4014	}
4015	case Hexagon::S4_storerb_ur:
4016	case Hexagon::S4_storerf_ur:
4017	case Hexagon::S4_storerh_ur:
4018	case Hexagon::S4_storeri_ur: {
4019	// op: Ii
4020	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4021	Value \|= (op & UINT64_C(`2`)) << `12`;
4022	Value \|= (op & UINT64_C(`1`)) << `6`;
4023	// op: II
4024	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4025	op &= UINT64_C(`63`);
4026	Value \|= op;
4027	// op: Ru32
4028	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4029	op &= UINT64_C(`31`);
4030	op <<= `16`;
4031	Value \|= op;
4032	// op: Rt32
4033	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4034	op &= UINT64_C(`31`);
4035	op <<= `8`;
4036	Value \|= op;
4037	break;
4038	}
4039	case Hexagon::S4_storerd_ur: {
4040	// op: Ii
4041	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4042	Value \|= (op & UINT64_C(`2`)) << `12`;
4043	Value \|= (op & UINT64_C(`1`)) << `6`;
4044	// op: II
4045	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4046	op &= UINT64_C(`63`);
4047	Value \|= op;
4048	// op: Ru32
4049	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4050	op &= UINT64_C(`31`);
4051	op <<= `16`;
4052	Value \|= op;
4053	// op: Rtt32
4054	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4055	op &= UINT64_C(`31`);
4056	op <<= `8`;
4057	Value \|= op;
4058	break;
4059	}
4060	case Hexagon::S4_addi_asl_ri:
4061	case Hexagon::S4_addi_lsr_ri:
4062	case Hexagon::S4_andi_asl_ri:
4063	case Hexagon::S4_andi_lsr_ri:
4064	case Hexagon::S4_ori_asl_ri:
4065	case Hexagon::S4_ori_lsr_ri:
4066	case Hexagon::S4_subi_asl_ri:
4067	case Hexagon::S4_subi_lsr_ri: {
4068	// op: Ii
4069	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4070	Value \|= (op & UINT64_C(`224`)) << `16`;
4071	Value \|= (op & UINT64_C(`16`)) << `9`;
4072	Value \|= (op & UINT64_C(`14`)) << `4`;
4073	Value \|= (op & UINT64_C(`1`)) << `3`;
4074	// op: II
4075	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4076	op &= UINT64_C(`31`);
4077	op <<= `8`;
4078	Value \|= op;
4079	// op: Rx32
4080	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4081	op &= UINT64_C(`31`);
4082	op <<= `16`;
4083	Value \|= op;
4084	break;
4085	}
4086	case Hexagon::S2_storerhnew_io: {
4087	// op: Ii
4088	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4089	Value \|= (op & UINT64_C(`3072`)) << `15`;
4090	Value \|= (op & UINT64_C(`512`)) << `4`;
4091	Value \|= (op & UINT64_C(`510`)) >> `1`;
4092	// op: Rs32
4093	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4094	op &= UINT64_C(`31`);
4095	op <<= `16`;
4096	Value \|= op;
4097	// op: Nt8
4098	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4099	op &= UINT64_C(`7`);
4100	op <<= `8`;
4101	Value \|= op;
4102	break;
4103	}
4104	case Hexagon::S2_storerf_io:
4105	case Hexagon::S2_storerh_io: {
4106	// op: Ii
4107	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4108	Value \|= (op & UINT64_C(`3072`)) << `15`;
4109	Value \|= (op & UINT64_C(`512`)) << `4`;
4110	Value \|= (op & UINT64_C(`510`)) >> `1`;
4111	// op: Rs32
4112	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4113	op &= UINT64_C(`31`);
4114	op <<= `16`;
4115	Value \|= op;
4116	// op: Rt32
4117	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4118	op &= UINT64_C(`31`);
4119	op <<= `8`;
4120	Value \|= op;
4121	break;
4122	}
4123	case Hexagon::L2_loadrdgp:
4124	case Hexagon::PS_loadrdabs: {
4125	// op: Ii
4126	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4127	Value \|= (op & UINT64_C(`393216`)) << `8`;
4128	Value \|= (op & UINT64_C(`126976`)) << `4`;
4129	Value \|= (op & UINT64_C(`4088`)) << `2`;
4130	// op: Rdd32
4131	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4132	op &= UINT64_C(`31`);
4133	Value \|= op;
4134	break;
4135	}
4136	case Hexagon::S4_pstorerbnewf_abs:
4137	case Hexagon::S4_pstorerbnewfnew_abs:
4138	case Hexagon::S4_pstorerbnewt_abs:
4139	case Hexagon::S4_pstorerbnewtnew_abs:
4140	case Hexagon::S4_pstorerhnewf_abs:
4141	case Hexagon::S4_pstorerhnewfnew_abs:
4142	case Hexagon::S4_pstorerhnewt_abs:
4143	case Hexagon::S4_pstorerhnewtnew_abs:
4144	case Hexagon::S4_pstorerinewf_abs:
4145	case Hexagon::S4_pstorerinewfnew_abs:
4146	case Hexagon::S4_pstorerinewt_abs:
4147	case Hexagon::S4_pstorerinewtnew_abs: {
4148	// op: Ii
4149	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4150	Value \|= (op & UINT64_C(`48`)) << `12`;
4151	Value \|= (op & UINT64_C(`15`)) << `3`;
4152	// op: Pv4
4153	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4154	op &= UINT64_C(`3`);
4155	Value \|= op;
4156	// op: Nt8
4157	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4158	op &= UINT64_C(`7`);
4159	op <<= `8`;
4160	Value \|= op;
4161	break;
4162	}
4163	case Hexagon::S4_pstorerbf_abs:
4164	case Hexagon::S4_pstorerbfnew_abs:
4165	case Hexagon::S4_pstorerbt_abs:
4166	case Hexagon::S4_pstorerbtnew_abs:
4167	case Hexagon::S4_pstorerff_abs:
4168	case Hexagon::S4_pstorerffnew_abs:
4169	case Hexagon::S4_pstorerft_abs:
4170	case Hexagon::S4_pstorerftnew_abs:
4171	case Hexagon::S4_pstorerhf_abs:
4172	case Hexagon::S4_pstorerhfnew_abs:
4173	case Hexagon::S4_pstorerht_abs:
4174	case Hexagon::S4_pstorerhtnew_abs:
4175	case Hexagon::S4_pstorerif_abs:
4176	case Hexagon::S4_pstorerifnew_abs:
4177	case Hexagon::S4_pstorerit_abs:
4178	case Hexagon::S4_pstoreritnew_abs: {
4179	// op: Ii
4180	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4181	Value \|= (op & UINT64_C(`48`)) << `12`;
4182	Value \|= (op & UINT64_C(`15`)) << `3`;
4183	// op: Pv4
4184	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4185	op &= UINT64_C(`3`);
4186	Value \|= op;
4187	// op: Rt32
4188	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4189	op &= UINT64_C(`31`);
4190	op <<= `8`;
4191	Value \|= op;
4192	break;
4193	}
4194	case Hexagon::S4_pstorerdf_abs:
4195	case Hexagon::S4_pstorerdfnew_abs:
4196	case Hexagon::S4_pstorerdt_abs:
4197	case Hexagon::S4_pstorerdtnew_abs: {
4198	// op: Ii
4199	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4200	Value \|= (op & UINT64_C(`48`)) << `12`;
4201	Value \|= (op & UINT64_C(`15`)) << `3`;
4202	// op: Pv4
4203	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4204	op &= UINT64_C(`3`);
4205	Value \|= op;
4206	// op: Rtt32
4207	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4208	op &= UINT64_C(`31`);
4209	op <<= `8`;
4210	Value \|= op;
4211	break;
4212	}
4213	case Hexagon::M4_mpyri_addi: {
4214	// op: Ii
4215	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4216	Value \|= (op & UINT64_C(`48`)) << `17`;
4217	Value \|= (op & UINT64_C(`8`)) << `10`;
4218	Value \|= (op & UINT64_C(`7`)) << `5`;
4219	// op: II
4220	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4221	Value \|= (op & UINT64_C(`32`)) << `18`;
4222	Value \|= (op & UINT64_C(`31`));
4223	// op: Rs32
4224	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4225	op &= UINT64_C(`31`);
4226	op <<= `16`;
4227	Value \|= op;
4228	// op: Rd32
4229	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4230	op &= UINT64_C(`31`);
4231	op <<= `8`;
4232	Value \|= op;
4233	break;
4234	}
4235	case Hexagon::M4_mpyrr_addi: {
4236	// op: Ii
4237	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4238	Value \|= (op & UINT64_C(`48`)) << `17`;
4239	Value \|= (op & UINT64_C(`8`)) << `10`;
4240	Value \|= (op & UINT64_C(`7`)) << `5`;
4241	// op: Rs32
4242	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4243	op &= UINT64_C(`31`);
4244	op <<= `16`;
4245	Value \|= op;
4246	// op: Rt32
4247	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4248	op &= UINT64_C(`31`);
4249	op <<= `8`;
4250	Value \|= op;
4251	// op: Rd32
4252	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4253	op &= UINT64_C(`31`);
4254	Value \|= op;
4255	break;
4256	}
4257	case Hexagon::L2_loadrbgp:
4258	case Hexagon::L2_loadrubgp:
4259	case Hexagon::PS_loadrbabs:
4260	case Hexagon::PS_loadrubabs: {
4261	// op: Ii
4262	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4263	Value \|= (op & UINT64_C(`49152`)) << `11`;
4264	Value \|= (op & UINT64_C(`15872`)) << `7`;
4265	Value \|= (op & UINT64_C(`511`)) << `5`;
4266	// op: Rd32
4267	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4268	op &= UINT64_C(`31`);
4269	Value \|= op;
4270	break;
4271	}
4272	case Hexagon::A2_tfrsi: {
4273	// op: Ii
4274	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4275	Value \|= (op & UINT64_C(`49152`)) << `8`;
4276	Value \|= (op & UINT64_C(`15872`)) << `7`;
4277	Value \|= (op & UINT64_C(`511`)) << `5`;
4278	// op: Rd32
4279	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4280	op &= UINT64_C(`31`);
4281	Value \|= op;
4282	break;
4283	}
4284	case Hexagon::F2_sfimm_n:
4285	case Hexagon::F2_sfimm_p: {
4286	// op: Ii
4287	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4288	Value \|= (op & UINT64_C(`512`)) << `12`;
4289	Value \|= (op & UINT64_C(`511`)) << `5`;
4290	// op: Rd32
4291	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4292	op &= UINT64_C(`31`);
4293	Value \|= op;
4294	break;
4295	}
4296	case Hexagon::F2_dfimm_n:
4297	case Hexagon::F2_dfimm_p: {
4298	// op: Ii
4299	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4300	Value \|= (op & UINT64_C(`512`)) << `12`;
4301	Value \|= (op & UINT64_C(`511`)) << `5`;
4302	// op: Rdd32
4303	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4304	op &= UINT64_C(`31`);
4305	Value \|= op;
4306	break;
4307	}
4308	case Hexagon::A2_subri: {
4309	// op: Ii
4310	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4311	Value \|= (op & UINT64_C(`512`)) << `12`;
4312	Value \|= (op & UINT64_C(`511`)) << `5`;
4313	// op: Rs32
4314	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4315	op &= UINT64_C(`31`);
4316	op <<= `16`;
4317	Value \|= op;
4318	// op: Rd32
4319	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4320	op &= UINT64_C(`31`);
4321	Value \|= op;
4322	break;
4323	}
4324	case Hexagon::S2_storerinew_io: {
4325	// op: Ii
4326	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4327	Value \|= (op & UINT64_C(`6144`)) << `14`;
4328	Value \|= (op & UINT64_C(`1024`)) << `3`;
4329	Value \|= (op & UINT64_C(`1020`)) >> `2`;
4330	// op: Rs32
4331	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4332	op &= UINT64_C(`31`);
4333	op <<= `16`;
4334	Value \|= op;
4335	// op: Nt8
4336	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4337	op &= UINT64_C(`7`);
4338	op <<= `8`;
4339	Value \|= op;
4340	break;
4341	}
4342	case Hexagon::S2_storeri_io: {
4343	// op: Ii
4344	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4345	Value \|= (op & UINT64_C(`6144`)) << `14`;
4346	Value \|= (op & UINT64_C(`1024`)) << `3`;
4347	Value \|= (op & UINT64_C(`1020`)) >> `2`;
4348	// op: Rs32
4349	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4350	op &= UINT64_C(`31`);
4351	op <<= `16`;
4352	Value \|= op;
4353	// op: Rt32
4354	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4355	op &= UINT64_C(`31`);
4356	op <<= `8`;
4357	Value \|= op;
4358	break;
4359	}
4360	case Hexagon::S4_lsli: {
4361	// op: Ii
4362	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4363	Value \|= (op & UINT64_C(`62`)) << `15`;
4364	Value \|= (op & UINT64_C(`1`)) << `5`;
4365	// op: Rt32
4366	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4367	op &= UINT64_C(`31`);
4368	op <<= `8`;
4369	Value \|= op;
4370	// op: Rd32
4371	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4372	op &= UINT64_C(`31`);
4373	Value \|= op;
4374	break;
4375	}
4376	case Hexagon::V6_vS32b_srls_ai:
4377	case Hexagon::V6_zLd_ai: {
4378	// op: Ii
4379	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4380	Value \|= (op & UINT64_C(`8`)) << `10`;
4381	Value \|= (op & UINT64_C(`7`)) << `8`;
4382	// op: Rt32
4383	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4384	op &= UINT64_C(`31`);
4385	op <<= `16`;
4386	Value \|= op;
4387	break;
4388	}
4389	case Hexagon::V6_vS32b_new_ai:
4390	case Hexagon::V6_vS32b_nt_new_ai: {
4391	// op: Ii
4392	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4393	Value \|= (op & UINT64_C(`8`)) << `10`;
4394	Value \|= (op & UINT64_C(`7`)) << `8`;
4395	// op: Rt32
4396	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4397	op &= UINT64_C(`31`);
4398	op <<= `16`;
4399	Value \|= op;
4400	// op: Os8
4401	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4402	op &= UINT64_C(`7`);
4403	Value \|= op;
4404	break;
4405	}
4406	case Hexagon::V6_vS32Ub_ai:
4407	case Hexagon::V6_vS32b_ai:
4408	case Hexagon::V6_vS32b_nt_ai: {
4409	// op: Ii
4410	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4411	Value \|= (op & UINT64_C(`8`)) << `10`;
4412	Value \|= (op & UINT64_C(`7`)) << `8`;
4413	// op: Rt32
4414	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4415	op &= UINT64_C(`31`);
4416	op <<= `16`;
4417	Value \|= op;
4418	// op: Vs32
4419	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4420	op &= UINT64_C(`31`);
4421	Value \|= op;
4422	break;
4423	}
4424	case Hexagon::L2_loadrhgp:
4425	case Hexagon::L2_loadruhgp:
4426	case Hexagon::PS_loadrhabs:
4427	case Hexagon::PS_loadruhabs: {
4428	// op: Ii
4429	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4430	Value \|= (op & UINT64_C(`98304`)) << `10`;
4431	Value \|= (op & UINT64_C(`31744`)) << `6`;
4432	Value \|= (op & UINT64_C(`1022`)) << `4`;
4433	// op: Rd32
4434	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4435	op &= UINT64_C(`31`);
4436	Value \|= op;
4437	break;
4438	}
4439	case Hexagon::J2_callf:
4440	case Hexagon::J2_callt:
4441	case Hexagon::J2_jumpf:
4442	case Hexagon::J2_jumpfnew:
4443	case Hexagon::J2_jumpfnewpt:
4444	case Hexagon::J2_jumpfpt:
4445	case Hexagon::J2_jumpt:
4446	case Hexagon::J2_jumptnew:
4447	case Hexagon::J2_jumptnewpt:
4448	case Hexagon::J2_jumptpt: {
4449	// op: Ii
4450	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4451	Value \|= (op & UINT64_C(`98304`)) << `7`;
4452	Value \|= (op & UINT64_C(`31744`)) << `6`;
4453	Value \|= (op & UINT64_C(`512`)) << `4`;
4454	Value \|= (op & UINT64_C(`508`)) >> `1`;
4455	// op: Pu4
4456	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4457	op &= UINT64_C(`3`);
4458	op <<= `8`;
4459	Value \|= op;
4460	break;
4461	}
4462	case Hexagon::V6_vwhist128qm: {
4463	// op: Ii
4464	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4465	op &= UINT64_C(`1`);
4466	op <<= `8`;
4467	Value \|= op;
4468	// op: Qv4
4469	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4470	op &= UINT64_C(`3`);
4471	op <<= `22`;
4472	Value \|= op;
4473	break;
4474	}
4475	case Hexagon::SL2_loadri_sp: {
4476	// op: Ii
4477	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4478	op &= UINT64_C(`124`);
4479	op <<= `2`;
4480	Value \|= op;
4481	// op: Rd16
4482	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4483	op &= UINT64_C(`15`);
4484	Value \|= op;
4485	break;
4486	}
4487	case Hexagon::S4_storeirh_io: {
4488	// op: Ii
4489	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4490	op &= UINT64_C(`126`);
4491	op <<= `6`;
4492	Value \|= op;
4493	// op: II
4494	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4495	Value \|= (op & UINT64_C(`128`)) << `6`;
4496	Value \|= (op & UINT64_C(`127`));
4497	// op: Rs32
4498	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4499	op &= UINT64_C(`31`);
4500	op <<= `16`;
4501	Value \|= op;
4502	break;
4503	}
4504	case Hexagon::L4_iadd_memoph_io:
4505	case Hexagon::L4_iand_memoph_io:
4506	case Hexagon::L4_ior_memoph_io:
4507	case Hexagon::L4_isub_memoph_io: {
4508	// op: Ii
4509	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4510	op &= UINT64_C(`126`);
4511	op <<= `6`;
4512	Value \|= op;
4513	// op: II
4514	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4515	op &= UINT64_C(`31`);
4516	Value \|= op;
4517	// op: Rs32
4518	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4519	op &= UINT64_C(`31`);
4520	op <<= `16`;
4521	Value \|= op;
4522	break;
4523	}
4524	case Hexagon::L4_add_memoph_io:
4525	case Hexagon::L4_and_memoph_io:
4526	case Hexagon::L4_or_memoph_io:
4527	case Hexagon::L4_sub_memoph_io: {
4528	// op: Ii
4529	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4530	op &= UINT64_C(`126`);
4531	op <<= `6`;
4532	Value \|= op;
4533	// op: Rs32
4534	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4535	op &= UINT64_C(`31`);
4536	op <<= `16`;
4537	Value \|= op;
4538	// op: Rt32
4539	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4540	op &= UINT64_C(`31`);
4541	Value \|= op;
4542	break;
4543	}
4544	case Hexagon::SS2_storeh_io: {
4545	// op: Ii
4546	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4547	op &= UINT64_C(`14`);
4548	op <<= `7`;
4549	Value \|= op;
4550	// op: Rs16
4551	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4552	op &= UINT64_C(`15`);
4553	op <<= `4`;
4554	Value \|= op;
4555	// op: Rt16
4556	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4557	op &= UINT64_C(`15`);
4558	Value \|= op;
4559	break;
4560	}
4561	case Hexagon::SS2_storebi0:
4562	case Hexagon::SS2_storebi1: {
4563	// op: Ii
4564	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4565	op &= UINT64_C(`15`);
4566	Value \|= op;
4567	// op: Rs16
4568	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4569	op &= UINT64_C(`15`);
4570	op <<= `4`;
4571	Value \|= op;
4572	break;
4573	}
4574	case Hexagon::SS1_storeb_io: {
4575	// op: Ii
4576	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4577	op &= UINT64_C(`15`);
4578	op <<= `8`;
4579	Value \|= op;
4580	// op: Rs16
4581	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4582	op &= UINT64_C(`15`);
4583	op <<= `4`;
4584	Value \|= op;
4585	// op: Rt16
4586	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4587	op &= UINT64_C(`15`);
4588	Value \|= op;
4589	break;
4590	}
4591	case Hexagon::Y2_dcfetchbo: {
4592	// op: Ii
4593	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4594	op &= UINT64_C(`16376`);
4595	op >>= `3`;
4596	Value \|= op;
4597	// op: Rs32
4598	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4599	op &= UINT64_C(`31`);
4600	op <<= `16`;
4601	Value \|= op;
4602	break;
4603	}
4604	case Hexagon::SL2_loadrd_sp: {
4605	// op: Ii
4606	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4607	op &= UINT64_C(`248`);
4608	Value \|= op;
4609	// op: Rdd8
4610	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4611	op &= UINT64_C(`7`);
4612	Value \|= op;
4613	break;
4614	}
4615	case Hexagon::SA1_addsp: {
4616	// op: Ii
4617	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4618	op &= UINT64_C(`252`);
4619	op <<= `2`;
4620	Value \|= op;
4621	// op: Rd16
4622	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4623	op &= UINT64_C(`15`);
4624	Value \|= op;
4625	break;
4626	}
4627	case Hexagon::S4_storeiri_io: {
4628	// op: Ii
4629	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4630	op &= UINT64_C(`252`);
4631	op <<= `5`;
4632	Value \|= op;
4633	// op: II
4634	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4635	Value \|= (op & UINT64_C(`128`)) << `6`;
4636	Value \|= (op & UINT64_C(`127`));
4637	// op: Rs32
4638	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4639	op &= UINT64_C(`31`);
4640	op <<= `16`;
4641	Value \|= op;
4642	break;
4643	}
4644	case Hexagon::L4_iadd_memopw_io:
4645	case Hexagon::L4_iand_memopw_io:
4646	case Hexagon::L4_ior_memopw_io:
4647	case Hexagon::L4_isub_memopw_io: {
4648	// op: Ii
4649	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4650	op &= UINT64_C(`252`);
4651	op <<= `5`;
4652	Value \|= op;
4653	// op: II
4654	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4655	op &= UINT64_C(`31`);
4656	Value \|= op;
4657	// op: Rs32
4658	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4659	op &= UINT64_C(`31`);
4660	op <<= `16`;
4661	Value \|= op;
4662	break;
4663	}
4664	case Hexagon::L4_add_memopw_io:
4665	case Hexagon::L4_and_memopw_io:
4666	case Hexagon::L4_or_memopw_io:
4667	case Hexagon::L4_sub_memopw_io: {
4668	// op: Ii
4669	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4670	op &= UINT64_C(`252`);
4671	op <<= `5`;
4672	Value \|= op;
4673	// op: Rs32
4674	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4675	op &= UINT64_C(`31`);
4676	op <<= `16`;
4677	Value \|= op;
4678	// op: Rt32
4679	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4680	op &= UINT64_C(`31`);
4681	Value \|= op;
4682	break;
4683	}
4684	case Hexagon::A2_combineii: {
4685	// op: Ii
4686	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4687	op &= UINT64_C(`255`);
4688	op <<= `5`;
4689	Value \|= op;
4690	// op: II
4691	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4692	Value \|= (op & UINT64_C(`254`)) << `15`;
4693	Value \|= (op & UINT64_C(`1`)) << `13`;
4694	// op: Rdd32
4695	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4696	op &= UINT64_C(`31`);
4697	Value \|= op;
4698	break;
4699	}
4700	case Hexagon::A4_combineii: {
4701	// op: Ii
4702	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4703	op &= UINT64_C(`255`);
4704	op <<= `5`;
4705	Value \|= op;
4706	// op: II
4707	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4708	Value \|= (op & UINT64_C(`62`)) << `15`;
4709	Value \|= (op & UINT64_C(`1`)) << `13`;
4710	// op: Rdd32
4711	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4712	op &= UINT64_C(`31`);
4713	Value \|= op;
4714	break;
4715	}
4716	case Hexagon::A4_combineir: {
4717	// op: Ii
4718	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4719	op &= UINT64_C(`255`);
4720	op <<= `5`;
4721	Value \|= op;
4722	// op: Rs32
4723	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4724	op &= UINT64_C(`31`);
4725	op <<= `16`;
4726	Value \|= op;
4727	// op: Rdd32
4728	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4729	op &= UINT64_C(`31`);
4730	Value \|= op;
4731	break;
4732	}
4733	case Hexagon::SA1_cmpeqi: {
4734	// op: Ii
4735	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4736	op &= UINT64_C(`3`);
4737	Value \|= op;
4738	// op: Rs16
4739	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4740	op &= UINT64_C(`15`);
4741	op <<= `4`;
4742	Value \|= op;
4743	break;
4744	}
4745	case Hexagon::SA1_combine0i:
4746	case Hexagon::SA1_combine1i:
4747	case Hexagon::SA1_combine2i:
4748	case Hexagon::SA1_combine3i: {
4749	// op: Ii
4750	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4751	op &= UINT64_C(`3`);
4752	op <<= `5`;
4753	Value \|= op;
4754	// op: Rdd8
4755	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4756	op &= UINT64_C(`7`);
4757	Value \|= op;
4758	break;
4759	}
4760	case Hexagon::S2_mask: {
4761	// op: Ii
4762	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4763	op &= UINT64_C(`31`);
4764	op <<= `8`;
4765	Value \|= op;
4766	// op: II
4767	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4768	Value \|= (op & UINT64_C(`24`)) << `18`;
4769	Value \|= (op & UINT64_C(`7`)) << `5`;
4770	// op: Rd32
4771	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4772	op &= UINT64_C(`31`);
4773	Value \|= op;
4774	break;
4775	}
4776	case Hexagon::SS1_storew_io: {
4777	// op: Ii
4778	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4779	op &= UINT64_C(`60`);
4780	op <<= `6`;
4781	Value \|= op;
4782	// op: Rs16
4783	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4784	op &= UINT64_C(`15`);
4785	op <<= `4`;
4786	Value \|= op;
4787	// op: Rt16
4788	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4789	op &= UINT64_C(`15`);
4790	Value \|= op;
4791	break;
4792	}
4793	case Hexagon::SS2_storewi0:
4794	case Hexagon::SS2_storewi1: {
4795	// op: Ii
4796	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4797	op &= UINT64_C(`60`);
4798	op >>= `2`;
4799	Value \|= op;
4800	// op: Rs16
4801	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4802	op &= UINT64_C(`15`);
4803	op <<= `4`;
4804	Value \|= op;
4805	break;
4806	}
4807	case Hexagon::SA1_seti: {
4808	// op: Ii
4809	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4810	op &= UINT64_C(`63`);
4811	op <<= `4`;
4812	Value \|= op;
4813	// op: Rd16
4814	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4815	op &= UINT64_C(`15`);
4816	Value \|= op;
4817	break;
4818	}
4819	case Hexagon::S4_storeirb_io: {
4820	// op: Ii
4821	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4822	op &= UINT64_C(`63`);
4823	op <<= `7`;
4824	Value \|= op;
4825	// op: II
4826	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4827	Value \|= (op & UINT64_C(`128`)) << `6`;
4828	Value \|= (op & UINT64_C(`127`));
4829	// op: Rs32
4830	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4831	op &= UINT64_C(`31`);
4832	op <<= `16`;
4833	Value \|= op;
4834	break;
4835	}
4836	case Hexagon::L4_iadd_memopb_io:
4837	case Hexagon::L4_iand_memopb_io:
4838	case Hexagon::L4_ior_memopb_io:
4839	case Hexagon::L4_isub_memopb_io: {
4840	// op: Ii
4841	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4842	op &= UINT64_C(`63`);
4843	op <<= `7`;
4844	Value \|= op;
4845	// op: II
4846	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4847	op &= UINT64_C(`31`);
4848	Value \|= op;
4849	// op: Rs32
4850	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4851	op &= UINT64_C(`31`);
4852	op <<= `16`;
4853	Value \|= op;
4854	break;
4855	}
4856	case Hexagon::C4_addipc: {
4857	// op: Ii
4858	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4859	op &= UINT64_C(`63`);
4860	op <<= `7`;
4861	Value \|= op;
4862	// op: Rd32
4863	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4864	op &= UINT64_C(`31`);
4865	Value \|= op;
4866	break;
4867	}
4868	case Hexagon::L4_add_memopb_io:
4869	case Hexagon::L4_and_memopb_io:
4870	case Hexagon::L4_or_memopb_io:
4871	case Hexagon::L4_sub_memopb_io: {
4872	// op: Ii
4873	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4874	op &= UINT64_C(`63`);
4875	op <<= `7`;
4876	Value \|= op;
4877	// op: Rs32
4878	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4879	op &= UINT64_C(`31`);
4880	op <<= `16`;
4881	Value \|= op;
4882	// op: Rt32
4883	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4884	op &= UINT64_C(`31`);
4885	Value \|= op;
4886	break;
4887	}
4888	case Hexagon::L2_loadrd_io: {
4889	// op: Ii
4890	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4891	Value \|= (op & UINT64_C(`12288`)) << `13`;
4892	Value \|= (op & UINT64_C(`4088`)) << `2`;
4893	// op: Rs32
4894	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4895	op &= UINT64_C(`31`);
4896	op <<= `16`;
4897	Value \|= op;
4898	// op: Rdd32
4899	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4900	op &= UINT64_C(`31`);
4901	Value \|= op;
4902	break;
4903	}
4904	case Hexagon::S2_pstorerinewf_io:
4905	case Hexagon::S2_pstorerinewt_io:
4906	case Hexagon::S4_pstorerinewfnew_io:
4907	case Hexagon::S4_pstorerinewtnew_io: {
4908	// op: Ii
4909	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4910	Value \|= (op & UINT64_C(`128`)) << `6`;
4911	Value \|= (op & UINT64_C(`124`)) << `1`;
4912	// op: Pv4
4913	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4914	op &= UINT64_C(`3`);
4915	Value \|= op;
4916	// op: Rs32
4917	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4918	op &= UINT64_C(`31`);
4919	op <<= `16`;
4920	Value \|= op;
4921	// op: Nt8
4922	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4923	op &= UINT64_C(`7`);
4924	op <<= `8`;
4925	Value \|= op;
4926	break;
4927	}
4928	case Hexagon::S2_pstorerif_io:
4929	case Hexagon::S2_pstorerit_io:
4930	case Hexagon::S4_pstorerifnew_io:
4931	case Hexagon::S4_pstoreritnew_io: {
4932	// op: Ii
4933	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4934	Value \|= (op & UINT64_C(`128`)) << `6`;
4935	Value \|= (op & UINT64_C(`124`)) << `1`;
4936	// op: Pv4
4937	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4938	op &= UINT64_C(`3`);
4939	Value \|= op;
4940	// op: Rs32
4941	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4942	op &= UINT64_C(`31`);
4943	op <<= `16`;
4944	Value \|= op;
4945	// op: Rt32
4946	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
4947	op &= UINT64_C(`31`);
4948	op <<= `8`;
4949	Value \|= op;
4950	break;
4951	}
4952	case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
4953	case Hexagon::J4_cmpeqn1_f_jumpnv_t:
4954	case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
4955	case Hexagon::J4_cmpeqn1_t_jumpnv_t:
4956	case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
4957	case Hexagon::J4_cmpgtn1_f_jumpnv_t:
4958	case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
4959	case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
4960	// op: Ii
4961	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4962	Value \|= (op & UINT64_C(`1536`)) << `11`;
4963	Value \|= (op & UINT64_C(`508`)) >> `1`;
4964	// op: Ns8
4965	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4966	op &= UINT64_C(`7`);
4967	op <<= `16`;
4968	Value \|= op;
4969	break;
4970	}
4971	case Hexagon::J4_cmpeq_f_jumpnv_nt:
4972	case Hexagon::J4_cmpeq_f_jumpnv_t:
4973	case Hexagon::J4_cmpeq_t_jumpnv_nt:
4974	case Hexagon::J4_cmpeq_t_jumpnv_t:
4975	case Hexagon::J4_cmpgt_f_jumpnv_nt:
4976	case Hexagon::J4_cmpgt_f_jumpnv_t:
4977	case Hexagon::J4_cmpgt_t_jumpnv_nt:
4978	case Hexagon::J4_cmpgt_t_jumpnv_t:
4979	case Hexagon::J4_cmpgtu_f_jumpnv_nt:
4980	case Hexagon::J4_cmpgtu_f_jumpnv_t:
4981	case Hexagon::J4_cmpgtu_t_jumpnv_nt:
4982	case Hexagon::J4_cmpgtu_t_jumpnv_t: {
4983	// op: Ii
4984	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
4985	Value \|= (op & UINT64_C(`1536`)) << `11`;
4986	Value \|= (op & UINT64_C(`508`)) >> `1`;
4987	// op: Ns8
4988	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
4989	op &= UINT64_C(`7`);
4990	op <<= `16`;
4991	Value \|= op;
4992	// op: Rt32
4993	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
4994	op &= UINT64_C(`31`);
4995	op <<= `8`;
4996	Value \|= op;
4997	break;
4998	}
4999	case Hexagon::J4_cmpeqn1_fp0_jump_nt:
5000	case Hexagon::J4_cmpeqn1_fp0_jump_t:
5001	case Hexagon::J4_cmpeqn1_fp1_jump_nt:
5002	case Hexagon::J4_cmpeqn1_fp1_jump_t:
5003	case Hexagon::J4_cmpeqn1_tp0_jump_nt:
5004	case Hexagon::J4_cmpeqn1_tp0_jump_t:
5005	case Hexagon::J4_cmpeqn1_tp1_jump_nt:
5006	case Hexagon::J4_cmpeqn1_tp1_jump_t:
5007	case Hexagon::J4_cmpgtn1_fp0_jump_nt:
5008	case Hexagon::J4_cmpgtn1_fp0_jump_t:
5009	case Hexagon::J4_cmpgtn1_fp1_jump_nt:
5010	case Hexagon::J4_cmpgtn1_fp1_jump_t:
5011	case Hexagon::J4_cmpgtn1_tp0_jump_nt:
5012	case Hexagon::J4_cmpgtn1_tp0_jump_t:
5013	case Hexagon::J4_cmpgtn1_tp1_jump_nt:
5014	case Hexagon::J4_cmpgtn1_tp1_jump_t: {
5015	// op: Ii
5016	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5017	Value \|= (op & UINT64_C(`1536`)) << `11`;
5018	Value \|= (op & UINT64_C(`508`)) >> `1`;
5019	// op: Rs16
5020	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5021	op &= UINT64_C(`15`);
5022	op <<= `16`;
5023	Value \|= op;
5024	break;
5025	}
5026	case Hexagon::J4_cmpeq_fp0_jump_nt:
5027	case Hexagon::J4_cmpeq_fp0_jump_t:
5028	case Hexagon::J4_cmpeq_fp1_jump_nt:
5029	case Hexagon::J4_cmpeq_fp1_jump_t:
5030	case Hexagon::J4_cmpeq_tp0_jump_nt:
5031	case Hexagon::J4_cmpeq_tp0_jump_t:
5032	case Hexagon::J4_cmpeq_tp1_jump_nt:
5033	case Hexagon::J4_cmpeq_tp1_jump_t:
5034	case Hexagon::J4_cmpgt_fp0_jump_nt:
5035	case Hexagon::J4_cmpgt_fp0_jump_t:
5036	case Hexagon::J4_cmpgt_fp1_jump_nt:
5037	case Hexagon::J4_cmpgt_fp1_jump_t:
5038	case Hexagon::J4_cmpgt_tp0_jump_nt:
5039	case Hexagon::J4_cmpgt_tp0_jump_t:
5040	case Hexagon::J4_cmpgt_tp1_jump_nt:
5041	case Hexagon::J4_cmpgt_tp1_jump_t:
5042	case Hexagon::J4_cmpgtu_fp0_jump_nt:
5043	case Hexagon::J4_cmpgtu_fp0_jump_t:
5044	case Hexagon::J4_cmpgtu_fp1_jump_nt:
5045	case Hexagon::J4_cmpgtu_fp1_jump_t:
5046	case Hexagon::J4_cmpgtu_tp0_jump_nt:
5047	case Hexagon::J4_cmpgtu_tp0_jump_t:
5048	case Hexagon::J4_cmpgtu_tp1_jump_nt:
5049	case Hexagon::J4_cmpgtu_tp1_jump_t: {
5050	// op: Ii
5051	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5052	Value \|= (op & UINT64_C(`1536`)) << `11`;
5053	Value \|= (op & UINT64_C(`508`)) >> `1`;
5054	// op: Rs16
5055	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5056	op &= UINT64_C(`15`);
5057	op <<= `16`;
5058	Value \|= op;
5059	// op: Rt16
5060	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5061	op &= UINT64_C(`15`);
5062	op <<= `8`;
5063	Value \|= op;
5064	break;
5065	}
5066	case Hexagon::J4_jumpsetr: {
5067	// op: Ii
5068	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5069	Value \|= (op & UINT64_C(`1536`)) << `11`;
5070	Value \|= (op & UINT64_C(`508`)) >> `1`;
5071	// op: Rs16
5072	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5073	op &= UINT64_C(`15`);
5074	op <<= `16`;
5075	Value \|= op;
5076	// op: Rd16
5077	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5078	op &= UINT64_C(`15`);
5079	op <<= `8`;
5080	Value \|= op;
5081	break;
5082	}
5083	case Hexagon::J4_cmplt_f_jumpnv_nt:
5084	case Hexagon::J4_cmplt_f_jumpnv_t:
5085	case Hexagon::J4_cmplt_t_jumpnv_nt:
5086	case Hexagon::J4_cmplt_t_jumpnv_t:
5087	case Hexagon::J4_cmpltu_f_jumpnv_nt:
5088	case Hexagon::J4_cmpltu_f_jumpnv_t:
5089	case Hexagon::J4_cmpltu_t_jumpnv_nt:
5090	case Hexagon::J4_cmpltu_t_jumpnv_t: {
5091	// op: Ii
5092	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5093	Value \|= (op & UINT64_C(`1536`)) << `11`;
5094	Value \|= (op & UINT64_C(`508`)) >> `1`;
5095	// op: Rt32
5096	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5097	op &= UINT64_C(`31`);
5098	op <<= `8`;
5099	Value \|= op;
5100	// op: Ns8
5101	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5102	op &= UINT64_C(`7`);
5103	op <<= `16`;
5104	Value \|= op;
5105	break;
5106	}
5107	case Hexagon::L2_loadrb_io:
5108	case Hexagon::L2_loadrub_io: {
5109	// op: Ii
5110	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5111	Value \|= (op & UINT64_C(`1536`)) << `16`;
5112	Value \|= (op & UINT64_C(`511`)) << `5`;
5113	// op: Rs32
5114	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5115	op &= UINT64_C(`31`);
5116	op <<= `16`;
5117	Value \|= op;
5118	// op: Rd32
5119	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5120	op &= UINT64_C(`31`);
5121	Value \|= op;
5122	break;
5123	}
5124	case Hexagon::M4_mpyri_addr_u2: {
5125	// op: Ii
5126	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5127	Value \|= (op & UINT64_C(`192`)) << `15`;
5128	Value \|= (op & UINT64_C(`32`)) << `8`;
5129	Value \|= (op & UINT64_C(`28`)) << `3`;
5130	// op: Ru32
5131	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5132	op &= UINT64_C(`31`);
5133	Value \|= op;
5134	// op: Rs32
5135	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5136	op &= UINT64_C(`31`);
5137	op <<= `16`;
5138	Value \|= op;
5139	// op: Rd32
5140	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5141	op &= UINT64_C(`31`);
5142	op <<= `8`;
5143	Value \|= op;
5144	break;
5145	}
5146	case Hexagon::L4_loadbsw2_ur:
5147	case Hexagon::L4_loadbzw2_ur:
5148	case Hexagon::L4_loadrb_ur:
5149	case Hexagon::L4_loadrh_ur:
5150	case Hexagon::L4_loadri_ur:
5151	case Hexagon::L4_loadrub_ur:
5152	case Hexagon::L4_loadruh_ur: {
5153	// op: Ii
5154	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5155	Value \|= (op & UINT64_C(`2`)) << `12`;
5156	Value \|= (op & UINT64_C(`1`)) << `7`;
5157	// op: II
5158	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5159	Value \|= (op & UINT64_C(`60`)) << `6`;
5160	Value \|= (op & UINT64_C(`3`)) << `5`;
5161	// op: Rt32
5162	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5163	op &= UINT64_C(`31`);
5164	op <<= `16`;
5165	Value \|= op;
5166	// op: Rd32
5167	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5168	op &= UINT64_C(`31`);
5169	Value \|= op;
5170	break;
5171	}
5172	case Hexagon::L4_loadbsw4_ur:
5173	case Hexagon::L4_loadbzw4_ur:
5174	case Hexagon::L4_loadrd_ur: {
5175	// op: Ii
5176	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5177	Value \|= (op & UINT64_C(`2`)) << `12`;
5178	Value \|= (op & UINT64_C(`1`)) << `7`;
5179	// op: II
5180	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5181	Value \|= (op & UINT64_C(`60`)) << `6`;
5182	Value \|= (op & UINT64_C(`3`)) << `5`;
5183	// op: Rt32
5184	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5185	op &= UINT64_C(`31`);
5186	op <<= `16`;
5187	Value \|= op;
5188	// op: Rdd32
5189	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5190	op &= UINT64_C(`31`);
5191	Value \|= op;
5192	break;
5193	}
5194	case Hexagon::S4_storerbnew_rr:
5195	case Hexagon::S4_storerhnew_rr:
5196	case Hexagon::S4_storerinew_rr: {
5197	// op: Ii
5198	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5199	Value \|= (op & UINT64_C(`2`)) << `12`;
5200	Value \|= (op & UINT64_C(`1`)) << `7`;
5201	// op: Rs32
5202	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5203	op &= UINT64_C(`31`);
5204	op <<= `16`;
5205	Value \|= op;
5206	// op: Ru32
5207	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5208	op &= UINT64_C(`31`);
5209	op <<= `8`;
5210	Value \|= op;
5211	// op: Nt8
5212	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5213	op &= UINT64_C(`7`);
5214	Value \|= op;
5215	break;
5216	}
5217	case Hexagon::S4_storerb_rr:
5218	case Hexagon::S4_storerf_rr:
5219	case Hexagon::S4_storerh_rr:
5220	case Hexagon::S4_storeri_rr: {
5221	// op: Ii
5222	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5223	Value \|= (op & UINT64_C(`2`)) << `12`;
5224	Value \|= (op & UINT64_C(`1`)) << `7`;
5225	// op: Rs32
5226	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5227	op &= UINT64_C(`31`);
5228	op <<= `16`;
5229	Value \|= op;
5230	// op: Ru32
5231	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5232	op &= UINT64_C(`31`);
5233	op <<= `8`;
5234	Value \|= op;
5235	// op: Rt32
5236	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5237	op &= UINT64_C(`31`);
5238	Value \|= op;
5239	break;
5240	}
5241	case Hexagon::S4_storerd_rr: {
5242	// op: Ii
5243	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5244	Value \|= (op & UINT64_C(`2`)) << `12`;
5245	Value \|= (op & UINT64_C(`1`)) << `7`;
5246	// op: Rs32
5247	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5248	op &= UINT64_C(`31`);
5249	op <<= `16`;
5250	Value \|= op;
5251	// op: Ru32
5252	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5253	op &= UINT64_C(`31`);
5254	op <<= `8`;
5255	Value \|= op;
5256	// op: Rtt32
5257	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5258	op &= UINT64_C(`31`);
5259	Value \|= op;
5260	break;
5261	}
5262	case Hexagon::J2_trap1: {
5263	// op: Ii
5264	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5265	Value \|= (op & UINT64_C(`248`)) << `5`;
5266	Value \|= (op & UINT64_C(`7`)) << `2`;
5267	// op: Rx32
5268	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5269	op &= UINT64_C(`31`);
5270	op <<= `16`;
5271	Value \|= op;
5272	break;
5273	}
5274	case Hexagon::S2_pstorerdf_io:
5275	case Hexagon::S2_pstorerdt_io:
5276	case Hexagon::S4_pstorerdfnew_io:
5277	case Hexagon::S4_pstorerdtnew_io: {
5278	// op: Ii
5279	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5280	Value \|= (op & UINT64_C(`256`)) << `5`;
5281	Value \|= (op & UINT64_C(`248`));
5282	// op: Pv4
5283	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5284	op &= UINT64_C(`3`);
5285	Value \|= op;
5286	// op: Rs32
5287	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5288	op &= UINT64_C(`31`);
5289	op <<= `16`;
5290	Value \|= op;
5291	// op: Rtt32
5292	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5293	op &= UINT64_C(`31`);
5294	op <<= `8`;
5295	Value \|= op;
5296	break;
5297	}
5298	case Hexagon::L2_loadbsw2_io:
5299	case Hexagon::L2_loadbzw2_io:
5300	case Hexagon::L2_loadrh_io:
5301	case Hexagon::L2_loadruh_io: {
5302	// op: Ii
5303	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5304	Value \|= (op & UINT64_C(`3072`)) << `15`;
5305	Value \|= (op & UINT64_C(`1022`)) << `4`;
5306	// op: Rs32
5307	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5308	op &= UINT64_C(`31`);
5309	op <<= `16`;
5310	Value \|= op;
5311	// op: Rd32
5312	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5313	op &= UINT64_C(`31`);
5314	Value \|= op;
5315	break;
5316	}
5317	case Hexagon::S2_pstorerbnewf_io:
5318	case Hexagon::S2_pstorerbnewt_io:
5319	case Hexagon::S4_pstorerbnewfnew_io:
5320	case Hexagon::S4_pstorerbnewtnew_io: {
5321	// op: Ii
5322	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5323	Value \|= (op & UINT64_C(`32`)) << `8`;
5324	Value \|= (op & UINT64_C(`31`)) << `3`;
5325	// op: Pv4
5326	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5327	op &= UINT64_C(`3`);
5328	Value \|= op;
5329	// op: Rs32
5330	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5331	op &= UINT64_C(`31`);
5332	op <<= `16`;
5333	Value \|= op;
5334	// op: Nt8
5335	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5336	op &= UINT64_C(`7`);
5337	op <<= `8`;
5338	Value \|= op;
5339	break;
5340	}
5341	case Hexagon::S2_pstorerbf_io:
5342	case Hexagon::S2_pstorerbt_io:
5343	case Hexagon::S4_pstorerbfnew_io:
5344	case Hexagon::S4_pstorerbtnew_io: {
5345	// op: Ii
5346	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5347	Value \|= (op & UINT64_C(`32`)) << `8`;
5348	Value \|= (op & UINT64_C(`31`)) << `3`;
5349	// op: Pv4
5350	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5351	op &= UINT64_C(`3`);
5352	Value \|= op;
5353	// op: Rs32
5354	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5355	op &= UINT64_C(`31`);
5356	op <<= `16`;
5357	Value \|= op;
5358	// op: Rt32
5359	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5360	op &= UINT64_C(`31`);
5361	op <<= `8`;
5362	Value \|= op;
5363	break;
5364	}
5365	case Hexagon::C2_cmoveif:
5366	case Hexagon::C2_cmoveit:
5367	case Hexagon::C2_cmovenewif:
5368	case Hexagon::C2_cmovenewit: {
5369	// op: Ii
5370	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5371	Value \|= (op & UINT64_C(`3840`)) << `8`;
5372	Value \|= (op & UINT64_C(`255`)) << `5`;
5373	// op: Pu4
5374	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5375	op &= UINT64_C(`3`);
5376	op <<= `21`;
5377	Value \|= op;
5378	// op: Rd32
5379	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5380	op &= UINT64_C(`31`);
5381	Value \|= op;
5382	break;
5383	}
5384	case Hexagon::S4_subaddi: {
5385	// op: Ii
5386	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5387	Value \|= (op & UINT64_C(`48`)) << `17`;
5388	Value \|= (op & UINT64_C(`8`)) << `10`;
5389	Value \|= (op & UINT64_C(`7`)) << `5`;
5390	// op: Rs32
5391	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5392	op &= UINT64_C(`31`);
5393	op <<= `16`;
5394	Value \|= op;
5395	// op: Ru32
5396	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5397	op &= UINT64_C(`31`);
5398	Value \|= op;
5399	// op: Rd32
5400	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5401	op &= UINT64_C(`31`);
5402	op <<= `8`;
5403	Value \|= op;
5404	break;
5405	}
5406	case Hexagon::A2_tfrih:
5407	case Hexagon::A2_tfril: {
5408	// op: Ii
5409	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5410	Value \|= (op & UINT64_C(`49152`)) << `8`;
5411	Value \|= (op & UINT64_C(`16383`));
5412	// op: Rx32
5413	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5414	op &= UINT64_C(`31`);
5415	op <<= `16`;
5416	Value \|= op;
5417	break;
5418	}
5419	case Hexagon::C2_cmpeqi:
5420	case Hexagon::C2_cmpgti:
5421	case Hexagon::C4_cmpltei:
5422	case Hexagon::C4_cmpneqi: {
5423	// op: Ii
5424	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5425	Value \|= (op & UINT64_C(`512`)) << `12`;
5426	Value \|= (op & UINT64_C(`511`)) << `5`;
5427	// op: Rs32
5428	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5429	op &= UINT64_C(`31`);
5430	op <<= `16`;
5431	Value \|= op;
5432	// op: Pd4
5433	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5434	op &= UINT64_C(`3`);
5435	Value \|= op;
5436	break;
5437	}
5438	case Hexagon::A2_andir:
5439	case Hexagon::A2_orir: {
5440	// op: Ii
5441	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5442	Value \|= (op & UINT64_C(`512`)) << `12`;
5443	Value \|= (op & UINT64_C(`511`)) << `5`;
5444	// op: Rs32
5445	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5446	op &= UINT64_C(`31`);
5447	op <<= `16`;
5448	Value \|= op;
5449	// op: Rd32
5450	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5451	op &= UINT64_C(`31`);
5452	Value \|= op;
5453	break;
5454	}
5455	case Hexagon::L2_loadri_io: {
5456	// op: Ii
5457	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5458	Value \|= (op & UINT64_C(`6144`)) << `14`;
5459	Value \|= (op & UINT64_C(`2044`)) << `3`;
5460	// op: Rs32
5461	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5462	op &= UINT64_C(`31`);
5463	op <<= `16`;
5464	Value \|= op;
5465	// op: Rd32
5466	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5467	op &= UINT64_C(`31`);
5468	Value \|= op;
5469	break;
5470	}
5471	case Hexagon::L2_loadbsw4_io:
5472	case Hexagon::L2_loadbzw4_io: {
5473	// op: Ii
5474	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5475	Value \|= (op & UINT64_C(`6144`)) << `14`;
5476	Value \|= (op & UINT64_C(`2044`)) << `3`;
5477	// op: Rs32
5478	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5479	op &= UINT64_C(`31`);
5480	op <<= `16`;
5481	Value \|= op;
5482	// op: Rdd32
5483	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5484	op &= UINT64_C(`31`);
5485	Value \|= op;
5486	break;
5487	}
5488	case Hexagon::L4_ploadrbf_abs:
5489	case Hexagon::L4_ploadrbfnew_abs:
5490	case Hexagon::L4_ploadrbt_abs:
5491	case Hexagon::L4_ploadrbtnew_abs:
5492	case Hexagon::L4_ploadrhf_abs:
5493	case Hexagon::L4_ploadrhfnew_abs:
5494	case Hexagon::L4_ploadrht_abs:
5495	case Hexagon::L4_ploadrhtnew_abs:
5496	case Hexagon::L4_ploadrif_abs:
5497	case Hexagon::L4_ploadrifnew_abs:
5498	case Hexagon::L4_ploadrit_abs:
5499	case Hexagon::L4_ploadritnew_abs:
5500	case Hexagon::L4_ploadrubf_abs:
5501	case Hexagon::L4_ploadrubfnew_abs:
5502	case Hexagon::L4_ploadrubt_abs:
5503	case Hexagon::L4_ploadrubtnew_abs:
5504	case Hexagon::L4_ploadruhf_abs:
5505	case Hexagon::L4_ploadruhfnew_abs:
5506	case Hexagon::L4_ploadruht_abs:
5507	case Hexagon::L4_ploadruhtnew_abs: {
5508	// op: Ii
5509	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5510	Value \|= (op & UINT64_C(`62`)) << `15`;
5511	Value \|= (op & UINT64_C(`1`)) << `8`;
5512	// op: Pt4
5513	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5514	op &= UINT64_C(`3`);
5515	op <<= `9`;
5516	Value \|= op;
5517	// op: Rd32
5518	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5519	op &= UINT64_C(`31`);
5520	Value \|= op;
5521	break;
5522	}
5523	case Hexagon::L4_ploadrdf_abs:
5524	case Hexagon::L4_ploadrdfnew_abs:
5525	case Hexagon::L4_ploadrdt_abs:
5526	case Hexagon::L4_ploadrdtnew_abs: {
5527	// op: Ii
5528	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5529	Value \|= (op & UINT64_C(`62`)) << `15`;
5530	Value \|= (op & UINT64_C(`1`)) << `8`;
5531	// op: Pt4
5532	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5533	op &= UINT64_C(`3`);
5534	op <<= `9`;
5535	Value \|= op;
5536	// op: Rdd32
5537	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5538	op &= UINT64_C(`31`);
5539	Value \|= op;
5540	break;
5541	}
5542	case Hexagon::S2_pstorerhnewf_io:
5543	case Hexagon::S2_pstorerhnewt_io:
5544	case Hexagon::S4_pstorerhnewfnew_io:
5545	case Hexagon::S4_pstorerhnewtnew_io: {
5546	// op: Ii
5547	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5548	Value \|= (op & UINT64_C(`64`)) << `7`;
5549	Value \|= (op & UINT64_C(`62`)) << `2`;
5550	// op: Pv4
5551	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5552	op &= UINT64_C(`3`);
5553	Value \|= op;
5554	// op: Rs32
5555	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5556	op &= UINT64_C(`31`);
5557	op <<= `16`;
5558	Value \|= op;
5559	// op: Nt8
5560	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5561	op &= UINT64_C(`7`);
5562	op <<= `8`;
5563	Value \|= op;
5564	break;
5565	}
5566	case Hexagon::S2_pstorerff_io:
5567	case Hexagon::S2_pstorerft_io:
5568	case Hexagon::S2_pstorerhf_io:
5569	case Hexagon::S2_pstorerht_io:
5570	case Hexagon::S4_pstorerffnew_io:
5571	case Hexagon::S4_pstorerftnew_io:
5572	case Hexagon::S4_pstorerhfnew_io:
5573	case Hexagon::S4_pstorerhtnew_io: {
5574	// op: Ii
5575	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5576	Value \|= (op & UINT64_C(`64`)) << `7`;
5577	Value \|= (op & UINT64_C(`62`)) << `2`;
5578	// op: Pv4
5579	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5580	op &= UINT64_C(`3`);
5581	Value \|= op;
5582	// op: Rs32
5583	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5584	op &= UINT64_C(`31`);
5585	op <<= `16`;
5586	Value \|= op;
5587	// op: Rt32
5588	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5589	op &= UINT64_C(`31`);
5590	op <<= `8`;
5591	Value \|= op;
5592	break;
5593	}
5594	case Hexagon::A2_addi: {
5595	// op: Ii
5596	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5597	Value \|= (op & UINT64_C(`65024`)) << `12`;
5598	Value \|= (op & UINT64_C(`511`)) << `5`;
5599	// op: Rs32
5600	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5601	op &= UINT64_C(`31`);
5602	op <<= `16`;
5603	Value \|= op;
5604	// op: Rd32
5605	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5606	op &= UINT64_C(`31`);
5607	Value \|= op;
5608	break;
5609	}
5610	case Hexagon::V6_zLd_pred_ai: {
5611	// op: Ii
5612	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5613	Value \|= (op & UINT64_C(`8`)) << `10`;
5614	Value \|= (op & UINT64_C(`7`)) << `8`;
5615	// op: Pv4
5616	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5617	op &= UINT64_C(`3`);
5618	op <<= `11`;
5619	Value \|= op;
5620	// op: Rt32
5621	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5622	op &= UINT64_C(`31`);
5623	op <<= `16`;
5624	Value \|= op;
5625	break;
5626	}
5627	case Hexagon::V6_vS32b_new_npred_ai:
5628	case Hexagon::V6_vS32b_new_pred_ai:
5629	case Hexagon::V6_vS32b_nt_new_npred_ai:
5630	case Hexagon::V6_vS32b_nt_new_pred_ai: {
5631	// op: Ii
5632	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5633	Value \|= (op & UINT64_C(`8`)) << `10`;
5634	Value \|= (op & UINT64_C(`7`)) << `8`;
5635	// op: Pv4
5636	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5637	op &= UINT64_C(`3`);
5638	op <<= `11`;
5639	Value \|= op;
5640	// op: Rt32
5641	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5642	op &= UINT64_C(`31`);
5643	op <<= `16`;
5644	Value \|= op;
5645	// op: Os8
5646	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5647	op &= UINT64_C(`7`);
5648	Value \|= op;
5649	break;
5650	}
5651	case Hexagon::V6_vS32Ub_npred_ai:
5652	case Hexagon::V6_vS32Ub_pred_ai:
5653	case Hexagon::V6_vS32b_npred_ai:
5654	case Hexagon::V6_vS32b_nt_npred_ai:
5655	case Hexagon::V6_vS32b_nt_pred_ai:
5656	case Hexagon::V6_vS32b_pred_ai: {
5657	// op: Ii
5658	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5659	Value \|= (op & UINT64_C(`8`)) << `10`;
5660	Value \|= (op & UINT64_C(`7`)) << `8`;
5661	// op: Pv4
5662	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5663	op &= UINT64_C(`3`);
5664	op <<= `11`;
5665	Value \|= op;
5666	// op: Rt32
5667	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5668	op &= UINT64_C(`31`);
5669	op <<= `16`;
5670	Value \|= op;
5671	// op: Vs32
5672	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5673	op &= UINT64_C(`31`);
5674	Value \|= op;
5675	break;
5676	}
5677	case Hexagon::V6_vS32b_nqpred_ai:
5678	case Hexagon::V6_vS32b_nt_nqpred_ai:
5679	case Hexagon::V6_vS32b_nt_qpred_ai:
5680	case Hexagon::V6_vS32b_qpred_ai: {
5681	// op: Ii
5682	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5683	Value \|= (op & UINT64_C(`8`)) << `10`;
5684	Value \|= (op & UINT64_C(`7`)) << `8`;
5685	// op: Qv4
5686	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5687	op &= UINT64_C(`3`);
5688	op <<= `11`;
5689	Value \|= op;
5690	// op: Rt32
5691	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5692	op &= UINT64_C(`31`);
5693	op <<= `16`;
5694	Value \|= op;
5695	// op: Vs32
5696	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5697	op &= UINT64_C(`31`);
5698	Value \|= op;
5699	break;
5700	}
5701	case Hexagon::V6_vL32Ub_ai:
5702	case Hexagon::V6_vL32b_ai:
5703	case Hexagon::V6_vL32b_cur_ai:
5704	case Hexagon::V6_vL32b_nt_ai:
5705	case Hexagon::V6_vL32b_nt_cur_ai:
5706	case Hexagon::V6_vL32b_nt_tmp_ai:
5707	case Hexagon::V6_vL32b_tmp_ai: {
5708	// op: Ii
5709	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5710	Value \|= (op & UINT64_C(`8`)) << `10`;
5711	Value \|= (op & UINT64_C(`7`)) << `8`;
5712	// op: Rt32
5713	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5714	op &= UINT64_C(`31`);
5715	op <<= `16`;
5716	Value \|= op;
5717	// op: Vd32
5718	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5719	op &= UINT64_C(`31`);
5720	Value \|= op;
5721	break;
5722	}
5723	case Hexagon::S2_storerd_pci: {
5724	// op: Ii
5725	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5726	op &= UINT64_C(`120`);
5727	Value \|= op;
5728	// op: Mu2
5729	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5730	op &= UINT64_C(`1`);
5731	op <<= `13`;
5732	Value \|= op;
5733	// op: Rtt32
5734	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
5735	op &= UINT64_C(`31`);
5736	op <<= `8`;
5737	Value \|= op;
5738	// op: Rx32
5739	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5740	op &= UINT64_C(`31`);
5741	op <<= `16`;
5742	Value \|= op;
5743	break;
5744	}
5745	case Hexagon::S2_storerd_pi: {
5746	// op: Ii
5747	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5748	op &= UINT64_C(`120`);
5749	Value \|= op;
5750	// op: Rtt32
5751	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5752	op &= UINT64_C(`31`);
5753	op <<= `8`;
5754	Value \|= op;
5755	// op: Rx32
5756	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5757	op &= UINT64_C(`31`);
5758	op <<= `16`;
5759	Value \|= op;
5760	break;
5761	}
5762	case Hexagon::S4_storeirhf_io:
5763	case Hexagon::S4_storeirhfnew_io:
5764	case Hexagon::S4_storeirht_io:
5765	case Hexagon::S4_storeirhtnew_io: {
5766	// op: Ii
5767	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5768	op &= UINT64_C(`126`);
5769	op <<= `6`;
5770	Value \|= op;
5771	// op: II
5772	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5773	Value \|= (op & UINT64_C(`32`)) << `8`;
5774	Value \|= (op & UINT64_C(`31`));
5775	// op: Pv4
5776	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5777	op &= UINT64_C(`3`);
5778	op <<= `5`;
5779	Value \|= op;
5780	// op: Rs32
5781	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5782	op &= UINT64_C(`31`);
5783	op <<= `16`;
5784	Value \|= op;
5785	break;
5786	}
5787	case Hexagon::SA1_addi: {
5788	// op: Ii
5789	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5790	op &= UINT64_C(`127`);
5791	op <<= `4`;
5792	Value \|= op;
5793	// op: Rx16
5794	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5795	op &= UINT64_C(`15`);
5796	Value \|= op;
5797	break;
5798	}
5799	case Hexagon::A4_cmpbgtui:
5800	case Hexagon::A4_cmphgtui: {
5801	// op: Ii
5802	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5803	op &= UINT64_C(`127`);
5804	op <<= `5`;
5805	Value \|= op;
5806	// op: Rs32
5807	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5808	op &= UINT64_C(`31`);
5809	op <<= `16`;
5810	Value \|= op;
5811	// op: Pd4
5812	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5813	op &= UINT64_C(`3`);
5814	Value \|= op;
5815	break;
5816	}
5817	case Hexagon::A4_vcmpbgtui:
5818	case Hexagon::A4_vcmphgtui:
5819	case Hexagon::A4_vcmpwgtui: {
5820	// op: Ii
5821	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5822	op &= UINT64_C(`127`);
5823	op <<= `5`;
5824	Value \|= op;
5825	// op: Rss32
5826	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5827	op &= UINT64_C(`31`);
5828	op <<= `16`;
5829	Value \|= op;
5830	// op: Pd4
5831	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5832	op &= UINT64_C(`3`);
5833	Value \|= op;
5834	break;
5835	}
5836	case Hexagon::SL2_loadrh_io:
5837	case Hexagon::SL2_loadruh_io: {
5838	// op: Ii
5839	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5840	op &= UINT64_C(`14`);
5841	op <<= `7`;
5842	Value \|= op;
5843	// op: Rs16
5844	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5845	op &= UINT64_C(`15`);
5846	op <<= `4`;
5847	Value \|= op;
5848	// op: Rd16
5849	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5850	op &= UINT64_C(`15`);
5851	Value \|= op;
5852	break;
5853	}
5854	case Hexagon::S2_storerbnew_pci: {
5855	// op: Ii
5856	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5857	op &= UINT64_C(`15`);
5858	op <<= `3`;
5859	Value \|= op;
5860	// op: Mu2
5861	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5862	op &= UINT64_C(`1`);
5863	op <<= `13`;
5864	Value \|= op;
5865	// op: Nt8
5866	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
5867	op &= UINT64_C(`7`);
5868	op <<= `8`;
5869	Value \|= op;
5870	// op: Rx32
5871	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5872	op &= UINT64_C(`31`);
5873	op <<= `16`;
5874	Value \|= op;
5875	break;
5876	}
5877	case Hexagon::S2_storerb_pci: {
5878	// op: Ii
5879	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5880	op &= UINT64_C(`15`);
5881	op <<= `3`;
5882	Value \|= op;
5883	// op: Mu2
5884	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5885	op &= UINT64_C(`1`);
5886	op <<= `13`;
5887	Value \|= op;
5888	// op: Rt32
5889	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
5890	op &= UINT64_C(`31`);
5891	op <<= `8`;
5892	Value \|= op;
5893	// op: Rx32
5894	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5895	op &= UINT64_C(`31`);
5896	op <<= `16`;
5897	Value \|= op;
5898	break;
5899	}
5900	case Hexagon::S2_storerbnew_pi: {
5901	// op: Ii
5902	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5903	op &= UINT64_C(`15`);
5904	op <<= `3`;
5905	Value \|= op;
5906	// op: Nt8
5907	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5908	op &= UINT64_C(`7`);
5909	op <<= `8`;
5910	Value \|= op;
5911	// op: Rx32
5912	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5913	op &= UINT64_C(`31`);
5914	op <<= `16`;
5915	Value \|= op;
5916	break;
5917	}
5918	case Hexagon::S2_storerb_pi: {
5919	// op: Ii
5920	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5921	op &= UINT64_C(`15`);
5922	op <<= `3`;
5923	Value \|= op;
5924	// op: Rt32
5925	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
5926	op &= UINT64_C(`31`);
5927	op <<= `8`;
5928	Value \|= op;
5929	// op: Rx32
5930	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5931	op &= UINT64_C(`31`);
5932	op <<= `16`;
5933	Value \|= op;
5934	break;
5935	}
5936	case Hexagon::SL1_loadrub_io: {
5937	// op: Ii
5938	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5939	op &= UINT64_C(`15`);
5940	op <<= `8`;
5941	Value \|= op;
5942	// op: Rs16
5943	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5944	op &= UINT64_C(`15`);
5945	op <<= `4`;
5946	Value \|= op;
5947	// op: Rd16
5948	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5949	op &= UINT64_C(`15`);
5950	Value \|= op;
5951	break;
5952	}
5953	case Hexagon::S5_asrhub_rnd_sat:
5954	case Hexagon::S5_asrhub_sat: {
5955	// op: Ii
5956	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5957	op &= UINT64_C(`15`);
5958	op <<= `8`;
5959	Value \|= op;
5960	// op: Rss32
5961	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5962	op &= UINT64_C(`31`);
5963	op <<= `16`;
5964	Value \|= op;
5965	// op: Rd32
5966	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5967	op &= UINT64_C(`31`);
5968	Value \|= op;
5969	break;
5970	}
5971	case Hexagon::S2_asl_i_vh:
5972	case Hexagon::S2_asr_i_vh:
5973	case Hexagon::S2_lsr_i_vh:
5974	case Hexagon::S5_vasrhrnd: {
5975	// op: Ii
5976	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5977	op &= UINT64_C(`15`);
5978	op <<= `8`;
5979	Value \|= op;
5980	// op: Rss32
5981	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
5982	op &= UINT64_C(`31`);
5983	op <<= `16`;
5984	Value \|= op;
5985	// op: Rdd32
5986	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5987	op &= UINT64_C(`31`);
5988	Value \|= op;
5989	break;
5990	}
5991	case Hexagon::S2_allocframe: {
5992	// op: Ii
5993	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
5994	op &= UINT64_C(`16376`);
5995	op >>= `3`;
5996	Value \|= op;
5997	// op: Rx32
5998	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
5999	op &= UINT64_C(`31`);
6000	op <<= `16`;
6001	Value \|= op;
6002	break;
6003	}
6004	case Hexagon::S4_storeirif_io:
6005	case Hexagon::S4_storeirifnew_io:
6006	case Hexagon::S4_storeirit_io:
6007	case Hexagon::S4_storeiritnew_io: {
6008	// op: Ii
6009	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6010	op &= UINT64_C(`252`);
6011	op <<= `5`;
6012	Value \|= op;
6013	// op: II
6014	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6015	Value \|= (op & UINT64_C(`32`)) << `8`;
6016	Value \|= (op & UINT64_C(`31`));
6017	// op: Pv4
6018	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6019	op &= UINT64_C(`3`);
6020	op <<= `5`;
6021	Value \|= op;
6022	// op: Rs32
6023	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6024	op &= UINT64_C(`31`);
6025	op <<= `16`;
6026	Value \|= op;
6027	break;
6028	}
6029	case Hexagon::C2_muxii: {
6030	// op: Ii
6031	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6032	op &= UINT64_C(`255`);
6033	op <<= `5`;
6034	Value \|= op;
6035	// op: II
6036	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6037	Value \|= (op & UINT64_C(`254`)) << `15`;
6038	Value \|= (op & UINT64_C(`1`)) << `13`;
6039	// op: Pu4
6040	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6041	op &= UINT64_C(`3`);
6042	op <<= `23`;
6043	Value \|= op;
6044	// op: Rd32
6045	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6046	op &= UINT64_C(`31`);
6047	Value \|= op;
6048	break;
6049	}
6050	case Hexagon::C2_muxri: {
6051	// op: Ii
6052	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6053	op &= UINT64_C(`255`);
6054	op <<= `5`;
6055	Value \|= op;
6056	// op: Pu4
6057	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6058	op &= UINT64_C(`3`);
6059	op <<= `21`;
6060	Value \|= op;
6061	// op: Rs32
6062	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6063	op &= UINT64_C(`31`);
6064	op <<= `16`;
6065	Value \|= op;
6066	// op: Rd32
6067	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6068	op &= UINT64_C(`31`);
6069	Value \|= op;
6070	break;
6071	}
6072	case Hexagon::A4_cmpbeqi:
6073	case Hexagon::A4_cmpbgti:
6074	case Hexagon::A4_cmpheqi:
6075	case Hexagon::A4_cmphgti: {
6076	// op: Ii
6077	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6078	op &= UINT64_C(`255`);
6079	op <<= `5`;
6080	Value \|= op;
6081	// op: Rs32
6082	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6083	op &= UINT64_C(`31`);
6084	op <<= `16`;
6085	Value \|= op;
6086	// op: Pd4
6087	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6088	op &= UINT64_C(`3`);
6089	Value \|= op;
6090	break;
6091	}
6092	case Hexagon::A4_rcmpeqi:
6093	case Hexagon::A4_rcmpneqi:
6094	case Hexagon::M2_mpysin:
6095	case Hexagon::M2_mpysip: {
6096	// op: Ii
6097	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6098	op &= UINT64_C(`255`);
6099	op <<= `5`;
6100	Value \|= op;
6101	// op: Rs32
6102	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6103	op &= UINT64_C(`31`);
6104	op <<= `16`;
6105	Value \|= op;
6106	// op: Rd32
6107	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6108	op &= UINT64_C(`31`);
6109	Value \|= op;
6110	break;
6111	}
6112	case Hexagon::A4_combineri: {
6113	// op: Ii
6114	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6115	op &= UINT64_C(`255`);
6116	op <<= `5`;
6117	Value \|= op;
6118	// op: Rs32
6119	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6120	op &= UINT64_C(`31`);
6121	op <<= `16`;
6122	Value \|= op;
6123	// op: Rdd32
6124	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6125	op &= UINT64_C(`31`);
6126	Value \|= op;
6127	break;
6128	}
6129	case Hexagon::A4_vcmpbeqi:
6130	case Hexagon::A4_vcmpbgti:
6131	case Hexagon::A4_vcmpheqi:
6132	case Hexagon::A4_vcmphgti:
6133	case Hexagon::A4_vcmpweqi:
6134	case Hexagon::A4_vcmpwgti: {
6135	// op: Ii
6136	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6137	op &= UINT64_C(`255`);
6138	op <<= `5`;
6139	Value \|= op;
6140	// op: Rss32
6141	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6142	op &= UINT64_C(`31`);
6143	op <<= `16`;
6144	Value \|= op;
6145	// op: Pd4
6146	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6147	op &= UINT64_C(`3`);
6148	Value \|= op;
6149	break;
6150	}
6151	case Hexagon::S2_storerhnew_pci: {
6152	// op: Ii
6153	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6154	op &= UINT64_C(`30`);
6155	op <<= `2`;
6156	Value \|= op;
6157	// op: Mu2
6158	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6159	op &= UINT64_C(`1`);
6160	op <<= `13`;
6161	Value \|= op;
6162	// op: Nt8
6163	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6164	op &= UINT64_C(`7`);
6165	op <<= `8`;
6166	Value \|= op;
6167	// op: Rx32
6168	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6169	op &= UINT64_C(`31`);
6170	op <<= `16`;
6171	Value \|= op;
6172	break;
6173	}
6174	case Hexagon::S2_storerf_pci:
6175	case Hexagon::S2_storerh_pci: {
6176	// op: Ii
6177	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6178	op &= UINT64_C(`30`);
6179	op <<= `2`;
6180	Value \|= op;
6181	// op: Mu2
6182	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6183	op &= UINT64_C(`1`);
6184	op <<= `13`;
6185	Value \|= op;
6186	// op: Rt32
6187	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6188	op &= UINT64_C(`31`);
6189	op <<= `8`;
6190	Value \|= op;
6191	// op: Rx32
6192	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6193	op &= UINT64_C(`31`);
6194	op <<= `16`;
6195	Value \|= op;
6196	break;
6197	}
6198	case Hexagon::S2_storerhnew_pi: {
6199	// op: Ii
6200	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6201	op &= UINT64_C(`30`);
6202	op <<= `2`;
6203	Value \|= op;
6204	// op: Nt8
6205	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6206	op &= UINT64_C(`7`);
6207	op <<= `8`;
6208	Value \|= op;
6209	// op: Rx32
6210	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6211	op &= UINT64_C(`31`);
6212	op <<= `16`;
6213	Value \|= op;
6214	break;
6215	}
6216	case Hexagon::S2_storerf_pi:
6217	case Hexagon::S2_storerh_pi: {
6218	// op: Ii
6219	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6220	op &= UINT64_C(`30`);
6221	op <<= `2`;
6222	Value \|= op;
6223	// op: Rt32
6224	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6225	op &= UINT64_C(`31`);
6226	op <<= `8`;
6227	Value \|= op;
6228	// op: Rx32
6229	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6230	op &= UINT64_C(`31`);
6231	op <<= `16`;
6232	Value \|= op;
6233	break;
6234	}
6235	case Hexagon::F2_dfclass: {
6236	// op: Ii
6237	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6238	op &= UINT64_C(`31`);
6239	op <<= `5`;
6240	Value \|= op;
6241	// op: Rss32
6242	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6243	op &= UINT64_C(`31`);
6244	op <<= `16`;
6245	Value \|= op;
6246	// op: Pd4
6247	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6248	op &= UINT64_C(`3`);
6249	Value \|= op;
6250	break;
6251	}
6252	case Hexagon::S2_extractu:
6253	case Hexagon::S4_extract: {
6254	// op: Ii
6255	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6256	op &= UINT64_C(`31`);
6257	op <<= `8`;
6258	Value \|= op;
6259	// op: II
6260	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6261	Value \|= (op & UINT64_C(`24`)) << `18`;
6262	Value \|= (op & UINT64_C(`7`)) << `5`;
6263	// op: Rs32
6264	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6265	op &= UINT64_C(`31`);
6266	op <<= `16`;
6267	Value \|= op;
6268	// op: Rd32
6269	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6270	op &= UINT64_C(`31`);
6271	Value \|= op;
6272	break;
6273	}
6274	case Hexagon::F2_sfclass:
6275	case Hexagon::S2_tstbit_i:
6276	case Hexagon::S4_ntstbit_i: {
6277	// op: Ii
6278	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6279	op &= UINT64_C(`31`);
6280	op <<= `8`;
6281	Value \|= op;
6282	// op: Rs32
6283	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6284	op &= UINT64_C(`31`);
6285	op <<= `16`;
6286	Value \|= op;
6287	// op: Pd4
6288	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6289	op &= UINT64_C(`3`);
6290	Value \|= op;
6291	break;
6292	}
6293	case Hexagon::A4_cround_ri:
6294	case Hexagon::A4_round_ri:
6295	case Hexagon::A4_round_ri_sat:
6296	case Hexagon::A7_clip:
6297	case Hexagon::S2_asl_i_r:
6298	case Hexagon::S2_asl_i_r_sat:
6299	case Hexagon::S2_asr_i_r:
6300	case Hexagon::S2_asr_i_r_rnd:
6301	case Hexagon::S2_clrbit_i:
6302	case Hexagon::S2_lsr_i_r:
6303	case Hexagon::S2_setbit_i:
6304	case Hexagon::S2_togglebit_i:
6305	case Hexagon::S6_rol_i_r: {
6306	// op: Ii
6307	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6308	op &= UINT64_C(`31`);
6309	op <<= `8`;
6310	Value \|= op;
6311	// op: Rs32
6312	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6313	op &= UINT64_C(`31`);
6314	op <<= `16`;
6315	Value \|= op;
6316	// op: Rd32
6317	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6318	op &= UINT64_C(`31`);
6319	Value \|= op;
6320	break;
6321	}
6322	case Hexagon::A4_bitspliti: {
6323	// op: Ii
6324	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6325	op &= UINT64_C(`31`);
6326	op <<= `8`;
6327	Value \|= op;
6328	// op: Rs32
6329	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6330	op &= UINT64_C(`31`);
6331	op <<= `16`;
6332	Value \|= op;
6333	// op: Rdd32
6334	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6335	op &= UINT64_C(`31`);
6336	Value \|= op;
6337	break;
6338	}
6339	case Hexagon::S2_asr_i_svw_trun: {
6340	// op: Ii
6341	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6342	op &= UINT64_C(`31`);
6343	op <<= `8`;
6344	Value \|= op;
6345	// op: Rss32
6346	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6347	op &= UINT64_C(`31`);
6348	op <<= `16`;
6349	Value \|= op;
6350	// op: Rd32
6351	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6352	op &= UINT64_C(`31`);
6353	Value \|= op;
6354	break;
6355	}
6356	case Hexagon::A7_vclip:
6357	case Hexagon::S2_asl_i_vw:
6358	case Hexagon::S2_asr_i_vw:
6359	case Hexagon::S2_lsr_i_vw: {
6360	// op: Ii
6361	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6362	op &= UINT64_C(`31`);
6363	op <<= `8`;
6364	Value \|= op;
6365	// op: Rss32
6366	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6367	op &= UINT64_C(`31`);
6368	op <<= `16`;
6369	Value \|= op;
6370	// op: Rdd32
6371	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6372	op &= UINT64_C(`31`);
6373	Value \|= op;
6374	break;
6375	}
6376	case Hexagon::C2_cmpgtui:
6377	case Hexagon::C4_cmplteui: {
6378	// op: Ii
6379	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6380	op &= UINT64_C(`511`);
6381	op <<= `5`;
6382	Value \|= op;
6383	// op: Rs32
6384	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6385	op &= UINT64_C(`31`);
6386	op <<= `16`;
6387	Value \|= op;
6388	// op: Pd4
6389	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6390	op &= UINT64_C(`3`);
6391	Value \|= op;
6392	break;
6393	}
6394	case Hexagon::S2_storerinew_pci: {
6395	// op: Ii
6396	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6397	op &= UINT64_C(`60`);
6398	op <<= `1`;
6399	Value \|= op;
6400	// op: Mu2
6401	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6402	op &= UINT64_C(`1`);
6403	op <<= `13`;
6404	Value \|= op;
6405	// op: Nt8
6406	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6407	op &= UINT64_C(`7`);
6408	op <<= `8`;
6409	Value \|= op;
6410	// op: Rx32
6411	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6412	op &= UINT64_C(`31`);
6413	op <<= `16`;
6414	Value \|= op;
6415	break;
6416	}
6417	case Hexagon::S2_storeri_pci: {
6418	// op: Ii
6419	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6420	op &= UINT64_C(`60`);
6421	op <<= `1`;
6422	Value \|= op;
6423	// op: Mu2
6424	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6425	op &= UINT64_C(`1`);
6426	op <<= `13`;
6427	Value \|= op;
6428	// op: Rt32
6429	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6430	op &= UINT64_C(`31`);
6431	op <<= `8`;
6432	Value \|= op;
6433	// op: Rx32
6434	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6435	op &= UINT64_C(`31`);
6436	op <<= `16`;
6437	Value \|= op;
6438	break;
6439	}
6440	case Hexagon::S2_storerinew_pi: {
6441	// op: Ii
6442	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6443	op &= UINT64_C(`60`);
6444	op <<= `1`;
6445	Value \|= op;
6446	// op: Nt8
6447	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6448	op &= UINT64_C(`7`);
6449	op <<= `8`;
6450	Value \|= op;
6451	// op: Rx32
6452	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6453	op &= UINT64_C(`31`);
6454	op <<= `16`;
6455	Value \|= op;
6456	break;
6457	}
6458	case Hexagon::S2_storeri_pi: {
6459	// op: Ii
6460	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6461	op &= UINT64_C(`60`);
6462	op <<= `1`;
6463	Value \|= op;
6464	// op: Rt32
6465	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6466	op &= UINT64_C(`31`);
6467	op <<= `8`;
6468	Value \|= op;
6469	// op: Rx32
6470	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6471	op &= UINT64_C(`31`);
6472	op <<= `16`;
6473	Value \|= op;
6474	break;
6475	}
6476	case Hexagon::SL1_loadri_io: {
6477	// op: Ii
6478	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6479	op &= UINT64_C(`60`);
6480	op <<= `6`;
6481	Value \|= op;
6482	// op: Rs16
6483	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6484	op &= UINT64_C(`15`);
6485	op <<= `4`;
6486	Value \|= op;
6487	// op: Rd16
6488	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6489	op &= UINT64_C(`15`);
6490	Value \|= op;
6491	break;
6492	}
6493	case Hexagon::S4_storeirbf_io:
6494	case Hexagon::S4_storeirbfnew_io:
6495	case Hexagon::S4_storeirbt_io:
6496	case Hexagon::S4_storeirbtnew_io: {
6497	// op: Ii
6498	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6499	op &= UINT64_C(`63`);
6500	op <<= `7`;
6501	Value \|= op;
6502	// op: II
6503	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6504	Value \|= (op & UINT64_C(`32`)) << `8`;
6505	Value \|= (op & UINT64_C(`31`));
6506	// op: Pv4
6507	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6508	op &= UINT64_C(`3`);
6509	op <<= `5`;
6510	Value \|= op;
6511	// op: Rs32
6512	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6513	op &= UINT64_C(`31`);
6514	op <<= `16`;
6515	Value \|= op;
6516	break;
6517	}
6518	case Hexagon::S2_extractup:
6519	case Hexagon::S4_extractp: {
6520	// op: Ii
6521	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6522	op &= UINT64_C(`63`);
6523	op <<= `8`;
6524	Value \|= op;
6525	// op: II
6526	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6527	Value \|= (op & UINT64_C(`56`)) << `18`;
6528	Value \|= (op & UINT64_C(`7`)) << `5`;
6529	// op: Rss32
6530	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6531	op &= UINT64_C(`31`);
6532	op <<= `16`;
6533	Value \|= op;
6534	// op: Rdd32
6535	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6536	op &= UINT64_C(`31`);
6537	Value \|= op;
6538	break;
6539	}
6540	case Hexagon::C2_bitsclri:
6541	case Hexagon::C4_nbitsclri: {
6542	// op: Ii
6543	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6544	op &= UINT64_C(`63`);
6545	op <<= `8`;
6546	Value \|= op;
6547	// op: Rs32
6548	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6549	op &= UINT64_C(`31`);
6550	op <<= `16`;
6551	Value \|= op;
6552	// op: Pd4
6553	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6554	op &= UINT64_C(`3`);
6555	Value \|= op;
6556	break;
6557	}
6558	case Hexagon::S4_clbaddi: {
6559	// op: Ii
6560	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6561	op &= UINT64_C(`63`);
6562	op <<= `8`;
6563	Value \|= op;
6564	// op: Rs32
6565	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6566	op &= UINT64_C(`31`);
6567	op <<= `16`;
6568	Value \|= op;
6569	// op: Rd32
6570	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6571	op &= UINT64_C(`31`);
6572	Value \|= op;
6573	break;
6574	}
6575	case Hexagon::S4_clbpaddi: {
6576	// op: Ii
6577	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6578	op &= UINT64_C(`63`);
6579	op <<= `8`;
6580	Value \|= op;
6581	// op: Rss32
6582	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6583	op &= UINT64_C(`31`);
6584	op <<= `16`;
6585	Value \|= op;
6586	// op: Rd32
6587	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6588	op &= UINT64_C(`31`);
6589	Value \|= op;
6590	break;
6591	}
6592	case Hexagon::A7_croundd_ri:
6593	case Hexagon::S2_asl_i_p:
6594	case Hexagon::S2_asr_i_p:
6595	case Hexagon::S2_asr_i_p_rnd:
6596	case Hexagon::S2_lsr_i_p:
6597	case Hexagon::S6_rol_i_p: {
6598	// op: Ii
6599	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6600	op &= UINT64_C(`63`);
6601	op <<= `8`;
6602	Value \|= op;
6603	// op: Rss32
6604	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6605	op &= UINT64_C(`31`);
6606	op <<= `16`;
6607	Value \|= op;
6608	// op: Rdd32
6609	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6610	op &= UINT64_C(`31`);
6611	Value \|= op;
6612	break;
6613	}
6614	case Hexagon::V6_vS32b_new_pi:
6615	case Hexagon::V6_vS32b_nt_new_pi: {
6616	// op: Ii
6617	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6618	op &= UINT64_C(`7`);
6619	op <<= `8`;
6620	Value \|= op;
6621	// op: Os8
6622	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6623	op &= UINT64_C(`7`);
6624	Value \|= op;
6625	// op: Rx32
6626	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6627	op &= UINT64_C(`31`);
6628	op <<= `16`;
6629	Value \|= op;
6630	break;
6631	}
6632	case Hexagon::SL2_loadrb_io: {
6633	// op: Ii
6634	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6635	op &= UINT64_C(`7`);
6636	op <<= `8`;
6637	Value \|= op;
6638	// op: Rs16
6639	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6640	op &= UINT64_C(`15`);
6641	op <<= `4`;
6642	Value \|= op;
6643	// op: Rd16
6644	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6645	op &= UINT64_C(`15`);
6646	Value \|= op;
6647	break;
6648	}
6649	case Hexagon::V6_vS32b_srls_pi:
6650	case Hexagon::V6_zLd_pi: {
6651	// op: Ii
6652	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6653	op &= UINT64_C(`7`);
6654	op <<= `8`;
6655	Value \|= op;
6656	// op: Rx32
6657	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6658	op &= UINT64_C(`31`);
6659	op <<= `16`;
6660	Value \|= op;
6661	break;
6662	}
6663	case Hexagon::V6_vS32Ub_pi:
6664	case Hexagon::V6_vS32b_nt_pi:
6665	case Hexagon::V6_vS32b_pi: {
6666	// op: Ii
6667	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6668	op &= UINT64_C(`7`);
6669	op <<= `8`;
6670	Value \|= op;
6671	// op: Vs32
6672	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6673	op &= UINT64_C(`31`);
6674	Value \|= op;
6675	// op: Rx32
6676	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6677	op &= UINT64_C(`31`);
6678	op <<= `16`;
6679	Value \|= op;
6680	break;
6681	}
6682	case Hexagon::L2_loadalignb_io: {
6683	// op: Ii
6684	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6685	Value \|= (op & UINT64_C(`1536`)) << `16`;
6686	Value \|= (op & UINT64_C(`511`)) << `5`;
6687	// op: Rs32
6688	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6689	op &= UINT64_C(`31`);
6690	op <<= `16`;
6691	Value \|= op;
6692	// op: Ryy32
6693	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6694	op &= UINT64_C(`31`);
6695	Value \|= op;
6696	break;
6697	}
6698	case Hexagon::S4_vrcrotate: {
6699	// op: Ii
6700	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6701	Value \|= (op & UINT64_C(`2`)) << `12`;
6702	Value \|= (op & UINT64_C(`1`)) << `5`;
6703	// op: Rss32
6704	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6705	op &= UINT64_C(`31`);
6706	op <<= `16`;
6707	Value \|= op;
6708	// op: Rt32
6709	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6710	op &= UINT64_C(`31`);
6711	op <<= `8`;
6712	Value \|= op;
6713	// op: Rdd32
6714	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6715	op &= UINT64_C(`31`);
6716	Value \|= op;
6717	break;
6718	}
6719	case Hexagon::L4_loadalignb_ur:
6720	case Hexagon::L4_loadalignh_ur: {
6721	// op: Ii
6722	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6723	Value \|= (op & UINT64_C(`2`)) << `12`;
6724	Value \|= (op & UINT64_C(`1`)) << `7`;
6725	// op: II
6726	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6727	Value \|= (op & UINT64_C(`60`)) << `6`;
6728	Value \|= (op & UINT64_C(`3`)) << `5`;
6729	// op: Rt32
6730	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6731	op &= UINT64_C(`31`);
6732	op <<= `16`;
6733	Value \|= op;
6734	// op: Ryy32
6735	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6736	op &= UINT64_C(`31`);
6737	Value \|= op;
6738	break;
6739	}
6740	case Hexagon::S4_pstorerbnewf_rr:
6741	case Hexagon::S4_pstorerbnewfnew_rr:
6742	case Hexagon::S4_pstorerbnewt_rr:
6743	case Hexagon::S4_pstorerbnewtnew_rr:
6744	case Hexagon::S4_pstorerhnewf_rr:
6745	case Hexagon::S4_pstorerhnewfnew_rr:
6746	case Hexagon::S4_pstorerhnewt_rr:
6747	case Hexagon::S4_pstorerhnewtnew_rr:
6748	case Hexagon::S4_pstorerinewf_rr:
6749	case Hexagon::S4_pstorerinewfnew_rr:
6750	case Hexagon::S4_pstorerinewt_rr:
6751	case Hexagon::S4_pstorerinewtnew_rr: {
6752	// op: Ii
6753	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6754	Value \|= (op & UINT64_C(`2`)) << `12`;
6755	Value \|= (op & UINT64_C(`1`)) << `7`;
6756	// op: Pv4
6757	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6758	op &= UINT64_C(`3`);
6759	op <<= `5`;
6760	Value \|= op;
6761	// op: Rs32
6762	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6763	op &= UINT64_C(`31`);
6764	op <<= `16`;
6765	Value \|= op;
6766	// op: Ru32
6767	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6768	op &= UINT64_C(`31`);
6769	op <<= `8`;
6770	Value \|= op;
6771	// op: Nt8
6772	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6773	op &= UINT64_C(`7`);
6774	Value \|= op;
6775	break;
6776	}
6777	case Hexagon::S4_pstorerbf_rr:
6778	case Hexagon::S4_pstorerbfnew_rr:
6779	case Hexagon::S4_pstorerbt_rr:
6780	case Hexagon::S4_pstorerbtnew_rr:
6781	case Hexagon::S4_pstorerff_rr:
6782	case Hexagon::S4_pstorerffnew_rr:
6783	case Hexagon::S4_pstorerft_rr:
6784	case Hexagon::S4_pstorerftnew_rr:
6785	case Hexagon::S4_pstorerhf_rr:
6786	case Hexagon::S4_pstorerhfnew_rr:
6787	case Hexagon::S4_pstorerht_rr:
6788	case Hexagon::S4_pstorerhtnew_rr:
6789	case Hexagon::S4_pstorerif_rr:
6790	case Hexagon::S4_pstorerifnew_rr:
6791	case Hexagon::S4_pstorerit_rr:
6792	case Hexagon::S4_pstoreritnew_rr: {
6793	// op: Ii
6794	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6795	Value \|= (op & UINT64_C(`2`)) << `12`;
6796	Value \|= (op & UINT64_C(`1`)) << `7`;
6797	// op: Pv4
6798	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6799	op &= UINT64_C(`3`);
6800	op <<= `5`;
6801	Value \|= op;
6802	// op: Rs32
6803	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6804	op &= UINT64_C(`31`);
6805	op <<= `16`;
6806	Value \|= op;
6807	// op: Ru32
6808	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6809	op &= UINT64_C(`31`);
6810	op <<= `8`;
6811	Value \|= op;
6812	// op: Rt32
6813	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6814	op &= UINT64_C(`31`);
6815	Value \|= op;
6816	break;
6817	}
6818	case Hexagon::S4_pstorerdf_rr:
6819	case Hexagon::S4_pstorerdfnew_rr:
6820	case Hexagon::S4_pstorerdt_rr:
6821	case Hexagon::S4_pstorerdtnew_rr: {
6822	// op: Ii
6823	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6824	Value \|= (op & UINT64_C(`2`)) << `12`;
6825	Value \|= (op & UINT64_C(`1`)) << `7`;
6826	// op: Pv4
6827	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6828	op &= UINT64_C(`3`);
6829	op <<= `5`;
6830	Value \|= op;
6831	// op: Rs32
6832	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6833	op &= UINT64_C(`31`);
6834	op <<= `16`;
6835	Value \|= op;
6836	// op: Ru32
6837	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6838	op &= UINT64_C(`31`);
6839	op <<= `8`;
6840	Value \|= op;
6841	// op: Rtt32
6842	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
6843	op &= UINT64_C(`31`);
6844	Value \|= op;
6845	break;
6846	}
6847	case Hexagon::L4_loadrb_rr:
6848	case Hexagon::L4_loadrh_rr:
6849	case Hexagon::L4_loadri_rr:
6850	case Hexagon::L4_loadrub_rr:
6851	case Hexagon::L4_loadruh_rr: {
6852	// op: Ii
6853	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6854	Value \|= (op & UINT64_C(`2`)) << `12`;
6855	Value \|= (op & UINT64_C(`1`)) << `7`;
6856	// op: Rs32
6857	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6858	op &= UINT64_C(`31`);
6859	op <<= `16`;
6860	Value \|= op;
6861	// op: Rt32
6862	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6863	op &= UINT64_C(`31`);
6864	op <<= `8`;
6865	Value \|= op;
6866	// op: Rd32
6867	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6868	op &= UINT64_C(`31`);
6869	Value \|= op;
6870	break;
6871	}
6872	case Hexagon::L4_loadrd_rr: {
6873	// op: Ii
6874	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6875	Value \|= (op & UINT64_C(`2`)) << `12`;
6876	Value \|= (op & UINT64_C(`1`)) << `7`;
6877	// op: Rs32
6878	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6879	op &= UINT64_C(`31`);
6880	op <<= `16`;
6881	Value \|= op;
6882	// op: Rt32
6883	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6884	op &= UINT64_C(`31`);
6885	op <<= `8`;
6886	Value \|= op;
6887	// op: Rdd32
6888	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6889	op &= UINT64_C(`31`);
6890	Value \|= op;
6891	break;
6892	}
6893	case Hexagon::L2_loadalignh_io: {
6894	// op: Ii
6895	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6896	Value \|= (op & UINT64_C(`3072`)) << `15`;
6897	Value \|= (op & UINT64_C(`1022`)) << `4`;
6898	// op: Rs32
6899	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6900	op &= UINT64_C(`31`);
6901	op <<= `16`;
6902	Value \|= op;
6903	// op: Ryy32
6904	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6905	op &= UINT64_C(`31`);
6906	Value \|= op;
6907	break;
6908	}
6909	case Hexagon::S4_addaddi: {
6910	// op: Ii
6911	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6912	Value \|= (op & UINT64_C(`48`)) << `17`;
6913	Value \|= (op & UINT64_C(`8`)) << `10`;
6914	Value \|= (op & UINT64_C(`7`)) << `5`;
6915	// op: Rs32
6916	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6917	op &= UINT64_C(`31`);
6918	op <<= `16`;
6919	Value \|= op;
6920	// op: Ru32
6921	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6922	op &= UINT64_C(`31`);
6923	Value \|= op;
6924	// op: Rd32
6925	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6926	op &= UINT64_C(`31`);
6927	op <<= `8`;
6928	Value \|= op;
6929	break;
6930	}
6931	case Hexagon::M4_mpyri_addr: {
6932	// op: Ii
6933	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6934	Value \|= (op & UINT64_C(`48`)) << `17`;
6935	Value \|= (op & UINT64_C(`8`)) << `10`;
6936	Value \|= (op & UINT64_C(`7`)) << `5`;
6937	// op: Ru32
6938	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6939	op &= UINT64_C(`31`);
6940	Value \|= op;
6941	// op: Rs32
6942	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6943	op &= UINT64_C(`31`);
6944	op <<= `16`;
6945	Value \|= op;
6946	// op: Rd32
6947	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6948	op &= UINT64_C(`31`);
6949	op <<= `8`;
6950	Value \|= op;
6951	break;
6952	}
6953	case Hexagon::S4_or_andi:
6954	case Hexagon::S4_or_ori: {
6955	// op: Ii
6956	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6957	Value \|= (op & UINT64_C(`512`)) << `12`;
6958	Value \|= (op & UINT64_C(`511`)) << `5`;
6959	// op: Rs32
6960	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
6961	op &= UINT64_C(`31`);
6962	op <<= `16`;
6963	Value \|= op;
6964	// op: Rx32
6965	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6966	op &= UINT64_C(`31`);
6967	Value \|= op;
6968	break;
6969	}
6970	case Hexagon::S4_or_andix: {
6971	// op: Ii
6972	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
6973	Value \|= (op & UINT64_C(`512`)) << `12`;
6974	Value \|= (op & UINT64_C(`511`)) << `5`;
6975	// op: Ru32
6976	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
6977	op &= UINT64_C(`31`);
6978	Value \|= op;
6979	// op: Rx32
6980	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
6981	op &= UINT64_C(`31`);
6982	op <<= `16`;
6983	Value \|= op;
6984	break;
6985	}
6986	case Hexagon::V6_vL32b_cur_npred_ai:
6987	case Hexagon::V6_vL32b_cur_pred_ai:
6988	case Hexagon::V6_vL32b_npred_ai:
6989	case Hexagon::V6_vL32b_nt_cur_npred_ai:
6990	case Hexagon::V6_vL32b_nt_cur_pred_ai:
6991	case Hexagon::V6_vL32b_nt_npred_ai:
6992	case Hexagon::V6_vL32b_nt_pred_ai:
6993	case Hexagon::V6_vL32b_nt_tmp_npred_ai:
6994	case Hexagon::V6_vL32b_nt_tmp_pred_ai:
6995	case Hexagon::V6_vL32b_pred_ai:
6996	case Hexagon::V6_vL32b_tmp_npred_ai:
6997	case Hexagon::V6_vL32b_tmp_pred_ai: {
6998	// op: Ii
6999	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7000	Value \|= (op & UINT64_C(`8`)) << `10`;
7001	Value \|= (op & UINT64_C(`7`)) << `8`;
7002	// op: Pv4
7003	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7004	op &= UINT64_C(`3`);
7005	op <<= `11`;
7006	Value \|= op;
7007	// op: Rt32
7008	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7009	op &= UINT64_C(`31`);
7010	op <<= `16`;
7011	Value \|= op;
7012	// op: Vd32
7013	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7014	op &= UINT64_C(`31`);
7015	Value \|= op;
7016	break;
7017	}
7018	case Hexagon::S2_tableidxb:
7019	case Hexagon::S2_tableidxd:
7020	case Hexagon::S2_tableidxh:
7021	case Hexagon::S2_tableidxw: {
7022	// op: Ii
7023	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7024	Value \|= (op & UINT64_C(`8`)) << `18`;
7025	Value \|= (op & UINT64_C(`7`)) << `5`;
7026	// op: II
7027	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7028	op &= UINT64_C(`63`);
7029	op <<= `8`;
7030	Value \|= op;
7031	// op: Rs32
7032	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7033	op &= UINT64_C(`31`);
7034	op <<= `16`;
7035	Value \|= op;
7036	// op: Rx32
7037	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7038	op &= UINT64_C(`31`);
7039	Value \|= op;
7040	break;
7041	}
7042	case Hexagon::V6_vrmpybusi:
7043	case Hexagon::V6_vrmpyubi:
7044	case Hexagon::V6_vrsadubi: {
7045	// op: Ii
7046	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7047	op &= UINT64_C(`1`);
7048	op <<= `5`;
7049	Value \|= op;
7050	// op: Vuu32
7051	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7052	op &= UINT64_C(`31`);
7053	op <<= `8`;
7054	Value \|= op;
7055	// op: Rt32
7056	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7057	op &= UINT64_C(`31`);
7058	op <<= `16`;
7059	Value \|= op;
7060	// op: Vdd32
7061	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7062	op &= UINT64_C(`31`);
7063	Value \|= op;
7064	break;
7065	}
7066	case Hexagon::S2_pstorerdf_pi:
7067	case Hexagon::S2_pstorerdfnew_pi:
7068	case Hexagon::S2_pstorerdt_pi:
7069	case Hexagon::S2_pstorerdtnew_pi: {
7070	// op: Ii
7071	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7072	op &= UINT64_C(`120`);
7073	Value \|= op;
7074	// op: Pv4
7075	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7076	op &= UINT64_C(`3`);
7077	Value \|= op;
7078	// op: Rtt32
7079	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7080	op &= UINT64_C(`31`);
7081	op <<= `8`;
7082	Value \|= op;
7083	// op: Rx32
7084	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7085	op &= UINT64_C(`31`);
7086	op <<= `16`;
7087	Value \|= op;
7088	break;
7089	}
7090	case Hexagon::L2_loadrd_pci: {
7091	// op: Ii
7092	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7093	op &= UINT64_C(`120`);
7094	op <<= `2`;
7095	Value \|= op;
7096	// op: Mu2
7097	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7098	op &= UINT64_C(`1`);
7099	op <<= `13`;
7100	Value \|= op;
7101	// op: Rdd32
7102	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7103	op &= UINT64_C(`31`);
7104	Value \|= op;
7105	// op: Rx32
7106	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7107	op &= UINT64_C(`31`);
7108	op <<= `16`;
7109	Value \|= op;
7110	break;
7111	}
7112	case Hexagon::L2_loadrd_pi: {
7113	// op: Ii
7114	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7115	op &= UINT64_C(`120`);
7116	op <<= `2`;
7117	Value \|= op;
7118	// op: Rdd32
7119	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7120	op &= UINT64_C(`31`);
7121	Value \|= op;
7122	// op: Rx32
7123	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7124	op &= UINT64_C(`31`);
7125	op <<= `16`;
7126	Value \|= op;
7127	break;
7128	}
7129	case Hexagon::L2_ploadrhf_io:
7130	case Hexagon::L2_ploadrhfnew_io:
7131	case Hexagon::L2_ploadrht_io:
7132	case Hexagon::L2_ploadrhtnew_io:
7133	case Hexagon::L2_ploadruhf_io:
7134	case Hexagon::L2_ploadruhfnew_io:
7135	case Hexagon::L2_ploadruht_io:
7136	case Hexagon::L2_ploadruhtnew_io: {
7137	// op: Ii
7138	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7139	op &= UINT64_C(`126`);
7140	op <<= `4`;
7141	Value \|= op;
7142	// op: Pt4
7143	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7144	op &= UINT64_C(`3`);
7145	op <<= `11`;
7146	Value \|= op;
7147	// op: Rs32
7148	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7149	op &= UINT64_C(`31`);
7150	op <<= `16`;
7151	Value \|= op;
7152	// op: Rd32
7153	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7154	op &= UINT64_C(`31`);
7155	Value \|= op;
7156	break;
7157	}
7158	case Hexagon::S2_pstorerbnewf_pi:
7159	case Hexagon::S2_pstorerbnewfnew_pi:
7160	case Hexagon::S2_pstorerbnewt_pi:
7161	case Hexagon::S2_pstorerbnewtnew_pi: {
7162	// op: Ii
7163	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7164	op &= UINT64_C(`15`);
7165	op <<= `3`;
7166	Value \|= op;
7167	// op: Pv4
7168	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7169	op &= UINT64_C(`3`);
7170	Value \|= op;
7171	// op: Nt8
7172	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7173	op &= UINT64_C(`7`);
7174	op <<= `8`;
7175	Value \|= op;
7176	// op: Rx32
7177	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7178	op &= UINT64_C(`31`);
7179	op <<= `16`;
7180	Value \|= op;
7181	break;
7182	}
7183	case Hexagon::S2_pstorerbf_pi:
7184	case Hexagon::S2_pstorerbfnew_pi:
7185	case Hexagon::S2_pstorerbt_pi:
7186	case Hexagon::S2_pstorerbtnew_pi: {
7187	// op: Ii
7188	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7189	op &= UINT64_C(`15`);
7190	op <<= `3`;
7191	Value \|= op;
7192	// op: Pv4
7193	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7194	op &= UINT64_C(`3`);
7195	Value \|= op;
7196	// op: Rt32
7197	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7198	op &= UINT64_C(`31`);
7199	op <<= `8`;
7200	Value \|= op;
7201	// op: Rx32
7202	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7203	op &= UINT64_C(`31`);
7204	op <<= `16`;
7205	Value \|= op;
7206	break;
7207	}
7208	case Hexagon::L2_loadrb_pci:
7209	case Hexagon::L2_loadrub_pci: {
7210	// op: Ii
7211	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7212	op &= UINT64_C(`15`);
7213	op <<= `5`;
7214	Value \|= op;
7215	// op: Mu2
7216	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7217	op &= UINT64_C(`1`);
7218	op <<= `13`;
7219	Value \|= op;
7220	// op: Rd32
7221	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7222	op &= UINT64_C(`31`);
7223	Value \|= op;
7224	// op: Rx32
7225	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7226	op &= UINT64_C(`31`);
7227	op <<= `16`;
7228	Value \|= op;
7229	break;
7230	}
7231	case Hexagon::L2_loadrb_pi:
7232	case Hexagon::L2_loadrub_pi: {
7233	// op: Ii
7234	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7235	op &= UINT64_C(`15`);
7236	op <<= `5`;
7237	Value \|= op;
7238	// op: Rd32
7239	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7240	op &= UINT64_C(`31`);
7241	Value \|= op;
7242	// op: Rx32
7243	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7244	op &= UINT64_C(`31`);
7245	op <<= `16`;
7246	Value \|= op;
7247	break;
7248	}
7249	case Hexagon::L2_ploadrif_io:
7250	case Hexagon::L2_ploadrifnew_io:
7251	case Hexagon::L2_ploadrit_io:
7252	case Hexagon::L2_ploadritnew_io: {
7253	// op: Ii
7254	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7255	op &= UINT64_C(`252`);
7256	op <<= `3`;
7257	Value \|= op;
7258	// op: Pt4
7259	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7260	op &= UINT64_C(`3`);
7261	op <<= `11`;
7262	Value \|= op;
7263	// op: Rs32
7264	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7265	op &= UINT64_C(`31`);
7266	op <<= `16`;
7267	Value \|= op;
7268	// op: Rd32
7269	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7270	op &= UINT64_C(`31`);
7271	Value \|= op;
7272	break;
7273	}
7274	case Hexagon::A2_paddif:
7275	case Hexagon::A2_paddifnew:
7276	case Hexagon::A2_paddit:
7277	case Hexagon::A2_padditnew:
7278	case Hexagon::C2_muxir: {
7279	// op: Ii
7280	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7281	op &= UINT64_C(`255`);
7282	op <<= `5`;
7283	Value \|= op;
7284	// op: Pu4
7285	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7286	op &= UINT64_C(`3`);
7287	op <<= `21`;
7288	Value \|= op;
7289	// op: Rs32
7290	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7291	op &= UINT64_C(`31`);
7292	op <<= `16`;
7293	Value \|= op;
7294	// op: Rd32
7295	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7296	op &= UINT64_C(`31`);
7297	Value \|= op;
7298	break;
7299	}
7300	case Hexagon::M2_accii:
7301	case Hexagon::M2_macsin:
7302	case Hexagon::M2_macsip:
7303	case Hexagon::M2_naccii: {
7304	// op: Ii
7305	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7306	op &= UINT64_C(`255`);
7307	op <<= `5`;
7308	Value \|= op;
7309	// op: Rs32
7310	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7311	op &= UINT64_C(`31`);
7312	op <<= `16`;
7313	Value \|= op;
7314	// op: Rx32
7315	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7316	op &= UINT64_C(`31`);
7317	Value \|= op;
7318	break;
7319	}
7320	case Hexagon::V6_v6mpyhubs10:
7321	case Hexagon::V6_v6mpyvubs10: {
7322	// op: Ii
7323	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7324	op &= UINT64_C(`3`);
7325	op <<= `5`;
7326	Value \|= op;
7327	// op: Vuu32
7328	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7329	op &= UINT64_C(`31`);
7330	op <<= `8`;
7331	Value \|= op;
7332	// op: Vvv32
7333	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7334	op &= UINT64_C(`31`);
7335	op <<= `16`;
7336	Value \|= op;
7337	// op: Vdd32
7338	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7339	op &= UINT64_C(`31`);
7340	Value \|= op;
7341	break;
7342	}
7343	case Hexagon::S2_pstorerhnewf_pi:
7344	case Hexagon::S2_pstorerhnewfnew_pi:
7345	case Hexagon::S2_pstorerhnewt_pi:
7346	case Hexagon::S2_pstorerhnewtnew_pi: {
7347	// op: Ii
7348	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7349	op &= UINT64_C(`30`);
7350	op <<= `2`;
7351	Value \|= op;
7352	// op: Pv4
7353	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7354	op &= UINT64_C(`3`);
7355	Value \|= op;
7356	// op: Nt8
7357	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7358	op &= UINT64_C(`7`);
7359	op <<= `8`;
7360	Value \|= op;
7361	// op: Rx32
7362	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7363	op &= UINT64_C(`31`);
7364	op <<= `16`;
7365	Value \|= op;
7366	break;
7367	}
7368	case Hexagon::S2_pstorerff_pi:
7369	case Hexagon::S2_pstorerffnew_pi:
7370	case Hexagon::S2_pstorerft_pi:
7371	case Hexagon::S2_pstorerftnew_pi:
7372	case Hexagon::S2_pstorerhf_pi:
7373	case Hexagon::S2_pstorerhfnew_pi:
7374	case Hexagon::S2_pstorerht_pi:
7375	case Hexagon::S2_pstorerhtnew_pi: {
7376	// op: Ii
7377	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7378	op &= UINT64_C(`30`);
7379	op <<= `2`;
7380	Value \|= op;
7381	// op: Pv4
7382	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7383	op &= UINT64_C(`3`);
7384	Value \|= op;
7385	// op: Rt32
7386	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7387	op &= UINT64_C(`31`);
7388	op <<= `8`;
7389	Value \|= op;
7390	// op: Rx32
7391	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7392	op &= UINT64_C(`31`);
7393	op <<= `16`;
7394	Value \|= op;
7395	break;
7396	}
7397	case Hexagon::L2_loadbsw2_pci:
7398	case Hexagon::L2_loadbzw2_pci:
7399	case Hexagon::L2_loadrh_pci:
7400	case Hexagon::L2_loadruh_pci: {
7401	// op: Ii
7402	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7403	op &= UINT64_C(`30`);
7404	op <<= `4`;
7405	Value \|= op;
7406	// op: Mu2
7407	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7408	op &= UINT64_C(`1`);
7409	op <<= `13`;
7410	Value \|= op;
7411	// op: Rd32
7412	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7413	op &= UINT64_C(`31`);
7414	Value \|= op;
7415	// op: Rx32
7416	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7417	op &= UINT64_C(`31`);
7418	op <<= `16`;
7419	Value \|= op;
7420	break;
7421	}
7422	case Hexagon::L2_loadbsw2_pi:
7423	case Hexagon::L2_loadbzw2_pi:
7424	case Hexagon::L2_loadrh_pi:
7425	case Hexagon::L2_loadruh_pi: {
7426	// op: Ii
7427	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7428	op &= UINT64_C(`30`);
7429	op <<= `4`;
7430	Value \|= op;
7431	// op: Rd32
7432	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7433	op &= UINT64_C(`31`);
7434	Value \|= op;
7435	// op: Rx32
7436	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7437	op &= UINT64_C(`31`);
7438	op <<= `16`;
7439	Value \|= op;
7440	break;
7441	}
7442	case Hexagon::S2_insert: {
7443	// op: Ii
7444	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7445	op &= UINT64_C(`31`);
7446	op <<= `8`;
7447	Value \|= op;
7448	// op: II
7449	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7450	Value \|= (op & UINT64_C(`24`)) << `18`;
7451	Value \|= (op & UINT64_C(`7`)) << `5`;
7452	// op: Rs32
7453	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7454	op &= UINT64_C(`31`);
7455	op <<= `16`;
7456	Value \|= op;
7457	// op: Rx32
7458	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7459	op &= UINT64_C(`31`);
7460	Value \|= op;
7461	break;
7462	}
7463	case Hexagon::S2_asl_i_r_acc:
7464	case Hexagon::S2_asl_i_r_and:
7465	case Hexagon::S2_asl_i_r_nac:
7466	case Hexagon::S2_asl_i_r_or:
7467	case Hexagon::S2_asl_i_r_xacc:
7468	case Hexagon::S2_asr_i_r_acc:
7469	case Hexagon::S2_asr_i_r_and:
7470	case Hexagon::S2_asr_i_r_nac:
7471	case Hexagon::S2_asr_i_r_or:
7472	case Hexagon::S2_lsr_i_r_acc:
7473	case Hexagon::S2_lsr_i_r_and:
7474	case Hexagon::S2_lsr_i_r_nac:
7475	case Hexagon::S2_lsr_i_r_or:
7476	case Hexagon::S2_lsr_i_r_xacc:
7477	case Hexagon::S6_rol_i_r_acc:
7478	case Hexagon::S6_rol_i_r_and:
7479	case Hexagon::S6_rol_i_r_nac:
7480	case Hexagon::S6_rol_i_r_or:
7481	case Hexagon::S6_rol_i_r_xacc: {
7482	// op: Ii
7483	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7484	op &= UINT64_C(`31`);
7485	op <<= `8`;
7486	Value \|= op;
7487	// op: Rs32
7488	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7489	op &= UINT64_C(`31`);
7490	op <<= `16`;
7491	Value \|= op;
7492	// op: Rx32
7493	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7494	op &= UINT64_C(`31`);
7495	Value \|= op;
7496	break;
7497	}
7498	case Hexagon::L2_ploadrdf_io:
7499	case Hexagon::L2_ploadrdfnew_io:
7500	case Hexagon::L2_ploadrdt_io:
7501	case Hexagon::L2_ploadrdtnew_io: {
7502	// op: Ii
7503	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7504	op &= UINT64_C(`504`);
7505	op <<= `2`;
7506	Value \|= op;
7507	// op: Pt4
7508	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7509	op &= UINT64_C(`3`);
7510	op <<= `11`;
7511	Value \|= op;
7512	// op: Rs32
7513	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7514	op &= UINT64_C(`31`);
7515	op <<= `16`;
7516	Value \|= op;
7517	// op: Rdd32
7518	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7519	op &= UINT64_C(`31`);
7520	Value \|= op;
7521	break;
7522	}
7523	case Hexagon::S2_pstorerinewf_pi:
7524	case Hexagon::S2_pstorerinewfnew_pi:
7525	case Hexagon::S2_pstorerinewt_pi:
7526	case Hexagon::S2_pstorerinewtnew_pi: {
7527	// op: Ii
7528	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7529	op &= UINT64_C(`60`);
7530	op <<= `1`;
7531	Value \|= op;
7532	// op: Pv4
7533	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7534	op &= UINT64_C(`3`);
7535	Value \|= op;
7536	// op: Nt8
7537	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7538	op &= UINT64_C(`7`);
7539	op <<= `8`;
7540	Value \|= op;
7541	// op: Rx32
7542	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7543	op &= UINT64_C(`31`);
7544	op <<= `16`;
7545	Value \|= op;
7546	break;
7547	}
7548	case Hexagon::S2_pstorerif_pi:
7549	case Hexagon::S2_pstorerifnew_pi:
7550	case Hexagon::S2_pstorerit_pi:
7551	case Hexagon::S2_pstoreritnew_pi: {
7552	// op: Ii
7553	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7554	op &= UINT64_C(`60`);
7555	op <<= `1`;
7556	Value \|= op;
7557	// op: Pv4
7558	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7559	op &= UINT64_C(`3`);
7560	Value \|= op;
7561	// op: Rt32
7562	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7563	op &= UINT64_C(`31`);
7564	op <<= `8`;
7565	Value \|= op;
7566	// op: Rx32
7567	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7568	op &= UINT64_C(`31`);
7569	op <<= `16`;
7570	Value \|= op;
7571	break;
7572	}
7573	case Hexagon::L2_loadri_pci: {
7574	// op: Ii
7575	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7576	op &= UINT64_C(`60`);
7577	op <<= `3`;
7578	Value \|= op;
7579	// op: Mu2
7580	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7581	op &= UINT64_C(`1`);
7582	op <<= `13`;
7583	Value \|= op;
7584	// op: Rd32
7585	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7586	op &= UINT64_C(`31`);
7587	Value \|= op;
7588	// op: Rx32
7589	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7590	op &= UINT64_C(`31`);
7591	op <<= `16`;
7592	Value \|= op;
7593	break;
7594	}
7595	case Hexagon::L2_loadbsw4_pci:
7596	case Hexagon::L2_loadbzw4_pci: {
7597	// op: Ii
7598	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7599	op &= UINT64_C(`60`);
7600	op <<= `3`;
7601	Value \|= op;
7602	// op: Mu2
7603	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7604	op &= UINT64_C(`1`);
7605	op <<= `13`;
7606	Value \|= op;
7607	// op: Rdd32
7608	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7609	op &= UINT64_C(`31`);
7610	Value \|= op;
7611	// op: Rx32
7612	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7613	op &= UINT64_C(`31`);
7614	op <<= `16`;
7615	Value \|= op;
7616	break;
7617	}
7618	case Hexagon::L2_loadri_pi: {
7619	// op: Ii
7620	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7621	op &= UINT64_C(`60`);
7622	op <<= `3`;
7623	Value \|= op;
7624	// op: Rd32
7625	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7626	op &= UINT64_C(`31`);
7627	Value \|= op;
7628	// op: Rx32
7629	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7630	op &= UINT64_C(`31`);
7631	op <<= `16`;
7632	Value \|= op;
7633	break;
7634	}
7635	case Hexagon::L2_loadbsw4_pi:
7636	case Hexagon::L2_loadbzw4_pi: {
7637	// op: Ii
7638	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7639	op &= UINT64_C(`60`);
7640	op <<= `3`;
7641	Value \|= op;
7642	// op: Rdd32
7643	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7644	op &= UINT64_C(`31`);
7645	Value \|= op;
7646	// op: Rx32
7647	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7648	op &= UINT64_C(`31`);
7649	op <<= `16`;
7650	Value \|= op;
7651	break;
7652	}
7653	case Hexagon::L2_ploadrbf_io:
7654	case Hexagon::L2_ploadrbfnew_io:
7655	case Hexagon::L2_ploadrbt_io:
7656	case Hexagon::L2_ploadrbtnew_io:
7657	case Hexagon::L2_ploadrubf_io:
7658	case Hexagon::L2_ploadrubfnew_io:
7659	case Hexagon::L2_ploadrubt_io:
7660	case Hexagon::L2_ploadrubtnew_io: {
7661	// op: Ii
7662	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7663	op &= UINT64_C(`63`);
7664	op <<= `5`;
7665	Value \|= op;
7666	// op: Pt4
7667	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7668	op &= UINT64_C(`3`);
7669	op <<= `11`;
7670	Value \|= op;
7671	// op: Rs32
7672	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7673	op &= UINT64_C(`31`);
7674	op <<= `16`;
7675	Value \|= op;
7676	// op: Rd32
7677	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7678	op &= UINT64_C(`31`);
7679	Value \|= op;
7680	break;
7681	}
7682	case Hexagon::S2_insertp: {
7683	// op: Ii
7684	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7685	op &= UINT64_C(`63`);
7686	op <<= `8`;
7687	Value \|= op;
7688	// op: II
7689	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7690	Value \|= (op & UINT64_C(`56`)) << `18`;
7691	Value \|= (op & UINT64_C(`7`)) << `5`;
7692	// op: Rss32
7693	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7694	op &= UINT64_C(`31`);
7695	op <<= `16`;
7696	Value \|= op;
7697	// op: Rxx32
7698	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7699	op &= UINT64_C(`31`);
7700	Value \|= op;
7701	break;
7702	}
7703	case Hexagon::S2_asl_i_p_acc:
7704	case Hexagon::S2_asl_i_p_and:
7705	case Hexagon::S2_asl_i_p_nac:
7706	case Hexagon::S2_asl_i_p_or:
7707	case Hexagon::S2_asl_i_p_xacc:
7708	case Hexagon::S2_asr_i_p_acc:
7709	case Hexagon::S2_asr_i_p_and:
7710	case Hexagon::S2_asr_i_p_nac:
7711	case Hexagon::S2_asr_i_p_or:
7712	case Hexagon::S2_lsr_i_p_acc:
7713	case Hexagon::S2_lsr_i_p_and:
7714	case Hexagon::S2_lsr_i_p_nac:
7715	case Hexagon::S2_lsr_i_p_or:
7716	case Hexagon::S2_lsr_i_p_xacc:
7717	case Hexagon::S6_rol_i_p_acc:
7718	case Hexagon::S6_rol_i_p_and:
7719	case Hexagon::S6_rol_i_p_nac:
7720	case Hexagon::S6_rol_i_p_or:
7721	case Hexagon::S6_rol_i_p_xacc: {
7722	// op: Ii
7723	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7724	op &= UINT64_C(`63`);
7725	op <<= `8`;
7726	Value \|= op;
7727	// op: Rss32
7728	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7729	op &= UINT64_C(`31`);
7730	op <<= `16`;
7731	Value \|= op;
7732	// op: Rxx32
7733	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7734	op &= UINT64_C(`31`);
7735	Value \|= op;
7736	break;
7737	}
7738	case Hexagon::S2_vspliceib: {
7739	// op: Ii
7740	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7741	op &= UINT64_C(`7`);
7742	op <<= `5`;
7743	Value \|= op;
7744	// op: Rss32
7745	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7746	op &= UINT64_C(`31`);
7747	op <<= `16`;
7748	Value \|= op;
7749	// op: Rtt32
7750	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7751	op &= UINT64_C(`31`);
7752	op <<= `8`;
7753	Value \|= op;
7754	// op: Rdd32
7755	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7756	op &= UINT64_C(`31`);
7757	Value \|= op;
7758	break;
7759	}
7760	case Hexagon::S2_addasl_rrri: {
7761	// op: Ii
7762	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7763	op &= UINT64_C(`7`);
7764	op <<= `5`;
7765	Value \|= op;
7766	// op: Rt32
7767	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7768	op &= UINT64_C(`31`);
7769	op <<= `8`;
7770	Value \|= op;
7771	// op: Rs32
7772	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7773	op &= UINT64_C(`31`);
7774	op <<= `16`;
7775	Value \|= op;
7776	// op: Rd32
7777	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7778	op &= UINT64_C(`31`);
7779	Value \|= op;
7780	break;
7781	}
7782	case Hexagon::S2_valignib: {
7783	// op: Ii
7784	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7785	op &= UINT64_C(`7`);
7786	op <<= `5`;
7787	Value \|= op;
7788	// op: Rtt32
7789	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7790	op &= UINT64_C(`31`);
7791	op <<= `8`;
7792	Value \|= op;
7793	// op: Rss32
7794	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7795	op &= UINT64_C(`31`);
7796	op <<= `16`;
7797	Value \|= op;
7798	// op: Rdd32
7799	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7800	op &= UINT64_C(`31`);
7801	Value \|= op;
7802	break;
7803	}
7804	case Hexagon::V6_valignbi:
7805	case Hexagon::V6_vlalignbi:
7806	case Hexagon::V6_vlutvvbi: {
7807	// op: Ii
7808	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7809	op &= UINT64_C(`7`);
7810	op <<= `5`;
7811	Value \|= op;
7812	// op: Vu32
7813	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7814	op &= UINT64_C(`31`);
7815	op <<= `8`;
7816	Value \|= op;
7817	// op: Vv32
7818	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7819	op &= UINT64_C(`31`);
7820	op <<= `16`;
7821	Value \|= op;
7822	// op: Vd32
7823	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7824	op &= UINT64_C(`31`);
7825	Value \|= op;
7826	break;
7827	}
7828	case Hexagon::V6_vlutvwhi: {
7829	// op: Ii
7830	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7831	op &= UINT64_C(`7`);
7832	op <<= `5`;
7833	Value \|= op;
7834	// op: Vu32
7835	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7836	op &= UINT64_C(`31`);
7837	op <<= `8`;
7838	Value \|= op;
7839	// op: Vv32
7840	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7841	op &= UINT64_C(`31`);
7842	op <<= `16`;
7843	Value \|= op;
7844	// op: Vdd32
7845	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7846	op &= UINT64_C(`31`);
7847	Value \|= op;
7848	break;
7849	}
7850	case Hexagon::V6_vS32b_new_npred_pi:
7851	case Hexagon::V6_vS32b_new_pred_pi:
7852	case Hexagon::V6_vS32b_nt_new_npred_pi:
7853	case Hexagon::V6_vS32b_nt_new_pred_pi: {
7854	// op: Ii
7855	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7856	op &= UINT64_C(`7`);
7857	op <<= `8`;
7858	Value \|= op;
7859	// op: Pv4
7860	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7861	op &= UINT64_C(`3`);
7862	op <<= `11`;
7863	Value \|= op;
7864	// op: Os8
7865	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7866	op &= UINT64_C(`7`);
7867	Value \|= op;
7868	// op: Rx32
7869	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7870	op &= UINT64_C(`31`);
7871	op <<= `16`;
7872	Value \|= op;
7873	break;
7874	}
7875	case Hexagon::V6_zLd_pred_pi: {
7876	// op: Ii
7877	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7878	op &= UINT64_C(`7`);
7879	op <<= `8`;
7880	Value \|= op;
7881	// op: Pv4
7882	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7883	op &= UINT64_C(`3`);
7884	op <<= `11`;
7885	Value \|= op;
7886	// op: Rx32
7887	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7888	op &= UINT64_C(`31`);
7889	op <<= `16`;
7890	Value \|= op;
7891	break;
7892	}
7893	case Hexagon::V6_vS32Ub_npred_pi:
7894	case Hexagon::V6_vS32Ub_pred_pi:
7895	case Hexagon::V6_vS32b_npred_pi:
7896	case Hexagon::V6_vS32b_nt_npred_pi:
7897	case Hexagon::V6_vS32b_nt_pred_pi:
7898	case Hexagon::V6_vS32b_pred_pi: {
7899	// op: Ii
7900	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7901	op &= UINT64_C(`7`);
7902	op <<= `8`;
7903	Value \|= op;
7904	// op: Pv4
7905	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7906	op &= UINT64_C(`3`);
7907	op <<= `11`;
7908	Value \|= op;
7909	// op: Vs32
7910	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7911	op &= UINT64_C(`31`);
7912	Value \|= op;
7913	// op: Rx32
7914	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7915	op &= UINT64_C(`31`);
7916	op <<= `16`;
7917	Value \|= op;
7918	break;
7919	}
7920	case Hexagon::V6_vS32b_nqpred_pi:
7921	case Hexagon::V6_vS32b_nt_nqpred_pi:
7922	case Hexagon::V6_vS32b_nt_qpred_pi:
7923	case Hexagon::V6_vS32b_qpred_pi: {
7924	// op: Ii
7925	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7926	op &= UINT64_C(`7`);
7927	op <<= `8`;
7928	Value \|= op;
7929	// op: Qv4
7930	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7931	op &= UINT64_C(`3`);
7932	op <<= `11`;
7933	Value \|= op;
7934	// op: Vs32
7935	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7936	op &= UINT64_C(`31`);
7937	Value \|= op;
7938	// op: Rx32
7939	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7940	op &= UINT64_C(`31`);
7941	op <<= `16`;
7942	Value \|= op;
7943	break;
7944	}
7945	case Hexagon::V6_vL32Ub_pi:
7946	case Hexagon::V6_vL32b_cur_pi:
7947	case Hexagon::V6_vL32b_nt_cur_pi:
7948	case Hexagon::V6_vL32b_nt_pi:
7949	case Hexagon::V6_vL32b_nt_tmp_pi:
7950	case Hexagon::V6_vL32b_pi:
7951	case Hexagon::V6_vL32b_tmp_pi: {
7952	// op: Ii
7953	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7954	op &= UINT64_C(`7`);
7955	op <<= `8`;
7956	Value \|= op;
7957	// op: Vd32
7958	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7959	op &= UINT64_C(`31`);
7960	Value \|= op;
7961	// op: Rx32
7962	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
7963	op &= UINT64_C(`31`);
7964	op <<= `16`;
7965	Value \|= op;
7966	break;
7967	}
7968	case Hexagon::S4_vrcrotate_acc: {
7969	// op: Ii
7970	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
7971	Value \|= (op & UINT64_C(`2`)) << `12`;
7972	Value \|= (op & UINT64_C(`1`)) << `5`;
7973	// op: Rss32
7974	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
7975	op &= UINT64_C(`31`);
7976	op <<= `16`;
7977	Value \|= op;
7978	// op: Rt32
7979	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
7980	op &= UINT64_C(`31`);
7981	op <<= `8`;
7982	Value \|= op;
7983	// op: Rxx32
7984	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
7985	op &= UINT64_C(`31`);
7986	Value \|= op;
7987	break;
7988	}
7989	case Hexagon::L4_ploadrbf_rr:
7990	case Hexagon::L4_ploadrbfnew_rr:
7991	case Hexagon::L4_ploadrbt_rr:
7992	case Hexagon::L4_ploadrbtnew_rr:
7993	case Hexagon::L4_ploadrhf_rr:
7994	case Hexagon::L4_ploadrhfnew_rr:
7995	case Hexagon::L4_ploadrht_rr:
7996	case Hexagon::L4_ploadrhtnew_rr:
7997	case Hexagon::L4_ploadrif_rr:
7998	case Hexagon::L4_ploadrifnew_rr:
7999	case Hexagon::L4_ploadrit_rr:
8000	case Hexagon::L4_ploadritnew_rr:
8001	case Hexagon::L4_ploadrubf_rr:
8002	case Hexagon::L4_ploadrubfnew_rr:
8003	case Hexagon::L4_ploadrubt_rr:
8004	case Hexagon::L4_ploadrubtnew_rr:
8005	case Hexagon::L4_ploadruhf_rr:
8006	case Hexagon::L4_ploadruhfnew_rr:
8007	case Hexagon::L4_ploadruht_rr:
8008	case Hexagon::L4_ploadruhtnew_rr: {
8009	// op: Ii
8010	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8011	Value \|= (op & UINT64_C(`2`)) << `12`;
8012	Value \|= (op & UINT64_C(`1`)) << `7`;
8013	// op: Pv4
8014	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8015	op &= UINT64_C(`3`);
8016	op <<= `5`;
8017	Value \|= op;
8018	// op: Rs32
8019	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8020	op &= UINT64_C(`31`);
8021	op <<= `16`;
8022	Value \|= op;
8023	// op: Rt32
8024	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8025	op &= UINT64_C(`31`);
8026	op <<= `8`;
8027	Value \|= op;
8028	// op: Rd32
8029	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8030	op &= UINT64_C(`31`);
8031	Value \|= op;
8032	break;
8033	}
8034	case Hexagon::L4_ploadrdf_rr:
8035	case Hexagon::L4_ploadrdfnew_rr:
8036	case Hexagon::L4_ploadrdt_rr:
8037	case Hexagon::L4_ploadrdtnew_rr: {
8038	// op: Ii
8039	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8040	Value \|= (op & UINT64_C(`2`)) << `12`;
8041	Value \|= (op & UINT64_C(`1`)) << `7`;
8042	// op: Pv4
8043	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8044	op &= UINT64_C(`3`);
8045	op <<= `5`;
8046	Value \|= op;
8047	// op: Rs32
8048	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8049	op &= UINT64_C(`31`);
8050	op <<= `16`;
8051	Value \|= op;
8052	// op: Rt32
8053	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8054	op &= UINT64_C(`31`);
8055	op <<= `8`;
8056	Value \|= op;
8057	// op: Rdd32
8058	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8059	op &= UINT64_C(`31`);
8060	Value \|= op;
8061	break;
8062	}
8063	case Hexagon::V6_vrmpybusi_acc:
8064	case Hexagon::V6_vrmpyubi_acc:
8065	case Hexagon::V6_vrsadubi_acc: {
8066	// op: Ii
8067	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8068	op &= UINT64_C(`1`);
8069	op <<= `5`;
8070	Value \|= op;
8071	// op: Vuu32
8072	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8073	op &= UINT64_C(`31`);
8074	op <<= `8`;
8075	Value \|= op;
8076	// op: Rt32
8077	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8078	op &= UINT64_C(`31`);
8079	op <<= `16`;
8080	Value \|= op;
8081	// op: Vxx32
8082	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8083	op &= UINT64_C(`31`);
8084	Value \|= op;
8085	break;
8086	}
8087	case Hexagon::L2_ploadrdf_pi:
8088	case Hexagon::L2_ploadrdfnew_pi:
8089	case Hexagon::L2_ploadrdt_pi:
8090	case Hexagon::L2_ploadrdtnew_pi: {
8091	// op: Ii
8092	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8093	op &= UINT64_C(`120`);
8094	op <<= `2`;
8095	Value \|= op;
8096	// op: Pt4
8097	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8098	op &= UINT64_C(`3`);
8099	op <<= `9`;
8100	Value \|= op;
8101	// op: Rdd32
8102	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8103	op &= UINT64_C(`31`);
8104	Value \|= op;
8105	// op: Rx32
8106	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8107	op &= UINT64_C(`31`);
8108	op <<= `16`;
8109	Value \|= op;
8110	break;
8111	}
8112	case Hexagon::L2_loadalignb_pci: {
8113	// op: Ii
8114	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8115	op &= UINT64_C(`15`);
8116	op <<= `5`;
8117	Value \|= op;
8118	// op: Mu2
8119	op = getMachineOpValue(MI, MO: MI.getOperand(i: `5`), Fixups, STI);
8120	op &= UINT64_C(`1`);
8121	op <<= `13`;
8122	Value \|= op;
8123	// op: Ryy32
8124	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8125	op &= UINT64_C(`31`);
8126	Value \|= op;
8127	// op: Rx32
8128	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8129	op &= UINT64_C(`31`);
8130	op <<= `16`;
8131	Value \|= op;
8132	break;
8133	}
8134	case Hexagon::L2_ploadrbf_pi:
8135	case Hexagon::L2_ploadrbfnew_pi:
8136	case Hexagon::L2_ploadrbt_pi:
8137	case Hexagon::L2_ploadrbtnew_pi:
8138	case Hexagon::L2_ploadrubf_pi:
8139	case Hexagon::L2_ploadrubfnew_pi:
8140	case Hexagon::L2_ploadrubt_pi:
8141	case Hexagon::L2_ploadrubtnew_pi: {
8142	// op: Ii
8143	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8144	op &= UINT64_C(`15`);
8145	op <<= `5`;
8146	Value \|= op;
8147	// op: Pt4
8148	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8149	op &= UINT64_C(`3`);
8150	op <<= `9`;
8151	Value \|= op;
8152	// op: Rd32
8153	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8154	op &= UINT64_C(`31`);
8155	Value \|= op;
8156	// op: Rx32
8157	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8158	op &= UINT64_C(`31`);
8159	op <<= `16`;
8160	Value \|= op;
8161	break;
8162	}
8163	case Hexagon::L2_loadalignb_pi: {
8164	// op: Ii
8165	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8166	op &= UINT64_C(`15`);
8167	op <<= `5`;
8168	Value \|= op;
8169	// op: Ryy32
8170	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8171	op &= UINT64_C(`31`);
8172	Value \|= op;
8173	// op: Rx32
8174	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8175	op &= UINT64_C(`31`);
8176	op <<= `16`;
8177	Value \|= op;
8178	break;
8179	}
8180	case Hexagon::V6_v6mpyhubs10_vxx:
8181	case Hexagon::V6_v6mpyvubs10_vxx: {
8182	// op: Ii
8183	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8184	op &= UINT64_C(`3`);
8185	op <<= `5`;
8186	Value \|= op;
8187	// op: Vuu32
8188	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8189	op &= UINT64_C(`31`);
8190	op <<= `8`;
8191	Value \|= op;
8192	// op: Vvv32
8193	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8194	op &= UINT64_C(`31`);
8195	op <<= `16`;
8196	Value \|= op;
8197	// op: Vxx32
8198	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8199	op &= UINT64_C(`31`);
8200	Value \|= op;
8201	break;
8202	}
8203	case Hexagon::L2_loadalignh_pci: {
8204	// op: Ii
8205	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8206	op &= UINT64_C(`30`);
8207	op <<= `4`;
8208	Value \|= op;
8209	// op: Mu2
8210	op = getMachineOpValue(MI, MO: MI.getOperand(i: `5`), Fixups, STI);
8211	op &= UINT64_C(`1`);
8212	op <<= `13`;
8213	Value \|= op;
8214	// op: Ryy32
8215	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8216	op &= UINT64_C(`31`);
8217	Value \|= op;
8218	// op: Rx32
8219	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8220	op &= UINT64_C(`31`);
8221	op <<= `16`;
8222	Value \|= op;
8223	break;
8224	}
8225	case Hexagon::L2_ploadrhf_pi:
8226	case Hexagon::L2_ploadrhfnew_pi:
8227	case Hexagon::L2_ploadrht_pi:
8228	case Hexagon::L2_ploadrhtnew_pi:
8229	case Hexagon::L2_ploadruhf_pi:
8230	case Hexagon::L2_ploadruhfnew_pi:
8231	case Hexagon::L2_ploadruht_pi:
8232	case Hexagon::L2_ploadruhtnew_pi: {
8233	// op: Ii
8234	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8235	op &= UINT64_C(`30`);
8236	op <<= `4`;
8237	Value \|= op;
8238	// op: Pt4
8239	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8240	op &= UINT64_C(`3`);
8241	op <<= `9`;
8242	Value \|= op;
8243	// op: Rd32
8244	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8245	op &= UINT64_C(`31`);
8246	Value \|= op;
8247	// op: Rx32
8248	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8249	op &= UINT64_C(`31`);
8250	op <<= `16`;
8251	Value \|= op;
8252	break;
8253	}
8254	case Hexagon::L2_loadalignh_pi: {
8255	// op: Ii
8256	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8257	op &= UINT64_C(`30`);
8258	op <<= `4`;
8259	Value \|= op;
8260	// op: Ryy32
8261	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8262	op &= UINT64_C(`31`);
8263	Value \|= op;
8264	// op: Rx32
8265	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8266	op &= UINT64_C(`31`);
8267	op <<= `16`;
8268	Value \|= op;
8269	break;
8270	}
8271	case Hexagon::L2_ploadrif_pi:
8272	case Hexagon::L2_ploadrifnew_pi:
8273	case Hexagon::L2_ploadrit_pi:
8274	case Hexagon::L2_ploadritnew_pi: {
8275	// op: Ii
8276	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8277	op &= UINT64_C(`60`);
8278	op <<= `3`;
8279	Value \|= op;
8280	// op: Pt4
8281	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8282	op &= UINT64_C(`3`);
8283	op <<= `9`;
8284	Value \|= op;
8285	// op: Rd32
8286	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8287	op &= UINT64_C(`31`);
8288	Value \|= op;
8289	// op: Rx32
8290	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8291	op &= UINT64_C(`31`);
8292	op <<= `16`;
8293	Value \|= op;
8294	break;
8295	}
8296	case Hexagon::V6_vlutvvb_oracci: {
8297	// op: Ii
8298	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8299	op &= UINT64_C(`7`);
8300	op <<= `5`;
8301	Value \|= op;
8302	// op: Vu32
8303	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8304	op &= UINT64_C(`31`);
8305	op <<= `8`;
8306	Value \|= op;
8307	// op: Vv32
8308	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8309	op &= UINT64_C(`31`);
8310	op <<= `16`;
8311	Value \|= op;
8312	// op: Vx32
8313	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8314	op &= UINT64_C(`31`);
8315	Value \|= op;
8316	break;
8317	}
8318	case Hexagon::V6_vlutvwh_oracci: {
8319	// op: Ii
8320	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8321	op &= UINT64_C(`7`);
8322	op <<= `5`;
8323	Value \|= op;
8324	// op: Vu32
8325	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8326	op &= UINT64_C(`31`);
8327	op <<= `8`;
8328	Value \|= op;
8329	// op: Vv32
8330	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8331	op &= UINT64_C(`31`);
8332	op <<= `16`;
8333	Value \|= op;
8334	// op: Vxx32
8335	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8336	op &= UINT64_C(`31`);
8337	Value \|= op;
8338	break;
8339	}
8340	case Hexagon::V6_vL32b_cur_npred_pi:
8341	case Hexagon::V6_vL32b_cur_pred_pi:
8342	case Hexagon::V6_vL32b_npred_pi:
8343	case Hexagon::V6_vL32b_nt_cur_npred_pi:
8344	case Hexagon::V6_vL32b_nt_cur_pred_pi:
8345	case Hexagon::V6_vL32b_nt_npred_pi:
8346	case Hexagon::V6_vL32b_nt_pred_pi:
8347	case Hexagon::V6_vL32b_nt_tmp_npred_pi:
8348	case Hexagon::V6_vL32b_nt_tmp_pred_pi:
8349	case Hexagon::V6_vL32b_pred_pi:
8350	case Hexagon::V6_vL32b_tmp_npred_pi:
8351	case Hexagon::V6_vL32b_tmp_pred_pi: {
8352	// op: Ii
8353	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8354	op &= UINT64_C(`7`);
8355	op <<= `8`;
8356	Value \|= op;
8357	// op: Pv4
8358	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8359	op &= UINT64_C(`3`);
8360	op <<= `11`;
8361	Value \|= op;
8362	// op: Vd32
8363	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8364	op &= UINT64_C(`31`);
8365	Value \|= op;
8366	// op: Rx32
8367	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8368	op &= UINT64_C(`31`);
8369	op <<= `16`;
8370	Value \|= op;
8371	break;
8372	}
8373	case Hexagon::S2_storerbnew_pbr:
8374	case Hexagon::S2_storerbnew_pcr:
8375	case Hexagon::S2_storerbnew_pr:
8376	case Hexagon::S2_storerhnew_pbr:
8377	case Hexagon::S2_storerhnew_pcr:
8378	case Hexagon::S2_storerhnew_pr:
8379	case Hexagon::S2_storerinew_pbr:
8380	case Hexagon::S2_storerinew_pcr:
8381	case Hexagon::S2_storerinew_pr: {
8382	// op: Mu2
8383	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8384	op &= UINT64_C(`1`);
8385	op <<= `13`;
8386	Value \|= op;
8387	// op: Nt8
8388	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8389	op &= UINT64_C(`7`);
8390	op <<= `8`;
8391	Value \|= op;
8392	// op: Rx32
8393	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8394	op &= UINT64_C(`31`);
8395	op <<= `16`;
8396	Value \|= op;
8397	break;
8398	}
8399	case Hexagon::V6_vS32b_new_ppu:
8400	case Hexagon::V6_vS32b_nt_new_ppu: {
8401	// op: Mu2
8402	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8403	op &= UINT64_C(`1`);
8404	op <<= `13`;
8405	Value \|= op;
8406	// op: Os8
8407	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8408	op &= UINT64_C(`7`);
8409	Value \|= op;
8410	// op: Rx32
8411	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8412	op &= UINT64_C(`31`);
8413	op <<= `16`;
8414	Value \|= op;
8415	break;
8416	}
8417	case Hexagon::S2_storerb_pbr:
8418	case Hexagon::S2_storerb_pcr:
8419	case Hexagon::S2_storerb_pr:
8420	case Hexagon::S2_storerf_pbr:
8421	case Hexagon::S2_storerf_pcr:
8422	case Hexagon::S2_storerf_pr:
8423	case Hexagon::S2_storerh_pbr:
8424	case Hexagon::S2_storerh_pcr:
8425	case Hexagon::S2_storerh_pr:
8426	case Hexagon::S2_storeri_pbr:
8427	case Hexagon::S2_storeri_pcr:
8428	case Hexagon::S2_storeri_pr: {
8429	// op: Mu2
8430	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8431	op &= UINT64_C(`1`);
8432	op <<= `13`;
8433	Value \|= op;
8434	// op: Rt32
8435	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8436	op &= UINT64_C(`31`);
8437	op <<= `8`;
8438	Value \|= op;
8439	// op: Rx32
8440	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8441	op &= UINT64_C(`31`);
8442	op <<= `16`;
8443	Value \|= op;
8444	break;
8445	}
8446	case Hexagon::S2_storerd_pbr:
8447	case Hexagon::S2_storerd_pcr:
8448	case Hexagon::S2_storerd_pr: {
8449	// op: Mu2
8450	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8451	op &= UINT64_C(`1`);
8452	op <<= `13`;
8453	Value \|= op;
8454	// op: Rtt32
8455	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8456	op &= UINT64_C(`31`);
8457	op <<= `8`;
8458	Value \|= op;
8459	// op: Rx32
8460	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8461	op &= UINT64_C(`31`);
8462	op <<= `16`;
8463	Value \|= op;
8464	break;
8465	}
8466	case Hexagon::V6_vS32b_srls_ppu:
8467	case Hexagon::V6_zLd_ppu: {
8468	// op: Mu2
8469	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8470	op &= UINT64_C(`1`);
8471	op <<= `13`;
8472	Value \|= op;
8473	// op: Rx32
8474	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8475	op &= UINT64_C(`31`);
8476	op <<= `16`;
8477	Value \|= op;
8478	break;
8479	}
8480	case Hexagon::V6_vS32Ub_ppu:
8481	case Hexagon::V6_vS32b_nt_ppu:
8482	case Hexagon::V6_vS32b_ppu: {
8483	// op: Mu2
8484	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8485	op &= UINT64_C(`1`);
8486	op <<= `13`;
8487	Value \|= op;
8488	// op: Vs32
8489	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8490	op &= UINT64_C(`31`);
8491	Value \|= op;
8492	// op: Rx32
8493	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8494	op &= UINT64_C(`31`);
8495	op <<= `16`;
8496	Value \|= op;
8497	break;
8498	}
8499	case Hexagon::L2_loadbsw2_pbr:
8500	case Hexagon::L2_loadbsw2_pcr:
8501	case Hexagon::L2_loadbsw2_pr:
8502	case Hexagon::L2_loadbzw2_pbr:
8503	case Hexagon::L2_loadbzw2_pcr:
8504	case Hexagon::L2_loadbzw2_pr:
8505	case Hexagon::L2_loadrb_pbr:
8506	case Hexagon::L2_loadrb_pcr:
8507	case Hexagon::L2_loadrb_pr:
8508	case Hexagon::L2_loadrh_pbr:
8509	case Hexagon::L2_loadrh_pcr:
8510	case Hexagon::L2_loadrh_pr:
8511	case Hexagon::L2_loadri_pbr:
8512	case Hexagon::L2_loadri_pcr:
8513	case Hexagon::L2_loadri_pr:
8514	case Hexagon::L2_loadrub_pbr:
8515	case Hexagon::L2_loadrub_pcr:
8516	case Hexagon::L2_loadrub_pr:
8517	case Hexagon::L2_loadruh_pbr:
8518	case Hexagon::L2_loadruh_pcr:
8519	case Hexagon::L2_loadruh_pr: {
8520	// op: Mu2
8521	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8522	op &= UINT64_C(`1`);
8523	op <<= `13`;
8524	Value \|= op;
8525	// op: Rd32
8526	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8527	op &= UINT64_C(`31`);
8528	Value \|= op;
8529	// op: Rx32
8530	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8531	op &= UINT64_C(`31`);
8532	op <<= `16`;
8533	Value \|= op;
8534	break;
8535	}
8536	case Hexagon::L2_loadbsw4_pbr:
8537	case Hexagon::L2_loadbsw4_pcr:
8538	case Hexagon::L2_loadbsw4_pr:
8539	case Hexagon::L2_loadbzw4_pbr:
8540	case Hexagon::L2_loadbzw4_pcr:
8541	case Hexagon::L2_loadbzw4_pr:
8542	case Hexagon::L2_loadrd_pbr:
8543	case Hexagon::L2_loadrd_pcr:
8544	case Hexagon::L2_loadrd_pr: {
8545	// op: Mu2
8546	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8547	op &= UINT64_C(`1`);
8548	op <<= `13`;
8549	Value \|= op;
8550	// op: Rdd32
8551	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8552	op &= UINT64_C(`31`);
8553	Value \|= op;
8554	// op: Rx32
8555	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8556	op &= UINT64_C(`31`);
8557	op <<= `16`;
8558	Value \|= op;
8559	break;
8560	}
8561	case Hexagon::V6_vL32Ub_ppu:
8562	case Hexagon::V6_vL32b_cur_ppu:
8563	case Hexagon::V6_vL32b_nt_cur_ppu:
8564	case Hexagon::V6_vL32b_nt_ppu:
8565	case Hexagon::V6_vL32b_nt_tmp_ppu:
8566	case Hexagon::V6_vL32b_ppu:
8567	case Hexagon::V6_vL32b_tmp_ppu: {
8568	// op: Mu2
8569	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8570	op &= UINT64_C(`1`);
8571	op <<= `13`;
8572	Value \|= op;
8573	// op: Vd32
8574	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8575	op &= UINT64_C(`31`);
8576	Value \|= op;
8577	// op: Rx32
8578	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8579	op &= UINT64_C(`31`);
8580	op <<= `16`;
8581	Value \|= op;
8582	break;
8583	}
8584	case Hexagon::L2_loadalignb_pbr:
8585	case Hexagon::L2_loadalignb_pcr:
8586	case Hexagon::L2_loadalignb_pr:
8587	case Hexagon::L2_loadalignh_pbr:
8588	case Hexagon::L2_loadalignh_pcr:
8589	case Hexagon::L2_loadalignh_pr: {
8590	// op: Mu2
8591	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8592	op &= UINT64_C(`1`);
8593	op <<= `13`;
8594	Value \|= op;
8595	// op: Ryy32
8596	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8597	op &= UINT64_C(`31`);
8598	Value \|= op;
8599	// op: Rx32
8600	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8601	op &= UINT64_C(`31`);
8602	op <<= `16`;
8603	Value \|= op;
8604	break;
8605	}
8606	case Hexagon::C2_all8:
8607	case Hexagon::C2_any8:
8608	case Hexagon::C2_not: {
8609	// op: Ps4
8610	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8611	op &= UINT64_C(`3`);
8612	op <<= `16`;
8613	Value \|= op;
8614	// op: Pd4
8615	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8616	op &= UINT64_C(`3`);
8617	Value \|= op;
8618	break;
8619	}
8620	case Hexagon::C2_xor:
8621	case Hexagon::C4_fastcorner9:
8622	case Hexagon::C4_fastcorner9_not: {
8623	// op: Ps4
8624	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8625	op &= UINT64_C(`3`);
8626	op <<= `16`;
8627	Value \|= op;
8628	// op: Pt4
8629	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8630	op &= UINT64_C(`3`);
8631	op <<= `8`;
8632	Value \|= op;
8633	// op: Pd4
8634	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8635	op &= UINT64_C(`3`);
8636	Value \|= op;
8637	break;
8638	}
8639	case Hexagon::C4_and_and:
8640	case Hexagon::C4_and_andn:
8641	case Hexagon::C4_and_or:
8642	case Hexagon::C4_and_orn:
8643	case Hexagon::C4_or_and:
8644	case Hexagon::C4_or_andn:
8645	case Hexagon::C4_or_or:
8646	case Hexagon::C4_or_orn: {
8647	// op: Ps4
8648	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8649	op &= UINT64_C(`3`);
8650	op <<= `16`;
8651	Value \|= op;
8652	// op: Pt4
8653	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8654	op &= UINT64_C(`3`);
8655	op <<= `8`;
8656	Value \|= op;
8657	// op: Pu4
8658	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8659	op &= UINT64_C(`3`);
8660	op <<= `6`;
8661	Value \|= op;
8662	// op: Pd4
8663	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8664	op &= UINT64_C(`3`);
8665	Value \|= op;
8666	break;
8667	}
8668	case Hexagon::C2_vitpack: {
8669	// op: Ps4
8670	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8671	op &= UINT64_C(`3`);
8672	op <<= `16`;
8673	Value \|= op;
8674	// op: Pt4
8675	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8676	op &= UINT64_C(`3`);
8677	op <<= `8`;
8678	Value \|= op;
8679	// op: Rd32
8680	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8681	op &= UINT64_C(`31`);
8682	Value \|= op;
8683	break;
8684	}
8685	case Hexagon::C2_tfrpr: {
8686	// op: Ps4
8687	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8688	op &= UINT64_C(`3`);
8689	op <<= `16`;
8690	Value \|= op;
8691	// op: Rd32
8692	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8693	op &= UINT64_C(`31`);
8694	Value \|= op;
8695	break;
8696	}
8697	case Hexagon::V6_vcmov:
8698	case Hexagon::V6_vncmov: {
8699	// op: Ps4
8700	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8701	op &= UINT64_C(`3`);
8702	op <<= `5`;
8703	Value \|= op;
8704	// op: Vu32
8705	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8706	op &= UINT64_C(`31`);
8707	op <<= `8`;
8708	Value \|= op;
8709	// op: Vd32
8710	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8711	op &= UINT64_C(`31`);
8712	Value \|= op;
8713	break;
8714	}
8715	case Hexagon::V6_vccombine:
8716	case Hexagon::V6_vnccombine: {
8717	// op: Ps4
8718	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8719	op &= UINT64_C(`3`);
8720	op <<= `5`;
8721	Value \|= op;
8722	// op: Vu32
8723	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8724	op &= UINT64_C(`31`);
8725	op <<= `8`;
8726	Value \|= op;
8727	// op: Vv32
8728	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8729	op &= UINT64_C(`31`);
8730	op <<= `16`;
8731	Value \|= op;
8732	// op: Vdd32
8733	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8734	op &= UINT64_C(`31`);
8735	Value \|= op;
8736	break;
8737	}
8738	case Hexagon::Y2_setimask:
8739	case Hexagon::Y2_setprio: {
8740	// op: Pt4
8741	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8742	op &= UINT64_C(`3`);
8743	op <<= `8`;
8744	Value \|= op;
8745	// op: Rs32
8746	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8747	op &= UINT64_C(`31`);
8748	op <<= `16`;
8749	Value \|= op;
8750	break;
8751	}
8752	case Hexagon::C2_and:
8753	case Hexagon::C2_andn:
8754	case Hexagon::C2_or:
8755	case Hexagon::C2_orn: {
8756	// op: Pt4
8757	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8758	op &= UINT64_C(`3`);
8759	op <<= `8`;
8760	Value \|= op;
8761	// op: Ps4
8762	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8763	op &= UINT64_C(`3`);
8764	op <<= `16`;
8765	Value \|= op;
8766	// op: Pd4
8767	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8768	op &= UINT64_C(`3`);
8769	Value \|= op;
8770	break;
8771	}
8772	case Hexagon::C2_mask: {
8773	// op: Pt4
8774	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8775	op &= UINT64_C(`3`);
8776	op <<= `8`;
8777	Value \|= op;
8778	// op: Rdd32
8779	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8780	op &= UINT64_C(`31`);
8781	Value \|= op;
8782	break;
8783	}
8784	case Hexagon::J2_callrf:
8785	case Hexagon::J2_callrt:
8786	case Hexagon::J2_jumprf:
8787	case Hexagon::J2_jumprfnew:
8788	case Hexagon::J2_jumprfnewpt:
8789	case Hexagon::J2_jumprfpt:
8790	case Hexagon::J2_jumprt:
8791	case Hexagon::J2_jumprtnew:
8792	case Hexagon::J2_jumprtnewpt:
8793	case Hexagon::J2_jumprtpt: {
8794	// op: Pu4
8795	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8796	op &= UINT64_C(`3`);
8797	op <<= `8`;
8798	Value \|= op;
8799	// op: Rs32
8800	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8801	op &= UINT64_C(`31`);
8802	op <<= `16`;
8803	Value \|= op;
8804	break;
8805	}
8806	case Hexagon::A2_paddf:
8807	case Hexagon::A2_paddfnew:
8808	case Hexagon::A2_paddt:
8809	case Hexagon::A2_paddtnew:
8810	case Hexagon::A2_pandf:
8811	case Hexagon::A2_pandfnew:
8812	case Hexagon::A2_pandt:
8813	case Hexagon::A2_pandtnew:
8814	case Hexagon::A2_porf:
8815	case Hexagon::A2_porfnew:
8816	case Hexagon::A2_port:
8817	case Hexagon::A2_portnew:
8818	case Hexagon::A2_pxorf:
8819	case Hexagon::A2_pxorfnew:
8820	case Hexagon::A2_pxort:
8821	case Hexagon::A2_pxortnew:
8822	case Hexagon::C2_mux: {
8823	// op: Pu4
8824	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8825	op &= UINT64_C(`3`);
8826	op <<= `5`;
8827	Value \|= op;
8828	// op: Rs32
8829	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8830	op &= UINT64_C(`31`);
8831	op <<= `16`;
8832	Value \|= op;
8833	// op: Rt32
8834	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8835	op &= UINT64_C(`31`);
8836	op <<= `8`;
8837	Value \|= op;
8838	// op: Rd32
8839	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8840	op &= UINT64_C(`31`);
8841	Value \|= op;
8842	break;
8843	}
8844	case Hexagon::C2_ccombinewf:
8845	case Hexagon::C2_ccombinewnewf:
8846	case Hexagon::C2_ccombinewnewt:
8847	case Hexagon::C2_ccombinewt: {
8848	// op: Pu4
8849	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8850	op &= UINT64_C(`3`);
8851	op <<= `5`;
8852	Value \|= op;
8853	// op: Rs32
8854	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8855	op &= UINT64_C(`31`);
8856	op <<= `16`;
8857	Value \|= op;
8858	// op: Rt32
8859	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8860	op &= UINT64_C(`31`);
8861	op <<= `8`;
8862	Value \|= op;
8863	// op: Rdd32
8864	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8865	op &= UINT64_C(`31`);
8866	Value \|= op;
8867	break;
8868	}
8869	case Hexagon::C2_vmux: {
8870	// op: Pu4
8871	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8872	op &= UINT64_C(`3`);
8873	op <<= `5`;
8874	Value \|= op;
8875	// op: Rss32
8876	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8877	op &= UINT64_C(`31`);
8878	op <<= `16`;
8879	Value \|= op;
8880	// op: Rtt32
8881	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8882	op &= UINT64_C(`31`);
8883	op <<= `8`;
8884	Value \|= op;
8885	// op: Rdd32
8886	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8887	op &= UINT64_C(`31`);
8888	Value \|= op;
8889	break;
8890	}
8891	case Hexagon::A2_psubf:
8892	case Hexagon::A2_psubfnew:
8893	case Hexagon::A2_psubt:
8894	case Hexagon::A2_psubtnew: {
8895	// op: Pu4
8896	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8897	op &= UINT64_C(`3`);
8898	op <<= `5`;
8899	Value \|= op;
8900	// op: Rt32
8901	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8902	op &= UINT64_C(`31`);
8903	op <<= `8`;
8904	Value \|= op;
8905	// op: Rs32
8906	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8907	op &= UINT64_C(`31`);
8908	op <<= `16`;
8909	Value \|= op;
8910	// op: Rd32
8911	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8912	op &= UINT64_C(`31`);
8913	Value \|= op;
8914	break;
8915	}
8916	case Hexagon::A4_paslhf:
8917	case Hexagon::A4_paslhfnew:
8918	case Hexagon::A4_paslht:
8919	case Hexagon::A4_paslhtnew:
8920	case Hexagon::A4_pasrhf:
8921	case Hexagon::A4_pasrhfnew:
8922	case Hexagon::A4_pasrht:
8923	case Hexagon::A4_pasrhtnew:
8924	case Hexagon::A4_psxtbf:
8925	case Hexagon::A4_psxtbfnew:
8926	case Hexagon::A4_psxtbt:
8927	case Hexagon::A4_psxtbtnew:
8928	case Hexagon::A4_psxthf:
8929	case Hexagon::A4_psxthfnew:
8930	case Hexagon::A4_psxtht:
8931	case Hexagon::A4_psxthtnew:
8932	case Hexagon::A4_pzxtbf:
8933	case Hexagon::A4_pzxtbfnew:
8934	case Hexagon::A4_pzxtbt:
8935	case Hexagon::A4_pzxtbtnew:
8936	case Hexagon::A4_pzxthf:
8937	case Hexagon::A4_pzxthfnew:
8938	case Hexagon::A4_pzxtht:
8939	case Hexagon::A4_pzxthtnew: {
8940	// op: Pu4
8941	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8942	op &= UINT64_C(`3`);
8943	op <<= `8`;
8944	Value \|= op;
8945	// op: Rs32
8946	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
8947	op &= UINT64_C(`31`);
8948	op <<= `16`;
8949	Value \|= op;
8950	// op: Rd32
8951	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8952	op &= UINT64_C(`31`);
8953	Value \|= op;
8954	break;
8955	}
8956	case Hexagon::V6_vS32b_new_npred_ppu:
8957	case Hexagon::V6_vS32b_new_pred_ppu:
8958	case Hexagon::V6_vS32b_nt_new_npred_ppu:
8959	case Hexagon::V6_vS32b_nt_new_pred_ppu: {
8960	// op: Pv4
8961	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8962	op &= UINT64_C(`3`);
8963	op <<= `11`;
8964	Value \|= op;
8965	// op: Mu2
8966	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8967	op &= UINT64_C(`1`);
8968	op <<= `13`;
8969	Value \|= op;
8970	// op: Os8
8971	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
8972	op &= UINT64_C(`7`);
8973	Value \|= op;
8974	// op: Rx32
8975	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8976	op &= UINT64_C(`31`);
8977	op <<= `16`;
8978	Value \|= op;
8979	break;
8980	}
8981	case Hexagon::V6_zLd_pred_ppu: {
8982	// op: Pv4
8983	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
8984	op &= UINT64_C(`3`);
8985	op <<= `11`;
8986	Value \|= op;
8987	// op: Mu2
8988	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
8989	op &= UINT64_C(`1`);
8990	op <<= `13`;
8991	Value \|= op;
8992	// op: Rx32
8993	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
8994	op &= UINT64_C(`31`);
8995	op <<= `16`;
8996	Value \|= op;
8997	break;
8998	}
8999	case Hexagon::V6_vS32Ub_npred_ppu:
9000	case Hexagon::V6_vS32Ub_pred_ppu:
9001	case Hexagon::V6_vS32b_npred_ppu:
9002	case Hexagon::V6_vS32b_nt_npred_ppu:
9003	case Hexagon::V6_vS32b_nt_pred_ppu:
9004	case Hexagon::V6_vS32b_pred_ppu: {
9005	// op: Pv4
9006	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9007	op &= UINT64_C(`3`);
9008	op <<= `11`;
9009	Value \|= op;
9010	// op: Mu2
9011	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9012	op &= UINT64_C(`1`);
9013	op <<= `13`;
9014	Value \|= op;
9015	// op: Vs32
9016	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
9017	op &= UINT64_C(`31`);
9018	Value \|= op;
9019	// op: Rx32
9020	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9021	op &= UINT64_C(`31`);
9022	op <<= `16`;
9023	Value \|= op;
9024	break;
9025	}
9026	case Hexagon::L4_return_f:
9027	case Hexagon::L4_return_fnew_pnt:
9028	case Hexagon::L4_return_fnew_pt:
9029	case Hexagon::L4_return_t:
9030	case Hexagon::L4_return_tnew_pnt:
9031	case Hexagon::L4_return_tnew_pt: {
9032	// op: Pv4
9033	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9034	op &= UINT64_C(`3`);
9035	op <<= `8`;
9036	Value \|= op;
9037	// op: Rs32
9038	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9039	op &= UINT64_C(`31`);
9040	op <<= `16`;
9041	Value \|= op;
9042	// op: Rdd32
9043	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9044	op &= UINT64_C(`31`);
9045	Value \|= op;
9046	break;
9047	}
9048	case Hexagon::V6_vL32b_cur_npred_ppu:
9049	case Hexagon::V6_vL32b_cur_pred_ppu:
9050	case Hexagon::V6_vL32b_npred_ppu:
9051	case Hexagon::V6_vL32b_nt_cur_npred_ppu:
9052	case Hexagon::V6_vL32b_nt_cur_pred_ppu:
9053	case Hexagon::V6_vL32b_nt_npred_ppu:
9054	case Hexagon::V6_vL32b_nt_pred_ppu:
9055	case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
9056	case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
9057	case Hexagon::V6_vL32b_pred_ppu:
9058	case Hexagon::V6_vL32b_tmp_npred_ppu:
9059	case Hexagon::V6_vL32b_tmp_pred_ppu: {
9060	// op: Pv4
9061	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9062	op &= UINT64_C(`3`);
9063	op <<= `11`;
9064	Value \|= op;
9065	// op: Mu2
9066	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
9067	op &= UINT64_C(`1`);
9068	op <<= `13`;
9069	Value \|= op;
9070	// op: Vd32
9071	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9072	op &= UINT64_C(`31`);
9073	Value \|= op;
9074	// op: Rx32
9075	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9076	op &= UINT64_C(`31`);
9077	op <<= `16`;
9078	Value \|= op;
9079	break;
9080	}
9081	case Hexagon::V6_vgathermhq:
9082	case Hexagon::V6_vgathermwq: {
9083	// op: Qs4
9084	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9085	op &= UINT64_C(`3`);
9086	op <<= `5`;
9087	Value \|= op;
9088	// op: Rt32
9089	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9090	op &= UINT64_C(`31`);
9091	op <<= `16`;
9092	Value \|= op;
9093	// op: Mu2
9094	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9095	op &= UINT64_C(`1`);
9096	op <<= `13`;
9097	Value \|= op;
9098	// op: Vv32
9099	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9100	op &= UINT64_C(`31`);
9101	Value \|= op;
9102	break;
9103	}
9104	case Hexagon::V6_vscattermhq:
9105	case Hexagon::V6_vscattermwq: {
9106	// op: Qs4
9107	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9108	op &= UINT64_C(`3`);
9109	op <<= `5`;
9110	Value \|= op;
9111	// op: Rt32
9112	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9113	op &= UINT64_C(`31`);
9114	op <<= `16`;
9115	Value \|= op;
9116	// op: Mu2
9117	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9118	op &= UINT64_C(`1`);
9119	op <<= `13`;
9120	Value \|= op;
9121	// op: Vv32
9122	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9123	op &= UINT64_C(`31`);
9124	op <<= `8`;
9125	Value \|= op;
9126	// op: Vw32
9127	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
9128	op &= UINT64_C(`31`);
9129	Value \|= op;
9130	break;
9131	}
9132	case Hexagon::V6_vgathermhwq: {
9133	// op: Qs4
9134	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9135	op &= UINT64_C(`3`);
9136	op <<= `5`;
9137	Value \|= op;
9138	// op: Rt32
9139	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9140	op &= UINT64_C(`31`);
9141	op <<= `16`;
9142	Value \|= op;
9143	// op: Mu2
9144	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9145	op &= UINT64_C(`1`);
9146	op <<= `13`;
9147	Value \|= op;
9148	// op: Vvv32
9149	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9150	op &= UINT64_C(`31`);
9151	Value \|= op;
9152	break;
9153	}
9154	case Hexagon::V6_vscattermhwq: {
9155	// op: Qs4
9156	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9157	op &= UINT64_C(`3`);
9158	op <<= `5`;
9159	Value \|= op;
9160	// op: Rt32
9161	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9162	op &= UINT64_C(`31`);
9163	op <<= `16`;
9164	Value \|= op;
9165	// op: Mu2
9166	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9167	op &= UINT64_C(`1`);
9168	op <<= `13`;
9169	Value \|= op;
9170	// op: Vvv32
9171	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9172	op &= UINT64_C(`31`);
9173	op <<= `8`;
9174	Value \|= op;
9175	// op: Vw32
9176	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
9177	op &= UINT64_C(`31`);
9178	Value \|= op;
9179	break;
9180	}
9181	case Hexagon::V6_pred_not: {
9182	// op: Qs4
9183	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9184	op &= UINT64_C(`3`);
9185	op <<= `8`;
9186	Value \|= op;
9187	// op: Qd4
9188	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9189	op &= UINT64_C(`3`);
9190	Value \|= op;
9191	break;
9192	}
9193	case Hexagon::V6_pred_and:
9194	case Hexagon::V6_pred_and_n:
9195	case Hexagon::V6_pred_or:
9196	case Hexagon::V6_pred_or_n:
9197	case Hexagon::V6_pred_xor:
9198	case Hexagon::V6_shuffeqh:
9199	case Hexagon::V6_shuffeqw: {
9200	// op: Qs4
9201	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9202	op &= UINT64_C(`3`);
9203	op <<= `8`;
9204	Value \|= op;
9205	// op: Qt4
9206	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9207	op &= UINT64_C(`3`);
9208	op <<= `22`;
9209	Value \|= op;
9210	// op: Qd4
9211	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9212	op &= UINT64_C(`3`);
9213	Value \|= op;
9214	break;
9215	}
9216	case Hexagon::V6_vmux: {
9217	// op: Qt4
9218	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9219	op &= UINT64_C(`3`);
9220	op <<= `5`;
9221	Value \|= op;
9222	// op: Vu32
9223	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9224	op &= UINT64_C(`31`);
9225	op <<= `8`;
9226	Value \|= op;
9227	// op: Vv32
9228	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9229	op &= UINT64_C(`31`);
9230	op <<= `16`;
9231	Value \|= op;
9232	// op: Vd32
9233	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9234	op &= UINT64_C(`31`);
9235	Value \|= op;
9236	break;
9237	}
9238	case Hexagon::V6_vswap: {
9239	// op: Qt4
9240	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9241	op &= UINT64_C(`3`);
9242	op <<= `5`;
9243	Value \|= op;
9244	// op: Vu32
9245	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9246	op &= UINT64_C(`31`);
9247	op <<= `8`;
9248	Value \|= op;
9249	// op: Vv32
9250	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9251	op &= UINT64_C(`31`);
9252	op <<= `16`;
9253	Value \|= op;
9254	// op: Vdd32
9255	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9256	op &= UINT64_C(`31`);
9257	Value \|= op;
9258	break;
9259	}
9260	case Hexagon::V6_vandnqrt:
9261	case Hexagon::V6_vandqrt: {
9262	// op: Qu4
9263	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9264	op &= UINT64_C(`3`);
9265	op <<= `8`;
9266	Value \|= op;
9267	// op: Rt32
9268	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9269	op &= UINT64_C(`31`);
9270	op <<= `16`;
9271	Value \|= op;
9272	// op: Vd32
9273	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9274	op &= UINT64_C(`31`);
9275	Value \|= op;
9276	break;
9277	}
9278	case Hexagon::V6_vandnqrt_acc:
9279	case Hexagon::V6_vandqrt_acc: {
9280	// op: Qu4
9281	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9282	op &= UINT64_C(`3`);
9283	op <<= `8`;
9284	Value \|= op;
9285	// op: Rt32
9286	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9287	op &= UINT64_C(`31`);
9288	op <<= `16`;
9289	Value \|= op;
9290	// op: Vx32
9291	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9292	op &= UINT64_C(`31`);
9293	Value \|= op;
9294	break;
9295	}
9296	case Hexagon::V6_vhistq:
9297	case Hexagon::V6_vwhist128q:
9298	case Hexagon::V6_vwhist256q:
9299	case Hexagon::V6_vwhist256q_sat: {
9300	// op: Qv4
9301	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9302	op &= UINT64_C(`3`);
9303	op <<= `22`;
9304	Value \|= op;
9305	break;
9306	}
9307	case Hexagon::V6_vS32b_nqpred_ppu:
9308	case Hexagon::V6_vS32b_nt_nqpred_ppu:
9309	case Hexagon::V6_vS32b_nt_qpred_ppu:
9310	case Hexagon::V6_vS32b_qpred_ppu: {
9311	// op: Qv4
9312	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9313	op &= UINT64_C(`3`);
9314	op <<= `11`;
9315	Value \|= op;
9316	// op: Mu2
9317	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9318	op &= UINT64_C(`1`);
9319	op <<= `13`;
9320	Value \|= op;
9321	// op: Vs32
9322	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
9323	op &= UINT64_C(`31`);
9324	Value \|= op;
9325	// op: Rx32
9326	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9327	op &= UINT64_C(`31`);
9328	op <<= `16`;
9329	Value \|= op;
9330	break;
9331	}
9332	case Hexagon::V6_vprefixqb:
9333	case Hexagon::V6_vprefixqh:
9334	case Hexagon::V6_vprefixqw: {
9335	// op: Qv4
9336	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9337	op &= UINT64_C(`3`);
9338	op <<= `22`;
9339	Value \|= op;
9340	// op: Vd32
9341	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9342	op &= UINT64_C(`31`);
9343	Value \|= op;
9344	break;
9345	}
9346	case Hexagon::V6_vandvnqv:
9347	case Hexagon::V6_vandvqv: {
9348	// op: Qv4
9349	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9350	op &= UINT64_C(`3`);
9351	op <<= `22`;
9352	Value \|= op;
9353	// op: Vu32
9354	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9355	op &= UINT64_C(`31`);
9356	op <<= `8`;
9357	Value \|= op;
9358	// op: Vd32
9359	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9360	op &= UINT64_C(`31`);
9361	Value \|= op;
9362	break;
9363	}
9364	case Hexagon::V6_vaddbnq:
9365	case Hexagon::V6_vaddbq:
9366	case Hexagon::V6_vaddhnq:
9367	case Hexagon::V6_vaddhq:
9368	case Hexagon::V6_vaddwnq:
9369	case Hexagon::V6_vaddwq:
9370	case Hexagon::V6_vsubbnq:
9371	case Hexagon::V6_vsubbq:
9372	case Hexagon::V6_vsubhnq:
9373	case Hexagon::V6_vsubhq:
9374	case Hexagon::V6_vsubwnq:
9375	case Hexagon::V6_vsubwq: {
9376	// op: Qv4
9377	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9378	op &= UINT64_C(`3`);
9379	op <<= `22`;
9380	Value \|= op;
9381	// op: Vu32
9382	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9383	op &= UINT64_C(`31`);
9384	op <<= `8`;
9385	Value \|= op;
9386	// op: Vx32
9387	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9388	op &= UINT64_C(`31`);
9389	Value \|= op;
9390	break;
9391	}
9392	case Hexagon::SA1_clrf:
9393	case Hexagon::SA1_clrfnew:
9394	case Hexagon::SA1_clrt:
9395	case Hexagon::SA1_clrtnew:
9396	case Hexagon::SA1_setin1: {
9397	// op: Rd16
9398	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9399	op &= UINT64_C(`15`);
9400	Value \|= op;
9401	break;
9402	}
9403	case Hexagon::Y6_dmpause:
9404	case Hexagon::Y6_dmpoll:
9405	case Hexagon::Y6_dmwait: {
9406	// op: Rd32
9407	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9408	op &= UINT64_C(`31`);
9409	Value \|= op;
9410	break;
9411	}
9412	case Hexagon::PS_callr_nr: {
9413	// op: Rs
9414	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9415	op &= UINT64_C(`31`);
9416	op <<= `16`;
9417	Value \|= op;
9418	break;
9419	}
9420	case Hexagon::SA1_and1:
9421	case Hexagon::SA1_dec:
9422	case Hexagon::SA1_inc:
9423	case Hexagon::SA1_sxtb:
9424	case Hexagon::SA1_sxth:
9425	case Hexagon::SA1_tfr:
9426	case Hexagon::SA1_zxtb:
9427	case Hexagon::SA1_zxth: {
9428	// op: Rs16
9429	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9430	op &= UINT64_C(`15`);
9431	op <<= `4`;
9432	Value \|= op;
9433	// op: Rd16
9434	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9435	op &= UINT64_C(`15`);
9436	Value \|= op;
9437	break;
9438	}
9439	case Hexagon::SA1_combinerz:
9440	case Hexagon::SA1_combinezr: {
9441	// op: Rs16
9442	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9443	op &= UINT64_C(`15`);
9444	op <<= `4`;
9445	Value \|= op;
9446	// op: Rdd8
9447	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9448	op &= UINT64_C(`7`);
9449	Value \|= op;
9450	break;
9451	}
9452	case Hexagon::SA1_addrx: {
9453	// op: Rs16
9454	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9455	op &= UINT64_C(`15`);
9456	op <<= `4`;
9457	Value \|= op;
9458	// op: Rx16
9459	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9460	op &= UINT64_C(`15`);
9461	Value \|= op;
9462	break;
9463	}
9464	case Hexagon::J2_callr:
9465	case Hexagon::J2_callrh:
9466	case Hexagon::J2_jumpr:
9467	case Hexagon::J2_jumprh:
9468	case Hexagon::J4_hintjumpr:
9469	case Hexagon::R6_release_at_vi:
9470	case Hexagon::R6_release_st_vi:
9471	case Hexagon::Y2_ciad:
9472	case Hexagon::Y2_cswi:
9473	case Hexagon::Y2_dccleana:
9474	case Hexagon::Y2_dccleanidx:
9475	case Hexagon::Y2_dccleaninva:
9476	case Hexagon::Y2_dccleaninvidx:
9477	case Hexagon::Y2_dcinva:
9478	case Hexagon::Y2_dcinvidx:
9479	case Hexagon::Y2_dczeroa:
9480	case Hexagon::Y2_iassignw:
9481	case Hexagon::Y2_icinva:
9482	case Hexagon::Y2_icinvidx:
9483	case Hexagon::Y2_l2cleaninvidx:
9484	case Hexagon::Y2_resume:
9485	case Hexagon::Y2_start:
9486	case Hexagon::Y2_stop:
9487	case Hexagon::Y2_swi:
9488	case Hexagon::Y2_wait:
9489	case Hexagon::Y4_nmi:
9490	case Hexagon::Y4_siad:
9491	case Hexagon::Y4_trace:
9492	case Hexagon::Y5_l2cleanidx:
9493	case Hexagon::Y5_l2invidx:
9494	case Hexagon::Y5_l2unlocka:
9495	case Hexagon::Y5_tlbasidi:
9496	case Hexagon::Y6_diag:
9497	case Hexagon::Y6_dmresume:
9498	case Hexagon::Y6_dmstart: {
9499	// op: Rs32
9500	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9501	op &= UINT64_C(`31`);
9502	op <<= `16`;
9503	Value \|= op;
9504	break;
9505	}
9506	case Hexagon::S2_storew_rl_at_vi:
9507	case Hexagon::S2_storew_rl_st_vi:
9508	case Hexagon::Y2_dctagw:
9509	case Hexagon::Y2_icdataw:
9510	case Hexagon::Y2_ictagw:
9511	case Hexagon::Y4_l2fetch:
9512	case Hexagon::Y4_l2tagw:
9513	case Hexagon::Y6_dmlink: {
9514	// op: Rs32
9515	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9516	op &= UINT64_C(`31`);
9517	op <<= `16`;
9518	Value \|= op;
9519	// op: Rt32
9520	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9521	op &= UINT64_C(`31`);
9522	op <<= `8`;
9523	Value \|= op;
9524	break;
9525	}
9526	case Hexagon::L6_memcpy: {
9527	// op: Rs32
9528	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9529	op &= UINT64_C(`31`);
9530	op <<= `16`;
9531	Value \|= op;
9532	// op: Rt32
9533	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9534	op &= UINT64_C(`31`);
9535	op <<= `8`;
9536	Value \|= op;
9537	// op: Mu2
9538	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9539	op &= UINT64_C(`1`);
9540	op <<= `13`;
9541	Value \|= op;
9542	break;
9543	}
9544	case Hexagon::S4_stored_rl_at_vi:
9545	case Hexagon::S4_stored_rl_st_vi:
9546	case Hexagon::Y5_l2fetch: {
9547	// op: Rs32
9548	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9549	op &= UINT64_C(`31`);
9550	op <<= `16`;
9551	Value \|= op;
9552	// op: Rtt32
9553	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9554	op &= UINT64_C(`31`);
9555	op <<= `8`;
9556	Value \|= op;
9557	break;
9558	}
9559	case Hexagon::A2_tfrrcr: {
9560	// op: Rs32
9561	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9562	op &= UINT64_C(`31`);
9563	op <<= `16`;
9564	Value \|= op;
9565	// op: Cd32
9566	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9567	op &= UINT64_C(`31`);
9568	Value \|= op;
9569	break;
9570	}
9571	case Hexagon::G4_tfrgrcr: {
9572	// op: Rs32
9573	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9574	op &= UINT64_C(`31`);
9575	op <<= `16`;
9576	Value \|= op;
9577	// op: Gd32
9578	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9579	op &= UINT64_C(`31`);
9580	Value \|= op;
9581	break;
9582	}
9583	case Hexagon::C2_tfrrp:
9584	case Hexagon::Y5_l2locka: {
9585	// op: Rs32
9586	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9587	op &= UINT64_C(`31`);
9588	op <<= `16`;
9589	Value \|= op;
9590	// op: Pd4
9591	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9592	op &= UINT64_C(`3`);
9593	Value \|= op;
9594	break;
9595	}
9596	case Hexagon::A2_abs:
9597	case Hexagon::A2_abssat:
9598	case Hexagon::A2_aslh:
9599	case Hexagon::A2_asrh:
9600	case Hexagon::A2_negsat:
9601	case Hexagon::A2_satb:
9602	case Hexagon::A2_sath:
9603	case Hexagon::A2_satub:
9604	case Hexagon::A2_satuh:
9605	case Hexagon::A2_swiz:
9606	case Hexagon::A2_sxtb:
9607	case Hexagon::A2_sxth:
9608	case Hexagon::A2_tfr:
9609	case Hexagon::A2_zxth:
9610	case Hexagon::F2_conv_sf2uw:
9611	case Hexagon::F2_conv_sf2uw_chop:
9612	case Hexagon::F2_conv_sf2w:
9613	case Hexagon::F2_conv_sf2w_chop:
9614	case Hexagon::F2_conv_uw2sf:
9615	case Hexagon::F2_conv_w2sf:
9616	case Hexagon::F2_sffixupr:
9617	case Hexagon::L2_loadw_aq:
9618	case Hexagon::L2_loadw_locked:
9619	case Hexagon::S2_brev:
9620	case Hexagon::S2_cl0:
9621	case Hexagon::S2_cl1:
9622	case Hexagon::S2_clb:
9623	case Hexagon::S2_clbnorm:
9624	case Hexagon::S2_ct0:
9625	case Hexagon::S2_ct1:
9626	case Hexagon::S2_svsathb:
9627	case Hexagon::S2_svsathub:
9628	case Hexagon::S2_vsplatrb:
9629	case Hexagon::Y2_dctagr:
9630	case Hexagon::Y2_getimask:
9631	case Hexagon::Y2_iassignr:
9632	case Hexagon::Y2_icdatar:
9633	case Hexagon::Y2_ictagr:
9634	case Hexagon::Y2_tlbp:
9635	case Hexagon::Y4_l2tagr: {
9636	// op: Rs32
9637	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9638	op &= UINT64_C(`31`);
9639	op <<= `16`;
9640	Value \|= op;
9641	// op: Rd32
9642	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9643	op &= UINT64_C(`31`);
9644	Value \|= op;
9645	break;
9646	}
9647	case Hexagon::A2_sxtw:
9648	case Hexagon::F2_conv_sf2d:
9649	case Hexagon::F2_conv_sf2d_chop:
9650	case Hexagon::F2_conv_sf2df:
9651	case Hexagon::F2_conv_sf2ud:
9652	case Hexagon::F2_conv_sf2ud_chop:
9653	case Hexagon::F2_conv_uw2df:
9654	case Hexagon::F2_conv_w2df:
9655	case Hexagon::L2_deallocframe:
9656	case Hexagon::L4_loadd_aq:
9657	case Hexagon::L4_loadd_locked:
9658	case Hexagon::L4_return:
9659	case Hexagon::S2_vsplatrh:
9660	case Hexagon::S2_vsxtbh:
9661	case Hexagon::S2_vsxthw:
9662	case Hexagon::S2_vzxtbh:
9663	case Hexagon::S2_vzxthw:
9664	case Hexagon::S6_vsplatrbp:
9665	case Hexagon::Y2_tlbr: {
9666	// op: Rs32
9667	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9668	op &= UINT64_C(`31`);
9669	op <<= `16`;
9670	Value \|= op;
9671	// op: Rdd32
9672	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9673	op &= UINT64_C(`31`);
9674	Value \|= op;
9675	break;
9676	}
9677	case Hexagon::A4_cmpbeq:
9678	case Hexagon::A4_cmpbgt:
9679	case Hexagon::A4_cmpbgtu:
9680	case Hexagon::A4_cmpheq:
9681	case Hexagon::A4_cmphgt:
9682	case Hexagon::A4_cmphgtu:
9683	case Hexagon::C2_bitsclr:
9684	case Hexagon::C2_bitsset:
9685	case Hexagon::C2_cmpeq:
9686	case Hexagon::C2_cmpgt:
9687	case Hexagon::C2_cmpgtu:
9688	case Hexagon::C4_cmplte:
9689	case Hexagon::C4_cmplteu:
9690	case Hexagon::C4_cmpneq:
9691	case Hexagon::C4_nbitsclr:
9692	case Hexagon::C4_nbitsset:
9693	case Hexagon::F2_sfcmpeq:
9694	case Hexagon::F2_sfcmpge:
9695	case Hexagon::F2_sfcmpgt:
9696	case Hexagon::F2_sfcmpuo:
9697	case Hexagon::S2_storew_locked:
9698	case Hexagon::S2_tstbit_r:
9699	case Hexagon::S4_ntstbit_r: {
9700	// op: Rs32
9701	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9702	op &= UINT64_C(`31`);
9703	op <<= `16`;
9704	Value \|= op;
9705	// op: Rt32
9706	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9707	op &= UINT64_C(`31`);
9708	op <<= `8`;
9709	Value \|= op;
9710	// op: Pd4
9711	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9712	op &= UINT64_C(`3`);
9713	Value \|= op;
9714	break;
9715	}
9716	case Hexagon::A2_add:
9717	case Hexagon::A2_addsat:
9718	case Hexagon::A2_and:
9719	case Hexagon::A2_max:
9720	case Hexagon::A2_maxu:
9721	case Hexagon::A2_or:
9722	case Hexagon::A2_svaddh:
9723	case Hexagon::A2_svaddhs:
9724	case Hexagon::A2_svadduhs:
9725	case Hexagon::A2_svavgh:
9726	case Hexagon::A2_svavghs:
9727	case Hexagon::A2_xor:
9728	case Hexagon::A4_cround_rr:
9729	case Hexagon::A4_modwrapu:
9730	case Hexagon::A4_rcmpeq:
9731	case Hexagon::A4_rcmpneq:
9732	case Hexagon::A4_round_rr:
9733	case Hexagon::A4_round_rr_sat:
9734	case Hexagon::F2_sfadd:
9735	case Hexagon::F2_sffixupd:
9736	case Hexagon::F2_sffixupn:
9737	case Hexagon::F2_sfmax:
9738	case Hexagon::F2_sfmin:
9739	case Hexagon::F2_sfmpy:
9740	case Hexagon::F2_sfsub:
9741	case Hexagon::L4_loadw_phys:
9742	case Hexagon::M2_cmpyrs_s0:
9743	case Hexagon::M2_cmpyrs_s1:
9744	case Hexagon::M2_cmpyrsc_s0:
9745	case Hexagon::M2_cmpyrsc_s1:
9746	case Hexagon::M2_dpmpyss_rnd_s0:
9747	case Hexagon::M2_hmmpyh_rs1:
9748	case Hexagon::M2_hmmpyh_s1:
9749	case Hexagon::M2_hmmpyl_rs1:
9750	case Hexagon::M2_hmmpyl_s1:
9751	case Hexagon::M2_mpy_hh_s0:
9752	case Hexagon::M2_mpy_hh_s1:
9753	case Hexagon::M2_mpy_hl_s0:
9754	case Hexagon::M2_mpy_hl_s1:
9755	case Hexagon::M2_mpy_lh_s0:
9756	case Hexagon::M2_mpy_lh_s1:
9757	case Hexagon::M2_mpy_ll_s0:
9758	case Hexagon::M2_mpy_ll_s1:
9759	case Hexagon::M2_mpy_rnd_hh_s0:
9760	case Hexagon::M2_mpy_rnd_hh_s1:
9761	case Hexagon::M2_mpy_rnd_hl_s0:
9762	case Hexagon::M2_mpy_rnd_hl_s1:
9763	case Hexagon::M2_mpy_rnd_lh_s0:
9764	case Hexagon::M2_mpy_rnd_lh_s1:
9765	case Hexagon::M2_mpy_rnd_ll_s0:
9766	case Hexagon::M2_mpy_rnd_ll_s1:
9767	case Hexagon::M2_mpy_sat_hh_s0:
9768	case Hexagon::M2_mpy_sat_hh_s1:
9769	case Hexagon::M2_mpy_sat_hl_s0:
9770	case Hexagon::M2_mpy_sat_hl_s1:
9771	case Hexagon::M2_mpy_sat_lh_s0:
9772	case Hexagon::M2_mpy_sat_lh_s1:
9773	case Hexagon::M2_mpy_sat_ll_s0:
9774	case Hexagon::M2_mpy_sat_ll_s1:
9775	case Hexagon::M2_mpy_sat_rnd_hh_s0:
9776	case Hexagon::M2_mpy_sat_rnd_hh_s1:
9777	case Hexagon::M2_mpy_sat_rnd_hl_s0:
9778	case Hexagon::M2_mpy_sat_rnd_hl_s1:
9779	case Hexagon::M2_mpy_sat_rnd_lh_s0:
9780	case Hexagon::M2_mpy_sat_rnd_lh_s1:
9781	case Hexagon::M2_mpy_sat_rnd_ll_s0:
9782	case Hexagon::M2_mpy_sat_rnd_ll_s1:
9783	case Hexagon::M2_mpy_up:
9784	case Hexagon::M2_mpy_up_s1:
9785	case Hexagon::M2_mpy_up_s1_sat:
9786	case Hexagon::M2_mpyi:
9787	case Hexagon::M2_mpysu_up:
9788	case Hexagon::M2_mpyu_hh_s0:
9789	case Hexagon::M2_mpyu_hh_s1:
9790	case Hexagon::M2_mpyu_hl_s0:
9791	case Hexagon::M2_mpyu_hl_s1:
9792	case Hexagon::M2_mpyu_lh_s0:
9793	case Hexagon::M2_mpyu_lh_s1:
9794	case Hexagon::M2_mpyu_ll_s0:
9795	case Hexagon::M2_mpyu_ll_s1:
9796	case Hexagon::M2_mpyu_up:
9797	case Hexagon::M2_vmpy2s_s0pack:
9798	case Hexagon::M2_vmpy2s_s1pack:
9799	case Hexagon::S2_asl_r_r:
9800	case Hexagon::S2_asl_r_r_sat:
9801	case Hexagon::S2_asr_r_r:
9802	case Hexagon::S2_asr_r_r_sat:
9803	case Hexagon::S2_clrbit_r:
9804	case Hexagon::S2_lsl_r_r:
9805	case Hexagon::S2_lsr_r_r:
9806	case Hexagon::S2_setbit_r:
9807	case Hexagon::S2_togglebit_r:
9808	case Hexagon::S4_parity:
9809	case Hexagon::dep_A2_addsat: {
9810	// op: Rs32
9811	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9812	op &= UINT64_C(`31`);
9813	op <<= `16`;
9814	Value \|= op;
9815	// op: Rt32
9816	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9817	op &= UINT64_C(`31`);
9818	op <<= `8`;
9819	Value \|= op;
9820	// op: Rd32
9821	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9822	op &= UINT64_C(`31`);
9823	Value \|= op;
9824	break;
9825	}
9826	case Hexagon::A2_combinew:
9827	case Hexagon::A4_bitsplit:
9828	case Hexagon::M2_cmpyi_s0:
9829	case Hexagon::M2_cmpyr_s0:
9830	case Hexagon::M2_cmpys_s0:
9831	case Hexagon::M2_cmpys_s1:
9832	case Hexagon::M2_cmpysc_s0:
9833	case Hexagon::M2_cmpysc_s1:
9834	case Hexagon::M2_dpmpyss_s0:
9835	case Hexagon::M2_dpmpyuu_s0:
9836	case Hexagon::M2_mpyd_hh_s0:
9837	case Hexagon::M2_mpyd_hh_s1:
9838	case Hexagon::M2_mpyd_hl_s0:
9839	case Hexagon::M2_mpyd_hl_s1:
9840	case Hexagon::M2_mpyd_lh_s0:
9841	case Hexagon::M2_mpyd_lh_s1:
9842	case Hexagon::M2_mpyd_ll_s0:
9843	case Hexagon::M2_mpyd_ll_s1:
9844	case Hexagon::M2_mpyd_rnd_hh_s0:
9845	case Hexagon::M2_mpyd_rnd_hh_s1:
9846	case Hexagon::M2_mpyd_rnd_hl_s0:
9847	case Hexagon::M2_mpyd_rnd_hl_s1:
9848	case Hexagon::M2_mpyd_rnd_lh_s0:
9849	case Hexagon::M2_mpyd_rnd_lh_s1:
9850	case Hexagon::M2_mpyd_rnd_ll_s0:
9851	case Hexagon::M2_mpyd_rnd_ll_s1:
9852	case Hexagon::M2_mpyud_hh_s0:
9853	case Hexagon::M2_mpyud_hh_s1:
9854	case Hexagon::M2_mpyud_hl_s0:
9855	case Hexagon::M2_mpyud_hl_s1:
9856	case Hexagon::M2_mpyud_lh_s0:
9857	case Hexagon::M2_mpyud_lh_s1:
9858	case Hexagon::M2_mpyud_ll_s0:
9859	case Hexagon::M2_mpyud_ll_s1:
9860	case Hexagon::M2_vmpy2s_s0:
9861	case Hexagon::M2_vmpy2s_s1:
9862	case Hexagon::M2_vmpy2su_s0:
9863	case Hexagon::M2_vmpy2su_s1:
9864	case Hexagon::M4_pmpyw:
9865	case Hexagon::M4_vpmpyh:
9866	case Hexagon::M5_vmpybsu:
9867	case Hexagon::M5_vmpybuu:
9868	case Hexagon::S2_packhl:
9869	case Hexagon::dep_S2_packhl: {
9870	// op: Rs32
9871	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9872	op &= UINT64_C(`31`);
9873	op <<= `16`;
9874	Value \|= op;
9875	// op: Rt32
9876	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9877	op &= UINT64_C(`31`);
9878	op <<= `8`;
9879	Value \|= op;
9880	// op: Rdd32
9881	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9882	op &= UINT64_C(`31`);
9883	Value \|= op;
9884	break;
9885	}
9886	case Hexagon::S4_stored_locked: {
9887	// op: Rs32
9888	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9889	op &= UINT64_C(`31`);
9890	op <<= `16`;
9891	Value \|= op;
9892	// op: Rtt32
9893	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9894	op &= UINT64_C(`31`);
9895	op <<= `8`;
9896	Value \|= op;
9897	// op: Pd4
9898	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9899	op &= UINT64_C(`3`);
9900	Value \|= op;
9901	break;
9902	}
9903	case Hexagon::S2_extractu_rp:
9904	case Hexagon::S4_extract_rp: {
9905	// op: Rs32
9906	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9907	op &= UINT64_C(`31`);
9908	op <<= `16`;
9909	Value \|= op;
9910	// op: Rtt32
9911	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9912	op &= UINT64_C(`31`);
9913	op <<= `8`;
9914	Value \|= op;
9915	// op: Rd32
9916	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9917	op &= UINT64_C(`31`);
9918	Value \|= op;
9919	break;
9920	}
9921	case Hexagon::Y2_tfrsrcr: {
9922	// op: Rs32
9923	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9924	op &= UINT64_C(`31`);
9925	op <<= `16`;
9926	Value \|= op;
9927	// op: Sd128
9928	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9929	op &= UINT64_C(`127`);
9930	Value \|= op;
9931	break;
9932	}
9933	case Hexagon::F2_sfinvsqrta: {
9934	// op: Rs32
9935	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9936	op &= UINT64_C(`31`);
9937	op <<= `16`;
9938	Value \|= op;
9939	// op: Rd32
9940	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9941	op &= UINT64_C(`31`);
9942	Value \|= op;
9943	// op: Pe4
9944	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9945	op &= UINT64_C(`3`);
9946	op <<= `5`;
9947	Value \|= op;
9948	break;
9949	}
9950	case Hexagon::F2_sffma_sc: {
9951	// op: Rs32
9952	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9953	op &= UINT64_C(`31`);
9954	op <<= `16`;
9955	Value \|= op;
9956	// op: Rt32
9957	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9958	op &= UINT64_C(`31`);
9959	op <<= `8`;
9960	Value \|= op;
9961	// op: Pu4
9962	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
9963	op &= UINT64_C(`3`);
9964	op <<= `5`;
9965	Value \|= op;
9966	// op: Rx32
9967	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9968	op &= UINT64_C(`31`);
9969	Value \|= op;
9970	break;
9971	}
9972	case Hexagon::F2_sfrecipa: {
9973	// op: Rs32
9974	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
9975	op &= UINT64_C(`31`);
9976	op <<= `16`;
9977	Value \|= op;
9978	// op: Rt32
9979	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
9980	op &= UINT64_C(`31`);
9981	op <<= `8`;
9982	Value \|= op;
9983	// op: Rd32
9984	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
9985	op &= UINT64_C(`31`);
9986	Value \|= op;
9987	// op: Pe4
9988	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
9989	op &= UINT64_C(`3`);
9990	op <<= `5`;
9991	Value \|= op;
9992	break;
9993	}
9994	case Hexagon::F2_sffma:
9995	case Hexagon::F2_sffma_lib:
9996	case Hexagon::F2_sffms:
9997	case Hexagon::F2_sffms_lib:
9998	case Hexagon::M2_acci:
9999	case Hexagon::M2_maci:
10000	case Hexagon::M2_mnaci:
10001	case Hexagon::M2_mpy_acc_hh_s0:
10002	case Hexagon::M2_mpy_acc_hh_s1:
10003	case Hexagon::M2_mpy_acc_hl_s0:
10004	case Hexagon::M2_mpy_acc_hl_s1:
10005	case Hexagon::M2_mpy_acc_lh_s0:
10006	case Hexagon::M2_mpy_acc_lh_s1:
10007	case Hexagon::M2_mpy_acc_ll_s0:
10008	case Hexagon::M2_mpy_acc_ll_s1:
10009	case Hexagon::M2_mpy_acc_sat_hh_s0:
10010	case Hexagon::M2_mpy_acc_sat_hh_s1:
10011	case Hexagon::M2_mpy_acc_sat_hl_s0:
10012	case Hexagon::M2_mpy_acc_sat_hl_s1:
10013	case Hexagon::M2_mpy_acc_sat_lh_s0:
10014	case Hexagon::M2_mpy_acc_sat_lh_s1:
10015	case Hexagon::M2_mpy_acc_sat_ll_s0:
10016	case Hexagon::M2_mpy_acc_sat_ll_s1:
10017	case Hexagon::M2_mpy_nac_hh_s0:
10018	case Hexagon::M2_mpy_nac_hh_s1:
10019	case Hexagon::M2_mpy_nac_hl_s0:
10020	case Hexagon::M2_mpy_nac_hl_s1:
10021	case Hexagon::M2_mpy_nac_lh_s0:
10022	case Hexagon::M2_mpy_nac_lh_s1:
10023	case Hexagon::M2_mpy_nac_ll_s0:
10024	case Hexagon::M2_mpy_nac_ll_s1:
10025	case Hexagon::M2_mpy_nac_sat_hh_s0:
10026	case Hexagon::M2_mpy_nac_sat_hh_s1:
10027	case Hexagon::M2_mpy_nac_sat_hl_s0:
10028	case Hexagon::M2_mpy_nac_sat_hl_s1:
10029	case Hexagon::M2_mpy_nac_sat_lh_s0:
10030	case Hexagon::M2_mpy_nac_sat_lh_s1:
10031	case Hexagon::M2_mpy_nac_sat_ll_s0:
10032	case Hexagon::M2_mpy_nac_sat_ll_s1:
10033	case Hexagon::M2_mpyu_acc_hh_s0:
10034	case Hexagon::M2_mpyu_acc_hh_s1:
10035	case Hexagon::M2_mpyu_acc_hl_s0:
10036	case Hexagon::M2_mpyu_acc_hl_s1:
10037	case Hexagon::M2_mpyu_acc_lh_s0:
10038	case Hexagon::M2_mpyu_acc_lh_s1:
10039	case Hexagon::M2_mpyu_acc_ll_s0:
10040	case Hexagon::M2_mpyu_acc_ll_s1:
10041	case Hexagon::M2_mpyu_nac_hh_s0:
10042	case Hexagon::M2_mpyu_nac_hh_s1:
10043	case Hexagon::M2_mpyu_nac_hl_s0:
10044	case Hexagon::M2_mpyu_nac_hl_s1:
10045	case Hexagon::M2_mpyu_nac_lh_s0:
10046	case Hexagon::M2_mpyu_nac_lh_s1:
10047	case Hexagon::M2_mpyu_nac_ll_s0:
10048	case Hexagon::M2_mpyu_nac_ll_s1:
10049	case Hexagon::M2_nacci:
10050	case Hexagon::M2_xor_xacc:
10051	case Hexagon::M4_and_and:
10052	case Hexagon::M4_and_andn:
10053	case Hexagon::M4_and_or:
10054	case Hexagon::M4_and_xor:
10055	case Hexagon::M4_mac_up_s1_sat:
10056	case Hexagon::M4_nac_up_s1_sat:
10057	case Hexagon::M4_or_and:
10058	case Hexagon::M4_or_andn:
10059	case Hexagon::M4_or_or:
10060	case Hexagon::M4_or_xor:
10061	case Hexagon::M4_xor_and:
10062	case Hexagon::M4_xor_andn:
10063	case Hexagon::M4_xor_or:
10064	case Hexagon::S2_asl_r_r_acc:
10065	case Hexagon::S2_asl_r_r_and:
10066	case Hexagon::S2_asl_r_r_nac:
10067	case Hexagon::S2_asl_r_r_or:
10068	case Hexagon::S2_asr_r_r_acc:
10069	case Hexagon::S2_asr_r_r_and:
10070	case Hexagon::S2_asr_r_r_nac:
10071	case Hexagon::S2_asr_r_r_or:
10072	case Hexagon::S2_lsl_r_r_acc:
10073	case Hexagon::S2_lsl_r_r_and:
10074	case Hexagon::S2_lsl_r_r_nac:
10075	case Hexagon::S2_lsl_r_r_or:
10076	case Hexagon::S2_lsr_r_r_acc:
10077	case Hexagon::S2_lsr_r_r_and:
10078	case Hexagon::S2_lsr_r_r_nac:
10079	case Hexagon::S2_lsr_r_r_or: {
10080	// op: Rs32
10081	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10082	op &= UINT64_C(`31`);
10083	op <<= `16`;
10084	Value \|= op;
10085	// op: Rt32
10086	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10087	op &= UINT64_C(`31`);
10088	op <<= `8`;
10089	Value \|= op;
10090	// op: Rx32
10091	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10092	op &= UINT64_C(`31`);
10093	Value \|= op;
10094	break;
10095	}
10096	case Hexagon::M2_cmaci_s0:
10097	case Hexagon::M2_cmacr_s0:
10098	case Hexagon::M2_cmacs_s0:
10099	case Hexagon::M2_cmacs_s1:
10100	case Hexagon::M2_cmacsc_s0:
10101	case Hexagon::M2_cmacsc_s1:
10102	case Hexagon::M2_cnacs_s0:
10103	case Hexagon::M2_cnacs_s1:
10104	case Hexagon::M2_cnacsc_s0:
10105	case Hexagon::M2_cnacsc_s1:
10106	case Hexagon::M2_dpmpyss_acc_s0:
10107	case Hexagon::M2_dpmpyss_nac_s0:
10108	case Hexagon::M2_dpmpyuu_acc_s0:
10109	case Hexagon::M2_dpmpyuu_nac_s0:
10110	case Hexagon::M2_mpyd_acc_hh_s0:
10111	case Hexagon::M2_mpyd_acc_hh_s1:
10112	case Hexagon::M2_mpyd_acc_hl_s0:
10113	case Hexagon::M2_mpyd_acc_hl_s1:
10114	case Hexagon::M2_mpyd_acc_lh_s0:
10115	case Hexagon::M2_mpyd_acc_lh_s1:
10116	case Hexagon::M2_mpyd_acc_ll_s0:
10117	case Hexagon::M2_mpyd_acc_ll_s1:
10118	case Hexagon::M2_mpyd_nac_hh_s0:
10119	case Hexagon::M2_mpyd_nac_hh_s1:
10120	case Hexagon::M2_mpyd_nac_hl_s0:
10121	case Hexagon::M2_mpyd_nac_hl_s1:
10122	case Hexagon::M2_mpyd_nac_lh_s0:
10123	case Hexagon::M2_mpyd_nac_lh_s1:
10124	case Hexagon::M2_mpyd_nac_ll_s0:
10125	case Hexagon::M2_mpyd_nac_ll_s1:
10126	case Hexagon::M2_mpyud_acc_hh_s0:
10127	case Hexagon::M2_mpyud_acc_hh_s1:
10128	case Hexagon::M2_mpyud_acc_hl_s0:
10129	case Hexagon::M2_mpyud_acc_hl_s1:
10130	case Hexagon::M2_mpyud_acc_lh_s0:
10131	case Hexagon::M2_mpyud_acc_lh_s1:
10132	case Hexagon::M2_mpyud_acc_ll_s0:
10133	case Hexagon::M2_mpyud_acc_ll_s1:
10134	case Hexagon::M2_mpyud_nac_hh_s0:
10135	case Hexagon::M2_mpyud_nac_hh_s1:
10136	case Hexagon::M2_mpyud_nac_hl_s0:
10137	case Hexagon::M2_mpyud_nac_hl_s1:
10138	case Hexagon::M2_mpyud_nac_lh_s0:
10139	case Hexagon::M2_mpyud_nac_lh_s1:
10140	case Hexagon::M2_mpyud_nac_ll_s0:
10141	case Hexagon::M2_mpyud_nac_ll_s1:
10142	case Hexagon::M2_vmac2:
10143	case Hexagon::M2_vmac2s_s0:
10144	case Hexagon::M2_vmac2s_s1:
10145	case Hexagon::M2_vmac2su_s0:
10146	case Hexagon::M2_vmac2su_s1:
10147	case Hexagon::M4_pmpyw_acc:
10148	case Hexagon::M4_vpmpyh_acc:
10149	case Hexagon::M5_vmacbsu:
10150	case Hexagon::M5_vmacbuu: {
10151	// op: Rs32
10152	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10153	op &= UINT64_C(`31`);
10154	op <<= `16`;
10155	Value \|= op;
10156	// op: Rt32
10157	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10158	op &= UINT64_C(`31`);
10159	op <<= `8`;
10160	Value \|= op;
10161	// op: Rxx32
10162	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10163	op &= UINT64_C(`31`);
10164	Value \|= op;
10165	break;
10166	}
10167	case Hexagon::S2_insert_rp: {
10168	// op: Rs32
10169	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10170	op &= UINT64_C(`31`);
10171	op <<= `16`;
10172	Value \|= op;
10173	// op: Rtt32
10174	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10175	op &= UINT64_C(`31`);
10176	op <<= `8`;
10177	Value \|= op;
10178	// op: Rx32
10179	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10180	op &= UINT64_C(`31`);
10181	Value \|= op;
10182	break;
10183	}
10184	case Hexagon::Y2_tlbw: {
10185	// op: Rss32
10186	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10187	op &= UINT64_C(`31`);
10188	op <<= `16`;
10189	Value \|= op;
10190	// op: Rt32
10191	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10192	op &= UINT64_C(`31`);
10193	op <<= `8`;
10194	Value \|= op;
10195	break;
10196	}
10197	case Hexagon::Y6_diag0:
10198	case Hexagon::Y6_diag1: {
10199	// op: Rss32
10200	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10201	op &= UINT64_C(`31`);
10202	op <<= `16`;
10203	Value \|= op;
10204	// op: Rtt32
10205	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10206	op &= UINT64_C(`31`);
10207	op <<= `8`;
10208	Value \|= op;
10209	break;
10210	}
10211	case Hexagon::A4_tfrpcp: {
10212	// op: Rss32
10213	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10214	op &= UINT64_C(`31`);
10215	op <<= `16`;
10216	Value \|= op;
10217	// op: Cdd32
10218	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10219	op &= UINT64_C(`31`);
10220	Value \|= op;
10221	break;
10222	}
10223	case Hexagon::G4_tfrgpcp: {
10224	// op: Rss32
10225	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10226	op &= UINT64_C(`31`);
10227	op <<= `16`;
10228	Value \|= op;
10229	// op: Gdd32
10230	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10231	op &= UINT64_C(`31`);
10232	Value \|= op;
10233	break;
10234	}
10235	case Hexagon::A2_roundsat:
10236	case Hexagon::A2_sat:
10237	case Hexagon::F2_conv_d2sf:
10238	case Hexagon::F2_conv_df2sf:
10239	case Hexagon::F2_conv_df2uw:
10240	case Hexagon::F2_conv_df2uw_chop:
10241	case Hexagon::F2_conv_df2w:
10242	case Hexagon::F2_conv_df2w_chop:
10243	case Hexagon::F2_conv_ud2sf:
10244	case Hexagon::S2_cl0p:
10245	case Hexagon::S2_cl1p:
10246	case Hexagon::S2_clbp:
10247	case Hexagon::S2_ct0p:
10248	case Hexagon::S2_ct1p:
10249	case Hexagon::S2_vrndpackwh:
10250	case Hexagon::S2_vrndpackwhs:
10251	case Hexagon::S2_vsathb:
10252	case Hexagon::S2_vsathub:
10253	case Hexagon::S2_vsatwh:
10254	case Hexagon::S2_vsatwuh:
10255	case Hexagon::S2_vtrunehb:
10256	case Hexagon::S2_vtrunohb:
10257	case Hexagon::S4_clbpnorm:
10258	case Hexagon::S5_popcountp:
10259	case Hexagon::Y5_tlboc: {
10260	// op: Rss32
10261	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10262	op &= UINT64_C(`31`);
10263	op <<= `16`;
10264	Value \|= op;
10265	// op: Rd32
10266	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10267	op &= UINT64_C(`31`);
10268	Value \|= op;
10269	break;
10270	}
10271	case Hexagon::A2_absp:
10272	case Hexagon::A2_negp:
10273	case Hexagon::A2_notp:
10274	case Hexagon::A2_vabsh:
10275	case Hexagon::A2_vabshsat:
10276	case Hexagon::A2_vabsw:
10277	case Hexagon::A2_vabswsat:
10278	case Hexagon::A2_vconj:
10279	case Hexagon::F2_conv_d2df:
10280	case Hexagon::F2_conv_df2d:
10281	case Hexagon::F2_conv_df2d_chop:
10282	case Hexagon::F2_conv_df2ud:
10283	case Hexagon::F2_conv_df2ud_chop:
10284	case Hexagon::F2_conv_ud2df:
10285	case Hexagon::S2_brevp:
10286	case Hexagon::S2_deinterleave:
10287	case Hexagon::S2_interleave:
10288	case Hexagon::S2_vsathb_nopack:
10289	case Hexagon::S2_vsathub_nopack:
10290	case Hexagon::S2_vsatwh_nopack:
10291	case Hexagon::S2_vsatwuh_nopack: {
10292	// op: Rss32
10293	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10294	op &= UINT64_C(`31`);
10295	op <<= `16`;
10296	Value \|= op;
10297	// op: Rdd32
10298	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10299	op &= UINT64_C(`31`);
10300	Value \|= op;
10301	break;
10302	}
10303	case Hexagon::A4_tlbmatch: {
10304	// op: Rss32
10305	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10306	op &= UINT64_C(`31`);
10307	op <<= `16`;
10308	Value \|= op;
10309	// op: Rt32
10310	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10311	op &= UINT64_C(`31`);
10312	op <<= `8`;
10313	Value \|= op;
10314	// op: Pd4
10315	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10316	op &= UINT64_C(`3`);
10317	Value \|= op;
10318	break;
10319	}
10320	case Hexagon::M4_cmpyi_wh:
10321	case Hexagon::M4_cmpyi_whc:
10322	case Hexagon::M4_cmpyr_wh:
10323	case Hexagon::M4_cmpyr_whc:
10324	case Hexagon::S2_asr_r_svw_trun:
10325	case Hexagon::Y5_ctlbw: {
10326	// op: Rss32
10327	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10328	op &= UINT64_C(`31`);
10329	op <<= `16`;
10330	Value \|= op;
10331	// op: Rt32
10332	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10333	op &= UINT64_C(`31`);
10334	op <<= `8`;
10335	Value \|= op;
10336	// op: Rd32
10337	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10338	op &= UINT64_C(`31`);
10339	Value \|= op;
10340	break;
10341	}
10342	case Hexagon::A7_croundd_rr:
10343	case Hexagon::S2_asl_r_p:
10344	case Hexagon::S2_asl_r_vh:
10345	case Hexagon::S2_asl_r_vw:
10346	case Hexagon::S2_asr_r_p:
10347	case Hexagon::S2_asr_r_vh:
10348	case Hexagon::S2_asr_r_vw:
10349	case Hexagon::S2_lsl_r_p:
10350	case Hexagon::S2_lsl_r_vh:
10351	case Hexagon::S2_lsl_r_vw:
10352	case Hexagon::S2_lsr_r_p:
10353	case Hexagon::S2_lsr_r_vh:
10354	case Hexagon::S2_lsr_r_vw:
10355	case Hexagon::S2_vcnegh:
10356	case Hexagon::S2_vcrotate: {
10357	// op: Rss32
10358	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10359	op &= UINT64_C(`31`);
10360	op <<= `16`;
10361	Value \|= op;
10362	// op: Rt32
10363	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10364	op &= UINT64_C(`31`);
10365	op <<= `8`;
10366	Value \|= op;
10367	// op: Rdd32
10368	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10369	op &= UINT64_C(`31`);
10370	Value \|= op;
10371	break;
10372	}
10373	case Hexagon::A2_vcmpbeq:
10374	case Hexagon::A2_vcmpbgtu:
10375	case Hexagon::A2_vcmpheq:
10376	case Hexagon::A2_vcmphgt:
10377	case Hexagon::A2_vcmphgtu:
10378	case Hexagon::A2_vcmpweq:
10379	case Hexagon::A2_vcmpwgt:
10380	case Hexagon::A2_vcmpwgtu:
10381	case Hexagon::A4_boundscheck_hi:
10382	case Hexagon::A4_boundscheck_lo:
10383	case Hexagon::A4_vcmpbeq_any:
10384	case Hexagon::A4_vcmpbgt:
10385	case Hexagon::A6_vcmpbeq_notany:
10386	case Hexagon::C2_cmpeqp:
10387	case Hexagon::C2_cmpgtp:
10388	case Hexagon::C2_cmpgtup:
10389	case Hexagon::F2_dfcmpeq:
10390	case Hexagon::F2_dfcmpge:
10391	case Hexagon::F2_dfcmpgt:
10392	case Hexagon::F2_dfcmpuo: {
10393	// op: Rss32
10394	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10395	op &= UINT64_C(`31`);
10396	op <<= `16`;
10397	Value \|= op;
10398	// op: Rtt32
10399	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10400	op &= UINT64_C(`31`);
10401	op <<= `8`;
10402	Value \|= op;
10403	// op: Pd4
10404	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10405	op &= UINT64_C(`3`);
10406	Value \|= op;
10407	break;
10408	}
10409	case Hexagon::S2_vsplicerb: {
10410	// op: Rss32
10411	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10412	op &= UINT64_C(`31`);
10413	op <<= `16`;
10414	Value \|= op;
10415	// op: Rtt32
10416	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10417	op &= UINT64_C(`31`);
10418	op <<= `8`;
10419	Value \|= op;
10420	// op: Pu4
10421	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10422	op &= UINT64_C(`3`);
10423	op <<= `5`;
10424	Value \|= op;
10425	// op: Rdd32
10426	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10427	op &= UINT64_C(`31`);
10428	Value \|= op;
10429	break;
10430	}
10431	case Hexagon::A5_vaddhubs:
10432	case Hexagon::M2_vdmpyrs_s0:
10433	case Hexagon::M2_vdmpyrs_s1:
10434	case Hexagon::M2_vraddh:
10435	case Hexagon::M2_vradduh:
10436	case Hexagon::M2_vrcmpys_s1rp_h:
10437	case Hexagon::M2_vrcmpys_s1rp_l:
10438	case Hexagon::M7_wcmpyiw:
10439	case Hexagon::M7_wcmpyiw_rnd:
10440	case Hexagon::M7_wcmpyiwc:
10441	case Hexagon::M7_wcmpyiwc_rnd:
10442	case Hexagon::M7_wcmpyrw:
10443	case Hexagon::M7_wcmpyrw_rnd:
10444	case Hexagon::M7_wcmpyrwc:
10445	case Hexagon::M7_wcmpyrwc_rnd:
10446	case Hexagon::S2_parityp: {
10447	// op: Rss32
10448	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10449	op &= UINT64_C(`31`);
10450	op <<= `16`;
10451	Value \|= op;
10452	// op: Rtt32
10453	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10454	op &= UINT64_C(`31`);
10455	op <<= `8`;
10456	Value \|= op;
10457	// op: Rd32
10458	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10459	op &= UINT64_C(`31`);
10460	Value \|= op;
10461	break;
10462	}
10463	case Hexagon::A2_addp:
10464	case Hexagon::A2_addpsat:
10465	case Hexagon::A2_addsph:
10466	case Hexagon::A2_addspl:
10467	case Hexagon::A2_andp:
10468	case Hexagon::A2_maxp:
10469	case Hexagon::A2_maxup:
10470	case Hexagon::A2_orp:
10471	case Hexagon::A2_vaddh:
10472	case Hexagon::A2_vaddhs:
10473	case Hexagon::A2_vaddub:
10474	case Hexagon::A2_vaddubs:
10475	case Hexagon::A2_vadduhs:
10476	case Hexagon::A2_vaddw:
10477	case Hexagon::A2_vaddws:
10478	case Hexagon::A2_vavgh:
10479	case Hexagon::A2_vavghcr:
10480	case Hexagon::A2_vavghr:
10481	case Hexagon::A2_vavgub:
10482	case Hexagon::A2_vavgubr:
10483	case Hexagon::A2_vavguh:
10484	case Hexagon::A2_vavguhr:
10485	case Hexagon::A2_vavguw:
10486	case Hexagon::A2_vavguwr:
10487	case Hexagon::A2_vavgw:
10488	case Hexagon::A2_vavgwcr:
10489	case Hexagon::A2_vavgwr:
10490	case Hexagon::A2_vraddub:
10491	case Hexagon::A2_vrsadub:
10492	case Hexagon::A2_xorp:
10493	case Hexagon::F2_dfadd:
10494	case Hexagon::F2_dfmax:
10495	case Hexagon::F2_dfmin:
10496	case Hexagon::F2_dfmpyfix:
10497	case Hexagon::F2_dfmpyll:
10498	case Hexagon::F2_dfsub:
10499	case Hexagon::M2_mmpyh_rs0:
10500	case Hexagon::M2_mmpyh_rs1:
10501	case Hexagon::M2_mmpyh_s0:
10502	case Hexagon::M2_mmpyh_s1:
10503	case Hexagon::M2_mmpyl_rs0:
10504	case Hexagon::M2_mmpyl_rs1:
10505	case Hexagon::M2_mmpyl_s0:
10506	case Hexagon::M2_mmpyl_s1:
10507	case Hexagon::M2_mmpyuh_rs0:
10508	case Hexagon::M2_mmpyuh_rs1:
10509	case Hexagon::M2_mmpyuh_s0:
10510	case Hexagon::M2_mmpyuh_s1:
10511	case Hexagon::M2_mmpyul_rs0:
10512	case Hexagon::M2_mmpyul_rs1:
10513	case Hexagon::M2_mmpyul_s0:
10514	case Hexagon::M2_mmpyul_s1:
10515	case Hexagon::M2_vcmpy_s0_sat_i:
10516	case Hexagon::M2_vcmpy_s0_sat_r:
10517	case Hexagon::M2_vcmpy_s1_sat_i:
10518	case Hexagon::M2_vcmpy_s1_sat_r:
10519	case Hexagon::M2_vdmpys_s0:
10520	case Hexagon::M2_vdmpys_s1:
10521	case Hexagon::M2_vmpy2es_s0:
10522	case Hexagon::M2_vmpy2es_s1:
10523	case Hexagon::M2_vrcmpyi_s0:
10524	case Hexagon::M2_vrcmpyi_s0c:
10525	case Hexagon::M2_vrcmpyr_s0:
10526	case Hexagon::M2_vrcmpyr_s0c:
10527	case Hexagon::M2_vrcmpys_s1_h:
10528	case Hexagon::M2_vrcmpys_s1_l:
10529	case Hexagon::M2_vrmpy_s0:
10530	case Hexagon::M4_vrmpyeh_s0:
10531	case Hexagon::M4_vrmpyeh_s1:
10532	case Hexagon::M4_vrmpyoh_s0:
10533	case Hexagon::M4_vrmpyoh_s1:
10534	case Hexagon::M5_vdmpybsu:
10535	case Hexagon::M5_vrmpybsu:
10536	case Hexagon::M5_vrmpybuu:
10537	case Hexagon::M7_dcmpyiw:
10538	case Hexagon::M7_dcmpyiwc:
10539	case Hexagon::M7_dcmpyrw:
10540	case Hexagon::M7_dcmpyrwc:
10541	case Hexagon::S2_cabacdecbin:
10542	case Hexagon::S2_extractup_rp:
10543	case Hexagon::S2_lfsp:
10544	case Hexagon::S2_shuffeb:
10545	case Hexagon::S2_shuffeh:
10546	case Hexagon::S2_vtrunewh:
10547	case Hexagon::S2_vtrunowh:
10548	case Hexagon::S4_extractp_rp:
10549	case Hexagon::S4_vxaddsubh:
10550	case Hexagon::S4_vxaddsubhr:
10551	case Hexagon::S4_vxaddsubw:
10552	case Hexagon::S4_vxsubaddh:
10553	case Hexagon::S4_vxsubaddhr:
10554	case Hexagon::S4_vxsubaddw:
10555	case Hexagon::S6_vtrunehb_ppp:
10556	case Hexagon::S6_vtrunohb_ppp: {
10557	// op: Rss32
10558	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10559	op &= UINT64_C(`31`);
10560	op <<= `16`;
10561	Value \|= op;
10562	// op: Rtt32
10563	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10564	op &= UINT64_C(`31`);
10565	op <<= `8`;
10566	Value \|= op;
10567	// op: Rdd32
10568	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10569	op &= UINT64_C(`31`);
10570	Value \|= op;
10571	break;
10572	}
10573	case Hexagon::Y4_tfrspcp: {
10574	// op: Rss32
10575	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10576	op &= UINT64_C(`31`);
10577	op <<= `16`;
10578	Value \|= op;
10579	// op: Sdd128
10580	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10581	op &= UINT64_C(`127`);
10582	Value \|= op;
10583	break;
10584	}
10585	case Hexagon::S2_asl_r_p_acc:
10586	case Hexagon::S2_asl_r_p_and:
10587	case Hexagon::S2_asl_r_p_nac:
10588	case Hexagon::S2_asl_r_p_or:
10589	case Hexagon::S2_asl_r_p_xor:
10590	case Hexagon::S2_asr_r_p_acc:
10591	case Hexagon::S2_asr_r_p_and:
10592	case Hexagon::S2_asr_r_p_nac:
10593	case Hexagon::S2_asr_r_p_or:
10594	case Hexagon::S2_asr_r_p_xor:
10595	case Hexagon::S2_lsl_r_p_acc:
10596	case Hexagon::S2_lsl_r_p_and:
10597	case Hexagon::S2_lsl_r_p_nac:
10598	case Hexagon::S2_lsl_r_p_or:
10599	case Hexagon::S2_lsl_r_p_xor:
10600	case Hexagon::S2_lsr_r_p_acc:
10601	case Hexagon::S2_lsr_r_p_and:
10602	case Hexagon::S2_lsr_r_p_nac:
10603	case Hexagon::S2_lsr_r_p_or:
10604	case Hexagon::S2_lsr_r_p_xor:
10605	case Hexagon::S2_vrcnegh: {
10606	// op: Rss32
10607	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10608	op &= UINT64_C(`31`);
10609	op <<= `16`;
10610	Value \|= op;
10611	// op: Rt32
10612	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10613	op &= UINT64_C(`31`);
10614	op <<= `8`;
10615	Value \|= op;
10616	// op: Rxx32
10617	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10618	op &= UINT64_C(`31`);
10619	Value \|= op;
10620	break;
10621	}
10622	case Hexagon::A4_addp_c:
10623	case Hexagon::A4_subp_c: {
10624	// op: Rss32
10625	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10626	op &= UINT64_C(`31`);
10627	op <<= `16`;
10628	Value \|= op;
10629	// op: Rtt32
10630	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10631	op &= UINT64_C(`31`);
10632	op <<= `8`;
10633	Value \|= op;
10634	// op: Rdd32
10635	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10636	op &= UINT64_C(`31`);
10637	Value \|= op;
10638	// op: Px4
10639	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10640	op &= UINT64_C(`3`);
10641	op <<= `5`;
10642	Value \|= op;
10643	break;
10644	}
10645	case Hexagon::A2_vraddub_acc:
10646	case Hexagon::A2_vrsadub_acc:
10647	case Hexagon::F2_dfmpyhh:
10648	case Hexagon::F2_dfmpylh:
10649	case Hexagon::M2_mmachs_rs0:
10650	case Hexagon::M2_mmachs_rs1:
10651	case Hexagon::M2_mmachs_s0:
10652	case Hexagon::M2_mmachs_s1:
10653	case Hexagon::M2_mmacls_rs0:
10654	case Hexagon::M2_mmacls_rs1:
10655	case Hexagon::M2_mmacls_s0:
10656	case Hexagon::M2_mmacls_s1:
10657	case Hexagon::M2_mmacuhs_rs0:
10658	case Hexagon::M2_mmacuhs_rs1:
10659	case Hexagon::M2_mmacuhs_s0:
10660	case Hexagon::M2_mmacuhs_s1:
10661	case Hexagon::M2_mmaculs_rs0:
10662	case Hexagon::M2_mmaculs_rs1:
10663	case Hexagon::M2_mmaculs_s0:
10664	case Hexagon::M2_mmaculs_s1:
10665	case Hexagon::M2_vcmac_s0_sat_i:
10666	case Hexagon::M2_vcmac_s0_sat_r:
10667	case Hexagon::M2_vdmacs_s0:
10668	case Hexagon::M2_vdmacs_s1:
10669	case Hexagon::M2_vmac2es:
10670	case Hexagon::M2_vmac2es_s0:
10671	case Hexagon::M2_vmac2es_s1:
10672	case Hexagon::M2_vrcmaci_s0:
10673	case Hexagon::M2_vrcmaci_s0c:
10674	case Hexagon::M2_vrcmacr_s0:
10675	case Hexagon::M2_vrcmacr_s0c:
10676	case Hexagon::M2_vrcmpys_acc_s1_h:
10677	case Hexagon::M2_vrcmpys_acc_s1_l:
10678	case Hexagon::M2_vrmac_s0:
10679	case Hexagon::M4_vrmpyeh_acc_s0:
10680	case Hexagon::M4_vrmpyeh_acc_s1:
10681	case Hexagon::M4_vrmpyoh_acc_s0:
10682	case Hexagon::M4_vrmpyoh_acc_s1:
10683	case Hexagon::M4_xor_xacc:
10684	case Hexagon::M5_vdmacbsu:
10685	case Hexagon::M5_vrmacbsu:
10686	case Hexagon::M5_vrmacbuu:
10687	case Hexagon::M7_dcmpyiw_acc:
10688	case Hexagon::M7_dcmpyiwc_acc:
10689	case Hexagon::M7_dcmpyrw_acc:
10690	case Hexagon::M7_dcmpyrwc_acc:
10691	case Hexagon::S2_insertp_rp: {
10692	// op: Rss32
10693	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10694	op &= UINT64_C(`31`);
10695	op <<= `16`;
10696	Value \|= op;
10697	// op: Rtt32
10698	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10699	op &= UINT64_C(`31`);
10700	op <<= `8`;
10701	Value \|= op;
10702	// op: Rxx32
10703	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10704	op &= UINT64_C(`31`);
10705	Value \|= op;
10706	break;
10707	}
10708	case Hexagon::A4_vrmaxh:
10709	case Hexagon::A4_vrmaxuh:
10710	case Hexagon::A4_vrmaxuw:
10711	case Hexagon::A4_vrmaxw:
10712	case Hexagon::A4_vrminh:
10713	case Hexagon::A4_vrminuh:
10714	case Hexagon::A4_vrminuw:
10715	case Hexagon::A4_vrminw: {
10716	// op: Rss32
10717	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10718	op &= UINT64_C(`31`);
10719	op <<= `16`;
10720	Value \|= op;
10721	// op: Ru32
10722	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10723	op &= UINT64_C(`31`);
10724	Value \|= op;
10725	// op: Rxx32
10726	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10727	op &= UINT64_C(`31`);
10728	op <<= `8`;
10729	Value \|= op;
10730	break;
10731	}
10732	case Hexagon::A5_ACS: {
10733	// op: Rss32
10734	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10735	op &= UINT64_C(`31`);
10736	op <<= `16`;
10737	Value \|= op;
10738	// op: Rtt32
10739	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
10740	op &= UINT64_C(`31`);
10741	op <<= `8`;
10742	Value \|= op;
10743	// op: Rxx32
10744	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10745	op &= UINT64_C(`31`);
10746	Value \|= op;
10747	// op: Pe4
10748	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10749	op &= UINT64_C(`3`);
10750	op <<= `5`;
10751	Value \|= op;
10752	break;
10753	}
10754	case Hexagon::V6_vgathermh:
10755	case Hexagon::V6_vgathermw: {
10756	// op: Rt32
10757	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10758	op &= UINT64_C(`31`);
10759	op <<= `16`;
10760	Value \|= op;
10761	// op: Mu2
10762	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10763	op &= UINT64_C(`1`);
10764	op <<= `13`;
10765	Value \|= op;
10766	// op: Vv32
10767	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10768	op &= UINT64_C(`31`);
10769	Value \|= op;
10770	break;
10771	}
10772	case Hexagon::V6_vscattermh:
10773	case Hexagon::V6_vscattermh_add:
10774	case Hexagon::V6_vscattermw:
10775	case Hexagon::V6_vscattermw_add: {
10776	// op: Rt32
10777	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10778	op &= UINT64_C(`31`);
10779	op <<= `16`;
10780	Value \|= op;
10781	// op: Mu2
10782	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10783	op &= UINT64_C(`1`);
10784	op <<= `13`;
10785	Value \|= op;
10786	// op: Vv32
10787	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10788	op &= UINT64_C(`31`);
10789	op <<= `8`;
10790	Value \|= op;
10791	// op: Vw32
10792	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10793	op &= UINT64_C(`31`);
10794	Value \|= op;
10795	break;
10796	}
10797	case Hexagon::V6_vgathermhw: {
10798	// op: Rt32
10799	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10800	op &= UINT64_C(`31`);
10801	op <<= `16`;
10802	Value \|= op;
10803	// op: Mu2
10804	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10805	op &= UINT64_C(`1`);
10806	op <<= `13`;
10807	Value \|= op;
10808	// op: Vvv32
10809	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10810	op &= UINT64_C(`31`);
10811	Value \|= op;
10812	break;
10813	}
10814	case Hexagon::V6_vscattermhw:
10815	case Hexagon::V6_vscattermhw_add: {
10816	// op: Rt32
10817	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10818	op &= UINT64_C(`31`);
10819	op <<= `16`;
10820	Value \|= op;
10821	// op: Mu2
10822	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10823	op &= UINT64_C(`1`);
10824	op <<= `13`;
10825	Value \|= op;
10826	// op: Vvv32
10827	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10828	op &= UINT64_C(`31`);
10829	op <<= `8`;
10830	Value \|= op;
10831	// op: Vw32
10832	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10833	op &= UINT64_C(`31`);
10834	Value \|= op;
10835	break;
10836	}
10837	case Hexagon::V6_pred_scalar2:
10838	case Hexagon::V6_pred_scalar2v2: {
10839	// op: Rt32
10840	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10841	op &= UINT64_C(`31`);
10842	op <<= `16`;
10843	Value \|= op;
10844	// op: Qd4
10845	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10846	op &= UINT64_C(`3`);
10847	Value \|= op;
10848	break;
10849	}
10850	case Hexagon::V6_lvsplatb:
10851	case Hexagon::V6_lvsplath:
10852	case Hexagon::V6_lvsplatw:
10853	case Hexagon::V6_zextract: {
10854	// op: Rt32
10855	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10856	op &= UINT64_C(`31`);
10857	op <<= `16`;
10858	Value \|= op;
10859	// op: Vd32
10860	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10861	op &= UINT64_C(`31`);
10862	Value \|= op;
10863	break;
10864	}
10865	case Hexagon::A2_addh_h16_hh:
10866	case Hexagon::A2_addh_h16_hl:
10867	case Hexagon::A2_addh_h16_lh:
10868	case Hexagon::A2_addh_h16_ll:
10869	case Hexagon::A2_addh_h16_sat_hh:
10870	case Hexagon::A2_addh_h16_sat_hl:
10871	case Hexagon::A2_addh_h16_sat_lh:
10872	case Hexagon::A2_addh_h16_sat_ll:
10873	case Hexagon::A2_addh_l16_hl:
10874	case Hexagon::A2_addh_l16_ll:
10875	case Hexagon::A2_addh_l16_sat_hl:
10876	case Hexagon::A2_addh_l16_sat_ll:
10877	case Hexagon::A2_combine_hh:
10878	case Hexagon::A2_combine_hl:
10879	case Hexagon::A2_combine_lh:
10880	case Hexagon::A2_combine_ll:
10881	case Hexagon::A2_min:
10882	case Hexagon::A2_minu:
10883	case Hexagon::A2_sub:
10884	case Hexagon::A2_subh_h16_hh:
10885	case Hexagon::A2_subh_h16_hl:
10886	case Hexagon::A2_subh_h16_lh:
10887	case Hexagon::A2_subh_h16_ll:
10888	case Hexagon::A2_subh_h16_sat_hh:
10889	case Hexagon::A2_subh_h16_sat_hl:
10890	case Hexagon::A2_subh_h16_sat_lh:
10891	case Hexagon::A2_subh_h16_sat_ll:
10892	case Hexagon::A2_subh_l16_hl:
10893	case Hexagon::A2_subh_l16_ll:
10894	case Hexagon::A2_subh_l16_sat_hl:
10895	case Hexagon::A2_subh_l16_sat_ll:
10896	case Hexagon::A2_subsat:
10897	case Hexagon::A2_svnavgh:
10898	case Hexagon::A2_svsubh:
10899	case Hexagon::A2_svsubhs:
10900	case Hexagon::A2_svsubuhs:
10901	case Hexagon::A4_andn:
10902	case Hexagon::A4_orn:
10903	case Hexagon::dep_A2_subsat: {
10904	// op: Rt32
10905	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10906	op &= UINT64_C(`31`);
10907	op <<= `8`;
10908	Value \|= op;
10909	// op: Rs32
10910	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10911	op &= UINT64_C(`31`);
10912	op <<= `16`;
10913	Value \|= op;
10914	// op: Rd32
10915	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10916	op &= UINT64_C(`31`);
10917	Value \|= op;
10918	break;
10919	}
10920	case Hexagon::V6_vinsertwr: {
10921	// op: Rt32
10922	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10923	op &= UINT64_C(`31`);
10924	op <<= `16`;
10925	Value \|= op;
10926	// op: Vx32
10927	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10928	op &= UINT64_C(`31`);
10929	Value \|= op;
10930	break;
10931	}
10932	case Hexagon::M2_subacc: {
10933	// op: Rt32
10934	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10935	op &= UINT64_C(`31`);
10936	op <<= `8`;
10937	Value \|= op;
10938	// op: Rs32
10939	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10940	op &= UINT64_C(`31`);
10941	op <<= `16`;
10942	Value \|= op;
10943	// op: Rx32
10944	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10945	op &= UINT64_C(`31`);
10946	Value \|= op;
10947	break;
10948	}
10949	case Hexagon::V6_vdeal:
10950	case Hexagon::V6_vshuff: {
10951	// op: Rt32
10952	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
10953	op &= UINT64_C(`31`);
10954	op <<= `16`;
10955	Value \|= op;
10956	// op: Vy32
10957	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10958	op &= UINT64_C(`31`);
10959	op <<= `8`;
10960	Value \|= op;
10961	// op: Vx32
10962	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10963	op &= UINT64_C(`31`);
10964	Value \|= op;
10965	break;
10966	}
10967	case Hexagon::Y6_l2gcleaninvpa:
10968	case Hexagon::Y6_l2gcleanpa: {
10969	// op: Rtt32
10970	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10971	op &= UINT64_C(`31`);
10972	op <<= `8`;
10973	Value \|= op;
10974	break;
10975	}
10976	case Hexagon::S2_valignrb: {
10977	// op: Rtt32
10978	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
10979	op &= UINT64_C(`31`);
10980	op <<= `8`;
10981	Value \|= op;
10982	// op: Rss32
10983	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
10984	op &= UINT64_C(`31`);
10985	op <<= `16`;
10986	Value \|= op;
10987	// op: Pu4
10988	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
10989	op &= UINT64_C(`3`);
10990	op <<= `5`;
10991	Value \|= op;
10992	// op: Rdd32
10993	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
10994	op &= UINT64_C(`31`);
10995	Value \|= op;
10996	break;
10997	}
10998	case Hexagon::A2_minp:
10999	case Hexagon::A2_minup:
11000	case Hexagon::A2_subp:
11001	case Hexagon::A2_vmaxb:
11002	case Hexagon::A2_vmaxh:
11003	case Hexagon::A2_vmaxub:
11004	case Hexagon::A2_vmaxuh:
11005	case Hexagon::A2_vmaxuw:
11006	case Hexagon::A2_vmaxw:
11007	case Hexagon::A2_vminb:
11008	case Hexagon::A2_vminh:
11009	case Hexagon::A2_vminub:
11010	case Hexagon::A2_vminuh:
11011	case Hexagon::A2_vminuw:
11012	case Hexagon::A2_vminw:
11013	case Hexagon::A2_vnavgh:
11014	case Hexagon::A2_vnavghcr:
11015	case Hexagon::A2_vnavghr:
11016	case Hexagon::A2_vnavgw:
11017	case Hexagon::A2_vnavgwcr:
11018	case Hexagon::A2_vnavgwr:
11019	case Hexagon::A2_vsubh:
11020	case Hexagon::A2_vsubhs:
11021	case Hexagon::A2_vsubub:
11022	case Hexagon::A2_vsububs:
11023	case Hexagon::A2_vsubuhs:
11024	case Hexagon::A2_vsubw:
11025	case Hexagon::A2_vsubws:
11026	case Hexagon::A4_andnp:
11027	case Hexagon::A4_ornp:
11028	case Hexagon::M2_vabsdiffh:
11029	case Hexagon::M2_vabsdiffw:
11030	case Hexagon::M6_vabsdiffb:
11031	case Hexagon::M6_vabsdiffub:
11032	case Hexagon::S2_shuffob:
11033	case Hexagon::S2_shuffoh: {
11034	// op: Rtt32
11035	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11036	op &= UINT64_C(`31`);
11037	op <<= `8`;
11038	Value \|= op;
11039	// op: Rss32
11040	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11041	op &= UINT64_C(`31`);
11042	op <<= `16`;
11043	Value \|= op;
11044	// op: Rdd32
11045	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11046	op &= UINT64_C(`31`);
11047	Value \|= op;
11048	break;
11049	}
11050	case Hexagon::A6_vminub_RdP: {
11051	// op: Rtt32
11052	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11053	op &= UINT64_C(`31`);
11054	op <<= `8`;
11055	Value \|= op;
11056	// op: Rss32
11057	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11058	op &= UINT64_C(`31`);
11059	op <<= `16`;
11060	Value \|= op;
11061	// op: Rdd32
11062	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11063	op &= UINT64_C(`31`);
11064	Value \|= op;
11065	// op: Pe4
11066	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11067	op &= UINT64_C(`3`);
11068	op <<= `5`;
11069	Value \|= op;
11070	break;
11071	}
11072	case Hexagon::M4_mpyrr_addr: {
11073	// op: Ru32
11074	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11075	op &= UINT64_C(`31`);
11076	Value \|= op;
11077	// op: Rs32
11078	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11079	op &= UINT64_C(`31`);
11080	op <<= `16`;
11081	Value \|= op;
11082	// op: Ry32
11083	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11084	op &= UINT64_C(`31`);
11085	op <<= `8`;
11086	Value \|= op;
11087	break;
11088	}
11089	case Hexagon::Y2_crswap0:
11090	case Hexagon::Y4_crswap1: {
11091	// op: Rx32
11092	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11093	op &= UINT64_C(`31`);
11094	op <<= `16`;
11095	Value \|= op;
11096	break;
11097	}
11098	case Hexagon::Y4_crswap10: {
11099	// op: Rxx32
11100	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11101	op &= UINT64_C(`31`);
11102	op <<= `16`;
11103	Value \|= op;
11104	break;
11105	}
11106	case Hexagon::Y2_tfrscrr: {
11107	// op: Ss128
11108	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11109	op &= UINT64_C(`127`);
11110	op <<= `16`;
11111	Value \|= op;
11112	// op: Rd32
11113	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11114	op &= UINT64_C(`31`);
11115	Value \|= op;
11116	break;
11117	}
11118	case Hexagon::Y4_tfrscpp: {
11119	// op: Sss128
11120	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11121	op &= UINT64_C(`127`);
11122	op <<= `16`;
11123	Value \|= op;
11124	// op: Rdd32
11125	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11126	op &= UINT64_C(`31`);
11127	Value \|= op;
11128	break;
11129	}
11130	case Hexagon::V6_extractw: {
11131	// op: Vu32
11132	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11133	op &= UINT64_C(`31`);
11134	op <<= `8`;
11135	Value \|= op;
11136	// op: Rs32
11137	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11138	op &= UINT64_C(`31`);
11139	op <<= `16`;
11140	Value \|= op;
11141	// op: Rd32
11142	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11143	op &= UINT64_C(`31`);
11144	Value \|= op;
11145	break;
11146	}
11147	case Hexagon::V6_vandvrt: {
11148	// op: Vu32
11149	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11150	op &= UINT64_C(`31`);
11151	op <<= `8`;
11152	Value \|= op;
11153	// op: Rt32
11154	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11155	op &= UINT64_C(`31`);
11156	op <<= `16`;
11157	Value \|= op;
11158	// op: Qd4
11159	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11160	op &= UINT64_C(`3`);
11161	Value \|= op;
11162	break;
11163	}
11164	case Hexagon::V6_vaslh:
11165	case Hexagon::V6_vaslw:
11166	case Hexagon::V6_vasrh:
11167	case Hexagon::V6_vasrw:
11168	case Hexagon::V6_vdmpybus:
11169	case Hexagon::V6_vdmpyhb:
11170	case Hexagon::V6_vdmpyhsat:
11171	case Hexagon::V6_vdmpyhsusat:
11172	case Hexagon::V6_vlsrb:
11173	case Hexagon::V6_vlsrh:
11174	case Hexagon::V6_vlsrw:
11175	case Hexagon::V6_vmpyhsrs:
11176	case Hexagon::V6_vmpyhss:
11177	case Hexagon::V6_vmpyihb:
11178	case Hexagon::V6_vmpyiwb:
11179	case Hexagon::V6_vmpyiwh:
11180	case Hexagon::V6_vmpyiwub:
11181	case Hexagon::V6_vmpyuhe:
11182	case Hexagon::V6_vrmpybus:
11183	case Hexagon::V6_vrmpyub:
11184	case Hexagon::V6_vror: {
11185	// op: Vu32
11186	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11187	op &= UINT64_C(`31`);
11188	op <<= `8`;
11189	Value \|= op;
11190	// op: Rt32
11191	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11192	op &= UINT64_C(`31`);
11193	op <<= `16`;
11194	Value \|= op;
11195	// op: Vd32
11196	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11197	op &= UINT64_C(`31`);
11198	Value \|= op;
11199	break;
11200	}
11201	case Hexagon::V6_vmpybus:
11202	case Hexagon::V6_vmpyh:
11203	case Hexagon::V6_vmpyub:
11204	case Hexagon::V6_vmpyuh: {
11205	// op: Vu32
11206	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11207	op &= UINT64_C(`31`);
11208	op <<= `8`;
11209	Value \|= op;
11210	// op: Rt32
11211	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11212	op &= UINT64_C(`31`);
11213	op <<= `16`;
11214	Value \|= op;
11215	// op: Vdd32
11216	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11217	op &= UINT64_C(`31`);
11218	Value \|= op;
11219	break;
11220	}
11221	case Hexagon::V6_vrmpyzbb_rt:
11222	case Hexagon::V6_vrmpyzbub_rt:
11223	case Hexagon::V6_vrmpyzcb_rt:
11224	case Hexagon::V6_vrmpyzcbs_rt:
11225	case Hexagon::V6_vrmpyznb_rt: {
11226	// op: Vu32
11227	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11228	op &= UINT64_C(`31`);
11229	op <<= `8`;
11230	Value \|= op;
11231	// op: Rt8
11232	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11233	op &= UINT64_C(`7`);
11234	op <<= `16`;
11235	Value \|= op;
11236	// op: Vdddd32
11237	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11238	op &= UINT64_C(`31`);
11239	Value \|= op;
11240	break;
11241	}
11242	case Hexagon::V6_vlut4: {
11243	// op: Vu32
11244	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11245	op &= UINT64_C(`31`);
11246	op <<= `8`;
11247	Value \|= op;
11248	// op: Rtt32
11249	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11250	op &= UINT64_C(`31`);
11251	op <<= `16`;
11252	Value \|= op;
11253	// op: Vd32
11254	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11255	op &= UINT64_C(`31`);
11256	Value \|= op;
11257	break;
11258	}
11259	case Hexagon::V6_vrmpybub_rtt:
11260	case Hexagon::V6_vrmpyub_rtt: {
11261	// op: Vu32
11262	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11263	op &= UINT64_C(`31`);
11264	op <<= `8`;
11265	Value \|= op;
11266	// op: Rtt32
11267	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11268	op &= UINT64_C(`31`);
11269	op <<= `16`;
11270	Value \|= op;
11271	// op: Vdd32
11272	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11273	op &= UINT64_C(`31`);
11274	Value \|= op;
11275	break;
11276	}
11277	case Hexagon::V6_vabs_hf:
11278	case Hexagon::V6_vabs_sf:
11279	case Hexagon::V6_vabsb:
11280	case Hexagon::V6_vabsb_sat:
11281	case Hexagon::V6_vabsh:
11282	case Hexagon::V6_vabsh_sat:
11283	case Hexagon::V6_vabsw:
11284	case Hexagon::V6_vabsw_sat:
11285	case Hexagon::V6_vassign:
11286	case Hexagon::V6_vassign_fp:
11287	case Hexagon::V6_vassign_tmp:
11288	case Hexagon::V6_vcl0h:
11289	case Hexagon::V6_vcl0w:
11290	case Hexagon::V6_vconv_h_hf:
11291	case Hexagon::V6_vconv_hf_h:
11292	case Hexagon::V6_vconv_hf_qf16:
11293	case Hexagon::V6_vconv_sf_qf32:
11294	case Hexagon::V6_vconv_sf_w:
11295	case Hexagon::V6_vconv_w_sf:
11296	case Hexagon::V6_vcvt_h_hf:
11297	case Hexagon::V6_vcvt_hf_h:
11298	case Hexagon::V6_vcvt_hf_uh:
11299	case Hexagon::V6_vcvt_uh_hf:
11300	case Hexagon::V6_vdealb:
11301	case Hexagon::V6_vdealh:
11302	case Hexagon::V6_vfneg_hf:
11303	case Hexagon::V6_vfneg_sf:
11304	case Hexagon::V6_vnormamth:
11305	case Hexagon::V6_vnormamtw:
11306	case Hexagon::V6_vnot:
11307	case Hexagon::V6_vpopcounth:
11308	case Hexagon::V6_vshuffb:
11309	case Hexagon::V6_vshuffh: {
11310	// op: Vu32
11311	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11312	op &= UINT64_C(`31`);
11313	op <<= `8`;
11314	Value \|= op;
11315	// op: Vd32
11316	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11317	op &= UINT64_C(`31`);
11318	Value \|= op;
11319	break;
11320	}
11321	case Hexagon::V6_vcvt_hf_b:
11322	case Hexagon::V6_vcvt_hf_ub:
11323	case Hexagon::V6_vcvt_sf_hf:
11324	case Hexagon::V6_vsb:
11325	case Hexagon::V6_vsh:
11326	case Hexagon::V6_vunpackb:
11327	case Hexagon::V6_vunpackh:
11328	case Hexagon::V6_vunpackub:
11329	case Hexagon::V6_vunpackuh:
11330	case Hexagon::V6_vzb:
11331	case Hexagon::V6_vzh: {
11332	// op: Vu32
11333	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11334	op &= UINT64_C(`31`);
11335	op <<= `8`;
11336	Value \|= op;
11337	// op: Vdd32
11338	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11339	op &= UINT64_C(`31`);
11340	Value \|= op;
11341	break;
11342	}
11343	case Hexagon::V6_veqb:
11344	case Hexagon::V6_veqh:
11345	case Hexagon::V6_veqw:
11346	case Hexagon::V6_vgtb:
11347	case Hexagon::V6_vgtbf:
11348	case Hexagon::V6_vgth:
11349	case Hexagon::V6_vgthf:
11350	case Hexagon::V6_vgtsf:
11351	case Hexagon::V6_vgtub:
11352	case Hexagon::V6_vgtuh:
11353	case Hexagon::V6_vgtuw:
11354	case Hexagon::V6_vgtw: {
11355	// op: Vu32
11356	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11357	op &= UINT64_C(`31`);
11358	op <<= `8`;
11359	Value \|= op;
11360	// op: Vv32
11361	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11362	op &= UINT64_C(`31`);
11363	op <<= `16`;
11364	Value \|= op;
11365	// op: Qd4
11366	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11367	op &= UINT64_C(`3`);
11368	Value \|= op;
11369	break;
11370	}
11371	case Hexagon::V6_vaddcarrysat: {
11372	// op: Vu32
11373	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11374	op &= UINT64_C(`31`);
11375	op <<= `8`;
11376	Value \|= op;
11377	// op: Vv32
11378	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11379	op &= UINT64_C(`31`);
11380	op <<= `16`;
11381	Value \|= op;
11382	// op: Qs4
11383	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11384	op &= UINT64_C(`3`);
11385	op <<= `5`;
11386	Value \|= op;
11387	// op: Vd32
11388	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11389	op &= UINT64_C(`31`);
11390	Value \|= op;
11391	break;
11392	}
11393	case Hexagon::V6_vabsdiffh:
11394	case Hexagon::V6_vabsdiffub:
11395	case Hexagon::V6_vabsdiffuh:
11396	case Hexagon::V6_vabsdiffw:
11397	case Hexagon::V6_vadd_hf:
11398	case Hexagon::V6_vadd_hf_hf:
11399	case Hexagon::V6_vadd_qf16:
11400	case Hexagon::V6_vadd_qf16_mix:
11401	case Hexagon::V6_vadd_qf32:
11402	case Hexagon::V6_vadd_qf32_mix:
11403	case Hexagon::V6_vadd_sf:
11404	case Hexagon::V6_vadd_sf_sf:
11405	case Hexagon::V6_vaddb:
11406	case Hexagon::V6_vaddbsat:
11407	case Hexagon::V6_vaddclbh:
11408	case Hexagon::V6_vaddclbw:
11409	case Hexagon::V6_vaddh:
11410	case Hexagon::V6_vaddhsat:
11411	case Hexagon::V6_vaddubsat:
11412	case Hexagon::V6_vaddububb_sat:
11413	case Hexagon::V6_vadduhsat:
11414	case Hexagon::V6_vadduwsat:
11415	case Hexagon::V6_vaddw:
11416	case Hexagon::V6_vaddwsat:
11417	case Hexagon::V6_vand:
11418	case Hexagon::V6_vaslhv:
11419	case Hexagon::V6_vaslwv:
11420	case Hexagon::V6_vasrhv:
11421	case Hexagon::V6_vasrwv:
11422	case Hexagon::V6_vavgb:
11423	case Hexagon::V6_vavgbrnd:
11424	case Hexagon::V6_vavgh:
11425	case Hexagon::V6_vavghrnd:
11426	case Hexagon::V6_vavgub:
11427	case Hexagon::V6_vavgubrnd:
11428	case Hexagon::V6_vavguh:
11429	case Hexagon::V6_vavguhrnd:
11430	case Hexagon::V6_vavguw:
11431	case Hexagon::V6_vavguwrnd:
11432	case Hexagon::V6_vavgw:
11433	case Hexagon::V6_vavgwrnd:
11434	case Hexagon::V6_vcvt_b_hf:
11435	case Hexagon::V6_vcvt_bf_sf:
11436	case Hexagon::V6_vcvt_hf_sf:
11437	case Hexagon::V6_vcvt_ub_hf:
11438	case Hexagon::V6_vdealb4w:
11439	case Hexagon::V6_vdelta:
11440	case Hexagon::V6_vdmpy_sf_hf:
11441	case Hexagon::V6_vdmpyhvsat:
11442	case Hexagon::V6_vfmax_hf:
11443	case Hexagon::V6_vfmax_sf:
11444	case Hexagon::V6_vfmin_hf:
11445	case Hexagon::V6_vfmin_sf:
11446	case Hexagon::V6_vlsrhv:
11447	case Hexagon::V6_vlsrwv:
11448	case Hexagon::V6_vmax_bf:
11449	case Hexagon::V6_vmax_hf:
11450	case Hexagon::V6_vmax_sf:
11451	case Hexagon::V6_vmaxb:
11452	case Hexagon::V6_vmaxh:
11453	case Hexagon::V6_vmaxub:
11454	case Hexagon::V6_vmaxuh:
11455	case Hexagon::V6_vmaxw:
11456	case Hexagon::V6_vmin_bf:
11457	case Hexagon::V6_vmin_hf:
11458	case Hexagon::V6_vmin_sf:
11459	case Hexagon::V6_vminb:
11460	case Hexagon::V6_vminh:
11461	case Hexagon::V6_vminub:
11462	case Hexagon::V6_vminuh:
11463	case Hexagon::V6_vminw:
11464	case Hexagon::V6_vmpy_hf_hf:
11465	case Hexagon::V6_vmpy_qf16:
11466	case Hexagon::V6_vmpy_qf16_hf:
11467	case Hexagon::V6_vmpy_qf16_mix_hf:
11468	case Hexagon::V6_vmpy_qf32:
11469	case Hexagon::V6_vmpy_qf32_sf:
11470	case Hexagon::V6_vmpy_sf_sf:
11471	case Hexagon::V6_vmpyewuh:
11472	case Hexagon::V6_vmpyhvsrs:
11473	case Hexagon::V6_vmpyieoh:
11474	case Hexagon::V6_vmpyiewuh:
11475	case Hexagon::V6_vmpyih:
11476	case Hexagon::V6_vmpyiowh:
11477	case Hexagon::V6_vmpyowh:
11478	case Hexagon::V6_vmpyowh_rnd:
11479	case Hexagon::V6_vmpyuhvs:
11480	case Hexagon::V6_vnavgb:
11481	case Hexagon::V6_vnavgh:
11482	case Hexagon::V6_vnavgub:
11483	case Hexagon::V6_vnavgw:
11484	case Hexagon::V6_vor:
11485	case Hexagon::V6_vpackeb:
11486	case Hexagon::V6_vpackeh:
11487	case Hexagon::V6_vpackhb_sat:
11488	case Hexagon::V6_vpackhub_sat:
11489	case Hexagon::V6_vpackob:
11490	case Hexagon::V6_vpackoh:
11491	case Hexagon::V6_vpackwh_sat:
11492	case Hexagon::V6_vpackwuh_sat:
11493	case Hexagon::V6_vrdelta:
11494	case Hexagon::V6_vrmpybusv:
11495	case Hexagon::V6_vrmpybv:
11496	case Hexagon::V6_vrmpyubv:
11497	case Hexagon::V6_vrotr:
11498	case Hexagon::V6_vroundhb:
11499	case Hexagon::V6_vroundhub:
11500	case Hexagon::V6_vrounduhub:
11501	case Hexagon::V6_vrounduwuh:
11502	case Hexagon::V6_vroundwh:
11503	case Hexagon::V6_vroundwuh:
11504	case Hexagon::V6_vsatdw:
11505	case Hexagon::V6_vsathub:
11506	case Hexagon::V6_vsatuwuh:
11507	case Hexagon::V6_vsatwh:
11508	case Hexagon::V6_vshufeh:
11509	case Hexagon::V6_vshuffeb:
11510	case Hexagon::V6_vshuffob:
11511	case Hexagon::V6_vshufoh:
11512	case Hexagon::V6_vsub_hf:
11513	case Hexagon::V6_vsub_hf_hf:
11514	case Hexagon::V6_vsub_qf16:
11515	case Hexagon::V6_vsub_qf16_mix:
11516	case Hexagon::V6_vsub_qf32:
11517	case Hexagon::V6_vsub_qf32_mix:
11518	case Hexagon::V6_vsub_sf:
11519	case Hexagon::V6_vsub_sf_sf:
11520	case Hexagon::V6_vsubb:
11521	case Hexagon::V6_vsubbsat:
11522	case Hexagon::V6_vsubh:
11523	case Hexagon::V6_vsubhsat:
11524	case Hexagon::V6_vsububsat:
11525	case Hexagon::V6_vsubububb_sat:
11526	case Hexagon::V6_vsubuhsat:
11527	case Hexagon::V6_vsubuwsat:
11528	case Hexagon::V6_vsubw:
11529	case Hexagon::V6_vsubwsat:
11530	case Hexagon::V6_vxor: {
11531	// op: Vu32
11532	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11533	op &= UINT64_C(`31`);
11534	op <<= `8`;
11535	Value \|= op;
11536	// op: Vv32
11537	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11538	op &= UINT64_C(`31`);
11539	op <<= `16`;
11540	Value \|= op;
11541	// op: Vd32
11542	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11543	op &= UINT64_C(`31`);
11544	Value \|= op;
11545	break;
11546	}
11547	case Hexagon::V6_vadd_sf_bf:
11548	case Hexagon::V6_vadd_sf_hf:
11549	case Hexagon::V6_vaddhw:
11550	case Hexagon::V6_vaddubh:
11551	case Hexagon::V6_vadduhw:
11552	case Hexagon::V6_vcombine:
11553	case Hexagon::V6_vcombine_tmp:
11554	case Hexagon::V6_vmpy_qf32_hf:
11555	case Hexagon::V6_vmpy_qf32_mix_hf:
11556	case Hexagon::V6_vmpy_qf32_qf16:
11557	case Hexagon::V6_vmpy_sf_bf:
11558	case Hexagon::V6_vmpy_sf_hf:
11559	case Hexagon::V6_vmpybusv:
11560	case Hexagon::V6_vmpybv:
11561	case Hexagon::V6_vmpyewuh_64:
11562	case Hexagon::V6_vmpyhus:
11563	case Hexagon::V6_vmpyhv:
11564	case Hexagon::V6_vmpyubv:
11565	case Hexagon::V6_vmpyuhv:
11566	case Hexagon::V6_vshufoeb:
11567	case Hexagon::V6_vshufoeh:
11568	case Hexagon::V6_vsub_sf_bf:
11569	case Hexagon::V6_vsub_sf_hf:
11570	case Hexagon::V6_vsubhw:
11571	case Hexagon::V6_vsububh:
11572	case Hexagon::V6_vsubuhw: {
11573	// op: Vu32
11574	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11575	op &= UINT64_C(`31`);
11576	op <<= `8`;
11577	Value \|= op;
11578	// op: Vv32
11579	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11580	op &= UINT64_C(`31`);
11581	op <<= `16`;
11582	Value \|= op;
11583	// op: Vdd32
11584	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11585	op &= UINT64_C(`31`);
11586	Value \|= op;
11587	break;
11588	}
11589	case Hexagon::V6_valignb:
11590	case Hexagon::V6_vasrhbrndsat:
11591	case Hexagon::V6_vasrhbsat:
11592	case Hexagon::V6_vasrhubrndsat:
11593	case Hexagon::V6_vasrhubsat:
11594	case Hexagon::V6_vasruhubrndsat:
11595	case Hexagon::V6_vasruhubsat:
11596	case Hexagon::V6_vasruwuhrndsat:
11597	case Hexagon::V6_vasruwuhsat:
11598	case Hexagon::V6_vasrwh:
11599	case Hexagon::V6_vasrwhrndsat:
11600	case Hexagon::V6_vasrwhsat:
11601	case Hexagon::V6_vasrwuhrndsat:
11602	case Hexagon::V6_vasrwuhsat:
11603	case Hexagon::V6_vlalignb:
11604	case Hexagon::V6_vlutvvb:
11605	case Hexagon::V6_vlutvvb_nm: {
11606	// op: Vu32
11607	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11608	op &= UINT64_C(`31`);
11609	op <<= `8`;
11610	Value \|= op;
11611	// op: Vv32
11612	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11613	op &= UINT64_C(`31`);
11614	op <<= `19`;
11615	Value \|= op;
11616	// op: Rt8
11617	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11618	op &= UINT64_C(`7`);
11619	op <<= `16`;
11620	Value \|= op;
11621	// op: Vd32
11622	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11623	op &= UINT64_C(`31`);
11624	Value \|= op;
11625	break;
11626	}
11627	case Hexagon::V6_vdealvdd:
11628	case Hexagon::V6_vlutvwh:
11629	case Hexagon::V6_vlutvwh_nm:
11630	case Hexagon::V6_vshuffvdd: {
11631	// op: Vu32
11632	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11633	op &= UINT64_C(`31`);
11634	op <<= `8`;
11635	Value \|= op;
11636	// op: Vv32
11637	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11638	op &= UINT64_C(`31`);
11639	op <<= `19`;
11640	Value \|= op;
11641	// op: Rt8
11642	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11643	op &= UINT64_C(`7`);
11644	op <<= `16`;
11645	Value \|= op;
11646	// op: Vdd32
11647	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11648	op &= UINT64_C(`31`);
11649	Value \|= op;
11650	break;
11651	}
11652	case Hexagon::V6_vandvrt_acc: {
11653	// op: Vu32
11654	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11655	op &= UINT64_C(`31`);
11656	op <<= `8`;
11657	Value \|= op;
11658	// op: Rt32
11659	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11660	op &= UINT64_C(`31`);
11661	op <<= `16`;
11662	Value \|= op;
11663	// op: Qx4
11664	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11665	op &= UINT64_C(`3`);
11666	Value \|= op;
11667	break;
11668	}
11669	case Hexagon::V6_vaslh_acc:
11670	case Hexagon::V6_vaslw_acc:
11671	case Hexagon::V6_vasrh_acc:
11672	case Hexagon::V6_vasrw_acc:
11673	case Hexagon::V6_vdmpybus_acc:
11674	case Hexagon::V6_vdmpyhb_acc:
11675	case Hexagon::V6_vdmpyhsat_acc:
11676	case Hexagon::V6_vdmpyhsusat_acc:
11677	case Hexagon::V6_vmpyihb_acc:
11678	case Hexagon::V6_vmpyiwb_acc:
11679	case Hexagon::V6_vmpyiwh_acc:
11680	case Hexagon::V6_vmpyiwub_acc:
11681	case Hexagon::V6_vmpyuhe_acc:
11682	case Hexagon::V6_vrmpybus_acc:
11683	case Hexagon::V6_vrmpyub_acc: {
11684	// op: Vu32
11685	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11686	op &= UINT64_C(`31`);
11687	op <<= `8`;
11688	Value \|= op;
11689	// op: Rt32
11690	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11691	op &= UINT64_C(`31`);
11692	op <<= `16`;
11693	Value \|= op;
11694	// op: Vx32
11695	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11696	op &= UINT64_C(`31`);
11697	Value \|= op;
11698	break;
11699	}
11700	case Hexagon::V6_vmpybus_acc:
11701	case Hexagon::V6_vmpyh_acc:
11702	case Hexagon::V6_vmpyhsat_acc:
11703	case Hexagon::V6_vmpyub_acc:
11704	case Hexagon::V6_vmpyuh_acc: {
11705	// op: Vu32
11706	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11707	op &= UINT64_C(`31`);
11708	op <<= `8`;
11709	Value \|= op;
11710	// op: Rt32
11711	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11712	op &= UINT64_C(`31`);
11713	op <<= `16`;
11714	Value \|= op;
11715	// op: Vxx32
11716	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11717	op &= UINT64_C(`31`);
11718	Value \|= op;
11719	break;
11720	}
11721	case Hexagon::V6_vrmpyzbb_rt_acc:
11722	case Hexagon::V6_vrmpyzbub_rt_acc:
11723	case Hexagon::V6_vrmpyzcb_rt_acc:
11724	case Hexagon::V6_vrmpyzcbs_rt_acc:
11725	case Hexagon::V6_vrmpyznb_rt_acc: {
11726	// op: Vu32
11727	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11728	op &= UINT64_C(`31`);
11729	op <<= `8`;
11730	Value \|= op;
11731	// op: Rt8
11732	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11733	op &= UINT64_C(`7`);
11734	op <<= `16`;
11735	Value \|= op;
11736	// op: Vyyyy32
11737	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11738	op &= UINT64_C(`31`);
11739	Value \|= op;
11740	break;
11741	}
11742	case Hexagon::V6_vmpahhsat:
11743	case Hexagon::V6_vmpauhuhsat:
11744	case Hexagon::V6_vmpsuhuhsat: {
11745	// op: Vu32
11746	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11747	op &= UINT64_C(`31`);
11748	op <<= `8`;
11749	Value \|= op;
11750	// op: Rtt32
11751	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11752	op &= UINT64_C(`31`);
11753	op <<= `16`;
11754	Value \|= op;
11755	// op: Vx32
11756	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11757	op &= UINT64_C(`31`);
11758	Value \|= op;
11759	break;
11760	}
11761	case Hexagon::V6_vrmpybub_rtt_acc:
11762	case Hexagon::V6_vrmpyub_rtt_acc: {
11763	// op: Vu32
11764	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11765	op &= UINT64_C(`31`);
11766	op <<= `8`;
11767	Value \|= op;
11768	// op: Rtt32
11769	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11770	op &= UINT64_C(`31`);
11771	op <<= `16`;
11772	Value \|= op;
11773	// op: Vxx32
11774	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11775	op &= UINT64_C(`31`);
11776	Value \|= op;
11777	break;
11778	}
11779	case Hexagon::V6_vrmpyzbb_rx:
11780	case Hexagon::V6_vrmpyzbub_rx:
11781	case Hexagon::V6_vrmpyzcb_rx:
11782	case Hexagon::V6_vrmpyzcbs_rx:
11783	case Hexagon::V6_vrmpyznb_rx: {
11784	// op: Vu32
11785	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11786	op &= UINT64_C(`31`);
11787	op <<= `8`;
11788	Value \|= op;
11789	// op: Vdddd32
11790	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11791	op &= UINT64_C(`31`);
11792	Value \|= op;
11793	// op: Rx8
11794	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11795	op &= UINT64_C(`7`);
11796	op <<= `16`;
11797	Value \|= op;
11798	break;
11799	}
11800	case Hexagon::V6_veqb_and:
11801	case Hexagon::V6_veqb_or:
11802	case Hexagon::V6_veqb_xor:
11803	case Hexagon::V6_veqh_and:
11804	case Hexagon::V6_veqh_or:
11805	case Hexagon::V6_veqh_xor:
11806	case Hexagon::V6_veqw_and:
11807	case Hexagon::V6_veqw_or:
11808	case Hexagon::V6_veqw_xor:
11809	case Hexagon::V6_vgtb_and:
11810	case Hexagon::V6_vgtb_or:
11811	case Hexagon::V6_vgtb_xor:
11812	case Hexagon::V6_vgtbf_and:
11813	case Hexagon::V6_vgtbf_or:
11814	case Hexagon::V6_vgtbf_xor:
11815	case Hexagon::V6_vgth_and:
11816	case Hexagon::V6_vgth_or:
11817	case Hexagon::V6_vgth_xor:
11818	case Hexagon::V6_vgthf_and:
11819	case Hexagon::V6_vgthf_or:
11820	case Hexagon::V6_vgthf_xor:
11821	case Hexagon::V6_vgtsf_and:
11822	case Hexagon::V6_vgtsf_or:
11823	case Hexagon::V6_vgtsf_xor:
11824	case Hexagon::V6_vgtub_and:
11825	case Hexagon::V6_vgtub_or:
11826	case Hexagon::V6_vgtub_xor:
11827	case Hexagon::V6_vgtuh_and:
11828	case Hexagon::V6_vgtuh_or:
11829	case Hexagon::V6_vgtuh_xor:
11830	case Hexagon::V6_vgtuw_and:
11831	case Hexagon::V6_vgtuw_or:
11832	case Hexagon::V6_vgtuw_xor:
11833	case Hexagon::V6_vgtw_and:
11834	case Hexagon::V6_vgtw_or:
11835	case Hexagon::V6_vgtw_xor: {
11836	// op: Vu32
11837	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11838	op &= UINT64_C(`31`);
11839	op <<= `8`;
11840	Value \|= op;
11841	// op: Vv32
11842	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11843	op &= UINT64_C(`31`);
11844	op <<= `16`;
11845	Value \|= op;
11846	// op: Qx4
11847	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11848	op &= UINT64_C(`3`);
11849	Value \|= op;
11850	break;
11851	}
11852	case Hexagon::V6_vaddcarryo:
11853	case Hexagon::V6_vsubcarryo: {
11854	// op: Vu32
11855	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11856	op &= UINT64_C(`31`);
11857	op <<= `8`;
11858	Value \|= op;
11859	// op: Vv32
11860	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11861	op &= UINT64_C(`31`);
11862	op <<= `16`;
11863	Value \|= op;
11864	// op: Vd32
11865	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11866	op &= UINT64_C(`31`);
11867	Value \|= op;
11868	// op: Qe4
11869	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11870	op &= UINT64_C(`3`);
11871	op <<= `5`;
11872	Value \|= op;
11873	break;
11874	}
11875	case Hexagon::V6_vaddcarry:
11876	case Hexagon::V6_vsubcarry: {
11877	// op: Vu32
11878	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11879	op &= UINT64_C(`31`);
11880	op <<= `8`;
11881	Value \|= op;
11882	// op: Vv32
11883	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11884	op &= UINT64_C(`31`);
11885	op <<= `16`;
11886	Value \|= op;
11887	// op: Vd32
11888	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11889	op &= UINT64_C(`31`);
11890	Value \|= op;
11891	// op: Qx4
11892	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
11893	op &= UINT64_C(`3`);
11894	op <<= `5`;
11895	Value \|= op;
11896	break;
11897	}
11898	case Hexagon::V6_vdmpy_sf_hf_acc:
11899	case Hexagon::V6_vdmpyhvsat_acc:
11900	case Hexagon::V6_vmpy_hf_hf_acc:
11901	case Hexagon::V6_vmpyiewh_acc:
11902	case Hexagon::V6_vmpyiewuh_acc:
11903	case Hexagon::V6_vmpyih_acc:
11904	case Hexagon::V6_vmpyowh_rnd_sacc:
11905	case Hexagon::V6_vmpyowh_sacc:
11906	case Hexagon::V6_vrmpybusv_acc:
11907	case Hexagon::V6_vrmpybv_acc:
11908	case Hexagon::V6_vrmpyubv_acc: {
11909	// op: Vu32
11910	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11911	op &= UINT64_C(`31`);
11912	op <<= `8`;
11913	Value \|= op;
11914	// op: Vv32
11915	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11916	op &= UINT64_C(`31`);
11917	op <<= `16`;
11918	Value \|= op;
11919	// op: Vx32
11920	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11921	op &= UINT64_C(`31`);
11922	Value \|= op;
11923	break;
11924	}
11925	case Hexagon::V6_vaddhw_acc:
11926	case Hexagon::V6_vaddubh_acc:
11927	case Hexagon::V6_vadduhw_acc:
11928	case Hexagon::V6_vasr_into:
11929	case Hexagon::V6_vmpy_sf_bf_acc:
11930	case Hexagon::V6_vmpy_sf_hf_acc:
11931	case Hexagon::V6_vmpybusv_acc:
11932	case Hexagon::V6_vmpybv_acc:
11933	case Hexagon::V6_vmpyhus_acc:
11934	case Hexagon::V6_vmpyhv_acc:
11935	case Hexagon::V6_vmpyowh_64_acc:
11936	case Hexagon::V6_vmpyubv_acc:
11937	case Hexagon::V6_vmpyuhv_acc: {
11938	// op: Vu32
11939	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11940	op &= UINT64_C(`31`);
11941	op <<= `8`;
11942	Value \|= op;
11943	// op: Vv32
11944	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11945	op &= UINT64_C(`31`);
11946	op <<= `16`;
11947	Value \|= op;
11948	// op: Vxx32
11949	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11950	op &= UINT64_C(`31`);
11951	Value \|= op;
11952	break;
11953	}
11954	case Hexagon::V6_vlutvvb_oracc: {
11955	// op: Vu32
11956	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11957	op &= UINT64_C(`31`);
11958	op <<= `8`;
11959	Value \|= op;
11960	// op: Vv32
11961	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11962	op &= UINT64_C(`31`);
11963	op <<= `19`;
11964	Value \|= op;
11965	// op: Rt8
11966	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
11967	op &= UINT64_C(`7`);
11968	op <<= `16`;
11969	Value \|= op;
11970	// op: Vx32
11971	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11972	op &= UINT64_C(`31`);
11973	Value \|= op;
11974	break;
11975	}
11976	case Hexagon::V6_vlutvwh_oracc: {
11977	// op: Vu32
11978	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
11979	op &= UINT64_C(`31`);
11980	op <<= `8`;
11981	Value \|= op;
11982	// op: Vv32
11983	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
11984	op &= UINT64_C(`31`);
11985	op <<= `19`;
11986	Value \|= op;
11987	// op: Rt8
11988	op = getMachineOpValue(MI, MO: MI.getOperand(i: `4`), Fixups, STI);
11989	op &= UINT64_C(`7`);
11990	op <<= `16`;
11991	Value \|= op;
11992	// op: Vxx32
11993	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
11994	op &= UINT64_C(`31`);
11995	Value \|= op;
11996	break;
11997	}
11998	case Hexagon::V6_vunpackob:
11999	case Hexagon::V6_vunpackoh: {
12000	// op: Vu32
12001	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12002	op &= UINT64_C(`31`);
12003	op <<= `8`;
12004	Value \|= op;
12005	// op: Vxx32
12006	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12007	op &= UINT64_C(`31`);
12008	Value \|= op;
12009	break;
12010	}
12011	case Hexagon::V6_vrmpyzbb_rx_acc:
12012	case Hexagon::V6_vrmpyzbub_rx_acc:
12013	case Hexagon::V6_vrmpyzcb_rx_acc:
12014	case Hexagon::V6_vrmpyzcbs_rx_acc:
12015	case Hexagon::V6_vrmpyznb_rx_acc: {
12016	// op: Vu32
12017	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
12018	op &= UINT64_C(`31`);
12019	op <<= `8`;
12020	Value \|= op;
12021	// op: Vyyyy32
12022	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12023	op &= UINT64_C(`31`);
12024	Value \|= op;
12025	// op: Rx8
12026	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12027	op &= UINT64_C(`7`);
12028	op <<= `16`;
12029	Value \|= op;
12030	break;
12031	}
12032	case Hexagon::V6_vdmpyhisat:
12033	case Hexagon::V6_vdmpyhsuisat: {
12034	// op: Vuu32
12035	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12036	op &= UINT64_C(`31`);
12037	op <<= `8`;
12038	Value \|= op;
12039	// op: Rt32
12040	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12041	op &= UINT64_C(`31`);
12042	op <<= `16`;
12043	Value \|= op;
12044	// op: Vd32
12045	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12046	op &= UINT64_C(`31`);
12047	Value \|= op;
12048	break;
12049	}
12050	case Hexagon::V6_vdmpybus_dv:
12051	case Hexagon::V6_vdmpyhb_dv:
12052	case Hexagon::V6_vdsaduh:
12053	case Hexagon::V6_vmpabus:
12054	case Hexagon::V6_vmpabuu:
12055	case Hexagon::V6_vmpahb:
12056	case Hexagon::V6_vmpauhb:
12057	case Hexagon::V6_vtmpyb:
12058	case Hexagon::V6_vtmpybus:
12059	case Hexagon::V6_vtmpyhb: {
12060	// op: Vuu32
12061	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12062	op &= UINT64_C(`31`);
12063	op <<= `8`;
12064	Value \|= op;
12065	// op: Rt32
12066	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12067	op &= UINT64_C(`31`);
12068	op <<= `16`;
12069	Value \|= op;
12070	// op: Vdd32
12071	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12072	op &= UINT64_C(`31`);
12073	Value \|= op;
12074	break;
12075	}
12076	case Hexagon::V6_vconv_hf_qf32: {
12077	// op: Vuu32
12078	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12079	op &= UINT64_C(`31`);
12080	op <<= `8`;
12081	Value \|= op;
12082	// op: Vd32
12083	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12084	op &= UINT64_C(`31`);
12085	Value \|= op;
12086	break;
12087	}
12088	case Hexagon::V6_vasrvuhubrndsat:
12089	case Hexagon::V6_vasrvuhubsat:
12090	case Hexagon::V6_vasrvwuhrndsat:
12091	case Hexagon::V6_vasrvwuhsat: {
12092	// op: Vuu32
12093	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12094	op &= UINT64_C(`31`);
12095	op <<= `8`;
12096	Value \|= op;
12097	// op: Vv32
12098	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12099	op &= UINT64_C(`31`);
12100	op <<= `16`;
12101	Value \|= op;
12102	// op: Vd32
12103	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12104	op &= UINT64_C(`31`);
12105	Value \|= op;
12106	break;
12107	}
12108	case Hexagon::V6_vaddb_dv:
12109	case Hexagon::V6_vaddbsat_dv:
12110	case Hexagon::V6_vaddh_dv:
12111	case Hexagon::V6_vaddhsat_dv:
12112	case Hexagon::V6_vaddubsat_dv:
12113	case Hexagon::V6_vadduhsat_dv:
12114	case Hexagon::V6_vadduwsat_dv:
12115	case Hexagon::V6_vaddw_dv:
12116	case Hexagon::V6_vaddwsat_dv:
12117	case Hexagon::V6_vmpabusv:
12118	case Hexagon::V6_vmpabuuv:
12119	case Hexagon::V6_vsubb_dv:
12120	case Hexagon::V6_vsubbsat_dv:
12121	case Hexagon::V6_vsubh_dv:
12122	case Hexagon::V6_vsubhsat_dv:
12123	case Hexagon::V6_vsububsat_dv:
12124	case Hexagon::V6_vsubuhsat_dv:
12125	case Hexagon::V6_vsubuwsat_dv:
12126	case Hexagon::V6_vsubw_dv:
12127	case Hexagon::V6_vsubwsat_dv: {
12128	// op: Vuu32
12129	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12130	op &= UINT64_C(`31`);
12131	op <<= `8`;
12132	Value \|= op;
12133	// op: Vvv32
12134	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12135	op &= UINT64_C(`31`);
12136	op <<= `16`;
12137	Value \|= op;
12138	// op: Vdd32
12139	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12140	op &= UINT64_C(`31`);
12141	Value \|= op;
12142	break;
12143	}
12144	case Hexagon::V6_vdmpyhisat_acc:
12145	case Hexagon::V6_vdmpyhsuisat_acc: {
12146	// op: Vuu32
12147	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12148	op &= UINT64_C(`31`);
12149	op <<= `8`;
12150	Value \|= op;
12151	// op: Rt32
12152	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
12153	op &= UINT64_C(`31`);
12154	op <<= `16`;
12155	Value \|= op;
12156	// op: Vx32
12157	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12158	op &= UINT64_C(`31`);
12159	Value \|= op;
12160	break;
12161	}
12162	case Hexagon::V6_vdmpybus_dv_acc:
12163	case Hexagon::V6_vdmpyhb_dv_acc:
12164	case Hexagon::V6_vdsaduh_acc:
12165	case Hexagon::V6_vmpabus_acc:
12166	case Hexagon::V6_vmpabuu_acc:
12167	case Hexagon::V6_vmpahb_acc:
12168	case Hexagon::V6_vmpauhb_acc:
12169	case Hexagon::V6_vtmpyb_acc:
12170	case Hexagon::V6_vtmpybus_acc:
12171	case Hexagon::V6_vtmpyhb_acc: {
12172	// op: Vuu32
12173	op = getMachineOpValue(MI, MO: MI.getOperand(i: `2`), Fixups, STI);
12174	op &= UINT64_C(`31`);
12175	op <<= `8`;
12176	Value \|= op;
12177	// op: Rt32
12178	op = getMachineOpValue(MI, MO: MI.getOperand(i: `3`), Fixups, STI);
12179	op &= UINT64_C(`31`);
12180	op <<= `16`;
12181	Value \|= op;
12182	// op: Vxx32
12183	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12184	op &= UINT64_C(`31`);
12185	Value \|= op;
12186	break;
12187	}
12188	case Hexagon::CALLProfile:
12189	case Hexagon::PS_call_stk:
12190	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
12191	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
12192	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
12193	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
12194	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
12195	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
12196	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
12197	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
12198	case Hexagon::SAVE_REGISTERS_CALL_V4:
12199	case Hexagon::SAVE_REGISTERS_CALL_V4STK:
12200	case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
12201	case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
12202	case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
12203	case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
12204	case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
12205	case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
12206	// op: dst
12207	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12208	Value \|= (op & UINT64_C(`16744448`)) << `1`;
12209	Value \|= (op & UINT64_C(`32764`)) >> `1`;
12210	break;
12211	}
12212	case Hexagon::EH_RETURN_JMPR:
12213	case Hexagon::PS_jmpret: {
12214	// op: dst
12215	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12216	op &= UINT64_C(`31`);
12217	op <<= `16`;
12218	Value \|= op;
12219	break;
12220	}
12221	case Hexagon::HI:
12222	case Hexagon::LO: {
12223	// op: dst
12224	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12225	op &= UINT64_C(`31`);
12226	op <<= `16`;
12227	Value \|= op;
12228	// op: imm_value
12229	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12230	Value \|= (op & UINT64_C(`49152`)) << `8`;
12231	Value \|= (op & UINT64_C(`16383`));
12232	break;
12233	}
12234	case Hexagon::J2_loop0iext:
12235	case Hexagon::J2_loop1iext: {
12236	// op: offset
12237	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12238	Value \|= (op & UINT64_C(`496`)) << `4`;
12239	Value \|= (op & UINT64_C(`12`)) << `1`;
12240	// op: src2
12241	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12242	Value \|= (op & UINT64_C(`992`)) << `11`;
12243	Value \|= (op & UINT64_C(`28`)) << `3`;
12244	Value \|= (op & UINT64_C(`3`));
12245	break;
12246	}
12247	case Hexagon::J2_loop0rext:
12248	case Hexagon::J2_loop1rext: {
12249	// op: offset
12250	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12251	Value \|= (op & UINT64_C(`496`)) << `4`;
12252	Value \|= (op & UINT64_C(`12`)) << `1`;
12253	// op: src2
12254	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12255	op &= UINT64_C(`31`);
12256	op <<= `16`;
12257	Value \|= op;
12258	break;
12259	}
12260	case Hexagon::PS_jmpretf:
12261	case Hexagon::PS_jmpretfnew:
12262	case Hexagon::PS_jmpretfnewpt:
12263	case Hexagon::PS_jmprett:
12264	case Hexagon::PS_jmprettnew:
12265	case Hexagon::PS_jmprettnewpt: {
12266	// op: src
12267	op = getMachineOpValue(MI, MO: MI.getOperand(i: `0`), Fixups, STI);
12268	op &= UINT64_C(`3`);
12269	op <<= `8`;
12270	Value \|= op;
12271	// op: dst
12272	op = getMachineOpValue(MI, MO: MI.getOperand(i: `1`), Fixups, STI);
12273	op &= UINT64_C(`31`);
12274	op <<= `16`;
12275	Value \|= op;
12276	break;
12277	}
12278	default:
12279	std::string msg;
12280	raw_string_ostream Msg(msg);
12281	Msg << "Not supported instr: " << MI;
12282	report_fatal_error(reason: Msg.str().c_str());
12283	}
12284	return Value;
12285	}
12286
12287	#ifdef GET_OPERAND_BIT_OFFSET
12288	#undef GET_OPERAND_BIT_OFFSET
12289
12290	uint32_t HexagonMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
12291	unsigned OpNum,
12292	const MCSubtargetInfo &STI) const {
12293	switch (MI.getOpcode()) {
12294	case Hexagon::A2_nop:
12295	case Hexagon::CONST32:
12296	case Hexagon::CONST64:
12297	case Hexagon::DuplexIClass0:
12298	case Hexagon::DuplexIClass1:
12299	case Hexagon::DuplexIClass2:
12300	case Hexagon::DuplexIClass3:
12301	case Hexagon::DuplexIClass4:
12302	case Hexagon::DuplexIClass5:
12303	case Hexagon::DuplexIClass6:
12304	case Hexagon::DuplexIClass7:
12305	case Hexagon::DuplexIClass8:
12306	case Hexagon::DuplexIClass9:
12307	case Hexagon::DuplexIClassA:
12308	case Hexagon::DuplexIClassB:
12309	case Hexagon::DuplexIClassC:
12310	case Hexagon::DuplexIClassD:
12311	case Hexagon::DuplexIClassE:
12312	case Hexagon::DuplexIClassF:
12313	case Hexagon::J2_rte:
12314	case Hexagon::J2_unpause:
12315	case Hexagon::SL2_deallocframe:
12316	case Hexagon::SL2_jumpr31:
12317	case Hexagon::SL2_jumpr31_f:
12318	case Hexagon::SL2_jumpr31_fnew:
12319	case Hexagon::SL2_jumpr31_t:
12320	case Hexagon::SL2_jumpr31_tnew:
12321	case Hexagon::SL2_return:
12322	case Hexagon::SL2_return_f:
12323	case Hexagon::SL2_return_fnew:
12324	case Hexagon::SL2_return_t:
12325	case Hexagon::SL2_return_tnew:
12326	case Hexagon::TFRI64_V2_ext:
12327	case Hexagon::TFRI64_V4:
12328	case Hexagon::V6_vhist:
12329	case Hexagon::V6_vwhist128:
12330	case Hexagon::V6_vwhist256:
12331	case Hexagon::V6_vwhist256_sat:
12332	case Hexagon::Y2_barrier:
12333	case Hexagon::Y2_break:
12334	case Hexagon::Y2_dckill:
12335	case Hexagon::Y2_ickill:
12336	case Hexagon::Y2_isync:
12337	case Hexagon::Y2_k0lock:
12338	case Hexagon::Y2_k0unlock:
12339	case Hexagon::Y2_l2kill:
12340	case Hexagon::Y2_syncht:
12341	case Hexagon::Y2_tlblock:
12342	case Hexagon::Y2_tlbunlock:
12343	case Hexagon::Y5_l2gclean:
12344	case Hexagon::Y5_l2gcleaninv:
12345	case Hexagon::Y5_l2gunlock:
12346	case Hexagon::invalid_decode: {
12347	break;
12348	}
12349	case Hexagon::PS_storerbnewabs:
12350	case Hexagon::PS_storerhnewabs:
12351	case Hexagon::PS_storerinewabs:
12352	case Hexagon::S2_storerbnewgp:
12353	case Hexagon::S2_storerhnewgp:
12354	case Hexagon::S2_storerinewgp: {
12355	switch (OpNum) {
12356	case `0`:
12357	// op: Ii
12358	return `0`;
12359	case `1`:
12360	// op: Nt8
12361	return `8`;
12362	}
12363	break;
12364	}
12365	case Hexagon::PS_storerbabs:
12366	case Hexagon::PS_storerfabs:
12367	case Hexagon::PS_storerhabs:
12368	case Hexagon::PS_storeriabs:
12369	case Hexagon::S2_storerbgp:
12370	case Hexagon::S2_storerfgp:
12371	case Hexagon::S2_storerhgp:
12372	case Hexagon::S2_storerigp: {
12373	switch (OpNum) {
12374	case `0`:
12375	// op: Ii
12376	return `0`;
12377	case `1`:
12378	// op: Rt32
12379	return `8`;
12380	}
12381	break;
12382	}
12383	case Hexagon::PS_storerdabs:
12384	case Hexagon::S2_storerdgp: {
12385	switch (OpNum) {
12386	case `0`:
12387	// op: Ii
12388	return `0`;
12389	case `1`:
12390	// op: Rtt32
12391	return `8`;
12392	}
12393	break;
12394	}
12395	case Hexagon::A4_ext: {
12396	switch (OpNum) {
12397	case `0`:
12398	// op: Ii
12399	return `0`;
12400	}
12401	break;
12402	}
12403	case Hexagon::J2_call:
12404	case Hexagon::J2_jump: {
12405	switch (OpNum) {
12406	case `0`:
12407	// op: Ii
12408	return `1`;
12409	}
12410	break;
12411	}
12412	case Hexagon::J2_pause:
12413	case Hexagon::J2_trap0:
12414	case Hexagon::PS_trap1: {
12415	switch (OpNum) {
12416	case `0`:
12417	// op: Ii
12418	return `2`;
12419	}
12420	break;
12421	}
12422	case Hexagon::J2_loop0i:
12423	case Hexagon::J2_loop1i:
12424	case Hexagon::J2_ploop1si:
12425	case Hexagon::J2_ploop2si:
12426	case Hexagon::J2_ploop3si: {
12427	switch (OpNum) {
12428	case `0`:
12429	// op: Ii
12430	return `3`;
12431	case `1`:
12432	// op: II
12433	return `0`;
12434	}
12435	break;
12436	}
12437	case Hexagon::J2_loop0r:
12438	case Hexagon::J2_loop1r:
12439	case Hexagon::J2_ploop1sr:
12440	case Hexagon::J2_ploop2sr:
12441	case Hexagon::J2_ploop3sr: {
12442	switch (OpNum) {
12443	case `0`:
12444	// op: Ii
12445	return `3`;
12446	case `1`:
12447	// op: Rs32
12448	return `16`;
12449	}
12450	break;
12451	}
12452	case Hexagon::SS2_stored_sp: {
12453	switch (OpNum) {
12454	case `0`:
12455	// op: Ii
12456	return `3`;
12457	case `1`:
12458	// op: Rtt8
12459	return `0`;
12460	}
12461	break;
12462	}
12463	case Hexagon::SS2_storew_sp: {
12464	switch (OpNum) {
12465	case `0`:
12466	// op: Ii
12467	return `4`;
12468	case `1`:
12469	// op: Rt16
12470	return `0`;
12471	}
12472	break;
12473	}
12474	case Hexagon::SS2_allocframe: {
12475	switch (OpNum) {
12476	case `0`:
12477	// op: Ii
12478	return `4`;
12479	}
12480	break;
12481	}
12482	case Hexagon::V6_vwhist128m: {
12483	switch (OpNum) {
12484	case `0`:
12485	// op: Ii
12486	return `8`;
12487	}
12488	break;
12489	}
12490	case Hexagon::Y2_setimask:
12491	case Hexagon::Y2_setprio: {
12492	switch (OpNum) {
12493	case `0`:
12494	// op: Pt4
12495	return `8`;
12496	case `1`:
12497	// op: Rs32
12498	return `16`;
12499	}
12500	break;
12501	}
12502	case Hexagon::J2_callrf:
12503	case Hexagon::J2_callrt:
12504	case Hexagon::J2_jumprf:
12505	case Hexagon::J2_jumprfnew:
12506	case Hexagon::J2_jumprfnewpt:
12507	case Hexagon::J2_jumprfpt:
12508	case Hexagon::J2_jumprt:
12509	case Hexagon::J2_jumprtnew:
12510	case Hexagon::J2_jumprtnewpt:
12511	case Hexagon::J2_jumprtpt: {
12512	switch (OpNum) {
12513	case `0`:
12514	// op: Pu4
12515	return `8`;
12516	case `1`:
12517	// op: Rs32
12518	return `16`;
12519	}
12520	break;
12521	}
12522	case Hexagon::V6_vgathermhq:
12523	case Hexagon::V6_vgathermwq: {
12524	switch (OpNum) {
12525	case `0`:
12526	// op: Qs4
12527	return `5`;
12528	case `1`:
12529	// op: Rt32
12530	return `16`;
12531	case `2`:
12532	// op: Mu2
12533	return `13`;
12534	case `3`:
12535	// op: Vv32
12536	return `0`;
12537	}
12538	break;
12539	}
12540	case Hexagon::V6_vscattermhq:
12541	case Hexagon::V6_vscattermwq: {
12542	switch (OpNum) {
12543	case `0`:
12544	// op: Qs4
12545	return `5`;
12546	case `1`:
12547	// op: Rt32
12548	return `16`;
12549	case `2`:
12550	// op: Mu2
12551	return `13`;
12552	case `3`:
12553	// op: Vv32
12554	return `8`;
12555	case `4`:
12556	// op: Vw32
12557	return `0`;
12558	}
12559	break;
12560	}
12561	case Hexagon::V6_vgathermhwq: {
12562	switch (OpNum) {
12563	case `0`:
12564	// op: Qs4
12565	return `5`;
12566	case `1`:
12567	// op: Rt32
12568	return `16`;
12569	case `2`:
12570	// op: Mu2
12571	return `13`;
12572	case `3`:
12573	// op: Vvv32
12574	return `0`;
12575	}
12576	break;
12577	}
12578	case Hexagon::V6_vscattermhwq: {
12579	switch (OpNum) {
12580	case `0`:
12581	// op: Qs4
12582	return `5`;
12583	case `1`:
12584	// op: Rt32
12585	return `16`;
12586	case `2`:
12587	// op: Mu2
12588	return `13`;
12589	case `3`:
12590	// op: Vvv32
12591	return `8`;
12592	case `4`:
12593	// op: Vw32
12594	return `0`;
12595	}
12596	break;
12597	}
12598	case Hexagon::V6_vhistq:
12599	case Hexagon::V6_vwhist128q:
12600	case Hexagon::V6_vwhist256q:
12601	case Hexagon::V6_vwhist256q_sat: {
12602	switch (OpNum) {
12603	case `0`:
12604	// op: Qv4
12605	return `22`;
12606	}
12607	break;
12608	}
12609	case Hexagon::SA1_clrf:
12610	case Hexagon::SA1_clrfnew:
12611	case Hexagon::SA1_clrt:
12612	case Hexagon::SA1_clrtnew:
12613	case Hexagon::SA1_setin1: {
12614	switch (OpNum) {
12615	case `0`:
12616	// op: Rd16
12617	return `0`;
12618	}
12619	break;
12620	}
12621	case Hexagon::Y6_dmpause:
12622	case Hexagon::Y6_dmpoll:
12623	case Hexagon::Y6_dmwait: {
12624	switch (OpNum) {
12625	case `0`:
12626	// op: Rd32
12627	return `0`;
12628	}
12629	break;
12630	}
12631	case Hexagon::PS_callr_nr: {
12632	switch (OpNum) {
12633	case `0`:
12634	// op: Rs
12635	return `16`;
12636	}
12637	break;
12638	}
12639	case Hexagon::L6_memcpy: {
12640	switch (OpNum) {
12641	case `0`:
12642	// op: Rs32
12643	return `16`;
12644	case `1`:
12645	// op: Rt32
12646	return `8`;
12647	case `2`:
12648	// op: Mu2
12649	return `13`;
12650	}
12651	break;
12652	}
12653	case Hexagon::S2_storew_rl_at_vi:
12654	case Hexagon::S2_storew_rl_st_vi:
12655	case Hexagon::Y2_dctagw:
12656	case Hexagon::Y2_icdataw:
12657	case Hexagon::Y2_ictagw:
12658	case Hexagon::Y4_l2fetch:
12659	case Hexagon::Y4_l2tagw:
12660	case Hexagon::Y6_dmlink: {
12661	switch (OpNum) {
12662	case `0`:
12663	// op: Rs32
12664	return `16`;
12665	case `1`:
12666	// op: Rt32
12667	return `8`;
12668	}
12669	break;
12670	}
12671	case Hexagon::S4_stored_rl_at_vi:
12672	case Hexagon::S4_stored_rl_st_vi:
12673	case Hexagon::Y5_l2fetch: {
12674	switch (OpNum) {
12675	case `0`:
12676	// op: Rs32
12677	return `16`;
12678	case `1`:
12679	// op: Rtt32
12680	return `8`;
12681	}
12682	break;
12683	}
12684	case Hexagon::J2_callr:
12685	case Hexagon::J2_callrh:
12686	case Hexagon::J2_jumpr:
12687	case Hexagon::J2_jumprh:
12688	case Hexagon::J4_hintjumpr:
12689	case Hexagon::R6_release_at_vi:
12690	case Hexagon::R6_release_st_vi:
12691	case Hexagon::Y2_ciad:
12692	case Hexagon::Y2_cswi:
12693	case Hexagon::Y2_dccleana:
12694	case Hexagon::Y2_dccleanidx:
12695	case Hexagon::Y2_dccleaninva:
12696	case Hexagon::Y2_dccleaninvidx:
12697	case Hexagon::Y2_dcinva:
12698	case Hexagon::Y2_dcinvidx:
12699	case Hexagon::Y2_dczeroa:
12700	case Hexagon::Y2_iassignw:
12701	case Hexagon::Y2_icinva:
12702	case Hexagon::Y2_icinvidx:
12703	case Hexagon::Y2_l2cleaninvidx:
12704	case Hexagon::Y2_resume:
12705	case Hexagon::Y2_start:
12706	case Hexagon::Y2_stop:
12707	case Hexagon::Y2_swi:
12708	case Hexagon::Y2_wait:
12709	case Hexagon::Y4_nmi:
12710	case Hexagon::Y4_siad:
12711	case Hexagon::Y4_trace:
12712	case Hexagon::Y5_l2cleanidx:
12713	case Hexagon::Y5_l2invidx:
12714	case Hexagon::Y5_l2unlocka:
12715	case Hexagon::Y5_tlbasidi:
12716	case Hexagon::Y6_diag:
12717	case Hexagon::Y6_dmresume:
12718	case Hexagon::Y6_dmstart: {
12719	switch (OpNum) {
12720	case `0`:
12721	// op: Rs32
12722	return `16`;
12723	}
12724	break;
12725	}
12726	case Hexagon::Y2_tlbw: {
12727	switch (OpNum) {
12728	case `0`:
12729	// op: Rss32
12730	return `16`;
12731	case `1`:
12732	// op: Rt32
12733	return `8`;
12734	}
12735	break;
12736	}
12737	case Hexagon::Y6_diag0:
12738	case Hexagon::Y6_diag1: {
12739	switch (OpNum) {
12740	case `0`:
12741	// op: Rss32
12742	return `16`;
12743	case `1`:
12744	// op: Rtt32
12745	return `8`;
12746	}
12747	break;
12748	}
12749	case Hexagon::V6_vgathermh:
12750	case Hexagon::V6_vgathermw: {
12751	switch (OpNum) {
12752	case `0`:
12753	// op: Rt32
12754	return `16`;
12755	case `1`:
12756	// op: Mu2
12757	return `13`;
12758	case `2`:
12759	// op: Vv32
12760	return `0`;
12761	}
12762	break;
12763	}
12764	case Hexagon::V6_vscattermh:
12765	case Hexagon::V6_vscattermh_add:
12766	case Hexagon::V6_vscattermw:
12767	case Hexagon::V6_vscattermw_add: {
12768	switch (OpNum) {
12769	case `0`:
12770	// op: Rt32
12771	return `16`;
12772	case `1`:
12773	// op: Mu2
12774	return `13`;
12775	case `2`:
12776	// op: Vv32
12777	return `8`;
12778	case `3`:
12779	// op: Vw32
12780	return `0`;
12781	}
12782	break;
12783	}
12784	case Hexagon::V6_vgathermhw: {
12785	switch (OpNum) {
12786	case `0`:
12787	// op: Rt32
12788	return `16`;
12789	case `1`:
12790	// op: Mu2
12791	return `13`;
12792	case `2`:
12793	// op: Vvv32
12794	return `0`;
12795	}
12796	break;
12797	}
12798	case Hexagon::V6_vscattermhw:
12799	case Hexagon::V6_vscattermhw_add: {
12800	switch (OpNum) {
12801	case `0`:
12802	// op: Rt32
12803	return `16`;
12804	case `1`:
12805	// op: Mu2
12806	return `13`;
12807	case `2`:
12808	// op: Vvv32
12809	return `8`;
12810	case `3`:
12811	// op: Vw32
12812	return `0`;
12813	}
12814	break;
12815	}
12816	case Hexagon::Y6_l2gcleaninvpa:
12817	case Hexagon::Y6_l2gcleanpa: {
12818	switch (OpNum) {
12819	case `0`:
12820	// op: Rtt32
12821	return `8`;
12822	}
12823	break;
12824	}
12825	case Hexagon::Y2_crswap0:
12826	case Hexagon::Y4_crswap1: {
12827	switch (OpNum) {
12828	case `0`:
12829	// op: Rx32
12830	return `16`;
12831	}
12832	break;
12833	}
12834	case Hexagon::Y4_crswap10: {
12835	switch (OpNum) {
12836	case `0`:
12837	// op: Rxx32
12838	return `16`;
12839	}
12840	break;
12841	}
12842	case Hexagon::HI:
12843	case Hexagon::LO: {
12844	switch (OpNum) {
12845	case `0`:
12846	// op: dst
12847	return `16`;
12848	case `1`:
12849	// op: imm_value
12850	return `0`;
12851	}
12852	break;
12853	}
12854	case Hexagon::EH_RETURN_JMPR:
12855	case Hexagon::PS_jmpret: {
12856	switch (OpNum) {
12857	case `0`:
12858	// op: dst
12859	return `16`;
12860	}
12861	break;
12862	}
12863	case Hexagon::CALLProfile:
12864	case Hexagon::PS_call_stk:
12865	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
12866	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
12867	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
12868	case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
12869	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
12870	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
12871	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
12872	case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
12873	case Hexagon::SAVE_REGISTERS_CALL_V4:
12874	case Hexagon::SAVE_REGISTERS_CALL_V4STK:
12875	case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
12876	case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
12877	case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
12878	case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
12879	case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
12880	case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
12881	switch (OpNum) {
12882	case `0`:
12883	// op: dst
12884	return `1`;
12885	}
12886	break;
12887	}
12888	case Hexagon::J2_loop0iext:
12889	case Hexagon::J2_loop1iext: {
12890	switch (OpNum) {
12891	case `0`:
12892	// op: offset
12893	return `3`;
12894	case `1`:
12895	// op: src2
12896	return `0`;
12897	}
12898	break;
12899	}
12900	case Hexagon::J2_loop0rext:
12901	case Hexagon::J2_loop1rext: {
12902	switch (OpNum) {
12903	case `0`:
12904	// op: offset
12905	return `3`;
12906	case `1`:
12907	// op: src2
12908	return `16`;
12909	}
12910	break;
12911	}
12912	case Hexagon::PS_jmpretf:
12913	case Hexagon::PS_jmpretfnew:
12914	case Hexagon::PS_jmpretfnewpt:
12915	case Hexagon::PS_jmprett:
12916	case Hexagon::PS_jmprettnew:
12917	case Hexagon::PS_jmprettnewpt: {
12918	switch (OpNum) {
12919	case `0`:
12920	// op: src
12921	return `8`;
12922	case `1`:
12923	// op: dst
12924	return `16`;
12925	}
12926	break;
12927	}
12928	case Hexagon::A2_tfrcrr: {
12929	switch (OpNum) {
12930	case `1`:
12931	// op: Cs32
12932	return `16`;
12933	case `0`:
12934	// op: Rd32
12935	return `0`;
12936	}
12937	break;
12938	}
12939	case Hexagon::A4_tfrcpp: {
12940	switch (OpNum) {
12941	case `1`:
12942	// op: Css32
12943	return `16`;
12944	case `0`:
12945	// op: Rdd32
12946	return `0`;
12947	}
12948	break;
12949	}
12950	case Hexagon::G4_tfrgcrr: {
12951	switch (OpNum) {
12952	case `1`:
12953	// op: Gs32
12954	return `16`;
12955	case `0`:
12956	// op: Rd32
12957	return `0`;
12958	}
12959	break;
12960	}
12961	case Hexagon::G4_tfrgcpp: {
12962	switch (OpNum) {
12963	case `1`:
12964	// op: Gss32
12965	return `16`;
12966	case `0`:
12967	// op: Rdd32
12968	return `0`;
12969	}
12970	break;
12971	}
12972	case Hexagon::S4_storerbnew_ap:
12973	case Hexagon::S4_storerhnew_ap:
12974	case Hexagon::S4_storerinew_ap: {
12975	switch (OpNum) {
12976	case `1`:
12977	// op: II
12978	return `0`;
12979	case `2`:
12980	// op: Nt8
12981	return `8`;
12982	case `0`:
12983	// op: Re32
12984	return `16`;
12985	}
12986	break;
12987	}
12988	case Hexagon::S4_storerb_ap:
12989	case Hexagon::S4_storerf_ap:
12990	case Hexagon::S4_storerh_ap:
12991	case Hexagon::S4_storeri_ap: {
12992	switch (OpNum) {
12993	case `1`:
12994	// op: II
12995	return `0`;
12996	case `2`:
12997	// op: Rt32
12998	return `8`;
12999	case `0`:
13000	// op: Re32
13001	return `16`;
13002	}
13003	break;
13004	}
13005	case Hexagon::S4_storerd_ap: {
13006	switch (OpNum) {
13007	case `1`:
13008	// op: II
13009	return `0`;
13010	case `2`:
13011	// op: Rtt32
13012	return `8`;
13013	case `0`:
13014	// op: Re32
13015	return `16`;
13016	}
13017	break;
13018	}
13019	case Hexagon::J4_cmpeqi_f_jumpnv_nt:
13020	case Hexagon::J4_cmpeqi_f_jumpnv_t:
13021	case Hexagon::J4_cmpeqi_t_jumpnv_nt:
13022	case Hexagon::J4_cmpeqi_t_jumpnv_t:
13023	case Hexagon::J4_cmpgti_f_jumpnv_nt:
13024	case Hexagon::J4_cmpgti_f_jumpnv_t:
13025	case Hexagon::J4_cmpgti_t_jumpnv_nt:
13026	case Hexagon::J4_cmpgti_t_jumpnv_t:
13027	case Hexagon::J4_cmpgtui_f_jumpnv_nt:
13028	case Hexagon::J4_cmpgtui_f_jumpnv_t:
13029	case Hexagon::J4_cmpgtui_t_jumpnv_nt:
13030	case Hexagon::J4_cmpgtui_t_jumpnv_t: {
13031	switch (OpNum) {
13032	case `1`:
13033	// op: II
13034	return `8`;
13035	case `2`:
13036	// op: Ii
13037	return `1`;
13038	case `0`:
13039	// op: Ns8
13040	return `16`;
13041	}
13042	break;
13043	}
13044	case Hexagon::J4_jumpseti: {
13045	switch (OpNum) {
13046	case `1`:
13047	// op: II
13048	return `8`;
13049	case `2`:
13050	// op: Ii
13051	return `1`;
13052	case `0`:
13053	// op: Rd16
13054	return `16`;
13055	}
13056	break;
13057	}
13058	case Hexagon::J4_cmpeqi_fp0_jump_nt:
13059	case Hexagon::J4_cmpeqi_fp0_jump_t:
13060	case Hexagon::J4_cmpeqi_fp1_jump_nt:
13061	case Hexagon::J4_cmpeqi_fp1_jump_t:
13062	case Hexagon::J4_cmpeqi_tp0_jump_nt:
13063	case Hexagon::J4_cmpeqi_tp0_jump_t:
13064	case Hexagon::J4_cmpeqi_tp1_jump_nt:
13065	case Hexagon::J4_cmpeqi_tp1_jump_t:
13066	case Hexagon::J4_cmpgti_fp0_jump_nt:
13067	case Hexagon::J4_cmpgti_fp0_jump_t:
13068	case Hexagon::J4_cmpgti_fp1_jump_nt:
13069	case Hexagon::J4_cmpgti_fp1_jump_t:
13070	case Hexagon::J4_cmpgti_tp0_jump_nt:
13071	case Hexagon::J4_cmpgti_tp0_jump_t:
13072	case Hexagon::J4_cmpgti_tp1_jump_nt:
13073	case Hexagon::J4_cmpgti_tp1_jump_t:
13074	case Hexagon::J4_cmpgtui_fp0_jump_nt:
13075	case Hexagon::J4_cmpgtui_fp0_jump_t:
13076	case Hexagon::J4_cmpgtui_fp1_jump_nt:
13077	case Hexagon::J4_cmpgtui_fp1_jump_t:
13078	case Hexagon::J4_cmpgtui_tp0_jump_nt:
13079	case Hexagon::J4_cmpgtui_tp0_jump_t:
13080	case Hexagon::J4_cmpgtui_tp1_jump_nt:
13081	case Hexagon::J4_cmpgtui_tp1_jump_t: {
13082	switch (OpNum) {
13083	case `1`:
13084	// op: II
13085	return `8`;
13086	case `2`:
13087	// op: Ii
13088	return `1`;
13089	case `0`:
13090	// op: Rs16
13091	return `16`;
13092	}
13093	break;
13094	}
13095	case Hexagon::SA1_cmpeqi:
13096	case Hexagon::SS2_storebi0:
13097	case Hexagon::SS2_storebi1:
13098	case Hexagon::SS2_storewi0:
13099	case Hexagon::SS2_storewi1: {
13100	switch (OpNum) {
13101	case `1`:
13102	// op: Ii
13103	return `0`;
13104	case `0`:
13105	// op: Rs16
13106	return `4`;
13107	}
13108	break;
13109	}
13110	case Hexagon::S2_storerbnew_io:
13111	case Hexagon::S2_storerhnew_io:
13112	case Hexagon::S2_storerinew_io: {
13113	switch (OpNum) {
13114	case `1`:
13115	// op: Ii
13116	return `0`;
13117	case `0`:
13118	// op: Rs32
13119	return `16`;
13120	case `2`:
13121	// op: Nt8
13122	return `8`;
13123	}
13124	break;
13125	}
13126	case Hexagon::S2_storerb_io:
13127	case Hexagon::S2_storerf_io:
13128	case Hexagon::S2_storerh_io:
13129	case Hexagon::S2_storeri_io: {
13130	switch (OpNum) {
13131	case `1`:
13132	// op: Ii
13133	return `0`;
13134	case `0`:
13135	// op: Rs32
13136	return `16`;
13137	case `2`:
13138	// op: Rt32
13139	return `8`;
13140	}
13141	break;
13142	}
13143	case Hexagon::S2_storerd_io: {
13144	switch (OpNum) {
13145	case `1`:
13146	// op: Ii
13147	return `0`;
13148	case `0`:
13149	// op: Rs32
13150	return `16`;
13151	case `2`:
13152	// op: Rtt32
13153	return `8`;
13154	}
13155	break;
13156	}
13157	case Hexagon::Y2_dcfetchbo: {
13158	switch (OpNum) {
13159	case `1`:
13160	// op: Ii
13161	return `0`;
13162	case `0`:
13163	// op: Rs32
13164	return `16`;
13165	}
13166	break;
13167	}
13168	case Hexagon::J4_tstbit0_f_jumpnv_nt:
13169	case Hexagon::J4_tstbit0_f_jumpnv_t:
13170	case Hexagon::J4_tstbit0_t_jumpnv_nt:
13171	case Hexagon::J4_tstbit0_t_jumpnv_t: {
13172	switch (OpNum) {
13173	case `1`:
13174	// op: Ii
13175	return `1`;
13176	case `0`:
13177	// op: Ns8
13178	return `16`;
13179	}
13180	break;
13181	}
13182	case Hexagon::J2_callf:
13183	case Hexagon::J2_callt:
13184	case Hexagon::J2_jumpf:
13185	case Hexagon::J2_jumpfnew:
13186	case Hexagon::J2_jumpfnewpt:
13187	case Hexagon::J2_jumpfpt:
13188	case Hexagon::J2_jumpt:
13189	case Hexagon::J2_jumptnew:
13190	case Hexagon::J2_jumptnewpt:
13191	case Hexagon::J2_jumptpt: {
13192	switch (OpNum) {
13193	case `1`:
13194	// op: Ii
13195	return `1`;
13196	case `0`:
13197	// op: Pu4
13198	return `8`;
13199	}
13200	break;
13201	}
13202	case Hexagon::J4_tstbit0_fp0_jump_nt:
13203	case Hexagon::J4_tstbit0_fp0_jump_t:
13204	case Hexagon::J4_tstbit0_fp1_jump_nt:
13205	case Hexagon::J4_tstbit0_fp1_jump_t:
13206	case Hexagon::J4_tstbit0_tp0_jump_nt:
13207	case Hexagon::J4_tstbit0_tp0_jump_t:
13208	case Hexagon::J4_tstbit0_tp1_jump_nt:
13209	case Hexagon::J4_tstbit0_tp1_jump_t: {
13210	switch (OpNum) {
13211	case `1`:
13212	// op: Ii
13213	return `1`;
13214	case `0`:
13215	// op: Rs16
13216	return `16`;
13217	}
13218	break;
13219	}
13220	case Hexagon::J2_jumprgtez:
13221	case Hexagon::J2_jumprgtezpt:
13222	case Hexagon::J2_jumprltez:
13223	case Hexagon::J2_jumprltezpt:
13224	case Hexagon::J2_jumprnz:
13225	case Hexagon::J2_jumprnzpt:
13226	case Hexagon::J2_jumprz:
13227	case Hexagon::J2_jumprzpt: {
13228	switch (OpNum) {
13229	case `1`:
13230	// op: Ii
13231	return `1`;
13232	case `0`:
13233	// op: Rs32
13234	return `16`;
13235	}
13236	break;
13237	}
13238	case Hexagon::S4_pstorerbnewf_abs:
13239	case Hexagon::S4_pstorerbnewfnew_abs:
13240	case Hexagon::S4_pstorerbnewt_abs:
13241	case Hexagon::S4_pstorerbnewtnew_abs:
13242	case Hexagon::S4_pstorerhnewf_abs:
13243	case Hexagon::S4_pstorerhnewfnew_abs:
13244	case Hexagon::S4_pstorerhnewt_abs:
13245	case Hexagon::S4_pstorerhnewtnew_abs:
13246	case Hexagon::S4_pstorerinewf_abs:
13247	case Hexagon::S4_pstorerinewfnew_abs:
13248	case Hexagon::S4_pstorerinewt_abs:
13249	case Hexagon::S4_pstorerinewtnew_abs: {
13250	switch (OpNum) {
13251	case `1`:
13252	// op: Ii
13253	return `3`;
13254	case `0`:
13255	// op: Pv4
13256	return `0`;
13257	case `2`:
13258	// op: Nt8
13259	return `8`;
13260	}
13261	break;
13262	}
13263	case Hexagon::S4_pstorerbf_abs:
13264	case Hexagon::S4_pstorerbfnew_abs:
13265	case Hexagon::S4_pstorerbt_abs:
13266	case Hexagon::S4_pstorerbtnew_abs:
13267	case Hexagon::S4_pstorerff_abs:
13268	case Hexagon::S4_pstorerffnew_abs:
13269	case Hexagon::S4_pstorerft_abs:
13270	case Hexagon::S4_pstorerftnew_abs:
13271	case Hexagon::S4_pstorerhf_abs:
13272	case Hexagon::S4_pstorerhfnew_abs:
13273	case Hexagon::S4_pstorerht_abs:
13274	case Hexagon::S4_pstorerhtnew_abs:
13275	case Hexagon::S4_pstorerif_abs:
13276	case Hexagon::S4_pstorerifnew_abs:
13277	case Hexagon::S4_pstorerit_abs:
13278	case Hexagon::S4_pstoreritnew_abs: {
13279	switch (OpNum) {
13280	case `1`:
13281	// op: Ii
13282	return `3`;
13283	case `0`:
13284	// op: Pv4
13285	return `0`;
13286	case `2`:
13287	// op: Rt32
13288	return `8`;
13289	}
13290	break;
13291	}
13292	case Hexagon::S4_pstorerdf_abs:
13293	case Hexagon::S4_pstorerdfnew_abs:
13294	case Hexagon::S4_pstorerdt_abs:
13295	case Hexagon::S4_pstorerdtnew_abs: {
13296	switch (OpNum) {
13297	case `1`:
13298	// op: Ii
13299	return `3`;
13300	case `0`:
13301	// op: Pv4
13302	return `0`;
13303	case `2`:
13304	// op: Rtt32
13305	return `8`;
13306	}
13307	break;
13308	}
13309	case Hexagon::SL2_loadrd_sp: {
13310	switch (OpNum) {
13311	case `1`:
13312	// op: Ii
13313	return `3`;
13314	case `0`:
13315	// op: Rdd8
13316	return `0`;
13317	}
13318	break;
13319	}
13320	case Hexagon::S4_addi_asl_ri:
13321	case Hexagon::S4_addi_lsr_ri:
13322	case Hexagon::S4_andi_asl_ri:
13323	case Hexagon::S4_andi_lsr_ri:
13324	case Hexagon::S4_ori_asl_ri:
13325	case Hexagon::S4_ori_lsr_ri:
13326	case Hexagon::S4_subi_asl_ri:
13327	case Hexagon::S4_subi_lsr_ri: {
13328	switch (OpNum) {
13329	case `1`:
13330	// op: Ii
13331	return `3`;
13332	case `3`:
13333	// op: II
13334	return `8`;
13335	case `0`:
13336	// op: Rx32
13337	return `16`;
13338	}
13339	break;
13340	}
13341	case Hexagon::SA1_addsp:
13342	case Hexagon::SA1_seti:
13343	case Hexagon::SL2_loadri_sp: {
13344	switch (OpNum) {
13345	case `1`:
13346	// op: Ii
13347	return `4`;
13348	case `0`:
13349	// op: Rd16
13350	return `0`;
13351	}
13352	break;
13353	}
13354	case Hexagon::A2_tfrsi:
13355	case Hexagon::F2_sfimm_n:
13356	case Hexagon::F2_sfimm_p:
13357	case Hexagon::L2_loadrbgp:
13358	case Hexagon::L2_loadrhgp:
13359	case Hexagon::L2_loadrigp:
13360	case Hexagon::L2_loadrubgp:
13361	case Hexagon::L2_loadruhgp:
13362	case Hexagon::PS_loadrbabs:
13363	case Hexagon::PS_loadrhabs:
13364	case Hexagon::PS_loadriabs:
13365	case Hexagon::PS_loadrubabs:
13366	case Hexagon::PS_loadruhabs: {
13367	switch (OpNum) {
13368	case `1`:
13369	// op: Ii
13370	return `5`;
13371	case `0`:
13372	// op: Rd32
13373	return `0`;
13374	}
13375	break;
13376	}
13377	case Hexagon::F2_dfimm_n:
13378	case Hexagon::F2_dfimm_p:
13379	case Hexagon::L2_loadrdgp:
13380	case Hexagon::PS_loadrdabs: {
13381	switch (OpNum) {
13382	case `1`:
13383	// op: Ii
13384	return `5`;
13385	case `0`:
13386	// op: Rdd32
13387	return `0`;
13388	}
13389	break;
13390	}
13391	case Hexagon::SA1_combine0i:
13392	case Hexagon::SA1_combine1i:
13393	case Hexagon::SA1_combine2i:
13394	case Hexagon::SA1_combine3i: {
13395	switch (OpNum) {
13396	case `1`:
13397	// op: Ii
13398	return `5`;
13399	case `0`:
13400	// op: Rdd8
13401	return `0`;
13402	}
13403	break;
13404	}
13405	case Hexagon::A2_combineii:
13406	case Hexagon::A4_combineii: {
13407	switch (OpNum) {
13408	case `1`:
13409	// op: Ii
13410	return `5`;
13411	case `2`:
13412	// op: II
13413	return `13`;
13414	case `0`:
13415	// op: Rdd32
13416	return `0`;
13417	}
13418	break;
13419	}
13420	case Hexagon::A2_subri: {
13421	switch (OpNum) {
13422	case `1`:
13423	// op: Ii
13424	return `5`;
13425	case `2`:
13426	// op: Rs32
13427	return `16`;
13428	case `0`:
13429	// op: Rd32
13430	return `0`;
13431	}
13432	break;
13433	}
13434	case Hexagon::A4_combineir: {
13435	switch (OpNum) {
13436	case `1`:
13437	// op: Ii
13438	return `5`;
13439	case `2`:
13440	// op: Rs32
13441	return `16`;
13442	case `0`:
13443	// op: Rdd32
13444	return `0`;
13445	}
13446	break;
13447	}
13448	case Hexagon::M4_mpyrr_addi: {
13449	switch (OpNum) {
13450	case `1`:
13451	// op: Ii
13452	return `5`;
13453	case `2`:
13454	// op: Rs32
13455	return `16`;
13456	case `3`:
13457	// op: Rt32
13458	return `8`;
13459	case `0`:
13460	// op: Rd32
13461	return `0`;
13462	}
13463	break;
13464	}
13465	case Hexagon::S4_lsli: {
13466	switch (OpNum) {
13467	case `1`:
13468	// op: Ii
13469	return `5`;
13470	case `2`:
13471	// op: Rt32
13472	return `8`;
13473	case `0`:
13474	// op: Rd32
13475	return `0`;
13476	}
13477	break;
13478	}
13479	case Hexagon::M4_mpyri_addi: {
13480	switch (OpNum) {
13481	case `1`:
13482	// op: Ii
13483	return `5`;
13484	case `3`:
13485	// op: II
13486	return `0`;
13487	case `2`:
13488	// op: Rs32
13489	return `16`;
13490	case `0`:
13491	// op: Rd32
13492	return `8`;
13493	}
13494	break;
13495	}
13496	case Hexagon::S4_storerbnew_ur:
13497	case Hexagon::S4_storerhnew_ur:
13498	case Hexagon::S4_storerinew_ur: {
13499	switch (OpNum) {
13500	case `1`:
13501	// op: Ii
13502	return `6`;
13503	case `2`:
13504	// op: II
13505	return `0`;
13506	case `0`:
13507	// op: Ru32
13508	return `16`;
13509	case `3`:
13510	// op: Nt8
13511	return `8`;
13512	}
13513	break;
13514	}
13515	case Hexagon::S4_storerb_ur:
13516	case Hexagon::S4_storerf_ur:
13517	case Hexagon::S4_storerh_ur:
13518	case Hexagon::S4_storeri_ur: {
13519	switch (OpNum) {
13520	case `1`:
13521	// op: Ii
13522	return `6`;
13523	case `2`:
13524	// op: II
13525	return `0`;
13526	case `0`:
13527	// op: Ru32
13528	return `16`;
13529	case `3`:
13530	// op: Rt32
13531	return `8`;
13532	}
13533	break;
13534	}
13535	case Hexagon::S4_storerd_ur: {
13536	switch (OpNum) {
13537	case `1`:
13538	// op: Ii
13539	return `6`;
13540	case `2`:
13541	// op: II
13542	return `0`;
13543	case `0`:
13544	// op: Ru32
13545	return `16`;
13546	case `3`:
13547	// op: Rtt32
13548	return `8`;
13549	}
13550	break;
13551	}
13552	case Hexagon::C4_addipc: {
13553	switch (OpNum) {
13554	case `1`:
13555	// op: Ii
13556	return `7`;
13557	case `0`:
13558	// op: Rd32
13559	return `0`;
13560	}
13561	break;
13562	}
13563	case Hexagon::L4_add_memopb_io:
13564	case Hexagon::L4_add_memoph_io:
13565	case Hexagon::L4_add_memopw_io:
13566	case Hexagon::L4_and_memopb_io:
13567	case Hexagon::L4_and_memoph_io:
13568	case Hexagon::L4_and_memopw_io:
13569	case Hexagon::L4_or_memopb_io:
13570	case Hexagon::L4_or_memoph_io:
13571	case Hexagon::L4_or_memopw_io:
13572	case Hexagon::L4_sub_memopb_io:
13573	case Hexagon::L4_sub_memoph_io:
13574	case Hexagon::L4_sub_memopw_io: {
13575	switch (OpNum) {
13576	case `1`:
13577	// op: Ii
13578	return `7`;
13579	case `0`:
13580	// op: Rs32
13581	return `16`;
13582	case `2`:
13583	// op: Rt32
13584	return `0`;
13585	}
13586	break;
13587	}
13588	case Hexagon::L4_iadd_memopb_io:
13589	case Hexagon::L4_iadd_memoph_io:
13590	case Hexagon::L4_iadd_memopw_io:
13591	case Hexagon::L4_iand_memopb_io:
13592	case Hexagon::L4_iand_memoph_io:
13593	case Hexagon::L4_iand_memopw_io:
13594	case Hexagon::L4_ior_memopb_io:
13595	case Hexagon::L4_ior_memoph_io:
13596	case Hexagon::L4_ior_memopw_io:
13597	case Hexagon::L4_isub_memopb_io:
13598	case Hexagon::L4_isub_memoph_io:
13599	case Hexagon::L4_isub_memopw_io:
13600	case Hexagon::S4_storeirb_io:
13601	case Hexagon::S4_storeirh_io:
13602	case Hexagon::S4_storeiri_io: {
13603	switch (OpNum) {
13604	case `1`:
13605	// op: Ii
13606	return `7`;
13607	case `2`:
13608	// op: II
13609	return `0`;
13610	case `0`:
13611	// op: Rs32
13612	return `16`;
13613	}
13614	break;
13615	}
13616	case Hexagon::V6_vwhist128qm: {
13617	switch (OpNum) {
13618	case `1`:
13619	// op: Ii
13620	return `8`;
13621	case `0`:
13622	// op: Qv4
13623	return `22`;
13624	}
13625	break;
13626	}
13627	case Hexagon::SS1_storeb_io:
13628	case Hexagon::SS1_storew_io:
13629	case Hexagon::SS2_storeh_io: {
13630	switch (OpNum) {
13631	case `1`:
13632	// op: Ii
13633	return `8`;
13634	case `0`:
13635	// op: Rs16
13636	return `4`;
13637	case `2`:
13638	// op: Rt16
13639	return `0`;
13640	}
13641	break;
13642	}
13643	case Hexagon::V6_vS32b_new_ai:
13644	case Hexagon::V6_vS32b_nt_new_ai: {
13645	switch (OpNum) {
13646	case `1`:
13647	// op: Ii
13648	return `8`;
13649	case `0`:
13650	// op: Rt32
13651	return `16`;
13652	case `2`:
13653	// op: Os8
13654	return `0`;
13655	}
13656	break;
13657	}
13658	case Hexagon::V6_vS32Ub_ai:
13659	case Hexagon::V6_vS32b_ai:
13660	case Hexagon::V6_vS32b_nt_ai: {
13661	switch (OpNum) {
13662	case `1`:
13663	// op: Ii
13664	return `8`;
13665	case `0`:
13666	// op: Rt32
13667	return `16`;
13668	case `2`:
13669	// op: Vs32
13670	return `0`;
13671	}
13672	break;
13673	}
13674	case Hexagon::V6_vS32b_srls_ai:
13675	case Hexagon::V6_zLd_ai: {
13676	switch (OpNum) {
13677	case `1`:
13678	// op: Ii
13679	return `8`;
13680	case `0`:
13681	// op: Rt32
13682	return `16`;
13683	}
13684	break;
13685	}
13686	case Hexagon::S2_mask: {
13687	switch (OpNum) {
13688	case `1`:
13689	// op: Ii
13690	return `8`;
13691	case `2`:
13692	// op: II
13693	return `5`;
13694	case `0`:
13695	// op: Rd32
13696	return `0`;
13697	}
13698	break;
13699	}
13700	case Hexagon::C2_all8:
13701	case Hexagon::C2_any8:
13702	case Hexagon::C2_not: {
13703	switch (OpNum) {
13704	case `1`:
13705	// op: Ps4
13706	return `16`;
13707	case `0`:
13708	// op: Pd4
13709	return `0`;
13710	}
13711	break;
13712	}
13713	case Hexagon::C2_tfrpr: {
13714	switch (OpNum) {
13715	case `1`:
13716	// op: Ps4
13717	return `16`;
13718	case `0`:
13719	// op: Rd32
13720	return `0`;
13721	}
13722	break;
13723	}
13724	case Hexagon::C2_xor:
13725	case Hexagon::C4_fastcorner9:
13726	case Hexagon::C4_fastcorner9_not: {
13727	switch (OpNum) {
13728	case `1`:
13729	// op: Ps4
13730	return `16`;
13731	case `2`:
13732	// op: Pt4
13733	return `8`;
13734	case `0`:
13735	// op: Pd4
13736	return `0`;
13737	}
13738	break;
13739	}
13740	case Hexagon::C2_vitpack: {
13741	switch (OpNum) {
13742	case `1`:
13743	// op: Ps4
13744	return `16`;
13745	case `2`:
13746	// op: Pt4
13747	return `8`;
13748	case `0`:
13749	// op: Rd32
13750	return `0`;
13751	}
13752	break;
13753	}
13754	case Hexagon::C4_and_and:
13755	case Hexagon::C4_and_andn:
13756	case Hexagon::C4_and_or:
13757	case Hexagon::C4_and_orn:
13758	case Hexagon::C4_or_and:
13759	case Hexagon::C4_or_andn:
13760	case Hexagon::C4_or_or:
13761	case Hexagon::C4_or_orn: {
13762	switch (OpNum) {
13763	case `1`:
13764	// op: Ps4
13765	return `16`;
13766	case `2`:
13767	// op: Pt4
13768	return `8`;
13769	case `3`:
13770	// op: Pu4
13771	return `6`;
13772	case `0`:
13773	// op: Pd4
13774	return `0`;
13775	}
13776	break;
13777	}
13778	case Hexagon::V6_vcmov:
13779	case Hexagon::V6_vncmov: {
13780	switch (OpNum) {
13781	case `1`:
13782	// op: Ps4
13783	return `5`;
13784	case `2`:
13785	// op: Vu32
13786	return `8`;
13787	case `0`:
13788	// op: Vd32
13789	return `0`;
13790	}
13791	break;
13792	}
13793	case Hexagon::V6_vccombine:
13794	case Hexagon::V6_vnccombine: {
13795	switch (OpNum) {
13796	case `1`:
13797	// op: Ps4
13798	return `5`;
13799	case `2`:
13800	// op: Vu32
13801	return `8`;
13802	case `3`:
13803	// op: Vv32
13804	return `16`;
13805	case `0`:
13806	// op: Vdd32
13807	return `0`;
13808	}
13809	break;
13810	}
13811	case Hexagon::C2_mask: {
13812	switch (OpNum) {
13813	case `1`:
13814	// op: Pt4
13815	return `8`;
13816	case `0`:
13817	// op: Rdd32
13818	return `0`;
13819	}
13820	break;
13821	}
13822	case Hexagon::C2_and:
13823	case Hexagon::C2_andn:
13824	case Hexagon::C2_or:
13825	case Hexagon::C2_orn: {
13826	switch (OpNum) {
13827	case `1`:
13828	// op: Pt4
13829	return `8`;
13830	case `2`:
13831	// op: Ps4
13832	return `16`;
13833	case `0`:
13834	// op: Pd4
13835	return `0`;
13836	}
13837	break;
13838	}
13839	case Hexagon::A2_paddf:
13840	case Hexagon::A2_paddfnew:
13841	case Hexagon::A2_paddt:
13842	case Hexagon::A2_paddtnew:
13843	case Hexagon::A2_pandf:
13844	case Hexagon::A2_pandfnew:
13845	case Hexagon::A2_pandt:
13846	case Hexagon::A2_pandtnew:
13847	case Hexagon::A2_porf:
13848	case Hexagon::A2_porfnew:
13849	case Hexagon::A2_port:
13850	case Hexagon::A2_portnew:
13851	case Hexagon::A2_pxorf:
13852	case Hexagon::A2_pxorfnew:
13853	case Hexagon::A2_pxort:
13854	case Hexagon::A2_pxortnew:
13855	case Hexagon::C2_mux: {
13856	switch (OpNum) {
13857	case `1`:
13858	// op: Pu4
13859	return `5`;
13860	case `2`:
13861	// op: Rs32
13862	return `16`;
13863	case `3`:
13864	// op: Rt32
13865	return `8`;
13866	case `0`:
13867	// op: Rd32
13868	return `0`;
13869	}
13870	break;
13871	}
13872	case Hexagon::C2_ccombinewf:
13873	case Hexagon::C2_ccombinewnewf:
13874	case Hexagon::C2_ccombinewnewt:
13875	case Hexagon::C2_ccombinewt: {
13876	switch (OpNum) {
13877	case `1`:
13878	// op: Pu4
13879	return `5`;
13880	case `2`:
13881	// op: Rs32
13882	return `16`;
13883	case `3`:
13884	// op: Rt32
13885	return `8`;
13886	case `0`:
13887	// op: Rdd32
13888	return `0`;
13889	}
13890	break;
13891	}
13892	case Hexagon::C2_vmux: {
13893	switch (OpNum) {
13894	case `1`:
13895	// op: Pu4
13896	return `5`;
13897	case `2`:
13898	// op: Rss32
13899	return `16`;
13900	case `3`:
13901	// op: Rtt32
13902	return `8`;
13903	case `0`:
13904	// op: Rdd32
13905	return `0`;
13906	}
13907	break;
13908	}
13909	case Hexagon::A2_psubf:
13910	case Hexagon::A2_psubfnew:
13911	case Hexagon::A2_psubt:
13912	case Hexagon::A2_psubtnew: {
13913	switch (OpNum) {
13914	case `1`:
13915	// op: Pu4
13916	return `5`;
13917	case `2`:
13918	// op: Rt32
13919	return `8`;
13920	case `3`:
13921	// op: Rs32
13922	return `16`;
13923	case `0`:
13924	// op: Rd32
13925	return `0`;
13926	}
13927	break;
13928	}
13929	case Hexagon::A4_paslhf:
13930	case Hexagon::A4_paslhfnew:
13931	case Hexagon::A4_paslht:
13932	case Hexagon::A4_paslhtnew:
13933	case Hexagon::A4_pasrhf:
13934	case Hexagon::A4_pasrhfnew:
13935	case Hexagon::A4_pasrht:
13936	case Hexagon::A4_pasrhtnew:
13937	case Hexagon::A4_psxtbf:
13938	case Hexagon::A4_psxtbfnew:
13939	case Hexagon::A4_psxtbt:
13940	case Hexagon::A4_psxtbtnew:
13941	case Hexagon::A4_psxthf:
13942	case Hexagon::A4_psxthfnew:
13943	case Hexagon::A4_psxtht:
13944	case Hexagon::A4_psxthtnew:
13945	case Hexagon::A4_pzxtbf:
13946	case Hexagon::A4_pzxtbfnew:
13947	case Hexagon::A4_pzxtbt:
13948	case Hexagon::A4_pzxtbtnew:
13949	case Hexagon::A4_pzxthf:
13950	case Hexagon::A4_pzxthfnew:
13951	case Hexagon::A4_pzxtht:
13952	case Hexagon::A4_pzxthtnew: {
13953	switch (OpNum) {
13954	case `1`:
13955	// op: Pu4
13956	return `8`;
13957	case `2`:
13958	// op: Rs32
13959	return `16`;
13960	case `0`:
13961	// op: Rd32
13962	return `0`;
13963	}
13964	break;
13965	}
13966	case Hexagon::V6_zLd_pred_ppu: {
13967	switch (OpNum) {
13968	case `1`:
13969	// op: Pv4
13970	return `11`;
13971	case `3`:
13972	// op: Mu2
13973	return `13`;
13974	case `0`:
13975	// op: Rx32
13976	return `16`;
13977	}
13978	break;
13979	}
13980	case Hexagon::V6_vS32b_new_npred_ppu:
13981	case Hexagon::V6_vS32b_new_pred_ppu:
13982	case Hexagon::V6_vS32b_nt_new_npred_ppu:
13983	case Hexagon::V6_vS32b_nt_new_pred_ppu: {
13984	switch (OpNum) {
13985	case `1`:
13986	// op: Pv4
13987	return `11`;
13988	case `3`:
13989	// op: Mu2
13990	return `13`;
13991	case `4`:
13992	// op: Os8
13993	return `0`;
13994	case `0`:
13995	// op: Rx32
13996	return `16`;
13997	}
13998	break;
13999	}
14000	case Hexagon::V6_vS32Ub_npred_ppu:
14001	case Hexagon::V6_vS32Ub_pred_ppu:
14002	case Hexagon::V6_vS32b_npred_ppu:
14003	case Hexagon::V6_vS32b_nt_npred_ppu:
14004	case Hexagon::V6_vS32b_nt_pred_ppu:
14005	case Hexagon::V6_vS32b_pred_ppu: {
14006	switch (OpNum) {
14007	case `1`:
14008	// op: Pv4
14009	return `11`;
14010	case `3`:
14011	// op: Mu2
14012	return `13`;
14013	case `4`:
14014	// op: Vs32
14015	return `0`;
14016	case `0`:
14017	// op: Rx32
14018	return `16`;
14019	}
14020	break;
14021	}
14022	case Hexagon::L4_return_f:
14023	case Hexagon::L4_return_fnew_pnt:
14024	case Hexagon::L4_return_fnew_pt:
14025	case Hexagon::L4_return_t:
14026	case Hexagon::L4_return_tnew_pnt:
14027	case Hexagon::L4_return_tnew_pt: {
14028	switch (OpNum) {
14029	case `1`:
14030	// op: Pv4
14031	return `8`;
14032	case `2`:
14033	// op: Rs32
14034	return `16`;
14035	case `0`:
14036	// op: Rdd32
14037	return `0`;
14038	}
14039	break;
14040	}
14041	case Hexagon::V6_pred_not: {
14042	switch (OpNum) {
14043	case `1`:
14044	// op: Qs4
14045	return `8`;
14046	case `0`:
14047	// op: Qd4
14048	return `0`;
14049	}
14050	break;
14051	}
14052	case Hexagon::V6_pred_and:
14053	case Hexagon::V6_pred_and_n:
14054	case Hexagon::V6_pred_or:
14055	case Hexagon::V6_pred_or_n:
14056	case Hexagon::V6_pred_xor:
14057	case Hexagon::V6_shuffeqh:
14058	case Hexagon::V6_shuffeqw: {
14059	switch (OpNum) {
14060	case `1`:
14061	// op: Qs4
14062	return `8`;
14063	case `2`:
14064	// op: Qt4
14065	return `22`;
14066	case `0`:
14067	// op: Qd4
14068	return `0`;
14069	}
14070	break;
14071	}
14072	case Hexagon::V6_vmux: {
14073	switch (OpNum) {
14074	case `1`:
14075	// op: Qt4
14076	return `5`;
14077	case `2`:
14078	// op: Vu32
14079	return `8`;
14080	case `3`:
14081	// op: Vv32
14082	return `16`;
14083	case `0`:
14084	// op: Vd32
14085	return `0`;
14086	}
14087	break;
14088	}
14089	case Hexagon::V6_vswap: {
14090	switch (OpNum) {
14091	case `1`:
14092	// op: Qt4
14093	return `5`;
14094	case `2`:
14095	// op: Vu32
14096	return `8`;
14097	case `3`:
14098	// op: Vv32
14099	return `16`;
14100	case `0`:
14101	// op: Vdd32
14102	return `0`;
14103	}
14104	break;
14105	}
14106	case Hexagon::V6_vandnqrt:
14107	case Hexagon::V6_vandqrt: {
14108	switch (OpNum) {
14109	case `1`:
14110	// op: Qu4
14111	return `8`;
14112	case `2`:
14113	// op: Rt32
14114	return `16`;
14115	case `0`:
14116	// op: Vd32
14117	return `0`;
14118	}
14119	break;
14120	}
14121	case Hexagon::V6_vS32b_nqpred_ppu:
14122	case Hexagon::V6_vS32b_nt_nqpred_ppu:
14123	case Hexagon::V6_vS32b_nt_qpred_ppu:
14124	case Hexagon::V6_vS32b_qpred_ppu: {
14125	switch (OpNum) {
14126	case `1`:
14127	// op: Qv4
14128	return `11`;
14129	case `3`:
14130	// op: Mu2
14131	return `13`;
14132	case `4`:
14133	// op: Vs32
14134	return `0`;
14135	case `0`:
14136	// op: Rx32
14137	return `16`;
14138	}
14139	break;
14140	}
14141	case Hexagon::V6_vprefixqb:
14142	case Hexagon::V6_vprefixqh:
14143	case Hexagon::V6_vprefixqw: {
14144	switch (OpNum) {
14145	case `1`:
14146	// op: Qv4
14147	return `22`;
14148	case `0`:
14149	// op: Vd32
14150	return `0`;
14151	}
14152	break;
14153	}
14154	case Hexagon::V6_vandvnqv:
14155	case Hexagon::V6_vandvqv: {
14156	switch (OpNum) {
14157	case `1`:
14158	// op: Qv4
14159	return `22`;
14160	case `2`:
14161	// op: Vu32
14162	return `8`;
14163	case `0`:
14164	// op: Vd32
14165	return `0`;
14166	}
14167	break;
14168	}
14169	case Hexagon::V6_vaddbnq:
14170	case Hexagon::V6_vaddbq:
14171	case Hexagon::V6_vaddhnq:
14172	case Hexagon::V6_vaddhq:
14173	case Hexagon::V6_vaddwnq:
14174	case Hexagon::V6_vaddwq:
14175	case Hexagon::V6_vsubbnq:
14176	case Hexagon::V6_vsubbq:
14177	case Hexagon::V6_vsubhnq:
14178	case Hexagon::V6_vsubhq:
14179	case Hexagon::V6_vsubwnq:
14180	case Hexagon::V6_vsubwq: {
14181	switch (OpNum) {
14182	case `1`:
14183	// op: Qv4
14184	return `22`;
14185	case `3`:
14186	// op: Vu32
14187	return `8`;
14188	case `0`:
14189	// op: Vx32
14190	return `0`;
14191	}
14192	break;
14193	}
14194	case Hexagon::SA1_and1:
14195	case Hexagon::SA1_dec:
14196	case Hexagon::SA1_inc:
14197	case Hexagon::SA1_sxtb:
14198	case Hexagon::SA1_sxth:
14199	case Hexagon::SA1_tfr:
14200	case Hexagon::SA1_zxtb:
14201	case Hexagon::SA1_zxth: {
14202	switch (OpNum) {
14203	case `1`:
14204	// op: Rs16
14205	return `4`;
14206	case `0`:
14207	// op: Rd16
14208	return `0`;
14209	}
14210	break;
14211	}
14212	case Hexagon::SA1_combinerz:
14213	case Hexagon::SA1_combinezr: {
14214	switch (OpNum) {
14215	case `1`:
14216	// op: Rs16
14217	return `4`;
14218	case `0`:
14219	// op: Rdd8
14220	return `0`;
14221	}
14222	break;
14223	}
14224	case Hexagon::A2_tfrrcr: {
14225	switch (OpNum) {
14226	case `1`:
14227	// op: Rs32
14228	return `16`;
14229	case `0`:
14230	// op: Cd32
14231	return `0`;
14232	}
14233	break;
14234	}
14235	case Hexagon::G4_tfrgrcr: {
14236	switch (OpNum) {
14237	case `1`:
14238	// op: Rs32
14239	return `16`;
14240	case `0`:
14241	// op: Gd32
14242	return `0`;
14243	}
14244	break;
14245	}
14246	case Hexagon::C2_tfrrp:
14247	case Hexagon::Y5_l2locka: {
14248	switch (OpNum) {
14249	case `1`:
14250	// op: Rs32
14251	return `16`;
14252	case `0`:
14253	// op: Pd4
14254	return `0`;
14255	}
14256	break;
14257	}
14258	case Hexagon::A2_abs:
14259	case Hexagon::A2_abssat:
14260	case Hexagon::A2_aslh:
14261	case Hexagon::A2_asrh:
14262	case Hexagon::A2_negsat:
14263	case Hexagon::A2_satb:
14264	case Hexagon::A2_sath:
14265	case Hexagon::A2_satub:
14266	case Hexagon::A2_satuh:
14267	case Hexagon::A2_swiz:
14268	case Hexagon::A2_sxtb:
14269	case Hexagon::A2_sxth:
14270	case Hexagon::A2_tfr:
14271	case Hexagon::A2_zxth:
14272	case Hexagon::F2_conv_sf2uw:
14273	case Hexagon::F2_conv_sf2uw_chop:
14274	case Hexagon::F2_conv_sf2w:
14275	case Hexagon::F2_conv_sf2w_chop:
14276	case Hexagon::F2_conv_uw2sf:
14277	case Hexagon::F2_conv_w2sf:
14278	case Hexagon::F2_sffixupr:
14279	case Hexagon::L2_loadw_aq:
14280	case Hexagon::L2_loadw_locked:
14281	case Hexagon::S2_brev:
14282	case Hexagon::S2_cl0:
14283	case Hexagon::S2_cl1:
14284	case Hexagon::S2_clb:
14285	case Hexagon::S2_clbnorm:
14286	case Hexagon::S2_ct0:
14287	case Hexagon::S2_ct1:
14288	case Hexagon::S2_svsathb:
14289	case Hexagon::S2_svsathub:
14290	case Hexagon::S2_vsplatrb:
14291	case Hexagon::Y2_dctagr:
14292	case Hexagon::Y2_getimask:
14293	case Hexagon::Y2_iassignr:
14294	case Hexagon::Y2_icdatar:
14295	case Hexagon::Y2_ictagr:
14296	case Hexagon::Y2_tlbp:
14297	case Hexagon::Y4_l2tagr: {
14298	switch (OpNum) {
14299	case `1`:
14300	// op: Rs32
14301	return `16`;
14302	case `0`:
14303	// op: Rd32
14304	return `0`;
14305	}
14306	break;
14307	}
14308	case Hexagon::A2_sxtw:
14309	case Hexagon::F2_conv_sf2d:
14310	case Hexagon::F2_conv_sf2d_chop:
14311	case Hexagon::F2_conv_sf2df:
14312	case Hexagon::F2_conv_sf2ud:
14313	case Hexagon::F2_conv_sf2ud_chop:
14314	case Hexagon::F2_conv_uw2df:
14315	case Hexagon::F2_conv_w2df:
14316	case Hexagon::L2_deallocframe:
14317	case Hexagon::L4_loadd_aq:
14318	case Hexagon::L4_loadd_locked:
14319	case Hexagon::L4_return:
14320	case Hexagon::S2_vsplatrh:
14321	case Hexagon::S2_vsxtbh:
14322	case Hexagon::S2_vsxthw:
14323	case Hexagon::S2_vzxtbh:
14324	case Hexagon::S2_vzxthw:
14325	case Hexagon::S6_vsplatrbp:
14326	case Hexagon::Y2_tlbr: {
14327	switch (OpNum) {
14328	case `1`:
14329	// op: Rs32
14330	return `16`;
14331	case `0`:
14332	// op: Rdd32
14333	return `0`;
14334	}
14335	break;
14336	}
14337	case Hexagon::Y2_tfrsrcr: {
14338	switch (OpNum) {
14339	case `1`:
14340	// op: Rs32
14341	return `16`;
14342	case `0`:
14343	// op: Sd128
14344	return `0`;
14345	}
14346	break;
14347	}
14348	case Hexagon::A4_cmpbeq:
14349	case Hexagon::A4_cmpbgt:
14350	case Hexagon::A4_cmpbgtu:
14351	case Hexagon::A4_cmpheq:
14352	case Hexagon::A4_cmphgt:
14353	case Hexagon::A4_cmphgtu:
14354	case Hexagon::C2_bitsclr:
14355	case Hexagon::C2_bitsset:
14356	case Hexagon::C2_cmpeq:
14357	case Hexagon::C2_cmpgt:
14358	case Hexagon::C2_cmpgtu:
14359	case Hexagon::C4_cmplte:
14360	case Hexagon::C4_cmplteu:
14361	case Hexagon::C4_cmpneq:
14362	case Hexagon::C4_nbitsclr:
14363	case Hexagon::C4_nbitsset:
14364	case Hexagon::F2_sfcmpeq:
14365	case Hexagon::F2_sfcmpge:
14366	case Hexagon::F2_sfcmpgt:
14367	case Hexagon::F2_sfcmpuo:
14368	case Hexagon::S2_storew_locked:
14369	case Hexagon::S2_tstbit_r:
14370	case Hexagon::S4_ntstbit_r: {
14371	switch (OpNum) {
14372	case `1`:
14373	// op: Rs32
14374	return `16`;
14375	case `2`:
14376	// op: Rt32
14377	return `8`;
14378	case `0`:
14379	// op: Pd4
14380	return `0`;
14381	}
14382	break;
14383	}
14384	case Hexagon::A2_add:
14385	case Hexagon::A2_addsat:
14386	case Hexagon::A2_and:
14387	case Hexagon::A2_max:
14388	case Hexagon::A2_maxu:
14389	case Hexagon::A2_or:
14390	case Hexagon::A2_svaddh:
14391	case Hexagon::A2_svaddhs:
14392	case Hexagon::A2_svadduhs:
14393	case Hexagon::A2_svavgh:
14394	case Hexagon::A2_svavghs:
14395	case Hexagon::A2_xor:
14396	case Hexagon::A4_cround_rr:
14397	case Hexagon::A4_modwrapu:
14398	case Hexagon::A4_rcmpeq:
14399	case Hexagon::A4_rcmpneq:
14400	case Hexagon::A4_round_rr:
14401	case Hexagon::A4_round_rr_sat:
14402	case Hexagon::F2_sfadd:
14403	case Hexagon::F2_sffixupd:
14404	case Hexagon::F2_sffixupn:
14405	case Hexagon::F2_sfmax:
14406	case Hexagon::F2_sfmin:
14407	case Hexagon::F2_sfmpy:
14408	case Hexagon::F2_sfsub:
14409	case Hexagon::L4_loadw_phys:
14410	case Hexagon::M2_cmpyrs_s0:
14411	case Hexagon::M2_cmpyrs_s1:
14412	case Hexagon::M2_cmpyrsc_s0:
14413	case Hexagon::M2_cmpyrsc_s1:
14414	case Hexagon::M2_dpmpyss_rnd_s0:
14415	case Hexagon::M2_hmmpyh_rs1:
14416	case Hexagon::M2_hmmpyh_s1:
14417	case Hexagon::M2_hmmpyl_rs1:
14418	case Hexagon::M2_hmmpyl_s1:
14419	case Hexagon::M2_mpy_hh_s0:
14420	case Hexagon::M2_mpy_hh_s1:
14421	case Hexagon::M2_mpy_hl_s0:
14422	case Hexagon::M2_mpy_hl_s1:
14423	case Hexagon::M2_mpy_lh_s0:
14424	case Hexagon::M2_mpy_lh_s1:
14425	case Hexagon::M2_mpy_ll_s0:
14426	case Hexagon::M2_mpy_ll_s1:
14427	case Hexagon::M2_mpy_rnd_hh_s0:
14428	case Hexagon::M2_mpy_rnd_hh_s1:
14429	case Hexagon::M2_mpy_rnd_hl_s0:
14430	case Hexagon::M2_mpy_rnd_hl_s1:
14431	case Hexagon::M2_mpy_rnd_lh_s0:
14432	case Hexagon::M2_mpy_rnd_lh_s1:
14433	case Hexagon::M2_mpy_rnd_ll_s0:
14434	case Hexagon::M2_mpy_rnd_ll_s1:
14435	case Hexagon::M2_mpy_sat_hh_s0:
14436	case Hexagon::M2_mpy_sat_hh_s1:
14437	case Hexagon::M2_mpy_sat_hl_s0:
14438	case Hexagon::M2_mpy_sat_hl_s1:
14439	case Hexagon::M2_mpy_sat_lh_s0:
14440	case Hexagon::M2_mpy_sat_lh_s1:
14441	case Hexagon::M2_mpy_sat_ll_s0:
14442	case Hexagon::M2_mpy_sat_ll_s1:
14443	case Hexagon::M2_mpy_sat_rnd_hh_s0:
14444	case Hexagon::M2_mpy_sat_rnd_hh_s1:
14445	case Hexagon::M2_mpy_sat_rnd_hl_s0:
14446	case Hexagon::M2_mpy_sat_rnd_hl_s1:
14447	case Hexagon::M2_mpy_sat_rnd_lh_s0:
14448	case Hexagon::M2_mpy_sat_rnd_lh_s1:
14449	case Hexagon::M2_mpy_sat_rnd_ll_s0:
14450	case Hexagon::M2_mpy_sat_rnd_ll_s1:
14451	case Hexagon::M2_mpy_up:
14452	case Hexagon::M2_mpy_up_s1:
14453	case Hexagon::M2_mpy_up_s1_sat:
14454	case Hexagon::M2_mpyi:
14455	case Hexagon::M2_mpysu_up:
14456	case Hexagon::M2_mpyu_hh_s0:
14457	case Hexagon::M2_mpyu_hh_s1:
14458	case Hexagon::M2_mpyu_hl_s0:
14459	case Hexagon::M2_mpyu_hl_s1:
14460	case Hexagon::M2_mpyu_lh_s0:
14461	case Hexagon::M2_mpyu_lh_s1:
14462	case Hexagon::M2_mpyu_ll_s0:
14463	case Hexagon::M2_mpyu_ll_s1:
14464	case Hexagon::M2_mpyu_up:
14465	case Hexagon::M2_vmpy2s_s0pack:
14466	case Hexagon::M2_vmpy2s_s1pack:
14467	case Hexagon::S2_asl_r_r:
14468	case Hexagon::S2_asl_r_r_sat:
14469	case Hexagon::S2_asr_r_r:
14470	case Hexagon::S2_asr_r_r_sat:
14471	case Hexagon::S2_clrbit_r:
14472	case Hexagon::S2_lsl_r_r:
14473	case Hexagon::S2_lsr_r_r:
14474	case Hexagon::S2_setbit_r:
14475	case Hexagon::S2_togglebit_r:
14476	case Hexagon::S4_parity:
14477	case Hexagon::dep_A2_addsat: {
14478	switch (OpNum) {
14479	case `1`:
14480	// op: Rs32
14481	return `16`;
14482	case `2`:
14483	// op: Rt32
14484	return `8`;
14485	case `0`:
14486	// op: Rd32
14487	return `0`;
14488	}
14489	break;
14490	}
14491	case Hexagon::A2_combinew:
14492	case Hexagon::A4_bitsplit:
14493	case Hexagon::M2_cmpyi_s0:
14494	case Hexagon::M2_cmpyr_s0:
14495	case Hexagon::M2_cmpys_s0:
14496	case Hexagon::M2_cmpys_s1:
14497	case Hexagon::M2_cmpysc_s0:
14498	case Hexagon::M2_cmpysc_s1:
14499	case Hexagon::M2_dpmpyss_s0:
14500	case Hexagon::M2_dpmpyuu_s0:
14501	case Hexagon::M2_mpyd_hh_s0:
14502	case Hexagon::M2_mpyd_hh_s1:
14503	case Hexagon::M2_mpyd_hl_s0:
14504	case Hexagon::M2_mpyd_hl_s1:
14505	case Hexagon::M2_mpyd_lh_s0:
14506	case Hexagon::M2_mpyd_lh_s1:
14507	case Hexagon::M2_mpyd_ll_s0:
14508	case Hexagon::M2_mpyd_ll_s1:
14509	case Hexagon::M2_mpyd_rnd_hh_s0:
14510	case Hexagon::M2_mpyd_rnd_hh_s1:
14511	case Hexagon::M2_mpyd_rnd_hl_s0:
14512	case Hexagon::M2_mpyd_rnd_hl_s1:
14513	case Hexagon::M2_mpyd_rnd_lh_s0:
14514	case Hexagon::M2_mpyd_rnd_lh_s1:
14515	case Hexagon::M2_mpyd_rnd_ll_s0:
14516	case Hexagon::M2_mpyd_rnd_ll_s1:
14517	case Hexagon::M2_mpyud_hh_s0:
14518	case Hexagon::M2_mpyud_hh_s1:
14519	case Hexagon::M2_mpyud_hl_s0:
14520	case Hexagon::M2_mpyud_hl_s1:
14521	case Hexagon::M2_mpyud_lh_s0:
14522	case Hexagon::M2_mpyud_lh_s1:
14523	case Hexagon::M2_mpyud_ll_s0:
14524	case Hexagon::M2_mpyud_ll_s1:
14525	case Hexagon::M2_vmpy2s_s0:
14526	case Hexagon::M2_vmpy2s_s1:
14527	case Hexagon::M2_vmpy2su_s0:
14528	case Hexagon::M2_vmpy2su_s1:
14529	case Hexagon::M4_pmpyw:
14530	case Hexagon::M4_vpmpyh:
14531	case Hexagon::M5_vmpybsu:
14532	case Hexagon::M5_vmpybuu:
14533	case Hexagon::S2_packhl:
14534	case Hexagon::dep_S2_packhl: {
14535	switch (OpNum) {
14536	case `1`:
14537	// op: Rs32
14538	return `16`;
14539	case `2`:
14540	// op: Rt32
14541	return `8`;
14542	case `0`:
14543	// op: Rdd32
14544	return `0`;
14545	}
14546	break;
14547	}
14548	case Hexagon::S4_stored_locked: {
14549	switch (OpNum) {
14550	case `1`:
14551	// op: Rs32
14552	return `16`;
14553	case `2`:
14554	// op: Rtt32
14555	return `8`;
14556	case `0`:
14557	// op: Pd4
14558	return `0`;
14559	}
14560	break;
14561	}
14562	case Hexagon::S2_extractu_rp:
14563	case Hexagon::S4_extract_rp: {
14564	switch (OpNum) {
14565	case `1`:
14566	// op: Rs32
14567	return `16`;
14568	case `2`:
14569	// op: Rtt32
14570	return `8`;
14571	case `0`:
14572	// op: Rd32
14573	return `0`;
14574	}
14575	break;
14576	}
14577	case Hexagon::A4_tfrpcp: {
14578	switch (OpNum) {
14579	case `1`:
14580	// op: Rss32
14581	return `16`;
14582	case `0`:
14583	// op: Cdd32
14584	return `0`;
14585	}
14586	break;
14587	}
14588	case Hexagon::G4_tfrgpcp: {
14589	switch (OpNum) {
14590	case `1`:
14591	// op: Rss32
14592	return `16`;
14593	case `0`:
14594	// op: Gdd32
14595	return `0`;
14596	}
14597	break;
14598	}
14599	case Hexagon::A2_roundsat:
14600	case Hexagon::A2_sat:
14601	case Hexagon::F2_conv_d2sf:
14602	case Hexagon::F2_conv_df2sf:
14603	case Hexagon::F2_conv_df2uw:
14604	case Hexagon::F2_conv_df2uw_chop:
14605	case Hexagon::F2_conv_df2w:
14606	case Hexagon::F2_conv_df2w_chop:
14607	case Hexagon::F2_conv_ud2sf:
14608	case Hexagon::S2_cl0p:
14609	case Hexagon::S2_cl1p:
14610	case Hexagon::S2_clbp:
14611	case Hexagon::S2_ct0p:
14612	case Hexagon::S2_ct1p:
14613	case Hexagon::S2_vrndpackwh:
14614	case Hexagon::S2_vrndpackwhs:
14615	case Hexagon::S2_vsathb:
14616	case Hexagon::S2_vsathub:
14617	case Hexagon::S2_vsatwh:
14618	case Hexagon::S2_vsatwuh:
14619	case Hexagon::S2_vtrunehb:
14620	case Hexagon::S2_vtrunohb:
14621	case Hexagon::S4_clbpnorm:
14622	case Hexagon::S5_popcountp:
14623	case Hexagon::Y5_tlboc: {
14624	switch (OpNum) {
14625	case `1`:
14626	// op: Rss32
14627	return `16`;
14628	case `0`:
14629	// op: Rd32
14630	return `0`;
14631	}
14632	break;
14633	}
14634	case Hexagon::A2_absp:
14635	case Hexagon::A2_negp:
14636	case Hexagon::A2_notp:
14637	case Hexagon::A2_vabsh:
14638	case Hexagon::A2_vabshsat:
14639	case Hexagon::A2_vabsw:
14640	case Hexagon::A2_vabswsat:
14641	case Hexagon::A2_vconj:
14642	case Hexagon::F2_conv_d2df:
14643	case Hexagon::F2_conv_df2d:
14644	case Hexagon::F2_conv_df2d_chop:
14645	case Hexagon::F2_conv_df2ud:
14646	case Hexagon::F2_conv_df2ud_chop:
14647	case Hexagon::F2_conv_ud2df:
14648	case Hexagon::S2_brevp:
14649	case Hexagon::S2_deinterleave:
14650	case Hexagon::S2_interleave:
14651	case Hexagon::S2_vsathb_nopack:
14652	case Hexagon::S2_vsathub_nopack:
14653	case Hexagon::S2_vsatwh_nopack:
14654	case Hexagon::S2_vsatwuh_nopack: {
14655	switch (OpNum) {
14656	case `1`:
14657	// op: Rss32
14658	return `16`;
14659	case `0`:
14660	// op: Rdd32
14661	return `0`;
14662	}
14663	break;
14664	}
14665	case Hexagon::Y4_tfrspcp: {
14666	switch (OpNum) {
14667	case `1`:
14668	// op: Rss32
14669	return `16`;
14670	case `0`:
14671	// op: Sdd128
14672	return `0`;
14673	}
14674	break;
14675	}
14676	case Hexagon::A4_tlbmatch: {
14677	switch (OpNum) {
14678	case `1`:
14679	// op: Rss32
14680	return `16`;
14681	case `2`:
14682	// op: Rt32
14683	return `8`;
14684	case `0`:
14685	// op: Pd4
14686	return `0`;
14687	}
14688	break;
14689	}
14690	case Hexagon::M4_cmpyi_wh:
14691	case Hexagon::M4_cmpyi_whc:
14692	case Hexagon::M4_cmpyr_wh:
14693	case Hexagon::M4_cmpyr_whc:
14694	case Hexagon::S2_asr_r_svw_trun:
14695	case Hexagon::Y5_ctlbw: {
14696	switch (OpNum) {
14697	case `1`:
14698	// op: Rss32
14699	return `16`;
14700	case `2`:
14701	// op: Rt32
14702	return `8`;
14703	case `0`:
14704	// op: Rd32
14705	return `0`;
14706	}
14707	break;
14708	}
14709	case Hexagon::A7_croundd_rr:
14710	case Hexagon::S2_asl_r_p:
14711	case Hexagon::S2_asl_r_vh:
14712	case Hexagon::S2_asl_r_vw:
14713	case Hexagon::S2_asr_r_p:
14714	case Hexagon::S2_asr_r_vh:
14715	case Hexagon::S2_asr_r_vw:
14716	case Hexagon::S2_lsl_r_p:
14717	case Hexagon::S2_lsl_r_vh:
14718	case Hexagon::S2_lsl_r_vw:
14719	case Hexagon::S2_lsr_r_p:
14720	case Hexagon::S2_lsr_r_vh:
14721	case Hexagon::S2_lsr_r_vw:
14722	case Hexagon::S2_vcnegh:
14723	case Hexagon::S2_vcrotate: {
14724	switch (OpNum) {
14725	case `1`:
14726	// op: Rss32
14727	return `16`;
14728	case `2`:
14729	// op: Rt32
14730	return `8`;
14731	case `0`:
14732	// op: Rdd32
14733	return `0`;
14734	}
14735	break;
14736	}
14737	case Hexagon::A2_vcmpbeq:
14738	case Hexagon::A2_vcmpbgtu:
14739	case Hexagon::A2_vcmpheq:
14740	case Hexagon::A2_vcmphgt:
14741	case Hexagon::A2_vcmphgtu:
14742	case Hexagon::A2_vcmpweq:
14743	case Hexagon::A2_vcmpwgt:
14744	case Hexagon::A2_vcmpwgtu:
14745	case Hexagon::A4_boundscheck_hi:
14746	case Hexagon::A4_boundscheck_lo:
14747	case Hexagon::A4_vcmpbeq_any:
14748	case Hexagon::A4_vcmpbgt:
14749	case Hexagon::A6_vcmpbeq_notany:
14750	case Hexagon::C2_cmpeqp:
14751	case Hexagon::C2_cmpgtp:
14752	case Hexagon::C2_cmpgtup:
14753	case Hexagon::F2_dfcmpeq:
14754	case Hexagon::F2_dfcmpge:
14755	case Hexagon::F2_dfcmpgt:
14756	case Hexagon::F2_dfcmpuo: {
14757	switch (OpNum) {
14758	case `1`:
14759	// op: Rss32
14760	return `16`;
14761	case `2`:
14762	// op: Rtt32
14763	return `8`;
14764	case `0`:
14765	// op: Pd4
14766	return `0`;
14767	}
14768	break;
14769	}
14770	case Hexagon::A5_vaddhubs:
14771	case Hexagon::M2_vdmpyrs_s0:
14772	case Hexagon::M2_vdmpyrs_s1:
14773	case Hexagon::M2_vraddh:
14774	case Hexagon::M2_vradduh:
14775	case Hexagon::M2_vrcmpys_s1rp_h:
14776	case Hexagon::M2_vrcmpys_s1rp_l:
14777	case Hexagon::M7_wcmpyiw:
14778	case Hexagon::M7_wcmpyiw_rnd:
14779	case Hexagon::M7_wcmpyiwc:
14780	case Hexagon::M7_wcmpyiwc_rnd:
14781	case Hexagon::M7_wcmpyrw:
14782	case Hexagon::M7_wcmpyrw_rnd:
14783	case Hexagon::M7_wcmpyrwc:
14784	case Hexagon::M7_wcmpyrwc_rnd:
14785	case Hexagon::S2_parityp: {
14786	switch (OpNum) {
14787	case `1`:
14788	// op: Rss32
14789	return `16`;
14790	case `2`:
14791	// op: Rtt32
14792	return `8`;
14793	case `0`:
14794	// op: Rd32
14795	return `0`;
14796	}
14797	break;
14798	}
14799	case Hexagon::A2_addp:
14800	case Hexagon::A2_addpsat:
14801	case Hexagon::A2_addsph:
14802	case Hexagon::A2_addspl:
14803	case Hexagon::A2_andp:
14804	case Hexagon::A2_maxp:
14805	case Hexagon::A2_maxup:
14806	case Hexagon::A2_orp:
14807	case Hexagon::A2_vaddh:
14808	case Hexagon::A2_vaddhs:
14809	case Hexagon::A2_vaddub:
14810	case Hexagon::A2_vaddubs:
14811	case Hexagon::A2_vadduhs:
14812	case Hexagon::A2_vaddw:
14813	case Hexagon::A2_vaddws:
14814	case Hexagon::A2_vavgh:
14815	case Hexagon::A2_vavghcr:
14816	case Hexagon::A2_vavghr:
14817	case Hexagon::A2_vavgub:
14818	case Hexagon::A2_vavgubr:
14819	case Hexagon::A2_vavguh:
14820	case Hexagon::A2_vavguhr:
14821	case Hexagon::A2_vavguw:
14822	case Hexagon::A2_vavguwr:
14823	case Hexagon::A2_vavgw:
14824	case Hexagon::A2_vavgwcr:
14825	case Hexagon::A2_vavgwr:
14826	case Hexagon::A2_vraddub:
14827	case Hexagon::A2_vrsadub:
14828	case Hexagon::A2_xorp:
14829	case Hexagon::F2_dfadd:
14830	case Hexagon::F2_dfmax:
14831	case Hexagon::F2_dfmin:
14832	case Hexagon::F2_dfmpyfix:
14833	case Hexagon::F2_dfmpyll:
14834	case Hexagon::F2_dfsub:
14835	case Hexagon::M2_mmpyh_rs0:
14836	case Hexagon::M2_mmpyh_rs1:
14837	case Hexagon::M2_mmpyh_s0:
14838	case Hexagon::M2_mmpyh_s1:
14839	case Hexagon::M2_mmpyl_rs0:
14840	case Hexagon::M2_mmpyl_rs1:
14841	case Hexagon::M2_mmpyl_s0:
14842	case Hexagon::M2_mmpyl_s1:
14843	case Hexagon::M2_mmpyuh_rs0:
14844	case Hexagon::M2_mmpyuh_rs1:
14845	case Hexagon::M2_mmpyuh_s0:
14846	case Hexagon::M2_mmpyuh_s1:
14847	case Hexagon::M2_mmpyul_rs0:
14848	case Hexagon::M2_mmpyul_rs1:
14849	case Hexagon::M2_mmpyul_s0:
14850	case Hexagon::M2_mmpyul_s1:
14851	case Hexagon::M2_vcmpy_s0_sat_i:
14852	case Hexagon::M2_vcmpy_s0_sat_r:
14853	case Hexagon::M2_vcmpy_s1_sat_i:
14854	case Hexagon::M2_vcmpy_s1_sat_r:
14855	case Hexagon::M2_vdmpys_s0:
14856	case Hexagon::M2_vdmpys_s1:
14857	case Hexagon::M2_vmpy2es_s0:
14858	case Hexagon::M2_vmpy2es_s1:
14859	case Hexagon::M2_vrcmpyi_s0:
14860	case Hexagon::M2_vrcmpyi_s0c:
14861	case Hexagon::M2_vrcmpyr_s0:
14862	case Hexagon::M2_vrcmpyr_s0c:
14863	case Hexagon::M2_vrcmpys_s1_h:
14864	case Hexagon::M2_vrcmpys_s1_l:
14865	case Hexagon::M2_vrmpy_s0:
14866	case Hexagon::M4_vrmpyeh_s0:
14867	case Hexagon::M4_vrmpyeh_s1:
14868	case Hexagon::M4_vrmpyoh_s0:
14869	case Hexagon::M4_vrmpyoh_s1:
14870	case Hexagon::M5_vdmpybsu:
14871	case Hexagon::M5_vrmpybsu:
14872	case Hexagon::M5_vrmpybuu:
14873	case Hexagon::M7_dcmpyiw:
14874	case Hexagon::M7_dcmpyiwc:
14875	case Hexagon::M7_dcmpyrw:
14876	case Hexagon::M7_dcmpyrwc:
14877	case Hexagon::S2_cabacdecbin:
14878	case Hexagon::S2_extractup_rp:
14879	case Hexagon::S2_lfsp:
14880	case Hexagon::S2_shuffeb:
14881	case Hexagon::S2_shuffeh:
14882	case Hexagon::S2_vtrunewh:
14883	case Hexagon::S2_vtrunowh:
14884	case Hexagon::S4_extractp_rp:
14885	case Hexagon::S4_vxaddsubh:
14886	case Hexagon::S4_vxaddsubhr:
14887	case Hexagon::S4_vxaddsubw:
14888	case Hexagon::S4_vxsubaddh:
14889	case Hexagon::S4_vxsubaddhr:
14890	case Hexagon::S4_vxsubaddw:
14891	case Hexagon::S6_vtrunehb_ppp:
14892	case Hexagon::S6_vtrunohb_ppp: {
14893	switch (OpNum) {
14894	case `1`:
14895	// op: Rss32
14896	return `16`;
14897	case `2`:
14898	// op: Rtt32
14899	return `8`;
14900	case `0`:
14901	// op: Rdd32
14902	return `0`;
14903	}
14904	break;
14905	}
14906	case Hexagon::S2_vsplicerb: {
14907	switch (OpNum) {
14908	case `1`:
14909	// op: Rss32
14910	return `16`;
14911	case `2`:
14912	// op: Rtt32
14913	return `8`;
14914	case `3`:
14915	// op: Pu4
14916	return `5`;
14917	case `0`:
14918	// op: Rdd32
14919	return `0`;
14920	}
14921	break;
14922	}
14923	case Hexagon::V6_pred_scalar2:
14924	case Hexagon::V6_pred_scalar2v2: {
14925	switch (OpNum) {
14926	case `1`:
14927	// op: Rt32
14928	return `16`;
14929	case `0`:
14930	// op: Qd4
14931	return `0`;
14932	}
14933	break;
14934	}
14935	case Hexagon::V6_lvsplatb:
14936	case Hexagon::V6_lvsplath:
14937	case Hexagon::V6_lvsplatw:
14938	case Hexagon::V6_zextract: {
14939	switch (OpNum) {
14940	case `1`:
14941	// op: Rt32
14942	return `16`;
14943	case `0`:
14944	// op: Vd32
14945	return `0`;
14946	}
14947	break;
14948	}
14949	case Hexagon::A2_addh_h16_hh:
14950	case Hexagon::A2_addh_h16_hl:
14951	case Hexagon::A2_addh_h16_lh:
14952	case Hexagon::A2_addh_h16_ll:
14953	case Hexagon::A2_addh_h16_sat_hh:
14954	case Hexagon::A2_addh_h16_sat_hl:
14955	case Hexagon::A2_addh_h16_sat_lh:
14956	case Hexagon::A2_addh_h16_sat_ll:
14957	case Hexagon::A2_addh_l16_hl:
14958	case Hexagon::A2_addh_l16_ll:
14959	case Hexagon::A2_addh_l16_sat_hl:
14960	case Hexagon::A2_addh_l16_sat_ll:
14961	case Hexagon::A2_combine_hh:
14962	case Hexagon::A2_combine_hl:
14963	case Hexagon::A2_combine_lh:
14964	case Hexagon::A2_combine_ll:
14965	case Hexagon::A2_min:
14966	case Hexagon::A2_minu:
14967	case Hexagon::A2_sub:
14968	case Hexagon::A2_subh_h16_hh:
14969	case Hexagon::A2_subh_h16_hl:
14970	case Hexagon::A2_subh_h16_lh:
14971	case Hexagon::A2_subh_h16_ll:
14972	case Hexagon::A2_subh_h16_sat_hh:
14973	case Hexagon::A2_subh_h16_sat_hl:
14974	case Hexagon::A2_subh_h16_sat_lh:
14975	case Hexagon::A2_subh_h16_sat_ll:
14976	case Hexagon::A2_subh_l16_hl:
14977	case Hexagon::A2_subh_l16_ll:
14978	case Hexagon::A2_subh_l16_sat_hl:
14979	case Hexagon::A2_subh_l16_sat_ll:
14980	case Hexagon::A2_subsat:
14981	case Hexagon::A2_svnavgh:
14982	case Hexagon::A2_svsubh:
14983	case Hexagon::A2_svsubhs:
14984	case Hexagon::A2_svsubuhs:
14985	case Hexagon::A4_andn:
14986	case Hexagon::A4_orn:
14987	case Hexagon::dep_A2_subsat: {
14988	switch (OpNum) {
14989	case `1`:
14990	// op: Rt32
14991	return `8`;
14992	case `2`:
14993	// op: Rs32
14994	return `16`;
14995	case `0`:
14996	// op: Rd32
14997	return `0`;
14998	}
14999	break;
15000	}
15001	case Hexagon::A2_minp:
15002	case Hexagon::A2_minup:
15003	case Hexagon::A2_subp:
15004	case Hexagon::A2_vmaxb:
15005	case Hexagon::A2_vmaxh:
15006	case Hexagon::A2_vmaxub:
15007	case Hexagon::A2_vmaxuh:
15008	case Hexagon::A2_vmaxuw:
15009	case Hexagon::A2_vmaxw:
15010	case Hexagon::A2_vminb:
15011	case Hexagon::A2_vminh:
15012	case Hexagon::A2_vminub:
15013	case Hexagon::A2_vminuh:
15014	case Hexagon::A2_vminuw:
15015	case Hexagon::A2_vminw:
15016	case Hexagon::A2_vnavgh:
15017	case Hexagon::A2_vnavghcr:
15018	case Hexagon::A2_vnavghr:
15019	case Hexagon::A2_vnavgw:
15020	case Hexagon::A2_vnavgwcr:
15021	case Hexagon::A2_vnavgwr:
15022	case Hexagon::A2_vsubh:
15023	case Hexagon::A2_vsubhs:
15024	case Hexagon::A2_vsubub:
15025	case Hexagon::A2_vsububs:
15026	case Hexagon::A2_vsubuhs:
15027	case Hexagon::A2_vsubw:
15028	case Hexagon::A2_vsubws:
15029	case Hexagon::A4_andnp:
15030	case Hexagon::A4_ornp:
15031	case Hexagon::M2_vabsdiffh:
15032	case Hexagon::M2_vabsdiffw:
15033	case Hexagon::M6_vabsdiffb:
15034	case Hexagon::M6_vabsdiffub:
15035	case Hexagon::S2_shuffob:
15036	case Hexagon::S2_shuffoh: {
15037	switch (OpNum) {
15038	case `1`:
15039	// op: Rtt32
15040	return `8`;
15041	case `2`:
15042	// op: Rss32
15043	return `16`;
15044	case `0`:
15045	// op: Rdd32
15046	return `0`;
15047	}
15048	break;
15049	}
15050	case Hexagon::S2_valignrb: {
15051	switch (OpNum) {
15052	case `1`:
15053	// op: Rtt32
15054	return `8`;
15055	case `2`:
15056	// op: Rss32
15057	return `16`;
15058	case `3`:
15059	// op: Pu4
15060	return `5`;
15061	case `0`:
15062	// op: Rdd32
15063	return `0`;
15064	}
15065	break;
15066	}
15067	case Hexagon::M4_mpyrr_addr: {
15068	switch (OpNum) {
15069	case `1`:
15070	// op: Ru32
15071	return `0`;
15072	case `3`:
15073	// op: Rs32
15074	return `16`;
15075	case `0`:
15076	// op: Ry32
15077	return `8`;
15078	}
15079	break;
15080	}
15081	case Hexagon::Y2_tfrscrr: {
15082	switch (OpNum) {
15083	case `1`:
15084	// op: Ss128
15085	return `16`;
15086	case `0`:
15087	// op: Rd32
15088	return `0`;
15089	}
15090	break;
15091	}
15092	case Hexagon::Y4_tfrscpp: {
15093	switch (OpNum) {
15094	case `1`:
15095	// op: Sss128
15096	return `16`;
15097	case `0`:
15098	// op: Rdd32
15099	return `0`;
15100	}
15101	break;
15102	}
15103	case Hexagon::V6_vabs_hf:
15104	case Hexagon::V6_vabs_sf:
15105	case Hexagon::V6_vabsb:
15106	case Hexagon::V6_vabsb_sat:
15107	case Hexagon::V6_vabsh:
15108	case Hexagon::V6_vabsh_sat:
15109	case Hexagon::V6_vabsw:
15110	case Hexagon::V6_vabsw_sat:
15111	case Hexagon::V6_vassign:
15112	case Hexagon::V6_vassign_fp:
15113	case Hexagon::V6_vassign_tmp:
15114	case Hexagon::V6_vcl0h:
15115	case Hexagon::V6_vcl0w:
15116	case Hexagon::V6_vconv_h_hf:
15117	case Hexagon::V6_vconv_hf_h:
15118	case Hexagon::V6_vconv_hf_qf16:
15119	case Hexagon::V6_vconv_sf_qf32:
15120	case Hexagon::V6_vconv_sf_w:
15121	case Hexagon::V6_vconv_w_sf:
15122	case Hexagon::V6_vcvt_h_hf:
15123	case Hexagon::V6_vcvt_hf_h:
15124	case Hexagon::V6_vcvt_hf_uh:
15125	case Hexagon::V6_vcvt_uh_hf:
15126	case Hexagon::V6_vdealb:
15127	case Hexagon::V6_vdealh:
15128	case Hexagon::V6_vfneg_hf:
15129	case Hexagon::V6_vfneg_sf:
15130	case Hexagon::V6_vnormamth:
15131	case Hexagon::V6_vnormamtw:
15132	case Hexagon::V6_vnot:
15133	case Hexagon::V6_vpopcounth:
15134	case Hexagon::V6_vshuffb:
15135	case Hexagon::V6_vshuffh: {
15136	switch (OpNum) {
15137	case `1`:
15138	// op: Vu32
15139	return `8`;
15140	case `0`:
15141	// op: Vd32
15142	return `0`;
15143	}
15144	break;
15145	}
15146	case Hexagon::V6_vcvt_hf_b:
15147	case Hexagon::V6_vcvt_hf_ub:
15148	case Hexagon::V6_vcvt_sf_hf:
15149	case Hexagon::V6_vsb:
15150	case Hexagon::V6_vsh:
15151	case Hexagon::V6_vunpackb:
15152	case Hexagon::V6_vunpackh:
15153	case Hexagon::V6_vunpackub:
15154	case Hexagon::V6_vunpackuh:
15155	case Hexagon::V6_vzb:
15156	case Hexagon::V6_vzh: {
15157	switch (OpNum) {
15158	case `1`:
15159	// op: Vu32
15160	return `8`;
15161	case `0`:
15162	// op: Vdd32
15163	return `0`;
15164	}
15165	break;
15166	}
15167	case Hexagon::V6_extractw: {
15168	switch (OpNum) {
15169	case `1`:
15170	// op: Vu32
15171	return `8`;
15172	case `2`:
15173	// op: Rs32
15174	return `16`;
15175	case `0`:
15176	// op: Rd32
15177	return `0`;
15178	}
15179	break;
15180	}
15181	case Hexagon::V6_vandvrt: {
15182	switch (OpNum) {
15183	case `1`:
15184	// op: Vu32
15185	return `8`;
15186	case `2`:
15187	// op: Rt32
15188	return `16`;
15189	case `0`:
15190	// op: Qd4
15191	return `0`;
15192	}
15193	break;
15194	}
15195	case Hexagon::V6_vaslh:
15196	case Hexagon::V6_vaslw:
15197	case Hexagon::V6_vasrh:
15198	case Hexagon::V6_vasrw:
15199	case Hexagon::V6_vdmpybus:
15200	case Hexagon::V6_vdmpyhb:
15201	case Hexagon::V6_vdmpyhsat:
15202	case Hexagon::V6_vdmpyhsusat:
15203	case Hexagon::V6_vlsrb:
15204	case Hexagon::V6_vlsrh:
15205	case Hexagon::V6_vlsrw:
15206	case Hexagon::V6_vmpyhsrs:
15207	case Hexagon::V6_vmpyhss:
15208	case Hexagon::V6_vmpyihb:
15209	case Hexagon::V6_vmpyiwb:
15210	case Hexagon::V6_vmpyiwh:
15211	case Hexagon::V6_vmpyiwub:
15212	case Hexagon::V6_vmpyuhe:
15213	case Hexagon::V6_vrmpybus:
15214	case Hexagon::V6_vrmpyub:
15215	case Hexagon::V6_vror: {
15216	switch (OpNum) {
15217	case `1`:
15218	// op: Vu32
15219	return `8`;
15220	case `2`:
15221	// op: Rt32
15222	return `16`;
15223	case `0`:
15224	// op: Vd32
15225	return `0`;
15226	}
15227	break;
15228	}
15229	case Hexagon::V6_vmpybus:
15230	case Hexagon::V6_vmpyh:
15231	case Hexagon::V6_vmpyub:
15232	case Hexagon::V6_vmpyuh: {
15233	switch (OpNum) {
15234	case `1`:
15235	// op: Vu32
15236	return `8`;
15237	case `2`:
15238	// op: Rt32
15239	return `16`;
15240	case `0`:
15241	// op: Vdd32
15242	return `0`;
15243	}
15244	break;
15245	}
15246	case Hexagon::V6_vrmpyzbb_rt:
15247	case Hexagon::V6_vrmpyzbub_rt:
15248	case Hexagon::V6_vrmpyzcb_rt:
15249	case Hexagon::V6_vrmpyzcbs_rt:
15250	case Hexagon::V6_vrmpyznb_rt: {
15251	switch (OpNum) {
15252	case `1`:
15253	// op: Vu32
15254	return `8`;
15255	case `2`:
15256	// op: Rt8
15257	return `16`;
15258	case `0`:
15259	// op: Vdddd32
15260	return `0`;
15261	}
15262	break;
15263	}
15264	case Hexagon::V6_vlut4: {
15265	switch (OpNum) {
15266	case `1`:
15267	// op: Vu32
15268	return `8`;
15269	case `2`:
15270	// op: Rtt32
15271	return `16`;
15272	case `0`:
15273	// op: Vd32
15274	return `0`;
15275	}
15276	break;
15277	}
15278	case Hexagon::V6_vrmpybub_rtt:
15279	case Hexagon::V6_vrmpyub_rtt: {
15280	switch (OpNum) {
15281	case `1`:
15282	// op: Vu32
15283	return `8`;
15284	case `2`:
15285	// op: Rtt32
15286	return `16`;
15287	case `0`:
15288	// op: Vdd32
15289	return `0`;
15290	}
15291	break;
15292	}
15293	case Hexagon::V6_veqb:
15294	case Hexagon::V6_veqh:
15295	case Hexagon::V6_veqw:
15296	case Hexagon::V6_vgtb:
15297	case Hexagon::V6_vgtbf:
15298	case Hexagon::V6_vgth:
15299	case Hexagon::V6_vgthf:
15300	case Hexagon::V6_vgtsf:
15301	case Hexagon::V6_vgtub:
15302	case Hexagon::V6_vgtuh:
15303	case Hexagon::V6_vgtuw:
15304	case Hexagon::V6_vgtw: {
15305	switch (OpNum) {
15306	case `1`:
15307	// op: Vu32
15308	return `8`;
15309	case `2`:
15310	// op: Vv32
15311	return `16`;
15312	case `0`:
15313	// op: Qd4
15314	return `0`;
15315	}
15316	break;
15317	}
15318	case Hexagon::V6_vabsdiffh:
15319	case Hexagon::V6_vabsdiffub:
15320	case Hexagon::V6_vabsdiffuh:
15321	case Hexagon::V6_vabsdiffw:
15322	case Hexagon::V6_vadd_hf:
15323	case Hexagon::V6_vadd_hf_hf:
15324	case Hexagon::V6_vadd_qf16:
15325	case Hexagon::V6_vadd_qf16_mix:
15326	case Hexagon::V6_vadd_qf32:
15327	case Hexagon::V6_vadd_qf32_mix:
15328	case Hexagon::V6_vadd_sf:
15329	case Hexagon::V6_vadd_sf_sf:
15330	case Hexagon::V6_vaddb:
15331	case Hexagon::V6_vaddbsat:
15332	case Hexagon::V6_vaddclbh:
15333	case Hexagon::V6_vaddclbw:
15334	case Hexagon::V6_vaddh:
15335	case Hexagon::V6_vaddhsat:
15336	case Hexagon::V6_vaddubsat:
15337	case Hexagon::V6_vaddububb_sat:
15338	case Hexagon::V6_vadduhsat:
15339	case Hexagon::V6_vadduwsat:
15340	case Hexagon::V6_vaddw:
15341	case Hexagon::V6_vaddwsat:
15342	case Hexagon::V6_vand:
15343	case Hexagon::V6_vaslhv:
15344	case Hexagon::V6_vaslwv:
15345	case Hexagon::V6_vasrhv:
15346	case Hexagon::V6_vasrwv:
15347	case Hexagon::V6_vavgb:
15348	case Hexagon::V6_vavgbrnd:
15349	case Hexagon::V6_vavgh:
15350	case Hexagon::V6_vavghrnd:
15351	case Hexagon::V6_vavgub:
15352	case Hexagon::V6_vavgubrnd:
15353	case Hexagon::V6_vavguh:
15354	case Hexagon::V6_vavguhrnd:
15355	case Hexagon::V6_vavguw:
15356	case Hexagon::V6_vavguwrnd:
15357	case Hexagon::V6_vavgw:
15358	case Hexagon::V6_vavgwrnd:
15359	case Hexagon::V6_vcvt_b_hf:
15360	case Hexagon::V6_vcvt_bf_sf:
15361	case Hexagon::V6_vcvt_hf_sf:
15362	case Hexagon::V6_vcvt_ub_hf:
15363	case Hexagon::V6_vdealb4w:
15364	case Hexagon::V6_vdelta:
15365	case Hexagon::V6_vdmpy_sf_hf:
15366	case Hexagon::V6_vdmpyhvsat:
15367	case Hexagon::V6_vfmax_hf:
15368	case Hexagon::V6_vfmax_sf:
15369	case Hexagon::V6_vfmin_hf:
15370	case Hexagon::V6_vfmin_sf:
15371	case Hexagon::V6_vlsrhv:
15372	case Hexagon::V6_vlsrwv:
15373	case Hexagon::V6_vmax_bf:
15374	case Hexagon::V6_vmax_hf:
15375	case Hexagon::V6_vmax_sf:
15376	case Hexagon::V6_vmaxb:
15377	case Hexagon::V6_vmaxh:
15378	case Hexagon::V6_vmaxub:
15379	case Hexagon::V6_vmaxuh:
15380	case Hexagon::V6_vmaxw:
15381	case Hexagon::V6_vmin_bf:
15382	case Hexagon::V6_vmin_hf:
15383	case Hexagon::V6_vmin_sf:
15384	case Hexagon::V6_vminb:
15385	case Hexagon::V6_vminh:
15386	case Hexagon::V6_vminub:
15387	case Hexagon::V6_vminuh:
15388	case Hexagon::V6_vminw:
15389	case Hexagon::V6_vmpy_hf_hf:
15390	case Hexagon::V6_vmpy_qf16:
15391	case Hexagon::V6_vmpy_qf16_hf:
15392	case Hexagon::V6_vmpy_qf16_mix_hf:
15393	case Hexagon::V6_vmpy_qf32:
15394	case Hexagon::V6_vmpy_qf32_sf:
15395	case Hexagon::V6_vmpy_sf_sf:
15396	case Hexagon::V6_vmpyewuh:
15397	case Hexagon::V6_vmpyhvsrs:
15398	case Hexagon::V6_vmpyieoh:
15399	case Hexagon::V6_vmpyiewuh:
15400	case Hexagon::V6_vmpyih:
15401	case Hexagon::V6_vmpyiowh:
15402	case Hexagon::V6_vmpyowh:
15403	case Hexagon::V6_vmpyowh_rnd:
15404	case Hexagon::V6_vmpyuhvs:
15405	case Hexagon::V6_vnavgb:
15406	case Hexagon::V6_vnavgh:
15407	case Hexagon::V6_vnavgub:
15408	case Hexagon::V6_vnavgw:
15409	case Hexagon::V6_vor:
15410	case Hexagon::V6_vpackeb:
15411	case Hexagon::V6_vpackeh:
15412	case Hexagon::V6_vpackhb_sat:
15413	case Hexagon::V6_vpackhub_sat:
15414	case Hexagon::V6_vpackob:
15415	case Hexagon::V6_vpackoh:
15416	case Hexagon::V6_vpackwh_sat:
15417	case Hexagon::V6_vpackwuh_sat:
15418	case Hexagon::V6_vrdelta:
15419	case Hexagon::V6_vrmpybusv:
15420	case Hexagon::V6_vrmpybv:
15421	case Hexagon::V6_vrmpyubv:
15422	case Hexagon::V6_vrotr:
15423	case Hexagon::V6_vroundhb:
15424	case Hexagon::V6_vroundhub:
15425	case Hexagon::V6_vrounduhub:
15426	case Hexagon::V6_vrounduwuh:
15427	case Hexagon::V6_vroundwh:
15428	case Hexagon::V6_vroundwuh:
15429	case Hexagon::V6_vsatdw:
15430	case Hexagon::V6_vsathub:
15431	case Hexagon::V6_vsatuwuh:
15432	case Hexagon::V6_vsatwh:
15433	case Hexagon::V6_vshufeh:
15434	case Hexagon::V6_vshuffeb:
15435	case Hexagon::V6_vshuffob:
15436	case Hexagon::V6_vshufoh:
15437	case Hexagon::V6_vsub_hf:
15438	case Hexagon::V6_vsub_hf_hf:
15439	case Hexagon::V6_vsub_qf16:
15440	case Hexagon::V6_vsub_qf16_mix:
15441	case Hexagon::V6_vsub_qf32:
15442	case Hexagon::V6_vsub_qf32_mix:
15443	case Hexagon::V6_vsub_sf:
15444	case Hexagon::V6_vsub_sf_sf:
15445	case Hexagon::V6_vsubb:
15446	case Hexagon::V6_vsubbsat:
15447	case Hexagon::V6_vsubh:
15448	case Hexagon::V6_vsubhsat:
15449	case Hexagon::V6_vsububsat:
15450	case Hexagon::V6_vsubububb_sat:
15451	case Hexagon::V6_vsubuhsat:
15452	case Hexagon::V6_vsubuwsat:
15453	case Hexagon::V6_vsubw:
15454	case Hexagon::V6_vsubwsat:
15455	case Hexagon::V6_vxor: {
15456	switch (OpNum) {
15457	case `1`:
15458	// op: Vu32
15459	return `8`;
15460	case `2`:
15461	// op: Vv32
15462	return `16`;
15463	case `0`:
15464	// op: Vd32
15465	return `0`;
15466	}
15467	break;
15468	}
15469	case Hexagon::V6_vadd_sf_bf:
15470	case Hexagon::V6_vadd_sf_hf:
15471	case Hexagon::V6_vaddhw:
15472	case Hexagon::V6_vaddubh:
15473	case Hexagon::V6_vadduhw:
15474	case Hexagon::V6_vcombine:
15475	case Hexagon::V6_vcombine_tmp:
15476	case Hexagon::V6_vmpy_qf32_hf:
15477	case Hexagon::V6_vmpy_qf32_mix_hf:
15478	case Hexagon::V6_vmpy_qf32_qf16:
15479	case Hexagon::V6_vmpy_sf_bf:
15480	case Hexagon::V6_vmpy_sf_hf:
15481	case Hexagon::V6_vmpybusv:
15482	case Hexagon::V6_vmpybv:
15483	case Hexagon::V6_vmpyewuh_64:
15484	case Hexagon::V6_vmpyhus:
15485	case Hexagon::V6_vmpyhv:
15486	case Hexagon::V6_vmpyubv:
15487	case Hexagon::V6_vmpyuhv:
15488	case Hexagon::V6_vshufoeb:
15489	case Hexagon::V6_vshufoeh:
15490	case Hexagon::V6_vsub_sf_bf:
15491	case Hexagon::V6_vsub_sf_hf:
15492	case Hexagon::V6_vsubhw:
15493	case Hexagon::V6_vsububh:
15494	case Hexagon::V6_vsubuhw: {
15495	switch (OpNum) {
15496	case `1`:
15497	// op: Vu32
15498	return `8`;
15499	case `2`:
15500	// op: Vv32
15501	return `16`;
15502	case `0`:
15503	// op: Vdd32
15504	return `0`;
15505	}
15506	break;
15507	}
15508	case Hexagon::V6_vaddcarrysat: {
15509	switch (OpNum) {
15510	case `1`:
15511	// op: Vu32
15512	return `8`;
15513	case `2`:
15514	// op: Vv32
15515	return `16`;
15516	case `3`:
15517	// op: Qs4
15518	return `5`;
15519	case `0`:
15520	// op: Vd32
15521	return `0`;
15522	}
15523	break;
15524	}
15525	case Hexagon::V6_valignb:
15526	case Hexagon::V6_vasrhbrndsat:
15527	case Hexagon::V6_vasrhbsat:
15528	case Hexagon::V6_vasrhubrndsat:
15529	case Hexagon::V6_vasrhubsat:
15530	case Hexagon::V6_vasruhubrndsat:
15531	case Hexagon::V6_vasruhubsat:
15532	case Hexagon::V6_vasruwuhrndsat:
15533	case Hexagon::V6_vasruwuhsat:
15534	case Hexagon::V6_vasrwh:
15535	case Hexagon::V6_vasrwhrndsat:
15536	case Hexagon::V6_vasrwhsat:
15537	case Hexagon::V6_vasrwuhrndsat:
15538	case Hexagon::V6_vasrwuhsat:
15539	case Hexagon::V6_vlalignb:
15540	case Hexagon::V6_vlutvvb:
15541	case Hexagon::V6_vlutvvb_nm: {
15542	switch (OpNum) {
15543	case `1`:
15544	// op: Vu32
15545	return `8`;
15546	case `2`:
15547	// op: Vv32
15548	return `19`;
15549	case `3`:
15550	// op: Rt8
15551	return `16`;
15552	case `0`:
15553	// op: Vd32
15554	return `0`;
15555	}
15556	break;
15557	}
15558	case Hexagon::V6_vdealvdd:
15559	case Hexagon::V6_vlutvwh:
15560	case Hexagon::V6_vlutvwh_nm:
15561	case Hexagon::V6_vshuffvdd: {
15562	switch (OpNum) {
15563	case `1`:
15564	// op: Vu32
15565	return `8`;
15566	case `2`:
15567	// op: Vv32
15568	return `19`;
15569	case `3`:
15570	// op: Rt8
15571	return `16`;
15572	case `0`:
15573	// op: Vdd32
15574	return `0`;
15575	}
15576	break;
15577	}
15578	case Hexagon::V6_vconv_hf_qf32: {
15579	switch (OpNum) {
15580	case `1`:
15581	// op: Vuu32
15582	return `8`;
15583	case `0`:
15584	// op: Vd32
15585	return `0`;
15586	}
15587	break;
15588	}
15589	case Hexagon::V6_vdmpyhisat:
15590	case Hexagon::V6_vdmpyhsuisat: {
15591	switch (OpNum) {
15592	case `1`:
15593	// op: Vuu32
15594	return `8`;
15595	case `2`:
15596	// op: Rt32
15597	return `16`;
15598	case `0`:
15599	// op: Vd32
15600	return `0`;
15601	}
15602	break;
15603	}
15604	case Hexagon::V6_vdmpybus_dv:
15605	case Hexagon::V6_vdmpyhb_dv:
15606	case Hexagon::V6_vdsaduh:
15607	case Hexagon::V6_vmpabus:
15608	case Hexagon::V6_vmpabuu:
15609	case Hexagon::V6_vmpahb:
15610	case Hexagon::V6_vmpauhb:
15611	case Hexagon::V6_vtmpyb:
15612	case Hexagon::V6_vtmpybus:
15613	case Hexagon::V6_vtmpyhb: {
15614	switch (OpNum) {
15615	case `1`:
15616	// op: Vuu32
15617	return `8`;
15618	case `2`:
15619	// op: Rt32
15620	return `16`;
15621	case `0`:
15622	// op: Vdd32
15623	return `0`;
15624	}
15625	break;
15626	}
15627	case Hexagon::V6_vasrvuhubrndsat:
15628	case Hexagon::V6_vasrvuhubsat:
15629	case Hexagon::V6_vasrvwuhrndsat:
15630	case Hexagon::V6_vasrvwuhsat: {
15631	switch (OpNum) {
15632	case `1`:
15633	// op: Vuu32
15634	return `8`;
15635	case `2`:
15636	// op: Vv32
15637	return `16`;
15638	case `0`:
15639	// op: Vd32
15640	return `0`;
15641	}
15642	break;
15643	}
15644	case Hexagon::V6_vaddb_dv:
15645	case Hexagon::V6_vaddbsat_dv:
15646	case Hexagon::V6_vaddh_dv:
15647	case Hexagon::V6_vaddhsat_dv:
15648	case Hexagon::V6_vaddubsat_dv:
15649	case Hexagon::V6_vadduhsat_dv:
15650	case Hexagon::V6_vadduwsat_dv:
15651	case Hexagon::V6_vaddw_dv:
15652	case Hexagon::V6_vaddwsat_dv:
15653	case Hexagon::V6_vmpabusv:
15654	case Hexagon::V6_vmpabuuv:
15655	case Hexagon::V6_vsubb_dv:
15656	case Hexagon::V6_vsubbsat_dv:
15657	case Hexagon::V6_vsubh_dv:
15658	case Hexagon::V6_vsubhsat_dv:
15659	case Hexagon::V6_vsububsat_dv:
15660	case Hexagon::V6_vsubuhsat_dv:
15661	case Hexagon::V6_vsubuwsat_dv:
15662	case Hexagon::V6_vsubw_dv:
15663	case Hexagon::V6_vsubwsat_dv: {
15664	switch (OpNum) {
15665	case `1`:
15666	// op: Vuu32
15667	return `8`;
15668	case `2`:
15669	// op: Vvv32
15670	return `16`;
15671	case `0`:
15672	// op: Vdd32
15673	return `0`;
15674	}
15675	break;
15676	}
15677	case Hexagon::L4_loadbsw2_ap:
15678	case Hexagon::L4_loadbzw2_ap:
15679	case Hexagon::L4_loadrb_ap:
15680	case Hexagon::L4_loadrh_ap:
15681	case Hexagon::L4_loadri_ap:
15682	case Hexagon::L4_loadrub_ap:
15683	case Hexagon::L4_loadruh_ap: {
15684	switch (OpNum) {
15685	case `2`:
15686	// op: II
15687	return `5`;
15688	case `0`:
15689	// op: Rd32
15690	return `0`;
15691	case `1`:
15692	// op: Re32
15693	return `16`;
15694	}
15695	break;
15696	}
15697	case Hexagon::L4_loadbsw4_ap:
15698	case Hexagon::L4_loadbzw4_ap:
15699	case Hexagon::L4_loadrd_ap: {
15700	switch (OpNum) {
15701	case `2`:
15702	// op: II
15703	return `5`;
15704	case `0`:
15705	// op: Rdd32
15706	return `0`;
15707	case `1`:
15708	// op: Re32
15709	return `16`;
15710	}
15711	break;
15712	}
15713	case Hexagon::A2_tfrih:
15714	case Hexagon::A2_tfril:
15715	case Hexagon::S2_allocframe: {
15716	switch (OpNum) {
15717	case `2`:
15718	// op: Ii
15719	return `0`;
15720	case `0`:
15721	// op: Rx32
15722	return `16`;
15723	}
15724	break;
15725	}
15726	case Hexagon::J4_cmpeq_f_jumpnv_nt:
15727	case Hexagon::J4_cmpeq_f_jumpnv_t:
15728	case Hexagon::J4_cmpeq_t_jumpnv_nt:
15729	case Hexagon::J4_cmpeq_t_jumpnv_t:
15730	case Hexagon::J4_cmpgt_f_jumpnv_nt:
15731	case Hexagon::J4_cmpgt_f_jumpnv_t:
15732	case Hexagon::J4_cmpgt_t_jumpnv_nt:
15733	case Hexagon::J4_cmpgt_t_jumpnv_t:
15734	case Hexagon::J4_cmpgtu_f_jumpnv_nt:
15735	case Hexagon::J4_cmpgtu_f_jumpnv_t:
15736	case Hexagon::J4_cmpgtu_t_jumpnv_nt:
15737	case Hexagon::J4_cmpgtu_t_jumpnv_t: {
15738	switch (OpNum) {
15739	case `2`:
15740	// op: Ii
15741	return `1`;
15742	case `0`:
15743	// op: Ns8
15744	return `16`;
15745	case `1`:
15746	// op: Rt32
15747	return `8`;
15748	}
15749	break;
15750	}
15751	case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
15752	case Hexagon::J4_cmpeqn1_f_jumpnv_t:
15753	case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
15754	case Hexagon::J4_cmpeqn1_t_jumpnv_t:
15755	case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
15756	case Hexagon::J4_cmpgtn1_f_jumpnv_t:
15757	case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
15758	case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
15759	switch (OpNum) {
15760	case `2`:
15761	// op: Ii
15762	return `1`;
15763	case `0`:
15764	// op: Ns8
15765	return `16`;
15766	}
15767	break;
15768	}
15769	case Hexagon::J4_cmpeq_fp0_jump_nt:
15770	case Hexagon::J4_cmpeq_fp0_jump_t:
15771	case Hexagon::J4_cmpeq_fp1_jump_nt:
15772	case Hexagon::J4_cmpeq_fp1_jump_t:
15773	case Hexagon::J4_cmpeq_tp0_jump_nt:
15774	case Hexagon::J4_cmpeq_tp0_jump_t:
15775	case Hexagon::J4_cmpeq_tp1_jump_nt:
15776	case Hexagon::J4_cmpeq_tp1_jump_t:
15777	case Hexagon::J4_cmpgt_fp0_jump_nt:
15778	case Hexagon::J4_cmpgt_fp0_jump_t:
15779	case Hexagon::J4_cmpgt_fp1_jump_nt:
15780	case Hexagon::J4_cmpgt_fp1_jump_t:
15781	case Hexagon::J4_cmpgt_tp0_jump_nt:
15782	case Hexagon::J4_cmpgt_tp0_jump_t:
15783	case Hexagon::J4_cmpgt_tp1_jump_nt:
15784	case Hexagon::J4_cmpgt_tp1_jump_t:
15785	case Hexagon::J4_cmpgtu_fp0_jump_nt:
15786	case Hexagon::J4_cmpgtu_fp0_jump_t:
15787	case Hexagon::J4_cmpgtu_fp1_jump_nt:
15788	case Hexagon::J4_cmpgtu_fp1_jump_t:
15789	case Hexagon::J4_cmpgtu_tp0_jump_nt:
15790	case Hexagon::J4_cmpgtu_tp0_jump_t:
15791	case Hexagon::J4_cmpgtu_tp1_jump_nt:
15792	case Hexagon::J4_cmpgtu_tp1_jump_t: {
15793	switch (OpNum) {
15794	case `2`:
15795	// op: Ii
15796	return `1`;
15797	case `0`:
15798	// op: Rs16
15799	return `16`;
15800	case `1`:
15801	// op: Rt16
15802	return `8`;
15803	}
15804	break;
15805	}
15806	case Hexagon::J4_cmpeqn1_fp0_jump_nt:
15807	case Hexagon::J4_cmpeqn1_fp0_jump_t:
15808	case Hexagon::J4_cmpeqn1_fp1_jump_nt:
15809	case Hexagon::J4_cmpeqn1_fp1_jump_t:
15810	case Hexagon::J4_cmpeqn1_tp0_jump_nt:
15811	case Hexagon::J4_cmpeqn1_tp0_jump_t:
15812	case Hexagon::J4_cmpeqn1_tp1_jump_nt:
15813	case Hexagon::J4_cmpeqn1_tp1_jump_t:
15814	case Hexagon::J4_cmpgtn1_fp0_jump_nt:
15815	case Hexagon::J4_cmpgtn1_fp0_jump_t:
15816	case Hexagon::J4_cmpgtn1_fp1_jump_nt:
15817	case Hexagon::J4_cmpgtn1_fp1_jump_t:
15818	case Hexagon::J4_cmpgtn1_tp0_jump_nt:
15819	case Hexagon::J4_cmpgtn1_tp0_jump_t:
15820	case Hexagon::J4_cmpgtn1_tp1_jump_nt:
15821	case Hexagon::J4_cmpgtn1_tp1_jump_t: {
15822	switch (OpNum) {
15823	case `2`:
15824	// op: Ii
15825	return `1`;
15826	case `0`:
15827	// op: Rs16
15828	return `16`;
15829	}
15830	break;
15831	}
15832	case Hexagon::J4_cmplt_f_jumpnv_nt:
15833	case Hexagon::J4_cmplt_f_jumpnv_t:
15834	case Hexagon::J4_cmplt_t_jumpnv_nt:
15835	case Hexagon::J4_cmplt_t_jumpnv_t:
15836	case Hexagon::J4_cmpltu_f_jumpnv_nt:
15837	case Hexagon::J4_cmpltu_f_jumpnv_t:
15838	case Hexagon::J4_cmpltu_t_jumpnv_nt:
15839	case Hexagon::J4_cmpltu_t_jumpnv_t: {
15840	switch (OpNum) {
15841	case `2`:
15842	// op: Ii
15843	return `1`;
15844	case `0`:
15845	// op: Rt32
15846	return `8`;
15847	case `1`:
15848	// op: Ns8
15849	return `16`;
15850	}
15851	break;
15852	}
15853	case Hexagon::J4_jumpsetr: {
15854	switch (OpNum) {
15855	case `2`:
15856	// op: Ii
15857	return `1`;
15858	case `1`:
15859	// op: Rs16
15860	return `16`;
15861	case `0`:
15862	// op: Rd16
15863	return `8`;
15864	}
15865	break;
15866	}
15867	case Hexagon::J2_trap1: {
15868	switch (OpNum) {
15869	case `2`:
15870	// op: Ii
15871	return `2`;
15872	case `0`:
15873	// op: Rx32
15874	return `16`;
15875	}
15876	break;
15877	}
15878	case Hexagon::S2_pstorerbnewf_io:
15879	case Hexagon::S2_pstorerbnewt_io:
15880	case Hexagon::S2_pstorerhnewf_io:
15881	case Hexagon::S2_pstorerhnewt_io:
15882	case Hexagon::S2_pstorerinewf_io:
15883	case Hexagon::S2_pstorerinewt_io:
15884	case Hexagon::S4_pstorerbnewfnew_io:
15885	case Hexagon::S4_pstorerbnewtnew_io:
15886	case Hexagon::S4_pstorerhnewfnew_io:
15887	case Hexagon::S4_pstorerhnewtnew_io:
15888	case Hexagon::S4_pstorerinewfnew_io:
15889	case Hexagon::S4_pstorerinewtnew_io: {
15890	switch (OpNum) {
15891	case `2`:
15892	// op: Ii
15893	return `3`;
15894	case `0`:
15895	// op: Pv4
15896	return `0`;
15897	case `1`:
15898	// op: Rs32
15899	return `16`;
15900	case `3`:
15901	// op: Nt8
15902	return `8`;
15903	}
15904	break;
15905	}
15906	case Hexagon::S2_pstorerbf_io:
15907	case Hexagon::S2_pstorerbt_io:
15908	case Hexagon::S2_pstorerff_io:
15909	case Hexagon::S2_pstorerft_io:
15910	case Hexagon::S2_pstorerhf_io:
15911	case Hexagon::S2_pstorerht_io:
15912	case Hexagon::S2_pstorerif_io:
15913	case Hexagon::S2_pstorerit_io:
15914	case Hexagon::S4_pstorerbfnew_io:
15915	case Hexagon::S4_pstorerbtnew_io:
15916	case Hexagon::S4_pstorerffnew_io:
15917	case Hexagon::S4_pstorerftnew_io:
15918	case Hexagon::S4_pstorerhfnew_io:
15919	case Hexagon::S4_pstorerhtnew_io:
15920	case Hexagon::S4_pstorerifnew_io:
15921	case Hexagon::S4_pstoreritnew_io: {
15922	switch (OpNum) {
15923	case `2`:
15924	// op: Ii
15925	return `3`;
15926	case `0`:
15927	// op: Pv4
15928	return `0`;
15929	case `1`:
15930	// op: Rs32
15931	return `16`;
15932	case `3`:
15933	// op: Rt32
15934	return `8`;
15935	}
15936	break;
15937	}
15938	case Hexagon::S2_pstorerdf_io:
15939	case Hexagon::S2_pstorerdt_io:
15940	case Hexagon::S4_pstorerdfnew_io:
15941	case Hexagon::S4_pstorerdtnew_io: {
15942	switch (OpNum) {
15943	case `2`:
15944	// op: Ii
15945	return `3`;
15946	case `0`:
15947	// op: Pv4
15948	return `0`;
15949	case `1`:
15950	// op: Rs32
15951	return `16`;
15952	case `3`:
15953	// op: Rtt32
15954	return `8`;
15955	}
15956	break;
15957	}
15958	case Hexagon::S2_storerbnew_pci:
15959	case Hexagon::S2_storerhnew_pci:
15960	case Hexagon::S2_storerinew_pci: {
15961	switch (OpNum) {
15962	case `2`:
15963	// op: Ii
15964	return `3`;
15965	case `3`:
15966	// op: Mu2
15967	return `13`;
15968	case `4`:
15969	// op: Nt8
15970	return `8`;
15971	case `0`:
15972	// op: Rx32
15973	return `16`;
15974	}
15975	break;
15976	}
15977	case Hexagon::S2_storerb_pci:
15978	case Hexagon::S2_storerf_pci:
15979	case Hexagon::S2_storerh_pci:
15980	case Hexagon::S2_storeri_pci: {
15981	switch (OpNum) {
15982	case `2`:
15983	// op: Ii
15984	return `3`;
15985	case `3`:
15986	// op: Mu2
15987	return `13`;
15988	case `4`:
15989	// op: Rt32
15990	return `8`;
15991	case `0`:
15992	// op: Rx32
15993	return `16`;
15994	}
15995	break;
15996	}
15997	case Hexagon::S2_storerd_pci: {
15998	switch (OpNum) {
15999	case `2`:
16000	// op: Ii
16001	return `3`;
16002	case `3`:
16003	// op: Mu2
16004	return `13`;
16005	case `4`:
16006	// op: Rtt32
16007	return `8`;
16008	case `0`:
16009	// op: Rx32
16010	return `16`;
16011	}
16012	break;
16013	}
16014	case Hexagon::S2_storerbnew_pi:
16015	case Hexagon::S2_storerhnew_pi:
16016	case Hexagon::S2_storerinew_pi: {
16017	switch (OpNum) {
16018	case `2`:
16019	// op: Ii
16020	return `3`;
16021	case `3`:
16022	// op: Nt8
16023	return `8`;
16024	case `0`:
16025	// op: Rx32
16026	return `16`;
16027	}
16028	break;
16029	}
16030	case Hexagon::S2_storerb_pi:
16031	case Hexagon::S2_storerf_pi:
16032	case Hexagon::S2_storerh_pi:
16033	case Hexagon::S2_storeri_pi: {
16034	switch (OpNum) {
16035	case `2`:
16036	// op: Ii
16037	return `3`;
16038	case `3`:
16039	// op: Rt32
16040	return `8`;
16041	case `0`:
16042	// op: Rx32
16043	return `16`;
16044	}
16045	break;
16046	}
16047	case Hexagon::S2_storerd_pi: {
16048	switch (OpNum) {
16049	case `2`:
16050	// op: Ii
16051	return `3`;
16052	case `3`:
16053	// op: Rtt32
16054	return `8`;
16055	case `0`:
16056	// op: Rx32
16057	return `16`;
16058	}
16059	break;
16060	}
16061	case Hexagon::SA1_addi: {
16062	switch (OpNum) {
16063	case `2`:
16064	// op: Ii
16065	return `4`;
16066	case `0`:
16067	// op: Rx16
16068	return `0`;
16069	}
16070	break;
16071	}
16072	case Hexagon::C2_cmoveif:
16073	case Hexagon::C2_cmoveit:
16074	case Hexagon::C2_cmovenewif:
16075	case Hexagon::C2_cmovenewit: {
16076	switch (OpNum) {
16077	case `2`:
16078	// op: Ii
16079	return `5`;
16080	case `1`:
16081	// op: Pu4
16082	return `21`;
16083	case `0`:
16084	// op: Rd32
16085	return `0`;
16086	}
16087	break;
16088	}
16089	case Hexagon::C2_muxri: {
16090	switch (OpNum) {
16091	case `2`:
16092	// op: Ii
16093	return `5`;
16094	case `1`:
16095	// op: Pu4
16096	return `21`;
16097	case `3`:
16098	// op: Rs32
16099	return `16`;
16100	case `0`:
16101	// op: Rd32
16102	return `0`;
16103	}
16104	break;
16105	}
16106	case Hexagon::A4_cmpbeqi:
16107	case Hexagon::A4_cmpbgti:
16108	case Hexagon::A4_cmpbgtui:
16109	case Hexagon::A4_cmpheqi:
16110	case Hexagon::A4_cmphgti:
16111	case Hexagon::A4_cmphgtui:
16112	case Hexagon::C2_cmpeqi:
16113	case Hexagon::C2_cmpgti:
16114	case Hexagon::C2_cmpgtui:
16115	case Hexagon::C4_cmpltei:
16116	case Hexagon::C4_cmplteui:
16117	case Hexagon::C4_cmpneqi: {
16118	switch (OpNum) {
16119	case `2`:
16120	// op: Ii
16121	return `5`;
16122	case `1`:
16123	// op: Rs32
16124	return `16`;
16125	case `0`:
16126	// op: Pd4
16127	return `0`;
16128	}
16129	break;
16130	}
16131	case Hexagon::A2_addi:
16132	case Hexagon::A2_andir:
16133	case Hexagon::A2_orir:
16134	case Hexagon::A4_rcmpeqi:
16135	case Hexagon::A4_rcmpneqi:
16136	case Hexagon::L2_loadbsw2_io:
16137	case Hexagon::L2_loadbzw2_io:
16138	case Hexagon::L2_loadrb_io:
16139	case Hexagon::L2_loadrh_io:
16140	case Hexagon::L2_loadri_io:
16141	case Hexagon::L2_loadrub_io:
16142	case Hexagon::L2_loadruh_io:
16143	case Hexagon::M2_mpysin:
16144	case Hexagon::M2_mpysip: {
16145	switch (OpNum) {
16146	case `2`:
16147	// op: Ii
16148	return `5`;
16149	case `1`:
16150	// op: Rs32
16151	return `16`;
16152	case `0`:
16153	// op: Rd32
16154	return `0`;
16155	}
16156	break;
16157	}
16158	case Hexagon::A4_combineri:
16159	case Hexagon::L2_loadbsw4_io:
16160	case Hexagon::L2_loadbzw4_io:
16161	case Hexagon::L2_loadrd_io: {
16162	switch (OpNum) {
16163	case `2`:
16164	// op: Ii
16165	return `5`;
16166	case `1`:
16167	// op: Rs32
16168	return `16`;
16169	case `0`:
16170	// op: Rdd32
16171	return `0`;
16172	}
16173	break;
16174	}
16175	case Hexagon::S4_subaddi: {
16176	switch (OpNum) {
16177	case `2`:
16178	// op: Ii
16179	return `5`;
16180	case `1`:
16181	// op: Rs32
16182	return `16`;
16183	case `3`:
16184	// op: Ru32
16185	return `0`;
16186	case `0`:
16187	// op: Rd32
16188	return `8`;
16189	}
16190	break;
16191	}
16192	case Hexagon::A4_vcmpbeqi:
16193	case Hexagon::A4_vcmpbgti:
16194	case Hexagon::A4_vcmpbgtui:
16195	case Hexagon::A4_vcmpheqi:
16196	case Hexagon::A4_vcmphgti:
16197	case Hexagon::A4_vcmphgtui:
16198	case Hexagon::A4_vcmpweqi:
16199	case Hexagon::A4_vcmpwgti:
16200	case Hexagon::A4_vcmpwgtui:
16201	case Hexagon::F2_dfclass: {
16202	switch (OpNum) {
16203	case `2`:
16204	// op: Ii
16205	return `5`;
16206	case `1`:
16207	// op: Rss32
16208	return `16`;
16209	case `0`:
16210	// op: Pd4
16211	return `0`;
16212	}
16213	break;
16214	}
16215	case Hexagon::M4_mpyri_addr_u2: {
16216	switch (OpNum) {
16217	case `2`:
16218	// op: Ii
16219	return `5`;
16220	case `1`:
16221	// op: Ru32
16222	return `0`;
16223	case `3`:
16224	// op: Rs32
16225	return `16`;
16226	case `0`:
16227	// op: Rd32
16228	return `8`;
16229	}
16230	break;
16231	}
16232	case Hexagon::C2_muxii: {
16233	switch (OpNum) {
16234	case `2`:
16235	// op: Ii
16236	return `5`;
16237	case `3`:
16238	// op: II
16239	return `13`;
16240	case `1`:
16241	// op: Pu4
16242	return `23`;
16243	case `0`:
16244	// op: Rd32
16245	return `0`;
16246	}
16247	break;
16248	}
16249	case Hexagon::S4_storerbnew_rr:
16250	case Hexagon::S4_storerhnew_rr:
16251	case Hexagon::S4_storerinew_rr: {
16252	switch (OpNum) {
16253	case `2`:
16254	// op: Ii
16255	return `7`;
16256	case `0`:
16257	// op: Rs32
16258	return `16`;
16259	case `1`:
16260	// op: Ru32
16261	return `8`;
16262	case `3`:
16263	// op: Nt8
16264	return `0`;
16265	}
16266	break;
16267	}
16268	case Hexagon::S4_storerb_rr:
16269	case Hexagon::S4_storerf_rr:
16270	case Hexagon::S4_storerh_rr:
16271	case Hexagon::S4_storeri_rr: {
16272	switch (OpNum) {
16273	case `2`:
16274	// op: Ii
16275	return `7`;
16276	case `0`:
16277	// op: Rs32
16278	return `16`;
16279	case `1`:
16280	// op: Ru32
16281	return `8`;
16282	case `3`:
16283	// op: Rt32
16284	return `0`;
16285	}
16286	break;
16287	}
16288	case Hexagon::S4_storerd_rr: {
16289	switch (OpNum) {
16290	case `2`:
16291	// op: Ii
16292	return `7`;
16293	case `0`:
16294	// op: Rs32
16295	return `16`;
16296	case `1`:
16297	// op: Ru32
16298	return `8`;
16299	case `3`:
16300	// op: Rtt32
16301	return `0`;
16302	}
16303	break;
16304	}
16305	case Hexagon::S4_storeirbf_io:
16306	case Hexagon::S4_storeirbfnew_io:
16307	case Hexagon::S4_storeirbt_io:
16308	case Hexagon::S4_storeirbtnew_io:
16309	case Hexagon::S4_storeirhf_io:
16310	case Hexagon::S4_storeirhfnew_io:
16311	case Hexagon::S4_storeirht_io:
16312	case Hexagon::S4_storeirhtnew_io:
16313	case Hexagon::S4_storeirif_io:
16314	case Hexagon::S4_storeirifnew_io:
16315	case Hexagon::S4_storeirit_io:
16316	case Hexagon::S4_storeiritnew_io: {
16317	switch (OpNum) {
16318	case `2`:
16319	// op: Ii
16320	return `7`;
16321	case `3`:
16322	// op: II
16323	return `0`;
16324	case `0`:
16325	// op: Pv4
16326	return `5`;
16327	case `1`:
16328	// op: Rs32
16329	return `16`;
16330	}
16331	break;
16332	}
16333	case Hexagon::L4_loadbsw2_ur:
16334	case Hexagon::L4_loadbzw2_ur:
16335	case Hexagon::L4_loadrb_ur:
16336	case Hexagon::L4_loadrh_ur:
16337	case Hexagon::L4_loadri_ur:
16338	case Hexagon::L4_loadrub_ur:
16339	case Hexagon::L4_loadruh_ur: {
16340	switch (OpNum) {
16341	case `2`:
16342	// op: Ii
16343	return `7`;
16344	case `3`:
16345	// op: II
16346	return `5`;
16347	case `1`:
16348	// op: Rt32
16349	return `16`;
16350	case `0`:
16351	// op: Rd32
16352	return `0`;
16353	}
16354	break;
16355	}
16356	case Hexagon::L4_loadbsw4_ur:
16357	case Hexagon::L4_loadbzw4_ur:
16358	case Hexagon::L4_loadrd_ur: {
16359	switch (OpNum) {
16360	case `2`:
16361	// op: Ii
16362	return `7`;
16363	case `3`:
16364	// op: II
16365	return `5`;
16366	case `1`:
16367	// op: Rt32
16368	return `16`;
16369	case `0`:
16370	// op: Rdd32
16371	return `0`;
16372	}
16373	break;
16374	}
16375	case Hexagon::V6_vS32b_new_npred_ai:
16376	case Hexagon::V6_vS32b_new_pred_ai:
16377	case Hexagon::V6_vS32b_nt_new_npred_ai:
16378	case Hexagon::V6_vS32b_nt_new_pred_ai: {
16379	switch (OpNum) {
16380	case `2`:
16381	// op: Ii
16382	return `8`;
16383	case `0`:
16384	// op: Pv4
16385	return `11`;
16386	case `1`:
16387	// op: Rt32
16388	return `16`;
16389	case `3`:
16390	// op: Os8
16391	return `0`;
16392	}
16393	break;
16394	}
16395	case Hexagon::V6_vS32Ub_npred_ai:
16396	case Hexagon::V6_vS32Ub_pred_ai:
16397	case Hexagon::V6_vS32b_npred_ai:
16398	case Hexagon::V6_vS32b_nt_npred_ai:
16399	case Hexagon::V6_vS32b_nt_pred_ai:
16400	case Hexagon::V6_vS32b_pred_ai: {
16401	switch (OpNum) {
16402	case `2`:
16403	// op: Ii
16404	return `8`;
16405	case `0`:
16406	// op: Pv4
16407	return `11`;
16408	case `1`:
16409	// op: Rt32
16410	return `16`;
16411	case `3`:
16412	// op: Vs32
16413	return `0`;
16414	}
16415	break;
16416	}
16417	case Hexagon::V6_zLd_pred_ai: {
16418	switch (OpNum) {
16419	case `2`:
16420	// op: Ii
16421	return `8`;
16422	case `0`:
16423	// op: Pv4
16424	return `11`;
16425	case `1`:
16426	// op: Rt32
16427	return `16`;
16428	}
16429	break;
16430	}
16431	case Hexagon::V6_vS32b_nqpred_ai:
16432	case Hexagon::V6_vS32b_nt_nqpred_ai:
16433	case Hexagon::V6_vS32b_nt_qpred_ai:
16434	case Hexagon::V6_vS32b_qpred_ai: {
16435	switch (OpNum) {
16436	case `2`:
16437	// op: Ii
16438	return `8`;
16439	case `0`:
16440	// op: Qv4
16441	return `11`;
16442	case `1`:
16443	// op: Rt32
16444	return `16`;
16445	case `3`:
16446	// op: Vs32
16447	return `0`;
16448	}
16449	break;
16450	}
16451	case Hexagon::V6_vS32b_srls_pi:
16452	case Hexagon::V6_zLd_pi: {
16453	switch (OpNum) {
16454	case `2`:
16455	// op: Ii
16456	return `8`;
16457	case `0`:
16458	// op: Rx32
16459	return `16`;
16460	}
16461	break;
16462	}
16463	case Hexagon::L4_ploadrbf_abs:
16464	case Hexagon::L4_ploadrbfnew_abs:
16465	case Hexagon::L4_ploadrbt_abs:
16466	case Hexagon::L4_ploadrbtnew_abs:
16467	case Hexagon::L4_ploadrhf_abs:
16468	case Hexagon::L4_ploadrhfnew_abs:
16469	case Hexagon::L4_ploadrht_abs:
16470	case Hexagon::L4_ploadrhtnew_abs:
16471	case Hexagon::L4_ploadrif_abs:
16472	case Hexagon::L4_ploadrifnew_abs:
16473	case Hexagon::L4_ploadrit_abs:
16474	case Hexagon::L4_ploadritnew_abs:
16475	case Hexagon::L4_ploadrubf_abs:
16476	case Hexagon::L4_ploadrubfnew_abs:
16477	case Hexagon::L4_ploadrubt_abs:
16478	case Hexagon::L4_ploadrubtnew_abs:
16479	case Hexagon::L4_ploadruhf_abs:
16480	case Hexagon::L4_ploadruhfnew_abs:
16481	case Hexagon::L4_ploadruht_abs:
16482	case Hexagon::L4_ploadruhtnew_abs: {
16483	switch (OpNum) {
16484	case `2`:
16485	// op: Ii
16486	return `8`;
16487	case `1`:
16488	// op: Pt4
16489	return `9`;
16490	case `0`:
16491	// op: Rd32
16492	return `0`;
16493	}
16494	break;
16495	}
16496	case Hexagon::L4_ploadrdf_abs:
16497	case Hexagon::L4_ploadrdfnew_abs:
16498	case Hexagon::L4_ploadrdt_abs:
16499	case Hexagon::L4_ploadrdtnew_abs: {
16500	switch (OpNum) {
16501	case `2`:
16502	// op: Ii
16503	return `8`;
16504	case `1`:
16505	// op: Pt4
16506	return `9`;
16507	case `0`:
16508	// op: Rdd32
16509	return `0`;
16510	}
16511	break;
16512	}
16513	case Hexagon::SL1_loadri_io:
16514	case Hexagon::SL1_loadrub_io:
16515	case Hexagon::SL2_loadrb_io:
16516	case Hexagon::SL2_loadrh_io:
16517	case Hexagon::SL2_loadruh_io: {
16518	switch (OpNum) {
16519	case `2`:
16520	// op: Ii
16521	return `8`;
16522	case `1`:
16523	// op: Rs16
16524	return `4`;
16525	case `0`:
16526	// op: Rd16
16527	return `0`;
16528	}
16529	break;
16530	}
16531	case Hexagon::C2_bitsclri:
16532	case Hexagon::C4_nbitsclri:
16533	case Hexagon::F2_sfclass:
16534	case Hexagon::S2_tstbit_i:
16535	case Hexagon::S4_ntstbit_i: {
16536	switch (OpNum) {
16537	case `2`:
16538	// op: Ii
16539	return `8`;
16540	case `1`:
16541	// op: Rs32
16542	return `16`;
16543	case `0`:
16544	// op: Pd4
16545	return `0`;
16546	}
16547	break;
16548	}
16549	case Hexagon::A4_cround_ri:
16550	case Hexagon::A4_round_ri:
16551	case Hexagon::A4_round_ri_sat:
16552	case Hexagon::A7_clip:
16553	case Hexagon::S2_asl_i_r:
16554	case Hexagon::S2_asl_i_r_sat:
16555	case Hexagon::S2_asr_i_r:
16556	case Hexagon::S2_asr_i_r_rnd:
16557	case Hexagon::S2_clrbit_i:
16558	case Hexagon::S2_lsr_i_r:
16559	case Hexagon::S2_setbit_i:
16560	case Hexagon::S2_togglebit_i:
16561	case Hexagon::S4_clbaddi:
16562	case Hexagon::S6_rol_i_r: {
16563	switch (OpNum) {
16564	case `2`:
16565	// op: Ii
16566	return `8`;
16567	case `1`:
16568	// op: Rs32
16569	return `16`;
16570	case `0`:
16571	// op: Rd32
16572	return `0`;
16573	}
16574	break;
16575	}
16576	case Hexagon::A4_bitspliti: {
16577	switch (OpNum) {
16578	case `2`:
16579	// op: Ii
16580	return `8`;
16581	case `1`:
16582	// op: Rs32
16583	return `16`;
16584	case `0`:
16585	// op: Rdd32
16586	return `0`;
16587	}
16588	break;
16589	}
16590	case Hexagon::S2_asr_i_svw_trun:
16591	case Hexagon::S4_clbpaddi:
16592	case Hexagon::S5_asrhub_rnd_sat:
16593	case Hexagon::S5_asrhub_sat: {
16594	switch (OpNum) {
16595	case `2`:
16596	// op: Ii
16597	return `8`;
16598	case `1`:
16599	// op: Rss32
16600	return `16`;
16601	case `0`:
16602	// op: Rd32
16603	return `0`;
16604	}
16605	break;
16606	}
16607	case Hexagon::A7_croundd_ri:
16608	case Hexagon::A7_vclip:
16609	case Hexagon::S2_asl_i_p:
16610	case Hexagon::S2_asl_i_vh:
16611	case Hexagon::S2_asl_i_vw:
16612	case Hexagon::S2_asr_i_p:
16613	case Hexagon::S2_asr_i_p_rnd:
16614	case Hexagon::S2_asr_i_vh:
16615	case Hexagon::S2_asr_i_vw:
16616	case Hexagon::S2_lsr_i_p:
16617	case Hexagon::S2_lsr_i_vh:
16618	case Hexagon::S2_lsr_i_vw:
16619	case Hexagon::S5_vasrhrnd:
16620	case Hexagon::S6_rol_i_p: {
16621	switch (OpNum) {
16622	case `2`:
16623	// op: Ii
16624	return `8`;
16625	case `1`:
16626	// op: Rss32
16627	return `16`;
16628	case `0`:
16629	// op: Rdd32
16630	return `0`;
16631	}
16632	break;
16633	}
16634	case Hexagon::V6_vL32Ub_ai:
16635	case Hexagon::V6_vL32b_ai:
16636	case Hexagon::V6_vL32b_cur_ai:
16637	case Hexagon::V6_vL32b_nt_ai:
16638	case Hexagon::V6_vL32b_nt_cur_ai:
16639	case Hexagon::V6_vL32b_nt_tmp_ai:
16640	case Hexagon::V6_vL32b_tmp_ai: {
16641	switch (OpNum) {
16642	case `2`:
16643	// op: Ii
16644	return `8`;
16645	case `1`:
16646	// op: Rt32
16647	return `16`;
16648	case `0`:
16649	// op: Vd32
16650	return `0`;
16651	}
16652	break;
16653	}
16654	case Hexagon::S2_extractu:
16655	case Hexagon::S4_extract: {
16656	switch (OpNum) {
16657	case `2`:
16658	// op: Ii
16659	return `8`;
16660	case `3`:
16661	// op: II
16662	return `5`;
16663	case `1`:
16664	// op: Rs32
16665	return `16`;
16666	case `0`:
16667	// op: Rd32
16668	return `0`;
16669	}
16670	break;
16671	}
16672	case Hexagon::S2_extractup:
16673	case Hexagon::S4_extractp: {
16674	switch (OpNum) {
16675	case `2`:
16676	// op: Ii
16677	return `8`;
16678	case `3`:
16679	// op: II
16680	return `5`;
16681	case `1`:
16682	// op: Rss32
16683	return `16`;
16684	case `0`:
16685	// op: Rdd32
16686	return `0`;
16687	}
16688	break;
16689	}
16690	case Hexagon::V6_vS32b_new_pi:
16691	case Hexagon::V6_vS32b_nt_new_pi: {
16692	switch (OpNum) {
16693	case `2`:
16694	// op: Ii
16695	return `8`;
16696	case `3`:
16697	// op: Os8
16698	return `0`;
16699	case `0`:
16700	// op: Rx32
16701	return `16`;
16702	}
16703	break;
16704	}
16705	case Hexagon::V6_vS32Ub_pi:
16706	case Hexagon::V6_vS32b_nt_pi:
16707	case Hexagon::V6_vS32b_pi: {
16708	switch (OpNum) {
16709	case `2`:
16710	// op: Ii
16711	return `8`;
16712	case `3`:
16713	// op: Vs32
16714	return `0`;
16715	case `0`:
16716	// op: Rx32
16717	return `16`;
16718	}
16719	break;
16720	}
16721	case Hexagon::V6_vS32b_srls_ppu:
16722	case Hexagon::V6_zLd_ppu: {
16723	switch (OpNum) {
16724	case `2`:
16725	// op: Mu2
16726	return `13`;
16727	case `0`:
16728	// op: Rx32
16729	return `16`;
16730	}
16731	break;
16732	}
16733	case Hexagon::S2_storerbnew_pbr:
16734	case Hexagon::S2_storerbnew_pcr:
16735	case Hexagon::S2_storerbnew_pr:
16736	case Hexagon::S2_storerhnew_pbr:
16737	case Hexagon::S2_storerhnew_pcr:
16738	case Hexagon::S2_storerhnew_pr:
16739	case Hexagon::S2_storerinew_pbr:
16740	case Hexagon::S2_storerinew_pcr:
16741	case Hexagon::S2_storerinew_pr: {
16742	switch (OpNum) {
16743	case `2`:
16744	// op: Mu2
16745	return `13`;
16746	case `3`:
16747	// op: Nt8
16748	return `8`;
16749	case `0`:
16750	// op: Rx32
16751	return `16`;
16752	}
16753	break;
16754	}
16755	case Hexagon::V6_vS32b_new_ppu:
16756	case Hexagon::V6_vS32b_nt_new_ppu: {
16757	switch (OpNum) {
16758	case `2`:
16759	// op: Mu2
16760	return `13`;
16761	case `3`:
16762	// op: Os8
16763	return `0`;
16764	case `0`:
16765	// op: Rx32
16766	return `16`;
16767	}
16768	break;
16769	}
16770	case Hexagon::S2_storerb_pbr:
16771	case Hexagon::S2_storerb_pcr:
16772	case Hexagon::S2_storerb_pr:
16773	case Hexagon::S2_storerf_pbr:
16774	case Hexagon::S2_storerf_pcr:
16775	case Hexagon::S2_storerf_pr:
16776	case Hexagon::S2_storerh_pbr:
16777	case Hexagon::S2_storerh_pcr:
16778	case Hexagon::S2_storerh_pr:
16779	case Hexagon::S2_storeri_pbr:
16780	case Hexagon::S2_storeri_pcr:
16781	case Hexagon::S2_storeri_pr: {
16782	switch (OpNum) {
16783	case `2`:
16784	// op: Mu2
16785	return `13`;
16786	case `3`:
16787	// op: Rt32
16788	return `8`;
16789	case `0`:
16790	// op: Rx32
16791	return `16`;
16792	}
16793	break;
16794	}
16795	case Hexagon::S2_storerd_pbr:
16796	case Hexagon::S2_storerd_pcr:
16797	case Hexagon::S2_storerd_pr: {
16798	switch (OpNum) {
16799	case `2`:
16800	// op: Mu2
16801	return `13`;
16802	case `3`:
16803	// op: Rtt32
16804	return `8`;
16805	case `0`:
16806	// op: Rx32
16807	return `16`;
16808	}
16809	break;
16810	}
16811	case Hexagon::V6_vS32Ub_ppu:
16812	case Hexagon::V6_vS32b_nt_ppu:
16813	case Hexagon::V6_vS32b_ppu: {
16814	switch (OpNum) {
16815	case `2`:
16816	// op: Mu2
16817	return `13`;
16818	case `3`:
16819	// op: Vs32
16820	return `0`;
16821	case `0`:
16822	// op: Rx32
16823	return `16`;
16824	}
16825	break;
16826	}
16827	case Hexagon::V6_vL32b_cur_npred_ppu:
16828	case Hexagon::V6_vL32b_cur_pred_ppu:
16829	case Hexagon::V6_vL32b_npred_ppu:
16830	case Hexagon::V6_vL32b_nt_cur_npred_ppu:
16831	case Hexagon::V6_vL32b_nt_cur_pred_ppu:
16832	case Hexagon::V6_vL32b_nt_npred_ppu:
16833	case Hexagon::V6_vL32b_nt_pred_ppu:
16834	case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
16835	case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
16836	case Hexagon::V6_vL32b_pred_ppu:
16837	case Hexagon::V6_vL32b_tmp_npred_ppu:
16838	case Hexagon::V6_vL32b_tmp_pred_ppu: {
16839	switch (OpNum) {
16840	case `2`:
16841	// op: Pv4
16842	return `11`;
16843	case `4`:
16844	// op: Mu2
16845	return `13`;
16846	case `0`:
16847	// op: Vd32
16848	return `0`;
16849	case `1`:
16850	// op: Rx32
16851	return `16`;
16852	}
16853	break;
16854	}
16855	case Hexagon::V6_vandnqrt_acc:
16856	case Hexagon::V6_vandqrt_acc: {
16857	switch (OpNum) {
16858	case `2`:
16859	// op: Qu4
16860	return `8`;
16861	case `3`:
16862	// op: Rt32
16863	return `16`;
16864	case `0`:
16865	// op: Vx32
16866	return `0`;
16867	}
16868	break;
16869	}
16870	case Hexagon::SA1_addrx: {
16871	switch (OpNum) {
16872	case `2`:
16873	// op: Rs16
16874	return `4`;
16875	case `0`:
16876	// op: Rx16
16877	return `0`;
16878	}
16879	break;
16880	}
16881	case Hexagon::F2_sfinvsqrta: {
16882	switch (OpNum) {
16883	case `2`:
16884	// op: Rs32
16885	return `16`;
16886	case `0`:
16887	// op: Rd32
16888	return `0`;
16889	case `1`:
16890	// op: Pe4
16891	return `5`;
16892	}
16893	break;
16894	}
16895	case Hexagon::F2_sfrecipa: {
16896	switch (OpNum) {
16897	case `2`:
16898	// op: Rs32
16899	return `16`;
16900	case `3`:
16901	// op: Rt32
16902	return `8`;
16903	case `0`:
16904	// op: Rd32
16905	return `0`;
16906	case `1`:
16907	// op: Pe4
16908	return `5`;
16909	}
16910	break;
16911	}
16912	case Hexagon::F2_sffma:
16913	case Hexagon::F2_sffma_lib:
16914	case Hexagon::F2_sffms:
16915	case Hexagon::F2_sffms_lib:
16916	case Hexagon::M2_acci:
16917	case Hexagon::M2_maci:
16918	case Hexagon::M2_mnaci:
16919	case Hexagon::M2_mpy_acc_hh_s0:
16920	case Hexagon::M2_mpy_acc_hh_s1:
16921	case Hexagon::M2_mpy_acc_hl_s0:
16922	case Hexagon::M2_mpy_acc_hl_s1:
16923	case Hexagon::M2_mpy_acc_lh_s0:
16924	case Hexagon::M2_mpy_acc_lh_s1:
16925	case Hexagon::M2_mpy_acc_ll_s0:
16926	case Hexagon::M2_mpy_acc_ll_s1:
16927	case Hexagon::M2_mpy_acc_sat_hh_s0:
16928	case Hexagon::M2_mpy_acc_sat_hh_s1:
16929	case Hexagon::M2_mpy_acc_sat_hl_s0:
16930	case Hexagon::M2_mpy_acc_sat_hl_s1:
16931	case Hexagon::M2_mpy_acc_sat_lh_s0:
16932	case Hexagon::M2_mpy_acc_sat_lh_s1:
16933	case Hexagon::M2_mpy_acc_sat_ll_s0:
16934	case Hexagon::M2_mpy_acc_sat_ll_s1:
16935	case Hexagon::M2_mpy_nac_hh_s0:
16936	case Hexagon::M2_mpy_nac_hh_s1:
16937	case Hexagon::M2_mpy_nac_hl_s0:
16938	case Hexagon::M2_mpy_nac_hl_s1:
16939	case Hexagon::M2_mpy_nac_lh_s0:
16940	case Hexagon::M2_mpy_nac_lh_s1:
16941	case Hexagon::M2_mpy_nac_ll_s0:
16942	case Hexagon::M2_mpy_nac_ll_s1:
16943	case Hexagon::M2_mpy_nac_sat_hh_s0:
16944	case Hexagon::M2_mpy_nac_sat_hh_s1:
16945	case Hexagon::M2_mpy_nac_sat_hl_s0:
16946	case Hexagon::M2_mpy_nac_sat_hl_s1:
16947	case Hexagon::M2_mpy_nac_sat_lh_s0:
16948	case Hexagon::M2_mpy_nac_sat_lh_s1:
16949	case Hexagon::M2_mpy_nac_sat_ll_s0:
16950	case Hexagon::M2_mpy_nac_sat_ll_s1:
16951	case Hexagon::M2_mpyu_acc_hh_s0:
16952	case Hexagon::M2_mpyu_acc_hh_s1:
16953	case Hexagon::M2_mpyu_acc_hl_s0:
16954	case Hexagon::M2_mpyu_acc_hl_s1:
16955	case Hexagon::M2_mpyu_acc_lh_s0:
16956	case Hexagon::M2_mpyu_acc_lh_s1:
16957	case Hexagon::M2_mpyu_acc_ll_s0:
16958	case Hexagon::M2_mpyu_acc_ll_s1:
16959	case Hexagon::M2_mpyu_nac_hh_s0:
16960	case Hexagon::M2_mpyu_nac_hh_s1:
16961	case Hexagon::M2_mpyu_nac_hl_s0:
16962	case Hexagon::M2_mpyu_nac_hl_s1:
16963	case Hexagon::M2_mpyu_nac_lh_s0:
16964	case Hexagon::M2_mpyu_nac_lh_s1:
16965	case Hexagon::M2_mpyu_nac_ll_s0:
16966	case Hexagon::M2_mpyu_nac_ll_s1:
16967	case Hexagon::M2_nacci:
16968	case Hexagon::M2_xor_xacc:
16969	case Hexagon::M4_and_and:
16970	case Hexagon::M4_and_andn:
16971	case Hexagon::M4_and_or:
16972	case Hexagon::M4_and_xor:
16973	case Hexagon::M4_mac_up_s1_sat:
16974	case Hexagon::M4_nac_up_s1_sat:
16975	case Hexagon::M4_or_and:
16976	case Hexagon::M4_or_andn:
16977	case Hexagon::M4_or_or:
16978	case Hexagon::M4_or_xor:
16979	case Hexagon::M4_xor_and:
16980	case Hexagon::M4_xor_andn:
16981	case Hexagon::M4_xor_or:
16982	case Hexagon::S2_asl_r_r_acc:
16983	case Hexagon::S2_asl_r_r_and:
16984	case Hexagon::S2_asl_r_r_nac:
16985	case Hexagon::S2_asl_r_r_or:
16986	case Hexagon::S2_asr_r_r_acc:
16987	case Hexagon::S2_asr_r_r_and:
16988	case Hexagon::S2_asr_r_r_nac:
16989	case Hexagon::S2_asr_r_r_or:
16990	case Hexagon::S2_lsl_r_r_acc:
16991	case Hexagon::S2_lsl_r_r_and:
16992	case Hexagon::S2_lsl_r_r_nac:
16993	case Hexagon::S2_lsl_r_r_or:
16994	case Hexagon::S2_lsr_r_r_acc:
16995	case Hexagon::S2_lsr_r_r_and:
16996	case Hexagon::S2_lsr_r_r_nac:
16997	case Hexagon::S2_lsr_r_r_or: {
16998	switch (OpNum) {
16999	case `2`:
17000	// op: Rs32
17001	return `16`;
17002	case `3`:
17003	// op: Rt32
17004	return `8`;
17005	case `0`:
17006	// op: Rx32
17007	return `0`;
17008	}
17009	break;
17010	}
17011	case Hexagon::M2_cmaci_s0:
17012	case Hexagon::M2_cmacr_s0:
17013	case Hexagon::M2_cmacs_s0:
17014	case Hexagon::M2_cmacs_s1:
17015	case Hexagon::M2_cmacsc_s0:
17016	case Hexagon::M2_cmacsc_s1:
17017	case Hexagon::M2_cnacs_s0:
17018	case Hexagon::M2_cnacs_s1:
17019	case Hexagon::M2_cnacsc_s0:
17020	case Hexagon::M2_cnacsc_s1:
17021	case Hexagon::M2_dpmpyss_acc_s0:
17022	case Hexagon::M2_dpmpyss_nac_s0:
17023	case Hexagon::M2_dpmpyuu_acc_s0:
17024	case Hexagon::M2_dpmpyuu_nac_s0:
17025	case Hexagon::M2_mpyd_acc_hh_s0:
17026	case Hexagon::M2_mpyd_acc_hh_s1:
17027	case Hexagon::M2_mpyd_acc_hl_s0:
17028	case Hexagon::M2_mpyd_acc_hl_s1:
17029	case Hexagon::M2_mpyd_acc_lh_s0:
17030	case Hexagon::M2_mpyd_acc_lh_s1:
17031	case Hexagon::M2_mpyd_acc_ll_s0:
17032	case Hexagon::M2_mpyd_acc_ll_s1:
17033	case Hexagon::M2_mpyd_nac_hh_s0:
17034	case Hexagon::M2_mpyd_nac_hh_s1:
17035	case Hexagon::M2_mpyd_nac_hl_s0:
17036	case Hexagon::M2_mpyd_nac_hl_s1:
17037	case Hexagon::M2_mpyd_nac_lh_s0:
17038	case Hexagon::M2_mpyd_nac_lh_s1:
17039	case Hexagon::M2_mpyd_nac_ll_s0:
17040	case Hexagon::M2_mpyd_nac_ll_s1:
17041	case Hexagon::M2_mpyud_acc_hh_s0:
17042	case Hexagon::M2_mpyud_acc_hh_s1:
17043	case Hexagon::M2_mpyud_acc_hl_s0:
17044	case Hexagon::M2_mpyud_acc_hl_s1:
17045	case Hexagon::M2_mpyud_acc_lh_s0:
17046	case Hexagon::M2_mpyud_acc_lh_s1:
17047	case Hexagon::M2_mpyud_acc_ll_s0:
17048	case Hexagon::M2_mpyud_acc_ll_s1:
17049	case Hexagon::M2_mpyud_nac_hh_s0:
17050	case Hexagon::M2_mpyud_nac_hh_s1:
17051	case Hexagon::M2_mpyud_nac_hl_s0:
17052	case Hexagon::M2_mpyud_nac_hl_s1:
17053	case Hexagon::M2_mpyud_nac_lh_s0:
17054	case Hexagon::M2_mpyud_nac_lh_s1:
17055	case Hexagon::M2_mpyud_nac_ll_s0:
17056	case Hexagon::M2_mpyud_nac_ll_s1:
17057	case Hexagon::M2_vmac2:
17058	case Hexagon::M2_vmac2s_s0:
17059	case Hexagon::M2_vmac2s_s1:
17060	case Hexagon::M2_vmac2su_s0:
17061	case Hexagon::M2_vmac2su_s1:
17062	case Hexagon::M4_pmpyw_acc:
17063	case Hexagon::M4_vpmpyh_acc:
17064	case Hexagon::M5_vmacbsu:
17065	case Hexagon::M5_vmacbuu: {
17066	switch (OpNum) {
17067	case `2`:
17068	// op: Rs32
17069	return `16`;
17070	case `3`:
17071	// op: Rt32
17072	return `8`;
17073	case `0`:
17074	// op: Rxx32
17075	return `0`;
17076	}
17077	break;
17078	}
17079	case Hexagon::F2_sffma_sc: {
17080	switch (OpNum) {
17081	case `2`:
17082	// op: Rs32
17083	return `16`;
17084	case `3`:
17085	// op: Rt32
17086	return `8`;
17087	case `4`:
17088	// op: Pu4
17089	return `5`;
17090	case `0`:
17091	// op: Rx32
17092	return `0`;
17093	}
17094	break;
17095	}
17096	case Hexagon::S2_insert_rp: {
17097	switch (OpNum) {
17098	case `2`:
17099	// op: Rs32
17100	return `16`;
17101	case `3`:
17102	// op: Rtt32
17103	return `8`;
17104	case `0`:
17105	// op: Rx32
17106	return `0`;
17107	}
17108	break;
17109	}
17110	case Hexagon::S2_asl_r_p_acc:
17111	case Hexagon::S2_asl_r_p_and:
17112	case Hexagon::S2_asl_r_p_nac:
17113	case Hexagon::S2_asl_r_p_or:
17114	case Hexagon::S2_asl_r_p_xor:
17115	case Hexagon::S2_asr_r_p_acc:
17116	case Hexagon::S2_asr_r_p_and:
17117	case Hexagon::S2_asr_r_p_nac:
17118	case Hexagon::S2_asr_r_p_or:
17119	case Hexagon::S2_asr_r_p_xor:
17120	case Hexagon::S2_lsl_r_p_acc:
17121	case Hexagon::S2_lsl_r_p_and:
17122	case Hexagon::S2_lsl_r_p_nac:
17123	case Hexagon::S2_lsl_r_p_or:
17124	case Hexagon::S2_lsl_r_p_xor:
17125	case Hexagon::S2_lsr_r_p_acc:
17126	case Hexagon::S2_lsr_r_p_and:
17127	case Hexagon::S2_lsr_r_p_nac:
17128	case Hexagon::S2_lsr_r_p_or:
17129	case Hexagon::S2_lsr_r_p_xor:
17130	case Hexagon::S2_vrcnegh: {
17131	switch (OpNum) {
17132	case `2`:
17133	// op: Rss32
17134	return `16`;
17135	case `3`:
17136	// op: Rt32
17137	return `8`;
17138	case `0`:
17139	// op: Rxx32
17140	return `0`;
17141	}
17142	break;
17143	}
17144	case Hexagon::A4_addp_c:
17145	case Hexagon::A4_subp_c: {
17146	switch (OpNum) {
17147	case `2`:
17148	// op: Rss32
17149	return `16`;
17150	case `3`:
17151	// op: Rtt32
17152	return `8`;
17153	case `0`:
17154	// op: Rdd32
17155	return `0`;
17156	case `1`:
17157	// op: Px4
17158	return `5`;
17159	}
17160	break;
17161	}
17162	case Hexagon::A2_vraddub_acc:
17163	case Hexagon::A2_vrsadub_acc:
17164	case Hexagon::F2_dfmpyhh:
17165	case Hexagon::F2_dfmpylh:
17166	case Hexagon::M2_mmachs_rs0:
17167	case Hexagon::M2_mmachs_rs1:
17168	case Hexagon::M2_mmachs_s0:
17169	case Hexagon::M2_mmachs_s1:
17170	case Hexagon::M2_mmacls_rs0:
17171	case Hexagon::M2_mmacls_rs1:
17172	case Hexagon::M2_mmacls_s0:
17173	case Hexagon::M2_mmacls_s1:
17174	case Hexagon::M2_mmacuhs_rs0:
17175	case Hexagon::M2_mmacuhs_rs1:
17176	case Hexagon::M2_mmacuhs_s0:
17177	case Hexagon::M2_mmacuhs_s1:
17178	case Hexagon::M2_mmaculs_rs0:
17179	case Hexagon::M2_mmaculs_rs1:
17180	case Hexagon::M2_mmaculs_s0:
17181	case Hexagon::M2_mmaculs_s1:
17182	case Hexagon::M2_vcmac_s0_sat_i:
17183	case Hexagon::M2_vcmac_s0_sat_r:
17184	case Hexagon::M2_vdmacs_s0:
17185	case Hexagon::M2_vdmacs_s1:
17186	case Hexagon::M2_vmac2es:
17187	case Hexagon::M2_vmac2es_s0:
17188	case Hexagon::M2_vmac2es_s1:
17189	case Hexagon::M2_vrcmaci_s0:
17190	case Hexagon::M2_vrcmaci_s0c:
17191	case Hexagon::M2_vrcmacr_s0:
17192	case Hexagon::M2_vrcmacr_s0c:
17193	case Hexagon::M2_vrcmpys_acc_s1_h:
17194	case Hexagon::M2_vrcmpys_acc_s1_l:
17195	case Hexagon::M2_vrmac_s0:
17196	case Hexagon::M4_vrmpyeh_acc_s0:
17197	case Hexagon::M4_vrmpyeh_acc_s1:
17198	case Hexagon::M4_vrmpyoh_acc_s0:
17199	case Hexagon::M4_vrmpyoh_acc_s1:
17200	case Hexagon::M4_xor_xacc:
17201	case Hexagon::M5_vdmacbsu:
17202	case Hexagon::M5_vrmacbsu:
17203	case Hexagon::M5_vrmacbuu:
17204	case Hexagon::M7_dcmpyiw_acc:
17205	case Hexagon::M7_dcmpyiwc_acc:
17206	case Hexagon::M7_dcmpyrw_acc:
17207	case Hexagon::M7_dcmpyrwc_acc:
17208	case Hexagon::S2_insertp_rp: {
17209	switch (OpNum) {
17210	case `2`:
17211	// op: Rss32
17212	return `16`;
17213	case `3`:
17214	// op: Rtt32
17215	return `8`;
17216	case `0`:
17217	// op: Rxx32
17218	return `0`;
17219	}
17220	break;
17221	}
17222	case Hexagon::A4_vrmaxh:
17223	case Hexagon::A4_vrmaxuh:
17224	case Hexagon::A4_vrmaxuw:
17225	case Hexagon::A4_vrmaxw:
17226	case Hexagon::A4_vrminh:
17227	case Hexagon::A4_vrminuh:
17228	case Hexagon::A4_vrminuw:
17229	case Hexagon::A4_vrminw: {
17230	switch (OpNum) {
17231	case `2`:
17232	// op: Rss32
17233	return `16`;
17234	case `3`:
17235	// op: Ru32
17236	return `0`;
17237	case `0`:
17238	// op: Rxx32
17239	return `8`;
17240	}
17241	break;
17242	}
17243	case Hexagon::V6_vinsertwr: {
17244	switch (OpNum) {
17245	case `2`:
17246	// op: Rt32
17247	return `16`;
17248	case `0`:
17249	// op: Vx32
17250	return `0`;
17251	}
17252	break;
17253	}
17254	case Hexagon::M2_subacc: {
17255	switch (OpNum) {
17256	case `2`:
17257	// op: Rt32
17258	return `8`;
17259	case `3`:
17260	// op: Rs32
17261	return `16`;
17262	case `0`:
17263	// op: Rx32
17264	return `0`;
17265	}
17266	break;
17267	}
17268	case Hexagon::A6_vminub_RdP: {
17269	switch (OpNum) {
17270	case `2`:
17271	// op: Rtt32
17272	return `8`;
17273	case `3`:
17274	// op: Rss32
17275	return `16`;
17276	case `0`:
17277	// op: Rdd32
17278	return `0`;
17279	case `1`:
17280	// op: Pe4
17281	return `5`;
17282	}
17283	break;
17284	}
17285	case Hexagon::V6_vrmpyzbb_rx:
17286	case Hexagon::V6_vrmpyzbub_rx:
17287	case Hexagon::V6_vrmpyzcb_rx:
17288	case Hexagon::V6_vrmpyzcbs_rx:
17289	case Hexagon::V6_vrmpyznb_rx: {
17290	switch (OpNum) {
17291	case `2`:
17292	// op: Vu32
17293	return `8`;
17294	case `0`:
17295	// op: Vdddd32
17296	return `0`;
17297	case `1`:
17298	// op: Rx8
17299	return `16`;
17300	}
17301	break;
17302	}
17303	case Hexagon::V6_vunpackob:
17304	case Hexagon::V6_vunpackoh: {
17305	switch (OpNum) {
17306	case `2`:
17307	// op: Vu32
17308	return `8`;
17309	case `0`:
17310	// op: Vxx32
17311	return `0`;
17312	}
17313	break;
17314	}
17315	case Hexagon::V6_vandvrt_acc: {
17316	switch (OpNum) {
17317	case `2`:
17318	// op: Vu32
17319	return `8`;
17320	case `3`:
17321	// op: Rt32
17322	return `16`;
17323	case `0`:
17324	// op: Qx4
17325	return `0`;
17326	}
17327	break;
17328	}
17329	case Hexagon::V6_vaslh_acc:
17330	case Hexagon::V6_vaslw_acc:
17331	case Hexagon::V6_vasrh_acc:
17332	case Hexagon::V6_vasrw_acc:
17333	case Hexagon::V6_vdmpybus_acc:
17334	case Hexagon::V6_vdmpyhb_acc:
17335	case Hexagon::V6_vdmpyhsat_acc:
17336	case Hexagon::V6_vdmpyhsusat_acc:
17337	case Hexagon::V6_vmpyihb_acc:
17338	case Hexagon::V6_vmpyiwb_acc:
17339	case Hexagon::V6_vmpyiwh_acc:
17340	case Hexagon::V6_vmpyiwub_acc:
17341	case Hexagon::V6_vmpyuhe_acc:
17342	case Hexagon::V6_vrmpybus_acc:
17343	case Hexagon::V6_vrmpyub_acc: {
17344	switch (OpNum) {
17345	case `2`:
17346	// op: Vu32
17347	return `8`;
17348	case `3`:
17349	// op: Rt32
17350	return `16`;
17351	case `0`:
17352	// op: Vx32
17353	return `0`;
17354	}
17355	break;
17356	}
17357	case Hexagon::V6_vmpybus_acc:
17358	case Hexagon::V6_vmpyh_acc:
17359	case Hexagon::V6_vmpyhsat_acc:
17360	case Hexagon::V6_vmpyub_acc:
17361	case Hexagon::V6_vmpyuh_acc: {
17362	switch (OpNum) {
17363	case `2`:
17364	// op: Vu32
17365	return `8`;
17366	case `3`:
17367	// op: Rt32
17368	return `16`;
17369	case `0`:
17370	// op: Vxx32
17371	return `0`;
17372	}
17373	break;
17374	}
17375	case Hexagon::V6_vrmpyzbb_rt_acc:
17376	case Hexagon::V6_vrmpyzbub_rt_acc:
17377	case Hexagon::V6_vrmpyzcb_rt_acc:
17378	case Hexagon::V6_vrmpyzcbs_rt_acc:
17379	case Hexagon::V6_vrmpyznb_rt_acc: {
17380	switch (OpNum) {
17381	case `2`:
17382	// op: Vu32
17383	return `8`;
17384	case `3`:
17385	// op: Rt8
17386	return `16`;
17387	case `0`:
17388	// op: Vyyyy32
17389	return `0`;
17390	}
17391	break;
17392	}
17393	case Hexagon::V6_vmpahhsat:
17394	case Hexagon::V6_vmpauhuhsat:
17395	case Hexagon::V6_vmpsuhuhsat: {
17396	switch (OpNum) {
17397	case `2`:
17398	// op: Vu32
17399	return `8`;
17400	case `3`:
17401	// op: Rtt32
17402	return `16`;
17403	case `0`:
17404	// op: Vx32
17405	return `0`;
17406	}
17407	break;
17408	}
17409	case Hexagon::V6_vrmpybub_rtt_acc:
17410	case Hexagon::V6_vrmpyub_rtt_acc: {
17411	switch (OpNum) {
17412	case `2`:
17413	// op: Vu32
17414	return `8`;
17415	case `3`:
17416	// op: Rtt32
17417	return `16`;
17418	case `0`:
17419	// op: Vxx32
17420	return `0`;
17421	}
17422	break;
17423	}
17424	case Hexagon::V6_veqb_and:
17425	case Hexagon::V6_veqb_or:
17426	case Hexagon::V6_veqb_xor:
17427	case Hexagon::V6_veqh_and:
17428	case Hexagon::V6_veqh_or:
17429	case Hexagon::V6_veqh_xor:
17430	case Hexagon::V6_veqw_and:
17431	case Hexagon::V6_veqw_or:
17432	case Hexagon::V6_veqw_xor:
17433	case Hexagon::V6_vgtb_and:
17434	case Hexagon::V6_vgtb_or:
17435	case Hexagon::V6_vgtb_xor:
17436	case Hexagon::V6_vgtbf_and:
17437	case Hexagon::V6_vgtbf_or:
17438	case Hexagon::V6_vgtbf_xor:
17439	case Hexagon::V6_vgth_and:
17440	case Hexagon::V6_vgth_or:
17441	case Hexagon::V6_vgth_xor:
17442	case Hexagon::V6_vgthf_and:
17443	case Hexagon::V6_vgthf_or:
17444	case Hexagon::V6_vgthf_xor:
17445	case Hexagon::V6_vgtsf_and:
17446	case Hexagon::V6_vgtsf_or:
17447	case Hexagon::V6_vgtsf_xor:
17448	case Hexagon::V6_vgtub_and:
17449	case Hexagon::V6_vgtub_or:
17450	case Hexagon::V6_vgtub_xor:
17451	case Hexagon::V6_vgtuh_and:
17452	case Hexagon::V6_vgtuh_or:
17453	case Hexagon::V6_vgtuh_xor:
17454	case Hexagon::V6_vgtuw_and:
17455	case Hexagon::V6_vgtuw_or:
17456	case Hexagon::V6_vgtuw_xor:
17457	case Hexagon::V6_vgtw_and:
17458	case Hexagon::V6_vgtw_or:
17459	case Hexagon::V6_vgtw_xor: {
17460	switch (OpNum) {
17461	case `2`:
17462	// op: Vu32
17463	return `8`;
17464	case `3`:
17465	// op: Vv32
17466	return `16`;
17467	case `0`:
17468	// op: Qx4
17469	return `0`;
17470	}
17471	break;
17472	}
17473	case Hexagon::V6_vaddcarryo:
17474	case Hexagon::V6_vsubcarryo: {
17475	switch (OpNum) {
17476	case `2`:
17477	// op: Vu32
17478	return `8`;
17479	case `3`:
17480	// op: Vv32
17481	return `16`;
17482	case `0`:
17483	// op: Vd32
17484	return `0`;
17485	case `1`:
17486	// op: Qe4
17487	return `5`;
17488	}
17489	break;
17490	}
17491	case Hexagon::V6_vaddcarry:
17492	case Hexagon::V6_vsubcarry: {
17493	switch (OpNum) {
17494	case `2`:
17495	// op: Vu32
17496	return `8`;
17497	case `3`:
17498	// op: Vv32
17499	return `16`;
17500	case `0`:
17501	// op: Vd32
17502	return `0`;
17503	case `1`:
17504	// op: Qx4
17505	return `5`;
17506	}
17507	break;
17508	}
17509	case Hexagon::V6_vdmpy_sf_hf_acc:
17510	case Hexagon::V6_vdmpyhvsat_acc:
17511	case Hexagon::V6_vmpy_hf_hf_acc:
17512	case Hexagon::V6_vmpyiewh_acc:
17513	case Hexagon::V6_vmpyiewuh_acc:
17514	case Hexagon::V6_vmpyih_acc:
17515	case Hexagon::V6_vmpyowh_rnd_sacc:
17516	case Hexagon::V6_vmpyowh_sacc:
17517	case Hexagon::V6_vrmpybusv_acc:
17518	case Hexagon::V6_vrmpybv_acc:
17519	case Hexagon::V6_vrmpyubv_acc: {
17520	switch (OpNum) {
17521	case `2`:
17522	// op: Vu32
17523	return `8`;
17524	case `3`:
17525	// op: Vv32
17526	return `16`;
17527	case `0`:
17528	// op: Vx32
17529	return `0`;
17530	}
17531	break;
17532	}
17533	case Hexagon::V6_vaddhw_acc:
17534	case Hexagon::V6_vaddubh_acc:
17535	case Hexagon::V6_vadduhw_acc:
17536	case Hexagon::V6_vasr_into:
17537	case Hexagon::V6_vmpy_sf_bf_acc:
17538	case Hexagon::V6_vmpy_sf_hf_acc:
17539	case Hexagon::V6_vmpybusv_acc:
17540	case Hexagon::V6_vmpybv_acc:
17541	case Hexagon::V6_vmpyhus_acc:
17542	case Hexagon::V6_vmpyhv_acc:
17543	case Hexagon::V6_vmpyowh_64_acc:
17544	case Hexagon::V6_vmpyubv_acc:
17545	case Hexagon::V6_vmpyuhv_acc: {
17546	switch (OpNum) {
17547	case `2`:
17548	// op: Vu32
17549	return `8`;
17550	case `3`:
17551	// op: Vv32
17552	return `16`;
17553	case `0`:
17554	// op: Vxx32
17555	return `0`;
17556	}
17557	break;
17558	}
17559	case Hexagon::V6_vlutvvb_oracc: {
17560	switch (OpNum) {
17561	case `2`:
17562	// op: Vu32
17563	return `8`;
17564	case `3`:
17565	// op: Vv32
17566	return `19`;
17567	case `4`:
17568	// op: Rt8
17569	return `16`;
17570	case `0`:
17571	// op: Vx32
17572	return `0`;
17573	}
17574	break;
17575	}
17576	case Hexagon::V6_vlutvwh_oracc: {
17577	switch (OpNum) {
17578	case `2`:
17579	// op: Vu32
17580	return `8`;
17581	case `3`:
17582	// op: Vv32
17583	return `19`;
17584	case `4`:
17585	// op: Rt8
17586	return `16`;
17587	case `0`:
17588	// op: Vxx32
17589	return `0`;
17590	}
17591	break;
17592	}
17593	case Hexagon::V6_vdmpyhisat_acc:
17594	case Hexagon::V6_vdmpyhsuisat_acc: {
17595	switch (OpNum) {
17596	case `2`:
17597	// op: Vuu32
17598	return `8`;
17599	case `3`:
17600	// op: Rt32
17601	return `16`;
17602	case `0`:
17603	// op: Vx32
17604	return `0`;
17605	}
17606	break;
17607	}
17608	case Hexagon::V6_vdmpybus_dv_acc:
17609	case Hexagon::V6_vdmpyhb_dv_acc:
17610	case Hexagon::V6_vdsaduh_acc:
17611	case Hexagon::V6_vmpabus_acc:
17612	case Hexagon::V6_vmpabuu_acc:
17613	case Hexagon::V6_vmpahb_acc:
17614	case Hexagon::V6_vmpauhb_acc:
17615	case Hexagon::V6_vtmpyb_acc:
17616	case Hexagon::V6_vtmpybus_acc:
17617	case Hexagon::V6_vtmpyhb_acc: {
17618	switch (OpNum) {
17619	case `2`:
17620	// op: Vuu32
17621	return `8`;
17622	case `3`:
17623	// op: Rt32
17624	return `16`;
17625	case `0`:
17626	// op: Vxx32
17627	return `0`;
17628	}
17629	break;
17630	}
17631	case Hexagon::L4_loadalignb_ap:
17632	case Hexagon::L4_loadalignh_ap: {
17633	switch (OpNum) {
17634	case `3`:
17635	// op: II
17636	return `5`;
17637	case `0`:
17638	// op: Ryy32
17639	return `0`;
17640	case `1`:
17641	// op: Re32
17642	return `16`;
17643	}
17644	break;
17645	}
17646	case Hexagon::S2_pstorerbnewf_pi:
17647	case Hexagon::S2_pstorerbnewfnew_pi:
17648	case Hexagon::S2_pstorerbnewt_pi:
17649	case Hexagon::S2_pstorerbnewtnew_pi:
17650	case Hexagon::S2_pstorerhnewf_pi:
17651	case Hexagon::S2_pstorerhnewfnew_pi:
17652	case Hexagon::S2_pstorerhnewt_pi:
17653	case Hexagon::S2_pstorerhnewtnew_pi:
17654	case Hexagon::S2_pstorerinewf_pi:
17655	case Hexagon::S2_pstorerinewfnew_pi:
17656	case Hexagon::S2_pstorerinewt_pi:
17657	case Hexagon::S2_pstorerinewtnew_pi: {
17658	switch (OpNum) {
17659	case `3`:
17660	// op: Ii
17661	return `3`;
17662	case `1`:
17663	// op: Pv4
17664	return `0`;
17665	case `4`:
17666	// op: Nt8
17667	return `8`;
17668	case `0`:
17669	// op: Rx32
17670	return `16`;
17671	}
17672	break;
17673	}
17674	case Hexagon::S2_pstorerbf_pi:
17675	case Hexagon::S2_pstorerbfnew_pi:
17676	case Hexagon::S2_pstorerbt_pi:
17677	case Hexagon::S2_pstorerbtnew_pi:
17678	case Hexagon::S2_pstorerff_pi:
17679	case Hexagon::S2_pstorerffnew_pi:
17680	case Hexagon::S2_pstorerft_pi:
17681	case Hexagon::S2_pstorerftnew_pi:
17682	case Hexagon::S2_pstorerhf_pi:
17683	case Hexagon::S2_pstorerhfnew_pi:
17684	case Hexagon::S2_pstorerht_pi:
17685	case Hexagon::S2_pstorerhtnew_pi:
17686	case Hexagon::S2_pstorerif_pi:
17687	case Hexagon::S2_pstorerifnew_pi:
17688	case Hexagon::S2_pstorerit_pi:
17689	case Hexagon::S2_pstoreritnew_pi: {
17690	switch (OpNum) {
17691	case `3`:
17692	// op: Ii
17693	return `3`;
17694	case `1`:
17695	// op: Pv4
17696	return `0`;
17697	case `4`:
17698	// op: Rt32
17699	return `8`;
17700	case `0`:
17701	// op: Rx32
17702	return `16`;
17703	}
17704	break;
17705	}
17706	case Hexagon::S2_pstorerdf_pi:
17707	case Hexagon::S2_pstorerdfnew_pi:
17708	case Hexagon::S2_pstorerdt_pi:
17709	case Hexagon::S2_pstorerdtnew_pi: {
17710	switch (OpNum) {
17711	case `3`:
17712	// op: Ii
17713	return `3`;
17714	case `1`:
17715	// op: Pv4
17716	return `0`;
17717	case `4`:
17718	// op: Rtt32
17719	return `8`;
17720	case `0`:
17721	// op: Rx32
17722	return `16`;
17723	}
17724	break;
17725	}
17726	case Hexagon::L2_loadbsw2_pi:
17727	case Hexagon::L2_loadbzw2_pi:
17728	case Hexagon::L2_loadrb_pi:
17729	case Hexagon::L2_loadrh_pi:
17730	case Hexagon::L2_loadri_pi:
17731	case Hexagon::L2_loadrub_pi:
17732	case Hexagon::L2_loadruh_pi: {
17733	switch (OpNum) {
17734	case `3`:
17735	// op: Ii
17736	return `5`;
17737	case `0`:
17738	// op: Rd32
17739	return `0`;
17740	case `1`:
17741	// op: Rx32
17742	return `16`;
17743	}
17744	break;
17745	}
17746	case Hexagon::L2_loadbsw4_pi:
17747	case Hexagon::L2_loadbzw4_pi:
17748	case Hexagon::L2_loadrd_pi: {
17749	switch (OpNum) {
17750	case `3`:
17751	// op: Ii
17752	return `5`;
17753	case `0`:
17754	// op: Rdd32
17755	return `0`;
17756	case `1`:
17757	// op: Rx32
17758	return `16`;
17759	}
17760	break;
17761	}
17762	case Hexagon::L2_ploadrbf_io:
17763	case Hexagon::L2_ploadrbfnew_io:
17764	case Hexagon::L2_ploadrbt_io:
17765	case Hexagon::L2_ploadrbtnew_io:
17766	case Hexagon::L2_ploadrhf_io:
17767	case Hexagon::L2_ploadrhfnew_io:
17768	case Hexagon::L2_ploadrht_io:
17769	case Hexagon::L2_ploadrhtnew_io:
17770	case Hexagon::L2_ploadrif_io:
17771	case Hexagon::L2_ploadrifnew_io:
17772	case Hexagon::L2_ploadrit_io:
17773	case Hexagon::L2_ploadritnew_io:
17774	case Hexagon::L2_ploadrubf_io:
17775	case Hexagon::L2_ploadrubfnew_io:
17776	case Hexagon::L2_ploadrubt_io:
17777	case Hexagon::L2_ploadrubtnew_io:
17778	case Hexagon::L2_ploadruhf_io:
17779	case Hexagon::L2_ploadruhfnew_io:
17780	case Hexagon::L2_ploadruht_io:
17781	case Hexagon::L2_ploadruhtnew_io: {
17782	switch (OpNum) {
17783	case `3`:
17784	// op: Ii
17785	return `5`;
17786	case `1`:
17787	// op: Pt4
17788	return `11`;
17789	case `2`:
17790	// op: Rs32
17791	return `16`;
17792	case `0`:
17793	// op: Rd32
17794	return `0`;
17795	}
17796	break;
17797	}
17798	case Hexagon::L2_ploadrdf_io:
17799	case Hexagon::L2_ploadrdfnew_io:
17800	case Hexagon::L2_ploadrdt_io:
17801	case Hexagon::L2_ploadrdtnew_io: {
17802	switch (OpNum) {
17803	case `3`:
17804	// op: Ii
17805	return `5`;
17806	case `1`:
17807	// op: Pt4
17808	return `11`;
17809	case `2`:
17810	// op: Rs32
17811	return `16`;
17812	case `0`:
17813	// op: Rdd32
17814	return `0`;
17815	}
17816	break;
17817	}
17818	case Hexagon::A2_paddif:
17819	case Hexagon::A2_paddifnew:
17820	case Hexagon::A2_paddit:
17821	case Hexagon::A2_padditnew:
17822	case Hexagon::C2_muxir: {
17823	switch (OpNum) {
17824	case `3`:
17825	// op: Ii
17826	return `5`;
17827	case `1`:
17828	// op: Pu4
17829	return `21`;
17830	case `2`:
17831	// op: Rs32
17832	return `16`;
17833	case `0`:
17834	// op: Rd32
17835	return `0`;
17836	}
17837	break;
17838	}
17839	case Hexagon::S4_addaddi: {
17840	switch (OpNum) {
17841	case `3`:
17842	// op: Ii
17843	return `5`;
17844	case `1`:
17845	// op: Rs32
17846	return `16`;
17847	case `2`:
17848	// op: Ru32
17849	return `0`;
17850	case `0`:
17851	// op: Rd32
17852	return `8`;
17853	}
17854	break;
17855	}
17856	case Hexagon::S4_vrcrotate: {
17857	switch (OpNum) {
17858	case `3`:
17859	// op: Ii
17860	return `5`;
17861	case `1`:
17862	// op: Rss32
17863	return `16`;
17864	case `2`:
17865	// op: Rt32
17866	return `8`;
17867	case `0`:
17868	// op: Rdd32
17869	return `0`;
17870	}
17871	break;
17872	}
17873	case Hexagon::S2_vspliceib: {
17874	switch (OpNum) {
17875	case `3`:
17876	// op: Ii
17877	return `5`;
17878	case `1`:
17879	// op: Rss32
17880	return `16`;
17881	case `2`:
17882	// op: Rtt32
17883	return `8`;
17884	case `0`:
17885	// op: Rdd32
17886	return `0`;
17887	}
17888	break;
17889	}
17890	case Hexagon::S2_addasl_rrri: {
17891	switch (OpNum) {
17892	case `3`:
17893	// op: Ii
17894	return `5`;
17895	case `1`:
17896	// op: Rt32
17897	return `8`;
17898	case `2`:
17899	// op: Rs32
17900	return `16`;
17901	case `0`:
17902	// op: Rd32
17903	return `0`;
17904	}
17905	break;
17906	}
17907	case Hexagon::S2_valignib: {
17908	switch (OpNum) {
17909	case `3`:
17910	// op: Ii
17911	return `5`;
17912	case `1`:
17913	// op: Rtt32
17914	return `8`;
17915	case `2`:
17916	// op: Rss32
17917	return `16`;
17918	case `0`:
17919	// op: Rdd32
17920	return `0`;
17921	}
17922	break;
17923	}
17924	case Hexagon::S4_or_andix: {
17925	switch (OpNum) {
17926	case `3`:
17927	// op: Ii
17928	return `5`;
17929	case `1`:
17930	// op: Ru32
17931	return `0`;
17932	case `0`:
17933	// op: Rx32
17934	return `16`;
17935	}
17936	break;
17937	}
17938	case Hexagon::M4_mpyri_addr: {
17939	switch (OpNum) {
17940	case `3`:
17941	// op: Ii
17942	return `5`;
17943	case `1`:
17944	// op: Ru32
17945	return `0`;
17946	case `2`:
17947	// op: Rs32
17948	return `16`;
17949	case `0`:
17950	// op: Rd32
17951	return `8`;
17952	}
17953	break;
17954	}
17955	case Hexagon::V6_valignbi:
17956	case Hexagon::V6_vlalignbi:
17957	case Hexagon::V6_vlutvvbi: {
17958	switch (OpNum) {
17959	case `3`:
17960	// op: Ii
17961	return `5`;
17962	case `1`:
17963	// op: Vu32
17964	return `8`;
17965	case `2`:
17966	// op: Vv32
17967	return `16`;
17968	case `0`:
17969	// op: Vd32
17970	return `0`;
17971	}
17972	break;
17973	}
17974	case Hexagon::V6_vlutvwhi: {
17975	switch (OpNum) {
17976	case `3`:
17977	// op: Ii
17978	return `5`;
17979	case `1`:
17980	// op: Vu32
17981	return `8`;
17982	case `2`:
17983	// op: Vv32
17984	return `16`;
17985	case `0`:
17986	// op: Vdd32
17987	return `0`;
17988	}
17989	break;
17990	}
17991	case Hexagon::V6_vrmpybusi:
17992	case Hexagon::V6_vrmpyubi:
17993	case Hexagon::V6_vrsadubi: {
17994	switch (OpNum) {
17995	case `3`:
17996	// op: Ii
17997	return `5`;
17998	case `1`:
17999	// op: Vuu32
18000	return `8`;
18001	case `2`:
18002	// op: Rt32
18003	return `16`;
18004	case `0`:
18005	// op: Vdd32
18006	return `0`;
18007	}
18008	break;
18009	}
18010	case Hexagon::V6_v6mpyhubs10:
18011	case Hexagon::V6_v6mpyvubs10: {
18012	switch (OpNum) {
18013	case `3`:
18014	// op: Ii
18015	return `5`;
18016	case `1`:
18017	// op: Vuu32
18018	return `8`;
18019	case `2`:
18020	// op: Vvv32
18021	return `16`;
18022	case `0`:
18023	// op: Vdd32
18024	return `0`;
18025	}
18026	break;
18027	}
18028	case Hexagon::M2_accii:
18029	case Hexagon::M2_macsin:
18030	case Hexagon::M2_macsip:
18031	case Hexagon::M2_naccii:
18032	case Hexagon::S4_or_andi:
18033	case Hexagon::S4_or_ori: {
18034	switch (OpNum) {
18035	case `3`:
18036	// op: Ii
18037	return `5`;
18038	case `2`:
18039	// op: Rs32
18040	return `16`;
18041	case `0`:
18042	// op: Rx32
18043	return `0`;
18044	}
18045	break;
18046	}
18047	case Hexagon::L2_loadalignb_io:
18048	case Hexagon::L2_loadalignh_io: {
18049	switch (OpNum) {
18050	case `3`:
18051	// op: Ii
18052	return `5`;
18053	case `2`:
18054	// op: Rs32
18055	return `16`;
18056	case `0`:
18057	// op: Ryy32
18058	return `0`;
18059	}
18060	break;
18061	}
18062	case Hexagon::S2_tableidxb:
18063	case Hexagon::S2_tableidxd:
18064	case Hexagon::S2_tableidxh:
18065	case Hexagon::S2_tableidxw: {
18066	switch (OpNum) {
18067	case `3`:
18068	// op: Ii
18069	return `5`;
18070	case `4`:
18071	// op: II
18072	return `8`;
18073	case `2`:
18074	// op: Rs32
18075	return `16`;
18076	case `0`:
18077	// op: Rx32
18078	return `0`;
18079	}
18080	break;
18081	}
18082	case Hexagon::L2_loadbsw2_pci:
18083	case Hexagon::L2_loadbzw2_pci:
18084	case Hexagon::L2_loadrb_pci:
18085	case Hexagon::L2_loadrh_pci:
18086	case Hexagon::L2_loadri_pci:
18087	case Hexagon::L2_loadrub_pci:
18088	case Hexagon::L2_loadruh_pci: {
18089	switch (OpNum) {
18090	case `3`:
18091	// op: Ii
18092	return `5`;
18093	case `4`:
18094	// op: Mu2
18095	return `13`;
18096	case `0`:
18097	// op: Rd32
18098	return `0`;
18099	case `1`:
18100	// op: Rx32
18101	return `16`;
18102	}
18103	break;
18104	}
18105	case Hexagon::L2_loadbsw4_pci:
18106	case Hexagon::L2_loadbzw4_pci:
18107	case Hexagon::L2_loadrd_pci: {
18108	switch (OpNum) {
18109	case `3`:
18110	// op: Ii
18111	return `5`;
18112	case `4`:
18113	// op: Mu2
18114	return `13`;
18115	case `0`:
18116	// op: Rdd32
18117	return `0`;
18118	case `1`:
18119	// op: Rx32
18120	return `16`;
18121	}
18122	break;
18123	}
18124	case Hexagon::S4_pstorerbnewf_rr:
18125	case Hexagon::S4_pstorerbnewfnew_rr:
18126	case Hexagon::S4_pstorerbnewt_rr:
18127	case Hexagon::S4_pstorerbnewtnew_rr:
18128	case Hexagon::S4_pstorerhnewf_rr:
18129	case Hexagon::S4_pstorerhnewfnew_rr:
18130	case Hexagon::S4_pstorerhnewt_rr:
18131	case Hexagon::S4_pstorerhnewtnew_rr:
18132	case Hexagon::S4_pstorerinewf_rr:
18133	case Hexagon::S4_pstorerinewfnew_rr:
18134	case Hexagon::S4_pstorerinewt_rr:
18135	case Hexagon::S4_pstorerinewtnew_rr: {
18136	switch (OpNum) {
18137	case `3`:
18138	// op: Ii
18139	return `7`;
18140	case `0`:
18141	// op: Pv4
18142	return `5`;
18143	case `1`:
18144	// op: Rs32
18145	return `16`;
18146	case `2`:
18147	// op: Ru32
18148	return `8`;
18149	case `4`:
18150	// op: Nt8
18151	return `0`;
18152	}
18153	break;
18154	}
18155	case Hexagon::S4_pstorerbf_rr:
18156	case Hexagon::S4_pstorerbfnew_rr:
18157	case Hexagon::S4_pstorerbt_rr:
18158	case Hexagon::S4_pstorerbtnew_rr:
18159	case Hexagon::S4_pstorerff_rr:
18160	case Hexagon::S4_pstorerffnew_rr:
18161	case Hexagon::S4_pstorerft_rr:
18162	case Hexagon::S4_pstorerftnew_rr:
18163	case Hexagon::S4_pstorerhf_rr:
18164	case Hexagon::S4_pstorerhfnew_rr:
18165	case Hexagon::S4_pstorerht_rr:
18166	case Hexagon::S4_pstorerhtnew_rr:
18167	case Hexagon::S4_pstorerif_rr:
18168	case Hexagon::S4_pstorerifnew_rr:
18169	case Hexagon::S4_pstorerit_rr:
18170	case Hexagon::S4_pstoreritnew_rr: {
18171	switch (OpNum) {
18172	case `3`:
18173	// op: Ii
18174	return `7`;
18175	case `0`:
18176	// op: Pv4
18177	return `5`;
18178	case `1`:
18179	// op: Rs32
18180	return `16`;
18181	case `2`:
18182	// op: Ru32
18183	return `8`;
18184	case `4`:
18185	// op: Rt32
18186	return `0`;
18187	}
18188	break;
18189	}
18190	case Hexagon::S4_pstorerdf_rr:
18191	case Hexagon::S4_pstorerdfnew_rr:
18192	case Hexagon::S4_pstorerdt_rr:
18193	case Hexagon::S4_pstorerdtnew_rr: {
18194	switch (OpNum) {
18195	case `3`:
18196	// op: Ii
18197	return `7`;
18198	case `0`:
18199	// op: Pv4
18200	return `5`;
18201	case `1`:
18202	// op: Rs32
18203	return `16`;
18204	case `2`:
18205	// op: Ru32
18206	return `8`;
18207	case `4`:
18208	// op: Rtt32
18209	return `0`;
18210	}
18211	break;
18212	}
18213	case Hexagon::L4_loadrb_rr:
18214	case Hexagon::L4_loadrh_rr:
18215	case Hexagon::L4_loadri_rr:
18216	case Hexagon::L4_loadrub_rr:
18217	case Hexagon::L4_loadruh_rr: {
18218	switch (OpNum) {
18219	case `3`:
18220	// op: Ii
18221	return `7`;
18222	case `1`:
18223	// op: Rs32
18224	return `16`;
18225	case `2`:
18226	// op: Rt32
18227	return `8`;
18228	case `0`:
18229	// op: Rd32
18230	return `0`;
18231	}
18232	break;
18233	}
18234	case Hexagon::L4_loadrd_rr: {
18235	switch (OpNum) {
18236	case `3`:
18237	// op: Ii
18238	return `7`;
18239	case `1`:
18240	// op: Rs32
18241	return `16`;
18242	case `2`:
18243	// op: Rt32
18244	return `8`;
18245	case `0`:
18246	// op: Rdd32
18247	return `0`;
18248	}
18249	break;
18250	}
18251	case Hexagon::L4_loadalignb_ur:
18252	case Hexagon::L4_loadalignh_ur: {
18253	switch (OpNum) {
18254	case `3`:
18255	// op: Ii
18256	return `7`;
18257	case `4`:
18258	// op: II
18259	return `5`;
18260	case `2`:
18261	// op: Rt32
18262	return `16`;
18263	case `0`:
18264	// op: Ryy32
18265	return `0`;
18266	}
18267	break;
18268	}
18269	case Hexagon::V6_vL32Ub_pi:
18270	case Hexagon::V6_vL32b_cur_pi:
18271	case Hexagon::V6_vL32b_nt_cur_pi:
18272	case Hexagon::V6_vL32b_nt_pi:
18273	case Hexagon::V6_vL32b_nt_tmp_pi:
18274	case Hexagon::V6_vL32b_pi:
18275	case Hexagon::V6_vL32b_tmp_pi: {
18276	switch (OpNum) {
18277	case `3`:
18278	// op: Ii
18279	return `8`;
18280	case `0`:
18281	// op: Vd32
18282	return `0`;
18283	case `1`:
18284	// op: Rx32
18285	return `16`;
18286	}
18287	break;
18288	}
18289	case Hexagon::V6_zLd_pred_pi: {
18290	switch (OpNum) {
18291	case `3`:
18292	// op: Ii
18293	return `8`;
18294	case `1`:
18295	// op: Pv4
18296	return `11`;
18297	case `0`:
18298	// op: Rx32
18299	return `16`;
18300	}
18301	break;
18302	}
18303	case Hexagon::V6_vL32b_cur_npred_ai:
18304	case Hexagon::V6_vL32b_cur_pred_ai:
18305	case Hexagon::V6_vL32b_npred_ai:
18306	case Hexagon::V6_vL32b_nt_cur_npred_ai:
18307	case Hexagon::V6_vL32b_nt_cur_pred_ai:
18308	case Hexagon::V6_vL32b_nt_npred_ai:
18309	case Hexagon::V6_vL32b_nt_pred_ai:
18310	case Hexagon::V6_vL32b_nt_tmp_npred_ai:
18311	case Hexagon::V6_vL32b_nt_tmp_pred_ai:
18312	case Hexagon::V6_vL32b_pred_ai:
18313	case Hexagon::V6_vL32b_tmp_npred_ai:
18314	case Hexagon::V6_vL32b_tmp_pred_ai: {
18315	switch (OpNum) {
18316	case `3`:
18317	// op: Ii
18318	return `8`;
18319	case `1`:
18320	// op: Pv4
18321	return `11`;
18322	case `2`:
18323	// op: Rt32
18324	return `16`;
18325	case `0`:
18326	// op: Vd32
18327	return `0`;
18328	}
18329	break;
18330	}
18331	case Hexagon::V6_vS32b_new_npred_pi:
18332	case Hexagon::V6_vS32b_new_pred_pi:
18333	case Hexagon::V6_vS32b_nt_new_npred_pi:
18334	case Hexagon::V6_vS32b_nt_new_pred_pi: {
18335	switch (OpNum) {
18336	case `3`:
18337	// op: Ii
18338	return `8`;
18339	case `1`:
18340	// op: Pv4
18341	return `11`;
18342	case `4`:
18343	// op: Os8
18344	return `0`;
18345	case `0`:
18346	// op: Rx32
18347	return `16`;
18348	}
18349	break;
18350	}
18351	case Hexagon::V6_vS32Ub_npred_pi:
18352	case Hexagon::V6_vS32Ub_pred_pi:
18353	case Hexagon::V6_vS32b_npred_pi:
18354	case Hexagon::V6_vS32b_nt_npred_pi:
18355	case Hexagon::V6_vS32b_nt_pred_pi:
18356	case Hexagon::V6_vS32b_pred_pi: {
18357	switch (OpNum) {
18358	case `3`:
18359	// op: Ii
18360	return `8`;
18361	case `1`:
18362	// op: Pv4
18363	return `11`;
18364	case `4`:
18365	// op: Vs32
18366	return `0`;
18367	case `0`:
18368	// op: Rx32
18369	return `16`;
18370	}
18371	break;
18372	}
18373	case Hexagon::V6_vS32b_nqpred_pi:
18374	case Hexagon::V6_vS32b_nt_nqpred_pi:
18375	case Hexagon::V6_vS32b_nt_qpred_pi:
18376	case Hexagon::V6_vS32b_qpred_pi: {
18377	switch (OpNum) {
18378	case `3`:
18379	// op: Ii
18380	return `8`;
18381	case `1`:
18382	// op: Qv4
18383	return `11`;
18384	case `4`:
18385	// op: Vs32
18386	return `0`;
18387	case `0`:
18388	// op: Rx32
18389	return `16`;
18390	}
18391	break;
18392	}
18393	case Hexagon::S2_asl_i_r_acc:
18394	case Hexagon::S2_asl_i_r_and:
18395	case Hexagon::S2_asl_i_r_nac:
18396	case Hexagon::S2_asl_i_r_or:
18397	case Hexagon::S2_asl_i_r_xacc:
18398	case Hexagon::S2_asr_i_r_acc:
18399	case Hexagon::S2_asr_i_r_and:
18400	case Hexagon::S2_asr_i_r_nac:
18401	case Hexagon::S2_asr_i_r_or:
18402	case Hexagon::S2_lsr_i_r_acc:
18403	case Hexagon::S2_lsr_i_r_and:
18404	case Hexagon::S2_lsr_i_r_nac:
18405	case Hexagon::S2_lsr_i_r_or:
18406	case Hexagon::S2_lsr_i_r_xacc:
18407	case Hexagon::S6_rol_i_r_acc:
18408	case Hexagon::S6_rol_i_r_and:
18409	case Hexagon::S6_rol_i_r_nac:
18410	case Hexagon::S6_rol_i_r_or:
18411	case Hexagon::S6_rol_i_r_xacc: {
18412	switch (OpNum) {
18413	case `3`:
18414	// op: Ii
18415	return `8`;
18416	case `2`:
18417	// op: Rs32
18418	return `16`;
18419	case `0`:
18420	// op: Rx32
18421	return `0`;
18422	}
18423	break;
18424	}
18425	case Hexagon::S2_asl_i_p_acc:
18426	case Hexagon::S2_asl_i_p_and:
18427	case Hexagon::S2_asl_i_p_nac:
18428	case Hexagon::S2_asl_i_p_or:
18429	case Hexagon::S2_asl_i_p_xacc:
18430	case Hexagon::S2_asr_i_p_acc:
18431	case Hexagon::S2_asr_i_p_and:
18432	case Hexagon::S2_asr_i_p_nac:
18433	case Hexagon::S2_asr_i_p_or:
18434	case Hexagon::S2_lsr_i_p_acc:
18435	case Hexagon::S2_lsr_i_p_and:
18436	case Hexagon::S2_lsr_i_p_nac:
18437	case Hexagon::S2_lsr_i_p_or:
18438	case Hexagon::S2_lsr_i_p_xacc:
18439	case Hexagon::S6_rol_i_p_acc:
18440	case Hexagon::S6_rol_i_p_and:
18441	case Hexagon::S6_rol_i_p_nac:
18442	case Hexagon::S6_rol_i_p_or:
18443	case Hexagon::S6_rol_i_p_xacc: {
18444	switch (OpNum) {
18445	case `3`:
18446	// op: Ii
18447	return `8`;
18448	case `2`:
18449	// op: Rss32
18450	return `16`;
18451	case `0`:
18452	// op: Rxx32
18453	return `0`;
18454	}
18455	break;
18456	}
18457	case Hexagon::S2_insert: {
18458	switch (OpNum) {
18459	case `3`:
18460	// op: Ii
18461	return `8`;
18462	case `4`:
18463	// op: II
18464	return `5`;
18465	case `2`:
18466	// op: Rs32
18467	return `16`;
18468	case `0`:
18469	// op: Rx32
18470	return `0`;
18471	}
18472	break;
18473	}
18474	case Hexagon::S2_insertp: {
18475	switch (OpNum) {
18476	case `3`:
18477	// op: Ii
18478	return `8`;
18479	case `4`:
18480	// op: II
18481	return `5`;
18482	case `2`:
18483	// op: Rss32
18484	return `16`;
18485	case `0`:
18486	// op: Rxx32
18487	return `0`;
18488	}
18489	break;
18490	}
18491	case Hexagon::L2_loadbsw2_pbr:
18492	case Hexagon::L2_loadbsw2_pcr:
18493	case Hexagon::L2_loadbsw2_pr:
18494	case Hexagon::L2_loadbzw2_pbr:
18495	case Hexagon::L2_loadbzw2_pcr:
18496	case Hexagon::L2_loadbzw2_pr:
18497	case Hexagon::L2_loadrb_pbr:
18498	case Hexagon::L2_loadrb_pcr:
18499	case Hexagon::L2_loadrb_pr:
18500	case Hexagon::L2_loadrh_pbr:
18501	case Hexagon::L2_loadrh_pcr:
18502	case Hexagon::L2_loadrh_pr:
18503	case Hexagon::L2_loadri_pbr:
18504	case Hexagon::L2_loadri_pcr:
18505	case Hexagon::L2_loadri_pr:
18506	case Hexagon::L2_loadrub_pbr:
18507	case Hexagon::L2_loadrub_pcr:
18508	case Hexagon::L2_loadrub_pr:
18509	case Hexagon::L2_loadruh_pbr:
18510	case Hexagon::L2_loadruh_pcr:
18511	case Hexagon::L2_loadruh_pr: {
18512	switch (OpNum) {
18513	case `3`:
18514	// op: Mu2
18515	return `13`;
18516	case `0`:
18517	// op: Rd32
18518	return `0`;
18519	case `1`:
18520	// op: Rx32
18521	return `16`;
18522	}
18523	break;
18524	}
18525	case Hexagon::L2_loadbsw4_pbr:
18526	case Hexagon::L2_loadbsw4_pcr:
18527	case Hexagon::L2_loadbsw4_pr:
18528	case Hexagon::L2_loadbzw4_pbr:
18529	case Hexagon::L2_loadbzw4_pcr:
18530	case Hexagon::L2_loadbzw4_pr:
18531	case Hexagon::L2_loadrd_pbr:
18532	case Hexagon::L2_loadrd_pcr:
18533	case Hexagon::L2_loadrd_pr: {
18534	switch (OpNum) {
18535	case `3`:
18536	// op: Mu2
18537	return `13`;
18538	case `0`:
18539	// op: Rdd32
18540	return `0`;
18541	case `1`:
18542	// op: Rx32
18543	return `16`;
18544	}
18545	break;
18546	}
18547	case Hexagon::V6_vL32Ub_ppu:
18548	case Hexagon::V6_vL32b_cur_ppu:
18549	case Hexagon::V6_vL32b_nt_cur_ppu:
18550	case Hexagon::V6_vL32b_nt_ppu:
18551	case Hexagon::V6_vL32b_nt_tmp_ppu:
18552	case Hexagon::V6_vL32b_ppu:
18553	case Hexagon::V6_vL32b_tmp_ppu: {
18554	switch (OpNum) {
18555	case `3`:
18556	// op: Mu2
18557	return `13`;
18558	case `0`:
18559	// op: Vd32
18560	return `0`;
18561	case `1`:
18562	// op: Rx32
18563	return `16`;
18564	}
18565	break;
18566	}
18567	case Hexagon::A5_ACS: {
18568	switch (OpNum) {
18569	case `3`:
18570	// op: Rss32
18571	return `16`;
18572	case `4`:
18573	// op: Rtt32
18574	return `8`;
18575	case `0`:
18576	// op: Rxx32
18577	return `0`;
18578	case `1`:
18579	// op: Pe4
18580	return `5`;
18581	}
18582	break;
18583	}
18584	case Hexagon::V6_vrmpyzbb_rx_acc:
18585	case Hexagon::V6_vrmpyzbub_rx_acc:
18586	case Hexagon::V6_vrmpyzcb_rx_acc:
18587	case Hexagon::V6_vrmpyzcbs_rx_acc:
18588	case Hexagon::V6_vrmpyznb_rx_acc: {
18589	switch (OpNum) {
18590	case `3`:
18591	// op: Vu32
18592	return `8`;
18593	case `0`:
18594	// op: Vyyyy32
18595	return `0`;
18596	case `1`:
18597	// op: Rx8
18598	return `16`;
18599	}
18600	break;
18601	}
18602	case Hexagon::L2_loadalignb_pi:
18603	case Hexagon::L2_loadalignh_pi: {
18604	switch (OpNum) {
18605	case `4`:
18606	// op: Ii
18607	return `5`;
18608	case `0`:
18609	// op: Ryy32
18610	return `0`;
18611	case `1`:
18612	// op: Rx32
18613	return `16`;
18614	}
18615	break;
18616	}
18617	case Hexagon::L2_ploadrbf_pi:
18618	case Hexagon::L2_ploadrbfnew_pi:
18619	case Hexagon::L2_ploadrbt_pi:
18620	case Hexagon::L2_ploadrbtnew_pi:
18621	case Hexagon::L2_ploadrhf_pi:
18622	case Hexagon::L2_ploadrhfnew_pi:
18623	case Hexagon::L2_ploadrht_pi:
18624	case Hexagon::L2_ploadrhtnew_pi:
18625	case Hexagon::L2_ploadrif_pi:
18626	case Hexagon::L2_ploadrifnew_pi:
18627	case Hexagon::L2_ploadrit_pi:
18628	case Hexagon::L2_ploadritnew_pi:
18629	case Hexagon::L2_ploadrubf_pi:
18630	case Hexagon::L2_ploadrubfnew_pi:
18631	case Hexagon::L2_ploadrubt_pi:
18632	case Hexagon::L2_ploadrubtnew_pi:
18633	case Hexagon::L2_ploadruhf_pi:
18634	case Hexagon::L2_ploadruhfnew_pi:
18635	case Hexagon::L2_ploadruht_pi:
18636	case Hexagon::L2_ploadruhtnew_pi: {
18637	switch (OpNum) {
18638	case `4`:
18639	// op: Ii
18640	return `5`;
18641	case `2`:
18642	// op: Pt4
18643	return `9`;
18644	case `0`:
18645	// op: Rd32
18646	return `0`;
18647	case `1`:
18648	// op: Rx32
18649	return `16`;
18650	}
18651	break;
18652	}
18653	case Hexagon::L2_ploadrdf_pi:
18654	case Hexagon::L2_ploadrdfnew_pi:
18655	case Hexagon::L2_ploadrdt_pi:
18656	case Hexagon::L2_ploadrdtnew_pi: {
18657	switch (OpNum) {
18658	case `4`:
18659	// op: Ii
18660	return `5`;
18661	case `2`:
18662	// op: Pt4
18663	return `9`;
18664	case `0`:
18665	// op: Rdd32
18666	return `0`;
18667	case `1`:
18668	// op: Rx32
18669	return `16`;
18670	}
18671	break;
18672	}
18673	case Hexagon::S4_vrcrotate_acc: {
18674	switch (OpNum) {
18675	case `4`:
18676	// op: Ii
18677	return `5`;
18678	case `2`:
18679	// op: Rss32
18680	return `16`;
18681	case `3`:
18682	// op: Rt32
18683	return `8`;
18684	case `0`:
18685	// op: Rxx32
18686	return `0`;
18687	}
18688	break;
18689	}
18690	case Hexagon::V6_vlutvvb_oracci: {
18691	switch (OpNum) {
18692	case `4`:
18693	// op: Ii
18694	return `5`;
18695	case `2`:
18696	// op: Vu32
18697	return `8`;
18698	case `3`:
18699	// op: Vv32
18700	return `16`;
18701	case `0`:
18702	// op: Vx32
18703	return `0`;
18704	}
18705	break;
18706	}
18707	case Hexagon::V6_vlutvwh_oracci: {
18708	switch (OpNum) {
18709	case `4`:
18710	// op: Ii
18711	return `5`;
18712	case `2`:
18713	// op: Vu32
18714	return `8`;
18715	case `3`:
18716	// op: Vv32
18717	return `16`;
18718	case `0`:
18719	// op: Vxx32
18720	return `0`;
18721	}
18722	break;
18723	}
18724	case Hexagon::V6_vrmpybusi_acc:
18725	case Hexagon::V6_vrmpyubi_acc:
18726	case Hexagon::V6_vrsadubi_acc: {
18727	switch (OpNum) {
18728	case `4`:
18729	// op: Ii
18730	return `5`;
18731	case `2`:
18732	// op: Vuu32
18733	return `8`;
18734	case `3`:
18735	// op: Rt32
18736	return `16`;
18737	case `0`:
18738	// op: Vxx32
18739	return `0`;
18740	}
18741	break;
18742	}
18743	case Hexagon::V6_v6mpyhubs10_vxx:
18744	case Hexagon::V6_v6mpyvubs10_vxx: {
18745	switch (OpNum) {
18746	case `4`:
18747	// op: Ii
18748	return `5`;
18749	case `2`:
18750	// op: Vuu32
18751	return `8`;
18752	case `3`:
18753	// op: Vvv32
18754	return `16`;
18755	case `0`:
18756	// op: Vxx32
18757	return `0`;
18758	}
18759	break;
18760	}
18761	case Hexagon::L2_loadalignb_pci:
18762	case Hexagon::L2_loadalignh_pci: {
18763	switch (OpNum) {
18764	case `4`:
18765	// op: Ii
18766	return `5`;
18767	case `5`:
18768	// op: Mu2
18769	return `13`;
18770	case `0`:
18771	// op: Ryy32
18772	return `0`;
18773	case `1`:
18774	// op: Rx32
18775	return `16`;
18776	}
18777	break;
18778	}
18779	case Hexagon::L4_ploadrbf_rr:
18780	case Hexagon::L4_ploadrbfnew_rr:
18781	case Hexagon::L4_ploadrbt_rr:
18782	case Hexagon::L4_ploadrbtnew_rr:
18783	case Hexagon::L4_ploadrhf_rr:
18784	case Hexagon::L4_ploadrhfnew_rr:
18785	case Hexagon::L4_ploadrht_rr:
18786	case Hexagon::L4_ploadrhtnew_rr:
18787	case Hexagon::L4_ploadrif_rr:
18788	case Hexagon::L4_ploadrifnew_rr:
18789	case Hexagon::L4_ploadrit_rr:
18790	case Hexagon::L4_ploadritnew_rr:
18791	case Hexagon::L4_ploadrubf_rr:
18792	case Hexagon::L4_ploadrubfnew_rr:
18793	case Hexagon::L4_ploadrubt_rr:
18794	case Hexagon::L4_ploadrubtnew_rr:
18795	case Hexagon::L4_ploadruhf_rr:
18796	case Hexagon::L4_ploadruhfnew_rr:
18797	case Hexagon::L4_ploadruht_rr:
18798	case Hexagon::L4_ploadruhtnew_rr: {
18799	switch (OpNum) {
18800	case `4`:
18801	// op: Ii
18802	return `7`;
18803	case `1`:
18804	// op: Pv4
18805	return `5`;
18806	case `2`:
18807	// op: Rs32
18808	return `16`;
18809	case `3`:
18810	// op: Rt32
18811	return `8`;
18812	case `0`:
18813	// op: Rd32
18814	return `0`;
18815	}
18816	break;
18817	}
18818	case Hexagon::L4_ploadrdf_rr:
18819	case Hexagon::L4_ploadrdfnew_rr:
18820	case Hexagon::L4_ploadrdt_rr:
18821	case Hexagon::L4_ploadrdtnew_rr: {
18822	switch (OpNum) {
18823	case `4`:
18824	// op: Ii
18825	return `7`;
18826	case `1`:
18827	// op: Pv4
18828	return `5`;
18829	case `2`:
18830	// op: Rs32
18831	return `16`;
18832	case `3`:
18833	// op: Rt32
18834	return `8`;
18835	case `0`:
18836	// op: Rdd32
18837	return `0`;
18838	}
18839	break;
18840	}
18841	case Hexagon::V6_vL32b_cur_npred_pi:
18842	case Hexagon::V6_vL32b_cur_pred_pi:
18843	case Hexagon::V6_vL32b_npred_pi:
18844	case Hexagon::V6_vL32b_nt_cur_npred_pi:
18845	case Hexagon::V6_vL32b_nt_cur_pred_pi:
18846	case Hexagon::V6_vL32b_nt_npred_pi:
18847	case Hexagon::V6_vL32b_nt_pred_pi:
18848	case Hexagon::V6_vL32b_nt_tmp_npred_pi:
18849	case Hexagon::V6_vL32b_nt_tmp_pred_pi:
18850	case Hexagon::V6_vL32b_pred_pi:
18851	case Hexagon::V6_vL32b_tmp_npred_pi:
18852	case Hexagon::V6_vL32b_tmp_pred_pi: {
18853	switch (OpNum) {
18854	case `4`:
18855	// op: Ii
18856	return `8`;
18857	case `2`:
18858	// op: Pv4
18859	return `11`;
18860	case `0`:
18861	// op: Vd32
18862	return `0`;
18863	case `1`:
18864	// op: Rx32
18865	return `16`;
18866	}
18867	break;
18868	}
18869	case Hexagon::L2_loadalignb_pbr:
18870	case Hexagon::L2_loadalignb_pcr:
18871	case Hexagon::L2_loadalignb_pr:
18872	case Hexagon::L2_loadalignh_pbr:
18873	case Hexagon::L2_loadalignh_pcr:
18874	case Hexagon::L2_loadalignh_pr: {
18875	switch (OpNum) {
18876	case `4`:
18877	// op: Mu2
18878	return `13`;
18879	case `0`:
18880	// op: Ryy32
18881	return `0`;
18882	case `1`:
18883	// op: Rx32
18884	return `16`;
18885	}
18886	break;
18887	}
18888	case Hexagon::V6_vdeal:
18889	case Hexagon::V6_vshuff: {
18890	switch (OpNum) {
18891	case `4`:
18892	// op: Rt32
18893	return `16`;
18894	case `0`:
18895	// op: Vy32
18896	return `8`;
18897	case `1`:
18898	// op: Vx32
18899	return `0`;
18900	}
18901	break;
18902	}
18903	}
18904	std::string msg;
18905	raw_string_ostream Msg(msg);
18906	Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
18907	report_fatal_error(Msg.str().c_str());
18908	}
18909
18910	#endif // GET_OPERAND_BIT_OFFSET
18911
18912

Browse the source code of llvm_projects/build/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc