1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(3145728), // ADC_B
406 UINT64_C(3244032), // ADC_D
407 UINT64_C(3178496), // ADC_H
408 UINT64_C(3211264), // ADC_W
409 UINT64_C(46137344), // ADDI_D
410 UINT64_C(41943040), // ADDI_W
411 UINT64_C(2719744), // ADDU12I_D
412 UINT64_C(2686976), // ADDU12I_W
413 UINT64_C(268435456), // ADDU16I_D
414 UINT64_C(1081344), // ADD_D
415 UINT64_C(1048576), // ADD_W
416 UINT64_C(2883584), // ALSL_D
417 UINT64_C(262144), // ALSL_W
418 UINT64_C(393216), // ALSL_WU
419 UINT64_C(945618944), // AMADD_B
420 UINT64_C(945913856), // AMADD_D
421 UINT64_C(945651712), // AMADD_H
422 UINT64_C(945881088), // AMADD_W
423 UINT64_C(945750016), // AMADD__DB_B
424 UINT64_C(946503680), // AMADD__DB_D
425 UINT64_C(945782784), // AMADD__DB_H
426 UINT64_C(946470912), // AMADD__DB_W
427 UINT64_C(945979392), // AMAND_D
428 UINT64_C(945946624), // AMAND_W
429 UINT64_C(946569216), // AMAND__DB_D
430 UINT64_C(946536448), // AMAND__DB_W
431 UINT64_C(945291264), // AMCAS_B
432 UINT64_C(945389568), // AMCAS_D
433 UINT64_C(945324032), // AMCAS_H
434 UINT64_C(945356800), // AMCAS_W
435 UINT64_C(945422336), // AMCAS__DB_B
436 UINT64_C(945520640), // AMCAS__DB_D
437 UINT64_C(945455104), // AMCAS__DB_H
438 UINT64_C(945487872), // AMCAS__DB_W
439 UINT64_C(946176000), // AMMAX_D
440 UINT64_C(946307072), // AMMAX_DU
441 UINT64_C(946143232), // AMMAX_W
442 UINT64_C(946274304), // AMMAX_WU
443 UINT64_C(946765824), // AMMAX__DB_D
444 UINT64_C(946896896), // AMMAX__DB_DU
445 UINT64_C(946733056), // AMMAX__DB_W
446 UINT64_C(946864128), // AMMAX__DB_WU
447 UINT64_C(946241536), // AMMIN_D
448 UINT64_C(946372608), // AMMIN_DU
449 UINT64_C(946208768), // AMMIN_W
450 UINT64_C(946339840), // AMMIN_WU
451 UINT64_C(946831360), // AMMIN__DB_D
452 UINT64_C(946962432), // AMMIN__DB_DU
453 UINT64_C(946798592), // AMMIN__DB_W
454 UINT64_C(946929664), // AMMIN__DB_WU
455 UINT64_C(946044928), // AMOR_D
456 UINT64_C(946012160), // AMOR_W
457 UINT64_C(946634752), // AMOR__DB_D
458 UINT64_C(946601984), // AMOR__DB_W
459 UINT64_C(945553408), // AMSWAP_B
460 UINT64_C(945848320), // AMSWAP_D
461 UINT64_C(945586176), // AMSWAP_H
462 UINT64_C(945815552), // AMSWAP_W
463 UINT64_C(945684480), // AMSWAP__DB_B
464 UINT64_C(946438144), // AMSWAP__DB_D
465 UINT64_C(945717248), // AMSWAP__DB_H
466 UINT64_C(946405376), // AMSWAP__DB_W
467 UINT64_C(946110464), // AMXOR_D
468 UINT64_C(946077696), // AMXOR_W
469 UINT64_C(946700288), // AMXOR__DB_D
470 UINT64_C(946667520), // AMXOR__DB_W
471 UINT64_C(1343488), // AND
472 UINT64_C(54525952), // ANDI
473 UINT64_C(1474560), // ANDN
474 UINT64_C(3670032), // ARMADC_W
475 UINT64_C(3604496), // ARMADD_W
476 UINT64_C(3735568), // ARMAND_W
477 UINT64_C(6029376), // ARMMFFLAG
478 UINT64_C(3555328), // ARMMOVE
479 UINT64_C(4177950), // ARMMOV_D
480 UINT64_C(4177949), // ARMMOV_W
481 UINT64_C(6029408), // ARMMTFLAG
482 UINT64_C(4177948), // ARMNOT_W
483 UINT64_C(3768336), // ARMOR_W
484 UINT64_C(4063248), // ARMROTRI_W
485 UINT64_C(3932176), // ARMROTR_W
486 UINT64_C(4177951), // ARMRRX_W
487 UINT64_C(3702800), // ARMSBC_W
488 UINT64_C(3964944), // ARMSLLI_W
489 UINT64_C(3833872), // ARMSLL_W
490 UINT64_C(4030480), // ARMSRAI_W
491 UINT64_C(3899408), // ARMSRA_W
492 UINT64_C(3997712), // ARMSRLI_W
493 UINT64_C(3866640), // ARMSRL_W
494 UINT64_C(3637264), // ARMSUB_W
495 UINT64_C(3801104), // ARMXOR_W
496 UINT64_C(98304), // ASRTGT_D
497 UINT64_C(65536), // ASRTLE_D
498 UINT64_C(1342177280), // B
499 UINT64_C(1207959552), // BCEQZ
500 UINT64_C(1207959808), // BCNEZ
501 UINT64_C(1476395008), // BEQ
502 UINT64_C(1073741824), // BEQZ
503 UINT64_C(1677721600), // BGE
504 UINT64_C(1811939328), // BGEU
505 UINT64_C(18432), // BITREV_4B
506 UINT64_C(19456), // BITREV_8B
507 UINT64_C(21504), // BITREV_D
508 UINT64_C(20480), // BITREV_W
509 UINT64_C(1409286144), // BL
510 UINT64_C(1610612736), // BLT
511 UINT64_C(1744830464), // BLTU
512 UINT64_C(1543503872), // BNE
513 UINT64_C(1140850688), // BNEZ
514 UINT64_C(2752512), // BREAK
515 UINT64_C(8388608), // BSTRINS_D
516 UINT64_C(6291456), // BSTRINS_W
517 UINT64_C(12582912), // BSTRPICK_D
518 UINT64_C(6324224), // BSTRPICK_W
519 UINT64_C(786432), // BYTEPICK_D
520 UINT64_C(524288), // BYTEPICK_W
521 UINT64_C(100663296), // CACOP
522 UINT64_C(8192), // CLO_D
523 UINT64_C(4096), // CLO_W
524 UINT64_C(9216), // CLZ_D
525 UINT64_C(5120), // CLZ_W
526 UINT64_C(27648), // CPUCFG
527 UINT64_C(2490368), // CRCC_W_B_W
528 UINT64_C(2588672), // CRCC_W_D_W
529 UINT64_C(2523136), // CRCC_W_H_W
530 UINT64_C(2555904), // CRCC_W_W_W
531 UINT64_C(2359296), // CRC_W_B_W
532 UINT64_C(2457600), // CRC_W_D_W
533 UINT64_C(2392064), // CRC_W_H_W
534 UINT64_C(2424832), // CRC_W_W_W
535 UINT64_C(67108864), // CSRRD
536 UINT64_C(67108896), // CSRWR
537 UINT64_C(67108864), // CSRXCHG
538 UINT64_C(10240), // CTO_D
539 UINT64_C(6144), // CTO_W
540 UINT64_C(11264), // CTZ_D
541 UINT64_C(7168), // CTZ_W
542 UINT64_C(946995200), // DBAR
543 UINT64_C(2785280), // DBCL
544 UINT64_C(2228224), // DIV_D
545 UINT64_C(2293760), // DIV_DU
546 UINT64_C(2097152), // DIV_W
547 UINT64_C(2162688), // DIV_WU
548 UINT64_C(105396224), // ERTN
549 UINT64_C(23552), // EXT_W_B
550 UINT64_C(22528), // EXT_W_H
551 UINT64_C(18089984), // FABS_D
552 UINT64_C(18088960), // FABS_S
553 UINT64_C(16842752), // FADD_D
554 UINT64_C(16809984), // FADD_S
555 UINT64_C(18102272), // FCLASS_D
556 UINT64_C(18101248), // FCLASS_S
557 UINT64_C(203423744), // FCMP_CAF_D
558 UINT64_C(202375168), // FCMP_CAF_S
559 UINT64_C(203554816), // FCMP_CEQ_D
560 UINT64_C(202506240), // FCMP_CEQ_S
561 UINT64_C(203620352), // FCMP_CLE_D
562 UINT64_C(202571776), // FCMP_CLE_S
563 UINT64_C(203489280), // FCMP_CLT_D
564 UINT64_C(202440704), // FCMP_CLT_S
565 UINT64_C(203948032), // FCMP_CNE_D
566 UINT64_C(202899456), // FCMP_CNE_S
567 UINT64_C(204079104), // FCMP_COR_D
568 UINT64_C(203030528), // FCMP_COR_S
569 UINT64_C(203816960), // FCMP_CUEQ_D
570 UINT64_C(202768384), // FCMP_CUEQ_S
571 UINT64_C(203882496), // FCMP_CULE_D
572 UINT64_C(202833920), // FCMP_CULE_S
573 UINT64_C(203751424), // FCMP_CULT_D
574 UINT64_C(202702848), // FCMP_CULT_S
575 UINT64_C(204210176), // FCMP_CUNE_D
576 UINT64_C(203161600), // FCMP_CUNE_S
577 UINT64_C(203685888), // FCMP_CUN_D
578 UINT64_C(202637312), // FCMP_CUN_S
579 UINT64_C(203456512), // FCMP_SAF_D
580 UINT64_C(202407936), // FCMP_SAF_S
581 UINT64_C(203587584), // FCMP_SEQ_D
582 UINT64_C(202539008), // FCMP_SEQ_S
583 UINT64_C(203653120), // FCMP_SLE_D
584 UINT64_C(202604544), // FCMP_SLE_S
585 UINT64_C(203522048), // FCMP_SLT_D
586 UINT64_C(202473472), // FCMP_SLT_S
587 UINT64_C(203980800), // FCMP_SNE_D
588 UINT64_C(202932224), // FCMP_SNE_S
589 UINT64_C(204111872), // FCMP_SOR_D
590 UINT64_C(203063296), // FCMP_SOR_S
591 UINT64_C(203849728), // FCMP_SUEQ_D
592 UINT64_C(202801152), // FCMP_SUEQ_S
593 UINT64_C(203915264), // FCMP_SULE_D
594 UINT64_C(202866688), // FCMP_SULE_S
595 UINT64_C(203784192), // FCMP_SULT_D
596 UINT64_C(202735616), // FCMP_SULT_S
597 UINT64_C(204242944), // FCMP_SUNE_D
598 UINT64_C(203194368), // FCMP_SUNE_S
599 UINT64_C(203718656), // FCMP_SUN_D
600 UINT64_C(202670080), // FCMP_SUN_S
601 UINT64_C(18022400), // FCOPYSIGN_D
602 UINT64_C(17989632), // FCOPYSIGN_S
603 UINT64_C(18153472), // FCVT_D_LD
604 UINT64_C(18424832), // FCVT_D_S
605 UINT64_C(18145280), // FCVT_LD_D
606 UINT64_C(18421760), // FCVT_S_D
607 UINT64_C(18146304), // FCVT_UD_D
608 UINT64_C(17235968), // FDIV_D
609 UINT64_C(17203200), // FDIV_S
610 UINT64_C(18688000), // FFINT_D_L
611 UINT64_C(18685952), // FFINT_D_W
612 UINT64_C(18683904), // FFINT_S_L
613 UINT64_C(18681856), // FFINT_S_W
614 UINT64_C(947159040), // FLDGT_D
615 UINT64_C(947126272), // FLDGT_S
616 UINT64_C(947224576), // FLDLE_D
617 UINT64_C(947191808), // FLDLE_S
618 UINT64_C(942931968), // FLDX_D
619 UINT64_C(942669824), // FLDX_S
620 UINT64_C(729808896), // FLD_D
621 UINT64_C(721420288), // FLD_S
622 UINT64_C(18098176), // FLOGB_D
623 UINT64_C(18097152), // FLOGB_S
624 UINT64_C(136314880), // FMADD_D
625 UINT64_C(135266304), // FMADD_S
626 UINT64_C(17629184), // FMAXA_D
627 UINT64_C(17596416), // FMAXA_S
628 UINT64_C(17367040), // FMAX_D
629 UINT64_C(17334272), // FMAX_S
630 UINT64_C(17760256), // FMINA_D
631 UINT64_C(17727488), // FMINA_S
632 UINT64_C(17498112), // FMIN_D
633 UINT64_C(17465344), // FMIN_S
634 UINT64_C(18126848), // FMOV_D
635 UINT64_C(18125824), // FMOV_S
636 UINT64_C(140509184), // FMSUB_D
637 UINT64_C(139460608), // FMSUB_S
638 UINT64_C(17104896), // FMUL_D
639 UINT64_C(17072128), // FMUL_S
640 UINT64_C(18094080), // FNEG_D
641 UINT64_C(18093056), // FNEG_S
642 UINT64_C(144703488), // FNMADD_D
643 UINT64_C(143654912), // FNMADD_S
644 UINT64_C(148897792), // FNMSUB_D
645 UINT64_C(147849216), // FNMSUB_S
646 UINT64_C(18118656), // FRECIPE_D
647 UINT64_C(18117632), // FRECIPE_S
648 UINT64_C(18110464), // FRECIP_D
649 UINT64_C(18109440), // FRECIP_S
650 UINT64_C(18761728), // FRINT_D
651 UINT64_C(18760704), // FRINT_S
652 UINT64_C(18122752), // FRSQRTE_D
653 UINT64_C(18121728), // FRSQRTE_S
654 UINT64_C(18114560), // FRSQRT_D
655 UINT64_C(18113536), // FRSQRT_S
656 UINT64_C(17891328), // FSCALEB_D
657 UINT64_C(17858560), // FSCALEB_S
658 UINT64_C(218103808), // FSEL_xD
659 UINT64_C(218103808), // FSEL_xS
660 UINT64_C(18106368), // FSQRT_D
661 UINT64_C(18105344), // FSQRT_S
662 UINT64_C(947290112), // FSTGT_D
663 UINT64_C(947257344), // FSTGT_S
664 UINT64_C(947355648), // FSTLE_D
665 UINT64_C(947322880), // FSTLE_S
666 UINT64_C(943456256), // FSTX_D
667 UINT64_C(943194112), // FSTX_S
668 UINT64_C(734003200), // FST_D
669 UINT64_C(725614592), // FST_S
670 UINT64_C(16973824), // FSUB_D
671 UINT64_C(16941056), // FSUB_S
672 UINT64_C(18491392), // FTINTRM_L_D
673 UINT64_C(18490368), // FTINTRM_L_S
674 UINT64_C(18483200), // FTINTRM_W_D
675 UINT64_C(18482176), // FTINTRM_W_S
676 UINT64_C(18540544), // FTINTRNE_L_D
677 UINT64_C(18539520), // FTINTRNE_L_S
678 UINT64_C(18532352), // FTINTRNE_W_D
679 UINT64_C(18531328), // FTINTRNE_W_S
680 UINT64_C(18507776), // FTINTRP_L_D
681 UINT64_C(18506752), // FTINTRP_L_S
682 UINT64_C(18499584), // FTINTRP_W_D
683 UINT64_C(18498560), // FTINTRP_W_S
684 UINT64_C(18524160), // FTINTRZ_L_D
685 UINT64_C(18523136), // FTINTRZ_L_S
686 UINT64_C(18515968), // FTINTRZ_W_D
687 UINT64_C(18514944), // FTINTRZ_W_S
688 UINT64_C(18556928), // FTINT_L_D
689 UINT64_C(18555904), // FTINT_L_S
690 UINT64_C(18548736), // FTINT_W_D
691 UINT64_C(18547712), // FTINT_W_S
692 UINT64_C(83886080), // GCSRRD
693 UINT64_C(83886112), // GCSRWR
694 UINT64_C(83886080), // GCSRXCHG
695 UINT64_C(105391105), // GTLBFLUSH
696 UINT64_C(2850816), // HVCL
697 UINT64_C(947027968), // IBAR
698 UINT64_C(105414656), // IDLE
699 UINT64_C(105480192), // INVTLB
700 UINT64_C(105381888), // IOCSRRD_B
701 UINT64_C(105384960), // IOCSRRD_D
702 UINT64_C(105382912), // IOCSRRD_H
703 UINT64_C(105383936), // IOCSRRD_W
704 UINT64_C(105385984), // IOCSRWR_B
705 UINT64_C(105389056), // IOCSRWR_D
706 UINT64_C(105387008), // IOCSRWR_H
707 UINT64_C(105388032), // IOCSRWR_W
708 UINT64_C(1275068416), // JIRL
709 UINT64_C(1207960064), // JISCR0
710 UINT64_C(1207960320), // JISCR1
711 UINT64_C(104857600), // LDDIR
712 UINT64_C(947388416), // LDGT_B
713 UINT64_C(947486720), // LDGT_D
714 UINT64_C(947421184), // LDGT_H
715 UINT64_C(947453952), // LDGT_W
716 UINT64_C(947519488), // LDLE_B
717 UINT64_C(947617792), // LDLE_D
718 UINT64_C(947552256), // LDLE_H
719 UINT64_C(947585024), // LDLE_W
720 UINT64_C(780140544), // LDL_D
721 UINT64_C(771751936), // LDL_W
722 UINT64_C(105119744), // LDPTE
723 UINT64_C(637534208), // LDPTR_D
724 UINT64_C(603979776), // LDPTR_W
725 UINT64_C(784334848), // LDR_D
726 UINT64_C(775946240), // LDR_W
727 UINT64_C(939524096), // LDX_B
728 UINT64_C(941621248), // LDX_BU
729 UINT64_C(940310528), // LDX_D
730 UINT64_C(939786240), // LDX_H
731 UINT64_C(941883392), // LDX_HU
732 UINT64_C(940048384), // LDX_W
733 UINT64_C(942145536), // LDX_WU
734 UINT64_C(671088640), // LD_B
735 UINT64_C(704643072), // LD_BU
736 UINT64_C(683671552), // LD_D
737 UINT64_C(675282944), // LD_H
738 UINT64_C(708837376), // LD_HU
739 UINT64_C(679477248), // LD_W
740 UINT64_C(713031680), // LD_WU
741 UINT64_C(945260544), // LLACQ_D
742 UINT64_C(945258496), // LLACQ_W
743 UINT64_C(570425344), // LL_D
744 UINT64_C(536870912), // LL_W
745 UINT64_C(335544320), // LU12I_W
746 UINT64_C(369098752), // LU32I_D
747 UINT64_C(50331648), // LU52I_D
748 UINT64_C(1245184), // MASKEQZ
749 UINT64_C(1277952), // MASKNEZ
750 UINT64_C(2260992), // MOD_D
751 UINT64_C(2326528), // MOD_DU
752 UINT64_C(2129920), // MOD_W
753 UINT64_C(2195456), // MOD_WU
754 UINT64_C(18142208), // MOVCF2FR_xS
755 UINT64_C(18144256), // MOVCF2GR
756 UINT64_C(18139136), // MOVFCSR2GR
757 UINT64_C(18141184), // MOVFR2CF_xS
758 UINT64_C(18135040), // MOVFR2GR_D
759 UINT64_C(18134016), // MOVFR2GR_S
760 UINT64_C(18134016), // MOVFR2GR_S_64
761 UINT64_C(18136064), // MOVFRH2GR_S
762 UINT64_C(18143232), // MOVGR2CF
763 UINT64_C(18137088), // MOVGR2FCSR
764 UINT64_C(18131968), // MOVGR2FRH_W
765 UINT64_C(18130944), // MOVGR2FR_D
766 UINT64_C(18129920), // MOVGR2FR_W
767 UINT64_C(18129920), // MOVGR2FR_W_64
768 UINT64_C(2048), // MOVGR2SCR
769 UINT64_C(3072), // MOVSCR2GR
770 UINT64_C(1966080), // MULH_D
771 UINT64_C(1998848), // MULH_DU
772 UINT64_C(1867776), // MULH_W
773 UINT64_C(1900544), // MULH_WU
774 UINT64_C(2031616), // MULW_D_W
775 UINT64_C(2064384), // MULW_D_WU
776 UINT64_C(1933312), // MUL_D
777 UINT64_C(1835008), // MUL_W
778 UINT64_C(1310720), // NOR
779 UINT64_C(1376256), // OR
780 UINT64_C(58720256), // ORI
781 UINT64_C(1441792), // ORN
782 UINT64_C(402653184), // PCADDI
783 UINT64_C(469762048), // PCADDU12I
784 UINT64_C(503316480), // PCADDU18I
785 UINT64_C(436207616), // PCALAU12I
786 UINT64_C(717225984), // PRELD
787 UINT64_C(942407680), // PRELDX
788 UINT64_C(5251072), // RCRI_B
789 UINT64_C(5308416), // RCRI_D
790 UINT64_C(5259264), // RCRI_H
791 UINT64_C(5275648), // RCRI_W
792 UINT64_C(3407872), // RCR_B
793 UINT64_C(3506176), // RCR_D
794 UINT64_C(3440640), // RCR_H
795 UINT64_C(3473408), // RCR_W
796 UINT64_C(25600), // RDTIMEH_W
797 UINT64_C(24576), // RDTIMEL_W
798 UINT64_C(26624), // RDTIME_D
799 UINT64_C(12288), // REVB_2H
800 UINT64_C(14336), // REVB_2W
801 UINT64_C(13312), // REVB_4H
802 UINT64_C(15360), // REVB_D
803 UINT64_C(16384), // REVH_2W
804 UINT64_C(17408), // REVH_D
805 UINT64_C(4988928), // ROTRI_B
806 UINT64_C(5046272), // ROTRI_D
807 UINT64_C(4997120), // ROTRI_H
808 UINT64_C(5013504), // ROTRI_W
809 UINT64_C(1703936), // ROTR_B
810 UINT64_C(1802240), // ROTR_D
811 UINT64_C(1736704), // ROTR_H
812 UINT64_C(1769472), // ROTR_W
813 UINT64_C(3276800), // SBC_B
814 UINT64_C(3375104), // SBC_D
815 UINT64_C(3309568), // SBC_H
816 UINT64_C(3342336), // SBC_W
817 UINT64_C(945261568), // SCREL_D
818 UINT64_C(945259520), // SCREL_W
819 UINT64_C(587202560), // SC_D
820 UINT64_C(945225728), // SC_Q
821 UINT64_C(553648128), // SC_W
822 UINT64_C(3588096), // SETARMJ
823 UINT64_C(3571712), // SETX86J
824 UINT64_C(30720), // SETX86LOOPE
825 UINT64_C(31744), // SETX86LOOPNE
826 UINT64_C(202375168), // SET_CFR_FALSE
827 UINT64_C(202768384), // SET_CFR_TRUE
828 UINT64_C(4259840), // SLLI_D
829 UINT64_C(4227072), // SLLI_W
830 UINT64_C(1605632), // SLL_D
831 UINT64_C(1507328), // SLL_W
832 UINT64_C(1179648), // SLT
833 UINT64_C(33554432), // SLTI
834 UINT64_C(1212416), // SLTU
835 UINT64_C(37748736), // SLTUI
836 UINT64_C(4784128), // SRAI_D
837 UINT64_C(4751360), // SRAI_W
838 UINT64_C(1671168), // SRA_D
839 UINT64_C(1572864), // SRA_W
840 UINT64_C(4521984), // SRLI_D
841 UINT64_C(4489216), // SRLI_W
842 UINT64_C(1638400), // SRL_D
843 UINT64_C(1540096), // SRL_W
844 UINT64_C(947650560), // STGT_B
845 UINT64_C(947748864), // STGT_D
846 UINT64_C(947683328), // STGT_H
847 UINT64_C(947716096), // STGT_W
848 UINT64_C(947781632), // STLE_B
849 UINT64_C(947879936), // STLE_D
850 UINT64_C(947814400), // STLE_H
851 UINT64_C(947847168), // STLE_W
852 UINT64_C(796917760), // STL_D
853 UINT64_C(788529152), // STL_W
854 UINT64_C(654311424), // STPTR_D
855 UINT64_C(620756992), // STPTR_W
856 UINT64_C(801112064), // STR_D
857 UINT64_C(792723456), // STR_W
858 UINT64_C(940572672), // STX_B
859 UINT64_C(941359104), // STX_D
860 UINT64_C(940834816), // STX_H
861 UINT64_C(941096960), // STX_W
862 UINT64_C(687865856), // ST_B
863 UINT64_C(700448768), // ST_D
864 UINT64_C(692060160), // ST_H
865 UINT64_C(696254464), // ST_W
866 UINT64_C(1146880), // SUB_D
867 UINT64_C(1114112), // SUB_W
868 UINT64_C(2818048), // SYSCALL
869 UINT64_C(105390080), // TLBCLR
870 UINT64_C(105395200), // TLBFILL
871 UINT64_C(105391104), // TLBFLUSH
872 UINT64_C(105393152), // TLBRD
873 UINT64_C(105392128), // TLBSRCH
874 UINT64_C(105394176), // TLBWR
875 UINT64_C(1885339648), // VABSD_B
876 UINT64_C(1885470720), // VABSD_BU
877 UINT64_C(1885437952), // VABSD_D
878 UINT64_C(1885569024), // VABSD_DU
879 UINT64_C(1885372416), // VABSD_H
880 UINT64_C(1885503488), // VABSD_HU
881 UINT64_C(1885405184), // VABSD_W
882 UINT64_C(1885536256), // VABSD_WU
883 UINT64_C(1885077504), // VADDA_B
884 UINT64_C(1885175808), // VADDA_D
885 UINT64_C(1885110272), // VADDA_H
886 UINT64_C(1885143040), // VADDA_W
887 UINT64_C(1921646592), // VADDI_BU
888 UINT64_C(1921744896), // VADDI_DU
889 UINT64_C(1921679360), // VADDI_HU
890 UINT64_C(1921712128), // VADDI_WU
891 UINT64_C(1881079808), // VADDWEV_D_W
892 UINT64_C(1882128384), // VADDWEV_D_WU
893 UINT64_C(1883176960), // VADDWEV_D_WU_W
894 UINT64_C(1881014272), // VADDWEV_H_B
895 UINT64_C(1882062848), // VADDWEV_H_BU
896 UINT64_C(1883111424), // VADDWEV_H_BU_B
897 UINT64_C(1881112576), // VADDWEV_Q_D
898 UINT64_C(1882161152), // VADDWEV_Q_DU
899 UINT64_C(1883209728), // VADDWEV_Q_DU_D
900 UINT64_C(1881047040), // VADDWEV_W_H
901 UINT64_C(1882095616), // VADDWEV_W_HU
902 UINT64_C(1883144192), // VADDWEV_W_HU_H
903 UINT64_C(1881341952), // VADDWOD_D_W
904 UINT64_C(1882390528), // VADDWOD_D_WU
905 UINT64_C(1883308032), // VADDWOD_D_WU_W
906 UINT64_C(1881276416), // VADDWOD_H_B
907 UINT64_C(1882324992), // VADDWOD_H_BU
908 UINT64_C(1883242496), // VADDWOD_H_BU_B
909 UINT64_C(1881374720), // VADDWOD_Q_D
910 UINT64_C(1882423296), // VADDWOD_Q_DU
911 UINT64_C(1883340800), // VADDWOD_Q_DU_D
912 UINT64_C(1881309184), // VADDWOD_W_H
913 UINT64_C(1882357760), // VADDWOD_W_HU
914 UINT64_C(1883275264), // VADDWOD_W_HU_H
915 UINT64_C(1879703552), // VADD_B
916 UINT64_C(1879801856), // VADD_D
917 UINT64_C(1879736320), // VADD_H
918 UINT64_C(1898774528), // VADD_Q
919 UINT64_C(1879769088), // VADD_W
920 UINT64_C(1943011328), // VANDI_B
921 UINT64_C(1898446848), // VANDN_V
922 UINT64_C(1898315776), // VAND_V
923 UINT64_C(1885863936), // VAVGR_B
924 UINT64_C(1885995008), // VAVGR_BU
925 UINT64_C(1885962240), // VAVGR_D
926 UINT64_C(1886093312), // VAVGR_DU
927 UINT64_C(1885896704), // VAVGR_H
928 UINT64_C(1886027776), // VAVGR_HU
929 UINT64_C(1885929472), // VAVGR_W
930 UINT64_C(1886060544), // VAVGR_WU
931 UINT64_C(1885601792), // VAVG_B
932 UINT64_C(1885732864), // VAVG_BU
933 UINT64_C(1885700096), // VAVG_D
934 UINT64_C(1885831168), // VAVG_DU
935 UINT64_C(1885634560), // VAVG_H
936 UINT64_C(1885765632), // VAVG_HU
937 UINT64_C(1885667328), // VAVG_W
938 UINT64_C(1885798400), // VAVG_WU
939 UINT64_C(1930436608), // VBITCLRI_B
940 UINT64_C(1930493952), // VBITCLRI_D
941 UINT64_C(1930444800), // VBITCLRI_H
942 UINT64_C(1930461184), // VBITCLRI_W
943 UINT64_C(1896611840), // VBITCLR_B
944 UINT64_C(1896710144), // VBITCLR_D
945 UINT64_C(1896644608), // VBITCLR_H
946 UINT64_C(1896677376), // VBITCLR_W
947 UINT64_C(1930960896), // VBITREVI_B
948 UINT64_C(1931018240), // VBITREVI_D
949 UINT64_C(1930969088), // VBITREVI_H
950 UINT64_C(1930985472), // VBITREVI_W
951 UINT64_C(1896873984), // VBITREV_B
952 UINT64_C(1896972288), // VBITREV_D
953 UINT64_C(1896906752), // VBITREV_H
954 UINT64_C(1896939520), // VBITREV_W
955 UINT64_C(1942224896), // VBITSELI_B
956 UINT64_C(219152384), // VBITSEL_V
957 UINT64_C(1930698752), // VBITSETI_B
958 UINT64_C(1930756096), // VBITSETI_D
959 UINT64_C(1930706944), // VBITSETI_H
960 UINT64_C(1930723328), // VBITSETI_W
961 UINT64_C(1896742912), // VBITSET_B
962 UINT64_C(1896841216), // VBITSET_D
963 UINT64_C(1896775680), // VBITSET_H
964 UINT64_C(1896808448), // VBITSET_W
965 UINT64_C(1921908736), // VBSLL_V
966 UINT64_C(1921941504), // VBSRL_V
967 UINT64_C(1922826240), // VCLO_B
968 UINT64_C(1922829312), // VCLO_D
969 UINT64_C(1922827264), // VCLO_H
970 UINT64_C(1922828288), // VCLO_W
971 UINT64_C(1922830336), // VCLZ_B
972 UINT64_C(1922833408), // VCLZ_D
973 UINT64_C(1922831360), // VCLZ_H
974 UINT64_C(1922832384), // VCLZ_W
975 UINT64_C(1893728256), // VDIV_B
976 UINT64_C(1893990400), // VDIV_BU
977 UINT64_C(1893826560), // VDIV_D
978 UINT64_C(1894088704), // VDIV_DU
979 UINT64_C(1893761024), // VDIV_H
980 UINT64_C(1894023168), // VDIV_HU
981 UINT64_C(1893793792), // VDIV_W
982 UINT64_C(1894055936), // VDIV_WU
983 UINT64_C(1990144000), // VEXT2XV_DU_BU
984 UINT64_C(1990146048), // VEXT2XV_DU_HU
985 UINT64_C(1990147072), // VEXT2XV_DU_WU
986 UINT64_C(1990137856), // VEXT2XV_D_B
987 UINT64_C(1990139904), // VEXT2XV_D_H
988 UINT64_C(1990140928), // VEXT2XV_D_W
989 UINT64_C(1990141952), // VEXT2XV_HU_BU
990 UINT64_C(1990135808), // VEXT2XV_H_B
991 UINT64_C(1990142976), // VEXT2XV_WU_BU
992 UINT64_C(1990145024), // VEXT2XV_WU_HU
993 UINT64_C(1990136832), // VEXT2XV_W_B
994 UINT64_C(1990138880), // VEXT2XV_W_H
995 UINT64_C(1923020800), // VEXTH_DU_WU
996 UINT64_C(1923016704), // VEXTH_D_W
997 UINT64_C(1923018752), // VEXTH_HU_BU
998 UINT64_C(1923014656), // VEXTH_H_B
999 UINT64_C(1923021824), // VEXTH_QU_DU
1000 UINT64_C(1923017728), // VEXTH_Q_D
1001 UINT64_C(1923019776), // VEXTH_WU_HU
1002 UINT64_C(1923015680), // VEXTH_W_H
1003 UINT64_C(1930231808), // VEXTL_QU_DU
1004 UINT64_C(1929969664), // VEXTL_Q_D
1005 UINT64_C(1938554880), // VEXTRINS_B
1006 UINT64_C(1937768448), // VEXTRINS_D
1007 UINT64_C(1938292736), // VEXTRINS_H
1008 UINT64_C(1938030592), // VEXTRINS_W
1009 UINT64_C(1899036672), // VFADD_D
1010 UINT64_C(1899003904), // VFADD_S
1011 UINT64_C(1922881536), // VFCLASS_D
1012 UINT64_C(1922880512), // VFCLASS_S
1013 UINT64_C(207618048), // VFCMP_CAF_D
1014 UINT64_C(206569472), // VFCMP_CAF_S
1015 UINT64_C(207749120), // VFCMP_CEQ_D
1016 UINT64_C(206700544), // VFCMP_CEQ_S
1017 UINT64_C(207814656), // VFCMP_CLE_D
1018 UINT64_C(206766080), // VFCMP_CLE_S
1019 UINT64_C(207683584), // VFCMP_CLT_D
1020 UINT64_C(206635008), // VFCMP_CLT_S
1021 UINT64_C(208142336), // VFCMP_CNE_D
1022 UINT64_C(207093760), // VFCMP_CNE_S
1023 UINT64_C(208273408), // VFCMP_COR_D
1024 UINT64_C(207224832), // VFCMP_COR_S
1025 UINT64_C(208011264), // VFCMP_CUEQ_D
1026 UINT64_C(206962688), // VFCMP_CUEQ_S
1027 UINT64_C(208076800), // VFCMP_CULE_D
1028 UINT64_C(207028224), // VFCMP_CULE_S
1029 UINT64_C(207945728), // VFCMP_CULT_D
1030 UINT64_C(206897152), // VFCMP_CULT_S
1031 UINT64_C(208404480), // VFCMP_CUNE_D
1032 UINT64_C(207355904), // VFCMP_CUNE_S
1033 UINT64_C(207880192), // VFCMP_CUN_D
1034 UINT64_C(206831616), // VFCMP_CUN_S
1035 UINT64_C(207650816), // VFCMP_SAF_D
1036 UINT64_C(206602240), // VFCMP_SAF_S
1037 UINT64_C(207781888), // VFCMP_SEQ_D
1038 UINT64_C(206733312), // VFCMP_SEQ_S
1039 UINT64_C(207847424), // VFCMP_SLE_D
1040 UINT64_C(206798848), // VFCMP_SLE_S
1041 UINT64_C(207716352), // VFCMP_SLT_D
1042 UINT64_C(206667776), // VFCMP_SLT_S
1043 UINT64_C(208175104), // VFCMP_SNE_D
1044 UINT64_C(207126528), // VFCMP_SNE_S
1045 UINT64_C(208306176), // VFCMP_SOR_D
1046 UINT64_C(207257600), // VFCMP_SOR_S
1047 UINT64_C(208044032), // VFCMP_SUEQ_D
1048 UINT64_C(206995456), // VFCMP_SUEQ_S
1049 UINT64_C(208109568), // VFCMP_SULE_D
1050 UINT64_C(207060992), // VFCMP_SULE_S
1051 UINT64_C(207978496), // VFCMP_SULT_D
1052 UINT64_C(206929920), // VFCMP_SULT_S
1053 UINT64_C(208437248), // VFCMP_SUNE_D
1054 UINT64_C(207388672), // VFCMP_SUNE_S
1055 UINT64_C(207912960), // VFCMP_SUN_D
1056 UINT64_C(206864384), // VFCMP_SUN_S
1057 UINT64_C(1922954240), // VFCVTH_D_S
1058 UINT64_C(1922952192), // VFCVTH_S_H
1059 UINT64_C(1922953216), // VFCVTL_D_S
1060 UINT64_C(1922951168), // VFCVTL_S_H
1061 UINT64_C(1900412928), // VFCVT_H_S
1062 UINT64_C(1900445696), // VFCVT_S_D
1063 UINT64_C(1899692032), // VFDIV_D
1064 UINT64_C(1899659264), // VFDIV_S
1065 UINT64_C(1922962432), // VFFINTH_D_W
1066 UINT64_C(1922961408), // VFFINTL_D_W
1067 UINT64_C(1922959360), // VFFINT_D_L
1068 UINT64_C(1922960384), // VFFINT_D_LU
1069 UINT64_C(1900544000), // VFFINT_S_L
1070 UINT64_C(1922957312), // VFFINT_S_W
1071 UINT64_C(1922958336), // VFFINT_S_WU
1072 UINT64_C(1922877440), // VFLOGB_D
1073 UINT64_C(1922876416), // VFLOGB_S
1074 UINT64_C(153092096), // VFMADD_D
1075 UINT64_C(152043520), // VFMADD_S
1076 UINT64_C(1900085248), // VFMAXA_D
1077 UINT64_C(1900052480), // VFMAXA_S
1078 UINT64_C(1899823104), // VFMAX_D
1079 UINT64_C(1899790336), // VFMAX_S
1080 UINT64_C(1900216320), // VFMINA_D
1081 UINT64_C(1900183552), // VFMINA_S
1082 UINT64_C(1899954176), // VFMIN_D
1083 UINT64_C(1899921408), // VFMIN_S
1084 UINT64_C(157286400), // VFMSUB_D
1085 UINT64_C(156237824), // VFMSUB_S
1086 UINT64_C(1899560960), // VFMUL_D
1087 UINT64_C(1899528192), // VFMUL_S
1088 UINT64_C(161480704), // VFNMADD_D
1089 UINT64_C(160432128), // VFNMADD_S
1090 UINT64_C(165675008), // VFNMSUB_D
1091 UINT64_C(164626432), // VFNMSUB_S
1092 UINT64_C(1922897920), // VFRECIPE_D
1093 UINT64_C(1922896896), // VFRECIPE_S
1094 UINT64_C(1922889728), // VFRECIP_D
1095 UINT64_C(1922888704), // VFRECIP_S
1096 UINT64_C(1922910208), // VFRINTRM_D
1097 UINT64_C(1922909184), // VFRINTRM_S
1098 UINT64_C(1922922496), // VFRINTRNE_D
1099 UINT64_C(1922921472), // VFRINTRNE_S
1100 UINT64_C(1922914304), // VFRINTRP_D
1101 UINT64_C(1922913280), // VFRINTRP_S
1102 UINT64_C(1922918400), // VFRINTRZ_D
1103 UINT64_C(1922917376), // VFRINTRZ_S
1104 UINT64_C(1922906112), // VFRINT_D
1105 UINT64_C(1922905088), // VFRINT_S
1106 UINT64_C(1922902016), // VFRSQRTE_D
1107 UINT64_C(1922900992), // VFRSQRTE_S
1108 UINT64_C(1922893824), // VFRSQRT_D
1109 UINT64_C(1922892800), // VFRSQRT_S
1110 UINT64_C(1922695168), // VFRSTPI_B
1111 UINT64_C(1922727936), // VFRSTPI_H
1112 UINT64_C(1898643456), // VFRSTP_B
1113 UINT64_C(1898676224), // VFRSTP_H
1114 UINT64_C(1922885632), // VFSQRT_D
1115 UINT64_C(1922884608), // VFSQRT_S
1116 UINT64_C(1899167744), // VFSUB_D
1117 UINT64_C(1899134976), // VFSUB_S
1118 UINT64_C(1922991104), // VFTINTH_L_S
1119 UINT64_C(1922990080), // VFTINTL_L_S
1120 UINT64_C(1922993152), // VFTINTRMH_L_S
1121 UINT64_C(1922992128), // VFTINTRML_L_S
1122 UINT64_C(1922972672), // VFTINTRM_L_D
1123 UINT64_C(1900675072), // VFTINTRM_W_D
1124 UINT64_C(1922971648), // VFTINTRM_W_S
1125 UINT64_C(1922999296), // VFTINTRNEH_L_S
1126 UINT64_C(1922998272), // VFTINTRNEL_L_S
1127 UINT64_C(1922978816), // VFTINTRNE_L_D
1128 UINT64_C(1900773376), // VFTINTRNE_W_D
1129 UINT64_C(1922977792), // VFTINTRNE_W_S
1130 UINT64_C(1922995200), // VFTINTRPH_L_S
1131 UINT64_C(1922994176), // VFTINTRPL_L_S
1132 UINT64_C(1922974720), // VFTINTRP_L_D
1133 UINT64_C(1900707840), // VFTINTRP_W_D
1134 UINT64_C(1922973696), // VFTINTRP_W_S
1135 UINT64_C(1922997248), // VFTINTRZH_L_S
1136 UINT64_C(1922996224), // VFTINTRZL_L_S
1137 UINT64_C(1922987008), // VFTINTRZ_LU_D
1138 UINT64_C(1922976768), // VFTINTRZ_L_D
1139 UINT64_C(1922985984), // VFTINTRZ_WU_S
1140 UINT64_C(1900740608), // VFTINTRZ_W_D
1141 UINT64_C(1922975744), // VFTINTRZ_W_S
1142 UINT64_C(1922980864), // VFTINT_LU_D
1143 UINT64_C(1922970624), // VFTINT_L_D
1144 UINT64_C(1922979840), // VFTINT_WU_S
1145 UINT64_C(1900642304), // VFTINT_W_D
1146 UINT64_C(1922969600), // VFTINT_W_S
1147 UINT64_C(1884880896), // VHADDW_DU_WU
1148 UINT64_C(1884618752), // VHADDW_D_W
1149 UINT64_C(1884815360), // VHADDW_HU_BU
1150 UINT64_C(1884553216), // VHADDW_H_B
1151 UINT64_C(1884913664), // VHADDW_QU_DU
1152 UINT64_C(1884651520), // VHADDW_Q_D
1153 UINT64_C(1884848128), // VHADDW_WU_HU
1154 UINT64_C(1884585984), // VHADDW_W_H
1155 UINT64_C(1885011968), // VHSUBW_DU_WU
1156 UINT64_C(1884749824), // VHSUBW_D_W
1157 UINT64_C(1884946432), // VHSUBW_HU_BU
1158 UINT64_C(1884684288), // VHSUBW_H_B
1159 UINT64_C(1885044736), // VHSUBW_QU_DU
1160 UINT64_C(1884782592), // VHSUBW_Q_D
1161 UINT64_C(1884979200), // VHSUBW_WU_HU
1162 UINT64_C(1884717056), // VHSUBW_W_H
1163 UINT64_C(1897660416), // VILVH_B
1164 UINT64_C(1897758720), // VILVH_D
1165 UINT64_C(1897693184), // VILVH_H
1166 UINT64_C(1897725952), // VILVH_W
1167 UINT64_C(1897529344), // VILVL_B
1168 UINT64_C(1897627648), // VILVL_D
1169 UINT64_C(1897562112), // VILVL_H
1170 UINT64_C(1897594880), // VILVL_W
1171 UINT64_C(1928036352), // VINSGR2VR_B
1172 UINT64_C(1928065024), // VINSGR2VR_D
1173 UINT64_C(1928052736), // VINSGR2VR_H
1174 UINT64_C(1928060928), // VINSGR2VR_W
1175 UINT64_C(738197504), // VLD
1176 UINT64_C(1944059904), // VLDI
1177 UINT64_C(813694976), // VLDREPL_B
1178 UINT64_C(806354944), // VLDREPL_D
1179 UINT64_C(809500672), // VLDREPL_H
1180 UINT64_C(807403520), // VLDREPL_W
1181 UINT64_C(943718400), // VLDX
1182 UINT64_C(1890385920), // VMADDWEV_D_W
1183 UINT64_C(1890910208), // VMADDWEV_D_WU
1184 UINT64_C(1891434496), // VMADDWEV_D_WU_W
1185 UINT64_C(1890320384), // VMADDWEV_H_B
1186 UINT64_C(1890844672), // VMADDWEV_H_BU
1187 UINT64_C(1891368960), // VMADDWEV_H_BU_B
1188 UINT64_C(1890418688), // VMADDWEV_Q_D
1189 UINT64_C(1890942976), // VMADDWEV_Q_DU
1190 UINT64_C(1891467264), // VMADDWEV_Q_DU_D
1191 UINT64_C(1890353152), // VMADDWEV_W_H
1192 UINT64_C(1890877440), // VMADDWEV_W_HU
1193 UINT64_C(1891401728), // VMADDWEV_W_HU_H
1194 UINT64_C(1890516992), // VMADDWOD_D_W
1195 UINT64_C(1891041280), // VMADDWOD_D_WU
1196 UINT64_C(1891565568), // VMADDWOD_D_WU_W
1197 UINT64_C(1890451456), // VMADDWOD_H_B
1198 UINT64_C(1890975744), // VMADDWOD_H_BU
1199 UINT64_C(1891500032), // VMADDWOD_H_BU_B
1200 UINT64_C(1890549760), // VMADDWOD_Q_D
1201 UINT64_C(1891074048), // VMADDWOD_Q_DU
1202 UINT64_C(1891598336), // VMADDWOD_Q_DU_D
1203 UINT64_C(1890484224), // VMADDWOD_W_H
1204 UINT64_C(1891008512), // VMADDWOD_W_HU
1205 UINT64_C(1891532800), // VMADDWOD_W_HU_H
1206 UINT64_C(1890058240), // VMADD_B
1207 UINT64_C(1890156544), // VMADD_D
1208 UINT64_C(1890091008), // VMADD_H
1209 UINT64_C(1890123776), // VMADD_W
1210 UINT64_C(1922039808), // VMAXI_B
1211 UINT64_C(1922301952), // VMAXI_BU
1212 UINT64_C(1922138112), // VMAXI_D
1213 UINT64_C(1922400256), // VMAXI_DU
1214 UINT64_C(1922072576), // VMAXI_H
1215 UINT64_C(1922334720), // VMAXI_HU
1216 UINT64_C(1922105344), // VMAXI_W
1217 UINT64_C(1922367488), // VMAXI_WU
1218 UINT64_C(1886388224), // VMAX_B
1219 UINT64_C(1886650368), // VMAX_BU
1220 UINT64_C(1886486528), // VMAX_D
1221 UINT64_C(1886748672), // VMAX_DU
1222 UINT64_C(1886420992), // VMAX_H
1223 UINT64_C(1886683136), // VMAX_HU
1224 UINT64_C(1886453760), // VMAX_W
1225 UINT64_C(1886715904), // VMAX_WU
1226 UINT64_C(1922170880), // VMINI_B
1227 UINT64_C(1922433024), // VMINI_BU
1228 UINT64_C(1922269184), // VMINI_D
1229 UINT64_C(1922531328), // VMINI_DU
1230 UINT64_C(1922203648), // VMINI_H
1231 UINT64_C(1922465792), // VMINI_HU
1232 UINT64_C(1922236416), // VMINI_W
1233 UINT64_C(1922498560), // VMINI_WU
1234 UINT64_C(1886519296), // VMIN_B
1235 UINT64_C(1886781440), // VMIN_BU
1236 UINT64_C(1886617600), // VMIN_D
1237 UINT64_C(1886879744), // VMIN_DU
1238 UINT64_C(1886552064), // VMIN_H
1239 UINT64_C(1886814208), // VMIN_HU
1240 UINT64_C(1886584832), // VMIN_W
1241 UINT64_C(1886846976), // VMIN_WU
1242 UINT64_C(1893859328), // VMOD_B
1243 UINT64_C(1894121472), // VMOD_BU
1244 UINT64_C(1893957632), // VMOD_D
1245 UINT64_C(1894219776), // VMOD_DU
1246 UINT64_C(1893892096), // VMOD_H
1247 UINT64_C(1894154240), // VMOD_HU
1248 UINT64_C(1893924864), // VMOD_W
1249 UINT64_C(1894187008), // VMOD_WU
1250 UINT64_C(1922846720), // VMSKGEZ_B
1251 UINT64_C(1922842624), // VMSKLTZ_B
1252 UINT64_C(1922845696), // VMSKLTZ_D
1253 UINT64_C(1922843648), // VMSKLTZ_H
1254 UINT64_C(1922844672), // VMSKLTZ_W
1255 UINT64_C(1922850816), // VMSKNZ_B
1256 UINT64_C(1890189312), // VMSUB_B
1257 UINT64_C(1890287616), // VMSUB_D
1258 UINT64_C(1890222080), // VMSUB_H
1259 UINT64_C(1890254848), // VMSUB_W
1260 UINT64_C(1887830016), // VMUH_B
1261 UINT64_C(1887961088), // VMUH_BU
1262 UINT64_C(1887928320), // VMUH_D
1263 UINT64_C(1888059392), // VMUH_DU
1264 UINT64_C(1887862784), // VMUH_H
1265 UINT64_C(1887993856), // VMUH_HU
1266 UINT64_C(1887895552), // VMUH_W
1267 UINT64_C(1888026624), // VMUH_WU
1268 UINT64_C(1888550912), // VMULWEV_D_W
1269 UINT64_C(1889075200), // VMULWEV_D_WU
1270 UINT64_C(1889599488), // VMULWEV_D_WU_W
1271 UINT64_C(1888485376), // VMULWEV_H_B
1272 UINT64_C(1889009664), // VMULWEV_H_BU
1273 UINT64_C(1889533952), // VMULWEV_H_BU_B
1274 UINT64_C(1888583680), // VMULWEV_Q_D
1275 UINT64_C(1889107968), // VMULWEV_Q_DU
1276 UINT64_C(1889632256), // VMULWEV_Q_DU_D
1277 UINT64_C(1888518144), // VMULWEV_W_H
1278 UINT64_C(1889042432), // VMULWEV_W_HU
1279 UINT64_C(1889566720), // VMULWEV_W_HU_H
1280 UINT64_C(1888681984), // VMULWOD_D_W
1281 UINT64_C(1889206272), // VMULWOD_D_WU
1282 UINT64_C(1889730560), // VMULWOD_D_WU_W
1283 UINT64_C(1888616448), // VMULWOD_H_B
1284 UINT64_C(1889140736), // VMULWOD_H_BU
1285 UINT64_C(1889665024), // VMULWOD_H_BU_B
1286 UINT64_C(1888714752), // VMULWOD_Q_D
1287 UINT64_C(1889239040), // VMULWOD_Q_DU
1288 UINT64_C(1889763328), // VMULWOD_Q_DU_D
1289 UINT64_C(1888649216), // VMULWOD_W_H
1290 UINT64_C(1889173504), // VMULWOD_W_HU
1291 UINT64_C(1889697792), // VMULWOD_W_HU_H
1292 UINT64_C(1887698944), // VMUL_B
1293 UINT64_C(1887797248), // VMUL_D
1294 UINT64_C(1887731712), // VMUL_H
1295 UINT64_C(1887764480), // VMUL_W
1296 UINT64_C(1922838528), // VNEG_B
1297 UINT64_C(1922841600), // VNEG_D
1298 UINT64_C(1922839552), // VNEG_H
1299 UINT64_C(1922840576), // VNEG_W
1300 UINT64_C(1943797760), // VNORI_B
1301 UINT64_C(1898414080), // VNOR_V
1302 UINT64_C(1943273472), // VORI_B
1303 UINT64_C(1898479616), // VORN_V
1304 UINT64_C(1898348544), // VOR_V
1305 UINT64_C(1897267200), // VPACKEV_B
1306 UINT64_C(1897365504), // VPACKEV_D
1307 UINT64_C(1897299968), // VPACKEV_H
1308 UINT64_C(1897332736), // VPACKEV_W
1309 UINT64_C(1897398272), // VPACKOD_B
1310 UINT64_C(1897496576), // VPACKOD_D
1311 UINT64_C(1897431040), // VPACKOD_H
1312 UINT64_C(1897463808), // VPACKOD_W
1313 UINT64_C(1922834432), // VPCNT_B
1314 UINT64_C(1922837504), // VPCNT_D
1315 UINT64_C(1922835456), // VPCNT_H
1316 UINT64_C(1922836480), // VPCNT_W
1317 UINT64_C(1944322048), // VPERMI_W
1318 UINT64_C(1897791488), // VPICKEV_B
1319 UINT64_C(1897889792), // VPICKEV_D
1320 UINT64_C(1897824256), // VPICKEV_H
1321 UINT64_C(1897857024), // VPICKEV_W
1322 UINT64_C(1897922560), // VPICKOD_B
1323 UINT64_C(1898020864), // VPICKOD_D
1324 UINT64_C(1897955328), // VPICKOD_H
1325 UINT64_C(1897988096), // VPICKOD_W
1326 UINT64_C(1928298496), // VPICKVE2GR_B
1327 UINT64_C(1928560640), // VPICKVE2GR_BU
1328 UINT64_C(1928327168), // VPICKVE2GR_D
1329 UINT64_C(1928589312), // VPICKVE2GR_DU
1330 UINT64_C(1928314880), // VPICKVE2GR_H
1331 UINT64_C(1928577024), // VPICKVE2GR_HU
1332 UINT64_C(1928323072), // VPICKVE2GR_W
1333 UINT64_C(1928585216), // VPICKVE2GR_WU
1334 UINT64_C(1923022848), // VREPLGR2VR_B
1335 UINT64_C(1923025920), // VREPLGR2VR_D
1336 UINT64_C(1923023872), // VREPLGR2VR_H
1337 UINT64_C(1923024896), // VREPLGR2VR_W
1338 UINT64_C(1928822784), // VREPLVEI_B
1339 UINT64_C(1928851456), // VREPLVEI_D
1340 UINT64_C(1928839168), // VREPLVEI_H
1341 UINT64_C(1928847360), // VREPLVEI_W
1342 UINT64_C(1898053632), // VREPLVE_B
1343 UINT64_C(1898151936), // VREPLVE_D
1344 UINT64_C(1898086400), // VREPLVE_H
1345 UINT64_C(1898119168), // VREPLVE_W
1346 UINT64_C(1923096576), // VROTRI_B
1347 UINT64_C(1923153920), // VROTRI_D
1348 UINT64_C(1923104768), // VROTRI_H
1349 UINT64_C(1923121152), // VROTRI_W
1350 UINT64_C(1894645760), // VROTR_B
1351 UINT64_C(1894744064), // VROTR_D
1352 UINT64_C(1894678528), // VROTR_H
1353 UINT64_C(1894711296), // VROTR_W
1354 UINT64_C(1883635712), // VSADD_B
1355 UINT64_C(1883897856), // VSADD_BU
1356 UINT64_C(1883734016), // VSADD_D
1357 UINT64_C(1883996160), // VSADD_DU
1358 UINT64_C(1883668480), // VSADD_H
1359 UINT64_C(1883930624), // VSADD_HU
1360 UINT64_C(1883701248), // VSADD_W
1361 UINT64_C(1883963392), // VSADD_WU
1362 UINT64_C(1931747328), // VSAT_B
1363 UINT64_C(1932009472), // VSAT_BU
1364 UINT64_C(1931804672), // VSAT_D
1365 UINT64_C(1932066816), // VSAT_DU
1366 UINT64_C(1931755520), // VSAT_H
1367 UINT64_C(1932017664), // VSAT_HU
1368 UINT64_C(1931771904), // VSAT_W
1369 UINT64_C(1932034048), // VSAT_WU
1370 UINT64_C(1920991232), // VSEQI_B
1371 UINT64_C(1921089536), // VSEQI_D
1372 UINT64_C(1921024000), // VSEQI_H
1373 UINT64_C(1921056768), // VSEQI_W
1374 UINT64_C(1879048192), // VSEQ_B
1375 UINT64_C(1879146496), // VSEQ_D
1376 UINT64_C(1879080960), // VSEQ_H
1377 UINT64_C(1879113728), // VSEQ_W
1378 UINT64_C(1922871296), // VSETALLNEZ_B
1379 UINT64_C(1922874368), // VSETALLNEZ_D
1380 UINT64_C(1922872320), // VSETALLNEZ_H
1381 UINT64_C(1922873344), // VSETALLNEZ_W
1382 UINT64_C(1922867200), // VSETANYEQZ_B
1383 UINT64_C(1922870272), // VSETANYEQZ_D
1384 UINT64_C(1922868224), // VSETANYEQZ_H
1385 UINT64_C(1922869248), // VSETANYEQZ_W
1386 UINT64_C(1922865152), // VSETEQZ_V
1387 UINT64_C(1922866176), // VSETNEZ_V
1388 UINT64_C(1938817024), // VSHUF4I_B
1389 UINT64_C(1939603456), // VSHUF4I_D
1390 UINT64_C(1939079168), // VSHUF4I_H
1391 UINT64_C(1939341312), // VSHUF4I_W
1392 UINT64_C(223346688), // VSHUF_B
1393 UINT64_C(1903919104), // VSHUF_D
1394 UINT64_C(1903853568), // VSHUF_H
1395 UINT64_C(1903886336), // VSHUF_W
1396 UINT64_C(1898840064), // VSIGNCOV_B
1397 UINT64_C(1898938368), // VSIGNCOV_D
1398 UINT64_C(1898872832), // VSIGNCOV_H
1399 UINT64_C(1898905600), // VSIGNCOV_W
1400 UINT64_C(1921122304), // VSLEI_B
1401 UINT64_C(1921253376), // VSLEI_BU
1402 UINT64_C(1921220608), // VSLEI_D
1403 UINT64_C(1921351680), // VSLEI_DU
1404 UINT64_C(1921155072), // VSLEI_H
1405 UINT64_C(1921286144), // VSLEI_HU
1406 UINT64_C(1921187840), // VSLEI_W
1407 UINT64_C(1921318912), // VSLEI_WU
1408 UINT64_C(1879179264), // VSLE_B
1409 UINT64_C(1879310336), // VSLE_BU
1410 UINT64_C(1879277568), // VSLE_D
1411 UINT64_C(1879408640), // VSLE_DU
1412 UINT64_C(1879212032), // VSLE_H
1413 UINT64_C(1879343104), // VSLE_HU
1414 UINT64_C(1879244800), // VSLE_W
1415 UINT64_C(1879375872), // VSLE_WU
1416 UINT64_C(1932271616), // VSLLI_B
1417 UINT64_C(1932328960), // VSLLI_D
1418 UINT64_C(1932279808), // VSLLI_H
1419 UINT64_C(1932296192), // VSLLI_W
1420 UINT64_C(1930199040), // VSLLWIL_DU_WU
1421 UINT64_C(1929936896), // VSLLWIL_D_W
1422 UINT64_C(1930174464), // VSLLWIL_HU_BU
1423 UINT64_C(1929912320), // VSLLWIL_H_B
1424 UINT64_C(1930182656), // VSLLWIL_WU_HU
1425 UINT64_C(1929920512), // VSLLWIL_W_H
1426 UINT64_C(1894252544), // VSLL_B
1427 UINT64_C(1894350848), // VSLL_D
1428 UINT64_C(1894285312), // VSLL_H
1429 UINT64_C(1894318080), // VSLL_W
1430 UINT64_C(1921384448), // VSLTI_B
1431 UINT64_C(1921515520), // VSLTI_BU
1432 UINT64_C(1921482752), // VSLTI_D
1433 UINT64_C(1921613824), // VSLTI_DU
1434 UINT64_C(1921417216), // VSLTI_H
1435 UINT64_C(1921548288), // VSLTI_HU
1436 UINT64_C(1921449984), // VSLTI_W
1437 UINT64_C(1921581056), // VSLTI_WU
1438 UINT64_C(1879441408), // VSLT_B
1439 UINT64_C(1879572480), // VSLT_BU
1440 UINT64_C(1879539712), // VSLT_D
1441 UINT64_C(1879670784), // VSLT_DU
1442 UINT64_C(1879474176), // VSLT_H
1443 UINT64_C(1879605248), // VSLT_HU
1444 UINT64_C(1879506944), // VSLT_W
1445 UINT64_C(1879638016), // VSLT_WU
1446 UINT64_C(1932795904), // VSRAI_B
1447 UINT64_C(1932853248), // VSRAI_D
1448 UINT64_C(1932804096), // VSRAI_H
1449 UINT64_C(1932820480), // VSRAI_W
1450 UINT64_C(1935163392), // VSRANI_B_H
1451 UINT64_C(1935278080), // VSRANI_D_Q
1452 UINT64_C(1935179776), // VSRANI_H_W
1453 UINT64_C(1935212544), // VSRANI_W_D
1454 UINT64_C(1895202816), // VSRAN_B_H
1455 UINT64_C(1895235584), // VSRAN_H_W
1456 UINT64_C(1895268352), // VSRAN_W_D
1457 UINT64_C(1923620864), // VSRARI_B
1458 UINT64_C(1923678208), // VSRARI_D
1459 UINT64_C(1923629056), // VSRARI_H
1460 UINT64_C(1923645440), // VSRARI_W
1461 UINT64_C(1935425536), // VSRARNI_B_H
1462 UINT64_C(1935540224), // VSRARNI_D_Q
1463 UINT64_C(1935441920), // VSRARNI_H_W
1464 UINT64_C(1935474688), // VSRARNI_W_D
1465 UINT64_C(1895464960), // VSRARN_B_H
1466 UINT64_C(1895497728), // VSRARN_H_W
1467 UINT64_C(1895530496), // VSRARN_W_D
1468 UINT64_C(1894907904), // VSRAR_B
1469 UINT64_C(1895006208), // VSRAR_D
1470 UINT64_C(1894940672), // VSRAR_H
1471 UINT64_C(1894973440), // VSRAR_W
1472 UINT64_C(1894514688), // VSRA_B
1473 UINT64_C(1894612992), // VSRA_D
1474 UINT64_C(1894547456), // VSRA_H
1475 UINT64_C(1894580224), // VSRA_W
1476 UINT64_C(1932533760), // VSRLI_B
1477 UINT64_C(1932591104), // VSRLI_D
1478 UINT64_C(1932541952), // VSRLI_H
1479 UINT64_C(1932558336), // VSRLI_W
1480 UINT64_C(1933590528), // VSRLNI_B_H
1481 UINT64_C(1933705216), // VSRLNI_D_Q
1482 UINT64_C(1933606912), // VSRLNI_H_W
1483 UINT64_C(1933639680), // VSRLNI_W_D
1484 UINT64_C(1895071744), // VSRLN_B_H
1485 UINT64_C(1895104512), // VSRLN_H_W
1486 UINT64_C(1895137280), // VSRLN_W_D
1487 UINT64_C(1923358720), // VSRLRI_B
1488 UINT64_C(1923416064), // VSRLRI_D
1489 UINT64_C(1923366912), // VSRLRI_H
1490 UINT64_C(1923383296), // VSRLRI_W
1491 UINT64_C(1933852672), // VSRLRNI_B_H
1492 UINT64_C(1933967360), // VSRLRNI_D_Q
1493 UINT64_C(1933869056), // VSRLRNI_H_W
1494 UINT64_C(1933901824), // VSRLRNI_W_D
1495 UINT64_C(1895333888), // VSRLRN_B_H
1496 UINT64_C(1895366656), // VSRLRN_H_W
1497 UINT64_C(1895399424), // VSRLRN_W_D
1498 UINT64_C(1894776832), // VSRLR_B
1499 UINT64_C(1894875136), // VSRLR_D
1500 UINT64_C(1894809600), // VSRLR_H
1501 UINT64_C(1894842368), // VSRLR_W
1502 UINT64_C(1894383616), // VSRL_B
1503 UINT64_C(1894481920), // VSRL_D
1504 UINT64_C(1894416384), // VSRL_H
1505 UINT64_C(1894449152), // VSRL_W
1506 UINT64_C(1935949824), // VSSRANI_BU_H
1507 UINT64_C(1935687680), // VSSRANI_B_H
1508 UINT64_C(1936064512), // VSSRANI_DU_Q
1509 UINT64_C(1935802368), // VSSRANI_D_Q
1510 UINT64_C(1935966208), // VSSRANI_HU_W
1511 UINT64_C(1935704064), // VSSRANI_H_W
1512 UINT64_C(1935998976), // VSSRANI_WU_D
1513 UINT64_C(1935736832), // VSSRANI_W_D
1514 UINT64_C(1896251392), // VSSRAN_BU_H
1515 UINT64_C(1895727104), // VSSRAN_B_H
1516 UINT64_C(1896284160), // VSSRAN_HU_W
1517 UINT64_C(1895759872), // VSSRAN_H_W
1518 UINT64_C(1896316928), // VSSRAN_WU_D
1519 UINT64_C(1895792640), // VSSRAN_W_D
1520 UINT64_C(1936474112), // VSSRARNI_BU_H
1521 UINT64_C(1936211968), // VSSRARNI_B_H
1522 UINT64_C(1936588800), // VSSRARNI_DU_Q
1523 UINT64_C(1936326656), // VSSRARNI_D_Q
1524 UINT64_C(1936490496), // VSSRARNI_HU_W
1525 UINT64_C(1936228352), // VSSRARNI_H_W
1526 UINT64_C(1936523264), // VSSRARNI_WU_D
1527 UINT64_C(1936261120), // VSSRARNI_W_D
1528 UINT64_C(1896513536), // VSSRARN_BU_H
1529 UINT64_C(1895989248), // VSSRARN_B_H
1530 UINT64_C(1896546304), // VSSRARN_HU_W
1531 UINT64_C(1896022016), // VSSRARN_H_W
1532 UINT64_C(1896579072), // VSSRARN_WU_D
1533 UINT64_C(1896054784), // VSSRARN_W_D
1534 UINT64_C(1934376960), // VSSRLNI_BU_H
1535 UINT64_C(1934114816), // VSSRLNI_B_H
1536 UINT64_C(1934491648), // VSSRLNI_DU_Q
1537 UINT64_C(1934229504), // VSSRLNI_D_Q
1538 UINT64_C(1934393344), // VSSRLNI_HU_W
1539 UINT64_C(1934131200), // VSSRLNI_H_W
1540 UINT64_C(1934426112), // VSSRLNI_WU_D
1541 UINT64_C(1934163968), // VSSRLNI_W_D
1542 UINT64_C(1896120320), // VSSRLN_BU_H
1543 UINT64_C(1895596032), // VSSRLN_B_H
1544 UINT64_C(1896153088), // VSSRLN_HU_W
1545 UINT64_C(1895628800), // VSSRLN_H_W
1546 UINT64_C(1896185856), // VSSRLN_WU_D
1547 UINT64_C(1895661568), // VSSRLN_W_D
1548 UINT64_C(1934901248), // VSSRLRNI_BU_H
1549 UINT64_C(1934639104), // VSSRLRNI_B_H
1550 UINT64_C(1935015936), // VSSRLRNI_DU_Q
1551 UINT64_C(1934753792), // VSSRLRNI_D_Q
1552 UINT64_C(1934917632), // VSSRLRNI_HU_W
1553 UINT64_C(1934655488), // VSSRLRNI_H_W
1554 UINT64_C(1934950400), // VSSRLRNI_WU_D
1555 UINT64_C(1934688256), // VSSRLRNI_W_D
1556 UINT64_C(1896382464), // VSSRLRN_BU_H
1557 UINT64_C(1895858176), // VSSRLRN_B_H
1558 UINT64_C(1896415232), // VSSRLRN_HU_W
1559 UINT64_C(1895890944), // VSSRLRN_H_W
1560 UINT64_C(1896448000), // VSSRLRN_WU_D
1561 UINT64_C(1895923712), // VSSRLRN_W_D
1562 UINT64_C(1883766784), // VSSUB_B
1563 UINT64_C(1884028928), // VSSUB_BU
1564 UINT64_C(1883865088), // VSSUB_D
1565 UINT64_C(1884127232), // VSSUB_DU
1566 UINT64_C(1883799552), // VSSUB_H
1567 UINT64_C(1884061696), // VSSUB_HU
1568 UINT64_C(1883832320), // VSSUB_W
1569 UINT64_C(1884094464), // VSSUB_WU
1570 UINT64_C(742391808), // VST
1571 UINT64_C(830472192), // VSTELM_B
1572 UINT64_C(823132160), // VSTELM_D
1573 UINT64_C(826277888), // VSTELM_H
1574 UINT64_C(824180736), // VSTELM_W
1575 UINT64_C(943980544), // VSTX
1576 UINT64_C(1921777664), // VSUBI_BU
1577 UINT64_C(1921875968), // VSUBI_DU
1578 UINT64_C(1921810432), // VSUBI_HU
1579 UINT64_C(1921843200), // VSUBI_WU
1580 UINT64_C(1881210880), // VSUBWEV_D_W
1581 UINT64_C(1882259456), // VSUBWEV_D_WU
1582 UINT64_C(1881145344), // VSUBWEV_H_B
1583 UINT64_C(1882193920), // VSUBWEV_H_BU
1584 UINT64_C(1881243648), // VSUBWEV_Q_D
1585 UINT64_C(1882292224), // VSUBWEV_Q_DU
1586 UINT64_C(1881178112), // VSUBWEV_W_H
1587 UINT64_C(1882226688), // VSUBWEV_W_HU
1588 UINT64_C(1881473024), // VSUBWOD_D_W
1589 UINT64_C(1882521600), // VSUBWOD_D_WU
1590 UINT64_C(1881407488), // VSUBWOD_H_B
1591 UINT64_C(1882456064), // VSUBWOD_H_BU
1592 UINT64_C(1881505792), // VSUBWOD_Q_D
1593 UINT64_C(1882554368), // VSUBWOD_Q_DU
1594 UINT64_C(1881440256), // VSUBWOD_W_H
1595 UINT64_C(1882488832), // VSUBWOD_W_HU
1596 UINT64_C(1879834624), // VSUB_B
1597 UINT64_C(1879932928), // VSUB_D
1598 UINT64_C(1879867392), // VSUB_H
1599 UINT64_C(1898807296), // VSUB_Q
1600 UINT64_C(1879900160), // VSUB_W
1601 UINT64_C(1943535616), // VXORI_B
1602 UINT64_C(1898381312), // VXOR_V
1603 UINT64_C(4128780), // X86ADC_B
1604 UINT64_C(4128783), // X86ADC_D
1605 UINT64_C(4128781), // X86ADC_H
1606 UINT64_C(4128782), // X86ADC_W
1607 UINT64_C(4128772), // X86ADD_B
1608 UINT64_C(4128775), // X86ADD_D
1609 UINT64_C(4128769), // X86ADD_DU
1610 UINT64_C(4128773), // X86ADD_H
1611 UINT64_C(4128774), // X86ADD_W
1612 UINT64_C(4128768), // X86ADD_WU
1613 UINT64_C(4161552), // X86AND_B
1614 UINT64_C(4161555), // X86AND_D
1615 UINT64_C(4161553), // X86AND_H
1616 UINT64_C(4161554), // X86AND_W
1617 UINT64_C(32808), // X86CLRTM
1618 UINT64_C(32809), // X86DECTOP
1619 UINT64_C(32772), // X86DEC_B
1620 UINT64_C(32775), // X86DEC_D
1621 UINT64_C(32773), // X86DEC_H
1622 UINT64_C(32774), // X86DEC_W
1623 UINT64_C(32777), // X86INCTOP
1624 UINT64_C(32768), // X86INC_B
1625 UINT64_C(32771), // X86INC_D
1626 UINT64_C(32769), // X86INC_H
1627 UINT64_C(32770), // X86INC_W
1628 UINT64_C(6029312), // X86MFFLAG
1629 UINT64_C(29696), // X86MFTOP
1630 UINT64_C(6029344), // X86MTFLAG
1631 UINT64_C(28672), // X86MTTOP
1632 UINT64_C(4096000), // X86MUL_B
1633 UINT64_C(4096004), // X86MUL_BU
1634 UINT64_C(4096003), // X86MUL_D
1635 UINT64_C(4096007), // X86MUL_DU
1636 UINT64_C(4096001), // X86MUL_H
1637 UINT64_C(4096005), // X86MUL_HU
1638 UINT64_C(4096002), // X86MUL_W
1639 UINT64_C(4096006), // X86MUL_WU
1640 UINT64_C(4161556), // X86OR_B
1641 UINT64_C(4161559), // X86OR_D
1642 UINT64_C(4161557), // X86OR_H
1643 UINT64_C(4161558), // X86OR_W
1644 UINT64_C(5513240), // X86RCLI_B
1645 UINT64_C(5570587), // X86RCLI_D
1646 UINT64_C(5521433), // X86RCLI_H
1647 UINT64_C(5537818), // X86RCLI_W
1648 UINT64_C(4161548), // X86RCL_B
1649 UINT64_C(4161551), // X86RCL_D
1650 UINT64_C(4161549), // X86RCL_H
1651 UINT64_C(4161550), // X86RCL_W
1652 UINT64_C(5513232), // X86RCRI_B
1653 UINT64_C(5570579), // X86RCRI_D
1654 UINT64_C(5521425), // X86RCRI_H
1655 UINT64_C(5537810), // X86RCRI_W
1656 UINT64_C(4161544), // X86RCR_B
1657 UINT64_C(4161547), // X86RCR_D
1658 UINT64_C(4161545), // X86RCR_H
1659 UINT64_C(4161546), // X86RCR_W
1660 UINT64_C(5513236), // X86ROTLI_B
1661 UINT64_C(5570583), // X86ROTLI_D
1662 UINT64_C(5521429), // X86ROTLI_H
1663 UINT64_C(5537814), // X86ROTLI_W
1664 UINT64_C(4161540), // X86ROTL_B
1665 UINT64_C(4161543), // X86ROTL_D
1666 UINT64_C(4161541), // X86ROTL_H
1667 UINT64_C(4161542), // X86ROTL_W
1668 UINT64_C(5513228), // X86ROTRI_B
1669 UINT64_C(5570575), // X86ROTRI_D
1670 UINT64_C(5521421), // X86ROTRI_H
1671 UINT64_C(5537806), // X86ROTRI_W
1672 UINT64_C(4161536), // X86ROTR_B
1673 UINT64_C(4161538), // X86ROTR_D
1674 UINT64_C(4161537), // X86ROTR_H
1675 UINT64_C(4161539), // X86ROTR_W
1676 UINT64_C(4128784), // X86SBC_B
1677 UINT64_C(4128787), // X86SBC_D
1678 UINT64_C(4128785), // X86SBC_H
1679 UINT64_C(4128786), // X86SBC_W
1680 UINT64_C(5767168), // X86SETTAG
1681 UINT64_C(32776), // X86SETTM
1682 UINT64_C(5513216), // X86SLLI_B
1683 UINT64_C(5570563), // X86SLLI_D
1684 UINT64_C(5521409), // X86SLLI_H
1685 UINT64_C(5537794), // X86SLLI_W
1686 UINT64_C(4128788), // X86SLL_B
1687 UINT64_C(4128791), // X86SLL_D
1688 UINT64_C(4128789), // X86SLL_H
1689 UINT64_C(4128790), // X86SLL_W
1690 UINT64_C(5513224), // X86SRAI_B
1691 UINT64_C(5570571), // X86SRAI_D
1692 UINT64_C(5521417), // X86SRAI_H
1693 UINT64_C(5537802), // X86SRAI_W
1694 UINT64_C(4128796), // X86SRA_B
1695 UINT64_C(4128799), // X86SRA_D
1696 UINT64_C(4128797), // X86SRA_H
1697 UINT64_C(4128798), // X86SRA_W
1698 UINT64_C(5513220), // X86SRLI_B
1699 UINT64_C(5570567), // X86SRLI_D
1700 UINT64_C(5521413), // X86SRLI_H
1701 UINT64_C(5537798), // X86SRLI_W
1702 UINT64_C(4128792), // X86SRL_B
1703 UINT64_C(4128795), // X86SRL_D
1704 UINT64_C(4128793), // X86SRL_H
1705 UINT64_C(4128794), // X86SRL_W
1706 UINT64_C(4128776), // X86SUB_B
1707 UINT64_C(4128779), // X86SUB_D
1708 UINT64_C(4128771), // X86SUB_DU
1709 UINT64_C(4128777), // X86SUB_H
1710 UINT64_C(4128778), // X86SUB_W
1711 UINT64_C(4128770), // X86SUB_WU
1712 UINT64_C(4161560), // X86XOR_B
1713 UINT64_C(4161563), // X86XOR_D
1714 UINT64_C(4161561), // X86XOR_H
1715 UINT64_C(4161562), // X86XOR_W
1716 UINT64_C(1409024), // XOR
1717 UINT64_C(62914560), // XORI
1718 UINT64_C(1952448512), // XVABSD_B
1719 UINT64_C(1952579584), // XVABSD_BU
1720 UINT64_C(1952546816), // XVABSD_D
1721 UINT64_C(1952677888), // XVABSD_DU
1722 UINT64_C(1952481280), // XVABSD_H
1723 UINT64_C(1952612352), // XVABSD_HU
1724 UINT64_C(1952514048), // XVABSD_W
1725 UINT64_C(1952645120), // XVABSD_WU
1726 UINT64_C(1952186368), // XVADDA_B
1727 UINT64_C(1952284672), // XVADDA_D
1728 UINT64_C(1952219136), // XVADDA_H
1729 UINT64_C(1952251904), // XVADDA_W
1730 UINT64_C(1988755456), // XVADDI_BU
1731 UINT64_C(1988853760), // XVADDI_DU
1732 UINT64_C(1988788224), // XVADDI_HU
1733 UINT64_C(1988820992), // XVADDI_WU
1734 UINT64_C(1948188672), // XVADDWEV_D_W
1735 UINT64_C(1949237248), // XVADDWEV_D_WU
1736 UINT64_C(1950285824), // XVADDWEV_D_WU_W
1737 UINT64_C(1948123136), // XVADDWEV_H_B
1738 UINT64_C(1949171712), // XVADDWEV_H_BU
1739 UINT64_C(1950220288), // XVADDWEV_H_BU_B
1740 UINT64_C(1948221440), // XVADDWEV_Q_D
1741 UINT64_C(1949270016), // XVADDWEV_Q_DU
1742 UINT64_C(1950318592), // XVADDWEV_Q_DU_D
1743 UINT64_C(1948155904), // XVADDWEV_W_H
1744 UINT64_C(1949204480), // XVADDWEV_W_HU
1745 UINT64_C(1950253056), // XVADDWEV_W_HU_H
1746 UINT64_C(1948450816), // XVADDWOD_D_W
1747 UINT64_C(1949499392), // XVADDWOD_D_WU
1748 UINT64_C(1950416896), // XVADDWOD_D_WU_W
1749 UINT64_C(1948385280), // XVADDWOD_H_B
1750 UINT64_C(1949433856), // XVADDWOD_H_BU
1751 UINT64_C(1950351360), // XVADDWOD_H_BU_B
1752 UINT64_C(1948483584), // XVADDWOD_Q_D
1753 UINT64_C(1949532160), // XVADDWOD_Q_DU
1754 UINT64_C(1950449664), // XVADDWOD_Q_DU_D
1755 UINT64_C(1948418048), // XVADDWOD_W_H
1756 UINT64_C(1949466624), // XVADDWOD_W_HU
1757 UINT64_C(1950384128), // XVADDWOD_W_HU_H
1758 UINT64_C(1946812416), // XVADD_B
1759 UINT64_C(1946910720), // XVADD_D
1760 UINT64_C(1946845184), // XVADD_H
1761 UINT64_C(1965883392), // XVADD_Q
1762 UINT64_C(1946877952), // XVADD_W
1763 UINT64_C(2010120192), // XVANDI_B
1764 UINT64_C(1965555712), // XVANDN_V
1765 UINT64_C(1965424640), // XVAND_V
1766 UINT64_C(1952972800), // XVAVGR_B
1767 UINT64_C(1953103872), // XVAVGR_BU
1768 UINT64_C(1953071104), // XVAVGR_D
1769 UINT64_C(1953202176), // XVAVGR_DU
1770 UINT64_C(1953005568), // XVAVGR_H
1771 UINT64_C(1953136640), // XVAVGR_HU
1772 UINT64_C(1953038336), // XVAVGR_W
1773 UINT64_C(1953169408), // XVAVGR_WU
1774 UINT64_C(1952710656), // XVAVG_B
1775 UINT64_C(1952841728), // XVAVG_BU
1776 UINT64_C(1952808960), // XVAVG_D
1777 UINT64_C(1952940032), // XVAVG_DU
1778 UINT64_C(1952743424), // XVAVG_H
1779 UINT64_C(1952874496), // XVAVG_HU
1780 UINT64_C(1952776192), // XVAVG_W
1781 UINT64_C(1952907264), // XVAVG_WU
1782 UINT64_C(1997545472), // XVBITCLRI_B
1783 UINT64_C(1997602816), // XVBITCLRI_D
1784 UINT64_C(1997553664), // XVBITCLRI_H
1785 UINT64_C(1997570048), // XVBITCLRI_W
1786 UINT64_C(1963720704), // XVBITCLR_B
1787 UINT64_C(1963819008), // XVBITCLR_D
1788 UINT64_C(1963753472), // XVBITCLR_H
1789 UINT64_C(1963786240), // XVBITCLR_W
1790 UINT64_C(1998069760), // XVBITREVI_B
1791 UINT64_C(1998127104), // XVBITREVI_D
1792 UINT64_C(1998077952), // XVBITREVI_H
1793 UINT64_C(1998094336), // XVBITREVI_W
1794 UINT64_C(1963982848), // XVBITREV_B
1795 UINT64_C(1964081152), // XVBITREV_D
1796 UINT64_C(1964015616), // XVBITREV_H
1797 UINT64_C(1964048384), // XVBITREV_W
1798 UINT64_C(2009333760), // XVBITSELI_B
1799 UINT64_C(220200960), // XVBITSEL_V
1800 UINT64_C(1997807616), // XVBITSETI_B
1801 UINT64_C(1997864960), // XVBITSETI_D
1802 UINT64_C(1997815808), // XVBITSETI_H
1803 UINT64_C(1997832192), // XVBITSETI_W
1804 UINT64_C(1963851776), // XVBITSET_B
1805 UINT64_C(1963950080), // XVBITSET_D
1806 UINT64_C(1963884544), // XVBITSET_H
1807 UINT64_C(1963917312), // XVBITSET_W
1808 UINT64_C(1989017600), // XVBSLL_V
1809 UINT64_C(1989050368), // XVBSRL_V
1810 UINT64_C(1989935104), // XVCLO_B
1811 UINT64_C(1989938176), // XVCLO_D
1812 UINT64_C(1989936128), // XVCLO_H
1813 UINT64_C(1989937152), // XVCLO_W
1814 UINT64_C(1989939200), // XVCLZ_B
1815 UINT64_C(1989942272), // XVCLZ_D
1816 UINT64_C(1989940224), // XVCLZ_H
1817 UINT64_C(1989941248), // XVCLZ_W
1818 UINT64_C(1960837120), // XVDIV_B
1819 UINT64_C(1961099264), // XVDIV_BU
1820 UINT64_C(1960935424), // XVDIV_D
1821 UINT64_C(1961197568), // XVDIV_DU
1822 UINT64_C(1960869888), // XVDIV_H
1823 UINT64_C(1961132032), // XVDIV_HU
1824 UINT64_C(1960902656), // XVDIV_W
1825 UINT64_C(1961164800), // XVDIV_WU
1826 UINT64_C(1990129664), // XVEXTH_DU_WU
1827 UINT64_C(1990125568), // XVEXTH_D_W
1828 UINT64_C(1990127616), // XVEXTH_HU_BU
1829 UINT64_C(1990123520), // XVEXTH_H_B
1830 UINT64_C(1990130688), // XVEXTH_QU_DU
1831 UINT64_C(1990126592), // XVEXTH_Q_D
1832 UINT64_C(1990128640), // XVEXTH_WU_HU
1833 UINT64_C(1990124544), // XVEXTH_W_H
1834 UINT64_C(1997340672), // XVEXTL_QU_DU
1835 UINT64_C(1997078528), // XVEXTL_Q_D
1836 UINT64_C(2005663744), // XVEXTRINS_B
1837 UINT64_C(2004877312), // XVEXTRINS_D
1838 UINT64_C(2005401600), // XVEXTRINS_H
1839 UINT64_C(2005139456), // XVEXTRINS_W
1840 UINT64_C(1966145536), // XVFADD_D
1841 UINT64_C(1966112768), // XVFADD_S
1842 UINT64_C(1989990400), // XVFCLASS_D
1843 UINT64_C(1989989376), // XVFCLASS_S
1844 UINT64_C(211812352), // XVFCMP_CAF_D
1845 UINT64_C(210763776), // XVFCMP_CAF_S
1846 UINT64_C(211943424), // XVFCMP_CEQ_D
1847 UINT64_C(210894848), // XVFCMP_CEQ_S
1848 UINT64_C(212008960), // XVFCMP_CLE_D
1849 UINT64_C(210960384), // XVFCMP_CLE_S
1850 UINT64_C(211877888), // XVFCMP_CLT_D
1851 UINT64_C(210829312), // XVFCMP_CLT_S
1852 UINT64_C(212336640), // XVFCMP_CNE_D
1853 UINT64_C(211288064), // XVFCMP_CNE_S
1854 UINT64_C(212467712), // XVFCMP_COR_D
1855 UINT64_C(211419136), // XVFCMP_COR_S
1856 UINT64_C(212205568), // XVFCMP_CUEQ_D
1857 UINT64_C(211156992), // XVFCMP_CUEQ_S
1858 UINT64_C(212271104), // XVFCMP_CULE_D
1859 UINT64_C(211222528), // XVFCMP_CULE_S
1860 UINT64_C(212140032), // XVFCMP_CULT_D
1861 UINT64_C(211091456), // XVFCMP_CULT_S
1862 UINT64_C(212598784), // XVFCMP_CUNE_D
1863 UINT64_C(211550208), // XVFCMP_CUNE_S
1864 UINT64_C(212074496), // XVFCMP_CUN_D
1865 UINT64_C(211025920), // XVFCMP_CUN_S
1866 UINT64_C(211845120), // XVFCMP_SAF_D
1867 UINT64_C(210796544), // XVFCMP_SAF_S
1868 UINT64_C(211976192), // XVFCMP_SEQ_D
1869 UINT64_C(210927616), // XVFCMP_SEQ_S
1870 UINT64_C(212041728), // XVFCMP_SLE_D
1871 UINT64_C(210993152), // XVFCMP_SLE_S
1872 UINT64_C(211910656), // XVFCMP_SLT_D
1873 UINT64_C(210862080), // XVFCMP_SLT_S
1874 UINT64_C(212369408), // XVFCMP_SNE_D
1875 UINT64_C(211320832), // XVFCMP_SNE_S
1876 UINT64_C(212500480), // XVFCMP_SOR_D
1877 UINT64_C(211451904), // XVFCMP_SOR_S
1878 UINT64_C(212238336), // XVFCMP_SUEQ_D
1879 UINT64_C(211189760), // XVFCMP_SUEQ_S
1880 UINT64_C(212303872), // XVFCMP_SULE_D
1881 UINT64_C(211255296), // XVFCMP_SULE_S
1882 UINT64_C(212172800), // XVFCMP_SULT_D
1883 UINT64_C(211124224), // XVFCMP_SULT_S
1884 UINT64_C(212631552), // XVFCMP_SUNE_D
1885 UINT64_C(211582976), // XVFCMP_SUNE_S
1886 UINT64_C(212107264), // XVFCMP_SUN_D
1887 UINT64_C(211058688), // XVFCMP_SUN_S
1888 UINT64_C(1990063104), // XVFCVTH_D_S
1889 UINT64_C(1990061056), // XVFCVTH_S_H
1890 UINT64_C(1990062080), // XVFCVTL_D_S
1891 UINT64_C(1990060032), // XVFCVTL_S_H
1892 UINT64_C(1967521792), // XVFCVT_H_S
1893 UINT64_C(1967554560), // XVFCVT_S_D
1894 UINT64_C(1966800896), // XVFDIV_D
1895 UINT64_C(1966768128), // XVFDIV_S
1896 UINT64_C(1990071296), // XVFFINTH_D_W
1897 UINT64_C(1990070272), // XVFFINTL_D_W
1898 UINT64_C(1990068224), // XVFFINT_D_L
1899 UINT64_C(1990069248), // XVFFINT_D_LU
1900 UINT64_C(1967652864), // XVFFINT_S_L
1901 UINT64_C(1990066176), // XVFFINT_S_W
1902 UINT64_C(1990067200), // XVFFINT_S_WU
1903 UINT64_C(1989986304), // XVFLOGB_D
1904 UINT64_C(1989985280), // XVFLOGB_S
1905 UINT64_C(169869312), // XVFMADD_D
1906 UINT64_C(168820736), // XVFMADD_S
1907 UINT64_C(1967194112), // XVFMAXA_D
1908 UINT64_C(1967161344), // XVFMAXA_S
1909 UINT64_C(1966931968), // XVFMAX_D
1910 UINT64_C(1966899200), // XVFMAX_S
1911 UINT64_C(1967325184), // XVFMINA_D
1912 UINT64_C(1967292416), // XVFMINA_S
1913 UINT64_C(1967063040), // XVFMIN_D
1914 UINT64_C(1967030272), // XVFMIN_S
1915 UINT64_C(174063616), // XVFMSUB_D
1916 UINT64_C(173015040), // XVFMSUB_S
1917 UINT64_C(1966669824), // XVFMUL_D
1918 UINT64_C(1966637056), // XVFMUL_S
1919 UINT64_C(178257920), // XVFNMADD_D
1920 UINT64_C(177209344), // XVFNMADD_S
1921 UINT64_C(182452224), // XVFNMSUB_D
1922 UINT64_C(181403648), // XVFNMSUB_S
1923 UINT64_C(1990006784), // XVFRECIPE_D
1924 UINT64_C(1990005760), // XVFRECIPE_S
1925 UINT64_C(1989998592), // XVFRECIP_D
1926 UINT64_C(1989997568), // XVFRECIP_S
1927 UINT64_C(1990019072), // XVFRINTRM_D
1928 UINT64_C(1990018048), // XVFRINTRM_S
1929 UINT64_C(1990031360), // XVFRINTRNE_D
1930 UINT64_C(1990030336), // XVFRINTRNE_S
1931 UINT64_C(1990023168), // XVFRINTRP_D
1932 UINT64_C(1990022144), // XVFRINTRP_S
1933 UINT64_C(1990027264), // XVFRINTRZ_D
1934 UINT64_C(1990026240), // XVFRINTRZ_S
1935 UINT64_C(1990014976), // XVFRINT_D
1936 UINT64_C(1990013952), // XVFRINT_S
1937 UINT64_C(1990010880), // XVFRSQRTE_D
1938 UINT64_C(1990009856), // XVFRSQRTE_S
1939 UINT64_C(1990002688), // XVFRSQRT_D
1940 UINT64_C(1990001664), // XVFRSQRT_S
1941 UINT64_C(1989804032), // XVFRSTPI_B
1942 UINT64_C(1989836800), // XVFRSTPI_H
1943 UINT64_C(1965752320), // XVFRSTP_B
1944 UINT64_C(1965785088), // XVFRSTP_H
1945 UINT64_C(1989994496), // XVFSQRT_D
1946 UINT64_C(1989993472), // XVFSQRT_S
1947 UINT64_C(1966276608), // XVFSUB_D
1948 UINT64_C(1966243840), // XVFSUB_S
1949 UINT64_C(1990099968), // XVFTINTH_L_S
1950 UINT64_C(1990098944), // XVFTINTL_L_S
1951 UINT64_C(1990102016), // XVFTINTRMH_L_S
1952 UINT64_C(1990100992), // XVFTINTRML_L_S
1953 UINT64_C(1990081536), // XVFTINTRM_L_D
1954 UINT64_C(1967783936), // XVFTINTRM_W_D
1955 UINT64_C(1990080512), // XVFTINTRM_W_S
1956 UINT64_C(1990108160), // XVFTINTRNEH_L_S
1957 UINT64_C(1990107136), // XVFTINTRNEL_L_S
1958 UINT64_C(1990087680), // XVFTINTRNE_L_D
1959 UINT64_C(1967882240), // XVFTINTRNE_W_D
1960 UINT64_C(1990086656), // XVFTINTRNE_W_S
1961 UINT64_C(1990104064), // XVFTINTRPH_L_S
1962 UINT64_C(1990103040), // XVFTINTRPL_L_S
1963 UINT64_C(1990083584), // XVFTINTRP_L_D
1964 UINT64_C(1967816704), // XVFTINTRP_W_D
1965 UINT64_C(1990082560), // XVFTINTRP_W_S
1966 UINT64_C(1990106112), // XVFTINTRZH_L_S
1967 UINT64_C(1990105088), // XVFTINTRZL_L_S
1968 UINT64_C(1990095872), // XVFTINTRZ_LU_D
1969 UINT64_C(1990085632), // XVFTINTRZ_L_D
1970 UINT64_C(1990094848), // XVFTINTRZ_WU_S
1971 UINT64_C(1967849472), // XVFTINTRZ_W_D
1972 UINT64_C(1990084608), // XVFTINTRZ_W_S
1973 UINT64_C(1990089728), // XVFTINT_LU_D
1974 UINT64_C(1990079488), // XVFTINT_L_D
1975 UINT64_C(1990088704), // XVFTINT_WU_S
1976 UINT64_C(1967751168), // XVFTINT_W_D
1977 UINT64_C(1990078464), // XVFTINT_W_S
1978 UINT64_C(1951989760), // XVHADDW_DU_WU
1979 UINT64_C(1951727616), // XVHADDW_D_W
1980 UINT64_C(1951924224), // XVHADDW_HU_BU
1981 UINT64_C(1951662080), // XVHADDW_H_B
1982 UINT64_C(1952022528), // XVHADDW_QU_DU
1983 UINT64_C(1951760384), // XVHADDW_Q_D
1984 UINT64_C(1951956992), // XVHADDW_WU_HU
1985 UINT64_C(1951694848), // XVHADDW_W_H
1986 UINT64_C(1990164480), // XVHSELI_D
1987 UINT64_C(1952120832), // XVHSUBW_DU_WU
1988 UINT64_C(1951858688), // XVHSUBW_D_W
1989 UINT64_C(1952055296), // XVHSUBW_HU_BU
1990 UINT64_C(1951793152), // XVHSUBW_H_B
1991 UINT64_C(1952153600), // XVHSUBW_QU_DU
1992 UINT64_C(1951891456), // XVHSUBW_Q_D
1993 UINT64_C(1952088064), // XVHSUBW_WU_HU
1994 UINT64_C(1951825920), // XVHSUBW_W_H
1995 UINT64_C(1964769280), // XVILVH_B
1996 UINT64_C(1964867584), // XVILVH_D
1997 UINT64_C(1964802048), // XVILVH_H
1998 UINT64_C(1964834816), // XVILVH_W
1999 UINT64_C(1964638208), // XVILVL_B
2000 UINT64_C(1964736512), // XVILVL_D
2001 UINT64_C(1964670976), // XVILVL_H
2002 UINT64_C(1964703744), // XVILVL_W
2003 UINT64_C(1995169792), // XVINSGR2VR_D
2004 UINT64_C(1995161600), // XVINSGR2VR_W
2005 UINT64_C(1996480512), // XVINSVE0_D
2006 UINT64_C(1996472320), // XVINSVE0_W
2007 UINT64_C(746586112), // XVLD
2008 UINT64_C(2011168768), // XVLDI
2009 UINT64_C(847249408), // XVLDREPL_B
2010 UINT64_C(839909376), // XVLDREPL_D
2011 UINT64_C(843055104), // XVLDREPL_H
2012 UINT64_C(840957952), // XVLDREPL_W
2013 UINT64_C(944242688), // XVLDX
2014 UINT64_C(1957494784), // XVMADDWEV_D_W
2015 UINT64_C(1958019072), // XVMADDWEV_D_WU
2016 UINT64_C(1958543360), // XVMADDWEV_D_WU_W
2017 UINT64_C(1957429248), // XVMADDWEV_H_B
2018 UINT64_C(1957953536), // XVMADDWEV_H_BU
2019 UINT64_C(1958477824), // XVMADDWEV_H_BU_B
2020 UINT64_C(1957527552), // XVMADDWEV_Q_D
2021 UINT64_C(1958051840), // XVMADDWEV_Q_DU
2022 UINT64_C(1958576128), // XVMADDWEV_Q_DU_D
2023 UINT64_C(1957462016), // XVMADDWEV_W_H
2024 UINT64_C(1957986304), // XVMADDWEV_W_HU
2025 UINT64_C(1958510592), // XVMADDWEV_W_HU_H
2026 UINT64_C(1957625856), // XVMADDWOD_D_W
2027 UINT64_C(1958150144), // XVMADDWOD_D_WU
2028 UINT64_C(1958674432), // XVMADDWOD_D_WU_W
2029 UINT64_C(1957560320), // XVMADDWOD_H_B
2030 UINT64_C(1958084608), // XVMADDWOD_H_BU
2031 UINT64_C(1958608896), // XVMADDWOD_H_BU_B
2032 UINT64_C(1957658624), // XVMADDWOD_Q_D
2033 UINT64_C(1958182912), // XVMADDWOD_Q_DU
2034 UINT64_C(1958707200), // XVMADDWOD_Q_DU_D
2035 UINT64_C(1957593088), // XVMADDWOD_W_H
2036 UINT64_C(1958117376), // XVMADDWOD_W_HU
2037 UINT64_C(1958641664), // XVMADDWOD_W_HU_H
2038 UINT64_C(1957167104), // XVMADD_B
2039 UINT64_C(1957265408), // XVMADD_D
2040 UINT64_C(1957199872), // XVMADD_H
2041 UINT64_C(1957232640), // XVMADD_W
2042 UINT64_C(1989148672), // XVMAXI_B
2043 UINT64_C(1989410816), // XVMAXI_BU
2044 UINT64_C(1989246976), // XVMAXI_D
2045 UINT64_C(1989509120), // XVMAXI_DU
2046 UINT64_C(1989181440), // XVMAXI_H
2047 UINT64_C(1989443584), // XVMAXI_HU
2048 UINT64_C(1989214208), // XVMAXI_W
2049 UINT64_C(1989476352), // XVMAXI_WU
2050 UINT64_C(1953497088), // XVMAX_B
2051 UINT64_C(1953759232), // XVMAX_BU
2052 UINT64_C(1953595392), // XVMAX_D
2053 UINT64_C(1953857536), // XVMAX_DU
2054 UINT64_C(1953529856), // XVMAX_H
2055 UINT64_C(1953792000), // XVMAX_HU
2056 UINT64_C(1953562624), // XVMAX_W
2057 UINT64_C(1953824768), // XVMAX_WU
2058 UINT64_C(1989279744), // XVMINI_B
2059 UINT64_C(1989541888), // XVMINI_BU
2060 UINT64_C(1989378048), // XVMINI_D
2061 UINT64_C(1989640192), // XVMINI_DU
2062 UINT64_C(1989312512), // XVMINI_H
2063 UINT64_C(1989574656), // XVMINI_HU
2064 UINT64_C(1989345280), // XVMINI_W
2065 UINT64_C(1989607424), // XVMINI_WU
2066 UINT64_C(1953628160), // XVMIN_B
2067 UINT64_C(1953890304), // XVMIN_BU
2068 UINT64_C(1953726464), // XVMIN_D
2069 UINT64_C(1953988608), // XVMIN_DU
2070 UINT64_C(1953660928), // XVMIN_H
2071 UINT64_C(1953923072), // XVMIN_HU
2072 UINT64_C(1953693696), // XVMIN_W
2073 UINT64_C(1953955840), // XVMIN_WU
2074 UINT64_C(1960968192), // XVMOD_B
2075 UINT64_C(1961230336), // XVMOD_BU
2076 UINT64_C(1961066496), // XVMOD_D
2077 UINT64_C(1961328640), // XVMOD_DU
2078 UINT64_C(1961000960), // XVMOD_H
2079 UINT64_C(1961263104), // XVMOD_HU
2080 UINT64_C(1961033728), // XVMOD_W
2081 UINT64_C(1961295872), // XVMOD_WU
2082 UINT64_C(1989955584), // XVMSKGEZ_B
2083 UINT64_C(1989951488), // XVMSKLTZ_B
2084 UINT64_C(1989954560), // XVMSKLTZ_D
2085 UINT64_C(1989952512), // XVMSKLTZ_H
2086 UINT64_C(1989953536), // XVMSKLTZ_W
2087 UINT64_C(1989959680), // XVMSKNZ_B
2088 UINT64_C(1957298176), // XVMSUB_B
2089 UINT64_C(1957396480), // XVMSUB_D
2090 UINT64_C(1957330944), // XVMSUB_H
2091 UINT64_C(1957363712), // XVMSUB_W
2092 UINT64_C(1954938880), // XVMUH_B
2093 UINT64_C(1955069952), // XVMUH_BU
2094 UINT64_C(1955037184), // XVMUH_D
2095 UINT64_C(1955168256), // XVMUH_DU
2096 UINT64_C(1954971648), // XVMUH_H
2097 UINT64_C(1955102720), // XVMUH_HU
2098 UINT64_C(1955004416), // XVMUH_W
2099 UINT64_C(1955135488), // XVMUH_WU
2100 UINT64_C(1955659776), // XVMULWEV_D_W
2101 UINT64_C(1956184064), // XVMULWEV_D_WU
2102 UINT64_C(1956708352), // XVMULWEV_D_WU_W
2103 UINT64_C(1955594240), // XVMULWEV_H_B
2104 UINT64_C(1956118528), // XVMULWEV_H_BU
2105 UINT64_C(1956642816), // XVMULWEV_H_BU_B
2106 UINT64_C(1955692544), // XVMULWEV_Q_D
2107 UINT64_C(1956216832), // XVMULWEV_Q_DU
2108 UINT64_C(1956741120), // XVMULWEV_Q_DU_D
2109 UINT64_C(1955627008), // XVMULWEV_W_H
2110 UINT64_C(1956151296), // XVMULWEV_W_HU
2111 UINT64_C(1956675584), // XVMULWEV_W_HU_H
2112 UINT64_C(1955790848), // XVMULWOD_D_W
2113 UINT64_C(1956315136), // XVMULWOD_D_WU
2114 UINT64_C(1956839424), // XVMULWOD_D_WU_W
2115 UINT64_C(1955725312), // XVMULWOD_H_B
2116 UINT64_C(1956249600), // XVMULWOD_H_BU
2117 UINT64_C(1956773888), // XVMULWOD_H_BU_B
2118 UINT64_C(1955823616), // XVMULWOD_Q_D
2119 UINT64_C(1956347904), // XVMULWOD_Q_DU
2120 UINT64_C(1956872192), // XVMULWOD_Q_DU_D
2121 UINT64_C(1955758080), // XVMULWOD_W_H
2122 UINT64_C(1956282368), // XVMULWOD_W_HU
2123 UINT64_C(1956806656), // XVMULWOD_W_HU_H
2124 UINT64_C(1954807808), // XVMUL_B
2125 UINT64_C(1954906112), // XVMUL_D
2126 UINT64_C(1954840576), // XVMUL_H
2127 UINT64_C(1954873344), // XVMUL_W
2128 UINT64_C(1989947392), // XVNEG_B
2129 UINT64_C(1989950464), // XVNEG_D
2130 UINT64_C(1989948416), // XVNEG_H
2131 UINT64_C(1989949440), // XVNEG_W
2132 UINT64_C(2010906624), // XVNORI_B
2133 UINT64_C(1965522944), // XVNOR_V
2134 UINT64_C(2010382336), // XVORI_B
2135 UINT64_C(1965588480), // XVORN_V
2136 UINT64_C(1965457408), // XVOR_V
2137 UINT64_C(1964376064), // XVPACKEV_B
2138 UINT64_C(1964474368), // XVPACKEV_D
2139 UINT64_C(1964408832), // XVPACKEV_H
2140 UINT64_C(1964441600), // XVPACKEV_W
2141 UINT64_C(1964507136), // XVPACKOD_B
2142 UINT64_C(1964605440), // XVPACKOD_D
2143 UINT64_C(1964539904), // XVPACKOD_H
2144 UINT64_C(1964572672), // XVPACKOD_W
2145 UINT64_C(1989943296), // XVPCNT_B
2146 UINT64_C(1989946368), // XVPCNT_D
2147 UINT64_C(1989944320), // XVPCNT_H
2148 UINT64_C(1989945344), // XVPCNT_W
2149 UINT64_C(2011693056), // XVPERMI_D
2150 UINT64_C(2011955200), // XVPERMI_Q
2151 UINT64_C(2011430912), // XVPERMI_W
2152 UINT64_C(1971126272), // XVPERM_W
2153 UINT64_C(1964900352), // XVPICKEV_B
2154 UINT64_C(1964998656), // XVPICKEV_D
2155 UINT64_C(1964933120), // XVPICKEV_H
2156 UINT64_C(1964965888), // XVPICKEV_W
2157 UINT64_C(1965031424), // XVPICKOD_B
2158 UINT64_C(1965129728), // XVPICKOD_D
2159 UINT64_C(1965064192), // XVPICKOD_H
2160 UINT64_C(1965096960), // XVPICKOD_W
2161 UINT64_C(1995431936), // XVPICKVE2GR_D
2162 UINT64_C(1995694080), // XVPICKVE2GR_DU
2163 UINT64_C(1995423744), // XVPICKVE2GR_W
2164 UINT64_C(1995685888), // XVPICKVE2GR_WU
2165 UINT64_C(1996742656), // XVPICKVE_D
2166 UINT64_C(1996734464), // XVPICKVE_W
2167 UINT64_C(1995931648), // XVREPL128VEI_B
2168 UINT64_C(1995960320), // XVREPL128VEI_D
2169 UINT64_C(1995948032), // XVREPL128VEI_H
2170 UINT64_C(1995956224), // XVREPL128VEI_W
2171 UINT64_C(1990131712), // XVREPLGR2VR_B
2172 UINT64_C(1990134784), // XVREPLGR2VR_D
2173 UINT64_C(1990132736), // XVREPLGR2VR_H
2174 UINT64_C(1990133760), // XVREPLGR2VR_W
2175 UINT64_C(1996947456), // XVREPLVE0_B
2176 UINT64_C(1997004800), // XVREPLVE0_D
2177 UINT64_C(1996980224), // XVREPLVE0_H
2178 UINT64_C(1997008896), // XVREPLVE0_Q
2179 UINT64_C(1996996608), // XVREPLVE0_W
2180 UINT64_C(1965162496), // XVREPLVE_B
2181 UINT64_C(1965260800), // XVREPLVE_D
2182 UINT64_C(1965195264), // XVREPLVE_H
2183 UINT64_C(1965228032), // XVREPLVE_W
2184 UINT64_C(1990205440), // XVROTRI_B
2185 UINT64_C(1990262784), // XVROTRI_D
2186 UINT64_C(1990213632), // XVROTRI_H
2187 UINT64_C(1990230016), // XVROTRI_W
2188 UINT64_C(1961754624), // XVROTR_B
2189 UINT64_C(1961852928), // XVROTR_D
2190 UINT64_C(1961787392), // XVROTR_H
2191 UINT64_C(1961820160), // XVROTR_W
2192 UINT64_C(1950744576), // XVSADD_B
2193 UINT64_C(1951006720), // XVSADD_BU
2194 UINT64_C(1950842880), // XVSADD_D
2195 UINT64_C(1951105024), // XVSADD_DU
2196 UINT64_C(1950777344), // XVSADD_H
2197 UINT64_C(1951039488), // XVSADD_HU
2198 UINT64_C(1950810112), // XVSADD_W
2199 UINT64_C(1951072256), // XVSADD_WU
2200 UINT64_C(1998856192), // XVSAT_B
2201 UINT64_C(1999118336), // XVSAT_BU
2202 UINT64_C(1998913536), // XVSAT_D
2203 UINT64_C(1999175680), // XVSAT_DU
2204 UINT64_C(1998864384), // XVSAT_H
2205 UINT64_C(1999126528), // XVSAT_HU
2206 UINT64_C(1998880768), // XVSAT_W
2207 UINT64_C(1999142912), // XVSAT_WU
2208 UINT64_C(1988100096), // XVSEQI_B
2209 UINT64_C(1988198400), // XVSEQI_D
2210 UINT64_C(1988132864), // XVSEQI_H
2211 UINT64_C(1988165632), // XVSEQI_W
2212 UINT64_C(1946157056), // XVSEQ_B
2213 UINT64_C(1946255360), // XVSEQ_D
2214 UINT64_C(1946189824), // XVSEQ_H
2215 UINT64_C(1946222592), // XVSEQ_W
2216 UINT64_C(1989980160), // XVSETALLNEZ_B
2217 UINT64_C(1989983232), // XVSETALLNEZ_D
2218 UINT64_C(1989981184), // XVSETALLNEZ_H
2219 UINT64_C(1989982208), // XVSETALLNEZ_W
2220 UINT64_C(1989976064), // XVSETANYEQZ_B
2221 UINT64_C(1989979136), // XVSETANYEQZ_D
2222 UINT64_C(1989977088), // XVSETANYEQZ_H
2223 UINT64_C(1989978112), // XVSETANYEQZ_W
2224 UINT64_C(1989974016), // XVSETEQZ_V
2225 UINT64_C(1989975040), // XVSETNEZ_V
2226 UINT64_C(2005925888), // XVSHUF4I_B
2227 UINT64_C(2006712320), // XVSHUF4I_D
2228 UINT64_C(2006188032), // XVSHUF4I_H
2229 UINT64_C(2006450176), // XVSHUF4I_W
2230 UINT64_C(224395264), // XVSHUF_B
2231 UINT64_C(1971027968), // XVSHUF_D
2232 UINT64_C(1970962432), // XVSHUF_H
2233 UINT64_C(1970995200), // XVSHUF_W
2234 UINT64_C(1965948928), // XVSIGNCOV_B
2235 UINT64_C(1966047232), // XVSIGNCOV_D
2236 UINT64_C(1965981696), // XVSIGNCOV_H
2237 UINT64_C(1966014464), // XVSIGNCOV_W
2238 UINT64_C(1988231168), // XVSLEI_B
2239 UINT64_C(1988362240), // XVSLEI_BU
2240 UINT64_C(1988329472), // XVSLEI_D
2241 UINT64_C(1988460544), // XVSLEI_DU
2242 UINT64_C(1988263936), // XVSLEI_H
2243 UINT64_C(1988395008), // XVSLEI_HU
2244 UINT64_C(1988296704), // XVSLEI_W
2245 UINT64_C(1988427776), // XVSLEI_WU
2246 UINT64_C(1946288128), // XVSLE_B
2247 UINT64_C(1946419200), // XVSLE_BU
2248 UINT64_C(1946386432), // XVSLE_D
2249 UINT64_C(1946517504), // XVSLE_DU
2250 UINT64_C(1946320896), // XVSLE_H
2251 UINT64_C(1946451968), // XVSLE_HU
2252 UINT64_C(1946353664), // XVSLE_W
2253 UINT64_C(1946484736), // XVSLE_WU
2254 UINT64_C(1999380480), // XVSLLI_B
2255 UINT64_C(1999437824), // XVSLLI_D
2256 UINT64_C(1999388672), // XVSLLI_H
2257 UINT64_C(1999405056), // XVSLLI_W
2258 UINT64_C(1997307904), // XVSLLWIL_DU_WU
2259 UINT64_C(1997045760), // XVSLLWIL_D_W
2260 UINT64_C(1997283328), // XVSLLWIL_HU_BU
2261 UINT64_C(1997021184), // XVSLLWIL_H_B
2262 UINT64_C(1997291520), // XVSLLWIL_WU_HU
2263 UINT64_C(1997029376), // XVSLLWIL_W_H
2264 UINT64_C(1961361408), // XVSLL_B
2265 UINT64_C(1961459712), // XVSLL_D
2266 UINT64_C(1961394176), // XVSLL_H
2267 UINT64_C(1961426944), // XVSLL_W
2268 UINT64_C(1988493312), // XVSLTI_B
2269 UINT64_C(1988624384), // XVSLTI_BU
2270 UINT64_C(1988591616), // XVSLTI_D
2271 UINT64_C(1988722688), // XVSLTI_DU
2272 UINT64_C(1988526080), // XVSLTI_H
2273 UINT64_C(1988657152), // XVSLTI_HU
2274 UINT64_C(1988558848), // XVSLTI_W
2275 UINT64_C(1988689920), // XVSLTI_WU
2276 UINT64_C(1946550272), // XVSLT_B
2277 UINT64_C(1946681344), // XVSLT_BU
2278 UINT64_C(1946648576), // XVSLT_D
2279 UINT64_C(1946779648), // XVSLT_DU
2280 UINT64_C(1946583040), // XVSLT_H
2281 UINT64_C(1946714112), // XVSLT_HU
2282 UINT64_C(1946615808), // XVSLT_W
2283 UINT64_C(1946746880), // XVSLT_WU
2284 UINT64_C(1999904768), // XVSRAI_B
2285 UINT64_C(1999962112), // XVSRAI_D
2286 UINT64_C(1999912960), // XVSRAI_H
2287 UINT64_C(1999929344), // XVSRAI_W
2288 UINT64_C(2002272256), // XVSRANI_B_H
2289 UINT64_C(2002386944), // XVSRANI_D_Q
2290 UINT64_C(2002288640), // XVSRANI_H_W
2291 UINT64_C(2002321408), // XVSRANI_W_D
2292 UINT64_C(1962311680), // XVSRAN_B_H
2293 UINT64_C(1962344448), // XVSRAN_H_W
2294 UINT64_C(1962377216), // XVSRAN_W_D
2295 UINT64_C(1990729728), // XVSRARI_B
2296 UINT64_C(1990787072), // XVSRARI_D
2297 UINT64_C(1990737920), // XVSRARI_H
2298 UINT64_C(1990754304), // XVSRARI_W
2299 UINT64_C(2002534400), // XVSRARNI_B_H
2300 UINT64_C(2002649088), // XVSRARNI_D_Q
2301 UINT64_C(2002550784), // XVSRARNI_H_W
2302 UINT64_C(2002583552), // XVSRARNI_W_D
2303 UINT64_C(1962573824), // XVSRARN_B_H
2304 UINT64_C(1962606592), // XVSRARN_H_W
2305 UINT64_C(1962639360), // XVSRARN_W_D
2306 UINT64_C(1962016768), // XVSRAR_B
2307 UINT64_C(1962115072), // XVSRAR_D
2308 UINT64_C(1962049536), // XVSRAR_H
2309 UINT64_C(1962082304), // XVSRAR_W
2310 UINT64_C(1961623552), // XVSRA_B
2311 UINT64_C(1961721856), // XVSRA_D
2312 UINT64_C(1961656320), // XVSRA_H
2313 UINT64_C(1961689088), // XVSRA_W
2314 UINT64_C(1999642624), // XVSRLI_B
2315 UINT64_C(1999699968), // XVSRLI_D
2316 UINT64_C(1999650816), // XVSRLI_H
2317 UINT64_C(1999667200), // XVSRLI_W
2318 UINT64_C(2000699392), // XVSRLNI_B_H
2319 UINT64_C(2000814080), // XVSRLNI_D_Q
2320 UINT64_C(2000715776), // XVSRLNI_H_W
2321 UINT64_C(2000748544), // XVSRLNI_W_D
2322 UINT64_C(1962180608), // XVSRLN_B_H
2323 UINT64_C(1962213376), // XVSRLN_H_W
2324 UINT64_C(1962246144), // XVSRLN_W_D
2325 UINT64_C(1990467584), // XVSRLRI_B
2326 UINT64_C(1990524928), // XVSRLRI_D
2327 UINT64_C(1990475776), // XVSRLRI_H
2328 UINT64_C(1990492160), // XVSRLRI_W
2329 UINT64_C(2000961536), // XVSRLRNI_B_H
2330 UINT64_C(2001076224), // XVSRLRNI_D_Q
2331 UINT64_C(2000977920), // XVSRLRNI_H_W
2332 UINT64_C(2001010688), // XVSRLRNI_W_D
2333 UINT64_C(1962442752), // XVSRLRN_B_H
2334 UINT64_C(1962475520), // XVSRLRN_H_W
2335 UINT64_C(1962508288), // XVSRLRN_W_D
2336 UINT64_C(1961885696), // XVSRLR_B
2337 UINT64_C(1961984000), // XVSRLR_D
2338 UINT64_C(1961918464), // XVSRLR_H
2339 UINT64_C(1961951232), // XVSRLR_W
2340 UINT64_C(1961492480), // XVSRL_B
2341 UINT64_C(1961590784), // XVSRL_D
2342 UINT64_C(1961525248), // XVSRL_H
2343 UINT64_C(1961558016), // XVSRL_W
2344 UINT64_C(2003058688), // XVSSRANI_BU_H
2345 UINT64_C(2002796544), // XVSSRANI_B_H
2346 UINT64_C(2003173376), // XVSSRANI_DU_Q
2347 UINT64_C(2002911232), // XVSSRANI_D_Q
2348 UINT64_C(2003075072), // XVSSRANI_HU_W
2349 UINT64_C(2002812928), // XVSSRANI_H_W
2350 UINT64_C(2003107840), // XVSSRANI_WU_D
2351 UINT64_C(2002845696), // XVSSRANI_W_D
2352 UINT64_C(1963360256), // XVSSRAN_BU_H
2353 UINT64_C(1962835968), // XVSSRAN_B_H
2354 UINT64_C(1963393024), // XVSSRAN_HU_W
2355 UINT64_C(1962868736), // XVSSRAN_H_W
2356 UINT64_C(1963425792), // XVSSRAN_WU_D
2357 UINT64_C(1962901504), // XVSSRAN_W_D
2358 UINT64_C(2003582976), // XVSSRARNI_BU_H
2359 UINT64_C(2003320832), // XVSSRARNI_B_H
2360 UINT64_C(2003697664), // XVSSRARNI_DU_Q
2361 UINT64_C(2003435520), // XVSSRARNI_D_Q
2362 UINT64_C(2003599360), // XVSSRARNI_HU_W
2363 UINT64_C(2003337216), // XVSSRARNI_H_W
2364 UINT64_C(2003632128), // XVSSRARNI_WU_D
2365 UINT64_C(2003369984), // XVSSRARNI_W_D
2366 UINT64_C(1963622400), // XVSSRARN_BU_H
2367 UINT64_C(1963098112), // XVSSRARN_B_H
2368 UINT64_C(1963655168), // XVSSRARN_HU_W
2369 UINT64_C(1963130880), // XVSSRARN_H_W
2370 UINT64_C(1963687936), // XVSSRARN_WU_D
2371 UINT64_C(1963163648), // XVSSRARN_W_D
2372 UINT64_C(2001485824), // XVSSRLNI_BU_H
2373 UINT64_C(2001223680), // XVSSRLNI_B_H
2374 UINT64_C(2001600512), // XVSSRLNI_DU_Q
2375 UINT64_C(2001338368), // XVSSRLNI_D_Q
2376 UINT64_C(2001502208), // XVSSRLNI_HU_W
2377 UINT64_C(2001240064), // XVSSRLNI_H_W
2378 UINT64_C(2001534976), // XVSSRLNI_WU_D
2379 UINT64_C(2001272832), // XVSSRLNI_W_D
2380 UINT64_C(1963229184), // XVSSRLN_BU_H
2381 UINT64_C(1962704896), // XVSSRLN_B_H
2382 UINT64_C(1963261952), // XVSSRLN_HU_W
2383 UINT64_C(1962737664), // XVSSRLN_H_W
2384 UINT64_C(1963294720), // XVSSRLN_WU_D
2385 UINT64_C(1962770432), // XVSSRLN_W_D
2386 UINT64_C(2002010112), // XVSSRLRNI_BU_H
2387 UINT64_C(2001747968), // XVSSRLRNI_B_H
2388 UINT64_C(2002124800), // XVSSRLRNI_DU_Q
2389 UINT64_C(2001862656), // XVSSRLRNI_D_Q
2390 UINT64_C(2002026496), // XVSSRLRNI_HU_W
2391 UINT64_C(2001764352), // XVSSRLRNI_H_W
2392 UINT64_C(2002059264), // XVSSRLRNI_WU_D
2393 UINT64_C(2001797120), // XVSSRLRNI_W_D
2394 UINT64_C(1963491328), // XVSSRLRN_BU_H
2395 UINT64_C(1962967040), // XVSSRLRN_B_H
2396 UINT64_C(1963524096), // XVSSRLRN_HU_W
2397 UINT64_C(1962999808), // XVSSRLRN_H_W
2398 UINT64_C(1963556864), // XVSSRLRN_WU_D
2399 UINT64_C(1963032576), // XVSSRLRN_W_D
2400 UINT64_C(1950875648), // XVSSUB_B
2401 UINT64_C(1951137792), // XVSSUB_BU
2402 UINT64_C(1950973952), // XVSSUB_D
2403 UINT64_C(1951236096), // XVSSUB_DU
2404 UINT64_C(1950908416), // XVSSUB_H
2405 UINT64_C(1951170560), // XVSSUB_HU
2406 UINT64_C(1950941184), // XVSSUB_W
2407 UINT64_C(1951203328), // XVSSUB_WU
2408 UINT64_C(750780416), // XVST
2409 UINT64_C(864026624), // XVSTELM_B
2410 UINT64_C(856686592), // XVSTELM_D
2411 UINT64_C(859832320), // XVSTELM_H
2412 UINT64_C(857735168), // XVSTELM_W
2413 UINT64_C(944504832), // XVSTX
2414 UINT64_C(1988886528), // XVSUBI_BU
2415 UINT64_C(1988984832), // XVSUBI_DU
2416 UINT64_C(1988919296), // XVSUBI_HU
2417 UINT64_C(1988952064), // XVSUBI_WU
2418 UINT64_C(1948319744), // XVSUBWEV_D_W
2419 UINT64_C(1949368320), // XVSUBWEV_D_WU
2420 UINT64_C(1948254208), // XVSUBWEV_H_B
2421 UINT64_C(1949302784), // XVSUBWEV_H_BU
2422 UINT64_C(1948352512), // XVSUBWEV_Q_D
2423 UINT64_C(1949401088), // XVSUBWEV_Q_DU
2424 UINT64_C(1948286976), // XVSUBWEV_W_H
2425 UINT64_C(1949335552), // XVSUBWEV_W_HU
2426 UINT64_C(1948581888), // XVSUBWOD_D_W
2427 UINT64_C(1949630464), // XVSUBWOD_D_WU
2428 UINT64_C(1948516352), // XVSUBWOD_H_B
2429 UINT64_C(1949564928), // XVSUBWOD_H_BU
2430 UINT64_C(1948614656), // XVSUBWOD_Q_D
2431 UINT64_C(1949663232), // XVSUBWOD_Q_DU
2432 UINT64_C(1948549120), // XVSUBWOD_W_H
2433 UINT64_C(1949597696), // XVSUBWOD_W_HU
2434 UINT64_C(1946943488), // XVSUB_B
2435 UINT64_C(1947041792), // XVSUB_D
2436 UINT64_C(1946976256), // XVSUB_H
2437 UINT64_C(1965916160), // XVSUB_Q
2438 UINT64_C(1947009024), // XVSUB_W
2439 UINT64_C(2010644480), // XVXORI_B
2440 UINT64_C(1965490176), // XVXOR_V
2441 UINT64_C(0)
2442 };
2443 const unsigned opcode = MI.getOpcode();
2444 uint64_t Value = InstBits[opcode];
2445 uint64_t op = 0;
2446 (void)op; // suppress warning
2447 switch (opcode) {
2448 case LoongArch::ERTN:
2449 case LoongArch::GTLBFLUSH:
2450 case LoongArch::TLBCLR:
2451 case LoongArch::TLBFILL:
2452 case LoongArch::TLBFLUSH:
2453 case LoongArch::TLBRD:
2454 case LoongArch::TLBSRCH:
2455 case LoongArch::TLBWR:
2456 case LoongArch::X86CLRTM:
2457 case LoongArch::X86DECTOP:
2458 case LoongArch::X86INCTOP:
2459 case LoongArch::X86SETTM: {
2460 break;
2461 }
2462 case LoongArch::FSEL_xD:
2463 case LoongArch::FSEL_xS: {
2464 // op: ca
2465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2466 op &= UINT64_C(7);
2467 op <<= 15;
2468 Value |= op;
2469 // op: fk
2470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2471 op &= UINT64_C(31);
2472 op <<= 10;
2473 Value |= op;
2474 // op: fj
2475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2476 op &= UINT64_C(31);
2477 op <<= 5;
2478 Value |= op;
2479 // op: fd
2480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2481 op &= UINT64_C(31);
2482 Value |= op;
2483 break;
2484 }
2485 case LoongArch::SET_CFR_FALSE:
2486 case LoongArch::SET_CFR_TRUE: {
2487 // op: cd
2488 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2489 op &= UINT64_C(7);
2490 Value |= op;
2491 break;
2492 }
2493 case LoongArch::CSRRD:
2494 case LoongArch::GCSRRD: {
2495 // op: csr_num
2496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2497 op &= UINT64_C(16383);
2498 op <<= 10;
2499 Value |= op;
2500 // op: rd
2501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2502 op &= UINT64_C(31);
2503 Value |= op;
2504 break;
2505 }
2506 case LoongArch::CSRWR:
2507 case LoongArch::GCSRWR: {
2508 // op: csr_num
2509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2510 op &= UINT64_C(16383);
2511 op <<= 10;
2512 Value |= op;
2513 // op: rd
2514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2515 op &= UINT64_C(31);
2516 Value |= op;
2517 break;
2518 }
2519 case LoongArch::CSRXCHG:
2520 case LoongArch::GCSRXCHG: {
2521 // op: csr_num
2522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2523 op &= UINT64_C(16383);
2524 op <<= 10;
2525 Value |= op;
2526 // op: rj
2527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2528 op &= UINT64_C(31);
2529 op <<= 5;
2530 Value |= op;
2531 // op: rd
2532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2533 op &= UINT64_C(31);
2534 Value |= op;
2535 break;
2536 }
2537 case LoongArch::FMADD_D:
2538 case LoongArch::FMADD_S:
2539 case LoongArch::FMSUB_D:
2540 case LoongArch::FMSUB_S:
2541 case LoongArch::FNMADD_D:
2542 case LoongArch::FNMADD_S:
2543 case LoongArch::FNMSUB_D:
2544 case LoongArch::FNMSUB_S: {
2545 // op: fa
2546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2547 op &= UINT64_C(31);
2548 op <<= 15;
2549 Value |= op;
2550 // op: fk
2551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2552 op &= UINT64_C(31);
2553 op <<= 10;
2554 Value |= op;
2555 // op: fj
2556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2557 op &= UINT64_C(31);
2558 op <<= 5;
2559 Value |= op;
2560 // op: fd
2561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2562 op &= UINT64_C(31);
2563 Value |= op;
2564 break;
2565 }
2566 case LoongArch::FABS_D:
2567 case LoongArch::FABS_S:
2568 case LoongArch::FCLASS_D:
2569 case LoongArch::FCLASS_S:
2570 case LoongArch::FCVT_D_S:
2571 case LoongArch::FCVT_LD_D:
2572 case LoongArch::FCVT_S_D:
2573 case LoongArch::FCVT_UD_D:
2574 case LoongArch::FFINT_D_L:
2575 case LoongArch::FFINT_D_W:
2576 case LoongArch::FFINT_S_L:
2577 case LoongArch::FFINT_S_W:
2578 case LoongArch::FLOGB_D:
2579 case LoongArch::FLOGB_S:
2580 case LoongArch::FNEG_D:
2581 case LoongArch::FNEG_S:
2582 case LoongArch::FRECIPE_D:
2583 case LoongArch::FRECIPE_S:
2584 case LoongArch::FRECIP_D:
2585 case LoongArch::FRECIP_S:
2586 case LoongArch::FRINT_D:
2587 case LoongArch::FRINT_S:
2588 case LoongArch::FRSQRTE_D:
2589 case LoongArch::FRSQRTE_S:
2590 case LoongArch::FRSQRT_D:
2591 case LoongArch::FRSQRT_S:
2592 case LoongArch::FSQRT_D:
2593 case LoongArch::FSQRT_S:
2594 case LoongArch::FTINTRM_L_D:
2595 case LoongArch::FTINTRM_L_S:
2596 case LoongArch::FTINTRM_W_D:
2597 case LoongArch::FTINTRM_W_S:
2598 case LoongArch::FTINTRNE_L_D:
2599 case LoongArch::FTINTRNE_L_S:
2600 case LoongArch::FTINTRNE_W_D:
2601 case LoongArch::FTINTRNE_W_S:
2602 case LoongArch::FTINTRP_L_D:
2603 case LoongArch::FTINTRP_L_S:
2604 case LoongArch::FTINTRP_W_D:
2605 case LoongArch::FTINTRP_W_S:
2606 case LoongArch::FTINTRZ_L_D:
2607 case LoongArch::FTINTRZ_L_S:
2608 case LoongArch::FTINTRZ_W_D:
2609 case LoongArch::FTINTRZ_W_S:
2610 case LoongArch::FTINT_L_D:
2611 case LoongArch::FTINT_L_S:
2612 case LoongArch::FTINT_W_D:
2613 case LoongArch::FTINT_W_S: {
2614 // op: fj
2615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2616 op &= UINT64_C(31);
2617 op <<= 5;
2618 Value |= op;
2619 // op: fd
2620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2621 op &= UINT64_C(31);
2622 Value |= op;
2623 break;
2624 }
2625 case LoongArch::FCMP_CAF_D:
2626 case LoongArch::FCMP_CAF_S:
2627 case LoongArch::FCMP_CEQ_D:
2628 case LoongArch::FCMP_CEQ_S:
2629 case LoongArch::FCMP_CLE_D:
2630 case LoongArch::FCMP_CLE_S:
2631 case LoongArch::FCMP_CLT_D:
2632 case LoongArch::FCMP_CLT_S:
2633 case LoongArch::FCMP_CNE_D:
2634 case LoongArch::FCMP_CNE_S:
2635 case LoongArch::FCMP_COR_D:
2636 case LoongArch::FCMP_COR_S:
2637 case LoongArch::FCMP_CUEQ_D:
2638 case LoongArch::FCMP_CUEQ_S:
2639 case LoongArch::FCMP_CULE_D:
2640 case LoongArch::FCMP_CULE_S:
2641 case LoongArch::FCMP_CULT_D:
2642 case LoongArch::FCMP_CULT_S:
2643 case LoongArch::FCMP_CUNE_D:
2644 case LoongArch::FCMP_CUNE_S:
2645 case LoongArch::FCMP_CUN_D:
2646 case LoongArch::FCMP_CUN_S:
2647 case LoongArch::FCMP_SAF_D:
2648 case LoongArch::FCMP_SAF_S:
2649 case LoongArch::FCMP_SEQ_D:
2650 case LoongArch::FCMP_SEQ_S:
2651 case LoongArch::FCMP_SLE_D:
2652 case LoongArch::FCMP_SLE_S:
2653 case LoongArch::FCMP_SLT_D:
2654 case LoongArch::FCMP_SLT_S:
2655 case LoongArch::FCMP_SNE_D:
2656 case LoongArch::FCMP_SNE_S:
2657 case LoongArch::FCMP_SOR_D:
2658 case LoongArch::FCMP_SOR_S:
2659 case LoongArch::FCMP_SUEQ_D:
2660 case LoongArch::FCMP_SUEQ_S:
2661 case LoongArch::FCMP_SULE_D:
2662 case LoongArch::FCMP_SULE_S:
2663 case LoongArch::FCMP_SULT_D:
2664 case LoongArch::FCMP_SULT_S:
2665 case LoongArch::FCMP_SUNE_D:
2666 case LoongArch::FCMP_SUNE_S:
2667 case LoongArch::FCMP_SUN_D:
2668 case LoongArch::FCMP_SUN_S: {
2669 // op: fk
2670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2671 op &= UINT64_C(31);
2672 op <<= 10;
2673 Value |= op;
2674 // op: fj
2675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2676 op &= UINT64_C(31);
2677 op <<= 5;
2678 Value |= op;
2679 // op: cd
2680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2681 op &= UINT64_C(7);
2682 Value |= op;
2683 break;
2684 }
2685 case LoongArch::FADD_D:
2686 case LoongArch::FADD_S:
2687 case LoongArch::FCOPYSIGN_D:
2688 case LoongArch::FCOPYSIGN_S:
2689 case LoongArch::FCVT_D_LD:
2690 case LoongArch::FDIV_D:
2691 case LoongArch::FDIV_S:
2692 case LoongArch::FMAXA_D:
2693 case LoongArch::FMAXA_S:
2694 case LoongArch::FMAX_D:
2695 case LoongArch::FMAX_S:
2696 case LoongArch::FMINA_D:
2697 case LoongArch::FMINA_S:
2698 case LoongArch::FMIN_D:
2699 case LoongArch::FMIN_S:
2700 case LoongArch::FMUL_D:
2701 case LoongArch::FMUL_S:
2702 case LoongArch::FSCALEB_D:
2703 case LoongArch::FSCALEB_S:
2704 case LoongArch::FSUB_D:
2705 case LoongArch::FSUB_S: {
2706 // op: fk
2707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2708 op &= UINT64_C(31);
2709 op <<= 10;
2710 Value |= op;
2711 // op: fj
2712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2713 op &= UINT64_C(31);
2714 op <<= 5;
2715 Value |= op;
2716 // op: fd
2717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2718 op &= UINT64_C(31);
2719 Value |= op;
2720 break;
2721 }
2722 case LoongArch::VPICKVE2GR_D:
2723 case LoongArch::VPICKVE2GR_DU: {
2724 // op: imm1
2725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2726 op &= UINT64_C(1);
2727 op <<= 10;
2728 Value |= op;
2729 // op: vj
2730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2731 op &= UINT64_C(31);
2732 op <<= 5;
2733 Value |= op;
2734 // op: rd
2735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2736 op &= UINT64_C(31);
2737 Value |= op;
2738 break;
2739 }
2740 case LoongArch::VREPLVEI_D: {
2741 // op: imm1
2742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2743 op &= UINT64_C(1);
2744 op <<= 10;
2745 Value |= op;
2746 // op: vj
2747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2748 op &= UINT64_C(31);
2749 op <<= 5;
2750 Value |= op;
2751 // op: vd
2752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2753 op &= UINT64_C(31);
2754 Value |= op;
2755 break;
2756 }
2757 case LoongArch::XVREPL128VEI_D: {
2758 // op: imm1
2759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2760 op &= UINT64_C(1);
2761 op <<= 10;
2762 Value |= op;
2763 // op: xj
2764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2765 op &= UINT64_C(31);
2766 op <<= 5;
2767 Value |= op;
2768 // op: xd
2769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2770 op &= UINT64_C(31);
2771 Value |= op;
2772 break;
2773 }
2774 case LoongArch::VINSGR2VR_D: {
2775 // op: imm1
2776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2777 op &= UINT64_C(1);
2778 op <<= 10;
2779 Value |= op;
2780 // op: rj
2781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2782 op &= UINT64_C(31);
2783 op <<= 5;
2784 Value |= op;
2785 // op: vd
2786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2787 op &= UINT64_C(31);
2788 Value |= op;
2789 break;
2790 }
2791 case LoongArch::VSTELM_D: {
2792 // op: imm1
2793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2794 op &= UINT64_C(1);
2795 op <<= 18;
2796 Value |= op;
2797 // op: imm8
2798 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
2799 op &= UINT64_C(255);
2800 op <<= 10;
2801 Value |= op;
2802 // op: rj
2803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2804 op &= UINT64_C(31);
2805 op <<= 5;
2806 Value |= op;
2807 // op: vd
2808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2809 op &= UINT64_C(31);
2810 Value |= op;
2811 break;
2812 }
2813 case LoongArch::VLDREPL_W: {
2814 // op: imm10
2815 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
2816 op &= UINT64_C(1023);
2817 op <<= 10;
2818 Value |= op;
2819 // op: rj
2820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2821 op &= UINT64_C(31);
2822 op <<= 5;
2823 Value |= op;
2824 // op: vd
2825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2826 op &= UINT64_C(31);
2827 Value |= op;
2828 break;
2829 }
2830 case LoongArch::XVLDREPL_W: {
2831 // op: imm10
2832 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
2833 op &= UINT64_C(1023);
2834 op <<= 10;
2835 Value |= op;
2836 // op: rj
2837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2838 op &= UINT64_C(31);
2839 op <<= 5;
2840 Value |= op;
2841 // op: xd
2842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2843 op &= UINT64_C(31);
2844 Value |= op;
2845 break;
2846 }
2847 case LoongArch::VLDREPL_H: {
2848 // op: imm11
2849 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
2850 op &= UINT64_C(2047);
2851 op <<= 10;
2852 Value |= op;
2853 // op: rj
2854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2855 op &= UINT64_C(31);
2856 op <<= 5;
2857 Value |= op;
2858 // op: vd
2859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2860 op &= UINT64_C(31);
2861 Value |= op;
2862 break;
2863 }
2864 case LoongArch::XVLDREPL_H: {
2865 // op: imm11
2866 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
2867 op &= UINT64_C(2047);
2868 op <<= 10;
2869 Value |= op;
2870 // op: rj
2871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2872 op &= UINT64_C(31);
2873 op <<= 5;
2874 Value |= op;
2875 // op: xd
2876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2877 op &= UINT64_C(31);
2878 Value |= op;
2879 break;
2880 }
2881 case LoongArch::FLD_D:
2882 case LoongArch::FLD_S:
2883 case LoongArch::FST_D:
2884 case LoongArch::FST_S: {
2885 // op: imm12
2886 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2887 op &= UINT64_C(4095);
2888 op <<= 10;
2889 Value |= op;
2890 // op: rj
2891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2892 op &= UINT64_C(31);
2893 op <<= 5;
2894 Value |= op;
2895 // op: fd
2896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2897 op &= UINT64_C(31);
2898 Value |= op;
2899 break;
2900 }
2901 case LoongArch::PRELD: {
2902 // op: imm12
2903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2904 op &= UINT64_C(4095);
2905 op <<= 10;
2906 Value |= op;
2907 // op: rj
2908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2909 op &= UINT64_C(31);
2910 op <<= 5;
2911 Value |= op;
2912 // op: imm5
2913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2914 op &= UINT64_C(31);
2915 Value |= op;
2916 break;
2917 }
2918 case LoongArch::CACOP: {
2919 // op: imm12
2920 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2921 op &= UINT64_C(4095);
2922 op <<= 10;
2923 Value |= op;
2924 // op: rj
2925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2926 op &= UINT64_C(31);
2927 op <<= 5;
2928 Value |= op;
2929 // op: op
2930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2931 op &= UINT64_C(31);
2932 Value |= op;
2933 break;
2934 }
2935 case LoongArch::ADDI_D:
2936 case LoongArch::ADDI_W:
2937 case LoongArch::ANDI:
2938 case LoongArch::LDL_D:
2939 case LoongArch::LDL_W:
2940 case LoongArch::LDR_D:
2941 case LoongArch::LDR_W:
2942 case LoongArch::LD_B:
2943 case LoongArch::LD_BU:
2944 case LoongArch::LD_D:
2945 case LoongArch::LD_H:
2946 case LoongArch::LD_HU:
2947 case LoongArch::LD_W:
2948 case LoongArch::LD_WU:
2949 case LoongArch::LU52I_D:
2950 case LoongArch::ORI:
2951 case LoongArch::SLTI:
2952 case LoongArch::SLTUI:
2953 case LoongArch::STL_D:
2954 case LoongArch::STL_W:
2955 case LoongArch::STR_D:
2956 case LoongArch::STR_W:
2957 case LoongArch::ST_B:
2958 case LoongArch::ST_D:
2959 case LoongArch::ST_H:
2960 case LoongArch::ST_W:
2961 case LoongArch::XORI: {
2962 // op: imm12
2963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2964 op &= UINT64_C(4095);
2965 op <<= 10;
2966 Value |= op;
2967 // op: rj
2968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2969 op &= UINT64_C(31);
2970 op <<= 5;
2971 Value |= op;
2972 // op: rd
2973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2974 op &= UINT64_C(31);
2975 Value |= op;
2976 break;
2977 }
2978 case LoongArch::VLD:
2979 case LoongArch::VLDREPL_B:
2980 case LoongArch::VST: {
2981 // op: imm12
2982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2983 op &= UINT64_C(4095);
2984 op <<= 10;
2985 Value |= op;
2986 // op: rj
2987 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2988 op &= UINT64_C(31);
2989 op <<= 5;
2990 Value |= op;
2991 // op: vd
2992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2993 op &= UINT64_C(31);
2994 Value |= op;
2995 break;
2996 }
2997 case LoongArch::XVLD:
2998 case LoongArch::XVLDREPL_B:
2999 case LoongArch::XVST: {
3000 // op: imm12
3001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3002 op &= UINT64_C(4095);
3003 op <<= 10;
3004 Value |= op;
3005 // op: rj
3006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3007 op &= UINT64_C(31);
3008 op <<= 5;
3009 Value |= op;
3010 // op: xd
3011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3012 op &= UINT64_C(31);
3013 Value |= op;
3014 break;
3015 }
3016 case LoongArch::VLDI: {
3017 // op: imm13
3018 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3019 op &= UINT64_C(8191);
3020 op <<= 5;
3021 Value |= op;
3022 // op: vd
3023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3024 op &= UINT64_C(31);
3025 Value |= op;
3026 break;
3027 }
3028 case LoongArch::XVLDI: {
3029 // op: imm13
3030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3031 op &= UINT64_C(8191);
3032 op <<= 5;
3033 Value |= op;
3034 // op: xd
3035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3036 op &= UINT64_C(31);
3037 Value |= op;
3038 break;
3039 }
3040 case LoongArch::LDPTR_D:
3041 case LoongArch::LDPTR_W:
3042 case LoongArch::LL_D:
3043 case LoongArch::LL_W:
3044 case LoongArch::STPTR_D:
3045 case LoongArch::STPTR_W: {
3046 // op: imm14
3047 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3048 op &= UINT64_C(16383);
3049 op <<= 10;
3050 Value |= op;
3051 // op: rj
3052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3053 op &= UINT64_C(31);
3054 op <<= 5;
3055 Value |= op;
3056 // op: rd
3057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3058 op &= UINT64_C(31);
3059 Value |= op;
3060 break;
3061 }
3062 case LoongArch::SC_D:
3063 case LoongArch::SC_W: {
3064 // op: imm14
3065 op = getImmOpValueAsr<2>(MI, OpNo: 3, Fixups, STI);
3066 op &= UINT64_C(16383);
3067 op <<= 10;
3068 Value |= op;
3069 // op: rj
3070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3071 op &= UINT64_C(31);
3072 op <<= 5;
3073 Value |= op;
3074 // op: rd
3075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3076 op &= UINT64_C(31);
3077 Value |= op;
3078 break;
3079 }
3080 case LoongArch::BREAK:
3081 case LoongArch::DBAR:
3082 case LoongArch::DBCL:
3083 case LoongArch::HVCL:
3084 case LoongArch::IBAR:
3085 case LoongArch::IDLE:
3086 case LoongArch::SYSCALL: {
3087 // op: imm15
3088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3089 op &= UINT64_C(32767);
3090 Value |= op;
3091 break;
3092 }
3093 case LoongArch::BEQ:
3094 case LoongArch::BGE:
3095 case LoongArch::BGEU:
3096 case LoongArch::BLT:
3097 case LoongArch::BLTU:
3098 case LoongArch::BNE: {
3099 // op: imm16
3100 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3101 op &= UINT64_C(65535);
3102 op <<= 10;
3103 Value |= op;
3104 // op: rj
3105 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3106 op &= UINT64_C(31);
3107 op <<= 5;
3108 Value |= op;
3109 // op: rd
3110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3111 op &= UINT64_C(31);
3112 Value |= op;
3113 break;
3114 }
3115 case LoongArch::JIRL: {
3116 // op: imm16
3117 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3118 op &= UINT64_C(65535);
3119 op <<= 10;
3120 Value |= op;
3121 // op: rj
3122 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3123 op &= UINT64_C(31);
3124 op <<= 5;
3125 Value |= op;
3126 // op: rd
3127 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3128 op &= UINT64_C(31);
3129 Value |= op;
3130 break;
3131 }
3132 case LoongArch::ADDU16I_D: {
3133 // op: imm16
3134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3135 op &= UINT64_C(65535);
3136 op <<= 10;
3137 Value |= op;
3138 // op: rj
3139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3140 op &= UINT64_C(31);
3141 op <<= 5;
3142 Value |= op;
3143 // op: rd
3144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3145 op &= UINT64_C(31);
3146 Value |= op;
3147 break;
3148 }
3149 case LoongArch::ALSL_D:
3150 case LoongArch::ALSL_W:
3151 case LoongArch::ALSL_WU: {
3152 // op: imm2
3153 op = getImmOpValueSub1(MI, OpNo: 3, Fixups, STI);
3154 op &= UINT64_C(3);
3155 op <<= 15;
3156 Value |= op;
3157 // op: rk
3158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3159 op &= UINT64_C(31);
3160 op <<= 10;
3161 Value |= op;
3162 // op: rj
3163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3164 op &= UINT64_C(31);
3165 op <<= 5;
3166 Value |= op;
3167 // op: rd
3168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3169 op &= UINT64_C(31);
3170 Value |= op;
3171 break;
3172 }
3173 case LoongArch::VPICKVE2GR_W:
3174 case LoongArch::VPICKVE2GR_WU: {
3175 // op: imm2
3176 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3177 op &= UINT64_C(3);
3178 op <<= 10;
3179 Value |= op;
3180 // op: vj
3181 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3182 op &= UINT64_C(31);
3183 op <<= 5;
3184 Value |= op;
3185 // op: rd
3186 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3187 op &= UINT64_C(31);
3188 Value |= op;
3189 break;
3190 }
3191 case LoongArch::VREPLVEI_W: {
3192 // op: imm2
3193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3194 op &= UINT64_C(3);
3195 op <<= 10;
3196 Value |= op;
3197 // op: vj
3198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3199 op &= UINT64_C(31);
3200 op <<= 5;
3201 Value |= op;
3202 // op: vd
3203 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3204 op &= UINT64_C(31);
3205 Value |= op;
3206 break;
3207 }
3208 case LoongArch::XVPICKVE2GR_D:
3209 case LoongArch::XVPICKVE2GR_DU: {
3210 // op: imm2
3211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3212 op &= UINT64_C(3);
3213 op <<= 10;
3214 Value |= op;
3215 // op: xj
3216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3217 op &= UINT64_C(31);
3218 op <<= 5;
3219 Value |= op;
3220 // op: rd
3221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3222 op &= UINT64_C(31);
3223 Value |= op;
3224 break;
3225 }
3226 case LoongArch::XVPICKVE_D:
3227 case LoongArch::XVREPL128VEI_W: {
3228 // op: imm2
3229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3230 op &= UINT64_C(3);
3231 op <<= 10;
3232 Value |= op;
3233 // op: xj
3234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3235 op &= UINT64_C(31);
3236 op <<= 5;
3237 Value |= op;
3238 // op: xd
3239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3240 op &= UINT64_C(31);
3241 Value |= op;
3242 break;
3243 }
3244 case LoongArch::VINSGR2VR_W: {
3245 // op: imm2
3246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3247 op &= UINT64_C(3);
3248 op <<= 10;
3249 Value |= op;
3250 // op: rj
3251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3252 op &= UINT64_C(31);
3253 op <<= 5;
3254 Value |= op;
3255 // op: vd
3256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3257 op &= UINT64_C(31);
3258 Value |= op;
3259 break;
3260 }
3261 case LoongArch::XVINSGR2VR_D: {
3262 // op: imm2
3263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3264 op &= UINT64_C(3);
3265 op <<= 10;
3266 Value |= op;
3267 // op: rj
3268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3269 op &= UINT64_C(31);
3270 op <<= 5;
3271 Value |= op;
3272 // op: xd
3273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3274 op &= UINT64_C(31);
3275 Value |= op;
3276 break;
3277 }
3278 case LoongArch::XVINSVE0_D: {
3279 // op: imm2
3280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3281 op &= UINT64_C(3);
3282 op <<= 10;
3283 Value |= op;
3284 // op: xj
3285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3286 op &= UINT64_C(31);
3287 op <<= 5;
3288 Value |= op;
3289 // op: xd
3290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3291 op &= UINT64_C(31);
3292 Value |= op;
3293 break;
3294 }
3295 case LoongArch::BYTEPICK_W: {
3296 // op: imm2
3297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3298 op &= UINT64_C(3);
3299 op <<= 15;
3300 Value |= op;
3301 // op: rk
3302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3303 op &= UINT64_C(31);
3304 op <<= 10;
3305 Value |= op;
3306 // op: rj
3307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3308 op &= UINT64_C(31);
3309 op <<= 5;
3310 Value |= op;
3311 // op: rd
3312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3313 op &= UINT64_C(31);
3314 Value |= op;
3315 break;
3316 }
3317 case LoongArch::VSTELM_W: {
3318 // op: imm2
3319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3320 op &= UINT64_C(3);
3321 op <<= 18;
3322 Value |= op;
3323 // op: imm8
3324 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3325 op &= UINT64_C(255);
3326 op <<= 10;
3327 Value |= op;
3328 // op: rj
3329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3330 op &= UINT64_C(31);
3331 op <<= 5;
3332 Value |= op;
3333 // op: vd
3334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3335 op &= UINT64_C(31);
3336 Value |= op;
3337 break;
3338 }
3339 case LoongArch::XVSTELM_D: {
3340 // op: imm2
3341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3342 op &= UINT64_C(3);
3343 op <<= 18;
3344 Value |= op;
3345 // op: imm8
3346 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
3347 op &= UINT64_C(255);
3348 op <<= 10;
3349 Value |= op;
3350 // op: rj
3351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3352 op &= UINT64_C(31);
3353 op <<= 5;
3354 Value |= op;
3355 // op: xd
3356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3357 op &= UINT64_C(31);
3358 Value |= op;
3359 break;
3360 }
3361 case LoongArch::LU12I_W:
3362 case LoongArch::PCADDI:
3363 case LoongArch::PCADDU12I:
3364 case LoongArch::PCADDU18I:
3365 case LoongArch::PCALAU12I: {
3366 // op: imm20
3367 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3368 op &= UINT64_C(1048575);
3369 op <<= 5;
3370 Value |= op;
3371 // op: rd
3372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3373 op &= UINT64_C(31);
3374 Value |= op;
3375 break;
3376 }
3377 case LoongArch::LU32I_D: {
3378 // op: imm20
3379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3380 op &= UINT64_C(1048575);
3381 op <<= 5;
3382 Value |= op;
3383 // op: rd
3384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3385 op &= UINT64_C(31);
3386 Value |= op;
3387 break;
3388 }
3389 case LoongArch::JISCR0:
3390 case LoongArch::JISCR1: {
3391 // op: imm21
3392 op = getImmOpValueAsr<2>(MI, OpNo: 0, Fixups, STI);
3393 Value |= (op & UINT64_C(65535)) << 10;
3394 Value |= (op & UINT64_C(2031616)) >> 16;
3395 break;
3396 }
3397 case LoongArch::BCEQZ:
3398 case LoongArch::BCNEZ: {
3399 // op: imm21
3400 op = getImmOpValueAsr<2>(MI, OpNo: 1, Fixups, STI);
3401 Value |= (op & UINT64_C(65535)) << 10;
3402 Value |= (op & UINT64_C(2031616)) >> 16;
3403 // op: cj
3404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3405 op &= UINT64_C(7);
3406 op <<= 5;
3407 Value |= op;
3408 break;
3409 }
3410 case LoongArch::BEQZ:
3411 case LoongArch::BNEZ: {
3412 // op: imm21
3413 op = getImmOpValueAsr<2>(MI, OpNo: 1, Fixups, STI);
3414 Value |= (op & UINT64_C(65535)) << 10;
3415 Value |= (op & UINT64_C(2031616)) >> 16;
3416 // op: rj
3417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3418 op &= UINT64_C(31);
3419 op <<= 5;
3420 Value |= op;
3421 break;
3422 }
3423 case LoongArch::B:
3424 case LoongArch::BL: {
3425 // op: imm26
3426 op = getImmOpValueAsr<2>(MI, OpNo: 0, Fixups, STI);
3427 Value |= (op & UINT64_C(65535)) << 10;
3428 Value |= (op & UINT64_C(67043328)) >> 16;
3429 break;
3430 }
3431 case LoongArch::X86RCLI_B:
3432 case LoongArch::X86RCRI_B:
3433 case LoongArch::X86ROTLI_B:
3434 case LoongArch::X86ROTRI_B:
3435 case LoongArch::X86SLLI_B:
3436 case LoongArch::X86SRAI_B:
3437 case LoongArch::X86SRLI_B: {
3438 // op: imm3
3439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3440 op &= UINT64_C(7);
3441 op <<= 10;
3442 Value |= op;
3443 // op: rj
3444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3445 op &= UINT64_C(31);
3446 op <<= 5;
3447 Value |= op;
3448 break;
3449 }
3450 case LoongArch::RCRI_B:
3451 case LoongArch::ROTRI_B: {
3452 // op: imm3
3453 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3454 op &= UINT64_C(7);
3455 op <<= 10;
3456 Value |= op;
3457 // op: rj
3458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3459 op &= UINT64_C(31);
3460 op <<= 5;
3461 Value |= op;
3462 // op: rd
3463 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3464 op &= UINT64_C(31);
3465 Value |= op;
3466 break;
3467 }
3468 case LoongArch::VPICKVE2GR_H:
3469 case LoongArch::VPICKVE2GR_HU: {
3470 // op: imm3
3471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3472 op &= UINT64_C(7);
3473 op <<= 10;
3474 Value |= op;
3475 // op: vj
3476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3477 op &= UINT64_C(31);
3478 op <<= 5;
3479 Value |= op;
3480 // op: rd
3481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3482 op &= UINT64_C(31);
3483 Value |= op;
3484 break;
3485 }
3486 case LoongArch::VBITCLRI_B:
3487 case LoongArch::VBITREVI_B:
3488 case LoongArch::VBITSETI_B:
3489 case LoongArch::VREPLVEI_H:
3490 case LoongArch::VROTRI_B:
3491 case LoongArch::VSAT_B:
3492 case LoongArch::VSAT_BU:
3493 case LoongArch::VSLLI_B:
3494 case LoongArch::VSLLWIL_HU_BU:
3495 case LoongArch::VSLLWIL_H_B:
3496 case LoongArch::VSRAI_B:
3497 case LoongArch::VSRARI_B:
3498 case LoongArch::VSRLI_B:
3499 case LoongArch::VSRLRI_B: {
3500 // op: imm3
3501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3502 op &= UINT64_C(7);
3503 op <<= 10;
3504 Value |= op;
3505 // op: vj
3506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3507 op &= UINT64_C(31);
3508 op <<= 5;
3509 Value |= op;
3510 // op: vd
3511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3512 op &= UINT64_C(31);
3513 Value |= op;
3514 break;
3515 }
3516 case LoongArch::XVPICKVE2GR_W:
3517 case LoongArch::XVPICKVE2GR_WU: {
3518 // op: imm3
3519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3520 op &= UINT64_C(7);
3521 op <<= 10;
3522 Value |= op;
3523 // op: xj
3524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3525 op &= UINT64_C(31);
3526 op <<= 5;
3527 Value |= op;
3528 // op: rd
3529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3530 op &= UINT64_C(31);
3531 Value |= op;
3532 break;
3533 }
3534 case LoongArch::XVBITCLRI_B:
3535 case LoongArch::XVBITREVI_B:
3536 case LoongArch::XVBITSETI_B:
3537 case LoongArch::XVPICKVE_W:
3538 case LoongArch::XVREPL128VEI_H:
3539 case LoongArch::XVROTRI_B:
3540 case LoongArch::XVSAT_B:
3541 case LoongArch::XVSAT_BU:
3542 case LoongArch::XVSLLI_B:
3543 case LoongArch::XVSLLWIL_HU_BU:
3544 case LoongArch::XVSLLWIL_H_B:
3545 case LoongArch::XVSRAI_B:
3546 case LoongArch::XVSRARI_B:
3547 case LoongArch::XVSRLI_B:
3548 case LoongArch::XVSRLRI_B: {
3549 // op: imm3
3550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3551 op &= UINT64_C(7);
3552 op <<= 10;
3553 Value |= op;
3554 // op: xj
3555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3556 op &= UINT64_C(31);
3557 op <<= 5;
3558 Value |= op;
3559 // op: xd
3560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3561 op &= UINT64_C(31);
3562 Value |= op;
3563 break;
3564 }
3565 case LoongArch::VINSGR2VR_H: {
3566 // op: imm3
3567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3568 op &= UINT64_C(7);
3569 op <<= 10;
3570 Value |= op;
3571 // op: rj
3572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3573 op &= UINT64_C(31);
3574 op <<= 5;
3575 Value |= op;
3576 // op: vd
3577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3578 op &= UINT64_C(31);
3579 Value |= op;
3580 break;
3581 }
3582 case LoongArch::XVINSGR2VR_W: {
3583 // op: imm3
3584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3585 op &= UINT64_C(7);
3586 op <<= 10;
3587 Value |= op;
3588 // op: rj
3589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3590 op &= UINT64_C(31);
3591 op <<= 5;
3592 Value |= op;
3593 // op: xd
3594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3595 op &= UINT64_C(31);
3596 Value |= op;
3597 break;
3598 }
3599 case LoongArch::XVINSVE0_W: {
3600 // op: imm3
3601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3602 op &= UINT64_C(7);
3603 op <<= 10;
3604 Value |= op;
3605 // op: xj
3606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3607 op &= UINT64_C(31);
3608 op <<= 5;
3609 Value |= op;
3610 // op: xd
3611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3612 op &= UINT64_C(31);
3613 Value |= op;
3614 break;
3615 }
3616 case LoongArch::BYTEPICK_D: {
3617 // op: imm3
3618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3619 op &= UINT64_C(7);
3620 op <<= 15;
3621 Value |= op;
3622 // op: rk
3623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3624 op &= UINT64_C(31);
3625 op <<= 10;
3626 Value |= op;
3627 // op: rj
3628 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3629 op &= UINT64_C(31);
3630 op <<= 5;
3631 Value |= op;
3632 // op: rd
3633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3634 op &= UINT64_C(31);
3635 Value |= op;
3636 break;
3637 }
3638 case LoongArch::VSTELM_H: {
3639 // op: imm3
3640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3641 op &= UINT64_C(7);
3642 op <<= 18;
3643 Value |= op;
3644 // op: imm8
3645 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
3646 op &= UINT64_C(255);
3647 op <<= 10;
3648 Value |= op;
3649 // op: rj
3650 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3651 op &= UINT64_C(31);
3652 op <<= 5;
3653 Value |= op;
3654 // op: vd
3655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3656 op &= UINT64_C(31);
3657 Value |= op;
3658 break;
3659 }
3660 case LoongArch::XVSTELM_W: {
3661 // op: imm3
3662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3663 op &= UINT64_C(7);
3664 op <<= 18;
3665 Value |= op;
3666 // op: imm8
3667 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3668 op &= UINT64_C(255);
3669 op <<= 10;
3670 Value |= op;
3671 // op: rj
3672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3673 op &= UINT64_C(31);
3674 op <<= 5;
3675 Value |= op;
3676 // op: xd
3677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3678 op &= UINT64_C(31);
3679 Value |= op;
3680 break;
3681 }
3682 case LoongArch::SETARMJ:
3683 case LoongArch::SETX86J: {
3684 // op: imm4
3685 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3686 op &= UINT64_C(15);
3687 op <<= 10;
3688 Value |= op;
3689 // op: rd
3690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3691 op &= UINT64_C(31);
3692 Value |= op;
3693 break;
3694 }
3695 case LoongArch::ARMMOV_D:
3696 case LoongArch::ARMMOV_W:
3697 case LoongArch::ARMNOT_W:
3698 case LoongArch::ARMRRX_W:
3699 case LoongArch::X86RCLI_H:
3700 case LoongArch::X86RCRI_H:
3701 case LoongArch::X86ROTLI_H:
3702 case LoongArch::X86ROTRI_H:
3703 case LoongArch::X86SLLI_H:
3704 case LoongArch::X86SRAI_H:
3705 case LoongArch::X86SRLI_H: {
3706 // op: imm4
3707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3708 op &= UINT64_C(15);
3709 op <<= 10;
3710 Value |= op;
3711 // op: rj
3712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3713 op &= UINT64_C(31);
3714 op <<= 5;
3715 Value |= op;
3716 break;
3717 }
3718 case LoongArch::ARMADC_W:
3719 case LoongArch::ARMADD_W:
3720 case LoongArch::ARMAND_W:
3721 case LoongArch::ARMOR_W:
3722 case LoongArch::ARMROTR_W:
3723 case LoongArch::ARMSBC_W:
3724 case LoongArch::ARMSLL_W:
3725 case LoongArch::ARMSRA_W:
3726 case LoongArch::ARMSRL_W:
3727 case LoongArch::ARMSUB_W:
3728 case LoongArch::ARMXOR_W: {
3729 // op: imm4
3730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3731 op &= UINT64_C(15);
3732 Value |= op;
3733 // op: rk
3734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3735 op &= UINT64_C(31);
3736 op <<= 10;
3737 Value |= op;
3738 // op: rj
3739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3740 op &= UINT64_C(31);
3741 op <<= 5;
3742 Value |= op;
3743 break;
3744 }
3745 case LoongArch::ARMMOVE:
3746 case LoongArch::RCRI_H:
3747 case LoongArch::ROTRI_H: {
3748 // op: imm4
3749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3750 op &= UINT64_C(15);
3751 op <<= 10;
3752 Value |= op;
3753 // op: rj
3754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3755 op &= UINT64_C(31);
3756 op <<= 5;
3757 Value |= op;
3758 // op: rd
3759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3760 op &= UINT64_C(31);
3761 Value |= op;
3762 break;
3763 }
3764 case LoongArch::VPICKVE2GR_B:
3765 case LoongArch::VPICKVE2GR_BU: {
3766 // op: imm4
3767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3768 op &= UINT64_C(15);
3769 op <<= 10;
3770 Value |= op;
3771 // op: vj
3772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3773 op &= UINT64_C(31);
3774 op <<= 5;
3775 Value |= op;
3776 // op: rd
3777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3778 op &= UINT64_C(31);
3779 Value |= op;
3780 break;
3781 }
3782 case LoongArch::VBITCLRI_H:
3783 case LoongArch::VBITREVI_H:
3784 case LoongArch::VBITSETI_H:
3785 case LoongArch::VREPLVEI_B:
3786 case LoongArch::VROTRI_H:
3787 case LoongArch::VSAT_H:
3788 case LoongArch::VSAT_HU:
3789 case LoongArch::VSLLI_H:
3790 case LoongArch::VSLLWIL_WU_HU:
3791 case LoongArch::VSLLWIL_W_H:
3792 case LoongArch::VSRAI_H:
3793 case LoongArch::VSRARI_H:
3794 case LoongArch::VSRLI_H:
3795 case LoongArch::VSRLRI_H: {
3796 // op: imm4
3797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3798 op &= UINT64_C(15);
3799 op <<= 10;
3800 Value |= op;
3801 // op: vj
3802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3803 op &= UINT64_C(31);
3804 op <<= 5;
3805 Value |= op;
3806 // op: vd
3807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3808 op &= UINT64_C(31);
3809 Value |= op;
3810 break;
3811 }
3812 case LoongArch::XVBITCLRI_H:
3813 case LoongArch::XVBITREVI_H:
3814 case LoongArch::XVBITSETI_H:
3815 case LoongArch::XVREPL128VEI_B:
3816 case LoongArch::XVROTRI_H:
3817 case LoongArch::XVSAT_H:
3818 case LoongArch::XVSAT_HU:
3819 case LoongArch::XVSLLI_H:
3820 case LoongArch::XVSLLWIL_WU_HU:
3821 case LoongArch::XVSLLWIL_W_H:
3822 case LoongArch::XVSRAI_H:
3823 case LoongArch::XVSRARI_H:
3824 case LoongArch::XVSRLI_H:
3825 case LoongArch::XVSRLRI_H: {
3826 // op: imm4
3827 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3828 op &= UINT64_C(15);
3829 op <<= 10;
3830 Value |= op;
3831 // op: xj
3832 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3833 op &= UINT64_C(31);
3834 op <<= 5;
3835 Value |= op;
3836 // op: xd
3837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3838 op &= UINT64_C(31);
3839 Value |= op;
3840 break;
3841 }
3842 case LoongArch::VINSGR2VR_B: {
3843 // op: imm4
3844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3845 op &= UINT64_C(15);
3846 op <<= 10;
3847 Value |= op;
3848 // op: rj
3849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3850 op &= UINT64_C(31);
3851 op <<= 5;
3852 Value |= op;
3853 // op: vd
3854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3855 op &= UINT64_C(31);
3856 Value |= op;
3857 break;
3858 }
3859 case LoongArch::VSRANI_B_H:
3860 case LoongArch::VSRARNI_B_H:
3861 case LoongArch::VSRLNI_B_H:
3862 case LoongArch::VSRLRNI_B_H:
3863 case LoongArch::VSSRANI_BU_H:
3864 case LoongArch::VSSRANI_B_H:
3865 case LoongArch::VSSRARNI_BU_H:
3866 case LoongArch::VSSRARNI_B_H:
3867 case LoongArch::VSSRLNI_BU_H:
3868 case LoongArch::VSSRLNI_B_H:
3869 case LoongArch::VSSRLRNI_BU_H:
3870 case LoongArch::VSSRLRNI_B_H: {
3871 // op: imm4
3872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3873 op &= UINT64_C(15);
3874 op <<= 10;
3875 Value |= op;
3876 // op: vj
3877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3878 op &= UINT64_C(31);
3879 op <<= 5;
3880 Value |= op;
3881 // op: vd
3882 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3883 op &= UINT64_C(31);
3884 Value |= op;
3885 break;
3886 }
3887 case LoongArch::XVSRANI_B_H:
3888 case LoongArch::XVSRARNI_B_H:
3889 case LoongArch::XVSRLNI_B_H:
3890 case LoongArch::XVSRLRNI_B_H:
3891 case LoongArch::XVSSRANI_BU_H:
3892 case LoongArch::XVSSRANI_B_H:
3893 case LoongArch::XVSSRARNI_BU_H:
3894 case LoongArch::XVSSRARNI_B_H:
3895 case LoongArch::XVSSRLNI_BU_H:
3896 case LoongArch::XVSSRLNI_B_H:
3897 case LoongArch::XVSSRLRNI_BU_H:
3898 case LoongArch::XVSSRLRNI_B_H: {
3899 // op: imm4
3900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3901 op &= UINT64_C(15);
3902 op <<= 10;
3903 Value |= op;
3904 // op: xj
3905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3906 op &= UINT64_C(31);
3907 op <<= 5;
3908 Value |= op;
3909 // op: xd
3910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3911 op &= UINT64_C(31);
3912 Value |= op;
3913 break;
3914 }
3915 case LoongArch::XVSTELM_H: {
3916 // op: imm4
3917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3918 op &= UINT64_C(15);
3919 op <<= 18;
3920 Value |= op;
3921 // op: imm8
3922 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
3923 op &= UINT64_C(255);
3924 op <<= 10;
3925 Value |= op;
3926 // op: rj
3927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3928 op &= UINT64_C(31);
3929 op <<= 5;
3930 Value |= op;
3931 // op: xd
3932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3933 op &= UINT64_C(31);
3934 Value |= op;
3935 break;
3936 }
3937 case LoongArch::VSTELM_B: {
3938 // op: imm4
3939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3940 op &= UINT64_C(15);
3941 op <<= 18;
3942 Value |= op;
3943 // op: imm8
3944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3945 op &= UINT64_C(255);
3946 op <<= 10;
3947 Value |= op;
3948 // op: rj
3949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3950 op &= UINT64_C(31);
3951 op <<= 5;
3952 Value |= op;
3953 // op: vd
3954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3955 op &= UINT64_C(31);
3956 Value |= op;
3957 break;
3958 }
3959 case LoongArch::X86RCLI_W:
3960 case LoongArch::X86RCRI_W:
3961 case LoongArch::X86ROTLI_W:
3962 case LoongArch::X86ROTRI_W:
3963 case LoongArch::X86SLLI_W:
3964 case LoongArch::X86SRAI_W:
3965 case LoongArch::X86SRLI_W: {
3966 // op: imm5
3967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3968 op &= UINT64_C(31);
3969 op <<= 10;
3970 Value |= op;
3971 // op: rj
3972 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3973 op &= UINT64_C(31);
3974 op <<= 5;
3975 Value |= op;
3976 break;
3977 }
3978 case LoongArch::ARMROTRI_W:
3979 case LoongArch::ARMSLLI_W:
3980 case LoongArch::ARMSRAI_W:
3981 case LoongArch::ARMSRLI_W: {
3982 // op: imm5
3983 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3984 op &= UINT64_C(31);
3985 op <<= 10;
3986 Value |= op;
3987 // op: rj
3988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3989 op &= UINT64_C(31);
3990 op <<= 5;
3991 Value |= op;
3992 // op: imm4
3993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3994 op &= UINT64_C(15);
3995 Value |= op;
3996 break;
3997 }
3998 case LoongArch::ADDU12I_D:
3999 case LoongArch::ADDU12I_W:
4000 case LoongArch::RCRI_W:
4001 case LoongArch::ROTRI_W:
4002 case LoongArch::SLLI_W:
4003 case LoongArch::SRAI_W:
4004 case LoongArch::SRLI_W: {
4005 // op: imm5
4006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4007 op &= UINT64_C(31);
4008 op <<= 10;
4009 Value |= op;
4010 // op: rj
4011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4012 op &= UINT64_C(31);
4013 op <<= 5;
4014 Value |= op;
4015 // op: rd
4016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4017 op &= UINT64_C(31);
4018 Value |= op;
4019 break;
4020 }
4021 case LoongArch::VADDI_BU:
4022 case LoongArch::VADDI_DU:
4023 case LoongArch::VADDI_HU:
4024 case LoongArch::VADDI_WU:
4025 case LoongArch::VBITCLRI_W:
4026 case LoongArch::VBITREVI_W:
4027 case LoongArch::VBITSETI_W:
4028 case LoongArch::VBSLL_V:
4029 case LoongArch::VBSRL_V:
4030 case LoongArch::VMAXI_B:
4031 case LoongArch::VMAXI_BU:
4032 case LoongArch::VMAXI_D:
4033 case LoongArch::VMAXI_DU:
4034 case LoongArch::VMAXI_H:
4035 case LoongArch::VMAXI_HU:
4036 case LoongArch::VMAXI_W:
4037 case LoongArch::VMAXI_WU:
4038 case LoongArch::VMINI_B:
4039 case LoongArch::VMINI_BU:
4040 case LoongArch::VMINI_D:
4041 case LoongArch::VMINI_DU:
4042 case LoongArch::VMINI_H:
4043 case LoongArch::VMINI_HU:
4044 case LoongArch::VMINI_W:
4045 case LoongArch::VMINI_WU:
4046 case LoongArch::VROTRI_W:
4047 case LoongArch::VSAT_W:
4048 case LoongArch::VSAT_WU:
4049 case LoongArch::VSEQI_B:
4050 case LoongArch::VSEQI_D:
4051 case LoongArch::VSEQI_H:
4052 case LoongArch::VSEQI_W:
4053 case LoongArch::VSLEI_B:
4054 case LoongArch::VSLEI_BU:
4055 case LoongArch::VSLEI_D:
4056 case LoongArch::VSLEI_DU:
4057 case LoongArch::VSLEI_H:
4058 case LoongArch::VSLEI_HU:
4059 case LoongArch::VSLEI_W:
4060 case LoongArch::VSLEI_WU:
4061 case LoongArch::VSLLI_W:
4062 case LoongArch::VSLLWIL_DU_WU:
4063 case LoongArch::VSLLWIL_D_W:
4064 case LoongArch::VSLTI_B:
4065 case LoongArch::VSLTI_BU:
4066 case LoongArch::VSLTI_D:
4067 case LoongArch::VSLTI_DU:
4068 case LoongArch::VSLTI_H:
4069 case LoongArch::VSLTI_HU:
4070 case LoongArch::VSLTI_W:
4071 case LoongArch::VSLTI_WU:
4072 case LoongArch::VSRAI_W:
4073 case LoongArch::VSRARI_W:
4074 case LoongArch::VSRLI_W:
4075 case LoongArch::VSRLRI_W:
4076 case LoongArch::VSUBI_BU:
4077 case LoongArch::VSUBI_DU:
4078 case LoongArch::VSUBI_HU:
4079 case LoongArch::VSUBI_WU: {
4080 // op: imm5
4081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4082 op &= UINT64_C(31);
4083 op <<= 10;
4084 Value |= op;
4085 // op: vj
4086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4087 op &= UINT64_C(31);
4088 op <<= 5;
4089 Value |= op;
4090 // op: vd
4091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4092 op &= UINT64_C(31);
4093 Value |= op;
4094 break;
4095 }
4096 case LoongArch::XVADDI_BU:
4097 case LoongArch::XVADDI_DU:
4098 case LoongArch::XVADDI_HU:
4099 case LoongArch::XVADDI_WU:
4100 case LoongArch::XVBITCLRI_W:
4101 case LoongArch::XVBITREVI_W:
4102 case LoongArch::XVBITSETI_W:
4103 case LoongArch::XVBSLL_V:
4104 case LoongArch::XVBSRL_V:
4105 case LoongArch::XVHSELI_D:
4106 case LoongArch::XVMAXI_B:
4107 case LoongArch::XVMAXI_BU:
4108 case LoongArch::XVMAXI_D:
4109 case LoongArch::XVMAXI_DU:
4110 case LoongArch::XVMAXI_H:
4111 case LoongArch::XVMAXI_HU:
4112 case LoongArch::XVMAXI_W:
4113 case LoongArch::XVMAXI_WU:
4114 case LoongArch::XVMINI_B:
4115 case LoongArch::XVMINI_BU:
4116 case LoongArch::XVMINI_D:
4117 case LoongArch::XVMINI_DU:
4118 case LoongArch::XVMINI_H:
4119 case LoongArch::XVMINI_HU:
4120 case LoongArch::XVMINI_W:
4121 case LoongArch::XVMINI_WU:
4122 case LoongArch::XVROTRI_W:
4123 case LoongArch::XVSAT_W:
4124 case LoongArch::XVSAT_WU:
4125 case LoongArch::XVSEQI_B:
4126 case LoongArch::XVSEQI_D:
4127 case LoongArch::XVSEQI_H:
4128 case LoongArch::XVSEQI_W:
4129 case LoongArch::XVSLEI_B:
4130 case LoongArch::XVSLEI_BU:
4131 case LoongArch::XVSLEI_D:
4132 case LoongArch::XVSLEI_DU:
4133 case LoongArch::XVSLEI_H:
4134 case LoongArch::XVSLEI_HU:
4135 case LoongArch::XVSLEI_W:
4136 case LoongArch::XVSLEI_WU:
4137 case LoongArch::XVSLLI_W:
4138 case LoongArch::XVSLLWIL_DU_WU:
4139 case LoongArch::XVSLLWIL_D_W:
4140 case LoongArch::XVSLTI_B:
4141 case LoongArch::XVSLTI_BU:
4142 case LoongArch::XVSLTI_D:
4143 case LoongArch::XVSLTI_DU:
4144 case LoongArch::XVSLTI_H:
4145 case LoongArch::XVSLTI_HU:
4146 case LoongArch::XVSLTI_W:
4147 case LoongArch::XVSLTI_WU:
4148 case LoongArch::XVSRAI_W:
4149 case LoongArch::XVSRARI_W:
4150 case LoongArch::XVSRLI_W:
4151 case LoongArch::XVSRLRI_W:
4152 case LoongArch::XVSUBI_BU:
4153 case LoongArch::XVSUBI_DU:
4154 case LoongArch::XVSUBI_HU:
4155 case LoongArch::XVSUBI_WU: {
4156 // op: imm5
4157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4158 op &= UINT64_C(31);
4159 op <<= 10;
4160 Value |= op;
4161 // op: xj
4162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4163 op &= UINT64_C(31);
4164 op <<= 5;
4165 Value |= op;
4166 // op: xd
4167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4168 op &= UINT64_C(31);
4169 Value |= op;
4170 break;
4171 }
4172 case LoongArch::VFRSTPI_B:
4173 case LoongArch::VFRSTPI_H:
4174 case LoongArch::VSRANI_H_W:
4175 case LoongArch::VSRARNI_H_W:
4176 case LoongArch::VSRLNI_H_W:
4177 case LoongArch::VSRLRNI_H_W:
4178 case LoongArch::VSSRANI_HU_W:
4179 case LoongArch::VSSRANI_H_W:
4180 case LoongArch::VSSRARNI_HU_W:
4181 case LoongArch::VSSRARNI_H_W:
4182 case LoongArch::VSSRLNI_HU_W:
4183 case LoongArch::VSSRLNI_H_W:
4184 case LoongArch::VSSRLRNI_HU_W:
4185 case LoongArch::VSSRLRNI_H_W: {
4186 // op: imm5
4187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4188 op &= UINT64_C(31);
4189 op <<= 10;
4190 Value |= op;
4191 // op: vj
4192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4193 op &= UINT64_C(31);
4194 op <<= 5;
4195 Value |= op;
4196 // op: vd
4197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4198 op &= UINT64_C(31);
4199 Value |= op;
4200 break;
4201 }
4202 case LoongArch::XVFRSTPI_B:
4203 case LoongArch::XVFRSTPI_H:
4204 case LoongArch::XVSRANI_H_W:
4205 case LoongArch::XVSRARNI_H_W:
4206 case LoongArch::XVSRLNI_H_W:
4207 case LoongArch::XVSRLRNI_H_W:
4208 case LoongArch::XVSSRANI_HU_W:
4209 case LoongArch::XVSSRANI_H_W:
4210 case LoongArch::XVSSRARNI_HU_W:
4211 case LoongArch::XVSSRARNI_H_W:
4212 case LoongArch::XVSSRLNI_HU_W:
4213 case LoongArch::XVSSRLNI_H_W:
4214 case LoongArch::XVSSRLRNI_HU_W:
4215 case LoongArch::XVSSRLRNI_H_W: {
4216 // op: imm5
4217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4218 op &= UINT64_C(31);
4219 op <<= 10;
4220 Value |= op;
4221 // op: xj
4222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4223 op &= UINT64_C(31);
4224 op <<= 5;
4225 Value |= op;
4226 // op: xd
4227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4228 op &= UINT64_C(31);
4229 Value |= op;
4230 break;
4231 }
4232 case LoongArch::XVSTELM_B: {
4233 // op: imm5
4234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4235 op &= UINT64_C(31);
4236 op <<= 18;
4237 Value |= op;
4238 // op: imm8
4239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4240 op &= UINT64_C(255);
4241 op <<= 10;
4242 Value |= op;
4243 // op: rj
4244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4245 op &= UINT64_C(31);
4246 op <<= 5;
4247 Value |= op;
4248 // op: xd
4249 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4250 op &= UINT64_C(31);
4251 Value |= op;
4252 break;
4253 }
4254 case LoongArch::X86RCLI_D:
4255 case LoongArch::X86RCRI_D:
4256 case LoongArch::X86ROTLI_D:
4257 case LoongArch::X86ROTRI_D:
4258 case LoongArch::X86SLLI_D:
4259 case LoongArch::X86SRAI_D:
4260 case LoongArch::X86SRLI_D: {
4261 // op: imm6
4262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4263 op &= UINT64_C(63);
4264 op <<= 10;
4265 Value |= op;
4266 // op: rj
4267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4268 op &= UINT64_C(31);
4269 op <<= 5;
4270 Value |= op;
4271 break;
4272 }
4273 case LoongArch::RCRI_D:
4274 case LoongArch::ROTRI_D:
4275 case LoongArch::SLLI_D:
4276 case LoongArch::SRAI_D:
4277 case LoongArch::SRLI_D: {
4278 // op: imm6
4279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4280 op &= UINT64_C(63);
4281 op <<= 10;
4282 Value |= op;
4283 // op: rj
4284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4285 op &= UINT64_C(31);
4286 op <<= 5;
4287 Value |= op;
4288 // op: rd
4289 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4290 op &= UINT64_C(31);
4291 Value |= op;
4292 break;
4293 }
4294 case LoongArch::VBITCLRI_D:
4295 case LoongArch::VBITREVI_D:
4296 case LoongArch::VBITSETI_D:
4297 case LoongArch::VROTRI_D:
4298 case LoongArch::VSAT_D:
4299 case LoongArch::VSAT_DU:
4300 case LoongArch::VSLLI_D:
4301 case LoongArch::VSRAI_D:
4302 case LoongArch::VSRARI_D:
4303 case LoongArch::VSRLI_D:
4304 case LoongArch::VSRLRI_D: {
4305 // op: imm6
4306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4307 op &= UINT64_C(63);
4308 op <<= 10;
4309 Value |= op;
4310 // op: vj
4311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4312 op &= UINT64_C(31);
4313 op <<= 5;
4314 Value |= op;
4315 // op: vd
4316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4317 op &= UINT64_C(31);
4318 Value |= op;
4319 break;
4320 }
4321 case LoongArch::XVBITCLRI_D:
4322 case LoongArch::XVBITREVI_D:
4323 case LoongArch::XVBITSETI_D:
4324 case LoongArch::XVROTRI_D:
4325 case LoongArch::XVSAT_D:
4326 case LoongArch::XVSAT_DU:
4327 case LoongArch::XVSLLI_D:
4328 case LoongArch::XVSRAI_D:
4329 case LoongArch::XVSRARI_D:
4330 case LoongArch::XVSRLI_D:
4331 case LoongArch::XVSRLRI_D: {
4332 // op: imm6
4333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4334 op &= UINT64_C(63);
4335 op <<= 10;
4336 Value |= op;
4337 // op: xj
4338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4339 op &= UINT64_C(31);
4340 op <<= 5;
4341 Value |= op;
4342 // op: xd
4343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4344 op &= UINT64_C(31);
4345 Value |= op;
4346 break;
4347 }
4348 case LoongArch::VSRANI_W_D:
4349 case LoongArch::VSRARNI_W_D:
4350 case LoongArch::VSRLNI_W_D:
4351 case LoongArch::VSRLRNI_W_D:
4352 case LoongArch::VSSRANI_WU_D:
4353 case LoongArch::VSSRANI_W_D:
4354 case LoongArch::VSSRARNI_WU_D:
4355 case LoongArch::VSSRARNI_W_D:
4356 case LoongArch::VSSRLNI_WU_D:
4357 case LoongArch::VSSRLNI_W_D:
4358 case LoongArch::VSSRLRNI_WU_D:
4359 case LoongArch::VSSRLRNI_W_D: {
4360 // op: imm6
4361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4362 op &= UINT64_C(63);
4363 op <<= 10;
4364 Value |= op;
4365 // op: vj
4366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4367 op &= UINT64_C(31);
4368 op <<= 5;
4369 Value |= op;
4370 // op: vd
4371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4372 op &= UINT64_C(31);
4373 Value |= op;
4374 break;
4375 }
4376 case LoongArch::XVSRANI_W_D:
4377 case LoongArch::XVSRARNI_W_D:
4378 case LoongArch::XVSRLNI_W_D:
4379 case LoongArch::XVSRLRNI_W_D:
4380 case LoongArch::XVSSRANI_WU_D:
4381 case LoongArch::XVSSRANI_W_D:
4382 case LoongArch::XVSSRARNI_WU_D:
4383 case LoongArch::XVSSRARNI_W_D:
4384 case LoongArch::XVSSRLNI_WU_D:
4385 case LoongArch::XVSSRLNI_W_D:
4386 case LoongArch::XVSSRLRNI_WU_D:
4387 case LoongArch::XVSSRLRNI_W_D: {
4388 // op: imm6
4389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4390 op &= UINT64_C(63);
4391 op <<= 10;
4392 Value |= op;
4393 // op: xj
4394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4395 op &= UINT64_C(31);
4396 op <<= 5;
4397 Value |= op;
4398 // op: xd
4399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4400 op &= UINT64_C(31);
4401 Value |= op;
4402 break;
4403 }
4404 case LoongArch::VSRANI_D_Q:
4405 case LoongArch::VSRARNI_D_Q:
4406 case LoongArch::VSRLNI_D_Q:
4407 case LoongArch::VSRLRNI_D_Q:
4408 case LoongArch::VSSRANI_DU_Q:
4409 case LoongArch::VSSRANI_D_Q:
4410 case LoongArch::VSSRARNI_DU_Q:
4411 case LoongArch::VSSRARNI_D_Q:
4412 case LoongArch::VSSRLNI_DU_Q:
4413 case LoongArch::VSSRLNI_D_Q:
4414 case LoongArch::VSSRLRNI_DU_Q:
4415 case LoongArch::VSSRLRNI_D_Q: {
4416 // op: imm7
4417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4418 op &= UINT64_C(127);
4419 op <<= 10;
4420 Value |= op;
4421 // op: vj
4422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4423 op &= UINT64_C(31);
4424 op <<= 5;
4425 Value |= op;
4426 // op: vd
4427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4428 op &= UINT64_C(31);
4429 Value |= op;
4430 break;
4431 }
4432 case LoongArch::XVSRANI_D_Q:
4433 case LoongArch::XVSRARNI_D_Q:
4434 case LoongArch::XVSRLNI_D_Q:
4435 case LoongArch::XVSRLRNI_D_Q:
4436 case LoongArch::XVSSRANI_DU_Q:
4437 case LoongArch::XVSSRANI_D_Q:
4438 case LoongArch::XVSSRARNI_DU_Q:
4439 case LoongArch::XVSSRARNI_D_Q:
4440 case LoongArch::XVSSRLNI_DU_Q:
4441 case LoongArch::XVSSRLNI_D_Q:
4442 case LoongArch::XVSSRLRNI_DU_Q:
4443 case LoongArch::XVSSRLRNI_D_Q: {
4444 // op: imm7
4445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4446 op &= UINT64_C(127);
4447 op <<= 10;
4448 Value |= op;
4449 // op: xj
4450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4451 op &= UINT64_C(31);
4452 op <<= 5;
4453 Value |= op;
4454 // op: xd
4455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4456 op &= UINT64_C(31);
4457 Value |= op;
4458 break;
4459 }
4460 case LoongArch::ARMMFFLAG:
4461 case LoongArch::ARMMTFLAG:
4462 case LoongArch::X86MFFLAG:
4463 case LoongArch::X86MTFLAG: {
4464 // op: imm8
4465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4466 op &= UINT64_C(255);
4467 op <<= 10;
4468 Value |= op;
4469 // op: rd
4470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4471 op &= UINT64_C(31);
4472 Value |= op;
4473 break;
4474 }
4475 case LoongArch::X86SETTAG: {
4476 // op: imm8
4477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4478 op &= UINT64_C(255);
4479 op <<= 10;
4480 Value |= op;
4481 // op: imm5
4482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4483 op &= UINT64_C(31);
4484 op <<= 5;
4485 Value |= op;
4486 // op: rd
4487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4488 op &= UINT64_C(31);
4489 Value |= op;
4490 break;
4491 }
4492 case LoongArch::LDDIR: {
4493 // op: imm8
4494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4495 op &= UINT64_C(255);
4496 op <<= 10;
4497 Value |= op;
4498 // op: rj
4499 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4500 op &= UINT64_C(31);
4501 op <<= 5;
4502 Value |= op;
4503 // op: rd
4504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4505 op &= UINT64_C(31);
4506 Value |= op;
4507 break;
4508 }
4509 case LoongArch::VANDI_B:
4510 case LoongArch::VNORI_B:
4511 case LoongArch::VORI_B:
4512 case LoongArch::VSHUF4I_B:
4513 case LoongArch::VSHUF4I_H:
4514 case LoongArch::VSHUF4I_W:
4515 case LoongArch::VXORI_B: {
4516 // op: imm8
4517 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4518 op &= UINT64_C(255);
4519 op <<= 10;
4520 Value |= op;
4521 // op: vj
4522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4523 op &= UINT64_C(31);
4524 op <<= 5;
4525 Value |= op;
4526 // op: vd
4527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4528 op &= UINT64_C(31);
4529 Value |= op;
4530 break;
4531 }
4532 case LoongArch::XVANDI_B:
4533 case LoongArch::XVNORI_B:
4534 case LoongArch::XVORI_B:
4535 case LoongArch::XVPERMI_D:
4536 case LoongArch::XVSHUF4I_B:
4537 case LoongArch::XVSHUF4I_H:
4538 case LoongArch::XVSHUF4I_W:
4539 case LoongArch::XVXORI_B: {
4540 // op: imm8
4541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4542 op &= UINT64_C(255);
4543 op <<= 10;
4544 Value |= op;
4545 // op: xj
4546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4547 op &= UINT64_C(31);
4548 op <<= 5;
4549 Value |= op;
4550 // op: xd
4551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4552 op &= UINT64_C(31);
4553 Value |= op;
4554 break;
4555 }
4556 case LoongArch::VBITSELI_B:
4557 case LoongArch::VEXTRINS_B:
4558 case LoongArch::VEXTRINS_D:
4559 case LoongArch::VEXTRINS_H:
4560 case LoongArch::VEXTRINS_W:
4561 case LoongArch::VPERMI_W:
4562 case LoongArch::VSHUF4I_D: {
4563 // op: imm8
4564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4565 op &= UINT64_C(255);
4566 op <<= 10;
4567 Value |= op;
4568 // op: vj
4569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4570 op &= UINT64_C(31);
4571 op <<= 5;
4572 Value |= op;
4573 // op: vd
4574 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4575 op &= UINT64_C(31);
4576 Value |= op;
4577 break;
4578 }
4579 case LoongArch::XVBITSELI_B:
4580 case LoongArch::XVEXTRINS_B:
4581 case LoongArch::XVEXTRINS_D:
4582 case LoongArch::XVEXTRINS_H:
4583 case LoongArch::XVEXTRINS_W:
4584 case LoongArch::XVPERMI_Q:
4585 case LoongArch::XVPERMI_W:
4586 case LoongArch::XVSHUF4I_D: {
4587 // op: imm8
4588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4589 op &= UINT64_C(255);
4590 op <<= 10;
4591 Value |= op;
4592 // op: xj
4593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4594 op &= UINT64_C(31);
4595 op <<= 5;
4596 Value |= op;
4597 // op: xd
4598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4599 op &= UINT64_C(31);
4600 Value |= op;
4601 break;
4602 }
4603 case LoongArch::VLDREPL_D: {
4604 // op: imm9
4605 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
4606 op &= UINT64_C(511);
4607 op <<= 10;
4608 Value |= op;
4609 // op: rj
4610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4611 op &= UINT64_C(31);
4612 op <<= 5;
4613 Value |= op;
4614 // op: vd
4615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4616 op &= UINT64_C(31);
4617 Value |= op;
4618 break;
4619 }
4620 case LoongArch::XVLDREPL_D: {
4621 // op: imm9
4622 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
4623 op &= UINT64_C(511);
4624 op <<= 10;
4625 Value |= op;
4626 // op: rj
4627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4628 op &= UINT64_C(31);
4629 op <<= 5;
4630 Value |= op;
4631 // op: xd
4632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4633 op &= UINT64_C(31);
4634 Value |= op;
4635 break;
4636 }
4637 case LoongArch::BSTRPICK_D: {
4638 // op: msbd
4639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4640 op &= UINT64_C(63);
4641 op <<= 16;
4642 Value |= op;
4643 // op: lsbd
4644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4645 op &= UINT64_C(63);
4646 op <<= 10;
4647 Value |= op;
4648 // op: rj
4649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4650 op &= UINT64_C(31);
4651 op <<= 5;
4652 Value |= op;
4653 // op: rd
4654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4655 op &= UINT64_C(31);
4656 Value |= op;
4657 break;
4658 }
4659 case LoongArch::BSTRINS_D: {
4660 // op: msbd
4661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4662 op &= UINT64_C(63);
4663 op <<= 16;
4664 Value |= op;
4665 // op: lsbd
4666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
4667 op &= UINT64_C(63);
4668 op <<= 10;
4669 Value |= op;
4670 // op: rj
4671 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4672 op &= UINT64_C(31);
4673 op <<= 5;
4674 Value |= op;
4675 // op: rd
4676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4677 op &= UINT64_C(31);
4678 Value |= op;
4679 break;
4680 }
4681 case LoongArch::BSTRPICK_W: {
4682 // op: msbw
4683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4684 op &= UINT64_C(31);
4685 op <<= 16;
4686 Value |= op;
4687 // op: lsbw
4688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4689 op &= UINT64_C(31);
4690 op <<= 10;
4691 Value |= op;
4692 // op: rj
4693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4694 op &= UINT64_C(31);
4695 op <<= 5;
4696 Value |= op;
4697 // op: rd
4698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4699 op &= UINT64_C(31);
4700 Value |= op;
4701 break;
4702 }
4703 case LoongArch::BSTRINS_W: {
4704 // op: msbw
4705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4706 op &= UINT64_C(31);
4707 op <<= 16;
4708 Value |= op;
4709 // op: lsbw
4710 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
4711 op &= UINT64_C(31);
4712 op <<= 10;
4713 Value |= op;
4714 // op: rj
4715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4716 op &= UINT64_C(31);
4717 op <<= 5;
4718 Value |= op;
4719 // op: rd
4720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4721 op &= UINT64_C(31);
4722 Value |= op;
4723 break;
4724 }
4725 case LoongArch::X86MTTOP: {
4726 // op: ptr
4727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4728 op &= UINT64_C(7);
4729 op <<= 5;
4730 Value |= op;
4731 break;
4732 }
4733 case LoongArch::X86MFTOP: {
4734 // op: rd
4735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4736 op &= UINT64_C(31);
4737 Value |= op;
4738 break;
4739 }
4740 case LoongArch::X86DEC_B:
4741 case LoongArch::X86DEC_D:
4742 case LoongArch::X86DEC_H:
4743 case LoongArch::X86DEC_W:
4744 case LoongArch::X86INC_B:
4745 case LoongArch::X86INC_D:
4746 case LoongArch::X86INC_H:
4747 case LoongArch::X86INC_W: {
4748 // op: rj
4749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4750 op &= UINT64_C(31);
4751 op <<= 5;
4752 Value |= op;
4753 break;
4754 }
4755 case LoongArch::BITREV_4B:
4756 case LoongArch::BITREV_8B:
4757 case LoongArch::BITREV_D:
4758 case LoongArch::BITREV_W:
4759 case LoongArch::CLO_D:
4760 case LoongArch::CLO_W:
4761 case LoongArch::CLZ_D:
4762 case LoongArch::CLZ_W:
4763 case LoongArch::CPUCFG:
4764 case LoongArch::CTO_D:
4765 case LoongArch::CTO_W:
4766 case LoongArch::CTZ_D:
4767 case LoongArch::CTZ_W:
4768 case LoongArch::EXT_W_B:
4769 case LoongArch::EXT_W_H:
4770 case LoongArch::IOCSRRD_B:
4771 case LoongArch::IOCSRRD_D:
4772 case LoongArch::IOCSRRD_H:
4773 case LoongArch::IOCSRRD_W:
4774 case LoongArch::IOCSRWR_B:
4775 case LoongArch::IOCSRWR_D:
4776 case LoongArch::IOCSRWR_H:
4777 case LoongArch::IOCSRWR_W:
4778 case LoongArch::LLACQ_D:
4779 case LoongArch::LLACQ_W:
4780 case LoongArch::RDTIMEH_W:
4781 case LoongArch::RDTIMEL_W:
4782 case LoongArch::RDTIME_D:
4783 case LoongArch::REVB_2H:
4784 case LoongArch::REVB_2W:
4785 case LoongArch::REVB_4H:
4786 case LoongArch::REVB_D:
4787 case LoongArch::REVH_2W:
4788 case LoongArch::REVH_D:
4789 case LoongArch::SETX86LOOPE:
4790 case LoongArch::SETX86LOOPNE: {
4791 // op: rj
4792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4793 op &= UINT64_C(31);
4794 op <<= 5;
4795 Value |= op;
4796 // op: rd
4797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4798 op &= UINT64_C(31);
4799 Value |= op;
4800 break;
4801 }
4802 case LoongArch::MOVGR2SCR: {
4803 // op: rj
4804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4805 op &= UINT64_C(31);
4806 op <<= 5;
4807 Value |= op;
4808 // op: sd
4809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4810 op &= UINT64_C(3);
4811 Value |= op;
4812 break;
4813 }
4814 case LoongArch::VREPLGR2VR_B:
4815 case LoongArch::VREPLGR2VR_D:
4816 case LoongArch::VREPLGR2VR_H:
4817 case LoongArch::VREPLGR2VR_W: {
4818 // op: rj
4819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4820 op &= UINT64_C(31);
4821 op <<= 5;
4822 Value |= op;
4823 // op: vd
4824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4825 op &= UINT64_C(31);
4826 Value |= op;
4827 break;
4828 }
4829 case LoongArch::XVREPLGR2VR_B:
4830 case LoongArch::XVREPLGR2VR_D:
4831 case LoongArch::XVREPLGR2VR_H:
4832 case LoongArch::XVREPLGR2VR_W: {
4833 // op: rj
4834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4835 op &= UINT64_C(31);
4836 op <<= 5;
4837 Value |= op;
4838 // op: xd
4839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4840 op &= UINT64_C(31);
4841 Value |= op;
4842 break;
4843 }
4844 case LoongArch::SCREL_D:
4845 case LoongArch::SCREL_W: {
4846 // op: rj
4847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4848 op &= UINT64_C(31);
4849 op <<= 5;
4850 Value |= op;
4851 // op: rd
4852 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4853 op &= UINT64_C(31);
4854 Value |= op;
4855 break;
4856 }
4857 case LoongArch::INVTLB: {
4858 // op: rk
4859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4860 op &= UINT64_C(31);
4861 op <<= 10;
4862 Value |= op;
4863 // op: rj
4864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4865 op &= UINT64_C(31);
4866 op <<= 5;
4867 Value |= op;
4868 // op: op
4869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4870 op &= UINT64_C(31);
4871 Value |= op;
4872 break;
4873 }
4874 case LoongArch::ASRTGT_D:
4875 case LoongArch::ASRTLE_D:
4876 case LoongArch::X86ADC_B:
4877 case LoongArch::X86ADC_D:
4878 case LoongArch::X86ADC_H:
4879 case LoongArch::X86ADC_W:
4880 case LoongArch::X86ADD_B:
4881 case LoongArch::X86ADD_D:
4882 case LoongArch::X86ADD_DU:
4883 case LoongArch::X86ADD_H:
4884 case LoongArch::X86ADD_W:
4885 case LoongArch::X86ADD_WU:
4886 case LoongArch::X86AND_B:
4887 case LoongArch::X86AND_D:
4888 case LoongArch::X86AND_H:
4889 case LoongArch::X86AND_W:
4890 case LoongArch::X86MUL_B:
4891 case LoongArch::X86MUL_BU:
4892 case LoongArch::X86MUL_D:
4893 case LoongArch::X86MUL_DU:
4894 case LoongArch::X86MUL_H:
4895 case LoongArch::X86MUL_HU:
4896 case LoongArch::X86MUL_W:
4897 case LoongArch::X86MUL_WU:
4898 case LoongArch::X86OR_B:
4899 case LoongArch::X86OR_D:
4900 case LoongArch::X86OR_H:
4901 case LoongArch::X86OR_W:
4902 case LoongArch::X86RCL_B:
4903 case LoongArch::X86RCL_D:
4904 case LoongArch::X86RCL_H:
4905 case LoongArch::X86RCL_W:
4906 case LoongArch::X86RCR_B:
4907 case LoongArch::X86RCR_D:
4908 case LoongArch::X86RCR_H:
4909 case LoongArch::X86RCR_W:
4910 case LoongArch::X86ROTL_B:
4911 case LoongArch::X86ROTL_D:
4912 case LoongArch::X86ROTL_H:
4913 case LoongArch::X86ROTL_W:
4914 case LoongArch::X86ROTR_B:
4915 case LoongArch::X86ROTR_D:
4916 case LoongArch::X86ROTR_H:
4917 case LoongArch::X86ROTR_W:
4918 case LoongArch::X86SBC_B:
4919 case LoongArch::X86SBC_D:
4920 case LoongArch::X86SBC_H:
4921 case LoongArch::X86SBC_W:
4922 case LoongArch::X86SLL_B:
4923 case LoongArch::X86SLL_D:
4924 case LoongArch::X86SLL_H:
4925 case LoongArch::X86SLL_W:
4926 case LoongArch::X86SRA_B:
4927 case LoongArch::X86SRA_D:
4928 case LoongArch::X86SRA_H:
4929 case LoongArch::X86SRA_W:
4930 case LoongArch::X86SRL_B:
4931 case LoongArch::X86SRL_D:
4932 case LoongArch::X86SRL_H:
4933 case LoongArch::X86SRL_W:
4934 case LoongArch::X86SUB_B:
4935 case LoongArch::X86SUB_D:
4936 case LoongArch::X86SUB_DU:
4937 case LoongArch::X86SUB_H:
4938 case LoongArch::X86SUB_W:
4939 case LoongArch::X86SUB_WU:
4940 case LoongArch::X86XOR_B:
4941 case LoongArch::X86XOR_D:
4942 case LoongArch::X86XOR_H:
4943 case LoongArch::X86XOR_W: {
4944 // op: rk
4945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4946 op &= UINT64_C(31);
4947 op <<= 10;
4948 Value |= op;
4949 // op: rj
4950 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4951 op &= UINT64_C(31);
4952 op <<= 5;
4953 Value |= op;
4954 break;
4955 }
4956 case LoongArch::AMADD_B:
4957 case LoongArch::AMADD_D:
4958 case LoongArch::AMADD_H:
4959 case LoongArch::AMADD_W:
4960 case LoongArch::AMADD__DB_B:
4961 case LoongArch::AMADD__DB_D:
4962 case LoongArch::AMADD__DB_H:
4963 case LoongArch::AMADD__DB_W:
4964 case LoongArch::AMAND_D:
4965 case LoongArch::AMAND_W:
4966 case LoongArch::AMAND__DB_D:
4967 case LoongArch::AMAND__DB_W:
4968 case LoongArch::AMCAS_B:
4969 case LoongArch::AMCAS_D:
4970 case LoongArch::AMCAS_H:
4971 case LoongArch::AMCAS_W:
4972 case LoongArch::AMCAS__DB_B:
4973 case LoongArch::AMCAS__DB_D:
4974 case LoongArch::AMCAS__DB_H:
4975 case LoongArch::AMCAS__DB_W:
4976 case LoongArch::AMMAX_D:
4977 case LoongArch::AMMAX_DU:
4978 case LoongArch::AMMAX_W:
4979 case LoongArch::AMMAX_WU:
4980 case LoongArch::AMMAX__DB_D:
4981 case LoongArch::AMMAX__DB_DU:
4982 case LoongArch::AMMAX__DB_W:
4983 case LoongArch::AMMAX__DB_WU:
4984 case LoongArch::AMMIN_D:
4985 case LoongArch::AMMIN_DU:
4986 case LoongArch::AMMIN_W:
4987 case LoongArch::AMMIN_WU:
4988 case LoongArch::AMMIN__DB_D:
4989 case LoongArch::AMMIN__DB_DU:
4990 case LoongArch::AMMIN__DB_W:
4991 case LoongArch::AMMIN__DB_WU:
4992 case LoongArch::AMOR_D:
4993 case LoongArch::AMOR_W:
4994 case LoongArch::AMOR__DB_D:
4995 case LoongArch::AMOR__DB_W:
4996 case LoongArch::AMSWAP_B:
4997 case LoongArch::AMSWAP_D:
4998 case LoongArch::AMSWAP_H:
4999 case LoongArch::AMSWAP_W:
5000 case LoongArch::AMSWAP__DB_B:
5001 case LoongArch::AMSWAP__DB_D:
5002 case LoongArch::AMSWAP__DB_H:
5003 case LoongArch::AMSWAP__DB_W:
5004 case LoongArch::AMXOR_D:
5005 case LoongArch::AMXOR_W:
5006 case LoongArch::AMXOR__DB_D:
5007 case LoongArch::AMXOR__DB_W: {
5008 // op: rk
5009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5010 op &= UINT64_C(31);
5011 op <<= 10;
5012 Value |= op;
5013 // op: rj
5014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5015 op &= UINT64_C(31);
5016 op <<= 5;
5017 Value |= op;
5018 // op: rd
5019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5020 op &= UINT64_C(31);
5021 Value |= op;
5022 break;
5023 }
5024 case LoongArch::FLDGT_D:
5025 case LoongArch::FLDGT_S:
5026 case LoongArch::FLDLE_D:
5027 case LoongArch::FLDLE_S:
5028 case LoongArch::FLDX_D:
5029 case LoongArch::FLDX_S:
5030 case LoongArch::FSTGT_D:
5031 case LoongArch::FSTGT_S:
5032 case LoongArch::FSTLE_D:
5033 case LoongArch::FSTLE_S:
5034 case LoongArch::FSTX_D:
5035 case LoongArch::FSTX_S: {
5036 // op: rk
5037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5038 op &= UINT64_C(31);
5039 op <<= 10;
5040 Value |= op;
5041 // op: rj
5042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5043 op &= UINT64_C(31);
5044 op <<= 5;
5045 Value |= op;
5046 // op: fd
5047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5048 op &= UINT64_C(31);
5049 Value |= op;
5050 break;
5051 }
5052 case LoongArch::PRELDX: {
5053 // op: rk
5054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5055 op &= UINT64_C(31);
5056 op <<= 10;
5057 Value |= op;
5058 // op: rj
5059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5060 op &= UINT64_C(31);
5061 op <<= 5;
5062 Value |= op;
5063 // op: imm5
5064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5065 op &= UINT64_C(31);
5066 Value |= op;
5067 break;
5068 }
5069 case LoongArch::ADC_B:
5070 case LoongArch::ADC_D:
5071 case LoongArch::ADC_H:
5072 case LoongArch::ADC_W:
5073 case LoongArch::ADD_D:
5074 case LoongArch::ADD_W:
5075 case LoongArch::AND:
5076 case LoongArch::ANDN:
5077 case LoongArch::CRCC_W_B_W:
5078 case LoongArch::CRCC_W_D_W:
5079 case LoongArch::CRCC_W_H_W:
5080 case LoongArch::CRCC_W_W_W:
5081 case LoongArch::CRC_W_B_W:
5082 case LoongArch::CRC_W_D_W:
5083 case LoongArch::CRC_W_H_W:
5084 case LoongArch::CRC_W_W_W:
5085 case LoongArch::DIV_D:
5086 case LoongArch::DIV_DU:
5087 case LoongArch::DIV_W:
5088 case LoongArch::DIV_WU:
5089 case LoongArch::LDGT_B:
5090 case LoongArch::LDGT_D:
5091 case LoongArch::LDGT_H:
5092 case LoongArch::LDGT_W:
5093 case LoongArch::LDLE_B:
5094 case LoongArch::LDLE_D:
5095 case LoongArch::LDLE_H:
5096 case LoongArch::LDLE_W:
5097 case LoongArch::LDX_B:
5098 case LoongArch::LDX_BU:
5099 case LoongArch::LDX_D:
5100 case LoongArch::LDX_H:
5101 case LoongArch::LDX_HU:
5102 case LoongArch::LDX_W:
5103 case LoongArch::LDX_WU:
5104 case LoongArch::MASKEQZ:
5105 case LoongArch::MASKNEZ:
5106 case LoongArch::MOD_D:
5107 case LoongArch::MOD_DU:
5108 case LoongArch::MOD_W:
5109 case LoongArch::MOD_WU:
5110 case LoongArch::MULH_D:
5111 case LoongArch::MULH_DU:
5112 case LoongArch::MULH_W:
5113 case LoongArch::MULH_WU:
5114 case LoongArch::MULW_D_W:
5115 case LoongArch::MULW_D_WU:
5116 case LoongArch::MUL_D:
5117 case LoongArch::MUL_W:
5118 case LoongArch::NOR:
5119 case LoongArch::OR:
5120 case LoongArch::ORN:
5121 case LoongArch::RCR_B:
5122 case LoongArch::RCR_D:
5123 case LoongArch::RCR_H:
5124 case LoongArch::RCR_W:
5125 case LoongArch::ROTR_B:
5126 case LoongArch::ROTR_D:
5127 case LoongArch::ROTR_H:
5128 case LoongArch::ROTR_W:
5129 case LoongArch::SBC_B:
5130 case LoongArch::SBC_D:
5131 case LoongArch::SBC_H:
5132 case LoongArch::SBC_W:
5133 case LoongArch::SLL_D:
5134 case LoongArch::SLL_W:
5135 case LoongArch::SLT:
5136 case LoongArch::SLTU:
5137 case LoongArch::SRA_D:
5138 case LoongArch::SRA_W:
5139 case LoongArch::SRL_D:
5140 case LoongArch::SRL_W:
5141 case LoongArch::STGT_B:
5142 case LoongArch::STGT_D:
5143 case LoongArch::STGT_H:
5144 case LoongArch::STGT_W:
5145 case LoongArch::STLE_B:
5146 case LoongArch::STLE_D:
5147 case LoongArch::STLE_H:
5148 case LoongArch::STLE_W:
5149 case LoongArch::STX_B:
5150 case LoongArch::STX_D:
5151 case LoongArch::STX_H:
5152 case LoongArch::STX_W:
5153 case LoongArch::SUB_D:
5154 case LoongArch::SUB_W:
5155 case LoongArch::XOR: {
5156 // op: rk
5157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5158 op &= UINT64_C(31);
5159 op <<= 10;
5160 Value |= op;
5161 // op: rj
5162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5163 op &= UINT64_C(31);
5164 op <<= 5;
5165 Value |= op;
5166 // op: rd
5167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5168 op &= UINT64_C(31);
5169 Value |= op;
5170 break;
5171 }
5172 case LoongArch::VLDX:
5173 case LoongArch::VSTX: {
5174 // op: rk
5175 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5176 op &= UINT64_C(31);
5177 op <<= 10;
5178 Value |= op;
5179 // op: rj
5180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5181 op &= UINT64_C(31);
5182 op <<= 5;
5183 Value |= op;
5184 // op: vd
5185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5186 op &= UINT64_C(31);
5187 Value |= op;
5188 break;
5189 }
5190 case LoongArch::XVLDX:
5191 case LoongArch::XVSTX: {
5192 // op: rk
5193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5194 op &= UINT64_C(31);
5195 op <<= 10;
5196 Value |= op;
5197 // op: rj
5198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5199 op &= UINT64_C(31);
5200 op <<= 5;
5201 Value |= op;
5202 // op: xd
5203 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5204 op &= UINT64_C(31);
5205 Value |= op;
5206 break;
5207 }
5208 case LoongArch::SC_Q: {
5209 // op: rk
5210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5211 op &= UINT64_C(31);
5212 op <<= 10;
5213 Value |= op;
5214 // op: rj
5215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5216 op &= UINT64_C(31);
5217 op <<= 5;
5218 Value |= op;
5219 // op: rd
5220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5221 op &= UINT64_C(31);
5222 Value |= op;
5223 break;
5224 }
5225 case LoongArch::VREPLVE_B:
5226 case LoongArch::VREPLVE_D:
5227 case LoongArch::VREPLVE_H:
5228 case LoongArch::VREPLVE_W: {
5229 // op: rk
5230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5231 op &= UINT64_C(31);
5232 op <<= 10;
5233 Value |= op;
5234 // op: vj
5235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5236 op &= UINT64_C(31);
5237 op <<= 5;
5238 Value |= op;
5239 // op: vd
5240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5241 op &= UINT64_C(31);
5242 Value |= op;
5243 break;
5244 }
5245 case LoongArch::XVREPLVE_B:
5246 case LoongArch::XVREPLVE_D:
5247 case LoongArch::XVREPLVE_H:
5248 case LoongArch::XVREPLVE_W: {
5249 // op: rk
5250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5251 op &= UINT64_C(31);
5252 op <<= 10;
5253 Value |= op;
5254 // op: xj
5255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5256 op &= UINT64_C(31);
5257 op <<= 5;
5258 Value |= op;
5259 // op: xd
5260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5261 op &= UINT64_C(31);
5262 Value |= op;
5263 break;
5264 }
5265 case LoongArch::LDPTE: {
5266 // op: seq
5267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5268 op &= UINT64_C(255);
5269 op <<= 10;
5270 Value |= op;
5271 // op: rj
5272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5273 op &= UINT64_C(31);
5274 op <<= 5;
5275 Value |= op;
5276 break;
5277 }
5278 case LoongArch::MOVSCR2GR: {
5279 // op: sj
5280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5281 op &= UINT64_C(3);
5282 op <<= 5;
5283 Value |= op;
5284 // op: rd
5285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5286 op &= UINT64_C(31);
5287 Value |= op;
5288 break;
5289 }
5290 case LoongArch::FMOV_D:
5291 case LoongArch::FMOV_S:
5292 case LoongArch::MOVCF2FR_xS:
5293 case LoongArch::MOVCF2GR:
5294 case LoongArch::MOVFCSR2GR:
5295 case LoongArch::MOVFR2CF_xS:
5296 case LoongArch::MOVFR2GR_D:
5297 case LoongArch::MOVFR2GR_S:
5298 case LoongArch::MOVFR2GR_S_64:
5299 case LoongArch::MOVFRH2GR_S:
5300 case LoongArch::MOVGR2CF:
5301 case LoongArch::MOVGR2FCSR:
5302 case LoongArch::MOVGR2FR_D:
5303 case LoongArch::MOVGR2FR_W:
5304 case LoongArch::MOVGR2FR_W_64: {
5305 // op: src
5306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5307 op &= UINT64_C(31);
5308 op <<= 5;
5309 Value |= op;
5310 // op: dst
5311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5312 op &= UINT64_C(31);
5313 Value |= op;
5314 break;
5315 }
5316 case LoongArch::MOVGR2FRH_W: {
5317 // op: src
5318 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5319 op &= UINT64_C(31);
5320 op <<= 5;
5321 Value |= op;
5322 // op: dst
5323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5324 op &= UINT64_C(31);
5325 Value |= op;
5326 break;
5327 }
5328 case LoongArch::VBITSEL_V:
5329 case LoongArch::VFMADD_D:
5330 case LoongArch::VFMADD_S:
5331 case LoongArch::VFMSUB_D:
5332 case LoongArch::VFMSUB_S:
5333 case LoongArch::VFNMADD_D:
5334 case LoongArch::VFNMADD_S:
5335 case LoongArch::VFNMSUB_D:
5336 case LoongArch::VFNMSUB_S:
5337 case LoongArch::VSHUF_B: {
5338 // op: va
5339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5340 op &= UINT64_C(31);
5341 op <<= 15;
5342 Value |= op;
5343 // op: vk
5344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5345 op &= UINT64_C(31);
5346 op <<= 10;
5347 Value |= op;
5348 // op: vj
5349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5350 op &= UINT64_C(31);
5351 op <<= 5;
5352 Value |= op;
5353 // op: vd
5354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5355 op &= UINT64_C(31);
5356 Value |= op;
5357 break;
5358 }
5359 case LoongArch::VSETALLNEZ_B:
5360 case LoongArch::VSETALLNEZ_D:
5361 case LoongArch::VSETALLNEZ_H:
5362 case LoongArch::VSETALLNEZ_W:
5363 case LoongArch::VSETANYEQZ_B:
5364 case LoongArch::VSETANYEQZ_D:
5365 case LoongArch::VSETANYEQZ_H:
5366 case LoongArch::VSETANYEQZ_W:
5367 case LoongArch::VSETEQZ_V:
5368 case LoongArch::VSETNEZ_V: {
5369 // op: vj
5370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5371 op &= UINT64_C(31);
5372 op <<= 5;
5373 Value |= op;
5374 // op: cd
5375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5376 op &= UINT64_C(7);
5377 Value |= op;
5378 break;
5379 }
5380 case LoongArch::VCLO_B:
5381 case LoongArch::VCLO_D:
5382 case LoongArch::VCLO_H:
5383 case LoongArch::VCLO_W:
5384 case LoongArch::VCLZ_B:
5385 case LoongArch::VCLZ_D:
5386 case LoongArch::VCLZ_H:
5387 case LoongArch::VCLZ_W:
5388 case LoongArch::VEXTH_DU_WU:
5389 case LoongArch::VEXTH_D_W:
5390 case LoongArch::VEXTH_HU_BU:
5391 case LoongArch::VEXTH_H_B:
5392 case LoongArch::VEXTH_QU_DU:
5393 case LoongArch::VEXTH_Q_D:
5394 case LoongArch::VEXTH_WU_HU:
5395 case LoongArch::VEXTH_W_H:
5396 case LoongArch::VEXTL_QU_DU:
5397 case LoongArch::VEXTL_Q_D:
5398 case LoongArch::VFCLASS_D:
5399 case LoongArch::VFCLASS_S:
5400 case LoongArch::VFCVTH_D_S:
5401 case LoongArch::VFCVTH_S_H:
5402 case LoongArch::VFCVTL_D_S:
5403 case LoongArch::VFCVTL_S_H:
5404 case LoongArch::VFFINTH_D_W:
5405 case LoongArch::VFFINTL_D_W:
5406 case LoongArch::VFFINT_D_L:
5407 case LoongArch::VFFINT_D_LU:
5408 case LoongArch::VFFINT_S_W:
5409 case LoongArch::VFFINT_S_WU:
5410 case LoongArch::VFLOGB_D:
5411 case LoongArch::VFLOGB_S:
5412 case LoongArch::VFRECIPE_D:
5413 case LoongArch::VFRECIPE_S:
5414 case LoongArch::VFRECIP_D:
5415 case LoongArch::VFRECIP_S:
5416 case LoongArch::VFRINTRM_D:
5417 case LoongArch::VFRINTRM_S:
5418 case LoongArch::VFRINTRNE_D:
5419 case LoongArch::VFRINTRNE_S:
5420 case LoongArch::VFRINTRP_D:
5421 case LoongArch::VFRINTRP_S:
5422 case LoongArch::VFRINTRZ_D:
5423 case LoongArch::VFRINTRZ_S:
5424 case LoongArch::VFRINT_D:
5425 case LoongArch::VFRINT_S:
5426 case LoongArch::VFRSQRTE_D:
5427 case LoongArch::VFRSQRTE_S:
5428 case LoongArch::VFRSQRT_D:
5429 case LoongArch::VFRSQRT_S:
5430 case LoongArch::VFSQRT_D:
5431 case LoongArch::VFSQRT_S:
5432 case LoongArch::VFTINTH_L_S:
5433 case LoongArch::VFTINTL_L_S:
5434 case LoongArch::VFTINTRMH_L_S:
5435 case LoongArch::VFTINTRML_L_S:
5436 case LoongArch::VFTINTRM_L_D:
5437 case LoongArch::VFTINTRM_W_S:
5438 case LoongArch::VFTINTRNEH_L_S:
5439 case LoongArch::VFTINTRNEL_L_S:
5440 case LoongArch::VFTINTRNE_L_D:
5441 case LoongArch::VFTINTRNE_W_S:
5442 case LoongArch::VFTINTRPH_L_S:
5443 case LoongArch::VFTINTRPL_L_S:
5444 case LoongArch::VFTINTRP_L_D:
5445 case LoongArch::VFTINTRP_W_S:
5446 case LoongArch::VFTINTRZH_L_S:
5447 case LoongArch::VFTINTRZL_L_S:
5448 case LoongArch::VFTINTRZ_LU_D:
5449 case LoongArch::VFTINTRZ_L_D:
5450 case LoongArch::VFTINTRZ_WU_S:
5451 case LoongArch::VFTINTRZ_W_S:
5452 case LoongArch::VFTINT_LU_D:
5453 case LoongArch::VFTINT_L_D:
5454 case LoongArch::VFTINT_WU_S:
5455 case LoongArch::VFTINT_W_S:
5456 case LoongArch::VMSKGEZ_B:
5457 case LoongArch::VMSKLTZ_B:
5458 case LoongArch::VMSKLTZ_D:
5459 case LoongArch::VMSKLTZ_H:
5460 case LoongArch::VMSKLTZ_W:
5461 case LoongArch::VMSKNZ_B:
5462 case LoongArch::VNEG_B:
5463 case LoongArch::VNEG_D:
5464 case LoongArch::VNEG_H:
5465 case LoongArch::VNEG_W:
5466 case LoongArch::VPCNT_B:
5467 case LoongArch::VPCNT_D:
5468 case LoongArch::VPCNT_H:
5469 case LoongArch::VPCNT_W: {
5470 // op: vj
5471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5472 op &= UINT64_C(31);
5473 op <<= 5;
5474 Value |= op;
5475 // op: vd
5476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5477 op &= UINT64_C(31);
5478 Value |= op;
5479 break;
5480 }
5481 case LoongArch::VABSD_B:
5482 case LoongArch::VABSD_BU:
5483 case LoongArch::VABSD_D:
5484 case LoongArch::VABSD_DU:
5485 case LoongArch::VABSD_H:
5486 case LoongArch::VABSD_HU:
5487 case LoongArch::VABSD_W:
5488 case LoongArch::VABSD_WU:
5489 case LoongArch::VADDA_B:
5490 case LoongArch::VADDA_D:
5491 case LoongArch::VADDA_H:
5492 case LoongArch::VADDA_W:
5493 case LoongArch::VADDWEV_D_W:
5494 case LoongArch::VADDWEV_D_WU:
5495 case LoongArch::VADDWEV_D_WU_W:
5496 case LoongArch::VADDWEV_H_B:
5497 case LoongArch::VADDWEV_H_BU:
5498 case LoongArch::VADDWEV_H_BU_B:
5499 case LoongArch::VADDWEV_Q_D:
5500 case LoongArch::VADDWEV_Q_DU:
5501 case LoongArch::VADDWEV_Q_DU_D:
5502 case LoongArch::VADDWEV_W_H:
5503 case LoongArch::VADDWEV_W_HU:
5504 case LoongArch::VADDWEV_W_HU_H:
5505 case LoongArch::VADDWOD_D_W:
5506 case LoongArch::VADDWOD_D_WU:
5507 case LoongArch::VADDWOD_D_WU_W:
5508 case LoongArch::VADDWOD_H_B:
5509 case LoongArch::VADDWOD_H_BU:
5510 case LoongArch::VADDWOD_H_BU_B:
5511 case LoongArch::VADDWOD_Q_D:
5512 case LoongArch::VADDWOD_Q_DU:
5513 case LoongArch::VADDWOD_Q_DU_D:
5514 case LoongArch::VADDWOD_W_H:
5515 case LoongArch::VADDWOD_W_HU:
5516 case LoongArch::VADDWOD_W_HU_H:
5517 case LoongArch::VADD_B:
5518 case LoongArch::VADD_D:
5519 case LoongArch::VADD_H:
5520 case LoongArch::VADD_Q:
5521 case LoongArch::VADD_W:
5522 case LoongArch::VANDN_V:
5523 case LoongArch::VAND_V:
5524 case LoongArch::VAVGR_B:
5525 case LoongArch::VAVGR_BU:
5526 case LoongArch::VAVGR_D:
5527 case LoongArch::VAVGR_DU:
5528 case LoongArch::VAVGR_H:
5529 case LoongArch::VAVGR_HU:
5530 case LoongArch::VAVGR_W:
5531 case LoongArch::VAVGR_WU:
5532 case LoongArch::VAVG_B:
5533 case LoongArch::VAVG_BU:
5534 case LoongArch::VAVG_D:
5535 case LoongArch::VAVG_DU:
5536 case LoongArch::VAVG_H:
5537 case LoongArch::VAVG_HU:
5538 case LoongArch::VAVG_W:
5539 case LoongArch::VAVG_WU:
5540 case LoongArch::VBITCLR_B:
5541 case LoongArch::VBITCLR_D:
5542 case LoongArch::VBITCLR_H:
5543 case LoongArch::VBITCLR_W:
5544 case LoongArch::VBITREV_B:
5545 case LoongArch::VBITREV_D:
5546 case LoongArch::VBITREV_H:
5547 case LoongArch::VBITREV_W:
5548 case LoongArch::VBITSET_B:
5549 case LoongArch::VBITSET_D:
5550 case LoongArch::VBITSET_H:
5551 case LoongArch::VBITSET_W:
5552 case LoongArch::VDIV_B:
5553 case LoongArch::VDIV_BU:
5554 case LoongArch::VDIV_D:
5555 case LoongArch::VDIV_DU:
5556 case LoongArch::VDIV_H:
5557 case LoongArch::VDIV_HU:
5558 case LoongArch::VDIV_W:
5559 case LoongArch::VDIV_WU:
5560 case LoongArch::VFADD_D:
5561 case LoongArch::VFADD_S:
5562 case LoongArch::VFCMP_CAF_D:
5563 case LoongArch::VFCMP_CAF_S:
5564 case LoongArch::VFCMP_CEQ_D:
5565 case LoongArch::VFCMP_CEQ_S:
5566 case LoongArch::VFCMP_CLE_D:
5567 case LoongArch::VFCMP_CLE_S:
5568 case LoongArch::VFCMP_CLT_D:
5569 case LoongArch::VFCMP_CLT_S:
5570 case LoongArch::VFCMP_CNE_D:
5571 case LoongArch::VFCMP_CNE_S:
5572 case LoongArch::VFCMP_COR_D:
5573 case LoongArch::VFCMP_COR_S:
5574 case LoongArch::VFCMP_CUEQ_D:
5575 case LoongArch::VFCMP_CUEQ_S:
5576 case LoongArch::VFCMP_CULE_D:
5577 case LoongArch::VFCMP_CULE_S:
5578 case LoongArch::VFCMP_CULT_D:
5579 case LoongArch::VFCMP_CULT_S:
5580 case LoongArch::VFCMP_CUNE_D:
5581 case LoongArch::VFCMP_CUNE_S:
5582 case LoongArch::VFCMP_CUN_D:
5583 case LoongArch::VFCMP_CUN_S:
5584 case LoongArch::VFCMP_SAF_D:
5585 case LoongArch::VFCMP_SAF_S:
5586 case LoongArch::VFCMP_SEQ_D:
5587 case LoongArch::VFCMP_SEQ_S:
5588 case LoongArch::VFCMP_SLE_D:
5589 case LoongArch::VFCMP_SLE_S:
5590 case LoongArch::VFCMP_SLT_D:
5591 case LoongArch::VFCMP_SLT_S:
5592 case LoongArch::VFCMP_SNE_D:
5593 case LoongArch::VFCMP_SNE_S:
5594 case LoongArch::VFCMP_SOR_D:
5595 case LoongArch::VFCMP_SOR_S:
5596 case LoongArch::VFCMP_SUEQ_D:
5597 case LoongArch::VFCMP_SUEQ_S:
5598 case LoongArch::VFCMP_SULE_D:
5599 case LoongArch::VFCMP_SULE_S:
5600 case LoongArch::VFCMP_SULT_D:
5601 case LoongArch::VFCMP_SULT_S:
5602 case LoongArch::VFCMP_SUNE_D:
5603 case LoongArch::VFCMP_SUNE_S:
5604 case LoongArch::VFCMP_SUN_D:
5605 case LoongArch::VFCMP_SUN_S:
5606 case LoongArch::VFCVT_H_S:
5607 case LoongArch::VFCVT_S_D:
5608 case LoongArch::VFDIV_D:
5609 case LoongArch::VFDIV_S:
5610 case LoongArch::VFFINT_S_L:
5611 case LoongArch::VFMAXA_D:
5612 case LoongArch::VFMAXA_S:
5613 case LoongArch::VFMAX_D:
5614 case LoongArch::VFMAX_S:
5615 case LoongArch::VFMINA_D:
5616 case LoongArch::VFMINA_S:
5617 case LoongArch::VFMIN_D:
5618 case LoongArch::VFMIN_S:
5619 case LoongArch::VFMUL_D:
5620 case LoongArch::VFMUL_S:
5621 case LoongArch::VFSUB_D:
5622 case LoongArch::VFSUB_S:
5623 case LoongArch::VFTINTRM_W_D:
5624 case LoongArch::VFTINTRNE_W_D:
5625 case LoongArch::VFTINTRP_W_D:
5626 case LoongArch::VFTINTRZ_W_D:
5627 case LoongArch::VFTINT_W_D:
5628 case LoongArch::VHADDW_DU_WU:
5629 case LoongArch::VHADDW_D_W:
5630 case LoongArch::VHADDW_HU_BU:
5631 case LoongArch::VHADDW_H_B:
5632 case LoongArch::VHADDW_QU_DU:
5633 case LoongArch::VHADDW_Q_D:
5634 case LoongArch::VHADDW_WU_HU:
5635 case LoongArch::VHADDW_W_H:
5636 case LoongArch::VHSUBW_DU_WU:
5637 case LoongArch::VHSUBW_D_W:
5638 case LoongArch::VHSUBW_HU_BU:
5639 case LoongArch::VHSUBW_H_B:
5640 case LoongArch::VHSUBW_QU_DU:
5641 case LoongArch::VHSUBW_Q_D:
5642 case LoongArch::VHSUBW_WU_HU:
5643 case LoongArch::VHSUBW_W_H:
5644 case LoongArch::VILVH_B:
5645 case LoongArch::VILVH_D:
5646 case LoongArch::VILVH_H:
5647 case LoongArch::VILVH_W:
5648 case LoongArch::VILVL_B:
5649 case LoongArch::VILVL_D:
5650 case LoongArch::VILVL_H:
5651 case LoongArch::VILVL_W:
5652 case LoongArch::VMAX_B:
5653 case LoongArch::VMAX_BU:
5654 case LoongArch::VMAX_D:
5655 case LoongArch::VMAX_DU:
5656 case LoongArch::VMAX_H:
5657 case LoongArch::VMAX_HU:
5658 case LoongArch::VMAX_W:
5659 case LoongArch::VMAX_WU:
5660 case LoongArch::VMIN_B:
5661 case LoongArch::VMIN_BU:
5662 case LoongArch::VMIN_D:
5663 case LoongArch::VMIN_DU:
5664 case LoongArch::VMIN_H:
5665 case LoongArch::VMIN_HU:
5666 case LoongArch::VMIN_W:
5667 case LoongArch::VMIN_WU:
5668 case LoongArch::VMOD_B:
5669 case LoongArch::VMOD_BU:
5670 case LoongArch::VMOD_D:
5671 case LoongArch::VMOD_DU:
5672 case LoongArch::VMOD_H:
5673 case LoongArch::VMOD_HU:
5674 case LoongArch::VMOD_W:
5675 case LoongArch::VMOD_WU:
5676 case LoongArch::VMUH_B:
5677 case LoongArch::VMUH_BU:
5678 case LoongArch::VMUH_D:
5679 case LoongArch::VMUH_DU:
5680 case LoongArch::VMUH_H:
5681 case LoongArch::VMUH_HU:
5682 case LoongArch::VMUH_W:
5683 case LoongArch::VMUH_WU:
5684 case LoongArch::VMULWEV_D_W:
5685 case LoongArch::VMULWEV_D_WU:
5686 case LoongArch::VMULWEV_D_WU_W:
5687 case LoongArch::VMULWEV_H_B:
5688 case LoongArch::VMULWEV_H_BU:
5689 case LoongArch::VMULWEV_H_BU_B:
5690 case LoongArch::VMULWEV_Q_D:
5691 case LoongArch::VMULWEV_Q_DU:
5692 case LoongArch::VMULWEV_Q_DU_D:
5693 case LoongArch::VMULWEV_W_H:
5694 case LoongArch::VMULWEV_W_HU:
5695 case LoongArch::VMULWEV_W_HU_H:
5696 case LoongArch::VMULWOD_D_W:
5697 case LoongArch::VMULWOD_D_WU:
5698 case LoongArch::VMULWOD_D_WU_W:
5699 case LoongArch::VMULWOD_H_B:
5700 case LoongArch::VMULWOD_H_BU:
5701 case LoongArch::VMULWOD_H_BU_B:
5702 case LoongArch::VMULWOD_Q_D:
5703 case LoongArch::VMULWOD_Q_DU:
5704 case LoongArch::VMULWOD_Q_DU_D:
5705 case LoongArch::VMULWOD_W_H:
5706 case LoongArch::VMULWOD_W_HU:
5707 case LoongArch::VMULWOD_W_HU_H:
5708 case LoongArch::VMUL_B:
5709 case LoongArch::VMUL_D:
5710 case LoongArch::VMUL_H:
5711 case LoongArch::VMUL_W:
5712 case LoongArch::VNOR_V:
5713 case LoongArch::VORN_V:
5714 case LoongArch::VOR_V:
5715 case LoongArch::VPACKEV_B:
5716 case LoongArch::VPACKEV_D:
5717 case LoongArch::VPACKEV_H:
5718 case LoongArch::VPACKEV_W:
5719 case LoongArch::VPACKOD_B:
5720 case LoongArch::VPACKOD_D:
5721 case LoongArch::VPACKOD_H:
5722 case LoongArch::VPACKOD_W:
5723 case LoongArch::VPICKEV_B:
5724 case LoongArch::VPICKEV_D:
5725 case LoongArch::VPICKEV_H:
5726 case LoongArch::VPICKEV_W:
5727 case LoongArch::VPICKOD_B:
5728 case LoongArch::VPICKOD_D:
5729 case LoongArch::VPICKOD_H:
5730 case LoongArch::VPICKOD_W:
5731 case LoongArch::VROTR_B:
5732 case LoongArch::VROTR_D:
5733 case LoongArch::VROTR_H:
5734 case LoongArch::VROTR_W:
5735 case LoongArch::VSADD_B:
5736 case LoongArch::VSADD_BU:
5737 case LoongArch::VSADD_D:
5738 case LoongArch::VSADD_DU:
5739 case LoongArch::VSADD_H:
5740 case LoongArch::VSADD_HU:
5741 case LoongArch::VSADD_W:
5742 case LoongArch::VSADD_WU:
5743 case LoongArch::VSEQ_B:
5744 case LoongArch::VSEQ_D:
5745 case LoongArch::VSEQ_H:
5746 case LoongArch::VSEQ_W:
5747 case LoongArch::VSIGNCOV_B:
5748 case LoongArch::VSIGNCOV_D:
5749 case LoongArch::VSIGNCOV_H:
5750 case LoongArch::VSIGNCOV_W:
5751 case LoongArch::VSLE_B:
5752 case LoongArch::VSLE_BU:
5753 case LoongArch::VSLE_D:
5754 case LoongArch::VSLE_DU:
5755 case LoongArch::VSLE_H:
5756 case LoongArch::VSLE_HU:
5757 case LoongArch::VSLE_W:
5758 case LoongArch::VSLE_WU:
5759 case LoongArch::VSLL_B:
5760 case LoongArch::VSLL_D:
5761 case LoongArch::VSLL_H:
5762 case LoongArch::VSLL_W:
5763 case LoongArch::VSLT_B:
5764 case LoongArch::VSLT_BU:
5765 case LoongArch::VSLT_D:
5766 case LoongArch::VSLT_DU:
5767 case LoongArch::VSLT_H:
5768 case LoongArch::VSLT_HU:
5769 case LoongArch::VSLT_W:
5770 case LoongArch::VSLT_WU:
5771 case LoongArch::VSRAN_B_H:
5772 case LoongArch::VSRAN_H_W:
5773 case LoongArch::VSRAN_W_D:
5774 case LoongArch::VSRARN_B_H:
5775 case LoongArch::VSRARN_H_W:
5776 case LoongArch::VSRARN_W_D:
5777 case LoongArch::VSRAR_B:
5778 case LoongArch::VSRAR_D:
5779 case LoongArch::VSRAR_H:
5780 case LoongArch::VSRAR_W:
5781 case LoongArch::VSRA_B:
5782 case LoongArch::VSRA_D:
5783 case LoongArch::VSRA_H:
5784 case LoongArch::VSRA_W:
5785 case LoongArch::VSRLN_B_H:
5786 case LoongArch::VSRLN_H_W:
5787 case LoongArch::VSRLN_W_D:
5788 case LoongArch::VSRLRN_B_H:
5789 case LoongArch::VSRLRN_H_W:
5790 case LoongArch::VSRLRN_W_D:
5791 case LoongArch::VSRLR_B:
5792 case LoongArch::VSRLR_D:
5793 case LoongArch::VSRLR_H:
5794 case LoongArch::VSRLR_W:
5795 case LoongArch::VSRL_B:
5796 case LoongArch::VSRL_D:
5797 case LoongArch::VSRL_H:
5798 case LoongArch::VSRL_W:
5799 case LoongArch::VSSRAN_BU_H:
5800 case LoongArch::VSSRAN_B_H:
5801 case LoongArch::VSSRAN_HU_W:
5802 case LoongArch::VSSRAN_H_W:
5803 case LoongArch::VSSRAN_WU_D:
5804 case LoongArch::VSSRAN_W_D:
5805 case LoongArch::VSSRARN_BU_H:
5806 case LoongArch::VSSRARN_B_H:
5807 case LoongArch::VSSRARN_HU_W:
5808 case LoongArch::VSSRARN_H_W:
5809 case LoongArch::VSSRARN_WU_D:
5810 case LoongArch::VSSRARN_W_D:
5811 case LoongArch::VSSRLN_BU_H:
5812 case LoongArch::VSSRLN_B_H:
5813 case LoongArch::VSSRLN_HU_W:
5814 case LoongArch::VSSRLN_H_W:
5815 case LoongArch::VSSRLN_WU_D:
5816 case LoongArch::VSSRLN_W_D:
5817 case LoongArch::VSSRLRN_BU_H:
5818 case LoongArch::VSSRLRN_B_H:
5819 case LoongArch::VSSRLRN_HU_W:
5820 case LoongArch::VSSRLRN_H_W:
5821 case LoongArch::VSSRLRN_WU_D:
5822 case LoongArch::VSSRLRN_W_D:
5823 case LoongArch::VSSUB_B:
5824 case LoongArch::VSSUB_BU:
5825 case LoongArch::VSSUB_D:
5826 case LoongArch::VSSUB_DU:
5827 case LoongArch::VSSUB_H:
5828 case LoongArch::VSSUB_HU:
5829 case LoongArch::VSSUB_W:
5830 case LoongArch::VSSUB_WU:
5831 case LoongArch::VSUBWEV_D_W:
5832 case LoongArch::VSUBWEV_D_WU:
5833 case LoongArch::VSUBWEV_H_B:
5834 case LoongArch::VSUBWEV_H_BU:
5835 case LoongArch::VSUBWEV_Q_D:
5836 case LoongArch::VSUBWEV_Q_DU:
5837 case LoongArch::VSUBWEV_W_H:
5838 case LoongArch::VSUBWEV_W_HU:
5839 case LoongArch::VSUBWOD_D_W:
5840 case LoongArch::VSUBWOD_D_WU:
5841 case LoongArch::VSUBWOD_H_B:
5842 case LoongArch::VSUBWOD_H_BU:
5843 case LoongArch::VSUBWOD_Q_D:
5844 case LoongArch::VSUBWOD_Q_DU:
5845 case LoongArch::VSUBWOD_W_H:
5846 case LoongArch::VSUBWOD_W_HU:
5847 case LoongArch::VSUB_B:
5848 case LoongArch::VSUB_D:
5849 case LoongArch::VSUB_H:
5850 case LoongArch::VSUB_Q:
5851 case LoongArch::VSUB_W:
5852 case LoongArch::VXOR_V: {
5853 // op: vk
5854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5855 op &= UINT64_C(31);
5856 op <<= 10;
5857 Value |= op;
5858 // op: vj
5859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5860 op &= UINT64_C(31);
5861 op <<= 5;
5862 Value |= op;
5863 // op: vd
5864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5865 op &= UINT64_C(31);
5866 Value |= op;
5867 break;
5868 }
5869 case LoongArch::VFRSTP_B:
5870 case LoongArch::VFRSTP_H:
5871 case LoongArch::VMADDWEV_D_W:
5872 case LoongArch::VMADDWEV_D_WU:
5873 case LoongArch::VMADDWEV_D_WU_W:
5874 case LoongArch::VMADDWEV_H_B:
5875 case LoongArch::VMADDWEV_H_BU:
5876 case LoongArch::VMADDWEV_H_BU_B:
5877 case LoongArch::VMADDWEV_Q_D:
5878 case LoongArch::VMADDWEV_Q_DU:
5879 case LoongArch::VMADDWEV_Q_DU_D:
5880 case LoongArch::VMADDWEV_W_H:
5881 case LoongArch::VMADDWEV_W_HU:
5882 case LoongArch::VMADDWEV_W_HU_H:
5883 case LoongArch::VMADDWOD_D_W:
5884 case LoongArch::VMADDWOD_D_WU:
5885 case LoongArch::VMADDWOD_D_WU_W:
5886 case LoongArch::VMADDWOD_H_B:
5887 case LoongArch::VMADDWOD_H_BU:
5888 case LoongArch::VMADDWOD_H_BU_B:
5889 case LoongArch::VMADDWOD_Q_D:
5890 case LoongArch::VMADDWOD_Q_DU:
5891 case LoongArch::VMADDWOD_Q_DU_D:
5892 case LoongArch::VMADDWOD_W_H:
5893 case LoongArch::VMADDWOD_W_HU:
5894 case LoongArch::VMADDWOD_W_HU_H:
5895 case LoongArch::VMADD_B:
5896 case LoongArch::VMADD_D:
5897 case LoongArch::VMADD_H:
5898 case LoongArch::VMADD_W:
5899 case LoongArch::VMSUB_B:
5900 case LoongArch::VMSUB_D:
5901 case LoongArch::VMSUB_H:
5902 case LoongArch::VMSUB_W:
5903 case LoongArch::VSHUF_D:
5904 case LoongArch::VSHUF_H:
5905 case LoongArch::VSHUF_W: {
5906 // op: vk
5907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5908 op &= UINT64_C(31);
5909 op <<= 10;
5910 Value |= op;
5911 // op: vj
5912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5913 op &= UINT64_C(31);
5914 op <<= 5;
5915 Value |= op;
5916 // op: vd
5917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5918 op &= UINT64_C(31);
5919 Value |= op;
5920 break;
5921 }
5922 case LoongArch::XVBITSEL_V:
5923 case LoongArch::XVFMADD_D:
5924 case LoongArch::XVFMADD_S:
5925 case LoongArch::XVFMSUB_D:
5926 case LoongArch::XVFMSUB_S:
5927 case LoongArch::XVFNMADD_D:
5928 case LoongArch::XVFNMADD_S:
5929 case LoongArch::XVFNMSUB_D:
5930 case LoongArch::XVFNMSUB_S:
5931 case LoongArch::XVSHUF_B: {
5932 // op: xa
5933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5934 op &= UINT64_C(31);
5935 op <<= 15;
5936 Value |= op;
5937 // op: xk
5938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5939 op &= UINT64_C(31);
5940 op <<= 10;
5941 Value |= op;
5942 // op: xj
5943 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5944 op &= UINT64_C(31);
5945 op <<= 5;
5946 Value |= op;
5947 // op: xd
5948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5949 op &= UINT64_C(31);
5950 Value |= op;
5951 break;
5952 }
5953 case LoongArch::XVSETALLNEZ_B:
5954 case LoongArch::XVSETALLNEZ_D:
5955 case LoongArch::XVSETALLNEZ_H:
5956 case LoongArch::XVSETALLNEZ_W:
5957 case LoongArch::XVSETANYEQZ_B:
5958 case LoongArch::XVSETANYEQZ_D:
5959 case LoongArch::XVSETANYEQZ_H:
5960 case LoongArch::XVSETANYEQZ_W:
5961 case LoongArch::XVSETEQZ_V:
5962 case LoongArch::XVSETNEZ_V: {
5963 // op: xj
5964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5965 op &= UINT64_C(31);
5966 op <<= 5;
5967 Value |= op;
5968 // op: cd
5969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5970 op &= UINT64_C(7);
5971 Value |= op;
5972 break;
5973 }
5974 case LoongArch::VEXT2XV_DU_BU:
5975 case LoongArch::VEXT2XV_DU_HU:
5976 case LoongArch::VEXT2XV_DU_WU:
5977 case LoongArch::VEXT2XV_D_B:
5978 case LoongArch::VEXT2XV_D_H:
5979 case LoongArch::VEXT2XV_D_W:
5980 case LoongArch::VEXT2XV_HU_BU:
5981 case LoongArch::VEXT2XV_H_B:
5982 case LoongArch::VEXT2XV_WU_BU:
5983 case LoongArch::VEXT2XV_WU_HU:
5984 case LoongArch::VEXT2XV_W_B:
5985 case LoongArch::VEXT2XV_W_H:
5986 case LoongArch::XVCLO_B:
5987 case LoongArch::XVCLO_D:
5988 case LoongArch::XVCLO_H:
5989 case LoongArch::XVCLO_W:
5990 case LoongArch::XVCLZ_B:
5991 case LoongArch::XVCLZ_D:
5992 case LoongArch::XVCLZ_H:
5993 case LoongArch::XVCLZ_W:
5994 case LoongArch::XVEXTH_DU_WU:
5995 case LoongArch::XVEXTH_D_W:
5996 case LoongArch::XVEXTH_HU_BU:
5997 case LoongArch::XVEXTH_H_B:
5998 case LoongArch::XVEXTH_QU_DU:
5999 case LoongArch::XVEXTH_Q_D:
6000 case LoongArch::XVEXTH_WU_HU:
6001 case LoongArch::XVEXTH_W_H:
6002 case LoongArch::XVEXTL_QU_DU:
6003 case LoongArch::XVEXTL_Q_D:
6004 case LoongArch::XVFCLASS_D:
6005 case LoongArch::XVFCLASS_S:
6006 case LoongArch::XVFCVTH_D_S:
6007 case LoongArch::XVFCVTH_S_H:
6008 case LoongArch::XVFCVTL_D_S:
6009 case LoongArch::XVFCVTL_S_H:
6010 case LoongArch::XVFFINTH_D_W:
6011 case LoongArch::XVFFINTL_D_W:
6012 case LoongArch::XVFFINT_D_L:
6013 case LoongArch::XVFFINT_D_LU:
6014 case LoongArch::XVFFINT_S_W:
6015 case LoongArch::XVFFINT_S_WU:
6016 case LoongArch::XVFLOGB_D:
6017 case LoongArch::XVFLOGB_S:
6018 case LoongArch::XVFRECIPE_D:
6019 case LoongArch::XVFRECIPE_S:
6020 case LoongArch::XVFRECIP_D:
6021 case LoongArch::XVFRECIP_S:
6022 case LoongArch::XVFRINTRM_D:
6023 case LoongArch::XVFRINTRM_S:
6024 case LoongArch::XVFRINTRNE_D:
6025 case LoongArch::XVFRINTRNE_S:
6026 case LoongArch::XVFRINTRP_D:
6027 case LoongArch::XVFRINTRP_S:
6028 case LoongArch::XVFRINTRZ_D:
6029 case LoongArch::XVFRINTRZ_S:
6030 case LoongArch::XVFRINT_D:
6031 case LoongArch::XVFRINT_S:
6032 case LoongArch::XVFRSQRTE_D:
6033 case LoongArch::XVFRSQRTE_S:
6034 case LoongArch::XVFRSQRT_D:
6035 case LoongArch::XVFRSQRT_S:
6036 case LoongArch::XVFSQRT_D:
6037 case LoongArch::XVFSQRT_S:
6038 case LoongArch::XVFTINTH_L_S:
6039 case LoongArch::XVFTINTL_L_S:
6040 case LoongArch::XVFTINTRMH_L_S:
6041 case LoongArch::XVFTINTRML_L_S:
6042 case LoongArch::XVFTINTRM_L_D:
6043 case LoongArch::XVFTINTRM_W_S:
6044 case LoongArch::XVFTINTRNEH_L_S:
6045 case LoongArch::XVFTINTRNEL_L_S:
6046 case LoongArch::XVFTINTRNE_L_D:
6047 case LoongArch::XVFTINTRNE_W_S:
6048 case LoongArch::XVFTINTRPH_L_S:
6049 case LoongArch::XVFTINTRPL_L_S:
6050 case LoongArch::XVFTINTRP_L_D:
6051 case LoongArch::XVFTINTRP_W_S:
6052 case LoongArch::XVFTINTRZH_L_S:
6053 case LoongArch::XVFTINTRZL_L_S:
6054 case LoongArch::XVFTINTRZ_LU_D:
6055 case LoongArch::XVFTINTRZ_L_D:
6056 case LoongArch::XVFTINTRZ_WU_S:
6057 case LoongArch::XVFTINTRZ_W_S:
6058 case LoongArch::XVFTINT_LU_D:
6059 case LoongArch::XVFTINT_L_D:
6060 case LoongArch::XVFTINT_WU_S:
6061 case LoongArch::XVFTINT_W_S:
6062 case LoongArch::XVMSKGEZ_B:
6063 case LoongArch::XVMSKLTZ_B:
6064 case LoongArch::XVMSKLTZ_D:
6065 case LoongArch::XVMSKLTZ_H:
6066 case LoongArch::XVMSKLTZ_W:
6067 case LoongArch::XVMSKNZ_B:
6068 case LoongArch::XVNEG_B:
6069 case LoongArch::XVNEG_D:
6070 case LoongArch::XVNEG_H:
6071 case LoongArch::XVNEG_W:
6072 case LoongArch::XVPCNT_B:
6073 case LoongArch::XVPCNT_D:
6074 case LoongArch::XVPCNT_H:
6075 case LoongArch::XVPCNT_W:
6076 case LoongArch::XVREPLVE0_B:
6077 case LoongArch::XVREPLVE0_D:
6078 case LoongArch::XVREPLVE0_H:
6079 case LoongArch::XVREPLVE0_Q:
6080 case LoongArch::XVREPLVE0_W: {
6081 // op: xj
6082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6083 op &= UINT64_C(31);
6084 op <<= 5;
6085 Value |= op;
6086 // op: xd
6087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6088 op &= UINT64_C(31);
6089 Value |= op;
6090 break;
6091 }
6092 case LoongArch::XVABSD_B:
6093 case LoongArch::XVABSD_BU:
6094 case LoongArch::XVABSD_D:
6095 case LoongArch::XVABSD_DU:
6096 case LoongArch::XVABSD_H:
6097 case LoongArch::XVABSD_HU:
6098 case LoongArch::XVABSD_W:
6099 case LoongArch::XVABSD_WU:
6100 case LoongArch::XVADDA_B:
6101 case LoongArch::XVADDA_D:
6102 case LoongArch::XVADDA_H:
6103 case LoongArch::XVADDA_W:
6104 case LoongArch::XVADDWEV_D_W:
6105 case LoongArch::XVADDWEV_D_WU:
6106 case LoongArch::XVADDWEV_D_WU_W:
6107 case LoongArch::XVADDWEV_H_B:
6108 case LoongArch::XVADDWEV_H_BU:
6109 case LoongArch::XVADDWEV_H_BU_B:
6110 case LoongArch::XVADDWEV_Q_D:
6111 case LoongArch::XVADDWEV_Q_DU:
6112 case LoongArch::XVADDWEV_Q_DU_D:
6113 case LoongArch::XVADDWEV_W_H:
6114 case LoongArch::XVADDWEV_W_HU:
6115 case LoongArch::XVADDWEV_W_HU_H:
6116 case LoongArch::XVADDWOD_D_W:
6117 case LoongArch::XVADDWOD_D_WU:
6118 case LoongArch::XVADDWOD_D_WU_W:
6119 case LoongArch::XVADDWOD_H_B:
6120 case LoongArch::XVADDWOD_H_BU:
6121 case LoongArch::XVADDWOD_H_BU_B:
6122 case LoongArch::XVADDWOD_Q_D:
6123 case LoongArch::XVADDWOD_Q_DU:
6124 case LoongArch::XVADDWOD_Q_DU_D:
6125 case LoongArch::XVADDWOD_W_H:
6126 case LoongArch::XVADDWOD_W_HU:
6127 case LoongArch::XVADDWOD_W_HU_H:
6128 case LoongArch::XVADD_B:
6129 case LoongArch::XVADD_D:
6130 case LoongArch::XVADD_H:
6131 case LoongArch::XVADD_Q:
6132 case LoongArch::XVADD_W:
6133 case LoongArch::XVANDN_V:
6134 case LoongArch::XVAND_V:
6135 case LoongArch::XVAVGR_B:
6136 case LoongArch::XVAVGR_BU:
6137 case LoongArch::XVAVGR_D:
6138 case LoongArch::XVAVGR_DU:
6139 case LoongArch::XVAVGR_H:
6140 case LoongArch::XVAVGR_HU:
6141 case LoongArch::XVAVGR_W:
6142 case LoongArch::XVAVGR_WU:
6143 case LoongArch::XVAVG_B:
6144 case LoongArch::XVAVG_BU:
6145 case LoongArch::XVAVG_D:
6146 case LoongArch::XVAVG_DU:
6147 case LoongArch::XVAVG_H:
6148 case LoongArch::XVAVG_HU:
6149 case LoongArch::XVAVG_W:
6150 case LoongArch::XVAVG_WU:
6151 case LoongArch::XVBITCLR_B:
6152 case LoongArch::XVBITCLR_D:
6153 case LoongArch::XVBITCLR_H:
6154 case LoongArch::XVBITCLR_W:
6155 case LoongArch::XVBITREV_B:
6156 case LoongArch::XVBITREV_D:
6157 case LoongArch::XVBITREV_H:
6158 case LoongArch::XVBITREV_W:
6159 case LoongArch::XVBITSET_B:
6160 case LoongArch::XVBITSET_D:
6161 case LoongArch::XVBITSET_H:
6162 case LoongArch::XVBITSET_W:
6163 case LoongArch::XVDIV_B:
6164 case LoongArch::XVDIV_BU:
6165 case LoongArch::XVDIV_D:
6166 case LoongArch::XVDIV_DU:
6167 case LoongArch::XVDIV_H:
6168 case LoongArch::XVDIV_HU:
6169 case LoongArch::XVDIV_W:
6170 case LoongArch::XVDIV_WU:
6171 case LoongArch::XVFADD_D:
6172 case LoongArch::XVFADD_S:
6173 case LoongArch::XVFCMP_CAF_D:
6174 case LoongArch::XVFCMP_CAF_S:
6175 case LoongArch::XVFCMP_CEQ_D:
6176 case LoongArch::XVFCMP_CEQ_S:
6177 case LoongArch::XVFCMP_CLE_D:
6178 case LoongArch::XVFCMP_CLE_S:
6179 case LoongArch::XVFCMP_CLT_D:
6180 case LoongArch::XVFCMP_CLT_S:
6181 case LoongArch::XVFCMP_CNE_D:
6182 case LoongArch::XVFCMP_CNE_S:
6183 case LoongArch::XVFCMP_COR_D:
6184 case LoongArch::XVFCMP_COR_S:
6185 case LoongArch::XVFCMP_CUEQ_D:
6186 case LoongArch::XVFCMP_CUEQ_S:
6187 case LoongArch::XVFCMP_CULE_D:
6188 case LoongArch::XVFCMP_CULE_S:
6189 case LoongArch::XVFCMP_CULT_D:
6190 case LoongArch::XVFCMP_CULT_S:
6191 case LoongArch::XVFCMP_CUNE_D:
6192 case LoongArch::XVFCMP_CUNE_S:
6193 case LoongArch::XVFCMP_CUN_D:
6194 case LoongArch::XVFCMP_CUN_S:
6195 case LoongArch::XVFCMP_SAF_D:
6196 case LoongArch::XVFCMP_SAF_S:
6197 case LoongArch::XVFCMP_SEQ_D:
6198 case LoongArch::XVFCMP_SEQ_S:
6199 case LoongArch::XVFCMP_SLE_D:
6200 case LoongArch::XVFCMP_SLE_S:
6201 case LoongArch::XVFCMP_SLT_D:
6202 case LoongArch::XVFCMP_SLT_S:
6203 case LoongArch::XVFCMP_SNE_D:
6204 case LoongArch::XVFCMP_SNE_S:
6205 case LoongArch::XVFCMP_SOR_D:
6206 case LoongArch::XVFCMP_SOR_S:
6207 case LoongArch::XVFCMP_SUEQ_D:
6208 case LoongArch::XVFCMP_SUEQ_S:
6209 case LoongArch::XVFCMP_SULE_D:
6210 case LoongArch::XVFCMP_SULE_S:
6211 case LoongArch::XVFCMP_SULT_D:
6212 case LoongArch::XVFCMP_SULT_S:
6213 case LoongArch::XVFCMP_SUNE_D:
6214 case LoongArch::XVFCMP_SUNE_S:
6215 case LoongArch::XVFCMP_SUN_D:
6216 case LoongArch::XVFCMP_SUN_S:
6217 case LoongArch::XVFCVT_H_S:
6218 case LoongArch::XVFCVT_S_D:
6219 case LoongArch::XVFDIV_D:
6220 case LoongArch::XVFDIV_S:
6221 case LoongArch::XVFFINT_S_L:
6222 case LoongArch::XVFMAXA_D:
6223 case LoongArch::XVFMAXA_S:
6224 case LoongArch::XVFMAX_D:
6225 case LoongArch::XVFMAX_S:
6226 case LoongArch::XVFMINA_D:
6227 case LoongArch::XVFMINA_S:
6228 case LoongArch::XVFMIN_D:
6229 case LoongArch::XVFMIN_S:
6230 case LoongArch::XVFMUL_D:
6231 case LoongArch::XVFMUL_S:
6232 case LoongArch::XVFSUB_D:
6233 case LoongArch::XVFSUB_S:
6234 case LoongArch::XVFTINTRM_W_D:
6235 case LoongArch::XVFTINTRNE_W_D:
6236 case LoongArch::XVFTINTRP_W_D:
6237 case LoongArch::XVFTINTRZ_W_D:
6238 case LoongArch::XVFTINT_W_D:
6239 case LoongArch::XVHADDW_DU_WU:
6240 case LoongArch::XVHADDW_D_W:
6241 case LoongArch::XVHADDW_HU_BU:
6242 case LoongArch::XVHADDW_H_B:
6243 case LoongArch::XVHADDW_QU_DU:
6244 case LoongArch::XVHADDW_Q_D:
6245 case LoongArch::XVHADDW_WU_HU:
6246 case LoongArch::XVHADDW_W_H:
6247 case LoongArch::XVHSUBW_DU_WU:
6248 case LoongArch::XVHSUBW_D_W:
6249 case LoongArch::XVHSUBW_HU_BU:
6250 case LoongArch::XVHSUBW_H_B:
6251 case LoongArch::XVHSUBW_QU_DU:
6252 case LoongArch::XVHSUBW_Q_D:
6253 case LoongArch::XVHSUBW_WU_HU:
6254 case LoongArch::XVHSUBW_W_H:
6255 case LoongArch::XVILVH_B:
6256 case LoongArch::XVILVH_D:
6257 case LoongArch::XVILVH_H:
6258 case LoongArch::XVILVH_W:
6259 case LoongArch::XVILVL_B:
6260 case LoongArch::XVILVL_D:
6261 case LoongArch::XVILVL_H:
6262 case LoongArch::XVILVL_W:
6263 case LoongArch::XVMAX_B:
6264 case LoongArch::XVMAX_BU:
6265 case LoongArch::XVMAX_D:
6266 case LoongArch::XVMAX_DU:
6267 case LoongArch::XVMAX_H:
6268 case LoongArch::XVMAX_HU:
6269 case LoongArch::XVMAX_W:
6270 case LoongArch::XVMAX_WU:
6271 case LoongArch::XVMIN_B:
6272 case LoongArch::XVMIN_BU:
6273 case LoongArch::XVMIN_D:
6274 case LoongArch::XVMIN_DU:
6275 case LoongArch::XVMIN_H:
6276 case LoongArch::XVMIN_HU:
6277 case LoongArch::XVMIN_W:
6278 case LoongArch::XVMIN_WU:
6279 case LoongArch::XVMOD_B:
6280 case LoongArch::XVMOD_BU:
6281 case LoongArch::XVMOD_D:
6282 case LoongArch::XVMOD_DU:
6283 case LoongArch::XVMOD_H:
6284 case LoongArch::XVMOD_HU:
6285 case LoongArch::XVMOD_W:
6286 case LoongArch::XVMOD_WU:
6287 case LoongArch::XVMUH_B:
6288 case LoongArch::XVMUH_BU:
6289 case LoongArch::XVMUH_D:
6290 case LoongArch::XVMUH_DU:
6291 case LoongArch::XVMUH_H:
6292 case LoongArch::XVMUH_HU:
6293 case LoongArch::XVMUH_W:
6294 case LoongArch::XVMUH_WU:
6295 case LoongArch::XVMULWEV_D_W:
6296 case LoongArch::XVMULWEV_D_WU:
6297 case LoongArch::XVMULWEV_D_WU_W:
6298 case LoongArch::XVMULWEV_H_B:
6299 case LoongArch::XVMULWEV_H_BU:
6300 case LoongArch::XVMULWEV_H_BU_B:
6301 case LoongArch::XVMULWEV_Q_D:
6302 case LoongArch::XVMULWEV_Q_DU:
6303 case LoongArch::XVMULWEV_Q_DU_D:
6304 case LoongArch::XVMULWEV_W_H:
6305 case LoongArch::XVMULWEV_W_HU:
6306 case LoongArch::XVMULWEV_W_HU_H:
6307 case LoongArch::XVMULWOD_D_W:
6308 case LoongArch::XVMULWOD_D_WU:
6309 case LoongArch::XVMULWOD_D_WU_W:
6310 case LoongArch::XVMULWOD_H_B:
6311 case LoongArch::XVMULWOD_H_BU:
6312 case LoongArch::XVMULWOD_H_BU_B:
6313 case LoongArch::XVMULWOD_Q_D:
6314 case LoongArch::XVMULWOD_Q_DU:
6315 case LoongArch::XVMULWOD_Q_DU_D:
6316 case LoongArch::XVMULWOD_W_H:
6317 case LoongArch::XVMULWOD_W_HU:
6318 case LoongArch::XVMULWOD_W_HU_H:
6319 case LoongArch::XVMUL_B:
6320 case LoongArch::XVMUL_D:
6321 case LoongArch::XVMUL_H:
6322 case LoongArch::XVMUL_W:
6323 case LoongArch::XVNOR_V:
6324 case LoongArch::XVORN_V:
6325 case LoongArch::XVOR_V:
6326 case LoongArch::XVPACKEV_B:
6327 case LoongArch::XVPACKEV_D:
6328 case LoongArch::XVPACKEV_H:
6329 case LoongArch::XVPACKEV_W:
6330 case LoongArch::XVPACKOD_B:
6331 case LoongArch::XVPACKOD_D:
6332 case LoongArch::XVPACKOD_H:
6333 case LoongArch::XVPACKOD_W:
6334 case LoongArch::XVPERM_W:
6335 case LoongArch::XVPICKEV_B:
6336 case LoongArch::XVPICKEV_D:
6337 case LoongArch::XVPICKEV_H:
6338 case LoongArch::XVPICKEV_W:
6339 case LoongArch::XVPICKOD_B:
6340 case LoongArch::XVPICKOD_D:
6341 case LoongArch::XVPICKOD_H:
6342 case LoongArch::XVPICKOD_W:
6343 case LoongArch::XVROTR_B:
6344 case LoongArch::XVROTR_D:
6345 case LoongArch::XVROTR_H:
6346 case LoongArch::XVROTR_W:
6347 case LoongArch::XVSADD_B:
6348 case LoongArch::XVSADD_BU:
6349 case LoongArch::XVSADD_D:
6350 case LoongArch::XVSADD_DU:
6351 case LoongArch::XVSADD_H:
6352 case LoongArch::XVSADD_HU:
6353 case LoongArch::XVSADD_W:
6354 case LoongArch::XVSADD_WU:
6355 case LoongArch::XVSEQ_B:
6356 case LoongArch::XVSEQ_D:
6357 case LoongArch::XVSEQ_H:
6358 case LoongArch::XVSEQ_W:
6359 case LoongArch::XVSIGNCOV_B:
6360 case LoongArch::XVSIGNCOV_D:
6361 case LoongArch::XVSIGNCOV_H:
6362 case LoongArch::XVSIGNCOV_W:
6363 case LoongArch::XVSLE_B:
6364 case LoongArch::XVSLE_BU:
6365 case LoongArch::XVSLE_D:
6366 case LoongArch::XVSLE_DU:
6367 case LoongArch::XVSLE_H:
6368 case LoongArch::XVSLE_HU:
6369 case LoongArch::XVSLE_W:
6370 case LoongArch::XVSLE_WU:
6371 case LoongArch::XVSLL_B:
6372 case LoongArch::XVSLL_D:
6373 case LoongArch::XVSLL_H:
6374 case LoongArch::XVSLL_W:
6375 case LoongArch::XVSLT_B:
6376 case LoongArch::XVSLT_BU:
6377 case LoongArch::XVSLT_D:
6378 case LoongArch::XVSLT_DU:
6379 case LoongArch::XVSLT_H:
6380 case LoongArch::XVSLT_HU:
6381 case LoongArch::XVSLT_W:
6382 case LoongArch::XVSLT_WU:
6383 case LoongArch::XVSRAN_B_H:
6384 case LoongArch::XVSRAN_H_W:
6385 case LoongArch::XVSRAN_W_D:
6386 case LoongArch::XVSRARN_B_H:
6387 case LoongArch::XVSRARN_H_W:
6388 case LoongArch::XVSRARN_W_D:
6389 case LoongArch::XVSRAR_B:
6390 case LoongArch::XVSRAR_D:
6391 case LoongArch::XVSRAR_H:
6392 case LoongArch::XVSRAR_W:
6393 case LoongArch::XVSRA_B:
6394 case LoongArch::XVSRA_D:
6395 case LoongArch::XVSRA_H:
6396 case LoongArch::XVSRA_W:
6397 case LoongArch::XVSRLN_B_H:
6398 case LoongArch::XVSRLN_H_W:
6399 case LoongArch::XVSRLN_W_D:
6400 case LoongArch::XVSRLRN_B_H:
6401 case LoongArch::XVSRLRN_H_W:
6402 case LoongArch::XVSRLRN_W_D:
6403 case LoongArch::XVSRLR_B:
6404 case LoongArch::XVSRLR_D:
6405 case LoongArch::XVSRLR_H:
6406 case LoongArch::XVSRLR_W:
6407 case LoongArch::XVSRL_B:
6408 case LoongArch::XVSRL_D:
6409 case LoongArch::XVSRL_H:
6410 case LoongArch::XVSRL_W:
6411 case LoongArch::XVSSRAN_BU_H:
6412 case LoongArch::XVSSRAN_B_H:
6413 case LoongArch::XVSSRAN_HU_W:
6414 case LoongArch::XVSSRAN_H_W:
6415 case LoongArch::XVSSRAN_WU_D:
6416 case LoongArch::XVSSRAN_W_D:
6417 case LoongArch::XVSSRARN_BU_H:
6418 case LoongArch::XVSSRARN_B_H:
6419 case LoongArch::XVSSRARN_HU_W:
6420 case LoongArch::XVSSRARN_H_W:
6421 case LoongArch::XVSSRARN_WU_D:
6422 case LoongArch::XVSSRARN_W_D:
6423 case LoongArch::XVSSRLN_BU_H:
6424 case LoongArch::XVSSRLN_B_H:
6425 case LoongArch::XVSSRLN_HU_W:
6426 case LoongArch::XVSSRLN_H_W:
6427 case LoongArch::XVSSRLN_WU_D:
6428 case LoongArch::XVSSRLN_W_D:
6429 case LoongArch::XVSSRLRN_BU_H:
6430 case LoongArch::XVSSRLRN_B_H:
6431 case LoongArch::XVSSRLRN_HU_W:
6432 case LoongArch::XVSSRLRN_H_W:
6433 case LoongArch::XVSSRLRN_WU_D:
6434 case LoongArch::XVSSRLRN_W_D:
6435 case LoongArch::XVSSUB_B:
6436 case LoongArch::XVSSUB_BU:
6437 case LoongArch::XVSSUB_D:
6438 case LoongArch::XVSSUB_DU:
6439 case LoongArch::XVSSUB_H:
6440 case LoongArch::XVSSUB_HU:
6441 case LoongArch::XVSSUB_W:
6442 case LoongArch::XVSSUB_WU:
6443 case LoongArch::XVSUBWEV_D_W:
6444 case LoongArch::XVSUBWEV_D_WU:
6445 case LoongArch::XVSUBWEV_H_B:
6446 case LoongArch::XVSUBWEV_H_BU:
6447 case LoongArch::XVSUBWEV_Q_D:
6448 case LoongArch::XVSUBWEV_Q_DU:
6449 case LoongArch::XVSUBWEV_W_H:
6450 case LoongArch::XVSUBWEV_W_HU:
6451 case LoongArch::XVSUBWOD_D_W:
6452 case LoongArch::XVSUBWOD_D_WU:
6453 case LoongArch::XVSUBWOD_H_B:
6454 case LoongArch::XVSUBWOD_H_BU:
6455 case LoongArch::XVSUBWOD_Q_D:
6456 case LoongArch::XVSUBWOD_Q_DU:
6457 case LoongArch::XVSUBWOD_W_H:
6458 case LoongArch::XVSUBWOD_W_HU:
6459 case LoongArch::XVSUB_B:
6460 case LoongArch::XVSUB_D:
6461 case LoongArch::XVSUB_H:
6462 case LoongArch::XVSUB_Q:
6463 case LoongArch::XVSUB_W:
6464 case LoongArch::XVXOR_V: {
6465 // op: xk
6466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6467 op &= UINT64_C(31);
6468 op <<= 10;
6469 Value |= op;
6470 // op: xj
6471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6472 op &= UINT64_C(31);
6473 op <<= 5;
6474 Value |= op;
6475 // op: xd
6476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6477 op &= UINT64_C(31);
6478 Value |= op;
6479 break;
6480 }
6481 case LoongArch::XVFRSTP_B:
6482 case LoongArch::XVFRSTP_H:
6483 case LoongArch::XVMADDWEV_D_W:
6484 case LoongArch::XVMADDWEV_D_WU:
6485 case LoongArch::XVMADDWEV_D_WU_W:
6486 case LoongArch::XVMADDWEV_H_B:
6487 case LoongArch::XVMADDWEV_H_BU:
6488 case LoongArch::XVMADDWEV_H_BU_B:
6489 case LoongArch::XVMADDWEV_Q_D:
6490 case LoongArch::XVMADDWEV_Q_DU:
6491 case LoongArch::XVMADDWEV_Q_DU_D:
6492 case LoongArch::XVMADDWEV_W_H:
6493 case LoongArch::XVMADDWEV_W_HU:
6494 case LoongArch::XVMADDWEV_W_HU_H:
6495 case LoongArch::XVMADDWOD_D_W:
6496 case LoongArch::XVMADDWOD_D_WU:
6497 case LoongArch::XVMADDWOD_D_WU_W:
6498 case LoongArch::XVMADDWOD_H_B:
6499 case LoongArch::XVMADDWOD_H_BU:
6500 case LoongArch::XVMADDWOD_H_BU_B:
6501 case LoongArch::XVMADDWOD_Q_D:
6502 case LoongArch::XVMADDWOD_Q_DU:
6503 case LoongArch::XVMADDWOD_Q_DU_D:
6504 case LoongArch::XVMADDWOD_W_H:
6505 case LoongArch::XVMADDWOD_W_HU:
6506 case LoongArch::XVMADDWOD_W_HU_H:
6507 case LoongArch::XVMADD_B:
6508 case LoongArch::XVMADD_D:
6509 case LoongArch::XVMADD_H:
6510 case LoongArch::XVMADD_W:
6511 case LoongArch::XVMSUB_B:
6512 case LoongArch::XVMSUB_D:
6513 case LoongArch::XVMSUB_H:
6514 case LoongArch::XVMSUB_W:
6515 case LoongArch::XVSHUF_D:
6516 case LoongArch::XVSHUF_H:
6517 case LoongArch::XVSHUF_W: {
6518 // op: xk
6519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6520 op &= UINT64_C(31);
6521 op <<= 10;
6522 Value |= op;
6523 // op: xj
6524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6525 op &= UINT64_C(31);
6526 op <<= 5;
6527 Value |= op;
6528 // op: xd
6529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6530 op &= UINT64_C(31);
6531 Value |= op;
6532 break;
6533 }
6534 default:
6535 std::string msg;
6536 raw_string_ostream Msg(msg);
6537 Msg << "Not supported instr: " << MI;
6538 report_fatal_error(reason: Msg.str().c_str());
6539 }
6540 return Value;
6541}
6542
6543#ifdef GET_OPERAND_BIT_OFFSET
6544#undef GET_OPERAND_BIT_OFFSET
6545
6546uint32_t LoongArchMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
6547 unsigned OpNum,
6548 const MCSubtargetInfo &STI) const {
6549 switch (MI.getOpcode()) {
6550 case LoongArch::ERTN:
6551 case LoongArch::GTLBFLUSH:
6552 case LoongArch::TLBCLR:
6553 case LoongArch::TLBFILL:
6554 case LoongArch::TLBFLUSH:
6555 case LoongArch::TLBRD:
6556 case LoongArch::TLBSRCH:
6557 case LoongArch::TLBWR:
6558 case LoongArch::X86CLRTM:
6559 case LoongArch::X86DECTOP:
6560 case LoongArch::X86INCTOP:
6561 case LoongArch::X86SETTM: {
6562 break;
6563 }
6564 case LoongArch::SET_CFR_FALSE:
6565 case LoongArch::SET_CFR_TRUE: {
6566 switch (OpNum) {
6567 case 0:
6568 // op: cd
6569 return 0;
6570 }
6571 break;
6572 }
6573 case LoongArch::BREAK:
6574 case LoongArch::DBAR:
6575 case LoongArch::DBCL:
6576 case LoongArch::HVCL:
6577 case LoongArch::IBAR:
6578 case LoongArch::IDLE:
6579 case LoongArch::SYSCALL: {
6580 switch (OpNum) {
6581 case 0:
6582 // op: imm15
6583 return 0;
6584 }
6585 break;
6586 }
6587 case LoongArch::JISCR0:
6588 case LoongArch::JISCR1: {
6589 switch (OpNum) {
6590 case 0:
6591 // op: imm21
6592 return 0;
6593 }
6594 break;
6595 }
6596 case LoongArch::B:
6597 case LoongArch::BL: {
6598 switch (OpNum) {
6599 case 0:
6600 // op: imm26
6601 return 0;
6602 }
6603 break;
6604 }
6605 case LoongArch::X86MTTOP: {
6606 switch (OpNum) {
6607 case 0:
6608 // op: ptr
6609 return 5;
6610 }
6611 break;
6612 }
6613 case LoongArch::X86MFTOP: {
6614 switch (OpNum) {
6615 case 0:
6616 // op: rd
6617 return 0;
6618 }
6619 break;
6620 }
6621 case LoongArch::X86DEC_B:
6622 case LoongArch::X86DEC_D:
6623 case LoongArch::X86DEC_H:
6624 case LoongArch::X86DEC_W:
6625 case LoongArch::X86INC_B:
6626 case LoongArch::X86INC_D:
6627 case LoongArch::X86INC_H:
6628 case LoongArch::X86INC_W: {
6629 switch (OpNum) {
6630 case 0:
6631 // op: rj
6632 return 5;
6633 }
6634 break;
6635 }
6636 case LoongArch::INVTLB: {
6637 switch (OpNum) {
6638 case 0:
6639 // op: rk
6640 return 10;
6641 case 1:
6642 // op: rj
6643 return 5;
6644 case 2:
6645 // op: op
6646 return 0;
6647 }
6648 break;
6649 }
6650 case LoongArch::CSRRD:
6651 case LoongArch::GCSRRD: {
6652 switch (OpNum) {
6653 case 1:
6654 // op: csr_num
6655 return 10;
6656 case 0:
6657 // op: rd
6658 return 0;
6659 }
6660 break;
6661 }
6662 case LoongArch::FABS_D:
6663 case LoongArch::FABS_S:
6664 case LoongArch::FCLASS_D:
6665 case LoongArch::FCLASS_S:
6666 case LoongArch::FCVT_D_S:
6667 case LoongArch::FCVT_LD_D:
6668 case LoongArch::FCVT_S_D:
6669 case LoongArch::FCVT_UD_D:
6670 case LoongArch::FFINT_D_L:
6671 case LoongArch::FFINT_D_W:
6672 case LoongArch::FFINT_S_L:
6673 case LoongArch::FFINT_S_W:
6674 case LoongArch::FLOGB_D:
6675 case LoongArch::FLOGB_S:
6676 case LoongArch::FNEG_D:
6677 case LoongArch::FNEG_S:
6678 case LoongArch::FRECIPE_D:
6679 case LoongArch::FRECIPE_S:
6680 case LoongArch::FRECIP_D:
6681 case LoongArch::FRECIP_S:
6682 case LoongArch::FRINT_D:
6683 case LoongArch::FRINT_S:
6684 case LoongArch::FRSQRTE_D:
6685 case LoongArch::FRSQRTE_S:
6686 case LoongArch::FRSQRT_D:
6687 case LoongArch::FRSQRT_S:
6688 case LoongArch::FSQRT_D:
6689 case LoongArch::FSQRT_S:
6690 case LoongArch::FTINTRM_L_D:
6691 case LoongArch::FTINTRM_L_S:
6692 case LoongArch::FTINTRM_W_D:
6693 case LoongArch::FTINTRM_W_S:
6694 case LoongArch::FTINTRNE_L_D:
6695 case LoongArch::FTINTRNE_L_S:
6696 case LoongArch::FTINTRNE_W_D:
6697 case LoongArch::FTINTRNE_W_S:
6698 case LoongArch::FTINTRP_L_D:
6699 case LoongArch::FTINTRP_L_S:
6700 case LoongArch::FTINTRP_W_D:
6701 case LoongArch::FTINTRP_W_S:
6702 case LoongArch::FTINTRZ_L_D:
6703 case LoongArch::FTINTRZ_L_S:
6704 case LoongArch::FTINTRZ_W_D:
6705 case LoongArch::FTINTRZ_W_S:
6706 case LoongArch::FTINT_L_D:
6707 case LoongArch::FTINT_L_S:
6708 case LoongArch::FTINT_W_D:
6709 case LoongArch::FTINT_W_S: {
6710 switch (OpNum) {
6711 case 1:
6712 // op: fj
6713 return 5;
6714 case 0:
6715 // op: fd
6716 return 0;
6717 }
6718 break;
6719 }
6720 case LoongArch::VLDI: {
6721 switch (OpNum) {
6722 case 1:
6723 // op: imm13
6724 return 5;
6725 case 0:
6726 // op: vd
6727 return 0;
6728 }
6729 break;
6730 }
6731 case LoongArch::XVLDI: {
6732 switch (OpNum) {
6733 case 1:
6734 // op: imm13
6735 return 5;
6736 case 0:
6737 // op: xd
6738 return 0;
6739 }
6740 break;
6741 }
6742 case LoongArch::LU12I_W:
6743 case LoongArch::PCADDI:
6744 case LoongArch::PCADDU12I:
6745 case LoongArch::PCADDU18I:
6746 case LoongArch::PCALAU12I: {
6747 switch (OpNum) {
6748 case 1:
6749 // op: imm20
6750 return 5;
6751 case 0:
6752 // op: rd
6753 return 0;
6754 }
6755 break;
6756 }
6757 case LoongArch::BCEQZ:
6758 case LoongArch::BCNEZ: {
6759 switch (OpNum) {
6760 case 1:
6761 // op: imm21
6762 return 0;
6763 case 0:
6764 // op: cj
6765 return 5;
6766 }
6767 break;
6768 }
6769 case LoongArch::BEQZ:
6770 case LoongArch::BNEZ: {
6771 switch (OpNum) {
6772 case 1:
6773 // op: imm21
6774 return 0;
6775 case 0:
6776 // op: rj
6777 return 5;
6778 }
6779 break;
6780 }
6781 case LoongArch::X86RCLI_B:
6782 case LoongArch::X86RCRI_B:
6783 case LoongArch::X86ROTLI_B:
6784 case LoongArch::X86ROTRI_B:
6785 case LoongArch::X86SLLI_B:
6786 case LoongArch::X86SRAI_B:
6787 case LoongArch::X86SRLI_B: {
6788 switch (OpNum) {
6789 case 1:
6790 // op: imm3
6791 return 10;
6792 case 0:
6793 // op: rj
6794 return 5;
6795 }
6796 break;
6797 }
6798 case LoongArch::SETARMJ:
6799 case LoongArch::SETX86J: {
6800 switch (OpNum) {
6801 case 1:
6802 // op: imm4
6803 return 10;
6804 case 0:
6805 // op: rd
6806 return 0;
6807 }
6808 break;
6809 }
6810 case LoongArch::ARMMOV_D:
6811 case LoongArch::ARMMOV_W:
6812 case LoongArch::ARMNOT_W:
6813 case LoongArch::ARMRRX_W:
6814 case LoongArch::X86RCLI_H:
6815 case LoongArch::X86RCRI_H:
6816 case LoongArch::X86ROTLI_H:
6817 case LoongArch::X86ROTRI_H:
6818 case LoongArch::X86SLLI_H:
6819 case LoongArch::X86SRAI_H:
6820 case LoongArch::X86SRLI_H: {
6821 switch (OpNum) {
6822 case 1:
6823 // op: imm4
6824 return 10;
6825 case 0:
6826 // op: rj
6827 return 5;
6828 }
6829 break;
6830 }
6831 case LoongArch::ARMROTRI_W:
6832 case LoongArch::ARMSLLI_W:
6833 case LoongArch::ARMSRAI_W:
6834 case LoongArch::ARMSRLI_W: {
6835 switch (OpNum) {
6836 case 1:
6837 // op: imm5
6838 return 10;
6839 case 0:
6840 // op: rj
6841 return 5;
6842 case 2:
6843 // op: imm4
6844 return 0;
6845 }
6846 break;
6847 }
6848 case LoongArch::X86RCLI_W:
6849 case LoongArch::X86RCRI_W:
6850 case LoongArch::X86ROTLI_W:
6851 case LoongArch::X86ROTRI_W:
6852 case LoongArch::X86SLLI_W:
6853 case LoongArch::X86SRAI_W:
6854 case LoongArch::X86SRLI_W: {
6855 switch (OpNum) {
6856 case 1:
6857 // op: imm5
6858 return 10;
6859 case 0:
6860 // op: rj
6861 return 5;
6862 }
6863 break;
6864 }
6865 case LoongArch::X86RCLI_D:
6866 case LoongArch::X86RCRI_D:
6867 case LoongArch::X86ROTLI_D:
6868 case LoongArch::X86ROTRI_D:
6869 case LoongArch::X86SLLI_D:
6870 case LoongArch::X86SRAI_D:
6871 case LoongArch::X86SRLI_D: {
6872 switch (OpNum) {
6873 case 1:
6874 // op: imm6
6875 return 10;
6876 case 0:
6877 // op: rj
6878 return 5;
6879 }
6880 break;
6881 }
6882 case LoongArch::ARMMFFLAG:
6883 case LoongArch::ARMMTFLAG:
6884 case LoongArch::X86MFFLAG:
6885 case LoongArch::X86MTFLAG: {
6886 switch (OpNum) {
6887 case 1:
6888 // op: imm8
6889 return 10;
6890 case 0:
6891 // op: rd
6892 return 0;
6893 }
6894 break;
6895 }
6896 case LoongArch::BITREV_4B:
6897 case LoongArch::BITREV_8B:
6898 case LoongArch::BITREV_D:
6899 case LoongArch::BITREV_W:
6900 case LoongArch::CLO_D:
6901 case LoongArch::CLO_W:
6902 case LoongArch::CLZ_D:
6903 case LoongArch::CLZ_W:
6904 case LoongArch::CPUCFG:
6905 case LoongArch::CTO_D:
6906 case LoongArch::CTO_W:
6907 case LoongArch::CTZ_D:
6908 case LoongArch::CTZ_W:
6909 case LoongArch::EXT_W_B:
6910 case LoongArch::EXT_W_H:
6911 case LoongArch::IOCSRRD_B:
6912 case LoongArch::IOCSRRD_D:
6913 case LoongArch::IOCSRRD_H:
6914 case LoongArch::IOCSRRD_W:
6915 case LoongArch::IOCSRWR_B:
6916 case LoongArch::IOCSRWR_D:
6917 case LoongArch::IOCSRWR_H:
6918 case LoongArch::IOCSRWR_W:
6919 case LoongArch::LLACQ_D:
6920 case LoongArch::LLACQ_W:
6921 case LoongArch::RDTIMEH_W:
6922 case LoongArch::RDTIMEL_W:
6923 case LoongArch::RDTIME_D:
6924 case LoongArch::REVB_2H:
6925 case LoongArch::REVB_2W:
6926 case LoongArch::REVB_4H:
6927 case LoongArch::REVB_D:
6928 case LoongArch::REVH_2W:
6929 case LoongArch::REVH_D:
6930 case LoongArch::SETX86LOOPE:
6931 case LoongArch::SETX86LOOPNE: {
6932 switch (OpNum) {
6933 case 1:
6934 // op: rj
6935 return 5;
6936 case 0:
6937 // op: rd
6938 return 0;
6939 }
6940 break;
6941 }
6942 case LoongArch::MOVGR2SCR: {
6943 switch (OpNum) {
6944 case 1:
6945 // op: rj
6946 return 5;
6947 case 0:
6948 // op: sd
6949 return 0;
6950 }
6951 break;
6952 }
6953 case LoongArch::VREPLGR2VR_B:
6954 case LoongArch::VREPLGR2VR_D:
6955 case LoongArch::VREPLGR2VR_H:
6956 case LoongArch::VREPLGR2VR_W: {
6957 switch (OpNum) {
6958 case 1:
6959 // op: rj
6960 return 5;
6961 case 0:
6962 // op: vd
6963 return 0;
6964 }
6965 break;
6966 }
6967 case LoongArch::XVREPLGR2VR_B:
6968 case LoongArch::XVREPLGR2VR_D:
6969 case LoongArch::XVREPLGR2VR_H:
6970 case LoongArch::XVREPLGR2VR_W: {
6971 switch (OpNum) {
6972 case 1:
6973 // op: rj
6974 return 5;
6975 case 0:
6976 // op: xd
6977 return 0;
6978 }
6979 break;
6980 }
6981 case LoongArch::ASRTGT_D:
6982 case LoongArch::ASRTLE_D:
6983 case LoongArch::X86ADC_B:
6984 case LoongArch::X86ADC_D:
6985 case LoongArch::X86ADC_H:
6986 case LoongArch::X86ADC_W:
6987 case LoongArch::X86ADD_B:
6988 case LoongArch::X86ADD_D:
6989 case LoongArch::X86ADD_DU:
6990 case LoongArch::X86ADD_H:
6991 case LoongArch::X86ADD_W:
6992 case LoongArch::X86ADD_WU:
6993 case LoongArch::X86AND_B:
6994 case LoongArch::X86AND_D:
6995 case LoongArch::X86AND_H:
6996 case LoongArch::X86AND_W:
6997 case LoongArch::X86MUL_B:
6998 case LoongArch::X86MUL_BU:
6999 case LoongArch::X86MUL_D:
7000 case LoongArch::X86MUL_DU:
7001 case LoongArch::X86MUL_H:
7002 case LoongArch::X86MUL_HU:
7003 case LoongArch::X86MUL_W:
7004 case LoongArch::X86MUL_WU:
7005 case LoongArch::X86OR_B:
7006 case LoongArch::X86OR_D:
7007 case LoongArch::X86OR_H:
7008 case LoongArch::X86OR_W:
7009 case LoongArch::X86RCL_B:
7010 case LoongArch::X86RCL_D:
7011 case LoongArch::X86RCL_H:
7012 case LoongArch::X86RCL_W:
7013 case LoongArch::X86RCR_B:
7014 case LoongArch::X86RCR_D:
7015 case LoongArch::X86RCR_H:
7016 case LoongArch::X86RCR_W:
7017 case LoongArch::X86ROTL_B:
7018 case LoongArch::X86ROTL_D:
7019 case LoongArch::X86ROTL_H:
7020 case LoongArch::X86ROTL_W:
7021 case LoongArch::X86ROTR_B:
7022 case LoongArch::X86ROTR_D:
7023 case LoongArch::X86ROTR_H:
7024 case LoongArch::X86ROTR_W:
7025 case LoongArch::X86SBC_B:
7026 case LoongArch::X86SBC_D:
7027 case LoongArch::X86SBC_H:
7028 case LoongArch::X86SBC_W:
7029 case LoongArch::X86SLL_B:
7030 case LoongArch::X86SLL_D:
7031 case LoongArch::X86SLL_H:
7032 case LoongArch::X86SLL_W:
7033 case LoongArch::X86SRA_B:
7034 case LoongArch::X86SRA_D:
7035 case LoongArch::X86SRA_H:
7036 case LoongArch::X86SRA_W:
7037 case LoongArch::X86SRL_B:
7038 case LoongArch::X86SRL_D:
7039 case LoongArch::X86SRL_H:
7040 case LoongArch::X86SRL_W:
7041 case LoongArch::X86SUB_B:
7042 case LoongArch::X86SUB_D:
7043 case LoongArch::X86SUB_DU:
7044 case LoongArch::X86SUB_H:
7045 case LoongArch::X86SUB_W:
7046 case LoongArch::X86SUB_WU:
7047 case LoongArch::X86XOR_B:
7048 case LoongArch::X86XOR_D:
7049 case LoongArch::X86XOR_H:
7050 case LoongArch::X86XOR_W: {
7051 switch (OpNum) {
7052 case 1:
7053 // op: rk
7054 return 10;
7055 case 0:
7056 // op: rj
7057 return 5;
7058 }
7059 break;
7060 }
7061 case LoongArch::AMADD_B:
7062 case LoongArch::AMADD_D:
7063 case LoongArch::AMADD_H:
7064 case LoongArch::AMADD_W:
7065 case LoongArch::AMADD__DB_B:
7066 case LoongArch::AMADD__DB_D:
7067 case LoongArch::AMADD__DB_H:
7068 case LoongArch::AMADD__DB_W:
7069 case LoongArch::AMAND_D:
7070 case LoongArch::AMAND_W:
7071 case LoongArch::AMAND__DB_D:
7072 case LoongArch::AMAND__DB_W:
7073 case LoongArch::AMCAS_B:
7074 case LoongArch::AMCAS_D:
7075 case LoongArch::AMCAS_H:
7076 case LoongArch::AMCAS_W:
7077 case LoongArch::AMCAS__DB_B:
7078 case LoongArch::AMCAS__DB_D:
7079 case LoongArch::AMCAS__DB_H:
7080 case LoongArch::AMCAS__DB_W:
7081 case LoongArch::AMMAX_D:
7082 case LoongArch::AMMAX_DU:
7083 case LoongArch::AMMAX_W:
7084 case LoongArch::AMMAX_WU:
7085 case LoongArch::AMMAX__DB_D:
7086 case LoongArch::AMMAX__DB_DU:
7087 case LoongArch::AMMAX__DB_W:
7088 case LoongArch::AMMAX__DB_WU:
7089 case LoongArch::AMMIN_D:
7090 case LoongArch::AMMIN_DU:
7091 case LoongArch::AMMIN_W:
7092 case LoongArch::AMMIN_WU:
7093 case LoongArch::AMMIN__DB_D:
7094 case LoongArch::AMMIN__DB_DU:
7095 case LoongArch::AMMIN__DB_W:
7096 case LoongArch::AMMIN__DB_WU:
7097 case LoongArch::AMOR_D:
7098 case LoongArch::AMOR_W:
7099 case LoongArch::AMOR__DB_D:
7100 case LoongArch::AMOR__DB_W:
7101 case LoongArch::AMSWAP_B:
7102 case LoongArch::AMSWAP_D:
7103 case LoongArch::AMSWAP_H:
7104 case LoongArch::AMSWAP_W:
7105 case LoongArch::AMSWAP__DB_B:
7106 case LoongArch::AMSWAP__DB_D:
7107 case LoongArch::AMSWAP__DB_H:
7108 case LoongArch::AMSWAP__DB_W:
7109 case LoongArch::AMXOR_D:
7110 case LoongArch::AMXOR_W:
7111 case LoongArch::AMXOR__DB_D:
7112 case LoongArch::AMXOR__DB_W: {
7113 switch (OpNum) {
7114 case 1:
7115 // op: rk
7116 return 10;
7117 case 2:
7118 // op: rj
7119 return 5;
7120 case 0:
7121 // op: rd
7122 return 0;
7123 }
7124 break;
7125 }
7126 case LoongArch::LDPTE: {
7127 switch (OpNum) {
7128 case 1:
7129 // op: seq
7130 return 10;
7131 case 0:
7132 // op: rj
7133 return 5;
7134 }
7135 break;
7136 }
7137 case LoongArch::MOVSCR2GR: {
7138 switch (OpNum) {
7139 case 1:
7140 // op: sj
7141 return 5;
7142 case 0:
7143 // op: rd
7144 return 0;
7145 }
7146 break;
7147 }
7148 case LoongArch::FMOV_D:
7149 case LoongArch::FMOV_S:
7150 case LoongArch::MOVCF2FR_xS:
7151 case LoongArch::MOVCF2GR:
7152 case LoongArch::MOVFCSR2GR:
7153 case LoongArch::MOVFR2CF_xS:
7154 case LoongArch::MOVFR2GR_D:
7155 case LoongArch::MOVFR2GR_S:
7156 case LoongArch::MOVFR2GR_S_64:
7157 case LoongArch::MOVFRH2GR_S:
7158 case LoongArch::MOVGR2CF:
7159 case LoongArch::MOVGR2FCSR:
7160 case LoongArch::MOVGR2FR_D:
7161 case LoongArch::MOVGR2FR_W:
7162 case LoongArch::MOVGR2FR_W_64: {
7163 switch (OpNum) {
7164 case 1:
7165 // op: src
7166 return 5;
7167 case 0:
7168 // op: dst
7169 return 0;
7170 }
7171 break;
7172 }
7173 case LoongArch::VSETALLNEZ_B:
7174 case LoongArch::VSETALLNEZ_D:
7175 case LoongArch::VSETALLNEZ_H:
7176 case LoongArch::VSETALLNEZ_W:
7177 case LoongArch::VSETANYEQZ_B:
7178 case LoongArch::VSETANYEQZ_D:
7179 case LoongArch::VSETANYEQZ_H:
7180 case LoongArch::VSETANYEQZ_W:
7181 case LoongArch::VSETEQZ_V:
7182 case LoongArch::VSETNEZ_V: {
7183 switch (OpNum) {
7184 case 1:
7185 // op: vj
7186 return 5;
7187 case 0:
7188 // op: cd
7189 return 0;
7190 }
7191 break;
7192 }
7193 case LoongArch::VCLO_B:
7194 case LoongArch::VCLO_D:
7195 case LoongArch::VCLO_H:
7196 case LoongArch::VCLO_W:
7197 case LoongArch::VCLZ_B:
7198 case LoongArch::VCLZ_D:
7199 case LoongArch::VCLZ_H:
7200 case LoongArch::VCLZ_W:
7201 case LoongArch::VEXTH_DU_WU:
7202 case LoongArch::VEXTH_D_W:
7203 case LoongArch::VEXTH_HU_BU:
7204 case LoongArch::VEXTH_H_B:
7205 case LoongArch::VEXTH_QU_DU:
7206 case LoongArch::VEXTH_Q_D:
7207 case LoongArch::VEXTH_WU_HU:
7208 case LoongArch::VEXTH_W_H:
7209 case LoongArch::VEXTL_QU_DU:
7210 case LoongArch::VEXTL_Q_D:
7211 case LoongArch::VFCLASS_D:
7212 case LoongArch::VFCLASS_S:
7213 case LoongArch::VFCVTH_D_S:
7214 case LoongArch::VFCVTH_S_H:
7215 case LoongArch::VFCVTL_D_S:
7216 case LoongArch::VFCVTL_S_H:
7217 case LoongArch::VFFINTH_D_W:
7218 case LoongArch::VFFINTL_D_W:
7219 case LoongArch::VFFINT_D_L:
7220 case LoongArch::VFFINT_D_LU:
7221 case LoongArch::VFFINT_S_W:
7222 case LoongArch::VFFINT_S_WU:
7223 case LoongArch::VFLOGB_D:
7224 case LoongArch::VFLOGB_S:
7225 case LoongArch::VFRECIPE_D:
7226 case LoongArch::VFRECIPE_S:
7227 case LoongArch::VFRECIP_D:
7228 case LoongArch::VFRECIP_S:
7229 case LoongArch::VFRINTRM_D:
7230 case LoongArch::VFRINTRM_S:
7231 case LoongArch::VFRINTRNE_D:
7232 case LoongArch::VFRINTRNE_S:
7233 case LoongArch::VFRINTRP_D:
7234 case LoongArch::VFRINTRP_S:
7235 case LoongArch::VFRINTRZ_D:
7236 case LoongArch::VFRINTRZ_S:
7237 case LoongArch::VFRINT_D:
7238 case LoongArch::VFRINT_S:
7239 case LoongArch::VFRSQRTE_D:
7240 case LoongArch::VFRSQRTE_S:
7241 case LoongArch::VFRSQRT_D:
7242 case LoongArch::VFRSQRT_S:
7243 case LoongArch::VFSQRT_D:
7244 case LoongArch::VFSQRT_S:
7245 case LoongArch::VFTINTH_L_S:
7246 case LoongArch::VFTINTL_L_S:
7247 case LoongArch::VFTINTRMH_L_S:
7248 case LoongArch::VFTINTRML_L_S:
7249 case LoongArch::VFTINTRM_L_D:
7250 case LoongArch::VFTINTRM_W_S:
7251 case LoongArch::VFTINTRNEH_L_S:
7252 case LoongArch::VFTINTRNEL_L_S:
7253 case LoongArch::VFTINTRNE_L_D:
7254 case LoongArch::VFTINTRNE_W_S:
7255 case LoongArch::VFTINTRPH_L_S:
7256 case LoongArch::VFTINTRPL_L_S:
7257 case LoongArch::VFTINTRP_L_D:
7258 case LoongArch::VFTINTRP_W_S:
7259 case LoongArch::VFTINTRZH_L_S:
7260 case LoongArch::VFTINTRZL_L_S:
7261 case LoongArch::VFTINTRZ_LU_D:
7262 case LoongArch::VFTINTRZ_L_D:
7263 case LoongArch::VFTINTRZ_WU_S:
7264 case LoongArch::VFTINTRZ_W_S:
7265 case LoongArch::VFTINT_LU_D:
7266 case LoongArch::VFTINT_L_D:
7267 case LoongArch::VFTINT_WU_S:
7268 case LoongArch::VFTINT_W_S:
7269 case LoongArch::VMSKGEZ_B:
7270 case LoongArch::VMSKLTZ_B:
7271 case LoongArch::VMSKLTZ_D:
7272 case LoongArch::VMSKLTZ_H:
7273 case LoongArch::VMSKLTZ_W:
7274 case LoongArch::VMSKNZ_B:
7275 case LoongArch::VNEG_B:
7276 case LoongArch::VNEG_D:
7277 case LoongArch::VNEG_H:
7278 case LoongArch::VNEG_W:
7279 case LoongArch::VPCNT_B:
7280 case LoongArch::VPCNT_D:
7281 case LoongArch::VPCNT_H:
7282 case LoongArch::VPCNT_W: {
7283 switch (OpNum) {
7284 case 1:
7285 // op: vj
7286 return 5;
7287 case 0:
7288 // op: vd
7289 return 0;
7290 }
7291 break;
7292 }
7293 case LoongArch::XVSETALLNEZ_B:
7294 case LoongArch::XVSETALLNEZ_D:
7295 case LoongArch::XVSETALLNEZ_H:
7296 case LoongArch::XVSETALLNEZ_W:
7297 case LoongArch::XVSETANYEQZ_B:
7298 case LoongArch::XVSETANYEQZ_D:
7299 case LoongArch::XVSETANYEQZ_H:
7300 case LoongArch::XVSETANYEQZ_W:
7301 case LoongArch::XVSETEQZ_V:
7302 case LoongArch::XVSETNEZ_V: {
7303 switch (OpNum) {
7304 case 1:
7305 // op: xj
7306 return 5;
7307 case 0:
7308 // op: cd
7309 return 0;
7310 }
7311 break;
7312 }
7313 case LoongArch::VEXT2XV_DU_BU:
7314 case LoongArch::VEXT2XV_DU_HU:
7315 case LoongArch::VEXT2XV_DU_WU:
7316 case LoongArch::VEXT2XV_D_B:
7317 case LoongArch::VEXT2XV_D_H:
7318 case LoongArch::VEXT2XV_D_W:
7319 case LoongArch::VEXT2XV_HU_BU:
7320 case LoongArch::VEXT2XV_H_B:
7321 case LoongArch::VEXT2XV_WU_BU:
7322 case LoongArch::VEXT2XV_WU_HU:
7323 case LoongArch::VEXT2XV_W_B:
7324 case LoongArch::VEXT2XV_W_H:
7325 case LoongArch::XVCLO_B:
7326 case LoongArch::XVCLO_D:
7327 case LoongArch::XVCLO_H:
7328 case LoongArch::XVCLO_W:
7329 case LoongArch::XVCLZ_B:
7330 case LoongArch::XVCLZ_D:
7331 case LoongArch::XVCLZ_H:
7332 case LoongArch::XVCLZ_W:
7333 case LoongArch::XVEXTH_DU_WU:
7334 case LoongArch::XVEXTH_D_W:
7335 case LoongArch::XVEXTH_HU_BU:
7336 case LoongArch::XVEXTH_H_B:
7337 case LoongArch::XVEXTH_QU_DU:
7338 case LoongArch::XVEXTH_Q_D:
7339 case LoongArch::XVEXTH_WU_HU:
7340 case LoongArch::XVEXTH_W_H:
7341 case LoongArch::XVEXTL_QU_DU:
7342 case LoongArch::XVEXTL_Q_D:
7343 case LoongArch::XVFCLASS_D:
7344 case LoongArch::XVFCLASS_S:
7345 case LoongArch::XVFCVTH_D_S:
7346 case LoongArch::XVFCVTH_S_H:
7347 case LoongArch::XVFCVTL_D_S:
7348 case LoongArch::XVFCVTL_S_H:
7349 case LoongArch::XVFFINTH_D_W:
7350 case LoongArch::XVFFINTL_D_W:
7351 case LoongArch::XVFFINT_D_L:
7352 case LoongArch::XVFFINT_D_LU:
7353 case LoongArch::XVFFINT_S_W:
7354 case LoongArch::XVFFINT_S_WU:
7355 case LoongArch::XVFLOGB_D:
7356 case LoongArch::XVFLOGB_S:
7357 case LoongArch::XVFRECIPE_D:
7358 case LoongArch::XVFRECIPE_S:
7359 case LoongArch::XVFRECIP_D:
7360 case LoongArch::XVFRECIP_S:
7361 case LoongArch::XVFRINTRM_D:
7362 case LoongArch::XVFRINTRM_S:
7363 case LoongArch::XVFRINTRNE_D:
7364 case LoongArch::XVFRINTRNE_S:
7365 case LoongArch::XVFRINTRP_D:
7366 case LoongArch::XVFRINTRP_S:
7367 case LoongArch::XVFRINTRZ_D:
7368 case LoongArch::XVFRINTRZ_S:
7369 case LoongArch::XVFRINT_D:
7370 case LoongArch::XVFRINT_S:
7371 case LoongArch::XVFRSQRTE_D:
7372 case LoongArch::XVFRSQRTE_S:
7373 case LoongArch::XVFRSQRT_D:
7374 case LoongArch::XVFRSQRT_S:
7375 case LoongArch::XVFSQRT_D:
7376 case LoongArch::XVFSQRT_S:
7377 case LoongArch::XVFTINTH_L_S:
7378 case LoongArch::XVFTINTL_L_S:
7379 case LoongArch::XVFTINTRMH_L_S:
7380 case LoongArch::XVFTINTRML_L_S:
7381 case LoongArch::XVFTINTRM_L_D:
7382 case LoongArch::XVFTINTRM_W_S:
7383 case LoongArch::XVFTINTRNEH_L_S:
7384 case LoongArch::XVFTINTRNEL_L_S:
7385 case LoongArch::XVFTINTRNE_L_D:
7386 case LoongArch::XVFTINTRNE_W_S:
7387 case LoongArch::XVFTINTRPH_L_S:
7388 case LoongArch::XVFTINTRPL_L_S:
7389 case LoongArch::XVFTINTRP_L_D:
7390 case LoongArch::XVFTINTRP_W_S:
7391 case LoongArch::XVFTINTRZH_L_S:
7392 case LoongArch::XVFTINTRZL_L_S:
7393 case LoongArch::XVFTINTRZ_LU_D:
7394 case LoongArch::XVFTINTRZ_L_D:
7395 case LoongArch::XVFTINTRZ_WU_S:
7396 case LoongArch::XVFTINTRZ_W_S:
7397 case LoongArch::XVFTINT_LU_D:
7398 case LoongArch::XVFTINT_L_D:
7399 case LoongArch::XVFTINT_WU_S:
7400 case LoongArch::XVFTINT_W_S:
7401 case LoongArch::XVMSKGEZ_B:
7402 case LoongArch::XVMSKLTZ_B:
7403 case LoongArch::XVMSKLTZ_D:
7404 case LoongArch::XVMSKLTZ_H:
7405 case LoongArch::XVMSKLTZ_W:
7406 case LoongArch::XVMSKNZ_B:
7407 case LoongArch::XVNEG_B:
7408 case LoongArch::XVNEG_D:
7409 case LoongArch::XVNEG_H:
7410 case LoongArch::XVNEG_W:
7411 case LoongArch::XVPCNT_B:
7412 case LoongArch::XVPCNT_D:
7413 case LoongArch::XVPCNT_H:
7414 case LoongArch::XVPCNT_W:
7415 case LoongArch::XVREPLVE0_B:
7416 case LoongArch::XVREPLVE0_D:
7417 case LoongArch::XVREPLVE0_H:
7418 case LoongArch::XVREPLVE0_Q:
7419 case LoongArch::XVREPLVE0_W: {
7420 switch (OpNum) {
7421 case 1:
7422 // op: xj
7423 return 5;
7424 case 0:
7425 // op: xd
7426 return 0;
7427 }
7428 break;
7429 }
7430 case LoongArch::CSRWR:
7431 case LoongArch::GCSRWR: {
7432 switch (OpNum) {
7433 case 2:
7434 // op: csr_num
7435 return 10;
7436 case 1:
7437 // op: rd
7438 return 0;
7439 }
7440 break;
7441 }
7442 case LoongArch::FCMP_CAF_D:
7443 case LoongArch::FCMP_CAF_S:
7444 case LoongArch::FCMP_CEQ_D:
7445 case LoongArch::FCMP_CEQ_S:
7446 case LoongArch::FCMP_CLE_D:
7447 case LoongArch::FCMP_CLE_S:
7448 case LoongArch::FCMP_CLT_D:
7449 case LoongArch::FCMP_CLT_S:
7450 case LoongArch::FCMP_CNE_D:
7451 case LoongArch::FCMP_CNE_S:
7452 case LoongArch::FCMP_COR_D:
7453 case LoongArch::FCMP_COR_S:
7454 case LoongArch::FCMP_CUEQ_D:
7455 case LoongArch::FCMP_CUEQ_S:
7456 case LoongArch::FCMP_CULE_D:
7457 case LoongArch::FCMP_CULE_S:
7458 case LoongArch::FCMP_CULT_D:
7459 case LoongArch::FCMP_CULT_S:
7460 case LoongArch::FCMP_CUNE_D:
7461 case LoongArch::FCMP_CUNE_S:
7462 case LoongArch::FCMP_CUN_D:
7463 case LoongArch::FCMP_CUN_S:
7464 case LoongArch::FCMP_SAF_D:
7465 case LoongArch::FCMP_SAF_S:
7466 case LoongArch::FCMP_SEQ_D:
7467 case LoongArch::FCMP_SEQ_S:
7468 case LoongArch::FCMP_SLE_D:
7469 case LoongArch::FCMP_SLE_S:
7470 case LoongArch::FCMP_SLT_D:
7471 case LoongArch::FCMP_SLT_S:
7472 case LoongArch::FCMP_SNE_D:
7473 case LoongArch::FCMP_SNE_S:
7474 case LoongArch::FCMP_SOR_D:
7475 case LoongArch::FCMP_SOR_S:
7476 case LoongArch::FCMP_SUEQ_D:
7477 case LoongArch::FCMP_SUEQ_S:
7478 case LoongArch::FCMP_SULE_D:
7479 case LoongArch::FCMP_SULE_S:
7480 case LoongArch::FCMP_SULT_D:
7481 case LoongArch::FCMP_SULT_S:
7482 case LoongArch::FCMP_SUNE_D:
7483 case LoongArch::FCMP_SUNE_S:
7484 case LoongArch::FCMP_SUN_D:
7485 case LoongArch::FCMP_SUN_S: {
7486 switch (OpNum) {
7487 case 2:
7488 // op: fk
7489 return 10;
7490 case 1:
7491 // op: fj
7492 return 5;
7493 case 0:
7494 // op: cd
7495 return 0;
7496 }
7497 break;
7498 }
7499 case LoongArch::FADD_D:
7500 case LoongArch::FADD_S:
7501 case LoongArch::FCOPYSIGN_D:
7502 case LoongArch::FCOPYSIGN_S:
7503 case LoongArch::FCVT_D_LD:
7504 case LoongArch::FDIV_D:
7505 case LoongArch::FDIV_S:
7506 case LoongArch::FMAXA_D:
7507 case LoongArch::FMAXA_S:
7508 case LoongArch::FMAX_D:
7509 case LoongArch::FMAX_S:
7510 case LoongArch::FMINA_D:
7511 case LoongArch::FMINA_S:
7512 case LoongArch::FMIN_D:
7513 case LoongArch::FMIN_S:
7514 case LoongArch::FMUL_D:
7515 case LoongArch::FMUL_S:
7516 case LoongArch::FSCALEB_D:
7517 case LoongArch::FSCALEB_S:
7518 case LoongArch::FSUB_D:
7519 case LoongArch::FSUB_S: {
7520 switch (OpNum) {
7521 case 2:
7522 // op: fk
7523 return 10;
7524 case 1:
7525 // op: fj
7526 return 5;
7527 case 0:
7528 // op: fd
7529 return 0;
7530 }
7531 break;
7532 }
7533 case LoongArch::VPICKVE2GR_D:
7534 case LoongArch::VPICKVE2GR_DU: {
7535 switch (OpNum) {
7536 case 2:
7537 // op: imm1
7538 return 10;
7539 case 1:
7540 // op: vj
7541 return 5;
7542 case 0:
7543 // op: rd
7544 return 0;
7545 }
7546 break;
7547 }
7548 case LoongArch::VREPLVEI_D: {
7549 switch (OpNum) {
7550 case 2:
7551 // op: imm1
7552 return 10;
7553 case 1:
7554 // op: vj
7555 return 5;
7556 case 0:
7557 // op: vd
7558 return 0;
7559 }
7560 break;
7561 }
7562 case LoongArch::XVREPL128VEI_D: {
7563 switch (OpNum) {
7564 case 2:
7565 // op: imm1
7566 return 10;
7567 case 1:
7568 // op: xj
7569 return 5;
7570 case 0:
7571 // op: xd
7572 return 0;
7573 }
7574 break;
7575 }
7576 case LoongArch::VLDREPL_W: {
7577 switch (OpNum) {
7578 case 2:
7579 // op: imm10
7580 return 10;
7581 case 1:
7582 // op: rj
7583 return 5;
7584 case 0:
7585 // op: vd
7586 return 0;
7587 }
7588 break;
7589 }
7590 case LoongArch::XVLDREPL_W: {
7591 switch (OpNum) {
7592 case 2:
7593 // op: imm10
7594 return 10;
7595 case 1:
7596 // op: rj
7597 return 5;
7598 case 0:
7599 // op: xd
7600 return 0;
7601 }
7602 break;
7603 }
7604 case LoongArch::VLDREPL_H: {
7605 switch (OpNum) {
7606 case 2:
7607 // op: imm11
7608 return 10;
7609 case 1:
7610 // op: rj
7611 return 5;
7612 case 0:
7613 // op: vd
7614 return 0;
7615 }
7616 break;
7617 }
7618 case LoongArch::XVLDREPL_H: {
7619 switch (OpNum) {
7620 case 2:
7621 // op: imm11
7622 return 10;
7623 case 1:
7624 // op: rj
7625 return 5;
7626 case 0:
7627 // op: xd
7628 return 0;
7629 }
7630 break;
7631 }
7632 case LoongArch::FLD_D:
7633 case LoongArch::FLD_S:
7634 case LoongArch::FST_D:
7635 case LoongArch::FST_S: {
7636 switch (OpNum) {
7637 case 2:
7638 // op: imm12
7639 return 10;
7640 case 1:
7641 // op: rj
7642 return 5;
7643 case 0:
7644 // op: fd
7645 return 0;
7646 }
7647 break;
7648 }
7649 case LoongArch::PRELD: {
7650 switch (OpNum) {
7651 case 2:
7652 // op: imm12
7653 return 10;
7654 case 1:
7655 // op: rj
7656 return 5;
7657 case 0:
7658 // op: imm5
7659 return 0;
7660 }
7661 break;
7662 }
7663 case LoongArch::CACOP: {
7664 switch (OpNum) {
7665 case 2:
7666 // op: imm12
7667 return 10;
7668 case 1:
7669 // op: rj
7670 return 5;
7671 case 0:
7672 // op: op
7673 return 0;
7674 }
7675 break;
7676 }
7677 case LoongArch::ADDI_D:
7678 case LoongArch::ADDI_W:
7679 case LoongArch::ANDI:
7680 case LoongArch::LDL_D:
7681 case LoongArch::LDL_W:
7682 case LoongArch::LDR_D:
7683 case LoongArch::LDR_W:
7684 case LoongArch::LD_B:
7685 case LoongArch::LD_BU:
7686 case LoongArch::LD_D:
7687 case LoongArch::LD_H:
7688 case LoongArch::LD_HU:
7689 case LoongArch::LD_W:
7690 case LoongArch::LD_WU:
7691 case LoongArch::LU52I_D:
7692 case LoongArch::ORI:
7693 case LoongArch::SLTI:
7694 case LoongArch::SLTUI:
7695 case LoongArch::STL_D:
7696 case LoongArch::STL_W:
7697 case LoongArch::STR_D:
7698 case LoongArch::STR_W:
7699 case LoongArch::ST_B:
7700 case LoongArch::ST_D:
7701 case LoongArch::ST_H:
7702 case LoongArch::ST_W:
7703 case LoongArch::XORI: {
7704 switch (OpNum) {
7705 case 2:
7706 // op: imm12
7707 return 10;
7708 case 1:
7709 // op: rj
7710 return 5;
7711 case 0:
7712 // op: rd
7713 return 0;
7714 }
7715 break;
7716 }
7717 case LoongArch::VLD:
7718 case LoongArch::VLDREPL_B:
7719 case LoongArch::VST: {
7720 switch (OpNum) {
7721 case 2:
7722 // op: imm12
7723 return 10;
7724 case 1:
7725 // op: rj
7726 return 5;
7727 case 0:
7728 // op: vd
7729 return 0;
7730 }
7731 break;
7732 }
7733 case LoongArch::XVLD:
7734 case LoongArch::XVLDREPL_B:
7735 case LoongArch::XVST: {
7736 switch (OpNum) {
7737 case 2:
7738 // op: imm12
7739 return 10;
7740 case 1:
7741 // op: rj
7742 return 5;
7743 case 0:
7744 // op: xd
7745 return 0;
7746 }
7747 break;
7748 }
7749 case LoongArch::LDPTR_D:
7750 case LoongArch::LDPTR_W:
7751 case LoongArch::LL_D:
7752 case LoongArch::LL_W:
7753 case LoongArch::STPTR_D:
7754 case LoongArch::STPTR_W: {
7755 switch (OpNum) {
7756 case 2:
7757 // op: imm14
7758 return 10;
7759 case 1:
7760 // op: rj
7761 return 5;
7762 case 0:
7763 // op: rd
7764 return 0;
7765 }
7766 break;
7767 }
7768 case LoongArch::BEQ:
7769 case LoongArch::BGE:
7770 case LoongArch::BGEU:
7771 case LoongArch::BLT:
7772 case LoongArch::BLTU:
7773 case LoongArch::BNE: {
7774 switch (OpNum) {
7775 case 2:
7776 // op: imm16
7777 return 10;
7778 case 0:
7779 // op: rj
7780 return 5;
7781 case 1:
7782 // op: rd
7783 return 0;
7784 }
7785 break;
7786 }
7787 case LoongArch::ADDU16I_D:
7788 case LoongArch::JIRL: {
7789 switch (OpNum) {
7790 case 2:
7791 // op: imm16
7792 return 10;
7793 case 1:
7794 // op: rj
7795 return 5;
7796 case 0:
7797 // op: rd
7798 return 0;
7799 }
7800 break;
7801 }
7802 case LoongArch::VPICKVE2GR_W:
7803 case LoongArch::VPICKVE2GR_WU: {
7804 switch (OpNum) {
7805 case 2:
7806 // op: imm2
7807 return 10;
7808 case 1:
7809 // op: vj
7810 return 5;
7811 case 0:
7812 // op: rd
7813 return 0;
7814 }
7815 break;
7816 }
7817 case LoongArch::VREPLVEI_W: {
7818 switch (OpNum) {
7819 case 2:
7820 // op: imm2
7821 return 10;
7822 case 1:
7823 // op: vj
7824 return 5;
7825 case 0:
7826 // op: vd
7827 return 0;
7828 }
7829 break;
7830 }
7831 case LoongArch::XVPICKVE2GR_D:
7832 case LoongArch::XVPICKVE2GR_DU: {
7833 switch (OpNum) {
7834 case 2:
7835 // op: imm2
7836 return 10;
7837 case 1:
7838 // op: xj
7839 return 5;
7840 case 0:
7841 // op: rd
7842 return 0;
7843 }
7844 break;
7845 }
7846 case LoongArch::XVPICKVE_D:
7847 case LoongArch::XVREPL128VEI_W: {
7848 switch (OpNum) {
7849 case 2:
7850 // op: imm2
7851 return 10;
7852 case 1:
7853 // op: xj
7854 return 5;
7855 case 0:
7856 // op: xd
7857 return 0;
7858 }
7859 break;
7860 }
7861 case LoongArch::LU32I_D: {
7862 switch (OpNum) {
7863 case 2:
7864 // op: imm20
7865 return 5;
7866 case 1:
7867 // op: rd
7868 return 0;
7869 }
7870 break;
7871 }
7872 case LoongArch::RCRI_B:
7873 case LoongArch::ROTRI_B: {
7874 switch (OpNum) {
7875 case 2:
7876 // op: imm3
7877 return 10;
7878 case 1:
7879 // op: rj
7880 return 5;
7881 case 0:
7882 // op: rd
7883 return 0;
7884 }
7885 break;
7886 }
7887 case LoongArch::VPICKVE2GR_H:
7888 case LoongArch::VPICKVE2GR_HU: {
7889 switch (OpNum) {
7890 case 2:
7891 // op: imm3
7892 return 10;
7893 case 1:
7894 // op: vj
7895 return 5;
7896 case 0:
7897 // op: rd
7898 return 0;
7899 }
7900 break;
7901 }
7902 case LoongArch::VBITCLRI_B:
7903 case LoongArch::VBITREVI_B:
7904 case LoongArch::VBITSETI_B:
7905 case LoongArch::VREPLVEI_H:
7906 case LoongArch::VROTRI_B:
7907 case LoongArch::VSAT_B:
7908 case LoongArch::VSAT_BU:
7909 case LoongArch::VSLLI_B:
7910 case LoongArch::VSLLWIL_HU_BU:
7911 case LoongArch::VSLLWIL_H_B:
7912 case LoongArch::VSRAI_B:
7913 case LoongArch::VSRARI_B:
7914 case LoongArch::VSRLI_B:
7915 case LoongArch::VSRLRI_B: {
7916 switch (OpNum) {
7917 case 2:
7918 // op: imm3
7919 return 10;
7920 case 1:
7921 // op: vj
7922 return 5;
7923 case 0:
7924 // op: vd
7925 return 0;
7926 }
7927 break;
7928 }
7929 case LoongArch::XVPICKVE2GR_W:
7930 case LoongArch::XVPICKVE2GR_WU: {
7931 switch (OpNum) {
7932 case 2:
7933 // op: imm3
7934 return 10;
7935 case 1:
7936 // op: xj
7937 return 5;
7938 case 0:
7939 // op: rd
7940 return 0;
7941 }
7942 break;
7943 }
7944 case LoongArch::XVBITCLRI_B:
7945 case LoongArch::XVBITREVI_B:
7946 case LoongArch::XVBITSETI_B:
7947 case LoongArch::XVPICKVE_W:
7948 case LoongArch::XVREPL128VEI_H:
7949 case LoongArch::XVROTRI_B:
7950 case LoongArch::XVSAT_B:
7951 case LoongArch::XVSAT_BU:
7952 case LoongArch::XVSLLI_B:
7953 case LoongArch::XVSLLWIL_HU_BU:
7954 case LoongArch::XVSLLWIL_H_B:
7955 case LoongArch::XVSRAI_B:
7956 case LoongArch::XVSRARI_B:
7957 case LoongArch::XVSRLI_B:
7958 case LoongArch::XVSRLRI_B: {
7959 switch (OpNum) {
7960 case 2:
7961 // op: imm3
7962 return 10;
7963 case 1:
7964 // op: xj
7965 return 5;
7966 case 0:
7967 // op: xd
7968 return 0;
7969 }
7970 break;
7971 }
7972 case LoongArch::ARMADC_W:
7973 case LoongArch::ARMADD_W:
7974 case LoongArch::ARMAND_W:
7975 case LoongArch::ARMOR_W:
7976 case LoongArch::ARMROTR_W:
7977 case LoongArch::ARMSBC_W:
7978 case LoongArch::ARMSLL_W:
7979 case LoongArch::ARMSRA_W:
7980 case LoongArch::ARMSRL_W:
7981 case LoongArch::ARMSUB_W:
7982 case LoongArch::ARMXOR_W: {
7983 switch (OpNum) {
7984 case 2:
7985 // op: imm4
7986 return 0;
7987 case 1:
7988 // op: rk
7989 return 10;
7990 case 0:
7991 // op: rj
7992 return 5;
7993 }
7994 break;
7995 }
7996 case LoongArch::ARMMOVE:
7997 case LoongArch::RCRI_H:
7998 case LoongArch::ROTRI_H: {
7999 switch (OpNum) {
8000 case 2:
8001 // op: imm4
8002 return 10;
8003 case 1:
8004 // op: rj
8005 return 5;
8006 case 0:
8007 // op: rd
8008 return 0;
8009 }
8010 break;
8011 }
8012 case LoongArch::VPICKVE2GR_B:
8013 case LoongArch::VPICKVE2GR_BU: {
8014 switch (OpNum) {
8015 case 2:
8016 // op: imm4
8017 return 10;
8018 case 1:
8019 // op: vj
8020 return 5;
8021 case 0:
8022 // op: rd
8023 return 0;
8024 }
8025 break;
8026 }
8027 case LoongArch::VBITCLRI_H:
8028 case LoongArch::VBITREVI_H:
8029 case LoongArch::VBITSETI_H:
8030 case LoongArch::VREPLVEI_B:
8031 case LoongArch::VROTRI_H:
8032 case LoongArch::VSAT_H:
8033 case LoongArch::VSAT_HU:
8034 case LoongArch::VSLLI_H:
8035 case LoongArch::VSLLWIL_WU_HU:
8036 case LoongArch::VSLLWIL_W_H:
8037 case LoongArch::VSRAI_H:
8038 case LoongArch::VSRARI_H:
8039 case LoongArch::VSRLI_H:
8040 case LoongArch::VSRLRI_H: {
8041 switch (OpNum) {
8042 case 2:
8043 // op: imm4
8044 return 10;
8045 case 1:
8046 // op: vj
8047 return 5;
8048 case 0:
8049 // op: vd
8050 return 0;
8051 }
8052 break;
8053 }
8054 case LoongArch::XVBITCLRI_H:
8055 case LoongArch::XVBITREVI_H:
8056 case LoongArch::XVBITSETI_H:
8057 case LoongArch::XVREPL128VEI_B:
8058 case LoongArch::XVROTRI_H:
8059 case LoongArch::XVSAT_H:
8060 case LoongArch::XVSAT_HU:
8061 case LoongArch::XVSLLI_H:
8062 case LoongArch::XVSLLWIL_WU_HU:
8063 case LoongArch::XVSLLWIL_W_H:
8064 case LoongArch::XVSRAI_H:
8065 case LoongArch::XVSRARI_H:
8066 case LoongArch::XVSRLI_H:
8067 case LoongArch::XVSRLRI_H: {
8068 switch (OpNum) {
8069 case 2:
8070 // op: imm4
8071 return 10;
8072 case 1:
8073 // op: xj
8074 return 5;
8075 case 0:
8076 // op: xd
8077 return 0;
8078 }
8079 break;
8080 }
8081 case LoongArch::ADDU12I_D:
8082 case LoongArch::ADDU12I_W:
8083 case LoongArch::RCRI_W:
8084 case LoongArch::ROTRI_W:
8085 case LoongArch::SLLI_W:
8086 case LoongArch::SRAI_W:
8087 case LoongArch::SRLI_W: {
8088 switch (OpNum) {
8089 case 2:
8090 // op: imm5
8091 return 10;
8092 case 1:
8093 // op: rj
8094 return 5;
8095 case 0:
8096 // op: rd
8097 return 0;
8098 }
8099 break;
8100 }
8101 case LoongArch::VADDI_BU:
8102 case LoongArch::VADDI_DU:
8103 case LoongArch::VADDI_HU:
8104 case LoongArch::VADDI_WU:
8105 case LoongArch::VBITCLRI_W:
8106 case LoongArch::VBITREVI_W:
8107 case LoongArch::VBITSETI_W:
8108 case LoongArch::VBSLL_V:
8109 case LoongArch::VBSRL_V:
8110 case LoongArch::VMAXI_B:
8111 case LoongArch::VMAXI_BU:
8112 case LoongArch::VMAXI_D:
8113 case LoongArch::VMAXI_DU:
8114 case LoongArch::VMAXI_H:
8115 case LoongArch::VMAXI_HU:
8116 case LoongArch::VMAXI_W:
8117 case LoongArch::VMAXI_WU:
8118 case LoongArch::VMINI_B:
8119 case LoongArch::VMINI_BU:
8120 case LoongArch::VMINI_D:
8121 case LoongArch::VMINI_DU:
8122 case LoongArch::VMINI_H:
8123 case LoongArch::VMINI_HU:
8124 case LoongArch::VMINI_W:
8125 case LoongArch::VMINI_WU:
8126 case LoongArch::VROTRI_W:
8127 case LoongArch::VSAT_W:
8128 case LoongArch::VSAT_WU:
8129 case LoongArch::VSEQI_B:
8130 case LoongArch::VSEQI_D:
8131 case LoongArch::VSEQI_H:
8132 case LoongArch::VSEQI_W:
8133 case LoongArch::VSLEI_B:
8134 case LoongArch::VSLEI_BU:
8135 case LoongArch::VSLEI_D:
8136 case LoongArch::VSLEI_DU:
8137 case LoongArch::VSLEI_H:
8138 case LoongArch::VSLEI_HU:
8139 case LoongArch::VSLEI_W:
8140 case LoongArch::VSLEI_WU:
8141 case LoongArch::VSLLI_W:
8142 case LoongArch::VSLLWIL_DU_WU:
8143 case LoongArch::VSLLWIL_D_W:
8144 case LoongArch::VSLTI_B:
8145 case LoongArch::VSLTI_BU:
8146 case LoongArch::VSLTI_D:
8147 case LoongArch::VSLTI_DU:
8148 case LoongArch::VSLTI_H:
8149 case LoongArch::VSLTI_HU:
8150 case LoongArch::VSLTI_W:
8151 case LoongArch::VSLTI_WU:
8152 case LoongArch::VSRAI_W:
8153 case LoongArch::VSRARI_W:
8154 case LoongArch::VSRLI_W:
8155 case LoongArch::VSRLRI_W:
8156 case LoongArch::VSUBI_BU:
8157 case LoongArch::VSUBI_DU:
8158 case LoongArch::VSUBI_HU:
8159 case LoongArch::VSUBI_WU: {
8160 switch (OpNum) {
8161 case 2:
8162 // op: imm5
8163 return 10;
8164 case 1:
8165 // op: vj
8166 return 5;
8167 case 0:
8168 // op: vd
8169 return 0;
8170 }
8171 break;
8172 }
8173 case LoongArch::XVADDI_BU:
8174 case LoongArch::XVADDI_DU:
8175 case LoongArch::XVADDI_HU:
8176 case LoongArch::XVADDI_WU:
8177 case LoongArch::XVBITCLRI_W:
8178 case LoongArch::XVBITREVI_W:
8179 case LoongArch::XVBITSETI_W:
8180 case LoongArch::XVBSLL_V:
8181 case LoongArch::XVBSRL_V:
8182 case LoongArch::XVHSELI_D:
8183 case LoongArch::XVMAXI_B:
8184 case LoongArch::XVMAXI_BU:
8185 case LoongArch::XVMAXI_D:
8186 case LoongArch::XVMAXI_DU:
8187 case LoongArch::XVMAXI_H:
8188 case LoongArch::XVMAXI_HU:
8189 case LoongArch::XVMAXI_W:
8190 case LoongArch::XVMAXI_WU:
8191 case LoongArch::XVMINI_B:
8192 case LoongArch::XVMINI_BU:
8193 case LoongArch::XVMINI_D:
8194 case LoongArch::XVMINI_DU:
8195 case LoongArch::XVMINI_H:
8196 case LoongArch::XVMINI_HU:
8197 case LoongArch::XVMINI_W:
8198 case LoongArch::XVMINI_WU:
8199 case LoongArch::XVROTRI_W:
8200 case LoongArch::XVSAT_W:
8201 case LoongArch::XVSAT_WU:
8202 case LoongArch::XVSEQI_B:
8203 case LoongArch::XVSEQI_D:
8204 case LoongArch::XVSEQI_H:
8205 case LoongArch::XVSEQI_W:
8206 case LoongArch::XVSLEI_B:
8207 case LoongArch::XVSLEI_BU:
8208 case LoongArch::XVSLEI_D:
8209 case LoongArch::XVSLEI_DU:
8210 case LoongArch::XVSLEI_H:
8211 case LoongArch::XVSLEI_HU:
8212 case LoongArch::XVSLEI_W:
8213 case LoongArch::XVSLEI_WU:
8214 case LoongArch::XVSLLI_W:
8215 case LoongArch::XVSLLWIL_DU_WU:
8216 case LoongArch::XVSLLWIL_D_W:
8217 case LoongArch::XVSLTI_B:
8218 case LoongArch::XVSLTI_BU:
8219 case LoongArch::XVSLTI_D:
8220 case LoongArch::XVSLTI_DU:
8221 case LoongArch::XVSLTI_H:
8222 case LoongArch::XVSLTI_HU:
8223 case LoongArch::XVSLTI_W:
8224 case LoongArch::XVSLTI_WU:
8225 case LoongArch::XVSRAI_W:
8226 case LoongArch::XVSRARI_W:
8227 case LoongArch::XVSRLI_W:
8228 case LoongArch::XVSRLRI_W:
8229 case LoongArch::XVSUBI_BU:
8230 case LoongArch::XVSUBI_DU:
8231 case LoongArch::XVSUBI_HU:
8232 case LoongArch::XVSUBI_WU: {
8233 switch (OpNum) {
8234 case 2:
8235 // op: imm5
8236 return 10;
8237 case 1:
8238 // op: xj
8239 return 5;
8240 case 0:
8241 // op: xd
8242 return 0;
8243 }
8244 break;
8245 }
8246 case LoongArch::RCRI_D:
8247 case LoongArch::ROTRI_D:
8248 case LoongArch::SLLI_D:
8249 case LoongArch::SRAI_D:
8250 case LoongArch::SRLI_D: {
8251 switch (OpNum) {
8252 case 2:
8253 // op: imm6
8254 return 10;
8255 case 1:
8256 // op: rj
8257 return 5;
8258 case 0:
8259 // op: rd
8260 return 0;
8261 }
8262 break;
8263 }
8264 case LoongArch::VBITCLRI_D:
8265 case LoongArch::VBITREVI_D:
8266 case LoongArch::VBITSETI_D:
8267 case LoongArch::VROTRI_D:
8268 case LoongArch::VSAT_D:
8269 case LoongArch::VSAT_DU:
8270 case LoongArch::VSLLI_D:
8271 case LoongArch::VSRAI_D:
8272 case LoongArch::VSRARI_D:
8273 case LoongArch::VSRLI_D:
8274 case LoongArch::VSRLRI_D: {
8275 switch (OpNum) {
8276 case 2:
8277 // op: imm6
8278 return 10;
8279 case 1:
8280 // op: vj
8281 return 5;
8282 case 0:
8283 // op: vd
8284 return 0;
8285 }
8286 break;
8287 }
8288 case LoongArch::XVBITCLRI_D:
8289 case LoongArch::XVBITREVI_D:
8290 case LoongArch::XVBITSETI_D:
8291 case LoongArch::XVROTRI_D:
8292 case LoongArch::XVSAT_D:
8293 case LoongArch::XVSAT_DU:
8294 case LoongArch::XVSLLI_D:
8295 case LoongArch::XVSRAI_D:
8296 case LoongArch::XVSRARI_D:
8297 case LoongArch::XVSRLI_D:
8298 case LoongArch::XVSRLRI_D: {
8299 switch (OpNum) {
8300 case 2:
8301 // op: imm6
8302 return 10;
8303 case 1:
8304 // op: xj
8305 return 5;
8306 case 0:
8307 // op: xd
8308 return 0;
8309 }
8310 break;
8311 }
8312 case LoongArch::X86SETTAG: {
8313 switch (OpNum) {
8314 case 2:
8315 // op: imm8
8316 return 10;
8317 case 1:
8318 // op: imm5
8319 return 5;
8320 case 0:
8321 // op: rd
8322 return 0;
8323 }
8324 break;
8325 }
8326 case LoongArch::LDDIR: {
8327 switch (OpNum) {
8328 case 2:
8329 // op: imm8
8330 return 10;
8331 case 1:
8332 // op: rj
8333 return 5;
8334 case 0:
8335 // op: rd
8336 return 0;
8337 }
8338 break;
8339 }
8340 case LoongArch::VANDI_B:
8341 case LoongArch::VNORI_B:
8342 case LoongArch::VORI_B:
8343 case LoongArch::VSHUF4I_B:
8344 case LoongArch::VSHUF4I_H:
8345 case LoongArch::VSHUF4I_W:
8346 case LoongArch::VXORI_B: {
8347 switch (OpNum) {
8348 case 2:
8349 // op: imm8
8350 return 10;
8351 case 1:
8352 // op: vj
8353 return 5;
8354 case 0:
8355 // op: vd
8356 return 0;
8357 }
8358 break;
8359 }
8360 case LoongArch::XVANDI_B:
8361 case LoongArch::XVNORI_B:
8362 case LoongArch::XVORI_B:
8363 case LoongArch::XVPERMI_D:
8364 case LoongArch::XVSHUF4I_B:
8365 case LoongArch::XVSHUF4I_H:
8366 case LoongArch::XVSHUF4I_W:
8367 case LoongArch::XVXORI_B: {
8368 switch (OpNum) {
8369 case 2:
8370 // op: imm8
8371 return 10;
8372 case 1:
8373 // op: xj
8374 return 5;
8375 case 0:
8376 // op: xd
8377 return 0;
8378 }
8379 break;
8380 }
8381 case LoongArch::VLDREPL_D: {
8382 switch (OpNum) {
8383 case 2:
8384 // op: imm9
8385 return 10;
8386 case 1:
8387 // op: rj
8388 return 5;
8389 case 0:
8390 // op: vd
8391 return 0;
8392 }
8393 break;
8394 }
8395 case LoongArch::XVLDREPL_D: {
8396 switch (OpNum) {
8397 case 2:
8398 // op: imm9
8399 return 10;
8400 case 1:
8401 // op: rj
8402 return 5;
8403 case 0:
8404 // op: xd
8405 return 0;
8406 }
8407 break;
8408 }
8409 case LoongArch::BSTRPICK_D: {
8410 switch (OpNum) {
8411 case 2:
8412 // op: msbd
8413 return 16;
8414 case 3:
8415 // op: lsbd
8416 return 10;
8417 case 1:
8418 // op: rj
8419 return 5;
8420 case 0:
8421 // op: rd
8422 return 0;
8423 }
8424 break;
8425 }
8426 case LoongArch::BSTRPICK_W: {
8427 switch (OpNum) {
8428 case 2:
8429 // op: msbw
8430 return 16;
8431 case 3:
8432 // op: lsbw
8433 return 10;
8434 case 1:
8435 // op: rj
8436 return 5;
8437 case 0:
8438 // op: rd
8439 return 0;
8440 }
8441 break;
8442 }
8443 case LoongArch::SCREL_D:
8444 case LoongArch::SCREL_W: {
8445 switch (OpNum) {
8446 case 2:
8447 // op: rj
8448 return 5;
8449 case 1:
8450 // op: rd
8451 return 0;
8452 }
8453 break;
8454 }
8455 case LoongArch::FLDGT_D:
8456 case LoongArch::FLDGT_S:
8457 case LoongArch::FLDLE_D:
8458 case LoongArch::FLDLE_S:
8459 case LoongArch::FLDX_D:
8460 case LoongArch::FLDX_S:
8461 case LoongArch::FSTGT_D:
8462 case LoongArch::FSTGT_S:
8463 case LoongArch::FSTLE_D:
8464 case LoongArch::FSTLE_S:
8465 case LoongArch::FSTX_D:
8466 case LoongArch::FSTX_S: {
8467 switch (OpNum) {
8468 case 2:
8469 // op: rk
8470 return 10;
8471 case 1:
8472 // op: rj
8473 return 5;
8474 case 0:
8475 // op: fd
8476 return 0;
8477 }
8478 break;
8479 }
8480 case LoongArch::PRELDX: {
8481 switch (OpNum) {
8482 case 2:
8483 // op: rk
8484 return 10;
8485 case 1:
8486 // op: rj
8487 return 5;
8488 case 0:
8489 // op: imm5
8490 return 0;
8491 }
8492 break;
8493 }
8494 case LoongArch::ADC_B:
8495 case LoongArch::ADC_D:
8496 case LoongArch::ADC_H:
8497 case LoongArch::ADC_W:
8498 case LoongArch::ADD_D:
8499 case LoongArch::ADD_W:
8500 case LoongArch::AND:
8501 case LoongArch::ANDN:
8502 case LoongArch::CRCC_W_B_W:
8503 case LoongArch::CRCC_W_D_W:
8504 case LoongArch::CRCC_W_H_W:
8505 case LoongArch::CRCC_W_W_W:
8506 case LoongArch::CRC_W_B_W:
8507 case LoongArch::CRC_W_D_W:
8508 case LoongArch::CRC_W_H_W:
8509 case LoongArch::CRC_W_W_W:
8510 case LoongArch::DIV_D:
8511 case LoongArch::DIV_DU:
8512 case LoongArch::DIV_W:
8513 case LoongArch::DIV_WU:
8514 case LoongArch::LDGT_B:
8515 case LoongArch::LDGT_D:
8516 case LoongArch::LDGT_H:
8517 case LoongArch::LDGT_W:
8518 case LoongArch::LDLE_B:
8519 case LoongArch::LDLE_D:
8520 case LoongArch::LDLE_H:
8521 case LoongArch::LDLE_W:
8522 case LoongArch::LDX_B:
8523 case LoongArch::LDX_BU:
8524 case LoongArch::LDX_D:
8525 case LoongArch::LDX_H:
8526 case LoongArch::LDX_HU:
8527 case LoongArch::LDX_W:
8528 case LoongArch::LDX_WU:
8529 case LoongArch::MASKEQZ:
8530 case LoongArch::MASKNEZ:
8531 case LoongArch::MOD_D:
8532 case LoongArch::MOD_DU:
8533 case LoongArch::MOD_W:
8534 case LoongArch::MOD_WU:
8535 case LoongArch::MULH_D:
8536 case LoongArch::MULH_DU:
8537 case LoongArch::MULH_W:
8538 case LoongArch::MULH_WU:
8539 case LoongArch::MULW_D_W:
8540 case LoongArch::MULW_D_WU:
8541 case LoongArch::MUL_D:
8542 case LoongArch::MUL_W:
8543 case LoongArch::NOR:
8544 case LoongArch::OR:
8545 case LoongArch::ORN:
8546 case LoongArch::RCR_B:
8547 case LoongArch::RCR_D:
8548 case LoongArch::RCR_H:
8549 case LoongArch::RCR_W:
8550 case LoongArch::ROTR_B:
8551 case LoongArch::ROTR_D:
8552 case LoongArch::ROTR_H:
8553 case LoongArch::ROTR_W:
8554 case LoongArch::SBC_B:
8555 case LoongArch::SBC_D:
8556 case LoongArch::SBC_H:
8557 case LoongArch::SBC_W:
8558 case LoongArch::SLL_D:
8559 case LoongArch::SLL_W:
8560 case LoongArch::SLT:
8561 case LoongArch::SLTU:
8562 case LoongArch::SRA_D:
8563 case LoongArch::SRA_W:
8564 case LoongArch::SRL_D:
8565 case LoongArch::SRL_W:
8566 case LoongArch::STGT_B:
8567 case LoongArch::STGT_D:
8568 case LoongArch::STGT_H:
8569 case LoongArch::STGT_W:
8570 case LoongArch::STLE_B:
8571 case LoongArch::STLE_D:
8572 case LoongArch::STLE_H:
8573 case LoongArch::STLE_W:
8574 case LoongArch::STX_B:
8575 case LoongArch::STX_D:
8576 case LoongArch::STX_H:
8577 case LoongArch::STX_W:
8578 case LoongArch::SUB_D:
8579 case LoongArch::SUB_W:
8580 case LoongArch::XOR: {
8581 switch (OpNum) {
8582 case 2:
8583 // op: rk
8584 return 10;
8585 case 1:
8586 // op: rj
8587 return 5;
8588 case 0:
8589 // op: rd
8590 return 0;
8591 }
8592 break;
8593 }
8594 case LoongArch::VLDX:
8595 case LoongArch::VSTX: {
8596 switch (OpNum) {
8597 case 2:
8598 // op: rk
8599 return 10;
8600 case 1:
8601 // op: rj
8602 return 5;
8603 case 0:
8604 // op: vd
8605 return 0;
8606 }
8607 break;
8608 }
8609 case LoongArch::XVLDX:
8610 case LoongArch::XVSTX: {
8611 switch (OpNum) {
8612 case 2:
8613 // op: rk
8614 return 10;
8615 case 1:
8616 // op: rj
8617 return 5;
8618 case 0:
8619 // op: xd
8620 return 0;
8621 }
8622 break;
8623 }
8624 case LoongArch::VREPLVE_B:
8625 case LoongArch::VREPLVE_D:
8626 case LoongArch::VREPLVE_H:
8627 case LoongArch::VREPLVE_W: {
8628 switch (OpNum) {
8629 case 2:
8630 // op: rk
8631 return 10;
8632 case 1:
8633 // op: vj
8634 return 5;
8635 case 0:
8636 // op: vd
8637 return 0;
8638 }
8639 break;
8640 }
8641 case LoongArch::XVREPLVE_B:
8642 case LoongArch::XVREPLVE_D:
8643 case LoongArch::XVREPLVE_H:
8644 case LoongArch::XVREPLVE_W: {
8645 switch (OpNum) {
8646 case 2:
8647 // op: rk
8648 return 10;
8649 case 1:
8650 // op: xj
8651 return 5;
8652 case 0:
8653 // op: xd
8654 return 0;
8655 }
8656 break;
8657 }
8658 case LoongArch::SC_Q: {
8659 switch (OpNum) {
8660 case 2:
8661 // op: rk
8662 return 10;
8663 case 3:
8664 // op: rj
8665 return 5;
8666 case 1:
8667 // op: rd
8668 return 0;
8669 }
8670 break;
8671 }
8672 case LoongArch::MOVGR2FRH_W: {
8673 switch (OpNum) {
8674 case 2:
8675 // op: src
8676 return 5;
8677 case 1:
8678 // op: dst
8679 return 0;
8680 }
8681 break;
8682 }
8683 case LoongArch::VABSD_B:
8684 case LoongArch::VABSD_BU:
8685 case LoongArch::VABSD_D:
8686 case LoongArch::VABSD_DU:
8687 case LoongArch::VABSD_H:
8688 case LoongArch::VABSD_HU:
8689 case LoongArch::VABSD_W:
8690 case LoongArch::VABSD_WU:
8691 case LoongArch::VADDA_B:
8692 case LoongArch::VADDA_D:
8693 case LoongArch::VADDA_H:
8694 case LoongArch::VADDA_W:
8695 case LoongArch::VADDWEV_D_W:
8696 case LoongArch::VADDWEV_D_WU:
8697 case LoongArch::VADDWEV_D_WU_W:
8698 case LoongArch::VADDWEV_H_B:
8699 case LoongArch::VADDWEV_H_BU:
8700 case LoongArch::VADDWEV_H_BU_B:
8701 case LoongArch::VADDWEV_Q_D:
8702 case LoongArch::VADDWEV_Q_DU:
8703 case LoongArch::VADDWEV_Q_DU_D:
8704 case LoongArch::VADDWEV_W_H:
8705 case LoongArch::VADDWEV_W_HU:
8706 case LoongArch::VADDWEV_W_HU_H:
8707 case LoongArch::VADDWOD_D_W:
8708 case LoongArch::VADDWOD_D_WU:
8709 case LoongArch::VADDWOD_D_WU_W:
8710 case LoongArch::VADDWOD_H_B:
8711 case LoongArch::VADDWOD_H_BU:
8712 case LoongArch::VADDWOD_H_BU_B:
8713 case LoongArch::VADDWOD_Q_D:
8714 case LoongArch::VADDWOD_Q_DU:
8715 case LoongArch::VADDWOD_Q_DU_D:
8716 case LoongArch::VADDWOD_W_H:
8717 case LoongArch::VADDWOD_W_HU:
8718 case LoongArch::VADDWOD_W_HU_H:
8719 case LoongArch::VADD_B:
8720 case LoongArch::VADD_D:
8721 case LoongArch::VADD_H:
8722 case LoongArch::VADD_Q:
8723 case LoongArch::VADD_W:
8724 case LoongArch::VANDN_V:
8725 case LoongArch::VAND_V:
8726 case LoongArch::VAVGR_B:
8727 case LoongArch::VAVGR_BU:
8728 case LoongArch::VAVGR_D:
8729 case LoongArch::VAVGR_DU:
8730 case LoongArch::VAVGR_H:
8731 case LoongArch::VAVGR_HU:
8732 case LoongArch::VAVGR_W:
8733 case LoongArch::VAVGR_WU:
8734 case LoongArch::VAVG_B:
8735 case LoongArch::VAVG_BU:
8736 case LoongArch::VAVG_D:
8737 case LoongArch::VAVG_DU:
8738 case LoongArch::VAVG_H:
8739 case LoongArch::VAVG_HU:
8740 case LoongArch::VAVG_W:
8741 case LoongArch::VAVG_WU:
8742 case LoongArch::VBITCLR_B:
8743 case LoongArch::VBITCLR_D:
8744 case LoongArch::VBITCLR_H:
8745 case LoongArch::VBITCLR_W:
8746 case LoongArch::VBITREV_B:
8747 case LoongArch::VBITREV_D:
8748 case LoongArch::VBITREV_H:
8749 case LoongArch::VBITREV_W:
8750 case LoongArch::VBITSET_B:
8751 case LoongArch::VBITSET_D:
8752 case LoongArch::VBITSET_H:
8753 case LoongArch::VBITSET_W:
8754 case LoongArch::VDIV_B:
8755 case LoongArch::VDIV_BU:
8756 case LoongArch::VDIV_D:
8757 case LoongArch::VDIV_DU:
8758 case LoongArch::VDIV_H:
8759 case LoongArch::VDIV_HU:
8760 case LoongArch::VDIV_W:
8761 case LoongArch::VDIV_WU:
8762 case LoongArch::VFADD_D:
8763 case LoongArch::VFADD_S:
8764 case LoongArch::VFCMP_CAF_D:
8765 case LoongArch::VFCMP_CAF_S:
8766 case LoongArch::VFCMP_CEQ_D:
8767 case LoongArch::VFCMP_CEQ_S:
8768 case LoongArch::VFCMP_CLE_D:
8769 case LoongArch::VFCMP_CLE_S:
8770 case LoongArch::VFCMP_CLT_D:
8771 case LoongArch::VFCMP_CLT_S:
8772 case LoongArch::VFCMP_CNE_D:
8773 case LoongArch::VFCMP_CNE_S:
8774 case LoongArch::VFCMP_COR_D:
8775 case LoongArch::VFCMP_COR_S:
8776 case LoongArch::VFCMP_CUEQ_D:
8777 case LoongArch::VFCMP_CUEQ_S:
8778 case LoongArch::VFCMP_CULE_D:
8779 case LoongArch::VFCMP_CULE_S:
8780 case LoongArch::VFCMP_CULT_D:
8781 case LoongArch::VFCMP_CULT_S:
8782 case LoongArch::VFCMP_CUNE_D:
8783 case LoongArch::VFCMP_CUNE_S:
8784 case LoongArch::VFCMP_CUN_D:
8785 case LoongArch::VFCMP_CUN_S:
8786 case LoongArch::VFCMP_SAF_D:
8787 case LoongArch::VFCMP_SAF_S:
8788 case LoongArch::VFCMP_SEQ_D:
8789 case LoongArch::VFCMP_SEQ_S:
8790 case LoongArch::VFCMP_SLE_D:
8791 case LoongArch::VFCMP_SLE_S:
8792 case LoongArch::VFCMP_SLT_D:
8793 case LoongArch::VFCMP_SLT_S:
8794 case LoongArch::VFCMP_SNE_D:
8795 case LoongArch::VFCMP_SNE_S:
8796 case LoongArch::VFCMP_SOR_D:
8797 case LoongArch::VFCMP_SOR_S:
8798 case LoongArch::VFCMP_SUEQ_D:
8799 case LoongArch::VFCMP_SUEQ_S:
8800 case LoongArch::VFCMP_SULE_D:
8801 case LoongArch::VFCMP_SULE_S:
8802 case LoongArch::VFCMP_SULT_D:
8803 case LoongArch::VFCMP_SULT_S:
8804 case LoongArch::VFCMP_SUNE_D:
8805 case LoongArch::VFCMP_SUNE_S:
8806 case LoongArch::VFCMP_SUN_D:
8807 case LoongArch::VFCMP_SUN_S:
8808 case LoongArch::VFCVT_H_S:
8809 case LoongArch::VFCVT_S_D:
8810 case LoongArch::VFDIV_D:
8811 case LoongArch::VFDIV_S:
8812 case LoongArch::VFFINT_S_L:
8813 case LoongArch::VFMAXA_D:
8814 case LoongArch::VFMAXA_S:
8815 case LoongArch::VFMAX_D:
8816 case LoongArch::VFMAX_S:
8817 case LoongArch::VFMINA_D:
8818 case LoongArch::VFMINA_S:
8819 case LoongArch::VFMIN_D:
8820 case LoongArch::VFMIN_S:
8821 case LoongArch::VFMUL_D:
8822 case LoongArch::VFMUL_S:
8823 case LoongArch::VFSUB_D:
8824 case LoongArch::VFSUB_S:
8825 case LoongArch::VFTINTRM_W_D:
8826 case LoongArch::VFTINTRNE_W_D:
8827 case LoongArch::VFTINTRP_W_D:
8828 case LoongArch::VFTINTRZ_W_D:
8829 case LoongArch::VFTINT_W_D:
8830 case LoongArch::VHADDW_DU_WU:
8831 case LoongArch::VHADDW_D_W:
8832 case LoongArch::VHADDW_HU_BU:
8833 case LoongArch::VHADDW_H_B:
8834 case LoongArch::VHADDW_QU_DU:
8835 case LoongArch::VHADDW_Q_D:
8836 case LoongArch::VHADDW_WU_HU:
8837 case LoongArch::VHADDW_W_H:
8838 case LoongArch::VHSUBW_DU_WU:
8839 case LoongArch::VHSUBW_D_W:
8840 case LoongArch::VHSUBW_HU_BU:
8841 case LoongArch::VHSUBW_H_B:
8842 case LoongArch::VHSUBW_QU_DU:
8843 case LoongArch::VHSUBW_Q_D:
8844 case LoongArch::VHSUBW_WU_HU:
8845 case LoongArch::VHSUBW_W_H:
8846 case LoongArch::VILVH_B:
8847 case LoongArch::VILVH_D:
8848 case LoongArch::VILVH_H:
8849 case LoongArch::VILVH_W:
8850 case LoongArch::VILVL_B:
8851 case LoongArch::VILVL_D:
8852 case LoongArch::VILVL_H:
8853 case LoongArch::VILVL_W:
8854 case LoongArch::VMAX_B:
8855 case LoongArch::VMAX_BU:
8856 case LoongArch::VMAX_D:
8857 case LoongArch::VMAX_DU:
8858 case LoongArch::VMAX_H:
8859 case LoongArch::VMAX_HU:
8860 case LoongArch::VMAX_W:
8861 case LoongArch::VMAX_WU:
8862 case LoongArch::VMIN_B:
8863 case LoongArch::VMIN_BU:
8864 case LoongArch::VMIN_D:
8865 case LoongArch::VMIN_DU:
8866 case LoongArch::VMIN_H:
8867 case LoongArch::VMIN_HU:
8868 case LoongArch::VMIN_W:
8869 case LoongArch::VMIN_WU:
8870 case LoongArch::VMOD_B:
8871 case LoongArch::VMOD_BU:
8872 case LoongArch::VMOD_D:
8873 case LoongArch::VMOD_DU:
8874 case LoongArch::VMOD_H:
8875 case LoongArch::VMOD_HU:
8876 case LoongArch::VMOD_W:
8877 case LoongArch::VMOD_WU:
8878 case LoongArch::VMUH_B:
8879 case LoongArch::VMUH_BU:
8880 case LoongArch::VMUH_D:
8881 case LoongArch::VMUH_DU:
8882 case LoongArch::VMUH_H:
8883 case LoongArch::VMUH_HU:
8884 case LoongArch::VMUH_W:
8885 case LoongArch::VMUH_WU:
8886 case LoongArch::VMULWEV_D_W:
8887 case LoongArch::VMULWEV_D_WU:
8888 case LoongArch::VMULWEV_D_WU_W:
8889 case LoongArch::VMULWEV_H_B:
8890 case LoongArch::VMULWEV_H_BU:
8891 case LoongArch::VMULWEV_H_BU_B:
8892 case LoongArch::VMULWEV_Q_D:
8893 case LoongArch::VMULWEV_Q_DU:
8894 case LoongArch::VMULWEV_Q_DU_D:
8895 case LoongArch::VMULWEV_W_H:
8896 case LoongArch::VMULWEV_W_HU:
8897 case LoongArch::VMULWEV_W_HU_H:
8898 case LoongArch::VMULWOD_D_W:
8899 case LoongArch::VMULWOD_D_WU:
8900 case LoongArch::VMULWOD_D_WU_W:
8901 case LoongArch::VMULWOD_H_B:
8902 case LoongArch::VMULWOD_H_BU:
8903 case LoongArch::VMULWOD_H_BU_B:
8904 case LoongArch::VMULWOD_Q_D:
8905 case LoongArch::VMULWOD_Q_DU:
8906 case LoongArch::VMULWOD_Q_DU_D:
8907 case LoongArch::VMULWOD_W_H:
8908 case LoongArch::VMULWOD_W_HU:
8909 case LoongArch::VMULWOD_W_HU_H:
8910 case LoongArch::VMUL_B:
8911 case LoongArch::VMUL_D:
8912 case LoongArch::VMUL_H:
8913 case LoongArch::VMUL_W:
8914 case LoongArch::VNOR_V:
8915 case LoongArch::VORN_V:
8916 case LoongArch::VOR_V:
8917 case LoongArch::VPACKEV_B:
8918 case LoongArch::VPACKEV_D:
8919 case LoongArch::VPACKEV_H:
8920 case LoongArch::VPACKEV_W:
8921 case LoongArch::VPACKOD_B:
8922 case LoongArch::VPACKOD_D:
8923 case LoongArch::VPACKOD_H:
8924 case LoongArch::VPACKOD_W:
8925 case LoongArch::VPICKEV_B:
8926 case LoongArch::VPICKEV_D:
8927 case LoongArch::VPICKEV_H:
8928 case LoongArch::VPICKEV_W:
8929 case LoongArch::VPICKOD_B:
8930 case LoongArch::VPICKOD_D:
8931 case LoongArch::VPICKOD_H:
8932 case LoongArch::VPICKOD_W:
8933 case LoongArch::VROTR_B:
8934 case LoongArch::VROTR_D:
8935 case LoongArch::VROTR_H:
8936 case LoongArch::VROTR_W:
8937 case LoongArch::VSADD_B:
8938 case LoongArch::VSADD_BU:
8939 case LoongArch::VSADD_D:
8940 case LoongArch::VSADD_DU:
8941 case LoongArch::VSADD_H:
8942 case LoongArch::VSADD_HU:
8943 case LoongArch::VSADD_W:
8944 case LoongArch::VSADD_WU:
8945 case LoongArch::VSEQ_B:
8946 case LoongArch::VSEQ_D:
8947 case LoongArch::VSEQ_H:
8948 case LoongArch::VSEQ_W:
8949 case LoongArch::VSIGNCOV_B:
8950 case LoongArch::VSIGNCOV_D:
8951 case LoongArch::VSIGNCOV_H:
8952 case LoongArch::VSIGNCOV_W:
8953 case LoongArch::VSLE_B:
8954 case LoongArch::VSLE_BU:
8955 case LoongArch::VSLE_D:
8956 case LoongArch::VSLE_DU:
8957 case LoongArch::VSLE_H:
8958 case LoongArch::VSLE_HU:
8959 case LoongArch::VSLE_W:
8960 case LoongArch::VSLE_WU:
8961 case LoongArch::VSLL_B:
8962 case LoongArch::VSLL_D:
8963 case LoongArch::VSLL_H:
8964 case LoongArch::VSLL_W:
8965 case LoongArch::VSLT_B:
8966 case LoongArch::VSLT_BU:
8967 case LoongArch::VSLT_D:
8968 case LoongArch::VSLT_DU:
8969 case LoongArch::VSLT_H:
8970 case LoongArch::VSLT_HU:
8971 case LoongArch::VSLT_W:
8972 case LoongArch::VSLT_WU:
8973 case LoongArch::VSRAN_B_H:
8974 case LoongArch::VSRAN_H_W:
8975 case LoongArch::VSRAN_W_D:
8976 case LoongArch::VSRARN_B_H:
8977 case LoongArch::VSRARN_H_W:
8978 case LoongArch::VSRARN_W_D:
8979 case LoongArch::VSRAR_B:
8980 case LoongArch::VSRAR_D:
8981 case LoongArch::VSRAR_H:
8982 case LoongArch::VSRAR_W:
8983 case LoongArch::VSRA_B:
8984 case LoongArch::VSRA_D:
8985 case LoongArch::VSRA_H:
8986 case LoongArch::VSRA_W:
8987 case LoongArch::VSRLN_B_H:
8988 case LoongArch::VSRLN_H_W:
8989 case LoongArch::VSRLN_W_D:
8990 case LoongArch::VSRLRN_B_H:
8991 case LoongArch::VSRLRN_H_W:
8992 case LoongArch::VSRLRN_W_D:
8993 case LoongArch::VSRLR_B:
8994 case LoongArch::VSRLR_D:
8995 case LoongArch::VSRLR_H:
8996 case LoongArch::VSRLR_W:
8997 case LoongArch::VSRL_B:
8998 case LoongArch::VSRL_D:
8999 case LoongArch::VSRL_H:
9000 case LoongArch::VSRL_W:
9001 case LoongArch::VSSRAN_BU_H:
9002 case LoongArch::VSSRAN_B_H:
9003 case LoongArch::VSSRAN_HU_W:
9004 case LoongArch::VSSRAN_H_W:
9005 case LoongArch::VSSRAN_WU_D:
9006 case LoongArch::VSSRAN_W_D:
9007 case LoongArch::VSSRARN_BU_H:
9008 case LoongArch::VSSRARN_B_H:
9009 case LoongArch::VSSRARN_HU_W:
9010 case LoongArch::VSSRARN_H_W:
9011 case LoongArch::VSSRARN_WU_D:
9012 case LoongArch::VSSRARN_W_D:
9013 case LoongArch::VSSRLN_BU_H:
9014 case LoongArch::VSSRLN_B_H:
9015 case LoongArch::VSSRLN_HU_W:
9016 case LoongArch::VSSRLN_H_W:
9017 case LoongArch::VSSRLN_WU_D:
9018 case LoongArch::VSSRLN_W_D:
9019 case LoongArch::VSSRLRN_BU_H:
9020 case LoongArch::VSSRLRN_B_H:
9021 case LoongArch::VSSRLRN_HU_W:
9022 case LoongArch::VSSRLRN_H_W:
9023 case LoongArch::VSSRLRN_WU_D:
9024 case LoongArch::VSSRLRN_W_D:
9025 case LoongArch::VSSUB_B:
9026 case LoongArch::VSSUB_BU:
9027 case LoongArch::VSSUB_D:
9028 case LoongArch::VSSUB_DU:
9029 case LoongArch::VSSUB_H:
9030 case LoongArch::VSSUB_HU:
9031 case LoongArch::VSSUB_W:
9032 case LoongArch::VSSUB_WU:
9033 case LoongArch::VSUBWEV_D_W:
9034 case LoongArch::VSUBWEV_D_WU:
9035 case LoongArch::VSUBWEV_H_B:
9036 case LoongArch::VSUBWEV_H_BU:
9037 case LoongArch::VSUBWEV_Q_D:
9038 case LoongArch::VSUBWEV_Q_DU:
9039 case LoongArch::VSUBWEV_W_H:
9040 case LoongArch::VSUBWEV_W_HU:
9041 case LoongArch::VSUBWOD_D_W:
9042 case LoongArch::VSUBWOD_D_WU:
9043 case LoongArch::VSUBWOD_H_B:
9044 case LoongArch::VSUBWOD_H_BU:
9045 case LoongArch::VSUBWOD_Q_D:
9046 case LoongArch::VSUBWOD_Q_DU:
9047 case LoongArch::VSUBWOD_W_H:
9048 case LoongArch::VSUBWOD_W_HU:
9049 case LoongArch::VSUB_B:
9050 case LoongArch::VSUB_D:
9051 case LoongArch::VSUB_H:
9052 case LoongArch::VSUB_Q:
9053 case LoongArch::VSUB_W:
9054 case LoongArch::VXOR_V: {
9055 switch (OpNum) {
9056 case 2:
9057 // op: vk
9058 return 10;
9059 case 1:
9060 // op: vj
9061 return 5;
9062 case 0:
9063 // op: vd
9064 return 0;
9065 }
9066 break;
9067 }
9068 case LoongArch::XVABSD_B:
9069 case LoongArch::XVABSD_BU:
9070 case LoongArch::XVABSD_D:
9071 case LoongArch::XVABSD_DU:
9072 case LoongArch::XVABSD_H:
9073 case LoongArch::XVABSD_HU:
9074 case LoongArch::XVABSD_W:
9075 case LoongArch::XVABSD_WU:
9076 case LoongArch::XVADDA_B:
9077 case LoongArch::XVADDA_D:
9078 case LoongArch::XVADDA_H:
9079 case LoongArch::XVADDA_W:
9080 case LoongArch::XVADDWEV_D_W:
9081 case LoongArch::XVADDWEV_D_WU:
9082 case LoongArch::XVADDWEV_D_WU_W:
9083 case LoongArch::XVADDWEV_H_B:
9084 case LoongArch::XVADDWEV_H_BU:
9085 case LoongArch::XVADDWEV_H_BU_B:
9086 case LoongArch::XVADDWEV_Q_D:
9087 case LoongArch::XVADDWEV_Q_DU:
9088 case LoongArch::XVADDWEV_Q_DU_D:
9089 case LoongArch::XVADDWEV_W_H:
9090 case LoongArch::XVADDWEV_W_HU:
9091 case LoongArch::XVADDWEV_W_HU_H:
9092 case LoongArch::XVADDWOD_D_W:
9093 case LoongArch::XVADDWOD_D_WU:
9094 case LoongArch::XVADDWOD_D_WU_W:
9095 case LoongArch::XVADDWOD_H_B:
9096 case LoongArch::XVADDWOD_H_BU:
9097 case LoongArch::XVADDWOD_H_BU_B:
9098 case LoongArch::XVADDWOD_Q_D:
9099 case LoongArch::XVADDWOD_Q_DU:
9100 case LoongArch::XVADDWOD_Q_DU_D:
9101 case LoongArch::XVADDWOD_W_H:
9102 case LoongArch::XVADDWOD_W_HU:
9103 case LoongArch::XVADDWOD_W_HU_H:
9104 case LoongArch::XVADD_B:
9105 case LoongArch::XVADD_D:
9106 case LoongArch::XVADD_H:
9107 case LoongArch::XVADD_Q:
9108 case LoongArch::XVADD_W:
9109 case LoongArch::XVANDN_V:
9110 case LoongArch::XVAND_V:
9111 case LoongArch::XVAVGR_B:
9112 case LoongArch::XVAVGR_BU:
9113 case LoongArch::XVAVGR_D:
9114 case LoongArch::XVAVGR_DU:
9115 case LoongArch::XVAVGR_H:
9116 case LoongArch::XVAVGR_HU:
9117 case LoongArch::XVAVGR_W:
9118 case LoongArch::XVAVGR_WU:
9119 case LoongArch::XVAVG_B:
9120 case LoongArch::XVAVG_BU:
9121 case LoongArch::XVAVG_D:
9122 case LoongArch::XVAVG_DU:
9123 case LoongArch::XVAVG_H:
9124 case LoongArch::XVAVG_HU:
9125 case LoongArch::XVAVG_W:
9126 case LoongArch::XVAVG_WU:
9127 case LoongArch::XVBITCLR_B:
9128 case LoongArch::XVBITCLR_D:
9129 case LoongArch::XVBITCLR_H:
9130 case LoongArch::XVBITCLR_W:
9131 case LoongArch::XVBITREV_B:
9132 case LoongArch::XVBITREV_D:
9133 case LoongArch::XVBITREV_H:
9134 case LoongArch::XVBITREV_W:
9135 case LoongArch::XVBITSET_B:
9136 case LoongArch::XVBITSET_D:
9137 case LoongArch::XVBITSET_H:
9138 case LoongArch::XVBITSET_W:
9139 case LoongArch::XVDIV_B:
9140 case LoongArch::XVDIV_BU:
9141 case LoongArch::XVDIV_D:
9142 case LoongArch::XVDIV_DU:
9143 case LoongArch::XVDIV_H:
9144 case LoongArch::XVDIV_HU:
9145 case LoongArch::XVDIV_W:
9146 case LoongArch::XVDIV_WU:
9147 case LoongArch::XVFADD_D:
9148 case LoongArch::XVFADD_S:
9149 case LoongArch::XVFCMP_CAF_D:
9150 case LoongArch::XVFCMP_CAF_S:
9151 case LoongArch::XVFCMP_CEQ_D:
9152 case LoongArch::XVFCMP_CEQ_S:
9153 case LoongArch::XVFCMP_CLE_D:
9154 case LoongArch::XVFCMP_CLE_S:
9155 case LoongArch::XVFCMP_CLT_D:
9156 case LoongArch::XVFCMP_CLT_S:
9157 case LoongArch::XVFCMP_CNE_D:
9158 case LoongArch::XVFCMP_CNE_S:
9159 case LoongArch::XVFCMP_COR_D:
9160 case LoongArch::XVFCMP_COR_S:
9161 case LoongArch::XVFCMP_CUEQ_D:
9162 case LoongArch::XVFCMP_CUEQ_S:
9163 case LoongArch::XVFCMP_CULE_D:
9164 case LoongArch::XVFCMP_CULE_S:
9165 case LoongArch::XVFCMP_CULT_D:
9166 case LoongArch::XVFCMP_CULT_S:
9167 case LoongArch::XVFCMP_CUNE_D:
9168 case LoongArch::XVFCMP_CUNE_S:
9169 case LoongArch::XVFCMP_CUN_D:
9170 case LoongArch::XVFCMP_CUN_S:
9171 case LoongArch::XVFCMP_SAF_D:
9172 case LoongArch::XVFCMP_SAF_S:
9173 case LoongArch::XVFCMP_SEQ_D:
9174 case LoongArch::XVFCMP_SEQ_S:
9175 case LoongArch::XVFCMP_SLE_D:
9176 case LoongArch::XVFCMP_SLE_S:
9177 case LoongArch::XVFCMP_SLT_D:
9178 case LoongArch::XVFCMP_SLT_S:
9179 case LoongArch::XVFCMP_SNE_D:
9180 case LoongArch::XVFCMP_SNE_S:
9181 case LoongArch::XVFCMP_SOR_D:
9182 case LoongArch::XVFCMP_SOR_S:
9183 case LoongArch::XVFCMP_SUEQ_D:
9184 case LoongArch::XVFCMP_SUEQ_S:
9185 case LoongArch::XVFCMP_SULE_D:
9186 case LoongArch::XVFCMP_SULE_S:
9187 case LoongArch::XVFCMP_SULT_D:
9188 case LoongArch::XVFCMP_SULT_S:
9189 case LoongArch::XVFCMP_SUNE_D:
9190 case LoongArch::XVFCMP_SUNE_S:
9191 case LoongArch::XVFCMP_SUN_D:
9192 case LoongArch::XVFCMP_SUN_S:
9193 case LoongArch::XVFCVT_H_S:
9194 case LoongArch::XVFCVT_S_D:
9195 case LoongArch::XVFDIV_D:
9196 case LoongArch::XVFDIV_S:
9197 case LoongArch::XVFFINT_S_L:
9198 case LoongArch::XVFMAXA_D:
9199 case LoongArch::XVFMAXA_S:
9200 case LoongArch::XVFMAX_D:
9201 case LoongArch::XVFMAX_S:
9202 case LoongArch::XVFMINA_D:
9203 case LoongArch::XVFMINA_S:
9204 case LoongArch::XVFMIN_D:
9205 case LoongArch::XVFMIN_S:
9206 case LoongArch::XVFMUL_D:
9207 case LoongArch::XVFMUL_S:
9208 case LoongArch::XVFSUB_D:
9209 case LoongArch::XVFSUB_S:
9210 case LoongArch::XVFTINTRM_W_D:
9211 case LoongArch::XVFTINTRNE_W_D:
9212 case LoongArch::XVFTINTRP_W_D:
9213 case LoongArch::XVFTINTRZ_W_D:
9214 case LoongArch::XVFTINT_W_D:
9215 case LoongArch::XVHADDW_DU_WU:
9216 case LoongArch::XVHADDW_D_W:
9217 case LoongArch::XVHADDW_HU_BU:
9218 case LoongArch::XVHADDW_H_B:
9219 case LoongArch::XVHADDW_QU_DU:
9220 case LoongArch::XVHADDW_Q_D:
9221 case LoongArch::XVHADDW_WU_HU:
9222 case LoongArch::XVHADDW_W_H:
9223 case LoongArch::XVHSUBW_DU_WU:
9224 case LoongArch::XVHSUBW_D_W:
9225 case LoongArch::XVHSUBW_HU_BU:
9226 case LoongArch::XVHSUBW_H_B:
9227 case LoongArch::XVHSUBW_QU_DU:
9228 case LoongArch::XVHSUBW_Q_D:
9229 case LoongArch::XVHSUBW_WU_HU:
9230 case LoongArch::XVHSUBW_W_H:
9231 case LoongArch::XVILVH_B:
9232 case LoongArch::XVILVH_D:
9233 case LoongArch::XVILVH_H:
9234 case LoongArch::XVILVH_W:
9235 case LoongArch::XVILVL_B:
9236 case LoongArch::XVILVL_D:
9237 case LoongArch::XVILVL_H:
9238 case LoongArch::XVILVL_W:
9239 case LoongArch::XVMAX_B:
9240 case LoongArch::XVMAX_BU:
9241 case LoongArch::XVMAX_D:
9242 case LoongArch::XVMAX_DU:
9243 case LoongArch::XVMAX_H:
9244 case LoongArch::XVMAX_HU:
9245 case LoongArch::XVMAX_W:
9246 case LoongArch::XVMAX_WU:
9247 case LoongArch::XVMIN_B:
9248 case LoongArch::XVMIN_BU:
9249 case LoongArch::XVMIN_D:
9250 case LoongArch::XVMIN_DU:
9251 case LoongArch::XVMIN_H:
9252 case LoongArch::XVMIN_HU:
9253 case LoongArch::XVMIN_W:
9254 case LoongArch::XVMIN_WU:
9255 case LoongArch::XVMOD_B:
9256 case LoongArch::XVMOD_BU:
9257 case LoongArch::XVMOD_D:
9258 case LoongArch::XVMOD_DU:
9259 case LoongArch::XVMOD_H:
9260 case LoongArch::XVMOD_HU:
9261 case LoongArch::XVMOD_W:
9262 case LoongArch::XVMOD_WU:
9263 case LoongArch::XVMUH_B:
9264 case LoongArch::XVMUH_BU:
9265 case LoongArch::XVMUH_D:
9266 case LoongArch::XVMUH_DU:
9267 case LoongArch::XVMUH_H:
9268 case LoongArch::XVMUH_HU:
9269 case LoongArch::XVMUH_W:
9270 case LoongArch::XVMUH_WU:
9271 case LoongArch::XVMULWEV_D_W:
9272 case LoongArch::XVMULWEV_D_WU:
9273 case LoongArch::XVMULWEV_D_WU_W:
9274 case LoongArch::XVMULWEV_H_B:
9275 case LoongArch::XVMULWEV_H_BU:
9276 case LoongArch::XVMULWEV_H_BU_B:
9277 case LoongArch::XVMULWEV_Q_D:
9278 case LoongArch::XVMULWEV_Q_DU:
9279 case LoongArch::XVMULWEV_Q_DU_D:
9280 case LoongArch::XVMULWEV_W_H:
9281 case LoongArch::XVMULWEV_W_HU:
9282 case LoongArch::XVMULWEV_W_HU_H:
9283 case LoongArch::XVMULWOD_D_W:
9284 case LoongArch::XVMULWOD_D_WU:
9285 case LoongArch::XVMULWOD_D_WU_W:
9286 case LoongArch::XVMULWOD_H_B:
9287 case LoongArch::XVMULWOD_H_BU:
9288 case LoongArch::XVMULWOD_H_BU_B:
9289 case LoongArch::XVMULWOD_Q_D:
9290 case LoongArch::XVMULWOD_Q_DU:
9291 case LoongArch::XVMULWOD_Q_DU_D:
9292 case LoongArch::XVMULWOD_W_H:
9293 case LoongArch::XVMULWOD_W_HU:
9294 case LoongArch::XVMULWOD_W_HU_H:
9295 case LoongArch::XVMUL_B:
9296 case LoongArch::XVMUL_D:
9297 case LoongArch::XVMUL_H:
9298 case LoongArch::XVMUL_W:
9299 case LoongArch::XVNOR_V:
9300 case LoongArch::XVORN_V:
9301 case LoongArch::XVOR_V:
9302 case LoongArch::XVPACKEV_B:
9303 case LoongArch::XVPACKEV_D:
9304 case LoongArch::XVPACKEV_H:
9305 case LoongArch::XVPACKEV_W:
9306 case LoongArch::XVPACKOD_B:
9307 case LoongArch::XVPACKOD_D:
9308 case LoongArch::XVPACKOD_H:
9309 case LoongArch::XVPACKOD_W:
9310 case LoongArch::XVPERM_W:
9311 case LoongArch::XVPICKEV_B:
9312 case LoongArch::XVPICKEV_D:
9313 case LoongArch::XVPICKEV_H:
9314 case LoongArch::XVPICKEV_W:
9315 case LoongArch::XVPICKOD_B:
9316 case LoongArch::XVPICKOD_D:
9317 case LoongArch::XVPICKOD_H:
9318 case LoongArch::XVPICKOD_W:
9319 case LoongArch::XVROTR_B:
9320 case LoongArch::XVROTR_D:
9321 case LoongArch::XVROTR_H:
9322 case LoongArch::XVROTR_W:
9323 case LoongArch::XVSADD_B:
9324 case LoongArch::XVSADD_BU:
9325 case LoongArch::XVSADD_D:
9326 case LoongArch::XVSADD_DU:
9327 case LoongArch::XVSADD_H:
9328 case LoongArch::XVSADD_HU:
9329 case LoongArch::XVSADD_W:
9330 case LoongArch::XVSADD_WU:
9331 case LoongArch::XVSEQ_B:
9332 case LoongArch::XVSEQ_D:
9333 case LoongArch::XVSEQ_H:
9334 case LoongArch::XVSEQ_W:
9335 case LoongArch::XVSIGNCOV_B:
9336 case LoongArch::XVSIGNCOV_D:
9337 case LoongArch::XVSIGNCOV_H:
9338 case LoongArch::XVSIGNCOV_W:
9339 case LoongArch::XVSLE_B:
9340 case LoongArch::XVSLE_BU:
9341 case LoongArch::XVSLE_D:
9342 case LoongArch::XVSLE_DU:
9343 case LoongArch::XVSLE_H:
9344 case LoongArch::XVSLE_HU:
9345 case LoongArch::XVSLE_W:
9346 case LoongArch::XVSLE_WU:
9347 case LoongArch::XVSLL_B:
9348 case LoongArch::XVSLL_D:
9349 case LoongArch::XVSLL_H:
9350 case LoongArch::XVSLL_W:
9351 case LoongArch::XVSLT_B:
9352 case LoongArch::XVSLT_BU:
9353 case LoongArch::XVSLT_D:
9354 case LoongArch::XVSLT_DU:
9355 case LoongArch::XVSLT_H:
9356 case LoongArch::XVSLT_HU:
9357 case LoongArch::XVSLT_W:
9358 case LoongArch::XVSLT_WU:
9359 case LoongArch::XVSRAN_B_H:
9360 case LoongArch::XVSRAN_H_W:
9361 case LoongArch::XVSRAN_W_D:
9362 case LoongArch::XVSRARN_B_H:
9363 case LoongArch::XVSRARN_H_W:
9364 case LoongArch::XVSRARN_W_D:
9365 case LoongArch::XVSRAR_B:
9366 case LoongArch::XVSRAR_D:
9367 case LoongArch::XVSRAR_H:
9368 case LoongArch::XVSRAR_W:
9369 case LoongArch::XVSRA_B:
9370 case LoongArch::XVSRA_D:
9371 case LoongArch::XVSRA_H:
9372 case LoongArch::XVSRA_W:
9373 case LoongArch::XVSRLN_B_H:
9374 case LoongArch::XVSRLN_H_W:
9375 case LoongArch::XVSRLN_W_D:
9376 case LoongArch::XVSRLRN_B_H:
9377 case LoongArch::XVSRLRN_H_W:
9378 case LoongArch::XVSRLRN_W_D:
9379 case LoongArch::XVSRLR_B:
9380 case LoongArch::XVSRLR_D:
9381 case LoongArch::XVSRLR_H:
9382 case LoongArch::XVSRLR_W:
9383 case LoongArch::XVSRL_B:
9384 case LoongArch::XVSRL_D:
9385 case LoongArch::XVSRL_H:
9386 case LoongArch::XVSRL_W:
9387 case LoongArch::XVSSRAN_BU_H:
9388 case LoongArch::XVSSRAN_B_H:
9389 case LoongArch::XVSSRAN_HU_W:
9390 case LoongArch::XVSSRAN_H_W:
9391 case LoongArch::XVSSRAN_WU_D:
9392 case LoongArch::XVSSRAN_W_D:
9393 case LoongArch::XVSSRARN_BU_H:
9394 case LoongArch::XVSSRARN_B_H:
9395 case LoongArch::XVSSRARN_HU_W:
9396 case LoongArch::XVSSRARN_H_W:
9397 case LoongArch::XVSSRARN_WU_D:
9398 case LoongArch::XVSSRARN_W_D:
9399 case LoongArch::XVSSRLN_BU_H:
9400 case LoongArch::XVSSRLN_B_H:
9401 case LoongArch::XVSSRLN_HU_W:
9402 case LoongArch::XVSSRLN_H_W:
9403 case LoongArch::XVSSRLN_WU_D:
9404 case LoongArch::XVSSRLN_W_D:
9405 case LoongArch::XVSSRLRN_BU_H:
9406 case LoongArch::XVSSRLRN_B_H:
9407 case LoongArch::XVSSRLRN_HU_W:
9408 case LoongArch::XVSSRLRN_H_W:
9409 case LoongArch::XVSSRLRN_WU_D:
9410 case LoongArch::XVSSRLRN_W_D:
9411 case LoongArch::XVSSUB_B:
9412 case LoongArch::XVSSUB_BU:
9413 case LoongArch::XVSSUB_D:
9414 case LoongArch::XVSSUB_DU:
9415 case LoongArch::XVSSUB_H:
9416 case LoongArch::XVSSUB_HU:
9417 case LoongArch::XVSSUB_W:
9418 case LoongArch::XVSSUB_WU:
9419 case LoongArch::XVSUBWEV_D_W:
9420 case LoongArch::XVSUBWEV_D_WU:
9421 case LoongArch::XVSUBWEV_H_B:
9422 case LoongArch::XVSUBWEV_H_BU:
9423 case LoongArch::XVSUBWEV_Q_D:
9424 case LoongArch::XVSUBWEV_Q_DU:
9425 case LoongArch::XVSUBWEV_W_H:
9426 case LoongArch::XVSUBWEV_W_HU:
9427 case LoongArch::XVSUBWOD_D_W:
9428 case LoongArch::XVSUBWOD_D_WU:
9429 case LoongArch::XVSUBWOD_H_B:
9430 case LoongArch::XVSUBWOD_H_BU:
9431 case LoongArch::XVSUBWOD_Q_D:
9432 case LoongArch::XVSUBWOD_Q_DU:
9433 case LoongArch::XVSUBWOD_W_H:
9434 case LoongArch::XVSUBWOD_W_HU:
9435 case LoongArch::XVSUB_B:
9436 case LoongArch::XVSUB_D:
9437 case LoongArch::XVSUB_H:
9438 case LoongArch::XVSUB_Q:
9439 case LoongArch::XVSUB_W:
9440 case LoongArch::XVXOR_V: {
9441 switch (OpNum) {
9442 case 2:
9443 // op: xk
9444 return 10;
9445 case 1:
9446 // op: xj
9447 return 5;
9448 case 0:
9449 // op: xd
9450 return 0;
9451 }
9452 break;
9453 }
9454 case LoongArch::FSEL_xD:
9455 case LoongArch::FSEL_xS: {
9456 switch (OpNum) {
9457 case 3:
9458 // op: ca
9459 return 15;
9460 case 2:
9461 // op: fk
9462 return 10;
9463 case 1:
9464 // op: fj
9465 return 5;
9466 case 0:
9467 // op: fd
9468 return 0;
9469 }
9470 break;
9471 }
9472 case LoongArch::CSRXCHG:
9473 case LoongArch::GCSRXCHG: {
9474 switch (OpNum) {
9475 case 3:
9476 // op: csr_num
9477 return 10;
9478 case 2:
9479 // op: rj
9480 return 5;
9481 case 1:
9482 // op: rd
9483 return 0;
9484 }
9485 break;
9486 }
9487 case LoongArch::FMADD_D:
9488 case LoongArch::FMADD_S:
9489 case LoongArch::FMSUB_D:
9490 case LoongArch::FMSUB_S:
9491 case LoongArch::FNMADD_D:
9492 case LoongArch::FNMADD_S:
9493 case LoongArch::FNMSUB_D:
9494 case LoongArch::FNMSUB_S: {
9495 switch (OpNum) {
9496 case 3:
9497 // op: fa
9498 return 15;
9499 case 2:
9500 // op: fk
9501 return 10;
9502 case 1:
9503 // op: fj
9504 return 5;
9505 case 0:
9506 // op: fd
9507 return 0;
9508 }
9509 break;
9510 }
9511 case LoongArch::VINSGR2VR_D: {
9512 switch (OpNum) {
9513 case 3:
9514 // op: imm1
9515 return 10;
9516 case 2:
9517 // op: rj
9518 return 5;
9519 case 1:
9520 // op: vd
9521 return 0;
9522 }
9523 break;
9524 }
9525 case LoongArch::VSTELM_D: {
9526 switch (OpNum) {
9527 case 3:
9528 // op: imm1
9529 return 18;
9530 case 2:
9531 // op: imm8
9532 return 10;
9533 case 1:
9534 // op: rj
9535 return 5;
9536 case 0:
9537 // op: vd
9538 return 0;
9539 }
9540 break;
9541 }
9542 case LoongArch::SC_D:
9543 case LoongArch::SC_W: {
9544 switch (OpNum) {
9545 case 3:
9546 // op: imm14
9547 return 10;
9548 case 2:
9549 // op: rj
9550 return 5;
9551 case 1:
9552 // op: rd
9553 return 0;
9554 }
9555 break;
9556 }
9557 case LoongArch::VINSGR2VR_W: {
9558 switch (OpNum) {
9559 case 3:
9560 // op: imm2
9561 return 10;
9562 case 2:
9563 // op: rj
9564 return 5;
9565 case 1:
9566 // op: vd
9567 return 0;
9568 }
9569 break;
9570 }
9571 case LoongArch::XVINSGR2VR_D: {
9572 switch (OpNum) {
9573 case 3:
9574 // op: imm2
9575 return 10;
9576 case 2:
9577 // op: rj
9578 return 5;
9579 case 1:
9580 // op: xd
9581 return 0;
9582 }
9583 break;
9584 }
9585 case LoongArch::XVINSVE0_D: {
9586 switch (OpNum) {
9587 case 3:
9588 // op: imm2
9589 return 10;
9590 case 2:
9591 // op: xj
9592 return 5;
9593 case 1:
9594 // op: xd
9595 return 0;
9596 }
9597 break;
9598 }
9599 case LoongArch::ALSL_D:
9600 case LoongArch::ALSL_W:
9601 case LoongArch::ALSL_WU:
9602 case LoongArch::BYTEPICK_W: {
9603 switch (OpNum) {
9604 case 3:
9605 // op: imm2
9606 return 15;
9607 case 2:
9608 // op: rk
9609 return 10;
9610 case 1:
9611 // op: rj
9612 return 5;
9613 case 0:
9614 // op: rd
9615 return 0;
9616 }
9617 break;
9618 }
9619 case LoongArch::VSTELM_W: {
9620 switch (OpNum) {
9621 case 3:
9622 // op: imm2
9623 return 18;
9624 case 2:
9625 // op: imm8
9626 return 10;
9627 case 1:
9628 // op: rj
9629 return 5;
9630 case 0:
9631 // op: vd
9632 return 0;
9633 }
9634 break;
9635 }
9636 case LoongArch::XVSTELM_D: {
9637 switch (OpNum) {
9638 case 3:
9639 // op: imm2
9640 return 18;
9641 case 2:
9642 // op: imm8
9643 return 10;
9644 case 1:
9645 // op: rj
9646 return 5;
9647 case 0:
9648 // op: xd
9649 return 0;
9650 }
9651 break;
9652 }
9653 case LoongArch::VINSGR2VR_H: {
9654 switch (OpNum) {
9655 case 3:
9656 // op: imm3
9657 return 10;
9658 case 2:
9659 // op: rj
9660 return 5;
9661 case 1:
9662 // op: vd
9663 return 0;
9664 }
9665 break;
9666 }
9667 case LoongArch::XVINSGR2VR_W: {
9668 switch (OpNum) {
9669 case 3:
9670 // op: imm3
9671 return 10;
9672 case 2:
9673 // op: rj
9674 return 5;
9675 case 1:
9676 // op: xd
9677 return 0;
9678 }
9679 break;
9680 }
9681 case LoongArch::XVINSVE0_W: {
9682 switch (OpNum) {
9683 case 3:
9684 // op: imm3
9685 return 10;
9686 case 2:
9687 // op: xj
9688 return 5;
9689 case 1:
9690 // op: xd
9691 return 0;
9692 }
9693 break;
9694 }
9695 case LoongArch::BYTEPICK_D: {
9696 switch (OpNum) {
9697 case 3:
9698 // op: imm3
9699 return 15;
9700 case 2:
9701 // op: rk
9702 return 10;
9703 case 1:
9704 // op: rj
9705 return 5;
9706 case 0:
9707 // op: rd
9708 return 0;
9709 }
9710 break;
9711 }
9712 case LoongArch::VSTELM_H: {
9713 switch (OpNum) {
9714 case 3:
9715 // op: imm3
9716 return 18;
9717 case 2:
9718 // op: imm8
9719 return 10;
9720 case 1:
9721 // op: rj
9722 return 5;
9723 case 0:
9724 // op: vd
9725 return 0;
9726 }
9727 break;
9728 }
9729 case LoongArch::XVSTELM_W: {
9730 switch (OpNum) {
9731 case 3:
9732 // op: imm3
9733 return 18;
9734 case 2:
9735 // op: imm8
9736 return 10;
9737 case 1:
9738 // op: rj
9739 return 5;
9740 case 0:
9741 // op: xd
9742 return 0;
9743 }
9744 break;
9745 }
9746 case LoongArch::VINSGR2VR_B: {
9747 switch (OpNum) {
9748 case 3:
9749 // op: imm4
9750 return 10;
9751 case 2:
9752 // op: rj
9753 return 5;
9754 case 1:
9755 // op: vd
9756 return 0;
9757 }
9758 break;
9759 }
9760 case LoongArch::VSRANI_B_H:
9761 case LoongArch::VSRARNI_B_H:
9762 case LoongArch::VSRLNI_B_H:
9763 case LoongArch::VSRLRNI_B_H:
9764 case LoongArch::VSSRANI_BU_H:
9765 case LoongArch::VSSRANI_B_H:
9766 case LoongArch::VSSRARNI_BU_H:
9767 case LoongArch::VSSRARNI_B_H:
9768 case LoongArch::VSSRLNI_BU_H:
9769 case LoongArch::VSSRLNI_B_H:
9770 case LoongArch::VSSRLRNI_BU_H:
9771 case LoongArch::VSSRLRNI_B_H: {
9772 switch (OpNum) {
9773 case 3:
9774 // op: imm4
9775 return 10;
9776 case 2:
9777 // op: vj
9778 return 5;
9779 case 1:
9780 // op: vd
9781 return 0;
9782 }
9783 break;
9784 }
9785 case LoongArch::XVSRANI_B_H:
9786 case LoongArch::XVSRARNI_B_H:
9787 case LoongArch::XVSRLNI_B_H:
9788 case LoongArch::XVSRLRNI_B_H:
9789 case LoongArch::XVSSRANI_BU_H:
9790 case LoongArch::XVSSRANI_B_H:
9791 case LoongArch::XVSSRARNI_BU_H:
9792 case LoongArch::XVSSRARNI_B_H:
9793 case LoongArch::XVSSRLNI_BU_H:
9794 case LoongArch::XVSSRLNI_B_H:
9795 case LoongArch::XVSSRLRNI_BU_H:
9796 case LoongArch::XVSSRLRNI_B_H: {
9797 switch (OpNum) {
9798 case 3:
9799 // op: imm4
9800 return 10;
9801 case 2:
9802 // op: xj
9803 return 5;
9804 case 1:
9805 // op: xd
9806 return 0;
9807 }
9808 break;
9809 }
9810 case LoongArch::VSTELM_B: {
9811 switch (OpNum) {
9812 case 3:
9813 // op: imm4
9814 return 18;
9815 case 2:
9816 // op: imm8
9817 return 10;
9818 case 1:
9819 // op: rj
9820 return 5;
9821 case 0:
9822 // op: vd
9823 return 0;
9824 }
9825 break;
9826 }
9827 case LoongArch::XVSTELM_H: {
9828 switch (OpNum) {
9829 case 3:
9830 // op: imm4
9831 return 18;
9832 case 2:
9833 // op: imm8
9834 return 10;
9835 case 1:
9836 // op: rj
9837 return 5;
9838 case 0:
9839 // op: xd
9840 return 0;
9841 }
9842 break;
9843 }
9844 case LoongArch::VFRSTPI_B:
9845 case LoongArch::VFRSTPI_H:
9846 case LoongArch::VSRANI_H_W:
9847 case LoongArch::VSRARNI_H_W:
9848 case LoongArch::VSRLNI_H_W:
9849 case LoongArch::VSRLRNI_H_W:
9850 case LoongArch::VSSRANI_HU_W:
9851 case LoongArch::VSSRANI_H_W:
9852 case LoongArch::VSSRARNI_HU_W:
9853 case LoongArch::VSSRARNI_H_W:
9854 case LoongArch::VSSRLNI_HU_W:
9855 case LoongArch::VSSRLNI_H_W:
9856 case LoongArch::VSSRLRNI_HU_W:
9857 case LoongArch::VSSRLRNI_H_W: {
9858 switch (OpNum) {
9859 case 3:
9860 // op: imm5
9861 return 10;
9862 case 2:
9863 // op: vj
9864 return 5;
9865 case 1:
9866 // op: vd
9867 return 0;
9868 }
9869 break;
9870 }
9871 case LoongArch::XVFRSTPI_B:
9872 case LoongArch::XVFRSTPI_H:
9873 case LoongArch::XVSRANI_H_W:
9874 case LoongArch::XVSRARNI_H_W:
9875 case LoongArch::XVSRLNI_H_W:
9876 case LoongArch::XVSRLRNI_H_W:
9877 case LoongArch::XVSSRANI_HU_W:
9878 case LoongArch::XVSSRANI_H_W:
9879 case LoongArch::XVSSRARNI_HU_W:
9880 case LoongArch::XVSSRARNI_H_W:
9881 case LoongArch::XVSSRLNI_HU_W:
9882 case LoongArch::XVSSRLNI_H_W:
9883 case LoongArch::XVSSRLRNI_HU_W:
9884 case LoongArch::XVSSRLRNI_H_W: {
9885 switch (OpNum) {
9886 case 3:
9887 // op: imm5
9888 return 10;
9889 case 2:
9890 // op: xj
9891 return 5;
9892 case 1:
9893 // op: xd
9894 return 0;
9895 }
9896 break;
9897 }
9898 case LoongArch::XVSTELM_B: {
9899 switch (OpNum) {
9900 case 3:
9901 // op: imm5
9902 return 18;
9903 case 2:
9904 // op: imm8
9905 return 10;
9906 case 1:
9907 // op: rj
9908 return 5;
9909 case 0:
9910 // op: xd
9911 return 0;
9912 }
9913 break;
9914 }
9915 case LoongArch::VSRANI_W_D:
9916 case LoongArch::VSRARNI_W_D:
9917 case LoongArch::VSRLNI_W_D:
9918 case LoongArch::VSRLRNI_W_D:
9919 case LoongArch::VSSRANI_WU_D:
9920 case LoongArch::VSSRANI_W_D:
9921 case LoongArch::VSSRARNI_WU_D:
9922 case LoongArch::VSSRARNI_W_D:
9923 case LoongArch::VSSRLNI_WU_D:
9924 case LoongArch::VSSRLNI_W_D:
9925 case LoongArch::VSSRLRNI_WU_D:
9926 case LoongArch::VSSRLRNI_W_D: {
9927 switch (OpNum) {
9928 case 3:
9929 // op: imm6
9930 return 10;
9931 case 2:
9932 // op: vj
9933 return 5;
9934 case 1:
9935 // op: vd
9936 return 0;
9937 }
9938 break;
9939 }
9940 case LoongArch::XVSRANI_W_D:
9941 case LoongArch::XVSRARNI_W_D:
9942 case LoongArch::XVSRLNI_W_D:
9943 case LoongArch::XVSRLRNI_W_D:
9944 case LoongArch::XVSSRANI_WU_D:
9945 case LoongArch::XVSSRANI_W_D:
9946 case LoongArch::XVSSRARNI_WU_D:
9947 case LoongArch::XVSSRARNI_W_D:
9948 case LoongArch::XVSSRLNI_WU_D:
9949 case LoongArch::XVSSRLNI_W_D:
9950 case LoongArch::XVSSRLRNI_WU_D:
9951 case LoongArch::XVSSRLRNI_W_D: {
9952 switch (OpNum) {
9953 case 3:
9954 // op: imm6
9955 return 10;
9956 case 2:
9957 // op: xj
9958 return 5;
9959 case 1:
9960 // op: xd
9961 return 0;
9962 }
9963 break;
9964 }
9965 case LoongArch::VSRANI_D_Q:
9966 case LoongArch::VSRARNI_D_Q:
9967 case LoongArch::VSRLNI_D_Q:
9968 case LoongArch::VSRLRNI_D_Q:
9969 case LoongArch::VSSRANI_DU_Q:
9970 case LoongArch::VSSRANI_D_Q:
9971 case LoongArch::VSSRARNI_DU_Q:
9972 case LoongArch::VSSRARNI_D_Q:
9973 case LoongArch::VSSRLNI_DU_Q:
9974 case LoongArch::VSSRLNI_D_Q:
9975 case LoongArch::VSSRLRNI_DU_Q:
9976 case LoongArch::VSSRLRNI_D_Q: {
9977 switch (OpNum) {
9978 case 3:
9979 // op: imm7
9980 return 10;
9981 case 2:
9982 // op: vj
9983 return 5;
9984 case 1:
9985 // op: vd
9986 return 0;
9987 }
9988 break;
9989 }
9990 case LoongArch::XVSRANI_D_Q:
9991 case LoongArch::XVSRARNI_D_Q:
9992 case LoongArch::XVSRLNI_D_Q:
9993 case LoongArch::XVSRLRNI_D_Q:
9994 case LoongArch::XVSSRANI_DU_Q:
9995 case LoongArch::XVSSRANI_D_Q:
9996 case LoongArch::XVSSRARNI_DU_Q:
9997 case LoongArch::XVSSRARNI_D_Q:
9998 case LoongArch::XVSSRLNI_DU_Q:
9999 case LoongArch::XVSSRLNI_D_Q:
10000 case LoongArch::XVSSRLRNI_DU_Q:
10001 case LoongArch::XVSSRLRNI_D_Q: {
10002 switch (OpNum) {
10003 case 3:
10004 // op: imm7
10005 return 10;
10006 case 2:
10007 // op: xj
10008 return 5;
10009 case 1:
10010 // op: xd
10011 return 0;
10012 }
10013 break;
10014 }
10015 case LoongArch::VBITSELI_B:
10016 case LoongArch::VEXTRINS_B:
10017 case LoongArch::VEXTRINS_D:
10018 case LoongArch::VEXTRINS_H:
10019 case LoongArch::VEXTRINS_W:
10020 case LoongArch::VPERMI_W:
10021 case LoongArch::VSHUF4I_D: {
10022 switch (OpNum) {
10023 case 3:
10024 // op: imm8
10025 return 10;
10026 case 2:
10027 // op: vj
10028 return 5;
10029 case 1:
10030 // op: vd
10031 return 0;
10032 }
10033 break;
10034 }
10035 case LoongArch::XVBITSELI_B:
10036 case LoongArch::XVEXTRINS_B:
10037 case LoongArch::XVEXTRINS_D:
10038 case LoongArch::XVEXTRINS_H:
10039 case LoongArch::XVEXTRINS_W:
10040 case LoongArch::XVPERMI_Q:
10041 case LoongArch::XVPERMI_W:
10042 case LoongArch::XVSHUF4I_D: {
10043 switch (OpNum) {
10044 case 3:
10045 // op: imm8
10046 return 10;
10047 case 2:
10048 // op: xj
10049 return 5;
10050 case 1:
10051 // op: xd
10052 return 0;
10053 }
10054 break;
10055 }
10056 case LoongArch::BSTRINS_D: {
10057 switch (OpNum) {
10058 case 3:
10059 // op: msbd
10060 return 16;
10061 case 4:
10062 // op: lsbd
10063 return 10;
10064 case 2:
10065 // op: rj
10066 return 5;
10067 case 1:
10068 // op: rd
10069 return 0;
10070 }
10071 break;
10072 }
10073 case LoongArch::BSTRINS_W: {
10074 switch (OpNum) {
10075 case 3:
10076 // op: msbw
10077 return 16;
10078 case 4:
10079 // op: lsbw
10080 return 10;
10081 case 2:
10082 // op: rj
10083 return 5;
10084 case 1:
10085 // op: rd
10086 return 0;
10087 }
10088 break;
10089 }
10090 case LoongArch::VBITSEL_V:
10091 case LoongArch::VFMADD_D:
10092 case LoongArch::VFMADD_S:
10093 case LoongArch::VFMSUB_D:
10094 case LoongArch::VFMSUB_S:
10095 case LoongArch::VFNMADD_D:
10096 case LoongArch::VFNMADD_S:
10097 case LoongArch::VFNMSUB_D:
10098 case LoongArch::VFNMSUB_S:
10099 case LoongArch::VSHUF_B: {
10100 switch (OpNum) {
10101 case 3:
10102 // op: va
10103 return 15;
10104 case 2:
10105 // op: vk
10106 return 10;
10107 case 1:
10108 // op: vj
10109 return 5;
10110 case 0:
10111 // op: vd
10112 return 0;
10113 }
10114 break;
10115 }
10116 case LoongArch::VFRSTP_B:
10117 case LoongArch::VFRSTP_H:
10118 case LoongArch::VMADDWEV_D_W:
10119 case LoongArch::VMADDWEV_D_WU:
10120 case LoongArch::VMADDWEV_D_WU_W:
10121 case LoongArch::VMADDWEV_H_B:
10122 case LoongArch::VMADDWEV_H_BU:
10123 case LoongArch::VMADDWEV_H_BU_B:
10124 case LoongArch::VMADDWEV_Q_D:
10125 case LoongArch::VMADDWEV_Q_DU:
10126 case LoongArch::VMADDWEV_Q_DU_D:
10127 case LoongArch::VMADDWEV_W_H:
10128 case LoongArch::VMADDWEV_W_HU:
10129 case LoongArch::VMADDWEV_W_HU_H:
10130 case LoongArch::VMADDWOD_D_W:
10131 case LoongArch::VMADDWOD_D_WU:
10132 case LoongArch::VMADDWOD_D_WU_W:
10133 case LoongArch::VMADDWOD_H_B:
10134 case LoongArch::VMADDWOD_H_BU:
10135 case LoongArch::VMADDWOD_H_BU_B:
10136 case LoongArch::VMADDWOD_Q_D:
10137 case LoongArch::VMADDWOD_Q_DU:
10138 case LoongArch::VMADDWOD_Q_DU_D:
10139 case LoongArch::VMADDWOD_W_H:
10140 case LoongArch::VMADDWOD_W_HU:
10141 case LoongArch::VMADDWOD_W_HU_H:
10142 case LoongArch::VMADD_B:
10143 case LoongArch::VMADD_D:
10144 case LoongArch::VMADD_H:
10145 case LoongArch::VMADD_W:
10146 case LoongArch::VMSUB_B:
10147 case LoongArch::VMSUB_D:
10148 case LoongArch::VMSUB_H:
10149 case LoongArch::VMSUB_W:
10150 case LoongArch::VSHUF_D:
10151 case LoongArch::VSHUF_H:
10152 case LoongArch::VSHUF_W: {
10153 switch (OpNum) {
10154 case 3:
10155 // op: vk
10156 return 10;
10157 case 2:
10158 // op: vj
10159 return 5;
10160 case 1:
10161 // op: vd
10162 return 0;
10163 }
10164 break;
10165 }
10166 case LoongArch::XVBITSEL_V:
10167 case LoongArch::XVFMADD_D:
10168 case LoongArch::XVFMADD_S:
10169 case LoongArch::XVFMSUB_D:
10170 case LoongArch::XVFMSUB_S:
10171 case LoongArch::XVFNMADD_D:
10172 case LoongArch::XVFNMADD_S:
10173 case LoongArch::XVFNMSUB_D:
10174 case LoongArch::XVFNMSUB_S:
10175 case LoongArch::XVSHUF_B: {
10176 switch (OpNum) {
10177 case 3:
10178 // op: xa
10179 return 15;
10180 case 2:
10181 // op: xk
10182 return 10;
10183 case 1:
10184 // op: xj
10185 return 5;
10186 case 0:
10187 // op: xd
10188 return 0;
10189 }
10190 break;
10191 }
10192 case LoongArch::XVFRSTP_B:
10193 case LoongArch::XVFRSTP_H:
10194 case LoongArch::XVMADDWEV_D_W:
10195 case LoongArch::XVMADDWEV_D_WU:
10196 case LoongArch::XVMADDWEV_D_WU_W:
10197 case LoongArch::XVMADDWEV_H_B:
10198 case LoongArch::XVMADDWEV_H_BU:
10199 case LoongArch::XVMADDWEV_H_BU_B:
10200 case LoongArch::XVMADDWEV_Q_D:
10201 case LoongArch::XVMADDWEV_Q_DU:
10202 case LoongArch::XVMADDWEV_Q_DU_D:
10203 case LoongArch::XVMADDWEV_W_H:
10204 case LoongArch::XVMADDWEV_W_HU:
10205 case LoongArch::XVMADDWEV_W_HU_H:
10206 case LoongArch::XVMADDWOD_D_W:
10207 case LoongArch::XVMADDWOD_D_WU:
10208 case LoongArch::XVMADDWOD_D_WU_W:
10209 case LoongArch::XVMADDWOD_H_B:
10210 case LoongArch::XVMADDWOD_H_BU:
10211 case LoongArch::XVMADDWOD_H_BU_B:
10212 case LoongArch::XVMADDWOD_Q_D:
10213 case LoongArch::XVMADDWOD_Q_DU:
10214 case LoongArch::XVMADDWOD_Q_DU_D:
10215 case LoongArch::XVMADDWOD_W_H:
10216 case LoongArch::XVMADDWOD_W_HU:
10217 case LoongArch::XVMADDWOD_W_HU_H:
10218 case LoongArch::XVMADD_B:
10219 case LoongArch::XVMADD_D:
10220 case LoongArch::XVMADD_H:
10221 case LoongArch::XVMADD_W:
10222 case LoongArch::XVMSUB_B:
10223 case LoongArch::XVMSUB_D:
10224 case LoongArch::XVMSUB_H:
10225 case LoongArch::XVMSUB_W:
10226 case LoongArch::XVSHUF_D:
10227 case LoongArch::XVSHUF_H:
10228 case LoongArch::XVSHUF_W: {
10229 switch (OpNum) {
10230 case 3:
10231 // op: xk
10232 return 10;
10233 case 2:
10234 // op: xj
10235 return 5;
10236 case 1:
10237 // op: xd
10238 return 0;
10239 }
10240 break;
10241 }
10242 }
10243 std::string msg;
10244 raw_string_ostream Msg(msg);
10245 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
10246 report_fatal_error(Msg.str().c_str());
10247}
10248
10249#endif // GET_OPERAND_BIT_OFFSET
10250
10251