1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(20608), // ADD16mc
309 UINT64_C(20656), // ADD16mi
310 UINT64_C(20624), // ADD16mm
311 UINT64_C(20640), // ADD16mn
312 UINT64_C(20656), // ADD16mp
313 UINT64_C(20608), // ADD16mr
314 UINT64_C(20480), // ADD16rc
315 UINT64_C(20528), // ADD16ri
316 UINT64_C(20496), // ADD16rm
317 UINT64_C(20512), // ADD16rn
318 UINT64_C(20528), // ADD16rp
319 UINT64_C(20480), // ADD16rr
320 UINT64_C(20672), // ADD8mc
321 UINT64_C(20720), // ADD8mi
322 UINT64_C(20688), // ADD8mm
323 UINT64_C(20704), // ADD8mn
324 UINT64_C(20720), // ADD8mp
325 UINT64_C(20672), // ADD8mr
326 UINT64_C(20544), // ADD8rc
327 UINT64_C(20592), // ADD8ri
328 UINT64_C(20560), // ADD8rm
329 UINT64_C(20576), // ADD8rn
330 UINT64_C(20592), // ADD8rp
331 UINT64_C(20544), // ADD8rr
332 UINT64_C(24704), // ADDC16mc
333 UINT64_C(24752), // ADDC16mi
334 UINT64_C(24720), // ADDC16mm
335 UINT64_C(24736), // ADDC16mn
336 UINT64_C(24752), // ADDC16mp
337 UINT64_C(24704), // ADDC16mr
338 UINT64_C(24576), // ADDC16rc
339 UINT64_C(24624), // ADDC16ri
340 UINT64_C(24592), // ADDC16rm
341 UINT64_C(24608), // ADDC16rn
342 UINT64_C(24624), // ADDC16rp
343 UINT64_C(24576), // ADDC16rr
344 UINT64_C(24768), // ADDC8mc
345 UINT64_C(24816), // ADDC8mi
346 UINT64_C(24784), // ADDC8mm
347 UINT64_C(24800), // ADDC8mn
348 UINT64_C(24816), // ADDC8mp
349 UINT64_C(24768), // ADDC8mr
350 UINT64_C(24640), // ADDC8rc
351 UINT64_C(24688), // ADDC8ri
352 UINT64_C(24656), // ADDC8rm
353 UINT64_C(24672), // ADDC8rn
354 UINT64_C(24688), // ADDC8rp
355 UINT64_C(24640), // ADDC8rr
356 UINT64_C(0), // ADDframe
357 UINT64_C(0), // ADJCALLSTACKDOWN
358 UINT64_C(0), // ADJCALLSTACKUP
359 UINT64_C(61568), // AND16mc
360 UINT64_C(61616), // AND16mi
361 UINT64_C(61584), // AND16mm
362 UINT64_C(61600), // AND16mn
363 UINT64_C(61616), // AND16mp
364 UINT64_C(61568), // AND16mr
365 UINT64_C(61440), // AND16rc
366 UINT64_C(61488), // AND16ri
367 UINT64_C(61456), // AND16rm
368 UINT64_C(61472), // AND16rn
369 UINT64_C(61488), // AND16rp
370 UINT64_C(61440), // AND16rr
371 UINT64_C(61632), // AND8mc
372 UINT64_C(61680), // AND8mi
373 UINT64_C(61648), // AND8mm
374 UINT64_C(61664), // AND8mn
375 UINT64_C(61680), // AND8mp
376 UINT64_C(61632), // AND8mr
377 UINT64_C(61504), // AND8rc
378 UINT64_C(61552), // AND8ri
379 UINT64_C(61520), // AND8rm
380 UINT64_C(61536), // AND8rn
381 UINT64_C(61552), // AND8rp
382 UINT64_C(61504), // AND8rr
383 UINT64_C(49280), // BIC16mc
384 UINT64_C(49328), // BIC16mi
385 UINT64_C(49296), // BIC16mm
386 UINT64_C(49312), // BIC16mn
387 UINT64_C(49328), // BIC16mp
388 UINT64_C(49280), // BIC16mr
389 UINT64_C(49152), // BIC16rc
390 UINT64_C(49200), // BIC16ri
391 UINT64_C(49168), // BIC16rm
392 UINT64_C(49184), // BIC16rn
393 UINT64_C(49200), // BIC16rp
394 UINT64_C(49152), // BIC16rr
395 UINT64_C(49344), // BIC8mc
396 UINT64_C(49392), // BIC8mi
397 UINT64_C(49360), // BIC8mm
398 UINT64_C(49376), // BIC8mn
399 UINT64_C(49392), // BIC8mp
400 UINT64_C(49344), // BIC8mr
401 UINT64_C(49216), // BIC8rc
402 UINT64_C(49264), // BIC8ri
403 UINT64_C(49232), // BIC8rm
404 UINT64_C(49248), // BIC8rn
405 UINT64_C(49264), // BIC8rp
406 UINT64_C(49216), // BIC8rr
407 UINT64_C(53376), // BIS16mc
408 UINT64_C(53424), // BIS16mi
409 UINT64_C(53392), // BIS16mm
410 UINT64_C(53408), // BIS16mn
411 UINT64_C(53424), // BIS16mp
412 UINT64_C(53376), // BIS16mr
413 UINT64_C(53248), // BIS16rc
414 UINT64_C(53296), // BIS16ri
415 UINT64_C(53264), // BIS16rm
416 UINT64_C(53280), // BIS16rn
417 UINT64_C(53296), // BIS16rp
418 UINT64_C(53248), // BIS16rr
419 UINT64_C(53440), // BIS8mc
420 UINT64_C(53488), // BIS8mi
421 UINT64_C(53456), // BIS8mm
422 UINT64_C(53472), // BIS8mn
423 UINT64_C(53488), // BIS8mp
424 UINT64_C(53440), // BIS8mr
425 UINT64_C(53312), // BIS8rc
426 UINT64_C(53360), // BIS8ri
427 UINT64_C(53328), // BIS8rm
428 UINT64_C(53344), // BIS8rn
429 UINT64_C(53360), // BIS8rp
430 UINT64_C(53312), // BIS8rr
431 UINT64_C(45184), // BIT16mc
432 UINT64_C(45232), // BIT16mi
433 UINT64_C(45200), // BIT16mm
434 UINT64_C(45216), // BIT16mn
435 UINT64_C(45232), // BIT16mp
436 UINT64_C(45184), // BIT16mr
437 UINT64_C(45056), // BIT16rc
438 UINT64_C(45104), // BIT16ri
439 UINT64_C(45072), // BIT16rm
440 UINT64_C(45088), // BIT16rn
441 UINT64_C(45104), // BIT16rp
442 UINT64_C(45056), // BIT16rr
443 UINT64_C(45248), // BIT8mc
444 UINT64_C(45296), // BIT8mi
445 UINT64_C(45264), // BIT8mm
446 UINT64_C(45280), // BIT8mn
447 UINT64_C(45296), // BIT8mp
448 UINT64_C(45248), // BIT8mr
449 UINT64_C(45120), // BIT8rc
450 UINT64_C(45168), // BIT8ri
451 UINT64_C(45136), // BIT8rm
452 UINT64_C(45152), // BIT8rn
453 UINT64_C(45168), // BIT8rp
454 UINT64_C(45120), // BIT8rr
455 UINT64_C(16432), // Bi
456 UINT64_C(16400), // Bm
457 UINT64_C(16384), // Br
458 UINT64_C(4784), // CALLi
459 UINT64_C(4752), // CALLm
460 UINT64_C(4768), // CALLn
461 UINT64_C(4784), // CALLp
462 UINT64_C(4736), // CALLr
463 UINT64_C(36992), // CMP16mc
464 UINT64_C(37040), // CMP16mi
465 UINT64_C(37008), // CMP16mm
466 UINT64_C(37024), // CMP16mn
467 UINT64_C(37040), // CMP16mp
468 UINT64_C(36992), // CMP16mr
469 UINT64_C(36864), // CMP16rc
470 UINT64_C(36912), // CMP16ri
471 UINT64_C(36880), // CMP16rm
472 UINT64_C(36896), // CMP16rn
473 UINT64_C(36912), // CMP16rp
474 UINT64_C(36864), // CMP16rr
475 UINT64_C(37056), // CMP8mc
476 UINT64_C(37104), // CMP8mi
477 UINT64_C(37072), // CMP8mm
478 UINT64_C(37088), // CMP8mn
479 UINT64_C(37104), // CMP8mp
480 UINT64_C(37056), // CMP8mr
481 UINT64_C(36928), // CMP8rc
482 UINT64_C(36976), // CMP8ri
483 UINT64_C(36944), // CMP8rm
484 UINT64_C(36960), // CMP8rn
485 UINT64_C(36976), // CMP8rp
486 UINT64_C(36928), // CMP8rr
487 UINT64_C(41088), // DADD16mc
488 UINT64_C(41136), // DADD16mi
489 UINT64_C(41104), // DADD16mm
490 UINT64_C(41120), // DADD16mn
491 UINT64_C(41136), // DADD16mp
492 UINT64_C(41088), // DADD16mr
493 UINT64_C(40960), // DADD16rc
494 UINT64_C(41008), // DADD16ri
495 UINT64_C(40976), // DADD16rm
496 UINT64_C(40992), // DADD16rn
497 UINT64_C(41008), // DADD16rp
498 UINT64_C(40960), // DADD16rr
499 UINT64_C(41152), // DADD8mc
500 UINT64_C(41200), // DADD8mi
501 UINT64_C(41168), // DADD8mm
502 UINT64_C(41184), // DADD8mn
503 UINT64_C(41200), // DADD8mp
504 UINT64_C(41152), // DADD8mr
505 UINT64_C(41024), // DADD8rc
506 UINT64_C(41072), // DADD8ri
507 UINT64_C(41040), // DADD8rm
508 UINT64_C(41056), // DADD8rn
509 UINT64_C(41072), // DADD8rp
510 UINT64_C(41024), // DADD8rr
511 UINT64_C(8192), // JCC
512 UINT64_C(15360), // JMP
513 UINT64_C(16512), // MOV16mc
514 UINT64_C(16560), // MOV16mi
515 UINT64_C(16528), // MOV16mm
516 UINT64_C(16544), // MOV16mn
517 UINT64_C(16512), // MOV16mr
518 UINT64_C(16384), // MOV16rc
519 UINT64_C(16432), // MOV16ri
520 UINT64_C(16400), // MOV16rm
521 UINT64_C(16416), // MOV16rn
522 UINT64_C(16432), // MOV16rp
523 UINT64_C(16384), // MOV16rr
524 UINT64_C(16576), // MOV8mc
525 UINT64_C(16624), // MOV8mi
526 UINT64_C(16592), // MOV8mm
527 UINT64_C(16608), // MOV8mn
528 UINT64_C(16576), // MOV8mr
529 UINT64_C(16448), // MOV8rc
530 UINT64_C(16496), // MOV8ri
531 UINT64_C(16464), // MOV8rm
532 UINT64_C(16480), // MOV8rn
533 UINT64_C(16496), // MOV8rp
534 UINT64_C(16448), // MOV8rr
535 UINT64_C(16464), // MOVZX16rm8
536 UINT64_C(16448), // MOVZX16rr8
537 UINT64_C(16688), // POP16r
538 UINT64_C(4608), // PUSH16c
539 UINT64_C(4656), // PUSH16i
540 UINT64_C(4608), // PUSH16r
541 UINT64_C(4672), // PUSH8r
542 UINT64_C(16688), // RET
543 UINT64_C(4864), // RETI
544 UINT64_C(4368), // RRA16m
545 UINT64_C(4384), // RRA16n
546 UINT64_C(4400), // RRA16p
547 UINT64_C(4352), // RRA16r
548 UINT64_C(4432), // RRA8m
549 UINT64_C(4448), // RRA8n
550 UINT64_C(4464), // RRA8p
551 UINT64_C(4416), // RRA8r
552 UINT64_C(4112), // RRC16m
553 UINT64_C(4128), // RRC16n
554 UINT64_C(4144), // RRC16p
555 UINT64_C(4096), // RRC16r
556 UINT64_C(4176), // RRC8m
557 UINT64_C(4192), // RRC8n
558 UINT64_C(4208), // RRC8p
559 UINT64_C(4160), // RRC8r
560 UINT64_C(0), // Rrcl16
561 UINT64_C(0), // Rrcl8
562 UINT64_C(4496), // SEXT16m
563 UINT64_C(4512), // SEXT16n
564 UINT64_C(4528), // SEXT16p
565 UINT64_C(4480), // SEXT16r
566 UINT64_C(32896), // SUB16mc
567 UINT64_C(32944), // SUB16mi
568 UINT64_C(32912), // SUB16mm
569 UINT64_C(32928), // SUB16mn
570 UINT64_C(32944), // SUB16mp
571 UINT64_C(32896), // SUB16mr
572 UINT64_C(32768), // SUB16rc
573 UINT64_C(32816), // SUB16ri
574 UINT64_C(32784), // SUB16rm
575 UINT64_C(32800), // SUB16rn
576 UINT64_C(32816), // SUB16rp
577 UINT64_C(32768), // SUB16rr
578 UINT64_C(32960), // SUB8mc
579 UINT64_C(33008), // SUB8mi
580 UINT64_C(32976), // SUB8mm
581 UINT64_C(32992), // SUB8mn
582 UINT64_C(33008), // SUB8mp
583 UINT64_C(32960), // SUB8mr
584 UINT64_C(32832), // SUB8rc
585 UINT64_C(32880), // SUB8ri
586 UINT64_C(32848), // SUB8rm
587 UINT64_C(32864), // SUB8rn
588 UINT64_C(32880), // SUB8rp
589 UINT64_C(32832), // SUB8rr
590 UINT64_C(28800), // SUBC16mc
591 UINT64_C(28848), // SUBC16mi
592 UINT64_C(28816), // SUBC16mm
593 UINT64_C(28832), // SUBC16mn
594 UINT64_C(28848), // SUBC16mp
595 UINT64_C(28800), // SUBC16mr
596 UINT64_C(28672), // SUBC16rc
597 UINT64_C(28720), // SUBC16ri
598 UINT64_C(28688), // SUBC16rm
599 UINT64_C(28704), // SUBC16rn
600 UINT64_C(28720), // SUBC16rp
601 UINT64_C(28672), // SUBC16rr
602 UINT64_C(28864), // SUBC8mc
603 UINT64_C(28912), // SUBC8mi
604 UINT64_C(28880), // SUBC8mm
605 UINT64_C(28896), // SUBC8mn
606 UINT64_C(28912), // SUBC8mp
607 UINT64_C(28864), // SUBC8mr
608 UINT64_C(28736), // SUBC8rc
609 UINT64_C(28784), // SUBC8ri
610 UINT64_C(28752), // SUBC8rm
611 UINT64_C(28768), // SUBC8rn
612 UINT64_C(28784), // SUBC8rp
613 UINT64_C(28736), // SUBC8rr
614 UINT64_C(4240), // SWPB16m
615 UINT64_C(4256), // SWPB16n
616 UINT64_C(4272), // SWPB16p
617 UINT64_C(4224), // SWPB16r
618 UINT64_C(0), // Select16
619 UINT64_C(0), // Select8
620 UINT64_C(0), // Shl16
621 UINT64_C(0), // Shl8
622 UINT64_C(0), // Sra16
623 UINT64_C(0), // Sra8
624 UINT64_C(0), // Srl16
625 UINT64_C(0), // Srl8
626 UINT64_C(57472), // XOR16mc
627 UINT64_C(57520), // XOR16mi
628 UINT64_C(57488), // XOR16mm
629 UINT64_C(57504), // XOR16mn
630 UINT64_C(57520), // XOR16mp
631 UINT64_C(57472), // XOR16mr
632 UINT64_C(57344), // XOR16rc
633 UINT64_C(57392), // XOR16ri
634 UINT64_C(57360), // XOR16rm
635 UINT64_C(57376), // XOR16rn
636 UINT64_C(57392), // XOR16rp
637 UINT64_C(57344), // XOR16rr
638 UINT64_C(57536), // XOR8mc
639 UINT64_C(57584), // XOR8mi
640 UINT64_C(57552), // XOR8mm
641 UINT64_C(57568), // XOR8mn
642 UINT64_C(57584), // XOR8mp
643 UINT64_C(57536), // XOR8mr
644 UINT64_C(57408), // XOR8rc
645 UINT64_C(57456), // XOR8ri
646 UINT64_C(57424), // XOR8rm
647 UINT64_C(57440), // XOR8rn
648 UINT64_C(57456), // XOR8rp
649 UINT64_C(57408), // XOR8rr
650 UINT64_C(16448), // ZEXT16r
651 UINT64_C(0)
652 };
653 const unsigned opcode = MI.getOpcode();
654 uint64_t Value = InstBits[opcode];
655 uint64_t op = 0;
656 (void)op; // suppress warning
657 switch (opcode) {
658 case MSP430::ADDframe:
659 case MSP430::ADJCALLSTACKDOWN:
660 case MSP430::ADJCALLSTACKUP:
661 case MSP430::RET:
662 case MSP430::RETI:
663 case MSP430::Rrcl8:
664 case MSP430::Rrcl16:
665 case MSP430::Select8:
666 case MSP430::Select16:
667 case MSP430::Shl8:
668 case MSP430::Shl16:
669 case MSP430::Sra8:
670 case MSP430::Sra16:
671 case MSP430::Srl8:
672 case MSP430::Srl16: {
673 break;
674 }
675 case MSP430::JCC: {
676 // op: cond
677 op = getCCOpValue(MI, Op: 1, Fixups, STI);
678 op &= UINT64_C(7);
679 op <<= 10;
680 Value |= op;
681 // op: dst
682 op = getPCRelImmOpValue(MI, Op: 0, Fixups, STI);
683 op &= UINT64_C(1023);
684 Value |= op;
685 break;
686 }
687 case MSP430::JMP: {
688 // op: dst
689 op = getPCRelImmOpValue(MI, Op: 0, Fixups, STI);
690 op &= UINT64_C(1023);
691 Value |= op;
692 break;
693 }
694 case MSP430::PUSH16c: {
695 // op: imm
696 op = getCGImmOpValue(MI, Op: 0, Fixups, STI);
697 op &= UINT64_C(63);
698 Value |= op;
699 break;
700 }
701 case MSP430::BIT8rc:
702 case MSP430::BIT16rc:
703 case MSP430::CMP8rc:
704 case MSP430::CMP16rc:
705 case MSP430::MOV8rc:
706 case MSP430::MOV16rc: {
707 // op: imm
708 op = getCGImmOpValue(MI, Op: 1, Fixups, STI);
709 Value |= (op & UINT64_C(15)) << 8;
710 Value |= (op & UINT64_C(48));
711 // op: rd
712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
713 op &= UINT64_C(15);
714 Value |= op;
715 break;
716 }
717 case MSP430::ADD8mc:
718 case MSP430::ADD16mc:
719 case MSP430::ADDC8mc:
720 case MSP430::ADDC16mc:
721 case MSP430::AND8mc:
722 case MSP430::AND16mc:
723 case MSP430::BIC8mc:
724 case MSP430::BIC16mc:
725 case MSP430::BIS8mc:
726 case MSP430::BIS16mc:
727 case MSP430::BIT8mc:
728 case MSP430::BIT16mc:
729 case MSP430::CMP8mc:
730 case MSP430::CMP16mc:
731 case MSP430::DADD8mc:
732 case MSP430::DADD16mc:
733 case MSP430::MOV8mc:
734 case MSP430::MOV16mc:
735 case MSP430::SUB8mc:
736 case MSP430::SUB16mc:
737 case MSP430::SUBC8mc:
738 case MSP430::SUBC16mc:
739 case MSP430::XOR8mc:
740 case MSP430::XOR16mc: {
741 // op: imm
742 op = getCGImmOpValue(MI, Op: 2, Fixups, STI);
743 Value |= (op & UINT64_C(15)) << 8;
744 Value |= (op & UINT64_C(48));
745 // op: dst
746 op = getMemOpValue(MI, Op: 0, Fixups, STI);
747 Value |= (op & UINT64_C(1048560)) << 12;
748 Value |= (op & UINT64_C(15));
749 break;
750 }
751 case MSP430::ADD8rc:
752 case MSP430::ADD16rc:
753 case MSP430::ADDC8rc:
754 case MSP430::ADDC16rc:
755 case MSP430::AND8rc:
756 case MSP430::AND16rc:
757 case MSP430::BIC8rc:
758 case MSP430::BIC16rc:
759 case MSP430::BIS8rc:
760 case MSP430::BIS16rc:
761 case MSP430::DADD8rc:
762 case MSP430::DADD16rc:
763 case MSP430::SUB8rc:
764 case MSP430::SUB16rc:
765 case MSP430::SUBC8rc:
766 case MSP430::SUBC16rc:
767 case MSP430::XOR8rc:
768 case MSP430::XOR16rc: {
769 // op: imm
770 op = getCGImmOpValue(MI, Op: 2, Fixups, STI);
771 Value |= (op & UINT64_C(15)) << 8;
772 Value |= (op & UINT64_C(48));
773 // op: rd
774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
775 op &= UINT64_C(15);
776 Value |= op;
777 break;
778 }
779 case MSP430::Bi:
780 case MSP430::CALLi:
781 case MSP430::PUSH16i: {
782 // op: imm
783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
784 op &= UINT64_C(65535);
785 op <<= 16;
786 Value |= op;
787 break;
788 }
789 case MSP430::ADD8mi:
790 case MSP430::ADD16mi:
791 case MSP430::ADDC8mi:
792 case MSP430::ADDC16mi:
793 case MSP430::AND8mi:
794 case MSP430::AND16mi:
795 case MSP430::BIC8mi:
796 case MSP430::BIC16mi:
797 case MSP430::BIS8mi:
798 case MSP430::BIS16mi:
799 case MSP430::BIT8mi:
800 case MSP430::BIT16mi:
801 case MSP430::CMP8mi:
802 case MSP430::CMP16mi:
803 case MSP430::DADD8mi:
804 case MSP430::DADD16mi:
805 case MSP430::MOV8mi:
806 case MSP430::MOV16mi:
807 case MSP430::SUB8mi:
808 case MSP430::SUB16mi:
809 case MSP430::SUBC8mi:
810 case MSP430::SUBC16mi:
811 case MSP430::XOR8mi:
812 case MSP430::XOR16mi: {
813 // op: imm
814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
815 op &= UINT64_C(65535);
816 op <<= 16;
817 Value |= op;
818 // op: dst
819 op = getMemOpValue(MI, Op: 0, Fixups, STI);
820 Value |= (op & UINT64_C(1048560)) << 28;
821 Value |= (op & UINT64_C(15));
822 break;
823 }
824 case MSP430::POP16r: {
825 // op: rd
826 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
827 op &= UINT64_C(15);
828 Value |= op;
829 break;
830 }
831 case MSP430::BIT8ri:
832 case MSP430::BIT16ri:
833 case MSP430::CMP8ri:
834 case MSP430::CMP16ri:
835 case MSP430::MOV8ri:
836 case MSP430::MOV16ri: {
837 // op: rd
838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
839 op &= UINT64_C(15);
840 Value |= op;
841 // op: imm
842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
843 op &= UINT64_C(65535);
844 op <<= 16;
845 Value |= op;
846 break;
847 }
848 case MSP430::ADD8ri:
849 case MSP430::ADD16ri:
850 case MSP430::ADDC8ri:
851 case MSP430::ADDC16ri:
852 case MSP430::AND8ri:
853 case MSP430::AND16ri:
854 case MSP430::BIC8ri:
855 case MSP430::BIC16ri:
856 case MSP430::BIS8ri:
857 case MSP430::BIS16ri:
858 case MSP430::DADD8ri:
859 case MSP430::DADD16ri:
860 case MSP430::SUB8ri:
861 case MSP430::SUB16ri:
862 case MSP430::SUBC8ri:
863 case MSP430::SUBC16ri:
864 case MSP430::XOR8ri:
865 case MSP430::XOR16ri: {
866 // op: rd
867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
868 op &= UINT64_C(15);
869 Value |= op;
870 // op: imm
871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
872 op &= UINT64_C(65535);
873 op <<= 16;
874 Value |= op;
875 break;
876 }
877 case MSP430::BIT8rm:
878 case MSP430::BIT16rm:
879 case MSP430::CMP8rm:
880 case MSP430::CMP16rm:
881 case MSP430::MOV8rm:
882 case MSP430::MOV16rm:
883 case MSP430::MOVZX16rm8: {
884 // op: rd
885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
886 op &= UINT64_C(15);
887 Value |= op;
888 // op: src
889 op = getMemOpValue(MI, Op: 1, Fixups, STI);
890 Value |= (op & UINT64_C(1048560)) << 12;
891 Value |= (op & UINT64_C(15)) << 8;
892 break;
893 }
894 case MSP430::ADD8rm:
895 case MSP430::ADD16rm:
896 case MSP430::ADDC8rm:
897 case MSP430::ADDC16rm:
898 case MSP430::AND8rm:
899 case MSP430::AND16rm:
900 case MSP430::BIC8rm:
901 case MSP430::BIC16rm:
902 case MSP430::BIS8rm:
903 case MSP430::BIS16rm:
904 case MSP430::DADD8rm:
905 case MSP430::DADD16rm:
906 case MSP430::SUB8rm:
907 case MSP430::SUB16rm:
908 case MSP430::SUBC8rm:
909 case MSP430::SUBC16rm:
910 case MSP430::XOR8rm:
911 case MSP430::XOR16rm: {
912 // op: rd
913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
914 op &= UINT64_C(15);
915 Value |= op;
916 // op: src
917 op = getMemOpValue(MI, Op: 2, Fixups, STI);
918 Value |= (op & UINT64_C(1048560)) << 12;
919 Value |= (op & UINT64_C(15)) << 8;
920 break;
921 }
922 case MSP430::CALLn:
923 case MSP430::CALLp:
924 case MSP430::CALLr:
925 case MSP430::PUSH8r:
926 case MSP430::PUSH16r:
927 case MSP430::RRA8n:
928 case MSP430::RRA8p:
929 case MSP430::RRA16n:
930 case MSP430::RRA16p:
931 case MSP430::RRC8n:
932 case MSP430::RRC8p:
933 case MSP430::RRC16n:
934 case MSP430::RRC16p:
935 case MSP430::SEXT16n:
936 case MSP430::SEXT16p:
937 case MSP430::SWPB16n:
938 case MSP430::SWPB16p: {
939 // op: rs
940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
941 op &= UINT64_C(15);
942 Value |= op;
943 break;
944 }
945 case MSP430::Br: {
946 // op: rs
947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
948 op &= UINT64_C(15);
949 op <<= 8;
950 Value |= op;
951 break;
952 }
953 case MSP430::RRA8r:
954 case MSP430::RRA16r:
955 case MSP430::RRC8r:
956 case MSP430::RRC16r:
957 case MSP430::SEXT16r:
958 case MSP430::SWPB16r: {
959 // op: rs
960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
961 op &= UINT64_C(15);
962 Value |= op;
963 break;
964 }
965 case MSP430::BIT8rn:
966 case MSP430::BIT8rp:
967 case MSP430::BIT8rr:
968 case MSP430::BIT16rn:
969 case MSP430::BIT16rp:
970 case MSP430::BIT16rr:
971 case MSP430::CMP8rn:
972 case MSP430::CMP8rp:
973 case MSP430::CMP8rr:
974 case MSP430::CMP16rn:
975 case MSP430::CMP16rp:
976 case MSP430::CMP16rr:
977 case MSP430::MOV8rn:
978 case MSP430::MOV8rr:
979 case MSP430::MOV16rn:
980 case MSP430::MOV16rr:
981 case MSP430::MOVZX16rr8:
982 case MSP430::ZEXT16r: {
983 // op: rs
984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
985 op &= UINT64_C(15);
986 op <<= 8;
987 Value |= op;
988 // op: rd
989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
990 op &= UINT64_C(15);
991 Value |= op;
992 break;
993 }
994 case MSP430::ADD8mn:
995 case MSP430::ADD8mp:
996 case MSP430::ADD8mr:
997 case MSP430::ADD16mn:
998 case MSP430::ADD16mp:
999 case MSP430::ADD16mr:
1000 case MSP430::ADDC8mn:
1001 case MSP430::ADDC8mp:
1002 case MSP430::ADDC8mr:
1003 case MSP430::ADDC16mn:
1004 case MSP430::ADDC16mp:
1005 case MSP430::ADDC16mr:
1006 case MSP430::AND8mn:
1007 case MSP430::AND8mp:
1008 case MSP430::AND8mr:
1009 case MSP430::AND16mn:
1010 case MSP430::AND16mp:
1011 case MSP430::AND16mr:
1012 case MSP430::BIC8mn:
1013 case MSP430::BIC8mp:
1014 case MSP430::BIC8mr:
1015 case MSP430::BIC16mn:
1016 case MSP430::BIC16mp:
1017 case MSP430::BIC16mr:
1018 case MSP430::BIS8mn:
1019 case MSP430::BIS8mp:
1020 case MSP430::BIS8mr:
1021 case MSP430::BIS16mn:
1022 case MSP430::BIS16mp:
1023 case MSP430::BIS16mr:
1024 case MSP430::BIT8mn:
1025 case MSP430::BIT8mp:
1026 case MSP430::BIT8mr:
1027 case MSP430::BIT16mn:
1028 case MSP430::BIT16mp:
1029 case MSP430::BIT16mr:
1030 case MSP430::CMP8mn:
1031 case MSP430::CMP8mp:
1032 case MSP430::CMP8mr:
1033 case MSP430::CMP16mn:
1034 case MSP430::CMP16mp:
1035 case MSP430::CMP16mr:
1036 case MSP430::DADD8mn:
1037 case MSP430::DADD8mp:
1038 case MSP430::DADD8mr:
1039 case MSP430::DADD16mn:
1040 case MSP430::DADD16mp:
1041 case MSP430::DADD16mr:
1042 case MSP430::MOV8mn:
1043 case MSP430::MOV8mr:
1044 case MSP430::MOV16mn:
1045 case MSP430::MOV16mr:
1046 case MSP430::SUB8mn:
1047 case MSP430::SUB8mp:
1048 case MSP430::SUB8mr:
1049 case MSP430::SUB16mn:
1050 case MSP430::SUB16mp:
1051 case MSP430::SUB16mr:
1052 case MSP430::SUBC8mn:
1053 case MSP430::SUBC8mp:
1054 case MSP430::SUBC8mr:
1055 case MSP430::SUBC16mn:
1056 case MSP430::SUBC16mp:
1057 case MSP430::SUBC16mr:
1058 case MSP430::XOR8mn:
1059 case MSP430::XOR8mp:
1060 case MSP430::XOR8mr:
1061 case MSP430::XOR16mn:
1062 case MSP430::XOR16mp:
1063 case MSP430::XOR16mr: {
1064 // op: rs
1065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1066 op &= UINT64_C(15);
1067 op <<= 8;
1068 Value |= op;
1069 // op: dst
1070 op = getMemOpValue(MI, Op: 0, Fixups, STI);
1071 Value |= (op & UINT64_C(1048560)) << 12;
1072 Value |= (op & UINT64_C(15));
1073 break;
1074 }
1075 case MSP430::ADD8rn:
1076 case MSP430::ADD8rr:
1077 case MSP430::ADD16rn:
1078 case MSP430::ADD16rr:
1079 case MSP430::ADDC8rn:
1080 case MSP430::ADDC8rr:
1081 case MSP430::ADDC16rn:
1082 case MSP430::ADDC16rr:
1083 case MSP430::AND8rn:
1084 case MSP430::AND8rr:
1085 case MSP430::AND16rn:
1086 case MSP430::AND16rr:
1087 case MSP430::BIC8rn:
1088 case MSP430::BIC8rr:
1089 case MSP430::BIC16rn:
1090 case MSP430::BIC16rr:
1091 case MSP430::BIS8rn:
1092 case MSP430::BIS8rr:
1093 case MSP430::BIS16rn:
1094 case MSP430::BIS16rr:
1095 case MSP430::DADD8rn:
1096 case MSP430::DADD8rr:
1097 case MSP430::DADD16rn:
1098 case MSP430::DADD16rr:
1099 case MSP430::MOV8rp:
1100 case MSP430::MOV16rp:
1101 case MSP430::SUB8rn:
1102 case MSP430::SUB8rr:
1103 case MSP430::SUB16rn:
1104 case MSP430::SUB16rr:
1105 case MSP430::SUBC8rn:
1106 case MSP430::SUBC8rr:
1107 case MSP430::SUBC16rn:
1108 case MSP430::SUBC16rr:
1109 case MSP430::XOR8rn:
1110 case MSP430::XOR8rr:
1111 case MSP430::XOR16rn:
1112 case MSP430::XOR16rr: {
1113 // op: rs
1114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1115 op &= UINT64_C(15);
1116 op <<= 8;
1117 Value |= op;
1118 // op: rd
1119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1120 op &= UINT64_C(15);
1121 Value |= op;
1122 break;
1123 }
1124 case MSP430::ADD8rp:
1125 case MSP430::ADD16rp:
1126 case MSP430::ADDC8rp:
1127 case MSP430::ADDC16rp:
1128 case MSP430::AND8rp:
1129 case MSP430::AND16rp:
1130 case MSP430::BIC8rp:
1131 case MSP430::BIC16rp:
1132 case MSP430::BIS8rp:
1133 case MSP430::BIS16rp:
1134 case MSP430::DADD8rp:
1135 case MSP430::DADD16rp:
1136 case MSP430::SUB8rp:
1137 case MSP430::SUB16rp:
1138 case MSP430::SUBC8rp:
1139 case MSP430::SUBC16rp:
1140 case MSP430::XOR8rp:
1141 case MSP430::XOR16rp: {
1142 // op: rs
1143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1144 op &= UINT64_C(15);
1145 op <<= 8;
1146 Value |= op;
1147 // op: rd
1148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1149 op &= UINT64_C(15);
1150 Value |= op;
1151 break;
1152 }
1153 case MSP430::Bm: {
1154 // op: src
1155 op = getMemOpValue(MI, Op: 0, Fixups, STI);
1156 Value |= (op & UINT64_C(1048560)) << 12;
1157 Value |= (op & UINT64_C(15)) << 8;
1158 break;
1159 }
1160 case MSP430::CALLm:
1161 case MSP430::RRA8m:
1162 case MSP430::RRA16m:
1163 case MSP430::RRC8m:
1164 case MSP430::RRC16m:
1165 case MSP430::SEXT16m:
1166 case MSP430::SWPB16m: {
1167 // op: src
1168 op = getMemOpValue(MI, Op: 0, Fixups, STI);
1169 Value |= (op & UINT64_C(1048560)) << 12;
1170 Value |= (op & UINT64_C(15));
1171 break;
1172 }
1173 case MSP430::ADD8mm:
1174 case MSP430::ADD16mm:
1175 case MSP430::ADDC8mm:
1176 case MSP430::ADDC16mm:
1177 case MSP430::AND8mm:
1178 case MSP430::AND16mm:
1179 case MSP430::BIC8mm:
1180 case MSP430::BIC16mm:
1181 case MSP430::BIS8mm:
1182 case MSP430::BIS16mm:
1183 case MSP430::BIT8mm:
1184 case MSP430::BIT16mm:
1185 case MSP430::CMP8mm:
1186 case MSP430::CMP16mm:
1187 case MSP430::DADD8mm:
1188 case MSP430::DADD16mm:
1189 case MSP430::MOV8mm:
1190 case MSP430::MOV16mm:
1191 case MSP430::SUB8mm:
1192 case MSP430::SUB16mm:
1193 case MSP430::SUBC8mm:
1194 case MSP430::SUBC16mm:
1195 case MSP430::XOR8mm:
1196 case MSP430::XOR16mm: {
1197 // op: src
1198 op = getMemOpValue(MI, Op: 2, Fixups, STI);
1199 Value |= (op & UINT64_C(1048560)) << 12;
1200 Value |= (op & UINT64_C(15)) << 8;
1201 // op: dst
1202 op = getMemOpValue(MI, Op: 0, Fixups, STI);
1203 Value |= (op & UINT64_C(1048560)) << 28;
1204 Value |= (op & UINT64_C(15));
1205 break;
1206 }
1207 default:
1208 std::string msg;
1209 raw_string_ostream Msg(msg);
1210 Msg << "Not supported instr: " << MI;
1211 report_fatal_error(reason: Msg.str().c_str());
1212 }
1213 return Value;
1214}
1215
1216#ifdef GET_OPERAND_BIT_OFFSET
1217#undef GET_OPERAND_BIT_OFFSET
1218
1219uint32_t MSP430MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
1220 unsigned OpNum,
1221 const MCSubtargetInfo &STI) const {
1222 switch (MI.getOpcode()) {
1223 case MSP430::ADDframe:
1224 case MSP430::ADJCALLSTACKDOWN:
1225 case MSP430::ADJCALLSTACKUP:
1226 case MSP430::RET:
1227 case MSP430::RETI:
1228 case MSP430::Rrcl8:
1229 case MSP430::Rrcl16:
1230 case MSP430::Select8:
1231 case MSP430::Select16:
1232 case MSP430::Shl8:
1233 case MSP430::Shl16:
1234 case MSP430::Sra8:
1235 case MSP430::Sra16:
1236 case MSP430::Srl8:
1237 case MSP430::Srl16: {
1238 break;
1239 }
1240 case MSP430::JMP: {
1241 switch (OpNum) {
1242 case 0:
1243 // op: dst
1244 return 0;
1245 }
1246 break;
1247 }
1248 case MSP430::PUSH16c: {
1249 switch (OpNum) {
1250 case 0:
1251 // op: imm
1252 return 0;
1253 }
1254 break;
1255 }
1256 case MSP430::Bi:
1257 case MSP430::CALLi:
1258 case MSP430::PUSH16i: {
1259 switch (OpNum) {
1260 case 0:
1261 // op: imm
1262 return 16;
1263 }
1264 break;
1265 }
1266 case MSP430::BIT8ri:
1267 case MSP430::BIT16ri:
1268 case MSP430::CMP8ri:
1269 case MSP430::CMP16ri:
1270 case MSP430::MOV8ri:
1271 case MSP430::MOV16ri: {
1272 switch (OpNum) {
1273 case 0:
1274 // op: rd
1275 return 0;
1276 case 1:
1277 // op: imm
1278 return 16;
1279 }
1280 break;
1281 }
1282 case MSP430::BIT8rm:
1283 case MSP430::BIT16rm:
1284 case MSP430::CMP8rm:
1285 case MSP430::CMP16rm:
1286 case MSP430::MOV8rm:
1287 case MSP430::MOV16rm:
1288 case MSP430::MOVZX16rm8: {
1289 switch (OpNum) {
1290 case 0:
1291 // op: rd
1292 return 0;
1293 case 1:
1294 // op: src
1295 return 8;
1296 }
1297 break;
1298 }
1299 case MSP430::ADD8ri:
1300 case MSP430::ADD16ri:
1301 case MSP430::ADDC8ri:
1302 case MSP430::ADDC16ri:
1303 case MSP430::AND8ri:
1304 case MSP430::AND16ri:
1305 case MSP430::BIC8ri:
1306 case MSP430::BIC16ri:
1307 case MSP430::BIS8ri:
1308 case MSP430::BIS16ri:
1309 case MSP430::DADD8ri:
1310 case MSP430::DADD16ri:
1311 case MSP430::SUB8ri:
1312 case MSP430::SUB16ri:
1313 case MSP430::SUBC8ri:
1314 case MSP430::SUBC16ri:
1315 case MSP430::XOR8ri:
1316 case MSP430::XOR16ri: {
1317 switch (OpNum) {
1318 case 0:
1319 // op: rd
1320 return 0;
1321 case 2:
1322 // op: imm
1323 return 16;
1324 }
1325 break;
1326 }
1327 case MSP430::ADD8rm:
1328 case MSP430::ADD16rm:
1329 case MSP430::ADDC8rm:
1330 case MSP430::ADDC16rm:
1331 case MSP430::AND8rm:
1332 case MSP430::AND16rm:
1333 case MSP430::BIC8rm:
1334 case MSP430::BIC16rm:
1335 case MSP430::BIS8rm:
1336 case MSP430::BIS16rm:
1337 case MSP430::DADD8rm:
1338 case MSP430::DADD16rm:
1339 case MSP430::SUB8rm:
1340 case MSP430::SUB16rm:
1341 case MSP430::SUBC8rm:
1342 case MSP430::SUBC16rm:
1343 case MSP430::XOR8rm:
1344 case MSP430::XOR16rm: {
1345 switch (OpNum) {
1346 case 0:
1347 // op: rd
1348 return 0;
1349 case 2:
1350 // op: src
1351 return 8;
1352 }
1353 break;
1354 }
1355 case MSP430::POP16r: {
1356 switch (OpNum) {
1357 case 0:
1358 // op: rd
1359 return 0;
1360 }
1361 break;
1362 }
1363 case MSP430::CALLn:
1364 case MSP430::CALLp:
1365 case MSP430::CALLr:
1366 case MSP430::PUSH8r:
1367 case MSP430::PUSH16r:
1368 case MSP430::RRA8n:
1369 case MSP430::RRA8p:
1370 case MSP430::RRA16n:
1371 case MSP430::RRA16p:
1372 case MSP430::RRC8n:
1373 case MSP430::RRC8p:
1374 case MSP430::RRC16n:
1375 case MSP430::RRC16p:
1376 case MSP430::SEXT16n:
1377 case MSP430::SEXT16p:
1378 case MSP430::SWPB16n:
1379 case MSP430::SWPB16p: {
1380 switch (OpNum) {
1381 case 0:
1382 // op: rs
1383 return 0;
1384 }
1385 break;
1386 }
1387 case MSP430::Br: {
1388 switch (OpNum) {
1389 case 0:
1390 // op: rs
1391 return 8;
1392 }
1393 break;
1394 }
1395 case MSP430::CALLm:
1396 case MSP430::RRA8m:
1397 case MSP430::RRA16m:
1398 case MSP430::RRC8m:
1399 case MSP430::RRC16m:
1400 case MSP430::SEXT16m:
1401 case MSP430::SWPB16m: {
1402 switch (OpNum) {
1403 case 0:
1404 // op: src
1405 return 0;
1406 }
1407 break;
1408 }
1409 case MSP430::Bm: {
1410 switch (OpNum) {
1411 case 0:
1412 // op: src
1413 return 8;
1414 }
1415 break;
1416 }
1417 case MSP430::JCC: {
1418 switch (OpNum) {
1419 case 1:
1420 // op: cond
1421 return 10;
1422 case 0:
1423 // op: dst
1424 return 0;
1425 }
1426 break;
1427 }
1428 case MSP430::BIT8rc:
1429 case MSP430::BIT16rc:
1430 case MSP430::CMP8rc:
1431 case MSP430::CMP16rc:
1432 case MSP430::MOV8rc:
1433 case MSP430::MOV16rc: {
1434 switch (OpNum) {
1435 case 1:
1436 // op: imm
1437 return 4;
1438 case 0:
1439 // op: rd
1440 return 0;
1441 }
1442 break;
1443 }
1444 case MSP430::RRA8r:
1445 case MSP430::RRA16r:
1446 case MSP430::RRC8r:
1447 case MSP430::RRC16r:
1448 case MSP430::SEXT16r:
1449 case MSP430::SWPB16r: {
1450 switch (OpNum) {
1451 case 1:
1452 // op: rs
1453 return 0;
1454 }
1455 break;
1456 }
1457 case MSP430::BIT8rn:
1458 case MSP430::BIT8rp:
1459 case MSP430::BIT8rr:
1460 case MSP430::BIT16rn:
1461 case MSP430::BIT16rp:
1462 case MSP430::BIT16rr:
1463 case MSP430::CMP8rn:
1464 case MSP430::CMP8rp:
1465 case MSP430::CMP8rr:
1466 case MSP430::CMP16rn:
1467 case MSP430::CMP16rp:
1468 case MSP430::CMP16rr:
1469 case MSP430::MOV8rn:
1470 case MSP430::MOV8rr:
1471 case MSP430::MOV16rn:
1472 case MSP430::MOV16rr:
1473 case MSP430::MOVZX16rr8:
1474 case MSP430::ZEXT16r: {
1475 switch (OpNum) {
1476 case 1:
1477 // op: rs
1478 return 8;
1479 case 0:
1480 // op: rd
1481 return 0;
1482 }
1483 break;
1484 }
1485 case MSP430::ADD8mi:
1486 case MSP430::ADD16mi:
1487 case MSP430::ADDC8mi:
1488 case MSP430::ADDC16mi:
1489 case MSP430::AND8mi:
1490 case MSP430::AND16mi:
1491 case MSP430::BIC8mi:
1492 case MSP430::BIC16mi:
1493 case MSP430::BIS8mi:
1494 case MSP430::BIS16mi:
1495 case MSP430::BIT8mi:
1496 case MSP430::BIT16mi:
1497 case MSP430::CMP8mi:
1498 case MSP430::CMP16mi:
1499 case MSP430::DADD8mi:
1500 case MSP430::DADD16mi:
1501 case MSP430::MOV8mi:
1502 case MSP430::MOV16mi:
1503 case MSP430::SUB8mi:
1504 case MSP430::SUB16mi:
1505 case MSP430::SUBC8mi:
1506 case MSP430::SUBC16mi:
1507 case MSP430::XOR8mi:
1508 case MSP430::XOR16mi: {
1509 switch (OpNum) {
1510 case 2:
1511 // op: imm
1512 return 16;
1513 case 0:
1514 // op: dst
1515 return 0;
1516 }
1517 break;
1518 }
1519 case MSP430::ADD8mc:
1520 case MSP430::ADD16mc:
1521 case MSP430::ADDC8mc:
1522 case MSP430::ADDC16mc:
1523 case MSP430::AND8mc:
1524 case MSP430::AND16mc:
1525 case MSP430::BIC8mc:
1526 case MSP430::BIC16mc:
1527 case MSP430::BIS8mc:
1528 case MSP430::BIS16mc:
1529 case MSP430::BIT8mc:
1530 case MSP430::BIT16mc:
1531 case MSP430::CMP8mc:
1532 case MSP430::CMP16mc:
1533 case MSP430::DADD8mc:
1534 case MSP430::DADD16mc:
1535 case MSP430::MOV8mc:
1536 case MSP430::MOV16mc:
1537 case MSP430::SUB8mc:
1538 case MSP430::SUB16mc:
1539 case MSP430::SUBC8mc:
1540 case MSP430::SUBC16mc:
1541 case MSP430::XOR8mc:
1542 case MSP430::XOR16mc: {
1543 switch (OpNum) {
1544 case 2:
1545 // op: imm
1546 return 4;
1547 case 0:
1548 // op: dst
1549 return 0;
1550 }
1551 break;
1552 }
1553 case MSP430::ADD8rc:
1554 case MSP430::ADD16rc:
1555 case MSP430::ADDC8rc:
1556 case MSP430::ADDC16rc:
1557 case MSP430::AND8rc:
1558 case MSP430::AND16rc:
1559 case MSP430::BIC8rc:
1560 case MSP430::BIC16rc:
1561 case MSP430::BIS8rc:
1562 case MSP430::BIS16rc:
1563 case MSP430::DADD8rc:
1564 case MSP430::DADD16rc:
1565 case MSP430::SUB8rc:
1566 case MSP430::SUB16rc:
1567 case MSP430::SUBC8rc:
1568 case MSP430::SUBC16rc:
1569 case MSP430::XOR8rc:
1570 case MSP430::XOR16rc: {
1571 switch (OpNum) {
1572 case 2:
1573 // op: imm
1574 return 4;
1575 case 0:
1576 // op: rd
1577 return 0;
1578 }
1579 break;
1580 }
1581 case MSP430::ADD8mn:
1582 case MSP430::ADD8mp:
1583 case MSP430::ADD8mr:
1584 case MSP430::ADD16mn:
1585 case MSP430::ADD16mp:
1586 case MSP430::ADD16mr:
1587 case MSP430::ADDC8mn:
1588 case MSP430::ADDC8mp:
1589 case MSP430::ADDC8mr:
1590 case MSP430::ADDC16mn:
1591 case MSP430::ADDC16mp:
1592 case MSP430::ADDC16mr:
1593 case MSP430::AND8mn:
1594 case MSP430::AND8mp:
1595 case MSP430::AND8mr:
1596 case MSP430::AND16mn:
1597 case MSP430::AND16mp:
1598 case MSP430::AND16mr:
1599 case MSP430::BIC8mn:
1600 case MSP430::BIC8mp:
1601 case MSP430::BIC8mr:
1602 case MSP430::BIC16mn:
1603 case MSP430::BIC16mp:
1604 case MSP430::BIC16mr:
1605 case MSP430::BIS8mn:
1606 case MSP430::BIS8mp:
1607 case MSP430::BIS8mr:
1608 case MSP430::BIS16mn:
1609 case MSP430::BIS16mp:
1610 case MSP430::BIS16mr:
1611 case MSP430::BIT8mn:
1612 case MSP430::BIT8mp:
1613 case MSP430::BIT8mr:
1614 case MSP430::BIT16mn:
1615 case MSP430::BIT16mp:
1616 case MSP430::BIT16mr:
1617 case MSP430::CMP8mn:
1618 case MSP430::CMP8mp:
1619 case MSP430::CMP8mr:
1620 case MSP430::CMP16mn:
1621 case MSP430::CMP16mp:
1622 case MSP430::CMP16mr:
1623 case MSP430::DADD8mn:
1624 case MSP430::DADD8mp:
1625 case MSP430::DADD8mr:
1626 case MSP430::DADD16mn:
1627 case MSP430::DADD16mp:
1628 case MSP430::DADD16mr:
1629 case MSP430::MOV8mn:
1630 case MSP430::MOV8mr:
1631 case MSP430::MOV16mn:
1632 case MSP430::MOV16mr:
1633 case MSP430::SUB8mn:
1634 case MSP430::SUB8mp:
1635 case MSP430::SUB8mr:
1636 case MSP430::SUB16mn:
1637 case MSP430::SUB16mp:
1638 case MSP430::SUB16mr:
1639 case MSP430::SUBC8mn:
1640 case MSP430::SUBC8mp:
1641 case MSP430::SUBC8mr:
1642 case MSP430::SUBC16mn:
1643 case MSP430::SUBC16mp:
1644 case MSP430::SUBC16mr:
1645 case MSP430::XOR8mn:
1646 case MSP430::XOR8mp:
1647 case MSP430::XOR8mr:
1648 case MSP430::XOR16mn:
1649 case MSP430::XOR16mp:
1650 case MSP430::XOR16mr: {
1651 switch (OpNum) {
1652 case 2:
1653 // op: rs
1654 return 8;
1655 case 0:
1656 // op: dst
1657 return 0;
1658 }
1659 break;
1660 }
1661 case MSP430::ADD8rn:
1662 case MSP430::ADD8rr:
1663 case MSP430::ADD16rn:
1664 case MSP430::ADD16rr:
1665 case MSP430::ADDC8rn:
1666 case MSP430::ADDC8rr:
1667 case MSP430::ADDC16rn:
1668 case MSP430::ADDC16rr:
1669 case MSP430::AND8rn:
1670 case MSP430::AND8rr:
1671 case MSP430::AND16rn:
1672 case MSP430::AND16rr:
1673 case MSP430::BIC8rn:
1674 case MSP430::BIC8rr:
1675 case MSP430::BIC16rn:
1676 case MSP430::BIC16rr:
1677 case MSP430::BIS8rn:
1678 case MSP430::BIS8rr:
1679 case MSP430::BIS16rn:
1680 case MSP430::BIS16rr:
1681 case MSP430::DADD8rn:
1682 case MSP430::DADD8rr:
1683 case MSP430::DADD16rn:
1684 case MSP430::DADD16rr:
1685 case MSP430::MOV8rp:
1686 case MSP430::MOV16rp:
1687 case MSP430::SUB8rn:
1688 case MSP430::SUB8rr:
1689 case MSP430::SUB16rn:
1690 case MSP430::SUB16rr:
1691 case MSP430::SUBC8rn:
1692 case MSP430::SUBC8rr:
1693 case MSP430::SUBC16rn:
1694 case MSP430::SUBC16rr:
1695 case MSP430::XOR8rn:
1696 case MSP430::XOR8rr:
1697 case MSP430::XOR16rn:
1698 case MSP430::XOR16rr: {
1699 switch (OpNum) {
1700 case 2:
1701 // op: rs
1702 return 8;
1703 case 0:
1704 // op: rd
1705 return 0;
1706 }
1707 break;
1708 }
1709 case MSP430::ADD8mm:
1710 case MSP430::ADD16mm:
1711 case MSP430::ADDC8mm:
1712 case MSP430::ADDC16mm:
1713 case MSP430::AND8mm:
1714 case MSP430::AND16mm:
1715 case MSP430::BIC8mm:
1716 case MSP430::BIC16mm:
1717 case MSP430::BIS8mm:
1718 case MSP430::BIS16mm:
1719 case MSP430::BIT8mm:
1720 case MSP430::BIT16mm:
1721 case MSP430::CMP8mm:
1722 case MSP430::CMP16mm:
1723 case MSP430::DADD8mm:
1724 case MSP430::DADD16mm:
1725 case MSP430::MOV8mm:
1726 case MSP430::MOV16mm:
1727 case MSP430::SUB8mm:
1728 case MSP430::SUB16mm:
1729 case MSP430::SUBC8mm:
1730 case MSP430::SUBC16mm:
1731 case MSP430::XOR8mm:
1732 case MSP430::XOR16mm: {
1733 switch (OpNum) {
1734 case 2:
1735 // op: src
1736 return 8;
1737 case 0:
1738 // op: dst
1739 return 0;
1740 }
1741 break;
1742 }
1743 case MSP430::ADD8rp:
1744 case MSP430::ADD16rp:
1745 case MSP430::ADDC8rp:
1746 case MSP430::ADDC16rp:
1747 case MSP430::AND8rp:
1748 case MSP430::AND16rp:
1749 case MSP430::BIC8rp:
1750 case MSP430::BIC16rp:
1751 case MSP430::BIS8rp:
1752 case MSP430::BIS16rp:
1753 case MSP430::DADD8rp:
1754 case MSP430::DADD16rp:
1755 case MSP430::SUB8rp:
1756 case MSP430::SUB16rp:
1757 case MSP430::SUBC8rp:
1758 case MSP430::SUBC16rp:
1759 case MSP430::XOR8rp:
1760 case MSP430::XOR16rp: {
1761 switch (OpNum) {
1762 case 3:
1763 // op: rs
1764 return 8;
1765 case 0:
1766 // op: rd
1767 return 0;
1768 }
1769 break;
1770 }
1771 }
1772 std::string msg;
1773 raw_string_ostream Msg(msg);
1774 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
1775 report_fatal_error(Msg.str().c_str());
1776}
1777
1778#endif // GET_OPERAND_BIT_OFFSET
1779
1780