1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace Mips {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ABSMacro = 295,
311 ADJCALLSTACKDOWN = 296,
312 ADJCALLSTACKUP = 297,
313 AND_V_D_PSEUDO = 298,
314 AND_V_H_PSEUDO = 299,
315 AND_V_W_PSEUDO = 300,
316 ATOMIC_CMP_SWAP_I16 = 301,
317 ATOMIC_CMP_SWAP_I16_POSTRA = 302,
318 ATOMIC_CMP_SWAP_I32 = 303,
319 ATOMIC_CMP_SWAP_I32_POSTRA = 304,
320 ATOMIC_CMP_SWAP_I64 = 305,
321 ATOMIC_CMP_SWAP_I64_POSTRA = 306,
322 ATOMIC_CMP_SWAP_I8 = 307,
323 ATOMIC_CMP_SWAP_I8_POSTRA = 308,
324 ATOMIC_LOAD_ADD_I16 = 309,
325 ATOMIC_LOAD_ADD_I16_POSTRA = 310,
326 ATOMIC_LOAD_ADD_I32 = 311,
327 ATOMIC_LOAD_ADD_I32_POSTRA = 312,
328 ATOMIC_LOAD_ADD_I64 = 313,
329 ATOMIC_LOAD_ADD_I64_POSTRA = 314,
330 ATOMIC_LOAD_ADD_I8 = 315,
331 ATOMIC_LOAD_ADD_I8_POSTRA = 316,
332 ATOMIC_LOAD_AND_I16 = 317,
333 ATOMIC_LOAD_AND_I16_POSTRA = 318,
334 ATOMIC_LOAD_AND_I32 = 319,
335 ATOMIC_LOAD_AND_I32_POSTRA = 320,
336 ATOMIC_LOAD_AND_I64 = 321,
337 ATOMIC_LOAD_AND_I64_POSTRA = 322,
338 ATOMIC_LOAD_AND_I8 = 323,
339 ATOMIC_LOAD_AND_I8_POSTRA = 324,
340 ATOMIC_LOAD_MAX_I16 = 325,
341 ATOMIC_LOAD_MAX_I16_POSTRA = 326,
342 ATOMIC_LOAD_MAX_I32 = 327,
343 ATOMIC_LOAD_MAX_I32_POSTRA = 328,
344 ATOMIC_LOAD_MAX_I64 = 329,
345 ATOMIC_LOAD_MAX_I64_POSTRA = 330,
346 ATOMIC_LOAD_MAX_I8 = 331,
347 ATOMIC_LOAD_MAX_I8_POSTRA = 332,
348 ATOMIC_LOAD_MIN_I16 = 333,
349 ATOMIC_LOAD_MIN_I16_POSTRA = 334,
350 ATOMIC_LOAD_MIN_I32 = 335,
351 ATOMIC_LOAD_MIN_I32_POSTRA = 336,
352 ATOMIC_LOAD_MIN_I64 = 337,
353 ATOMIC_LOAD_MIN_I64_POSTRA = 338,
354 ATOMIC_LOAD_MIN_I8 = 339,
355 ATOMIC_LOAD_MIN_I8_POSTRA = 340,
356 ATOMIC_LOAD_NAND_I16 = 341,
357 ATOMIC_LOAD_NAND_I16_POSTRA = 342,
358 ATOMIC_LOAD_NAND_I32 = 343,
359 ATOMIC_LOAD_NAND_I32_POSTRA = 344,
360 ATOMIC_LOAD_NAND_I64 = 345,
361 ATOMIC_LOAD_NAND_I64_POSTRA = 346,
362 ATOMIC_LOAD_NAND_I8 = 347,
363 ATOMIC_LOAD_NAND_I8_POSTRA = 348,
364 ATOMIC_LOAD_OR_I16 = 349,
365 ATOMIC_LOAD_OR_I16_POSTRA = 350,
366 ATOMIC_LOAD_OR_I32 = 351,
367 ATOMIC_LOAD_OR_I32_POSTRA = 352,
368 ATOMIC_LOAD_OR_I64 = 353,
369 ATOMIC_LOAD_OR_I64_POSTRA = 354,
370 ATOMIC_LOAD_OR_I8 = 355,
371 ATOMIC_LOAD_OR_I8_POSTRA = 356,
372 ATOMIC_LOAD_SUB_I16 = 357,
373 ATOMIC_LOAD_SUB_I16_POSTRA = 358,
374 ATOMIC_LOAD_SUB_I32 = 359,
375 ATOMIC_LOAD_SUB_I32_POSTRA = 360,
376 ATOMIC_LOAD_SUB_I64 = 361,
377 ATOMIC_LOAD_SUB_I64_POSTRA = 362,
378 ATOMIC_LOAD_SUB_I8 = 363,
379 ATOMIC_LOAD_SUB_I8_POSTRA = 364,
380 ATOMIC_LOAD_UMAX_I16 = 365,
381 ATOMIC_LOAD_UMAX_I16_POSTRA = 366,
382 ATOMIC_LOAD_UMAX_I32 = 367,
383 ATOMIC_LOAD_UMAX_I32_POSTRA = 368,
384 ATOMIC_LOAD_UMAX_I64 = 369,
385 ATOMIC_LOAD_UMAX_I64_POSTRA = 370,
386 ATOMIC_LOAD_UMAX_I8 = 371,
387 ATOMIC_LOAD_UMAX_I8_POSTRA = 372,
388 ATOMIC_LOAD_UMIN_I16 = 373,
389 ATOMIC_LOAD_UMIN_I16_POSTRA = 374,
390 ATOMIC_LOAD_UMIN_I32 = 375,
391 ATOMIC_LOAD_UMIN_I32_POSTRA = 376,
392 ATOMIC_LOAD_UMIN_I64 = 377,
393 ATOMIC_LOAD_UMIN_I64_POSTRA = 378,
394 ATOMIC_LOAD_UMIN_I8 = 379,
395 ATOMIC_LOAD_UMIN_I8_POSTRA = 380,
396 ATOMIC_LOAD_XOR_I16 = 381,
397 ATOMIC_LOAD_XOR_I16_POSTRA = 382,
398 ATOMIC_LOAD_XOR_I32 = 383,
399 ATOMIC_LOAD_XOR_I32_POSTRA = 384,
400 ATOMIC_LOAD_XOR_I64 = 385,
401 ATOMIC_LOAD_XOR_I64_POSTRA = 386,
402 ATOMIC_LOAD_XOR_I8 = 387,
403 ATOMIC_LOAD_XOR_I8_POSTRA = 388,
404 ATOMIC_SWAP_I16 = 389,
405 ATOMIC_SWAP_I16_POSTRA = 390,
406 ATOMIC_SWAP_I32 = 391,
407 ATOMIC_SWAP_I32_POSTRA = 392,
408 ATOMIC_SWAP_I64 = 393,
409 ATOMIC_SWAP_I64_POSTRA = 394,
410 ATOMIC_SWAP_I8 = 395,
411 ATOMIC_SWAP_I8_POSTRA = 396,
412 B = 397,
413 BAL_BR = 398,
414 BAL_BR_MM = 399,
415 BEQLImmMacro = 400,
416 BGE = 401,
417 BGEImmMacro = 402,
418 BGEL = 403,
419 BGELImmMacro = 404,
420 BGEU = 405,
421 BGEUImmMacro = 406,
422 BGEUL = 407,
423 BGEULImmMacro = 408,
424 BGT = 409,
425 BGTImmMacro = 410,
426 BGTL = 411,
427 BGTLImmMacro = 412,
428 BGTU = 413,
429 BGTUImmMacro = 414,
430 BGTUL = 415,
431 BGTULImmMacro = 416,
432 BLE = 417,
433 BLEImmMacro = 418,
434 BLEL = 419,
435 BLELImmMacro = 420,
436 BLEU = 421,
437 BLEUImmMacro = 422,
438 BLEUL = 423,
439 BLEULImmMacro = 424,
440 BLT = 425,
441 BLTImmMacro = 426,
442 BLTL = 427,
443 BLTLImmMacro = 428,
444 BLTU = 429,
445 BLTUImmMacro = 430,
446 BLTUL = 431,
447 BLTULImmMacro = 432,
448 BNELImmMacro = 433,
449 BPOSGE32_PSEUDO = 434,
450 BSEL_D_PSEUDO = 435,
451 BSEL_FD_PSEUDO = 436,
452 BSEL_FW_PSEUDO = 437,
453 BSEL_H_PSEUDO = 438,
454 BSEL_W_PSEUDO = 439,
455 B_MM = 440,
456 B_MMR6_Pseudo = 441,
457 B_MM_Pseudo = 442,
458 BeqImm = 443,
459 BneImm = 444,
460 BteqzT8CmpX16 = 445,
461 BteqzT8CmpiX16 = 446,
462 BteqzT8SltX16 = 447,
463 BteqzT8SltiX16 = 448,
464 BteqzT8SltiuX16 = 449,
465 BteqzT8SltuX16 = 450,
466 BtnezT8CmpX16 = 451,
467 BtnezT8CmpiX16 = 452,
468 BtnezT8SltX16 = 453,
469 BtnezT8SltiX16 = 454,
470 BtnezT8SltiuX16 = 455,
471 BtnezT8SltuX16 = 456,
472 BuildPairF64 = 457,
473 BuildPairF64_64 = 458,
474 CFTC1 = 459,
475 CONSTPOOL_ENTRY = 460,
476 COPY_FD_PSEUDO = 461,
477 COPY_FW_PSEUDO = 462,
478 CTTC1 = 463,
479 Constant32 = 464,
480 DMULImmMacro = 465,
481 DMULMacro = 466,
482 DMULOMacro = 467,
483 DMULOUMacro = 468,
484 DROL = 469,
485 DROLImm = 470,
486 DROR = 471,
487 DRORImm = 472,
488 DSDivIMacro = 473,
489 DSDivMacro = 474,
490 DSRemIMacro = 475,
491 DSRemMacro = 476,
492 DUDivIMacro = 477,
493 DUDivMacro = 478,
494 DURemIMacro = 479,
495 DURemMacro = 480,
496 ERet = 481,
497 ExtractElementF64 = 482,
498 ExtractElementF64_64 = 483,
499 FABS_D = 484,
500 FABS_W = 485,
501 FEXP2_D_1_PSEUDO = 486,
502 FEXP2_W_1_PSEUDO = 487,
503 FILL_FD_PSEUDO = 488,
504 FILL_FW_PSEUDO = 489,
505 GotPrologue16 = 490,
506 INSERT_B_VIDX64_PSEUDO = 491,
507 INSERT_B_VIDX_PSEUDO = 492,
508 INSERT_D_VIDX64_PSEUDO = 493,
509 INSERT_D_VIDX_PSEUDO = 494,
510 INSERT_FD_PSEUDO = 495,
511 INSERT_FD_VIDX64_PSEUDO = 496,
512 INSERT_FD_VIDX_PSEUDO = 497,
513 INSERT_FW_PSEUDO = 498,
514 INSERT_FW_VIDX64_PSEUDO = 499,
515 INSERT_FW_VIDX_PSEUDO = 500,
516 INSERT_H_VIDX64_PSEUDO = 501,
517 INSERT_H_VIDX_PSEUDO = 502,
518 INSERT_W_VIDX64_PSEUDO = 503,
519 INSERT_W_VIDX_PSEUDO = 504,
520 JALR64Pseudo = 505,
521 JALRHB64Pseudo = 506,
522 JALRHBPseudo = 507,
523 JALRPseudo = 508,
524 JAL_MMR6 = 509,
525 JalOneReg = 510,
526 JalTwoReg = 511,
527 LDMacro = 512,
528 LDR_D = 513,
529 LDR_W = 514,
530 LD_F16 = 515,
531 LOAD_ACC128 = 516,
532 LOAD_ACC64 = 517,
533 LOAD_ACC64DSP = 518,
534 LOAD_CCOND_DSP = 519,
535 LONG_BRANCH_ADDiu = 520,
536 LONG_BRANCH_ADDiu2Op = 521,
537 LONG_BRANCH_DADDiu = 522,
538 LONG_BRANCH_DADDiu2Op = 523,
539 LONG_BRANCH_LUi = 524,
540 LONG_BRANCH_LUi2Op = 525,
541 LONG_BRANCH_LUi2Op_64 = 526,
542 LWM_MM = 527,
543 LoadAddrImm32 = 528,
544 LoadAddrImm64 = 529,
545 LoadAddrReg32 = 530,
546 LoadAddrReg64 = 531,
547 LoadImm32 = 532,
548 LoadImm64 = 533,
549 LoadImmDoubleFGR = 534,
550 LoadImmDoubleFGR_32 = 535,
551 LoadImmDoubleGPR = 536,
552 LoadImmSingleFGR = 537,
553 LoadImmSingleGPR = 538,
554 LwConstant32 = 539,
555 MFTACX = 540,
556 MFTC0 = 541,
557 MFTC1 = 542,
558 MFTDSP = 543,
559 MFTGPR = 544,
560 MFTHC1 = 545,
561 MFTHI = 546,
562 MFTLO = 547,
563 MIPSeh_return32 = 548,
564 MIPSeh_return64 = 549,
565 MSA_FP_EXTEND_D_PSEUDO = 550,
566 MSA_FP_EXTEND_W_PSEUDO = 551,
567 MSA_FP_ROUND_D_PSEUDO = 552,
568 MSA_FP_ROUND_W_PSEUDO = 553,
569 MTTACX = 554,
570 MTTC0 = 555,
571 MTTC1 = 556,
572 MTTDSP = 557,
573 MTTGPR = 558,
574 MTTHC1 = 559,
575 MTTHI = 560,
576 MTTLO = 561,
577 MULImmMacro = 562,
578 MULOMacro = 563,
579 MULOUMacro = 564,
580 MultRxRy16 = 565,
581 MultRxRyRz16 = 566,
582 MultuRxRy16 = 567,
583 MultuRxRyRz16 = 568,
584 NOP = 569,
585 NORImm = 570,
586 NORImm64 = 571,
587 NOR_V_D_PSEUDO = 572,
588 NOR_V_H_PSEUDO = 573,
589 NOR_V_W_PSEUDO = 574,
590 OR_V_D_PSEUDO = 575,
591 OR_V_H_PSEUDO = 576,
592 OR_V_W_PSEUDO = 577,
593 PseudoCMPU_EQ_QB = 578,
594 PseudoCMPU_LE_QB = 579,
595 PseudoCMPU_LT_QB = 580,
596 PseudoCMP_EQ_PH = 581,
597 PseudoCMP_LE_PH = 582,
598 PseudoCMP_LT_PH = 583,
599 PseudoCVT_D32_W = 584,
600 PseudoCVT_D64_L = 585,
601 PseudoCVT_D64_W = 586,
602 PseudoCVT_S_L = 587,
603 PseudoCVT_S_W = 588,
604 PseudoDMULT = 589,
605 PseudoDMULTu = 590,
606 PseudoDSDIV = 591,
607 PseudoDUDIV = 592,
608 PseudoD_SELECT_I = 593,
609 PseudoD_SELECT_I64 = 594,
610 PseudoIndirectBranch = 595,
611 PseudoIndirectBranch64 = 596,
612 PseudoIndirectBranch64R6 = 597,
613 PseudoIndirectBranchR6 = 598,
614 PseudoIndirectBranch_MM = 599,
615 PseudoIndirectBranch_MMR6 = 600,
616 PseudoIndirectHazardBranch = 601,
617 PseudoIndirectHazardBranch64 = 602,
618 PseudoIndrectHazardBranch64R6 = 603,
619 PseudoIndrectHazardBranchR6 = 604,
620 PseudoMADD = 605,
621 PseudoMADDU = 606,
622 PseudoMADDU_MM = 607,
623 PseudoMADD_MM = 608,
624 PseudoMFHI = 609,
625 PseudoMFHI64 = 610,
626 PseudoMFHI_MM = 611,
627 PseudoMFLO = 612,
628 PseudoMFLO64 = 613,
629 PseudoMFLO_MM = 614,
630 PseudoMSUB = 615,
631 PseudoMSUBU = 616,
632 PseudoMSUBU_MM = 617,
633 PseudoMSUB_MM = 618,
634 PseudoMTLOHI = 619,
635 PseudoMTLOHI64 = 620,
636 PseudoMTLOHI_DSP = 621,
637 PseudoMTLOHI_MM = 622,
638 PseudoMULT = 623,
639 PseudoMULT_MM = 624,
640 PseudoMULTu = 625,
641 PseudoMULTu_MM = 626,
642 PseudoPICK_PH = 627,
643 PseudoPICK_QB = 628,
644 PseudoReturn = 629,
645 PseudoReturn64 = 630,
646 PseudoSDIV = 631,
647 PseudoSELECTFP_F_D32 = 632,
648 PseudoSELECTFP_F_D64 = 633,
649 PseudoSELECTFP_F_I = 634,
650 PseudoSELECTFP_F_I64 = 635,
651 PseudoSELECTFP_F_S = 636,
652 PseudoSELECTFP_T_D32 = 637,
653 PseudoSELECTFP_T_D64 = 638,
654 PseudoSELECTFP_T_I = 639,
655 PseudoSELECTFP_T_I64 = 640,
656 PseudoSELECTFP_T_S = 641,
657 PseudoSELECT_D32 = 642,
658 PseudoSELECT_D64 = 643,
659 PseudoSELECT_I = 644,
660 PseudoSELECT_I64 = 645,
661 PseudoSELECT_S = 646,
662 PseudoTRUNC_W_D = 647,
663 PseudoTRUNC_W_D32 = 648,
664 PseudoTRUNC_W_S = 649,
665 PseudoUDIV = 650,
666 ROL = 651,
667 ROLImm = 652,
668 ROR = 653,
669 RORImm = 654,
670 RetRA = 655,
671 RetRA16 = 656,
672 SDC1_M1 = 657,
673 SDIV_MM_Pseudo = 658,
674 SDMacro = 659,
675 SDivIMacro = 660,
676 SDivMacro = 661,
677 SEQIMacro = 662,
678 SEQMacro = 663,
679 SGE = 664,
680 SGEImm = 665,
681 SGEImm64 = 666,
682 SGEU = 667,
683 SGEUImm = 668,
684 SGEUImm64 = 669,
685 SGTImm = 670,
686 SGTImm64 = 671,
687 SGTUImm = 672,
688 SGTUImm64 = 673,
689 SLE = 674,
690 SLEImm = 675,
691 SLEImm64 = 676,
692 SLEU = 677,
693 SLEUImm = 678,
694 SLEUImm64 = 679,
695 SLTImm64 = 680,
696 SLTUImm64 = 681,
697 SNEIMacro = 682,
698 SNEMacro = 683,
699 SNZ_B_PSEUDO = 684,
700 SNZ_D_PSEUDO = 685,
701 SNZ_H_PSEUDO = 686,
702 SNZ_V_PSEUDO = 687,
703 SNZ_W_PSEUDO = 688,
704 SRemIMacro = 689,
705 SRemMacro = 690,
706 STORE_ACC128 = 691,
707 STORE_ACC64 = 692,
708 STORE_ACC64DSP = 693,
709 STORE_CCOND_DSP = 694,
710 STR_D = 695,
711 STR_W = 696,
712 ST_F16 = 697,
713 SWM_MM = 698,
714 SZ_B_PSEUDO = 699,
715 SZ_D_PSEUDO = 700,
716 SZ_H_PSEUDO = 701,
717 SZ_V_PSEUDO = 702,
718 SZ_W_PSEUDO = 703,
719 SaaAddr = 704,
720 SaadAddr = 705,
721 SelBeqZ = 706,
722 SelBneZ = 707,
723 SelTBteqZCmp = 708,
724 SelTBteqZCmpi = 709,
725 SelTBteqZSlt = 710,
726 SelTBteqZSlti = 711,
727 SelTBteqZSltiu = 712,
728 SelTBteqZSltu = 713,
729 SelTBtneZCmp = 714,
730 SelTBtneZCmpi = 715,
731 SelTBtneZSlt = 716,
732 SelTBtneZSlti = 717,
733 SelTBtneZSltiu = 718,
734 SelTBtneZSltu = 719,
735 SltCCRxRy16 = 720,
736 SltiCCRxImmX16 = 721,
737 SltiuCCRxImmX16 = 722,
738 SltuCCRxRy16 = 723,
739 SltuRxRyRz16 = 724,
740 TAILCALL = 725,
741 TAILCALL64R6REG = 726,
742 TAILCALLHB64R6REG = 727,
743 TAILCALLHBR6REG = 728,
744 TAILCALLR6REG = 729,
745 TAILCALLREG = 730,
746 TAILCALLREG64 = 731,
747 TAILCALLREGHB = 732,
748 TAILCALLREGHB64 = 733,
749 TAILCALLREG_MM = 734,
750 TAILCALLREG_MMR6 = 735,
751 TAILCALL_MM = 736,
752 TAILCALL_MMR6 = 737,
753 TRAP = 738,
754 TRAP_MM = 739,
755 UDIV_MM_Pseudo = 740,
756 UDivIMacro = 741,
757 UDivMacro = 742,
758 URemIMacro = 743,
759 URemMacro = 744,
760 Ulh = 745,
761 Ulhu = 746,
762 Ulw = 747,
763 Ush = 748,
764 Usw = 749,
765 XOR_V_D_PSEUDO = 750,
766 XOR_V_H_PSEUDO = 751,
767 XOR_V_W_PSEUDO = 752,
768 ABSQ_S_PH = 753,
769 ABSQ_S_PH_MM = 754,
770 ABSQ_S_QB = 755,
771 ABSQ_S_QB_MMR2 = 756,
772 ABSQ_S_W = 757,
773 ABSQ_S_W_MM = 758,
774 ADD = 759,
775 ADDIUPC = 760,
776 ADDIUPC_MM = 761,
777 ADDIUPC_MMR6 = 762,
778 ADDIUR1SP_MM = 763,
779 ADDIUR2_MM = 764,
780 ADDIUS5_MM = 765,
781 ADDIUSP_MM = 766,
782 ADDIU_MMR6 = 767,
783 ADDQH_PH = 768,
784 ADDQH_PH_MMR2 = 769,
785 ADDQH_R_PH = 770,
786 ADDQH_R_PH_MMR2 = 771,
787 ADDQH_R_W = 772,
788 ADDQH_R_W_MMR2 = 773,
789 ADDQH_W = 774,
790 ADDQH_W_MMR2 = 775,
791 ADDQ_PH = 776,
792 ADDQ_PH_MM = 777,
793 ADDQ_S_PH = 778,
794 ADDQ_S_PH_MM = 779,
795 ADDQ_S_W = 780,
796 ADDQ_S_W_MM = 781,
797 ADDR_PS64 = 782,
798 ADDSC = 783,
799 ADDSC_MM = 784,
800 ADDS_A_B = 785,
801 ADDS_A_D = 786,
802 ADDS_A_H = 787,
803 ADDS_A_W = 788,
804 ADDS_S_B = 789,
805 ADDS_S_D = 790,
806 ADDS_S_H = 791,
807 ADDS_S_W = 792,
808 ADDS_U_B = 793,
809 ADDS_U_D = 794,
810 ADDS_U_H = 795,
811 ADDS_U_W = 796,
812 ADDU16_MM = 797,
813 ADDU16_MMR6 = 798,
814 ADDUH_QB = 799,
815 ADDUH_QB_MMR2 = 800,
816 ADDUH_R_QB = 801,
817 ADDUH_R_QB_MMR2 = 802,
818 ADDU_MMR6 = 803,
819 ADDU_PH = 804,
820 ADDU_PH_MMR2 = 805,
821 ADDU_QB = 806,
822 ADDU_QB_MM = 807,
823 ADDU_S_PH = 808,
824 ADDU_S_PH_MMR2 = 809,
825 ADDU_S_QB = 810,
826 ADDU_S_QB_MM = 811,
827 ADDVI_B = 812,
828 ADDVI_D = 813,
829 ADDVI_H = 814,
830 ADDVI_W = 815,
831 ADDV_B = 816,
832 ADDV_D = 817,
833 ADDV_H = 818,
834 ADDV_W = 819,
835 ADDWC = 820,
836 ADDWC_MM = 821,
837 ADD_A_B = 822,
838 ADD_A_D = 823,
839 ADD_A_H = 824,
840 ADD_A_W = 825,
841 ADD_MM = 826,
842 ADD_MMR6 = 827,
843 ADDi = 828,
844 ADDi_MM = 829,
845 ADDiu = 830,
846 ADDiu_MM = 831,
847 ADDu = 832,
848 ADDu_MM = 833,
849 ALIGN = 834,
850 ALIGN_MMR6 = 835,
851 ALUIPC = 836,
852 ALUIPC_MMR6 = 837,
853 AND = 838,
854 AND16_MM = 839,
855 AND16_MMR6 = 840,
856 AND64 = 841,
857 ANDI16_MM = 842,
858 ANDI16_MMR6 = 843,
859 ANDI_B = 844,
860 ANDI_MMR6 = 845,
861 AND_MM = 846,
862 AND_MMR6 = 847,
863 AND_V = 848,
864 ANDi = 849,
865 ANDi64 = 850,
866 ANDi_MM = 851,
867 APPEND = 852,
868 APPEND_MMR2 = 853,
869 ASUB_S_B = 854,
870 ASUB_S_D = 855,
871 ASUB_S_H = 856,
872 ASUB_S_W = 857,
873 ASUB_U_B = 858,
874 ASUB_U_D = 859,
875 ASUB_U_H = 860,
876 ASUB_U_W = 861,
877 AUI = 862,
878 AUIPC = 863,
879 AUIPC_MMR6 = 864,
880 AUI_MMR6 = 865,
881 AVER_S_B = 866,
882 AVER_S_D = 867,
883 AVER_S_H = 868,
884 AVER_S_W = 869,
885 AVER_U_B = 870,
886 AVER_U_D = 871,
887 AVER_U_H = 872,
888 AVER_U_W = 873,
889 AVE_S_B = 874,
890 AVE_S_D = 875,
891 AVE_S_H = 876,
892 AVE_S_W = 877,
893 AVE_U_B = 878,
894 AVE_U_D = 879,
895 AVE_U_H = 880,
896 AVE_U_W = 881,
897 AddiuRxImmX16 = 882,
898 AddiuRxPcImmX16 = 883,
899 AddiuRxRxImm16 = 884,
900 AddiuRxRxImmX16 = 885,
901 AddiuRxRyOffMemX16 = 886,
902 AddiuSpImm16 = 887,
903 AddiuSpImmX16 = 888,
904 AdduRxRyRz16 = 889,
905 AndRxRxRy16 = 890,
906 B16_MM = 891,
907 BADDu = 892,
908 BAL = 893,
909 BALC = 894,
910 BALC_MMR6 = 895,
911 BALIGN = 896,
912 BALIGN_MMR2 = 897,
913 BBIT0 = 898,
914 BBIT032 = 899,
915 BBIT1 = 900,
916 BBIT132 = 901,
917 BC = 902,
918 BC16_MMR6 = 903,
919 BC1EQZ = 904,
920 BC1EQZC_MMR6 = 905,
921 BC1F = 906,
922 BC1FL = 907,
923 BC1F_MM = 908,
924 BC1NEZ = 909,
925 BC1NEZC_MMR6 = 910,
926 BC1T = 911,
927 BC1TL = 912,
928 BC1T_MM = 913,
929 BC2EQZ = 914,
930 BC2EQZC_MMR6 = 915,
931 BC2NEZ = 916,
932 BC2NEZC_MMR6 = 917,
933 BCLRI_B = 918,
934 BCLRI_D = 919,
935 BCLRI_H = 920,
936 BCLRI_W = 921,
937 BCLR_B = 922,
938 BCLR_D = 923,
939 BCLR_H = 924,
940 BCLR_W = 925,
941 BC_MMR6 = 926,
942 BEQ = 927,
943 BEQ64 = 928,
944 BEQC = 929,
945 BEQC64 = 930,
946 BEQC_MMR6 = 931,
947 BEQL = 932,
948 BEQZ16_MM = 933,
949 BEQZALC = 934,
950 BEQZALC_MMR6 = 935,
951 BEQZC = 936,
952 BEQZC16_MMR6 = 937,
953 BEQZC64 = 938,
954 BEQZC_MM = 939,
955 BEQZC_MMR6 = 940,
956 BEQ_MM = 941,
957 BGEC = 942,
958 BGEC64 = 943,
959 BGEC_MMR6 = 944,
960 BGEUC = 945,
961 BGEUC64 = 946,
962 BGEUC_MMR6 = 947,
963 BGEZ = 948,
964 BGEZ64 = 949,
965 BGEZAL = 950,
966 BGEZALC = 951,
967 BGEZALC_MMR6 = 952,
968 BGEZALL = 953,
969 BGEZALS_MM = 954,
970 BGEZAL_MM = 955,
971 BGEZC = 956,
972 BGEZC64 = 957,
973 BGEZC_MMR6 = 958,
974 BGEZL = 959,
975 BGEZ_MM = 960,
976 BGTZ = 961,
977 BGTZ64 = 962,
978 BGTZALC = 963,
979 BGTZALC_MMR6 = 964,
980 BGTZC = 965,
981 BGTZC64 = 966,
982 BGTZC_MMR6 = 967,
983 BGTZL = 968,
984 BGTZ_MM = 969,
985 BINSLI_B = 970,
986 BINSLI_D = 971,
987 BINSLI_H = 972,
988 BINSLI_W = 973,
989 BINSL_B = 974,
990 BINSL_D = 975,
991 BINSL_H = 976,
992 BINSL_W = 977,
993 BINSRI_B = 978,
994 BINSRI_D = 979,
995 BINSRI_H = 980,
996 BINSRI_W = 981,
997 BINSR_B = 982,
998 BINSR_D = 983,
999 BINSR_H = 984,
1000 BINSR_W = 985,
1001 BITREV = 986,
1002 BITREV_MM = 987,
1003 BITSWAP = 988,
1004 BITSWAP_MMR6 = 989,
1005 BLEZ = 990,
1006 BLEZ64 = 991,
1007 BLEZALC = 992,
1008 BLEZALC_MMR6 = 993,
1009 BLEZC = 994,
1010 BLEZC64 = 995,
1011 BLEZC_MMR6 = 996,
1012 BLEZL = 997,
1013 BLEZ_MM = 998,
1014 BLTC = 999,
1015 BLTC64 = 1000,
1016 BLTC_MMR6 = 1001,
1017 BLTUC = 1002,
1018 BLTUC64 = 1003,
1019 BLTUC_MMR6 = 1004,
1020 BLTZ = 1005,
1021 BLTZ64 = 1006,
1022 BLTZAL = 1007,
1023 BLTZALC = 1008,
1024 BLTZALC_MMR6 = 1009,
1025 BLTZALL = 1010,
1026 BLTZALS_MM = 1011,
1027 BLTZAL_MM = 1012,
1028 BLTZC = 1013,
1029 BLTZC64 = 1014,
1030 BLTZC_MMR6 = 1015,
1031 BLTZL = 1016,
1032 BLTZ_MM = 1017,
1033 BMNZI_B = 1018,
1034 BMNZ_V = 1019,
1035 BMZI_B = 1020,
1036 BMZ_V = 1021,
1037 BNE = 1022,
1038 BNE64 = 1023,
1039 BNEC = 1024,
1040 BNEC64 = 1025,
1041 BNEC_MMR6 = 1026,
1042 BNEGI_B = 1027,
1043 BNEGI_D = 1028,
1044 BNEGI_H = 1029,
1045 BNEGI_W = 1030,
1046 BNEG_B = 1031,
1047 BNEG_D = 1032,
1048 BNEG_H = 1033,
1049 BNEG_W = 1034,
1050 BNEL = 1035,
1051 BNEZ16_MM = 1036,
1052 BNEZALC = 1037,
1053 BNEZALC_MMR6 = 1038,
1054 BNEZC = 1039,
1055 BNEZC16_MMR6 = 1040,
1056 BNEZC64 = 1041,
1057 BNEZC_MM = 1042,
1058 BNEZC_MMR6 = 1043,
1059 BNE_MM = 1044,
1060 BNVC = 1045,
1061 BNVC_MMR6 = 1046,
1062 BNZ_B = 1047,
1063 BNZ_D = 1048,
1064 BNZ_H = 1049,
1065 BNZ_V = 1050,
1066 BNZ_W = 1051,
1067 BOVC = 1052,
1068 BOVC_MMR6 = 1053,
1069 BPOSGE32 = 1054,
1070 BPOSGE32C_MMR3 = 1055,
1071 BPOSGE32_MM = 1056,
1072 BREAK = 1057,
1073 BREAK16_MM = 1058,
1074 BREAK16_MMR6 = 1059,
1075 BREAK_MM = 1060,
1076 BREAK_MMR6 = 1061,
1077 BSELI_B = 1062,
1078 BSEL_V = 1063,
1079 BSETI_B = 1064,
1080 BSETI_D = 1065,
1081 BSETI_H = 1066,
1082 BSETI_W = 1067,
1083 BSET_B = 1068,
1084 BSET_D = 1069,
1085 BSET_H = 1070,
1086 BSET_W = 1071,
1087 BZ_B = 1072,
1088 BZ_D = 1073,
1089 BZ_H = 1074,
1090 BZ_V = 1075,
1091 BZ_W = 1076,
1092 BeqzRxImm16 = 1077,
1093 BeqzRxImmX16 = 1078,
1094 Bimm16 = 1079,
1095 BimmX16 = 1080,
1096 BnezRxImm16 = 1081,
1097 BnezRxImmX16 = 1082,
1098 Break16 = 1083,
1099 Bteqz16 = 1084,
1100 BteqzX16 = 1085,
1101 Btnez16 = 1086,
1102 BtnezX16 = 1087,
1103 CACHE = 1088,
1104 CACHEE = 1089,
1105 CACHEE_MM = 1090,
1106 CACHE_MM = 1091,
1107 CACHE_MMR6 = 1092,
1108 CACHE_R6 = 1093,
1109 CEIL_L_D64 = 1094,
1110 CEIL_L_D_MMR6 = 1095,
1111 CEIL_L_S = 1096,
1112 CEIL_L_S_MMR6 = 1097,
1113 CEIL_W_D32 = 1098,
1114 CEIL_W_D64 = 1099,
1115 CEIL_W_D_MMR6 = 1100,
1116 CEIL_W_MM = 1101,
1117 CEIL_W_S = 1102,
1118 CEIL_W_S_MM = 1103,
1119 CEIL_W_S_MMR6 = 1104,
1120 CEQI_B = 1105,
1121 CEQI_D = 1106,
1122 CEQI_H = 1107,
1123 CEQI_W = 1108,
1124 CEQ_B = 1109,
1125 CEQ_D = 1110,
1126 CEQ_H = 1111,
1127 CEQ_W = 1112,
1128 CFC1 = 1113,
1129 CFC1_MM = 1114,
1130 CFC2_MM = 1115,
1131 CFCMSA = 1116,
1132 CINS = 1117,
1133 CINS32 = 1118,
1134 CINS64_32 = 1119,
1135 CINS_i32 = 1120,
1136 CLASS_D = 1121,
1137 CLASS_D_MMR6 = 1122,
1138 CLASS_S = 1123,
1139 CLASS_S_MMR6 = 1124,
1140 CLEI_S_B = 1125,
1141 CLEI_S_D = 1126,
1142 CLEI_S_H = 1127,
1143 CLEI_S_W = 1128,
1144 CLEI_U_B = 1129,
1145 CLEI_U_D = 1130,
1146 CLEI_U_H = 1131,
1147 CLEI_U_W = 1132,
1148 CLE_S_B = 1133,
1149 CLE_S_D = 1134,
1150 CLE_S_H = 1135,
1151 CLE_S_W = 1136,
1152 CLE_U_B = 1137,
1153 CLE_U_D = 1138,
1154 CLE_U_H = 1139,
1155 CLE_U_W = 1140,
1156 CLO = 1141,
1157 CLO_MM = 1142,
1158 CLO_MMR6 = 1143,
1159 CLO_R6 = 1144,
1160 CLTI_S_B = 1145,
1161 CLTI_S_D = 1146,
1162 CLTI_S_H = 1147,
1163 CLTI_S_W = 1148,
1164 CLTI_U_B = 1149,
1165 CLTI_U_D = 1150,
1166 CLTI_U_H = 1151,
1167 CLTI_U_W = 1152,
1168 CLT_S_B = 1153,
1169 CLT_S_D = 1154,
1170 CLT_S_H = 1155,
1171 CLT_S_W = 1156,
1172 CLT_U_B = 1157,
1173 CLT_U_D = 1158,
1174 CLT_U_H = 1159,
1175 CLT_U_W = 1160,
1176 CLZ = 1161,
1177 CLZ_MM = 1162,
1178 CLZ_MMR6 = 1163,
1179 CLZ_R6 = 1164,
1180 CMPGDU_EQ_QB = 1165,
1181 CMPGDU_EQ_QB_MMR2 = 1166,
1182 CMPGDU_LE_QB = 1167,
1183 CMPGDU_LE_QB_MMR2 = 1168,
1184 CMPGDU_LT_QB = 1169,
1185 CMPGDU_LT_QB_MMR2 = 1170,
1186 CMPGU_EQ_QB = 1171,
1187 CMPGU_EQ_QB_MM = 1172,
1188 CMPGU_LE_QB = 1173,
1189 CMPGU_LE_QB_MM = 1174,
1190 CMPGU_LT_QB = 1175,
1191 CMPGU_LT_QB_MM = 1176,
1192 CMPU_EQ_QB = 1177,
1193 CMPU_EQ_QB_MM = 1178,
1194 CMPU_LE_QB = 1179,
1195 CMPU_LE_QB_MM = 1180,
1196 CMPU_LT_QB = 1181,
1197 CMPU_LT_QB_MM = 1182,
1198 CMP_AF_D_MMR6 = 1183,
1199 CMP_AF_S_MMR6 = 1184,
1200 CMP_EQ_D = 1185,
1201 CMP_EQ_D_MMR6 = 1186,
1202 CMP_EQ_PH = 1187,
1203 CMP_EQ_PH_MM = 1188,
1204 CMP_EQ_S = 1189,
1205 CMP_EQ_S_MMR6 = 1190,
1206 CMP_F_D = 1191,
1207 CMP_F_S = 1192,
1208 CMP_LE_D = 1193,
1209 CMP_LE_D_MMR6 = 1194,
1210 CMP_LE_PH = 1195,
1211 CMP_LE_PH_MM = 1196,
1212 CMP_LE_S = 1197,
1213 CMP_LE_S_MMR6 = 1198,
1214 CMP_LT_D = 1199,
1215 CMP_LT_D_MMR6 = 1200,
1216 CMP_LT_PH = 1201,
1217 CMP_LT_PH_MM = 1202,
1218 CMP_LT_S = 1203,
1219 CMP_LT_S_MMR6 = 1204,
1220 CMP_SAF_D = 1205,
1221 CMP_SAF_D_MMR6 = 1206,
1222 CMP_SAF_S = 1207,
1223 CMP_SAF_S_MMR6 = 1208,
1224 CMP_SEQ_D = 1209,
1225 CMP_SEQ_D_MMR6 = 1210,
1226 CMP_SEQ_S = 1211,
1227 CMP_SEQ_S_MMR6 = 1212,
1228 CMP_SLE_D = 1213,
1229 CMP_SLE_D_MMR6 = 1214,
1230 CMP_SLE_S = 1215,
1231 CMP_SLE_S_MMR6 = 1216,
1232 CMP_SLT_D = 1217,
1233 CMP_SLT_D_MMR6 = 1218,
1234 CMP_SLT_S = 1219,
1235 CMP_SLT_S_MMR6 = 1220,
1236 CMP_SUEQ_D = 1221,
1237 CMP_SUEQ_D_MMR6 = 1222,
1238 CMP_SUEQ_S = 1223,
1239 CMP_SUEQ_S_MMR6 = 1224,
1240 CMP_SULE_D = 1225,
1241 CMP_SULE_D_MMR6 = 1226,
1242 CMP_SULE_S = 1227,
1243 CMP_SULE_S_MMR6 = 1228,
1244 CMP_SULT_D = 1229,
1245 CMP_SULT_D_MMR6 = 1230,
1246 CMP_SULT_S = 1231,
1247 CMP_SULT_S_MMR6 = 1232,
1248 CMP_SUN_D = 1233,
1249 CMP_SUN_D_MMR6 = 1234,
1250 CMP_SUN_S = 1235,
1251 CMP_SUN_S_MMR6 = 1236,
1252 CMP_UEQ_D = 1237,
1253 CMP_UEQ_D_MMR6 = 1238,
1254 CMP_UEQ_S = 1239,
1255 CMP_UEQ_S_MMR6 = 1240,
1256 CMP_ULE_D = 1241,
1257 CMP_ULE_D_MMR6 = 1242,
1258 CMP_ULE_S = 1243,
1259 CMP_ULE_S_MMR6 = 1244,
1260 CMP_ULT_D = 1245,
1261 CMP_ULT_D_MMR6 = 1246,
1262 CMP_ULT_S = 1247,
1263 CMP_ULT_S_MMR6 = 1248,
1264 CMP_UN_D = 1249,
1265 CMP_UN_D_MMR6 = 1250,
1266 CMP_UN_S = 1251,
1267 CMP_UN_S_MMR6 = 1252,
1268 COPY_S_B = 1253,
1269 COPY_S_D = 1254,
1270 COPY_S_H = 1255,
1271 COPY_S_W = 1256,
1272 COPY_U_B = 1257,
1273 COPY_U_H = 1258,
1274 COPY_U_W = 1259,
1275 CRC32B = 1260,
1276 CRC32CB = 1261,
1277 CRC32CD = 1262,
1278 CRC32CH = 1263,
1279 CRC32CW = 1264,
1280 CRC32D = 1265,
1281 CRC32H = 1266,
1282 CRC32W = 1267,
1283 CTC1 = 1268,
1284 CTC1_MM = 1269,
1285 CTC2_MM = 1270,
1286 CTCMSA = 1271,
1287 CVT_D32_S = 1272,
1288 CVT_D32_S_MM = 1273,
1289 CVT_D32_W = 1274,
1290 CVT_D32_W_MM = 1275,
1291 CVT_D64_L = 1276,
1292 CVT_D64_S = 1277,
1293 CVT_D64_S_MM = 1278,
1294 CVT_D64_W = 1279,
1295 CVT_D64_W_MM = 1280,
1296 CVT_D_L_MMR6 = 1281,
1297 CVT_L_D64 = 1282,
1298 CVT_L_D64_MM = 1283,
1299 CVT_L_D_MMR6 = 1284,
1300 CVT_L_S = 1285,
1301 CVT_L_S_MM = 1286,
1302 CVT_L_S_MMR6 = 1287,
1303 CVT_PS_PW64 = 1288,
1304 CVT_PS_S64 = 1289,
1305 CVT_PW_PS64 = 1290,
1306 CVT_S_D32 = 1291,
1307 CVT_S_D32_MM = 1292,
1308 CVT_S_D64 = 1293,
1309 CVT_S_D64_MM = 1294,
1310 CVT_S_L = 1295,
1311 CVT_S_L_MMR6 = 1296,
1312 CVT_S_PL64 = 1297,
1313 CVT_S_PU64 = 1298,
1314 CVT_S_W = 1299,
1315 CVT_S_W_MM = 1300,
1316 CVT_S_W_MMR6 = 1301,
1317 CVT_W_D32 = 1302,
1318 CVT_W_D32_MM = 1303,
1319 CVT_W_D64 = 1304,
1320 CVT_W_D64_MM = 1305,
1321 CVT_W_S = 1306,
1322 CVT_W_S_MM = 1307,
1323 CVT_W_S_MMR6 = 1308,
1324 C_EQ_D32 = 1309,
1325 C_EQ_D32_MM = 1310,
1326 C_EQ_D64 = 1311,
1327 C_EQ_D64_MM = 1312,
1328 C_EQ_S = 1313,
1329 C_EQ_S_MM = 1314,
1330 C_F_D32 = 1315,
1331 C_F_D32_MM = 1316,
1332 C_F_D64 = 1317,
1333 C_F_D64_MM = 1318,
1334 C_F_S = 1319,
1335 C_F_S_MM = 1320,
1336 C_LE_D32 = 1321,
1337 C_LE_D32_MM = 1322,
1338 C_LE_D64 = 1323,
1339 C_LE_D64_MM = 1324,
1340 C_LE_S = 1325,
1341 C_LE_S_MM = 1326,
1342 C_LT_D32 = 1327,
1343 C_LT_D32_MM = 1328,
1344 C_LT_D64 = 1329,
1345 C_LT_D64_MM = 1330,
1346 C_LT_S = 1331,
1347 C_LT_S_MM = 1332,
1348 C_NGE_D32 = 1333,
1349 C_NGE_D32_MM = 1334,
1350 C_NGE_D64 = 1335,
1351 C_NGE_D64_MM = 1336,
1352 C_NGE_S = 1337,
1353 C_NGE_S_MM = 1338,
1354 C_NGLE_D32 = 1339,
1355 C_NGLE_D32_MM = 1340,
1356 C_NGLE_D64 = 1341,
1357 C_NGLE_D64_MM = 1342,
1358 C_NGLE_S = 1343,
1359 C_NGLE_S_MM = 1344,
1360 C_NGL_D32 = 1345,
1361 C_NGL_D32_MM = 1346,
1362 C_NGL_D64 = 1347,
1363 C_NGL_D64_MM = 1348,
1364 C_NGL_S = 1349,
1365 C_NGL_S_MM = 1350,
1366 C_NGT_D32 = 1351,
1367 C_NGT_D32_MM = 1352,
1368 C_NGT_D64 = 1353,
1369 C_NGT_D64_MM = 1354,
1370 C_NGT_S = 1355,
1371 C_NGT_S_MM = 1356,
1372 C_OLE_D32 = 1357,
1373 C_OLE_D32_MM = 1358,
1374 C_OLE_D64 = 1359,
1375 C_OLE_D64_MM = 1360,
1376 C_OLE_S = 1361,
1377 C_OLE_S_MM = 1362,
1378 C_OLT_D32 = 1363,
1379 C_OLT_D32_MM = 1364,
1380 C_OLT_D64 = 1365,
1381 C_OLT_D64_MM = 1366,
1382 C_OLT_S = 1367,
1383 C_OLT_S_MM = 1368,
1384 C_SEQ_D32 = 1369,
1385 C_SEQ_D32_MM = 1370,
1386 C_SEQ_D64 = 1371,
1387 C_SEQ_D64_MM = 1372,
1388 C_SEQ_S = 1373,
1389 C_SEQ_S_MM = 1374,
1390 C_SF_D32 = 1375,
1391 C_SF_D32_MM = 1376,
1392 C_SF_D64 = 1377,
1393 C_SF_D64_MM = 1378,
1394 C_SF_S = 1379,
1395 C_SF_S_MM = 1380,
1396 C_UEQ_D32 = 1381,
1397 C_UEQ_D32_MM = 1382,
1398 C_UEQ_D64 = 1383,
1399 C_UEQ_D64_MM = 1384,
1400 C_UEQ_S = 1385,
1401 C_UEQ_S_MM = 1386,
1402 C_ULE_D32 = 1387,
1403 C_ULE_D32_MM = 1388,
1404 C_ULE_D64 = 1389,
1405 C_ULE_D64_MM = 1390,
1406 C_ULE_S = 1391,
1407 C_ULE_S_MM = 1392,
1408 C_ULT_D32 = 1393,
1409 C_ULT_D32_MM = 1394,
1410 C_ULT_D64 = 1395,
1411 C_ULT_D64_MM = 1396,
1412 C_ULT_S = 1397,
1413 C_ULT_S_MM = 1398,
1414 C_UN_D32 = 1399,
1415 C_UN_D32_MM = 1400,
1416 C_UN_D64 = 1401,
1417 C_UN_D64_MM = 1402,
1418 C_UN_S = 1403,
1419 C_UN_S_MM = 1404,
1420 CmpRxRy16 = 1405,
1421 CmpiRxImm16 = 1406,
1422 CmpiRxImmX16 = 1407,
1423 DADD = 1408,
1424 DADDi = 1409,
1425 DADDiu = 1410,
1426 DADDu = 1411,
1427 DAHI = 1412,
1428 DALIGN = 1413,
1429 DATI = 1414,
1430 DAUI = 1415,
1431 DBITSWAP = 1416,
1432 DCLO = 1417,
1433 DCLO_R6 = 1418,
1434 DCLZ = 1419,
1435 DCLZ_R6 = 1420,
1436 DDIV = 1421,
1437 DDIVU = 1422,
1438 DERET = 1423,
1439 DERET_MM = 1424,
1440 DERET_MMR6 = 1425,
1441 DEXT = 1426,
1442 DEXT64_32 = 1427,
1443 DEXTM = 1428,
1444 DEXTU = 1429,
1445 DI = 1430,
1446 DINS = 1431,
1447 DINSM = 1432,
1448 DINSU = 1433,
1449 DIV = 1434,
1450 DIVU = 1435,
1451 DIVU_MMR6 = 1436,
1452 DIV_MMR6 = 1437,
1453 DIV_S_B = 1438,
1454 DIV_S_D = 1439,
1455 DIV_S_H = 1440,
1456 DIV_S_W = 1441,
1457 DIV_U_B = 1442,
1458 DIV_U_D = 1443,
1459 DIV_U_H = 1444,
1460 DIV_U_W = 1445,
1461 DI_MM = 1446,
1462 DI_MMR6 = 1447,
1463 DLSA = 1448,
1464 DLSA_R6 = 1449,
1465 DMFC0 = 1450,
1466 DMFC1 = 1451,
1467 DMFC2 = 1452,
1468 DMFC2_OCTEON = 1453,
1469 DMFGC0 = 1454,
1470 DMOD = 1455,
1471 DMODU = 1456,
1472 DMT = 1457,
1473 DMTC0 = 1458,
1474 DMTC1 = 1459,
1475 DMTC2 = 1460,
1476 DMTC2_OCTEON = 1461,
1477 DMTGC0 = 1462,
1478 DMUH = 1463,
1479 DMUHU = 1464,
1480 DMUL = 1465,
1481 DMULT = 1466,
1482 DMULTu = 1467,
1483 DMULU = 1468,
1484 DMUL_R6 = 1469,
1485 DOTP_S_D = 1470,
1486 DOTP_S_H = 1471,
1487 DOTP_S_W = 1472,
1488 DOTP_U_D = 1473,
1489 DOTP_U_H = 1474,
1490 DOTP_U_W = 1475,
1491 DPADD_S_D = 1476,
1492 DPADD_S_H = 1477,
1493 DPADD_S_W = 1478,
1494 DPADD_U_D = 1479,
1495 DPADD_U_H = 1480,
1496 DPADD_U_W = 1481,
1497 DPAQX_SA_W_PH = 1482,
1498 DPAQX_SA_W_PH_MMR2 = 1483,
1499 DPAQX_S_W_PH = 1484,
1500 DPAQX_S_W_PH_MMR2 = 1485,
1501 DPAQ_SA_L_W = 1486,
1502 DPAQ_SA_L_W_MM = 1487,
1503 DPAQ_S_W_PH = 1488,
1504 DPAQ_S_W_PH_MM = 1489,
1505 DPAU_H_QBL = 1490,
1506 DPAU_H_QBL_MM = 1491,
1507 DPAU_H_QBR = 1492,
1508 DPAU_H_QBR_MM = 1493,
1509 DPAX_W_PH = 1494,
1510 DPAX_W_PH_MMR2 = 1495,
1511 DPA_W_PH = 1496,
1512 DPA_W_PH_MMR2 = 1497,
1513 DPOP = 1498,
1514 DPSQX_SA_W_PH = 1499,
1515 DPSQX_SA_W_PH_MMR2 = 1500,
1516 DPSQX_S_W_PH = 1501,
1517 DPSQX_S_W_PH_MMR2 = 1502,
1518 DPSQ_SA_L_W = 1503,
1519 DPSQ_SA_L_W_MM = 1504,
1520 DPSQ_S_W_PH = 1505,
1521 DPSQ_S_W_PH_MM = 1506,
1522 DPSUB_S_D = 1507,
1523 DPSUB_S_H = 1508,
1524 DPSUB_S_W = 1509,
1525 DPSUB_U_D = 1510,
1526 DPSUB_U_H = 1511,
1527 DPSUB_U_W = 1512,
1528 DPSU_H_QBL = 1513,
1529 DPSU_H_QBL_MM = 1514,
1530 DPSU_H_QBR = 1515,
1531 DPSU_H_QBR_MM = 1516,
1532 DPSX_W_PH = 1517,
1533 DPSX_W_PH_MMR2 = 1518,
1534 DPS_W_PH = 1519,
1535 DPS_W_PH_MMR2 = 1520,
1536 DROTR = 1521,
1537 DROTR32 = 1522,
1538 DROTRV = 1523,
1539 DSBH = 1524,
1540 DSDIV = 1525,
1541 DSHD = 1526,
1542 DSLL = 1527,
1543 DSLL32 = 1528,
1544 DSLL64_32 = 1529,
1545 DSLLV = 1530,
1546 DSRA = 1531,
1547 DSRA32 = 1532,
1548 DSRAV = 1533,
1549 DSRL = 1534,
1550 DSRL32 = 1535,
1551 DSRLV = 1536,
1552 DSUB = 1537,
1553 DSUBu = 1538,
1554 DUDIV = 1539,
1555 DVP = 1540,
1556 DVPE = 1541,
1557 DVP_MMR6 = 1542,
1558 DivRxRy16 = 1543,
1559 DivuRxRy16 = 1544,
1560 EHB = 1545,
1561 EHB_MM = 1546,
1562 EHB_MMR6 = 1547,
1563 EI = 1548,
1564 EI_MM = 1549,
1565 EI_MMR6 = 1550,
1566 EMT = 1551,
1567 ERET = 1552,
1568 ERETNC = 1553,
1569 ERETNC_MMR6 = 1554,
1570 ERET_MM = 1555,
1571 ERET_MMR6 = 1556,
1572 EVP = 1557,
1573 EVPE = 1558,
1574 EVP_MMR6 = 1559,
1575 EXT = 1560,
1576 EXTP = 1561,
1577 EXTPDP = 1562,
1578 EXTPDPV = 1563,
1579 EXTPDPV_MM = 1564,
1580 EXTPDP_MM = 1565,
1581 EXTPV = 1566,
1582 EXTPV_MM = 1567,
1583 EXTP_MM = 1568,
1584 EXTRV_RS_W = 1569,
1585 EXTRV_RS_W_MM = 1570,
1586 EXTRV_R_W = 1571,
1587 EXTRV_R_W_MM = 1572,
1588 EXTRV_S_H = 1573,
1589 EXTRV_S_H_MM = 1574,
1590 EXTRV_W = 1575,
1591 EXTRV_W_MM = 1576,
1592 EXTR_RS_W = 1577,
1593 EXTR_RS_W_MM = 1578,
1594 EXTR_R_W = 1579,
1595 EXTR_R_W_MM = 1580,
1596 EXTR_S_H = 1581,
1597 EXTR_S_H_MM = 1582,
1598 EXTR_W = 1583,
1599 EXTR_W_MM = 1584,
1600 EXTS = 1585,
1601 EXTS32 = 1586,
1602 EXT_MM = 1587,
1603 EXT_MMR6 = 1588,
1604 FABS_D32 = 1589,
1605 FABS_D32_MM = 1590,
1606 FABS_D64 = 1591,
1607 FABS_D64_MM = 1592,
1608 FABS_S = 1593,
1609 FABS_S_MM = 1594,
1610 FADD_D = 1595,
1611 FADD_D32 = 1596,
1612 FADD_D32_MM = 1597,
1613 FADD_D64 = 1598,
1614 FADD_D64_MM = 1599,
1615 FADD_PS64 = 1600,
1616 FADD_S = 1601,
1617 FADD_S_MM = 1602,
1618 FADD_S_MMR6 = 1603,
1619 FADD_W = 1604,
1620 FCAF_D = 1605,
1621 FCAF_W = 1606,
1622 FCEQ_D = 1607,
1623 FCEQ_W = 1608,
1624 FCLASS_D = 1609,
1625 FCLASS_W = 1610,
1626 FCLE_D = 1611,
1627 FCLE_W = 1612,
1628 FCLT_D = 1613,
1629 FCLT_W = 1614,
1630 FCMP_D32 = 1615,
1631 FCMP_D32_MM = 1616,
1632 FCMP_D64 = 1617,
1633 FCMP_S32 = 1618,
1634 FCMP_S32_MM = 1619,
1635 FCNE_D = 1620,
1636 FCNE_W = 1621,
1637 FCOR_D = 1622,
1638 FCOR_W = 1623,
1639 FCUEQ_D = 1624,
1640 FCUEQ_W = 1625,
1641 FCULE_D = 1626,
1642 FCULE_W = 1627,
1643 FCULT_D = 1628,
1644 FCULT_W = 1629,
1645 FCUNE_D = 1630,
1646 FCUNE_W = 1631,
1647 FCUN_D = 1632,
1648 FCUN_W = 1633,
1649 FDIV_D = 1634,
1650 FDIV_D32 = 1635,
1651 FDIV_D32_MM = 1636,
1652 FDIV_D64 = 1637,
1653 FDIV_D64_MM = 1638,
1654 FDIV_S = 1639,
1655 FDIV_S_MM = 1640,
1656 FDIV_S_MMR6 = 1641,
1657 FDIV_W = 1642,
1658 FEXDO_H = 1643,
1659 FEXDO_W = 1644,
1660 FEXP2_D = 1645,
1661 FEXP2_W = 1646,
1662 FEXUPL_D = 1647,
1663 FEXUPL_W = 1648,
1664 FEXUPR_D = 1649,
1665 FEXUPR_W = 1650,
1666 FFINT_S_D = 1651,
1667 FFINT_S_W = 1652,
1668 FFINT_U_D = 1653,
1669 FFINT_U_W = 1654,
1670 FFQL_D = 1655,
1671 FFQL_W = 1656,
1672 FFQR_D = 1657,
1673 FFQR_W = 1658,
1674 FILL_B = 1659,
1675 FILL_D = 1660,
1676 FILL_H = 1661,
1677 FILL_W = 1662,
1678 FLOG2_D = 1663,
1679 FLOG2_W = 1664,
1680 FLOOR_L_D64 = 1665,
1681 FLOOR_L_D_MMR6 = 1666,
1682 FLOOR_L_S = 1667,
1683 FLOOR_L_S_MMR6 = 1668,
1684 FLOOR_W_D32 = 1669,
1685 FLOOR_W_D64 = 1670,
1686 FLOOR_W_D_MMR6 = 1671,
1687 FLOOR_W_MM = 1672,
1688 FLOOR_W_S = 1673,
1689 FLOOR_W_S_MM = 1674,
1690 FLOOR_W_S_MMR6 = 1675,
1691 FMADD_D = 1676,
1692 FMADD_W = 1677,
1693 FMAX_A_D = 1678,
1694 FMAX_A_W = 1679,
1695 FMAX_D = 1680,
1696 FMAX_W = 1681,
1697 FMIN_A_D = 1682,
1698 FMIN_A_W = 1683,
1699 FMIN_D = 1684,
1700 FMIN_W = 1685,
1701 FMOV_D32 = 1686,
1702 FMOV_D32_MM = 1687,
1703 FMOV_D64 = 1688,
1704 FMOV_D64_MM = 1689,
1705 FMOV_D_MMR6 = 1690,
1706 FMOV_S = 1691,
1707 FMOV_S_MM = 1692,
1708 FMOV_S_MMR6 = 1693,
1709 FMSUB_D = 1694,
1710 FMSUB_W = 1695,
1711 FMUL_D = 1696,
1712 FMUL_D32 = 1697,
1713 FMUL_D32_MM = 1698,
1714 FMUL_D64 = 1699,
1715 FMUL_D64_MM = 1700,
1716 FMUL_PS64 = 1701,
1717 FMUL_S = 1702,
1718 FMUL_S_MM = 1703,
1719 FMUL_S_MMR6 = 1704,
1720 FMUL_W = 1705,
1721 FNEG_D32 = 1706,
1722 FNEG_D32_MM = 1707,
1723 FNEG_D64 = 1708,
1724 FNEG_D64_MM = 1709,
1725 FNEG_S = 1710,
1726 FNEG_S_MM = 1711,
1727 FNEG_S_MMR6 = 1712,
1728 FORK = 1713,
1729 FRCP_D = 1714,
1730 FRCP_W = 1715,
1731 FRINT_D = 1716,
1732 FRINT_W = 1717,
1733 FRSQRT_D = 1718,
1734 FRSQRT_W = 1719,
1735 FSAF_D = 1720,
1736 FSAF_W = 1721,
1737 FSEQ_D = 1722,
1738 FSEQ_W = 1723,
1739 FSLE_D = 1724,
1740 FSLE_W = 1725,
1741 FSLT_D = 1726,
1742 FSLT_W = 1727,
1743 FSNE_D = 1728,
1744 FSNE_W = 1729,
1745 FSOR_D = 1730,
1746 FSOR_W = 1731,
1747 FSQRT_D = 1732,
1748 FSQRT_D32 = 1733,
1749 FSQRT_D32_MM = 1734,
1750 FSQRT_D64 = 1735,
1751 FSQRT_D64_MM = 1736,
1752 FSQRT_S = 1737,
1753 FSQRT_S_MM = 1738,
1754 FSQRT_W = 1739,
1755 FSUB_D = 1740,
1756 FSUB_D32 = 1741,
1757 FSUB_D32_MM = 1742,
1758 FSUB_D64 = 1743,
1759 FSUB_D64_MM = 1744,
1760 FSUB_PS64 = 1745,
1761 FSUB_S = 1746,
1762 FSUB_S_MM = 1747,
1763 FSUB_S_MMR6 = 1748,
1764 FSUB_W = 1749,
1765 FSUEQ_D = 1750,
1766 FSUEQ_W = 1751,
1767 FSULE_D = 1752,
1768 FSULE_W = 1753,
1769 FSULT_D = 1754,
1770 FSULT_W = 1755,
1771 FSUNE_D = 1756,
1772 FSUNE_W = 1757,
1773 FSUN_D = 1758,
1774 FSUN_W = 1759,
1775 FTINT_S_D = 1760,
1776 FTINT_S_W = 1761,
1777 FTINT_U_D = 1762,
1778 FTINT_U_W = 1763,
1779 FTQ_H = 1764,
1780 FTQ_W = 1765,
1781 FTRUNC_S_D = 1766,
1782 FTRUNC_S_W = 1767,
1783 FTRUNC_U_D = 1768,
1784 FTRUNC_U_W = 1769,
1785 GINVI = 1770,
1786 GINVI_MMR6 = 1771,
1787 GINVT = 1772,
1788 GINVT_MMR6 = 1773,
1789 HADD_S_D = 1774,
1790 HADD_S_H = 1775,
1791 HADD_S_W = 1776,
1792 HADD_U_D = 1777,
1793 HADD_U_H = 1778,
1794 HADD_U_W = 1779,
1795 HSUB_S_D = 1780,
1796 HSUB_S_H = 1781,
1797 HSUB_S_W = 1782,
1798 HSUB_U_D = 1783,
1799 HSUB_U_H = 1784,
1800 HSUB_U_W = 1785,
1801 HYPCALL = 1786,
1802 HYPCALL_MM = 1787,
1803 ILVEV_B = 1788,
1804 ILVEV_D = 1789,
1805 ILVEV_H = 1790,
1806 ILVEV_W = 1791,
1807 ILVL_B = 1792,
1808 ILVL_D = 1793,
1809 ILVL_H = 1794,
1810 ILVL_W = 1795,
1811 ILVOD_B = 1796,
1812 ILVOD_D = 1797,
1813 ILVOD_H = 1798,
1814 ILVOD_W = 1799,
1815 ILVR_B = 1800,
1816 ILVR_D = 1801,
1817 ILVR_H = 1802,
1818 ILVR_W = 1803,
1819 INS = 1804,
1820 INSERT_B = 1805,
1821 INSERT_D = 1806,
1822 INSERT_H = 1807,
1823 INSERT_W = 1808,
1824 INSV = 1809,
1825 INSVE_B = 1810,
1826 INSVE_D = 1811,
1827 INSVE_H = 1812,
1828 INSVE_W = 1813,
1829 INSV_MM = 1814,
1830 INS_MM = 1815,
1831 INS_MMR6 = 1816,
1832 J = 1817,
1833 JAL = 1818,
1834 JALR = 1819,
1835 JALR16_MM = 1820,
1836 JALR64 = 1821,
1837 JALRC16_MMR6 = 1822,
1838 JALRC_HB_MMR6 = 1823,
1839 JALRC_MMR6 = 1824,
1840 JALRS16_MM = 1825,
1841 JALRS_MM = 1826,
1842 JALR_HB = 1827,
1843 JALR_HB64 = 1828,
1844 JALR_MM = 1829,
1845 JALS_MM = 1830,
1846 JALX = 1831,
1847 JALX_MM = 1832,
1848 JAL_MM = 1833,
1849 JIALC = 1834,
1850 JIALC64 = 1835,
1851 JIALC_MMR6 = 1836,
1852 JIC = 1837,
1853 JIC64 = 1838,
1854 JIC_MMR6 = 1839,
1855 JR = 1840,
1856 JR16_MM = 1841,
1857 JR64 = 1842,
1858 JRADDIUSP = 1843,
1859 JRC16_MM = 1844,
1860 JRC16_MMR6 = 1845,
1861 JRCADDIUSP_MMR6 = 1846,
1862 JR_HB = 1847,
1863 JR_HB64 = 1848,
1864 JR_HB64_R6 = 1849,
1865 JR_HB_R6 = 1850,
1866 JR_MM = 1851,
1867 J_MM = 1852,
1868 Jal16 = 1853,
1869 JalB16 = 1854,
1870 JrRa16 = 1855,
1871 JrcRa16 = 1856,
1872 JrcRx16 = 1857,
1873 JumpLinkReg16 = 1858,
1874 LB = 1859,
1875 LB64 = 1860,
1876 LBE = 1861,
1877 LBE_MM = 1862,
1878 LBU16_MM = 1863,
1879 LBUX = 1864,
1880 LBUX_MM = 1865,
1881 LBU_MMR6 = 1866,
1882 LB_MM = 1867,
1883 LB_MMR6 = 1868,
1884 LBu = 1869,
1885 LBu64 = 1870,
1886 LBuE = 1871,
1887 LBuE_MM = 1872,
1888 LBu_MM = 1873,
1889 LD = 1874,
1890 LDC1 = 1875,
1891 LDC164 = 1876,
1892 LDC1_D64_MMR6 = 1877,
1893 LDC1_MM_D32 = 1878,
1894 LDC1_MM_D64 = 1879,
1895 LDC2 = 1880,
1896 LDC2_MMR6 = 1881,
1897 LDC2_R6 = 1882,
1898 LDC3 = 1883,
1899 LDI_B = 1884,
1900 LDI_D = 1885,
1901 LDI_H = 1886,
1902 LDI_W = 1887,
1903 LDL = 1888,
1904 LDPC = 1889,
1905 LDR = 1890,
1906 LDXC1 = 1891,
1907 LDXC164 = 1892,
1908 LD_B = 1893,
1909 LD_D = 1894,
1910 LD_H = 1895,
1911 LD_W = 1896,
1912 LEA_ADDiu = 1897,
1913 LEA_ADDiu64 = 1898,
1914 LEA_ADDiu_MM = 1899,
1915 LH = 1900,
1916 LH64 = 1901,
1917 LHE = 1902,
1918 LHE_MM = 1903,
1919 LHU16_MM = 1904,
1920 LHX = 1905,
1921 LHX_MM = 1906,
1922 LH_MM = 1907,
1923 LHu = 1908,
1924 LHu64 = 1909,
1925 LHuE = 1910,
1926 LHuE_MM = 1911,
1927 LHu_MM = 1912,
1928 LI16_MM = 1913,
1929 LI16_MMR6 = 1914,
1930 LL = 1915,
1931 LL64 = 1916,
1932 LL64_R6 = 1917,
1933 LLD = 1918,
1934 LLD_R6 = 1919,
1935 LLE = 1920,
1936 LLE_MM = 1921,
1937 LL_MM = 1922,
1938 LL_MMR6 = 1923,
1939 LL_R6 = 1924,
1940 LSA = 1925,
1941 LSA_MMR6 = 1926,
1942 LSA_R6 = 1927,
1943 LUI_MMR6 = 1928,
1944 LUXC1 = 1929,
1945 LUXC164 = 1930,
1946 LUXC1_MM = 1931,
1947 LUi = 1932,
1948 LUi64 = 1933,
1949 LUi_MM = 1934,
1950 LW = 1935,
1951 LW16_MM = 1936,
1952 LW64 = 1937,
1953 LWC1 = 1938,
1954 LWC1_MM = 1939,
1955 LWC2 = 1940,
1956 LWC2_MMR6 = 1941,
1957 LWC2_R6 = 1942,
1958 LWC3 = 1943,
1959 LWDSP = 1944,
1960 LWDSP_MM = 1945,
1961 LWE = 1946,
1962 LWE_MM = 1947,
1963 LWGP_MM = 1948,
1964 LWL = 1949,
1965 LWL64 = 1950,
1966 LWLE = 1951,
1967 LWLE_MM = 1952,
1968 LWL_MM = 1953,
1969 LWM16_MM = 1954,
1970 LWM16_MMR6 = 1955,
1971 LWM32_MM = 1956,
1972 LWPC = 1957,
1973 LWPC_MMR6 = 1958,
1974 LWP_MM = 1959,
1975 LWR = 1960,
1976 LWR64 = 1961,
1977 LWRE = 1962,
1978 LWRE_MM = 1963,
1979 LWR_MM = 1964,
1980 LWSP_MM = 1965,
1981 LWUPC = 1966,
1982 LWU_MM = 1967,
1983 LWX = 1968,
1984 LWXC1 = 1969,
1985 LWXC1_MM = 1970,
1986 LWXS_MM = 1971,
1987 LWX_MM = 1972,
1988 LW_MM = 1973,
1989 LW_MMR6 = 1974,
1990 LWu = 1975,
1991 LbRxRyOffMemX16 = 1976,
1992 LbuRxRyOffMemX16 = 1977,
1993 LhRxRyOffMemX16 = 1978,
1994 LhuRxRyOffMemX16 = 1979,
1995 LiRxImm16 = 1980,
1996 LiRxImmAlignX16 = 1981,
1997 LiRxImmX16 = 1982,
1998 LwRxPcTcp16 = 1983,
1999 LwRxPcTcpX16 = 1984,
2000 LwRxRyOffMemX16 = 1985,
2001 LwRxSpImmX16 = 1986,
2002 MADD = 1987,
2003 MADDF_D = 1988,
2004 MADDF_D_MMR6 = 1989,
2005 MADDF_S = 1990,
2006 MADDF_S_MMR6 = 1991,
2007 MADDR_Q_H = 1992,
2008 MADDR_Q_W = 1993,
2009 MADDU = 1994,
2010 MADDU_DSP = 1995,
2011 MADDU_DSP_MM = 1996,
2012 MADDU_MM = 1997,
2013 MADDV_B = 1998,
2014 MADDV_D = 1999,
2015 MADDV_H = 2000,
2016 MADDV_W = 2001,
2017 MADD_D32 = 2002,
2018 MADD_D32_MM = 2003,
2019 MADD_D64 = 2004,
2020 MADD_DSP = 2005,
2021 MADD_DSP_MM = 2006,
2022 MADD_MM = 2007,
2023 MADD_Q_H = 2008,
2024 MADD_Q_W = 2009,
2025 MADD_S = 2010,
2026 MADD_S_MM = 2011,
2027 MAQ_SA_W_PHL = 2012,
2028 MAQ_SA_W_PHL_MM = 2013,
2029 MAQ_SA_W_PHR = 2014,
2030 MAQ_SA_W_PHR_MM = 2015,
2031 MAQ_S_W_PHL = 2016,
2032 MAQ_S_W_PHL_MM = 2017,
2033 MAQ_S_W_PHR = 2018,
2034 MAQ_S_W_PHR_MM = 2019,
2035 MAXA_D = 2020,
2036 MAXA_D_MMR6 = 2021,
2037 MAXA_S = 2022,
2038 MAXA_S_MMR6 = 2023,
2039 MAXI_S_B = 2024,
2040 MAXI_S_D = 2025,
2041 MAXI_S_H = 2026,
2042 MAXI_S_W = 2027,
2043 MAXI_U_B = 2028,
2044 MAXI_U_D = 2029,
2045 MAXI_U_H = 2030,
2046 MAXI_U_W = 2031,
2047 MAX_A_B = 2032,
2048 MAX_A_D = 2033,
2049 MAX_A_H = 2034,
2050 MAX_A_W = 2035,
2051 MAX_D = 2036,
2052 MAX_D_MMR6 = 2037,
2053 MAX_S = 2038,
2054 MAX_S_B = 2039,
2055 MAX_S_D = 2040,
2056 MAX_S_H = 2041,
2057 MAX_S_MMR6 = 2042,
2058 MAX_S_W = 2043,
2059 MAX_U_B = 2044,
2060 MAX_U_D = 2045,
2061 MAX_U_H = 2046,
2062 MAX_U_W = 2047,
2063 MFC0 = 2048,
2064 MFC0_MMR6 = 2049,
2065 MFC1 = 2050,
2066 MFC1_D64 = 2051,
2067 MFC1_MM = 2052,
2068 MFC1_MMR6 = 2053,
2069 MFC2 = 2054,
2070 MFC2_MMR6 = 2055,
2071 MFGC0 = 2056,
2072 MFGC0_MM = 2057,
2073 MFHC0_MMR6 = 2058,
2074 MFHC1_D32 = 2059,
2075 MFHC1_D32_MM = 2060,
2076 MFHC1_D64 = 2061,
2077 MFHC1_D64_MM = 2062,
2078 MFHC2_MMR6 = 2063,
2079 MFHGC0 = 2064,
2080 MFHGC0_MM = 2065,
2081 MFHI = 2066,
2082 MFHI16_MM = 2067,
2083 MFHI64 = 2068,
2084 MFHI_DSP = 2069,
2085 MFHI_DSP_MM = 2070,
2086 MFHI_MM = 2071,
2087 MFLO = 2072,
2088 MFLO16_MM = 2073,
2089 MFLO64 = 2074,
2090 MFLO_DSP = 2075,
2091 MFLO_DSP_MM = 2076,
2092 MFLO_MM = 2077,
2093 MFTR = 2078,
2094 MINA_D = 2079,
2095 MINA_D_MMR6 = 2080,
2096 MINA_S = 2081,
2097 MINA_S_MMR6 = 2082,
2098 MINI_S_B = 2083,
2099 MINI_S_D = 2084,
2100 MINI_S_H = 2085,
2101 MINI_S_W = 2086,
2102 MINI_U_B = 2087,
2103 MINI_U_D = 2088,
2104 MINI_U_H = 2089,
2105 MINI_U_W = 2090,
2106 MIN_A_B = 2091,
2107 MIN_A_D = 2092,
2108 MIN_A_H = 2093,
2109 MIN_A_W = 2094,
2110 MIN_D = 2095,
2111 MIN_D_MMR6 = 2096,
2112 MIN_S = 2097,
2113 MIN_S_B = 2098,
2114 MIN_S_D = 2099,
2115 MIN_S_H = 2100,
2116 MIN_S_MMR6 = 2101,
2117 MIN_S_W = 2102,
2118 MIN_U_B = 2103,
2119 MIN_U_D = 2104,
2120 MIN_U_H = 2105,
2121 MIN_U_W = 2106,
2122 MOD = 2107,
2123 MODSUB = 2108,
2124 MODSUB_MM = 2109,
2125 MODU = 2110,
2126 MODU_MMR6 = 2111,
2127 MOD_MMR6 = 2112,
2128 MOD_S_B = 2113,
2129 MOD_S_D = 2114,
2130 MOD_S_H = 2115,
2131 MOD_S_W = 2116,
2132 MOD_U_B = 2117,
2133 MOD_U_D = 2118,
2134 MOD_U_H = 2119,
2135 MOD_U_W = 2120,
2136 MOVE16_MM = 2121,
2137 MOVE16_MMR6 = 2122,
2138 MOVEP_MM = 2123,
2139 MOVEP_MMR6 = 2124,
2140 MOVE_V = 2125,
2141 MOVF_D32 = 2126,
2142 MOVF_D32_MM = 2127,
2143 MOVF_D64 = 2128,
2144 MOVF_I = 2129,
2145 MOVF_I64 = 2130,
2146 MOVF_I_MM = 2131,
2147 MOVF_S = 2132,
2148 MOVF_S_MM = 2133,
2149 MOVN_I64_D64 = 2134,
2150 MOVN_I64_I = 2135,
2151 MOVN_I64_I64 = 2136,
2152 MOVN_I64_S = 2137,
2153 MOVN_I_D32 = 2138,
2154 MOVN_I_D32_MM = 2139,
2155 MOVN_I_D64 = 2140,
2156 MOVN_I_I = 2141,
2157 MOVN_I_I64 = 2142,
2158 MOVN_I_MM = 2143,
2159 MOVN_I_S = 2144,
2160 MOVN_I_S_MM = 2145,
2161 MOVT_D32 = 2146,
2162 MOVT_D32_MM = 2147,
2163 MOVT_D64 = 2148,
2164 MOVT_I = 2149,
2165 MOVT_I64 = 2150,
2166 MOVT_I_MM = 2151,
2167 MOVT_S = 2152,
2168 MOVT_S_MM = 2153,
2169 MOVZ_I64_D64 = 2154,
2170 MOVZ_I64_I = 2155,
2171 MOVZ_I64_I64 = 2156,
2172 MOVZ_I64_S = 2157,
2173 MOVZ_I_D32 = 2158,
2174 MOVZ_I_D32_MM = 2159,
2175 MOVZ_I_D64 = 2160,
2176 MOVZ_I_I = 2161,
2177 MOVZ_I_I64 = 2162,
2178 MOVZ_I_MM = 2163,
2179 MOVZ_I_S = 2164,
2180 MOVZ_I_S_MM = 2165,
2181 MSUB = 2166,
2182 MSUBF_D = 2167,
2183 MSUBF_D_MMR6 = 2168,
2184 MSUBF_S = 2169,
2185 MSUBF_S_MMR6 = 2170,
2186 MSUBR_Q_H = 2171,
2187 MSUBR_Q_W = 2172,
2188 MSUBU = 2173,
2189 MSUBU_DSP = 2174,
2190 MSUBU_DSP_MM = 2175,
2191 MSUBU_MM = 2176,
2192 MSUBV_B = 2177,
2193 MSUBV_D = 2178,
2194 MSUBV_H = 2179,
2195 MSUBV_W = 2180,
2196 MSUB_D32 = 2181,
2197 MSUB_D32_MM = 2182,
2198 MSUB_D64 = 2183,
2199 MSUB_DSP = 2184,
2200 MSUB_DSP_MM = 2185,
2201 MSUB_MM = 2186,
2202 MSUB_Q_H = 2187,
2203 MSUB_Q_W = 2188,
2204 MSUB_S = 2189,
2205 MSUB_S_MM = 2190,
2206 MTC0 = 2191,
2207 MTC0_MMR6 = 2192,
2208 MTC1 = 2193,
2209 MTC1_D64 = 2194,
2210 MTC1_D64_MM = 2195,
2211 MTC1_MM = 2196,
2212 MTC1_MMR6 = 2197,
2213 MTC2 = 2198,
2214 MTC2_MMR6 = 2199,
2215 MTGC0 = 2200,
2216 MTGC0_MM = 2201,
2217 MTHC0_MMR6 = 2202,
2218 MTHC1_D32 = 2203,
2219 MTHC1_D32_MM = 2204,
2220 MTHC1_D64 = 2205,
2221 MTHC1_D64_MM = 2206,
2222 MTHC2_MMR6 = 2207,
2223 MTHGC0 = 2208,
2224 MTHGC0_MM = 2209,
2225 MTHI = 2210,
2226 MTHI64 = 2211,
2227 MTHI_DSP = 2212,
2228 MTHI_DSP_MM = 2213,
2229 MTHI_MM = 2214,
2230 MTHLIP = 2215,
2231 MTHLIP_MM = 2216,
2232 MTLO = 2217,
2233 MTLO64 = 2218,
2234 MTLO_DSP = 2219,
2235 MTLO_DSP_MM = 2220,
2236 MTLO_MM = 2221,
2237 MTM0 = 2222,
2238 MTM1 = 2223,
2239 MTM2 = 2224,
2240 MTP0 = 2225,
2241 MTP1 = 2226,
2242 MTP2 = 2227,
2243 MTTR = 2228,
2244 MUH = 2229,
2245 MUHU = 2230,
2246 MUHU_MMR6 = 2231,
2247 MUH_MMR6 = 2232,
2248 MUL = 2233,
2249 MULEQ_S_W_PHL = 2234,
2250 MULEQ_S_W_PHL_MM = 2235,
2251 MULEQ_S_W_PHR = 2236,
2252 MULEQ_S_W_PHR_MM = 2237,
2253 MULEU_S_PH_QBL = 2238,
2254 MULEU_S_PH_QBL_MM = 2239,
2255 MULEU_S_PH_QBR = 2240,
2256 MULEU_S_PH_QBR_MM = 2241,
2257 MULQ_RS_PH = 2242,
2258 MULQ_RS_PH_MM = 2243,
2259 MULQ_RS_W = 2244,
2260 MULQ_RS_W_MMR2 = 2245,
2261 MULQ_S_PH = 2246,
2262 MULQ_S_PH_MMR2 = 2247,
2263 MULQ_S_W = 2248,
2264 MULQ_S_W_MMR2 = 2249,
2265 MULR_PS64 = 2250,
2266 MULR_Q_H = 2251,
2267 MULR_Q_W = 2252,
2268 MULSAQ_S_W_PH = 2253,
2269 MULSAQ_S_W_PH_MM = 2254,
2270 MULSA_W_PH = 2255,
2271 MULSA_W_PH_MMR2 = 2256,
2272 MULT = 2257,
2273 MULTU_DSP = 2258,
2274 MULTU_DSP_MM = 2259,
2275 MULT_DSP = 2260,
2276 MULT_DSP_MM = 2261,
2277 MULT_MM = 2262,
2278 MULTu = 2263,
2279 MULTu_MM = 2264,
2280 MULU = 2265,
2281 MULU_MMR6 = 2266,
2282 MULV_B = 2267,
2283 MULV_D = 2268,
2284 MULV_H = 2269,
2285 MULV_W = 2270,
2286 MUL_MM = 2271,
2287 MUL_MMR6 = 2272,
2288 MUL_PH = 2273,
2289 MUL_PH_MMR2 = 2274,
2290 MUL_Q_H = 2275,
2291 MUL_Q_W = 2276,
2292 MUL_R6 = 2277,
2293 MUL_S_PH = 2278,
2294 MUL_S_PH_MMR2 = 2279,
2295 Mfhi16 = 2280,
2296 Mflo16 = 2281,
2297 Move32R16 = 2282,
2298 MoveR3216 = 2283,
2299 NAL = 2284,
2300 NLOC_B = 2285,
2301 NLOC_D = 2286,
2302 NLOC_H = 2287,
2303 NLOC_W = 2288,
2304 NLZC_B = 2289,
2305 NLZC_D = 2290,
2306 NLZC_H = 2291,
2307 NLZC_W = 2292,
2308 NMADD_D32 = 2293,
2309 NMADD_D32_MM = 2294,
2310 NMADD_D64 = 2295,
2311 NMADD_S = 2296,
2312 NMADD_S_MM = 2297,
2313 NMSUB_D32 = 2298,
2314 NMSUB_D32_MM = 2299,
2315 NMSUB_D64 = 2300,
2316 NMSUB_S = 2301,
2317 NMSUB_S_MM = 2302,
2318 NOR = 2303,
2319 NOR64 = 2304,
2320 NORI_B = 2305,
2321 NOR_MM = 2306,
2322 NOR_MMR6 = 2307,
2323 NOR_V = 2308,
2324 NOT16_MM = 2309,
2325 NOT16_MMR6 = 2310,
2326 NegRxRy16 = 2311,
2327 NotRxRy16 = 2312,
2328 OR = 2313,
2329 OR16_MM = 2314,
2330 OR16_MMR6 = 2315,
2331 OR64 = 2316,
2332 ORI_B = 2317,
2333 ORI_MMR6 = 2318,
2334 OR_MM = 2319,
2335 OR_MMR6 = 2320,
2336 OR_V = 2321,
2337 ORi = 2322,
2338 ORi64 = 2323,
2339 ORi_MM = 2324,
2340 OrRxRxRy16 = 2325,
2341 PACKRL_PH = 2326,
2342 PACKRL_PH_MM = 2327,
2343 PAUSE = 2328,
2344 PAUSE_MM = 2329,
2345 PAUSE_MMR6 = 2330,
2346 PCKEV_B = 2331,
2347 PCKEV_D = 2332,
2348 PCKEV_H = 2333,
2349 PCKEV_W = 2334,
2350 PCKOD_B = 2335,
2351 PCKOD_D = 2336,
2352 PCKOD_H = 2337,
2353 PCKOD_W = 2338,
2354 PCNT_B = 2339,
2355 PCNT_D = 2340,
2356 PCNT_H = 2341,
2357 PCNT_W = 2342,
2358 PICK_PH = 2343,
2359 PICK_PH_MM = 2344,
2360 PICK_QB = 2345,
2361 PICK_QB_MM = 2346,
2362 PLL_PS64 = 2347,
2363 PLU_PS64 = 2348,
2364 POP = 2349,
2365 PRECEQU_PH_QBL = 2350,
2366 PRECEQU_PH_QBLA = 2351,
2367 PRECEQU_PH_QBLA_MM = 2352,
2368 PRECEQU_PH_QBL_MM = 2353,
2369 PRECEQU_PH_QBR = 2354,
2370 PRECEQU_PH_QBRA = 2355,
2371 PRECEQU_PH_QBRA_MM = 2356,
2372 PRECEQU_PH_QBR_MM = 2357,
2373 PRECEQ_W_PHL = 2358,
2374 PRECEQ_W_PHL_MM = 2359,
2375 PRECEQ_W_PHR = 2360,
2376 PRECEQ_W_PHR_MM = 2361,
2377 PRECEU_PH_QBL = 2362,
2378 PRECEU_PH_QBLA = 2363,
2379 PRECEU_PH_QBLA_MM = 2364,
2380 PRECEU_PH_QBL_MM = 2365,
2381 PRECEU_PH_QBR = 2366,
2382 PRECEU_PH_QBRA = 2367,
2383 PRECEU_PH_QBRA_MM = 2368,
2384 PRECEU_PH_QBR_MM = 2369,
2385 PRECRQU_S_QB_PH = 2370,
2386 PRECRQU_S_QB_PH_MM = 2371,
2387 PRECRQ_PH_W = 2372,
2388 PRECRQ_PH_W_MM = 2373,
2389 PRECRQ_QB_PH = 2374,
2390 PRECRQ_QB_PH_MM = 2375,
2391 PRECRQ_RS_PH_W = 2376,
2392 PRECRQ_RS_PH_W_MM = 2377,
2393 PRECR_QB_PH = 2378,
2394 PRECR_QB_PH_MMR2 = 2379,
2395 PRECR_SRA_PH_W = 2380,
2396 PRECR_SRA_PH_W_MMR2 = 2381,
2397 PRECR_SRA_R_PH_W = 2382,
2398 PRECR_SRA_R_PH_W_MMR2 = 2383,
2399 PREF = 2384,
2400 PREFE = 2385,
2401 PREFE_MM = 2386,
2402 PREFX_MM = 2387,
2403 PREF_MM = 2388,
2404 PREF_MMR6 = 2389,
2405 PREF_R6 = 2390,
2406 PREPEND = 2391,
2407 PREPEND_MMR2 = 2392,
2408 PUL_PS64 = 2393,
2409 PUU_PS64 = 2394,
2410 RADDU_W_QB = 2395,
2411 RADDU_W_QB_MM = 2396,
2412 RDDSP = 2397,
2413 RDDSP_MM = 2398,
2414 RDHWR = 2399,
2415 RDHWR64 = 2400,
2416 RDHWR_MM = 2401,
2417 RDHWR_MMR6 = 2402,
2418 RDPGPR_MMR6 = 2403,
2419 RECIP_D32 = 2404,
2420 RECIP_D32_MM = 2405,
2421 RECIP_D64 = 2406,
2422 RECIP_D64_MM = 2407,
2423 RECIP_S = 2408,
2424 RECIP_S_MM = 2409,
2425 REPLV_PH = 2410,
2426 REPLV_PH_MM = 2411,
2427 REPLV_QB = 2412,
2428 REPLV_QB_MM = 2413,
2429 REPL_PH = 2414,
2430 REPL_PH_MM = 2415,
2431 REPL_QB = 2416,
2432 REPL_QB_MM = 2417,
2433 RINT_D = 2418,
2434 RINT_D_MMR6 = 2419,
2435 RINT_S = 2420,
2436 RINT_S_MMR6 = 2421,
2437 ROTR = 2422,
2438 ROTRV = 2423,
2439 ROTRV_MM = 2424,
2440 ROTR_MM = 2425,
2441 ROUND_L_D64 = 2426,
2442 ROUND_L_D_MMR6 = 2427,
2443 ROUND_L_S = 2428,
2444 ROUND_L_S_MMR6 = 2429,
2445 ROUND_W_D32 = 2430,
2446 ROUND_W_D64 = 2431,
2447 ROUND_W_D_MMR6 = 2432,
2448 ROUND_W_MM = 2433,
2449 ROUND_W_S = 2434,
2450 ROUND_W_S_MM = 2435,
2451 ROUND_W_S_MMR6 = 2436,
2452 RSQRT_D32 = 2437,
2453 RSQRT_D32_MM = 2438,
2454 RSQRT_D64 = 2439,
2455 RSQRT_D64_MM = 2440,
2456 RSQRT_S = 2441,
2457 RSQRT_S_MM = 2442,
2458 Restore16 = 2443,
2459 RestoreX16 = 2444,
2460 SAA = 2445,
2461 SAAD = 2446,
2462 SAT_S_B = 2447,
2463 SAT_S_D = 2448,
2464 SAT_S_H = 2449,
2465 SAT_S_W = 2450,
2466 SAT_U_B = 2451,
2467 SAT_U_D = 2452,
2468 SAT_U_H = 2453,
2469 SAT_U_W = 2454,
2470 SB = 2455,
2471 SB16_MM = 2456,
2472 SB16_MMR6 = 2457,
2473 SB64 = 2458,
2474 SBE = 2459,
2475 SBE_MM = 2460,
2476 SB_MM = 2461,
2477 SB_MMR6 = 2462,
2478 SC = 2463,
2479 SC64 = 2464,
2480 SC64_R6 = 2465,
2481 SCD = 2466,
2482 SCD_R6 = 2467,
2483 SCE = 2468,
2484 SCE_MM = 2469,
2485 SC_MM = 2470,
2486 SC_MMR6 = 2471,
2487 SC_R6 = 2472,
2488 SD = 2473,
2489 SDBBP = 2474,
2490 SDBBP16_MM = 2475,
2491 SDBBP16_MMR6 = 2476,
2492 SDBBP_MM = 2477,
2493 SDBBP_MMR6 = 2478,
2494 SDBBP_R6 = 2479,
2495 SDC1 = 2480,
2496 SDC164 = 2481,
2497 SDC1_D64_MMR6 = 2482,
2498 SDC1_MM_D32 = 2483,
2499 SDC1_MM_D64 = 2484,
2500 SDC2 = 2485,
2501 SDC2_MMR6 = 2486,
2502 SDC2_R6 = 2487,
2503 SDC3 = 2488,
2504 SDIV = 2489,
2505 SDIV_MM = 2490,
2506 SDL = 2491,
2507 SDR = 2492,
2508 SDXC1 = 2493,
2509 SDXC164 = 2494,
2510 SEB = 2495,
2511 SEB64 = 2496,
2512 SEB_MM = 2497,
2513 SEH = 2498,
2514 SEH64 = 2499,
2515 SEH_MM = 2500,
2516 SELEQZ = 2501,
2517 SELEQZ64 = 2502,
2518 SELEQZ_D = 2503,
2519 SELEQZ_D_MMR6 = 2504,
2520 SELEQZ_MMR6 = 2505,
2521 SELEQZ_S = 2506,
2522 SELEQZ_S_MMR6 = 2507,
2523 SELNEZ = 2508,
2524 SELNEZ64 = 2509,
2525 SELNEZ_D = 2510,
2526 SELNEZ_D_MMR6 = 2511,
2527 SELNEZ_MMR6 = 2512,
2528 SELNEZ_S = 2513,
2529 SELNEZ_S_MMR6 = 2514,
2530 SEL_D = 2515,
2531 SEL_D_MMR6 = 2516,
2532 SEL_S = 2517,
2533 SEL_S_MMR6 = 2518,
2534 SEQ = 2519,
2535 SEQi = 2520,
2536 SH = 2521,
2537 SH16_MM = 2522,
2538 SH16_MMR6 = 2523,
2539 SH64 = 2524,
2540 SHE = 2525,
2541 SHE_MM = 2526,
2542 SHF_B = 2527,
2543 SHF_H = 2528,
2544 SHF_W = 2529,
2545 SHILO = 2530,
2546 SHILOV = 2531,
2547 SHILOV_MM = 2532,
2548 SHILO_MM = 2533,
2549 SHLLV_PH = 2534,
2550 SHLLV_PH_MM = 2535,
2551 SHLLV_QB = 2536,
2552 SHLLV_QB_MM = 2537,
2553 SHLLV_S_PH = 2538,
2554 SHLLV_S_PH_MM = 2539,
2555 SHLLV_S_W = 2540,
2556 SHLLV_S_W_MM = 2541,
2557 SHLL_PH = 2542,
2558 SHLL_PH_MM = 2543,
2559 SHLL_QB = 2544,
2560 SHLL_QB_MM = 2545,
2561 SHLL_S_PH = 2546,
2562 SHLL_S_PH_MM = 2547,
2563 SHLL_S_W = 2548,
2564 SHLL_S_W_MM = 2549,
2565 SHRAV_PH = 2550,
2566 SHRAV_PH_MM = 2551,
2567 SHRAV_QB = 2552,
2568 SHRAV_QB_MMR2 = 2553,
2569 SHRAV_R_PH = 2554,
2570 SHRAV_R_PH_MM = 2555,
2571 SHRAV_R_QB = 2556,
2572 SHRAV_R_QB_MMR2 = 2557,
2573 SHRAV_R_W = 2558,
2574 SHRAV_R_W_MM = 2559,
2575 SHRA_PH = 2560,
2576 SHRA_PH_MM = 2561,
2577 SHRA_QB = 2562,
2578 SHRA_QB_MMR2 = 2563,
2579 SHRA_R_PH = 2564,
2580 SHRA_R_PH_MM = 2565,
2581 SHRA_R_QB = 2566,
2582 SHRA_R_QB_MMR2 = 2567,
2583 SHRA_R_W = 2568,
2584 SHRA_R_W_MM = 2569,
2585 SHRLV_PH = 2570,
2586 SHRLV_PH_MMR2 = 2571,
2587 SHRLV_QB = 2572,
2588 SHRLV_QB_MM = 2573,
2589 SHRL_PH = 2574,
2590 SHRL_PH_MMR2 = 2575,
2591 SHRL_QB = 2576,
2592 SHRL_QB_MM = 2577,
2593 SH_MM = 2578,
2594 SH_MMR6 = 2579,
2595 SIGRIE = 2580,
2596 SIGRIE_MMR6 = 2581,
2597 SLDI_B = 2582,
2598 SLDI_D = 2583,
2599 SLDI_H = 2584,
2600 SLDI_W = 2585,
2601 SLD_B = 2586,
2602 SLD_D = 2587,
2603 SLD_H = 2588,
2604 SLD_W = 2589,
2605 SLL = 2590,
2606 SLL16_MM = 2591,
2607 SLL16_MMR6 = 2592,
2608 SLL64_32 = 2593,
2609 SLL64_64 = 2594,
2610 SLLI_B = 2595,
2611 SLLI_D = 2596,
2612 SLLI_H = 2597,
2613 SLLI_W = 2598,
2614 SLLV = 2599,
2615 SLLV_MM = 2600,
2616 SLL_B = 2601,
2617 SLL_D = 2602,
2618 SLL_H = 2603,
2619 SLL_MM = 2604,
2620 SLL_MMR6 = 2605,
2621 SLL_W = 2606,
2622 SLT = 2607,
2623 SLT64 = 2608,
2624 SLT_MM = 2609,
2625 SLTi = 2610,
2626 SLTi64 = 2611,
2627 SLTi_MM = 2612,
2628 SLTiu = 2613,
2629 SLTiu64 = 2614,
2630 SLTiu_MM = 2615,
2631 SLTu = 2616,
2632 SLTu64 = 2617,
2633 SLTu_MM = 2618,
2634 SNE = 2619,
2635 SNEi = 2620,
2636 SPLATI_B = 2621,
2637 SPLATI_D = 2622,
2638 SPLATI_H = 2623,
2639 SPLATI_W = 2624,
2640 SPLAT_B = 2625,
2641 SPLAT_D = 2626,
2642 SPLAT_H = 2627,
2643 SPLAT_W = 2628,
2644 SRA = 2629,
2645 SRAI_B = 2630,
2646 SRAI_D = 2631,
2647 SRAI_H = 2632,
2648 SRAI_W = 2633,
2649 SRARI_B = 2634,
2650 SRARI_D = 2635,
2651 SRARI_H = 2636,
2652 SRARI_W = 2637,
2653 SRAR_B = 2638,
2654 SRAR_D = 2639,
2655 SRAR_H = 2640,
2656 SRAR_W = 2641,
2657 SRAV = 2642,
2658 SRAV_MM = 2643,
2659 SRA_B = 2644,
2660 SRA_D = 2645,
2661 SRA_H = 2646,
2662 SRA_MM = 2647,
2663 SRA_W = 2648,
2664 SRL = 2649,
2665 SRL16_MM = 2650,
2666 SRL16_MMR6 = 2651,
2667 SRLI_B = 2652,
2668 SRLI_D = 2653,
2669 SRLI_H = 2654,
2670 SRLI_W = 2655,
2671 SRLRI_B = 2656,
2672 SRLRI_D = 2657,
2673 SRLRI_H = 2658,
2674 SRLRI_W = 2659,
2675 SRLR_B = 2660,
2676 SRLR_D = 2661,
2677 SRLR_H = 2662,
2678 SRLR_W = 2663,
2679 SRLV = 2664,
2680 SRLV_MM = 2665,
2681 SRL_B = 2666,
2682 SRL_D = 2667,
2683 SRL_H = 2668,
2684 SRL_MM = 2669,
2685 SRL_W = 2670,
2686 SSNOP = 2671,
2687 SSNOP_MM = 2672,
2688 SSNOP_MMR6 = 2673,
2689 ST_B = 2674,
2690 ST_D = 2675,
2691 ST_H = 2676,
2692 ST_W = 2677,
2693 SUB = 2678,
2694 SUBQH_PH = 2679,
2695 SUBQH_PH_MMR2 = 2680,
2696 SUBQH_R_PH = 2681,
2697 SUBQH_R_PH_MMR2 = 2682,
2698 SUBQH_R_W = 2683,
2699 SUBQH_R_W_MMR2 = 2684,
2700 SUBQH_W = 2685,
2701 SUBQH_W_MMR2 = 2686,
2702 SUBQ_PH = 2687,
2703 SUBQ_PH_MM = 2688,
2704 SUBQ_S_PH = 2689,
2705 SUBQ_S_PH_MM = 2690,
2706 SUBQ_S_W = 2691,
2707 SUBQ_S_W_MM = 2692,
2708 SUBSUS_U_B = 2693,
2709 SUBSUS_U_D = 2694,
2710 SUBSUS_U_H = 2695,
2711 SUBSUS_U_W = 2696,
2712 SUBSUU_S_B = 2697,
2713 SUBSUU_S_D = 2698,
2714 SUBSUU_S_H = 2699,
2715 SUBSUU_S_W = 2700,
2716 SUBS_S_B = 2701,
2717 SUBS_S_D = 2702,
2718 SUBS_S_H = 2703,
2719 SUBS_S_W = 2704,
2720 SUBS_U_B = 2705,
2721 SUBS_U_D = 2706,
2722 SUBS_U_H = 2707,
2723 SUBS_U_W = 2708,
2724 SUBU16_MM = 2709,
2725 SUBU16_MMR6 = 2710,
2726 SUBUH_QB = 2711,
2727 SUBUH_QB_MMR2 = 2712,
2728 SUBUH_R_QB = 2713,
2729 SUBUH_R_QB_MMR2 = 2714,
2730 SUBU_MMR6 = 2715,
2731 SUBU_PH = 2716,
2732 SUBU_PH_MMR2 = 2717,
2733 SUBU_QB = 2718,
2734 SUBU_QB_MM = 2719,
2735 SUBU_S_PH = 2720,
2736 SUBU_S_PH_MMR2 = 2721,
2737 SUBU_S_QB = 2722,
2738 SUBU_S_QB_MM = 2723,
2739 SUBVI_B = 2724,
2740 SUBVI_D = 2725,
2741 SUBVI_H = 2726,
2742 SUBVI_W = 2727,
2743 SUBV_B = 2728,
2744 SUBV_D = 2729,
2745 SUBV_H = 2730,
2746 SUBV_W = 2731,
2747 SUB_MM = 2732,
2748 SUB_MMR6 = 2733,
2749 SUBu = 2734,
2750 SUBu_MM = 2735,
2751 SUXC1 = 2736,
2752 SUXC164 = 2737,
2753 SUXC1_MM = 2738,
2754 SW = 2739,
2755 SW16_MM = 2740,
2756 SW16_MMR6 = 2741,
2757 SW64 = 2742,
2758 SWC1 = 2743,
2759 SWC1_MM = 2744,
2760 SWC2 = 2745,
2761 SWC2_MMR6 = 2746,
2762 SWC2_R6 = 2747,
2763 SWC3 = 2748,
2764 SWDSP = 2749,
2765 SWDSP_MM = 2750,
2766 SWE = 2751,
2767 SWE_MM = 2752,
2768 SWL = 2753,
2769 SWL64 = 2754,
2770 SWLE = 2755,
2771 SWLE_MM = 2756,
2772 SWL_MM = 2757,
2773 SWM16_MM = 2758,
2774 SWM16_MMR6 = 2759,
2775 SWM32_MM = 2760,
2776 SWP_MM = 2761,
2777 SWR = 2762,
2778 SWR64 = 2763,
2779 SWRE = 2764,
2780 SWRE_MM = 2765,
2781 SWR_MM = 2766,
2782 SWSP_MM = 2767,
2783 SWSP_MMR6 = 2768,
2784 SWXC1 = 2769,
2785 SWXC1_MM = 2770,
2786 SW_MM = 2771,
2787 SW_MMR6 = 2772,
2788 SYNC = 2773,
2789 SYNCI = 2774,
2790 SYNCI_MM = 2775,
2791 SYNCI_MMR6 = 2776,
2792 SYNC_MM = 2777,
2793 SYNC_MMR6 = 2778,
2794 SYSCALL = 2779,
2795 SYSCALL_MM = 2780,
2796 Save16 = 2781,
2797 SaveX16 = 2782,
2798 SbRxRyOffMemX16 = 2783,
2799 SebRx16 = 2784,
2800 SehRx16 = 2785,
2801 ShRxRyOffMemX16 = 2786,
2802 SllX16 = 2787,
2803 SllvRxRy16 = 2788,
2804 SltRxRy16 = 2789,
2805 SltiRxImm16 = 2790,
2806 SltiRxImmX16 = 2791,
2807 SltiuRxImm16 = 2792,
2808 SltiuRxImmX16 = 2793,
2809 SltuRxRy16 = 2794,
2810 SraX16 = 2795,
2811 SravRxRy16 = 2796,
2812 SrlX16 = 2797,
2813 SrlvRxRy16 = 2798,
2814 SubuRxRyRz16 = 2799,
2815 SwRxRyOffMemX16 = 2800,
2816 SwRxSpImmX16 = 2801,
2817 TEQ = 2802,
2818 TEQI = 2803,
2819 TEQI_MM = 2804,
2820 TEQ_MM = 2805,
2821 TGE = 2806,
2822 TGEI = 2807,
2823 TGEIU = 2808,
2824 TGEIU_MM = 2809,
2825 TGEI_MM = 2810,
2826 TGEU = 2811,
2827 TGEU_MM = 2812,
2828 TGE_MM = 2813,
2829 TLBGINV = 2814,
2830 TLBGINVF = 2815,
2831 TLBGINVF_MM = 2816,
2832 TLBGINV_MM = 2817,
2833 TLBGP = 2818,
2834 TLBGP_MM = 2819,
2835 TLBGR = 2820,
2836 TLBGR_MM = 2821,
2837 TLBGWI = 2822,
2838 TLBGWI_MM = 2823,
2839 TLBGWR = 2824,
2840 TLBGWR_MM = 2825,
2841 TLBINV = 2826,
2842 TLBINVF = 2827,
2843 TLBINVF_MMR6 = 2828,
2844 TLBINV_MMR6 = 2829,
2845 TLBP = 2830,
2846 TLBP_MM = 2831,
2847 TLBR = 2832,
2848 TLBR_MM = 2833,
2849 TLBWI = 2834,
2850 TLBWI_MM = 2835,
2851 TLBWR = 2836,
2852 TLBWR_MM = 2837,
2853 TLT = 2838,
2854 TLTI = 2839,
2855 TLTIU_MM = 2840,
2856 TLTI_MM = 2841,
2857 TLTU = 2842,
2858 TLTU_MM = 2843,
2859 TLT_MM = 2844,
2860 TNE = 2845,
2861 TNEI = 2846,
2862 TNEI_MM = 2847,
2863 TNE_MM = 2848,
2864 TRUNC_L_D64 = 2849,
2865 TRUNC_L_D_MMR6 = 2850,
2866 TRUNC_L_S = 2851,
2867 TRUNC_L_S_MMR6 = 2852,
2868 TRUNC_W_D32 = 2853,
2869 TRUNC_W_D64 = 2854,
2870 TRUNC_W_D_MMR6 = 2855,
2871 TRUNC_W_MM = 2856,
2872 TRUNC_W_S = 2857,
2873 TRUNC_W_S_MM = 2858,
2874 TRUNC_W_S_MMR6 = 2859,
2875 TTLTIU = 2860,
2876 UDIV = 2861,
2877 UDIV_MM = 2862,
2878 V3MULU = 2863,
2879 VMM0 = 2864,
2880 VMULU = 2865,
2881 VSHF_B = 2866,
2882 VSHF_D = 2867,
2883 VSHF_H = 2868,
2884 VSHF_W = 2869,
2885 WAIT = 2870,
2886 WAIT_MM = 2871,
2887 WAIT_MMR6 = 2872,
2888 WRDSP = 2873,
2889 WRDSP_MM = 2874,
2890 WRPGPR_MMR6 = 2875,
2891 WSBH = 2876,
2892 WSBH_MM = 2877,
2893 WSBH_MMR6 = 2878,
2894 XOR = 2879,
2895 XOR16_MM = 2880,
2896 XOR16_MMR6 = 2881,
2897 XOR64 = 2882,
2898 XORI_B = 2883,
2899 XORI_MMR6 = 2884,
2900 XOR_MM = 2885,
2901 XOR_MMR6 = 2886,
2902 XOR_V = 2887,
2903 XORi = 2888,
2904 XORi64 = 2889,
2905 XORi_MM = 2890,
2906 XorRxRxRy16 = 2891,
2907 YIELD = 2892,
2908 INSTRUCTION_LIST_END = 2893
2909 };
2910
2911} // end namespace Mips
2912} // end namespace llvm
2913#endif // GET_INSTRINFO_ENUM
2914
2915#ifdef GET_INSTRINFO_SCHED_ENUM
2916#undef GET_INSTRINFO_SCHED_ENUM
2917namespace llvm {
2918
2919namespace Mips {
2920namespace Sched {
2921 enum {
2922 NoInstrModel = 0,
2923 IIPseudo = 1,
2924 II_B = 2,
2925 II_BCCZAL = 3,
2926 II_MTC1 = 4,
2927 II_MFC1 = 5,
2928 II_JALR = 6,
2929 II_JAL = 7,
2930 II_CVT = 8,
2931 II_DMULT = 9,
2932 II_DMULTU = 10,
2933 II_DDIV = 11,
2934 II_DDIVU = 12,
2935 II_IndirectBranchPseudo = 13,
2936 II_MADD = 14,
2937 II_MADDU = 15,
2938 II_MFHI_MFLO = 16,
2939 II_MSUB = 17,
2940 II_MSUBU = 18,
2941 II_MTHI_MTLO = 19,
2942 II_MULT = 20,
2943 II_MULTU = 21,
2944 II_ReturnPseudo = 22,
2945 II_DIV = 23,
2946 II_DIVU = 24,
2947 II_J = 25,
2948 II_JR = 26,
2949 II_TRAP = 27,
2950 II_ADD = 28,
2951 II_ADDIUPC = 29,
2952 II_ADDIU = 30,
2953 II_ADDR_PS = 31,
2954 II_ADDU = 32,
2955 II_ADDI = 33,
2956 II_ALIGN = 34,
2957 II_ALUIPC = 35,
2958 II_AND = 36,
2959 II_ANDI = 37,
2960 II_AUI = 38,
2961 II_AUIPC = 39,
2962 IIM16Alu = 40,
2963 II_BADDU = 41,
2964 II_BC = 42,
2965 II_BALC = 43,
2966 II_BBIT = 44,
2967 II_BC1CCZ = 45,
2968 II_BC1F = 46,
2969 II_BC1FL = 47,
2970 II_BC1T = 48,
2971 II_BC1TL = 49,
2972 II_BC2CCZ = 50,
2973 II_BCC = 51,
2974 II_BCCC = 52,
2975 II_BCCZ = 53,
2976 II_BCCZC = 54,
2977 II_BCCZALS = 55,
2978 II_BITSWAP = 56,
2979 II_BREAK = 57,
2980 II_CACHE = 58,
2981 II_CACHEE = 59,
2982 II_CEIL = 60,
2983 II_CFC1 = 61,
2984 II_CFC2 = 62,
2985 II_INS = 63,
2986 II_CLASS_D = 64,
2987 II_CLASS_S = 65,
2988 II_CLO = 66,
2989 II_CLZ = 67,
2990 II_CMP_CC_D = 68,
2991 II_CMP_CC_S = 69,
2992 II_CRC32B = 70,
2993 II_CRC32CB = 71,
2994 II_CRC32CD = 72,
2995 II_CRC32CH = 73,
2996 II_CRC32CW = 74,
2997 II_CRC32D = 75,
2998 II_CRC32H = 76,
2999 II_CRC32W = 77,
3000 II_CTC1 = 78,
3001 II_CTC2 = 79,
3002 II_C_CC_D = 80,
3003 II_C_CC_S = 81,
3004 II_DADD = 82,
3005 II_DADDI = 83,
3006 II_DADDIU = 84,
3007 II_DADDU = 85,
3008 II_DAHI = 86,
3009 II_DALIGN = 87,
3010 II_DATI = 88,
3011 II_DAUI = 89,
3012 II_DBITSWAP = 90,
3013 II_DCLO = 91,
3014 II_DCLZ = 92,
3015 II_DERET = 93,
3016 II_EXT = 94,
3017 II_DI = 95,
3018 II_DLSA = 96,
3019 II_DMFC0 = 97,
3020 II_DMFC1 = 98,
3021 II_DMFC2 = 99,
3022 II_DMFGC0 = 100,
3023 II_DMOD = 101,
3024 II_DMODU = 102,
3025 II_DMT = 103,
3026 II_DMTC0 = 104,
3027 II_DMTC1 = 105,
3028 II_DMTC2 = 106,
3029 II_DMTGC0 = 107,
3030 II_DMUH = 108,
3031 II_DMUHU = 109,
3032 II_DMUL = 110,
3033 II_POP = 111,
3034 II_DROTR = 112,
3035 II_DROTR32 = 113,
3036 II_DROTRV = 114,
3037 II_DSBH = 115,
3038 II_DSHD = 116,
3039 II_DSLL = 117,
3040 II_DSLL32 = 118,
3041 II_DSLLV = 119,
3042 II_DSRA = 120,
3043 II_DSRA32 = 121,
3044 II_DSRAV = 122,
3045 II_DSRL = 123,
3046 II_DSRL32 = 124,
3047 II_DSRLV = 125,
3048 II_DSUB = 126,
3049 II_DSUBU = 127,
3050 II_DVP = 128,
3051 II_DVPE = 129,
3052 II_EHB = 130,
3053 II_EI = 131,
3054 II_EMT = 132,
3055 II_ERET = 133,
3056 II_ERETNC = 134,
3057 II_EVP = 135,
3058 II_EVPE = 136,
3059 II_ABS = 137,
3060 II_SQRT_D = 138,
3061 II_ADD_D = 139,
3062 II_ADD_PS = 140,
3063 II_ADD_S = 141,
3064 II_DIV_D = 142,
3065 II_DIV_S = 143,
3066 II_FLOOR = 144,
3067 II_MOV_D = 145,
3068 II_MOV_S = 146,
3069 II_MUL_D = 147,
3070 II_MUL_PS = 148,
3071 II_MUL_S = 149,
3072 II_NEG = 150,
3073 II_FORK = 151,
3074 II_SQRT_S = 152,
3075 II_SUB_D = 153,
3076 II_SUB_PS = 154,
3077 II_SUB_S = 155,
3078 II_GINVI = 156,
3079 II_GINVT = 157,
3080 II_HYPCALL = 158,
3081 II_JALR_HB = 159,
3082 II_JALRC = 160,
3083 II_JALRS = 161,
3084 II_JALS = 162,
3085 II_JIALC = 163,
3086 II_JIC = 164,
3087 II_JRADDIUSP = 165,
3088 II_JRC = 166,
3089 II_JR_HB = 167,
3090 II_LB = 168,
3091 II_LBE = 169,
3092 II_LBU = 170,
3093 II_LBUE = 171,
3094 II_LD = 172,
3095 II_LDC1 = 173,
3096 II_LDC2 = 174,
3097 II_LDC3 = 175,
3098 II_LDL = 176,
3099 II_LDPC = 177,
3100 II_LDR = 178,
3101 II_LDXC1 = 179,
3102 II_LH = 180,
3103 II_LHE = 181,
3104 II_LHU = 182,
3105 II_LHUE = 183,
3106 II_LI = 184,
3107 II_LL = 185,
3108 II_LLD = 186,
3109 II_LLE = 187,
3110 II_LSA = 188,
3111 II_LUI = 189,
3112 II_LUXC1 = 190,
3113 II_LW = 191,
3114 II_LWC1 = 192,
3115 II_LWC2 = 193,
3116 II_LWC3 = 194,
3117 II_LWE = 195,
3118 II_LWL = 196,
3119 II_LWLE = 197,
3120 II_LWM = 198,
3121 II_LWPC = 199,
3122 II_LWP = 200,
3123 II_LWR = 201,
3124 II_LWRE = 202,
3125 II_LWUPC = 203,
3126 II_LWU = 204,
3127 II_LWXC1 = 205,
3128 II_LWXS = 206,
3129 II_MADDF_D = 207,
3130 II_MADDF_S = 208,
3131 II_MADD_D = 209,
3132 II_MADD_S = 210,
3133 II_MAX_D = 211,
3134 II_MAXA_D = 212,
3135 II_MAX_S = 213,
3136 II_MAXA_S = 214,
3137 II_MFC0 = 215,
3138 II_MFC2 = 216,
3139 II_MFGC0 = 217,
3140 II_MFHC0 = 218,
3141 II_MFHC1 = 219,
3142 II_MFHGC0 = 220,
3143 II_MFTR = 221,
3144 II_MIN_S = 222,
3145 II_MINA_D = 223,
3146 II_MIN_D = 224,
3147 II_MINA_S = 225,
3148 II_MOD = 226,
3149 II_MODU = 227,
3150 II_MOVE = 228,
3151 II_MOVF_D = 229,
3152 II_MOVF = 230,
3153 II_MOVF_S = 231,
3154 II_MOVN_D = 232,
3155 II_MOVN = 233,
3156 II_MOVN_S = 234,
3157 II_MOVT_D = 235,
3158 II_MOVT = 236,
3159 II_MOVT_S = 237,
3160 II_MOVZ_D = 238,
3161 II_MOVZ = 239,
3162 II_MOVZ_S = 240,
3163 II_MSUBF_D = 241,
3164 II_MSUBF_S = 242,
3165 II_MSUB_D = 243,
3166 II_MSUB_S = 244,
3167 II_MTC0 = 245,
3168 II_MTC2 = 246,
3169 II_MTGC0 = 247,
3170 II_MTHC0 = 248,
3171 II_MTHC1 = 249,
3172 II_MTHGC0 = 250,
3173 II_MTTR = 251,
3174 II_MUH = 252,
3175 II_MUHU = 253,
3176 II_MUL = 254,
3177 II_MULR_PS = 255,
3178 II_MULU = 256,
3179 II_NMADD_D = 257,
3180 II_NMADD_S = 258,
3181 II_NMSUB_D = 259,
3182 II_NMSUB_S = 260,
3183 II_NOR = 261,
3184 II_NOT = 262,
3185 II_OR = 263,
3186 II_ORI = 264,
3187 II_PAUSE = 265,
3188 II_PREF = 266,
3189 II_PREFE = 267,
3190 II_RDHWR = 268,
3191 II_RDPGPR = 269,
3192 II_RECIP_D = 270,
3193 II_RECIP_S = 271,
3194 II_RINT_D = 272,
3195 II_RINT_S = 273,
3196 II_ROTR = 274,
3197 II_ROTRV = 275,
3198 II_ROUND = 276,
3199 II_RSQRT_D = 277,
3200 II_RSQRT_S = 278,
3201 II_RESTORE = 279,
3202 II_SB = 280,
3203 II_SBE = 281,
3204 II_SC = 282,
3205 II_SCD = 283,
3206 II_SCE = 284,
3207 II_SD = 285,
3208 II_SDBBP = 286,
3209 II_SDC1 = 287,
3210 II_SDC2 = 288,
3211 II_SDC3 = 289,
3212 II_SDL = 290,
3213 II_SDR = 291,
3214 II_SDXC1 = 292,
3215 II_SEB = 293,
3216 II_SEH = 294,
3217 II_SELCCZ = 295,
3218 II_SELCCZ_D = 296,
3219 II_SELCCZ_S = 297,
3220 II_SEL_D = 298,
3221 II_SEL_S = 299,
3222 II_SEQ_SNE = 300,
3223 II_SEQI_SNEI = 301,
3224 II_SH = 302,
3225 II_SHE = 303,
3226 II_SIGRIE = 304,
3227 II_SLL = 305,
3228 II_SLLV = 306,
3229 II_SLT_SLTU = 307,
3230 II_SLTI_SLTIU = 308,
3231 II_SRA = 309,
3232 II_SRAV = 310,
3233 II_SRL = 311,
3234 II_SRLV = 312,
3235 II_SSNOP = 313,
3236 II_SUB = 314,
3237 II_SUBU = 315,
3238 II_SUXC1 = 316,
3239 II_SW = 317,
3240 II_SWC1 = 318,
3241 II_SWC2 = 319,
3242 II_SWC3 = 320,
3243 II_SWE = 321,
3244 II_SWL = 322,
3245 II_SWLE = 323,
3246 II_SWM = 324,
3247 II_SWP = 325,
3248 II_SWR = 326,
3249 II_SWRE = 327,
3250 II_SWXC1 = 328,
3251 II_SYNC = 329,
3252 II_SYNCI = 330,
3253 II_SYSCALL = 331,
3254 II_SAVE = 332,
3255 II_TEQ = 333,
3256 II_TEQI = 334,
3257 II_TGE = 335,
3258 II_TGEI = 336,
3259 II_TGEIU = 337,
3260 II_TGEU = 338,
3261 II_TLBGINV = 339,
3262 II_TLBGINVF = 340,
3263 II_TLBGP = 341,
3264 II_TLBGR = 342,
3265 II_TLBGWI = 343,
3266 II_TLBGWR = 344,
3267 II_TLBINV = 345,
3268 II_TLBINVF = 346,
3269 II_TLBP = 347,
3270 II_TLBR = 348,
3271 II_TLBWI = 349,
3272 II_TLBWR = 350,
3273 II_TLT = 351,
3274 II_TLTI = 352,
3275 II_TTLTIU = 353,
3276 II_TLTU = 354,
3277 II_TNE = 355,
3278 II_TNEI = 356,
3279 II_TRUNC = 357,
3280 II_WAIT = 358,
3281 II_WRPGPR = 359,
3282 II_WSBH = 360,
3283 II_XOR = 361,
3284 II_XORI = 362,
3285 II_YIELD = 363,
3286 AND = 364,
3287 LUi = 365,
3288 NOR = 366,
3289 OR = 367,
3290 SLTi_SLTiu = 368,
3291 SUB = 369,
3292 SUBu = 370,
3293 XOR = 371,
3294 SSNOP = 372,
3295 NOP = 373,
3296 B = 374,
3297 BAL = 375,
3298 BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376,
3299 BEQ_BEQL_BNE_BNEL = 377,
3300 BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378,
3301 BREAK = 379,
3302 DERET = 380,
3303 ERET = 381,
3304 ERet_RetRA = 382,
3305 ERETNC = 383,
3306 J_TAILCALL = 384,
3307 JR_TAILCALLREG_TAILCALLREGHB = 385,
3308 JR_HB = 386,
3309 PseudoIndirectBranch_PseudoIndirectHazardBranch = 387,
3310 PseudoReturn = 388,
3311 SDBBP = 389,
3312 SYSCALL = 390,
3313 TEQ = 391,
3314 TEQI = 392,
3315 TGE = 393,
3316 TGEI = 394,
3317 TGEIU = 395,
3318 TGEU = 396,
3319 TLT = 397,
3320 TLTI = 398,
3321 TLTU = 399,
3322 TNE = 400,
3323 TNEI = 401,
3324 TRAP = 402,
3325 TTLTIU = 403,
3326 WAIT = 404,
3327 PAUSE = 405,
3328 JAL = 406,
3329 JALR_JALRHBPseudo_JALRPseudo = 407,
3330 JALR_HB = 408,
3331 JALX = 409,
3332 TLBINV = 410,
3333 TLBINVF = 411,
3334 TLBP = 412,
3335 TLBR = 413,
3336 TLBWI = 414,
3337 TLBWR = 415,
3338 MFC0 = 416,
3339 MTC0 = 417,
3340 MFC2 = 418,
3341 MTC2 = 419,
3342 HYPCALL = 420,
3343 MFGC0 = 421,
3344 MFHGC0 = 422,
3345 MTGC0 = 423,
3346 MTHGC0 = 424,
3347 TLBGINV = 425,
3348 TLBGINVF = 426,
3349 TLBGP = 427,
3350 TLBGR = 428,
3351 TLBGWI = 429,
3352 TLBGWR = 430,
3353 LB = 431,
3354 LBu = 432,
3355 LH = 433,
3356 LHu = 434,
3357 LW = 435,
3358 LL = 436,
3359 LWC2 = 437,
3360 LWC3 = 438,
3361 LDC2 = 439,
3362 LDC3 = 440,
3363 LBE = 441,
3364 LBuE = 442,
3365 LHE = 443,
3366 LHuE = 444,
3367 LWE = 445,
3368 LLE = 446,
3369 LWPC = 447,
3370 LWL = 448,
3371 LWR = 449,
3372 LWLE = 450,
3373 LWRE = 451,
3374 SB = 452,
3375 SH = 453,
3376 SW = 454,
3377 SWC2 = 455,
3378 SWC3 = 456,
3379 SDC2 = 457,
3380 SDC3 = 458,
3381 SC = 459,
3382 SBE = 460,
3383 SHE = 461,
3384 SWE = 462,
3385 SCE = 463,
3386 SWL = 464,
3387 SWR = 465,
3388 SWLE = 466,
3389 SWRE = 467,
3390 PREF = 468,
3391 PREFE = 469,
3392 CACHE = 470,
3393 CACHEE = 471,
3394 SYNC = 472,
3395 SYNCI = 473,
3396 CLO = 474,
3397 CLZ = 475,
3398 DI = 476,
3399 EI = 477,
3400 MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478,
3401 EHB = 479,
3402 RDHWR = 480,
3403 WSBH = 481,
3404 MOVN_I_I = 482,
3405 MOVZ_I_I = 483,
3406 DIV_PseudoSDIV_SDIV = 484,
3407 DIVU_PseudoUDIV_UDIV = 485,
3408 MUL = 486,
3409 MULT_PseudoMULT = 487,
3410 MULTu_PseudoMULTu = 488,
3411 MADD_PseudoMADD = 489,
3412 MADDU_PseudoMADDU = 490,
3413 MSUB_PseudoMSUB = 491,
3414 MSUBU_PseudoMSUBU = 492,
3415 MTHI_MTLO_PseudoMTLOHI = 493,
3416 EXT = 494,
3417 INS = 495,
3418 ADD = 496,
3419 ADDi = 497,
3420 ADDiu = 498,
3421 ANDi = 499,
3422 ORi = 500,
3423 ROTR = 501,
3424 SEB = 502,
3425 SEH = 503,
3426 SLT_SLTu = 504,
3427 SLL = 505,
3428 SRA = 506,
3429 SRL = 507,
3430 XORi = 508,
3431 ADDu = 509,
3432 SLLV = 510,
3433 SRAV = 511,
3434 SRLV = 512,
3435 LSA = 513,
3436 COPY = 514,
3437 VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515,
3438 BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516,
3439 BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517,
3440 INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518,
3441 SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519,
3442 BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520,
3443 BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521,
3444 BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522,
3445 BSELI_B_BSEL_V = 523,
3446 BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524,
3447 BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525,
3448 PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526,
3449 SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527,
3450 BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528,
3451 CFCMSA_CTCMSA = 529,
3452 FABS_S_FABS_D32_FABS_D64 = 530,
3453 MOVF_D32_MOVF_D64 = 531,
3454 MOVF_S = 532,
3455 MOVT_D32_MOVT_D64 = 533,
3456 MOVT_S = 534,
3457 FMOV_D32_FMOV_D64 = 535,
3458 FMOV_S = 536,
3459 FNEG_S_FNEG_D32_FNEG_D64 = 537,
3460 ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538,
3461 ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539,
3462 ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540,
3463 ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541,
3464 AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542,
3465 SHF_B_SHF_H_SHF_W = 543,
3466 FILL_B_FILL_D_FILL_H_FILL_W = 544,
3467 SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545,
3468 MOVE_V = 546,
3469 LDI_B_LDI_D_LDI_H_LDI_W = 547,
3470 AND_V_NOR_V_OR_V_XOR_V = 548,
3471 ANDI_B_NORI_B_ORI_B_XORI_B = 549,
3472 AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550,
3473 FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551,
3474 INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552,
3475 FEXP2_D_FEXP2_W = 553,
3476 CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554,
3477 CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555,
3478 CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556,
3479 CMP_UN_D = 557,
3480 CMP_UN_S = 558,
3481 CMP_UEQ_D = 559,
3482 CMP_UEQ_S = 560,
3483 CMP_EQ_D = 561,
3484 CMP_EQ_S = 562,
3485 CMP_LT_D = 563,
3486 CMP_LT_S = 564,
3487 CMP_ULT_D = 565,
3488 CMP_ULT_S = 566,
3489 CMP_LE_D = 567,
3490 CMP_LE_S = 568,
3491 CMP_ULE_D = 569,
3492 CMP_ULE_S = 570,
3493 FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571,
3494 FSUEQ_D_FSUEQ_W = 572,
3495 FSULE_D_FSULE_W = 573,
3496 FSULT_D_FSULT_W = 574,
3497 FSUNE_D_FSUNE_W = 575,
3498 FSUN_D_FSUN_W = 576,
3499 FCAF_D_FCAF_W = 577,
3500 FCEQ_D_FCEQ_W = 578,
3501 FCLE_D_FCLE_W = 579,
3502 FCLT_D_FCLT_W = 580,
3503 FCNE_D_FCNE_W = 581,
3504 FCOR_D_FCOR_W = 582,
3505 FCUEQ_D_FCUEQ_W = 583,
3506 FCULE_D_FCULE_W = 584,
3507 FCULT_D_FCULT_W = 585,
3508 FCUNE_D_FCUNE_W = 586,
3509 FCUN_D_FCUN_W = 587,
3510 FABS_D_FABS_W = 588,
3511 FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589,
3512 FFQL_D_FFQL_W = 590,
3513 FFQR_D_FFQR_W = 591,
3514 FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592,
3515 FRINT_D_FRINT_W = 593,
3516 FTQ_H_FTQ_W = 594,
3517 FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595,
3518 FEXDO_H_FEXDO_W = 596,
3519 FEXUPL_D_FEXUPL_W = 597,
3520 FEXUPR_D_FEXUPR_W = 598,
3521 FCLASS_D_FCLASS_W = 599,
3522 FMAX_A_D_FMAX_A_W = 600,
3523 FMAX_D_FMAX_W = 601,
3524 FMIN_A_D_FMIN_A_W = 602,
3525 FMIN_D_FMIN_W = 603,
3526 FLOG2_D_FLOG2_W = 604,
3527 ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605,
3528 ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606,
3529 INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607,
3530 SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608,
3531 SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609,
3532 SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610,
3533 SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611,
3534 SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612,
3535 MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613,
3536 DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614,
3537 HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615,
3538 HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616,
3539 MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617,
3540 MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618,
3541 MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619,
3542 MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620,
3543 SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621,
3544 SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622,
3545 SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623,
3546 SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624,
3547 SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625,
3548 PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626,
3549 NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627,
3550 FADD_D32_FADD_D64 = 628,
3551 FADD_PS64 = 629,
3552 FADD_S = 630,
3553 FMUL_D32_FMUL_D64 = 631,
3554 FMUL_PS64 = 632,
3555 FMUL_S = 633,
3556 FSUB_D32_FSUB_D64 = 634,
3557 FSUB_PS64 = 635,
3558 FSUB_S = 636,
3559 TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637,
3560 CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638,
3561 CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639,
3562 C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640,
3563 C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641,
3564 FCMP_D32_FCMP_D64 = 642,
3565 FCMP_S32 = 643,
3566 PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644,
3567 PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645,
3568 FDIV_S = 646,
3569 FDIV_D32_FDIV_D64 = 647,
3570 FSQRT_S = 648,
3571 FSQRT_D32_FSQRT_D64 = 649,
3572 FRCP_D_FRCP_W = 650,
3573 FRSQRT_D_FRSQRT_W = 651,
3574 RECIP_D32_RECIP_D64 = 652,
3575 RSQRT_D32_RSQRT_D64 = 653,
3576 RECIP_S = 654,
3577 RSQRT_S = 655,
3578 FMADD_D_FMADD_W = 656,
3579 FMSUB_D_FMSUB_W = 657,
3580 FDIV_W = 658,
3581 FDIV_D = 659,
3582 FSQRT_W = 660,
3583 FSQRT_D = 661,
3584 FMUL_D_FMUL_W = 662,
3585 FADD_D_FADD_W = 663,
3586 FSUB_D_FSUB_W = 664,
3587 DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665,
3588 DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666,
3589 DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667,
3590 MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668,
3591 MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669,
3592 MULV_B_MULV_D_MULV_H_MULV_W = 670,
3593 MADDR_Q_H_MADDR_Q_W = 671,
3594 MADD_Q_H_MADD_Q_W = 672,
3595 MSUBR_Q_H_MSUBR_Q_W = 673,
3596 MSUB_Q_H_MSUB_Q_W = 674,
3597 MULR_Q_H_MULR_Q_W = 675,
3598 MUL_Q_H_MUL_Q_W = 676,
3599 MADD_D32_MADD_D64 = 677,
3600 MADD_S = 678,
3601 MSUB_D32_MSUB_D64 = 679,
3602 MSUB_S = 680,
3603 NMADD_D32_NMADD_D64 = 681,
3604 NMADD_S = 682,
3605 NMSUB_D32_NMSUB_D64 = 683,
3606 NMSUB_S = 684,
3607 CTC1 = 685,
3608 MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686,
3609 MTHC1_D32_MTHC1_D64 = 687,
3610 COPY_U_B_COPY_U_H_COPY_U_W = 688,
3611 COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689,
3612 BC1F = 690,
3613 BC1FL = 691,
3614 BC1T = 692,
3615 BC1TL = 693,
3616 CFC1 = 694,
3617 MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695,
3618 MFHC1_D32_MFHC1_D64 = 696,
3619 MOVF_I = 697,
3620 MOVT_I = 698,
3621 SDC1_SDC164 = 699,
3622 SDXC1_SDXC164 = 700,
3623 SWC1 = 701,
3624 SWXC1 = 702,
3625 SUXC1_SUXC164 = 703,
3626 ST_B_ST_D_ST_H_ST_W = 704,
3627 ST_F16 = 705,
3628 MOVN_I_D32_MOVN_I_D64 = 706,
3629 MOVN_I_S = 707,
3630 MOVZ_I_D32_MOVZ_I_D64 = 708,
3631 MOVZ_I_S = 709,
3632 LDC1_LDC164 = 710,
3633 LDXC1_LDXC164 = 711,
3634 LWC1 = 712,
3635 LWXC1 = 713,
3636 LUXC1_LUXC164 = 714,
3637 LD_B_LD_D_LD_H_LD_W = 715,
3638 LD_F16 = 716,
3639 CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717,
3640 FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718,
3641 ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719,
3642 ROTRV = 720,
3643 ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721,
3644 ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722,
3645 ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723,
3646 LEA_ADDiu = 724,
3647 ADDIUPC = 725,
3648 ALIGN = 726,
3649 ALUIPC = 727,
3650 AUI = 728,
3651 AUIPC = 729,
3652 BITSWAP = 730,
3653 CLO_R6 = 731,
3654 CLZ_R6 = 732,
3655 LSA_R6 = 733,
3656 SELEQZ_SELNEZ = 734,
3657 AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735,
3658 SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736,
3659 Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737,
3660 ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738,
3661 ADDU16_MM_ADDu_MM = 739,
3662 ADD_MM = 740,
3663 ADDi_MM = 741,
3664 AND16_MM_ANDI16_MM_AND_MM = 742,
3665 ANDi_MM = 743,
3666 CLO_MM = 744,
3667 CLZ_MM = 745,
3668 EXT_MM = 746,
3669 INS_MM = 747,
3670 LI16_MM = 748,
3671 LUi_MM = 749,
3672 MOVE16_MM = 750,
3673 MOVEP_MM = 751,
3674 NOR_MM = 752,
3675 NOT16_MM = 753,
3676 OR16_MM_OR_MM = 754,
3677 ORi_MM = 755,
3678 ROTRV_MM = 756,
3679 ROTR_MM = 757,
3680 SEB_MM = 758,
3681 SEH_MM = 759,
3682 SLL16_MM_SLL_MM = 760,
3683 SLLV_MM = 761,
3684 SLT_MM_SLTu_MM = 762,
3685 SLTi_MM_SLTiu_MM = 763,
3686 SRAV_MM = 764,
3687 SRA_MM = 765,
3688 SRL16_MM_SRL_MM = 766,
3689 SRLV_MM = 767,
3690 SSNOP_MM = 768,
3691 SUBU16_MM_SUBu_MM = 769,
3692 SUB_MM = 770,
3693 WSBH_MM = 771,
3694 XOR16_MM_XOR_MM = 772,
3695 XORi_MM = 773,
3696 ADDIUPC_MMR6 = 774,
3697 ADDIU_MMR6 = 775,
3698 ADDU16_MMR6_ADDU_MMR6 = 776,
3699 ADD_MMR6 = 777,
3700 ALIGN_MMR6 = 778,
3701 ALUIPC_MMR6 = 779,
3702 AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780,
3703 ANDI_MMR6 = 781,
3704 AUIPC_MMR6 = 782,
3705 AUI_MMR6 = 783,
3706 BITSWAP_MMR6 = 784,
3707 CLO_MMR6 = 785,
3708 CLZ_MMR6 = 786,
3709 EXT_MMR6 = 787,
3710 INS_MMR6 = 788,
3711 LI16_MMR6 = 789,
3712 LSA_MMR6 = 790,
3713 LUI_MMR6 = 791,
3714 MOVE16_MMR6 = 792,
3715 NOR_MMR6 = 793,
3716 NOT16_MMR6 = 794,
3717 OR16_MMR6_OR_MMR6 = 795,
3718 ORI_MMR6 = 796,
3719 SELEQZ_MMR6_SELNEZ_MMR6 = 797,
3720 SLL16_MMR6_SLL_MMR6 = 798,
3721 SRL16_MMR6 = 799,
3722 SSNOP_MMR6 = 800,
3723 SUBU16_MMR6_SUBU_MMR6 = 801,
3724 SUB_MMR6 = 802,
3725 WSBH_MMR6 = 803,
3726 XOR16_MMR6_XOR_MMR6 = 804,
3727 XORI_MMR6 = 805,
3728 AND64_ANDi64 = 806,
3729 DEXT64_32 = 807,
3730 DSLL64_32 = 808,
3731 ORi64 = 809,
3732 SEB64 = 810,
3733 SEH64 = 811,
3734 SLL64_32_SLL64_64 = 812,
3735 SLT64_SLTu64 = 813,
3736 SLTi64_SLTiu64 = 814,
3737 XOR64_XORi64 = 815,
3738 DADD = 816,
3739 DADDi = 817,
3740 DADDiu = 818,
3741 DADDu = 819,
3742 DCLO = 820,
3743 DCLZ = 821,
3744 DEXT_DEXTM_DEXTU = 822,
3745 DINS_DINSM_DINSU = 823,
3746 DROTR = 824,
3747 DROTR32 = 825,
3748 DROTRV = 826,
3749 DSBH = 827,
3750 DSHD = 828,
3751 DSLL = 829,
3752 DSLL32 = 830,
3753 DSLLV = 831,
3754 DSRA = 832,
3755 DSRA32 = 833,
3756 DSRAV = 834,
3757 DSRL = 835,
3758 DSRL32 = 836,
3759 DSRLV = 837,
3760 DSUB = 838,
3761 DSUBu = 839,
3762 LEA_ADDiu64 = 840,
3763 LUi64 = 841,
3764 NOR64 = 842,
3765 OR64 = 843,
3766 DALIGN = 844,
3767 DAHI = 845,
3768 DATI = 846,
3769 DAUI = 847,
3770 DCLO_R6 = 848,
3771 DCLZ_R6 = 849,
3772 DBITSWAP = 850,
3773 DLSA_DLSA_R6 = 851,
3774 SELEQZ64_SELNEZ64 = 852,
3775 MADD = 853,
3776 MADDU = 854,
3777 MSUB = 855,
3778 MSUBU = 856,
3779 PseudoMADD_MM = 857,
3780 PseudoMADDU_MM = 858,
3781 PseudoMSUB_MM = 859,
3782 PseudoMSUBU_MM = 860,
3783 PseudoMULT_MM = 861,
3784 PseudoMULTu_MM = 862,
3785 PseudoMULT = 863,
3786 PseudoMULTu = 864,
3787 PseudoSDIV_SDIV = 865,
3788 PseudoUDIV_UDIV = 866,
3789 PseudoMFHI_MM_PseudoMFLO_MM = 867,
3790 PseudoMTLOHI_MM = 868,
3791 MUH = 869,
3792 MUHU = 870,
3793 MULU = 871,
3794 MUL_R6 = 872,
3795 MOD = 873,
3796 MODU = 874,
3797 MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875,
3798 DivRxRy16 = 876,
3799 DivuRxRy16 = 877,
3800 MULT_MM = 878,
3801 MULTu_MM = 879,
3802 MADD_MM = 880,
3803 MADDU_MM = 881,
3804 MSUB_MM = 882,
3805 MSUBU_MM = 883,
3806 MUL_MM = 884,
3807 SDIV_MM_SDIV_MM_Pseudo = 885,
3808 UDIV_MM_UDIV_MM_Pseudo = 886,
3809 MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887,
3810 MOVF_I_MM = 888,
3811 MOVT_I_MM = 889,
3812 MTHI_MM_MTLO_MM = 890,
3813 RDHWR_MM = 891,
3814 MUHU_MMR6 = 892,
3815 MUH_MMR6 = 893,
3816 MULU_MMR6 = 894,
3817 MUL_MMR6 = 895,
3818 MODU_MMR6 = 896,
3819 MOD_MMR6 = 897,
3820 DIVU_MMR6 = 898,
3821 DIV_MMR6 = 899,
3822 RDHWR_MMR6 = 900,
3823 DMULU = 901,
3824 DMULT_PseudoDMULT = 902,
3825 DMULTu_PseudoDMULTu = 903,
3826 DSDIV_PseudoDSDIV = 904,
3827 DUDIV_PseudoDUDIV = 905,
3828 MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906,
3829 PseudoMTLOHI64 = 907,
3830 MTHI64_MTLO64 = 908,
3831 RDHWR64 = 909,
3832 MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910,
3833 MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911,
3834 DMUH = 912,
3835 DMUHU = 913,
3836 DMUL_R6 = 914,
3837 DDIV = 915,
3838 DMOD = 916,
3839 DDIVU = 917,
3840 DMODU = 918,
3841 BAL_BR_BLTZAL = 919,
3842 BEQ_BNE = 920,
3843 BGTZ_BGEZ_BLEZ_BLTZ = 921,
3844 J = 922,
3845 JR = 923,
3846 ERet = 924,
3847 NAL = 925,
3848 BGEZAL = 926,
3849 BALC = 927,
3850 BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 928,
3851 JIALC = 929,
3852 BC = 930,
3853 BC2EQZ_BC2NEZ = 931,
3854 BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 932,
3855 BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 933,
3856 JIC = 934,
3857 JR_HB_R6 = 935,
3858 SIGRIE = 936,
3859 PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 937,
3860 TAILCALLR6REG_TAILCALLHBR6REG = 938,
3861 SDBBP_R6 = 939,
3862 Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 940,
3863 BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 941,
3864 Jal16_JalB16 = 942,
3865 JumpLinkReg16 = 943,
3866 Break16 = 944,
3867 SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 945,
3868 B16_MM_B_MM = 946,
3869 BAL_BR_MM = 947,
3870 BC1F_MM = 948,
3871 BC1T_MM = 949,
3872 BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 950,
3873 BEQZC_MM_BNEZC_MM = 951,
3874 BEQ_MM_BNE_MM = 952,
3875 DERET_MM = 953,
3876 ERET_MM = 954,
3877 JR16_MM_JR_MM = 955,
3878 J_MM = 956,
3879 B_MM_Pseudo = 957,
3880 BGEZALS_MM_BLTZALS_MM = 958,
3881 BGEZAL_MM_BLTZAL_MM = 959,
3882 JALR16_MM_JALR_MM = 960,
3883 JALRS16_MM_JALRS_MM = 961,
3884 JALS_MM = 962,
3885 JALX_MM_JAL_MM = 963,
3886 TAILCALLREG_MM = 964,
3887 TAILCALL_MM = 965,
3888 PseudoIndirectBranch_MM = 966,
3889 BREAK16_MM_BREAK_MM = 967,
3890 SDBBP16_MM_SDBBP_MM = 968,
3891 SYSCALL_MM = 969,
3892 TEQI_MM = 970,
3893 TEQ_MM = 971,
3894 TGEIU_MM = 972,
3895 TGEI_MM = 973,
3896 TGEU_MM = 974,
3897 TGE_MM = 975,
3898 TLTIU_MM = 976,
3899 TLTI_MM = 977,
3900 TLTU_MM = 978,
3901 TLT_MM = 979,
3902 TNEI_MM = 980,
3903 TNE_MM = 981,
3904 TRAP_MM = 982,
3905 BC16_MMR6_BC_MMR6 = 983,
3906 BC1EQZC_MMR6_BC1NEZC_MMR6 = 984,
3907 BC2EQZC_MMR6_BC2NEZC_MMR6 = 985,
3908 BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 986,
3909 BEQZC16_MMR6_BNEZC16_MMR6 = 987,
3910 BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 988,
3911 DERET_MMR6 = 989,
3912 ERETNC_MMR6 = 990,
3913 JAL_MMR6 = 991,
3914 ERET_MMR6 = 992,
3915 JIC_MMR6 = 993,
3916 JRADDIUSP_JRCADDIUSP_MMR6 = 994,
3917 JRC16_MM = 995,
3918 JRC16_MMR6 = 996,
3919 SIGRIE_MMR6 = 997,
3920 B_MMR6_Pseudo = 998,
3921 PseudoIndirectBranch_MMR6 = 999,
3922 BALC_MMR6 = 1000,
3923 BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1001,
3924 JALRC16_MMR6 = 1002,
3925 JALRC_HB_MMR6 = 1003,
3926 JALRC_MMR6 = 1004,
3927 JIALC_MMR6 = 1005,
3928 TAILCALLREG_MMR6 = 1006,
3929 TAILCALL_MMR6 = 1007,
3930 BREAK16_MMR6_BREAK_MMR6 = 1008,
3931 SDBBP_MMR6_SDBBP16_MMR6 = 1009,
3932 BEQ64_BNE64 = 1010,
3933 BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1011,
3934 JR64 = 1012,
3935 JALR64_JALR64Pseudo_JALRHB64Pseudo = 1013,
3936 JALR_HB64 = 1014,
3937 JR_HB64 = 1015,
3938 TAILCALLREG64_TAILCALLREGHB64 = 1016,
3939 PseudoReturn64 = 1017,
3940 BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1018,
3941 BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1019,
3942 JIC64 = 1020,
3943 PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1021,
3944 JIALC64 = 1022,
3945 JR_HB64_R6 = 1023,
3946 TAILCALL64R6REG_TAILCALLHB64R6REG = 1024,
3947 PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1025,
3948 EVP = 1026,
3949 DVP = 1027,
3950 TLBP_MM = 1028,
3951 TLBR_MM = 1029,
3952 TLBWI_MM = 1030,
3953 TLBWR_MM = 1031,
3954 DI_MM = 1032,
3955 EI_MM = 1033,
3956 EHB_MM = 1034,
3957 PAUSE_MM = 1035,
3958 WAIT_MM = 1036,
3959 RDPGPR_MMR6 = 1037,
3960 WRPGPR_MMR6 = 1038,
3961 TLBINV_MMR6 = 1039,
3962 TLBINVF_MMR6 = 1040,
3963 MFHC0_MMR6 = 1041,
3964 MFC0_MMR6 = 1042,
3965 MFHC2_MMR6_MFC2_MMR6 = 1043,
3966 MTHC0_MMR6 = 1044,
3967 MTC0_MMR6 = 1045,
3968 MTHC2_MMR6_MTC2_MMR6 = 1046,
3969 EVP_MMR6 = 1047,
3970 DVP_MMR6 = 1048,
3971 DI_MMR6 = 1049,
3972 EI_MMR6 = 1050,
3973 EHB_MMR6 = 1051,
3974 PAUSE_MMR6 = 1052,
3975 WAIT_MMR6 = 1053,
3976 DMFC0 = 1054,
3977 DMTC0 = 1055,
3978 DMFC2 = 1056,
3979 DMTC2 = 1057,
3980 CFC2_MM = 1058,
3981 CTC2_MM = 1059,
3982 DMT = 1060,
3983 DVPE = 1061,
3984 EMT = 1062,
3985 EVPE = 1063,
3986 MFTR = 1064,
3987 MTTR = 1065,
3988 YIELD = 1066,
3989 FORK = 1067,
3990 DMFGC0 = 1068,
3991 DMTGC0 = 1069,
3992 HYPCALL_MM = 1070,
3993 TLBGINVF_MM = 1071,
3994 TLBGINV_MM = 1072,
3995 TLBGP_MM = 1073,
3996 TLBGR_MM = 1074,
3997 TLBGWI_MM = 1075,
3998 TLBGWR_MM = 1076,
3999 MFGC0_MM = 1077,
4000 MFHGC0_MM = 1078,
4001 MTGC0_MM = 1079,
4002 MTHGC0_MM = 1080,
4003 SC_MMR6 = 1081,
4004 LDC2_R6 = 1082,
4005 LL_R6 = 1083,
4006 LWC2_R6 = 1084,
4007 SWC2_R6 = 1085,
4008 SDC2_R6 = 1086,
4009 SC_R6 = 1087,
4010 PREF_R6 = 1088,
4011 CACHE_R6 = 1089,
4012 GINVI = 1090,
4013 GINVT = 1091,
4014 LBE_MM = 1092,
4015 LBuE_MM = 1093,
4016 LHE_MM = 1094,
4017 LHuE_MM = 1095,
4018 LWE_MM = 1096,
4019 LWLE_MM = 1097,
4020 LWRE_MM = 1098,
4021 LLE_MM = 1099,
4022 SBE_MM = 1100,
4023 SB_MM = 1101,
4024 SHE_MM = 1102,
4025 SWE_MM = 1103,
4026 SWLE_MM = 1104,
4027 SWRE_MM = 1105,
4028 SCE_MM = 1106,
4029 PREFE_MM = 1107,
4030 CACHEE_MM = 1108,
4031 Restore16_RestoreX16 = 1109,
4032 LbRxRyOffMemX16 = 1110,
4033 LbuRxRyOffMemX16 = 1111,
4034 LhRxRyOffMemX16 = 1112,
4035 LhuRxRyOffMemX16 = 1113,
4036 LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1114,
4037 Save16_SaveX16 = 1115,
4038 SbRxRyOffMemX16 = 1116,
4039 ShRxRyOffMemX16 = 1117,
4040 SwRxRyOffMemX16_SwRxSpImmX16 = 1118,
4041 LBU16_MM_LBu_MM = 1119,
4042 LB_MM = 1120,
4043 LHU16_MM_LHu_MM = 1121,
4044 LH_MM = 1122,
4045 LL_MM = 1123,
4046 LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1124,
4047 LWL_MM = 1125,
4048 LWM16_MM_LWM32_MM = 1126,
4049 LWP_MM = 1127,
4050 LWR_MM = 1128,
4051 LWU_MM = 1129,
4052 LWXS_MM = 1130,
4053 SB16_MM = 1131,
4054 SC_MM = 1132,
4055 SH16_MM_SH_MM = 1133,
4056 SW16_MM_SWSP_MM_SW_MM = 1134,
4057 SWL_MM = 1135,
4058 SWM16_MM_SWM32_MM = 1136,
4059 SWM_MM = 1137,
4060 SWP_MM = 1138,
4061 SWR_MM = 1139,
4062 PREF_MM_PREFX_MM = 1140,
4063 CACHE_MM = 1141,
4064 SYNC_MM = 1142,
4065 SYNCI_MM = 1143,
4066 GINVI_MMR6 = 1144,
4067 GINVT_MMR6 = 1145,
4068 LBU_MMR6 = 1146,
4069 LB_MMR6 = 1147,
4070 LDC2_MMR6 = 1148,
4071 LL_MMR6 = 1149,
4072 LWM16_MMR6 = 1150,
4073 LWC2_MMR6 = 1151,
4074 LWPC_MMR6 = 1152,
4075 LW_MMR6 = 1153,
4076 SB16_MMR6_SB_MMR6 = 1154,
4077 SDC2_MMR6 = 1155,
4078 SH16_MMR6_SH_MMR6 = 1156,
4079 SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1157,
4080 SWC2_MMR6 = 1158,
4081 SWM16_MMR6 = 1159,
4082 SYNC_MMR6 = 1160,
4083 SYNCI_MMR6 = 1161,
4084 PREF_MMR6 = 1162,
4085 CACHE_MMR6 = 1163,
4086 LD = 1164,
4087 LL64_LLD = 1165,
4088 LWu = 1166,
4089 LB64 = 1167,
4090 LBu64 = 1168,
4091 LH64 = 1169,
4092 LHu64 = 1170,
4093 LW64 = 1171,
4094 LWL64 = 1172,
4095 LWR64 = 1173,
4096 LDL = 1174,
4097 LDR = 1175,
4098 SD = 1176,
4099 SC64_SCD = 1177,
4100 SB64 = 1178,
4101 SH64 = 1179,
4102 SW64 = 1180,
4103 SWL64 = 1181,
4104 SWR64 = 1182,
4105 SDL = 1183,
4106 SDR = 1184,
4107 LWUPC = 1185,
4108 LDPC = 1186,
4109 LLD_R6 = 1187,
4110 LL64_R6 = 1188,
4111 SC64_R6 = 1189,
4112 SCD_R6 = 1190,
4113 CRC32B = 1191,
4114 CRC32H = 1192,
4115 CRC32W = 1193,
4116 CRC32CB = 1194,
4117 CRC32CH = 1195,
4118 CRC32CW = 1196,
4119 CRC32D = 1197,
4120 CRC32CD = 1198,
4121 BADDu = 1199,
4122 BBIT0_BBIT032_BBIT1_BBIT132 = 1200,
4123 CINS_CINS32_CINS64_32_CINS_i32 = 1201,
4124 DMFC2_OCTEON = 1202,
4125 DMTC2_OCTEON = 1203,
4126 DPOP_POP = 1204,
4127 EXTS_EXTS32 = 1205,
4128 MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1206,
4129 SEQ_SNE = 1207,
4130 SEQi_SNEi = 1208,
4131 V3MULU_VMM0_VMULU = 1209,
4132 DMUL = 1210,
4133 SAA_SAAD = 1211,
4134 ADDR_PS64 = 1212,
4135 CVT_PS_PW64_CVT_PW_PS64 = 1213,
4136 MULR_PS64 = 1214,
4137 PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1215,
4138 MOVT_I64 = 1216,
4139 MOVF_I64 = 1217,
4140 MOVZ_I64_S = 1218,
4141 MOVN_I64_D64 = 1219,
4142 MOVN_I64_S = 1220,
4143 MOVZ_I64_D64 = 1221,
4144 SELEQZ_S_SELNEZ_S = 1222,
4145 SELEQZ_D_SELNEZ_D = 1223,
4146 MAX_S_MAXA_S = 1224,
4147 MAX_D_MAXA_D = 1225,
4148 MIN_S_MINA_D = 1226,
4149 MIN_D_MINA_S = 1227,
4150 CLASS_S = 1228,
4151 CLASS_D = 1229,
4152 RINT_S = 1230,
4153 RINT_D = 1231,
4154 BC1EQZ_BC1NEZ = 1232,
4155 SEL_D = 1233,
4156 SEL_S = 1234,
4157 MADDF_S = 1235,
4158 MSUBF_S = 1236,
4159 MADDF_D = 1237,
4160 MSUBF_D = 1238,
4161 MOVF_D32_MM = 1239,
4162 MOVF_S_MM = 1240,
4163 MOVN_I_D32_MM = 1241,
4164 MOVN_I_S_MM = 1242,
4165 MOVT_D32_MM = 1243,
4166 MOVT_S_MM = 1244,
4167 MOVZ_I_D32_MM = 1245,
4168 MOVZ_I_S_MM = 1246,
4169 CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1247,
4170 CEIL_W_MM_CEIL_W_S_MM = 1248,
4171 FLOOR_W_MM_FLOOR_W_S_MM = 1249,
4172 NMADD_S_MM = 1250,
4173 NMADD_D32_MM = 1251,
4174 NMSUB_S_MM = 1252,
4175 NMSUB_D32_MM = 1253,
4176 MADD_S_MM = 1254,
4177 MADD_D32_MM = 1255,
4178 ROUND_W_MM_ROUND_W_S_MM = 1256,
4179 TRUNC_W_MM_TRUNC_W_S_MM = 1257,
4180 C_F_D32_MM_C_F_D64_MM = 1258,
4181 C_F_S_MM = 1259,
4182 C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1260,
4183 C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1261,
4184 C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1262,
4185 C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1263,
4186 C_NGLE_D32_MM_C_NGLE_D64_MM = 1264,
4187 C_NGLE_S_MM = 1265,
4188 FCMP_S32_MM = 1266,
4189 FCMP_D32_MM = 1267,
4190 MFC1_MM = 1268,
4191 MFHC1_D32_MM_MFHC1_D64_MM = 1269,
4192 MTC1_MM_MTC1_D64_MM = 1270,
4193 MTHC1_D32_MM_MTHC1_D64_MM = 1271,
4194 FABS_D32_MM_FABS_D64_MM = 1272,
4195 FABS_S_MM = 1273,
4196 FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1274,
4197 FADD_D32_MM_FADD_D64_MM = 1275,
4198 FADD_S_MM = 1276,
4199 FMOV_D32_MM_FMOV_D64_MM = 1277,
4200 FMOV_S_MM = 1278,
4201 FMUL_D32_MM_FMUL_D64_MM = 1279,
4202 FMUL_S_MM = 1280,
4203 FSUB_D32_MM_FSUB_D64_MM = 1281,
4204 FSUB_S_MM = 1282,
4205 MSUB_S_MM = 1283,
4206 MSUB_D32_MM = 1284,
4207 FDIV_S_MM = 1285,
4208 FDIV_D32_MM_FDIV_D64_MM = 1286,
4209 FSQRT_S_MM = 1287,
4210 FSQRT_D32_MM_FSQRT_D64_MM = 1288,
4211 RECIP_S_MM_RSQRT_S_MM = 1289,
4212 RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1290,
4213 SDC1_MM_D32_SDC1_MM_D64 = 1291,
4214 SWC1_MM = 1292,
4215 SUXC1_MM = 1293,
4216 SWXC1_MM = 1294,
4217 CFC1_MM = 1295,
4218 CTC1_MM = 1296,
4219 LDC1_MM_D32_LDC1_MM_D64 = 1297,
4220 LUXC1_MM = 1298,
4221 LWC1_MM = 1299,
4222 LWXC1_MM = 1300,
4223 FNEG_S_MMR6 = 1301,
4224 CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1302,
4225 CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1303,
4226 CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1304,
4227 CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1305,
4228 CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1306,
4229 CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1307,
4230 CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1308,
4231 TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1309,
4232 ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1310,
4233 FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1311,
4234 CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1312,
4235 MFC1_MMR6 = 1313,
4236 MTC1_MMR6 = 1314,
4237 CLASS_S_MMR6_CLASS_D_MMR6 = 1315,
4238 FADD_S_MMR6 = 1316,
4239 MAX_D_MMR6 = 1317,
4240 MAX_S_MMR6 = 1318,
4241 MIN_D_MMR6 = 1319,
4242 MIN_S_MMR6 = 1320,
4243 MAXA_D_MMR6 = 1321,
4244 MAXA_S_MMR6 = 1322,
4245 MINA_D_MMR6 = 1323,
4246 MINA_S_MMR6 = 1324,
4247 SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1325,
4248 SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1326,
4249 SEL_D_MMR6 = 1327,
4250 SEL_S_MMR6 = 1328,
4251 RINT_S_MMR6_RINT_D_MMR6 = 1329,
4252 MADDF_D_MMR6 = 1330,
4253 MADDF_S_MMR6 = 1331,
4254 MSUBF_D_MMR6 = 1332,
4255 MSUBF_S_MMR6 = 1333,
4256 FMOV_S_MMR6 = 1334,
4257 FMUL_S_MMR6 = 1335,
4258 FSUB_S_MMR6 = 1336,
4259 FMOV_D_MMR6 = 1337,
4260 FDIV_S_MMR6 = 1338,
4261 SDC1_D64_MMR6 = 1339,
4262 LDC1_D64_MMR6 = 1340,
4263 DMFC1 = 1341,
4264 DMTC1 = 1342,
4265 SWDSP = 1343,
4266 LWDSP = 1344,
4267 PseudoMTLOHI_DSP = 1345,
4268 EXTRV_RS_W = 1346,
4269 EXTRV_R_W = 1347,
4270 EXTRV_S_H = 1348,
4271 EXTRV_W = 1349,
4272 EXTR_RS_W = 1350,
4273 EXTR_R_W = 1351,
4274 EXTR_S_H = 1352,
4275 EXTR_W = 1353,
4276 INSV = 1354,
4277 MTHLIP = 1355,
4278 MTHI_DSP = 1356,
4279 MTLO_DSP = 1357,
4280 ABSQ_S_PH = 1358,
4281 ABSQ_S_W = 1359,
4282 ADDQ_PH = 1360,
4283 ADDQ_S_PH = 1361,
4284 ADDQ_S_W = 1362,
4285 ADDSC = 1363,
4286 ADDU_QB = 1364,
4287 ADDU_S_QB = 1365,
4288 ADDWC = 1366,
4289 BITREV = 1367,
4290 BPOSGE32 = 1368,
4291 CMPGU_EQ_QB = 1369,
4292 CMPGU_LE_QB = 1370,
4293 CMPGU_LT_QB = 1371,
4294 CMPU_EQ_QB = 1372,
4295 CMPU_LE_QB = 1373,
4296 CMPU_LT_QB = 1374,
4297 CMP_EQ_PH = 1375,
4298 CMP_LE_PH = 1376,
4299 CMP_LT_PH = 1377,
4300 DPAQ_SA_L_W = 1378,
4301 DPAQ_S_W_PH = 1379,
4302 DPAU_H_QBL = 1380,
4303 DPAU_H_QBR = 1381,
4304 DPSQ_SA_L_W = 1382,
4305 DPSQ_S_W_PH = 1383,
4306 DPSU_H_QBL = 1384,
4307 DPSU_H_QBR = 1385,
4308 EXTPDPV = 1386,
4309 EXTPDP = 1387,
4310 EXTPV = 1388,
4311 EXTP = 1389,
4312 LBUX = 1390,
4313 LHX = 1391,
4314 LWX = 1392,
4315 MADDU_DSP = 1393,
4316 MADD_DSP = 1394,
4317 MAQ_SA_W_PHL = 1395,
4318 MAQ_SA_W_PHR = 1396,
4319 MAQ_S_W_PHL = 1397,
4320 MAQ_S_W_PHR = 1398,
4321 MFHI_DSP = 1399,
4322 MFLO_DSP = 1400,
4323 MODSUB = 1401,
4324 MSUBU_DSP = 1402,
4325 MSUB_DSP = 1403,
4326 MULEQ_S_W_PHL = 1404,
4327 MULEQ_S_W_PHR = 1405,
4328 MULEU_S_PH_QBL = 1406,
4329 MULEU_S_PH_QBR = 1407,
4330 MULQ_RS_PH = 1408,
4331 MULSAQ_S_W_PH = 1409,
4332 MULTU_DSP = 1410,
4333 MULT_DSP = 1411,
4334 PACKRL_PH = 1412,
4335 PICK_PH = 1413,
4336 PICK_QB = 1414,
4337 PRECEQU_PH_QBLA = 1415,
4338 PRECEQU_PH_QBL = 1416,
4339 PRECEQU_PH_QBRA = 1417,
4340 PRECEQU_PH_QBR = 1418,
4341 PRECEQ_W_PHL = 1419,
4342 PRECEQ_W_PHR = 1420,
4343 PRECEU_PH_QBLA = 1421,
4344 PRECEU_PH_QBL = 1422,
4345 PRECEU_PH_QBRA = 1423,
4346 PRECEU_PH_QBR = 1424,
4347 PRECRQU_S_QB_PH = 1425,
4348 PRECRQ_PH_W = 1426,
4349 PRECRQ_QB_PH = 1427,
4350 PRECRQ_RS_PH_W = 1428,
4351 RADDU_W_QB = 1429,
4352 RDDSP = 1430,
4353 REPLV_PH = 1431,
4354 REPLV_QB = 1432,
4355 REPL_PH = 1433,
4356 REPL_QB = 1434,
4357 SHILOV = 1435,
4358 SHILO = 1436,
4359 SHLLV_PH = 1437,
4360 SHLLV_QB = 1438,
4361 SHLLV_S_PH = 1439,
4362 SHLLV_S_W = 1440,
4363 SHLL_PH = 1441,
4364 SHLL_QB = 1442,
4365 SHLL_S_PH = 1443,
4366 SHLL_S_W = 1444,
4367 SHRAV_PH = 1445,
4368 SHRAV_R_PH = 1446,
4369 SHRAV_R_W = 1447,
4370 SHRA_PH = 1448,
4371 SHRA_R_PH = 1449,
4372 SHRA_R_W = 1450,
4373 SHRLV_QB = 1451,
4374 SHRL_QB = 1452,
4375 SUBQ_PH = 1453,
4376 SUBQ_S_PH = 1454,
4377 SUBQ_S_W = 1455,
4378 SUBU_QB = 1456,
4379 SUBU_S_QB = 1457,
4380 WRDSP = 1458,
4381 PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1459,
4382 PseudoPICK_PH_PseudoPICK_QB = 1460,
4383 ABSQ_S_QB = 1461,
4384 ADDQH_PH = 1462,
4385 ADDQH_R_PH = 1463,
4386 ADDQH_R_W = 1464,
4387 ADDQH_W = 1465,
4388 ADDUH_QB = 1466,
4389 ADDUH_R_QB = 1467,
4390 ADDU_PH = 1468,
4391 ADDU_S_PH = 1469,
4392 APPEND = 1470,
4393 BALIGN = 1471,
4394 CMPGDU_EQ_QB = 1472,
4395 CMPGDU_LE_QB = 1473,
4396 CMPGDU_LT_QB = 1474,
4397 DPA_W_PH = 1475,
4398 DPAQX_SA_W_PH = 1476,
4399 DPAQX_S_W_PH = 1477,
4400 DPAX_W_PH = 1478,
4401 DPS_W_PH = 1479,
4402 DPSQX_S_W_PH = 1480,
4403 DPSQX_SA_W_PH = 1481,
4404 DPSX_W_PH = 1482,
4405 MUL_PH = 1483,
4406 MUL_S_PH = 1484,
4407 MULQ_RS_W = 1485,
4408 MULQ_S_PH = 1486,
4409 MULQ_S_W = 1487,
4410 MULSA_W_PH = 1488,
4411 PRECR_QB_PH = 1489,
4412 PRECR_SRA_PH_W = 1490,
4413 PRECR_SRA_R_PH_W = 1491,
4414 PREPEND = 1492,
4415 SHRA_QB = 1493,
4416 SHRA_R_QB = 1494,
4417 SHRAV_QB = 1495,
4418 SHRAV_R_QB = 1496,
4419 SHRL_PH = 1497,
4420 SHRLV_PH = 1498,
4421 SUBQH_PH = 1499,
4422 SUBQH_R_PH = 1500,
4423 SUBQH_W = 1501,
4424 SUBQH_R_W = 1502,
4425 SUBU_PH = 1503,
4426 SUBU_S_PH = 1504,
4427 SUBUH_QB = 1505,
4428 SUBUH_R_QB = 1506,
4429 LWDSP_MM = 1507,
4430 SWDSP_MM = 1508,
4431 ABSQ_S_PH_MM = 1509,
4432 ABSQ_S_W_MM = 1510,
4433 ADDQ_PH_MM = 1511,
4434 ADDQ_S_PH_MM = 1512,
4435 ADDQ_S_W_MM = 1513,
4436 ADDSC_MM = 1514,
4437 ADDU_QB_MM = 1515,
4438 ADDU_S_QB_MM = 1516,
4439 ADDWC_MM = 1517,
4440 BITREV_MM = 1518,
4441 BPOSGE32_MM = 1519,
4442 CMPGU_EQ_QB_MM = 1520,
4443 CMPGU_LE_QB_MM = 1521,
4444 CMPGU_LT_QB_MM = 1522,
4445 CMPU_EQ_QB_MM = 1523,
4446 CMPU_LE_QB_MM = 1524,
4447 CMPU_LT_QB_MM = 1525,
4448 CMP_EQ_PH_MM = 1526,
4449 CMP_LE_PH_MM = 1527,
4450 CMP_LT_PH_MM = 1528,
4451 DPAQ_SA_L_W_MM = 1529,
4452 DPAQ_S_W_PH_MM = 1530,
4453 DPAU_H_QBL_MM = 1531,
4454 DPAU_H_QBR_MM = 1532,
4455 DPSQ_SA_L_W_MM = 1533,
4456 DPSQ_S_W_PH_MM = 1534,
4457 DPSU_H_QBL_MM = 1535,
4458 DPSU_H_QBR_MM = 1536,
4459 EXTPDPV_MM = 1537,
4460 EXTPDP_MM = 1538,
4461 EXTPV_MM = 1539,
4462 EXTP_MM = 1540,
4463 EXTRV_RS_W_MM = 1541,
4464 EXTRV_R_W_MM = 1542,
4465 EXTRV_S_H_MM = 1543,
4466 EXTRV_W_MM = 1544,
4467 EXTR_RS_W_MM = 1545,
4468 EXTR_R_W_MM = 1546,
4469 EXTR_S_H_MM = 1547,
4470 EXTR_W_MM = 1548,
4471 INSV_MM = 1549,
4472 LBUX_MM = 1550,
4473 LHX_MM = 1551,
4474 LWX_MM = 1552,
4475 MADDU_DSP_MM = 1553,
4476 MADD_DSP_MM = 1554,
4477 MAQ_SA_W_PHL_MM = 1555,
4478 MAQ_SA_W_PHR_MM = 1556,
4479 MAQ_S_W_PHL_MM = 1557,
4480 MAQ_S_W_PHR_MM = 1558,
4481 MFHI_DSP_MM = 1559,
4482 MFLO_DSP_MM = 1560,
4483 MODSUB_MM = 1561,
4484 MOVEP_MMR6 = 1562,
4485 MOVN_I_MM = 1563,
4486 MOVZ_I_MM = 1564,
4487 MSUBU_DSP_MM = 1565,
4488 MSUB_DSP_MM = 1566,
4489 MTHI_DSP_MM = 1567,
4490 MTHLIP_MM = 1568,
4491 MTLO_DSP_MM = 1569,
4492 MULEQ_S_W_PHL_MM = 1570,
4493 MULEQ_S_W_PHR_MM = 1571,
4494 MULEU_S_PH_QBL_MM = 1572,
4495 MULEU_S_PH_QBR_MM = 1573,
4496 MULQ_RS_PH_MM = 1574,
4497 MULSAQ_S_W_PH_MM = 1575,
4498 MULTU_DSP_MM = 1576,
4499 MULT_DSP_MM = 1577,
4500 PACKRL_PH_MM = 1578,
4501 PICK_PH_MM = 1579,
4502 PICK_QB_MM = 1580,
4503 PRECEQU_PH_QBLA_MM = 1581,
4504 PRECEQU_PH_QBL_MM = 1582,
4505 PRECEQU_PH_QBRA_MM = 1583,
4506 PRECEQU_PH_QBR_MM = 1584,
4507 PRECEQ_W_PHL_MM = 1585,
4508 PRECEQ_W_PHR_MM = 1586,
4509 PRECEU_PH_QBLA_MM = 1587,
4510 PRECEU_PH_QBL_MM = 1588,
4511 PRECEU_PH_QBRA_MM = 1589,
4512 PRECEU_PH_QBR_MM = 1590,
4513 PRECRQU_S_QB_PH_MM = 1591,
4514 PRECRQ_PH_W_MM = 1592,
4515 PRECRQ_QB_PH_MM = 1593,
4516 PRECRQ_RS_PH_W_MM = 1594,
4517 RADDU_W_QB_MM = 1595,
4518 RDDSP_MM = 1596,
4519 REPLV_PH_MM = 1597,
4520 REPLV_QB_MM = 1598,
4521 REPL_PH_MM = 1599,
4522 REPL_QB_MM = 1600,
4523 SHILOV_MM = 1601,
4524 SHILO_MM = 1602,
4525 SHLLV_PH_MM = 1603,
4526 SHLLV_QB_MM = 1604,
4527 SHLLV_S_PH_MM = 1605,
4528 SHLLV_S_W_MM = 1606,
4529 SHLL_PH_MM = 1607,
4530 SHLL_QB_MM = 1608,
4531 SHLL_S_PH_MM = 1609,
4532 SHLL_S_W_MM = 1610,
4533 SHRAV_PH_MM = 1611,
4534 SHRAV_R_PH_MM = 1612,
4535 SHRAV_R_W_MM = 1613,
4536 SHRA_PH_MM = 1614,
4537 SHRA_R_PH_MM = 1615,
4538 SHRA_R_W_MM = 1616,
4539 SHRLV_QB_MM = 1617,
4540 SHRL_QB_MM = 1618,
4541 SUBQ_PH_MM = 1619,
4542 SUBQ_S_PH_MM = 1620,
4543 SUBQ_S_W_MM = 1621,
4544 SUBU_QB_MM = 1622,
4545 SUBU_S_QB_MM = 1623,
4546 WRDSP_MM = 1624,
4547 ABSQ_S_QB_MMR2 = 1625,
4548 ADDQH_PH_MMR2 = 1626,
4549 ADDQH_R_PH_MMR2 = 1627,
4550 ADDQH_R_W_MMR2 = 1628,
4551 ADDQH_W_MMR2 = 1629,
4552 ADDUH_QB_MMR2 = 1630,
4553 ADDUH_R_QB_MMR2 = 1631,
4554 ADDU_PH_MMR2 = 1632,
4555 ADDU_S_PH_MMR2 = 1633,
4556 APPEND_MMR2 = 1634,
4557 BALIGN_MMR2 = 1635,
4558 CMPGDU_EQ_QB_MMR2 = 1636,
4559 CMPGDU_LE_QB_MMR2 = 1637,
4560 CMPGDU_LT_QB_MMR2 = 1638,
4561 DPA_W_PH_MMR2 = 1639,
4562 DPAQX_SA_W_PH_MMR2 = 1640,
4563 DPAQX_S_W_PH_MMR2 = 1641,
4564 DPAX_W_PH_MMR2 = 1642,
4565 DPS_W_PH_MMR2 = 1643,
4566 DPSQX_S_W_PH_MMR2 = 1644,
4567 DPSQX_SA_W_PH_MMR2 = 1645,
4568 DPSX_W_PH_MMR2 = 1646,
4569 MUL_PH_MMR2 = 1647,
4570 MUL_S_PH_MMR2 = 1648,
4571 MULQ_RS_W_MMR2 = 1649,
4572 MULQ_S_PH_MMR2 = 1650,
4573 MULQ_S_W_MMR2 = 1651,
4574 MULSA_W_PH_MMR2 = 1652,
4575 PRECR_QB_PH_MMR2 = 1653,
4576 PRECR_SRA_PH_W_MMR2 = 1654,
4577 PRECR_SRA_R_PH_W_MMR2 = 1655,
4578 PREPEND_MMR2 = 1656,
4579 SHRA_QB_MMR2 = 1657,
4580 SHRA_R_QB_MMR2 = 1658,
4581 SHRAV_QB_MMR2 = 1659,
4582 SHRAV_R_QB_MMR2 = 1660,
4583 SHRL_PH_MMR2 = 1661,
4584 SHRLV_PH_MMR2 = 1662,
4585 SUBQH_PH_MMR2 = 1663,
4586 SUBQH_R_PH_MMR2 = 1664,
4587 SUBQH_W_MMR2 = 1665,
4588 SUBQH_R_W_MMR2 = 1666,
4589 SUBU_PH_MMR2 = 1667,
4590 SUBU_S_PH_MMR2 = 1668,
4591 SUBUH_QB_MMR2 = 1669,
4592 SUBUH_R_QB_MMR2 = 1670,
4593 BPOSGE32C_MMR3 = 1671,
4594 CMP_F_D = 1672,
4595 CMP_F_S = 1673,
4596 CMP_SAF_D = 1674,
4597 CMP_SAF_S = 1675,
4598 CMP_SEQ_D = 1676,
4599 CMP_SEQ_S = 1677,
4600 CMP_SLE_D = 1678,
4601 CMP_SLE_S = 1679,
4602 CMP_SLT_D = 1680,
4603 CMP_SLT_S = 1681,
4604 CMP_SUEQ_D = 1682,
4605 CMP_SUEQ_S = 1683,
4606 CMP_SULE_D = 1684,
4607 CMP_SULE_S = 1685,
4608 CMP_SULT_D = 1686,
4609 CMP_SULT_S = 1687,
4610 CMP_SUN_D = 1688,
4611 CMP_SUN_S = 1689,
4612 SCHED_LIST_END = 1690
4613 };
4614} // end namespace Sched
4615} // end namespace Mips
4616} // end namespace llvm
4617#endif // GET_INSTRINFO_SCHED_ENUM
4618
4619#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
4620namespace llvm {
4621
4622struct MipsInstrTable {
4623 MCInstrDesc Insts[2893];
4624 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
4625 MCOperandInfo OperandInfo[1142];
4626 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
4627 MCPhysReg ImplicitOps[67];
4628};
4629
4630} // end namespace llvm
4631#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
4632
4633#ifdef GET_INSTRINFO_MC_DESC
4634#undef GET_INSTRINFO_MC_DESC
4635namespace llvm {
4636
4637static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
4638static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));
4639
4640extern const MipsInstrTable MipsDescs = {
4641 {
4642 { 2892, 2, 1, 4, 1066, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2892 = YIELD
4643 { 2891, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2891 = XorRxRxRy16
4644 { 2890, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2890 = XORi_MM
4645 { 2889, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2889 = XORi64
4646 { 2888, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2888 = XORi
4647 { 2887, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2887 = XOR_V
4648 { 2886, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2886 = XOR_MMR6
4649 { 2885, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2885 = XOR_MM
4650 { 2884, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2884 = XORI_MMR6
4651 { 2883, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2883 = XORI_B
4652 { 2882, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2882 = XOR64
4653 { 2881, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2881 = XOR16_MMR6
4654 { 2880, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2880 = XOR16_MM
4655 { 2879, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2879 = XOR
4656 { 2878, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #2878 = WSBH_MMR6
4657 { 2877, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2877 = WSBH_MM
4658 { 2876, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2876 = WSBH
4659 { 2875, 2, 1, 4, 1038, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #2875 = WRPGPR_MMR6
4660 { 2874, 2, 0, 4, 1624, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2874 = WRDSP_MM
4661 { 2873, 2, 0, 4, 1458, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2873 = WRDSP
4662 { 2872, 1, 0, 4, 1053, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2872 = WAIT_MMR6
4663 { 2871, 1, 0, 4, 1036, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2871 = WAIT_MM
4664 { 2870, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2870 = WAIT
4665 { 2869, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2869 = VSHF_W
4666 { 2868, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2868 = VSHF_H
4667 { 2867, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #2867 = VSHF_D
4668 { 2866, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #2866 = VSHF_B
4669 { 2865, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 62, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2865 = VMULU
4670 { 2864, 3, 1, 4, 1209, 0, 4, MipsImpOpBase + 42, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2864 = VMM0
4671 { 2863, 3, 1, 4, 1209, 0, 3, MipsImpOpBase + 59, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2863 = V3MULU
4672 { 2862, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2862 = UDIV_MM
4673 { 2861, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2861 = UDIV
4674 { 2860, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2860 = TTLTIU
4675 { 2859, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2859 = TRUNC_W_S_MMR6
4676 { 2858, 2, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2858 = TRUNC_W_S_MM
4677 { 2857, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2857 = TRUNC_W_S
4678 { 2856, 2, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2856 = TRUNC_W_MM
4679 { 2855, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #2855 = TRUNC_W_D_MMR6
4680 { 2854, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #2854 = TRUNC_W_D64
4681 { 2853, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2853 = TRUNC_W_D32
4682 { 2852, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2852 = TRUNC_L_S_MMR6
4683 { 2851, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2851 = TRUNC_L_S
4684 { 2850, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2850 = TRUNC_L_D_MMR6
4685 { 2849, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2849 = TRUNC_L_D64
4686 { 2848, 3, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2848 = TNE_MM
4687 { 2847, 2, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2847 = TNEI_MM
4688 { 2846, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2846 = TNEI
4689 { 2845, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2845 = TNE
4690 { 2844, 3, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2844 = TLT_MM
4691 { 2843, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2843 = TLTU_MM
4692 { 2842, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2842 = TLTU
4693 { 2841, 2, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2841 = TLTI_MM
4694 { 2840, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2840 = TLTIU_MM
4695 { 2839, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2839 = TLTI
4696 { 2838, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2838 = TLT
4697 { 2837, 0, 0, 4, 1031, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2837 = TLBWR_MM
4698 { 2836, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2836 = TLBWR
4699 { 2835, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2835 = TLBWI_MM
4700 { 2834, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2834 = TLBWI
4701 { 2833, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2833 = TLBR_MM
4702 { 2832, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2832 = TLBR
4703 { 2831, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2831 = TLBP_MM
4704 { 2830, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2830 = TLBP
4705 { 2829, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2829 = TLBINV_MMR6
4706 { 2828, 0, 0, 4, 1040, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2828 = TLBINVF_MMR6
4707 { 2827, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2827 = TLBINVF
4708 { 2826, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2826 = TLBINV
4709 { 2825, 0, 0, 4, 1076, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2825 = TLBGWR_MM
4710 { 2824, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2824 = TLBGWR
4711 { 2823, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2823 = TLBGWI_MM
4712 { 2822, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2822 = TLBGWI
4713 { 2821, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2821 = TLBGR_MM
4714 { 2820, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2820 = TLBGR
4715 { 2819, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2819 = TLBGP_MM
4716 { 2818, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2818 = TLBGP
4717 { 2817, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2817 = TLBGINV_MM
4718 { 2816, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2816 = TLBGINVF_MM
4719 { 2815, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2815 = TLBGINVF
4720 { 2814, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2814 = TLBGINV
4721 { 2813, 3, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2813 = TGE_MM
4722 { 2812, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2812 = TGEU_MM
4723 { 2811, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2811 = TGEU
4724 { 2810, 2, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2810 = TGEI_MM
4725 { 2809, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2809 = TGEIU_MM
4726 { 2808, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2808 = TGEIU
4727 { 2807, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2807 = TGEI
4728 { 2806, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2806 = TGE
4729 { 2805, 3, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2805 = TEQ_MM
4730 { 2804, 2, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2804 = TEQI_MM
4731 { 2803, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2803 = TEQI
4732 { 2802, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2802 = TEQ
4733 { 2801, 3, 0, 4, 1118, 0, 0, MipsImpOpBase + 0, 585, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2801 = SwRxSpImmX16
4734 { 2800, 3, 0, 4, 1118, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2800 = SwRxRyOffMemX16
4735 { 2799, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2799 = SubuRxRyRz16
4736 { 2798, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0, 0x0ULL }, // Inst #2798 = SrlvRxRy16
4737 { 2797, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 532, 0, 0x0ULL }, // Inst #2797 = SrlX16
4738 { 2796, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0, 0x0ULL }, // Inst #2796 = SravRxRy16
4739 { 2795, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 532, 0, 0x0ULL }, // Inst #2795 = SraX16
4740 { 2794, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2794 = SltuRxRy16
4741 { 2793, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2793 = SltiuRxImmX16
4742 { 2792, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2792 = SltiuRxImm16
4743 { 2791, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2791 = SltiRxImmX16
4744 { 2790, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2790 = SltiRxImm16
4745 { 2789, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2789 = SltRxRy16
4746 { 2788, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0, 0x0ULL }, // Inst #2788 = SllvRxRy16
4747 { 2787, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 532, 0, 0x0ULL }, // Inst #2787 = SllX16
4748 { 2786, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2786 = ShRxRyOffMemX16
4749 { 2785, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1140, 0, 0x0ULL }, // Inst #2785 = SehRx16
4750 { 2784, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1140, 0, 0x0ULL }, // Inst #2784 = SebRx16
4751 { 2783, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2783 = SbRxRyOffMemX16
4752 { 2782, 0, 0, 2, 1115, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2782 = SaveX16
4753 { 2781, 0, 0, 2, 1115, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2781 = Save16
4754 { 2780, 1, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2780 = SYSCALL_MM
4755 { 2779, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2779 = SYSCALL
4756 { 2778, 1, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2778 = SYNC_MMR6
4757 { 2777, 1, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2777 = SYNC_MM
4758 { 2776, 2, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2776 = SYNCI_MMR6
4759 { 2775, 2, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2775 = SYNCI_MM
4760 { 2774, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2774 = SYNCI
4761 { 2773, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2773 = SYNC
4762 { 2772, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2772 = SW_MMR6
4763 { 2771, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2771 = SW_MM
4764 { 2770, 3, 0, 4, 1294, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2770 = SWXC1_MM
4765 { 2769, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2769 = SWXC1
4766 { 2768, 3, 0, 2, 1157, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2768 = SWSP_MMR6
4767 { 2767, 3, 0, 2, 1134, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2767 = SWSP_MM
4768 { 2766, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2766 = SWR_MM
4769 { 2765, 3, 0, 4, 1105, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2765 = SWRE_MM
4770 { 2764, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2764 = SWRE
4771 { 2763, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2763 = SWR64
4772 { 2762, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2762 = SWR
4773 { 2761, 4, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 916, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2761 = SWP_MM
4774 { 2760, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2760 = SWM32_MM
4775 { 2759, 3, 0, 2, 1159, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2759 = SWM16_MMR6
4776 { 2758, 3, 0, 2, 1136, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2758 = SWM16_MM
4777 { 2757, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2757 = SWL_MM
4778 { 2756, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2756 = SWLE_MM
4779 { 2755, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2755 = SWLE
4780 { 2754, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2754 = SWL64
4781 { 2753, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2753 = SWL
4782 { 2752, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2752 = SWE_MM
4783 { 2751, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2751 = SWE
4784 { 2750, 3, 0, 4, 1508, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2750 = SWDSP_MM
4785 { 2749, 3, 0, 4, 1343, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2749 = SWDSP
4786 { 2748, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2748 = SWC3
4787 { 2747, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2747 = SWC2_R6
4788 { 2746, 3, 0, 4, 1158, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2746 = SWC2_MMR6
4789 { 2745, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2745 = SWC2
4790 { 2744, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2744 = SWC1_MM
4791 { 2743, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2743 = SWC1
4792 { 2742, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2742 = SW64
4793 { 2741, 3, 0, 2, 1157, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2741 = SW16_MMR6
4794 { 2740, 3, 0, 2, 1134, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2740 = SW16_MM
4795 { 2739, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2739 = SW
4796 { 2738, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2738 = SUXC1_MM
4797 { 2737, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2737 = SUXC164
4798 { 2736, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2736 = SUXC1
4799 { 2735, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2735 = SUBu_MM
4800 { 2734, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2734 = SUBu
4801 { 2733, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2733 = SUB_MMR6
4802 { 2732, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2732 = SUB_MM
4803 { 2731, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2731 = SUBV_W
4804 { 2730, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2730 = SUBV_H
4805 { 2729, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2729 = SUBV_D
4806 { 2728, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2728 = SUBV_B
4807 { 2727, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2727 = SUBVI_W
4808 { 2726, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2726 = SUBVI_H
4809 { 2725, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2725 = SUBVI_D
4810 { 2724, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2724 = SUBVI_B
4811 { 2723, 3, 1, 4, 1623, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2723 = SUBU_S_QB_MM
4812 { 2722, 3, 1, 4, 1457, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2722 = SUBU_S_QB
4813 { 2721, 3, 1, 4, 1668, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2721 = SUBU_S_PH_MMR2
4814 { 2720, 3, 1, 4, 1504, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2720 = SUBU_S_PH
4815 { 2719, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2719 = SUBU_QB_MM
4816 { 2718, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2718 = SUBU_QB
4817 { 2717, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2717 = SUBU_PH_MMR2
4818 { 2716, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2716 = SUBU_PH
4819 { 2715, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2715 = SUBU_MMR6
4820 { 2714, 3, 1, 4, 1670, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2714 = SUBUH_R_QB_MMR2
4821 { 2713, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2713 = SUBUH_R_QB
4822 { 2712, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2712 = SUBUH_QB_MMR2
4823 { 2711, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2711 = SUBUH_QB
4824 { 2710, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 554, 0, 0x0ULL }, // Inst #2710 = SUBU16_MMR6
4825 { 2709, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 554, 0, 0x0ULL }, // Inst #2709 = SUBU16_MM
4826 { 2708, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2708 = SUBS_U_W
4827 { 2707, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2707 = SUBS_U_H
4828 { 2706, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2706 = SUBS_U_D
4829 { 2705, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2705 = SUBS_U_B
4830 { 2704, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2704 = SUBS_S_W
4831 { 2703, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2703 = SUBS_S_H
4832 { 2702, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2702 = SUBS_S_D
4833 { 2701, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2701 = SUBS_S_B
4834 { 2700, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2700 = SUBSUU_S_W
4835 { 2699, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2699 = SUBSUU_S_H
4836 { 2698, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2698 = SUBSUU_S_D
4837 { 2697, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2697 = SUBSUU_S_B
4838 { 2696, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2696 = SUBSUS_U_W
4839 { 2695, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2695 = SUBSUS_U_H
4840 { 2694, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2694 = SUBSUS_U_D
4841 { 2693, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2693 = SUBSUS_U_B
4842 { 2692, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2692 = SUBQ_S_W_MM
4843 { 2691, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2691 = SUBQ_S_W
4844 { 2690, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2690 = SUBQ_S_PH_MM
4845 { 2689, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2689 = SUBQ_S_PH
4846 { 2688, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2688 = SUBQ_PH_MM
4847 { 2687, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2687 = SUBQ_PH
4848 { 2686, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2686 = SUBQH_W_MMR2
4849 { 2685, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2685 = SUBQH_W
4850 { 2684, 3, 1, 4, 1666, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2684 = SUBQH_R_W_MMR2
4851 { 2683, 3, 1, 4, 1502, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2683 = SUBQH_R_W
4852 { 2682, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2682 = SUBQH_R_PH_MMR2
4853 { 2681, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2681 = SUBQH_R_PH
4854 { 2680, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2680 = SUBQH_PH_MMR2
4855 { 2679, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2679 = SUBQH_PH
4856 { 2678, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2678 = SUB
4857 { 2677, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2677 = ST_W
4858 { 2676, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2676 = ST_H
4859 { 2675, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 885, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2675 = ST_D
4860 { 2674, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 882, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2674 = ST_B
4861 { 2673, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2673 = SSNOP_MMR6
4862 { 2672, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2672 = SSNOP_MM
4863 { 2671, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2671 = SSNOP
4864 { 2670, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2670 = SRL_W
4865 { 2669, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2669 = SRL_MM
4866 { 2668, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2668 = SRL_H
4867 { 2667, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2667 = SRL_D
4868 { 2666, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2666 = SRL_B
4869 { 2665, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2665 = SRLV_MM
4870 { 2664, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2664 = SRLV
4871 { 2663, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2663 = SRLR_W
4872 { 2662, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2662 = SRLR_H
4873 { 2661, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2661 = SRLR_D
4874 { 2660, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2660 = SRLR_B
4875 { 2659, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2659 = SRLRI_W
4876 { 2658, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2658 = SRLRI_H
4877 { 2657, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2657 = SRLRI_D
4878 { 2656, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2656 = SRLRI_B
4879 { 2655, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2655 = SRLI_W
4880 { 2654, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2654 = SRLI_H
4881 { 2653, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2653 = SRLI_D
4882 { 2652, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2652 = SRLI_B
4883 { 2651, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2651 = SRL16_MMR6
4884 { 2650, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #2650 = SRL16_MM
4885 { 2649, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2649 = SRL
4886 { 2648, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2648 = SRA_W
4887 { 2647, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2647 = SRA_MM
4888 { 2646, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2646 = SRA_H
4889 { 2645, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2645 = SRA_D
4890 { 2644, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2644 = SRA_B
4891 { 2643, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2643 = SRAV_MM
4892 { 2642, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2642 = SRAV
4893 { 2641, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2641 = SRAR_W
4894 { 2640, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2640 = SRAR_H
4895 { 2639, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2639 = SRAR_D
4896 { 2638, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2638 = SRAR_B
4897 { 2637, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2637 = SRARI_W
4898 { 2636, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2636 = SRARI_H
4899 { 2635, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2635 = SRARI_D
4900 { 2634, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2634 = SRARI_B
4901 { 2633, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2633 = SRAI_W
4902 { 2632, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2632 = SRAI_H
4903 { 2631, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2631 = SRAI_D
4904 { 2630, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2630 = SRAI_B
4905 { 2629, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2629 = SRA
4906 { 2628, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1135, 0, 0x6ULL }, // Inst #2628 = SPLAT_W
4907 { 2627, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1132, 0, 0x6ULL }, // Inst #2627 = SPLAT_H
4908 { 2626, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1129, 0, 0x6ULL }, // Inst #2626 = SPLAT_D
4909 { 2625, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1126, 0, 0x6ULL }, // Inst #2625 = SPLAT_B
4910 { 2624, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2624 = SPLATI_W
4911 { 2623, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2623 = SPLATI_H
4912 { 2622, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2622 = SPLATI_D
4913 { 2621, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2621 = SPLATI_B
4914 { 2620, 3, 1, 4, 1208, 0, 0, MipsImpOpBase + 0, 232, 0, 0x2ULL }, // Inst #2620 = SNEi
4915 { 2619, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 235, 0, 0x1ULL }, // Inst #2619 = SNE
4916 { 2618, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2618 = SLTu_MM
4917 { 2617, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1120, 0, 0x1ULL }, // Inst #2617 = SLTu64
4918 { 2616, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2616 = SLTu
4919 { 2615, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2615 = SLTiu_MM
4920 { 2614, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1123, 0, 0x2ULL }, // Inst #2614 = SLTiu64
4921 { 2613, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2613 = SLTiu
4922 { 2612, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2612 = SLTi_MM
4923 { 2611, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1123, 0, 0x2ULL }, // Inst #2611 = SLTi64
4924 { 2610, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2610 = SLTi
4925 { 2609, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2609 = SLT_MM
4926 { 2608, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1120, 0, 0x1ULL }, // Inst #2608 = SLT64
4927 { 2607, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2607 = SLT
4928 { 2606, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2606 = SLL_W
4929 { 2605, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2605 = SLL_MMR6
4930 { 2604, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2604 = SLL_MM
4931 { 2603, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2603 = SLL_H
4932 { 2602, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2602 = SLL_D
4933 { 2601, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2601 = SLL_B
4934 { 2600, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2600 = SLLV_MM
4935 { 2599, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2599 = SLLV
4936 { 2598, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2598 = SLLI_W
4937 { 2597, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2597 = SLLI_H
4938 { 2596, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2596 = SLLI_D
4939 { 2595, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2595 = SLLI_B
4940 { 2594, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2594 = SLL64_64
4941 { 2593, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 758, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2593 = SLL64_32
4942 { 2592, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2592 = SLL16_MMR6
4943 { 2591, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #2591 = SLL16_MM
4944 { 2590, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2590 = SLL
4945 { 2589, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2589 = SLD_W
4946 { 2588, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1112, 0, 0x6ULL }, // Inst #2588 = SLD_H
4947 { 2587, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1108, 0, 0x6ULL }, // Inst #2587 = SLD_D
4948 { 2586, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x6ULL }, // Inst #2586 = SLD_B
4949 { 2585, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 614, 0, 0x6ULL }, // Inst #2585 = SLDI_W
4950 { 2584, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 610, 0, 0x6ULL }, // Inst #2584 = SLDI_H
4951 { 2583, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #2583 = SLDI_D
4952 { 2582, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2582 = SLDI_B
4953 { 2581, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2581 = SIGRIE_MMR6
4954 { 2580, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2580 = SIGRIE
4955 { 2579, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2579 = SH_MMR6
4956 { 2578, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2578 = SH_MM
4957 { 2577, 3, 1, 4, 1618, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2577 = SHRL_QB_MM
4958 { 2576, 3, 1, 4, 1452, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2576 = SHRL_QB
4959 { 2575, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2575 = SHRL_PH_MMR2
4960 { 2574, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2574 = SHRL_PH
4961 { 2573, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2573 = SHRLV_QB_MM
4962 { 2572, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2572 = SHRLV_QB
4963 { 2571, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2571 = SHRLV_PH_MMR2
4964 { 2570, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2570 = SHRLV_PH
4965 { 2569, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2569 = SHRA_R_W_MM
4966 { 2568, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2568 = SHRA_R_W
4967 { 2567, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2567 = SHRA_R_QB_MMR2
4968 { 2566, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2566 = SHRA_R_QB
4969 { 2565, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2565 = SHRA_R_PH_MM
4970 { 2564, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2564 = SHRA_R_PH
4971 { 2563, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2563 = SHRA_QB_MMR2
4972 { 2562, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2562 = SHRA_QB
4973 { 2561, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2561 = SHRA_PH_MM
4974 { 2560, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2560 = SHRA_PH
4975 { 2559, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2559 = SHRAV_R_W_MM
4976 { 2558, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2558 = SHRAV_R_W
4977 { 2557, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2557 = SHRAV_R_QB_MMR2
4978 { 2556, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2556 = SHRAV_R_QB
4979 { 2555, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2555 = SHRAV_R_PH_MM
4980 { 2554, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2554 = SHRAV_R_PH
4981 { 2553, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2553 = SHRAV_QB_MMR2
4982 { 2552, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2552 = SHRAV_QB
4983 { 2551, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2551 = SHRAV_PH_MM
4984 { 2550, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2550 = SHRAV_PH
4985 { 2549, 3, 1, 4, 1610, 0, 1, MipsImpOpBase + 58, 241, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2549 = SHLL_S_W_MM
4986 { 2548, 3, 1, 4, 1444, 0, 1, MipsImpOpBase + 58, 241, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2548 = SHLL_S_W
4987 { 2547, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2547 = SHLL_S_PH_MM
4988 { 2546, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2546 = SHLL_S_PH
4989 { 2545, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2545 = SHLL_QB_MM
4990 { 2544, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2544 = SHLL_QB
4991 { 2543, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2543 = SHLL_PH_MM
4992 { 2542, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2542 = SHLL_PH
4993 { 2541, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2541 = SHLLV_S_W_MM
4994 { 2540, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2540 = SHLLV_S_W
4995 { 2539, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2539 = SHLLV_S_PH_MM
4996 { 2538, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2538 = SHLLV_S_PH
4997 { 2537, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2537 = SHLLV_QB_MM
4998 { 2536, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2536 = SHLLV_QB
4999 { 2535, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2535 = SHLLV_PH_MM
5000 { 2534, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2534 = SHLLV_PH
5001 { 2533, 3, 1, 4, 1602, 0, 0, MipsImpOpBase + 0, 1095, 0, 0x6ULL }, // Inst #2533 = SHILO_MM
5002 { 2532, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1037, 0, 0x6ULL }, // Inst #2532 = SHILOV_MM
5003 { 2531, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1037, 0, 0x6ULL }, // Inst #2531 = SHILOV
5004 { 2530, 3, 1, 4, 1436, 0, 0, MipsImpOpBase + 0, 1095, 0, 0x6ULL }, // Inst #2530 = SHILO
5005 { 2529, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2529 = SHF_W
5006 { 2528, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2528 = SHF_H
5007 { 2527, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2527 = SHF_B
5008 { 2526, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2526 = SHE_MM
5009 { 2525, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2525 = SHE
5010 { 2524, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2524 = SH64
5011 { 2523, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2523 = SH16_MMR6
5012 { 2522, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2522 = SH16_MM
5013 { 2521, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2521 = SH
5014 { 2520, 3, 1, 4, 1208, 0, 0, MipsImpOpBase + 0, 232, 0, 0x2ULL }, // Inst #2520 = SEQi
5015 { 2519, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 235, 0, 0x1ULL }, // Inst #2519 = SEQ
5016 { 2518, 4, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 1091, 0, 0x6ULL }, // Inst #2518 = SEL_S_MMR6
5017 { 2517, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 1091, 0, 0x6ULL }, // Inst #2517 = SEL_S
5018 { 2516, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 932, 0, 0x6ULL }, // Inst #2516 = SEL_D_MMR6
5019 { 2515, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 932, 0, 0x6ULL }, // Inst #2515 = SEL_D
5020 { 2514, 3, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2514 = SELNEZ_S_MMR6
5021 { 2513, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2513 = SELNEZ_S
5022 { 2512, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2512 = SELNEZ_MMR6
5023 { 2511, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2511 = SELNEZ_D_MMR6
5024 { 2510, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2510 = SELNEZ_D
5025 { 2509, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #2509 = SELNEZ64
5026 { 2508, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2508 = SELNEZ
5027 { 2507, 3, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2507 = SELEQZ_S_MMR6
5028 { 2506, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2506 = SELEQZ_S
5029 { 2505, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2505 = SELEQZ_MMR6
5030 { 2504, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2504 = SELEQZ_D_MMR6
5031 { 2503, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2503 = SELEQZ_D
5032 { 2502, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #2502 = SELEQZ64
5033 { 2501, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2501 = SELEQZ
5034 { 2500, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2500 = SEH_MM
5035 { 2499, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #2499 = SEH64
5036 { 2498, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2498 = SEH
5037 { 2497, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2497 = SEB_MM
5038 { 2496, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #2496 = SEB64
5039 { 2495, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2495 = SEB
5040 { 2494, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2494 = SDXC164
5041 { 2493, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2493 = SDXC1
5042 { 2492, 3, 0, 4, 1184, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2492 = SDR
5043 { 2491, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2491 = SDL
5044 { 2490, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2490 = SDIV_MM
5045 { 2489, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2489 = SDIV
5046 { 2488, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2488 = SDC3
5047 { 2487, 3, 0, 4, 1086, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2487 = SDC2_R6
5048 { 2486, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2486 = SDC2_MMR6
5049 { 2485, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2485 = SDC2
5050 { 2484, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2484 = SDC1_MM_D64
5051 { 2483, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2483 = SDC1_MM_D32
5052 { 2482, 3, 0, 4, 1339, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2482 = SDC1_D64_MMR6
5053 { 2481, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2481 = SDC164
5054 { 2480, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2480 = SDC1
5055 { 2479, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2479 = SDBBP_R6
5056 { 2478, 1, 0, 4, 1009, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2478 = SDBBP_MMR6
5057 { 2477, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2477 = SDBBP_MM
5058 { 2476, 1, 0, 2, 1009, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2476 = SDBBP16_MMR6
5059 { 2475, 1, 0, 2, 968, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2475 = SDBBP16_MM
5060 { 2474, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2474 = SDBBP
5061 { 2473, 3, 0, 4, 1176, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2473 = SD
5062 { 2472, 4, 1, 4, 1087, 0, 0, MipsImpOpBase + 0, 1079, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2472 = SC_R6
5063 { 2471, 4, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2471 = SC_MMR6
5064 { 2470, 4, 1, 4, 1132, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2470 = SC_MM
5065 { 2469, 4, 1, 4, 1106, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2469 = SCE_MM
5066 { 2468, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2468 = SCE
5067 { 2467, 4, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 1087, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2467 = SCD_R6
5068 { 2466, 4, 1, 4, 1177, 0, 0, MipsImpOpBase + 0, 1083, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2466 = SCD
5069 { 2465, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1079, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2465 = SC64_R6
5070 { 2464, 4, 1, 4, 1177, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2464 = SC64
5071 { 2463, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2463 = SC
5072 { 2462, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2462 = SB_MMR6
5073 { 2461, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2461 = SB_MM
5074 { 2460, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2460 = SBE_MM
5075 { 2459, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2459 = SBE
5076 { 2458, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2458 = SB64
5077 { 2457, 3, 0, 2, 1154, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2457 = SB16_MMR6
5078 { 2456, 3, 0, 2, 1131, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2456 = SB16_MM
5079 { 2455, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2455 = SB
5080 { 2454, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2454 = SAT_U_W
5081 { 2453, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2453 = SAT_U_H
5082 { 2452, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2452 = SAT_U_D
5083 { 2451, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2451 = SAT_U_B
5084 { 2450, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2450 = SAT_S_W
5085 { 2449, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2449 = SAT_S_H
5086 { 2448, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2448 = SAT_S_D
5087 { 2447, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2447 = SAT_S_B
5088 { 2446, 2, 0, 4, 1211, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2446 = SAAD
5089 { 2445, 2, 0, 4, 1211, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2445 = SAA
5090 { 2444, 0, 0, 2, 1109, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2444 = RestoreX16
5091 { 2443, 0, 0, 2, 1109, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2443 = Restore16
5092 { 2442, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2442 = RSQRT_S_MM
5093 { 2441, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2441 = RSQRT_S
5094 { 2440, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2440 = RSQRT_D64_MM
5095 { 2439, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2439 = RSQRT_D64
5096 { 2438, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2438 = RSQRT_D32_MM
5097 { 2437, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2437 = RSQRT_D32
5098 { 2436, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2436 = ROUND_W_S_MMR6
5099 { 2435, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2435 = ROUND_W_S_MM
5100 { 2434, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2434 = ROUND_W_S
5101 { 2433, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2433 = ROUND_W_MM
5102 { 2432, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2432 = ROUND_W_D_MMR6
5103 { 2431, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #2431 = ROUND_W_D64
5104 { 2430, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2430 = ROUND_W_D32
5105 { 2429, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2429 = ROUND_L_S_MMR6
5106 { 2428, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2428 = ROUND_L_S
5107 { 2427, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2427 = ROUND_L_D_MMR6
5108 { 2426, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2426 = ROUND_L_D64
5109 { 2425, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2425 = ROTR_MM
5110 { 2424, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2424 = ROTRV_MM
5111 { 2423, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2423 = ROTRV
5112 { 2422, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2422 = ROTR
5113 { 2421, 2, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2421 = RINT_S_MMR6
5114 { 2420, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2420 = RINT_S
5115 { 2419, 2, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2419 = RINT_D_MMR6
5116 { 2418, 2, 1, 4, 1231, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2418 = RINT_D
5117 { 2417, 2, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2417 = REPL_QB_MM
5118 { 2416, 2, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2416 = REPL_QB
5119 { 2415, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2415 = REPL_PH_MM
5120 { 2414, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2414 = REPL_PH
5121 { 2413, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2413 = REPLV_QB_MM
5122 { 2412, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2412 = REPLV_QB
5123 { 2411, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2411 = REPLV_PH_MM
5124 { 2410, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2410 = REPLV_PH
5125 { 2409, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2409 = RECIP_S_MM
5126 { 2408, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2408 = RECIP_S
5127 { 2407, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2407 = RECIP_D64_MM
5128 { 2406, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2406 = RECIP_D64
5129 { 2405, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2405 = RECIP_D32_MM
5130 { 2404, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2404 = RECIP_D32
5131 { 2403, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2403 = RDPGPR_MMR6
5132 { 2402, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2402 = RDHWR_MMR6
5133 { 2401, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2401 = RDHWR_MM
5134 { 2400, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1065, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2400 = RDHWR64
5135 { 2399, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2399 = RDHWR
5136 { 2398, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2398 = RDDSP_MM
5137 { 2397, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2397 = RDDSP
5138 { 2396, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2396 = RADDU_W_QB_MM
5139 { 2395, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2395 = RADDU_W_QB
5140 { 2394, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2394 = PUU_PS64
5141 { 2393, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2393 = PUL_PS64
5142 { 2392, 4, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #2392 = PREPEND_MMR2
5143 { 2391, 4, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #2391 = PREPEND
5144 { 2390, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2390 = PREF_R6
5145 { 2389, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2389 = PREF_MMR6
5146 { 2388, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2388 = PREF_MM
5147 { 2387, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 1059, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2387 = PREFX_MM
5148 { 2386, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2386 = PREFE_MM
5149 { 2385, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2385 = PREFE
5150 { 2384, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2384 = PREF
5151 { 2383, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2383 = PRECR_SRA_R_PH_W_MMR2
5152 { 2382, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2382 = PRECR_SRA_R_PH_W
5153 { 2381, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2381 = PRECR_SRA_PH_W_MMR2
5154 { 2380, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2380 = PRECR_SRA_PH_W
5155 { 2379, 3, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2379 = PRECR_QB_PH_MMR2
5156 { 2378, 3, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2378 = PRECR_QB_PH
5157 { 2377, 3, 1, 4, 1594, 0, 1, MipsImpOpBase + 58, 1052, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2377 = PRECRQ_RS_PH_W_MM
5158 { 2376, 3, 1, 4, 1428, 0, 1, MipsImpOpBase + 58, 1052, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2376 = PRECRQ_RS_PH_W
5159 { 2375, 3, 1, 4, 1593, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2375 = PRECRQ_QB_PH_MM
5160 { 2374, 3, 1, 4, 1427, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2374 = PRECRQ_QB_PH
5161 { 2373, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2373 = PRECRQ_PH_W_MM
5162 { 2372, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2372 = PRECRQ_PH_W
5163 { 2371, 3, 1, 4, 1591, 0, 1, MipsImpOpBase + 58, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2371 = PRECRQU_S_QB_PH_MM
5164 { 2370, 3, 1, 4, 1425, 0, 1, MipsImpOpBase + 58, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2370 = PRECRQU_S_QB_PH
5165 { 2369, 2, 1, 4, 1590, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2369 = PRECEU_PH_QBR_MM
5166 { 2368, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2368 = PRECEU_PH_QBRA_MM
5167 { 2367, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2367 = PRECEU_PH_QBRA
5168 { 2366, 2, 1, 4, 1424, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2366 = PRECEU_PH_QBR
5169 { 2365, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2365 = PRECEU_PH_QBL_MM
5170 { 2364, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2364 = PRECEU_PH_QBLA_MM
5171 { 2363, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2363 = PRECEU_PH_QBLA
5172 { 2362, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2362 = PRECEU_PH_QBL
5173 { 2361, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2361 = PRECEQ_W_PHR_MM
5174 { 2360, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2360 = PRECEQ_W_PHR
5175 { 2359, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2359 = PRECEQ_W_PHL_MM
5176 { 2358, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2358 = PRECEQ_W_PHL
5177 { 2357, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2357 = PRECEQU_PH_QBR_MM
5178 { 2356, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2356 = PRECEQU_PH_QBRA_MM
5179 { 2355, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2355 = PRECEQU_PH_QBRA
5180 { 2354, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2354 = PRECEQU_PH_QBR
5181 { 2353, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2353 = PRECEQU_PH_QBL_MM
5182 { 2352, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2352 = PRECEQU_PH_QBLA_MM
5183 { 2351, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2351 = PRECEQU_PH_QBLA
5184 { 2350, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2350 = PRECEQU_PH_QBL
5185 { 2349, 2, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2349 = POP
5186 { 2348, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2348 = PLU_PS64
5187 { 2347, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2347 = PLL_PS64
5188 { 2346, 3, 1, 4, 1580, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2346 = PICK_QB_MM
5189 { 2345, 3, 1, 4, 1414, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2345 = PICK_QB
5190 { 2344, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2344 = PICK_PH_MM
5191 { 2343, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2343 = PICK_PH
5192 { 2342, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #2342 = PCNT_W
5193 { 2341, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1046, 0, 0x6ULL }, // Inst #2341 = PCNT_H
5194 { 2340, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #2340 = PCNT_D
5195 { 2339, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 968, 0, 0x6ULL }, // Inst #2339 = PCNT_B
5196 { 2338, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2338 = PCKOD_W
5197 { 2337, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2337 = PCKOD_H
5198 { 2336, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2336 = PCKOD_D
5199 { 2335, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2335 = PCKOD_B
5200 { 2334, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2334 = PCKEV_W
5201 { 2333, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2333 = PCKEV_H
5202 { 2332, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2332 = PCKEV_D
5203 { 2331, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2331 = PCKEV_B
5204 { 2330, 0, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2330 = PAUSE_MMR6
5205 { 2329, 0, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2329 = PAUSE_MM
5206 { 2328, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2328 = PAUSE
5207 { 2327, 3, 1, 4, 1578, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2327 = PACKRL_PH_MM
5208 { 2326, 3, 1, 4, 1412, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2326 = PACKRL_PH
5209 { 2325, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2325 = OrRxRxRy16
5210 { 2324, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2324 = ORi_MM
5211 { 2323, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2323 = ORi64
5212 { 2322, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2322 = ORi
5213 { 2321, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2321 = OR_V
5214 { 2320, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2320 = OR_MMR6
5215 { 2319, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2319 = OR_MM
5216 { 2318, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2318 = ORI_MMR6
5217 { 2317, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2317 = ORI_B
5218 { 2316, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2316 = OR64
5219 { 2315, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2315 = OR16_MMR6
5220 { 2314, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2314 = OR16_MM
5221 { 2313, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2313 = OR
5222 { 2312, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2312 = NotRxRy16
5223 { 2311, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2311 = NegRxRy16
5224 { 2310, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1048, 0, 0x0ULL }, // Inst #2310 = NOT16_MMR6
5225 { 2309, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1048, 0, 0x0ULL }, // Inst #2309 = NOT16_MM
5226 { 2308, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2308 = NOR_V
5227 { 2307, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2307 = NOR_MMR6
5228 { 2306, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2306 = NOR_MM
5229 { 2305, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2305 = NORI_B
5230 { 2304, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2304 = NOR64
5231 { 2303, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2303 = NOR
5232 { 2302, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2302 = NMSUB_S_MM
5233 { 2301, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2301 = NMSUB_S
5234 { 2300, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2300 = NMSUB_D64
5235 { 2299, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2299 = NMSUB_D32_MM
5236 { 2298, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2298 = NMSUB_D32
5237 { 2297, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2297 = NMADD_S_MM
5238 { 2296, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2296 = NMADD_S
5239 { 2295, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2295 = NMADD_D64
5240 { 2294, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2294 = NMADD_D32_MM
5241 { 2293, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2293 = NMADD_D32
5242 { 2292, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #2292 = NLZC_W
5243 { 2291, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1046, 0, 0x6ULL }, // Inst #2291 = NLZC_H
5244 { 2290, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #2290 = NLZC_D
5245 { 2289, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 968, 0, 0x6ULL }, // Inst #2289 = NLZC_B
5246 { 2288, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #2288 = NLOC_W
5247 { 2287, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1046, 0, 0x6ULL }, // Inst #2287 = NLOC_H
5248 { 2286, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #2286 = NLOC_D
5249 { 2285, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 968, 0, 0x6ULL }, // Inst #2285 = NLOC_B
5250 { 2284, 0, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2284 = NAL
5251 { 2283, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1044, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2283 = MoveR3216
5252 { 2282, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1042, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2282 = Move32R16
5253 { 2281, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 845, 0, 0x0ULL }, // Inst #2281 = Mflo16
5254 { 2280, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 845, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2280 = Mfhi16
5255 { 2279, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2279 = MUL_S_PH_MMR2
5256 { 2278, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2278 = MUL_S_PH
5257 { 2277, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2277 = MUL_R6
5258 { 2276, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2276 = MUL_Q_W
5259 { 2275, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2275 = MUL_Q_H
5260 { 2274, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2274 = MUL_PH_MMR2
5261 { 2273, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2273 = MUL_PH
5262 { 2272, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2272 = MUL_MMR6
5263 { 2271, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2271 = MUL_MM
5264 { 2270, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2270 = MULV_W
5265 { 2269, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2269 = MULV_H
5266 { 2268, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2268 = MULV_D
5267 { 2267, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2267 = MULV_B
5268 { 2266, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2266 = MULU_MMR6
5269 { 2265, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2265 = MULU
5270 { 2264, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2264 = MULTu_MM
5271 { 2263, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2263 = MULTu
5272 { 2262, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2262 = MULT_MM
5273 { 2261, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2261 = MULT_DSP_MM
5274 { 2260, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2260 = MULT_DSP
5275 { 2259, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2259 = MULTU_DSP_MM
5276 { 2258, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2258 = MULTU_DSP
5277 { 2257, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2257 = MULT
5278 { 2256, 4, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2256 = MULSA_W_PH_MMR2
5279 { 2255, 4, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2255 = MULSA_W_PH
5280 { 2254, 4, 1, 4, 1575, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2254 = MULSAQ_S_W_PH_MM
5281 { 2253, 4, 1, 4, 1409, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2253 = MULSAQ_S_W_PH
5282 { 2252, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2252 = MULR_Q_W
5283 { 2251, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2251 = MULR_Q_H
5284 { 2250, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2250 = MULR_PS64
5285 { 2249, 3, 1, 4, 1651, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2249 = MULQ_S_W_MMR2
5286 { 2248, 3, 1, 4, 1487, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2248 = MULQ_S_W
5287 { 2247, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2247 = MULQ_S_PH_MMR2
5288 { 2246, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2246 = MULQ_S_PH
5289 { 2245, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2245 = MULQ_RS_W_MMR2
5290 { 2244, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2244 = MULQ_RS_W
5291 { 2243, 3, 1, 4, 1574, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2243 = MULQ_RS_PH_MM
5292 { 2242, 3, 1, 4, 1408, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2242 = MULQ_RS_PH
5293 { 2241, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2241 = MULEU_S_PH_QBR_MM
5294 { 2240, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2240 = MULEU_S_PH_QBR
5295 { 2239, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2239 = MULEU_S_PH_QBL_MM
5296 { 2238, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2238 = MULEU_S_PH_QBL
5297 { 2237, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2237 = MULEQ_S_W_PHR_MM
5298 { 2236, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2236 = MULEQ_S_W_PHR
5299 { 2235, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2235 = MULEQ_S_W_PHL_MM
5300 { 2234, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2234 = MULEQ_S_W_PHL
5301 { 2233, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2233 = MUL
5302 { 2232, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2232 = MUH_MMR6
5303 { 2231, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2231 = MUHU_MMR6
5304 { 2230, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2230 = MUHU
5305 { 2229, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2229 = MUH
5306 { 2228, 5, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 959, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2228 = MTTR
5307 { 2227, 1, 0, 4, 1206, 0, 1, MipsImpOpBase + 56, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2227 = MTP2
5308 { 2226, 1, 0, 4, 1206, 0, 1, MipsImpOpBase + 55, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2226 = MTP1
5309 { 2225, 1, 0, 4, 1206, 0, 1, MipsImpOpBase + 54, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2225 = MTP0
5310 { 2224, 1, 0, 4, 1206, 0, 4, MipsImpOpBase + 50, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2224 = MTM2
5311 { 2223, 1, 0, 4, 1206, 0, 4, MipsImpOpBase + 46, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2223 = MTM1
5312 { 2222, 1, 0, 4, 1206, 0, 4, MipsImpOpBase + 42, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2222 = MTM0
5313 { 2221, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2221 = MTLO_MM
5314 { 2220, 2, 1, 4, 1569, 0, 0, MipsImpOpBase + 0, 1040, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2220 = MTLO_DSP_MM
5315 { 2219, 2, 1, 4, 1357, 0, 0, MipsImpOpBase + 0, 1040, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2219 = MTLO_DSP
5316 { 2218, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2218 = MTLO64
5317 { 2217, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2217 = MTLO
5318 { 2216, 3, 1, 4, 1568, 0, 1, MipsImpOpBase + 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2216 = MTHLIP_MM
5319 { 2215, 3, 1, 4, 1355, 0, 1, MipsImpOpBase + 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2215 = MTHLIP
5320 { 2214, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2214 = MTHI_MM
5321 { 2213, 2, 1, 4, 1567, 0, 0, MipsImpOpBase + 0, 1035, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2213 = MTHI_DSP_MM
5322 { 2212, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1035, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2212 = MTHI_DSP
5323 { 2211, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2211 = MTHI64
5324 { 2210, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2210 = MTHI
5325 { 2209, 3, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2209 = MTHGC0_MM
5326 { 2208, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2208 = MTHGC0
5327 { 2207, 2, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2207 = MTHC2_MMR6
5328 { 2206, 3, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 1032, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2206 = MTHC1_D64_MM
5329 { 2205, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1032, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2205 = MTHC1_D64
5330 { 2204, 3, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 1029, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2204 = MTHC1_D32_MM
5331 { 2203, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1029, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2203 = MTHC1_D32
5332 { 2202, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2202 = MTHC0_MMR6
5333 { 2201, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2201 = MTGC0_MM
5334 { 2200, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2200 = MTGC0
5335 { 2199, 2, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2199 = MTC2_MMR6
5336 { 2198, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1026, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2198 = MTC2
5337 { 2197, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2197 = MTC1_MMR6
5338 { 2196, 2, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2196 = MTC1_MM
5339 { 2195, 2, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 418, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2195 = MTC1_D64_MM
5340 { 2194, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 418, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2194 = MTC1_D64
5341 { 2193, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2193 = MTC1
5342 { 2192, 3, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2192 = MTC0_MMR6
5343 { 2191, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2191 = MTC0
5344 { 2190, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 948, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2190 = MSUB_S_MM
5345 { 2189, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2189 = MSUB_S
5346 { 2188, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2188 = MSUB_Q_W
5347 { 2187, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2187 = MSUB_Q_H
5348 { 2186, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2186 = MSUB_MM
5349 { 2185, 4, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2185 = MSUB_DSP_MM
5350 { 2184, 4, 1, 4, 1403, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2184 = MSUB_DSP
5351 { 2183, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2183 = MSUB_D64
5352 { 2182, 4, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2182 = MSUB_D32_MM
5353 { 2181, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2181 = MSUB_D32
5354 { 2180, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2180 = MSUBV_W
5355 { 2179, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2179 = MSUBV_H
5356 { 2178, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #2178 = MSUBV_D
5357 { 2177, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #2177 = MSUBV_B
5358 { 2176, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2176 = MSUBU_MM
5359 { 2175, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2175 = MSUBU_DSP_MM
5360 { 2174, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2174 = MSUBU_DSP
5361 { 2173, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2173 = MSUBU
5362 { 2172, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2172 = MSUBR_Q_W
5363 { 2171, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2171 = MSUBR_Q_H
5364 { 2170, 4, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2170 = MSUBF_S_MMR6
5365 { 2169, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2169 = MSUBF_S
5366 { 2168, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2168 = MSUBF_D_MMR6
5367 { 2167, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2167 = MSUBF_D
5368 { 2166, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2166 = MSUB
5369 { 2165, 4, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2165 = MOVZ_I_S_MM
5370 { 2164, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2164 = MOVZ_I_S
5371 { 2163, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2163 = MOVZ_I_MM
5372 { 2162, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1018, 0, 0x4ULL }, // Inst #2162 = MOVZ_I_I64
5373 { 2161, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2161 = MOVZ_I_I
5374 { 2160, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2160 = MOVZ_I_D64
5375 { 2159, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2159 = MOVZ_I_D32_MM
5376 { 2158, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2158 = MOVZ_I_D32
5377 { 2157, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2157 = MOVZ_I64_S
5378 { 2156, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2156 = MOVZ_I64_I64
5379 { 2155, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2155 = MOVZ_I64_I
5380 { 2154, 4, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2154 = MOVZ_I64_D64
5381 { 2153, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2153 = MOVT_S_MM
5382 { 2152, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2152 = MOVT_S
5383 { 2151, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2151 = MOVT_I_MM
5384 { 2150, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2150 = MOVT_I64
5385 { 2149, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2149 = MOVT_I
5386 { 2148, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2148 = MOVT_D64
5387 { 2147, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2147 = MOVT_D32_MM
5388 { 2146, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2146 = MOVT_D32
5389 { 2145, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2145 = MOVN_I_S_MM
5390 { 2144, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2144 = MOVN_I_S
5391 { 2143, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2143 = MOVN_I_MM
5392 { 2142, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1018, 0, 0x4ULL }, // Inst #2142 = MOVN_I_I64
5393 { 2141, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2141 = MOVN_I_I
5394 { 2140, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2140 = MOVN_I_D64
5395 { 2139, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2139 = MOVN_I_D32_MM
5396 { 2138, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2138 = MOVN_I_D32
5397 { 2137, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2137 = MOVN_I64_S
5398 { 2136, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2136 = MOVN_I64_I64
5399 { 2135, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2135 = MOVN_I64_I
5400 { 2134, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2134 = MOVN_I64_D64
5401 { 2133, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2133 = MOVF_S_MM
5402 { 2132, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2132 = MOVF_S
5403 { 2131, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2131 = MOVF_I_MM
5404 { 2130, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2130 = MOVF_I64
5405 { 2129, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2129 = MOVF_I
5406 { 2128, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2128 = MOVF_D64
5407 { 2127, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2127 = MOVF_D32_MM
5408 { 2126, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2126 = MOVF_D32
5409 { 2125, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 968, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2125 = MOVE_V
5410 { 2124, 4, 2, 2, 1562, 0, 0, MipsImpOpBase + 0, 964, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2124 = MOVEP_MMR6
5411 { 2123, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 964, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2123 = MOVEP_MM
5412 { 2122, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2122 = MOVE16_MMR6
5413 { 2121, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2121 = MOVE16_MM
5414 { 2120, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2120 = MOD_U_W
5415 { 2119, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2119 = MOD_U_H
5416 { 2118, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2118 = MOD_U_D
5417 { 2117, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2117 = MOD_U_B
5418 { 2116, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2116 = MOD_S_W
5419 { 2115, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2115 = MOD_S_H
5420 { 2114, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2114 = MOD_S_D
5421 { 2113, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2113 = MOD_S_B
5422 { 2112, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2112 = MOD_MMR6
5423 { 2111, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2111 = MODU_MMR6
5424 { 2110, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2110 = MODU
5425 { 2109, 3, 1, 4, 1561, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2109 = MODSUB_MM
5426 { 2108, 3, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2108 = MODSUB
5427 { 2107, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2107 = MOD
5428 { 2106, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2106 = MIN_U_W
5429 { 2105, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2105 = MIN_U_H
5430 { 2104, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2104 = MIN_U_D
5431 { 2103, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2103 = MIN_U_B
5432 { 2102, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2102 = MIN_S_W
5433 { 2101, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2101 = MIN_S_MMR6
5434 { 2100, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2100 = MIN_S_H
5435 { 2099, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2099 = MIN_S_D
5436 { 2098, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2098 = MIN_S_B
5437 { 2097, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #2097 = MIN_S
5438 { 2096, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2096 = MIN_D_MMR6
5439 { 2095, 3, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2095 = MIN_D
5440 { 2094, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2094 = MIN_A_W
5441 { 2093, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2093 = MIN_A_H
5442 { 2092, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2092 = MIN_A_D
5443 { 2091, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2091 = MIN_A_B
5444 { 2090, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2090 = MINI_U_W
5445 { 2089, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2089 = MINI_U_H
5446 { 2088, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2088 = MINI_U_D
5447 { 2087, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2087 = MINI_U_B
5448 { 2086, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2086 = MINI_S_W
5449 { 2085, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2085 = MINI_S_H
5450 { 2084, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2084 = MINI_S_D
5451 { 2083, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2083 = MINI_S_B
5452 { 2082, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2082 = MINA_S_MMR6
5453 { 2081, 3, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2081 = MINA_S
5454 { 2080, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2080 = MINA_D_MMR6
5455 { 2079, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2079 = MINA_D
5456 { 2078, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 959, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2078 = MFTR
5457 { 2077, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2077 = MFLO_MM
5458 { 2076, 2, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 382, 0, 0x6ULL }, // Inst #2076 = MFLO_DSP_MM
5459 { 2075, 2, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2075 = MFLO_DSP
5460 { 2074, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2074 = MFLO64
5461 { 2073, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2073 = MFLO16_MM
5462 { 2072, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2072 = MFLO
5463 { 2071, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2071 = MFHI_MM
5464 { 2070, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 382, 0, 0x6ULL }, // Inst #2070 = MFHI_DSP_MM
5465 { 2069, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2069 = MFHI_DSP
5466 { 2068, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2068 = MFHI64
5467 { 2067, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2067 = MFHI16_MM
5468 { 2066, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2066 = MFHI
5469 { 2065, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2065 = MFHGC0_MM
5470 { 2064, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2064 = MFHGC0
5471 { 2063, 2, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 647, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2063 = MFHC2_MMR6
5472 { 2062, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2062 = MFHC1_D64_MM
5473 { 2061, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2061 = MFHC1_D64
5474 { 2060, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 957, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2060 = MFHC1_D32_MM
5475 { 2059, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 957, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2059 = MFHC1_D32
5476 { 2058, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2058 = MFHC0_MMR6
5477 { 2057, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2057 = MFGC0_MM
5478 { 2056, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2056 = MFGC0
5479 { 2055, 2, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 647, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2055 = MFC2_MMR6
5480 { 2054, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 954, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2054 = MFC2
5481 { 2053, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2053 = MFC1_MMR6
5482 { 2052, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2052 = MFC1_MM
5483 { 2051, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2051 = MFC1_D64
5484 { 2050, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2050 = MFC1
5485 { 2049, 3, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2049 = MFC0_MMR6
5486 { 2048, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2048 = MFC0
5487 { 2047, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2047 = MAX_U_W
5488 { 2046, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2046 = MAX_U_H
5489 { 2045, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2045 = MAX_U_D
5490 { 2044, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2044 = MAX_U_B
5491 { 2043, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2043 = MAX_S_W
5492 { 2042, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2042 = MAX_S_MMR6
5493 { 2041, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2041 = MAX_S_H
5494 { 2040, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2040 = MAX_S_D
5495 { 2039, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2039 = MAX_S_B
5496 { 2038, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #2038 = MAX_S
5497 { 2037, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2037 = MAX_D_MMR6
5498 { 2036, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2036 = MAX_D
5499 { 2035, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2035 = MAX_A_W
5500 { 2034, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2034 = MAX_A_H
5501 { 2033, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2033 = MAX_A_D
5502 { 2032, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2032 = MAX_A_B
5503 { 2031, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2031 = MAXI_U_W
5504 { 2030, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2030 = MAXI_U_H
5505 { 2029, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2029 = MAXI_U_D
5506 { 2028, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2028 = MAXI_U_B
5507 { 2027, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2027 = MAXI_S_W
5508 { 2026, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2026 = MAXI_S_H
5509 { 2025, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2025 = MAXI_S_D
5510 { 2024, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2024 = MAXI_S_B
5511 { 2023, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2023 = MAXA_S_MMR6
5512 { 2022, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2022 = MAXA_S
5513 { 2021, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2021 = MAXA_D_MMR6
5514 { 2020, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2020 = MAXA_D
5515 { 2019, 4, 1, 4, 1558, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2019 = MAQ_S_W_PHR_MM
5516 { 2018, 4, 1, 4, 1398, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2018 = MAQ_S_W_PHR
5517 { 2017, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2017 = MAQ_S_W_PHL_MM
5518 { 2016, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2016 = MAQ_S_W_PHL
5519 { 2015, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2015 = MAQ_SA_W_PHR_MM
5520 { 2014, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2014 = MAQ_SA_W_PHR
5521 { 2013, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2013 = MAQ_SA_W_PHL_MM
5522 { 2012, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2012 = MAQ_SA_W_PHL
5523 { 2011, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 948, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2011 = MADD_S_MM
5524 { 2010, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2010 = MADD_S
5525 { 2009, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2009 = MADD_Q_W
5526 { 2008, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2008 = MADD_Q_H
5527 { 2007, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2007 = MADD_MM
5528 { 2006, 4, 1, 4, 1554, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2006 = MADD_DSP_MM
5529 { 2005, 4, 1, 4, 1394, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2005 = MADD_DSP
5530 { 2004, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2004 = MADD_D64
5531 { 2003, 4, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2003 = MADD_D32_MM
5532 { 2002, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2002 = MADD_D32
5533 { 2001, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2001 = MADDV_W
5534 { 2000, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2000 = MADDV_H
5535 { 1999, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #1999 = MADDV_D
5536 { 1998, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1998 = MADDV_B
5537 { 1997, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1997 = MADDU_MM
5538 { 1996, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1996 = MADDU_DSP_MM
5539 { 1995, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1995 = MADDU_DSP
5540 { 1994, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1994 = MADDU
5541 { 1993, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #1993 = MADDR_Q_W
5542 { 1992, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #1992 = MADDR_Q_H
5543 { 1991, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1991 = MADDF_S_MMR6
5544 { 1990, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1990 = MADDF_S
5545 { 1989, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1989 = MADDF_D_MMR6
5546 { 1988, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1988 = MADDF_D
5547 { 1987, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1987 = MADD
5548 { 1986, 3, 1, 4, 1114, 0, 0, MipsImpOpBase + 0, 585, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1986 = LwRxSpImmX16
5549 { 1985, 3, 1, 4, 1114, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1985 = LwRxRyOffMemX16
5550 { 1984, 3, 1, 4, 1114, 0, 0, MipsImpOpBase + 0, 929, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1984 = LwRxPcTcpX16
5551 { 1983, 3, 1, 2, 1114, 0, 0, MipsImpOpBase + 0, 929, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1983 = LwRxPcTcp16
5552 { 1982, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0, 0x0ULL }, // Inst #1982 = LiRxImmX16
5553 { 1981, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1981 = LiRxImmAlignX16
5554 { 1980, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1980 = LiRxImm16
5555 { 1979, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1979 = LhuRxRyOffMemX16
5556 { 1978, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1978 = LhRxRyOffMemX16
5557 { 1977, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1977 = LbuRxRyOffMemX16
5558 { 1976, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1976 = LbRxRyOffMemX16
5559 { 1975, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1975 = LWu
5560 { 1974, 3, 1, 4, 1153, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1974 = LW_MMR6
5561 { 1973, 3, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1973 = LW_MM
5562 { 1972, 3, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1972 = LWX_MM
5563 { 1971, 3, 1, 4, 1130, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1971 = LWXS_MM
5564 { 1970, 3, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1970 = LWXC1_MM
5565 { 1969, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1969 = LWXC1
5566 { 1968, 3, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1968 = LWX
5567 { 1967, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1967 = LWU_MM
5568 { 1966, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1966 = LWUPC
5569 { 1965, 3, 1, 2, 1124, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1965 = LWSP_MM
5570 { 1964, 4, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1964 = LWR_MM
5571 { 1963, 4, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1963 = LWRE_MM
5572 { 1962, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1962 = LWRE
5573 { 1961, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1961 = LWR64
5574 { 1960, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1960 = LWR
5575 { 1959, 4, 2, 4, 1127, 0, 0, MipsImpOpBase + 0, 916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1959 = LWP_MM
5576 { 1958, 2, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1958 = LWPC_MMR6
5577 { 1957, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1957 = LWPC
5578 { 1956, 3, 1, 4, 1126, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1956 = LWM32_MM
5579 { 1955, 3, 1, 2, 1150, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1955 = LWM16_MMR6
5580 { 1954, 3, 1, 2, 1126, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1954 = LWM16_MM
5581 { 1953, 4, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1953 = LWL_MM
5582 { 1952, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1952 = LWLE_MM
5583 { 1951, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1951 = LWLE
5584 { 1950, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1950 = LWL64
5585 { 1949, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1949 = LWL
5586 { 1948, 3, 1, 2, 1124, 0, 0, MipsImpOpBase + 0, 906, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1948 = LWGP_MM
5587 { 1947, 3, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1947 = LWE_MM
5588 { 1946, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1946 = LWE
5589 { 1945, 3, 1, 4, 1507, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1945 = LWDSP_MM
5590 { 1944, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1944 = LWDSP
5591 { 1943, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1943 = LWC3
5592 { 1942, 3, 1, 4, 1084, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1942 = LWC2_R6
5593 { 1941, 3, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1941 = LWC2_MMR6
5594 { 1940, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1940 = LWC2
5595 { 1939, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1939 = LWC1_MM
5596 { 1938, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1938 = LWC1
5597 { 1937, 3, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1937 = LW64
5598 { 1936, 3, 1, 2, 1124, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1936 = LW16_MM
5599 { 1935, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1935 = LW
5600 { 1934, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1934 = LUi_MM
5601 { 1933, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1933 = LUi64
5602 { 1932, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1932 = LUi
5603 { 1931, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1931 = LUXC1_MM
5604 { 1930, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1930 = LUXC164
5605 { 1929, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1929 = LUXC1
5606 { 1928, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #1928 = LUI_MMR6
5607 { 1927, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1927 = LSA_R6
5608 { 1926, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1926 = LSA_MMR6
5609 { 1925, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 569, 0, 0x6ULL }, // Inst #1925 = LSA
5610 { 1924, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 894, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1924 = LL_R6
5611 { 1923, 3, 1, 4, 1149, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1923 = LL_MMR6
5612 { 1922, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1922 = LL_MM
5613 { 1921, 3, 1, 4, 1099, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1921 = LLE_MM
5614 { 1920, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1920 = LLE
5615 { 1919, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1919 = LLD_R6
5616 { 1918, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1918 = LLD
5617 { 1917, 3, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 894, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1917 = LL64_R6
5618 { 1916, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1916 = LL64
5619 { 1915, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1915 = LL
5620 { 1914, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1914 = LI16_MMR6
5621 { 1913, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1913 = LI16_MM
5622 { 1912, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1912 = LHu_MM
5623 { 1911, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1911 = LHuE_MM
5624 { 1910, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1910 = LHuE
5625 { 1909, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1909 = LHu64
5626 { 1908, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1908 = LHu
5627 { 1907, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1907 = LH_MM
5628 { 1906, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1906 = LHX_MM
5629 { 1905, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1905 = LHX
5630 { 1904, 3, 1, 2, 1121, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1904 = LHU16_MM
5631 { 1903, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1903 = LHE_MM
5632 { 1902, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1902 = LHE
5633 { 1901, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1901 = LH64
5634 { 1900, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1900 = LH
5635 { 1899, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 319, 0, 0x2ULL }, // Inst #1899 = LEA_ADDiu_MM
5636 { 1898, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 368, 0, 0x2ULL }, // Inst #1898 = LEA_ADDiu64
5637 { 1897, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 319, 0, 0x2ULL }, // Inst #1897 = LEA_ADDiu
5638 { 1896, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1896 = LD_W
5639 { 1895, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1895 = LD_H
5640 { 1894, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 885, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1894 = LD_D
5641 { 1893, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 882, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1893 = LD_B
5642 { 1892, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1892 = LDXC164
5643 { 1891, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1891 = LDXC1
5644 { 1890, 4, 1, 4, 1175, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1890 = LDR
5645 { 1889, 2, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1889 = LDPC
5646 { 1888, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1888 = LDL
5647 { 1887, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 870, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1887 = LDI_W
5648 { 1886, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 868, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1886 = LDI_H
5649 { 1885, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 866, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1885 = LDI_D
5650 { 1884, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 864, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1884 = LDI_B
5651 { 1883, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1883 = LDC3
5652 { 1882, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1882 = LDC2_R6
5653 { 1881, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1881 = LDC2_MMR6
5654 { 1880, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1880 = LDC2
5655 { 1879, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1879 = LDC1_MM_D64
5656 { 1878, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1878 = LDC1_MM_D32
5657 { 1877, 3, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1877 = LDC1_D64_MMR6
5658 { 1876, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1876 = LDC164
5659 { 1875, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1875 = LDC1
5660 { 1874, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1874 = LD
5661 { 1873, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1873 = LBu_MM
5662 { 1872, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1872 = LBuE_MM
5663 { 1871, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1871 = LBuE
5664 { 1870, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1870 = LBu64
5665 { 1869, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1869 = LBu
5666 { 1868, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1868 = LB_MMR6
5667 { 1867, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1867 = LB_MM
5668 { 1866, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1866 = LBU_MMR6
5669 { 1865, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1865 = LBUX_MM
5670 { 1864, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1864 = LBUX
5671 { 1863, 3, 1, 2, 1119, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1863 = LBU16_MM
5672 { 1862, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1862 = LBE_MM
5673 { 1861, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1861 = LBE
5674 { 1860, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1860 = LB64
5675 { 1859, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1859 = LB
5676 { 1858, 1, 0, 2, 943, 0, 1, MipsImpOpBase + 3, 845, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1858 = JumpLinkReg16
5677 { 1857, 1, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 845, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1857 = JrcRx16
5678 { 1856, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1856 = JrcRa16
5679 { 1855, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1855 = JrRa16
5680 { 1854, 1, 0, 6, 942, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1854 = JalB16
5681 { 1853, 1, 0, 6, 942, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1853 = Jal16
5682 { 1852, 1, 0, 4, 956, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1852 = J_MM
5683 { 1851, 1, 0, 4, 955, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1851 = JR_MM
5684 { 1850, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1850 = JR_HB_R6
5685 { 1849, 1, 0, 4, 1023, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1849 = JR_HB64_R6
5686 { 1848, 1, 0, 4, 1015, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1848 = JR_HB64
5687 { 1847, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1847 = JR_HB
5688 { 1846, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1846 = JRCADDIUSP_MMR6
5689 { 1845, 1, 0, 2, 996, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1845 = JRC16_MMR6
5690 { 1844, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1844 = JRC16_MM
5691 { 1843, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1843 = JRADDIUSP
5692 { 1842, 1, 0, 4, 1012, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1842 = JR64
5693 { 1841, 1, 0, 2, 955, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1841 = JR16_MM
5694 { 1840, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1840 = JR
5695 { 1839, 2, 0, 4, 993, 0, 1, MipsImpOpBase + 2, 371, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1839 = JIC_MMR6
5696 { 1838, 2, 0, 4, 1020, 0, 1, MipsImpOpBase + 2, 366, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1838 = JIC64
5697 { 1837, 2, 0, 4, 934, 0, 1, MipsImpOpBase + 2, 371, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1837 = JIC
5698 { 1836, 2, 0, 4, 1005, 0, 1, MipsImpOpBase + 3, 371, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1836 = JIALC_MMR6
5699 { 1835, 2, 0, 4, 1022, 0, 1, MipsImpOpBase + 3, 366, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1835 = JIALC64
5700 { 1834, 2, 0, 4, 929, 0, 1, MipsImpOpBase + 3, 371, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1834 = JIALC
5701 { 1833, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1833 = JAL_MM
5702 { 1832, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1832 = JALX_MM
5703 { 1831, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1831 = JALX
5704 { 1830, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1830 = JALS_MM
5705 { 1829, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1829 = JALR_MM
5706 { 1828, 2, 1, 4, 1014, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1828 = JALR_HB64
5707 { 1827, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1827 = JALR_HB
5708 { 1826, 2, 1, 4, 961, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1826 = JALRS_MM
5709 { 1825, 1, 0, 2, 961, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1825 = JALRS16_MM
5710 { 1824, 2, 1, 4, 1004, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1824 = JALRC_MMR6
5711 { 1823, 2, 1, 4, 1003, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1823 = JALRC_HB_MMR6
5712 { 1822, 1, 0, 2, 1002, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1822 = JALRC16_MMR6
5713 { 1821, 2, 1, 4, 1013, 0, 1, MipsImpOpBase + 3, 389, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1821 = JALR64
5714 { 1820, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1820 = JALR16_MM
5715 { 1819, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1819 = JALR
5716 { 1818, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1818 = JAL
5717 { 1817, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1817 = J
5718 { 1816, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 801, 0, 0x1ULL }, // Inst #1816 = INS_MMR6
5719 { 1815, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 801, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1815 = INS_MM
5720 { 1814, 3, 1, 4, 1549, 2, 0, MipsImpOpBase + 30, 822, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1814 = INSV_MM
5721 { 1813, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 840, 0, 0x6ULL }, // Inst #1813 = INSVE_W
5722 { 1812, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 835, 0, 0x6ULL }, // Inst #1812 = INSVE_H
5723 { 1811, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 830, 0, 0x6ULL }, // Inst #1811 = INSVE_D
5724 { 1810, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 825, 0, 0x6ULL }, // Inst #1810 = INSVE_B
5725 { 1809, 3, 1, 4, 1354, 2, 0, MipsImpOpBase + 30, 822, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1809 = INSV
5726 { 1808, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 818, 0, 0x6ULL }, // Inst #1808 = INSERT_W
5727 { 1807, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1807 = INSERT_H
5728 { 1806, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 810, 0, 0x6ULL }, // Inst #1806 = INSERT_D
5729 { 1805, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 806, 0, 0x6ULL }, // Inst #1805 = INSERT_B
5730 { 1804, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 801, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1804 = INS
5731 { 1803, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1803 = ILVR_W
5732 { 1802, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1802 = ILVR_H
5733 { 1801, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1801 = ILVR_D
5734 { 1800, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1800 = ILVR_B
5735 { 1799, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1799 = ILVOD_W
5736 { 1798, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1798 = ILVOD_H
5737 { 1797, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1797 = ILVOD_D
5738 { 1796, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1796 = ILVOD_B
5739 { 1795, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1795 = ILVL_W
5740 { 1794, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1794 = ILVL_H
5741 { 1793, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1793 = ILVL_D
5742 { 1792, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1792 = ILVL_B
5743 { 1791, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1791 = ILVEV_W
5744 { 1790, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1790 = ILVEV_H
5745 { 1789, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1789 = ILVEV_D
5746 { 1788, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1788 = ILVEV_B
5747 { 1787, 1, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1787 = HYPCALL_MM
5748 { 1786, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1786 = HYPCALL
5749 { 1785, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1785 = HSUB_U_W
5750 { 1784, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1784 = HSUB_U_H
5751 { 1783, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1783 = HSUB_U_D
5752 { 1782, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1782 = HSUB_S_W
5753 { 1781, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1781 = HSUB_S_H
5754 { 1780, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1780 = HSUB_S_D
5755 { 1779, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1779 = HADD_U_W
5756 { 1778, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1778 = HADD_U_H
5757 { 1777, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1777 = HADD_U_D
5758 { 1776, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1776 = HADD_S_W
5759 { 1775, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1775 = HADD_S_H
5760 { 1774, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1774 = HADD_S_D
5761 { 1773, 2, 0, 4, 1145, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1773 = GINVT_MMR6
5762 { 1772, 2, 0, 4, 1091, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1772 = GINVT
5763 { 1771, 1, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1771 = GINVI_MMR6
5764 { 1770, 1, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1770 = GINVI
5765 { 1769, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1769 = FTRUNC_U_W
5766 { 1768, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1768 = FTRUNC_U_D
5767 { 1767, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1767 = FTRUNC_S_W
5768 { 1766, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1766 = FTRUNC_S_D
5769 { 1765, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 786, 0, 0x6ULL }, // Inst #1765 = FTQ_W
5770 { 1764, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1764 = FTQ_H
5771 { 1763, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1763 = FTINT_U_W
5772 { 1762, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1762 = FTINT_U_D
5773 { 1761, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1761 = FTINT_S_W
5774 { 1760, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1760 = FTINT_S_D
5775 { 1759, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1759 = FSUN_W
5776 { 1758, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1758 = FSUN_D
5777 { 1757, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1757 = FSUNE_W
5778 { 1756, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1756 = FSUNE_D
5779 { 1755, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1755 = FSULT_W
5780 { 1754, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1754 = FSULT_D
5781 { 1753, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1753 = FSULE_W
5782 { 1752, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1752 = FSULE_D
5783 { 1751, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1751 = FSUEQ_W
5784 { 1750, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1750 = FSUEQ_D
5785 { 1749, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1749 = FSUB_W
5786 { 1748, 3, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #1748 = FSUB_S_MMR6
5787 { 1747, 3, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1747 = FSUB_S_MM
5788 { 1746, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1746 = FSUB_S
5789 { 1745, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1745 = FSUB_PS64
5790 { 1744, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1744 = FSUB_D64_MM
5791 { 1743, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1743 = FSUB_D64
5792 { 1742, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1742 = FSUB_D32_MM
5793 { 1741, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1741 = FSUB_D32
5794 { 1740, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1740 = FSUB_D
5795 { 1739, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1739 = FSQRT_W
5796 { 1738, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1738 = FSQRT_S_MM
5797 { 1737, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1737 = FSQRT_S
5798 { 1736, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1736 = FSQRT_D64_MM
5799 { 1735, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1735 = FSQRT_D64
5800 { 1734, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1734 = FSQRT_D32_MM
5801 { 1733, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1733 = FSQRT_D32
5802 { 1732, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1732 = FSQRT_D
5803 { 1731, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1731 = FSOR_W
5804 { 1730, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1730 = FSOR_D
5805 { 1729, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1729 = FSNE_W
5806 { 1728, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1728 = FSNE_D
5807 { 1727, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1727 = FSLT_W
5808 { 1726, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1726 = FSLT_D
5809 { 1725, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1725 = FSLE_W
5810 { 1724, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1724 = FSLE_D
5811 { 1723, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1723 = FSEQ_W
5812 { 1722, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1722 = FSEQ_D
5813 { 1721, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1721 = FSAF_W
5814 { 1720, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1720 = FSAF_D
5815 { 1719, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1719 = FRSQRT_W
5816 { 1718, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1718 = FRSQRT_D
5817 { 1717, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1717 = FRINT_W
5818 { 1716, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1716 = FRINT_D
5819 { 1715, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1715 = FRCP_W
5820 { 1714, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1714 = FRCP_D
5821 { 1713, 3, 2, 4, 1067, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1713 = FORK
5822 { 1712, 2, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1712 = FNEG_S_MMR6
5823 { 1711, 2, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1711 = FNEG_S_MM
5824 { 1710, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1710 = FNEG_S
5825 { 1709, 2, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1709 = FNEG_D64_MM
5826 { 1708, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1708 = FNEG_D64
5827 { 1707, 2, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1707 = FNEG_D32_MM
5828 { 1706, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1706 = FNEG_D32
5829 { 1705, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1705 = FMUL_W
5830 { 1704, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1704 = FMUL_S_MMR6
5831 { 1703, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1703 = FMUL_S_MM
5832 { 1702, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1702 = FMUL_S
5833 { 1701, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1701 = FMUL_PS64
5834 { 1700, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1700 = FMUL_D64_MM
5835 { 1699, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1699 = FMUL_D64
5836 { 1698, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1698 = FMUL_D32_MM
5837 { 1697, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1697 = FMUL_D32
5838 { 1696, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1696 = FMUL_D
5839 { 1695, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #1695 = FMSUB_W
5840 { 1694, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #1694 = FMSUB_D
5841 { 1693, 2, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1693 = FMOV_S_MMR6
5842 { 1692, 2, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1692 = FMOV_S_MM
5843 { 1691, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1691 = FMOV_S
5844 { 1690, 2, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1690 = FMOV_D_MMR6
5845 { 1689, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1689 = FMOV_D64_MM
5846 { 1688, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1688 = FMOV_D64
5847 { 1687, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1687 = FMOV_D32_MM
5848 { 1686, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 766, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1686 = FMOV_D32
5849 { 1685, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1685 = FMIN_W
5850 { 1684, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1684 = FMIN_D
5851 { 1683, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1683 = FMIN_A_W
5852 { 1682, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1682 = FMIN_A_D
5853 { 1681, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1681 = FMAX_W
5854 { 1680, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1680 = FMAX_D
5855 { 1679, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1679 = FMAX_A_W
5856 { 1678, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1678 = FMAX_A_D
5857 { 1677, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #1677 = FMADD_W
5858 { 1676, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #1676 = FMADD_D
5859 { 1675, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1675 = FLOOR_W_S_MMR6
5860 { 1674, 2, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1674 = FLOOR_W_S_MM
5861 { 1673, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1673 = FLOOR_W_S
5862 { 1672, 2, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1672 = FLOOR_W_MM
5863 { 1671, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1671 = FLOOR_W_D_MMR6
5864 { 1670, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1670 = FLOOR_W_D64
5865 { 1669, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1669 = FLOOR_W_D32
5866 { 1668, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1668 = FLOOR_L_S_MMR6
5867 { 1667, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1667 = FLOOR_L_S
5868 { 1666, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1666 = FLOOR_L_D_MMR6
5869 { 1665, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1665 = FLOOR_L_D64
5870 { 1664, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1664 = FLOG2_W
5871 { 1663, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1663 = FLOG2_D
5872 { 1662, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 799, 0, 0x6ULL }, // Inst #1662 = FILL_W
5873 { 1661, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 797, 0, 0x6ULL }, // Inst #1661 = FILL_H
5874 { 1660, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 795, 0, 0x6ULL }, // Inst #1660 = FILL_D
5875 { 1659, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 793, 0, 0x6ULL }, // Inst #1659 = FILL_B
5876 { 1658, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1658 = FFQR_W
5877 { 1657, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1657 = FFQR_D
5878 { 1656, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1656 = FFQL_W
5879 { 1655, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1655 = FFQL_D
5880 { 1654, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1654 = FFINT_U_W
5881 { 1653, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1653 = FFINT_U_D
5882 { 1652, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1652 = FFINT_S_W
5883 { 1651, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1651 = FFINT_S_D
5884 { 1650, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1650 = FEXUPR_W
5885 { 1649, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1649 = FEXUPR_D
5886 { 1648, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1648 = FEXUPL_W
5887 { 1647, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1647 = FEXUPL_D
5888 { 1646, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1646 = FEXP2_W
5889 { 1645, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1645 = FEXP2_D
5890 { 1644, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 786, 0, 0x6ULL }, // Inst #1644 = FEXDO_W
5891 { 1643, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1643 = FEXDO_H
5892 { 1642, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1642 = FDIV_W
5893 { 1641, 3, 1, 4, 1338, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #1641 = FDIV_S_MMR6
5894 { 1640, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1640 = FDIV_S_MM
5895 { 1639, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1639 = FDIV_S
5896 { 1638, 3, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1638 = FDIV_D64_MM
5897 { 1637, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1637 = FDIV_D64
5898 { 1636, 3, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1636 = FDIV_D32_MM
5899 { 1635, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1635 = FDIV_D32
5900 { 1634, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1634 = FDIV_D
5901 { 1633, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1633 = FCUN_W
5902 { 1632, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1632 = FCUN_D
5903 { 1631, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1631 = FCUNE_W
5904 { 1630, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1630 = FCUNE_D
5905 { 1629, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1629 = FCULT_W
5906 { 1628, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1628 = FCULT_D
5907 { 1627, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1627 = FCULE_W
5908 { 1626, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1626 = FCULE_D
5909 { 1625, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1625 = FCUEQ_W
5910 { 1624, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1624 = FCUEQ_D
5911 { 1623, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1623 = FCOR_W
5912 { 1622, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1622 = FCOR_D
5913 { 1621, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1621 = FCNE_W
5914 { 1620, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1620 = FCNE_D
5915 { 1619, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 780, 0, 0x44ULL }, // Inst #1619 = FCMP_S32_MM
5916 { 1618, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 780, 0, 0x44ULL }, // Inst #1618 = FCMP_S32
5917 { 1617, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 777, 0, 0x44ULL }, // Inst #1617 = FCMP_D64
5918 { 1616, 3, 0, 4, 1267, 0, 1, MipsImpOpBase + 29, 774, 0, 0x44ULL }, // Inst #1616 = FCMP_D32_MM
5919 { 1615, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 774, 0, 0x44ULL }, // Inst #1615 = FCMP_D32
5920 { 1614, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1614 = FCLT_W
5921 { 1613, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1613 = FCLT_D
5922 { 1612, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1612 = FCLE_W
5923 { 1611, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1611 = FCLE_D
5924 { 1610, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1610 = FCLASS_W
5925 { 1609, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1609 = FCLASS_D
5926 { 1608, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1608 = FCEQ_W
5927 { 1607, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1607 = FCEQ_D
5928 { 1606, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1606 = FCAF_W
5929 { 1605, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1605 = FCAF_D
5930 { 1604, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1604 = FADD_W
5931 { 1603, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1603 = FADD_S_MMR6
5932 { 1602, 3, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1602 = FADD_S_MM
5933 { 1601, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1601 = FADD_S
5934 { 1600, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1600 = FADD_PS64
5935 { 1599, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1599 = FADD_D64_MM
5936 { 1598, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1598 = FADD_D64
5937 { 1597, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1597 = FADD_D32_MM
5938 { 1596, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1596 = FADD_D32
5939 { 1595, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1595 = FADD_D
5940 { 1594, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1594 = FABS_S_MM
5941 { 1593, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1593 = FABS_S
5942 { 1592, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1592 = FABS_D64_MM
5943 { 1591, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1591 = FABS_D64
5944 { 1590, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1590 = FABS_D32_MM
5945 { 1589, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1589 = FABS_D32
5946 { 1588, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1588 = EXT_MMR6
5947 { 1587, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1587 = EXT_MM
5948 { 1586, 4, 1, 4, 1205, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1586 = EXTS32
5949 { 1585, 4, 1, 4, 1205, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1585 = EXTS
5950 { 1584, 3, 1, 4, 1548, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1584 = EXTR_W_MM
5951 { 1583, 3, 1, 4, 1353, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1583 = EXTR_W
5952 { 1582, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1582 = EXTR_S_H_MM
5953 { 1581, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1581 = EXTR_S_H
5954 { 1580, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1580 = EXTR_R_W_MM
5955 { 1579, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1579 = EXTR_R_W
5956 { 1578, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1578 = EXTR_RS_W_MM
5957 { 1577, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1577 = EXTR_RS_W
5958 { 1576, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1576 = EXTRV_W_MM
5959 { 1575, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1575 = EXTRV_W
5960 { 1574, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1574 = EXTRV_S_H_MM
5961 { 1573, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1573 = EXTRV_S_H
5962 { 1572, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1572 = EXTRV_R_W_MM
5963 { 1571, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1571 = EXTRV_R_W
5964 { 1570, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1570 = EXTRV_RS_W_MM
5965 { 1569, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1569 = EXTRV_RS_W
5966 { 1568, 3, 1, 4, 1540, 1, 1, MipsImpOpBase + 23, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1568 = EXTP_MM
5967 { 1567, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1567 = EXTPV_MM
5968 { 1566, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1566 = EXTPV
5969 { 1565, 3, 1, 4, 1538, 1, 2, MipsImpOpBase + 25, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1565 = EXTPDP_MM
5970 { 1564, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1564 = EXTPDPV_MM
5971 { 1563, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1563 = EXTPDPV
5972 { 1562, 3, 1, 4, 1387, 1, 2, MipsImpOpBase + 25, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1562 = EXTPDP
5973 { 1561, 3, 1, 4, 1389, 1, 1, MipsImpOpBase + 23, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1561 = EXTP
5974 { 1560, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1560 = EXT
5975 { 1559, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1559 = EVP_MMR6
5976 { 1558, 1, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1558 = EVPE
5977 { 1557, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1557 = EVP
5978 { 1556, 0, 0, 4, 992, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1556 = ERET_MMR6
5979 { 1555, 0, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1555 = ERET_MM
5980 { 1554, 0, 0, 4, 990, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1554 = ERETNC_MMR6
5981 { 1553, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1553 = ERETNC
5982 { 1552, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1552 = ERET
5983 { 1551, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1551 = EMT
5984 { 1550, 1, 1, 4, 1050, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1550 = EI_MMR6
5985 { 1549, 1, 1, 4, 1033, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1549 = EI_MM
5986 { 1548, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1548 = EI
5987 { 1547, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1547 = EHB_MMR6
5988 { 1546, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1546 = EHB_MM
5989 { 1545, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1545 = EHB
5990 { 1544, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 406, 0, 0x0ULL }, // Inst #1544 = DivuRxRy16
5991 { 1543, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 406, 0, 0x0ULL }, // Inst #1543 = DivRxRy16
5992 { 1542, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1542 = DVP_MMR6
5993 { 1541, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1541 = DVPE
5994 { 1540, 1, 1, 4, 1027, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1540 = DVP
5995 { 1539, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1539 = DUDIV
5996 { 1538, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1538 = DSUBu
5997 { 1537, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1537 = DSUB
5998 { 1536, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1536 = DSRLV
5999 { 1535, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1535 = DSRL32
6000 { 1534, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1534 = DSRL
6001 { 1533, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1533 = DSRAV
6002 { 1532, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1532 = DSRA32
6003 { 1531, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1531 = DSRA
6004 { 1530, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1530 = DSLLV
6005 { 1529, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 758, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1529 = DSLL64_32
6006 { 1528, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1528 = DSLL32
6007 { 1527, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1527 = DSLL
6008 { 1526, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1526 = DSHD
6009 { 1525, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1525 = DSDIV
6010 { 1524, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1524 = DSBH
6011 { 1523, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1523 = DROTRV
6012 { 1522, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1522 = DROTR32
6013 { 1521, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1521 = DROTR
6014 { 1520, 4, 1, 4, 1643, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1520 = DPS_W_PH_MMR2
6015 { 1519, 4, 1, 4, 1479, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1519 = DPS_W_PH
6016 { 1518, 4, 1, 4, 1646, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1518 = DPSX_W_PH_MMR2
6017 { 1517, 4, 1, 4, 1482, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1517 = DPSX_W_PH
6018 { 1516, 4, 1, 4, 1536, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1516 = DPSU_H_QBR_MM
6019 { 1515, 4, 1, 4, 1385, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1515 = DPSU_H_QBR
6020 { 1514, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1514 = DPSU_H_QBL_MM
6021 { 1513, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1513 = DPSU_H_QBL
6022 { 1512, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 747, 0, 0x6ULL }, // Inst #1512 = DPSUB_U_W
6023 { 1511, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 743, 0, 0x6ULL }, // Inst #1511 = DPSUB_U_H
6024 { 1510, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1510 = DPSUB_U_D
6025 { 1509, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 747, 0, 0x6ULL }, // Inst #1509 = DPSUB_S_W
6026 { 1508, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 743, 0, 0x6ULL }, // Inst #1508 = DPSUB_S_H
6027 { 1507, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1507 = DPSUB_S_D
6028 { 1506, 4, 1, 4, 1534, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1506 = DPSQ_S_W_PH_MM
6029 { 1505, 4, 1, 4, 1383, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1505 = DPSQ_S_W_PH
6030 { 1504, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1504 = DPSQ_SA_L_W_MM
6031 { 1503, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1503 = DPSQ_SA_L_W
6032 { 1502, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1502 = DPSQX_S_W_PH_MMR2
6033 { 1501, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1501 = DPSQX_S_W_PH
6034 { 1500, 4, 1, 4, 1645, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1500 = DPSQX_SA_W_PH_MMR2
6035 { 1499, 4, 1, 4, 1481, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1499 = DPSQX_SA_W_PH
6036 { 1498, 2, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1498 = DPOP
6037 { 1497, 4, 1, 4, 1639, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1497 = DPA_W_PH_MMR2
6038 { 1496, 4, 1, 4, 1475, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1496 = DPA_W_PH
6039 { 1495, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1495 = DPAX_W_PH_MMR2
6040 { 1494, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1494 = DPAX_W_PH
6041 { 1493, 4, 1, 4, 1532, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1493 = DPAU_H_QBR_MM
6042 { 1492, 4, 1, 4, 1381, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1492 = DPAU_H_QBR
6043 { 1491, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1491 = DPAU_H_QBL_MM
6044 { 1490, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1490 = DPAU_H_QBL
6045 { 1489, 4, 1, 4, 1530, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1489 = DPAQ_S_W_PH_MM
6046 { 1488, 4, 1, 4, 1379, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1488 = DPAQ_S_W_PH
6047 { 1487, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1487 = DPAQ_SA_L_W_MM
6048 { 1486, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1486 = DPAQ_SA_L_W
6049 { 1485, 4, 1, 4, 1641, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1485 = DPAQX_S_W_PH_MMR2
6050 { 1484, 4, 1, 4, 1477, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1484 = DPAQX_S_W_PH
6051 { 1483, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1483 = DPAQX_SA_W_PH_MMR2
6052 { 1482, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1482 = DPAQX_SA_W_PH
6053 { 1481, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 747, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1481 = DPADD_U_W
6054 { 1480, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 743, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1480 = DPADD_U_H
6055 { 1479, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 739, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1479 = DPADD_U_D
6056 { 1478, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 747, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1478 = DPADD_S_W
6057 { 1477, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 743, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1477 = DPADD_S_H
6058 { 1476, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 739, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1476 = DPADD_S_D
6059 { 1475, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 736, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1475 = DOTP_U_W
6060 { 1474, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 733, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1474 = DOTP_U_H
6061 { 1473, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 730, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1473 = DOTP_U_D
6062 { 1472, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 736, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1472 = DOTP_S_W
6063 { 1471, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 733, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1471 = DOTP_S_H
6064 { 1470, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 730, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1470 = DOTP_S_D
6065 { 1469, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #1469 = DMUL_R6
6066 { 1468, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1468 = DMULU
6067 { 1467, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1467 = DMULTu
6068 { 1466, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1466 = DMULT
6069 { 1465, 3, 1, 4, 1210, 0, 5, MipsImpOpBase + 15, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1465 = DMUL
6070 { 1464, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #1464 = DMUHU
6071 { 1463, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #1463 = DMUH
6072 { 1462, 3, 1, 4, 1069, 0, 0, MipsImpOpBase + 0, 724, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1462 = DMTGC0
6073 { 1461, 2, 2, 4, 1203, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1461 = DMTC2_OCTEON
6074 { 1460, 3, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1460 = DMTC2
6075 { 1459, 2, 1, 4, 1342, 0, 0, MipsImpOpBase + 0, 416, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1459 = DMTC1
6076 { 1458, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 724, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1458 = DMTC0
6077 { 1457, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1457 = DMT
6078 { 1456, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1456 = DMODU
6079 { 1455, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1455 = DMOD
6080 { 1454, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 716, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1454 = DMFGC0
6081 { 1453, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1453 = DMFC2_OCTEON
6082 { 1452, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 721, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1452 = DMFC2
6083 { 1451, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 719, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1451 = DMFC1
6084 { 1450, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 716, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1450 = DMFC0
6085 { 1449, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 707, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1449 = DLSA_R6
6086 { 1448, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 707, 0, 0x6ULL }, // Inst #1448 = DLSA
6087 { 1447, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1447 = DI_MMR6
6088 { 1446, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1446 = DI_MM
6089 { 1445, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1445 = DIV_U_W
6090 { 1444, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1444 = DIV_U_H
6091 { 1443, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1443 = DIV_U_D
6092 { 1442, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1442 = DIV_U_B
6093 { 1441, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1441 = DIV_S_W
6094 { 1440, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1440 = DIV_S_H
6095 { 1439, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1439 = DIV_S_D
6096 { 1438, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1438 = DIV_S_B
6097 { 1437, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1437 = DIV_MMR6
6098 { 1436, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1436 = DIVU_MMR6
6099 { 1435, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1435 = DIVU
6100 { 1434, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1434 = DIV
6101 { 1433, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1433 = DINSU
6102 { 1432, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1432 = DINSM
6103 { 1431, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1431 = DINS
6104 { 1430, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1430 = DI
6105 { 1429, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1429 = DEXTU
6106 { 1428, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1428 = DEXTM
6107 { 1427, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 655, 0, 0x1ULL }, // Inst #1427 = DEXT64_32
6108 { 1426, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1426 = DEXT
6109 { 1425, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1425 = DERET_MMR6
6110 { 1424, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1424 = DERET_MM
6111 { 1423, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1423 = DERET
6112 { 1422, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1422 = DDIVU
6113 { 1421, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1421 = DDIV
6114 { 1420, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 389, 0, 0x6ULL }, // Inst #1420 = DCLZ_R6
6115 { 1419, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1419 = DCLZ
6116 { 1418, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 389, 0, 0x6ULL }, // Inst #1418 = DCLO_R6
6117 { 1417, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1417 = DCLO
6118 { 1416, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1416 = DBITSWAP
6119 { 1415, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1415 = DAUI
6120 { 1414, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 704, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1414 = DATI
6121 { 1413, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 707, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1413 = DALIGN
6122 { 1412, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 704, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1412 = DAHI
6123 { 1411, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1411 = DADDu
6124 { 1410, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1410 = DADDiu
6125 { 1409, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1409 = DADDi
6126 { 1408, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1408 = DADD
6127 { 1407, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1407 = CmpiRxImmX16
6128 { 1406, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1406 = CmpiRxImm16
6129 { 1405, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1405 = CmpRxRy16
6130 { 1404, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1404 = C_UN_S_MM
6131 { 1403, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1403 = C_UN_S
6132 { 1402, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1402 = C_UN_D64_MM
6133 { 1401, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1401 = C_UN_D64
6134 { 1400, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1400 = C_UN_D32_MM
6135 { 1399, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1399 = C_UN_D32
6136 { 1398, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1398 = C_ULT_S_MM
6137 { 1397, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1397 = C_ULT_S
6138 { 1396, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1396 = C_ULT_D64_MM
6139 { 1395, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1395 = C_ULT_D64
6140 { 1394, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1394 = C_ULT_D32_MM
6141 { 1393, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1393 = C_ULT_D32
6142 { 1392, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1392 = C_ULE_S_MM
6143 { 1391, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1391 = C_ULE_S
6144 { 1390, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1390 = C_ULE_D64_MM
6145 { 1389, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1389 = C_ULE_D64
6146 { 1388, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1388 = C_ULE_D32_MM
6147 { 1387, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1387 = C_ULE_D32
6148 { 1386, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1386 = C_UEQ_S_MM
6149 { 1385, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1385 = C_UEQ_S
6150 { 1384, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1384 = C_UEQ_D64_MM
6151 { 1383, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1383 = C_UEQ_D64
6152 { 1382, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1382 = C_UEQ_D32_MM
6153 { 1381, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1381 = C_UEQ_D32
6154 { 1380, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1380 = C_SF_S_MM
6155 { 1379, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1379 = C_SF_S
6156 { 1378, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1378 = C_SF_D64_MM
6157 { 1377, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1377 = C_SF_D64
6158 { 1376, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1376 = C_SF_D32_MM
6159 { 1375, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1375 = C_SF_D32
6160 { 1374, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1374 = C_SEQ_S_MM
6161 { 1373, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1373 = C_SEQ_S
6162 { 1372, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1372 = C_SEQ_D64_MM
6163 { 1371, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1371 = C_SEQ_D64
6164 { 1370, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1370 = C_SEQ_D32_MM
6165 { 1369, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1369 = C_SEQ_D32
6166 { 1368, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1368 = C_OLT_S_MM
6167 { 1367, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1367 = C_OLT_S
6168 { 1366, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1366 = C_OLT_D64_MM
6169 { 1365, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1365 = C_OLT_D64
6170 { 1364, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1364 = C_OLT_D32_MM
6171 { 1363, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1363 = C_OLT_D32
6172 { 1362, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1362 = C_OLE_S_MM
6173 { 1361, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1361 = C_OLE_S
6174 { 1360, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1360 = C_OLE_D64_MM
6175 { 1359, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1359 = C_OLE_D64
6176 { 1358, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1358 = C_OLE_D32_MM
6177 { 1357, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1357 = C_OLE_D32
6178 { 1356, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1356 = C_NGT_S_MM
6179 { 1355, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1355 = C_NGT_S
6180 { 1354, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1354 = C_NGT_D64_MM
6181 { 1353, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1353 = C_NGT_D64
6182 { 1352, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1352 = C_NGT_D32_MM
6183 { 1351, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1351 = C_NGT_D32
6184 { 1350, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1350 = C_NGL_S_MM
6185 { 1349, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1349 = C_NGL_S
6186 { 1348, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1348 = C_NGL_D64_MM
6187 { 1347, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1347 = C_NGL_D64
6188 { 1346, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1346 = C_NGL_D32_MM
6189 { 1345, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1345 = C_NGL_D32
6190 { 1344, 3, 1, 4, 1265, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1344 = C_NGLE_S_MM
6191 { 1343, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1343 = C_NGLE_S
6192 { 1342, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1342 = C_NGLE_D64_MM
6193 { 1341, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1341 = C_NGLE_D64
6194 { 1340, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1340 = C_NGLE_D32_MM
6195 { 1339, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1339 = C_NGLE_D32
6196 { 1338, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1338 = C_NGE_S_MM
6197 { 1337, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1337 = C_NGE_S
6198 { 1336, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1336 = C_NGE_D64_MM
6199 { 1335, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1335 = C_NGE_D64
6200 { 1334, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1334 = C_NGE_D32_MM
6201 { 1333, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1333 = C_NGE_D32
6202 { 1332, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1332 = C_LT_S_MM
6203 { 1331, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1331 = C_LT_S
6204 { 1330, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1330 = C_LT_D64_MM
6205 { 1329, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1329 = C_LT_D64
6206 { 1328, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1328 = C_LT_D32_MM
6207 { 1327, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1327 = C_LT_D32
6208 { 1326, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1326 = C_LE_S_MM
6209 { 1325, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1325 = C_LE_S
6210 { 1324, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1324 = C_LE_D64_MM
6211 { 1323, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1323 = C_LE_D64
6212 { 1322, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1322 = C_LE_D32_MM
6213 { 1321, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1321 = C_LE_D32
6214 { 1320, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1320 = C_F_S_MM
6215 { 1319, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1319 = C_F_S
6216 { 1318, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1318 = C_F_D64_MM
6217 { 1317, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1317 = C_F_D64
6218 { 1316, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1316 = C_F_D32_MM
6219 { 1315, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1315 = C_F_D32
6220 { 1314, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1314 = C_EQ_S_MM
6221 { 1313, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1313 = C_EQ_S
6222 { 1312, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1312 = C_EQ_D64_MM
6223 { 1311, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1311 = C_EQ_D64
6224 { 1310, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1310 = C_EQ_D32_MM
6225 { 1309, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1309 = C_EQ_D32
6226 { 1308, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1308 = CVT_W_S_MMR6
6227 { 1307, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1307 = CVT_W_S_MM
6228 { 1306, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1306 = CVT_W_S
6229 { 1305, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1305 = CVT_W_D64_MM
6230 { 1304, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1304 = CVT_W_D64
6231 { 1303, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1303 = CVT_W_D32_MM
6232 { 1302, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1302 = CVT_W_D32
6233 { 1301, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1301 = CVT_S_W_MMR6
6234 { 1300, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1300 = CVT_S_W_MM
6235 { 1299, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1299 = CVT_S_W
6236 { 1298, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1298 = CVT_S_PU64
6237 { 1297, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1297 = CVT_S_PL64
6238 { 1296, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1296 = CVT_S_L_MMR6
6239 { 1295, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1295 = CVT_S_L
6240 { 1294, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1294 = CVT_S_D64_MM
6241 { 1293, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1293 = CVT_S_D64
6242 { 1292, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1292 = CVT_S_D32_MM
6243 { 1291, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1291 = CVT_S_D32
6244 { 1290, 2, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1290 = CVT_PW_PS64
6245 { 1289, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1289 = CVT_PS_S64
6246 { 1288, 2, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1288 = CVT_PS_PW64
6247 { 1287, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1287 = CVT_L_S_MMR6
6248 { 1286, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1286 = CVT_L_S_MM
6249 { 1285, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1285 = CVT_L_S
6250 { 1284, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1284 = CVT_L_D_MMR6
6251 { 1283, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1283 = CVT_L_D64_MM
6252 { 1282, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1282 = CVT_L_D64
6253 { 1281, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1281 = CVT_D_L_MMR6
6254 { 1280, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1280 = CVT_D64_W_MM
6255 { 1279, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1279 = CVT_D64_W
6256 { 1278, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1278 = CVT_D64_S_MM
6257 { 1277, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1277 = CVT_D64_S
6258 { 1276, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1276 = CVT_D64_L
6259 { 1275, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1275 = CVT_D32_W_MM
6260 { 1274, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1274 = CVT_D32_W
6261 { 1273, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1273 = CVT_D32_S_MM
6262 { 1272, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1272 = CVT_D32_S
6263 { 1271, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1271 = CTCMSA
6264 { 1270, 2, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1270 = CTC2_MM
6265 { 1269, 2, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 684, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1269 = CTC1_MM
6266 { 1268, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 684, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1268 = CTC1
6267 { 1267, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1267 = CRC32W
6268 { 1266, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1266 = CRC32H
6269 { 1265, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1265 = CRC32D
6270 { 1264, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1264 = CRC32CW
6271 { 1263, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1263 = CRC32CH
6272 { 1262, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1262 = CRC32CD
6273 { 1261, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1261 = CRC32CB
6274 { 1260, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1260 = CRC32B
6275 { 1259, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 681, 0, 0x6ULL }, // Inst #1259 = COPY_U_W
6276 { 1258, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 678, 0, 0x6ULL }, // Inst #1258 = COPY_U_H
6277 { 1257, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 672, 0, 0x6ULL }, // Inst #1257 = COPY_U_B
6278 { 1256, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 681, 0, 0x6ULL }, // Inst #1256 = COPY_S_W
6279 { 1255, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 678, 0, 0x6ULL }, // Inst #1255 = COPY_S_H
6280 { 1254, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 675, 0, 0x6ULL }, // Inst #1254 = COPY_S_D
6281 { 1253, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 672, 0, 0x6ULL }, // Inst #1253 = COPY_S_B
6282 { 1252, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1252 = CMP_UN_S_MMR6
6283 { 1251, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1251 = CMP_UN_S
6284 { 1250, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1250 = CMP_UN_D_MMR6
6285 { 1249, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1249 = CMP_UN_D
6286 { 1248, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1248 = CMP_ULT_S_MMR6
6287 { 1247, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1247 = CMP_ULT_S
6288 { 1246, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1246 = CMP_ULT_D_MMR6
6289 { 1245, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1245 = CMP_ULT_D
6290 { 1244, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1244 = CMP_ULE_S_MMR6
6291 { 1243, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1243 = CMP_ULE_S
6292 { 1242, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1242 = CMP_ULE_D_MMR6
6293 { 1241, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1241 = CMP_ULE_D
6294 { 1240, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1240 = CMP_UEQ_S_MMR6
6295 { 1239, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1239 = CMP_UEQ_S
6296 { 1238, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1238 = CMP_UEQ_D_MMR6
6297 { 1237, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1237 = CMP_UEQ_D
6298 { 1236, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1236 = CMP_SUN_S_MMR6
6299 { 1235, 3, 1, 4, 1689, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1235 = CMP_SUN_S
6300 { 1234, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1234 = CMP_SUN_D_MMR6
6301 { 1233, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1233 = CMP_SUN_D
6302 { 1232, 3, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1232 = CMP_SULT_S_MMR6
6303 { 1231, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1231 = CMP_SULT_S
6304 { 1230, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1230 = CMP_SULT_D_MMR6
6305 { 1229, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1229 = CMP_SULT_D
6306 { 1228, 3, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1228 = CMP_SULE_S_MMR6
6307 { 1227, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1227 = CMP_SULE_S
6308 { 1226, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1226 = CMP_SULE_D_MMR6
6309 { 1225, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1225 = CMP_SULE_D
6310 { 1224, 3, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1224 = CMP_SUEQ_S_MMR6
6311 { 1223, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1223 = CMP_SUEQ_S
6312 { 1222, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1222 = CMP_SUEQ_D_MMR6
6313 { 1221, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1221 = CMP_SUEQ_D
6314 { 1220, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1220 = CMP_SLT_S_MMR6
6315 { 1219, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1219 = CMP_SLT_S
6316 { 1218, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1218 = CMP_SLT_D_MMR6
6317 { 1217, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1217 = CMP_SLT_D
6318 { 1216, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1216 = CMP_SLE_S_MMR6
6319 { 1215, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1215 = CMP_SLE_S
6320 { 1214, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1214 = CMP_SLE_D_MMR6
6321 { 1213, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1213 = CMP_SLE_D
6322 { 1212, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1212 = CMP_SEQ_S_MMR6
6323 { 1211, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1211 = CMP_SEQ_S
6324 { 1210, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1210 = CMP_SEQ_D_MMR6
6325 { 1209, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1209 = CMP_SEQ_D
6326 { 1208, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1208 = CMP_SAF_S_MMR6
6327 { 1207, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1207 = CMP_SAF_S
6328 { 1206, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1206 = CMP_SAF_D_MMR6
6329 { 1205, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1205 = CMP_SAF_D
6330 { 1204, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1204 = CMP_LT_S_MMR6
6331 { 1203, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1203 = CMP_LT_S
6332 { 1202, 2, 0, 4, 1528, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1202 = CMP_LT_PH_MM
6333 { 1201, 2, 0, 4, 1377, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1201 = CMP_LT_PH
6334 { 1200, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1200 = CMP_LT_D_MMR6
6335 { 1199, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1199 = CMP_LT_D
6336 { 1198, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1198 = CMP_LE_S_MMR6
6337 { 1197, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1197 = CMP_LE_S
6338 { 1196, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1196 = CMP_LE_PH_MM
6339 { 1195, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1195 = CMP_LE_PH
6340 { 1194, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1194 = CMP_LE_D_MMR6
6341 { 1193, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1193 = CMP_LE_D
6342 { 1192, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1192 = CMP_F_S
6343 { 1191, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1191 = CMP_F_D
6344 { 1190, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1190 = CMP_EQ_S_MMR6
6345 { 1189, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1189 = CMP_EQ_S
6346 { 1188, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1188 = CMP_EQ_PH_MM
6347 { 1187, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1187 = CMP_EQ_PH
6348 { 1186, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1186 = CMP_EQ_D_MMR6
6349 { 1185, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1185 = CMP_EQ_D
6350 { 1184, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1184 = CMP_AF_S_MMR6
6351 { 1183, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1183 = CMP_AF_D_MMR6
6352 { 1182, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1182 = CMPU_LT_QB_MM
6353 { 1181, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1181 = CMPU_LT_QB
6354 { 1180, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1180 = CMPU_LE_QB_MM
6355 { 1179, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1179 = CMPU_LE_QB
6356 { 1178, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1178 = CMPU_EQ_QB_MM
6357 { 1177, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1177 = CMPU_EQ_QB
6358 { 1176, 3, 1, 4, 1522, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1176 = CMPGU_LT_QB_MM
6359 { 1175, 3, 1, 4, 1371, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1175 = CMPGU_LT_QB
6360 { 1174, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1174 = CMPGU_LE_QB_MM
6361 { 1173, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1173 = CMPGU_LE_QB
6362 { 1172, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1172 = CMPGU_EQ_QB_MM
6363 { 1171, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1171 = CMPGU_EQ_QB
6364 { 1170, 3, 1, 4, 1638, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1170 = CMPGDU_LT_QB_MMR2
6365 { 1169, 3, 1, 4, 1474, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1169 = CMPGDU_LT_QB
6366 { 1168, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1168 = CMPGDU_LE_QB_MMR2
6367 { 1167, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1167 = CMPGDU_LE_QB
6368 { 1166, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1166 = CMPGDU_EQ_QB_MMR2
6369 { 1165, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1165 = CMPGDU_EQ_QB
6370 { 1164, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #1164 = CLZ_R6
6371 { 1163, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1163 = CLZ_MMR6
6372 { 1162, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1162 = CLZ_MM
6373 { 1161, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1161 = CLZ
6374 { 1160, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1160 = CLT_U_W
6375 { 1159, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1159 = CLT_U_H
6376 { 1158, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1158 = CLT_U_D
6377 { 1157, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1157 = CLT_U_B
6378 { 1156, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1156 = CLT_S_W
6379 { 1155, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1155 = CLT_S_H
6380 { 1154, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1154 = CLT_S_D
6381 { 1153, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1153 = CLT_S_B
6382 { 1152, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1152 = CLTI_U_W
6383 { 1151, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1151 = CLTI_U_H
6384 { 1150, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1150 = CLTI_U_D
6385 { 1149, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1149 = CLTI_U_B
6386 { 1148, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1148 = CLTI_S_W
6387 { 1147, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1147 = CLTI_S_H
6388 { 1146, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1146 = CLTI_S_D
6389 { 1145, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1145 = CLTI_S_B
6390 { 1144, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #1144 = CLO_R6
6391 { 1143, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1143 = CLO_MMR6
6392 { 1142, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1142 = CLO_MM
6393 { 1141, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1141 = CLO
6394 { 1140, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1140 = CLE_U_W
6395 { 1139, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1139 = CLE_U_H
6396 { 1138, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1138 = CLE_U_D
6397 { 1137, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1137 = CLE_U_B
6398 { 1136, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1136 = CLE_S_W
6399 { 1135, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1135 = CLE_S_H
6400 { 1134, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1134 = CLE_S_D
6401 { 1133, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1133 = CLE_S_B
6402 { 1132, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1132 = CLEI_U_W
6403 { 1131, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1131 = CLEI_U_H
6404 { 1130, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1130 = CLEI_U_D
6405 { 1129, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1129 = CLEI_U_B
6406 { 1128, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1128 = CLEI_S_W
6407 { 1127, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1127 = CLEI_S_H
6408 { 1126, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1126 = CLEI_S_D
6409 { 1125, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1125 = CLEI_S_B
6410 { 1124, 2, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1124 = CLASS_S_MMR6
6411 { 1123, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1123 = CLASS_S
6412 { 1122, 2, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1122 = CLASS_D_MMR6
6413 { 1121, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1121 = CLASS_D
6414 { 1120, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1120 = CINS_i32
6415 { 1119, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 655, 0, 0x1ULL }, // Inst #1119 = CINS64_32
6416 { 1118, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1118 = CINS32
6417 { 1117, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1117 = CINS
6418 { 1116, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 649, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1116 = CFCMSA
6419 { 1115, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 647, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1115 = CFC2_MM
6420 { 1114, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 645, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1114 = CFC1_MM
6421 { 1113, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 645, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1113 = CFC1
6422 { 1112, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1112 = CEQ_W
6423 { 1111, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1111 = CEQ_H
6424 { 1110, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1110 = CEQ_D
6425 { 1109, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1109 = CEQ_B
6426 { 1108, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1108 = CEQI_W
6427 { 1107, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1107 = CEQI_H
6428 { 1106, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1106 = CEQI_D
6429 { 1105, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1105 = CEQI_B
6430 { 1104, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1104 = CEIL_W_S_MMR6
6431 { 1103, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1103 = CEIL_W_S_MM
6432 { 1102, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1102 = CEIL_W_S
6433 { 1101, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1101 = CEIL_W_MM
6434 { 1100, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1100 = CEIL_W_D_MMR6
6435 { 1099, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1099 = CEIL_W_D64
6436 { 1098, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1098 = CEIL_W_D32
6437 { 1097, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1097 = CEIL_L_S_MMR6
6438 { 1096, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1096 = CEIL_L_S
6439 { 1095, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1095 = CEIL_L_D_MMR6
6440 { 1094, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1094 = CEIL_L_D64
6441 { 1093, 3, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1093 = CACHE_R6
6442 { 1092, 3, 0, 4, 1163, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1092 = CACHE_MMR6
6443 { 1091, 3, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1091 = CACHE_MM
6444 { 1090, 3, 0, 4, 1108, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1090 = CACHEE_MM
6445 { 1089, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1089 = CACHEE
6446 { 1088, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1088 = CACHE
6447 { 1087, 1, 0, 4, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1087 = BtnezX16
6448 { 1086, 1, 0, 2, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1086 = Btnez16
6449 { 1085, 1, 0, 4, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1085 = BteqzX16
6450 { 1084, 1, 0, 2, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1084 = Bteqz16
6451 { 1083, 0, 0, 2, 944, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1083 = Break16
6452 { 1082, 2, 0, 4, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1082 = BnezRxImmX16
6453 { 1081, 2, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1081 = BnezRxImm16
6454 { 1080, 1, 0, 4, 940, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1080 = BimmX16
6455 { 1079, 1, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1079 = Bimm16
6456 { 1078, 2, 0, 4, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1078 = BeqzRxImmX16
6457 { 1077, 2, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1077 = BeqzRxImm16
6458 { 1076, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1076 = BZ_W
6459 { 1075, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1075 = BZ_V
6460 { 1074, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 626, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1074 = BZ_H
6461 { 1073, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 624, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1073 = BZ_D
6462 { 1072, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1072 = BZ_B
6463 { 1071, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1071 = BSET_W
6464 { 1070, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1070 = BSET_H
6465 { 1069, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1069 = BSET_D
6466 { 1068, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1068 = BSET_B
6467 { 1067, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1067 = BSETI_W
6468 { 1066, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1066 = BSETI_H
6469 { 1065, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1065 = BSETI_D
6470 { 1064, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1064 = BSETI_B
6471 { 1063, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1063 = BSEL_V
6472 { 1062, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1062 = BSELI_B
6473 { 1061, 2, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1061 = BREAK_MMR6
6474 { 1060, 2, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1060 = BREAK_MM
6475 { 1059, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1059 = BREAK16_MMR6
6476 { 1058, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1058 = BREAK16_MM
6477 { 1057, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1057 = BREAK
6478 { 1056, 1, 0, 4, 1519, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1056 = BPOSGE32_MM
6479 { 1055, 1, 0, 4, 1671, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1055 = BPOSGE32C_MMR3
6480 { 1054, 1, 0, 4, 1368, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1054 = BPOSGE32
6481 { 1053, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1053 = BOVC_MMR6
6482 { 1052, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1052 = BOVC
6483 { 1051, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1051 = BNZ_W
6484 { 1050, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1050 = BNZ_V
6485 { 1049, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 626, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1049 = BNZ_H
6486 { 1048, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 624, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1048 = BNZ_D
6487 { 1047, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1047 = BNZ_B
6488 { 1046, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1046 = BNVC_MMR6
6489 { 1045, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1045 = BNVC
6490 { 1044, 3, 0, 4, 952, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1044 = BNE_MM
6491 { 1043, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #1043 = BNEZC_MMR6
6492 { 1042, 2, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1042 = BNEZC_MM
6493 { 1041, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1041 = BNEZC64
6494 { 1040, 2, 0, 2, 987, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1040 = BNEZC16_MMR6
6495 { 1039, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1039 = BNEZC
6496 { 1038, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1038 = BNEZALC_MMR6
6497 { 1037, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1037 = BNEZALC
6498 { 1036, 2, 0, 2, 950, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1036 = BNEZ16_MM
6499 { 1035, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1035 = BNEL
6500 { 1034, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1034 = BNEG_W
6501 { 1033, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1033 = BNEG_H
6502 { 1032, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1032 = BNEG_D
6503 { 1031, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1031 = BNEG_B
6504 { 1030, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1030 = BNEGI_W
6505 { 1029, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1029 = BNEGI_H
6506 { 1028, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1028 = BNEGI_D
6507 { 1027, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1027 = BNEGI_B
6508 { 1026, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1026 = BNEC_MMR6
6509 { 1025, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1025 = BNEC64
6510 { 1024, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1024 = BNEC
6511 { 1023, 3, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1023 = BNE64
6512 { 1022, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1022 = BNE
6513 { 1021, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1021 = BMZ_V
6514 { 1020, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1020 = BMZI_B
6515 { 1019, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1019 = BMNZ_V
6516 { 1018, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1018 = BMNZI_B
6517 { 1017, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1017 = BLTZ_MM
6518 { 1016, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1016 = BLTZL
6519 { 1015, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1015 = BLTZC_MMR6
6520 { 1014, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1014 = BLTZC64
6521 { 1013, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1013 = BLTZC
6522 { 1012, 2, 0, 4, 959, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1012 = BLTZAL_MM
6523 { 1011, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1011 = BLTZALS_MM
6524 { 1010, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1010 = BLTZALL
6525 { 1009, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1009 = BLTZALC_MMR6
6526 { 1008, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1008 = BLTZALC
6527 { 1007, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1007 = BLTZAL
6528 { 1006, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1006 = BLTZ64
6529 { 1005, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1005 = BLTZ
6530 { 1004, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1004 = BLTUC_MMR6
6531 { 1003, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1003 = BLTUC64
6532 { 1002, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1002 = BLTUC
6533 { 1001, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1001 = BLTC_MMR6
6534 { 1000, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1000 = BLTC64
6535 { 999, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #999 = BLTC
6536 { 998, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #998 = BLEZ_MM
6537 { 997, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #997 = BLEZL
6538 { 996, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #996 = BLEZC_MMR6
6539 { 995, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #995 = BLEZC64
6540 { 994, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #994 = BLEZC
6541 { 993, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #993 = BLEZALC_MMR6
6542 { 992, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #992 = BLEZALC
6543 { 991, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #991 = BLEZ64
6544 { 990, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #990 = BLEZ
6545 { 989, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #989 = BITSWAP_MMR6
6546 { 988, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #988 = BITSWAP
6547 { 987, 2, 1, 4, 1518, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #987 = BITREV_MM
6548 { 986, 2, 1, 4, 1367, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #986 = BITREV
6549 { 985, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #985 = BINSR_W
6550 { 984, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #984 = BINSR_H
6551 { 983, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #983 = BINSR_D
6552 { 982, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #982 = BINSR_B
6553 { 981, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 614, 0, 0x6ULL }, // Inst #981 = BINSRI_W
6554 { 980, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 610, 0, 0x6ULL }, // Inst #980 = BINSRI_H
6555 { 979, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #979 = BINSRI_D
6556 { 978, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #978 = BINSRI_B
6557 { 977, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #977 = BINSL_W
6558 { 976, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #976 = BINSL_H
6559 { 975, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #975 = BINSL_D
6560 { 974, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #974 = BINSL_B
6561 { 973, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 614, 0, 0x6ULL }, // Inst #973 = BINSLI_W
6562 { 972, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 610, 0, 0x6ULL }, // Inst #972 = BINSLI_H
6563 { 971, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #971 = BINSLI_D
6564 { 970, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #970 = BINSLI_B
6565 { 969, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #969 = BGTZ_MM
6566 { 968, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #968 = BGTZL
6567 { 967, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #967 = BGTZC_MMR6
6568 { 966, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #966 = BGTZC64
6569 { 965, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #965 = BGTZC
6570 { 964, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #964 = BGTZALC_MMR6
6571 { 963, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #963 = BGTZALC
6572 { 962, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #962 = BGTZ64
6573 { 961, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #961 = BGTZ
6574 { 960, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #960 = BGEZ_MM
6575 { 959, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #959 = BGEZL
6576 { 958, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #958 = BGEZC_MMR6
6577 { 957, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #957 = BGEZC64
6578 { 956, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #956 = BGEZC
6579 { 955, 2, 0, 4, 959, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #955 = BGEZAL_MM
6580 { 954, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #954 = BGEZALS_MM
6581 { 953, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #953 = BGEZALL
6582 { 952, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #952 = BGEZALC_MMR6
6583 { 951, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #951 = BGEZALC
6584 { 950, 2, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #950 = BGEZAL
6585 { 949, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #949 = BGEZ64
6586 { 948, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #948 = BGEZ
6587 { 947, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #947 = BGEUC_MMR6
6588 { 946, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #946 = BGEUC64
6589 { 945, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #945 = BGEUC
6590 { 944, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #944 = BGEC_MMR6
6591 { 943, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #943 = BGEC64
6592 { 942, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #942 = BGEC
6593 { 941, 3, 0, 4, 952, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #941 = BEQ_MM
6594 { 940, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #940 = BEQZC_MMR6
6595 { 939, 2, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #939 = BEQZC_MM
6596 { 938, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #938 = BEQZC64
6597 { 937, 2, 0, 2, 987, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #937 = BEQZC16_MMR6
6598 { 936, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #936 = BEQZC
6599 { 935, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #935 = BEQZALC_MMR6
6600 { 934, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #934 = BEQZALC
6601 { 933, 2, 0, 2, 950, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #933 = BEQZ16_MM
6602 { 932, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #932 = BEQL
6603 { 931, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #931 = BEQC_MMR6
6604 { 930, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #930 = BEQC64
6605 { 929, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #929 = BEQC
6606 { 928, 3, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #928 = BEQ64
6607 { 927, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #927 = BEQ
6608 { 926, 1, 0, 4, 983, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL }, // Inst #926 = BC_MMR6
6609 { 925, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #925 = BCLR_W
6610 { 924, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #924 = BCLR_H
6611 { 923, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #923 = BCLR_D
6612 { 922, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #922 = BCLR_B
6613 { 921, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #921 = BCLRI_W
6614 { 920, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #920 = BCLRI_H
6615 { 919, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #919 = BCLRI_D
6616 { 918, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #918 = BCLRI_B
6617 { 917, 2, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #917 = BC2NEZC_MMR6
6618 { 916, 2, 0, 4, 931, 0, 0, MipsImpOpBase + 0, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #916 = BC2NEZ
6619 { 915, 2, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #915 = BC2EQZC_MMR6
6620 { 914, 2, 0, 4, 931, 0, 0, MipsImpOpBase + 0, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #914 = BC2EQZ
6621 { 913, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #913 = BC1T_MM
6622 { 912, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #912 = BC1TL
6623 { 911, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #911 = BC1T
6624 { 910, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #910 = BC1NEZC_MMR6
6625 { 909, 2, 0, 4, 1232, 0, 0, MipsImpOpBase + 0, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #909 = BC1NEZ
6626 { 908, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #908 = BC1F_MM
6627 { 907, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #907 = BC1FL
6628 { 906, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #906 = BC1F
6629 { 905, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #905 = BC1EQZC_MMR6
6630 { 904, 2, 0, 4, 1232, 0, 0, MipsImpOpBase + 0, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #904 = BC1EQZ
6631 { 903, 1, 0, 2, 983, 0, 1, MipsImpOpBase + 2, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #903 = BC16_MMR6
6632 { 902, 1, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #902 = BC
6633 { 901, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #901 = BBIT132
6634 { 900, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #900 = BBIT1
6635 { 899, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #899 = BBIT032
6636 { 898, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #898 = BBIT0
6637 { 897, 4, 1, 4, 1635, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #897 = BALIGN_MMR2
6638 { 896, 4, 1, 4, 1471, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #896 = BALIGN
6639 { 895, 1, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #895 = BALC_MMR6
6640 { 894, 1, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #894 = BALC
6641 { 893, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #893 = BAL
6642 { 892, 3, 1, 4, 1199, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #892 = BADDu
6643 { 891, 1, 0, 2, 946, 0, 1, MipsImpOpBase + 2, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #891 = B16_MM
6644 { 890, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #890 = AndRxRxRy16
6645 { 889, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #889 = AdduRxRyRz16
6646 { 888, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #888 = AddiuSpImmX16
6647 { 887, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #887 = AddiuSpImm16
6648 { 886, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 585, 0, 0x0ULL }, // Inst #886 = AddiuRxRyOffMemX16
6649 { 885, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 582, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #885 = AddiuRxRxImmX16
6650 { 884, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 582, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #884 = AddiuRxRxImm16
6651 { 883, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #883 = AddiuRxPcImmX16
6652 { 882, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #882 = AddiuRxImmX16
6653 { 881, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #881 = AVE_U_W
6654 { 880, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #880 = AVE_U_H
6655 { 879, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #879 = AVE_U_D
6656 { 878, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #878 = AVE_U_B
6657 { 877, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #877 = AVE_S_W
6658 { 876, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #876 = AVE_S_H
6659 { 875, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #875 = AVE_S_D
6660 { 874, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #874 = AVE_S_B
6661 { 873, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #873 = AVER_U_W
6662 { 872, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #872 = AVER_U_H
6663 { 871, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #871 = AVER_U_D
6664 { 870, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #870 = AVER_U_B
6665 { 869, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #869 = AVER_S_W
6666 { 868, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #868 = AVER_S_H
6667 { 867, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #867 = AVER_S_D
6668 { 866, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #866 = AVER_S_B
6669 { 865, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #865 = AUI_MMR6
6670 { 864, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #864 = AUIPC_MMR6
6671 { 863, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #863 = AUIPC
6672 { 862, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #862 = AUI
6673 { 861, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #861 = ASUB_U_W
6674 { 860, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #860 = ASUB_U_H
6675 { 859, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #859 = ASUB_U_D
6676 { 858, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #858 = ASUB_U_B
6677 { 857, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #857 = ASUB_S_W
6678 { 856, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #856 = ASUB_S_H
6679 { 855, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #855 = ASUB_S_D
6680 { 854, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #854 = ASUB_S_B
6681 { 853, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #853 = APPEND_MMR2
6682 { 852, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #852 = APPEND
6683 { 851, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #851 = ANDi_MM
6684 { 850, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #850 = ANDi64
6685 { 849, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #849 = ANDi
6686 { 848, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #848 = AND_V
6687 { 847, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #847 = AND_MMR6
6688 { 846, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #846 = AND_MM
6689 { 845, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #845 = ANDI_MMR6
6690 { 844, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #844 = ANDI_B
6691 { 843, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #843 = ANDI16_MMR6
6692 { 842, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #842 = ANDI16_MM
6693 { 841, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #841 = AND64
6694 { 840, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #840 = AND16_MMR6
6695 { 839, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #839 = AND16_MM
6696 { 838, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #838 = AND
6697 { 837, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #837 = ALUIPC_MMR6
6698 { 836, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #836 = ALUIPC
6699 { 835, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #835 = ALIGN_MMR6
6700 { 834, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #834 = ALIGN
6701 { 833, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #833 = ADDu_MM
6702 { 832, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #832 = ADDu
6703 { 831, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #831 = ADDiu_MM
6704 { 830, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #830 = ADDiu
6705 { 829, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #829 = ADDi_MM
6706 { 828, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #828 = ADDi
6707 { 827, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #827 = ADD_MMR6
6708 { 826, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #826 = ADD_MM
6709 { 825, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #825 = ADD_A_W
6710 { 824, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #824 = ADD_A_H
6711 { 823, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #823 = ADD_A_D
6712 { 822, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #822 = ADD_A_B
6713 { 821, 3, 1, 4, 1517, 1, 1, MipsImpOpBase + 12, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #821 = ADDWC_MM
6714 { 820, 3, 1, 4, 1366, 1, 1, MipsImpOpBase + 12, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #820 = ADDWC
6715 { 819, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #819 = ADDV_W
6716 { 818, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #818 = ADDV_H
6717 { 817, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #817 = ADDV_D
6718 { 816, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #816 = ADDV_B
6719 { 815, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #815 = ADDVI_W
6720 { 814, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #814 = ADDVI_H
6721 { 813, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #813 = ADDVI_D
6722 { 812, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #812 = ADDVI_B
6723 { 811, 3, 1, 4, 1516, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #811 = ADDU_S_QB_MM
6724 { 810, 3, 1, 4, 1365, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #810 = ADDU_S_QB
6725 { 809, 3, 1, 4, 1633, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #809 = ADDU_S_PH_MMR2
6726 { 808, 3, 1, 4, 1469, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #808 = ADDU_S_PH
6727 { 807, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #807 = ADDU_QB_MM
6728 { 806, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #806 = ADDU_QB
6729 { 805, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #805 = ADDU_PH_MMR2
6730 { 804, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #804 = ADDU_PH
6731 { 803, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #803 = ADDU_MMR6
6732 { 802, 3, 1, 4, 1631, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #802 = ADDUH_R_QB_MMR2
6733 { 801, 3, 1, 4, 1467, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #801 = ADDUH_R_QB
6734 { 800, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #800 = ADDUH_QB_MMR2
6735 { 799, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #799 = ADDUH_QB
6736 { 798, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 554, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #798 = ADDU16_MMR6
6737 { 797, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 554, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #797 = ADDU16_MM
6738 { 796, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #796 = ADDS_U_W
6739 { 795, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #795 = ADDS_U_H
6740 { 794, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #794 = ADDS_U_D
6741 { 793, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #793 = ADDS_U_B
6742 { 792, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #792 = ADDS_S_W
6743 { 791, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #791 = ADDS_S_H
6744 { 790, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #790 = ADDS_S_D
6745 { 789, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #789 = ADDS_S_B
6746 { 788, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #788 = ADDS_A_W
6747 { 787, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #787 = ADDS_A_H
6748 { 786, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #786 = ADDS_A_D
6749 { 785, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #785 = ADDS_A_B
6750 { 784, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 11, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #784 = ADDSC_MM
6751 { 783, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 11, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #783 = ADDSC
6752 { 782, 3, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #782 = ADDR_PS64
6753 { 781, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #781 = ADDQ_S_W_MM
6754 { 780, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #780 = ADDQ_S_W
6755 { 779, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #779 = ADDQ_S_PH_MM
6756 { 778, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #778 = ADDQ_S_PH
6757 { 777, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #777 = ADDQ_PH_MM
6758 { 776, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #776 = ADDQ_PH
6759 { 775, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #775 = ADDQH_W_MMR2
6760 { 774, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #774 = ADDQH_W
6761 { 773, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #773 = ADDQH_R_W_MMR2
6762 { 772, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #772 = ADDQH_R_W
6763 { 771, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #771 = ADDQH_R_PH_MMR2
6764 { 770, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #770 = ADDQH_R_PH
6765 { 769, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #769 = ADDQH_PH_MMR2
6766 { 768, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #768 = ADDQH_PH
6767 { 767, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #767 = ADDIU_MMR6
6768 { 766, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #766 = ADDIUSP_MM
6769 { 765, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 542, 0, 0x0ULL }, // Inst #765 = ADDIUS5_MM
6770 { 764, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #764 = ADDIUR2_MM
6771 { 763, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #763 = ADDIUR1SP_MM
6772 { 762, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #762 = ADDIUPC_MMR6
6773 { 761, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #761 = ADDIUPC_MM
6774 { 760, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #760 = ADDIUPC
6775 { 759, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #759 = ADD
6776 { 758, 2, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #758 = ABSQ_S_W_MM
6777 { 757, 2, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #757 = ABSQ_S_W
6778 { 756, 2, 1, 4, 1625, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #756 = ABSQ_S_QB_MMR2
6779 { 755, 2, 1, 4, 1461, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #755 = ABSQ_S_QB
6780 { 754, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #754 = ABSQ_S_PH_MM
6781 { 753, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #753 = ABSQ_S_PH
6782 { 752, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #752 = XOR_V_W_PSEUDO
6783 { 751, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #751 = XOR_V_H_PSEUDO
6784 { 750, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #750 = XOR_V_D_PSEUDO
6785 { 749, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #749 = Usw
6786 { 748, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #748 = Ush
6787 { 747, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #747 = Ulw
6788 { 746, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #746 = Ulhu
6789 { 745, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #745 = Ulh
6790 { 744, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #744 = URemMacro
6791 { 743, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #743 = URemIMacro
6792 { 742, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #742 = UDivMacro
6793 { 741, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #741 = UDivIMacro
6794 { 740, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #740 = UDIV_MM_Pseudo
6795 { 739, 0, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = TRAP_MM
6796 { 738, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = TRAP
6797 { 737, 1, 0, 4, 1007, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #737 = TAILCALL_MMR6
6798 { 736, 1, 0, 4, 965, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #736 = TAILCALL_MM
6799 { 735, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #735 = TAILCALLREG_MMR6
6800 { 734, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #734 = TAILCALLREG_MM
6801 { 733, 1, 0, 4, 1016, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #733 = TAILCALLREGHB64
6802 { 732, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #732 = TAILCALLREGHB
6803 { 731, 1, 0, 4, 1016, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #731 = TAILCALLREG64
6804 { 730, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #730 = TAILCALLREG
6805 { 729, 1, 0, 4, 938, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #729 = TAILCALLR6REG
6806 { 728, 1, 0, 4, 938, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #728 = TAILCALLHBR6REG
6807 { 727, 1, 0, 4, 1024, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #727 = TAILCALLHB64R6REG
6808 { 726, 1, 0, 4, 1024, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #726 = TAILCALL64R6REG
6809 { 725, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #725 = TAILCALL
6810 { 724, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #724 = SltuRxRyRz16
6811 { 723, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #723 = SltuCCRxRy16
6812 { 722, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 532, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #722 = SltiuCCRxImmX16
6813 { 721, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 532, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #721 = SltiCCRxImmX16
6814 { 720, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #720 = SltCCRxRy16
6815 { 719, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #719 = SelTBtneZSltu
6816 { 718, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = SelTBtneZSltiu
6817 { 717, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #717 = SelTBtneZSlti
6818 { 716, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #716 = SelTBtneZSlt
6819 { 715, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #715 = SelTBtneZCmpi
6820 { 714, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #714 = SelTBtneZCmp
6821 { 713, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #713 = SelTBteqZSltu
6822 { 712, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #712 = SelTBteqZSltiu
6823 { 711, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #711 = SelTBteqZSlti
6824 { 710, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #710 = SelTBteqZSlt
6825 { 709, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #709 = SelTBteqZCmpi
6826 { 708, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #708 = SelTBteqZCmp
6827 { 707, 4, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 518, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #707 = SelBneZ
6828 { 706, 4, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 518, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #706 = SelBeqZ
6829 { 705, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #705 = SaadAddr
6830 { 704, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #704 = SaaAddr
6831 { 703, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #703 = SZ_W_PSEUDO
6832 { 702, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #702 = SZ_V_PSEUDO
6833 { 701, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 514, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #701 = SZ_H_PSEUDO
6834 { 700, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 512, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #700 = SZ_D_PSEUDO
6835 { 699, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #699 = SZ_B_PSEUDO
6836 { 698, 3, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #698 = SWM_MM
6837 { 697, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #697 = ST_F16
6838 { 696, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 325, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #696 = STR_W
6839 { 695, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 322, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #695 = STR_D
6840 { 694, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #694 = STORE_CCOND_DSP
6841 { 693, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 337, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #693 = STORE_ACC64DSP
6842 { 692, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 334, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #692 = STORE_ACC64
6843 { 691, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #691 = STORE_ACC128
6844 { 690, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = SRemMacro
6845 { 689, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = SRemIMacro
6846 { 688, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #688 = SNZ_W_PSEUDO
6847 { 687, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #687 = SNZ_V_PSEUDO
6848 { 686, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 514, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #686 = SNZ_H_PSEUDO
6849 { 685, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 512, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #685 = SNZ_D_PSEUDO
6850 { 684, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #684 = SNZ_B_PSEUDO
6851 { 683, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = SNEMacro
6852 { 682, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = SNEIMacro
6853 { 681, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = SLTUImm64
6854 { 680, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = SLTImm64
6855 { 679, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = SLEUImm64
6856 { 678, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #678 = SLEUImm
6857 { 677, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #677 = SLEU
6858 { 676, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #676 = SLEImm64
6859 { 675, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #675 = SLEImm
6860 { 674, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = SLE
6861 { 673, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #673 = SGTUImm64
6862 { 672, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #672 = SGTUImm
6863 { 671, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = SGTImm64
6864 { 670, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #670 = SGTImm
6865 { 669, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = SGEUImm64
6866 { 668, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #668 = SGEUImm
6867 { 667, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #667 = SGEU
6868 { 666, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = SGEImm64
6869 { 665, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #665 = SGEImm
6870 { 664, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = SGE
6871 { 663, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = SEQMacro
6872 { 662, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #662 = SEQIMacro
6873 { 661, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 507, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #661 = SDivMacro
6874 { 660, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #660 = SDivIMacro
6875 { 659, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = SDMacro
6876 { 658, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = SDIV_MM_Pseudo
6877 { 657, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = SDC1_M1
6878 { 656, 0, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL }, // Inst #656 = RetRA16
6879 { 655, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #655 = RetRA
6880 { 654, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = RORImm
6881 { 653, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #653 = ROR
6882 { 652, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #652 = ROLImm
6883 { 651, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = ROL
6884 { 650, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = PseudoUDIV
6885 { 649, 3, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 501, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #649 = PseudoTRUNC_W_S
6886 { 648, 3, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #648 = PseudoTRUNC_W_D32
6887 { 647, 3, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 495, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #647 = PseudoTRUNC_W_D
6888 { 646, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #646 = PseudoSELECT_S
6889 { 645, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 487, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #645 = PseudoSELECT_I64
6890 { 644, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 483, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #644 = PseudoSELECT_I
6891 { 643, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 479, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #643 = PseudoSELECT_D64
6892 { 642, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #642 = PseudoSELECT_D32
6893 { 641, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #641 = PseudoSELECTFP_T_S
6894 { 640, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #640 = PseudoSELECTFP_T_I64
6895 { 639, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #639 = PseudoSELECTFP_T_I
6896 { 638, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #638 = PseudoSELECTFP_T_D64
6897 { 637, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #637 = PseudoSELECTFP_T_D32
6898 { 636, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #636 = PseudoSELECTFP_F_S
6899 { 635, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #635 = PseudoSELECTFP_F_I64
6900 { 634, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #634 = PseudoSELECTFP_F_I
6901 { 633, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #633 = PseudoSELECTFP_F_D64
6902 { 632, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #632 = PseudoSELECTFP_F_D32
6903 { 631, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #631 = PseudoSDIV
6904 { 630, 1, 0, 4, 1017, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #630 = PseudoReturn64
6905 { 629, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #629 = PseudoReturn
6906 { 628, 4, 1, 4, 1460, 0, 0, MipsImpOpBase + 0, 451, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #628 = PseudoPICK_QB
6907 { 627, 4, 1, 4, 1460, 0, 0, MipsImpOpBase + 0, 451, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #627 = PseudoPICK_PH
6908 { 626, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #626 = PseudoMULTu_MM
6909 { 625, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #625 = PseudoMULTu
6910 { 624, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #624 = PseudoMULT_MM
6911 { 623, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #623 = PseudoMULT
6912 { 622, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #622 = PseudoMTLOHI_MM
6913 { 621, 3, 1, 4, 1345, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #621 = PseudoMTLOHI_DSP
6914 { 620, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #620 = PseudoMTLOHI64
6915 { 619, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #619 = PseudoMTLOHI
6916 { 618, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #618 = PseudoMSUB_MM
6917 { 617, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #617 = PseudoMSUBU_MM
6918 { 616, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #616 = PseudoMSUBU
6919 { 615, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #615 = PseudoMSUB
6920 { 614, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 441, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #614 = PseudoMFLO_MM
6921 { 613, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 443, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #613 = PseudoMFLO64
6922 { 612, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 441, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #612 = PseudoMFLO
6923 { 611, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 441, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #611 = PseudoMFHI_MM
6924 { 610, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 443, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #610 = PseudoMFHI64
6925 { 609, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 441, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #609 = PseudoMFHI
6926 { 608, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #608 = PseudoMADD_MM
6927 { 607, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #607 = PseudoMADDU_MM
6928 { 606, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #606 = PseudoMADDU
6929 { 605, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #605 = PseudoMADD
6930 { 604, 1, 0, 4, 937, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #604 = PseudoIndrectHazardBranchR6
6931 { 603, 1, 0, 4, 1025, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #603 = PseudoIndrectHazardBranch64R6
6932 { 602, 1, 0, 4, 1021, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #602 = PseudoIndirectHazardBranch64
6933 { 601, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #601 = PseudoIndirectHazardBranch
6934 { 600, 1, 0, 4, 999, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #600 = PseudoIndirectBranch_MMR6
6935 { 599, 1, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #599 = PseudoIndirectBranch_MM
6936 { 598, 1, 0, 4, 937, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #598 = PseudoIndirectBranchR6
6937 { 597, 1, 0, 4, 1025, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #597 = PseudoIndirectBranch64R6
6938 { 596, 1, 0, 4, 1021, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #596 = PseudoIndirectBranch64
6939 { 595, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #595 = PseudoIndirectBranch
6940 { 594, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 430, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #594 = PseudoD_SELECT_I64
6941 { 593, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 423, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #593 = PseudoD_SELECT_I
6942 { 592, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #592 = PseudoDUDIV
6943 { 591, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #591 = PseudoDSDIV
6944 { 590, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #590 = PseudoDMULTu
6945 { 589, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #589 = PseudoDMULT
6946 { 588, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #588 = PseudoCVT_S_W
6947 { 587, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #587 = PseudoCVT_S_L
6948 { 586, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 418, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #586 = PseudoCVT_D64_W
6949 { 585, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #585 = PseudoCVT_D64_L
6950 { 584, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 414, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #584 = PseudoCVT_D32_W
6951 { 583, 3, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #583 = PseudoCMP_LT_PH
6952 { 582, 3, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #582 = PseudoCMP_LE_PH
6953 { 581, 3, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #581 = PseudoCMP_EQ_PH
6954 { 580, 3, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #580 = PseudoCMPU_LT_QB
6955 { 579, 3, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #579 = PseudoCMPU_LE_QB
6956 { 578, 3, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #578 = PseudoCMPU_EQ_QB
6957 { 577, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #577 = OR_V_W_PSEUDO
6958 { 576, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #576 = OR_V_H_PSEUDO
6959 { 575, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #575 = OR_V_D_PSEUDO
6960 { 574, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #574 = NOR_V_W_PSEUDO
6961 { 573, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #573 = NOR_V_H_PSEUDO
6962 { 572, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #572 = NOR_V_D_PSEUDO
6963 { 571, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #571 = NORImm64
6964 { 570, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #570 = NORImm
6965 { 569, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = NOP
6966 { 568, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #568 = MultuRxRyRz16
6967 { 567, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 406, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #567 = MultuRxRy16
6968 { 566, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #566 = MultRxRyRz16
6969 { 565, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 406, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #565 = MultRxRy16
6970 { 564, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #564 = MULOUMacro
6971 { 563, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #563 = MULOMacro
6972 { 562, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #562 = MULImmMacro
6973 { 561, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = MTTLO
6974 { 560, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = MTTHI
6975 { 559, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = MTTHC1
6976 { 558, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #558 = MTTGPR
6977 { 557, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #557 = MTTDSP
6978 { 556, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #556 = MTTC1
6979 { 555, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #555 = MTTC0
6980 { 554, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #554 = MTTACX
6981 { 553, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 397, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #553 = MSA_FP_ROUND_W_PSEUDO
6982 { 552, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 395, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #552 = MSA_FP_ROUND_D_PSEUDO
6983 { 551, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #551 = MSA_FP_EXTEND_W_PSEUDO
6984 { 550, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 391, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #550 = MSA_FP_EXTEND_D_PSEUDO
6985 { 549, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 389, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #549 = MIPSeh_return64
6986 { 548, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #548 = MIPSeh_return32
6987 { 547, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #547 = MFTLO
6988 { 546, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #546 = MFTHI
6989 { 545, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = MFTHC1
6990 { 544, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #544 = MFTGPR
6991 { 543, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = MFTDSP
6992 { 542, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = MFTC1
6993 { 541, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = MFTC0
6994 { 540, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = MFTACX
6995 { 539, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 379, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #539 = LwConstant32
6996 { 538, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = LoadImmSingleGPR
6997 { 537, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = LoadImmSingleFGR
6998 { 536, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = LoadImmDoubleGPR
6999 { 535, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = LoadImmDoubleFGR_32
7000 { 534, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 373, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #534 = LoadImmDoubleFGR
7001 { 533, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = LoadImm64
7002 { 532, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = LoadImm32
7003 { 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = LoadAddrReg64
7004 { 530, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = LoadAddrReg32
7005 { 529, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = LoadAddrImm64
7006 { 528, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #528 = LoadAddrImm32
7007 { 527, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #527 = LWM_MM
7008 { 526, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #526 = LONG_BRANCH_LUi2Op_64
7009 { 525, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 357, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #525 = LONG_BRANCH_LUi2Op
7010 { 524, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #524 = LONG_BRANCH_LUi
7011 { 523, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 351, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = LONG_BRANCH_DADDiu2Op
7012 { 522, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 347, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = LONG_BRANCH_DADDiu
7013 { 521, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = LONG_BRANCH_ADDiu2Op
7014 { 520, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 343, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = LONG_BRANCH_ADDiu
7015 { 519, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #519 = LOAD_CCOND_DSP
7016 { 518, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 337, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #518 = LOAD_ACC64DSP
7017 { 517, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 334, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #517 = LOAD_ACC64
7018 { 516, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #516 = LOAD_ACC128
7019 { 515, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #515 = LD_F16
7020 { 514, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 325, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #514 = LDR_W
7021 { 513, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 322, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #513 = LDR_D
7022 { 512, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #512 = LDMacro
7023 { 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #511 = JalTwoReg
7024 { 510, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #510 = JalOneReg
7025 { 509, 1, 0, 4, 991, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL }, // Inst #509 = JAL_MMR6
7026 { 508, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #508 = JALRPseudo
7027 { 507, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #507 = JALRHBPseudo
7028 { 506, 1, 0, 4, 1013, 0, 1, MipsImpOpBase + 3, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #506 = JALRHB64Pseudo
7029 { 505, 1, 0, 4, 1013, 0, 1, MipsImpOpBase + 3, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #505 = JALR64Pseudo
7030 { 504, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 314, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #504 = INSERT_W_VIDX_PSEUDO
7031 { 503, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 310, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #503 = INSERT_W_VIDX64_PSEUDO
7032 { 502, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #502 = INSERT_H_VIDX_PSEUDO
7033 { 501, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 302, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #501 = INSERT_H_VIDX64_PSEUDO
7034 { 500, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #500 = INSERT_FW_VIDX_PSEUDO
7035 { 499, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #499 = INSERT_FW_VIDX64_PSEUDO
7036 { 498, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 290, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #498 = INSERT_FW_PSEUDO
7037 { 497, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #497 = INSERT_FD_VIDX_PSEUDO
7038 { 496, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #496 = INSERT_FD_VIDX64_PSEUDO
7039 { 495, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 278, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #495 = INSERT_FD_PSEUDO
7040 { 494, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 274, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #494 = INSERT_D_VIDX_PSEUDO
7041 { 493, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #493 = INSERT_D_VIDX64_PSEUDO
7042 { 492, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 266, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #492 = INSERT_B_VIDX_PSEUDO
7043 { 491, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 262, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #491 = INSERT_B_VIDX64_PSEUDO
7044 { 490, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 258, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = GotPrologue16
7045 { 489, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #489 = FILL_FW_PSEUDO
7046 { 488, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 254, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #488 = FILL_FD_PSEUDO
7047 { 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #487 = FEXP2_W_1_PSEUDO
7048 { 486, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #486 = FEXP2_D_1_PSEUDO
7049 { 485, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 252, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #485 = FABS_W
7050 { 484, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 250, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #484 = FABS_D
7051 { 483, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 247, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #483 = ExtractElementF64_64
7052 { 482, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 244, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #482 = ExtractElementF64
7053 { 481, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #481 = ERet
7054 { 480, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = DURemMacro
7055 { 479, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = DURemIMacro
7056 { 478, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #478 = DUDivMacro
7057 { 477, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #477 = DUDivIMacro
7058 { 476, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #476 = DSRemMacro
7059 { 475, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #475 = DSRemIMacro
7060 { 474, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = DSDivMacro
7061 { 473, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = DSDivIMacro
7062 { 472, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #472 = DRORImm
7063 { 471, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #471 = DROR
7064 { 470, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #470 = DROLImm
7065 { 469, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #469 = DROL
7066 { 468, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #468 = DMULOUMacro
7067 { 467, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #467 = DMULOMacro
7068 { 466, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = DMULMacro
7069 { 465, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #465 = DMULImmMacro
7070 { 464, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = Constant32
7071 { 463, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 230, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #463 = CTTC1
7072 { 462, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 227, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #462 = COPY_FW_PSEUDO
7073 { 461, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 224, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #461 = COPY_FD_PSEUDO
7074 { 460, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #460 = CONSTPOOL_ENTRY
7075 { 459, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 222, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #459 = CFTC1
7076 { 458, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 219, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #458 = BuildPairF64_64
7077 { 457, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #457 = BuildPairF64
7078 { 456, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = BtnezT8SltuX16
7079 { 455, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 213, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = BtnezT8SltiuX16
7080 { 454, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 213, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #454 = BtnezT8SltiX16
7081 { 453, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #453 = BtnezT8SltX16
7082 { 452, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 213, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #452 = BtnezT8CmpiX16
7083 { 451, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #451 = BtnezT8CmpX16
7084 { 450, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #450 = BteqzT8SltuX16
7085 { 449, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 213, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #449 = BteqzT8SltiuX16
7086 { 448, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 213, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #448 = BteqzT8SltiX16
7087 { 447, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #447 = BteqzT8SltX16
7088 { 446, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 213, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #446 = BteqzT8CmpiX16
7089 { 445, 3, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #445 = BteqzT8CmpX16
7090 { 444, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #444 = BneImm
7091 { 443, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #443 = BeqImm
7092 { 442, 1, 0, 4, 957, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #442 = B_MM_Pseudo
7093 { 441, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #441 = B_MMR6_Pseudo
7094 { 440, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 2, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #440 = B_MM
7095 { 439, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 202, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #439 = BSEL_W_PSEUDO
7096 { 438, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #438 = BSEL_H_PSEUDO
7097 { 437, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 202, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #437 = BSEL_FW_PSEUDO
7098 { 436, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #436 = BSEL_FD_PSEUDO
7099 { 435, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #435 = BSEL_D_PSEUDO
7100 { 434, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #434 = BPOSGE32_PSEUDO
7101 { 433, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #433 = BNELImmMacro
7102 { 432, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #432 = BLTULImmMacro
7103 { 431, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #431 = BLTUL
7104 { 430, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #430 = BLTUImmMacro
7105 { 429, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #429 = BLTU
7106 { 428, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #428 = BLTLImmMacro
7107 { 427, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #427 = BLTL
7108 { 426, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #426 = BLTImmMacro
7109 { 425, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #425 = BLT
7110 { 424, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #424 = BLEULImmMacro
7111 { 423, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #423 = BLEUL
7112 { 422, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #422 = BLEUImmMacro
7113 { 421, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #421 = BLEU
7114 { 420, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #420 = BLELImmMacro
7115 { 419, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #419 = BLEL
7116 { 418, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #418 = BLEImmMacro
7117 { 417, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #417 = BLE
7118 { 416, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #416 = BGTULImmMacro
7119 { 415, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #415 = BGTUL
7120 { 414, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #414 = BGTUImmMacro
7121 { 413, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #413 = BGTU
7122 { 412, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #412 = BGTLImmMacro
7123 { 411, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #411 = BGTL
7124 { 410, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #410 = BGTImmMacro
7125 { 409, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #409 = BGT
7126 { 408, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #408 = BGEULImmMacro
7127 { 407, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #407 = BGEUL
7128 { 406, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #406 = BGEUImmMacro
7129 { 405, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #405 = BGEU
7130 { 404, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #404 = BGELImmMacro
7131 { 403, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #403 = BGEL
7132 { 402, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #402 = BGEImmMacro
7133 { 401, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #401 = BGE
7134 { 400, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #400 = BEQLImmMacro
7135 { 399, 1, 0, 4, 947, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #399 = BAL_BR_MM
7136 { 398, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #398 = BAL_BR
7137 { 397, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #397 = B
7138 { 396, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #396 = ATOMIC_SWAP_I8_POSTRA
7139 { 395, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #395 = ATOMIC_SWAP_I8
7140 { 394, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #394 = ATOMIC_SWAP_I64_POSTRA
7141 { 393, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #393 = ATOMIC_SWAP_I64
7142 { 392, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = ATOMIC_SWAP_I32_POSTRA
7143 { 391, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #391 = ATOMIC_SWAP_I32
7144 { 390, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = ATOMIC_SWAP_I16_POSTRA
7145 { 389, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #389 = ATOMIC_SWAP_I16
7146 { 388, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #388 = ATOMIC_LOAD_XOR_I8_POSTRA
7147 { 387, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #387 = ATOMIC_LOAD_XOR_I8
7148 { 386, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = ATOMIC_LOAD_XOR_I64_POSTRA
7149 { 385, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #385 = ATOMIC_LOAD_XOR_I64
7150 { 384, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #384 = ATOMIC_LOAD_XOR_I32_POSTRA
7151 { 383, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #383 = ATOMIC_LOAD_XOR_I32
7152 { 382, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #382 = ATOMIC_LOAD_XOR_I16_POSTRA
7153 { 381, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #381 = ATOMIC_LOAD_XOR_I16
7154 { 380, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = ATOMIC_LOAD_UMIN_I8_POSTRA
7155 { 379, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #379 = ATOMIC_LOAD_UMIN_I8
7156 { 378, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = ATOMIC_LOAD_UMIN_I64_POSTRA
7157 { 377, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #377 = ATOMIC_LOAD_UMIN_I64
7158 { 376, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = ATOMIC_LOAD_UMIN_I32_POSTRA
7159 { 375, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #375 = ATOMIC_LOAD_UMIN_I32
7160 { 374, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = ATOMIC_LOAD_UMIN_I16_POSTRA
7161 { 373, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #373 = ATOMIC_LOAD_UMIN_I16
7162 { 372, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = ATOMIC_LOAD_UMAX_I8_POSTRA
7163 { 371, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #371 = ATOMIC_LOAD_UMAX_I8
7164 { 370, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = ATOMIC_LOAD_UMAX_I64_POSTRA
7165 { 369, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #369 = ATOMIC_LOAD_UMAX_I64
7166 { 368, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = ATOMIC_LOAD_UMAX_I32_POSTRA
7167 { 367, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #367 = ATOMIC_LOAD_UMAX_I32
7168 { 366, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #366 = ATOMIC_LOAD_UMAX_I16_POSTRA
7169 { 365, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #365 = ATOMIC_LOAD_UMAX_I16
7170 { 364, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #364 = ATOMIC_LOAD_SUB_I8_POSTRA
7171 { 363, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #363 = ATOMIC_LOAD_SUB_I8
7172 { 362, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #362 = ATOMIC_LOAD_SUB_I64_POSTRA
7173 { 361, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #361 = ATOMIC_LOAD_SUB_I64
7174 { 360, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #360 = ATOMIC_LOAD_SUB_I32_POSTRA
7175 { 359, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #359 = ATOMIC_LOAD_SUB_I32
7176 { 358, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #358 = ATOMIC_LOAD_SUB_I16_POSTRA
7177 { 357, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #357 = ATOMIC_LOAD_SUB_I16
7178 { 356, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #356 = ATOMIC_LOAD_OR_I8_POSTRA
7179 { 355, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #355 = ATOMIC_LOAD_OR_I8
7180 { 354, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #354 = ATOMIC_LOAD_OR_I64_POSTRA
7181 { 353, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #353 = ATOMIC_LOAD_OR_I64
7182 { 352, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #352 = ATOMIC_LOAD_OR_I32_POSTRA
7183 { 351, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #351 = ATOMIC_LOAD_OR_I32
7184 { 350, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = ATOMIC_LOAD_OR_I16_POSTRA
7185 { 349, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #349 = ATOMIC_LOAD_OR_I16
7186 { 348, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = ATOMIC_LOAD_NAND_I8_POSTRA
7187 { 347, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #347 = ATOMIC_LOAD_NAND_I8
7188 { 346, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #346 = ATOMIC_LOAD_NAND_I64_POSTRA
7189 { 345, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #345 = ATOMIC_LOAD_NAND_I64
7190 { 344, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = ATOMIC_LOAD_NAND_I32_POSTRA
7191 { 343, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #343 = ATOMIC_LOAD_NAND_I32
7192 { 342, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = ATOMIC_LOAD_NAND_I16_POSTRA
7193 { 341, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #341 = ATOMIC_LOAD_NAND_I16
7194 { 340, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #340 = ATOMIC_LOAD_MIN_I8_POSTRA
7195 { 339, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #339 = ATOMIC_LOAD_MIN_I8
7196 { 338, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #338 = ATOMIC_LOAD_MIN_I64_POSTRA
7197 { 337, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #337 = ATOMIC_LOAD_MIN_I64
7198 { 336, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #336 = ATOMIC_LOAD_MIN_I32_POSTRA
7199 { 335, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #335 = ATOMIC_LOAD_MIN_I32
7200 { 334, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = ATOMIC_LOAD_MIN_I16_POSTRA
7201 { 333, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #333 = ATOMIC_LOAD_MIN_I16
7202 { 332, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #332 = ATOMIC_LOAD_MAX_I8_POSTRA
7203 { 331, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #331 = ATOMIC_LOAD_MAX_I8
7204 { 330, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #330 = ATOMIC_LOAD_MAX_I64_POSTRA
7205 { 329, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #329 = ATOMIC_LOAD_MAX_I64
7206 { 328, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #328 = ATOMIC_LOAD_MAX_I32_POSTRA
7207 { 327, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #327 = ATOMIC_LOAD_MAX_I32
7208 { 326, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = ATOMIC_LOAD_MAX_I16_POSTRA
7209 { 325, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #325 = ATOMIC_LOAD_MAX_I16
7210 { 324, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #324 = ATOMIC_LOAD_AND_I8_POSTRA
7211 { 323, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #323 = ATOMIC_LOAD_AND_I8
7212 { 322, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #322 = ATOMIC_LOAD_AND_I64_POSTRA
7213 { 321, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #321 = ATOMIC_LOAD_AND_I64
7214 { 320, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #320 = ATOMIC_LOAD_AND_I32_POSTRA
7215 { 319, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #319 = ATOMIC_LOAD_AND_I32
7216 { 318, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #318 = ATOMIC_LOAD_AND_I16_POSTRA
7217 { 317, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #317 = ATOMIC_LOAD_AND_I16
7218 { 316, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #316 = ATOMIC_LOAD_ADD_I8_POSTRA
7219 { 315, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #315 = ATOMIC_LOAD_ADD_I8
7220 { 314, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #314 = ATOMIC_LOAD_ADD_I64_POSTRA
7221 { 313, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #313 = ATOMIC_LOAD_ADD_I64
7222 { 312, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #312 = ATOMIC_LOAD_ADD_I32_POSTRA
7223 { 311, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #311 = ATOMIC_LOAD_ADD_I32
7224 { 310, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #310 = ATOMIC_LOAD_ADD_I16_POSTRA
7225 { 309, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #309 = ATOMIC_LOAD_ADD_I16
7226 { 308, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #308 = ATOMIC_CMP_SWAP_I8_POSTRA
7227 { 307, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 163, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #307 = ATOMIC_CMP_SWAP_I8
7228 { 306, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #306 = ATOMIC_CMP_SWAP_I64_POSTRA
7229 { 305, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #305 = ATOMIC_CMP_SWAP_I64
7230 { 304, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 163, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #304 = ATOMIC_CMP_SWAP_I32_POSTRA
7231 { 303, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 163, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #303 = ATOMIC_CMP_SWAP_I32
7232 { 302, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #302 = ATOMIC_CMP_SWAP_I16_POSTRA
7233 { 301, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 163, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #301 = ATOMIC_CMP_SWAP_I16
7234 { 300, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = AND_V_W_PSEUDO
7235 { 299, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = AND_V_H_PSEUDO
7236 { 298, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = AND_V_D_PSEUDO
7237 { 297, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #297 = ADJCALLSTACKUP
7238 { 296, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #296 = ADJCALLSTACKDOWN
7239 { 295, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #295 = ABSMacro
7240 { 294, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_UBFX
7241 { 293, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_SBFX
7242 { 292, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
7243 { 291, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
7244 { 290, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
7245 { 289, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
7246 { 288, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
7247 { 287, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
7248 { 286, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
7249 { 285, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
7250 { 284, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
7251 { 283, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
7252 { 282, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
7253 { 281, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
7254 { 280, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
7255 { 279, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
7256 { 278, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
7257 { 277, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
7258 { 276, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
7259 { 275, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_UBSANTRAP
7260 { 274, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
7261 { 273, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_TRAP
7262 { 272, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_BZERO
7263 { 271, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMSET
7264 { 270, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMMOVE
7265 { 269, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
7266 { 268, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #268 = G_MEMCPY
7267 { 267, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
7268 { 266, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
7269 { 265, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
7270 { 264, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
7271 { 263, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FMA
7272 { 262, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FREM
7273 { 261, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
7274 { 260, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
7275 { 259, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
7276 { 258, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STRICT_FADD
7277 { 257, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKRESTORE
7278 { 256, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_STACKSAVE
7279 { 255, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
7280 { 254, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
7281 { 253, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
7282 { 252, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
7283 { 251, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FNEARBYINT
7284 { 250, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FRINT
7285 { 249, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FFLOOR
7286 { 248, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FSQRT
7287 { 247, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTANH
7288 { 246, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSINH
7289 { 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOSH
7290 { 244, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FATAN
7291 { 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FASIN
7292 { 242, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FACOS
7293 { 241, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FTAN
7294 { 240, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FSIN
7295 { 239, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCOS
7296 { 238, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_FCEIL
7297 { 237, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BITREVERSE
7298 { 236, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_BSWAP
7299 { 235, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTPOP
7300 { 234, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
7301 { 233, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTLZ
7302 { 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
7303 { 231, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_CTTZ
7304 { 230, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
7305 { 229, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
7306 { 228, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
7307 { 227, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
7308 { 226, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
7309 { 225, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
7310 { 224, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
7311 { 223, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_VSCALE
7312 { 222, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BRJT
7313 { 221, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #221 = G_BR
7314 { 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LLROUND
7315 { 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_LROUND
7316 { 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_ABS
7317 { 217, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMAX
7318 { 216, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_UMIN
7319 { 215, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMAX
7320 { 214, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_SMIN
7321 { 213, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTRMASK
7322 { 212, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #212 = G_PTR_ADD
7323 { 211, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
7324 { 210, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_SET_FPMODE
7325 { 209, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_GET_FPMODE
7326 { 208, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_RESET_FPENV
7327 { 207, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_SET_FPENV
7328 { 206, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #206 = G_GET_FPENV
7329 { 205, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMAXIMUM
7330 { 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMINIMUM
7331 { 203, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
7332 { 202, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
7333 { 201, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMAXNUM
7334 { 200, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #200 = G_FMINNUM
7335 { 199, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
7336 { 198, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
7337 { 197, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
7338 { 196, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FABS
7339 { 195, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_UITOFP
7340 { 194, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_SITOFP
7341 { 193, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOUI
7342 { 192, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTOSI
7343 { 191, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPTRUNC
7344 { 190, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FPEXT
7345 { 189, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FNEG
7346 { 188, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FFREXP
7347 { 187, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLDEXP
7348 { 186, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG10
7349 { 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG2
7350 { 184, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FLOG
7351 { 183, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP10
7352 { 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP2
7353 { 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FEXP
7354 { 180, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOWI
7355 { 179, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FPOW
7356 { 178, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FREM
7357 { 177, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FDIV
7358 { 176, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMAD
7359 { 175, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FMA
7360 { 174, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_FMUL
7361 { 173, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FSUB
7362 { 172, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_FADD
7363 { 171, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
7364 { 170, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
7365 { 169, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_UDIVFIX
7366 { 168, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_SDIVFIX
7367 { 167, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
7368 { 166, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
7369 { 165, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_UMULFIX
7370 { 164, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_SMULFIX
7371 { 163, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_SSHLSAT
7372 { 162, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_USHLSAT
7373 { 161, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBSAT
7374 { 160, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_USUBSAT
7375 { 159, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SADDSAT
7376 { 158, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UADDSAT
7377 { 157, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULH
7378 { 156, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULH
7379 { 155, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULO
7380 { 154, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UMULO
7381 { 153, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBE
7382 { 152, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBO
7383 { 151, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SADDE
7384 { 150, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDO
7385 { 149, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBE
7386 { 148, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_USUBO
7387 { 147, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_UADDE
7388 { 146, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_UADDO
7389 { 145, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_SELECT
7390 { 144, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_UCMP
7391 { 143, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SCMP
7392 { 142, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FCMP
7393 { 141, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ICMP
7394 { 140, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTL
7395 { 139, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_ROTR
7396 { 138, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHR
7397 { 137, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_FSHL
7398 { 136, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_ASHR
7399 { 135, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_LSHR
7400 { 134, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_SHL
7401 { 133, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ZEXT
7402 { 132, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT_INREG
7403 { 131, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_SEXT
7404 { 130, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VAARG
7405 { 129, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #129 = G_VASTART
7406 { 128, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_FCONSTANT
7407 { 127, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_CONSTANT
7408 { 126, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_TRUNC
7409 { 125, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_ANYEXT
7410 { 124, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
7411 { 123, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
7412 { 122, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
7413 { 121, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #121 = G_INTRINSIC
7414 { 120, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
7415 { 119, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRINDIRECT
7416 { 118, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #118 = G_BRCOND
7417 { 117, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_PREFETCH
7418 { 116, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #116 = G_FENCE
7419 { 115, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
7420 { 114, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
7421 { 113, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
7422 { 112, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
7423 { 111, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
7424 { 110, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
7425 { 109, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
7426 { 108, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
7427 { 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
7428 { 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
7429 { 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
7430 { 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
7431 { 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
7432 { 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
7433 { 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
7434 { 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
7435 { 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
7436 { 98, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
7437 { 97, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
7438 { 96, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
7439 { 95, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_STORE
7440 { 94, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
7441 { 93, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
7442 { 92, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
7443 { 91, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
7444 { 90, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_SEXTLOAD
7445 { 89, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #89 = G_LOAD
7446 { 88, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
7447 { 87, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
7448 { 86, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
7449 { 85, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
7450 { 84, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
7451 { 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
7452 { 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
7453 { 81, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
7454 { 80, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
7455 { 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_FREEZE
7456 { 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_BITCAST
7457 { 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTTOPTR
7458 { 76, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_PTRTOINT
7459 { 75, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
7460 { 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
7461 { 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
7462 { 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
7463 { 71, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_INSERT
7464 { 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
7465 { 69, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_EXTRACT
7466 { 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
7467 { 67, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
7468 { 66, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
7469 { 65, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
7470 { 64, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #64 = G_PHI
7471 { 63, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
7472 { 62, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_XOR
7473 { 61, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_OR
7474 { 60, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #60 = G_AND
7475 { 59, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UDIVREM
7476 { 58, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SDIVREM
7477 { 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UREM
7478 { 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SREM
7479 { 55, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIV
7480 { 54, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIV
7481 { 53, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_MUL
7482 { 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SUB
7483 { 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #51 = G_ADD
7484 { 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
7485 { 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
7486 { 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
7487 { 47, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
7488 { 46, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
7489 { 45, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
7490 { 44, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
7491 { 43, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
7492 { 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER
7493 { 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
7494 { 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
7495 { 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
7496 { 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
7497 { 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
7498 { 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET
7499 { 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
7500 { 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP
7501 { 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP
7502 { 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
7503 { 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT
7504 { 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
7505 { 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
7506 { 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
7507 { 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT
7508 { 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL
7509 { 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP
7510 { 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE
7511 { 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
7512 { 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END
7513 { 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START
7514 { 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE
7515 { 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY
7516 { 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE
7517 { 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL
7518 { 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI
7519 { 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
7520 { 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
7521 { 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE
7522 { 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
7523 { 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
7524 { 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
7525 { 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
7526 { 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
7527 { 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
7528 { 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
7529 { 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
7530 { 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
7531 { 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
7532 { 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
7533 { 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
7534 { 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
7535 }, {
7536 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7537 /* 1 */
7538 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7539 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7540 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7541 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7542 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7543 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7544 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
7545 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7546 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7547 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7548 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7549 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7550 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7551 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7552 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7553 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7554 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7555 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7556 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7557 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7558 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7559 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7560 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7561 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7562 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7563 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7564 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7565 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7566 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7567 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7568 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7569 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7570 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7571 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7572 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7573 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7574 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7575 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7576 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7577 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7578 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7579 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7580 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7581 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7582 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7583 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7584 /* 152 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7585 /* 154 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7586 /* 157 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7587 /* 160 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7588 /* 163 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7589 /* 167 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7590 /* 174 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7591 /* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7592 /* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7593 /* 187 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7594 /* 190 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
7595 /* 191 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7596 /* 194 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7597 /* 197 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7598 /* 198 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7599 /* 202 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7600 /* 206 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7601 /* 210 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7602 /* 213 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7603 /* 216 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7604 /* 219 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7605 /* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7606 /* 224 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7607 /* 227 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7608 /* 230 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7609 /* 232 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7610 /* 235 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7611 /* 238 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7612 /* 241 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7613 /* 244 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7614 /* 247 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7615 /* 250 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7616 /* 252 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7617 /* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7618 /* 256 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7619 /* 258 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7620 /* 262 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7621 /* 266 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7622 /* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7623 /* 274 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7624 /* 278 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7625 /* 282 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7626 /* 286 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7627 /* 290 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7628 /* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7629 /* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7630 /* 302 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7631 /* 306 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7632 /* 310 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7633 /* 314 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7634 /* 318 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7635 /* 319 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7636 /* 322 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7637 /* 325 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7638 /* 328 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7639 /* 331 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7640 /* 334 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7641 /* 337 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7642 /* 340 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7643 /* 343 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7644 /* 347 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7645 /* 351 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7646 /* 354 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7647 /* 357 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7648 /* 359 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7649 /* 361 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7650 /* 364 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7651 /* 366 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7652 /* 368 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7653 /* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7654 /* 373 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7655 /* 375 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7656 /* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7657 /* 379 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7658 /* 382 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7659 /* 384 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7660 /* 387 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7661 /* 389 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7662 /* 391 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7663 /* 393 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7664 /* 395 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7665 /* 397 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7666 /* 399 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7667 /* 401 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7668 /* 404 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7669 /* 406 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7670 /* 408 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7671 /* 411 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7672 /* 414 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7673 /* 416 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7674 /* 418 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7675 /* 420 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7676 /* 423 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7677 /* 430 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7678 /* 437 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7679 /* 441 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7680 /* 443 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7681 /* 445 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7682 /* 448 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7683 /* 451 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7684 /* 455 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7685 /* 459 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7686 /* 463 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7687 /* 467 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7688 /* 471 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7689 /* 475 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7690 /* 479 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7691 /* 483 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7692 /* 487 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7693 /* 491 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7694 /* 495 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7695 /* 498 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7696 /* 501 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7697 /* 504 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7698 /* 507 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7699 /* 510 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7700 /* 512 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7701 /* 514 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7702 /* 516 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7703 /* 518 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7704 /* 522 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7705 /* 527 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7706 /* 532 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7707 /* 535 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7708 /* 537 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7709 /* 539 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7710 /* 542 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7711 /* 545 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7712 /* 548 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7713 /* 551 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7714 /* 554 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7715 /* 557 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7716 /* 560 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7717 /* 563 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7718 /* 566 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7719 /* 569 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7720 /* 573 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7721 /* 576 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7722 /* 580 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7723 /* 582 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7724 /* 585 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7725 /* 588 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7726 /* 591 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7727 /* 594 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7728 /* 596 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7729 /* 598 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7730 /* 600 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7731 /* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7732 /* 606 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7733 /* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7734 /* 614 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7735 /* 618 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7736 /* 622 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7737 /* 624 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7738 /* 626 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7739 /* 628 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7740 /* 630 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7741 /* 632 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7742 /* 635 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7743 /* 637 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7744 /* 639 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7745 /* 641 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7746 /* 643 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7747 /* 645 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7748 /* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7749 /* 649 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7750 /* 651 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7751 /* 655 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7752 /* 659 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7753 /* 663 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7754 /* 666 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7755 /* 669 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7756 /* 672 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7757 /* 675 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7758 /* 678 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7759 /* 681 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7760 /* 684 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7761 /* 686 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7762 /* 688 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7763 /* 690 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7764 /* 692 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7765 /* 695 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7766 /* 698 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7767 /* 701 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7768 /* 704 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7769 /* 707 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7770 /* 711 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7771 /* 716 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7772 /* 719 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7773 /* 721 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7774 /* 724 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7775 /* 727 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7776 /* 730 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7777 /* 733 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7778 /* 736 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7779 /* 739 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7780 /* 743 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7781 /* 747 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7782 /* 751 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7783 /* 755 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7784 /* 758 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7785 /* 760 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7786 /* 763 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7787 /* 766 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7788 /* 768 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7789 /* 771 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7790 /* 774 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7791 /* 777 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7792 /* 780 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7793 /* 783 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7794 /* 786 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7795 /* 789 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7796 /* 791 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7797 /* 793 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7798 /* 795 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7799 /* 797 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7800 /* 799 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7801 /* 801 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7802 /* 806 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7803 /* 810 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7804 /* 814 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7805 /* 818 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7806 /* 822 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7807 /* 825 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7808 /* 830 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7809 /* 835 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7810 /* 840 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7811 /* 845 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7812 /* 846 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7813 /* 849 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7814 /* 852 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7815 /* 855 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7816 /* 858 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7817 /* 861 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7818 /* 864 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7819 /* 866 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7820 /* 868 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7821 /* 870 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7822 /* 872 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7823 /* 876 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7824 /* 879 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7825 /* 882 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7826 /* 885 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7827 /* 888 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7828 /* 891 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7829 /* 894 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7830 /* 897 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7831 /* 900 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7832 /* 903 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7833 /* 906 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7834 /* 909 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7835 /* 913 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7836 /* 916 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7837 /* 920 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7838 /* 923 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7839 /* 926 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7840 /* 929 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7841 /* 932 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7842 /* 936 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7843 /* 940 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7844 /* 944 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7845 /* 948 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7846 /* 952 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7847 /* 954 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7848 /* 957 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7849 /* 959 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7850 /* 964 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7851 /* 968 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7852 /* 970 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7853 /* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7854 /* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7855 /* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7856 /* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7857 /* 990 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7858 /* 994 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7859 /* 998 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7860 /* 1002 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7861 /* 1006 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7862 /* 1010 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7863 /* 1014 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7864 /* 1018 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7865 /* 1022 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7866 /* 1026 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7867 /* 1029 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7868 /* 1032 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7869 /* 1035 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7870 /* 1037 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7871 /* 1040 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7872 /* 1042 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7873 /* 1044 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7874 /* 1046 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7875 /* 1048 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7876 /* 1050 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7877 /* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7878 /* 1055 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7879 /* 1059 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7880 /* 1062 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7881 /* 1065 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7882 /* 1068 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7883 /* 1070 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7884 /* 1072 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7885 /* 1075 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7886 /* 1079 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7887 /* 1083 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7888 /* 1087 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7889 /* 1091 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7890 /* 1095 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7891 /* 1098 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7892 /* 1101 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7893 /* 1104 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7894 /* 1108 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7895 /* 1112 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7896 /* 1116 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7897 /* 1120 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7898 /* 1123 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7899 /* 1126 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7900 /* 1129 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7901 /* 1132 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7902 /* 1135 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7903 /* 1138 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7904 /* 1140 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7905 }, {
7906 /* 0 */
7907 /* 0 */ Mips::SP, Mips::SP,
7908 /* 2 */ Mips::AT,
7909 /* 3 */ Mips::RA,
7910 /* 4 */ Mips::DSPPos,
7911 /* 5 */ Mips::V0, Mips::V1,
7912 /* 7 */ Mips::HI0, Mips::LO0,
7913 /* 9 */ Mips::T8,
7914 /* 10 */ Mips::DSPOutFlag20,
7915 /* 11 */ Mips::DSPCarry,
7916 /* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,
7917 /* 14 */ Mips::DSPCCond,
7918 /* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,
7919 /* 20 */ Mips::HI0_64, Mips::LO0_64,
7920 /* 22 */ Mips::DSPOutFlag16_19,
7921 /* 23 */ Mips::DSPPos, Mips::DSPEFI,
7922 /* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,
7923 /* 28 */ Mips::DSPOutFlag23,
7924 /* 29 */ Mips::FCC0,
7925 /* 30 */ Mips::DSPPos, Mips::DSPSCount,
7926 /* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,
7927 /* 36 */ Mips::AC0,
7928 /* 37 */ Mips::AC0_64,
7929 /* 38 */ Mips::HI0,
7930 /* 39 */ Mips::HI0_64,
7931 /* 40 */ Mips::LO0,
7932 /* 41 */ Mips::LO0_64,
7933 /* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,
7934 /* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,
7935 /* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,
7936 /* 54 */ Mips::P0,
7937 /* 55 */ Mips::P1,
7938 /* 56 */ Mips::P2,
7939 /* 57 */ Mips::DSPOutFlag21,
7940 /* 58 */ Mips::DSPOutFlag22,
7941 /* 59 */ Mips::P0, Mips::P1, Mips::P2,
7942 /* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,
7943 }
7944};
7945
7946
7947#ifdef __GNUC__
7948#pragma GCC diagnostic push
7949#pragma GCC diagnostic ignored "-Woverlength-strings"
7950#endif
7951extern const char MipsInstrNameData[] = {
7952 /* 0 */ "G_FLOG10\0"
7953 /* 9 */ "G_FEXP10\0"
7954 /* 18 */ "DMFC0\0"
7955 /* 24 */ "DMFGC0\0"
7956 /* 31 */ "MFHGC0\0"
7957 /* 38 */ "MTHGC0\0"
7958 /* 45 */ "DMTGC0\0"
7959 /* 52 */ "MFTC0\0"
7960 /* 58 */ "DMTC0\0"
7961 /* 64 */ "MTTC0\0"
7962 /* 70 */ "VMM0\0"
7963 /* 75 */ "MTM0\0"
7964 /* 80 */ "MTP0\0"
7965 /* 85 */ "BBIT0\0"
7966 /* 91 */ "LDC1\0"
7967 /* 96 */ "SDC1\0"
7968 /* 101 */ "CFC1\0"
7969 /* 106 */ "DMFC1\0"
7970 /* 112 */ "MFTHC1\0"
7971 /* 119 */ "MTTHC1\0"
7972 /* 126 */ "CTC1\0"
7973 /* 131 */ "CFTC1\0"
7974 /* 137 */ "MFTC1\0"
7975 /* 143 */ "DMTC1\0"
7976 /* 149 */ "CTTC1\0"
7977 /* 155 */ "MTTC1\0"
7978 /* 161 */ "LWC1\0"
7979 /* 166 */ "SWC1\0"
7980 /* 171 */ "LDXC1\0"
7981 /* 177 */ "SDXC1\0"
7982 /* 183 */ "LUXC1\0"
7983 /* 189 */ "SUXC1\0"
7984 /* 195 */ "LWXC1\0"
7985 /* 201 */ "SWXC1\0"
7986 /* 207 */ "MTM1\0"
7987 /* 212 */ "SDC1_M1\0"
7988 /* 220 */ "MTP1\0"
7989 /* 225 */ "BBIT1\0"
7990 /* 231 */ "BBIT032\0"
7991 /* 239 */ "BBIT132\0"
7992 /* 247 */ "DSRA32\0"
7993 /* 254 */ "MFHC1_D32\0"
7994 /* 264 */ "MTHC1_D32\0"
7995 /* 274 */ "FSUB_D32\0"
7996 /* 283 */ "NMSUB_D32\0"
7997 /* 293 */ "FADD_D32\0"
7998 /* 302 */ "NMADD_D32\0"
7999 /* 312 */ "C_NGE_D32\0"
8000 /* 322 */ "C_NGLE_D32\0"
8001 /* 333 */ "C_OLE_D32\0"
8002 /* 343 */ "C_ULE_D32\0"
8003 /* 353 */ "C_LE_D32\0"
8004 /* 362 */ "C_SF_D32\0"
8005 /* 371 */ "MOVF_D32\0"
8006 /* 380 */ "C_F_D32\0"
8007 /* 388 */ "PseudoSELECTFP_F_D32\0"
8008 /* 409 */ "FNEG_D32\0"
8009 /* 418 */ "MOVN_I_D32\0"
8010 /* 429 */ "MOVZ_I_D32\0"
8011 /* 440 */ "C_NGL_D32\0"
8012 /* 450 */ "FMUL_D32\0"
8013 /* 459 */ "LDC1_MM_D32\0"
8014 /* 471 */ "SDC1_MM_D32\0"
8015 /* 483 */ "C_UN_D32\0"
8016 /* 492 */ "RECIP_D32\0"
8017 /* 502 */ "FCMP_D32\0"
8018 /* 511 */ "C_SEQ_D32\0"
8019 /* 521 */ "C_UEQ_D32\0"
8020 /* 531 */ "C_EQ_D32\0"
8021 /* 540 */ "FABS_D32\0"
8022 /* 549 */ "CVT_S_D32\0"
8023 /* 559 */ "PseudoSELECT_D32\0"
8024 /* 576 */ "C_NGT_D32\0"
8025 /* 586 */ "C_OLT_D32\0"
8026 /* 596 */ "C_ULT_D32\0"
8027 /* 606 */ "C_LT_D32\0"
8028 /* 615 */ "FSQRT_D32\0"
8029 /* 625 */ "RSQRT_D32\0"
8030 /* 635 */ "MOVT_D32\0"
8031 /* 644 */ "PseudoSELECTFP_T_D32\0"
8032 /* 665 */ "FDIV_D32\0"
8033 /* 674 */ "FMOV_D32\0"
8034 /* 683 */ "PseudoTRUNC_W_D32\0"
8035 /* 701 */ "ROUND_W_D32\0"
8036 /* 713 */ "CEIL_W_D32\0"
8037 /* 724 */ "FLOOR_W_D32\0"
8038 /* 736 */ "CVT_W_D32\0"
8039 /* 746 */ "BPOSGE32\0"
8040 /* 755 */ "ATOMIC_LOAD_SUB_I32\0"
8041 /* 775 */ "ATOMIC_LOAD_ADD_I32\0"
8042 /* 795 */ "ATOMIC_LOAD_NAND_I32\0"
8043 /* 816 */ "ATOMIC_LOAD_AND_I32\0"
8044 /* 836 */ "ATOMIC_LOAD_UMIN_I32\0"
8045 /* 857 */ "ATOMIC_LOAD_MIN_I32\0"
8046 /* 877 */ "ATOMIC_SWAP_I32\0"
8047 /* 893 */ "ATOMIC_CMP_SWAP_I32\0"
8048 /* 913 */ "ATOMIC_LOAD_XOR_I32\0"
8049 /* 933 */ "ATOMIC_LOAD_OR_I32\0"
8050 /* 952 */ "ATOMIC_LOAD_UMAX_I32\0"
8051 /* 973 */ "ATOMIC_LOAD_MAX_I32\0"
8052 /* 993 */ "DSLL32\0"
8053 /* 1000 */ "DSRL32\0"
8054 /* 1007 */ "DROTR32\0"
8055 /* 1015 */ "CINS32\0"
8056 /* 1022 */ "EXTS32\0"
8057 /* 1029 */ "FCMP_S32\0"
8058 /* 1038 */ "DSLL64_32\0"
8059 /* 1048 */ "CINS64_32\0"
8060 /* 1058 */ "DEXT64_32\0"
8061 /* 1068 */ "LoadImmDoubleFGR_32\0"
8062 /* 1088 */ "LoadAddrReg32\0"
8063 /* 1102 */ "CINS_i32\0"
8064 /* 1111 */ "LoadImm32\0"
8065 /* 1121 */ "LoadAddrImm32\0"
8066 /* 1135 */ "MIPSeh_return32\0"
8067 /* 1151 */ "LwConstant32\0"
8068 /* 1164 */ "LDC2\0"
8069 /* 1169 */ "SDC2\0"
8070 /* 1174 */ "DMFC2\0"
8071 /* 1180 */ "DMTC2\0"
8072 /* 1186 */ "LWC2\0"
8073 /* 1191 */ "SWC2\0"
8074 /* 1196 */ "G_FLOG2\0"
8075 /* 1204 */ "MTM2\0"
8076 /* 1209 */ "MTP2\0"
8077 /* 1214 */ "G_FEXP2\0"
8078 /* 1222 */ "SHRA_QB_MMR2\0"
8079 /* 1235 */ "CMPGDU_LE_QB_MMR2\0"
8080 /* 1253 */ "SUBUH_QB_MMR2\0"
8081 /* 1267 */ "ADDUH_QB_MMR2\0"
8082 /* 1281 */ "CMPGDU_EQ_QB_MMR2\0"
8083 /* 1299 */ "SHRA_R_QB_MMR2\0"
8084 /* 1314 */ "SUBUH_R_QB_MMR2\0"
8085 /* 1330 */ "ADDUH_R_QB_MMR2\0"
8086 /* 1346 */ "SHRAV_R_QB_MMR2\0"
8087 /* 1362 */ "ABSQ_S_QB_MMR2\0"
8088 /* 1377 */ "CMPGDU_LT_QB_MMR2\0"
8089 /* 1395 */ "SHRAV_QB_MMR2\0"
8090 /* 1409 */ "PREPEND_MMR2\0"
8091 /* 1422 */ "APPEND_MMR2\0"
8092 /* 1434 */ "PRECR_QB_PH_MMR2\0"
8093 /* 1451 */ "SUBQH_PH_MMR2\0"
8094 /* 1465 */ "ADDQH_PH_MMR2\0"
8095 /* 1479 */ "SHRL_PH_MMR2\0"
8096 /* 1492 */ "MUL_PH_MMR2\0"
8097 /* 1504 */ "SUBQH_R_PH_MMR2\0"
8098 /* 1520 */ "ADDQH_R_PH_MMR2\0"
8099 /* 1536 */ "MUL_S_PH_MMR2\0"
8100 /* 1550 */ "MULQ_S_PH_MMR2\0"
8101 /* 1565 */ "SUBU_S_PH_MMR2\0"
8102 /* 1580 */ "ADDU_S_PH_MMR2\0"
8103 /* 1595 */ "SUBU_PH_MMR2\0"
8104 /* 1608 */ "ADDU_PH_MMR2\0"
8105 /* 1621 */ "SHRLV_PH_MMR2\0"
8106 /* 1635 */ "DPA_W_PH_MMR2\0"
8107 /* 1649 */ "MULSA_W_PH_MMR2\0"
8108 /* 1665 */ "DPAQX_SA_W_PH_MMR2\0"
8109 /* 1684 */ "DPSQX_SA_W_PH_MMR2\0"
8110 /* 1703 */ "DPS_W_PH_MMR2\0"
8111 /* 1717 */ "DPAQX_S_W_PH_MMR2\0"
8112 /* 1735 */ "DPSQX_S_W_PH_MMR2\0"
8113 /* 1753 */ "DPAX_W_PH_MMR2\0"
8114 /* 1768 */ "DPSX_W_PH_MMR2\0"
8115 /* 1783 */ "BALIGN_MMR2\0"
8116 /* 1795 */ "PRECR_SRA_PH_W_MMR2\0"
8117 /* 1815 */ "PRECR_SRA_R_PH_W_MMR2\0"
8118 /* 1837 */ "SUBQH_W_MMR2\0"
8119 /* 1850 */ "ADDQH_W_MMR2\0"
8120 /* 1863 */ "SUBQH_R_W_MMR2\0"
8121 /* 1878 */ "ADDQH_R_W_MMR2\0"
8122 /* 1893 */ "MULQ_RS_W_MMR2\0"
8123 /* 1908 */ "MULQ_S_W_MMR2\0"
8124 /* 1922 */ "LDC3\0"
8125 /* 1927 */ "SDC3\0"
8126 /* 1932 */ "LWC3\0"
8127 /* 1937 */ "SWC3\0"
8128 /* 1942 */ "BPOSGE32C_MMR3\0"
8129 /* 1957 */ "LDC164\0"
8130 /* 1964 */ "SDC164\0"
8131 /* 1971 */ "LDXC164\0"
8132 /* 1979 */ "SDXC164\0"
8133 /* 1987 */ "LUXC164\0"
8134 /* 1995 */ "SUXC164\0"
8135 /* 2003 */ "SEB64\0"
8136 /* 2009 */ "TAILCALLREGHB64\0"
8137 /* 2025 */ "JR_HB64\0"
8138 /* 2033 */ "JALR_HB64\0"
8139 /* 2043 */ "LB64\0"
8140 /* 2048 */ "SB64\0"
8141 /* 2053 */ "LOAD_ACC64\0"
8142 /* 2064 */ "STORE_ACC64\0"
8143 /* 2076 */ "BGEC64\0"
8144 /* 2083 */ "BNEC64\0"
8145 /* 2090 */ "JIC64\0"
8146 /* 2096 */ "JIALC64\0"
8147 /* 2104 */ "BEQC64\0"
8148 /* 2111 */ "SC64\0"
8149 /* 2116 */ "BLTC64\0"
8150 /* 2123 */ "BGEUC64\0"
8151 /* 2131 */ "BLTUC64\0"
8152 /* 2139 */ "BGEZC64\0"
8153 /* 2147 */ "BLEZC64\0"
8154 /* 2155 */ "BNEZC64\0"
8155 /* 2163 */ "BEQZC64\0"
8156 /* 2171 */ "BGTZC64\0"
8157 /* 2179 */ "BLTZC64\0"
8158 /* 2187 */ "AND64\0"
8159 /* 2193 */ "MFC1_D64\0"
8160 /* 2202 */ "MFHC1_D64\0"
8161 /* 2212 */ "MTHC1_D64\0"
8162 /* 2222 */ "MTC1_D64\0"
8163 /* 2231 */ "MOVN_I64_D64\0"
8164 /* 2244 */ "MOVZ_I64_D64\0"
8165 /* 2257 */ "FSUB_D64\0"
8166 /* 2266 */ "NMSUB_D64\0"
8167 /* 2276 */ "FADD_D64\0"
8168 /* 2285 */ "NMADD_D64\0"
8169 /* 2295 */ "C_NGE_D64\0"
8170 /* 2305 */ "C_NGLE_D64\0"
8171 /* 2316 */ "C_OLE_D64\0"
8172 /* 2326 */ "C_ULE_D64\0"
8173 /* 2336 */ "C_LE_D64\0"
8174 /* 2345 */ "C_SF_D64\0"
8175 /* 2354 */ "MOVF_D64\0"
8176 /* 2363 */ "C_F_D64\0"
8177 /* 2371 */ "PseudoSELECTFP_F_D64\0"
8178 /* 2392 */ "FNEG_D64\0"
8179 /* 2401 */ "MOVN_I_D64\0"
8180 /* 2412 */ "MOVZ_I_D64\0"
8181 /* 2423 */ "C_NGL_D64\0"
8182 /* 2433 */ "FMUL_D64\0"
8183 /* 2442 */ "TRUNC_L_D64\0"
8184 /* 2454 */ "ROUND_L_D64\0"
8185 /* 2466 */ "CEIL_L_D64\0"
8186 /* 2477 */ "FLOOR_L_D64\0"
8187 /* 2489 */ "CVT_L_D64\0"
8188 /* 2499 */ "LDC1_MM_D64\0"
8189 /* 2511 */ "SDC1_MM_D64\0"
8190 /* 2523 */ "C_UN_D64\0"
8191 /* 2532 */ "RECIP_D64\0"
8192 /* 2542 */ "FCMP_D64\0"
8193 /* 2551 */ "C_SEQ_D64\0"
8194 /* 2561 */ "C_UEQ_D64\0"
8195 /* 2571 */ "C_EQ_D64\0"
8196 /* 2580 */ "FABS_D64\0"
8197 /* 2589 */ "CVT_S_D64\0"
8198 /* 2599 */ "PseudoSELECT_D64\0"
8199 /* 2616 */ "C_NGT_D64\0"
8200 /* 2626 */ "C_OLT_D64\0"
8201 /* 2636 */ "C_ULT_D64\0"
8202 /* 2646 */ "C_LT_D64\0"
8203 /* 2655 */ "FSQRT_D64\0"
8204 /* 2665 */ "RSQRT_D64\0"
8205 /* 2675 */ "MOVT_D64\0"
8206 /* 2684 */ "PseudoSELECTFP_T_D64\0"
8207 /* 2705 */ "FDIV_D64\0"
8208 /* 2714 */ "FMOV_D64\0"
8209 /* 2723 */ "TRUNC_W_D64\0"
8210 /* 2735 */ "ROUND_W_D64\0"
8211 /* 2747 */ "CEIL_W_D64\0"
8212 /* 2758 */ "FLOOR_W_D64\0"
8213 /* 2770 */ "CVT_W_D64\0"
8214 /* 2780 */ "BNE64\0"
8215 /* 2786 */ "BuildPairF64\0"
8216 /* 2799 */ "ExtractElementF64\0"
8217 /* 2817 */ "TAILCALLREG64\0"
8218 /* 2831 */ "SEH64\0"
8219 /* 2837 */ "LH64\0"
8220 /* 2842 */ "SH64\0"
8221 /* 2847 */ "PseudoMFHI64\0"
8222 /* 2860 */ "PseudoMTLOHI64\0"
8223 /* 2875 */ "MTHI64\0"
8224 /* 2882 */ "MOVN_I64_I64\0"
8225 /* 2895 */ "MOVZ_I64_I64\0"
8226 /* 2908 */ "ATOMIC_LOAD_SUB_I64\0"
8227 /* 2928 */ "ATOMIC_LOAD_ADD_I64\0"
8228 /* 2948 */ "ATOMIC_LOAD_NAND_I64\0"
8229 /* 2969 */ "ATOMIC_LOAD_AND_I64\0"
8230 /* 2989 */ "MOVF_I64\0"
8231 /* 2998 */ "PseudoSELECTFP_F_I64\0"
8232 /* 3019 */ "MOVN_I_I64\0"
8233 /* 3030 */ "MOVZ_I_I64\0"
8234 /* 3041 */ "ATOMIC_LOAD_UMIN_I64\0"
8235 /* 3062 */ "ATOMIC_LOAD_MIN_I64\0"
8236 /* 3082 */ "ATOMIC_SWAP_I64\0"
8237 /* 3098 */ "ATOMIC_CMP_SWAP_I64\0"
8238 /* 3118 */ "ATOMIC_LOAD_XOR_I64\0"
8239 /* 3138 */ "ATOMIC_LOAD_OR_I64\0"
8240 /* 3157 */ "PseudoD_SELECT_I64\0"
8241 /* 3176 */ "PseudoSELECT_I64\0"
8242 /* 3193 */ "MOVT_I64\0"
8243 /* 3202 */ "PseudoSELECTFP_T_I64\0"
8244 /* 3223 */ "ATOMIC_LOAD_UMAX_I64\0"
8245 /* 3244 */ "ATOMIC_LOAD_MAX_I64\0"
8246 /* 3264 */ "LL64\0"
8247 /* 3269 */ "CVT_S_PL64\0"
8248 /* 3280 */ "LWL64\0"
8249 /* 3286 */ "SWL64\0"
8250 /* 3292 */ "PseudoMFLO64\0"
8251 /* 3305 */ "MTLO64\0"
8252 /* 3312 */ "BEQ64\0"
8253 /* 3318 */ "JR64\0"
8254 /* 3323 */ "JALR64\0"
8255 /* 3330 */ "NOR64\0"
8256 /* 3336 */ "XOR64\0"
8257 /* 3342 */ "RDHWR64\0"
8258 /* 3350 */ "LWR64\0"
8259 /* 3356 */ "SWR64\0"
8260 /* 3362 */ "FSUB_PS64\0"
8261 /* 3372 */ "FADD_PS64\0"
8262 /* 3382 */ "PLL_PS64\0"
8263 /* 3391 */ "FMUL_PS64\0"
8264 /* 3401 */ "PUL_PS64\0"
8265 /* 3410 */ "ADDR_PS64\0"
8266 /* 3420 */ "MULR_PS64\0"
8267 /* 3430 */ "PLU_PS64\0"
8268 /* 3439 */ "PUU_PS64\0"
8269 /* 3448 */ "CVT_PW_PS64\0"
8270 /* 3460 */ "CVT_PS_S64\0"
8271 /* 3471 */ "SLT64\0"
8272 /* 3477 */ "CVT_S_PU64\0"
8273 /* 3488 */ "LW64\0"
8274 /* 3493 */ "CVT_PS_PW64\0"
8275 /* 3505 */ "SW64\0"
8276 /* 3510 */ "BGEZ64\0"
8277 /* 3517 */ "BLEZ64\0"
8278 /* 3524 */ "SELNEZ64\0"
8279 /* 3533 */ "SELEQZ64\0"
8280 /* 3542 */ "BGTZ64\0"
8281 /* 3549 */ "BLTZ64\0"
8282 /* 3556 */ "BuildPairF64_64\0"
8283 /* 3572 */ "ExtractElementF64_64\0"
8284 /* 3593 */ "SLL64_64\0"
8285 /* 3602 */ "LONG_BRANCH_LUi2Op_64\0"
8286 /* 3624 */ "LoadAddrReg64\0"
8287 /* 3638 */ "PseudoIndirectHazardBranch64\0"
8288 /* 3667 */ "PseudoIndirectBranch64\0"
8289 /* 3690 */ "ANDi64\0"
8290 /* 3697 */ "XORi64\0"
8291 /* 3704 */ "SLTi64\0"
8292 /* 3711 */ "LUi64\0"
8293 /* 3717 */ "SGEImm64\0"
8294 /* 3726 */ "SLEImm64\0"
8295 /* 3735 */ "NORImm64\0"
8296 /* 3744 */ "SGTImm64\0"
8297 /* 3753 */ "SLTImm64\0"
8298 /* 3762 */ "SGEUImm64\0"
8299 /* 3772 */ "SLEUImm64\0"
8300 /* 3782 */ "SGTUImm64\0"
8301 /* 3792 */ "SLTUImm64\0"
8302 /* 3802 */ "LoadImm64\0"
8303 /* 3812 */ "LoadAddrImm64\0"
8304 /* 3826 */ "PseudoReturn64\0"
8305 /* 3841 */ "MIPSeh_return64\0"
8306 /* 3857 */ "LBu64\0"
8307 /* 3863 */ "LHu64\0"
8308 /* 3869 */ "SLTu64\0"
8309 /* 3876 */ "LEA_ADDiu64\0"
8310 /* 3888 */ "SLTiu64\0"
8311 /* 3896 */ "MoveR3216\0"
8312 /* 3906 */ "RetRA16\0"
8313 /* 3914 */ "JalB16\0"
8314 /* 3921 */ "LD_F16\0"
8315 /* 3928 */ "ST_F16\0"
8316 /* 3935 */ "ATOMIC_LOAD_SUB_I16\0"
8317 /* 3955 */ "ATOMIC_LOAD_ADD_I16\0"
8318 /* 3975 */ "ATOMIC_LOAD_NAND_I16\0"
8319 /* 3996 */ "ATOMIC_LOAD_AND_I16\0"
8320 /* 4016 */ "ATOMIC_LOAD_UMIN_I16\0"
8321 /* 4037 */ "ATOMIC_LOAD_MIN_I16\0"
8322 /* 4057 */ "ATOMIC_SWAP_I16\0"
8323 /* 4073 */ "ATOMIC_CMP_SWAP_I16\0"
8324 /* 4093 */ "ATOMIC_LOAD_XOR_I16\0"
8325 /* 4113 */ "ATOMIC_LOAD_OR_I16\0"
8326 /* 4132 */ "ATOMIC_LOAD_UMAX_I16\0"
8327 /* 4153 */ "ATOMIC_LOAD_MAX_I16\0"
8328 /* 4173 */ "Move32R16\0"
8329 /* 4183 */ "SraX16\0"
8330 /* 4190 */ "RestoreX16\0"
8331 /* 4201 */ "SaveX16\0"
8332 /* 4209 */ "BtnezT8CmpiX16\0"
8333 /* 4224 */ "BteqzT8CmpiX16\0"
8334 /* 4239 */ "BtnezT8SltiX16\0"
8335 /* 4254 */ "BteqzT8SltiX16\0"
8336 /* 4269 */ "SllX16\0"
8337 /* 4276 */ "SrlX16\0"
8338 /* 4283 */ "LbRxRyOffMemX16\0"
8339 /* 4299 */ "SbRxRyOffMemX16\0"
8340 /* 4315 */ "LhRxRyOffMemX16\0"
8341 /* 4331 */ "ShRxRyOffMemX16\0"
8342 /* 4347 */ "LbuRxRyOffMemX16\0"
8343 /* 4364 */ "LhuRxRyOffMemX16\0"
8344 /* 4381 */ "AddiuRxRyOffMemX16\0"
8345 /* 4400 */ "LwRxRyOffMemX16\0"
8346 /* 4416 */ "SwRxRyOffMemX16\0"
8347 /* 4432 */ "AddiuRxPcImmX16\0"
8348 /* 4448 */ "AddiuSpImmX16\0"
8349 /* 4462 */ "LwRxSpImmX16\0"
8350 /* 4475 */ "SwRxSpImmX16\0"
8351 /* 4488 */ "SltiCCRxImmX16\0"
8352 /* 4503 */ "SltiuCCRxImmX16\0"
8353 /* 4519 */ "LiRxImmX16\0"
8354 /* 4530 */ "CmpiRxImmX16\0"
8355 /* 4543 */ "SltiRxImmX16\0"
8356 /* 4556 */ "AddiuRxImmX16\0"
8357 /* 4570 */ "SltiuRxImmX16\0"
8358 /* 4584 */ "AddiuRxRxImmX16\0"
8359 /* 4600 */ "BnezRxImmX16\0"
8360 /* 4613 */ "BeqzRxImmX16\0"
8361 /* 4626 */ "BimmX16\0"
8362 /* 4634 */ "LiRxImmAlignX16\0"
8363 /* 4650 */ "LwRxPcTcpX16\0"
8364 /* 4663 */ "BtnezT8CmpX16\0"
8365 /* 4677 */ "BteqzT8CmpX16\0"
8366 /* 4691 */ "BtnezT8SltX16\0"
8367 /* 4705 */ "BteqzT8SltX16\0"
8368 /* 4719 */ "BtnezT8SltiuX16\0"
8369 /* 4735 */ "BteqzT8SltiuX16\0"
8370 /* 4751 */ "BtnezT8SltuX16\0"
8371 /* 4766 */ "BteqzT8SltuX16\0"
8372 /* 4781 */ "BtnezX16\0"
8373 /* 4790 */ "BteqzX16\0"
8374 /* 4799 */ "JrcRa16\0"
8375 /* 4807 */ "JrRa16\0"
8376 /* 4814 */ "Restore16\0"
8377 /* 4824 */ "GotPrologue16\0"
8378 /* 4838 */ "Save16\0"
8379 /* 4845 */ "JumpLinkReg16\0"
8380 /* 4859 */ "Mfhi16\0"
8381 /* 4866 */ "Break16\0"
8382 /* 4874 */ "Jal16\0"
8383 /* 4880 */ "AddiuSpImm16\0"
8384 /* 4893 */ "LiRxImm16\0"
8385 /* 4903 */ "CmpiRxImm16\0"
8386 /* 4915 */ "SltiRxImm16\0"
8387 /* 4927 */ "SltiuRxImm16\0"
8388 /* 4940 */ "AddiuRxRxImm16\0"
8389 /* 4955 */ "BnezRxImm16\0"
8390 /* 4967 */ "BeqzRxImm16\0"
8391 /* 4979 */ "Bimm16\0"
8392 /* 4986 */ "Mflo16\0"
8393 /* 4993 */ "LwRxPcTcp16\0"
8394 /* 5005 */ "SebRx16\0"
8395 /* 5013 */ "JrcRx16\0"
8396 /* 5021 */ "SehRx16\0"
8397 /* 5029 */ "SltCCRxRy16\0"
8398 /* 5041 */ "SltuCCRxRy16\0"
8399 /* 5054 */ "NegRxRy16\0"
8400 /* 5064 */ "CmpRxRy16\0"
8401 /* 5074 */ "SltRxRy16\0"
8402 /* 5084 */ "MultRxRy16\0"
8403 /* 5095 */ "NotRxRy16\0"
8404 /* 5105 */ "SltuRxRy16\0"
8405 /* 5116 */ "MultuRxRy16\0"
8406 /* 5128 */ "DivuRxRy16\0"
8407 /* 5139 */ "SravRxRy16\0"
8408 /* 5150 */ "DivRxRy16\0"
8409 /* 5160 */ "SllvRxRy16\0"
8410 /* 5171 */ "SrlvRxRy16\0"
8411 /* 5182 */ "AndRxRxRy16\0"
8412 /* 5194 */ "OrRxRxRy16\0"
8413 /* 5205 */ "XorRxRxRy16\0"
8414 /* 5217 */ "MultRxRyRz16\0"
8415 /* 5230 */ "SubuRxRyRz16\0"
8416 /* 5243 */ "AdduRxRyRz16\0"
8417 /* 5256 */ "SltuRxRyRz16\0"
8418 /* 5269 */ "MultuRxRyRz16\0"
8419 /* 5283 */ "Btnez16\0"
8420 /* 5291 */ "Bteqz16\0"
8421 /* 5299 */ "PseudoIndrectHazardBranch64R6\0"
8422 /* 5329 */ "PseudoIndirectBranch64R6\0"
8423 /* 5354 */ "MFC0_MMR6\0"
8424 /* 5364 */ "MFHC0_MMR6\0"
8425 /* 5375 */ "MTHC0_MMR6\0"
8426 /* 5386 */ "MTC0_MMR6\0"
8427 /* 5396 */ "MFC1_MMR6\0"
8428 /* 5406 */ "MTC1_MMR6\0"
8429 /* 5416 */ "LDC2_MMR6\0"
8430 /* 5426 */ "SDC2_MMR6\0"
8431 /* 5436 */ "MFC2_MMR6\0"
8432 /* 5446 */ "MFHC2_MMR6\0"
8433 /* 5457 */ "MTHC2_MMR6\0"
8434 /* 5468 */ "MTC2_MMR6\0"
8435 /* 5478 */ "LWC2_MMR6\0"
8436 /* 5488 */ "SWC2_MMR6\0"
8437 /* 5498 */ "LDC1_D64_MMR6\0"
8438 /* 5512 */ "SDC1_D64_MMR6\0"
8439 /* 5526 */ "SB16_MMR6\0"
8440 /* 5536 */ "BC16_MMR6\0"
8441 /* 5546 */ "JRC16_MMR6\0"
8442 /* 5557 */ "JALRC16_MMR6\0"
8443 /* 5570 */ "BNEZC16_MMR6\0"
8444 /* 5583 */ "BEQZC16_MMR6\0"
8445 /* 5596 */ "AND16_MMR6\0"
8446 /* 5607 */ "MOVE16_MMR6\0"
8447 /* 5619 */ "SH16_MMR6\0"
8448 /* 5629 */ "ANDI16_MMR6\0"
8449 /* 5641 */ "LI16_MMR6\0"
8450 /* 5651 */ "BREAK16_MMR6\0"
8451 /* 5664 */ "SLL16_MMR6\0"
8452 /* 5675 */ "SRL16_MMR6\0"
8453 /* 5686 */ "LWM16_MMR6\0"
8454 /* 5697 */ "SWM16_MMR6\0"
8455 /* 5708 */ "SDBBP16_MMR6\0"
8456 /* 5721 */ "XOR16_MMR6\0"
8457 /* 5732 */ "NOT16_MMR6\0"
8458 /* 5743 */ "SUBU16_MMR6\0"
8459 /* 5755 */ "ADDU16_MMR6\0"
8460 /* 5767 */ "SW16_MMR6\0"
8461 /* 5777 */ "LSA_MMR6\0"
8462 /* 5786 */ "EHB_MMR6\0"
8463 /* 5795 */ "JALRC_HB_MMR6\0"
8464 /* 5809 */ "LB_MMR6\0"
8465 /* 5817 */ "SB_MMR6\0"
8466 /* 5825 */ "SUB_MMR6\0"
8467 /* 5834 */ "BC_MMR6\0"
8468 /* 5842 */ "BGEC_MMR6\0"
8469 /* 5852 */ "BNEC_MMR6\0"
8470 /* 5862 */ "JIC_MMR6\0"
8471 /* 5871 */ "BALC_MMR6\0"
8472 /* 5881 */ "JIALC_MMR6\0"
8473 /* 5892 */ "BGEZALC_MMR6\0"
8474 /* 5905 */ "BLEZALC_MMR6\0"
8475 /* 5918 */ "BNEZALC_MMR6\0"
8476 /* 5931 */ "BEQZALC_MMR6\0"
8477 /* 5944 */ "BGTZALC_MMR6\0"
8478 /* 5957 */ "BLTZALC_MMR6\0"
8479 /* 5970 */ "ERETNC_MMR6\0"
8480 /* 5982 */ "SYNC_MMR6\0"
8481 /* 5992 */ "AUIPC_MMR6\0"
8482 /* 6003 */ "ALUIPC_MMR6\0"
8483 /* 6015 */ "ADDIUPC_MMR6\0"
8484 /* 6028 */ "LWPC_MMR6\0"
8485 /* 6038 */ "BEQC_MMR6\0"
8486 /* 6048 */ "JALRC_MMR6\0"
8487 /* 6059 */ "SC_MMR6\0"
8488 /* 6067 */ "BLTC_MMR6\0"
8489 /* 6077 */ "BGEUC_MMR6\0"
8490 /* 6088 */ "BLTUC_MMR6\0"
8491 /* 6099 */ "BNVC_MMR6\0"
8492 /* 6109 */ "BOVC_MMR6\0"
8493 /* 6119 */ "BGEZC_MMR6\0"
8494 /* 6130 */ "BLEZC_MMR6\0"
8495 /* 6141 */ "BC1NEZC_MMR6\0"
8496 /* 6154 */ "BC2NEZC_MMR6\0"
8497 /* 6167 */ "BNEZC_MMR6\0"
8498 /* 6178 */ "BC1EQZC_MMR6\0"
8499 /* 6191 */ "BC2EQZC_MMR6\0"
8500 /* 6204 */ "BEQZC_MMR6\0"
8501 /* 6215 */ "BGTZC_MMR6\0"
8502 /* 6226 */ "BLTZC_MMR6\0"
8503 /* 6237 */ "ADD_MMR6\0"
8504 /* 6246 */ "AND_MMR6\0"
8505 /* 6255 */ "MOD_MMR6\0"
8506 /* 6264 */ "MINA_D_MMR6\0"
8507 /* 6276 */ "MAXA_D_MMR6\0"
8508 /* 6288 */ "CMP_SLE_D_MMR6\0"
8509 /* 6303 */ "CMP_SULE_D_MMR6\0"
8510 /* 6319 */ "CMP_ULE_D_MMR6\0"
8511 /* 6334 */ "CMP_LE_D_MMR6\0"
8512 /* 6348 */ "CMP_SAF_D_MMR6\0"
8513 /* 6363 */ "CMP_AF_D_MMR6\0"
8514 /* 6377 */ "MSUBF_D_MMR6\0"
8515 /* 6390 */ "MADDF_D_MMR6\0"
8516 /* 6403 */ "SEL_D_MMR6\0"
8517 /* 6414 */ "TRUNC_L_D_MMR6\0"
8518 /* 6429 */ "ROUND_L_D_MMR6\0"
8519 /* 6444 */ "CEIL_L_D_MMR6\0"
8520 /* 6458 */ "FLOOR_L_D_MMR6\0"
8521 /* 6473 */ "CVT_L_D_MMR6\0"
8522 /* 6486 */ "MIN_D_MMR6\0"
8523 /* 6497 */ "CMP_SUN_D_MMR6\0"
8524 /* 6512 */ "CMP_UN_D_MMR6\0"
8525 /* 6526 */ "CMP_SEQ_D_MMR6\0"
8526 /* 6541 */ "CMP_SUEQ_D_MMR6\0"
8527 /* 6557 */ "CMP_UEQ_D_MMR6\0"
8528 /* 6572 */ "CMP_EQ_D_MMR6\0"
8529 /* 6586 */ "CLASS_D_MMR6\0"
8530 /* 6599 */ "CMP_SLT_D_MMR6\0"
8531 /* 6614 */ "CMP_SULT_D_MMR6\0"
8532 /* 6630 */ "CMP_ULT_D_MMR6\0"
8533 /* 6645 */ "CMP_LT_D_MMR6\0"
8534 /* 6659 */ "RINT_D_MMR6\0"
8535 /* 6671 */ "FMOV_D_MMR6\0"
8536 /* 6683 */ "TRUNC_W_D_MMR6\0"
8537 /* 6698 */ "ROUND_W_D_MMR6\0"
8538 /* 6713 */ "CEIL_W_D_MMR6\0"
8539 /* 6727 */ "FLOOR_W_D_MMR6\0"
8540 /* 6742 */ "MAX_D_MMR6\0"
8541 /* 6753 */ "SELNEZ_D_MMR6\0"
8542 /* 6767 */ "SELEQZ_D_MMR6\0"
8543 /* 6781 */ "CACHE_MMR6\0"
8544 /* 6792 */ "SIGRIE_MMR6\0"
8545 /* 6804 */ "PAUSE_MMR6\0"
8546 /* 6815 */ "PREF_MMR6\0"
8547 /* 6825 */ "TLBINVF_MMR6\0"
8548 /* 6838 */ "TAILCALLREG_MMR6\0"
8549 /* 6855 */ "WSBH_MMR6\0"
8550 /* 6865 */ "SH_MMR6\0"
8551 /* 6873 */ "MUH_MMR6\0"
8552 /* 6882 */ "SYNCI_MMR6\0"
8553 /* 6893 */ "ANDI_MMR6\0"
8554 /* 6903 */ "EI_MMR6\0"
8555 /* 6911 */ "XORI_MMR6\0"
8556 /* 6921 */ "AUI_MMR6\0"
8557 /* 6930 */ "LUI_MMR6\0"
8558 /* 6939 */ "GINVI_MMR6\0"
8559 /* 6950 */ "BREAK_MMR6\0"
8560 /* 6961 */ "JAL_MMR6\0"
8561 /* 6970 */ "TAILCALL_MMR6\0"
8562 /* 6984 */ "SLL_MMR6\0"
8563 /* 6993 */ "MUL_MMR6\0"
8564 /* 7002 */ "CVT_D_L_MMR6\0"
8565 /* 7015 */ "CVT_S_L_MMR6\0"
8566 /* 7028 */ "ALIGN_MMR6\0"
8567 /* 7039 */ "CLO_MMR6\0"
8568 /* 7048 */ "BITSWAP_MMR6\0"
8569 /* 7061 */ "SDBBP_MMR6\0"
8570 /* 7072 */ "MOVEP_MMR6\0"
8571 /* 7083 */ "SSNOP_MMR6\0"
8572 /* 7094 */ "JRCADDIUSP_MMR6\0"
8573 /* 7110 */ "SWSP_MMR6\0"
8574 /* 7120 */ "DVP_MMR6\0"
8575 /* 7129 */ "EVP_MMR6\0"
8576 /* 7138 */ "NOR_MMR6\0"
8577 /* 7147 */ "XOR_MMR6\0"
8578 /* 7156 */ "RDPGPR_MMR6\0"
8579 /* 7168 */ "WRPGPR_MMR6\0"
8580 /* 7180 */ "RDHWR_MMR6\0"
8581 /* 7191 */ "INS_MMR6\0"
8582 /* 7200 */ "MINA_S_MMR6\0"
8583 /* 7212 */ "MAXA_S_MMR6\0"
8584 /* 7224 */ "FSUB_S_MMR6\0"
8585 /* 7236 */ "FADD_S_MMR6\0"
8586 /* 7248 */ "CMP_SLE_S_MMR6\0"
8587 /* 7263 */ "CMP_SULE_S_MMR6\0"
8588 /* 7279 */ "CMP_ULE_S_MMR6\0"
8589 /* 7294 */ "CMP_LE_S_MMR6\0"
8590 /* 7308 */ "CMP_SAF_S_MMR6\0"
8591 /* 7323 */ "CMP_AF_S_MMR6\0"
8592 /* 7337 */ "MSUBF_S_MMR6\0"
8593 /* 7350 */ "MADDF_S_MMR6\0"
8594 /* 7363 */ "FNEG_S_MMR6\0"
8595 /* 7375 */ "SEL_S_MMR6\0"
8596 /* 7386 */ "FMUL_S_MMR6\0"
8597 /* 7398 */ "TRUNC_L_S_MMR6\0"
8598 /* 7413 */ "ROUND_L_S_MMR6\0"
8599 /* 7428 */ "CEIL_L_S_MMR6\0"
8600 /* 7442 */ "FLOOR_L_S_MMR6\0"
8601 /* 7457 */ "CVT_L_S_MMR6\0"
8602 /* 7470 */ "MIN_S_MMR6\0"
8603 /* 7481 */ "CMP_SUN_S_MMR6\0"
8604 /* 7496 */ "CMP_UN_S_MMR6\0"
8605 /* 7510 */ "CMP_SEQ_S_MMR6\0"
8606 /* 7525 */ "CMP_SUEQ_S_MMR6\0"
8607 /* 7541 */ "CMP_UEQ_S_MMR6\0"
8608 /* 7556 */ "CMP_EQ_S_MMR6\0"
8609 /* 7570 */ "CLASS_S_MMR6\0"
8610 /* 7583 */ "CMP_SLT_S_MMR6\0"
8611 /* 7598 */ "CMP_SULT_S_MMR6\0"
8612 /* 7614 */ "CMP_ULT_S_MMR6\0"
8613 /* 7629 */ "CMP_LT_S_MMR6\0"
8614 /* 7643 */ "RINT_S_MMR6\0"
8615 /* 7655 */ "FDIV_S_MMR6\0"
8616 /* 7667 */ "FMOV_S_MMR6\0"
8617 /* 7679 */ "TRUNC_W_S_MMR6\0"
8618 /* 7694 */ "ROUND_W_S_MMR6\0"
8619 /* 7709 */ "CEIL_W_S_MMR6\0"
8620 /* 7723 */ "FLOOR_W_S_MMR6\0"
8621 /* 7738 */ "CVT_W_S_MMR6\0"
8622 /* 7751 */ "MAX_S_MMR6\0"
8623 /* 7762 */ "SELNEZ_S_MMR6\0"
8624 /* 7776 */ "SELEQZ_S_MMR6\0"
8625 /* 7790 */ "DERET_MMR6\0"
8626 /* 7801 */ "WAIT_MMR6\0"
8627 /* 7811 */ "GINVT_MMR6\0"
8628 /* 7822 */ "EXT_MMR6\0"
8629 /* 7831 */ "LBU_MMR6\0"
8630 /* 7840 */ "SUBU_MMR6\0"
8631 /* 7850 */ "ADDU_MMR6\0"
8632 /* 7860 */ "MODU_MMR6\0"
8633 /* 7870 */ "MUHU_MMR6\0"
8634 /* 7880 */ "ADDIU_MMR6\0"
8635 /* 7891 */ "MULU_MMR6\0"
8636 /* 7901 */ "DIVU_MMR6\0"
8637 /* 7911 */ "DIV_MMR6\0"
8638 /* 7920 */ "TLBINV_MMR6\0"
8639 /* 7932 */ "LW_MMR6\0"
8640 /* 7940 */ "SW_MMR6\0"
8641 /* 7948 */ "CVT_S_W_MMR6\0"
8642 /* 7961 */ "SELNEZ_MMR6\0"
8643 /* 7973 */ "CLZ_MMR6\0"
8644 /* 7982 */ "SELEQZ_MMR6\0"
8645 /* 7994 */ "PseudoIndirectBranch_MMR6\0"
8646 /* 8020 */ "LDC2_R6\0"
8647 /* 8028 */ "SDC2_R6\0"
8648 /* 8036 */ "LWC2_R6\0"
8649 /* 8044 */ "SWC2_R6\0"
8650 /* 8052 */ "JR_HB64_R6\0"
8651 /* 8063 */ "SC64_R6\0"
8652 /* 8071 */ "LL64_R6\0"
8653 /* 8079 */ "DLSA_R6\0"
8654 /* 8087 */ "JR_HB_R6\0"
8655 /* 8096 */ "SC_R6\0"
8656 /* 8102 */ "SCD_R6\0"
8657 /* 8109 */ "LLD_R6\0"
8658 /* 8116 */ "CACHE_R6\0"
8659 /* 8125 */ "PREF_R6\0"
8660 /* 8133 */ "LL_R6\0"
8661 /* 8139 */ "DMUL_R6\0"
8662 /* 8147 */ "DCLO_R6\0"
8663 /* 8155 */ "SDBBP_R6\0"
8664 /* 8164 */ "DCLZ_R6\0"
8665 /* 8172 */ "PseudoIndrectHazardBranchR6\0"
8666 /* 8200 */ "PseudoIndirectBranchR6\0"
8667 /* 8223 */ "LOAD_ACC128\0"
8668 /* 8235 */ "STORE_ACC128\0"
8669 /* 8248 */ "ATOMIC_LOAD_SUB_I8\0"
8670 /* 8267 */ "ATOMIC_LOAD_ADD_I8\0"
8671 /* 8286 */ "ATOMIC_LOAD_NAND_I8\0"
8672 /* 8306 */ "ATOMIC_LOAD_AND_I8\0"
8673 /* 8325 */ "ATOMIC_LOAD_UMIN_I8\0"
8674 /* 8345 */ "ATOMIC_LOAD_MIN_I8\0"
8675 /* 8364 */ "ATOMIC_SWAP_I8\0"
8676 /* 8379 */ "ATOMIC_CMP_SWAP_I8\0"
8677 /* 8398 */ "ATOMIC_LOAD_XOR_I8\0"
8678 /* 8417 */ "ATOMIC_LOAD_OR_I8\0"
8679 /* 8435 */ "ATOMIC_LOAD_UMAX_I8\0"
8680 /* 8455 */ "ATOMIC_LOAD_MAX_I8\0"
8681 /* 8474 */ "SAA\0"
8682 /* 8478 */ "PRECEU_PH_QBLA\0"
8683 /* 8493 */ "PRECEQU_PH_QBLA\0"
8684 /* 8509 */ "G_FMA\0"
8685 /* 8515 */ "G_STRICT_FMA\0"
8686 /* 8528 */ "PRECEU_PH_QBRA\0"
8687 /* 8543 */ "PRECEQU_PH_QBRA\0"
8688 /* 8559 */ "DSRA\0"
8689 /* 8564 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0"
8690 /* 8591 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0"
8691 /* 8618 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0"
8692 /* 8646 */ "ATOMIC_LOAD_AND_I32_POSTRA\0"
8693 /* 8673 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0"
8694 /* 8701 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0"
8695 /* 8728 */ "ATOMIC_SWAP_I32_POSTRA\0"
8696 /* 8751 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0"
8697 /* 8778 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0"
8698 /* 8805 */ "ATOMIC_LOAD_OR_I32_POSTRA\0"
8699 /* 8831 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0"
8700 /* 8859 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0"
8701 /* 8886 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0"
8702 /* 8913 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0"
8703 /* 8940 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0"
8704 /* 8968 */ "ATOMIC_LOAD_AND_I64_POSTRA\0"
8705 /* 8995 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0"
8706 /* 9023 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0"
8707 /* 9050 */ "ATOMIC_SWAP_I64_POSTRA\0"
8708 /* 9073 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0"
8709 /* 9100 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0"
8710 /* 9127 */ "ATOMIC_LOAD_OR_I64_POSTRA\0"
8711 /* 9153 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0"
8712 /* 9181 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0"
8713 /* 9208 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0"
8714 /* 9235 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0"
8715 /* 9262 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0"
8716 /* 9290 */ "ATOMIC_LOAD_AND_I16_POSTRA\0"
8717 /* 9317 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0"
8718 /* 9345 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0"
8719 /* 9372 */ "ATOMIC_SWAP_I16_POSTRA\0"
8720 /* 9395 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0"
8721 /* 9422 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0"
8722 /* 9449 */ "ATOMIC_LOAD_OR_I16_POSTRA\0"
8723 /* 9475 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0"
8724 /* 9503 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0"
8725 /* 9530 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0"
8726 /* 9556 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0"
8727 /* 9582 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0"
8728 /* 9609 */ "ATOMIC_LOAD_AND_I8_POSTRA\0"
8729 /* 9635 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0"
8730 /* 9662 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0"
8731 /* 9688 */ "ATOMIC_SWAP_I8_POSTRA\0"
8732 /* 9710 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0"
8733 /* 9736 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0"
8734 /* 9762 */ "ATOMIC_LOAD_OR_I8_POSTRA\0"
8735 /* 9787 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0"
8736 /* 9814 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0"
8737 /* 9840 */ "RetRA\0"
8738 /* 9846 */ "DLSA\0"
8739 /* 9851 */ "CFCMSA\0"
8740 /* 9858 */ "CTCMSA\0"
8741 /* 9865 */ "CRC32B\0"
8742 /* 9872 */ "CRC32CB\0"
8743 /* 9880 */ "SEB\0"
8744 /* 9884 */ "EHB\0"
8745 /* 9888 */ "TAILCALLREGHB\0"
8746 /* 9902 */ "JR_HB\0"
8747 /* 9908 */ "JALR_HB\0"
8748 /* 9916 */ "LB\0"
8749 /* 9919 */ "SHRA_QB\0"
8750 /* 9927 */ "CMPGDU_LE_QB\0"
8751 /* 9940 */ "CMPGU_LE_QB\0"
8752 /* 9952 */ "PseudoCMPU_LE_QB\0"
8753 /* 9969 */ "SUBUH_QB\0"
8754 /* 9978 */ "ADDUH_QB\0"
8755 /* 9987 */ "PseudoPICK_QB\0"
8756 /* 10001 */ "SHLL_QB\0"
8757 /* 10009 */ "REPL_QB\0"
8758 /* 10017 */ "SHRL_QB\0"
8759 /* 10025 */ "CMPGDU_EQ_QB\0"
8760 /* 10038 */ "CMPGU_EQ_QB\0"
8761 /* 10050 */ "PseudoCMPU_EQ_QB\0"
8762 /* 10067 */ "SHRA_R_QB\0"
8763 /* 10077 */ "SUBUH_R_QB\0"
8764 /* 10088 */ "ADDUH_R_QB\0"
8765 /* 10099 */ "SHRAV_R_QB\0"
8766 /* 10110 */ "ABSQ_S_QB\0"
8767 /* 10120 */ "SUBU_S_QB\0"
8768 /* 10130 */ "ADDU_S_QB\0"
8769 /* 10140 */ "CMPGDU_LT_QB\0"
8770 /* 10153 */ "CMPGU_LT_QB\0"
8771 /* 10165 */ "PseudoCMPU_LT_QB\0"
8772 /* 10182 */ "SUBU_QB\0"
8773 /* 10190 */ "ADDU_QB\0"
8774 /* 10198 */ "SHRAV_QB\0"
8775 /* 10207 */ "SHLLV_QB\0"
8776 /* 10216 */ "REPLV_QB\0"
8777 /* 10225 */ "SHRLV_QB\0"
8778 /* 10234 */ "RADDU_W_QB\0"
8779 /* 10245 */ "SB\0"
8780 /* 10248 */ "MODSUB\0"
8781 /* 10255 */ "G_FSUB\0"
8782 /* 10262 */ "G_STRICT_FSUB\0"
8783 /* 10276 */ "G_ATOMICRMW_FSUB\0"
8784 /* 10293 */ "PseudoMSUB\0"
8785 /* 10304 */ "G_SUB\0"
8786 /* 10310 */ "G_ATOMICRMW_SUB\0"
8787 /* 10326 */ "SRA_B\0"
8788 /* 10332 */ "ADD_A_B\0"
8789 /* 10340 */ "MIN_A_B\0"
8790 /* 10348 */ "ADDS_A_B\0"
8791 /* 10357 */ "MAX_A_B\0"
8792 /* 10365 */ "NLOC_B\0"
8793 /* 10372 */ "NLZC_B\0"
8794 /* 10379 */ "SLD_B\0"
8795 /* 10385 */ "PCKOD_B\0"
8796 /* 10393 */ "ILVOD_B\0"
8797 /* 10401 */ "INSVE_B\0"
8798 /* 10409 */ "VSHF_B\0"
8799 /* 10416 */ "BNEG_B\0"
8800 /* 10423 */ "SRAI_B\0"
8801 /* 10430 */ "SLDI_B\0"
8802 /* 10437 */ "ANDI_B\0"
8803 /* 10444 */ "BNEGI_B\0"
8804 /* 10452 */ "BSELI_B\0"
8805 /* 10460 */ "SLLI_B\0"
8806 /* 10467 */ "SRLI_B\0"
8807 /* 10474 */ "BINSLI_B\0"
8808 /* 10483 */ "CEQI_B\0"
8809 /* 10490 */ "SRARI_B\0"
8810 /* 10498 */ "BCLRI_B\0"
8811 /* 10506 */ "SRLRI_B\0"
8812 /* 10514 */ "NORI_B\0"
8813 /* 10521 */ "XORI_B\0"
8814 /* 10528 */ "BINSRI_B\0"
8815 /* 10537 */ "SPLATI_B\0"
8816 /* 10546 */ "BSETI_B\0"
8817 /* 10554 */ "SUBVI_B\0"
8818 /* 10562 */ "ADDVI_B\0"
8819 /* 10570 */ "BMZI_B\0"
8820 /* 10577 */ "BMNZI_B\0"
8821 /* 10585 */ "FILL_B\0"
8822 /* 10592 */ "SLL_B\0"
8823 /* 10598 */ "SRL_B\0"
8824 /* 10604 */ "BINSL_B\0"
8825 /* 10612 */ "ILVL_B\0"
8826 /* 10619 */ "CEQ_B\0"
8827 /* 10625 */ "SRAR_B\0"
8828 /* 10632 */ "BCLR_B\0"
8829 /* 10639 */ "SRLR_B\0"
8830 /* 10646 */ "BINSR_B\0"
8831 /* 10654 */ "ILVR_B\0"
8832 /* 10661 */ "ASUB_S_B\0"
8833 /* 10670 */ "MOD_S_B\0"
8834 /* 10678 */ "CLE_S_B\0"
8835 /* 10686 */ "AVE_S_B\0"
8836 /* 10694 */ "CLEI_S_B\0"
8837 /* 10703 */ "MINI_S_B\0"
8838 /* 10712 */ "CLTI_S_B\0"
8839 /* 10721 */ "MAXI_S_B\0"
8840 /* 10730 */ "MIN_S_B\0"
8841 /* 10738 */ "AVER_S_B\0"
8842 /* 10747 */ "SUBS_S_B\0"
8843 /* 10756 */ "ADDS_S_B\0"
8844 /* 10765 */ "SAT_S_B\0"
8845 /* 10773 */ "CLT_S_B\0"
8846 /* 10781 */ "SUBSUU_S_B\0"
8847 /* 10792 */ "DIV_S_B\0"
8848 /* 10800 */ "MAX_S_B\0"
8849 /* 10808 */ "COPY_S_B\0"
8850 /* 10817 */ "SPLAT_B\0"
8851 /* 10825 */ "BSET_B\0"
8852 /* 10832 */ "PCNT_B\0"
8853 /* 10839 */ "INSERT_B\0"
8854 /* 10848 */ "ST_B\0"
8855 /* 10853 */ "ASUB_U_B\0"
8856 /* 10862 */ "MOD_U_B\0"
8857 /* 10870 */ "CLE_U_B\0"
8858 /* 10878 */ "AVE_U_B\0"
8859 /* 10886 */ "CLEI_U_B\0"
8860 /* 10895 */ "MINI_U_B\0"
8861 /* 10904 */ "CLTI_U_B\0"
8862 /* 10913 */ "MAXI_U_B\0"
8863 /* 10922 */ "MIN_U_B\0"
8864 /* 10930 */ "AVER_U_B\0"
8865 /* 10939 */ "SUBS_U_B\0"
8866 /* 10948 */ "ADDS_U_B\0"
8867 /* 10957 */ "SUBSUS_U_B\0"
8868 /* 10968 */ "SAT_U_B\0"
8869 /* 10976 */ "CLT_U_B\0"
8870 /* 10984 */ "DIV_U_B\0"
8871 /* 10992 */ "MAX_U_B\0"
8872 /* 11000 */ "COPY_U_B\0"
8873 /* 11009 */ "MSUBV_B\0"
8874 /* 11017 */ "MADDV_B\0"
8875 /* 11025 */ "PCKEV_B\0"
8876 /* 11033 */ "ILVEV_B\0"
8877 /* 11041 */ "MULV_B\0"
8878 /* 11048 */ "BZ_B\0"
8879 /* 11053 */ "BNZ_B\0"
8880 /* 11059 */ "BC\0"
8881 /* 11062 */ "BGEC\0"
8882 /* 11067 */ "BNEC\0"
8883 /* 11072 */ "JIC\0"
8884 /* 11076 */ "G_INTRINSIC\0"
8885 /* 11088 */ "BALC\0"
8886 /* 11093 */ "JIALC\0"
8887 /* 11099 */ "BGEZALC\0"
8888 /* 11107 */ "BLEZALC\0"
8889 /* 11115 */ "BNEZALC\0"
8890 /* 11123 */ "BEQZALC\0"
8891 /* 11131 */ "BGTZALC\0"
8892 /* 11139 */ "BLTZALC\0"
8893 /* 11147 */ "ERETNC\0"
8894 /* 11154 */ "G_FPTRUNC\0"
8895 /* 11164 */ "G_INTRINSIC_TRUNC\0"
8896 /* 11182 */ "G_TRUNC\0"
8897 /* 11190 */ "G_BUILD_VECTOR_TRUNC\0"
8898 /* 11211 */ "SYNC\0"
8899 /* 11216 */ "G_DYN_STACKALLOC\0"
8900 /* 11233 */ "LDPC\0"
8901 /* 11238 */ "AUIPC\0"
8902 /* 11244 */ "ALUIPC\0"
8903 /* 11251 */ "ADDIUPC\0"
8904 /* 11259 */ "LWUPC\0"
8905 /* 11265 */ "LWPC\0"
8906 /* 11270 */ "BEQC\0"
8907 /* 11275 */ "ADDSC\0"
8908 /* 11281 */ "BLTC\0"
8909 /* 11286 */ "BGEUC\0"
8910 /* 11292 */ "BLTUC\0"
8911 /* 11298 */ "BNVC\0"
8912 /* 11303 */ "BOVC\0"
8913 /* 11308 */ "ADDWC\0"
8914 /* 11314 */ "BGEZC\0"
8915 /* 11320 */ "BLEZC\0"
8916 /* 11326 */ "BNEZC\0"
8917 /* 11332 */ "BEQZC\0"
8918 /* 11338 */ "BGTZC\0"
8919 /* 11344 */ "BLTZC\0"
8920 /* 11350 */ "CRC32D\0"
8921 /* 11357 */ "SAAD\0"
8922 /* 11362 */ "G_FMAD\0"
8923 /* 11369 */ "G_INDEXED_SEXTLOAD\0"
8924 /* 11388 */ "G_SEXTLOAD\0"
8925 /* 11399 */ "G_INDEXED_ZEXTLOAD\0"
8926 /* 11418 */ "G_ZEXTLOAD\0"
8927 /* 11429 */ "G_INDEXED_LOAD\0"
8928 /* 11444 */ "G_LOAD\0"
8929 /* 11451 */ "CRC32CD\0"
8930 /* 11459 */ "SCD\0"
8931 /* 11463 */ "DADD\0"
8932 /* 11468 */ "G_VECREDUCE_FADD\0"
8933 /* 11485 */ "G_FADD\0"
8934 /* 11492 */ "G_VECREDUCE_SEQ_FADD\0"
8935 /* 11513 */ "G_STRICT_FADD\0"
8936 /* 11527 */ "G_ATOMICRMW_FADD\0"
8937 /* 11544 */ "PseudoMADD\0"
8938 /* 11555 */ "G_VECREDUCE_ADD\0"
8939 /* 11571 */ "G_ADD\0"
8940 /* 11577 */ "G_PTR_ADD\0"
8941 /* 11587 */ "G_ATOMICRMW_ADD\0"
8942 /* 11603 */ "DSHD\0"
8943 /* 11608 */ "YIELD\0"
8944 /* 11614 */ "LLD\0"
8945 /* 11618 */ "G_ATOMICRMW_NAND\0"
8946 /* 11635 */ "G_VECREDUCE_AND\0"
8947 /* 11651 */ "G_AND\0"
8948 /* 11657 */ "G_ATOMICRMW_AND\0"
8949 /* 11673 */ "PREPEND\0"
8950 /* 11681 */ "APPEND\0"
8951 /* 11688 */ "LIFETIME_END\0"
8952 /* 11701 */ "G_BRCOND\0"
8953 /* 11710 */ "G_LLROUND\0"
8954 /* 11720 */ "G_LROUND\0"
8955 /* 11729 */ "G_INTRINSIC_ROUND\0"
8956 /* 11747 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
8957 /* 11773 */ "DMOD\0"
8958 /* 11778 */ "LOAD_STACK_GUARD\0"
8959 /* 11795 */ "SD\0"
8960 /* 11798 */ "FLOG2_D\0"
8961 /* 11806 */ "FEXP2_D\0"
8962 /* 11814 */ "MINA_D\0"
8963 /* 11821 */ "SRA_D\0"
8964 /* 11827 */ "MAXA_D\0"
8965 /* 11834 */ "ADD_A_D\0"
8966 /* 11842 */ "FMIN_A_D\0"
8967 /* 11851 */ "ADDS_A_D\0"
8968 /* 11860 */ "FMAX_A_D\0"
8969 /* 11869 */ "FSUB_D\0"
8970 /* 11876 */ "FMSUB_D\0"
8971 /* 11884 */ "NLOC_D\0"
8972 /* 11891 */ "NLZC_D\0"
8973 /* 11898 */ "FADD_D\0"
8974 /* 11905 */ "FMADD_D\0"
8975 /* 11913 */ "SLD_D\0"
8976 /* 11919 */ "PCKOD_D\0"
8977 /* 11927 */ "ILVOD_D\0"
8978 /* 11935 */ "FCLE_D\0"
8979 /* 11942 */ "FSLE_D\0"
8980 /* 11949 */ "CMP_SLE_D\0"
8981 /* 11959 */ "FCULE_D\0"
8982 /* 11967 */ "FSULE_D\0"
8983 /* 11975 */ "CMP_SULE_D\0"
8984 /* 11986 */ "CMP_ULE_D\0"
8985 /* 11996 */ "CMP_LE_D\0"
8986 /* 12005 */ "FCNE_D\0"
8987 /* 12012 */ "FSNE_D\0"
8988 /* 12019 */ "FCUNE_D\0"
8989 /* 12027 */ "FSUNE_D\0"
8990 /* 12035 */ "INSVE_D\0"
8991 /* 12043 */ "FCAF_D\0"
8992 /* 12050 */ "FSAF_D\0"
8993 /* 12057 */ "CMP_SAF_D\0"
8994 /* 12067 */ "MSUBF_D\0"
8995 /* 12075 */ "MADDF_D\0"
8996 /* 12083 */ "VSHF_D\0"
8997 /* 12090 */ "CMP_F_D\0"
8998 /* 12098 */ "BNEG_D\0"
8999 /* 12105 */ "SRAI_D\0"
9000 /* 12112 */ "SLDI_D\0"
9001 /* 12119 */ "BNEGI_D\0"
9002 /* 12127 */ "SLLI_D\0"
9003 /* 12134 */ "SRLI_D\0"
9004 /* 12141 */ "BINSLI_D\0"
9005 /* 12150 */ "CEQI_D\0"
9006 /* 12157 */ "SRARI_D\0"
9007 /* 12165 */ "BCLRI_D\0"
9008 /* 12173 */ "SRLRI_D\0"
9009 /* 12181 */ "BINSRI_D\0"
9010 /* 12190 */ "SPLATI_D\0"
9011 /* 12199 */ "BSETI_D\0"
9012 /* 12207 */ "SUBVI_D\0"
9013 /* 12215 */ "ADDVI_D\0"
9014 /* 12223 */ "SEL_D\0"
9015 /* 12229 */ "FILL_D\0"
9016 /* 12236 */ "SLL_D\0"
9017 /* 12242 */ "FEXUPL_D\0"
9018 /* 12251 */ "FFQL_D\0"
9019 /* 12258 */ "SRL_D\0"
9020 /* 12264 */ "BINSL_D\0"
9021 /* 12272 */ "FMUL_D\0"
9022 /* 12279 */ "ILVL_D\0"
9023 /* 12286 */ "FMIN_D\0"
9024 /* 12293 */ "FCUN_D\0"
9025 /* 12300 */ "FSUN_D\0"
9026 /* 12307 */ "CMP_SUN_D\0"
9027 /* 12317 */ "CMP_UN_D\0"
9028 /* 12326 */ "FRCP_D\0"
9029 /* 12333 */ "FCEQ_D\0"
9030 /* 12340 */ "FSEQ_D\0"
9031 /* 12347 */ "CMP_SEQ_D\0"
9032 /* 12357 */ "FCUEQ_D\0"
9033 /* 12365 */ "FSUEQ_D\0"
9034 /* 12373 */ "CMP_SUEQ_D\0"
9035 /* 12384 */ "CMP_UEQ_D\0"
9036 /* 12394 */ "CMP_EQ_D\0"
9037 /* 12403 */ "SRAR_D\0"
9038 /* 12410 */ "LDR_D\0"
9039 /* 12416 */ "BCLR_D\0"
9040 /* 12423 */ "SRLR_D\0"
9041 /* 12430 */ "FCOR_D\0"
9042 /* 12437 */ "FSOR_D\0"
9043 /* 12444 */ "FEXUPR_D\0"
9044 /* 12453 */ "FFQR_D\0"
9045 /* 12460 */ "BINSR_D\0"
9046 /* 12468 */ "STR_D\0"
9047 /* 12474 */ "ILVR_D\0"
9048 /* 12481 */ "FABS_D\0"
9049 /* 12488 */ "FCLASS_D\0"
9050 /* 12497 */ "ASUB_S_D\0"
9051 /* 12506 */ "HSUB_S_D\0"
9052 /* 12515 */ "DPSUB_S_D\0"
9053 /* 12525 */ "FTRUNC_S_D\0"
9054 /* 12536 */ "HADD_S_D\0"
9055 /* 12545 */ "DPADD_S_D\0"
9056 /* 12555 */ "MOD_S_D\0"
9057 /* 12563 */ "CLE_S_D\0"
9058 /* 12571 */ "AVE_S_D\0"
9059 /* 12579 */ "CLEI_S_D\0"
9060 /* 12588 */ "MINI_S_D\0"
9061 /* 12597 */ "CLTI_S_D\0"
9062 /* 12606 */ "MAXI_S_D\0"
9063 /* 12615 */ "MIN_S_D\0"
9064 /* 12623 */ "DOTP_S_D\0"
9065 /* 12632 */ "AVER_S_D\0"
9066 /* 12641 */ "SUBS_S_D\0"
9067 /* 12650 */ "ADDS_S_D\0"
9068 /* 12659 */ "SAT_S_D\0"
9069 /* 12667 */ "CLT_S_D\0"
9070 /* 12675 */ "FFINT_S_D\0"
9071 /* 12685 */ "FTINT_S_D\0"
9072 /* 12695 */ "SUBSUU_S_D\0"
9073 /* 12706 */ "DIV_S_D\0"
9074 /* 12714 */ "MAX_S_D\0"
9075 /* 12722 */ "COPY_S_D\0"
9076 /* 12731 */ "SPLAT_D\0"
9077 /* 12739 */ "BSET_D\0"
9078 /* 12746 */ "FCLT_D\0"
9079 /* 12753 */ "FSLT_D\0"
9080 /* 12760 */ "CMP_SLT_D\0"
9081 /* 12770 */ "FCULT_D\0"
9082 /* 12778 */ "FSULT_D\0"
9083 /* 12786 */ "CMP_SULT_D\0"
9084 /* 12797 */ "CMP_ULT_D\0"
9085 /* 12807 */ "CMP_LT_D\0"
9086 /* 12816 */ "PCNT_D\0"
9087 /* 12823 */ "FRINT_D\0"
9088 /* 12831 */ "INSERT_D\0"
9089 /* 12840 */ "FSQRT_D\0"
9090 /* 12848 */ "FRSQRT_D\0"
9091 /* 12857 */ "ST_D\0"
9092 /* 12862 */ "ASUB_U_D\0"
9093 /* 12871 */ "HSUB_U_D\0"
9094 /* 12880 */ "DPSUB_U_D\0"
9095 /* 12890 */ "FTRUNC_U_D\0"
9096 /* 12901 */ "HADD_U_D\0"
9097 /* 12910 */ "DPADD_U_D\0"
9098 /* 12920 */ "MOD_U_D\0"
9099 /* 12928 */ "CLE_U_D\0"
9100 /* 12936 */ "AVE_U_D\0"
9101 /* 12944 */ "CLEI_U_D\0"
9102 /* 12953 */ "MINI_U_D\0"
9103 /* 12962 */ "CLTI_U_D\0"
9104 /* 12971 */ "MAXI_U_D\0"
9105 /* 12980 */ "MIN_U_D\0"
9106 /* 12988 */ "DOTP_U_D\0"
9107 /* 12997 */ "AVER_U_D\0"
9108 /* 13006 */ "SUBS_U_D\0"
9109 /* 13015 */ "ADDS_U_D\0"
9110 /* 13024 */ "SUBSUS_U_D\0"
9111 /* 13035 */ "SAT_U_D\0"
9112 /* 13043 */ "CLT_U_D\0"
9113 /* 13051 */ "FFINT_U_D\0"
9114 /* 13061 */ "FTINT_U_D\0"
9115 /* 13071 */ "DIV_U_D\0"
9116 /* 13079 */ "MAX_U_D\0"
9117 /* 13087 */ "MSUBV_D\0"
9118 /* 13095 */ "MADDV_D\0"
9119 /* 13103 */ "PCKEV_D\0"
9120 /* 13111 */ "ILVEV_D\0"
9121 /* 13119 */ "FDIV_D\0"
9122 /* 13126 */ "MULV_D\0"
9123 /* 13133 */ "PseudoTRUNC_W_D\0"
9124 /* 13149 */ "FMAX_D\0"
9125 /* 13156 */ "BZ_D\0"
9126 /* 13161 */ "SELNEZ_D\0"
9127 /* 13170 */ "BNZ_D\0"
9128 /* 13176 */ "SELEQZ_D\0"
9129 /* 13185 */ "LBE\0"
9130 /* 13189 */ "PSEUDO_PROBE\0"
9131 /* 13202 */ "SBE\0"
9132 /* 13206 */ "G_SSUBE\0"
9133 /* 13214 */ "G_USUBE\0"
9134 /* 13222 */ "G_FENCE\0"
9135 /* 13230 */ "ARITH_FENCE\0"
9136 /* 13242 */ "REG_SEQUENCE\0"
9137 /* 13255 */ "SCE\0"
9138 /* 13259 */ "G_SADDE\0"
9139 /* 13267 */ "G_UADDE\0"
9140 /* 13275 */ "G_GET_FPMODE\0"
9141 /* 13288 */ "G_RESET_FPMODE\0"
9142 /* 13303 */ "G_SET_FPMODE\0"
9143 /* 13316 */ "G_FMINNUM_IEEE\0"
9144 /* 13331 */ "G_FMAXNUM_IEEE\0"
9145 /* 13346 */ "CACHEE\0"
9146 /* 13353 */ "PREFE\0"
9147 /* 13359 */ "BGE\0"
9148 /* 13363 */ "SGE\0"
9149 /* 13367 */ "TGE\0"
9150 /* 13371 */ "CACHE\0"
9151 /* 13377 */ "LHE\0"
9152 /* 13381 */ "SHE\0"
9153 /* 13385 */ "SIGRIE\0"
9154 /* 13392 */ "G_VSCALE\0"
9155 /* 13401 */ "G_JUMP_TABLE\0"
9156 /* 13414 */ "BUNDLE\0"
9157 /* 13421 */ "LLE\0"
9158 /* 13425 */ "SLE\0"
9159 /* 13429 */ "LWLE\0"
9160 /* 13434 */ "SWLE\0"
9161 /* 13439 */ "BNE\0"
9162 /* 13443 */ "G_MEMCPY_INLINE\0"
9163 /* 13459 */ "SNE\0"
9164 /* 13463 */ "TNE\0"
9165 /* 13467 */ "LOCAL_ESCAPE\0"
9166 /* 13480 */ "DVPE\0"
9167 /* 13485 */ "EVPE\0"
9168 /* 13490 */ "G_STACKRESTORE\0"
9169 /* 13505 */ "G_INDEXED_STORE\0"
9170 /* 13521 */ "G_STORE\0"
9171 /* 13529 */ "LWRE\0"
9172 /* 13534 */ "SWRE\0"
9173 /* 13539 */ "G_BITREVERSE\0"
9174 /* 13552 */ "PAUSE\0"
9175 /* 13558 */ "DBG_VALUE\0"
9176 /* 13568 */ "G_GLOBAL_VALUE\0"
9177 /* 13583 */ "G_PTRAUTH_GLOBAL_VALUE\0"
9178 /* 13606 */ "CONVERGENCECTRL_GLUE\0"
9179 /* 13627 */ "G_STACKSAVE\0"
9180 /* 13639 */ "G_MEMMOVE\0"
9181 /* 13649 */ "LWE\0"
9182 /* 13653 */ "SWE\0"
9183 /* 13657 */ "G_FREEZE\0"
9184 /* 13666 */ "G_FCANONICALIZE\0"
9185 /* 13682 */ "LBuE\0"
9186 /* 13687 */ "LHuE\0"
9187 /* 13692 */ "BC1F\0"
9188 /* 13697 */ "G_CTLZ_ZERO_UNDEF\0"
9189 /* 13715 */ "G_CTTZ_ZERO_UNDEF\0"
9190 /* 13733 */ "G_IMPLICIT_DEF\0"
9191 /* 13748 */ "PREF\0"
9192 /* 13753 */ "DBG_INSTR_REF\0"
9193 /* 13767 */ "TLBINVF\0"
9194 /* 13775 */ "TLBGINVF\0"
9195 /* 13784 */ "G_FNEG\0"
9196 /* 13791 */ "TAILCALLHB64R6REG\0"
9197 /* 13809 */ "TAILCALL64R6REG\0"
9198 /* 13825 */ "TAILCALLHBR6REG\0"
9199 /* 13841 */ "TAILCALLR6REG\0"
9200 /* 13855 */ "EXTRACT_SUBREG\0"
9201 /* 13870 */ "INSERT_SUBREG\0"
9202 /* 13884 */ "TAILCALLREG\0"
9203 /* 13896 */ "G_SEXT_INREG\0"
9204 /* 13909 */ "SUBREG_TO_REG\0"
9205 /* 13923 */ "G_ATOMIC_CMPXCHG\0"
9206 /* 13940 */ "G_ATOMICRMW_XCHG\0"
9207 /* 13957 */ "G_FLOG\0"
9208 /* 13964 */ "G_VAARG\0"
9209 /* 13972 */ "PREALLOCATED_ARG\0"
9210 /* 13989 */ "CRC32H\0"
9211 /* 13996 */ "DSBH\0"
9212 /* 14001 */ "WSBH\0"
9213 /* 14006 */ "CRC32CH\0"
9214 /* 14014 */ "G_PREFETCH\0"
9215 /* 14025 */ "SEH\0"
9216 /* 14029 */ "G_SMULH\0"
9217 /* 14037 */ "G_UMULH\0"
9218 /* 14045 */ "G_FTANH\0"
9219 /* 14053 */ "G_FSINH\0"
9220 /* 14061 */ "SHRA_PH\0"
9221 /* 14069 */ "PRECRQ_QB_PH\0"
9222 /* 14082 */ "PRECR_QB_PH\0"
9223 /* 14094 */ "PRECRQU_S_QB_PH\0"
9224 /* 14110 */ "PseudoCMP_LE_PH\0"
9225 /* 14126 */ "SUBQH_PH\0"
9226 /* 14135 */ "ADDQH_PH\0"
9227 /* 14144 */ "PseudoPICK_PH\0"
9228 /* 14158 */ "SHLL_PH\0"
9229 /* 14166 */ "REPL_PH\0"
9230 /* 14174 */ "SHRL_PH\0"
9231 /* 14182 */ "PACKRL_PH\0"
9232 /* 14192 */ "MUL_PH\0"
9233 /* 14199 */ "SUBQ_PH\0"
9234 /* 14207 */ "ADDQ_PH\0"
9235 /* 14215 */ "PseudoCMP_EQ_PH\0"
9236 /* 14231 */ "SHRA_R_PH\0"
9237 /* 14241 */ "SUBQH_R_PH\0"
9238 /* 14252 */ "ADDQH_R_PH\0"
9239 /* 14263 */ "SHRAV_R_PH\0"
9240 /* 14274 */ "MULQ_RS_PH\0"
9241 /* 14285 */ "SHLL_S_PH\0"
9242 /* 14295 */ "MUL_S_PH\0"
9243 /* 14304 */ "SUBQ_S_PH\0"
9244 /* 14314 */ "ADDQ_S_PH\0"
9245 /* 14324 */ "MULQ_S_PH\0"
9246 /* 14334 */ "ABSQ_S_PH\0"
9247 /* 14344 */ "SUBU_S_PH\0"
9248 /* 14354 */ "ADDU_S_PH\0"
9249 /* 14364 */ "SHLLV_S_PH\0"
9250 /* 14375 */ "PseudoCMP_LT_PH\0"
9251 /* 14391 */ "SUBU_PH\0"
9252 /* 14399 */ "ADDU_PH\0"
9253 /* 14407 */ "SHRAV_PH\0"
9254 /* 14416 */ "SHLLV_PH\0"
9255 /* 14425 */ "REPLV_PH\0"
9256 /* 14434 */ "SHRLV_PH\0"
9257 /* 14443 */ "DPA_W_PH\0"
9258 /* 14452 */ "MULSA_W_PH\0"
9259 /* 14463 */ "DPAQX_SA_W_PH\0"
9260 /* 14477 */ "DPSQX_SA_W_PH\0"
9261 /* 14491 */ "DPS_W_PH\0"
9262 /* 14500 */ "DPAQ_S_W_PH\0"
9263 /* 14512 */ "MULSAQ_S_W_PH\0"
9264 /* 14526 */ "DPSQ_S_W_PH\0"
9265 /* 14538 */ "DPAQX_S_W_PH\0"
9266 /* 14551 */ "DPSQX_S_W_PH\0"
9267 /* 14564 */ "DPAX_W_PH\0"
9268 /* 14574 */ "DPSX_W_PH\0"
9269 /* 14584 */ "G_FCOSH\0"
9270 /* 14592 */ "DMUH\0"
9271 /* 14597 */ "SRA_H\0"
9272 /* 14603 */ "ADD_A_H\0"
9273 /* 14611 */ "MIN_A_H\0"
9274 /* 14619 */ "ADDS_A_H\0"
9275 /* 14628 */ "MAX_A_H\0"
9276 /* 14636 */ "NLOC_H\0"
9277 /* 14643 */ "NLZC_H\0"
9278 /* 14650 */ "SLD_H\0"
9279 /* 14656 */ "PCKOD_H\0"
9280 /* 14664 */ "ILVOD_H\0"
9281 /* 14672 */ "INSVE_H\0"
9282 /* 14680 */ "VSHF_H\0"
9283 /* 14687 */ "BNEG_H\0"
9284 /* 14694 */ "SRAI_H\0"
9285 /* 14701 */ "SLDI_H\0"
9286 /* 14708 */ "BNEGI_H\0"
9287 /* 14716 */ "SLLI_H\0"
9288 /* 14723 */ "SRLI_H\0"
9289 /* 14730 */ "BINSLI_H\0"
9290 /* 14739 */ "CEQI_H\0"
9291 /* 14746 */ "SRARI_H\0"
9292 /* 14754 */ "BCLRI_H\0"
9293 /* 14762 */ "SRLRI_H\0"
9294 /* 14770 */ "BINSRI_H\0"
9295 /* 14779 */ "SPLATI_H\0"
9296 /* 14788 */ "BSETI_H\0"
9297 /* 14796 */ "SUBVI_H\0"
9298 /* 14804 */ "ADDVI_H\0"
9299 /* 14812 */ "FILL_H\0"
9300 /* 14819 */ "SLL_H\0"
9301 /* 14825 */ "SRL_H\0"
9302 /* 14831 */ "BINSL_H\0"
9303 /* 14839 */ "ILVL_H\0"
9304 /* 14846 */ "FEXDO_H\0"
9305 /* 14854 */ "CEQ_H\0"
9306 /* 14860 */ "FTQ_H\0"
9307 /* 14866 */ "MSUB_Q_H\0"
9308 /* 14875 */ "MADD_Q_H\0"
9309 /* 14884 */ "MUL_Q_H\0"
9310 /* 14892 */ "MSUBR_Q_H\0"
9311 /* 14902 */ "MADDR_Q_H\0"
9312 /* 14912 */ "MULR_Q_H\0"
9313 /* 14921 */ "SRAR_H\0"
9314 /* 14928 */ "BCLR_H\0"
9315 /* 14935 */ "SRLR_H\0"
9316 /* 14942 */ "BINSR_H\0"
9317 /* 14950 */ "ILVR_H\0"
9318 /* 14957 */ "ASUB_S_H\0"
9319 /* 14966 */ "HSUB_S_H\0"
9320 /* 14975 */ "DPSUB_S_H\0"
9321 /* 14985 */ "HADD_S_H\0"
9322 /* 14994 */ "DPADD_S_H\0"
9323 /* 15004 */ "MOD_S_H\0"
9324 /* 15012 */ "CLE_S_H\0"
9325 /* 15020 */ "AVE_S_H\0"
9326 /* 15028 */ "CLEI_S_H\0"
9327 /* 15037 */ "MINI_S_H\0"
9328 /* 15046 */ "CLTI_S_H\0"
9329 /* 15055 */ "MAXI_S_H\0"
9330 /* 15064 */ "MIN_S_H\0"
9331 /* 15072 */ "DOTP_S_H\0"
9332 /* 15081 */ "AVER_S_H\0"
9333 /* 15090 */ "EXTR_S_H\0"
9334 /* 15099 */ "SUBS_S_H\0"
9335 /* 15108 */ "ADDS_S_H\0"
9336 /* 15117 */ "SAT_S_H\0"
9337 /* 15125 */ "CLT_S_H\0"
9338 /* 15133 */ "SUBSUU_S_H\0"
9339 /* 15144 */ "DIV_S_H\0"
9340 /* 15152 */ "EXTRV_S_H\0"
9341 /* 15162 */ "MAX_S_H\0"
9342 /* 15170 */ "COPY_S_H\0"
9343 /* 15179 */ "SPLAT_H\0"
9344 /* 15187 */ "BSET_H\0"
9345 /* 15194 */ "PCNT_H\0"
9346 /* 15201 */ "INSERT_H\0"
9347 /* 15210 */ "ST_H\0"
9348 /* 15215 */ "ASUB_U_H\0"
9349 /* 15224 */ "HSUB_U_H\0"
9350 /* 15233 */ "DPSUB_U_H\0"
9351 /* 15243 */ "HADD_U_H\0"
9352 /* 15252 */ "DPADD_U_H\0"
9353 /* 15262 */ "MOD_U_H\0"
9354 /* 15270 */ "CLE_U_H\0"
9355 /* 15278 */ "AVE_U_H\0"
9356 /* 15286 */ "CLEI_U_H\0"
9357 /* 15295 */ "MINI_U_H\0"
9358 /* 15304 */ "CLTI_U_H\0"
9359 /* 15313 */ "MAXI_U_H\0"
9360 /* 15322 */ "MIN_U_H\0"
9361 /* 15330 */ "DOTP_U_H\0"
9362 /* 15339 */ "AVER_U_H\0"
9363 /* 15348 */ "SUBS_U_H\0"
9364 /* 15357 */ "ADDS_U_H\0"
9365 /* 15366 */ "SUBSUS_U_H\0"
9366 /* 15377 */ "SAT_U_H\0"
9367 /* 15385 */ "CLT_U_H\0"
9368 /* 15393 */ "DIV_U_H\0"
9369 /* 15401 */ "MAX_U_H\0"
9370 /* 15409 */ "COPY_U_H\0"
9371 /* 15418 */ "MSUBV_H\0"
9372 /* 15426 */ "MADDV_H\0"
9373 /* 15434 */ "PCKEV_H\0"
9374 /* 15442 */ "ILVEV_H\0"
9375 /* 15450 */ "MULV_H\0"
9376 /* 15457 */ "BZ_H\0"
9377 /* 15462 */ "BNZ_H\0"
9378 /* 15468 */ "SYNCI\0"
9379 /* 15474 */ "DI\0"
9380 /* 15477 */ "TGEI\0"
9381 /* 15482 */ "TNEI\0"
9382 /* 15487 */ "DAHI\0"
9383 /* 15492 */ "PseudoMFHI\0"
9384 /* 15503 */ "PseudoMTLOHI\0"
9385 /* 15516 */ "DBG_PHI\0"
9386 /* 15524 */ "MFTHI\0"
9387 /* 15530 */ "MTHI\0"
9388 /* 15535 */ "MTTHI\0"
9389 /* 15541 */ "TEQI\0"
9390 /* 15546 */ "G_FPTOSI\0"
9391 /* 15555 */ "DATI\0"
9392 /* 15560 */ "TLTI\0"
9393 /* 15565 */ "DAUI\0"
9394 /* 15570 */ "G_FPTOUI\0"
9395 /* 15579 */ "GINVI\0"
9396 /* 15585 */ "TLBWI\0"
9397 /* 15591 */ "TLBGWI\0"
9398 /* 15598 */ "G_FPOWI\0"
9399 /* 15606 */ "MOVN_I64_I\0"
9400 /* 15617 */ "MOVZ_I64_I\0"
9401 /* 15628 */ "MOVF_I\0"
9402 /* 15635 */ "PseudoSELECTFP_F_I\0"
9403 /* 15654 */ "MOVN_I_I\0"
9404 /* 15663 */ "MOVZ_I_I\0"
9405 /* 15672 */ "PseudoD_SELECT_I\0"
9406 /* 15689 */ "PseudoSELECT_I\0"
9407 /* 15704 */ "MOVT_I\0"
9408 /* 15711 */ "PseudoSELECTFP_T_I\0"
9409 /* 15730 */ "J\0"
9410 /* 15732 */ "BREAK\0"
9411 /* 15738 */ "FORK\0"
9412 /* 15743 */ "G_PTRMASK\0"
9413 /* 15753 */ "BAL\0"
9414 /* 15757 */ "JAL\0"
9415 /* 15761 */ "NAL\0"
9416 /* 15765 */ "BGEZAL\0"
9417 /* 15772 */ "BLTZAL\0"
9418 /* 15779 */ "MULEU_S_PH_QBL\0"
9419 /* 15794 */ "PRECEU_PH_QBL\0"
9420 /* 15808 */ "PRECEQU_PH_QBL\0"
9421 /* 15823 */ "DPAU_H_QBL\0"
9422 /* 15834 */ "DPSU_H_QBL\0"
9423 /* 15845 */ "LDL\0"
9424 /* 15849 */ "SDL\0"
9425 /* 15853 */ "GC_LABEL\0"
9426 /* 15862 */ "DBG_LABEL\0"
9427 /* 15872 */ "EH_LABEL\0"
9428 /* 15881 */ "ANNOTATION_LABEL\0"
9429 /* 15898 */ "BGEL\0"
9430 /* 15903 */ "BLEL\0"
9431 /* 15908 */ "BNEL\0"
9432 /* 15913 */ "ICALL_BRANCH_FUNNEL\0"
9433 /* 15933 */ "BC1FL\0"
9434 /* 15939 */ "MAQ_SA_W_PHL\0"
9435 /* 15952 */ "PRECEQ_W_PHL\0"
9436 /* 15965 */ "MAQ_S_W_PHL\0"
9437 /* 15977 */ "MULEQ_S_W_PHL\0"
9438 /* 15991 */ "G_FSHL\0"
9439 /* 15998 */ "G_SHL\0"
9440 /* 16004 */ "G_FCEIL\0"
9441 /* 16012 */ "TAILCALL\0"
9442 /* 16021 */ "HYPCALL\0"
9443 /* 16029 */ "SYSCALL\0"
9444 /* 16037 */ "PATCHABLE_TAIL_CALL\0"
9445 /* 16057 */ "PATCHABLE_TYPED_EVENT_CALL\0"
9446 /* 16084 */ "PATCHABLE_EVENT_CALL\0"
9447 /* 16105 */ "FENTRY_CALL\0"
9448 /* 16117 */ "BGEZALL\0"
9449 /* 16125 */ "BLTZALL\0"
9450 /* 16133 */ "KILL\0"
9451 /* 16138 */ "DSLL\0"
9452 /* 16143 */ "G_CONSTANT_POOL\0"
9453 /* 16159 */ "DROL\0"
9454 /* 16164 */ "BEQL\0"
9455 /* 16169 */ "DSRL\0"
9456 /* 16174 */ "BC1TL\0"
9457 /* 16180 */ "BGTL\0"
9458 /* 16185 */ "BLTL\0"
9459 /* 16190 */ "G_ROTL\0"
9460 /* 16197 */ "BGEUL\0"
9461 /* 16203 */ "BLEUL\0"
9462 /* 16209 */ "DMUL\0"
9463 /* 16214 */ "G_VECREDUCE_FMUL\0"
9464 /* 16231 */ "G_FMUL\0"
9465 /* 16238 */ "G_VECREDUCE_SEQ_FMUL\0"
9466 /* 16259 */ "G_STRICT_FMUL\0"
9467 /* 16273 */ "G_VECREDUCE_MUL\0"
9468 /* 16289 */ "G_MUL\0"
9469 /* 16295 */ "BGTUL\0"
9470 /* 16301 */ "BLTUL\0"
9471 /* 16307 */ "LWL\0"
9472 /* 16311 */ "SWL\0"
9473 /* 16315 */ "BGEZL\0"
9474 /* 16321 */ "BLEZL\0"
9475 /* 16327 */ "BGTZL\0"
9476 /* 16333 */ "BLTZL\0"
9477 /* 16339 */ "PseudoCVT_D64_L\0"
9478 /* 16355 */ "PseudoCVT_S_L\0"
9479 /* 16369 */ "G_FREM\0"
9480 /* 16376 */ "G_STRICT_FREM\0"
9481 /* 16390 */ "G_SREM\0"
9482 /* 16397 */ "G_UREM\0"
9483 /* 16404 */ "G_SDIVREM\0"
9484 /* 16414 */ "G_UDIVREM\0"
9485 /* 16424 */ "MFGC0_MM\0"
9486 /* 16433 */ "MFHGC0_MM\0"
9487 /* 16443 */ "MTHGC0_MM\0"
9488 /* 16453 */ "MTGC0_MM\0"
9489 /* 16462 */ "CFC1_MM\0"
9490 /* 16470 */ "MFC1_MM\0"
9491 /* 16478 */ "CTC1_MM\0"
9492 /* 16486 */ "MTC1_MM\0"
9493 /* 16494 */ "LWC1_MM\0"
9494 /* 16502 */ "SWC1_MM\0"
9495 /* 16510 */ "LUXC1_MM\0"
9496 /* 16519 */ "SUXC1_MM\0"
9497 /* 16528 */ "LWXC1_MM\0"
9498 /* 16537 */ "SWXC1_MM\0"
9499 /* 16546 */ "MFHC1_D32_MM\0"
9500 /* 16559 */ "MTHC1_D32_MM\0"
9501 /* 16572 */ "FSUB_D32_MM\0"
9502 /* 16584 */ "NMSUB_D32_MM\0"
9503 /* 16597 */ "FADD_D32_MM\0"
9504 /* 16609 */ "NMADD_D32_MM\0"
9505 /* 16622 */ "C_NGE_D32_MM\0"
9506 /* 16635 */ "C_NGLE_D32_MM\0"
9507 /* 16649 */ "C_OLE_D32_MM\0"
9508 /* 16662 */ "C_ULE_D32_MM\0"
9509 /* 16675 */ "C_LE_D32_MM\0"
9510 /* 16687 */ "C_SF_D32_MM\0"
9511 /* 16699 */ "MOVF_D32_MM\0"
9512 /* 16711 */ "C_F_D32_MM\0"
9513 /* 16722 */ "FNEG_D32_MM\0"
9514 /* 16734 */ "MOVN_I_D32_MM\0"
9515 /* 16748 */ "MOVZ_I_D32_MM\0"
9516 /* 16762 */ "C_NGL_D32_MM\0"
9517 /* 16775 */ "FMUL_D32_MM\0"
9518 /* 16787 */ "C_UN_D32_MM\0"
9519 /* 16799 */ "RECIP_D32_MM\0"
9520 /* 16812 */ "FCMP_D32_MM\0"
9521 /* 16824 */ "C_SEQ_D32_MM\0"
9522 /* 16837 */ "C_UEQ_D32_MM\0"
9523 /* 16850 */ "C_EQ_D32_MM\0"
9524 /* 16862 */ "FABS_D32_MM\0"
9525 /* 16874 */ "CVT_S_D32_MM\0"
9526 /* 16887 */ "C_NGT_D32_MM\0"
9527 /* 16900 */ "C_OLT_D32_MM\0"
9528 /* 16913 */ "C_ULT_D32_MM\0"
9529 /* 16926 */ "C_LT_D32_MM\0"
9530 /* 16938 */ "FSQRT_D32_MM\0"
9531 /* 16951 */ "RSQRT_D32_MM\0"
9532 /* 16964 */ "MOVT_D32_MM\0"
9533 /* 16976 */ "FDIV_D32_MM\0"
9534 /* 16988 */ "FMOV_D32_MM\0"
9535 /* 17000 */ "CVT_W_D32_MM\0"
9536 /* 17013 */ "BPOSGE32_MM\0"
9537 /* 17025 */ "LWM32_MM\0"
9538 /* 17034 */ "SWM32_MM\0"
9539 /* 17043 */ "FCMP_S32_MM\0"
9540 /* 17055 */ "CFC2_MM\0"
9541 /* 17063 */ "CTC2_MM\0"
9542 /* 17071 */ "ADDIUR2_MM\0"
9543 /* 17082 */ "MFHC1_D64_MM\0"
9544 /* 17095 */ "MTHC1_D64_MM\0"
9545 /* 17108 */ "MTC1_D64_MM\0"
9546 /* 17120 */ "FSUB_D64_MM\0"
9547 /* 17132 */ "FADD_D64_MM\0"
9548 /* 17144 */ "C_NGE_D64_MM\0"
9549 /* 17157 */ "C_NGLE_D64_MM\0"
9550 /* 17171 */ "C_OLE_D64_MM\0"
9551 /* 17184 */ "C_ULE_D64_MM\0"
9552 /* 17197 */ "C_LE_D64_MM\0"
9553 /* 17209 */ "C_SF_D64_MM\0"
9554 /* 17221 */ "C_F_D64_MM\0"
9555 /* 17232 */ "FNEG_D64_MM\0"
9556 /* 17244 */ "C_NGL_D64_MM\0"
9557 /* 17257 */ "FMUL_D64_MM\0"
9558 /* 17269 */ "CVT_L_D64_MM\0"
9559 /* 17282 */ "C_UN_D64_MM\0"
9560 /* 17294 */ "RECIP_D64_MM\0"
9561 /* 17307 */ "C_SEQ_D64_MM\0"
9562 /* 17320 */ "C_UEQ_D64_MM\0"
9563 /* 17333 */ "C_EQ_D64_MM\0"
9564 /* 17345 */ "FABS_D64_MM\0"
9565 /* 17357 */ "CVT_S_D64_MM\0"
9566 /* 17370 */ "C_NGT_D64_MM\0"
9567 /* 17383 */ "C_OLT_D64_MM\0"
9568 /* 17396 */ "C_ULT_D64_MM\0"
9569 /* 17409 */ "C_LT_D64_MM\0"
9570 /* 17421 */ "FSQRT_D64_MM\0"
9571 /* 17434 */ "RSQRT_D64_MM\0"
9572 /* 17447 */ "FDIV_D64_MM\0"
9573 /* 17459 */ "FMOV_D64_MM\0"
9574 /* 17471 */ "CVT_W_D64_MM\0"
9575 /* 17484 */ "ADDIUS5_MM\0"
9576 /* 17495 */ "SB16_MM\0"
9577 /* 17503 */ "JRC16_MM\0"
9578 /* 17512 */ "AND16_MM\0"
9579 /* 17521 */ "MOVE16_MM\0"
9580 /* 17531 */ "SH16_MM\0"
9581 /* 17539 */ "ANDI16_MM\0"
9582 /* 17549 */ "MFHI16_MM\0"
9583 /* 17559 */ "LI16_MM\0"
9584 /* 17567 */ "BREAK16_MM\0"
9585 /* 17578 */ "SLL16_MM\0"
9586 /* 17587 */ "SRL16_MM\0"
9587 /* 17596 */ "LWM16_MM\0"
9588 /* 17605 */ "SWM16_MM\0"
9589 /* 17614 */ "MFLO16_MM\0"
9590 /* 17624 */ "SDBBP16_MM\0"
9591 /* 17635 */ "JR16_MM\0"
9592 /* 17643 */ "JALR16_MM\0"
9593 /* 17653 */ "XOR16_MM\0"
9594 /* 17662 */ "JALRS16_MM\0"
9595 /* 17673 */ "NOT16_MM\0"
9596 /* 17682 */ "LBU16_MM\0"
9597 /* 17691 */ "SUBU16_MM\0"
9598 /* 17701 */ "ADDU16_MM\0"
9599 /* 17711 */ "LHU16_MM\0"
9600 /* 17720 */ "LW16_MM\0"
9601 /* 17728 */ "SW16_MM\0"
9602 /* 17736 */ "BNEZ16_MM\0"
9603 /* 17746 */ "BEQZ16_MM\0"
9604 /* 17756 */ "PRECEU_PH_QBLA_MM\0"
9605 /* 17774 */ "PRECEQU_PH_QBLA_MM\0"
9606 /* 17793 */ "PRECEU_PH_QBRA_MM\0"
9607 /* 17811 */ "PRECEQU_PH_QBRA_MM\0"
9608 /* 17830 */ "SRA_MM\0"
9609 /* 17837 */ "SEB_MM\0"
9610 /* 17844 */ "EHB_MM\0"
9611 /* 17851 */ "LB_MM\0"
9612 /* 17857 */ "CMPGU_LE_QB_MM\0"
9613 /* 17872 */ "CMPU_LE_QB_MM\0"
9614 /* 17886 */ "PICK_QB_MM\0"
9615 /* 17897 */ "SHLL_QB_MM\0"
9616 /* 17908 */ "REPL_QB_MM\0"
9617 /* 17919 */ "SHRL_QB_MM\0"
9618 /* 17930 */ "CMPGU_EQ_QB_MM\0"
9619 /* 17945 */ "CMPU_EQ_QB_MM\0"
9620 /* 17959 */ "SUBU_S_QB_MM\0"
9621 /* 17972 */ "ADDU_S_QB_MM\0"
9622 /* 17985 */ "CMPGU_LT_QB_MM\0"
9623 /* 18000 */ "CMPU_LT_QB_MM\0"
9624 /* 18014 */ "SUBU_QB_MM\0"
9625 /* 18025 */ "ADDU_QB_MM\0"
9626 /* 18036 */ "SHLLV_QB_MM\0"
9627 /* 18048 */ "REPLV_QB_MM\0"
9628 /* 18060 */ "SHRLV_QB_MM\0"
9629 /* 18072 */ "RADDU_W_QB_MM\0"
9630 /* 18086 */ "SB_MM\0"
9631 /* 18092 */ "MODSUB_MM\0"
9632 /* 18102 */ "PseudoMSUB_MM\0"
9633 /* 18116 */ "SYNC_MM\0"
9634 /* 18124 */ "ADDIUPC_MM\0"
9635 /* 18135 */ "ADDSC_MM\0"
9636 /* 18144 */ "ADDWC_MM\0"
9637 /* 18153 */ "BNEZC_MM\0"
9638 /* 18162 */ "BEQZC_MM\0"
9639 /* 18171 */ "PseudoMADD_MM\0"
9640 /* 18185 */ "AND_MM\0"
9641 /* 18192 */ "LBE_MM\0"
9642 /* 18199 */ "SBE_MM\0"
9643 /* 18206 */ "SCE_MM\0"
9644 /* 18213 */ "CACHEE_MM\0"
9645 /* 18223 */ "PREFE_MM\0"
9646 /* 18232 */ "TGE_MM\0"
9647 /* 18239 */ "CACHE_MM\0"
9648 /* 18248 */ "LHE_MM\0"
9649 /* 18255 */ "SHE_MM\0"
9650 /* 18262 */ "LLE_MM\0"
9651 /* 18269 */ "LWLE_MM\0"
9652 /* 18277 */ "SWLE_MM\0"
9653 /* 18285 */ "BNE_MM\0"
9654 /* 18292 */ "TNE_MM\0"
9655 /* 18299 */ "LWRE_MM\0"
9656 /* 18307 */ "SWRE_MM\0"
9657 /* 18315 */ "PAUSE_MM\0"
9658 /* 18324 */ "LWE_MM\0"
9659 /* 18331 */ "SWE_MM\0"
9660 /* 18338 */ "LBuE_MM\0"
9661 /* 18346 */ "LHuE_MM\0"
9662 /* 18354 */ "BC1F_MM\0"
9663 /* 18362 */ "PREF_MM\0"
9664 /* 18370 */ "TLBGINVF_MM\0"
9665 /* 18382 */ "TAILCALLREG_MM\0"
9666 /* 18397 */ "WSBH_MM\0"
9667 /* 18405 */ "SEH_MM\0"
9668 /* 18412 */ "LH_MM\0"
9669 /* 18418 */ "SHRA_PH_MM\0"
9670 /* 18429 */ "PRECRQ_QB_PH_MM\0"
9671 /* 18445 */ "PRECRQU_S_QB_PH_MM\0"
9672 /* 18464 */ "CMP_LE_PH_MM\0"
9673 /* 18477 */ "PICK_PH_MM\0"
9674 /* 18488 */ "SHLL_PH_MM\0"
9675 /* 18499 */ "REPL_PH_MM\0"
9676 /* 18510 */ "PACKRL_PH_MM\0"
9677 /* 18523 */ "SUBQ_PH_MM\0"
9678 /* 18534 */ "ADDQ_PH_MM\0"
9679 /* 18545 */ "CMP_EQ_PH_MM\0"
9680 /* 18558 */ "SHRA_R_PH_MM\0"
9681 /* 18571 */ "SHRAV_R_PH_MM\0"
9682 /* 18585 */ "MULQ_RS_PH_MM\0"
9683 /* 18599 */ "SHLL_S_PH_MM\0"
9684 /* 18612 */ "SUBQ_S_PH_MM\0"
9685 /* 18625 */ "ADDQ_S_PH_MM\0"
9686 /* 18638 */ "ABSQ_S_PH_MM\0"
9687 /* 18651 */ "SHLLV_S_PH_MM\0"
9688 /* 18665 */ "CMP_LT_PH_MM\0"
9689 /* 18678 */ "SHRAV_PH_MM\0"
9690 /* 18690 */ "SHLLV_PH_MM\0"
9691 /* 18702 */ "REPLV_PH_MM\0"
9692 /* 18714 */ "DPAQ_S_W_PH_MM\0"
9693 /* 18729 */ "MULSAQ_S_W_PH_MM\0"
9694 /* 18746 */ "DPSQ_S_W_PH_MM\0"
9695 /* 18761 */ "SH_MM\0"
9696 /* 18767 */ "EXTR_S_H_MM\0"
9697 /* 18779 */ "EXTRV_S_H_MM\0"
9698 /* 18792 */ "SYNCI_MM\0"
9699 /* 18801 */ "DI_MM\0"
9700 /* 18807 */ "TGEI_MM\0"
9701 /* 18815 */ "TNEI_MM\0"
9702 /* 18823 */ "PseudoMFHI_MM\0"
9703 /* 18837 */ "PseudoMTLOHI_MM\0"
9704 /* 18853 */ "MTHI_MM\0"
9705 /* 18861 */ "TEQI_MM\0"
9706 /* 18869 */ "TLTI_MM\0"
9707 /* 18877 */ "TLBWI_MM\0"
9708 /* 18886 */ "TLBGWI_MM\0"
9709 /* 18896 */ "MOVF_I_MM\0"
9710 /* 18906 */ "MOVN_I_MM\0"
9711 /* 18916 */ "MOVT_I_MM\0"
9712 /* 18926 */ "MOVZ_I_MM\0"
9713 /* 18936 */ "J_MM\0"
9714 /* 18941 */ "BREAK_MM\0"
9715 /* 18950 */ "JAL_MM\0"
9716 /* 18957 */ "BGEZAL_MM\0"
9717 /* 18967 */ "BLTZAL_MM\0"
9718 /* 18977 */ "MULEU_S_PH_QBL_MM\0"
9719 /* 18995 */ "PRECEU_PH_QBL_MM\0"
9720 /* 19012 */ "PRECEQU_PH_QBL_MM\0"
9721 /* 19030 */ "DPAU_H_QBL_MM\0"
9722 /* 19044 */ "DPSU_H_QBL_MM\0"
9723 /* 19058 */ "MAQ_SA_W_PHL_MM\0"
9724 /* 19074 */ "PRECEQ_W_PHL_MM\0"
9725 /* 19090 */ "MAQ_S_W_PHL_MM\0"
9726 /* 19105 */ "MULEQ_S_W_PHL_MM\0"
9727 /* 19122 */ "TAILCALL_MM\0"
9728 /* 19134 */ "HYPCALL_MM\0"
9729 /* 19145 */ "SYSCALL_MM\0"
9730 /* 19156 */ "SLL_MM\0"
9731 /* 19163 */ "SRL_MM\0"
9732 /* 19170 */ "MUL_MM\0"
9733 /* 19177 */ "LWL_MM\0"
9734 /* 19184 */ "SWL_MM\0"
9735 /* 19191 */ "LWM_MM\0"
9736 /* 19198 */ "SWM_MM\0"
9737 /* 19205 */ "CLO_MM\0"
9738 /* 19212 */ "PseudoMFLO_MM\0"
9739 /* 19226 */ "SHILO_MM\0"
9740 /* 19235 */ "MTLO_MM\0"
9741 /* 19243 */ "TRAP_MM\0"
9742 /* 19251 */ "SDBBP_MM\0"
9743 /* 19260 */ "TLBP_MM\0"
9744 /* 19268 */ "EXTPDP_MM\0"
9745 /* 19278 */ "MOVEP_MM\0"
9746 /* 19287 */ "TLBGP_MM\0"
9747 /* 19296 */ "LWGP_MM\0"
9748 /* 19304 */ "MTHLIP_MM\0"
9749 /* 19314 */ "SSNOP_MM\0"
9750 /* 19323 */ "ADDIUR1SP_MM\0"
9751 /* 19336 */ "RDDSP_MM\0"
9752 /* 19345 */ "WRDSP_MM\0"
9753 /* 19354 */ "LWDSP_MM\0"
9754 /* 19363 */ "SWDSP_MM\0"
9755 /* 19372 */ "MSUB_DSP_MM\0"
9756 /* 19384 */ "MADD_DSP_MM\0"
9757 /* 19396 */ "MFHI_DSP_MM\0"
9758 /* 19408 */ "MTHI_DSP_MM\0"
9759 /* 19420 */ "MFLO_DSP_MM\0"
9760 /* 19432 */ "MTLO_DSP_MM\0"
9761 /* 19444 */ "MULT_DSP_MM\0"
9762 /* 19456 */ "MSUBU_DSP_MM\0"
9763 /* 19469 */ "MADDU_DSP_MM\0"
9764 /* 19482 */ "MULTU_DSP_MM\0"
9765 /* 19495 */ "ADDIUSP_MM\0"
9766 /* 19506 */ "LWSP_MM\0"
9767 /* 19514 */ "SWSP_MM\0"
9768 /* 19522 */ "EXTP_MM\0"
9769 /* 19530 */ "LWP_MM\0"
9770 /* 19537 */ "SWP_MM\0"
9771 /* 19544 */ "BEQ_MM\0"
9772 /* 19551 */ "TEQ_MM\0"
9773 /* 19558 */ "TLBR_MM\0"
9774 /* 19566 */ "MULEU_S_PH_QBR_MM\0"
9775 /* 19584 */ "PRECEU_PH_QBR_MM\0"
9776 /* 19601 */ "PRECEQU_PH_QBR_MM\0"
9777 /* 19619 */ "DPAU_H_QBR_MM\0"
9778 /* 19633 */ "DPSU_H_QBR_MM\0"
9779 /* 19647 */ "BAL_BR_MM\0"
9780 /* 19657 */ "TLBGR_MM\0"
9781 /* 19666 */ "MAQ_SA_W_PHR_MM\0"
9782 /* 19682 */ "PRECEQ_W_PHR_MM\0"
9783 /* 19698 */ "MAQ_S_W_PHR_MM\0"
9784 /* 19713 */ "MULEQ_S_W_PHR_MM\0"
9785 /* 19730 */ "JR_MM\0"
9786 /* 19736 */ "JALR_MM\0"
9787 /* 19744 */ "NOR_MM\0"
9788 /* 19751 */ "XOR_MM\0"
9789 /* 19758 */ "ROTR_MM\0"
9790 /* 19766 */ "TLBWR_MM\0"
9791 /* 19775 */ "TLBGWR_MM\0"
9792 /* 19785 */ "RDHWR_MM\0"
9793 /* 19794 */ "LWR_MM\0"
9794 /* 19801 */ "SWR_MM\0"
9795 /* 19808 */ "JALS_MM\0"
9796 /* 19816 */ "BGEZALS_MM\0"
9797 /* 19827 */ "BLTZALS_MM\0"
9798 /* 19838 */ "INS_MM\0"
9799 /* 19845 */ "JALRS_MM\0"
9800 /* 19854 */ "LWXS_MM\0"
9801 /* 19862 */ "CVT_D32_S_MM\0"
9802 /* 19875 */ "CVT_D64_S_MM\0"
9803 /* 19888 */ "FSUB_S_MM\0"
9804 /* 19898 */ "NMSUB_S_MM\0"
9805 /* 19909 */ "FADD_S_MM\0"
9806 /* 19919 */ "NMADD_S_MM\0"
9807 /* 19930 */ "C_NGE_S_MM\0"
9808 /* 19941 */ "C_NGLE_S_MM\0"
9809 /* 19953 */ "C_OLE_S_MM\0"
9810 /* 19964 */ "C_ULE_S_MM\0"
9811 /* 19975 */ "C_LE_S_MM\0"
9812 /* 19985 */ "C_SF_S_MM\0"
9813 /* 19995 */ "MOVF_S_MM\0"
9814 /* 20005 */ "C_F_S_MM\0"
9815 /* 20014 */ "FNEG_S_MM\0"
9816 /* 20024 */ "MOVN_I_S_MM\0"
9817 /* 20036 */ "MOVZ_I_S_MM\0"
9818 /* 20048 */ "C_NGL_S_MM\0"
9819 /* 20059 */ "FMUL_S_MM\0"
9820 /* 20069 */ "CVT_L_S_MM\0"
9821 /* 20080 */ "C_UN_S_MM\0"
9822 /* 20090 */ "RECIP_S_MM\0"
9823 /* 20101 */ "C_SEQ_S_MM\0"
9824 /* 20112 */ "C_UEQ_S_MM\0"
9825 /* 20123 */ "C_EQ_S_MM\0"
9826 /* 20133 */ "FABS_S_MM\0"
9827 /* 20143 */ "C_NGT_S_MM\0"
9828 /* 20154 */ "C_OLT_S_MM\0"
9829 /* 20165 */ "C_ULT_S_MM\0"
9830 /* 20176 */ "C_LT_S_MM\0"
9831 /* 20186 */ "FSQRT_S_MM\0"
9832 /* 20197 */ "RSQRT_S_MM\0"
9833 /* 20208 */ "MOVT_S_MM\0"
9834 /* 20218 */ "FDIV_S_MM\0"
9835 /* 20228 */ "FMOV_S_MM\0"
9836 /* 20238 */ "TRUNC_W_S_MM\0"
9837 /* 20251 */ "ROUND_W_S_MM\0"
9838 /* 20264 */ "CEIL_W_S_MM\0"
9839 /* 20276 */ "FLOOR_W_S_MM\0"
9840 /* 20289 */ "CVT_W_S_MM\0"
9841 /* 20300 */ "BC1T_MM\0"
9842 /* 20308 */ "DERET_MM\0"
9843 /* 20317 */ "WAIT_MM\0"
9844 /* 20325 */ "SLT_MM\0"
9845 /* 20332 */ "TLT_MM\0"
9846 /* 20339 */ "PseudoMULT_MM\0"
9847 /* 20353 */ "EXT_MM\0"
9848 /* 20360 */ "PseudoMSUBU_MM\0"
9849 /* 20375 */ "PseudoMADDU_MM\0"
9850 /* 20390 */ "TGEU_MM\0"
9851 /* 20398 */ "TGEIU_MM\0"
9852 /* 20407 */ "TLTIU_MM\0"
9853 /* 20416 */ "TLTU_MM\0"
9854 /* 20424 */ "LWU_MM\0"
9855 /* 20431 */ "SRAV_MM\0"
9856 /* 20439 */ "BITREV_MM\0"
9857 /* 20449 */ "SDIV_MM\0"
9858 /* 20457 */ "UDIV_MM\0"
9859 /* 20465 */ "SLLV_MM\0"
9860 /* 20473 */ "SRLV_MM\0"
9861 /* 20481 */ "TLBGINV_MM\0"
9862 /* 20492 */ "SHILOV_MM\0"
9863 /* 20502 */ "EXTPDPV_MM\0"
9864 /* 20513 */ "EXTPV_MM\0"
9865 /* 20522 */ "ROTRV_MM\0"
9866 /* 20531 */ "INSV_MM\0"
9867 /* 20539 */ "LW_MM\0"
9868 /* 20545 */ "SW_MM\0"
9869 /* 20551 */ "CVT_D32_W_MM\0"
9870 /* 20564 */ "CVT_D64_W_MM\0"
9871 /* 20577 */ "TRUNC_W_MM\0"
9872 /* 20588 */ "ROUND_W_MM\0"
9873 /* 20599 */ "PRECRQ_PH_W_MM\0"
9874 /* 20614 */ "PRECRQ_RS_PH_W_MM\0"
9875 /* 20632 */ "CEIL_W_MM\0"
9876 /* 20642 */ "DPAQ_SA_L_W_MM\0"
9877 /* 20657 */ "DPSQ_SA_L_W_MM\0"
9878 /* 20672 */ "FLOOR_W_MM\0"
9879 /* 20683 */ "EXTR_W_MM\0"
9880 /* 20693 */ "SHRA_R_W_MM\0"
9881 /* 20705 */ "EXTR_R_W_MM\0"
9882 /* 20717 */ "SHRAV_R_W_MM\0"
9883 /* 20730 */ "EXTRV_R_W_MM\0"
9884 /* 20743 */ "EXTR_RS_W_MM\0"
9885 /* 20756 */ "EXTRV_RS_W_MM\0"
9886 /* 20770 */ "SHLL_S_W_MM\0"
9887 /* 20782 */ "SUBQ_S_W_MM\0"
9888 /* 20794 */ "ADDQ_S_W_MM\0"
9889 /* 20806 */ "ABSQ_S_W_MM\0"
9890 /* 20818 */ "CVT_S_W_MM\0"
9891 /* 20829 */ "SHLLV_S_W_MM\0"
9892 /* 20842 */ "EXTRV_W_MM\0"
9893 /* 20853 */ "PREFX_MM\0"
9894 /* 20862 */ "LHX_MM\0"
9895 /* 20869 */ "JALX_MM\0"
9896 /* 20877 */ "LBUX_MM\0"
9897 /* 20885 */ "LWX_MM\0"
9898 /* 20892 */ "BGEZ_MM\0"
9899 /* 20900 */ "BLEZ_MM\0"
9900 /* 20908 */ "CLZ_MM\0"
9901 /* 20915 */ "BGTZ_MM\0"
9902 /* 20923 */ "BLTZ_MM\0"
9903 /* 20931 */ "PseudoIndirectBranch_MM\0"
9904 /* 20955 */ "ADDi_MM\0"
9905 /* 20963 */ "ANDi_MM\0"
9906 /* 20971 */ "XORi_MM\0"
9907 /* 20979 */ "SLTi_MM\0"
9908 /* 20987 */ "LUi_MM\0"
9909 /* 20994 */ "LBu_MM\0"
9910 /* 21001 */ "SUBu_MM\0"
9911 /* 21009 */ "ADDu_MM\0"
9912 /* 21017 */ "LHu_MM\0"
9913 /* 21024 */ "SLTu_MM\0"
9914 /* 21032 */ "PseudoMULTu_MM\0"
9915 /* 21047 */ "LEA_ADDiu_MM\0"
9916 /* 21060 */ "SLTiu_MM\0"
9917 /* 21069 */ "INLINEASM\0"
9918 /* 21079 */ "DINSM\0"
9919 /* 21085 */ "DEXTM\0"
9920 /* 21091 */ "G_VECREDUCE_FMINIMUM\0"
9921 /* 21112 */ "G_FMINIMUM\0"
9922 /* 21123 */ "G_VECREDUCE_FMAXIMUM\0"
9923 /* 21144 */ "G_FMAXIMUM\0"
9924 /* 21155 */ "G_FMINNUM\0"
9925 /* 21165 */ "G_FMAXNUM\0"
9926 /* 21175 */ "G_FATAN\0"
9927 /* 21183 */ "G_FTAN\0"
9928 /* 21190 */ "G_INTRINSIC_ROUNDEVEN\0"
9929 /* 21212 */ "BALIGN\0"
9930 /* 21219 */ "DALIGN\0"
9931 /* 21226 */ "G_ASSERT_ALIGN\0"
9932 /* 21241 */ "G_FCOPYSIGN\0"
9933 /* 21253 */ "G_VECREDUCE_FMIN\0"
9934 /* 21270 */ "G_ATOMICRMW_FMIN\0"
9935 /* 21287 */ "G_VECREDUCE_SMIN\0"
9936 /* 21304 */ "G_SMIN\0"
9937 /* 21311 */ "G_VECREDUCE_UMIN\0"
9938 /* 21328 */ "G_UMIN\0"
9939 /* 21335 */ "G_ATOMICRMW_UMIN\0"
9940 /* 21352 */ "G_ATOMICRMW_MIN\0"
9941 /* 21368 */ "G_FASIN\0"
9942 /* 21376 */ "G_FSIN\0"
9943 /* 21383 */ "DMFC2_OCTEON\0"
9944 /* 21396 */ "DMTC2_OCTEON\0"
9945 /* 21409 */ "CFI_INSTRUCTION\0"
9946 /* 21425 */ "ADJCALLSTACKDOWN\0"
9947 /* 21442 */ "G_SSUBO\0"
9948 /* 21450 */ "G_USUBO\0"
9949 /* 21458 */ "G_SADDO\0"
9950 /* 21466 */ "G_UADDO\0"
9951 /* 21474 */ "FEXP2_D_1_PSEUDO\0"
9952 /* 21491 */ "FEXP2_W_1_PSEUDO\0"
9953 /* 21508 */ "BPOSGE32_PSEUDO\0"
9954 /* 21524 */ "INSERT_B_VIDX64_PSEUDO\0"
9955 /* 21547 */ "INSERT_FD_VIDX64_PSEUDO\0"
9956 /* 21571 */ "INSERT_D_VIDX64_PSEUDO\0"
9957 /* 21594 */ "INSERT_H_VIDX64_PSEUDO\0"
9958 /* 21617 */ "INSERT_FW_VIDX64_PSEUDO\0"
9959 /* 21641 */ "INSERT_W_VIDX64_PSEUDO\0"
9960 /* 21664 */ "SNZ_B_PSEUDO\0"
9961 /* 21677 */ "SZ_B_PSEUDO\0"
9962 /* 21689 */ "BSEL_FD_PSEUDO\0"
9963 /* 21704 */ "FILL_FD_PSEUDO\0"
9964 /* 21719 */ "INSERT_FD_PSEUDO\0"
9965 /* 21736 */ "COPY_FD_PSEUDO\0"
9966 /* 21751 */ "MSA_FP_EXTEND_D_PSEUDO\0"
9967 /* 21774 */ "MSA_FP_ROUND_D_PSEUDO\0"
9968 /* 21796 */ "BSEL_D_PSEUDO\0"
9969 /* 21810 */ "AND_V_D_PSEUDO\0"
9970 /* 21825 */ "NOR_V_D_PSEUDO\0"
9971 /* 21840 */ "XOR_V_D_PSEUDO\0"
9972 /* 21855 */ "SNZ_D_PSEUDO\0"
9973 /* 21868 */ "SZ_D_PSEUDO\0"
9974 /* 21880 */ "BSEL_H_PSEUDO\0"
9975 /* 21894 */ "AND_V_H_PSEUDO\0"
9976 /* 21909 */ "NOR_V_H_PSEUDO\0"
9977 /* 21924 */ "XOR_V_H_PSEUDO\0"
9978 /* 21939 */ "SNZ_H_PSEUDO\0"
9979 /* 21952 */ "SZ_H_PSEUDO\0"
9980 /* 21964 */ "SNZ_V_PSEUDO\0"
9981 /* 21977 */ "SZ_V_PSEUDO\0"
9982 /* 21989 */ "BSEL_FW_PSEUDO\0"
9983 /* 22004 */ "FILL_FW_PSEUDO\0"
9984 /* 22019 */ "INSERT_FW_PSEUDO\0"
9985 /* 22036 */ "COPY_FW_PSEUDO\0"
9986 /* 22051 */ "MSA_FP_EXTEND_W_PSEUDO\0"
9987 /* 22074 */ "MSA_FP_ROUND_W_PSEUDO\0"
9988 /* 22096 */ "BSEL_W_PSEUDO\0"
9989 /* 22110 */ "AND_V_W_PSEUDO\0"
9990 /* 22125 */ "NOR_V_W_PSEUDO\0"
9991 /* 22140 */ "XOR_V_W_PSEUDO\0"
9992 /* 22155 */ "SNZ_W_PSEUDO\0"
9993 /* 22168 */ "SZ_W_PSEUDO\0"
9994 /* 22180 */ "INSERT_B_VIDX_PSEUDO\0"
9995 /* 22201 */ "INSERT_FD_VIDX_PSEUDO\0"
9996 /* 22223 */ "INSERT_D_VIDX_PSEUDO\0"
9997 /* 22244 */ "INSERT_H_VIDX_PSEUDO\0"
9998 /* 22265 */ "INSERT_FW_VIDX_PSEUDO\0"
9999 /* 22287 */ "INSERT_W_VIDX_PSEUDO\0"
10000 /* 22308 */ "JUMP_TABLE_DEBUG_INFO\0"
10001 /* 22330 */ "DCLO\0"
10002 /* 22335 */ "PseudoMFLO\0"
10003 /* 22346 */ "SHILO\0"
10004 /* 22352 */ "MFTLO\0"
10005 /* 22358 */ "MTLO\0"
10006 /* 22363 */ "MTTLO\0"
10007 /* 22369 */ "G_SMULO\0"
10008 /* 22377 */ "G_UMULO\0"
10009 /* 22385 */ "G_BZERO\0"
10010 /* 22393 */ "STACKMAP\0"
10011 /* 22402 */ "G_DEBUGTRAP\0"
10012 /* 22414 */ "G_UBSANTRAP\0"
10013 /* 22426 */ "G_TRAP\0"
10014 /* 22433 */ "G_ATOMICRMW_UDEC_WRAP\0"
10015 /* 22455 */ "G_ATOMICRMW_UINC_WRAP\0"
10016 /* 22477 */ "G_BSWAP\0"
10017 /* 22485 */ "DBITSWAP\0"
10018 /* 22494 */ "SDBBP\0"
10019 /* 22500 */ "TLBP\0"
10020 /* 22505 */ "EXTPDP\0"
10021 /* 22512 */ "G_SITOFP\0"
10022 /* 22521 */ "G_UITOFP\0"
10023 /* 22530 */ "TLBGP\0"
10024 /* 22536 */ "MTHLIP\0"
10025 /* 22543 */ "G_FCMP\0"
10026 /* 22550 */ "G_ICMP\0"
10027 /* 22557 */ "G_SCMP\0"
10028 /* 22564 */ "G_UCMP\0"
10029 /* 22571 */ "SSNOP\0"
10030 /* 22577 */ "CONVERGENCECTRL_LOOP\0"
10031 /* 22598 */ "DPOP\0"
10032 /* 22603 */ "G_CTPOP\0"
10033 /* 22611 */ "PATCHABLE_OP\0"
10034 /* 22624 */ "FAULTING_OP\0"
10035 /* 22636 */ "LOAD_ACC64DSP\0"
10036 /* 22650 */ "STORE_ACC64DSP\0"
10037 /* 22665 */ "RDDSP\0"
10038 /* 22671 */ "WRDSP\0"
10039 /* 22677 */ "MFTDSP\0"
10040 /* 22684 */ "MTTDSP\0"
10041 /* 22691 */ "LWDSP\0"
10042 /* 22697 */ "SWDSP\0"
10043 /* 22703 */ "MSUB_DSP\0"
10044 /* 22712 */ "MADD_DSP\0"
10045 /* 22721 */ "LOAD_CCOND_DSP\0"
10046 /* 22736 */ "STORE_CCOND_DSP\0"
10047 /* 22752 */ "MFHI_DSP\0"
10048 /* 22761 */ "PseudoMTLOHI_DSP\0"
10049 /* 22778 */ "MTHI_DSP\0"
10050 /* 22787 */ "MFLO_DSP\0"
10051 /* 22796 */ "MTLO_DSP\0"
10052 /* 22805 */ "MULT_DSP\0"
10053 /* 22814 */ "MSUBU_DSP\0"
10054 /* 22824 */ "MADDU_DSP\0"
10055 /* 22834 */ "MULTU_DSP\0"
10056 /* 22844 */ "JRADDIUSP\0"
10057 /* 22854 */ "EXTP\0"
10058 /* 22859 */ "ADJCALLSTACKUP\0"
10059 /* 22874 */ "PREALLOCATED_SETUP\0"
10060 /* 22893 */ "DVP\0"
10061 /* 22897 */ "EVP\0"
10062 /* 22901 */ "G_FLDEXP\0"
10063 /* 22910 */ "G_STRICT_FLDEXP\0"
10064 /* 22926 */ "G_FEXP\0"
10065 /* 22933 */ "G_FFREXP\0"
10066 /* 22942 */ "BEQ\0"
10067 /* 22946 */ "SEQ\0"
10068 /* 22950 */ "TEQ\0"
10069 /* 22954 */ "TLBR\0"
10070 /* 22959 */ "MULEU_S_PH_QBR\0"
10071 /* 22974 */ "PRECEU_PH_QBR\0"
10072 /* 22988 */ "PRECEQU_PH_QBR\0"
10073 /* 23003 */ "DPAU_H_QBR\0"
10074 /* 23014 */ "DPSU_H_QBR\0"
10075 /* 23025 */ "G_BR\0"
10076 /* 23030 */ "BAL_BR\0"
10077 /* 23037 */ "INLINEASM_BR\0"
10078 /* 23050 */ "G_BLOCK_ADDR\0"
10079 /* 23063 */ "LDR\0"
10080 /* 23067 */ "SDR\0"
10081 /* 23071 */ "MEMBARRIER\0"
10082 /* 23082 */ "G_CONSTANT_FOLD_BARRIER\0"
10083 /* 23106 */ "PATCHABLE_FUNCTION_ENTER\0"
10084 /* 23131 */ "G_READCYCLECOUNTER\0"
10085 /* 23150 */ "G_READSTEADYCOUNTER\0"
10086 /* 23170 */ "G_READ_REGISTER\0"
10087 /* 23186 */ "G_WRITE_REGISTER\0"
10088 /* 23203 */ "TLBGR\0"
10089 /* 23209 */ "LoadImmDoubleFGR\0"
10090 /* 23226 */ "LoadImmSingleFGR\0"
10091 /* 23243 */ "MAQ_SA_W_PHR\0"
10092 /* 23256 */ "PRECEQ_W_PHR\0"
10093 /* 23269 */ "MAQ_S_W_PHR\0"
10094 /* 23281 */ "MULEQ_S_W_PHR\0"
10095 /* 23295 */ "G_ASHR\0"
10096 /* 23302 */ "G_FSHR\0"
10097 /* 23309 */ "G_LSHR\0"
10098 /* 23316 */ "JR\0"
10099 /* 23319 */ "JALR\0"
10100 /* 23324 */ "CONVERGENCECTRL_ANCHOR\0"
10101 /* 23347 */ "NOR\0"
10102 /* 23351 */ "G_FFLOOR\0"
10103 /* 23360 */ "DROR\0"
10104 /* 23365 */ "G_EXTRACT_SUBVECTOR\0"
10105 /* 23385 */ "G_INSERT_SUBVECTOR\0"
10106 /* 23404 */ "G_BUILD_VECTOR\0"
10107 /* 23419 */ "G_SHUFFLE_VECTOR\0"
10108 /* 23436 */ "G_SPLAT_VECTOR\0"
10109 /* 23451 */ "G_VECREDUCE_XOR\0"
10110 /* 23467 */ "G_XOR\0"
10111 /* 23473 */ "G_ATOMICRMW_XOR\0"
10112 /* 23489 */ "G_VECREDUCE_OR\0"
10113 /* 23504 */ "G_OR\0"
10114 /* 23509 */ "G_ATOMICRMW_OR\0"
10115 /* 23524 */ "MFTGPR\0"
10116 /* 23531 */ "MTTGPR\0"
10117 /* 23538 */ "LoadImmDoubleGPR\0"
10118 /* 23555 */ "LoadImmSingleGPR\0"
10119 /* 23572 */ "MFTR\0"
10120 /* 23577 */ "DROTR\0"
10121 /* 23583 */ "G_ROTR\0"
10122 /* 23590 */ "G_INTTOPTR\0"
10123 /* 23601 */ "MTTR\0"
10124 /* 23606 */ "TLBWR\0"
10125 /* 23612 */ "TLBGWR\0"
10126 /* 23619 */ "RDHWR\0"
10127 /* 23625 */ "LWR\0"
10128 /* 23629 */ "SWR\0"
10129 /* 23633 */ "G_FABS\0"
10130 /* 23640 */ "G_ABS\0"
10131 /* 23646 */ "G_UNMERGE_VALUES\0"
10132 /* 23663 */ "G_MERGE_VALUES\0"
10133 /* 23678 */ "CINS\0"
10134 /* 23683 */ "DINS\0"
10135 /* 23688 */ "G_FACOS\0"
10136 /* 23696 */ "G_FCOS\0"
10137 /* 23703 */ "G_CONCAT_VECTORS\0"
10138 /* 23720 */ "COPY_TO_REGCLASS\0"
10139 /* 23737 */ "G_IS_FPCLASS\0"
10140 /* 23750 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
10141 /* 23780 */ "G_VECTOR_COMPRESS\0"
10142 /* 23798 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
10143 /* 23825 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
10144 /* 23863 */ "EXTS\0"
10145 /* 23868 */ "CVT_D32_S\0"
10146 /* 23878 */ "CVT_D64_S\0"
10147 /* 23888 */ "MOVN_I64_S\0"
10148 /* 23899 */ "MOVZ_I64_S\0"
10149 /* 23910 */ "MINA_S\0"
10150 /* 23917 */ "MAXA_S\0"
10151 /* 23924 */ "FSUB_S\0"
10152 /* 23931 */ "NMSUB_S\0"
10153 /* 23939 */ "FADD_S\0"
10154 /* 23946 */ "NMADD_S\0"
10155 /* 23954 */ "C_NGE_S\0"
10156 /* 23962 */ "C_NGLE_S\0"
10157 /* 23971 */ "C_OLE_S\0"
10158 /* 23979 */ "CMP_SLE_S\0"
10159 /* 23989 */ "CMP_SULE_S\0"
10160 /* 24000 */ "C_ULE_S\0"
10161 /* 24008 */ "CMP_ULE_S\0"
10162 /* 24018 */ "C_LE_S\0"
10163 /* 24025 */ "CMP_LE_S\0"
10164 /* 24034 */ "CMP_SAF_S\0"
10165 /* 24044 */ "MSUBF_S\0"
10166 /* 24052 */ "MADDF_S\0"
10167 /* 24060 */ "C_SF_S\0"
10168 /* 24067 */ "MOVF_S\0"
10169 /* 24074 */ "C_F_S\0"
10170 /* 24080 */ "PseudoSELECTFP_F_S\0"
10171 /* 24099 */ "CMP_F_S\0"
10172 /* 24107 */ "FNEG_S\0"
10173 /* 24114 */ "MOVN_I_S\0"
10174 /* 24123 */ "MOVZ_I_S\0"
10175 /* 24132 */ "SEL_S\0"
10176 /* 24138 */ "C_NGL_S\0"
10177 /* 24146 */ "FMUL_S\0"
10178 /* 24153 */ "TRUNC_L_S\0"
10179 /* 24163 */ "ROUND_L_S\0"
10180 /* 24173 */ "CEIL_L_S\0"
10181 /* 24182 */ "FLOOR_L_S\0"
10182 /* 24192 */ "CVT_L_S\0"
10183 /* 24200 */ "MIN_S\0"
10184 /* 24206 */ "CMP_SUN_S\0"
10185 /* 24216 */ "C_UN_S\0"
10186 /* 24223 */ "CMP_UN_S\0"
10187 /* 24232 */ "RECIP_S\0"
10188 /* 24240 */ "C_SEQ_S\0"
10189 /* 24248 */ "CMP_SEQ_S\0"
10190 /* 24258 */ "CMP_SUEQ_S\0"
10191 /* 24269 */ "C_UEQ_S\0"
10192 /* 24277 */ "CMP_UEQ_S\0"
10193 /* 24287 */ "C_EQ_S\0"
10194 /* 24294 */ "CMP_EQ_S\0"
10195 /* 24303 */ "FABS_S\0"
10196 /* 24310 */ "CLASS_S\0"
10197 /* 24318 */ "PseudoSELECT_S\0"
10198 /* 24333 */ "C_NGT_S\0"
10199 /* 24341 */ "C_OLT_S\0"
10200 /* 24349 */ "CMP_SLT_S\0"
10201 /* 24359 */ "CMP_SULT_S\0"
10202 /* 24370 */ "C_ULT_S\0"
10203 /* 24378 */ "CMP_ULT_S\0"
10204 /* 24388 */ "C_LT_S\0"
10205 /* 24395 */ "CMP_LT_S\0"
10206 /* 24404 */ "RINT_S\0"
10207 /* 24411 */ "FSQRT_S\0"
10208 /* 24419 */ "RSQRT_S\0"
10209 /* 24427 */ "MOVT_S\0"
10210 /* 24434 */ "PseudoSELECTFP_T_S\0"
10211 /* 24453 */ "FDIV_S\0"
10212 /* 24460 */ "FMOV_S\0"
10213 /* 24467 */ "PseudoTRUNC_W_S\0"
10214 /* 24483 */ "ROUND_W_S\0"
10215 /* 24493 */ "CEIL_W_S\0"
10216 /* 24502 */ "FLOOR_W_S\0"
10217 /* 24512 */ "CVT_W_S\0"
10218 /* 24520 */ "MAX_S\0"
10219 /* 24526 */ "SELNEZ_S\0"
10220 /* 24535 */ "SELEQZ_S\0"
10221 /* 24544 */ "BC1T\0"
10222 /* 24549 */ "G_SSUBSAT\0"
10223 /* 24559 */ "G_USUBSAT\0"
10224 /* 24569 */ "G_SADDSAT\0"
10225 /* 24579 */ "G_UADDSAT\0"
10226 /* 24589 */ "G_SSHLSAT\0"
10227 /* 24599 */ "G_USHLSAT\0"
10228 /* 24609 */ "G_SMULFIXSAT\0"
10229 /* 24622 */ "G_UMULFIXSAT\0"
10230 /* 24635 */ "G_SDIVFIXSAT\0"
10231 /* 24648 */ "G_UDIVFIXSAT\0"
10232 /* 24661 */ "G_EXTRACT\0"
10233 /* 24671 */ "G_SELECT\0"
10234 /* 24680 */ "G_BRINDIRECT\0"
10235 /* 24693 */ "DERET\0"
10236 /* 24699 */ "PATCHABLE_RET\0"
10237 /* 24713 */ "G_MEMSET\0"
10238 /* 24722 */ "BGT\0"
10239 /* 24726 */ "WAIT\0"
10240 /* 24731 */ "PATCHABLE_FUNCTION_EXIT\0"
10241 /* 24755 */ "G_BRJT\0"
10242 /* 24762 */ "BLT\0"
10243 /* 24766 */ "G_EXTRACT_VECTOR_ELT\0"
10244 /* 24787 */ "G_INSERT_VECTOR_ELT\0"
10245 /* 24807 */ "SLT\0"
10246 /* 24811 */ "TLT\0"
10247 /* 24815 */ "PseudoDMULT\0"
10248 /* 24827 */ "PseudoMULT\0"
10249 /* 24838 */ "DMT\0"
10250 /* 24842 */ "EMT\0"
10251 /* 24846 */ "G_FCONSTANT\0"
10252 /* 24858 */ "G_CONSTANT\0"
10253 /* 24869 */ "G_INTRINSIC_CONVERGENT\0"
10254 /* 24892 */ "STATEPOINT\0"
10255 /* 24903 */ "PATCHPOINT\0"
10256 /* 24914 */ "G_PTRTOINT\0"
10257 /* 24925 */ "G_FRINT\0"
10258 /* 24933 */ "G_INTRINSIC_LLRINT\0"
10259 /* 24952 */ "G_INTRINSIC_LRINT\0"
10260 /* 24970 */ "G_FNEARBYINT\0"
10261 /* 24983 */ "G_VASTART\0"
10262 /* 24993 */ "LIFETIME_START\0"
10263 /* 25008 */ "G_INVOKE_REGION_START\0"
10264 /* 25030 */ "G_INSERT\0"
10265 /* 25039 */ "G_FSQRT\0"
10266 /* 25047 */ "G_STRICT_FSQRT\0"
10267 /* 25062 */ "G_BITCAST\0"
10268 /* 25072 */ "G_ADDRSPACE_CAST\0"
10269 /* 25089 */ "DBG_VALUE_LIST\0"
10270 /* 25104 */ "GINVT\0"
10271 /* 25110 */ "DEXT\0"
10272 /* 25115 */ "G_FPEXT\0"
10273 /* 25123 */ "G_SEXT\0"
10274 /* 25130 */ "G_ASSERT_SEXT\0"
10275 /* 25144 */ "G_ANYEXT\0"
10276 /* 25153 */ "G_ZEXT\0"
10277 /* 25160 */ "G_ASSERT_ZEXT\0"
10278 /* 25174 */ "PseudoMSUBU\0"
10279 /* 25186 */ "PseudoMADDU\0"
10280 /* 25198 */ "DMODU\0"
10281 /* 25204 */ "BGEU\0"
10282 /* 25209 */ "SGEU\0"
10283 /* 25214 */ "TGEU\0"
10284 /* 25219 */ "BLEU\0"
10285 /* 25224 */ "SLEU\0"
10286 /* 25229 */ "DMUHU\0"
10287 /* 25235 */ "TGEIU\0"
10288 /* 25241 */ "TTLTIU\0"
10289 /* 25248 */ "V3MULU\0"
10290 /* 25255 */ "DMULU\0"
10291 /* 25261 */ "VMULU\0"
10292 /* 25267 */ "DINSU\0"
10293 /* 25273 */ "BGTU\0"
10294 /* 25278 */ "BLTU\0"
10295 /* 25283 */ "TLTU\0"
10296 /* 25288 */ "DEXTU\0"
10297 /* 25294 */ "DDIVU\0"
10298 /* 25300 */ "DSRAV\0"
10299 /* 25306 */ "BITREV\0"
10300 /* 25313 */ "DDIV\0"
10301 /* 25318 */ "G_FDIV\0"
10302 /* 25325 */ "G_STRICT_FDIV\0"
10303 /* 25339 */ "PseudoDSDIV\0"
10304 /* 25351 */ "G_SDIV\0"
10305 /* 25358 */ "PseudoSDIV\0"
10306 /* 25369 */ "PseudoDUDIV\0"
10307 /* 25381 */ "G_UDIV\0"
10308 /* 25388 */ "PseudoUDIV\0"
10309 /* 25399 */ "DSLLV\0"
10310 /* 25405 */ "DSRLV\0"
10311 /* 25411 */ "G_GET_FPENV\0"
10312 /* 25423 */ "G_RESET_FPENV\0"
10313 /* 25437 */ "G_SET_FPENV\0"
10314 /* 25449 */ "TLBINV\0"
10315 /* 25456 */ "TLBGINV\0"
10316 /* 25464 */ "SHILOV\0"
10317 /* 25471 */ "EXTPDPV\0"
10318 /* 25479 */ "EXTPV\0"
10319 /* 25485 */ "DROTRV\0"
10320 /* 25492 */ "INSV\0"
10321 /* 25497 */ "AND_V\0"
10322 /* 25503 */ "MOVE_V\0"
10323 /* 25510 */ "BSEL_V\0"
10324 /* 25517 */ "NOR_V\0"
10325 /* 25523 */ "XOR_V\0"
10326 /* 25529 */ "BZ_V\0"
10327 /* 25534 */ "BMZ_V\0"
10328 /* 25540 */ "BNZ_V\0"
10329 /* 25546 */ "BMNZ_V\0"
10330 /* 25553 */ "CRC32W\0"
10331 /* 25560 */ "CRC32CW\0"
10332 /* 25568 */ "LW\0"
10333 /* 25571 */ "G_FPOW\0"
10334 /* 25578 */ "SW\0"
10335 /* 25581 */ "PseudoCVT_D32_W\0"
10336 /* 25597 */ "FLOG2_W\0"
10337 /* 25605 */ "FEXP2_W\0"
10338 /* 25613 */ "PseudoCVT_D64_W\0"
10339 /* 25629 */ "SRA_W\0"
10340 /* 25635 */ "ADD_A_W\0"
10341 /* 25643 */ "FMIN_A_W\0"
10342 /* 25652 */ "ADDS_A_W\0"
10343 /* 25661 */ "FMAX_A_W\0"
10344 /* 25670 */ "FSUB_W\0"
10345 /* 25677 */ "FMSUB_W\0"
10346 /* 25685 */ "NLOC_W\0"
10347 /* 25692 */ "NLZC_W\0"
10348 /* 25699 */ "FADD_W\0"
10349 /* 25706 */ "FMADD_W\0"
10350 /* 25714 */ "SLD_W\0"
10351 /* 25720 */ "PCKOD_W\0"
10352 /* 25728 */ "ILVOD_W\0"
10353 /* 25736 */ "FCLE_W\0"
10354 /* 25743 */ "FSLE_W\0"
10355 /* 25750 */ "FCULE_W\0"
10356 /* 25758 */ "FSULE_W\0"
10357 /* 25766 */ "FCNE_W\0"
10358 /* 25773 */ "FSNE_W\0"
10359 /* 25780 */ "FCUNE_W\0"
10360 /* 25788 */ "FSUNE_W\0"
10361 /* 25796 */ "INSVE_W\0"
10362 /* 25804 */ "FCAF_W\0"
10363 /* 25811 */ "FSAF_W\0"
10364 /* 25818 */ "VSHF_W\0"
10365 /* 25825 */ "BNEG_W\0"
10366 /* 25832 */ "PRECR_SRA_PH_W\0"
10367 /* 25847 */ "PRECRQ_PH_W\0"
10368 /* 25859 */ "PRECR_SRA_R_PH_W\0"
10369 /* 25876 */ "PRECRQ_RS_PH_W\0"
10370 /* 25891 */ "SUBQH_W\0"
10371 /* 25899 */ "ADDQH_W\0"
10372 /* 25907 */ "SRAI_W\0"
10373 /* 25914 */ "SLDI_W\0"
10374 /* 25921 */ "BNEGI_W\0"
10375 /* 25929 */ "SLLI_W\0"
10376 /* 25936 */ "SRLI_W\0"
10377 /* 25943 */ "BINSLI_W\0"
10378 /* 25952 */ "CEQI_W\0"
10379 /* 25959 */ "SRARI_W\0"
10380 /* 25967 */ "BCLRI_W\0"
10381 /* 25975 */ "SRLRI_W\0"
10382 /* 25983 */ "BINSRI_W\0"
10383 /* 25992 */ "SPLATI_W\0"
10384 /* 26001 */ "BSETI_W\0"
10385 /* 26009 */ "SUBVI_W\0"
10386 /* 26017 */ "ADDVI_W\0"
10387 /* 26025 */ "FILL_W\0"
10388 /* 26032 */ "SLL_W\0"
10389 /* 26038 */ "FEXUPL_W\0"
10390 /* 26047 */ "FFQL_W\0"
10391 /* 26054 */ "SRL_W\0"
10392 /* 26060 */ "BINSL_W\0"
10393 /* 26068 */ "FMUL_W\0"
10394 /* 26075 */ "ILVL_W\0"
10395 /* 26082 */ "DPAQ_SA_L_W\0"
10396 /* 26094 */ "DPSQ_SA_L_W\0"
10397 /* 26106 */ "FMIN_W\0"
10398 /* 26113 */ "FCUN_W\0"
10399 /* 26120 */ "FSUN_W\0"
10400 /* 26127 */ "FEXDO_W\0"
10401 /* 26135 */ "FRCP_W\0"
10402 /* 26142 */ "FCEQ_W\0"
10403 /* 26149 */ "FSEQ_W\0"
10404 /* 26156 */ "FCUEQ_W\0"
10405 /* 26164 */ "FSUEQ_W\0"
10406 /* 26172 */ "FTQ_W\0"
10407 /* 26178 */ "MSUB_Q_W\0"
10408 /* 26187 */ "MADD_Q_W\0"
10409 /* 26196 */ "MUL_Q_W\0"
10410 /* 26204 */ "MSUBR_Q_W\0"
10411 /* 26214 */ "MADDR_Q_W\0"
10412 /* 26224 */ "MULR_Q_W\0"
10413 /* 26233 */ "SRAR_W\0"
10414 /* 26240 */ "LDR_W\0"
10415 /* 26246 */ "BCLR_W\0"
10416 /* 26253 */ "SRLR_W\0"
10417 /* 26260 */ "FCOR_W\0"
10418 /* 26267 */ "FSOR_W\0"
10419 /* 26274 */ "FEXUPR_W\0"
10420 /* 26283 */ "FFQR_W\0"
10421 /* 26290 */ "BINSR_W\0"
10422 /* 26298 */ "STR_W\0"
10423 /* 26304 */ "EXTR_W\0"
10424 /* 26311 */ "ILVR_W\0"
10425 /* 26318 */ "SHRA_R_W\0"
10426 /* 26327 */ "SUBQH_R_W\0"
10427 /* 26337 */ "ADDQH_R_W\0"
10428 /* 26347 */ "EXTR_R_W\0"
10429 /* 26356 */ "SHRAV_R_W\0"
10430 /* 26366 */ "EXTRV_R_W\0"
10431 /* 26376 */ "FABS_W\0"
10432 /* 26383 */ "MULQ_RS_W\0"
10433 /* 26393 */ "EXTR_RS_W\0"
10434 /* 26403 */ "EXTRV_RS_W\0"
10435 /* 26414 */ "FCLASS_W\0"
10436 /* 26423 */ "ASUB_S_W\0"
10437 /* 26432 */ "HSUB_S_W\0"
10438 /* 26441 */ "DPSUB_S_W\0"
10439 /* 26451 */ "FTRUNC_S_W\0"
10440 /* 26462 */ "HADD_S_W\0"
10441 /* 26471 */ "DPADD_S_W\0"
10442 /* 26481 */ "MOD_S_W\0"
10443 /* 26489 */ "CLE_S_W\0"
10444 /* 26497 */ "AVE_S_W\0"
10445 /* 26505 */ "CLEI_S_W\0"
10446 /* 26514 */ "MINI_S_W\0"
10447 /* 26523 */ "CLTI_S_W\0"
10448 /* 26532 */ "MAXI_S_W\0"
10449 /* 26541 */ "SHLL_S_W\0"
10450 /* 26550 */ "MIN_S_W\0"
10451 /* 26558 */ "DOTP_S_W\0"
10452 /* 26567 */ "SUBQ_S_W\0"
10453 /* 26576 */ "ADDQ_S_W\0"
10454 /* 26585 */ "MULQ_S_W\0"
10455 /* 26594 */ "ABSQ_S_W\0"
10456 /* 26603 */ "AVER_S_W\0"
10457 /* 26612 */ "SUBS_S_W\0"
10458 /* 26621 */ "ADDS_S_W\0"
10459 /* 26630 */ "SAT_S_W\0"
10460 /* 26638 */ "CLT_S_W\0"
10461 /* 26646 */ "FFINT_S_W\0"
10462 /* 26656 */ "FTINT_S_W\0"
10463 /* 26666 */ "PseudoCVT_S_W\0"
10464 /* 26680 */ "SUBSUU_S_W\0"
10465 /* 26691 */ "DIV_S_W\0"
10466 /* 26699 */ "SHLLV_S_W\0"
10467 /* 26709 */ "MAX_S_W\0"
10468 /* 26717 */ "COPY_S_W\0"
10469 /* 26726 */ "SPLAT_W\0"
10470 /* 26734 */ "BSET_W\0"
10471 /* 26741 */ "FCLT_W\0"
10472 /* 26748 */ "FSLT_W\0"
10473 /* 26755 */ "FCULT_W\0"
10474 /* 26763 */ "FSULT_W\0"
10475 /* 26771 */ "PCNT_W\0"
10476 /* 26778 */ "FRINT_W\0"
10477 /* 26786 */ "INSERT_W\0"
10478 /* 26795 */ "FSQRT_W\0"
10479 /* 26803 */ "FRSQRT_W\0"
10480 /* 26812 */ "ST_W\0"
10481 /* 26817 */ "ASUB_U_W\0"
10482 /* 26826 */ "HSUB_U_W\0"
10483 /* 26835 */ "DPSUB_U_W\0"
10484 /* 26845 */ "FTRUNC_U_W\0"
10485 /* 26856 */ "HADD_U_W\0"
10486 /* 26865 */ "DPADD_U_W\0"
10487 /* 26875 */ "MOD_U_W\0"
10488 /* 26883 */ "CLE_U_W\0"
10489 /* 26891 */ "AVE_U_W\0"
10490 /* 26899 */ "CLEI_U_W\0"
10491 /* 26908 */ "MINI_U_W\0"
10492 /* 26917 */ "CLTI_U_W\0"
10493 /* 26926 */ "MAXI_U_W\0"
10494 /* 26935 */ "MIN_U_W\0"
10495 /* 26943 */ "DOTP_U_W\0"
10496 /* 26952 */ "AVER_U_W\0"
10497 /* 26961 */ "SUBS_U_W\0"
10498 /* 26970 */ "ADDS_U_W\0"
10499 /* 26979 */ "SUBSUS_U_W\0"
10500 /* 26990 */ "SAT_U_W\0"
10501 /* 26998 */ "CLT_U_W\0"
10502 /* 27006 */ "FFINT_U_W\0"
10503 /* 27016 */ "FTINT_U_W\0"
10504 /* 27026 */ "DIV_U_W\0"
10505 /* 27034 */ "MAX_U_W\0"
10506 /* 27042 */ "COPY_U_W\0"
10507 /* 27051 */ "MSUBV_W\0"
10508 /* 27059 */ "MADDV_W\0"
10509 /* 27067 */ "PCKEV_W\0"
10510 /* 27075 */ "ILVEV_W\0"
10511 /* 27083 */ "FDIV_W\0"
10512 /* 27090 */ "MULV_W\0"
10513 /* 27097 */ "EXTRV_W\0"
10514 /* 27105 */ "FMAX_W\0"
10515 /* 27112 */ "BZ_W\0"
10516 /* 27117 */ "BNZ_W\0"
10517 /* 27123 */ "G_VECREDUCE_FMAX\0"
10518 /* 27140 */ "G_ATOMICRMW_FMAX\0"
10519 /* 27157 */ "G_VECREDUCE_SMAX\0"
10520 /* 27174 */ "G_SMAX\0"
10521 /* 27181 */ "G_VECREDUCE_UMAX\0"
10522 /* 27198 */ "G_UMAX\0"
10523 /* 27205 */ "G_ATOMICRMW_UMAX\0"
10524 /* 27222 */ "G_ATOMICRMW_MAX\0"
10525 /* 27238 */ "MFTACX\0"
10526 /* 27245 */ "MTTACX\0"
10527 /* 27252 */ "G_FRAME_INDEX\0"
10528 /* 27266 */ "G_SBFX\0"
10529 /* 27273 */ "G_UBFX\0"
10530 /* 27280 */ "LHX\0"
10531 /* 27284 */ "G_SMULFIX\0"
10532 /* 27294 */ "G_UMULFIX\0"
10533 /* 27304 */ "G_SDIVFIX\0"
10534 /* 27314 */ "G_UDIVFIX\0"
10535 /* 27324 */ "JALX\0"
10536 /* 27329 */ "LBUX\0"
10537 /* 27334 */ "LWX\0"
10538 /* 27338 */ "G_MEMCPY\0"
10539 /* 27347 */ "COPY\0"
10540 /* 27352 */ "CONSTPOOL_ENTRY\0"
10541 /* 27368 */ "CONVERGENCECTRL_ENTRY\0"
10542 /* 27390 */ "BGEZ\0"
10543 /* 27395 */ "BLEZ\0"
10544 /* 27400 */ "BC1NEZ\0"
10545 /* 27407 */ "BC2NEZ\0"
10546 /* 27414 */ "SELNEZ\0"
10547 /* 27421 */ "DCLZ\0"
10548 /* 27426 */ "G_CTLZ\0"
10549 /* 27433 */ "BC1EQZ\0"
10550 /* 27440 */ "BC2EQZ\0"
10551 /* 27447 */ "SELEQZ\0"
10552 /* 27454 */ "BGTZ\0"
10553 /* 27459 */ "BLTZ\0"
10554 /* 27464 */ "G_CTTZ\0"
10555 /* 27471 */ "SelBneZ\0"
10556 /* 27479 */ "SelBeqZ\0"
10557 /* 27487 */ "JalOneReg\0"
10558 /* 27497 */ "JalTwoReg\0"
10559 /* 27507 */ "PseudoIndirectHazardBranch\0"
10560 /* 27534 */ "PseudoIndirectBranch\0"
10561 /* 27555 */ "Ulh\0"
10562 /* 27559 */ "Ush\0"
10563 /* 27563 */ "DADDi\0"
10564 /* 27569 */ "ANDi\0"
10565 /* 27574 */ "SNEi\0"
10566 /* 27579 */ "SEQi\0"
10567 /* 27584 */ "XORi\0"
10568 /* 27589 */ "SLTi\0"
10569 /* 27594 */ "LONG_BRANCH_LUi\0"
10570 /* 27610 */ "SelTBtneZCmpi\0"
10571 /* 27624 */ "SelTBteqZCmpi\0"
10572 /* 27638 */ "SelTBtneZSlti\0"
10573 /* 27652 */ "SelTBteqZSlti\0"
10574 /* 27666 */ "SGEImm\0"
10575 /* 27673 */ "SLEImm\0"
10576 /* 27680 */ "DROLImm\0"
10577 /* 27688 */ "NORImm\0"
10578 /* 27695 */ "DRORImm\0"
10579 /* 27703 */ "SGTImm\0"
10580 /* 27710 */ "SGEUImm\0"
10581 /* 27718 */ "SLEUImm\0"
10582 /* 27726 */ "SGTUImm\0"
10583 /* 27734 */ "BneImm\0"
10584 /* 27741 */ "BeqImm\0"
10585 /* 27748 */ "PseudoReturn\0"
10586 /* 27761 */ "JALRHB64Pseudo\0"
10587 /* 27776 */ "JALR64Pseudo\0"
10588 /* 27789 */ "JALRHBPseudo\0"
10589 /* 27802 */ "JALRPseudo\0"
10590 /* 27813 */ "B_MMR6_Pseudo\0"
10591 /* 27827 */ "B_MM_Pseudo\0"
10592 /* 27839 */ "SDIV_MM_Pseudo\0"
10593 /* 27854 */ "UDIV_MM_Pseudo\0"
10594 /* 27869 */ "LDMacro\0"
10595 /* 27877 */ "SDMacro\0"
10596 /* 27885 */ "SNEMacro\0"
10597 /* 27894 */ "SNEIMacro\0"
10598 /* 27904 */ "SEQIMacro\0"
10599 /* 27914 */ "DSRemIMacro\0"
10600 /* 27926 */ "DURemIMacro\0"
10601 /* 27938 */ "DSDivIMacro\0"
10602 /* 27950 */ "DUDivIMacro\0"
10603 /* 27962 */ "DMULMacro\0"
10604 /* 27972 */ "DMULOMacro\0"
10605 /* 27983 */ "SEQMacro\0"
10606 /* 27992 */ "ABSMacro\0"
10607 /* 28001 */ "DMULOUMacro\0"
10608 /* 28013 */ "DSRemMacro\0"
10609 /* 28024 */ "DURemMacro\0"
10610 /* 28035 */ "BGEImmMacro\0"
10611 /* 28047 */ "BLEImmMacro\0"
10612 /* 28059 */ "BGELImmMacro\0"
10613 /* 28072 */ "BLELImmMacro\0"
10614 /* 28085 */ "BNELImmMacro\0"
10615 /* 28098 */ "BEQLImmMacro\0"
10616 /* 28111 */ "BGTLImmMacro\0"
10617 /* 28124 */ "BLTLImmMacro\0"
10618 /* 28137 */ "BGEULImmMacro\0"
10619 /* 28151 */ "BLEULImmMacro\0"
10620 /* 28165 */ "DMULImmMacro\0"
10621 /* 28178 */ "BGTULImmMacro\0"
10622 /* 28192 */ "BLTULImmMacro\0"
10623 /* 28206 */ "BGTImmMacro\0"
10624 /* 28218 */ "BLTImmMacro\0"
10625 /* 28230 */ "BGEUImmMacro\0"
10626 /* 28243 */ "BLEUImmMacro\0"
10627 /* 28256 */ "BGTUImmMacro\0"
10628 /* 28269 */ "BLTUImmMacro\0"
10629 /* 28282 */ "DSDivMacro\0"
10630 /* 28293 */ "DUDivMacro\0"
10631 /* 28304 */ "LONG_BRANCH_LUi2Op\0"
10632 /* 28323 */ "LONG_BRANCH_DADDiu2Op\0"
10633 /* 28345 */ "LONG_BRANCH_ADDiu2Op\0"
10634 /* 28366 */ "SelTBtneZCmp\0"
10635 /* 28379 */ "SelTBteqZCmp\0"
10636 /* 28392 */ "SaaAddr\0"
10637 /* 28400 */ "SaadAddr\0"
10638 /* 28409 */ "ERet\0"
10639 /* 28414 */ "SelTBtneZSlt\0"
10640 /* 28427 */ "SelTBteqZSlt\0"
10641 /* 28440 */ "LBu\0"
10642 /* 28444 */ "DSUBu\0"
10643 /* 28450 */ "BADDu\0"
10644 /* 28456 */ "DADDu\0"
10645 /* 28462 */ "LHu\0"
10646 /* 28466 */ "SLTu\0"
10647 /* 28471 */ "PseudoDMULTu\0"
10648 /* 28484 */ "PseudoMULTu\0"
10649 /* 28496 */ "LWu\0"
10650 /* 28500 */ "Ulhu\0"
10651 /* 28505 */ "LONG_BRANCH_DADDiu\0"
10652 /* 28524 */ "LEA_ADDiu\0"
10653 /* 28534 */ "LONG_BRANCH_ADDiu\0"
10654 /* 28552 */ "SLTiu\0"
10655 /* 28558 */ "SelTBtneZSltiu\0"
10656 /* 28573 */ "SelTBteqZSltiu\0"
10657 /* 28588 */ "SelTBtneZSltu\0"
10658 /* 28602 */ "SelTBteqZSltu\0"
10659 /* 28616 */ "Ulw\0"
10660 /* 28620 */ "Usw\0"
10661};
10662#ifdef __GNUC__
10663#pragma GCC diagnostic pop
10664#endif
10665
10666extern const unsigned MipsInstrNameIndices[] = {
10667 15520U, 21069U, 23037U, 21409U, 15872U, 15853U, 15881U, 16133U,
10668 13855U, 13870U, 13735U, 13909U, 23720U, 13558U, 25089U, 13753U,
10669 15516U, 15862U, 13242U, 27347U, 13414U, 24993U, 11688U, 13189U,
10670 13230U, 22393U, 16105U, 24903U, 11778U, 22874U, 13972U, 24892U,
10671 13467U, 22624U, 22611U, 23106U, 24699U, 24731U, 16037U, 16084U,
10672 16057U, 15913U, 23071U, 22308U, 27368U, 23324U, 22577U, 13606U,
10673 25130U, 25160U, 21226U, 11571U, 10304U, 16289U, 25351U, 25381U,
10674 16390U, 16397U, 16404U, 16414U, 11651U, 23504U, 23467U, 13733U,
10675 15518U, 27252U, 13568U, 13583U, 16143U, 24661U, 23646U, 25030U,
10676 23663U, 23404U, 11190U, 23703U, 24914U, 23590U, 25062U, 13657U,
10677 23082U, 11747U, 11164U, 11729U, 24952U, 24933U, 21190U, 23131U,
10678 23150U, 11444U, 11388U, 11418U, 11429U, 11369U, 11399U, 13521U,
10679 13505U, 23750U, 13923U, 13940U, 11587U, 10310U, 11657U, 11618U,
10680 23509U, 23473U, 27222U, 21352U, 27205U, 21335U, 11527U, 10276U,
10681 27140U, 21270U, 22455U, 22433U, 13222U, 14014U, 11701U, 24680U,
10682 25008U, 11076U, 23798U, 24869U, 23825U, 25144U, 11182U, 24858U,
10683 24846U, 24983U, 13964U, 25123U, 13896U, 25153U, 15998U, 23309U,
10684 23295U, 15991U, 23302U, 23583U, 16190U, 22550U, 22543U, 22557U,
10685 22564U, 24671U, 21466U, 13267U, 21450U, 13214U, 21458U, 13259U,
10686 21442U, 13206U, 22377U, 22369U, 14037U, 14029U, 24579U, 24569U,
10687 24559U, 24549U, 24599U, 24589U, 27284U, 27294U, 24609U, 24622U,
10688 27304U, 27314U, 24635U, 24648U, 11485U, 10255U, 16231U, 8509U,
10689 11362U, 25318U, 16369U, 25571U, 15598U, 22926U, 1214U, 9U,
10690 13957U, 1196U, 0U, 22901U, 22933U, 13784U, 25115U, 11154U,
10691 15546U, 15570U, 22512U, 22521U, 23633U, 21241U, 23737U, 13666U,
10692 21155U, 21165U, 13316U, 13331U, 21112U, 21144U, 25411U, 25437U,
10693 25423U, 13275U, 13303U, 13288U, 11577U, 15743U, 21304U, 27174U,
10694 21328U, 27198U, 23640U, 11720U, 11710U, 23025U, 24755U, 13392U,
10695 23385U, 23365U, 24787U, 24766U, 23419U, 23436U, 23780U, 27464U,
10696 13715U, 27426U, 13697U, 22603U, 22477U, 13539U, 16004U, 23696U,
10697 21376U, 21183U, 23688U, 21368U, 21175U, 14584U, 14053U, 14045U,
10698 25039U, 23351U, 24925U, 24970U, 25072U, 23050U, 13401U, 11216U,
10699 13627U, 13490U, 11513U, 10262U, 16259U, 25325U, 16376U, 8515U,
10700 25047U, 22910U, 23170U, 23186U, 27338U, 13443U, 13639U, 24713U,
10701 22385U, 22426U, 22402U, 22414U, 11492U, 16238U, 11468U, 16214U,
10702 27123U, 21253U, 21123U, 21091U, 11555U, 16273U, 11635U, 23489U,
10703 23451U, 27157U, 21287U, 27181U, 21311U, 27266U, 27273U, 27992U,
10704 21425U, 22859U, 21810U, 21894U, 22110U, 4073U, 9395U, 893U,
10705 8751U, 3098U, 9073U, 8379U, 9710U, 3955U, 9235U, 775U,
10706 8591U, 2928U, 8913U, 8267U, 9556U, 3996U, 9290U, 816U,
10707 8646U, 2969U, 8968U, 8306U, 9609U, 4153U, 9503U, 973U,
10708 8859U, 3244U, 9181U, 8455U, 9814U, 4037U, 9345U, 857U,
10709 8701U, 3062U, 9023U, 8345U, 9662U, 3975U, 9262U, 795U,
10710 8618U, 2948U, 8940U, 8286U, 9582U, 4113U, 9449U, 933U,
10711 8805U, 3138U, 9127U, 8417U, 9762U, 3935U, 9208U, 755U,
10712 8564U, 2908U, 8886U, 8248U, 9530U, 4132U, 9475U, 952U,
10713 8831U, 3223U, 9153U, 8435U, 9787U, 4016U, 9317U, 836U,
10714 8673U, 3041U, 8995U, 8325U, 9635U, 4093U, 9422U, 913U,
10715 8778U, 3118U, 9100U, 8398U, 9736U, 4057U, 9372U, 877U,
10716 8728U, 3082U, 9050U, 8364U, 9688U, 9870U, 23030U, 19647U,
10717 28098U, 13359U, 28035U, 15898U, 28059U, 25204U, 28230U, 16197U,
10718 28137U, 24722U, 28206U, 16180U, 28111U, 25273U, 28256U, 16295U,
10719 28178U, 13410U, 28047U, 15903U, 28072U, 25219U, 28243U, 16203U,
10720 28151U, 24762U, 28218U, 16185U, 28124U, 25278U, 28269U, 16301U,
10721 28192U, 28085U, 21508U, 21796U, 21689U, 21989U, 21880U, 22096U,
10722 17839U, 27813U, 27827U, 27741U, 27734U, 4677U, 4224U, 4705U,
10723 4254U, 4735U, 4766U, 4663U, 4209U, 4691U, 4239U, 4719U,
10724 4751U, 2786U, 3556U, 131U, 27352U, 21736U, 22036U, 149U,
10725 1153U, 28165U, 27962U, 27972U, 28001U, 16159U, 27680U, 23360U,
10726 27695U, 27938U, 28282U, 27914U, 28013U, 27950U, 28293U, 27926U,
10727 28024U, 28409U, 2799U, 3572U, 12481U, 26376U, 21474U, 21491U,
10728 21704U, 22004U, 4824U, 21524U, 22180U, 21571U, 22223U, 21719U,
10729 21547U, 22201U, 22019U, 21617U, 22265U, 21594U, 22244U, 21641U,
10730 22287U, 27776U, 27761U, 27789U, 27802U, 6961U, 27487U, 27497U,
10731 27869U, 12410U, 26240U, 3921U, 8223U, 2053U, 22636U, 22721U,
10732 28534U, 28345U, 28505U, 28323U, 27594U, 28304U, 3602U, 19191U,
10733 1121U, 3812U, 1088U, 3624U, 1111U, 3802U, 23209U, 1068U,
10734 23538U, 23226U, 23555U, 1151U, 27238U, 52U, 137U, 22677U,
10735 23524U, 112U, 15524U, 22352U, 1135U, 3841U, 21751U, 22051U,
10736 21774U, 22074U, 27245U, 64U, 155U, 22684U, 23531U, 119U,
10737 15535U, 22363U, 28166U, 27973U, 28002U, 5084U, 5217U, 5116U,
10738 5269U, 22573U, 27688U, 3735U, 21825U, 21909U, 22125U, 21826U,
10739 21910U, 22126U, 10050U, 9952U, 10165U, 14215U, 14110U, 14375U,
10740 25581U, 16339U, 25613U, 16355U, 26666U, 24815U, 28471U, 25339U,
10741 25369U, 15672U, 3157U, 27534U, 3667U, 5329U, 8200U, 20931U,
10742 7994U, 27507U, 3638U, 5299U, 8172U, 11544U, 25186U, 20375U,
10743 18171U, 15492U, 2847U, 18823U, 22335U, 3292U, 19212U, 10293U,
10744 25174U, 20360U, 18102U, 15503U, 2860U, 22761U, 18837U, 24827U,
10745 20339U, 28484U, 21032U, 14144U, 9987U, 27748U, 3826U, 25358U,
10746 388U, 2371U, 15635U, 2998U, 24080U, 644U, 2684U, 15711U,
10747 3202U, 24434U, 559U, 2599U, 15689U, 3176U, 24318U, 13133U,
10748 683U, 24467U, 25388U, 16160U, 27681U, 23361U, 27696U, 9840U,
10749 3906U, 212U, 27839U, 27877U, 27939U, 28283U, 27904U, 27983U,
10750 13363U, 27666U, 3717U, 25209U, 27710U, 3762U, 27703U, 3744U,
10751 27726U, 3782U, 13425U, 27673U, 3726U, 25224U, 27718U, 3772U,
10752 3753U, 3792U, 27894U, 27885U, 21664U, 21855U, 21939U, 21964U,
10753 22155U, 27915U, 28014U, 8235U, 2064U, 22650U, 22736U, 12468U,
10754 26298U, 3928U, 19198U, 21677U, 21868U, 21952U, 21977U, 22168U,
10755 28392U, 28400U, 27479U, 27471U, 28379U, 27624U, 28427U, 27652U,
10756 28573U, 28602U, 28366U, 27610U, 28414U, 27638U, 28558U, 28588U,
10757 5029U, 4488U, 4503U, 5041U, 5256U, 16012U, 13809U, 13791U,
10758 13825U, 13841U, 13884U, 2817U, 9888U, 2009U, 18382U, 6838U,
10759 19122U, 6970U, 22409U, 19243U, 27854U, 27951U, 28294U, 27927U,
10760 28025U, 27555U, 28500U, 28616U, 27559U, 28620U, 21840U, 21924U,
10761 22140U, 14334U, 18638U, 10110U, 1362U, 26594U, 20806U, 11464U,
10762 11251U, 18124U, 6015U, 19323U, 17071U, 17484U, 19495U, 7880U,
10763 14135U, 1465U, 14252U, 1520U, 26337U, 1878U, 25899U, 1850U,
10764 14207U, 18534U, 14314U, 18625U, 26576U, 20794U, 3410U, 11275U,
10765 18135U, 10348U, 11851U, 14619U, 25652U, 10756U, 12650U, 15108U,
10766 26621U, 10948U, 13015U, 15357U, 26970U, 17701U, 5755U, 9978U,
10767 1267U, 10088U, 1330U, 7850U, 14399U, 1608U, 10190U, 18025U,
10768 14354U, 1580U, 10130U, 17972U, 10562U, 12215U, 14804U, 26017U,
10769 11018U, 13096U, 15427U, 27060U, 11308U, 18144U, 10332U, 11834U,
10770 14603U, 25635U, 18178U, 6237U, 27564U, 20955U, 28518U, 21051U,
10771 28451U, 21009U, 21213U, 7028U, 11244U, 6003U, 11631U, 17512U,
10772 5596U, 2187U, 17539U, 5629U, 10437U, 6893U, 18185U, 6246U,
10773 25497U, 27569U, 3690U, 20963U, 11681U, 1422U, 10661U, 12497U,
10774 14957U, 26423U, 10853U, 12862U, 15215U, 26817U, 15566U, 11238U,
10775 5992U, 6921U, 10738U, 12632U, 15081U, 26603U, 10930U, 12997U,
10776 15339U, 26952U, 10686U, 12571U, 15020U, 26497U, 10878U, 12936U,
10777 15278U, 26891U, 4556U, 4432U, 4940U, 4584U, 4381U, 4880U,
10778 4448U, 5243U, 5182U, 17496U, 28450U, 15753U, 11088U, 5871U,
10779 21212U, 1783U, 85U, 231U, 225U, 239U, 11059U, 5536U,
10780 27433U, 6178U, 13692U, 15933U, 18354U, 27400U, 6141U, 24544U,
10781 16174U, 20300U, 27440U, 6191U, 27407U, 6154U, 10498U, 12165U,
10782 14754U, 25967U, 10632U, 12416U, 14928U, 26246U, 5834U, 22942U,
10783 3312U, 11270U, 2104U, 6038U, 16164U, 17746U, 11123U, 5931U,
10784 11332U, 5583U, 2163U, 18162U, 6204U, 19544U, 11062U, 2076U,
10785 5842U, 11286U, 2123U, 6077U, 27390U, 3510U, 15765U, 11099U,
10786 5892U, 16117U, 19816U, 18957U, 11314U, 2139U, 6119U, 16315U,
10787 20892U, 27454U, 3542U, 11131U, 5944U, 11338U, 2171U, 6215U,
10788 16327U, 20915U, 10474U, 12141U, 14730U, 25943U, 10604U, 12264U,
10789 14831U, 26060U, 10528U, 12181U, 14770U, 25983U, 10646U, 12460U,
10790 14942U, 26290U, 25306U, 20439U, 22486U, 7048U, 27395U, 3517U,
10791 11107U, 5905U, 11320U, 2147U, 6130U, 16321U, 20900U, 11281U,
10792 2116U, 6067U, 11292U, 2131U, 6088U, 27459U, 3549U, 15772U,
10793 11139U, 5957U, 16125U, 19827U, 18967U, 11344U, 2179U, 6226U,
10794 16333U, 20923U, 10577U, 25546U, 10570U, 25534U, 13439U, 2780U,
10795 11067U, 2083U, 5852U, 10444U, 12119U, 14708U, 25921U, 10416U,
10796 12098U, 14687U, 25825U, 15908U, 17736U, 11115U, 5918U, 11326U,
10797 5570U, 2155U, 18153U, 6167U, 18285U, 11298U, 6099U, 11053U,
10798 13170U, 15462U, 25540U, 27117U, 11303U, 6109U, 746U, 1942U,
10799 17013U, 15732U, 17567U, 5651U, 18941U, 6950U, 10452U, 25510U,
10800 10546U, 12199U, 14788U, 26001U, 10825U, 12739U, 15187U, 26734U,
10801 11048U, 13156U, 15457U, 25529U, 27112U, 4967U, 4613U, 4979U,
10802 4626U, 4955U, 4600U, 4866U, 5291U, 4790U, 5283U, 4781U,
10803 13371U, 13346U, 18213U, 18239U, 6781U, 8116U, 2466U, 6444U,
10804 24173U, 7428U, 713U, 2747U, 6713U, 20632U, 24493U, 20264U,
10805 7709U, 10483U, 12150U, 14739U, 25952U, 10619U, 12334U, 14854U,
10806 26143U, 101U, 16462U, 17055U, 9851U, 23678U, 1015U, 1048U,
10807 1102U, 12489U, 6586U, 24310U, 7570U, 10694U, 12579U, 15028U,
10808 26505U, 10886U, 12944U, 15286U, 26899U, 10678U, 12563U, 15012U,
10809 26489U, 10870U, 12928U, 15270U, 26883U, 22331U, 19205U, 7039U,
10810 8148U, 10712U, 12597U, 15046U, 26523U, 10904U, 12962U, 15304U,
10811 26917U, 10773U, 12667U, 15125U, 26638U, 10976U, 13043U, 15385U,
10812 26998U, 27422U, 20908U, 7973U, 8165U, 10025U, 1281U, 9927U,
10813 1235U, 10140U, 1377U, 10038U, 17930U, 9940U, 17857U, 10153U,
10814 17985U, 10056U, 17945U, 9958U, 17872U, 10171U, 18000U, 6363U,
10815 7323U, 12394U, 6572U, 14221U, 18545U, 24294U, 7556U, 12090U,
10816 24099U, 11996U, 6334U, 14116U, 18464U, 24025U, 7294U, 12807U,
10817 6645U, 14381U, 18665U, 24395U, 7629U, 12057U, 6348U, 24034U,
10818 7308U, 12347U, 6526U, 24248U, 7510U, 11949U, 6288U, 23979U,
10819 7248U, 12760U, 6599U, 24349U, 7583U, 12373U, 6541U, 24258U,
10820 7525U, 11975U, 6303U, 23989U, 7263U, 12786U, 6614U, 24359U,
10821 7598U, 12307U, 6497U, 24206U, 7481U, 12384U, 6557U, 24277U,
10822 7541U, 11986U, 6319U, 24008U, 7279U, 12797U, 6630U, 24378U,
10823 7614U, 12317U, 6512U, 24223U, 7496U, 10808U, 12722U, 15170U,
10824 26717U, 11000U, 15409U, 27042U, 9865U, 9872U, 11451U, 14006U,
10825 25560U, 11350U, 13989U, 25553U, 126U, 16478U, 17063U, 9858U,
10826 23868U, 19862U, 25587U, 20551U, 16345U, 23878U, 19875U, 25619U,
10827 20564U, 7002U, 2489U, 17269U, 6473U, 24192U, 20069U, 7457U,
10828 3493U, 3460U, 3448U, 549U, 16874U, 2589U, 17357U, 16361U,
10829 7015U, 3269U, 3477U, 26672U, 20818U, 7948U, 736U, 17000U,
10830 2770U, 17471U, 24512U, 20289U, 7738U, 531U, 16850U, 2571U,
10831 17333U, 24287U, 20123U, 380U, 16711U, 2363U, 17221U, 24074U,
10832 20005U, 353U, 16675U, 2336U, 17197U, 24018U, 19975U, 606U,
10833 16926U, 2646U, 17409U, 24388U, 20176U, 312U, 16622U, 2295U,
10834 17144U, 23954U, 19930U, 322U, 16635U, 2305U, 17157U, 23962U,
10835 19941U, 440U, 16762U, 2423U, 17244U, 24138U, 20048U, 576U,
10836 16887U, 2616U, 17370U, 24333U, 20143U, 333U, 16649U, 2316U,
10837 17171U, 23971U, 19953U, 586U, 16900U, 2626U, 17383U, 24341U,
10838 20154U, 511U, 16824U, 2551U, 17307U, 24240U, 20101U, 362U,
10839 16687U, 2345U, 17209U, 24060U, 19985U, 521U, 16837U, 2561U,
10840 17320U, 24269U, 20112U, 343U, 16662U, 2326U, 17184U, 24000U,
10841 19964U, 596U, 16913U, 2636U, 17396U, 24370U, 20165U, 483U,
10842 16787U, 2523U, 17282U, 24216U, 20080U, 5064U, 4903U, 4530U,
10843 11463U, 27563U, 28517U, 28456U, 15487U, 21219U, 15555U, 15565U,
10844 22485U, 22330U, 8147U, 27421U, 8164U, 25313U, 25294U, 24693U,
10845 20308U, 7790U, 25110U, 1058U, 21085U, 25288U, 15474U, 23683U,
10846 21079U, 25267U, 25314U, 25295U, 7901U, 7911U, 10792U, 12706U,
10847 15144U, 26691U, 10984U, 13071U, 15393U, 27026U, 18801U, 6895U,
10848 9846U, 8079U, 18U, 106U, 1174U, 21383U, 24U, 11773U,
10849 25198U, 24838U, 58U, 143U, 1180U, 21396U, 45U, 14592U,
10850 25229U, 16209U, 24821U, 28477U, 25255U, 8139U, 12623U, 15072U,
10851 26558U, 12988U, 15330U, 26943U, 12545U, 14994U, 26471U, 12910U,
10852 15252U, 26865U, 14463U, 1665U, 14538U, 1717U, 26082U, 20642U,
10853 14500U, 18714U, 15823U, 19030U, 23003U, 19619U, 14564U, 1753U,
10854 14443U, 1635U, 22598U, 14477U, 1684U, 14551U, 1735U, 26094U,
10855 20657U, 14526U, 18746U, 12515U, 14975U, 26441U, 12880U, 15233U,
10856 26835U, 15834U, 19044U, 23014U, 19633U, 14574U, 1768U, 14491U,
10857 1703U, 23577U, 1007U, 25485U, 13996U, 25345U, 11603U, 16138U,
10858 993U, 1038U, 25399U, 8559U, 247U, 25300U, 16169U, 1000U,
10859 25405U, 10250U, 28444U, 25375U, 22893U, 13480U, 7120U, 5150U,
10860 5128U, 9884U, 17844U, 5786U, 15479U, 18809U, 6903U, 24842U,
10861 24694U, 11147U, 5970U, 20309U, 7791U, 22897U, 13485U, 7129U,
10862 25111U, 22854U, 22505U, 25471U, 20502U, 19268U, 25479U, 20513U,
10863 19522U, 26403U, 20756U, 26366U, 20730U, 15152U, 18779U, 27097U,
10864 20842U, 26393U, 20743U, 26347U, 20705U, 15090U, 18767U, 26304U,
10865 20683U, 23863U, 1022U, 20353U, 7822U, 540U, 16862U, 2580U,
10866 17345U, 24303U, 20133U, 11898U, 293U, 16597U, 2276U, 17132U,
10867 3372U, 23939U, 19909U, 7236U, 25699U, 12043U, 25804U, 12333U,
10868 26142U, 12488U, 26414U, 11935U, 25736U, 12746U, 26741U, 502U,
10869 16812U, 2542U, 1029U, 17043U, 12005U, 25766U, 12430U, 26260U,
10870 12357U, 26156U, 11959U, 25750U, 12770U, 26755U, 12019U, 25780U,
10871 12293U, 26113U, 13119U, 665U, 16976U, 2705U, 17447U, 24453U,
10872 20218U, 7655U, 27083U, 14846U, 26127U, 11806U, 25605U, 12242U,
10873 26038U, 12444U, 26274U, 12675U, 26646U, 13051U, 27006U, 12251U,
10874 26047U, 12453U, 26283U, 10585U, 12229U, 14812U, 26025U, 11798U,
10875 25597U, 2477U, 6458U, 24182U, 7442U, 724U, 2758U, 6727U,
10876 20672U, 24502U, 20276U, 7723U, 11905U, 25706U, 11860U, 25661U,
10877 13149U, 27105U, 11842U, 25643U, 12286U, 26106U, 674U, 16988U,
10878 2714U, 17459U, 6671U, 24460U, 20228U, 7667U, 11876U, 25677U,
10879 12272U, 450U, 16775U, 2433U, 17257U, 3391U, 24146U, 20059U,
10880 7386U, 26068U, 409U, 16722U, 2392U, 17232U, 24107U, 20014U,
10881 7363U, 15738U, 12326U, 26135U, 12823U, 26778U, 12848U, 26803U,
10882 12050U, 25811U, 12340U, 26149U, 11942U, 25743U, 12753U, 26748U,
10883 12012U, 25773U, 12437U, 26267U, 12840U, 615U, 16938U, 2655U,
10884 17421U, 24411U, 20186U, 26795U, 11869U, 274U, 16572U, 2257U,
10885 17120U, 3362U, 23924U, 19888U, 7224U, 25670U, 12365U, 26164U,
10886 11967U, 25758U, 12778U, 26763U, 12027U, 25788U, 12300U, 26120U,
10887 12685U, 26656U, 13061U, 27016U, 14860U, 26172U, 12525U, 26451U,
10888 12890U, 26845U, 15579U, 6939U, 25104U, 7811U, 12536U, 14985U,
10889 26462U, 12901U, 15243U, 26856U, 12506U, 14966U, 26432U, 12871U,
10890 15224U, 26826U, 16021U, 19134U, 11033U, 13111U, 15442U, 27075U,
10891 10612U, 12279U, 14839U, 26075U, 10393U, 11927U, 14664U, 25728U,
10892 10654U, 12474U, 14950U, 26311U, 23679U, 10839U, 12831U, 15201U,
10893 26786U, 25492U, 10401U, 12035U, 14672U, 25796U, 20531U, 19838U,
10894 7191U, 15730U, 15757U, 23319U, 17643U, 3323U, 5557U, 5795U,
10895 6048U, 17662U, 19845U, 9908U, 2033U, 19736U, 19808U, 27324U,
10896 20869U, 18950U, 11093U, 2096U, 5881U, 11072U, 2090U, 5862U,
10897 23316U, 17635U, 3318U, 22844U, 17503U, 5546U, 7094U, 9902U,
10898 2025U, 8052U, 8087U, 19730U, 18936U, 4874U, 3914U, 4807U,
10899 4799U, 5013U, 4845U, 9916U, 2043U, 13185U, 18192U, 17682U,
10900 27329U, 20877U, 7831U, 17851U, 5809U, 28440U, 3857U, 13682U,
10901 18338U, 20994U, 11611U, 91U, 1957U, 5498U, 459U, 2499U,
10902 1164U, 5416U, 8020U, 1922U, 10431U, 12113U, 14702U, 25915U,
10903 15845U, 11233U, 23063U, 171U, 1971U, 10380U, 11914U, 14651U,
10904 25715U, 28524U, 3876U, 21047U, 14034U, 2837U, 13377U, 18248U,
10905 17711U, 27280U, 20862U, 18412U, 28462U, 3863U, 13687U, 18346U,
10906 21017U, 17559U, 5641U, 16018U, 3264U, 8071U, 11614U, 8109U,
10907 13421U, 18262U, 19128U, 6976U, 8133U, 9847U, 5777U, 8080U,
10908 6930U, 183U, 1987U, 16510U, 27606U, 3711U, 20987U, 25568U,
10909 17720U, 3488U, 161U, 16494U, 1186U, 5478U, 8036U, 1932U,
10910 22691U, 19354U, 13649U, 18324U, 19296U, 16307U, 3280U, 13429U,
10911 18269U, 19177U, 17596U, 5686U, 17025U, 11265U, 6028U, 19530U,
10912 23625U, 3350U, 13529U, 18299U, 19794U, 19506U, 11259U, 20424U,
10913 27334U, 195U, 16528U, 19854U, 20885U, 20539U, 7932U, 28496U,
10914 4283U, 4347U, 4315U, 4364U, 4893U, 4634U, 4519U, 4993U,
10915 4650U, 4400U, 4462U, 11550U, 12075U, 6390U, 24052U, 7350U,
10916 14902U, 26214U, 25192U, 22824U, 19469U, 20381U, 11017U, 13095U,
10917 15426U, 27059U, 303U, 16610U, 2286U, 22712U, 19384U, 18177U,
10918 14875U, 26187U, 23947U, 19920U, 15939U, 19058U, 23243U, 19666U,
10919 15965U, 19090U, 23269U, 19698U, 11827U, 6276U, 23917U, 7212U,
10920 10721U, 12606U, 15055U, 26532U, 10913U, 12971U, 15313U, 26926U,
10921 10357U, 11861U, 14628U, 25662U, 13150U, 6742U, 24520U, 10800U,
10922 12714U, 15162U, 7751U, 26709U, 10992U, 13079U, 15401U, 27034U,
10923 19U, 5354U, 107U, 2193U, 16470U, 5396U, 1175U, 5436U,
10924 25U, 16424U, 5364U, 254U, 16546U, 2202U, 17082U, 5446U,
10925 31U, 16433U, 15498U, 17549U, 2853U, 22752U, 19396U, 18829U,
10926 22341U, 17614U, 3298U, 22787U, 19420U, 19218U, 23572U, 11814U,
10927 6264U, 23910U, 7200U, 10703U, 12588U, 15037U, 26514U, 10895U,
10928 12953U, 15295U, 26908U, 10340U, 11843U, 14611U, 25644U, 12287U,
10929 6486U, 24200U, 10730U, 12615U, 15064U, 7470U, 26550U, 10922U,
10930 12980U, 15322U, 26935U, 11774U, 10248U, 18092U, 25199U, 7860U,
10931 6255U, 10670U, 12555U, 15004U, 26481U, 10862U, 12920U, 15262U,
10932 26875U, 17521U, 5607U, 19278U, 7072U, 25503U, 371U, 16699U,
10933 2354U, 15628U, 2989U, 18896U, 24067U, 19995U, 2231U, 15606U,
10934 2882U, 23888U, 418U, 16734U, 2401U, 15654U, 3019U, 18906U,
10935 24114U, 20024U, 635U, 16964U, 2675U, 15704U, 3193U, 18916U,
10936 24427U, 20208U, 2244U, 15617U, 2895U, 23899U, 429U, 16748U,
10937 2412U, 15663U, 3030U, 18926U, 24123U, 20036U, 10299U, 12067U,
10938 6377U, 24044U, 7337U, 14892U, 26204U, 25180U, 22814U, 19456U,
10939 20366U, 11009U, 13087U, 15418U, 27051U, 284U, 16585U, 2267U,
10940 22703U, 19372U, 18108U, 14866U, 26178U, 23932U, 19899U, 59U,
10941 5386U, 144U, 2222U, 17108U, 16486U, 5406U, 1181U, 5468U,
10942 46U, 16453U, 5375U, 264U, 16559U, 2212U, 17095U, 5457U,
10943 38U, 16443U, 15530U, 2875U, 22778U, 19408U, 18853U, 22536U,
10944 19304U, 22358U, 3305U, 22796U, 19432U, 19235U, 75U, 207U,
10945 1204U, 80U, 220U, 1209U, 23601U, 14593U, 25230U, 7870U,
10946 6873U, 16210U, 15977U, 19105U, 23281U, 19713U, 15779U, 18977U,
10947 22959U, 19566U, 14274U, 18585U, 26383U, 1893U, 14324U, 1550U,
10948 26585U, 1908U, 3420U, 14912U, 26224U, 14512U, 18729U, 14452U,
10949 1649U, 24822U, 22834U, 19482U, 22805U, 19444U, 20345U, 28478U,
10950 21038U, 25250U, 7891U, 11041U, 13126U, 15450U, 27090U, 19170U,
10951 6993U, 14192U, 1492U, 14884U, 26196U, 8140U, 14295U, 1536U,
10952 4859U, 4986U, 4173U, 3896U, 15761U, 10365U, 11884U, 14636U,
10953 25685U, 10372U, 11891U, 14643U, 25692U, 302U, 16609U, 2285U,
10954 23946U, 19919U, 283U, 16584U, 2266U, 23931U, 19898U, 23347U,
10955 3330U, 10514U, 19744U, 7138U, 25517U, 17673U, 5732U, 5054U,
10956 5095U, 23344U, 17654U, 5722U, 3331U, 10515U, 6912U, 19745U,
10957 7139U, 25518U, 27585U, 3698U, 20972U, 5194U, 14182U, 18510U,
10958 13552U, 18315U, 6804U, 11025U, 13103U, 15434U, 27067U, 10385U,
10959 11919U, 14656U, 25720U, 10832U, 12816U, 15194U, 26771U, 14150U,
10960 18477U, 9993U, 17886U, 3382U, 3430U, 22599U, 15808U, 8493U,
10961 17774U, 19012U, 22988U, 8543U, 17811U, 19601U, 15952U, 19074U,
10962 23256U, 19682U, 15794U, 8478U, 17756U, 18995U, 22974U, 8528U,
10963 17793U, 19584U, 14094U, 18445U, 25847U, 20599U, 14069U, 18429U,
10964 25876U, 20614U, 14082U, 1434U, 25832U, 1795U, 25859U, 1815U,
10965 13748U, 13353U, 18223U, 20853U, 18362U, 6815U, 8125U, 11673U,
10966 1409U, 3401U, 3439U, 10234U, 18072U, 22665U, 19336U, 23619U,
10967 3342U, 19785U, 7180U, 7156U, 492U, 16799U, 2532U, 17294U,
10968 24232U, 20090U, 14425U, 18702U, 10216U, 18048U, 14166U, 18499U,
10969 10009U, 17908U, 12824U, 6659U, 24404U, 7643U, 23578U, 25486U,
10970 20522U, 19758U, 2454U, 6429U, 24163U, 7413U, 701U, 2735U,
10971 6698U, 20588U, 24483U, 20251U, 7694U, 625U, 16951U, 2665U,
10972 17434U, 24419U, 20197U, 4814U, 4190U, 8474U, 11357U, 10765U,
10973 12659U, 15117U, 26630U, 10968U, 13035U, 15377U, 26990U, 10245U,
10974 17495U, 5526U, 2048U, 13202U, 18199U, 18086U, 5817U, 11278U,
10975 2111U, 8063U, 11459U, 8102U, 13255U, 18206U, 18138U, 6059U,
10976 8096U, 11795U, 22494U, 17624U, 5708U, 19251U, 7061U, 8155U,
10977 96U, 1964U, 5512U, 471U, 2511U, 1169U, 5426U, 8028U,
10978 1927U, 25346U, 20449U, 15849U, 23067U, 177U, 1979U, 9880U,
10979 2003U, 17837U, 14025U, 2831U, 18405U, 27447U, 3533U, 13176U,
10980 6767U, 7982U, 24535U, 7776U, 27414U, 3524U, 13161U, 6753U,
10981 7961U, 24526U, 7762U, 12223U, 6403U, 24132U, 7375U, 22946U,
10982 27579U, 14589U, 17531U, 5619U, 2842U, 13381U, 18255U, 10410U,
10983 14681U, 25819U, 22346U, 25464U, 20492U, 19226U, 14416U, 18690U,
10984 10207U, 18036U, 14364U, 18651U, 26699U, 20829U, 14158U, 18488U,
10985 10001U, 17897U, 14285U, 18599U, 26541U, 20770U, 14407U, 18678U,
10986 10198U, 1395U, 14263U, 18571U, 10099U, 1346U, 26356U, 20717U,
10987 14061U, 18418U, 9919U, 1222U, 14231U, 18558U, 10067U, 1299U,
10988 26318U, 20693U, 14434U, 1621U, 10225U, 18060U, 14174U, 1479U,
10989 10017U, 17919U, 18761U, 6865U, 13385U, 6792U, 10430U, 12112U,
10990 14701U, 25914U, 10379U, 11913U, 14650U, 25714U, 16139U, 17578U,
10991 5664U, 1039U, 3593U, 10460U, 12127U, 14716U, 25929U, 25400U,
10992 20465U, 10592U, 12236U, 14819U, 19156U, 6984U, 26032U, 24807U,
10993 3471U, 20325U, 27589U, 3704U, 20979U, 28552U, 3888U, 21060U,
10994 28466U, 3869U, 21024U, 13459U, 27574U, 10537U, 12190U, 14779U,
10995 25992U, 10817U, 12731U, 15179U, 26726U, 8560U, 10423U, 12105U,
10996 14694U, 25907U, 10490U, 12157U, 14746U, 25959U, 10625U, 12403U,
10997 14921U, 26233U, 25301U, 20431U, 10326U, 11821U, 14597U, 17830U,
10998 25629U, 16170U, 17587U, 5675U, 10467U, 12134U, 14723U, 25936U,
10999 10506U, 12173U, 14762U, 25975U, 10639U, 12423U, 14935U, 26253U,
11000 25406U, 20473U, 10598U, 12258U, 14825U, 19163U, 26054U, 22571U,
11001 19314U, 7083U, 10848U, 12857U, 15210U, 26812U, 10251U, 14126U,
11002 1451U, 14241U, 1504U, 26327U, 1863U, 25891U, 1837U, 14199U,
11003 18523U, 14304U, 18612U, 26567U, 20782U, 10957U, 13024U, 15366U,
11004 26979U, 10781U, 12695U, 15133U, 26680U, 10747U, 12641U, 15099U,
11005 26612U, 10939U, 13006U, 15348U, 26961U, 17691U, 5743U, 9969U,
11006 1253U, 10077U, 1314U, 7840U, 14391U, 1595U, 10182U, 18014U,
11007 14344U, 1565U, 10120U, 17959U, 10554U, 12207U, 14796U, 26009U,
11008 11010U, 13088U, 15419U, 27052U, 18095U, 5825U, 28445U, 21001U,
11009 189U, 1995U, 16519U, 25578U, 17728U, 5767U, 3505U, 166U,
11010 16502U, 1191U, 5488U, 8044U, 1937U, 22697U, 19363U, 13653U,
11011 18331U, 16311U, 3286U, 13434U, 18277U, 19184U, 17605U, 5697U,
11012 17034U, 19537U, 23629U, 3356U, 13534U, 18307U, 19801U, 19514U,
11013 7110U, 201U, 16537U, 20545U, 7940U, 11211U, 15468U, 18792U,
11014 6882U, 18116U, 5982U, 16029U, 19145U, 4838U, 4201U, 4299U,
11015 5005U, 5021U, 4331U, 4269U, 5160U, 5074U, 4915U, 4543U,
11016 4927U, 4570U, 5105U, 4183U, 5139U, 4276U, 5171U, 5230U,
11017 4416U, 4475U, 22950U, 15541U, 18861U, 19551U, 13367U, 15477U,
11018 25235U, 20398U, 18807U, 25214U, 20390U, 18232U, 25456U, 13775U,
11019 18370U, 20481U, 22530U, 19287U, 23203U, 19657U, 15591U, 18886U,
11020 23612U, 19775U, 25449U, 13767U, 6825U, 7920U, 22500U, 19260U,
11021 22954U, 19558U, 15585U, 18877U, 23606U, 19766U, 24811U, 15560U,
11022 20407U, 18869U, 25283U, 20416U, 20332U, 13463U, 15482U, 18815U,
11023 18292U, 2442U, 6414U, 24153U, 7398U, 689U, 2723U, 6683U,
11024 20577U, 24473U, 20238U, 7679U, 25241U, 25376U, 20457U, 25248U,
11025 70U, 25261U, 10409U, 12083U, 14680U, 25818U, 24726U, 20317U,
11026 7801U, 22671U, 19345U, 7168U, 14001U, 18397U, 6855U, 23463U,
11027 17653U, 5721U, 3336U, 10521U, 6911U, 19751U, 7147U, 25523U,
11028 27584U, 3697U, 20971U, 5205U, 11608U,
11029};
11030
11031static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {
11032 II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2893);
11033}
11034
11035} // end namespace llvm
11036#endif // GET_INSTRINFO_MC_DESC
11037
11038#ifdef GET_INSTRINFO_HEADER
11039#undef GET_INSTRINFO_HEADER
11040namespace llvm {
11041struct MipsGenInstrInfo : public TargetInstrInfo {
11042 explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
11043 ~MipsGenInstrInfo() override = default;
11044
11045};
11046} // end namespace llvm
11047#endif // GET_INSTRINFO_HEADER
11048
11049#ifdef GET_INSTRINFO_HELPER_DECLS
11050#undef GET_INSTRINFO_HELPER_DECLS
11051
11052
11053#endif // GET_INSTRINFO_HELPER_DECLS
11054
11055#ifdef GET_INSTRINFO_HELPERS
11056#undef GET_INSTRINFO_HELPERS
11057
11058#endif // GET_INSTRINFO_HELPERS
11059
11060#ifdef GET_INSTRINFO_CTOR_DTOR
11061#undef GET_INSTRINFO_CTOR_DTOR
11062namespace llvm {
11063extern const MipsInstrTable MipsDescs;
11064extern const unsigned MipsInstrNameIndices[];
11065extern const char MipsInstrNameData[];
11066MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
11067 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
11068 InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2893);
11069}
11070} // end namespace llvm
11071#endif // GET_INSTRINFO_CTOR_DTOR
11072
11073#ifdef GET_INSTRINFO_OPERAND_ENUM
11074#undef GET_INSTRINFO_OPERAND_ENUM
11075namespace llvm {
11076namespace Mips {
11077namespace OpName {
11078enum {
11079 OPERAND_LAST
11080};
11081} // end namespace OpName
11082} // end namespace Mips
11083} // end namespace llvm
11084#endif //GET_INSTRINFO_OPERAND_ENUM
11085
11086#ifdef GET_INSTRINFO_NAMED_OPS
11087#undef GET_INSTRINFO_NAMED_OPS
11088namespace llvm {
11089namespace Mips {
11090LLVM_READONLY
11091int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
11092 return -1;
11093}
11094} // end namespace Mips
11095} // end namespace llvm
11096#endif //GET_INSTRINFO_NAMED_OPS
11097
11098#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
11099#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
11100namespace llvm {
11101namespace Mips {
11102namespace OpTypes {
11103enum OperandType {
11104 InvertedImOperand = 0,
11105 InvertedImOperand64 = 1,
11106 PtrRC = 2,
11107 brtarget = 3,
11108 brtarget1SImm16 = 4,
11109 brtarget7_mm = 5,
11110 brtarget10_mm = 6,
11111 brtarget21 = 7,
11112 brtarget21_mm = 8,
11113 brtarget26 = 9,
11114 brtarget26_mm = 10,
11115 brtarget_lsl2_mm = 11,
11116 brtarget_mm = 12,
11117 brtargetr6 = 13,
11118 calloffset16 = 14,
11119 calltarget = 15,
11120 calltarget_mm = 16,
11121 condcode = 17,
11122 cpinst_operand = 18,
11123 f32imm = 19,
11124 f64imm = 20,
11125 i1imm = 21,
11126 i8imm = 22,
11127 i16imm = 23,
11128 i32imm = 24,
11129 i64imm = 25,
11130 imm64 = 26,
11131 jmpoffset16 = 27,
11132 jmptarget = 28,
11133 jmptarget_mm = 29,
11134 li16_imm = 30,
11135 mem = 31,
11136 mem16 = 32,
11137 mem16_ea = 33,
11138 mem16sp = 34,
11139 mem_ea = 35,
11140 mem_mm_4 = 36,
11141 mem_mm_4_lsl1 = 37,
11142 mem_mm_4_lsl2 = 38,
11143 mem_mm_4sp = 39,
11144 mem_mm_9 = 40,
11145 mem_mm_11 = 41,
11146 mem_mm_12 = 42,
11147 mem_mm_16 = 43,
11148 mem_mm_gp_simm7_lsl2 = 44,
11149 mem_mm_sp_imm5_lsl2 = 45,
11150 mem_msa = 46,
11151 mem_simm9 = 47,
11152 mem_simm9_exp = 48,
11153 mem_simm10 = 49,
11154 mem_simm10_lsl1 = 50,
11155 mem_simm10_lsl2 = 51,
11156 mem_simm10_lsl3 = 52,
11157 mem_simm11 = 53,
11158 mem_simm12 = 54,
11159 mem_simm16 = 55,
11160 mem_simmptr = 56,
11161 pcrel16 = 57,
11162 ptype0 = 58,
11163 ptype1 = 59,
11164 ptype2 = 60,
11165 ptype3 = 61,
11166 ptype4 = 62,
11167 ptype5 = 63,
11168 reglist = 64,
11169 reglist16 = 65,
11170 simm3_lsa2 = 66,
11171 simm4 = 67,
11172 simm5 = 68,
11173 simm6 = 69,
11174 simm7_lsl2 = 70,
11175 simm9 = 71,
11176 simm9_addiusp = 72,
11177 simm10 = 73,
11178 simm10_64 = 74,
11179 simm10_lsl1 = 75,
11180 simm10_lsl2 = 76,
11181 simm10_lsl3 = 77,
11182 simm11 = 78,
11183 simm12 = 79,
11184 simm16 = 80,
11185 simm16_64 = 81,
11186 simm16_relaxed = 82,
11187 simm18_lsl3 = 83,
11188 simm19_lsl2 = 84,
11189 simm23_lsl2 = 85,
11190 simm32 = 86,
11191 simm32_relaxed = 87,
11192 size_ins = 88,
11193 type0 = 89,
11194 type1 = 90,
11195 type2 = 91,
11196 type3 = 92,
11197 type4 = 93,
11198 type5 = 94,
11199 uimm1 = 95,
11200 uimm1_ptr = 96,
11201 uimm2 = 97,
11202 uimm2_plus1 = 98,
11203 uimm2_ptr = 99,
11204 uimm3 = 100,
11205 uimm3_ptr = 101,
11206 uimm3_shift = 102,
11207 uimm4 = 103,
11208 uimm4_andi = 104,
11209 uimm4_ptr = 105,
11210 uimm5 = 106,
11211 uimm5_64 = 107,
11212 uimm5_64_report_uimm6 = 108,
11213 uimm5_inssize_plus1 = 109,
11214 uimm5_lsl2 = 110,
11215 uimm5_plus1 = 111,
11216 uimm5_plus1_report_uimm6 = 112,
11217 uimm5_plus32 = 113,
11218 uimm5_plus32_normalize = 114,
11219 uimm5_plus32_normalize_64 = 115,
11220 uimm5_plus33 = 116,
11221 uimm5_report_uimm6 = 117,
11222 uimm6 = 118,
11223 uimm6_lsl2 = 119,
11224 uimm7 = 120,
11225 uimm8 = 121,
11226 uimm10 = 122,
11227 uimm16 = 123,
11228 uimm16_64 = 124,
11229 uimm16_64_relaxed = 125,
11230 uimm16_altrelaxed = 126,
11231 uimm16_relaxed = 127,
11232 uimm20 = 128,
11233 uimm26 = 129,
11234 uimm32_coerced = 130,
11235 uimm_range_2_64 = 131,
11236 uimmz = 132,
11237 untyped_imm_0 = 133,
11238 vsplat_simm5 = 134,
11239 vsplat_simm10 = 135,
11240 vsplat_uimm1 = 136,
11241 vsplat_uimm2 = 137,
11242 vsplat_uimm3 = 138,
11243 vsplat_uimm4 = 139,
11244 vsplat_uimm5 = 140,
11245 vsplat_uimm6 = 141,
11246 vsplat_uimm8 = 142,
11247 ACC64DSPOpnd = 143,
11248 AFGR64Opnd = 144,
11249 CCROpnd = 145,
11250 COP0Opnd = 146,
11251 COP2Opnd = 147,
11252 COP3Opnd = 148,
11253 DSPROpnd = 149,
11254 FCCRegsOpnd = 150,
11255 FGR32Opnd = 151,
11256 FGR64Opnd = 152,
11257 FGRCCOpnd = 153,
11258 GPR32NonZeroOpnd = 154,
11259 GPR32Opnd = 155,
11260 GPR32ZeroOpnd = 156,
11261 GPR64Opnd = 157,
11262 GPRMM16Opnd = 158,
11263 GPRMM16OpndMoveP = 159,
11264 GPRMM16OpndMovePPairFirst = 160,
11265 GPRMM16OpndMovePPairSecond = 161,
11266 GPRMM16OpndZero = 162,
11267 HI32DSPOpnd = 163,
11268 HWRegsOpnd = 164,
11269 LO32DSPOpnd = 165,
11270 MSA128BOpnd = 166,
11271 MSA128CROpnd = 167,
11272 MSA128DOpnd = 168,
11273 MSA128F16Opnd = 169,
11274 MSA128HOpnd = 170,
11275 MSA128WOpnd = 171,
11276 StrictlyAFGR64Opnd = 172,
11277 StrictlyFGR32Opnd = 173,
11278 StrictlyFGR64Opnd = 174,
11279 ACC64 = 175,
11280 ACC64DSP = 176,
11281 ACC128 = 177,
11282 AFGR64 = 178,
11283 CCR = 179,
11284 COP0 = 180,
11285 COP2 = 181,
11286 COP3 = 182,
11287 CPU16Regs = 183,
11288 CPU16RegsPlusSP = 184,
11289 CPURAReg = 185,
11290 CPUSPReg = 186,
11291 DSPCC = 187,
11292 DSPR = 188,
11293 FCC = 189,
11294 FGR32 = 190,
11295 FGR64 = 191,
11296 FGRCC = 192,
11297 GP32 = 193,
11298 GP64 = 194,
11299 GPR32 = 195,
11300 GPR32NONZERO = 196,
11301 GPR32ZERO = 197,
11302 GPR64 = 198,
11303 GPRMM16 = 199,
11304 GPRMM16MoveP = 200,
11305 GPRMM16MovePPairFirst = 201,
11306 GPRMM16MovePPairSecond = 202,
11307 GPRMM16Zero = 203,
11308 HI32 = 204,
11309 HI32DSP = 205,
11310 HI64 = 206,
11311 HWRegs = 207,
11312 LO32 = 208,
11313 LO32DSP = 209,
11314 LO64 = 210,
11315 MSA128B = 211,
11316 MSA128D = 212,
11317 MSA128F16 = 213,
11318 MSA128H = 214,
11319 MSA128W = 215,
11320 MSA128WEvens = 216,
11321 MSACtrl = 217,
11322 OCTEON_MPL = 218,
11323 OCTEON_P = 219,
11324 SP32 = 220,
11325 SP64 = 221,
11326 OPERAND_TYPE_LIST_END
11327};
11328} // end namespace OpTypes
11329} // end namespace Mips
11330} // end namespace llvm
11331#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
11332
11333#ifdef GET_INSTRINFO_OPERAND_TYPE
11334#undef GET_INSTRINFO_OPERAND_TYPE
11335namespace llvm {
11336namespace Mips {
11337LLVM_READONLY
11338static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
11339 static const uint16_t Offsets[] = {
11340 /* PHI */
11341 0,
11342 /* INLINEASM */
11343 1,
11344 /* INLINEASM_BR */
11345 1,
11346 /* CFI_INSTRUCTION */
11347 1,
11348 /* EH_LABEL */
11349 2,
11350 /* GC_LABEL */
11351 3,
11352 /* ANNOTATION_LABEL */
11353 4,
11354 /* KILL */
11355 5,
11356 /* EXTRACT_SUBREG */
11357 5,
11358 /* INSERT_SUBREG */
11359 8,
11360 /* IMPLICIT_DEF */
11361 12,
11362 /* SUBREG_TO_REG */
11363 13,
11364 /* COPY_TO_REGCLASS */
11365 17,
11366 /* DBG_VALUE */
11367 20,
11368 /* DBG_VALUE_LIST */
11369 20,
11370 /* DBG_INSTR_REF */
11371 20,
11372 /* DBG_PHI */
11373 20,
11374 /* DBG_LABEL */
11375 20,
11376 /* REG_SEQUENCE */
11377 21,
11378 /* COPY */
11379 23,
11380 /* BUNDLE */
11381 25,
11382 /* LIFETIME_START */
11383 25,
11384 /* LIFETIME_END */
11385 26,
11386 /* PSEUDO_PROBE */
11387 27,
11388 /* ARITH_FENCE */
11389 31,
11390 /* STACKMAP */
11391 33,
11392 /* FENTRY_CALL */
11393 35,
11394 /* PATCHPOINT */
11395 35,
11396 /* LOAD_STACK_GUARD */
11397 41,
11398 /* PREALLOCATED_SETUP */
11399 42,
11400 /* PREALLOCATED_ARG */
11401 43,
11402 /* STATEPOINT */
11403 46,
11404 /* LOCAL_ESCAPE */
11405 46,
11406 /* FAULTING_OP */
11407 48,
11408 /* PATCHABLE_OP */
11409 49,
11410 /* PATCHABLE_FUNCTION_ENTER */
11411 49,
11412 /* PATCHABLE_RET */
11413 49,
11414 /* PATCHABLE_FUNCTION_EXIT */
11415 49,
11416 /* PATCHABLE_TAIL_CALL */
11417 49,
11418 /* PATCHABLE_EVENT_CALL */
11419 49,
11420 /* PATCHABLE_TYPED_EVENT_CALL */
11421 51,
11422 /* ICALL_BRANCH_FUNNEL */
11423 54,
11424 /* MEMBARRIER */
11425 54,
11426 /* JUMP_TABLE_DEBUG_INFO */
11427 54,
11428 /* CONVERGENCECTRL_ENTRY */
11429 55,
11430 /* CONVERGENCECTRL_ANCHOR */
11431 56,
11432 /* CONVERGENCECTRL_LOOP */
11433 57,
11434 /* CONVERGENCECTRL_GLUE */
11435 59,
11436 /* G_ASSERT_SEXT */
11437 60,
11438 /* G_ASSERT_ZEXT */
11439 63,
11440 /* G_ASSERT_ALIGN */
11441 66,
11442 /* G_ADD */
11443 69,
11444 /* G_SUB */
11445 72,
11446 /* G_MUL */
11447 75,
11448 /* G_SDIV */
11449 78,
11450 /* G_UDIV */
11451 81,
11452 /* G_SREM */
11453 84,
11454 /* G_UREM */
11455 87,
11456 /* G_SDIVREM */
11457 90,
11458 /* G_UDIVREM */
11459 94,
11460 /* G_AND */
11461 98,
11462 /* G_OR */
11463 101,
11464 /* G_XOR */
11465 104,
11466 /* G_IMPLICIT_DEF */
11467 107,
11468 /* G_PHI */
11469 108,
11470 /* G_FRAME_INDEX */
11471 109,
11472 /* G_GLOBAL_VALUE */
11473 111,
11474 /* G_PTRAUTH_GLOBAL_VALUE */
11475 113,
11476 /* G_CONSTANT_POOL */
11477 118,
11478 /* G_EXTRACT */
11479 120,
11480 /* G_UNMERGE_VALUES */
11481 123,
11482 /* G_INSERT */
11483 125,
11484 /* G_MERGE_VALUES */
11485 129,
11486 /* G_BUILD_VECTOR */
11487 131,
11488 /* G_BUILD_VECTOR_TRUNC */
11489 133,
11490 /* G_CONCAT_VECTORS */
11491 135,
11492 /* G_PTRTOINT */
11493 137,
11494 /* G_INTTOPTR */
11495 139,
11496 /* G_BITCAST */
11497 141,
11498 /* G_FREEZE */
11499 143,
11500 /* G_CONSTANT_FOLD_BARRIER */
11501 145,
11502 /* G_INTRINSIC_FPTRUNC_ROUND */
11503 147,
11504 /* G_INTRINSIC_TRUNC */
11505 150,
11506 /* G_INTRINSIC_ROUND */
11507 152,
11508 /* G_INTRINSIC_LRINT */
11509 154,
11510 /* G_INTRINSIC_LLRINT */
11511 156,
11512 /* G_INTRINSIC_ROUNDEVEN */
11513 158,
11514 /* G_READCYCLECOUNTER */
11515 160,
11516 /* G_READSTEADYCOUNTER */
11517 161,
11518 /* G_LOAD */
11519 162,
11520 /* G_SEXTLOAD */
11521 164,
11522 /* G_ZEXTLOAD */
11523 166,
11524 /* G_INDEXED_LOAD */
11525 168,
11526 /* G_INDEXED_SEXTLOAD */
11527 173,
11528 /* G_INDEXED_ZEXTLOAD */
11529 178,
11530 /* G_STORE */
11531 183,
11532 /* G_INDEXED_STORE */
11533 185,
11534 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
11535 190,
11536 /* G_ATOMIC_CMPXCHG */
11537 195,
11538 /* G_ATOMICRMW_XCHG */
11539 199,
11540 /* G_ATOMICRMW_ADD */
11541 202,
11542 /* G_ATOMICRMW_SUB */
11543 205,
11544 /* G_ATOMICRMW_AND */
11545 208,
11546 /* G_ATOMICRMW_NAND */
11547 211,
11548 /* G_ATOMICRMW_OR */
11549 214,
11550 /* G_ATOMICRMW_XOR */
11551 217,
11552 /* G_ATOMICRMW_MAX */
11553 220,
11554 /* G_ATOMICRMW_MIN */
11555 223,
11556 /* G_ATOMICRMW_UMAX */
11557 226,
11558 /* G_ATOMICRMW_UMIN */
11559 229,
11560 /* G_ATOMICRMW_FADD */
11561 232,
11562 /* G_ATOMICRMW_FSUB */
11563 235,
11564 /* G_ATOMICRMW_FMAX */
11565 238,
11566 /* G_ATOMICRMW_FMIN */
11567 241,
11568 /* G_ATOMICRMW_UINC_WRAP */
11569 244,
11570 /* G_ATOMICRMW_UDEC_WRAP */
11571 247,
11572 /* G_FENCE */
11573 250,
11574 /* G_PREFETCH */
11575 252,
11576 /* G_BRCOND */
11577 256,
11578 /* G_BRINDIRECT */
11579 258,
11580 /* G_INVOKE_REGION_START */
11581 259,
11582 /* G_INTRINSIC */
11583 259,
11584 /* G_INTRINSIC_W_SIDE_EFFECTS */
11585 260,
11586 /* G_INTRINSIC_CONVERGENT */
11587 261,
11588 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
11589 262,
11590 /* G_ANYEXT */
11591 263,
11592 /* G_TRUNC */
11593 265,
11594 /* G_CONSTANT */
11595 267,
11596 /* G_FCONSTANT */
11597 269,
11598 /* G_VASTART */
11599 271,
11600 /* G_VAARG */
11601 272,
11602 /* G_SEXT */
11603 275,
11604 /* G_SEXT_INREG */
11605 277,
11606 /* G_ZEXT */
11607 280,
11608 /* G_SHL */
11609 282,
11610 /* G_LSHR */
11611 285,
11612 /* G_ASHR */
11613 288,
11614 /* G_FSHL */
11615 291,
11616 /* G_FSHR */
11617 295,
11618 /* G_ROTR */
11619 299,
11620 /* G_ROTL */
11621 302,
11622 /* G_ICMP */
11623 305,
11624 /* G_FCMP */
11625 309,
11626 /* G_SCMP */
11627 313,
11628 /* G_UCMP */
11629 316,
11630 /* G_SELECT */
11631 319,
11632 /* G_UADDO */
11633 323,
11634 /* G_UADDE */
11635 327,
11636 /* G_USUBO */
11637 332,
11638 /* G_USUBE */
11639 336,
11640 /* G_SADDO */
11641 341,
11642 /* G_SADDE */
11643 345,
11644 /* G_SSUBO */
11645 350,
11646 /* G_SSUBE */
11647 354,
11648 /* G_UMULO */
11649 359,
11650 /* G_SMULO */
11651 363,
11652 /* G_UMULH */
11653 367,
11654 /* G_SMULH */
11655 370,
11656 /* G_UADDSAT */
11657 373,
11658 /* G_SADDSAT */
11659 376,
11660 /* G_USUBSAT */
11661 379,
11662 /* G_SSUBSAT */
11663 382,
11664 /* G_USHLSAT */
11665 385,
11666 /* G_SSHLSAT */
11667 388,
11668 /* G_SMULFIX */
11669 391,
11670 /* G_UMULFIX */
11671 395,
11672 /* G_SMULFIXSAT */
11673 399,
11674 /* G_UMULFIXSAT */
11675 403,
11676 /* G_SDIVFIX */
11677 407,
11678 /* G_UDIVFIX */
11679 411,
11680 /* G_SDIVFIXSAT */
11681 415,
11682 /* G_UDIVFIXSAT */
11683 419,
11684 /* G_FADD */
11685 423,
11686 /* G_FSUB */
11687 426,
11688 /* G_FMUL */
11689 429,
11690 /* G_FMA */
11691 432,
11692 /* G_FMAD */
11693 436,
11694 /* G_FDIV */
11695 440,
11696 /* G_FREM */
11697 443,
11698 /* G_FPOW */
11699 446,
11700 /* G_FPOWI */
11701 449,
11702 /* G_FEXP */
11703 452,
11704 /* G_FEXP2 */
11705 454,
11706 /* G_FEXP10 */
11707 456,
11708 /* G_FLOG */
11709 458,
11710 /* G_FLOG2 */
11711 460,
11712 /* G_FLOG10 */
11713 462,
11714 /* G_FLDEXP */
11715 464,
11716 /* G_FFREXP */
11717 467,
11718 /* G_FNEG */
11719 470,
11720 /* G_FPEXT */
11721 472,
11722 /* G_FPTRUNC */
11723 474,
11724 /* G_FPTOSI */
11725 476,
11726 /* G_FPTOUI */
11727 478,
11728 /* G_SITOFP */
11729 480,
11730 /* G_UITOFP */
11731 482,
11732 /* G_FABS */
11733 484,
11734 /* G_FCOPYSIGN */
11735 486,
11736 /* G_IS_FPCLASS */
11737 489,
11738 /* G_FCANONICALIZE */
11739 492,
11740 /* G_FMINNUM */
11741 494,
11742 /* G_FMAXNUM */
11743 497,
11744 /* G_FMINNUM_IEEE */
11745 500,
11746 /* G_FMAXNUM_IEEE */
11747 503,
11748 /* G_FMINIMUM */
11749 506,
11750 /* G_FMAXIMUM */
11751 509,
11752 /* G_GET_FPENV */
11753 512,
11754 /* G_SET_FPENV */
11755 513,
11756 /* G_RESET_FPENV */
11757 514,
11758 /* G_GET_FPMODE */
11759 514,
11760 /* G_SET_FPMODE */
11761 515,
11762 /* G_RESET_FPMODE */
11763 516,
11764 /* G_PTR_ADD */
11765 516,
11766 /* G_PTRMASK */
11767 519,
11768 /* G_SMIN */
11769 522,
11770 /* G_SMAX */
11771 525,
11772 /* G_UMIN */
11773 528,
11774 /* G_UMAX */
11775 531,
11776 /* G_ABS */
11777 534,
11778 /* G_LROUND */
11779 536,
11780 /* G_LLROUND */
11781 538,
11782 /* G_BR */
11783 540,
11784 /* G_BRJT */
11785 541,
11786 /* G_VSCALE */
11787 544,
11788 /* G_INSERT_SUBVECTOR */
11789 546,
11790 /* G_EXTRACT_SUBVECTOR */
11791 550,
11792 /* G_INSERT_VECTOR_ELT */
11793 553,
11794 /* G_EXTRACT_VECTOR_ELT */
11795 557,
11796 /* G_SHUFFLE_VECTOR */
11797 560,
11798 /* G_SPLAT_VECTOR */
11799 564,
11800 /* G_VECTOR_COMPRESS */
11801 566,
11802 /* G_CTTZ */
11803 570,
11804 /* G_CTTZ_ZERO_UNDEF */
11805 572,
11806 /* G_CTLZ */
11807 574,
11808 /* G_CTLZ_ZERO_UNDEF */
11809 576,
11810 /* G_CTPOP */
11811 578,
11812 /* G_BSWAP */
11813 580,
11814 /* G_BITREVERSE */
11815 582,
11816 /* G_FCEIL */
11817 584,
11818 /* G_FCOS */
11819 586,
11820 /* G_FSIN */
11821 588,
11822 /* G_FTAN */
11823 590,
11824 /* G_FACOS */
11825 592,
11826 /* G_FASIN */
11827 594,
11828 /* G_FATAN */
11829 596,
11830 /* G_FCOSH */
11831 598,
11832 /* G_FSINH */
11833 600,
11834 /* G_FTANH */
11835 602,
11836 /* G_FSQRT */
11837 604,
11838 /* G_FFLOOR */
11839 606,
11840 /* G_FRINT */
11841 608,
11842 /* G_FNEARBYINT */
11843 610,
11844 /* G_ADDRSPACE_CAST */
11845 612,
11846 /* G_BLOCK_ADDR */
11847 614,
11848 /* G_JUMP_TABLE */
11849 616,
11850 /* G_DYN_STACKALLOC */
11851 618,
11852 /* G_STACKSAVE */
11853 621,
11854 /* G_STACKRESTORE */
11855 622,
11856 /* G_STRICT_FADD */
11857 623,
11858 /* G_STRICT_FSUB */
11859 626,
11860 /* G_STRICT_FMUL */
11861 629,
11862 /* G_STRICT_FDIV */
11863 632,
11864 /* G_STRICT_FREM */
11865 635,
11866 /* G_STRICT_FMA */
11867 638,
11868 /* G_STRICT_FSQRT */
11869 642,
11870 /* G_STRICT_FLDEXP */
11871 644,
11872 /* G_READ_REGISTER */
11873 647,
11874 /* G_WRITE_REGISTER */
11875 649,
11876 /* G_MEMCPY */
11877 651,
11878 /* G_MEMCPY_INLINE */
11879 655,
11880 /* G_MEMMOVE */
11881 658,
11882 /* G_MEMSET */
11883 662,
11884 /* G_BZERO */
11885 666,
11886 /* G_TRAP */
11887 669,
11888 /* G_DEBUGTRAP */
11889 669,
11890 /* G_UBSANTRAP */
11891 669,
11892 /* G_VECREDUCE_SEQ_FADD */
11893 670,
11894 /* G_VECREDUCE_SEQ_FMUL */
11895 673,
11896 /* G_VECREDUCE_FADD */
11897 676,
11898 /* G_VECREDUCE_FMUL */
11899 678,
11900 /* G_VECREDUCE_FMAX */
11901 680,
11902 /* G_VECREDUCE_FMIN */
11903 682,
11904 /* G_VECREDUCE_FMAXIMUM */
11905 684,
11906 /* G_VECREDUCE_FMINIMUM */
11907 686,
11908 /* G_VECREDUCE_ADD */
11909 688,
11910 /* G_VECREDUCE_MUL */
11911 690,
11912 /* G_VECREDUCE_AND */
11913 692,
11914 /* G_VECREDUCE_OR */
11915 694,
11916 /* G_VECREDUCE_XOR */
11917 696,
11918 /* G_VECREDUCE_SMAX */
11919 698,
11920 /* G_VECREDUCE_SMIN */
11921 700,
11922 /* G_VECREDUCE_UMAX */
11923 702,
11924 /* G_VECREDUCE_UMIN */
11925 704,
11926 /* G_SBFX */
11927 706,
11928 /* G_UBFX */
11929 710,
11930 /* ABSMacro */
11931 714,
11932 /* ADJCALLSTACKDOWN */
11933 716,
11934 /* ADJCALLSTACKUP */
11935 718,
11936 /* AND_V_D_PSEUDO */
11937 720,
11938 /* AND_V_H_PSEUDO */
11939 723,
11940 /* AND_V_W_PSEUDO */
11941 726,
11942 /* ATOMIC_CMP_SWAP_I16 */
11943 729,
11944 /* ATOMIC_CMP_SWAP_I16_POSTRA */
11945 733,
11946 /* ATOMIC_CMP_SWAP_I32 */
11947 740,
11948 /* ATOMIC_CMP_SWAP_I32_POSTRA */
11949 744,
11950 /* ATOMIC_CMP_SWAP_I64 */
11951 748,
11952 /* ATOMIC_CMP_SWAP_I64_POSTRA */
11953 752,
11954 /* ATOMIC_CMP_SWAP_I8 */
11955 756,
11956 /* ATOMIC_CMP_SWAP_I8_POSTRA */
11957 760,
11958 /* ATOMIC_LOAD_ADD_I16 */
11959 767,
11960 /* ATOMIC_LOAD_ADD_I16_POSTRA */
11961 770,
11962 /* ATOMIC_LOAD_ADD_I32 */
11963 776,
11964 /* ATOMIC_LOAD_ADD_I32_POSTRA */
11965 779,
11966 /* ATOMIC_LOAD_ADD_I64 */
11967 782,
11968 /* ATOMIC_LOAD_ADD_I64_POSTRA */
11969 785,
11970 /* ATOMIC_LOAD_ADD_I8 */
11971 788,
11972 /* ATOMIC_LOAD_ADD_I8_POSTRA */
11973 791,
11974 /* ATOMIC_LOAD_AND_I16 */
11975 797,
11976 /* ATOMIC_LOAD_AND_I16_POSTRA */
11977 800,
11978 /* ATOMIC_LOAD_AND_I32 */
11979 806,
11980 /* ATOMIC_LOAD_AND_I32_POSTRA */
11981 809,
11982 /* ATOMIC_LOAD_AND_I64 */
11983 812,
11984 /* ATOMIC_LOAD_AND_I64_POSTRA */
11985 815,
11986 /* ATOMIC_LOAD_AND_I8 */
11987 818,
11988 /* ATOMIC_LOAD_AND_I8_POSTRA */
11989 821,
11990 /* ATOMIC_LOAD_MAX_I16 */
11991 827,
11992 /* ATOMIC_LOAD_MAX_I16_POSTRA */
11993 830,
11994 /* ATOMIC_LOAD_MAX_I32 */
11995 836,
11996 /* ATOMIC_LOAD_MAX_I32_POSTRA */
11997 839,
11998 /* ATOMIC_LOAD_MAX_I64 */
11999 842,
12000 /* ATOMIC_LOAD_MAX_I64_POSTRA */
12001 845,
12002 /* ATOMIC_LOAD_MAX_I8 */
12003 848,
12004 /* ATOMIC_LOAD_MAX_I8_POSTRA */
12005 851,
12006 /* ATOMIC_LOAD_MIN_I16 */
12007 857,
12008 /* ATOMIC_LOAD_MIN_I16_POSTRA */
12009 860,
12010 /* ATOMIC_LOAD_MIN_I32 */
12011 866,
12012 /* ATOMIC_LOAD_MIN_I32_POSTRA */
12013 869,
12014 /* ATOMIC_LOAD_MIN_I64 */
12015 872,
12016 /* ATOMIC_LOAD_MIN_I64_POSTRA */
12017 875,
12018 /* ATOMIC_LOAD_MIN_I8 */
12019 878,
12020 /* ATOMIC_LOAD_MIN_I8_POSTRA */
12021 881,
12022 /* ATOMIC_LOAD_NAND_I16 */
12023 887,
12024 /* ATOMIC_LOAD_NAND_I16_POSTRA */
12025 890,
12026 /* ATOMIC_LOAD_NAND_I32 */
12027 896,
12028 /* ATOMIC_LOAD_NAND_I32_POSTRA */
12029 899,
12030 /* ATOMIC_LOAD_NAND_I64 */
12031 902,
12032 /* ATOMIC_LOAD_NAND_I64_POSTRA */
12033 905,
12034 /* ATOMIC_LOAD_NAND_I8 */
12035 908,
12036 /* ATOMIC_LOAD_NAND_I8_POSTRA */
12037 911,
12038 /* ATOMIC_LOAD_OR_I16 */
12039 917,
12040 /* ATOMIC_LOAD_OR_I16_POSTRA */
12041 920,
12042 /* ATOMIC_LOAD_OR_I32 */
12043 926,
12044 /* ATOMIC_LOAD_OR_I32_POSTRA */
12045 929,
12046 /* ATOMIC_LOAD_OR_I64 */
12047 932,
12048 /* ATOMIC_LOAD_OR_I64_POSTRA */
12049 935,
12050 /* ATOMIC_LOAD_OR_I8 */
12051 938,
12052 /* ATOMIC_LOAD_OR_I8_POSTRA */
12053 941,
12054 /* ATOMIC_LOAD_SUB_I16 */
12055 947,
12056 /* ATOMIC_LOAD_SUB_I16_POSTRA */
12057 950,
12058 /* ATOMIC_LOAD_SUB_I32 */
12059 956,
12060 /* ATOMIC_LOAD_SUB_I32_POSTRA */
12061 959,
12062 /* ATOMIC_LOAD_SUB_I64 */
12063 962,
12064 /* ATOMIC_LOAD_SUB_I64_POSTRA */
12065 965,
12066 /* ATOMIC_LOAD_SUB_I8 */
12067 968,
12068 /* ATOMIC_LOAD_SUB_I8_POSTRA */
12069 971,
12070 /* ATOMIC_LOAD_UMAX_I16 */
12071 977,
12072 /* ATOMIC_LOAD_UMAX_I16_POSTRA */
12073 980,
12074 /* ATOMIC_LOAD_UMAX_I32 */
12075 986,
12076 /* ATOMIC_LOAD_UMAX_I32_POSTRA */
12077 989,
12078 /* ATOMIC_LOAD_UMAX_I64 */
12079 992,
12080 /* ATOMIC_LOAD_UMAX_I64_POSTRA */
12081 995,
12082 /* ATOMIC_LOAD_UMAX_I8 */
12083 998,
12084 /* ATOMIC_LOAD_UMAX_I8_POSTRA */
12085 1001,
12086 /* ATOMIC_LOAD_UMIN_I16 */
12087 1007,
12088 /* ATOMIC_LOAD_UMIN_I16_POSTRA */
12089 1010,
12090 /* ATOMIC_LOAD_UMIN_I32 */
12091 1016,
12092 /* ATOMIC_LOAD_UMIN_I32_POSTRA */
12093 1019,
12094 /* ATOMIC_LOAD_UMIN_I64 */
12095 1022,
12096 /* ATOMIC_LOAD_UMIN_I64_POSTRA */
12097 1025,
12098 /* ATOMIC_LOAD_UMIN_I8 */
12099 1028,
12100 /* ATOMIC_LOAD_UMIN_I8_POSTRA */
12101 1031,
12102 /* ATOMIC_LOAD_XOR_I16 */
12103 1037,
12104 /* ATOMIC_LOAD_XOR_I16_POSTRA */
12105 1040,
12106 /* ATOMIC_LOAD_XOR_I32 */
12107 1046,
12108 /* ATOMIC_LOAD_XOR_I32_POSTRA */
12109 1049,
12110 /* ATOMIC_LOAD_XOR_I64 */
12111 1052,
12112 /* ATOMIC_LOAD_XOR_I64_POSTRA */
12113 1055,
12114 /* ATOMIC_LOAD_XOR_I8 */
12115 1058,
12116 /* ATOMIC_LOAD_XOR_I8_POSTRA */
12117 1061,
12118 /* ATOMIC_SWAP_I16 */
12119 1067,
12120 /* ATOMIC_SWAP_I16_POSTRA */
12121 1070,
12122 /* ATOMIC_SWAP_I32 */
12123 1076,
12124 /* ATOMIC_SWAP_I32_POSTRA */
12125 1079,
12126 /* ATOMIC_SWAP_I64 */
12127 1082,
12128 /* ATOMIC_SWAP_I64_POSTRA */
12129 1085,
12130 /* ATOMIC_SWAP_I8 */
12131 1088,
12132 /* ATOMIC_SWAP_I8_POSTRA */
12133 1091,
12134 /* B */
12135 1097,
12136 /* BAL_BR */
12137 1098,
12138 /* BAL_BR_MM */
12139 1099,
12140 /* BEQLImmMacro */
12141 1100,
12142 /* BGE */
12143 1103,
12144 /* BGEImmMacro */
12145 1106,
12146 /* BGEL */
12147 1109,
12148 /* BGELImmMacro */
12149 1112,
12150 /* BGEU */
12151 1115,
12152 /* BGEUImmMacro */
12153 1118,
12154 /* BGEUL */
12155 1121,
12156 /* BGEULImmMacro */
12157 1124,
12158 /* BGT */
12159 1127,
12160 /* BGTImmMacro */
12161 1130,
12162 /* BGTL */
12163 1133,
12164 /* BGTLImmMacro */
12165 1136,
12166 /* BGTU */
12167 1139,
12168 /* BGTUImmMacro */
12169 1142,
12170 /* BGTUL */
12171 1145,
12172 /* BGTULImmMacro */
12173 1148,
12174 /* BLE */
12175 1151,
12176 /* BLEImmMacro */
12177 1154,
12178 /* BLEL */
12179 1157,
12180 /* BLELImmMacro */
12181 1160,
12182 /* BLEU */
12183 1163,
12184 /* BLEUImmMacro */
12185 1166,
12186 /* BLEUL */
12187 1169,
12188 /* BLEULImmMacro */
12189 1172,
12190 /* BLT */
12191 1175,
12192 /* BLTImmMacro */
12193 1178,
12194 /* BLTL */
12195 1181,
12196 /* BLTLImmMacro */
12197 1184,
12198 /* BLTU */
12199 1187,
12200 /* BLTUImmMacro */
12201 1190,
12202 /* BLTUL */
12203 1193,
12204 /* BLTULImmMacro */
12205 1196,
12206 /* BNELImmMacro */
12207 1199,
12208 /* BPOSGE32_PSEUDO */
12209 1202,
12210 /* BSEL_D_PSEUDO */
12211 1203,
12212 /* BSEL_FD_PSEUDO */
12213 1207,
12214 /* BSEL_FW_PSEUDO */
12215 1211,
12216 /* BSEL_H_PSEUDO */
12217 1215,
12218 /* BSEL_W_PSEUDO */
12219 1219,
12220 /* B_MM */
12221 1223,
12222 /* B_MMR6_Pseudo */
12223 1224,
12224 /* B_MM_Pseudo */
12225 1225,
12226 /* BeqImm */
12227 1226,
12228 /* BneImm */
12229 1229,
12230 /* BteqzT8CmpX16 */
12231 1232,
12232 /* BteqzT8CmpiX16 */
12233 1235,
12234 /* BteqzT8SltX16 */
12235 1238,
12236 /* BteqzT8SltiX16 */
12237 1241,
12238 /* BteqzT8SltiuX16 */
12239 1244,
12240 /* BteqzT8SltuX16 */
12241 1247,
12242 /* BtnezT8CmpX16 */
12243 1250,
12244 /* BtnezT8CmpiX16 */
12245 1253,
12246 /* BtnezT8SltX16 */
12247 1256,
12248 /* BtnezT8SltiX16 */
12249 1259,
12250 /* BtnezT8SltiuX16 */
12251 1262,
12252 /* BtnezT8SltuX16 */
12253 1265,
12254 /* BuildPairF64 */
12255 1268,
12256 /* BuildPairF64_64 */
12257 1271,
12258 /* CFTC1 */
12259 1274,
12260 /* CONSTPOOL_ENTRY */
12261 1276,
12262 /* COPY_FD_PSEUDO */
12263 1279,
12264 /* COPY_FW_PSEUDO */
12265 1282,
12266 /* CTTC1 */
12267 1285,
12268 /* Constant32 */
12269 1287,
12270 /* DMULImmMacro */
12271 1288,
12272 /* DMULMacro */
12273 1291,
12274 /* DMULOMacro */
12275 1294,
12276 /* DMULOUMacro */
12277 1297,
12278 /* DROL */
12279 1300,
12280 /* DROLImm */
12281 1303,
12282 /* DROR */
12283 1306,
12284 /* DRORImm */
12285 1309,
12286 /* DSDivIMacro */
12287 1312,
12288 /* DSDivMacro */
12289 1315,
12290 /* DSRemIMacro */
12291 1318,
12292 /* DSRemMacro */
12293 1321,
12294 /* DUDivIMacro */
12295 1324,
12296 /* DUDivMacro */
12297 1327,
12298 /* DURemIMacro */
12299 1330,
12300 /* DURemMacro */
12301 1333,
12302 /* ERet */
12303 1336,
12304 /* ExtractElementF64 */
12305 1336,
12306 /* ExtractElementF64_64 */
12307 1339,
12308 /* FABS_D */
12309 1342,
12310 /* FABS_W */
12311 1344,
12312 /* FEXP2_D_1_PSEUDO */
12313 1346,
12314 /* FEXP2_W_1_PSEUDO */
12315 1348,
12316 /* FILL_FD_PSEUDO */
12317 1350,
12318 /* FILL_FW_PSEUDO */
12319 1352,
12320 /* GotPrologue16 */
12321 1354,
12322 /* INSERT_B_VIDX64_PSEUDO */
12323 1358,
12324 /* INSERT_B_VIDX_PSEUDO */
12325 1362,
12326 /* INSERT_D_VIDX64_PSEUDO */
12327 1366,
12328 /* INSERT_D_VIDX_PSEUDO */
12329 1370,
12330 /* INSERT_FD_PSEUDO */
12331 1374,
12332 /* INSERT_FD_VIDX64_PSEUDO */
12333 1378,
12334 /* INSERT_FD_VIDX_PSEUDO */
12335 1382,
12336 /* INSERT_FW_PSEUDO */
12337 1386,
12338 /* INSERT_FW_VIDX64_PSEUDO */
12339 1390,
12340 /* INSERT_FW_VIDX_PSEUDO */
12341 1394,
12342 /* INSERT_H_VIDX64_PSEUDO */
12343 1398,
12344 /* INSERT_H_VIDX_PSEUDO */
12345 1402,
12346 /* INSERT_W_VIDX64_PSEUDO */
12347 1406,
12348 /* INSERT_W_VIDX_PSEUDO */
12349 1410,
12350 /* JALR64Pseudo */
12351 1414,
12352 /* JALRHB64Pseudo */
12353 1415,
12354 /* JALRHBPseudo */
12355 1416,
12356 /* JALRPseudo */
12357 1417,
12358 /* JAL_MMR6 */
12359 1418,
12360 /* JalOneReg */
12361 1419,
12362 /* JalTwoReg */
12363 1420,
12364 /* LDMacro */
12365 1422,
12366 /* LDR_D */
12367 1425,
12368 /* LDR_W */
12369 1428,
12370 /* LD_F16 */
12371 1431,
12372 /* LOAD_ACC128 */
12373 1434,
12374 /* LOAD_ACC64 */
12375 1437,
12376 /* LOAD_ACC64DSP */
12377 1440,
12378 /* LOAD_CCOND_DSP */
12379 1443,
12380 /* LONG_BRANCH_ADDiu */
12381 1446,
12382 /* LONG_BRANCH_ADDiu2Op */
12383 1450,
12384 /* LONG_BRANCH_DADDiu */
12385 1453,
12386 /* LONG_BRANCH_DADDiu2Op */
12387 1457,
12388 /* LONG_BRANCH_LUi */
12389 1460,
12390 /* LONG_BRANCH_LUi2Op */
12391 1463,
12392 /* LONG_BRANCH_LUi2Op_64 */
12393 1465,
12394 /* LWM_MM */
12395 1467,
12396 /* LoadAddrImm32 */
12397 1470,
12398 /* LoadAddrImm64 */
12399 1472,
12400 /* LoadAddrReg32 */
12401 1474,
12402 /* LoadAddrReg64 */
12403 1477,
12404 /* LoadImm32 */
12405 1480,
12406 /* LoadImm64 */
12407 1482,
12408 /* LoadImmDoubleFGR */
12409 1484,
12410 /* LoadImmDoubleFGR_32 */
12411 1486,
12412 /* LoadImmDoubleGPR */
12413 1488,
12414 /* LoadImmSingleFGR */
12415 1490,
12416 /* LoadImmSingleGPR */
12417 1492,
12418 /* LwConstant32 */
12419 1494,
12420 /* MFTACX */
12421 1497,
12422 /* MFTC0 */
12423 1499,
12424 /* MFTC1 */
12425 1502,
12426 /* MFTDSP */
12427 1504,
12428 /* MFTGPR */
12429 1505,
12430 /* MFTHC1 */
12431 1508,
12432 /* MFTHI */
12433 1510,
12434 /* MFTLO */
12435 1512,
12436 /* MIPSeh_return32 */
12437 1514,
12438 /* MIPSeh_return64 */
12439 1516,
12440 /* MSA_FP_EXTEND_D_PSEUDO */
12441 1518,
12442 /* MSA_FP_EXTEND_W_PSEUDO */
12443 1520,
12444 /* MSA_FP_ROUND_D_PSEUDO */
12445 1522,
12446 /* MSA_FP_ROUND_W_PSEUDO */
12447 1524,
12448 /* MTTACX */
12449 1526,
12450 /* MTTC0 */
12451 1528,
12452 /* MTTC1 */
12453 1531,
12454 /* MTTDSP */
12455 1533,
12456 /* MTTGPR */
12457 1534,
12458 /* MTTHC1 */
12459 1536,
12460 /* MTTHI */
12461 1538,
12462 /* MTTLO */
12463 1540,
12464 /* MULImmMacro */
12465 1542,
12466 /* MULOMacro */
12467 1545,
12468 /* MULOUMacro */
12469 1548,
12470 /* MultRxRy16 */
12471 1551,
12472 /* MultRxRyRz16 */
12473 1553,
12474 /* MultuRxRy16 */
12475 1556,
12476 /* MultuRxRyRz16 */
12477 1558,
12478 /* NOP */
12479 1561,
12480 /* NORImm */
12481 1561,
12482 /* NORImm64 */
12483 1564,
12484 /* NOR_V_D_PSEUDO */
12485 1567,
12486 /* NOR_V_H_PSEUDO */
12487 1570,
12488 /* NOR_V_W_PSEUDO */
12489 1573,
12490 /* OR_V_D_PSEUDO */
12491 1576,
12492 /* OR_V_H_PSEUDO */
12493 1579,
12494 /* OR_V_W_PSEUDO */
12495 1582,
12496 /* PseudoCMPU_EQ_QB */
12497 1585,
12498 /* PseudoCMPU_LE_QB */
12499 1588,
12500 /* PseudoCMPU_LT_QB */
12501 1591,
12502 /* PseudoCMP_EQ_PH */
12503 1594,
12504 /* PseudoCMP_LE_PH */
12505 1597,
12506 /* PseudoCMP_LT_PH */
12507 1600,
12508 /* PseudoCVT_D32_W */
12509 1603,
12510 /* PseudoCVT_D64_L */
12511 1605,
12512 /* PseudoCVT_D64_W */
12513 1607,
12514 /* PseudoCVT_S_L */
12515 1609,
12516 /* PseudoCVT_S_W */
12517 1611,
12518 /* PseudoDMULT */
12519 1613,
12520 /* PseudoDMULTu */
12521 1616,
12522 /* PseudoDSDIV */
12523 1619,
12524 /* PseudoDUDIV */
12525 1622,
12526 /* PseudoD_SELECT_I */
12527 1625,
12528 /* PseudoD_SELECT_I64 */
12529 1632,
12530 /* PseudoIndirectBranch */
12531 1639,
12532 /* PseudoIndirectBranch64 */
12533 1640,
12534 /* PseudoIndirectBranch64R6 */
12535 1641,
12536 /* PseudoIndirectBranchR6 */
12537 1642,
12538 /* PseudoIndirectBranch_MM */
12539 1643,
12540 /* PseudoIndirectBranch_MMR6 */
12541 1644,
12542 /* PseudoIndirectHazardBranch */
12543 1645,
12544 /* PseudoIndirectHazardBranch64 */
12545 1646,
12546 /* PseudoIndrectHazardBranch64R6 */
12547 1647,
12548 /* PseudoIndrectHazardBranchR6 */
12549 1648,
12550 /* PseudoMADD */
12551 1649,
12552 /* PseudoMADDU */
12553 1653,
12554 /* PseudoMADDU_MM */
12555 1657,
12556 /* PseudoMADD_MM */
12557 1661,
12558 /* PseudoMFHI */
12559 1665,
12560 /* PseudoMFHI64 */
12561 1667,
12562 /* PseudoMFHI_MM */
12563 1669,
12564 /* PseudoMFLO */
12565 1671,
12566 /* PseudoMFLO64 */
12567 1673,
12568 /* PseudoMFLO_MM */
12569 1675,
12570 /* PseudoMSUB */
12571 1677,
12572 /* PseudoMSUBU */
12573 1681,
12574 /* PseudoMSUBU_MM */
12575 1685,
12576 /* PseudoMSUB_MM */
12577 1689,
12578 /* PseudoMTLOHI */
12579 1693,
12580 /* PseudoMTLOHI64 */
12581 1696,
12582 /* PseudoMTLOHI_DSP */
12583 1699,
12584 /* PseudoMTLOHI_MM */
12585 1702,
12586 /* PseudoMULT */
12587 1705,
12588 /* PseudoMULT_MM */
12589 1708,
12590 /* PseudoMULTu */
12591 1711,
12592 /* PseudoMULTu_MM */
12593 1714,
12594 /* PseudoPICK_PH */
12595 1717,
12596 /* PseudoPICK_QB */
12597 1721,
12598 /* PseudoReturn */
12599 1725,
12600 /* PseudoReturn64 */
12601 1726,
12602 /* PseudoSDIV */
12603 1727,
12604 /* PseudoSELECTFP_F_D32 */
12605 1730,
12606 /* PseudoSELECTFP_F_D64 */
12607 1734,
12608 /* PseudoSELECTFP_F_I */
12609 1738,
12610 /* PseudoSELECTFP_F_I64 */
12611 1742,
12612 /* PseudoSELECTFP_F_S */
12613 1746,
12614 /* PseudoSELECTFP_T_D32 */
12615 1750,
12616 /* PseudoSELECTFP_T_D64 */
12617 1754,
12618 /* PseudoSELECTFP_T_I */
12619 1758,
12620 /* PseudoSELECTFP_T_I64 */
12621 1762,
12622 /* PseudoSELECTFP_T_S */
12623 1766,
12624 /* PseudoSELECT_D32 */
12625 1770,
12626 /* PseudoSELECT_D64 */
12627 1774,
12628 /* PseudoSELECT_I */
12629 1778,
12630 /* PseudoSELECT_I64 */
12631 1782,
12632 /* PseudoSELECT_S */
12633 1786,
12634 /* PseudoTRUNC_W_D */
12635 1790,
12636 /* PseudoTRUNC_W_D32 */
12637 1793,
12638 /* PseudoTRUNC_W_S */
12639 1796,
12640 /* PseudoUDIV */
12641 1799,
12642 /* ROL */
12643 1802,
12644 /* ROLImm */
12645 1805,
12646 /* ROR */
12647 1808,
12648 /* RORImm */
12649 1811,
12650 /* RetRA */
12651 1814,
12652 /* RetRA16 */
12653 1814,
12654 /* SDC1_M1 */
12655 1814,
12656 /* SDIV_MM_Pseudo */
12657 1817,
12658 /* SDMacro */
12659 1820,
12660 /* SDivIMacro */
12661 1823,
12662 /* SDivMacro */
12663 1826,
12664 /* SEQIMacro */
12665 1829,
12666 /* SEQMacro */
12667 1832,
12668 /* SGE */
12669 1835,
12670 /* SGEImm */
12671 1838,
12672 /* SGEImm64 */
12673 1841,
12674 /* SGEU */
12675 1844,
12676 /* SGEUImm */
12677 1847,
12678 /* SGEUImm64 */
12679 1850,
12680 /* SGTImm */
12681 1853,
12682 /* SGTImm64 */
12683 1856,
12684 /* SGTUImm */
12685 1859,
12686 /* SGTUImm64 */
12687 1862,
12688 /* SLE */
12689 1865,
12690 /* SLEImm */
12691 1868,
12692 /* SLEImm64 */
12693 1871,
12694 /* SLEU */
12695 1874,
12696 /* SLEUImm */
12697 1877,
12698 /* SLEUImm64 */
12699 1880,
12700 /* SLTImm64 */
12701 1883,
12702 /* SLTUImm64 */
12703 1886,
12704 /* SNEIMacro */
12705 1889,
12706 /* SNEMacro */
12707 1892,
12708 /* SNZ_B_PSEUDO */
12709 1895,
12710 /* SNZ_D_PSEUDO */
12711 1897,
12712 /* SNZ_H_PSEUDO */
12713 1899,
12714 /* SNZ_V_PSEUDO */
12715 1901,
12716 /* SNZ_W_PSEUDO */
12717 1903,
12718 /* SRemIMacro */
12719 1905,
12720 /* SRemMacro */
12721 1908,
12722 /* STORE_ACC128 */
12723 1911,
12724 /* STORE_ACC64 */
12725 1914,
12726 /* STORE_ACC64DSP */
12727 1917,
12728 /* STORE_CCOND_DSP */
12729 1920,
12730 /* STR_D */
12731 1923,
12732 /* STR_W */
12733 1926,
12734 /* ST_F16 */
12735 1929,
12736 /* SWM_MM */
12737 1932,
12738 /* SZ_B_PSEUDO */
12739 1935,
12740 /* SZ_D_PSEUDO */
12741 1937,
12742 /* SZ_H_PSEUDO */
12743 1939,
12744 /* SZ_V_PSEUDO */
12745 1941,
12746 /* SZ_W_PSEUDO */
12747 1943,
12748 /* SaaAddr */
12749 1945,
12750 /* SaadAddr */
12751 1948,
12752 /* SelBeqZ */
12753 1951,
12754 /* SelBneZ */
12755 1955,
12756 /* SelTBteqZCmp */
12757 1959,
12758 /* SelTBteqZCmpi */
12759 1964,
12760 /* SelTBteqZSlt */
12761 1969,
12762 /* SelTBteqZSlti */
12763 1974,
12764 /* SelTBteqZSltiu */
12765 1979,
12766 /* SelTBteqZSltu */
12767 1984,
12768 /* SelTBtneZCmp */
12769 1989,
12770 /* SelTBtneZCmpi */
12771 1994,
12772 /* SelTBtneZSlt */
12773 1999,
12774 /* SelTBtneZSlti */
12775 2004,
12776 /* SelTBtneZSltiu */
12777 2009,
12778 /* SelTBtneZSltu */
12779 2014,
12780 /* SltCCRxRy16 */
12781 2019,
12782 /* SltiCCRxImmX16 */
12783 2022,
12784 /* SltiuCCRxImmX16 */
12785 2025,
12786 /* SltuCCRxRy16 */
12787 2028,
12788 /* SltuRxRyRz16 */
12789 2031,
12790 /* TAILCALL */
12791 2034,
12792 /* TAILCALL64R6REG */
12793 2035,
12794 /* TAILCALLHB64R6REG */
12795 2036,
12796 /* TAILCALLHBR6REG */
12797 2037,
12798 /* TAILCALLR6REG */
12799 2038,
12800 /* TAILCALLREG */
12801 2039,
12802 /* TAILCALLREG64 */
12803 2040,
12804 /* TAILCALLREGHB */
12805 2041,
12806 /* TAILCALLREGHB64 */
12807 2042,
12808 /* TAILCALLREG_MM */
12809 2043,
12810 /* TAILCALLREG_MMR6 */
12811 2044,
12812 /* TAILCALL_MM */
12813 2045,
12814 /* TAILCALL_MMR6 */
12815 2046,
12816 /* TRAP */
12817 2047,
12818 /* TRAP_MM */
12819 2047,
12820 /* UDIV_MM_Pseudo */
12821 2047,
12822 /* UDivIMacro */
12823 2050,
12824 /* UDivMacro */
12825 2053,
12826 /* URemIMacro */
12827 2056,
12828 /* URemMacro */
12829 2059,
12830 /* Ulh */
12831 2062,
12832 /* Ulhu */
12833 2065,
12834 /* Ulw */
12835 2068,
12836 /* Ush */
12837 2071,
12838 /* Usw */
12839 2074,
12840 /* XOR_V_D_PSEUDO */
12841 2077,
12842 /* XOR_V_H_PSEUDO */
12843 2080,
12844 /* XOR_V_W_PSEUDO */
12845 2083,
12846 /* ABSQ_S_PH */
12847 2086,
12848 /* ABSQ_S_PH_MM */
12849 2088,
12850 /* ABSQ_S_QB */
12851 2090,
12852 /* ABSQ_S_QB_MMR2 */
12853 2092,
12854 /* ABSQ_S_W */
12855 2094,
12856 /* ABSQ_S_W_MM */
12857 2096,
12858 /* ADD */
12859 2098,
12860 /* ADDIUPC */
12861 2101,
12862 /* ADDIUPC_MM */
12863 2103,
12864 /* ADDIUPC_MMR6 */
12865 2105,
12866 /* ADDIUR1SP_MM */
12867 2107,
12868 /* ADDIUR2_MM */
12869 2109,
12870 /* ADDIUS5_MM */
12871 2112,
12872 /* ADDIUSP_MM */
12873 2115,
12874 /* ADDIU_MMR6 */
12875 2116,
12876 /* ADDQH_PH */
12877 2119,
12878 /* ADDQH_PH_MMR2 */
12879 2122,
12880 /* ADDQH_R_PH */
12881 2125,
12882 /* ADDQH_R_PH_MMR2 */
12883 2128,
12884 /* ADDQH_R_W */
12885 2131,
12886 /* ADDQH_R_W_MMR2 */
12887 2134,
12888 /* ADDQH_W */
12889 2137,
12890 /* ADDQH_W_MMR2 */
12891 2140,
12892 /* ADDQ_PH */
12893 2143,
12894 /* ADDQ_PH_MM */
12895 2146,
12896 /* ADDQ_S_PH */
12897 2149,
12898 /* ADDQ_S_PH_MM */
12899 2152,
12900 /* ADDQ_S_W */
12901 2155,
12902 /* ADDQ_S_W_MM */
12903 2158,
12904 /* ADDR_PS64 */
12905 2161,
12906 /* ADDSC */
12907 2164,
12908 /* ADDSC_MM */
12909 2167,
12910 /* ADDS_A_B */
12911 2170,
12912 /* ADDS_A_D */
12913 2173,
12914 /* ADDS_A_H */
12915 2176,
12916 /* ADDS_A_W */
12917 2179,
12918 /* ADDS_S_B */
12919 2182,
12920 /* ADDS_S_D */
12921 2185,
12922 /* ADDS_S_H */
12923 2188,
12924 /* ADDS_S_W */
12925 2191,
12926 /* ADDS_U_B */
12927 2194,
12928 /* ADDS_U_D */
12929 2197,
12930 /* ADDS_U_H */
12931 2200,
12932 /* ADDS_U_W */
12933 2203,
12934 /* ADDU16_MM */
12935 2206,
12936 /* ADDU16_MMR6 */
12937 2209,
12938 /* ADDUH_QB */
12939 2212,
12940 /* ADDUH_QB_MMR2 */
12941 2215,
12942 /* ADDUH_R_QB */
12943 2218,
12944 /* ADDUH_R_QB_MMR2 */
12945 2221,
12946 /* ADDU_MMR6 */
12947 2224,
12948 /* ADDU_PH */
12949 2227,
12950 /* ADDU_PH_MMR2 */
12951 2230,
12952 /* ADDU_QB */
12953 2233,
12954 /* ADDU_QB_MM */
12955 2236,
12956 /* ADDU_S_PH */
12957 2239,
12958 /* ADDU_S_PH_MMR2 */
12959 2242,
12960 /* ADDU_S_QB */
12961 2245,
12962 /* ADDU_S_QB_MM */
12963 2248,
12964 /* ADDVI_B */
12965 2251,
12966 /* ADDVI_D */
12967 2254,
12968 /* ADDVI_H */
12969 2257,
12970 /* ADDVI_W */
12971 2260,
12972 /* ADDV_B */
12973 2263,
12974 /* ADDV_D */
12975 2266,
12976 /* ADDV_H */
12977 2269,
12978 /* ADDV_W */
12979 2272,
12980 /* ADDWC */
12981 2275,
12982 /* ADDWC_MM */
12983 2278,
12984 /* ADD_A_B */
12985 2281,
12986 /* ADD_A_D */
12987 2284,
12988 /* ADD_A_H */
12989 2287,
12990 /* ADD_A_W */
12991 2290,
12992 /* ADD_MM */
12993 2293,
12994 /* ADD_MMR6 */
12995 2296,
12996 /* ADDi */
12997 2299,
12998 /* ADDi_MM */
12999 2302,
13000 /* ADDiu */
13001 2305,
13002 /* ADDiu_MM */
13003 2308,
13004 /* ADDu */
13005 2311,
13006 /* ADDu_MM */
13007 2314,
13008 /* ALIGN */
13009 2317,
13010 /* ALIGN_MMR6 */
13011 2321,
13012 /* ALUIPC */
13013 2325,
13014 /* ALUIPC_MMR6 */
13015 2327,
13016 /* AND */
13017 2329,
13018 /* AND16_MM */
13019 2332,
13020 /* AND16_MMR6 */
13021 2335,
13022 /* AND64 */
13023 2338,
13024 /* ANDI16_MM */
13025 2341,
13026 /* ANDI16_MMR6 */
13027 2344,
13028 /* ANDI_B */
13029 2347,
13030 /* ANDI_MMR6 */
13031 2350,
13032 /* AND_MM */
13033 2353,
13034 /* AND_MMR6 */
13035 2356,
13036 /* AND_V */
13037 2359,
13038 /* ANDi */
13039 2362,
13040 /* ANDi64 */
13041 2365,
13042 /* ANDi_MM */
13043 2368,
13044 /* APPEND */
13045 2371,
13046 /* APPEND_MMR2 */
13047 2375,
13048 /* ASUB_S_B */
13049 2379,
13050 /* ASUB_S_D */
13051 2382,
13052 /* ASUB_S_H */
13053 2385,
13054 /* ASUB_S_W */
13055 2388,
13056 /* ASUB_U_B */
13057 2391,
13058 /* ASUB_U_D */
13059 2394,
13060 /* ASUB_U_H */
13061 2397,
13062 /* ASUB_U_W */
13063 2400,
13064 /* AUI */
13065 2403,
13066 /* AUIPC */
13067 2406,
13068 /* AUIPC_MMR6 */
13069 2408,
13070 /* AUI_MMR6 */
13071 2410,
13072 /* AVER_S_B */
13073 2413,
13074 /* AVER_S_D */
13075 2416,
13076 /* AVER_S_H */
13077 2419,
13078 /* AVER_S_W */
13079 2422,
13080 /* AVER_U_B */
13081 2425,
13082 /* AVER_U_D */
13083 2428,
13084 /* AVER_U_H */
13085 2431,
13086 /* AVER_U_W */
13087 2434,
13088 /* AVE_S_B */
13089 2437,
13090 /* AVE_S_D */
13091 2440,
13092 /* AVE_S_H */
13093 2443,
13094 /* AVE_S_W */
13095 2446,
13096 /* AVE_U_B */
13097 2449,
13098 /* AVE_U_D */
13099 2452,
13100 /* AVE_U_H */
13101 2455,
13102 /* AVE_U_W */
13103 2458,
13104 /* AddiuRxImmX16 */
13105 2461,
13106 /* AddiuRxPcImmX16 */
13107 2463,
13108 /* AddiuRxRxImm16 */
13109 2465,
13110 /* AddiuRxRxImmX16 */
13111 2468,
13112 /* AddiuRxRyOffMemX16 */
13113 2471,
13114 /* AddiuSpImm16 */
13115 2474,
13116 /* AddiuSpImmX16 */
13117 2475,
13118 /* AdduRxRyRz16 */
13119 2476,
13120 /* AndRxRxRy16 */
13121 2479,
13122 /* B16_MM */
13123 2482,
13124 /* BADDu */
13125 2483,
13126 /* BAL */
13127 2486,
13128 /* BALC */
13129 2487,
13130 /* BALC_MMR6 */
13131 2488,
13132 /* BALIGN */
13133 2489,
13134 /* BALIGN_MMR2 */
13135 2493,
13136 /* BBIT0 */
13137 2497,
13138 /* BBIT032 */
13139 2500,
13140 /* BBIT1 */
13141 2503,
13142 /* BBIT132 */
13143 2506,
13144 /* BC */
13145 2509,
13146 /* BC16_MMR6 */
13147 2510,
13148 /* BC1EQZ */
13149 2511,
13150 /* BC1EQZC_MMR6 */
13151 2513,
13152 /* BC1F */
13153 2515,
13154 /* BC1FL */
13155 2517,
13156 /* BC1F_MM */
13157 2519,
13158 /* BC1NEZ */
13159 2521,
13160 /* BC1NEZC_MMR6 */
13161 2523,
13162 /* BC1T */
13163 2525,
13164 /* BC1TL */
13165 2527,
13166 /* BC1T_MM */
13167 2529,
13168 /* BC2EQZ */
13169 2531,
13170 /* BC2EQZC_MMR6 */
13171 2533,
13172 /* BC2NEZ */
13173 2535,
13174 /* BC2NEZC_MMR6 */
13175 2537,
13176 /* BCLRI_B */
13177 2539,
13178 /* BCLRI_D */
13179 2542,
13180 /* BCLRI_H */
13181 2545,
13182 /* BCLRI_W */
13183 2548,
13184 /* BCLR_B */
13185 2551,
13186 /* BCLR_D */
13187 2554,
13188 /* BCLR_H */
13189 2557,
13190 /* BCLR_W */
13191 2560,
13192 /* BC_MMR6 */
13193 2563,
13194 /* BEQ */
13195 2564,
13196 /* BEQ64 */
13197 2567,
13198 /* BEQC */
13199 2570,
13200 /* BEQC64 */
13201 2573,
13202 /* BEQC_MMR6 */
13203 2576,
13204 /* BEQL */
13205 2579,
13206 /* BEQZ16_MM */
13207 2582,
13208 /* BEQZALC */
13209 2584,
13210 /* BEQZALC_MMR6 */
13211 2586,
13212 /* BEQZC */
13213 2588,
13214 /* BEQZC16_MMR6 */
13215 2590,
13216 /* BEQZC64 */
13217 2592,
13218 /* BEQZC_MM */
13219 2594,
13220 /* BEQZC_MMR6 */
13221 2596,
13222 /* BEQ_MM */
13223 2598,
13224 /* BGEC */
13225 2601,
13226 /* BGEC64 */
13227 2604,
13228 /* BGEC_MMR6 */
13229 2607,
13230 /* BGEUC */
13231 2610,
13232 /* BGEUC64 */
13233 2613,
13234 /* BGEUC_MMR6 */
13235 2616,
13236 /* BGEZ */
13237 2619,
13238 /* BGEZ64 */
13239 2621,
13240 /* BGEZAL */
13241 2623,
13242 /* BGEZALC */
13243 2625,
13244 /* BGEZALC_MMR6 */
13245 2627,
13246 /* BGEZALL */
13247 2629,
13248 /* BGEZALS_MM */
13249 2631,
13250 /* BGEZAL_MM */
13251 2633,
13252 /* BGEZC */
13253 2635,
13254 /* BGEZC64 */
13255 2637,
13256 /* BGEZC_MMR6 */
13257 2639,
13258 /* BGEZL */
13259 2641,
13260 /* BGEZ_MM */
13261 2643,
13262 /* BGTZ */
13263 2645,
13264 /* BGTZ64 */
13265 2647,
13266 /* BGTZALC */
13267 2649,
13268 /* BGTZALC_MMR6 */
13269 2651,
13270 /* BGTZC */
13271 2653,
13272 /* BGTZC64 */
13273 2655,
13274 /* BGTZC_MMR6 */
13275 2657,
13276 /* BGTZL */
13277 2659,
13278 /* BGTZ_MM */
13279 2661,
13280 /* BINSLI_B */
13281 2663,
13282 /* BINSLI_D */
13283 2667,
13284 /* BINSLI_H */
13285 2671,
13286 /* BINSLI_W */
13287 2675,
13288 /* BINSL_B */
13289 2679,
13290 /* BINSL_D */
13291 2683,
13292 /* BINSL_H */
13293 2687,
13294 /* BINSL_W */
13295 2691,
13296 /* BINSRI_B */
13297 2695,
13298 /* BINSRI_D */
13299 2699,
13300 /* BINSRI_H */
13301 2703,
13302 /* BINSRI_W */
13303 2707,
13304 /* BINSR_B */
13305 2711,
13306 /* BINSR_D */
13307 2715,
13308 /* BINSR_H */
13309 2719,
13310 /* BINSR_W */
13311 2723,
13312 /* BITREV */
13313 2727,
13314 /* BITREV_MM */
13315 2729,
13316 /* BITSWAP */
13317 2731,
13318 /* BITSWAP_MMR6 */
13319 2733,
13320 /* BLEZ */
13321 2735,
13322 /* BLEZ64 */
13323 2737,
13324 /* BLEZALC */
13325 2739,
13326 /* BLEZALC_MMR6 */
13327 2741,
13328 /* BLEZC */
13329 2743,
13330 /* BLEZC64 */
13331 2745,
13332 /* BLEZC_MMR6 */
13333 2747,
13334 /* BLEZL */
13335 2749,
13336 /* BLEZ_MM */
13337 2751,
13338 /* BLTC */
13339 2753,
13340 /* BLTC64 */
13341 2756,
13342 /* BLTC_MMR6 */
13343 2759,
13344 /* BLTUC */
13345 2762,
13346 /* BLTUC64 */
13347 2765,
13348 /* BLTUC_MMR6 */
13349 2768,
13350 /* BLTZ */
13351 2771,
13352 /* BLTZ64 */
13353 2773,
13354 /* BLTZAL */
13355 2775,
13356 /* BLTZALC */
13357 2777,
13358 /* BLTZALC_MMR6 */
13359 2779,
13360 /* BLTZALL */
13361 2781,
13362 /* BLTZALS_MM */
13363 2783,
13364 /* BLTZAL_MM */
13365 2785,
13366 /* BLTZC */
13367 2787,
13368 /* BLTZC64 */
13369 2789,
13370 /* BLTZC_MMR6 */
13371 2791,
13372 /* BLTZL */
13373 2793,
13374 /* BLTZ_MM */
13375 2795,
13376 /* BMNZI_B */
13377 2797,
13378 /* BMNZ_V */
13379 2801,
13380 /* BMZI_B */
13381 2805,
13382 /* BMZ_V */
13383 2809,
13384 /* BNE */
13385 2813,
13386 /* BNE64 */
13387 2816,
13388 /* BNEC */
13389 2819,
13390 /* BNEC64 */
13391 2822,
13392 /* BNEC_MMR6 */
13393 2825,
13394 /* BNEGI_B */
13395 2828,
13396 /* BNEGI_D */
13397 2831,
13398 /* BNEGI_H */
13399 2834,
13400 /* BNEGI_W */
13401 2837,
13402 /* BNEG_B */
13403 2840,
13404 /* BNEG_D */
13405 2843,
13406 /* BNEG_H */
13407 2846,
13408 /* BNEG_W */
13409 2849,
13410 /* BNEL */
13411 2852,
13412 /* BNEZ16_MM */
13413 2855,
13414 /* BNEZALC */
13415 2857,
13416 /* BNEZALC_MMR6 */
13417 2859,
13418 /* BNEZC */
13419 2861,
13420 /* BNEZC16_MMR6 */
13421 2863,
13422 /* BNEZC64 */
13423 2865,
13424 /* BNEZC_MM */
13425 2867,
13426 /* BNEZC_MMR6 */
13427 2869,
13428 /* BNE_MM */
13429 2871,
13430 /* BNVC */
13431 2874,
13432 /* BNVC_MMR6 */
13433 2877,
13434 /* BNZ_B */
13435 2880,
13436 /* BNZ_D */
13437 2882,
13438 /* BNZ_H */
13439 2884,
13440 /* BNZ_V */
13441 2886,
13442 /* BNZ_W */
13443 2888,
13444 /* BOVC */
13445 2890,
13446 /* BOVC_MMR6 */
13447 2893,
13448 /* BPOSGE32 */
13449 2896,
13450 /* BPOSGE32C_MMR3 */
13451 2897,
13452 /* BPOSGE32_MM */
13453 2898,
13454 /* BREAK */
13455 2899,
13456 /* BREAK16_MM */
13457 2901,
13458 /* BREAK16_MMR6 */
13459 2902,
13460 /* BREAK_MM */
13461 2903,
13462 /* BREAK_MMR6 */
13463 2905,
13464 /* BSELI_B */
13465 2907,
13466 /* BSEL_V */
13467 2911,
13468 /* BSETI_B */
13469 2915,
13470 /* BSETI_D */
13471 2918,
13472 /* BSETI_H */
13473 2921,
13474 /* BSETI_W */
13475 2924,
13476 /* BSET_B */
13477 2927,
13478 /* BSET_D */
13479 2930,
13480 /* BSET_H */
13481 2933,
13482 /* BSET_W */
13483 2936,
13484 /* BZ_B */
13485 2939,
13486 /* BZ_D */
13487 2941,
13488 /* BZ_H */
13489 2943,
13490 /* BZ_V */
13491 2945,
13492 /* BZ_W */
13493 2947,
13494 /* BeqzRxImm16 */
13495 2949,
13496 /* BeqzRxImmX16 */
13497 2951,
13498 /* Bimm16 */
13499 2953,
13500 /* BimmX16 */
13501 2954,
13502 /* BnezRxImm16 */
13503 2955,
13504 /* BnezRxImmX16 */
13505 2957,
13506 /* Break16 */
13507 2959,
13508 /* Bteqz16 */
13509 2959,
13510 /* BteqzX16 */
13511 2960,
13512 /* Btnez16 */
13513 2961,
13514 /* BtnezX16 */
13515 2962,
13516 /* CACHE */
13517 2963,
13518 /* CACHEE */
13519 2966,
13520 /* CACHEE_MM */
13521 2969,
13522 /* CACHE_MM */
13523 2972,
13524 /* CACHE_MMR6 */
13525 2975,
13526 /* CACHE_R6 */
13527 2978,
13528 /* CEIL_L_D64 */
13529 2981,
13530 /* CEIL_L_D_MMR6 */
13531 2983,
13532 /* CEIL_L_S */
13533 2985,
13534 /* CEIL_L_S_MMR6 */
13535 2987,
13536 /* CEIL_W_D32 */
13537 2989,
13538 /* CEIL_W_D64 */
13539 2991,
13540 /* CEIL_W_D_MMR6 */
13541 2993,
13542 /* CEIL_W_MM */
13543 2995,
13544 /* CEIL_W_S */
13545 2997,
13546 /* CEIL_W_S_MM */
13547 2999,
13548 /* CEIL_W_S_MMR6 */
13549 3001,
13550 /* CEQI_B */
13551 3003,
13552 /* CEQI_D */
13553 3006,
13554 /* CEQI_H */
13555 3009,
13556 /* CEQI_W */
13557 3012,
13558 /* CEQ_B */
13559 3015,
13560 /* CEQ_D */
13561 3018,
13562 /* CEQ_H */
13563 3021,
13564 /* CEQ_W */
13565 3024,
13566 /* CFC1 */
13567 3027,
13568 /* CFC1_MM */
13569 3029,
13570 /* CFC2_MM */
13571 3031,
13572 /* CFCMSA */
13573 3033,
13574 /* CINS */
13575 3035,
13576 /* CINS32 */
13577 3039,
13578 /* CINS64_32 */
13579 3043,
13580 /* CINS_i32 */
13581 3047,
13582 /* CLASS_D */
13583 3051,
13584 /* CLASS_D_MMR6 */
13585 3053,
13586 /* CLASS_S */
13587 3055,
13588 /* CLASS_S_MMR6 */
13589 3057,
13590 /* CLEI_S_B */
13591 3059,
13592 /* CLEI_S_D */
13593 3062,
13594 /* CLEI_S_H */
13595 3065,
13596 /* CLEI_S_W */
13597 3068,
13598 /* CLEI_U_B */
13599 3071,
13600 /* CLEI_U_D */
13601 3074,
13602 /* CLEI_U_H */
13603 3077,
13604 /* CLEI_U_W */
13605 3080,
13606 /* CLE_S_B */
13607 3083,
13608 /* CLE_S_D */
13609 3086,
13610 /* CLE_S_H */
13611 3089,
13612 /* CLE_S_W */
13613 3092,
13614 /* CLE_U_B */
13615 3095,
13616 /* CLE_U_D */
13617 3098,
13618 /* CLE_U_H */
13619 3101,
13620 /* CLE_U_W */
13621 3104,
13622 /* CLO */
13623 3107,
13624 /* CLO_MM */
13625 3109,
13626 /* CLO_MMR6 */
13627 3111,
13628 /* CLO_R6 */
13629 3113,
13630 /* CLTI_S_B */
13631 3115,
13632 /* CLTI_S_D */
13633 3118,
13634 /* CLTI_S_H */
13635 3121,
13636 /* CLTI_S_W */
13637 3124,
13638 /* CLTI_U_B */
13639 3127,
13640 /* CLTI_U_D */
13641 3130,
13642 /* CLTI_U_H */
13643 3133,
13644 /* CLTI_U_W */
13645 3136,
13646 /* CLT_S_B */
13647 3139,
13648 /* CLT_S_D */
13649 3142,
13650 /* CLT_S_H */
13651 3145,
13652 /* CLT_S_W */
13653 3148,
13654 /* CLT_U_B */
13655 3151,
13656 /* CLT_U_D */
13657 3154,
13658 /* CLT_U_H */
13659 3157,
13660 /* CLT_U_W */
13661 3160,
13662 /* CLZ */
13663 3163,
13664 /* CLZ_MM */
13665 3165,
13666 /* CLZ_MMR6 */
13667 3167,
13668 /* CLZ_R6 */
13669 3169,
13670 /* CMPGDU_EQ_QB */
13671 3171,
13672 /* CMPGDU_EQ_QB_MMR2 */
13673 3174,
13674 /* CMPGDU_LE_QB */
13675 3177,
13676 /* CMPGDU_LE_QB_MMR2 */
13677 3180,
13678 /* CMPGDU_LT_QB */
13679 3183,
13680 /* CMPGDU_LT_QB_MMR2 */
13681 3186,
13682 /* CMPGU_EQ_QB */
13683 3189,
13684 /* CMPGU_EQ_QB_MM */
13685 3192,
13686 /* CMPGU_LE_QB */
13687 3195,
13688 /* CMPGU_LE_QB_MM */
13689 3198,
13690 /* CMPGU_LT_QB */
13691 3201,
13692 /* CMPGU_LT_QB_MM */
13693 3204,
13694 /* CMPU_EQ_QB */
13695 3207,
13696 /* CMPU_EQ_QB_MM */
13697 3209,
13698 /* CMPU_LE_QB */
13699 3211,
13700 /* CMPU_LE_QB_MM */
13701 3213,
13702 /* CMPU_LT_QB */
13703 3215,
13704 /* CMPU_LT_QB_MM */
13705 3217,
13706 /* CMP_AF_D_MMR6 */
13707 3219,
13708 /* CMP_AF_S_MMR6 */
13709 3222,
13710 /* CMP_EQ_D */
13711 3225,
13712 /* CMP_EQ_D_MMR6 */
13713 3228,
13714 /* CMP_EQ_PH */
13715 3231,
13716 /* CMP_EQ_PH_MM */
13717 3233,
13718 /* CMP_EQ_S */
13719 3235,
13720 /* CMP_EQ_S_MMR6 */
13721 3238,
13722 /* CMP_F_D */
13723 3241,
13724 /* CMP_F_S */
13725 3244,
13726 /* CMP_LE_D */
13727 3247,
13728 /* CMP_LE_D_MMR6 */
13729 3250,
13730 /* CMP_LE_PH */
13731 3253,
13732 /* CMP_LE_PH_MM */
13733 3255,
13734 /* CMP_LE_S */
13735 3257,
13736 /* CMP_LE_S_MMR6 */
13737 3260,
13738 /* CMP_LT_D */
13739 3263,
13740 /* CMP_LT_D_MMR6 */
13741 3266,
13742 /* CMP_LT_PH */
13743 3269,
13744 /* CMP_LT_PH_MM */
13745 3271,
13746 /* CMP_LT_S */
13747 3273,
13748 /* CMP_LT_S_MMR6 */
13749 3276,
13750 /* CMP_SAF_D */
13751 3279,
13752 /* CMP_SAF_D_MMR6 */
13753 3282,
13754 /* CMP_SAF_S */
13755 3285,
13756 /* CMP_SAF_S_MMR6 */
13757 3288,
13758 /* CMP_SEQ_D */
13759 3291,
13760 /* CMP_SEQ_D_MMR6 */
13761 3294,
13762 /* CMP_SEQ_S */
13763 3297,
13764 /* CMP_SEQ_S_MMR6 */
13765 3300,
13766 /* CMP_SLE_D */
13767 3303,
13768 /* CMP_SLE_D_MMR6 */
13769 3306,
13770 /* CMP_SLE_S */
13771 3309,
13772 /* CMP_SLE_S_MMR6 */
13773 3312,
13774 /* CMP_SLT_D */
13775 3315,
13776 /* CMP_SLT_D_MMR6 */
13777 3318,
13778 /* CMP_SLT_S */
13779 3321,
13780 /* CMP_SLT_S_MMR6 */
13781 3324,
13782 /* CMP_SUEQ_D */
13783 3327,
13784 /* CMP_SUEQ_D_MMR6 */
13785 3330,
13786 /* CMP_SUEQ_S */
13787 3333,
13788 /* CMP_SUEQ_S_MMR6 */
13789 3336,
13790 /* CMP_SULE_D */
13791 3339,
13792 /* CMP_SULE_D_MMR6 */
13793 3342,
13794 /* CMP_SULE_S */
13795 3345,
13796 /* CMP_SULE_S_MMR6 */
13797 3348,
13798 /* CMP_SULT_D */
13799 3351,
13800 /* CMP_SULT_D_MMR6 */
13801 3354,
13802 /* CMP_SULT_S */
13803 3357,
13804 /* CMP_SULT_S_MMR6 */
13805 3360,
13806 /* CMP_SUN_D */
13807 3363,
13808 /* CMP_SUN_D_MMR6 */
13809 3366,
13810 /* CMP_SUN_S */
13811 3369,
13812 /* CMP_SUN_S_MMR6 */
13813 3372,
13814 /* CMP_UEQ_D */
13815 3375,
13816 /* CMP_UEQ_D_MMR6 */
13817 3378,
13818 /* CMP_UEQ_S */
13819 3381,
13820 /* CMP_UEQ_S_MMR6 */
13821 3384,
13822 /* CMP_ULE_D */
13823 3387,
13824 /* CMP_ULE_D_MMR6 */
13825 3390,
13826 /* CMP_ULE_S */
13827 3393,
13828 /* CMP_ULE_S_MMR6 */
13829 3396,
13830 /* CMP_ULT_D */
13831 3399,
13832 /* CMP_ULT_D_MMR6 */
13833 3402,
13834 /* CMP_ULT_S */
13835 3405,
13836 /* CMP_ULT_S_MMR6 */
13837 3408,
13838 /* CMP_UN_D */
13839 3411,
13840 /* CMP_UN_D_MMR6 */
13841 3414,
13842 /* CMP_UN_S */
13843 3417,
13844 /* CMP_UN_S_MMR6 */
13845 3420,
13846 /* COPY_S_B */
13847 3423,
13848 /* COPY_S_D */
13849 3426,
13850 /* COPY_S_H */
13851 3429,
13852 /* COPY_S_W */
13853 3432,
13854 /* COPY_U_B */
13855 3435,
13856 /* COPY_U_H */
13857 3438,
13858 /* COPY_U_W */
13859 3441,
13860 /* CRC32B */
13861 3444,
13862 /* CRC32CB */
13863 3447,
13864 /* CRC32CD */
13865 3450,
13866 /* CRC32CH */
13867 3453,
13868 /* CRC32CW */
13869 3456,
13870 /* CRC32D */
13871 3459,
13872 /* CRC32H */
13873 3462,
13874 /* CRC32W */
13875 3465,
13876 /* CTC1 */
13877 3468,
13878 /* CTC1_MM */
13879 3470,
13880 /* CTC2_MM */
13881 3472,
13882 /* CTCMSA */
13883 3474,
13884 /* CVT_D32_S */
13885 3476,
13886 /* CVT_D32_S_MM */
13887 3478,
13888 /* CVT_D32_W */
13889 3480,
13890 /* CVT_D32_W_MM */
13891 3482,
13892 /* CVT_D64_L */
13893 3484,
13894 /* CVT_D64_S */
13895 3486,
13896 /* CVT_D64_S_MM */
13897 3488,
13898 /* CVT_D64_W */
13899 3490,
13900 /* CVT_D64_W_MM */
13901 3492,
13902 /* CVT_D_L_MMR6 */
13903 3494,
13904 /* CVT_L_D64 */
13905 3496,
13906 /* CVT_L_D64_MM */
13907 3498,
13908 /* CVT_L_D_MMR6 */
13909 3500,
13910 /* CVT_L_S */
13911 3502,
13912 /* CVT_L_S_MM */
13913 3504,
13914 /* CVT_L_S_MMR6 */
13915 3506,
13916 /* CVT_PS_PW64 */
13917 3508,
13918 /* CVT_PS_S64 */
13919 3510,
13920 /* CVT_PW_PS64 */
13921 3513,
13922 /* CVT_S_D32 */
13923 3515,
13924 /* CVT_S_D32_MM */
13925 3517,
13926 /* CVT_S_D64 */
13927 3519,
13928 /* CVT_S_D64_MM */
13929 3521,
13930 /* CVT_S_L */
13931 3523,
13932 /* CVT_S_L_MMR6 */
13933 3525,
13934 /* CVT_S_PL64 */
13935 3527,
13936 /* CVT_S_PU64 */
13937 3529,
13938 /* CVT_S_W */
13939 3531,
13940 /* CVT_S_W_MM */
13941 3533,
13942 /* CVT_S_W_MMR6 */
13943 3535,
13944 /* CVT_W_D32 */
13945 3537,
13946 /* CVT_W_D32_MM */
13947 3539,
13948 /* CVT_W_D64 */
13949 3541,
13950 /* CVT_W_D64_MM */
13951 3543,
13952 /* CVT_W_S */
13953 3545,
13954 /* CVT_W_S_MM */
13955 3547,
13956 /* CVT_W_S_MMR6 */
13957 3549,
13958 /* C_EQ_D32 */
13959 3551,
13960 /* C_EQ_D32_MM */
13961 3554,
13962 /* C_EQ_D64 */
13963 3557,
13964 /* C_EQ_D64_MM */
13965 3560,
13966 /* C_EQ_S */
13967 3563,
13968 /* C_EQ_S_MM */
13969 3566,
13970 /* C_F_D32 */
13971 3569,
13972 /* C_F_D32_MM */
13973 3572,
13974 /* C_F_D64 */
13975 3575,
13976 /* C_F_D64_MM */
13977 3578,
13978 /* C_F_S */
13979 3581,
13980 /* C_F_S_MM */
13981 3584,
13982 /* C_LE_D32 */
13983 3587,
13984 /* C_LE_D32_MM */
13985 3590,
13986 /* C_LE_D64 */
13987 3593,
13988 /* C_LE_D64_MM */
13989 3596,
13990 /* C_LE_S */
13991 3599,
13992 /* C_LE_S_MM */
13993 3602,
13994 /* C_LT_D32 */
13995 3605,
13996 /* C_LT_D32_MM */
13997 3608,
13998 /* C_LT_D64 */
13999 3611,
14000 /* C_LT_D64_MM */
14001 3614,
14002 /* C_LT_S */
14003 3617,
14004 /* C_LT_S_MM */
14005 3620,
14006 /* C_NGE_D32 */
14007 3623,
14008 /* C_NGE_D32_MM */
14009 3626,
14010 /* C_NGE_D64 */
14011 3629,
14012 /* C_NGE_D64_MM */
14013 3632,
14014 /* C_NGE_S */
14015 3635,
14016 /* C_NGE_S_MM */
14017 3638,
14018 /* C_NGLE_D32 */
14019 3641,
14020 /* C_NGLE_D32_MM */
14021 3644,
14022 /* C_NGLE_D64 */
14023 3647,
14024 /* C_NGLE_D64_MM */
14025 3650,
14026 /* C_NGLE_S */
14027 3653,
14028 /* C_NGLE_S_MM */
14029 3656,
14030 /* C_NGL_D32 */
14031 3659,
14032 /* C_NGL_D32_MM */
14033 3662,
14034 /* C_NGL_D64 */
14035 3665,
14036 /* C_NGL_D64_MM */
14037 3668,
14038 /* C_NGL_S */
14039 3671,
14040 /* C_NGL_S_MM */
14041 3674,
14042 /* C_NGT_D32 */
14043 3677,
14044 /* C_NGT_D32_MM */
14045 3680,
14046 /* C_NGT_D64 */
14047 3683,
14048 /* C_NGT_D64_MM */
14049 3686,
14050 /* C_NGT_S */
14051 3689,
14052 /* C_NGT_S_MM */
14053 3692,
14054 /* C_OLE_D32 */
14055 3695,
14056 /* C_OLE_D32_MM */
14057 3698,
14058 /* C_OLE_D64 */
14059 3701,
14060 /* C_OLE_D64_MM */
14061 3704,
14062 /* C_OLE_S */
14063 3707,
14064 /* C_OLE_S_MM */
14065 3710,
14066 /* C_OLT_D32 */
14067 3713,
14068 /* C_OLT_D32_MM */
14069 3716,
14070 /* C_OLT_D64 */
14071 3719,
14072 /* C_OLT_D64_MM */
14073 3722,
14074 /* C_OLT_S */
14075 3725,
14076 /* C_OLT_S_MM */
14077 3728,
14078 /* C_SEQ_D32 */
14079 3731,
14080 /* C_SEQ_D32_MM */
14081 3734,
14082 /* C_SEQ_D64 */
14083 3737,
14084 /* C_SEQ_D64_MM */
14085 3740,
14086 /* C_SEQ_S */
14087 3743,
14088 /* C_SEQ_S_MM */
14089 3746,
14090 /* C_SF_D32 */
14091 3749,
14092 /* C_SF_D32_MM */
14093 3752,
14094 /* C_SF_D64 */
14095 3755,
14096 /* C_SF_D64_MM */
14097 3758,
14098 /* C_SF_S */
14099 3761,
14100 /* C_SF_S_MM */
14101 3764,
14102 /* C_UEQ_D32 */
14103 3767,
14104 /* C_UEQ_D32_MM */
14105 3770,
14106 /* C_UEQ_D64 */
14107 3773,
14108 /* C_UEQ_D64_MM */
14109 3776,
14110 /* C_UEQ_S */
14111 3779,
14112 /* C_UEQ_S_MM */
14113 3782,
14114 /* C_ULE_D32 */
14115 3785,
14116 /* C_ULE_D32_MM */
14117 3788,
14118 /* C_ULE_D64 */
14119 3791,
14120 /* C_ULE_D64_MM */
14121 3794,
14122 /* C_ULE_S */
14123 3797,
14124 /* C_ULE_S_MM */
14125 3800,
14126 /* C_ULT_D32 */
14127 3803,
14128 /* C_ULT_D32_MM */
14129 3806,
14130 /* C_ULT_D64 */
14131 3809,
14132 /* C_ULT_D64_MM */
14133 3812,
14134 /* C_ULT_S */
14135 3815,
14136 /* C_ULT_S_MM */
14137 3818,
14138 /* C_UN_D32 */
14139 3821,
14140 /* C_UN_D32_MM */
14141 3824,
14142 /* C_UN_D64 */
14143 3827,
14144 /* C_UN_D64_MM */
14145 3830,
14146 /* C_UN_S */
14147 3833,
14148 /* C_UN_S_MM */
14149 3836,
14150 /* CmpRxRy16 */
14151 3839,
14152 /* CmpiRxImm16 */
14153 3841,
14154 /* CmpiRxImmX16 */
14155 3843,
14156 /* DADD */
14157 3845,
14158 /* DADDi */
14159 3848,
14160 /* DADDiu */
14161 3851,
14162 /* DADDu */
14163 3854,
14164 /* DAHI */
14165 3857,
14166 /* DALIGN */
14167 3860,
14168 /* DATI */
14169 3864,
14170 /* DAUI */
14171 3867,
14172 /* DBITSWAP */
14173 3870,
14174 /* DCLO */
14175 3872,
14176 /* DCLO_R6 */
14177 3874,
14178 /* DCLZ */
14179 3876,
14180 /* DCLZ_R6 */
14181 3878,
14182 /* DDIV */
14183 3880,
14184 /* DDIVU */
14185 3883,
14186 /* DERET */
14187 3886,
14188 /* DERET_MM */
14189 3886,
14190 /* DERET_MMR6 */
14191 3886,
14192 /* DEXT */
14193 3886,
14194 /* DEXT64_32 */
14195 3890,
14196 /* DEXTM */
14197 3894,
14198 /* DEXTU */
14199 3898,
14200 /* DI */
14201 3902,
14202 /* DINS */
14203 3903,
14204 /* DINSM */
14205 3908,
14206 /* DINSU */
14207 3913,
14208 /* DIV */
14209 3918,
14210 /* DIVU */
14211 3921,
14212 /* DIVU_MMR6 */
14213 3924,
14214 /* DIV_MMR6 */
14215 3927,
14216 /* DIV_S_B */
14217 3930,
14218 /* DIV_S_D */
14219 3933,
14220 /* DIV_S_H */
14221 3936,
14222 /* DIV_S_W */
14223 3939,
14224 /* DIV_U_B */
14225 3942,
14226 /* DIV_U_D */
14227 3945,
14228 /* DIV_U_H */
14229 3948,
14230 /* DIV_U_W */
14231 3951,
14232 /* DI_MM */
14233 3954,
14234 /* DI_MMR6 */
14235 3955,
14236 /* DLSA */
14237 3956,
14238 /* DLSA_R6 */
14239 3960,
14240 /* DMFC0 */
14241 3964,
14242 /* DMFC1 */
14243 3967,
14244 /* DMFC2 */
14245 3969,
14246 /* DMFC2_OCTEON */
14247 3972,
14248 /* DMFGC0 */
14249 3974,
14250 /* DMOD */
14251 3977,
14252 /* DMODU */
14253 3980,
14254 /* DMT */
14255 3983,
14256 /* DMTC0 */
14257 3984,
14258 /* DMTC1 */
14259 3987,
14260 /* DMTC2 */
14261 3989,
14262 /* DMTC2_OCTEON */
14263 3992,
14264 /* DMTGC0 */
14265 3994,
14266 /* DMUH */
14267 3997,
14268 /* DMUHU */
14269 4000,
14270 /* DMUL */
14271 4003,
14272 /* DMULT */
14273 4006,
14274 /* DMULTu */
14275 4008,
14276 /* DMULU */
14277 4010,
14278 /* DMUL_R6 */
14279 4013,
14280 /* DOTP_S_D */
14281 4016,
14282 /* DOTP_S_H */
14283 4019,
14284 /* DOTP_S_W */
14285 4022,
14286 /* DOTP_U_D */
14287 4025,
14288 /* DOTP_U_H */
14289 4028,
14290 /* DOTP_U_W */
14291 4031,
14292 /* DPADD_S_D */
14293 4034,
14294 /* DPADD_S_H */
14295 4038,
14296 /* DPADD_S_W */
14297 4042,
14298 /* DPADD_U_D */
14299 4046,
14300 /* DPADD_U_H */
14301 4050,
14302 /* DPADD_U_W */
14303 4054,
14304 /* DPAQX_SA_W_PH */
14305 4058,
14306 /* DPAQX_SA_W_PH_MMR2 */
14307 4062,
14308 /* DPAQX_S_W_PH */
14309 4066,
14310 /* DPAQX_S_W_PH_MMR2 */
14311 4070,
14312 /* DPAQ_SA_L_W */
14313 4074,
14314 /* DPAQ_SA_L_W_MM */
14315 4078,
14316 /* DPAQ_S_W_PH */
14317 4082,
14318 /* DPAQ_S_W_PH_MM */
14319 4086,
14320 /* DPAU_H_QBL */
14321 4090,
14322 /* DPAU_H_QBL_MM */
14323 4094,
14324 /* DPAU_H_QBR */
14325 4098,
14326 /* DPAU_H_QBR_MM */
14327 4102,
14328 /* DPAX_W_PH */
14329 4106,
14330 /* DPAX_W_PH_MMR2 */
14331 4110,
14332 /* DPA_W_PH */
14333 4114,
14334 /* DPA_W_PH_MMR2 */
14335 4118,
14336 /* DPOP */
14337 4122,
14338 /* DPSQX_SA_W_PH */
14339 4124,
14340 /* DPSQX_SA_W_PH_MMR2 */
14341 4128,
14342 /* DPSQX_S_W_PH */
14343 4132,
14344 /* DPSQX_S_W_PH_MMR2 */
14345 4136,
14346 /* DPSQ_SA_L_W */
14347 4140,
14348 /* DPSQ_SA_L_W_MM */
14349 4144,
14350 /* DPSQ_S_W_PH */
14351 4148,
14352 /* DPSQ_S_W_PH_MM */
14353 4152,
14354 /* DPSUB_S_D */
14355 4156,
14356 /* DPSUB_S_H */
14357 4160,
14358 /* DPSUB_S_W */
14359 4164,
14360 /* DPSUB_U_D */
14361 4168,
14362 /* DPSUB_U_H */
14363 4172,
14364 /* DPSUB_U_W */
14365 4176,
14366 /* DPSU_H_QBL */
14367 4180,
14368 /* DPSU_H_QBL_MM */
14369 4184,
14370 /* DPSU_H_QBR */
14371 4188,
14372 /* DPSU_H_QBR_MM */
14373 4192,
14374 /* DPSX_W_PH */
14375 4196,
14376 /* DPSX_W_PH_MMR2 */
14377 4200,
14378 /* DPS_W_PH */
14379 4204,
14380 /* DPS_W_PH_MMR2 */
14381 4208,
14382 /* DROTR */
14383 4212,
14384 /* DROTR32 */
14385 4215,
14386 /* DROTRV */
14387 4218,
14388 /* DSBH */
14389 4221,
14390 /* DSDIV */
14391 4223,
14392 /* DSHD */
14393 4225,
14394 /* DSLL */
14395 4227,
14396 /* DSLL32 */
14397 4230,
14398 /* DSLL64_32 */
14399 4233,
14400 /* DSLLV */
14401 4235,
14402 /* DSRA */
14403 4238,
14404 /* DSRA32 */
14405 4241,
14406 /* DSRAV */
14407 4244,
14408 /* DSRL */
14409 4247,
14410 /* DSRL32 */
14411 4250,
14412 /* DSRLV */
14413 4253,
14414 /* DSUB */
14415 4256,
14416 /* DSUBu */
14417 4259,
14418 /* DUDIV */
14419 4262,
14420 /* DVP */
14421 4264,
14422 /* DVPE */
14423 4265,
14424 /* DVP_MMR6 */
14425 4266,
14426 /* DivRxRy16 */
14427 4267,
14428 /* DivuRxRy16 */
14429 4269,
14430 /* EHB */
14431 4271,
14432 /* EHB_MM */
14433 4271,
14434 /* EHB_MMR6 */
14435 4271,
14436 /* EI */
14437 4271,
14438 /* EI_MM */
14439 4272,
14440 /* EI_MMR6 */
14441 4273,
14442 /* EMT */
14443 4274,
14444 /* ERET */
14445 4275,
14446 /* ERETNC */
14447 4275,
14448 /* ERETNC_MMR6 */
14449 4275,
14450 /* ERET_MM */
14451 4275,
14452 /* ERET_MMR6 */
14453 4275,
14454 /* EVP */
14455 4275,
14456 /* EVPE */
14457 4276,
14458 /* EVP_MMR6 */
14459 4277,
14460 /* EXT */
14461 4278,
14462 /* EXTP */
14463 4282,
14464 /* EXTPDP */
14465 4285,
14466 /* EXTPDPV */
14467 4288,
14468 /* EXTPDPV_MM */
14469 4291,
14470 /* EXTPDP_MM */
14471 4294,
14472 /* EXTPV */
14473 4297,
14474 /* EXTPV_MM */
14475 4300,
14476 /* EXTP_MM */
14477 4303,
14478 /* EXTRV_RS_W */
14479 4306,
14480 /* EXTRV_RS_W_MM */
14481 4309,
14482 /* EXTRV_R_W */
14483 4312,
14484 /* EXTRV_R_W_MM */
14485 4315,
14486 /* EXTRV_S_H */
14487 4318,
14488 /* EXTRV_S_H_MM */
14489 4321,
14490 /* EXTRV_W */
14491 4324,
14492 /* EXTRV_W_MM */
14493 4327,
14494 /* EXTR_RS_W */
14495 4330,
14496 /* EXTR_RS_W_MM */
14497 4333,
14498 /* EXTR_R_W */
14499 4336,
14500 /* EXTR_R_W_MM */
14501 4339,
14502 /* EXTR_S_H */
14503 4342,
14504 /* EXTR_S_H_MM */
14505 4345,
14506 /* EXTR_W */
14507 4348,
14508 /* EXTR_W_MM */
14509 4351,
14510 /* EXTS */
14511 4354,
14512 /* EXTS32 */
14513 4358,
14514 /* EXT_MM */
14515 4362,
14516 /* EXT_MMR6 */
14517 4366,
14518 /* FABS_D32 */
14519 4370,
14520 /* FABS_D32_MM */
14521 4372,
14522 /* FABS_D64 */
14523 4374,
14524 /* FABS_D64_MM */
14525 4376,
14526 /* FABS_S */
14527 4378,
14528 /* FABS_S_MM */
14529 4380,
14530 /* FADD_D */
14531 4382,
14532 /* FADD_D32 */
14533 4385,
14534 /* FADD_D32_MM */
14535 4388,
14536 /* FADD_D64 */
14537 4391,
14538 /* FADD_D64_MM */
14539 4394,
14540 /* FADD_PS64 */
14541 4397,
14542 /* FADD_S */
14543 4400,
14544 /* FADD_S_MM */
14545 4403,
14546 /* FADD_S_MMR6 */
14547 4406,
14548 /* FADD_W */
14549 4409,
14550 /* FCAF_D */
14551 4412,
14552 /* FCAF_W */
14553 4415,
14554 /* FCEQ_D */
14555 4418,
14556 /* FCEQ_W */
14557 4421,
14558 /* FCLASS_D */
14559 4424,
14560 /* FCLASS_W */
14561 4426,
14562 /* FCLE_D */
14563 4428,
14564 /* FCLE_W */
14565 4431,
14566 /* FCLT_D */
14567 4434,
14568 /* FCLT_W */
14569 4437,
14570 /* FCMP_D32 */
14571 4440,
14572 /* FCMP_D32_MM */
14573 4443,
14574 /* FCMP_D64 */
14575 4446,
14576 /* FCMP_S32 */
14577 4449,
14578 /* FCMP_S32_MM */
14579 4452,
14580 /* FCNE_D */
14581 4455,
14582 /* FCNE_W */
14583 4458,
14584 /* FCOR_D */
14585 4461,
14586 /* FCOR_W */
14587 4464,
14588 /* FCUEQ_D */
14589 4467,
14590 /* FCUEQ_W */
14591 4470,
14592 /* FCULE_D */
14593 4473,
14594 /* FCULE_W */
14595 4476,
14596 /* FCULT_D */
14597 4479,
14598 /* FCULT_W */
14599 4482,
14600 /* FCUNE_D */
14601 4485,
14602 /* FCUNE_W */
14603 4488,
14604 /* FCUN_D */
14605 4491,
14606 /* FCUN_W */
14607 4494,
14608 /* FDIV_D */
14609 4497,
14610 /* FDIV_D32 */
14611 4500,
14612 /* FDIV_D32_MM */
14613 4503,
14614 /* FDIV_D64 */
14615 4506,
14616 /* FDIV_D64_MM */
14617 4509,
14618 /* FDIV_S */
14619 4512,
14620 /* FDIV_S_MM */
14621 4515,
14622 /* FDIV_S_MMR6 */
14623 4518,
14624 /* FDIV_W */
14625 4521,
14626 /* FEXDO_H */
14627 4524,
14628 /* FEXDO_W */
14629 4527,
14630 /* FEXP2_D */
14631 4530,
14632 /* FEXP2_W */
14633 4533,
14634 /* FEXUPL_D */
14635 4536,
14636 /* FEXUPL_W */
14637 4538,
14638 /* FEXUPR_D */
14639 4540,
14640 /* FEXUPR_W */
14641 4542,
14642 /* FFINT_S_D */
14643 4544,
14644 /* FFINT_S_W */
14645 4546,
14646 /* FFINT_U_D */
14647 4548,
14648 /* FFINT_U_W */
14649 4550,
14650 /* FFQL_D */
14651 4552,
14652 /* FFQL_W */
14653 4554,
14654 /* FFQR_D */
14655 4556,
14656 /* FFQR_W */
14657 4558,
14658 /* FILL_B */
14659 4560,
14660 /* FILL_D */
14661 4562,
14662 /* FILL_H */
14663 4564,
14664 /* FILL_W */
14665 4566,
14666 /* FLOG2_D */
14667 4568,
14668 /* FLOG2_W */
14669 4570,
14670 /* FLOOR_L_D64 */
14671 4572,
14672 /* FLOOR_L_D_MMR6 */
14673 4574,
14674 /* FLOOR_L_S */
14675 4576,
14676 /* FLOOR_L_S_MMR6 */
14677 4578,
14678 /* FLOOR_W_D32 */
14679 4580,
14680 /* FLOOR_W_D64 */
14681 4582,
14682 /* FLOOR_W_D_MMR6 */
14683 4584,
14684 /* FLOOR_W_MM */
14685 4586,
14686 /* FLOOR_W_S */
14687 4588,
14688 /* FLOOR_W_S_MM */
14689 4590,
14690 /* FLOOR_W_S_MMR6 */
14691 4592,
14692 /* FMADD_D */
14693 4594,
14694 /* FMADD_W */
14695 4598,
14696 /* FMAX_A_D */
14697 4602,
14698 /* FMAX_A_W */
14699 4605,
14700 /* FMAX_D */
14701 4608,
14702 /* FMAX_W */
14703 4611,
14704 /* FMIN_A_D */
14705 4614,
14706 /* FMIN_A_W */
14707 4617,
14708 /* FMIN_D */
14709 4620,
14710 /* FMIN_W */
14711 4623,
14712 /* FMOV_D32 */
14713 4626,
14714 /* FMOV_D32_MM */
14715 4628,
14716 /* FMOV_D64 */
14717 4630,
14718 /* FMOV_D64_MM */
14719 4632,
14720 /* FMOV_D_MMR6 */
14721 4634,
14722 /* FMOV_S */
14723 4636,
14724 /* FMOV_S_MM */
14725 4638,
14726 /* FMOV_S_MMR6 */
14727 4640,
14728 /* FMSUB_D */
14729 4642,
14730 /* FMSUB_W */
14731 4646,
14732 /* FMUL_D */
14733 4650,
14734 /* FMUL_D32 */
14735 4653,
14736 /* FMUL_D32_MM */
14737 4656,
14738 /* FMUL_D64 */
14739 4659,
14740 /* FMUL_D64_MM */
14741 4662,
14742 /* FMUL_PS64 */
14743 4665,
14744 /* FMUL_S */
14745 4668,
14746 /* FMUL_S_MM */
14747 4671,
14748 /* FMUL_S_MMR6 */
14749 4674,
14750 /* FMUL_W */
14751 4677,
14752 /* FNEG_D32 */
14753 4680,
14754 /* FNEG_D32_MM */
14755 4682,
14756 /* FNEG_D64 */
14757 4684,
14758 /* FNEG_D64_MM */
14759 4686,
14760 /* FNEG_S */
14761 4688,
14762 /* FNEG_S_MM */
14763 4690,
14764 /* FNEG_S_MMR6 */
14765 4692,
14766 /* FORK */
14767 4694,
14768 /* FRCP_D */
14769 4697,
14770 /* FRCP_W */
14771 4699,
14772 /* FRINT_D */
14773 4701,
14774 /* FRINT_W */
14775 4703,
14776 /* FRSQRT_D */
14777 4705,
14778 /* FRSQRT_W */
14779 4707,
14780 /* FSAF_D */
14781 4709,
14782 /* FSAF_W */
14783 4712,
14784 /* FSEQ_D */
14785 4715,
14786 /* FSEQ_W */
14787 4718,
14788 /* FSLE_D */
14789 4721,
14790 /* FSLE_W */
14791 4724,
14792 /* FSLT_D */
14793 4727,
14794 /* FSLT_W */
14795 4730,
14796 /* FSNE_D */
14797 4733,
14798 /* FSNE_W */
14799 4736,
14800 /* FSOR_D */
14801 4739,
14802 /* FSOR_W */
14803 4742,
14804 /* FSQRT_D */
14805 4745,
14806 /* FSQRT_D32 */
14807 4747,
14808 /* FSQRT_D32_MM */
14809 4749,
14810 /* FSQRT_D64 */
14811 4751,
14812 /* FSQRT_D64_MM */
14813 4753,
14814 /* FSQRT_S */
14815 4755,
14816 /* FSQRT_S_MM */
14817 4757,
14818 /* FSQRT_W */
14819 4759,
14820 /* FSUB_D */
14821 4761,
14822 /* FSUB_D32 */
14823 4764,
14824 /* FSUB_D32_MM */
14825 4767,
14826 /* FSUB_D64 */
14827 4770,
14828 /* FSUB_D64_MM */
14829 4773,
14830 /* FSUB_PS64 */
14831 4776,
14832 /* FSUB_S */
14833 4779,
14834 /* FSUB_S_MM */
14835 4782,
14836 /* FSUB_S_MMR6 */
14837 4785,
14838 /* FSUB_W */
14839 4788,
14840 /* FSUEQ_D */
14841 4791,
14842 /* FSUEQ_W */
14843 4794,
14844 /* FSULE_D */
14845 4797,
14846 /* FSULE_W */
14847 4800,
14848 /* FSULT_D */
14849 4803,
14850 /* FSULT_W */
14851 4806,
14852 /* FSUNE_D */
14853 4809,
14854 /* FSUNE_W */
14855 4812,
14856 /* FSUN_D */
14857 4815,
14858 /* FSUN_W */
14859 4818,
14860 /* FTINT_S_D */
14861 4821,
14862 /* FTINT_S_W */
14863 4823,
14864 /* FTINT_U_D */
14865 4825,
14866 /* FTINT_U_W */
14867 4827,
14868 /* FTQ_H */
14869 4829,
14870 /* FTQ_W */
14871 4832,
14872 /* FTRUNC_S_D */
14873 4835,
14874 /* FTRUNC_S_W */
14875 4837,
14876 /* FTRUNC_U_D */
14877 4839,
14878 /* FTRUNC_U_W */
14879 4841,
14880 /* GINVI */
14881 4843,
14882 /* GINVI_MMR6 */
14883 4844,
14884 /* GINVT */
14885 4845,
14886 /* GINVT_MMR6 */
14887 4847,
14888 /* HADD_S_D */
14889 4849,
14890 /* HADD_S_H */
14891 4852,
14892 /* HADD_S_W */
14893 4855,
14894 /* HADD_U_D */
14895 4858,
14896 /* HADD_U_H */
14897 4861,
14898 /* HADD_U_W */
14899 4864,
14900 /* HSUB_S_D */
14901 4867,
14902 /* HSUB_S_H */
14903 4870,
14904 /* HSUB_S_W */
14905 4873,
14906 /* HSUB_U_D */
14907 4876,
14908 /* HSUB_U_H */
14909 4879,
14910 /* HSUB_U_W */
14911 4882,
14912 /* HYPCALL */
14913 4885,
14914 /* HYPCALL_MM */
14915 4886,
14916 /* ILVEV_B */
14917 4887,
14918 /* ILVEV_D */
14919 4890,
14920 /* ILVEV_H */
14921 4893,
14922 /* ILVEV_W */
14923 4896,
14924 /* ILVL_B */
14925 4899,
14926 /* ILVL_D */
14927 4902,
14928 /* ILVL_H */
14929 4905,
14930 /* ILVL_W */
14931 4908,
14932 /* ILVOD_B */
14933 4911,
14934 /* ILVOD_D */
14935 4914,
14936 /* ILVOD_H */
14937 4917,
14938 /* ILVOD_W */
14939 4920,
14940 /* ILVR_B */
14941 4923,
14942 /* ILVR_D */
14943 4926,
14944 /* ILVR_H */
14945 4929,
14946 /* ILVR_W */
14947 4932,
14948 /* INS */
14949 4935,
14950 /* INSERT_B */
14951 4940,
14952 /* INSERT_D */
14953 4944,
14954 /* INSERT_H */
14955 4948,
14956 /* INSERT_W */
14957 4952,
14958 /* INSV */
14959 4956,
14960 /* INSVE_B */
14961 4959,
14962 /* INSVE_D */
14963 4964,
14964 /* INSVE_H */
14965 4969,
14966 /* INSVE_W */
14967 4974,
14968 /* INSV_MM */
14969 4979,
14970 /* INS_MM */
14971 4982,
14972 /* INS_MMR6 */
14973 4987,
14974 /* J */
14975 4992,
14976 /* JAL */
14977 4993,
14978 /* JALR */
14979 4994,
14980 /* JALR16_MM */
14981 4996,
14982 /* JALR64 */
14983 4997,
14984 /* JALRC16_MMR6 */
14985 4999,
14986 /* JALRC_HB_MMR6 */
14987 5000,
14988 /* JALRC_MMR6 */
14989 5002,
14990 /* JALRS16_MM */
14991 5004,
14992 /* JALRS_MM */
14993 5005,
14994 /* JALR_HB */
14995 5007,
14996 /* JALR_HB64 */
14997 5009,
14998 /* JALR_MM */
14999 5011,
15000 /* JALS_MM */
15001 5013,
15002 /* JALX */
15003 5014,
15004 /* JALX_MM */
15005 5015,
15006 /* JAL_MM */
15007 5016,
15008 /* JIALC */
15009 5017,
15010 /* JIALC64 */
15011 5019,
15012 /* JIALC_MMR6 */
15013 5021,
15014 /* JIC */
15015 5023,
15016 /* JIC64 */
15017 5025,
15018 /* JIC_MMR6 */
15019 5027,
15020 /* JR */
15021 5029,
15022 /* JR16_MM */
15023 5030,
15024 /* JR64 */
15025 5031,
15026 /* JRADDIUSP */
15027 5032,
15028 /* JRC16_MM */
15029 5033,
15030 /* JRC16_MMR6 */
15031 5034,
15032 /* JRCADDIUSP_MMR6 */
15033 5035,
15034 /* JR_HB */
15035 5036,
15036 /* JR_HB64 */
15037 5037,
15038 /* JR_HB64_R6 */
15039 5038,
15040 /* JR_HB_R6 */
15041 5039,
15042 /* JR_MM */
15043 5040,
15044 /* J_MM */
15045 5041,
15046 /* Jal16 */
15047 5042,
15048 /* JalB16 */
15049 5043,
15050 /* JrRa16 */
15051 5044,
15052 /* JrcRa16 */
15053 5044,
15054 /* JrcRx16 */
15055 5044,
15056 /* JumpLinkReg16 */
15057 5045,
15058 /* LB */
15059 5046,
15060 /* LB64 */
15061 5049,
15062 /* LBE */
15063 5052,
15064 /* LBE_MM */
15065 5055,
15066 /* LBU16_MM */
15067 5058,
15068 /* LBUX */
15069 5061,
15070 /* LBUX_MM */
15071 5064,
15072 /* LBU_MMR6 */
15073 5067,
15074 /* LB_MM */
15075 5070,
15076 /* LB_MMR6 */
15077 5073,
15078 /* LBu */
15079 5076,
15080 /* LBu64 */
15081 5079,
15082 /* LBuE */
15083 5082,
15084 /* LBuE_MM */
15085 5085,
15086 /* LBu_MM */
15087 5088,
15088 /* LD */
15089 5091,
15090 /* LDC1 */
15091 5094,
15092 /* LDC164 */
15093 5097,
15094 /* LDC1_D64_MMR6 */
15095 5100,
15096 /* LDC1_MM_D32 */
15097 5103,
15098 /* LDC1_MM_D64 */
15099 5106,
15100 /* LDC2 */
15101 5109,
15102 /* LDC2_MMR6 */
15103 5112,
15104 /* LDC2_R6 */
15105 5115,
15106 /* LDC3 */
15107 5118,
15108 /* LDI_B */
15109 5121,
15110 /* LDI_D */
15111 5123,
15112 /* LDI_H */
15113 5125,
15114 /* LDI_W */
15115 5127,
15116 /* LDL */
15117 5129,
15118 /* LDPC */
15119 5133,
15120 /* LDR */
15121 5135,
15122 /* LDXC1 */
15123 5139,
15124 /* LDXC164 */
15125 5142,
15126 /* LD_B */
15127 5145,
15128 /* LD_D */
15129 5148,
15130 /* LD_H */
15131 5151,
15132 /* LD_W */
15133 5154,
15134 /* LEA_ADDiu */
15135 5157,
15136 /* LEA_ADDiu64 */
15137 5160,
15138 /* LEA_ADDiu_MM */
15139 5163,
15140 /* LH */
15141 5166,
15142 /* LH64 */
15143 5169,
15144 /* LHE */
15145 5172,
15146 /* LHE_MM */
15147 5175,
15148 /* LHU16_MM */
15149 5178,
15150 /* LHX */
15151 5181,
15152 /* LHX_MM */
15153 5184,
15154 /* LH_MM */
15155 5187,
15156 /* LHu */
15157 5190,
15158 /* LHu64 */
15159 5193,
15160 /* LHuE */
15161 5196,
15162 /* LHuE_MM */
15163 5199,
15164 /* LHu_MM */
15165 5202,
15166 /* LI16_MM */
15167 5205,
15168 /* LI16_MMR6 */
15169 5207,
15170 /* LL */
15171 5209,
15172 /* LL64 */
15173 5212,
15174 /* LL64_R6 */
15175 5215,
15176 /* LLD */
15177 5218,
15178 /* LLD_R6 */
15179 5221,
15180 /* LLE */
15181 5224,
15182 /* LLE_MM */
15183 5227,
15184 /* LL_MM */
15185 5230,
15186 /* LL_MMR6 */
15187 5233,
15188 /* LL_R6 */
15189 5236,
15190 /* LSA */
15191 5239,
15192 /* LSA_MMR6 */
15193 5243,
15194 /* LSA_R6 */
15195 5247,
15196 /* LUI_MMR6 */
15197 5251,
15198 /* LUXC1 */
15199 5253,
15200 /* LUXC164 */
15201 5256,
15202 /* LUXC1_MM */
15203 5259,
15204 /* LUi */
15205 5262,
15206 /* LUi64 */
15207 5264,
15208 /* LUi_MM */
15209 5266,
15210 /* LW */
15211 5268,
15212 /* LW16_MM */
15213 5271,
15214 /* LW64 */
15215 5274,
15216 /* LWC1 */
15217 5277,
15218 /* LWC1_MM */
15219 5280,
15220 /* LWC2 */
15221 5283,
15222 /* LWC2_MMR6 */
15223 5286,
15224 /* LWC2_R6 */
15225 5289,
15226 /* LWC3 */
15227 5292,
15228 /* LWDSP */
15229 5295,
15230 /* LWDSP_MM */
15231 5298,
15232 /* LWE */
15233 5301,
15234 /* LWE_MM */
15235 5304,
15236 /* LWGP_MM */
15237 5307,
15238 /* LWL */
15239 5310,
15240 /* LWL64 */
15241 5314,
15242 /* LWLE */
15243 5318,
15244 /* LWLE_MM */
15245 5322,
15246 /* LWL_MM */
15247 5326,
15248 /* LWM16_MM */
15249 5330,
15250 /* LWM16_MMR6 */
15251 5333,
15252 /* LWM32_MM */
15253 5336,
15254 /* LWPC */
15255 5339,
15256 /* LWPC_MMR6 */
15257 5341,
15258 /* LWP_MM */
15259 5343,
15260 /* LWR */
15261 5347,
15262 /* LWR64 */
15263 5351,
15264 /* LWRE */
15265 5355,
15266 /* LWRE_MM */
15267 5359,
15268 /* LWR_MM */
15269 5363,
15270 /* LWSP_MM */
15271 5367,
15272 /* LWUPC */
15273 5370,
15274 /* LWU_MM */
15275 5372,
15276 /* LWX */
15277 5375,
15278 /* LWXC1 */
15279 5378,
15280 /* LWXC1_MM */
15281 5381,
15282 /* LWXS_MM */
15283 5384,
15284 /* LWX_MM */
15285 5387,
15286 /* LW_MM */
15287 5390,
15288 /* LW_MMR6 */
15289 5393,
15290 /* LWu */
15291 5396,
15292 /* LbRxRyOffMemX16 */
15293 5399,
15294 /* LbuRxRyOffMemX16 */
15295 5402,
15296 /* LhRxRyOffMemX16 */
15297 5405,
15298 /* LhuRxRyOffMemX16 */
15299 5408,
15300 /* LiRxImm16 */
15301 5411,
15302 /* LiRxImmAlignX16 */
15303 5413,
15304 /* LiRxImmX16 */
15305 5415,
15306 /* LwRxPcTcp16 */
15307 5417,
15308 /* LwRxPcTcpX16 */
15309 5420,
15310 /* LwRxRyOffMemX16 */
15311 5423,
15312 /* LwRxSpImmX16 */
15313 5426,
15314 /* MADD */
15315 5429,
15316 /* MADDF_D */
15317 5431,
15318 /* MADDF_D_MMR6 */
15319 5435,
15320 /* MADDF_S */
15321 5439,
15322 /* MADDF_S_MMR6 */
15323 5443,
15324 /* MADDR_Q_H */
15325 5447,
15326 /* MADDR_Q_W */
15327 5451,
15328 /* MADDU */
15329 5455,
15330 /* MADDU_DSP */
15331 5457,
15332 /* MADDU_DSP_MM */
15333 5461,
15334 /* MADDU_MM */
15335 5465,
15336 /* MADDV_B */
15337 5467,
15338 /* MADDV_D */
15339 5471,
15340 /* MADDV_H */
15341 5475,
15342 /* MADDV_W */
15343 5479,
15344 /* MADD_D32 */
15345 5483,
15346 /* MADD_D32_MM */
15347 5487,
15348 /* MADD_D64 */
15349 5491,
15350 /* MADD_DSP */
15351 5495,
15352 /* MADD_DSP_MM */
15353 5499,
15354 /* MADD_MM */
15355 5503,
15356 /* MADD_Q_H */
15357 5505,
15358 /* MADD_Q_W */
15359 5509,
15360 /* MADD_S */
15361 5513,
15362 /* MADD_S_MM */
15363 5517,
15364 /* MAQ_SA_W_PHL */
15365 5521,
15366 /* MAQ_SA_W_PHL_MM */
15367 5525,
15368 /* MAQ_SA_W_PHR */
15369 5529,
15370 /* MAQ_SA_W_PHR_MM */
15371 5533,
15372 /* MAQ_S_W_PHL */
15373 5537,
15374 /* MAQ_S_W_PHL_MM */
15375 5541,
15376 /* MAQ_S_W_PHR */
15377 5545,
15378 /* MAQ_S_W_PHR_MM */
15379 5549,
15380 /* MAXA_D */
15381 5553,
15382 /* MAXA_D_MMR6 */
15383 5556,
15384 /* MAXA_S */
15385 5559,
15386 /* MAXA_S_MMR6 */
15387 5562,
15388 /* MAXI_S_B */
15389 5565,
15390 /* MAXI_S_D */
15391 5568,
15392 /* MAXI_S_H */
15393 5571,
15394 /* MAXI_S_W */
15395 5574,
15396 /* MAXI_U_B */
15397 5577,
15398 /* MAXI_U_D */
15399 5580,
15400 /* MAXI_U_H */
15401 5583,
15402 /* MAXI_U_W */
15403 5586,
15404 /* MAX_A_B */
15405 5589,
15406 /* MAX_A_D */
15407 5592,
15408 /* MAX_A_H */
15409 5595,
15410 /* MAX_A_W */
15411 5598,
15412 /* MAX_D */
15413 5601,
15414 /* MAX_D_MMR6 */
15415 5604,
15416 /* MAX_S */
15417 5607,
15418 /* MAX_S_B */
15419 5610,
15420 /* MAX_S_D */
15421 5613,
15422 /* MAX_S_H */
15423 5616,
15424 /* MAX_S_MMR6 */
15425 5619,
15426 /* MAX_S_W */
15427 5622,
15428 /* MAX_U_B */
15429 5625,
15430 /* MAX_U_D */
15431 5628,
15432 /* MAX_U_H */
15433 5631,
15434 /* MAX_U_W */
15435 5634,
15436 /* MFC0 */
15437 5637,
15438 /* MFC0_MMR6 */
15439 5640,
15440 /* MFC1 */
15441 5643,
15442 /* MFC1_D64 */
15443 5645,
15444 /* MFC1_MM */
15445 5647,
15446 /* MFC1_MMR6 */
15447 5649,
15448 /* MFC2 */
15449 5651,
15450 /* MFC2_MMR6 */
15451 5654,
15452 /* MFGC0 */
15453 5656,
15454 /* MFGC0_MM */
15455 5659,
15456 /* MFHC0_MMR6 */
15457 5662,
15458 /* MFHC1_D32 */
15459 5665,
15460 /* MFHC1_D32_MM */
15461 5667,
15462 /* MFHC1_D64 */
15463 5669,
15464 /* MFHC1_D64_MM */
15465 5671,
15466 /* MFHC2_MMR6 */
15467 5673,
15468 /* MFHGC0 */
15469 5675,
15470 /* MFHGC0_MM */
15471 5678,
15472 /* MFHI */
15473 5681,
15474 /* MFHI16_MM */
15475 5682,
15476 /* MFHI64 */
15477 5683,
15478 /* MFHI_DSP */
15479 5684,
15480 /* MFHI_DSP_MM */
15481 5686,
15482 /* MFHI_MM */
15483 5688,
15484 /* MFLO */
15485 5689,
15486 /* MFLO16_MM */
15487 5690,
15488 /* MFLO64 */
15489 5691,
15490 /* MFLO_DSP */
15491 5692,
15492 /* MFLO_DSP_MM */
15493 5694,
15494 /* MFLO_MM */
15495 5696,
15496 /* MFTR */
15497 5697,
15498 /* MINA_D */
15499 5702,
15500 /* MINA_D_MMR6 */
15501 5705,
15502 /* MINA_S */
15503 5708,
15504 /* MINA_S_MMR6 */
15505 5711,
15506 /* MINI_S_B */
15507 5714,
15508 /* MINI_S_D */
15509 5717,
15510 /* MINI_S_H */
15511 5720,
15512 /* MINI_S_W */
15513 5723,
15514 /* MINI_U_B */
15515 5726,
15516 /* MINI_U_D */
15517 5729,
15518 /* MINI_U_H */
15519 5732,
15520 /* MINI_U_W */
15521 5735,
15522 /* MIN_A_B */
15523 5738,
15524 /* MIN_A_D */
15525 5741,
15526 /* MIN_A_H */
15527 5744,
15528 /* MIN_A_W */
15529 5747,
15530 /* MIN_D */
15531 5750,
15532 /* MIN_D_MMR6 */
15533 5753,
15534 /* MIN_S */
15535 5756,
15536 /* MIN_S_B */
15537 5759,
15538 /* MIN_S_D */
15539 5762,
15540 /* MIN_S_H */
15541 5765,
15542 /* MIN_S_MMR6 */
15543 5768,
15544 /* MIN_S_W */
15545 5771,
15546 /* MIN_U_B */
15547 5774,
15548 /* MIN_U_D */
15549 5777,
15550 /* MIN_U_H */
15551 5780,
15552 /* MIN_U_W */
15553 5783,
15554 /* MOD */
15555 5786,
15556 /* MODSUB */
15557 5789,
15558 /* MODSUB_MM */
15559 5792,
15560 /* MODU */
15561 5795,
15562 /* MODU_MMR6 */
15563 5798,
15564 /* MOD_MMR6 */
15565 5801,
15566 /* MOD_S_B */
15567 5804,
15568 /* MOD_S_D */
15569 5807,
15570 /* MOD_S_H */
15571 5810,
15572 /* MOD_S_W */
15573 5813,
15574 /* MOD_U_B */
15575 5816,
15576 /* MOD_U_D */
15577 5819,
15578 /* MOD_U_H */
15579 5822,
15580 /* MOD_U_W */
15581 5825,
15582 /* MOVE16_MM */
15583 5828,
15584 /* MOVE16_MMR6 */
15585 5830,
15586 /* MOVEP_MM */
15587 5832,
15588 /* MOVEP_MMR6 */
15589 5836,
15590 /* MOVE_V */
15591 5840,
15592 /* MOVF_D32 */
15593 5842,
15594 /* MOVF_D32_MM */
15595 5846,
15596 /* MOVF_D64 */
15597 5850,
15598 /* MOVF_I */
15599 5854,
15600 /* MOVF_I64 */
15601 5858,
15602 /* MOVF_I_MM */
15603 5862,
15604 /* MOVF_S */
15605 5866,
15606 /* MOVF_S_MM */
15607 5870,
15608 /* MOVN_I64_D64 */
15609 5874,
15610 /* MOVN_I64_I */
15611 5878,
15612 /* MOVN_I64_I64 */
15613 5882,
15614 /* MOVN_I64_S */
15615 5886,
15616 /* MOVN_I_D32 */
15617 5890,
15618 /* MOVN_I_D32_MM */
15619 5894,
15620 /* MOVN_I_D64 */
15621 5898,
15622 /* MOVN_I_I */
15623 5902,
15624 /* MOVN_I_I64 */
15625 5906,
15626 /* MOVN_I_MM */
15627 5910,
15628 /* MOVN_I_S */
15629 5914,
15630 /* MOVN_I_S_MM */
15631 5918,
15632 /* MOVT_D32 */
15633 5922,
15634 /* MOVT_D32_MM */
15635 5926,
15636 /* MOVT_D64 */
15637 5930,
15638 /* MOVT_I */
15639 5934,
15640 /* MOVT_I64 */
15641 5938,
15642 /* MOVT_I_MM */
15643 5942,
15644 /* MOVT_S */
15645 5946,
15646 /* MOVT_S_MM */
15647 5950,
15648 /* MOVZ_I64_D64 */
15649 5954,
15650 /* MOVZ_I64_I */
15651 5958,
15652 /* MOVZ_I64_I64 */
15653 5962,
15654 /* MOVZ_I64_S */
15655 5966,
15656 /* MOVZ_I_D32 */
15657 5970,
15658 /* MOVZ_I_D32_MM */
15659 5974,
15660 /* MOVZ_I_D64 */
15661 5978,
15662 /* MOVZ_I_I */
15663 5982,
15664 /* MOVZ_I_I64 */
15665 5986,
15666 /* MOVZ_I_MM */
15667 5990,
15668 /* MOVZ_I_S */
15669 5994,
15670 /* MOVZ_I_S_MM */
15671 5998,
15672 /* MSUB */
15673 6002,
15674 /* MSUBF_D */
15675 6004,
15676 /* MSUBF_D_MMR6 */
15677 6008,
15678 /* MSUBF_S */
15679 6012,
15680 /* MSUBF_S_MMR6 */
15681 6016,
15682 /* MSUBR_Q_H */
15683 6020,
15684 /* MSUBR_Q_W */
15685 6024,
15686 /* MSUBU */
15687 6028,
15688 /* MSUBU_DSP */
15689 6030,
15690 /* MSUBU_DSP_MM */
15691 6034,
15692 /* MSUBU_MM */
15693 6038,
15694 /* MSUBV_B */
15695 6040,
15696 /* MSUBV_D */
15697 6044,
15698 /* MSUBV_H */
15699 6048,
15700 /* MSUBV_W */
15701 6052,
15702 /* MSUB_D32 */
15703 6056,
15704 /* MSUB_D32_MM */
15705 6060,
15706 /* MSUB_D64 */
15707 6064,
15708 /* MSUB_DSP */
15709 6068,
15710 /* MSUB_DSP_MM */
15711 6072,
15712 /* MSUB_MM */
15713 6076,
15714 /* MSUB_Q_H */
15715 6078,
15716 /* MSUB_Q_W */
15717 6082,
15718 /* MSUB_S */
15719 6086,
15720 /* MSUB_S_MM */
15721 6090,
15722 /* MTC0 */
15723 6094,
15724 /* MTC0_MMR6 */
15725 6097,
15726 /* MTC1 */
15727 6100,
15728 /* MTC1_D64 */
15729 6102,
15730 /* MTC1_D64_MM */
15731 6104,
15732 /* MTC1_MM */
15733 6106,
15734 /* MTC1_MMR6 */
15735 6108,
15736 /* MTC2 */
15737 6110,
15738 /* MTC2_MMR6 */
15739 6113,
15740 /* MTGC0 */
15741 6115,
15742 /* MTGC0_MM */
15743 6118,
15744 /* MTHC0_MMR6 */
15745 6121,
15746 /* MTHC1_D32 */
15747 6124,
15748 /* MTHC1_D32_MM */
15749 6127,
15750 /* MTHC1_D64 */
15751 6130,
15752 /* MTHC1_D64_MM */
15753 6133,
15754 /* MTHC2_MMR6 */
15755 6136,
15756 /* MTHGC0 */
15757 6138,
15758 /* MTHGC0_MM */
15759 6141,
15760 /* MTHI */
15761 6144,
15762 /* MTHI64 */
15763 6145,
15764 /* MTHI_DSP */
15765 6146,
15766 /* MTHI_DSP_MM */
15767 6148,
15768 /* MTHI_MM */
15769 6150,
15770 /* MTHLIP */
15771 6151,
15772 /* MTHLIP_MM */
15773 6154,
15774 /* MTLO */
15775 6157,
15776 /* MTLO64 */
15777 6158,
15778 /* MTLO_DSP */
15779 6159,
15780 /* MTLO_DSP_MM */
15781 6161,
15782 /* MTLO_MM */
15783 6163,
15784 /* MTM0 */
15785 6164,
15786 /* MTM1 */
15787 6165,
15788 /* MTM2 */
15789 6166,
15790 /* MTP0 */
15791 6167,
15792 /* MTP1 */
15793 6168,
15794 /* MTP2 */
15795 6169,
15796 /* MTTR */
15797 6170,
15798 /* MUH */
15799 6175,
15800 /* MUHU */
15801 6178,
15802 /* MUHU_MMR6 */
15803 6181,
15804 /* MUH_MMR6 */
15805 6184,
15806 /* MUL */
15807 6187,
15808 /* MULEQ_S_W_PHL */
15809 6190,
15810 /* MULEQ_S_W_PHL_MM */
15811 6193,
15812 /* MULEQ_S_W_PHR */
15813 6196,
15814 /* MULEQ_S_W_PHR_MM */
15815 6199,
15816 /* MULEU_S_PH_QBL */
15817 6202,
15818 /* MULEU_S_PH_QBL_MM */
15819 6205,
15820 /* MULEU_S_PH_QBR */
15821 6208,
15822 /* MULEU_S_PH_QBR_MM */
15823 6211,
15824 /* MULQ_RS_PH */
15825 6214,
15826 /* MULQ_RS_PH_MM */
15827 6217,
15828 /* MULQ_RS_W */
15829 6220,
15830 /* MULQ_RS_W_MMR2 */
15831 6223,
15832 /* MULQ_S_PH */
15833 6226,
15834 /* MULQ_S_PH_MMR2 */
15835 6229,
15836 /* MULQ_S_W */
15837 6232,
15838 /* MULQ_S_W_MMR2 */
15839 6235,
15840 /* MULR_PS64 */
15841 6238,
15842 /* MULR_Q_H */
15843 6241,
15844 /* MULR_Q_W */
15845 6244,
15846 /* MULSAQ_S_W_PH */
15847 6247,
15848 /* MULSAQ_S_W_PH_MM */
15849 6251,
15850 /* MULSA_W_PH */
15851 6255,
15852 /* MULSA_W_PH_MMR2 */
15853 6259,
15854 /* MULT */
15855 6263,
15856 /* MULTU_DSP */
15857 6265,
15858 /* MULTU_DSP_MM */
15859 6268,
15860 /* MULT_DSP */
15861 6271,
15862 /* MULT_DSP_MM */
15863 6274,
15864 /* MULT_MM */
15865 6277,
15866 /* MULTu */
15867 6279,
15868 /* MULTu_MM */
15869 6281,
15870 /* MULU */
15871 6283,
15872 /* MULU_MMR6 */
15873 6286,
15874 /* MULV_B */
15875 6289,
15876 /* MULV_D */
15877 6292,
15878 /* MULV_H */
15879 6295,
15880 /* MULV_W */
15881 6298,
15882 /* MUL_MM */
15883 6301,
15884 /* MUL_MMR6 */
15885 6304,
15886 /* MUL_PH */
15887 6307,
15888 /* MUL_PH_MMR2 */
15889 6310,
15890 /* MUL_Q_H */
15891 6313,
15892 /* MUL_Q_W */
15893 6316,
15894 /* MUL_R6 */
15895 6319,
15896 /* MUL_S_PH */
15897 6322,
15898 /* MUL_S_PH_MMR2 */
15899 6325,
15900 /* Mfhi16 */
15901 6328,
15902 /* Mflo16 */
15903 6329,
15904 /* Move32R16 */
15905 6330,
15906 /* MoveR3216 */
15907 6332,
15908 /* NAL */
15909 6334,
15910 /* NLOC_B */
15911 6334,
15912 /* NLOC_D */
15913 6336,
15914 /* NLOC_H */
15915 6338,
15916 /* NLOC_W */
15917 6340,
15918 /* NLZC_B */
15919 6342,
15920 /* NLZC_D */
15921 6344,
15922 /* NLZC_H */
15923 6346,
15924 /* NLZC_W */
15925 6348,
15926 /* NMADD_D32 */
15927 6350,
15928 /* NMADD_D32_MM */
15929 6354,
15930 /* NMADD_D64 */
15931 6358,
15932 /* NMADD_S */
15933 6362,
15934 /* NMADD_S_MM */
15935 6366,
15936 /* NMSUB_D32 */
15937 6370,
15938 /* NMSUB_D32_MM */
15939 6374,
15940 /* NMSUB_D64 */
15941 6378,
15942 /* NMSUB_S */
15943 6382,
15944 /* NMSUB_S_MM */
15945 6386,
15946 /* NOR */
15947 6390,
15948 /* NOR64 */
15949 6393,
15950 /* NORI_B */
15951 6396,
15952 /* NOR_MM */
15953 6399,
15954 /* NOR_MMR6 */
15955 6402,
15956 /* NOR_V */
15957 6405,
15958 /* NOT16_MM */
15959 6408,
15960 /* NOT16_MMR6 */
15961 6410,
15962 /* NegRxRy16 */
15963 6412,
15964 /* NotRxRy16 */
15965 6414,
15966 /* OR */
15967 6416,
15968 /* OR16_MM */
15969 6419,
15970 /* OR16_MMR6 */
15971 6422,
15972 /* OR64 */
15973 6425,
15974 /* ORI_B */
15975 6428,
15976 /* ORI_MMR6 */
15977 6431,
15978 /* OR_MM */
15979 6434,
15980 /* OR_MMR6 */
15981 6437,
15982 /* OR_V */
15983 6440,
15984 /* ORi */
15985 6443,
15986 /* ORi64 */
15987 6446,
15988 /* ORi_MM */
15989 6449,
15990 /* OrRxRxRy16 */
15991 6452,
15992 /* PACKRL_PH */
15993 6455,
15994 /* PACKRL_PH_MM */
15995 6458,
15996 /* PAUSE */
15997 6461,
15998 /* PAUSE_MM */
15999 6461,
16000 /* PAUSE_MMR6 */
16001 6461,
16002 /* PCKEV_B */
16003 6461,
16004 /* PCKEV_D */
16005 6464,
16006 /* PCKEV_H */
16007 6467,
16008 /* PCKEV_W */
16009 6470,
16010 /* PCKOD_B */
16011 6473,
16012 /* PCKOD_D */
16013 6476,
16014 /* PCKOD_H */
16015 6479,
16016 /* PCKOD_W */
16017 6482,
16018 /* PCNT_B */
16019 6485,
16020 /* PCNT_D */
16021 6487,
16022 /* PCNT_H */
16023 6489,
16024 /* PCNT_W */
16025 6491,
16026 /* PICK_PH */
16027 6493,
16028 /* PICK_PH_MM */
16029 6496,
16030 /* PICK_QB */
16031 6499,
16032 /* PICK_QB_MM */
16033 6502,
16034 /* PLL_PS64 */
16035 6505,
16036 /* PLU_PS64 */
16037 6508,
16038 /* POP */
16039 6511,
16040 /* PRECEQU_PH_QBL */
16041 6513,
16042 /* PRECEQU_PH_QBLA */
16043 6515,
16044 /* PRECEQU_PH_QBLA_MM */
16045 6517,
16046 /* PRECEQU_PH_QBL_MM */
16047 6519,
16048 /* PRECEQU_PH_QBR */
16049 6521,
16050 /* PRECEQU_PH_QBRA */
16051 6523,
16052 /* PRECEQU_PH_QBRA_MM */
16053 6525,
16054 /* PRECEQU_PH_QBR_MM */
16055 6527,
16056 /* PRECEQ_W_PHL */
16057 6529,
16058 /* PRECEQ_W_PHL_MM */
16059 6531,
16060 /* PRECEQ_W_PHR */
16061 6533,
16062 /* PRECEQ_W_PHR_MM */
16063 6535,
16064 /* PRECEU_PH_QBL */
16065 6537,
16066 /* PRECEU_PH_QBLA */
16067 6539,
16068 /* PRECEU_PH_QBLA_MM */
16069 6541,
16070 /* PRECEU_PH_QBL_MM */
16071 6543,
16072 /* PRECEU_PH_QBR */
16073 6545,
16074 /* PRECEU_PH_QBRA */
16075 6547,
16076 /* PRECEU_PH_QBRA_MM */
16077 6549,
16078 /* PRECEU_PH_QBR_MM */
16079 6551,
16080 /* PRECRQU_S_QB_PH */
16081 6553,
16082 /* PRECRQU_S_QB_PH_MM */
16083 6556,
16084 /* PRECRQ_PH_W */
16085 6559,
16086 /* PRECRQ_PH_W_MM */
16087 6562,
16088 /* PRECRQ_QB_PH */
16089 6565,
16090 /* PRECRQ_QB_PH_MM */
16091 6568,
16092 /* PRECRQ_RS_PH_W */
16093 6571,
16094 /* PRECRQ_RS_PH_W_MM */
16095 6574,
16096 /* PRECR_QB_PH */
16097 6577,
16098 /* PRECR_QB_PH_MMR2 */
16099 6580,
16100 /* PRECR_SRA_PH_W */
16101 6583,
16102 /* PRECR_SRA_PH_W_MMR2 */
16103 6587,
16104 /* PRECR_SRA_R_PH_W */
16105 6591,
16106 /* PRECR_SRA_R_PH_W_MMR2 */
16107 6595,
16108 /* PREF */
16109 6599,
16110 /* PREFE */
16111 6602,
16112 /* PREFE_MM */
16113 6605,
16114 /* PREFX_MM */
16115 6608,
16116 /* PREF_MM */
16117 6611,
16118 /* PREF_MMR6 */
16119 6614,
16120 /* PREF_R6 */
16121 6617,
16122 /* PREPEND */
16123 6620,
16124 /* PREPEND_MMR2 */
16125 6624,
16126 /* PUL_PS64 */
16127 6628,
16128 /* PUU_PS64 */
16129 6631,
16130 /* RADDU_W_QB */
16131 6634,
16132 /* RADDU_W_QB_MM */
16133 6636,
16134 /* RDDSP */
16135 6638,
16136 /* RDDSP_MM */
16137 6640,
16138 /* RDHWR */
16139 6642,
16140 /* RDHWR64 */
16141 6645,
16142 /* RDHWR_MM */
16143 6648,
16144 /* RDHWR_MMR6 */
16145 6651,
16146 /* RDPGPR_MMR6 */
16147 6654,
16148 /* RECIP_D32 */
16149 6656,
16150 /* RECIP_D32_MM */
16151 6658,
16152 /* RECIP_D64 */
16153 6660,
16154 /* RECIP_D64_MM */
16155 6662,
16156 /* RECIP_S */
16157 6664,
16158 /* RECIP_S_MM */
16159 6666,
16160 /* REPLV_PH */
16161 6668,
16162 /* REPLV_PH_MM */
16163 6670,
16164 /* REPLV_QB */
16165 6672,
16166 /* REPLV_QB_MM */
16167 6674,
16168 /* REPL_PH */
16169 6676,
16170 /* REPL_PH_MM */
16171 6678,
16172 /* REPL_QB */
16173 6680,
16174 /* REPL_QB_MM */
16175 6682,
16176 /* RINT_D */
16177 6684,
16178 /* RINT_D_MMR6 */
16179 6686,
16180 /* RINT_S */
16181 6688,
16182 /* RINT_S_MMR6 */
16183 6690,
16184 /* ROTR */
16185 6692,
16186 /* ROTRV */
16187 6695,
16188 /* ROTRV_MM */
16189 6698,
16190 /* ROTR_MM */
16191 6701,
16192 /* ROUND_L_D64 */
16193 6704,
16194 /* ROUND_L_D_MMR6 */
16195 6706,
16196 /* ROUND_L_S */
16197 6708,
16198 /* ROUND_L_S_MMR6 */
16199 6710,
16200 /* ROUND_W_D32 */
16201 6712,
16202 /* ROUND_W_D64 */
16203 6714,
16204 /* ROUND_W_D_MMR6 */
16205 6716,
16206 /* ROUND_W_MM */
16207 6718,
16208 /* ROUND_W_S */
16209 6720,
16210 /* ROUND_W_S_MM */
16211 6722,
16212 /* ROUND_W_S_MMR6 */
16213 6724,
16214 /* RSQRT_D32 */
16215 6726,
16216 /* RSQRT_D32_MM */
16217 6728,
16218 /* RSQRT_D64 */
16219 6730,
16220 /* RSQRT_D64_MM */
16221 6732,
16222 /* RSQRT_S */
16223 6734,
16224 /* RSQRT_S_MM */
16225 6736,
16226 /* Restore16 */
16227 6738,
16228 /* RestoreX16 */
16229 6738,
16230 /* SAA */
16231 6738,
16232 /* SAAD */
16233 6740,
16234 /* SAT_S_B */
16235 6742,
16236 /* SAT_S_D */
16237 6745,
16238 /* SAT_S_H */
16239 6748,
16240 /* SAT_S_W */
16241 6751,
16242 /* SAT_U_B */
16243 6754,
16244 /* SAT_U_D */
16245 6757,
16246 /* SAT_U_H */
16247 6760,
16248 /* SAT_U_W */
16249 6763,
16250 /* SB */
16251 6766,
16252 /* SB16_MM */
16253 6769,
16254 /* SB16_MMR6 */
16255 6772,
16256 /* SB64 */
16257 6775,
16258 /* SBE */
16259 6778,
16260 /* SBE_MM */
16261 6781,
16262 /* SB_MM */
16263 6784,
16264 /* SB_MMR6 */
16265 6787,
16266 /* SC */
16267 6790,
16268 /* SC64 */
16269 6794,
16270 /* SC64_R6 */
16271 6798,
16272 /* SCD */
16273 6802,
16274 /* SCD_R6 */
16275 6806,
16276 /* SCE */
16277 6810,
16278 /* SCE_MM */
16279 6814,
16280 /* SC_MM */
16281 6818,
16282 /* SC_MMR6 */
16283 6822,
16284 /* SC_R6 */
16285 6826,
16286 /* SD */
16287 6830,
16288 /* SDBBP */
16289 6833,
16290 /* SDBBP16_MM */
16291 6834,
16292 /* SDBBP16_MMR6 */
16293 6835,
16294 /* SDBBP_MM */
16295 6836,
16296 /* SDBBP_MMR6 */
16297 6837,
16298 /* SDBBP_R6 */
16299 6838,
16300 /* SDC1 */
16301 6839,
16302 /* SDC164 */
16303 6842,
16304 /* SDC1_D64_MMR6 */
16305 6845,
16306 /* SDC1_MM_D32 */
16307 6848,
16308 /* SDC1_MM_D64 */
16309 6851,
16310 /* SDC2 */
16311 6854,
16312 /* SDC2_MMR6 */
16313 6857,
16314 /* SDC2_R6 */
16315 6860,
16316 /* SDC3 */
16317 6863,
16318 /* SDIV */
16319 6866,
16320 /* SDIV_MM */
16321 6868,
16322 /* SDL */
16323 6870,
16324 /* SDR */
16325 6873,
16326 /* SDXC1 */
16327 6876,
16328 /* SDXC164 */
16329 6879,
16330 /* SEB */
16331 6882,
16332 /* SEB64 */
16333 6884,
16334 /* SEB_MM */
16335 6886,
16336 /* SEH */
16337 6888,
16338 /* SEH64 */
16339 6890,
16340 /* SEH_MM */
16341 6892,
16342 /* SELEQZ */
16343 6894,
16344 /* SELEQZ64 */
16345 6897,
16346 /* SELEQZ_D */
16347 6900,
16348 /* SELEQZ_D_MMR6 */
16349 6903,
16350 /* SELEQZ_MMR6 */
16351 6906,
16352 /* SELEQZ_S */
16353 6909,
16354 /* SELEQZ_S_MMR6 */
16355 6912,
16356 /* SELNEZ */
16357 6915,
16358 /* SELNEZ64 */
16359 6918,
16360 /* SELNEZ_D */
16361 6921,
16362 /* SELNEZ_D_MMR6 */
16363 6924,
16364 /* SELNEZ_MMR6 */
16365 6927,
16366 /* SELNEZ_S */
16367 6930,
16368 /* SELNEZ_S_MMR6 */
16369 6933,
16370 /* SEL_D */
16371 6936,
16372 /* SEL_D_MMR6 */
16373 6940,
16374 /* SEL_S */
16375 6944,
16376 /* SEL_S_MMR6 */
16377 6948,
16378 /* SEQ */
16379 6952,
16380 /* SEQi */
16381 6955,
16382 /* SH */
16383 6958,
16384 /* SH16_MM */
16385 6961,
16386 /* SH16_MMR6 */
16387 6964,
16388 /* SH64 */
16389 6967,
16390 /* SHE */
16391 6970,
16392 /* SHE_MM */
16393 6973,
16394 /* SHF_B */
16395 6976,
16396 /* SHF_H */
16397 6979,
16398 /* SHF_W */
16399 6982,
16400 /* SHILO */
16401 6985,
16402 /* SHILOV */
16403 6988,
16404 /* SHILOV_MM */
16405 6991,
16406 /* SHILO_MM */
16407 6994,
16408 /* SHLLV_PH */
16409 6997,
16410 /* SHLLV_PH_MM */
16411 7000,
16412 /* SHLLV_QB */
16413 7003,
16414 /* SHLLV_QB_MM */
16415 7006,
16416 /* SHLLV_S_PH */
16417 7009,
16418 /* SHLLV_S_PH_MM */
16419 7012,
16420 /* SHLLV_S_W */
16421 7015,
16422 /* SHLLV_S_W_MM */
16423 7018,
16424 /* SHLL_PH */
16425 7021,
16426 /* SHLL_PH_MM */
16427 7024,
16428 /* SHLL_QB */
16429 7027,
16430 /* SHLL_QB_MM */
16431 7030,
16432 /* SHLL_S_PH */
16433 7033,
16434 /* SHLL_S_PH_MM */
16435 7036,
16436 /* SHLL_S_W */
16437 7039,
16438 /* SHLL_S_W_MM */
16439 7042,
16440 /* SHRAV_PH */
16441 7045,
16442 /* SHRAV_PH_MM */
16443 7048,
16444 /* SHRAV_QB */
16445 7051,
16446 /* SHRAV_QB_MMR2 */
16447 7054,
16448 /* SHRAV_R_PH */
16449 7057,
16450 /* SHRAV_R_PH_MM */
16451 7060,
16452 /* SHRAV_R_QB */
16453 7063,
16454 /* SHRAV_R_QB_MMR2 */
16455 7066,
16456 /* SHRAV_R_W */
16457 7069,
16458 /* SHRAV_R_W_MM */
16459 7072,
16460 /* SHRA_PH */
16461 7075,
16462 /* SHRA_PH_MM */
16463 7078,
16464 /* SHRA_QB */
16465 7081,
16466 /* SHRA_QB_MMR2 */
16467 7084,
16468 /* SHRA_R_PH */
16469 7087,
16470 /* SHRA_R_PH_MM */
16471 7090,
16472 /* SHRA_R_QB */
16473 7093,
16474 /* SHRA_R_QB_MMR2 */
16475 7096,
16476 /* SHRA_R_W */
16477 7099,
16478 /* SHRA_R_W_MM */
16479 7102,
16480 /* SHRLV_PH */
16481 7105,
16482 /* SHRLV_PH_MMR2 */
16483 7108,
16484 /* SHRLV_QB */
16485 7111,
16486 /* SHRLV_QB_MM */
16487 7114,
16488 /* SHRL_PH */
16489 7117,
16490 /* SHRL_PH_MMR2 */
16491 7120,
16492 /* SHRL_QB */
16493 7123,
16494 /* SHRL_QB_MM */
16495 7126,
16496 /* SH_MM */
16497 7129,
16498 /* SH_MMR6 */
16499 7132,
16500 /* SIGRIE */
16501 7135,
16502 /* SIGRIE_MMR6 */
16503 7136,
16504 /* SLDI_B */
16505 7137,
16506 /* SLDI_D */
16507 7141,
16508 /* SLDI_H */
16509 7145,
16510 /* SLDI_W */
16511 7149,
16512 /* SLD_B */
16513 7153,
16514 /* SLD_D */
16515 7157,
16516 /* SLD_H */
16517 7161,
16518 /* SLD_W */
16519 7165,
16520 /* SLL */
16521 7169,
16522 /* SLL16_MM */
16523 7172,
16524 /* SLL16_MMR6 */
16525 7175,
16526 /* SLL64_32 */
16527 7178,
16528 /* SLL64_64 */
16529 7180,
16530 /* SLLI_B */
16531 7182,
16532 /* SLLI_D */
16533 7185,
16534 /* SLLI_H */
16535 7188,
16536 /* SLLI_W */
16537 7191,
16538 /* SLLV */
16539 7194,
16540 /* SLLV_MM */
16541 7197,
16542 /* SLL_B */
16543 7200,
16544 /* SLL_D */
16545 7203,
16546 /* SLL_H */
16547 7206,
16548 /* SLL_MM */
16549 7209,
16550 /* SLL_MMR6 */
16551 7212,
16552 /* SLL_W */
16553 7215,
16554 /* SLT */
16555 7218,
16556 /* SLT64 */
16557 7221,
16558 /* SLT_MM */
16559 7224,
16560 /* SLTi */
16561 7227,
16562 /* SLTi64 */
16563 7230,
16564 /* SLTi_MM */
16565 7233,
16566 /* SLTiu */
16567 7236,
16568 /* SLTiu64 */
16569 7239,
16570 /* SLTiu_MM */
16571 7242,
16572 /* SLTu */
16573 7245,
16574 /* SLTu64 */
16575 7248,
16576 /* SLTu_MM */
16577 7251,
16578 /* SNE */
16579 7254,
16580 /* SNEi */
16581 7257,
16582 /* SPLATI_B */
16583 7260,
16584 /* SPLATI_D */
16585 7263,
16586 /* SPLATI_H */
16587 7266,
16588 /* SPLATI_W */
16589 7269,
16590 /* SPLAT_B */
16591 7272,
16592 /* SPLAT_D */
16593 7275,
16594 /* SPLAT_H */
16595 7278,
16596 /* SPLAT_W */
16597 7281,
16598 /* SRA */
16599 7284,
16600 /* SRAI_B */
16601 7287,
16602 /* SRAI_D */
16603 7290,
16604 /* SRAI_H */
16605 7293,
16606 /* SRAI_W */
16607 7296,
16608 /* SRARI_B */
16609 7299,
16610 /* SRARI_D */
16611 7302,
16612 /* SRARI_H */
16613 7305,
16614 /* SRARI_W */
16615 7308,
16616 /* SRAR_B */
16617 7311,
16618 /* SRAR_D */
16619 7314,
16620 /* SRAR_H */
16621 7317,
16622 /* SRAR_W */
16623 7320,
16624 /* SRAV */
16625 7323,
16626 /* SRAV_MM */
16627 7326,
16628 /* SRA_B */
16629 7329,
16630 /* SRA_D */
16631 7332,
16632 /* SRA_H */
16633 7335,
16634 /* SRA_MM */
16635 7338,
16636 /* SRA_W */
16637 7341,
16638 /* SRL */
16639 7344,
16640 /* SRL16_MM */
16641 7347,
16642 /* SRL16_MMR6 */
16643 7350,
16644 /* SRLI_B */
16645 7353,
16646 /* SRLI_D */
16647 7356,
16648 /* SRLI_H */
16649 7359,
16650 /* SRLI_W */
16651 7362,
16652 /* SRLRI_B */
16653 7365,
16654 /* SRLRI_D */
16655 7368,
16656 /* SRLRI_H */
16657 7371,
16658 /* SRLRI_W */
16659 7374,
16660 /* SRLR_B */
16661 7377,
16662 /* SRLR_D */
16663 7380,
16664 /* SRLR_H */
16665 7383,
16666 /* SRLR_W */
16667 7386,
16668 /* SRLV */
16669 7389,
16670 /* SRLV_MM */
16671 7392,
16672 /* SRL_B */
16673 7395,
16674 /* SRL_D */
16675 7398,
16676 /* SRL_H */
16677 7401,
16678 /* SRL_MM */
16679 7404,
16680 /* SRL_W */
16681 7407,
16682 /* SSNOP */
16683 7410,
16684 /* SSNOP_MM */
16685 7410,
16686 /* SSNOP_MMR6 */
16687 7410,
16688 /* ST_B */
16689 7410,
16690 /* ST_D */
16691 7413,
16692 /* ST_H */
16693 7416,
16694 /* ST_W */
16695 7419,
16696 /* SUB */
16697 7422,
16698 /* SUBQH_PH */
16699 7425,
16700 /* SUBQH_PH_MMR2 */
16701 7428,
16702 /* SUBQH_R_PH */
16703 7431,
16704 /* SUBQH_R_PH_MMR2 */
16705 7434,
16706 /* SUBQH_R_W */
16707 7437,
16708 /* SUBQH_R_W_MMR2 */
16709 7440,
16710 /* SUBQH_W */
16711 7443,
16712 /* SUBQH_W_MMR2 */
16713 7446,
16714 /* SUBQ_PH */
16715 7449,
16716 /* SUBQ_PH_MM */
16717 7452,
16718 /* SUBQ_S_PH */
16719 7455,
16720 /* SUBQ_S_PH_MM */
16721 7458,
16722 /* SUBQ_S_W */
16723 7461,
16724 /* SUBQ_S_W_MM */
16725 7464,
16726 /* SUBSUS_U_B */
16727 7467,
16728 /* SUBSUS_U_D */
16729 7470,
16730 /* SUBSUS_U_H */
16731 7473,
16732 /* SUBSUS_U_W */
16733 7476,
16734 /* SUBSUU_S_B */
16735 7479,
16736 /* SUBSUU_S_D */
16737 7482,
16738 /* SUBSUU_S_H */
16739 7485,
16740 /* SUBSUU_S_W */
16741 7488,
16742 /* SUBS_S_B */
16743 7491,
16744 /* SUBS_S_D */
16745 7494,
16746 /* SUBS_S_H */
16747 7497,
16748 /* SUBS_S_W */
16749 7500,
16750 /* SUBS_U_B */
16751 7503,
16752 /* SUBS_U_D */
16753 7506,
16754 /* SUBS_U_H */
16755 7509,
16756 /* SUBS_U_W */
16757 7512,
16758 /* SUBU16_MM */
16759 7515,
16760 /* SUBU16_MMR6 */
16761 7518,
16762 /* SUBUH_QB */
16763 7521,
16764 /* SUBUH_QB_MMR2 */
16765 7524,
16766 /* SUBUH_R_QB */
16767 7527,
16768 /* SUBUH_R_QB_MMR2 */
16769 7530,
16770 /* SUBU_MMR6 */
16771 7533,
16772 /* SUBU_PH */
16773 7536,
16774 /* SUBU_PH_MMR2 */
16775 7539,
16776 /* SUBU_QB */
16777 7542,
16778 /* SUBU_QB_MM */
16779 7545,
16780 /* SUBU_S_PH */
16781 7548,
16782 /* SUBU_S_PH_MMR2 */
16783 7551,
16784 /* SUBU_S_QB */
16785 7554,
16786 /* SUBU_S_QB_MM */
16787 7557,
16788 /* SUBVI_B */
16789 7560,
16790 /* SUBVI_D */
16791 7563,
16792 /* SUBVI_H */
16793 7566,
16794 /* SUBVI_W */
16795 7569,
16796 /* SUBV_B */
16797 7572,
16798 /* SUBV_D */
16799 7575,
16800 /* SUBV_H */
16801 7578,
16802 /* SUBV_W */
16803 7581,
16804 /* SUB_MM */
16805 7584,
16806 /* SUB_MMR6 */
16807 7587,
16808 /* SUBu */
16809 7590,
16810 /* SUBu_MM */
16811 7593,
16812 /* SUXC1 */
16813 7596,
16814 /* SUXC164 */
16815 7599,
16816 /* SUXC1_MM */
16817 7602,
16818 /* SW */
16819 7605,
16820 /* SW16_MM */
16821 7608,
16822 /* SW16_MMR6 */
16823 7611,
16824 /* SW64 */
16825 7614,
16826 /* SWC1 */
16827 7617,
16828 /* SWC1_MM */
16829 7620,
16830 /* SWC2 */
16831 7623,
16832 /* SWC2_MMR6 */
16833 7626,
16834 /* SWC2_R6 */
16835 7629,
16836 /* SWC3 */
16837 7632,
16838 /* SWDSP */
16839 7635,
16840 /* SWDSP_MM */
16841 7638,
16842 /* SWE */
16843 7641,
16844 /* SWE_MM */
16845 7644,
16846 /* SWL */
16847 7647,
16848 /* SWL64 */
16849 7650,
16850 /* SWLE */
16851 7653,
16852 /* SWLE_MM */
16853 7656,
16854 /* SWL_MM */
16855 7659,
16856 /* SWM16_MM */
16857 7662,
16858 /* SWM16_MMR6 */
16859 7665,
16860 /* SWM32_MM */
16861 7668,
16862 /* SWP_MM */
16863 7671,
16864 /* SWR */
16865 7675,
16866 /* SWR64 */
16867 7678,
16868 /* SWRE */
16869 7681,
16870 /* SWRE_MM */
16871 7684,
16872 /* SWR_MM */
16873 7687,
16874 /* SWSP_MM */
16875 7690,
16876 /* SWSP_MMR6 */
16877 7693,
16878 /* SWXC1 */
16879 7696,
16880 /* SWXC1_MM */
16881 7699,
16882 /* SW_MM */
16883 7702,
16884 /* SW_MMR6 */
16885 7705,
16886 /* SYNC */
16887 7708,
16888 /* SYNCI */
16889 7709,
16890 /* SYNCI_MM */
16891 7711,
16892 /* SYNCI_MMR6 */
16893 7713,
16894 /* SYNC_MM */
16895 7715,
16896 /* SYNC_MMR6 */
16897 7716,
16898 /* SYSCALL */
16899 7717,
16900 /* SYSCALL_MM */
16901 7718,
16902 /* Save16 */
16903 7719,
16904 /* SaveX16 */
16905 7719,
16906 /* SbRxRyOffMemX16 */
16907 7719,
16908 /* SebRx16 */
16909 7722,
16910 /* SehRx16 */
16911 7724,
16912 /* ShRxRyOffMemX16 */
16913 7726,
16914 /* SllX16 */
16915 7729,
16916 /* SllvRxRy16 */
16917 7732,
16918 /* SltRxRy16 */
16919 7735,
16920 /* SltiRxImm16 */
16921 7737,
16922 /* SltiRxImmX16 */
16923 7739,
16924 /* SltiuRxImm16 */
16925 7741,
16926 /* SltiuRxImmX16 */
16927 7743,
16928 /* SltuRxRy16 */
16929 7745,
16930 /* SraX16 */
16931 7747,
16932 /* SravRxRy16 */
16933 7750,
16934 /* SrlX16 */
16935 7753,
16936 /* SrlvRxRy16 */
16937 7756,
16938 /* SubuRxRyRz16 */
16939 7759,
16940 /* SwRxRyOffMemX16 */
16941 7762,
16942 /* SwRxSpImmX16 */
16943 7765,
16944 /* TEQ */
16945 7768,
16946 /* TEQI */
16947 7771,
16948 /* TEQI_MM */
16949 7773,
16950 /* TEQ_MM */
16951 7775,
16952 /* TGE */
16953 7778,
16954 /* TGEI */
16955 7781,
16956 /* TGEIU */
16957 7783,
16958 /* TGEIU_MM */
16959 7785,
16960 /* TGEI_MM */
16961 7787,
16962 /* TGEU */
16963 7789,
16964 /* TGEU_MM */
16965 7792,
16966 /* TGE_MM */
16967 7795,
16968 /* TLBGINV */
16969 7798,
16970 /* TLBGINVF */
16971 7798,
16972 /* TLBGINVF_MM */
16973 7798,
16974 /* TLBGINV_MM */
16975 7798,
16976 /* TLBGP */
16977 7798,
16978 /* TLBGP_MM */
16979 7798,
16980 /* TLBGR */
16981 7798,
16982 /* TLBGR_MM */
16983 7798,
16984 /* TLBGWI */
16985 7798,
16986 /* TLBGWI_MM */
16987 7798,
16988 /* TLBGWR */
16989 7798,
16990 /* TLBGWR_MM */
16991 7798,
16992 /* TLBINV */
16993 7798,
16994 /* TLBINVF */
16995 7798,
16996 /* TLBINVF_MMR6 */
16997 7798,
16998 /* TLBINV_MMR6 */
16999 7798,
17000 /* TLBP */
17001 7798,
17002 /* TLBP_MM */
17003 7798,
17004 /* TLBR */
17005 7798,
17006 /* TLBR_MM */
17007 7798,
17008 /* TLBWI */
17009 7798,
17010 /* TLBWI_MM */
17011 7798,
17012 /* TLBWR */
17013 7798,
17014 /* TLBWR_MM */
17015 7798,
17016 /* TLT */
17017 7798,
17018 /* TLTI */
17019 7801,
17020 /* TLTIU_MM */
17021 7803,
17022 /* TLTI_MM */
17023 7805,
17024 /* TLTU */
17025 7807,
17026 /* TLTU_MM */
17027 7810,
17028 /* TLT_MM */
17029 7813,
17030 /* TNE */
17031 7816,
17032 /* TNEI */
17033 7819,
17034 /* TNEI_MM */
17035 7821,
17036 /* TNE_MM */
17037 7823,
17038 /* TRUNC_L_D64 */
17039 7826,
17040 /* TRUNC_L_D_MMR6 */
17041 7828,
17042 /* TRUNC_L_S */
17043 7830,
17044 /* TRUNC_L_S_MMR6 */
17045 7832,
17046 /* TRUNC_W_D32 */
17047 7834,
17048 /* TRUNC_W_D64 */
17049 7836,
17050 /* TRUNC_W_D_MMR6 */
17051 7838,
17052 /* TRUNC_W_MM */
17053 7840,
17054 /* TRUNC_W_S */
17055 7842,
17056 /* TRUNC_W_S_MM */
17057 7844,
17058 /* TRUNC_W_S_MMR6 */
17059 7846,
17060 /* TTLTIU */
17061 7848,
17062 /* UDIV */
17063 7850,
17064 /* UDIV_MM */
17065 7852,
17066 /* V3MULU */
17067 7854,
17068 /* VMM0 */
17069 7857,
17070 /* VMULU */
17071 7860,
17072 /* VSHF_B */
17073 7863,
17074 /* VSHF_D */
17075 7867,
17076 /* VSHF_H */
17077 7871,
17078 /* VSHF_W */
17079 7875,
17080 /* WAIT */
17081 7879,
17082 /* WAIT_MM */
17083 7879,
17084 /* WAIT_MMR6 */
17085 7880,
17086 /* WRDSP */
17087 7881,
17088 /* WRDSP_MM */
17089 7883,
17090 /* WRPGPR_MMR6 */
17091 7885,
17092 /* WSBH */
17093 7887,
17094 /* WSBH_MM */
17095 7889,
17096 /* WSBH_MMR6 */
17097 7891,
17098 /* XOR */
17099 7893,
17100 /* XOR16_MM */
17101 7896,
17102 /* XOR16_MMR6 */
17103 7899,
17104 /* XOR64 */
17105 7902,
17106 /* XORI_B */
17107 7905,
17108 /* XORI_MMR6 */
17109 7908,
17110 /* XOR_MM */
17111 7911,
17112 /* XOR_MMR6 */
17113 7914,
17114 /* XOR_V */
17115 7917,
17116 /* XORi */
17117 7920,
17118 /* XORi64 */
17119 7923,
17120 /* XORi_MM */
17121 7926,
17122 /* XorRxRxRy16 */
17123 7929,
17124 /* YIELD */
17125 7932,
17126 };
17127
17128 using namespace OpTypes;
17129 static const int16_t OpcodeOperandTypes[] = {
17130
17131 /* PHI */
17132 -1,
17133 /* INLINEASM */
17134 /* INLINEASM_BR */
17135 /* CFI_INSTRUCTION */
17136 i32imm,
17137 /* EH_LABEL */
17138 i32imm,
17139 /* GC_LABEL */
17140 i32imm,
17141 /* ANNOTATION_LABEL */
17142 i32imm,
17143 /* KILL */
17144 /* EXTRACT_SUBREG */
17145 -1, -1, i32imm,
17146 /* INSERT_SUBREG */
17147 -1, -1, -1, i32imm,
17148 /* IMPLICIT_DEF */
17149 -1,
17150 /* SUBREG_TO_REG */
17151 -1, -1, -1, i32imm,
17152 /* COPY_TO_REGCLASS */
17153 -1, -1, i32imm,
17154 /* DBG_VALUE */
17155 /* DBG_VALUE_LIST */
17156 /* DBG_INSTR_REF */
17157 /* DBG_PHI */
17158 /* DBG_LABEL */
17159 -1,
17160 /* REG_SEQUENCE */
17161 -1, -1,
17162 /* COPY */
17163 -1, -1,
17164 /* BUNDLE */
17165 /* LIFETIME_START */
17166 i32imm,
17167 /* LIFETIME_END */
17168 i32imm,
17169 /* PSEUDO_PROBE */
17170 i64imm, i64imm, i8imm, i32imm,
17171 /* ARITH_FENCE */
17172 -1, -1,
17173 /* STACKMAP */
17174 i64imm, i32imm,
17175 /* FENTRY_CALL */
17176 /* PATCHPOINT */
17177 -1, i64imm, i32imm, -1, i32imm, i32imm,
17178 /* LOAD_STACK_GUARD */
17179 -1,
17180 /* PREALLOCATED_SETUP */
17181 i32imm,
17182 /* PREALLOCATED_ARG */
17183 -1, i32imm, i32imm,
17184 /* STATEPOINT */
17185 /* LOCAL_ESCAPE */
17186 -1, i32imm,
17187 /* FAULTING_OP */
17188 -1,
17189 /* PATCHABLE_OP */
17190 /* PATCHABLE_FUNCTION_ENTER */
17191 /* PATCHABLE_RET */
17192 /* PATCHABLE_FUNCTION_EXIT */
17193 /* PATCHABLE_TAIL_CALL */
17194 /* PATCHABLE_EVENT_CALL */
17195 -1, -1,
17196 /* PATCHABLE_TYPED_EVENT_CALL */
17197 -1, -1, -1,
17198 /* ICALL_BRANCH_FUNNEL */
17199 /* MEMBARRIER */
17200 /* JUMP_TABLE_DEBUG_INFO */
17201 i64imm,
17202 /* CONVERGENCECTRL_ENTRY */
17203 -1,
17204 /* CONVERGENCECTRL_ANCHOR */
17205 -1,
17206 /* CONVERGENCECTRL_LOOP */
17207 -1, -1,
17208 /* CONVERGENCECTRL_GLUE */
17209 -1,
17210 /* G_ASSERT_SEXT */
17211 type0, type0, untyped_imm_0,
17212 /* G_ASSERT_ZEXT */
17213 type0, type0, untyped_imm_0,
17214 /* G_ASSERT_ALIGN */
17215 type0, type0, untyped_imm_0,
17216 /* G_ADD */
17217 type0, type0, type0,
17218 /* G_SUB */
17219 type0, type0, type0,
17220 /* G_MUL */
17221 type0, type0, type0,
17222 /* G_SDIV */
17223 type0, type0, type0,
17224 /* G_UDIV */
17225 type0, type0, type0,
17226 /* G_SREM */
17227 type0, type0, type0,
17228 /* G_UREM */
17229 type0, type0, type0,
17230 /* G_SDIVREM */
17231 type0, type0, type0, type0,
17232 /* G_UDIVREM */
17233 type0, type0, type0, type0,
17234 /* G_AND */
17235 type0, type0, type0,
17236 /* G_OR */
17237 type0, type0, type0,
17238 /* G_XOR */
17239 type0, type0, type0,
17240 /* G_IMPLICIT_DEF */
17241 type0,
17242 /* G_PHI */
17243 type0,
17244 /* G_FRAME_INDEX */
17245 type0, -1,
17246 /* G_GLOBAL_VALUE */
17247 type0, -1,
17248 /* G_PTRAUTH_GLOBAL_VALUE */
17249 type0, -1, i32imm, type1, i64imm,
17250 /* G_CONSTANT_POOL */
17251 type0, -1,
17252 /* G_EXTRACT */
17253 type0, type1, untyped_imm_0,
17254 /* G_UNMERGE_VALUES */
17255 type0, type1,
17256 /* G_INSERT */
17257 type0, type0, type1, untyped_imm_0,
17258 /* G_MERGE_VALUES */
17259 type0, type1,
17260 /* G_BUILD_VECTOR */
17261 type0, type1,
17262 /* G_BUILD_VECTOR_TRUNC */
17263 type0, type1,
17264 /* G_CONCAT_VECTORS */
17265 type0, type1,
17266 /* G_PTRTOINT */
17267 type0, type1,
17268 /* G_INTTOPTR */
17269 type0, type1,
17270 /* G_BITCAST */
17271 type0, type1,
17272 /* G_FREEZE */
17273 type0, type0,
17274 /* G_CONSTANT_FOLD_BARRIER */
17275 type0, type0,
17276 /* G_INTRINSIC_FPTRUNC_ROUND */
17277 type0, type1, i32imm,
17278 /* G_INTRINSIC_TRUNC */
17279 type0, type0,
17280 /* G_INTRINSIC_ROUND */
17281 type0, type0,
17282 /* G_INTRINSIC_LRINT */
17283 type0, type1,
17284 /* G_INTRINSIC_LLRINT */
17285 type0, type1,
17286 /* G_INTRINSIC_ROUNDEVEN */
17287 type0, type0,
17288 /* G_READCYCLECOUNTER */
17289 type0,
17290 /* G_READSTEADYCOUNTER */
17291 type0,
17292 /* G_LOAD */
17293 type0, ptype1,
17294 /* G_SEXTLOAD */
17295 type0, ptype1,
17296 /* G_ZEXTLOAD */
17297 type0, ptype1,
17298 /* G_INDEXED_LOAD */
17299 type0, ptype1, ptype1, type2, -1,
17300 /* G_INDEXED_SEXTLOAD */
17301 type0, ptype1, ptype1, type2, -1,
17302 /* G_INDEXED_ZEXTLOAD */
17303 type0, ptype1, ptype1, type2, -1,
17304 /* G_STORE */
17305 type0, ptype1,
17306 /* G_INDEXED_STORE */
17307 ptype0, type1, ptype0, ptype2, -1,
17308 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
17309 type0, type1, type2, type0, type0,
17310 /* G_ATOMIC_CMPXCHG */
17311 type0, ptype1, type0, type0,
17312 /* G_ATOMICRMW_XCHG */
17313 type0, ptype1, type0,
17314 /* G_ATOMICRMW_ADD */
17315 type0, ptype1, type0,
17316 /* G_ATOMICRMW_SUB */
17317 type0, ptype1, type0,
17318 /* G_ATOMICRMW_AND */
17319 type0, ptype1, type0,
17320 /* G_ATOMICRMW_NAND */
17321 type0, ptype1, type0,
17322 /* G_ATOMICRMW_OR */
17323 type0, ptype1, type0,
17324 /* G_ATOMICRMW_XOR */
17325 type0, ptype1, type0,
17326 /* G_ATOMICRMW_MAX */
17327 type0, ptype1, type0,
17328 /* G_ATOMICRMW_MIN */
17329 type0, ptype1, type0,
17330 /* G_ATOMICRMW_UMAX */
17331 type0, ptype1, type0,
17332 /* G_ATOMICRMW_UMIN */
17333 type0, ptype1, type0,
17334 /* G_ATOMICRMW_FADD */
17335 type0, ptype1, type0,
17336 /* G_ATOMICRMW_FSUB */
17337 type0, ptype1, type0,
17338 /* G_ATOMICRMW_FMAX */
17339 type0, ptype1, type0,
17340 /* G_ATOMICRMW_FMIN */
17341 type0, ptype1, type0,
17342 /* G_ATOMICRMW_UINC_WRAP */
17343 type0, ptype1, type0,
17344 /* G_ATOMICRMW_UDEC_WRAP */
17345 type0, ptype1, type0,
17346 /* G_FENCE */
17347 i32imm, i32imm,
17348 /* G_PREFETCH */
17349 ptype0, i32imm, i32imm, i32imm,
17350 /* G_BRCOND */
17351 type0, -1,
17352 /* G_BRINDIRECT */
17353 type0,
17354 /* G_INVOKE_REGION_START */
17355 /* G_INTRINSIC */
17356 -1,
17357 /* G_INTRINSIC_W_SIDE_EFFECTS */
17358 -1,
17359 /* G_INTRINSIC_CONVERGENT */
17360 -1,
17361 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
17362 -1,
17363 /* G_ANYEXT */
17364 type0, type1,
17365 /* G_TRUNC */
17366 type0, type1,
17367 /* G_CONSTANT */
17368 type0, -1,
17369 /* G_FCONSTANT */
17370 type0, -1,
17371 /* G_VASTART */
17372 type0,
17373 /* G_VAARG */
17374 type0, type1, -1,
17375 /* G_SEXT */
17376 type0, type1,
17377 /* G_SEXT_INREG */
17378 type0, type0, untyped_imm_0,
17379 /* G_ZEXT */
17380 type0, type1,
17381 /* G_SHL */
17382 type0, type0, type1,
17383 /* G_LSHR */
17384 type0, type0, type1,
17385 /* G_ASHR */
17386 type0, type0, type1,
17387 /* G_FSHL */
17388 type0, type0, type0, type1,
17389 /* G_FSHR */
17390 type0, type0, type0, type1,
17391 /* G_ROTR */
17392 type0, type0, type1,
17393 /* G_ROTL */
17394 type0, type0, type1,
17395 /* G_ICMP */
17396 type0, -1, type1, type1,
17397 /* G_FCMP */
17398 type0, -1, type1, type1,
17399 /* G_SCMP */
17400 type0, type1, type1,
17401 /* G_UCMP */
17402 type0, type1, type1,
17403 /* G_SELECT */
17404 type0, type1, type0, type0,
17405 /* G_UADDO */
17406 type0, type1, type0, type0,
17407 /* G_UADDE */
17408 type0, type1, type0, type0, type1,
17409 /* G_USUBO */
17410 type0, type1, type0, type0,
17411 /* G_USUBE */
17412 type0, type1, type0, type0, type1,
17413 /* G_SADDO */
17414 type0, type1, type0, type0,
17415 /* G_SADDE */
17416 type0, type1, type0, type0, type1,
17417 /* G_SSUBO */
17418 type0, type1, type0, type0,
17419 /* G_SSUBE */
17420 type0, type1, type0, type0, type1,
17421 /* G_UMULO */
17422 type0, type1, type0, type0,
17423 /* G_SMULO */
17424 type0, type1, type0, type0,
17425 /* G_UMULH */
17426 type0, type0, type0,
17427 /* G_SMULH */
17428 type0, type0, type0,
17429 /* G_UADDSAT */
17430 type0, type0, type0,
17431 /* G_SADDSAT */
17432 type0, type0, type0,
17433 /* G_USUBSAT */
17434 type0, type0, type0,
17435 /* G_SSUBSAT */
17436 type0, type0, type0,
17437 /* G_USHLSAT */
17438 type0, type0, type1,
17439 /* G_SSHLSAT */
17440 type0, type0, type1,
17441 /* G_SMULFIX */
17442 type0, type0, type0, untyped_imm_0,
17443 /* G_UMULFIX */
17444 type0, type0, type0, untyped_imm_0,
17445 /* G_SMULFIXSAT */
17446 type0, type0, type0, untyped_imm_0,
17447 /* G_UMULFIXSAT */
17448 type0, type0, type0, untyped_imm_0,
17449 /* G_SDIVFIX */
17450 type0, type0, type0, untyped_imm_0,
17451 /* G_UDIVFIX */
17452 type0, type0, type0, untyped_imm_0,
17453 /* G_SDIVFIXSAT */
17454 type0, type0, type0, untyped_imm_0,
17455 /* G_UDIVFIXSAT */
17456 type0, type0, type0, untyped_imm_0,
17457 /* G_FADD */
17458 type0, type0, type0,
17459 /* G_FSUB */
17460 type0, type0, type0,
17461 /* G_FMUL */
17462 type0, type0, type0,
17463 /* G_FMA */
17464 type0, type0, type0, type0,
17465 /* G_FMAD */
17466 type0, type0, type0, type0,
17467 /* G_FDIV */
17468 type0, type0, type0,
17469 /* G_FREM */
17470 type0, type0, type0,
17471 /* G_FPOW */
17472 type0, type0, type0,
17473 /* G_FPOWI */
17474 type0, type0, type1,
17475 /* G_FEXP */
17476 type0, type0,
17477 /* G_FEXP2 */
17478 type0, type0,
17479 /* G_FEXP10 */
17480 type0, type0,
17481 /* G_FLOG */
17482 type0, type0,
17483 /* G_FLOG2 */
17484 type0, type0,
17485 /* G_FLOG10 */
17486 type0, type0,
17487 /* G_FLDEXP */
17488 type0, type0, type1,
17489 /* G_FFREXP */
17490 type0, type1, type0,
17491 /* G_FNEG */
17492 type0, type0,
17493 /* G_FPEXT */
17494 type0, type1,
17495 /* G_FPTRUNC */
17496 type0, type1,
17497 /* G_FPTOSI */
17498 type0, type1,
17499 /* G_FPTOUI */
17500 type0, type1,
17501 /* G_SITOFP */
17502 type0, type1,
17503 /* G_UITOFP */
17504 type0, type1,
17505 /* G_FABS */
17506 type0, type0,
17507 /* G_FCOPYSIGN */
17508 type0, type0, type1,
17509 /* G_IS_FPCLASS */
17510 type0, type1, -1,
17511 /* G_FCANONICALIZE */
17512 type0, type0,
17513 /* G_FMINNUM */
17514 type0, type0, type0,
17515 /* G_FMAXNUM */
17516 type0, type0, type0,
17517 /* G_FMINNUM_IEEE */
17518 type0, type0, type0,
17519 /* G_FMAXNUM_IEEE */
17520 type0, type0, type0,
17521 /* G_FMINIMUM */
17522 type0, type0, type0,
17523 /* G_FMAXIMUM */
17524 type0, type0, type0,
17525 /* G_GET_FPENV */
17526 type0,
17527 /* G_SET_FPENV */
17528 type0,
17529 /* G_RESET_FPENV */
17530 /* G_GET_FPMODE */
17531 type0,
17532 /* G_SET_FPMODE */
17533 type0,
17534 /* G_RESET_FPMODE */
17535 /* G_PTR_ADD */
17536 ptype0, ptype0, type1,
17537 /* G_PTRMASK */
17538 ptype0, ptype0, type1,
17539 /* G_SMIN */
17540 type0, type0, type0,
17541 /* G_SMAX */
17542 type0, type0, type0,
17543 /* G_UMIN */
17544 type0, type0, type0,
17545 /* G_UMAX */
17546 type0, type0, type0,
17547 /* G_ABS */
17548 type0, type0,
17549 /* G_LROUND */
17550 type0, type1,
17551 /* G_LLROUND */
17552 type0, type1,
17553 /* G_BR */
17554 -1,
17555 /* G_BRJT */
17556 ptype0, -1, type1,
17557 /* G_VSCALE */
17558 type0, -1,
17559 /* G_INSERT_SUBVECTOR */
17560 type0, type0, type1, untyped_imm_0,
17561 /* G_EXTRACT_SUBVECTOR */
17562 type0, type0, untyped_imm_0,
17563 /* G_INSERT_VECTOR_ELT */
17564 type0, type0, type1, type2,
17565 /* G_EXTRACT_VECTOR_ELT */
17566 type0, type1, type2,
17567 /* G_SHUFFLE_VECTOR */
17568 type0, type1, type1, -1,
17569 /* G_SPLAT_VECTOR */
17570 type0, type1,
17571 /* G_VECTOR_COMPRESS */
17572 type0, type0, type1, type0,
17573 /* G_CTTZ */
17574 type0, type1,
17575 /* G_CTTZ_ZERO_UNDEF */
17576 type0, type1,
17577 /* G_CTLZ */
17578 type0, type1,
17579 /* G_CTLZ_ZERO_UNDEF */
17580 type0, type1,
17581 /* G_CTPOP */
17582 type0, type1,
17583 /* G_BSWAP */
17584 type0, type0,
17585 /* G_BITREVERSE */
17586 type0, type0,
17587 /* G_FCEIL */
17588 type0, type0,
17589 /* G_FCOS */
17590 type0, type0,
17591 /* G_FSIN */
17592 type0, type0,
17593 /* G_FTAN */
17594 type0, type0,
17595 /* G_FACOS */
17596 type0, type0,
17597 /* G_FASIN */
17598 type0, type0,
17599 /* G_FATAN */
17600 type0, type0,
17601 /* G_FCOSH */
17602 type0, type0,
17603 /* G_FSINH */
17604 type0, type0,
17605 /* G_FTANH */
17606 type0, type0,
17607 /* G_FSQRT */
17608 type0, type0,
17609 /* G_FFLOOR */
17610 type0, type0,
17611 /* G_FRINT */
17612 type0, type0,
17613 /* G_FNEARBYINT */
17614 type0, type0,
17615 /* G_ADDRSPACE_CAST */
17616 type0, type1,
17617 /* G_BLOCK_ADDR */
17618 type0, -1,
17619 /* G_JUMP_TABLE */
17620 type0, -1,
17621 /* G_DYN_STACKALLOC */
17622 ptype0, type1, i32imm,
17623 /* G_STACKSAVE */
17624 ptype0,
17625 /* G_STACKRESTORE */
17626 ptype0,
17627 /* G_STRICT_FADD */
17628 type0, type0, type0,
17629 /* G_STRICT_FSUB */
17630 type0, type0, type0,
17631 /* G_STRICT_FMUL */
17632 type0, type0, type0,
17633 /* G_STRICT_FDIV */
17634 type0, type0, type0,
17635 /* G_STRICT_FREM */
17636 type0, type0, type0,
17637 /* G_STRICT_FMA */
17638 type0, type0, type0, type0,
17639 /* G_STRICT_FSQRT */
17640 type0, type0,
17641 /* G_STRICT_FLDEXP */
17642 type0, type0, type1,
17643 /* G_READ_REGISTER */
17644 type0, -1,
17645 /* G_WRITE_REGISTER */
17646 -1, type0,
17647 /* G_MEMCPY */
17648 ptype0, ptype1, type2, untyped_imm_0,
17649 /* G_MEMCPY_INLINE */
17650 ptype0, ptype1, type2,
17651 /* G_MEMMOVE */
17652 ptype0, ptype1, type2, untyped_imm_0,
17653 /* G_MEMSET */
17654 ptype0, type1, type2, untyped_imm_0,
17655 /* G_BZERO */
17656 ptype0, type1, untyped_imm_0,
17657 /* G_TRAP */
17658 /* G_DEBUGTRAP */
17659 /* G_UBSANTRAP */
17660 i8imm,
17661 /* G_VECREDUCE_SEQ_FADD */
17662 type0, type1, type2,
17663 /* G_VECREDUCE_SEQ_FMUL */
17664 type0, type1, type2,
17665 /* G_VECREDUCE_FADD */
17666 type0, type1,
17667 /* G_VECREDUCE_FMUL */
17668 type0, type1,
17669 /* G_VECREDUCE_FMAX */
17670 type0, type1,
17671 /* G_VECREDUCE_FMIN */
17672 type0, type1,
17673 /* G_VECREDUCE_FMAXIMUM */
17674 type0, type1,
17675 /* G_VECREDUCE_FMINIMUM */
17676 type0, type1,
17677 /* G_VECREDUCE_ADD */
17678 type0, type1,
17679 /* G_VECREDUCE_MUL */
17680 type0, type1,
17681 /* G_VECREDUCE_AND */
17682 type0, type1,
17683 /* G_VECREDUCE_OR */
17684 type0, type1,
17685 /* G_VECREDUCE_XOR */
17686 type0, type1,
17687 /* G_VECREDUCE_SMAX */
17688 type0, type1,
17689 /* G_VECREDUCE_SMIN */
17690 type0, type1,
17691 /* G_VECREDUCE_UMAX */
17692 type0, type1,
17693 /* G_VECREDUCE_UMIN */
17694 type0, type1,
17695 /* G_SBFX */
17696 type0, type0, type1, type1,
17697 /* G_UBFX */
17698 type0, type0, type1, type1,
17699 /* ABSMacro */
17700 GPR32Opnd, GPR32Opnd,
17701 /* ADJCALLSTACKDOWN */
17702 i32imm, i32imm,
17703 /* ADJCALLSTACKUP */
17704 i32imm, i32imm,
17705 /* AND_V_D_PSEUDO */
17706 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17707 /* AND_V_H_PSEUDO */
17708 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
17709 /* AND_V_W_PSEUDO */
17710 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17711 /* ATOMIC_CMP_SWAP_I16 */
17712 GPR32, -1, GPR32, GPR32,
17713 /* ATOMIC_CMP_SWAP_I16_POSTRA */
17714 GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,
17715 /* ATOMIC_CMP_SWAP_I32 */
17716 GPR32, -1, GPR32, GPR32,
17717 /* ATOMIC_CMP_SWAP_I32_POSTRA */
17718 GPR32, -1, GPR32, GPR32,
17719 /* ATOMIC_CMP_SWAP_I64 */
17720 GPR64, -1, GPR64, GPR64,
17721 /* ATOMIC_CMP_SWAP_I64_POSTRA */
17722 GPR64, -1, GPR64, GPR64,
17723 /* ATOMIC_CMP_SWAP_I8 */
17724 GPR32, -1, GPR32, GPR32,
17725 /* ATOMIC_CMP_SWAP_I8_POSTRA */
17726 GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32,
17727 /* ATOMIC_LOAD_ADD_I16 */
17728 GPR32, -1, GPR32,
17729 /* ATOMIC_LOAD_ADD_I16_POSTRA */
17730 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17731 /* ATOMIC_LOAD_ADD_I32 */
17732 GPR32, -1, GPR32,
17733 /* ATOMIC_LOAD_ADD_I32_POSTRA */
17734 GPR32, -1, GPR32,
17735 /* ATOMIC_LOAD_ADD_I64 */
17736 GPR64, -1, GPR64,
17737 /* ATOMIC_LOAD_ADD_I64_POSTRA */
17738 GPR64, -1, GPR64,
17739 /* ATOMIC_LOAD_ADD_I8 */
17740 GPR32, -1, GPR32,
17741 /* ATOMIC_LOAD_ADD_I8_POSTRA */
17742 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17743 /* ATOMIC_LOAD_AND_I16 */
17744 GPR32, -1, GPR32,
17745 /* ATOMIC_LOAD_AND_I16_POSTRA */
17746 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17747 /* ATOMIC_LOAD_AND_I32 */
17748 GPR32, -1, GPR32,
17749 /* ATOMIC_LOAD_AND_I32_POSTRA */
17750 GPR32, -1, GPR32,
17751 /* ATOMIC_LOAD_AND_I64 */
17752 GPR64, -1, GPR64,
17753 /* ATOMIC_LOAD_AND_I64_POSTRA */
17754 GPR64, -1, GPR64,
17755 /* ATOMIC_LOAD_AND_I8 */
17756 GPR32, -1, GPR32,
17757 /* ATOMIC_LOAD_AND_I8_POSTRA */
17758 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17759 /* ATOMIC_LOAD_MAX_I16 */
17760 GPR32, -1, GPR32,
17761 /* ATOMIC_LOAD_MAX_I16_POSTRA */
17762 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17763 /* ATOMIC_LOAD_MAX_I32 */
17764 GPR32, -1, GPR32,
17765 /* ATOMIC_LOAD_MAX_I32_POSTRA */
17766 GPR32, -1, GPR32,
17767 /* ATOMIC_LOAD_MAX_I64 */
17768 GPR64, -1, GPR64,
17769 /* ATOMIC_LOAD_MAX_I64_POSTRA */
17770 GPR64, -1, GPR64,
17771 /* ATOMIC_LOAD_MAX_I8 */
17772 GPR32, -1, GPR32,
17773 /* ATOMIC_LOAD_MAX_I8_POSTRA */
17774 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17775 /* ATOMIC_LOAD_MIN_I16 */
17776 GPR32, -1, GPR32,
17777 /* ATOMIC_LOAD_MIN_I16_POSTRA */
17778 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17779 /* ATOMIC_LOAD_MIN_I32 */
17780 GPR32, -1, GPR32,
17781 /* ATOMIC_LOAD_MIN_I32_POSTRA */
17782 GPR32, -1, GPR32,
17783 /* ATOMIC_LOAD_MIN_I64 */
17784 GPR64, -1, GPR64,
17785 /* ATOMIC_LOAD_MIN_I64_POSTRA */
17786 GPR64, -1, GPR64,
17787 /* ATOMIC_LOAD_MIN_I8 */
17788 GPR32, -1, GPR32,
17789 /* ATOMIC_LOAD_MIN_I8_POSTRA */
17790 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17791 /* ATOMIC_LOAD_NAND_I16 */
17792 GPR32, -1, GPR32,
17793 /* ATOMIC_LOAD_NAND_I16_POSTRA */
17794 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17795 /* ATOMIC_LOAD_NAND_I32 */
17796 GPR32, -1, GPR32,
17797 /* ATOMIC_LOAD_NAND_I32_POSTRA */
17798 GPR32, -1, GPR32,
17799 /* ATOMIC_LOAD_NAND_I64 */
17800 GPR64, -1, GPR64,
17801 /* ATOMIC_LOAD_NAND_I64_POSTRA */
17802 GPR64, -1, GPR64,
17803 /* ATOMIC_LOAD_NAND_I8 */
17804 GPR32, -1, GPR32,
17805 /* ATOMIC_LOAD_NAND_I8_POSTRA */
17806 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17807 /* ATOMIC_LOAD_OR_I16 */
17808 GPR32, -1, GPR32,
17809 /* ATOMIC_LOAD_OR_I16_POSTRA */
17810 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17811 /* ATOMIC_LOAD_OR_I32 */
17812 GPR32, -1, GPR32,
17813 /* ATOMIC_LOAD_OR_I32_POSTRA */
17814 GPR32, -1, GPR32,
17815 /* ATOMIC_LOAD_OR_I64 */
17816 GPR64, -1, GPR64,
17817 /* ATOMIC_LOAD_OR_I64_POSTRA */
17818 GPR64, -1, GPR64,
17819 /* ATOMIC_LOAD_OR_I8 */
17820 GPR32, -1, GPR32,
17821 /* ATOMIC_LOAD_OR_I8_POSTRA */
17822 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17823 /* ATOMIC_LOAD_SUB_I16 */
17824 GPR32, -1, GPR32,
17825 /* ATOMIC_LOAD_SUB_I16_POSTRA */
17826 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17827 /* ATOMIC_LOAD_SUB_I32 */
17828 GPR32, -1, GPR32,
17829 /* ATOMIC_LOAD_SUB_I32_POSTRA */
17830 GPR32, -1, GPR32,
17831 /* ATOMIC_LOAD_SUB_I64 */
17832 GPR64, -1, GPR64,
17833 /* ATOMIC_LOAD_SUB_I64_POSTRA */
17834 GPR64, -1, GPR64,
17835 /* ATOMIC_LOAD_SUB_I8 */
17836 GPR32, -1, GPR32,
17837 /* ATOMIC_LOAD_SUB_I8_POSTRA */
17838 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17839 /* ATOMIC_LOAD_UMAX_I16 */
17840 GPR32, -1, GPR32,
17841 /* ATOMIC_LOAD_UMAX_I16_POSTRA */
17842 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17843 /* ATOMIC_LOAD_UMAX_I32 */
17844 GPR32, -1, GPR32,
17845 /* ATOMIC_LOAD_UMAX_I32_POSTRA */
17846 GPR32, -1, GPR32,
17847 /* ATOMIC_LOAD_UMAX_I64 */
17848 GPR64, -1, GPR64,
17849 /* ATOMIC_LOAD_UMAX_I64_POSTRA */
17850 GPR64, -1, GPR64,
17851 /* ATOMIC_LOAD_UMAX_I8 */
17852 GPR32, -1, GPR32,
17853 /* ATOMIC_LOAD_UMAX_I8_POSTRA */
17854 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17855 /* ATOMIC_LOAD_UMIN_I16 */
17856 GPR32, -1, GPR32,
17857 /* ATOMIC_LOAD_UMIN_I16_POSTRA */
17858 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17859 /* ATOMIC_LOAD_UMIN_I32 */
17860 GPR32, -1, GPR32,
17861 /* ATOMIC_LOAD_UMIN_I32_POSTRA */
17862 GPR32, -1, GPR32,
17863 /* ATOMIC_LOAD_UMIN_I64 */
17864 GPR64, -1, GPR64,
17865 /* ATOMIC_LOAD_UMIN_I64_POSTRA */
17866 GPR64, -1, GPR64,
17867 /* ATOMIC_LOAD_UMIN_I8 */
17868 GPR32, -1, GPR32,
17869 /* ATOMIC_LOAD_UMIN_I8_POSTRA */
17870 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17871 /* ATOMIC_LOAD_XOR_I16 */
17872 GPR32, -1, GPR32,
17873 /* ATOMIC_LOAD_XOR_I16_POSTRA */
17874 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17875 /* ATOMIC_LOAD_XOR_I32 */
17876 GPR32, -1, GPR32,
17877 /* ATOMIC_LOAD_XOR_I32_POSTRA */
17878 GPR32, -1, GPR32,
17879 /* ATOMIC_LOAD_XOR_I64 */
17880 GPR64, -1, GPR64,
17881 /* ATOMIC_LOAD_XOR_I64_POSTRA */
17882 GPR64, -1, GPR64,
17883 /* ATOMIC_LOAD_XOR_I8 */
17884 GPR32, -1, GPR32,
17885 /* ATOMIC_LOAD_XOR_I8_POSTRA */
17886 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17887 /* ATOMIC_SWAP_I16 */
17888 GPR32, -1, GPR32,
17889 /* ATOMIC_SWAP_I16_POSTRA */
17890 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17891 /* ATOMIC_SWAP_I32 */
17892 GPR32, -1, GPR32,
17893 /* ATOMIC_SWAP_I32_POSTRA */
17894 GPR32, -1, GPR32,
17895 /* ATOMIC_SWAP_I64 */
17896 GPR64, -1, GPR64,
17897 /* ATOMIC_SWAP_I64_POSTRA */
17898 GPR64, -1, GPR64,
17899 /* ATOMIC_SWAP_I8 */
17900 GPR32, -1, GPR32,
17901 /* ATOMIC_SWAP_I8_POSTRA */
17902 GPR32, -1, GPR32, GPR32, GPR32, GPR32,
17903 /* B */
17904 brtarget,
17905 /* BAL_BR */
17906 brtarget,
17907 /* BAL_BR_MM */
17908 brtarget_mm,
17909 /* BEQLImmMacro */
17910 GPR32Opnd, imm64, brtarget,
17911 /* BGE */
17912 GPR32Opnd, GPR32Opnd, brtarget,
17913 /* BGEImmMacro */
17914 GPR32Opnd, imm64, brtarget,
17915 /* BGEL */
17916 GPR32Opnd, GPR32Opnd, brtarget,
17917 /* BGELImmMacro */
17918 GPR32Opnd, imm64, brtarget,
17919 /* BGEU */
17920 GPR32Opnd, GPR32Opnd, brtarget,
17921 /* BGEUImmMacro */
17922 GPR32Opnd, imm64, brtarget,
17923 /* BGEUL */
17924 GPR32Opnd, GPR32Opnd, brtarget,
17925 /* BGEULImmMacro */
17926 GPR32Opnd, imm64, brtarget,
17927 /* BGT */
17928 GPR32Opnd, GPR32Opnd, brtarget,
17929 /* BGTImmMacro */
17930 GPR32Opnd, imm64, brtarget,
17931 /* BGTL */
17932 GPR32Opnd, GPR32Opnd, brtarget,
17933 /* BGTLImmMacro */
17934 GPR32Opnd, imm64, brtarget,
17935 /* BGTU */
17936 GPR32Opnd, GPR32Opnd, brtarget,
17937 /* BGTUImmMacro */
17938 GPR32Opnd, imm64, brtarget,
17939 /* BGTUL */
17940 GPR32Opnd, GPR32Opnd, brtarget,
17941 /* BGTULImmMacro */
17942 GPR32Opnd, imm64, brtarget,
17943 /* BLE */
17944 GPR32Opnd, GPR32Opnd, brtarget,
17945 /* BLEImmMacro */
17946 GPR32Opnd, imm64, brtarget,
17947 /* BLEL */
17948 GPR32Opnd, GPR32Opnd, brtarget,
17949 /* BLELImmMacro */
17950 GPR32Opnd, imm64, brtarget,
17951 /* BLEU */
17952 GPR32Opnd, GPR32Opnd, brtarget,
17953 /* BLEUImmMacro */
17954 GPR32Opnd, imm64, brtarget,
17955 /* BLEUL */
17956 GPR32Opnd, GPR32Opnd, brtarget,
17957 /* BLEULImmMacro */
17958 GPR32Opnd, imm64, brtarget,
17959 /* BLT */
17960 GPR32Opnd, GPR32Opnd, brtarget,
17961 /* BLTImmMacro */
17962 GPR32Opnd, imm64, brtarget,
17963 /* BLTL */
17964 GPR32Opnd, GPR32Opnd, brtarget,
17965 /* BLTLImmMacro */
17966 GPR32Opnd, imm64, brtarget,
17967 /* BLTU */
17968 GPR32Opnd, GPR32Opnd, brtarget,
17969 /* BLTUImmMacro */
17970 GPR32Opnd, imm64, brtarget,
17971 /* BLTUL */
17972 GPR32Opnd, GPR32Opnd, brtarget,
17973 /* BLTULImmMacro */
17974 GPR32Opnd, imm64, brtarget,
17975 /* BNELImmMacro */
17976 GPR32Opnd, imm64, brtarget,
17977 /* BPOSGE32_PSEUDO */
17978 GPR32Opnd,
17979 /* BSEL_D_PSEUDO */
17980 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17981 /* BSEL_FD_PSEUDO */
17982 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
17983 /* BSEL_FW_PSEUDO */
17984 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17985 /* BSEL_H_PSEUDO */
17986 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
17987 /* BSEL_W_PSEUDO */
17988 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
17989 /* B_MM */
17990 brtarget,
17991 /* B_MMR6_Pseudo */
17992 brtarget_mm,
17993 /* B_MM_Pseudo */
17994 brtarget_mm,
17995 /* BeqImm */
17996 GPR32Opnd, imm64, brtarget,
17997 /* BneImm */
17998 GPR32Opnd, imm64, brtarget,
17999 /* BteqzT8CmpX16 */
18000 CPU16Regs, CPU16Regs, brtarget,
18001 /* BteqzT8CmpiX16 */
18002 CPU16Regs, simm16, brtarget,
18003 /* BteqzT8SltX16 */
18004 CPU16Regs, CPU16Regs, brtarget,
18005 /* BteqzT8SltiX16 */
18006 CPU16Regs, simm16, brtarget,
18007 /* BteqzT8SltiuX16 */
18008 CPU16Regs, simm16, brtarget,
18009 /* BteqzT8SltuX16 */
18010 CPU16Regs, CPU16Regs, brtarget,
18011 /* BtnezT8CmpX16 */
18012 CPU16Regs, CPU16Regs, brtarget,
18013 /* BtnezT8CmpiX16 */
18014 CPU16Regs, simm16, brtarget,
18015 /* BtnezT8SltX16 */
18016 CPU16Regs, CPU16Regs, brtarget,
18017 /* BtnezT8SltiX16 */
18018 CPU16Regs, simm16, brtarget,
18019 /* BtnezT8SltiuX16 */
18020 CPU16Regs, simm16, brtarget,
18021 /* BtnezT8SltuX16 */
18022 CPU16Regs, CPU16Regs, brtarget,
18023 /* BuildPairF64 */
18024 AFGR64Opnd, GPR32Opnd, GPR32Opnd,
18025 /* BuildPairF64_64 */
18026 FGR64Opnd, GPR32Opnd, GPR32Opnd,
18027 /* CFTC1 */
18028 GPR32Opnd, FGRCCOpnd,
18029 /* CONSTPOOL_ENTRY */
18030 cpinst_operand, cpinst_operand, i32imm,
18031 /* COPY_FD_PSEUDO */
18032 FGR64, MSA128D, uimm1_ptr,
18033 /* COPY_FW_PSEUDO */
18034 FGR32, MSA128W, uimm2_ptr,
18035 /* CTTC1 */
18036 FGRCCOpnd, GPR32Opnd,
18037 /* Constant32 */
18038 simm32,
18039 /* DMULImmMacro */
18040 GPR64Opnd, GPR64Opnd, simm32_relaxed,
18041 /* DMULMacro */
18042 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18043 /* DMULOMacro */
18044 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18045 /* DMULOUMacro */
18046 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18047 /* DROL */
18048 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18049 /* DROLImm */
18050 GPR32Opnd, GPR32Opnd, simm16,
18051 /* DROR */
18052 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18053 /* DRORImm */
18054 GPR32Opnd, GPR32Opnd, simm16,
18055 /* DSDivIMacro */
18056 GPR64Opnd, GPR64Opnd, imm64,
18057 /* DSDivMacro */
18058 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18059 /* DSRemIMacro */
18060 GPR64Opnd, GPR64Opnd, simm32_relaxed,
18061 /* DSRemMacro */
18062 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18063 /* DUDivIMacro */
18064 GPR64Opnd, GPR64Opnd, imm64,
18065 /* DUDivMacro */
18066 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18067 /* DURemIMacro */
18068 GPR64Opnd, GPR64Opnd, simm32_relaxed,
18069 /* DURemMacro */
18070 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18071 /* ERet */
18072 /* ExtractElementF64 */
18073 GPR32Opnd, AFGR64Opnd, i32imm,
18074 /* ExtractElementF64_64 */
18075 GPR32Opnd, FGR64Opnd, i32imm,
18076 /* FABS_D */
18077 MSA128DOpnd, MSA128DOpnd,
18078 /* FABS_W */
18079 MSA128WOpnd, MSA128WOpnd,
18080 /* FEXP2_D_1_PSEUDO */
18081 MSA128D, MSA128D,
18082 /* FEXP2_W_1_PSEUDO */
18083 MSA128W, MSA128W,
18084 /* FILL_FD_PSEUDO */
18085 MSA128D, FGR64,
18086 /* FILL_FW_PSEUDO */
18087 MSA128W, FGR32,
18088 /* GotPrologue16 */
18089 CPU16Regs, CPU16Regs, simm16, simm16,
18090 /* INSERT_B_VIDX64_PSEUDO */
18091 MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd,
18092 /* INSERT_B_VIDX_PSEUDO */
18093 MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd,
18094 /* INSERT_D_VIDX64_PSEUDO */
18095 MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd,
18096 /* INSERT_D_VIDX_PSEUDO */
18097 MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd,
18098 /* INSERT_FD_PSEUDO */
18099 MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd,
18100 /* INSERT_FD_VIDX64_PSEUDO */
18101 MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd,
18102 /* INSERT_FD_VIDX_PSEUDO */
18103 MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd,
18104 /* INSERT_FW_PSEUDO */
18105 MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd,
18106 /* INSERT_FW_VIDX64_PSEUDO */
18107 MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd,
18108 /* INSERT_FW_VIDX_PSEUDO */
18109 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd,
18110 /* INSERT_H_VIDX64_PSEUDO */
18111 MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd,
18112 /* INSERT_H_VIDX_PSEUDO */
18113 MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd,
18114 /* INSERT_W_VIDX64_PSEUDO */
18115 MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd,
18116 /* INSERT_W_VIDX_PSEUDO */
18117 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd,
18118 /* JALR64Pseudo */
18119 GPR64Opnd,
18120 /* JALRHB64Pseudo */
18121 GPR64Opnd,
18122 /* JALRHBPseudo */
18123 GPR32Opnd,
18124 /* JALRPseudo */
18125 GPR32Opnd,
18126 /* JAL_MMR6 */
18127 calltarget,
18128 /* JalOneReg */
18129 GPR32Opnd,
18130 /* JalTwoReg */
18131 GPR32Opnd, GPR32Opnd,
18132 /* LDMacro */
18133 GPR32Opnd, -1, simm16,
18134 /* LDR_D */
18135 MSA128DOpnd, -1, GPR32,
18136 /* LDR_W */
18137 MSA128WOpnd, -1, GPR32,
18138 /* LD_F16 */
18139 MSA128F16, -1, simm10,
18140 /* LOAD_ACC128 */
18141 ACC128, -1, simm16,
18142 /* LOAD_ACC64 */
18143 ACC64, -1, simm16,
18144 /* LOAD_ACC64DSP */
18145 ACC64DSPOpnd, -1, simm16,
18146 /* LOAD_CCOND_DSP */
18147 DSPCC, -1, simm16,
18148 /* LONG_BRANCH_ADDiu */
18149 GPR32Opnd, GPR32Opnd, brtarget, brtarget,
18150 /* LONG_BRANCH_ADDiu2Op */
18151 GPR32Opnd, GPR32Opnd, brtarget,
18152 /* LONG_BRANCH_DADDiu */
18153 GPR64Opnd, GPR64Opnd, brtarget, brtarget,
18154 /* LONG_BRANCH_DADDiu2Op */
18155 GPR64Opnd, GPR64Opnd, brtarget,
18156 /* LONG_BRANCH_LUi */
18157 GPR32Opnd, brtarget, brtarget,
18158 /* LONG_BRANCH_LUi2Op */
18159 GPR32Opnd, brtarget,
18160 /* LONG_BRANCH_LUi2Op_64 */
18161 GPR64Opnd, brtarget,
18162 /* LWM_MM */
18163 reglist, -1, simm12,
18164 /* LoadAddrImm32 */
18165 GPR32Opnd, i32imm,
18166 /* LoadAddrImm64 */
18167 GPR64Opnd, imm64,
18168 /* LoadAddrReg32 */
18169 GPR32Opnd, -1, simm16,
18170 /* LoadAddrReg64 */
18171 GPR64Opnd, -1, simm16,
18172 /* LoadImm32 */
18173 GPR32Opnd, uimm32_coerced,
18174 /* LoadImm64 */
18175 GPR64Opnd, imm64,
18176 /* LoadImmDoubleFGR */
18177 StrictlyFGR64Opnd, imm64,
18178 /* LoadImmDoubleFGR_32 */
18179 StrictlyAFGR64Opnd, imm64,
18180 /* LoadImmDoubleGPR */
18181 GPR32Opnd, imm64,
18182 /* LoadImmSingleFGR */
18183 StrictlyFGR32Opnd, imm64,
18184 /* LoadImmSingleGPR */
18185 GPR32Opnd, imm64,
18186 /* LwConstant32 */
18187 CPU16Regs, simm32, simm32,
18188 /* MFTACX */
18189 GPR32Opnd, ACC64DSPOpnd,
18190 /* MFTC0 */
18191 GPR32Opnd, COP0Opnd, uimm3,
18192 /* MFTC1 */
18193 GPR32Opnd, FGR32Opnd,
18194 /* MFTDSP */
18195 GPR32Opnd,
18196 /* MFTGPR */
18197 GPR32Opnd, GPR32Opnd, uimm3,
18198 /* MFTHC1 */
18199 GPR32Opnd, FGR32Opnd,
18200 /* MFTHI */
18201 GPR32Opnd, ACC64DSPOpnd,
18202 /* MFTLO */
18203 GPR32Opnd, ACC64DSPOpnd,
18204 /* MIPSeh_return32 */
18205 GPR32, GPR32,
18206 /* MIPSeh_return64 */
18207 GPR64, GPR64,
18208 /* MSA_FP_EXTEND_D_PSEUDO */
18209 FGR64Opnd, MSA128F16,
18210 /* MSA_FP_EXTEND_W_PSEUDO */
18211 FGR32Opnd, MSA128F16,
18212 /* MSA_FP_ROUND_D_PSEUDO */
18213 MSA128F16, FGR64Opnd,
18214 /* MSA_FP_ROUND_W_PSEUDO */
18215 MSA128F16, FGR32Opnd,
18216 /* MTTACX */
18217 ACC64DSPOpnd, GPR32Opnd,
18218 /* MTTC0 */
18219 COP0Opnd, GPR32Opnd, uimm3,
18220 /* MTTC1 */
18221 FGR32Opnd, GPR32Opnd,
18222 /* MTTDSP */
18223 GPR32Opnd,
18224 /* MTTGPR */
18225 GPR32Opnd, GPR32Opnd,
18226 /* MTTHC1 */
18227 FGR32Opnd, GPR32Opnd,
18228 /* MTTHI */
18229 ACC64DSPOpnd, GPR32Opnd,
18230 /* MTTLO */
18231 ACC64DSPOpnd, GPR32Opnd,
18232 /* MULImmMacro */
18233 GPR32Opnd, GPR32Opnd, simm32_relaxed,
18234 /* MULOMacro */
18235 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18236 /* MULOUMacro */
18237 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18238 /* MultRxRy16 */
18239 CPU16Regs, CPU16Regs,
18240 /* MultRxRyRz16 */
18241 CPU16Regs, CPU16Regs, CPU16Regs,
18242 /* MultuRxRy16 */
18243 CPU16Regs, CPU16Regs,
18244 /* MultuRxRyRz16 */
18245 CPU16Regs, CPU16Regs, CPU16Regs,
18246 /* NOP */
18247 /* NORImm */
18248 GPR32Opnd, GPR32Opnd, simm32_relaxed,
18249 /* NORImm64 */
18250 GPR64Opnd, GPR64Opnd, imm64,
18251 /* NOR_V_D_PSEUDO */
18252 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18253 /* NOR_V_H_PSEUDO */
18254 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18255 /* NOR_V_W_PSEUDO */
18256 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18257 /* OR_V_D_PSEUDO */
18258 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18259 /* OR_V_H_PSEUDO */
18260 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18261 /* OR_V_W_PSEUDO */
18262 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18263 /* PseudoCMPU_EQ_QB */
18264 DSPCC, DSPROpnd, DSPROpnd,
18265 /* PseudoCMPU_LE_QB */
18266 DSPCC, DSPROpnd, DSPROpnd,
18267 /* PseudoCMPU_LT_QB */
18268 DSPCC, DSPROpnd, DSPROpnd,
18269 /* PseudoCMP_EQ_PH */
18270 DSPCC, DSPROpnd, DSPROpnd,
18271 /* PseudoCMP_LE_PH */
18272 DSPCC, DSPROpnd, DSPROpnd,
18273 /* PseudoCMP_LT_PH */
18274 DSPCC, DSPROpnd, DSPROpnd,
18275 /* PseudoCVT_D32_W */
18276 AFGR64Opnd, GPR32Opnd,
18277 /* PseudoCVT_D64_L */
18278 FGR64Opnd, GPR64Opnd,
18279 /* PseudoCVT_D64_W */
18280 FGR64Opnd, GPR32Opnd,
18281 /* PseudoCVT_S_L */
18282 FGR64Opnd, GPR64Opnd,
18283 /* PseudoCVT_S_W */
18284 FGR32Opnd, GPR32Opnd,
18285 /* PseudoDMULT */
18286 ACC128, GPR64Opnd, GPR64Opnd,
18287 /* PseudoDMULTu */
18288 ACC128, GPR64Opnd, GPR64Opnd,
18289 /* PseudoDSDIV */
18290 ACC128, GPR64Opnd, GPR64Opnd,
18291 /* PseudoDUDIV */
18292 ACC128, GPR64Opnd, GPR64Opnd,
18293 /* PseudoD_SELECT_I */
18294 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
18295 /* PseudoD_SELECT_I64 */
18296 GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,
18297 /* PseudoIndirectBranch */
18298 GPR32Opnd,
18299 /* PseudoIndirectBranch64 */
18300 GPR64Opnd,
18301 /* PseudoIndirectBranch64R6 */
18302 GPR64Opnd,
18303 /* PseudoIndirectBranchR6 */
18304 GPR32Opnd,
18305 /* PseudoIndirectBranch_MM */
18306 GPR32Opnd,
18307 /* PseudoIndirectBranch_MMR6 */
18308 GPR32Opnd,
18309 /* PseudoIndirectHazardBranch */
18310 GPR32Opnd,
18311 /* PseudoIndirectHazardBranch64 */
18312 GPR64Opnd,
18313 /* PseudoIndrectHazardBranch64R6 */
18314 GPR64Opnd,
18315 /* PseudoIndrectHazardBranchR6 */
18316 GPR32Opnd,
18317 /* PseudoMADD */
18318 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18319 /* PseudoMADDU */
18320 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18321 /* PseudoMADDU_MM */
18322 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18323 /* PseudoMADD_MM */
18324 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18325 /* PseudoMFHI */
18326 GPR32, ACC64,
18327 /* PseudoMFHI64 */
18328 GPR64, ACC128,
18329 /* PseudoMFHI_MM */
18330 GPR32, ACC64,
18331 /* PseudoMFLO */
18332 GPR32, ACC64,
18333 /* PseudoMFLO64 */
18334 GPR64, ACC128,
18335 /* PseudoMFLO_MM */
18336 GPR32, ACC64,
18337 /* PseudoMSUB */
18338 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18339 /* PseudoMSUBU */
18340 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18341 /* PseudoMSUBU_MM */
18342 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18343 /* PseudoMSUB_MM */
18344 ACC64, GPR32Opnd, GPR32Opnd, ACC64,
18345 /* PseudoMTLOHI */
18346 ACC64, GPR32, GPR32,
18347 /* PseudoMTLOHI64 */
18348 ACC128, GPR64, GPR64,
18349 /* PseudoMTLOHI_DSP */
18350 ACC64DSP, GPR32, GPR32,
18351 /* PseudoMTLOHI_MM */
18352 ACC64, GPR32, GPR32,
18353 /* PseudoMULT */
18354 ACC64, GPR32Opnd, GPR32Opnd,
18355 /* PseudoMULT_MM */
18356 ACC64, GPR32Opnd, GPR32Opnd,
18357 /* PseudoMULTu */
18358 ACC64, GPR32Opnd, GPR32Opnd,
18359 /* PseudoMULTu_MM */
18360 ACC64, GPR32Opnd, GPR32Opnd,
18361 /* PseudoPICK_PH */
18362 DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,
18363 /* PseudoPICK_QB */
18364 DSPROpnd, DSPCC, DSPROpnd, DSPROpnd,
18365 /* PseudoReturn */
18366 GPR32Opnd,
18367 /* PseudoReturn64 */
18368 GPR64Opnd,
18369 /* PseudoSDIV */
18370 ACC64, GPR32Opnd, GPR32Opnd,
18371 /* PseudoSELECTFP_F_D32 */
18372 AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
18373 /* PseudoSELECTFP_F_D64 */
18374 FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
18375 /* PseudoSELECTFP_F_I */
18376 GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,
18377 /* PseudoSELECTFP_F_I64 */
18378 GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,
18379 /* PseudoSELECTFP_F_S */
18380 FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
18381 /* PseudoSELECTFP_T_D32 */
18382 AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
18383 /* PseudoSELECTFP_T_D64 */
18384 FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
18385 /* PseudoSELECTFP_T_I */
18386 GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd,
18387 /* PseudoSELECTFP_T_I64 */
18388 GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd,
18389 /* PseudoSELECTFP_T_S */
18390 FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
18391 /* PseudoSELECT_D32 */
18392 AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd,
18393 /* PseudoSELECT_D64 */
18394 FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd,
18395 /* PseudoSELECT_I */
18396 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
18397 /* PseudoSELECT_I64 */
18398 GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd,
18399 /* PseudoSELECT_S */
18400 FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd,
18401 /* PseudoTRUNC_W_D */
18402 FGR32Opnd, FGR64Opnd, GPR32Opnd,
18403 /* PseudoTRUNC_W_D32 */
18404 FGR32Opnd, AFGR64Opnd, GPR32Opnd,
18405 /* PseudoTRUNC_W_S */
18406 FGR32Opnd, FGR32Opnd, GPR32Opnd,
18407 /* PseudoUDIV */
18408 ACC64, GPR32Opnd, GPR32Opnd,
18409 /* ROL */
18410 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18411 /* ROLImm */
18412 GPR32Opnd, GPR32Opnd, simm16,
18413 /* ROR */
18414 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18415 /* RORImm */
18416 GPR32Opnd, GPR32Opnd, simm16,
18417 /* RetRA */
18418 /* RetRA16 */
18419 /* SDC1_M1 */
18420 AFGR64Opnd, -1, simm16,
18421 /* SDIV_MM_Pseudo */
18422 ACC64, GPR32Opnd, GPR32Opnd,
18423 /* SDMacro */
18424 GPR32Opnd, -1, simm16,
18425 /* SDivIMacro */
18426 GPR32Opnd, GPR32Opnd, simm32,
18427 /* SDivMacro */
18428 GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd,
18429 /* SEQIMacro */
18430 GPR32Opnd, GPR32Opnd, simm32_relaxed,
18431 /* SEQMacro */
18432 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18433 /* SGE */
18434 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18435 /* SGEImm */
18436 GPR32Opnd, GPR32Opnd, simm32,
18437 /* SGEImm64 */
18438 GPR64Opnd, GPR64Opnd, imm64,
18439 /* SGEU */
18440 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18441 /* SGEUImm */
18442 GPR32Opnd, GPR32Opnd, uimm32_coerced,
18443 /* SGEUImm64 */
18444 GPR64Opnd, GPR64Opnd, imm64,
18445 /* SGTImm */
18446 GPR32Opnd, GPR32Opnd, simm32,
18447 /* SGTImm64 */
18448 GPR64Opnd, GPR64Opnd, imm64,
18449 /* SGTUImm */
18450 GPR32Opnd, GPR32Opnd, uimm32_coerced,
18451 /* SGTUImm64 */
18452 GPR64Opnd, GPR64Opnd, imm64,
18453 /* SLE */
18454 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18455 /* SLEImm */
18456 GPR32Opnd, GPR32Opnd, simm32,
18457 /* SLEImm64 */
18458 GPR64Opnd, GPR64Opnd, imm64,
18459 /* SLEU */
18460 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18461 /* SLEUImm */
18462 GPR32Opnd, GPR32Opnd, uimm32_coerced,
18463 /* SLEUImm64 */
18464 GPR64Opnd, GPR64Opnd, imm64,
18465 /* SLTImm64 */
18466 GPR64Opnd, GPR64Opnd, imm64,
18467 /* SLTUImm64 */
18468 GPR64Opnd, GPR64Opnd, imm64,
18469 /* SNEIMacro */
18470 GPR32Opnd, GPR32Opnd, simm32_relaxed,
18471 /* SNEMacro */
18472 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18473 /* SNZ_B_PSEUDO */
18474 GPR32, MSA128B,
18475 /* SNZ_D_PSEUDO */
18476 GPR32, MSA128D,
18477 /* SNZ_H_PSEUDO */
18478 GPR32, MSA128H,
18479 /* SNZ_V_PSEUDO */
18480 GPR32, MSA128B,
18481 /* SNZ_W_PSEUDO */
18482 GPR32, MSA128W,
18483 /* SRemIMacro */
18484 GPR32Opnd, GPR32Opnd, simm32_relaxed,
18485 /* SRemMacro */
18486 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18487 /* STORE_ACC128 */
18488 ACC128, -1, simm16,
18489 /* STORE_ACC64 */
18490 ACC64, -1, simm16,
18491 /* STORE_ACC64DSP */
18492 ACC64DSPOpnd, -1, simm16,
18493 /* STORE_CCOND_DSP */
18494 DSPCC, -1, simm16,
18495 /* STR_D */
18496 MSA128DOpnd, -1, GPR32,
18497 /* STR_W */
18498 MSA128WOpnd, -1, GPR32,
18499 /* ST_F16 */
18500 MSA128F16, -1, simm10,
18501 /* SWM_MM */
18502 reglist, -1, simm12,
18503 /* SZ_B_PSEUDO */
18504 GPR32, MSA128B,
18505 /* SZ_D_PSEUDO */
18506 GPR32, MSA128D,
18507 /* SZ_H_PSEUDO */
18508 GPR32, MSA128H,
18509 /* SZ_V_PSEUDO */
18510 GPR32, MSA128B,
18511 /* SZ_W_PSEUDO */
18512 GPR32, MSA128W,
18513 /* SaaAddr */
18514 GPR64Opnd, -1, simm16,
18515 /* SaadAddr */
18516 GPR64Opnd, -1, simm16,
18517 /* SelBeqZ */
18518 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18519 /* SelBneZ */
18520 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18521 /* SelTBteqZCmp */
18522 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18523 /* SelTBteqZCmpi */
18524 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18525 /* SelTBteqZSlt */
18526 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18527 /* SelTBteqZSlti */
18528 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18529 /* SelTBteqZSltiu */
18530 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18531 /* SelTBteqZSltu */
18532 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18533 /* SelTBtneZCmp */
18534 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18535 /* SelTBtneZCmpi */
18536 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18537 /* SelTBtneZSlt */
18538 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18539 /* SelTBtneZSlti */
18540 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18541 /* SelTBtneZSltiu */
18542 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16,
18543 /* SelTBtneZSltu */
18544 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs,
18545 /* SltCCRxRy16 */
18546 CPU16Regs, CPU16Regs, CPU16Regs,
18547 /* SltiCCRxImmX16 */
18548 CPU16Regs, CPU16Regs, simm16,
18549 /* SltiuCCRxImmX16 */
18550 CPU16Regs, CPU16Regs, simm16,
18551 /* SltuCCRxRy16 */
18552 CPU16Regs, CPU16Regs, CPU16Regs,
18553 /* SltuRxRyRz16 */
18554 CPU16Regs, CPU16Regs, CPU16Regs,
18555 /* TAILCALL */
18556 calltarget,
18557 /* TAILCALL64R6REG */
18558 GPR64Opnd,
18559 /* TAILCALLHB64R6REG */
18560 GPR64Opnd,
18561 /* TAILCALLHBR6REG */
18562 GPR32Opnd,
18563 /* TAILCALLR6REG */
18564 GPR32Opnd,
18565 /* TAILCALLREG */
18566 GPR32Opnd,
18567 /* TAILCALLREG64 */
18568 GPR64Opnd,
18569 /* TAILCALLREGHB */
18570 GPR32Opnd,
18571 /* TAILCALLREGHB64 */
18572 GPR64Opnd,
18573 /* TAILCALLREG_MM */
18574 GPR32Opnd,
18575 /* TAILCALLREG_MMR6 */
18576 GPR32Opnd,
18577 /* TAILCALL_MM */
18578 calltarget,
18579 /* TAILCALL_MMR6 */
18580 calltarget,
18581 /* TRAP */
18582 /* TRAP_MM */
18583 /* UDIV_MM_Pseudo */
18584 ACC64, GPR32Opnd, GPR32Opnd,
18585 /* UDivIMacro */
18586 GPR32Opnd, GPR32Opnd, simm32,
18587 /* UDivMacro */
18588 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18589 /* URemIMacro */
18590 GPR32Opnd, GPR32Opnd, simm32_relaxed,
18591 /* URemMacro */
18592 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18593 /* Ulh */
18594 GPR32Opnd, -1, simm16,
18595 /* Ulhu */
18596 GPR32Opnd, -1, simm16,
18597 /* Ulw */
18598 GPR32Opnd, -1, simm16,
18599 /* Ush */
18600 GPR32Opnd, -1, simm16,
18601 /* Usw */
18602 GPR32Opnd, -1, simm16,
18603 /* XOR_V_D_PSEUDO */
18604 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18605 /* XOR_V_H_PSEUDO */
18606 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18607 /* XOR_V_W_PSEUDO */
18608 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18609 /* ABSQ_S_PH */
18610 DSPROpnd, DSPROpnd,
18611 /* ABSQ_S_PH_MM */
18612 DSPROpnd, DSPROpnd,
18613 /* ABSQ_S_QB */
18614 DSPROpnd, DSPROpnd,
18615 /* ABSQ_S_QB_MMR2 */
18616 DSPROpnd, DSPROpnd,
18617 /* ABSQ_S_W */
18618 GPR32Opnd, GPR32Opnd,
18619 /* ABSQ_S_W_MM */
18620 GPR32Opnd, GPR32Opnd,
18621 /* ADD */
18622 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18623 /* ADDIUPC */
18624 GPR32Opnd, simm19_lsl2,
18625 /* ADDIUPC_MM */
18626 GPRMM16Opnd, simm23_lsl2,
18627 /* ADDIUPC_MMR6 */
18628 GPR32Opnd, simm19_lsl2,
18629 /* ADDIUR1SP_MM */
18630 GPRMM16Opnd, uimm6_lsl2,
18631 /* ADDIUR2_MM */
18632 GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2,
18633 /* ADDIUS5_MM */
18634 GPR32Opnd, GPR32Opnd, simm4,
18635 /* ADDIUSP_MM */
18636 simm9_addiusp,
18637 /* ADDIU_MMR6 */
18638 GPR32Opnd, GPR32Opnd, simm16,
18639 /* ADDQH_PH */
18640 DSPROpnd, DSPROpnd, DSPROpnd,
18641 /* ADDQH_PH_MMR2 */
18642 DSPROpnd, DSPROpnd, DSPROpnd,
18643 /* ADDQH_R_PH */
18644 DSPROpnd, DSPROpnd, DSPROpnd,
18645 /* ADDQH_R_PH_MMR2 */
18646 DSPROpnd, DSPROpnd, DSPROpnd,
18647 /* ADDQH_R_W */
18648 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18649 /* ADDQH_R_W_MMR2 */
18650 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18651 /* ADDQH_W */
18652 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18653 /* ADDQH_W_MMR2 */
18654 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18655 /* ADDQ_PH */
18656 DSPROpnd, DSPROpnd, DSPROpnd,
18657 /* ADDQ_PH_MM */
18658 DSPROpnd, DSPROpnd, DSPROpnd,
18659 /* ADDQ_S_PH */
18660 DSPROpnd, DSPROpnd, DSPROpnd,
18661 /* ADDQ_S_PH_MM */
18662 DSPROpnd, DSPROpnd, DSPROpnd,
18663 /* ADDQ_S_W */
18664 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18665 /* ADDQ_S_W_MM */
18666 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18667 /* ADDR_PS64 */
18668 FGR64Opnd, FGR64Opnd, FGR64Opnd,
18669 /* ADDSC */
18670 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18671 /* ADDSC_MM */
18672 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18673 /* ADDS_A_B */
18674 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18675 /* ADDS_A_D */
18676 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18677 /* ADDS_A_H */
18678 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18679 /* ADDS_A_W */
18680 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18681 /* ADDS_S_B */
18682 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18683 /* ADDS_S_D */
18684 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18685 /* ADDS_S_H */
18686 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18687 /* ADDS_S_W */
18688 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18689 /* ADDS_U_B */
18690 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18691 /* ADDS_U_D */
18692 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18693 /* ADDS_U_H */
18694 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18695 /* ADDS_U_W */
18696 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18697 /* ADDU16_MM */
18698 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18699 /* ADDU16_MMR6 */
18700 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18701 /* ADDUH_QB */
18702 DSPROpnd, DSPROpnd, DSPROpnd,
18703 /* ADDUH_QB_MMR2 */
18704 DSPROpnd, DSPROpnd, DSPROpnd,
18705 /* ADDUH_R_QB */
18706 DSPROpnd, DSPROpnd, DSPROpnd,
18707 /* ADDUH_R_QB_MMR2 */
18708 DSPROpnd, DSPROpnd, DSPROpnd,
18709 /* ADDU_MMR6 */
18710 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18711 /* ADDU_PH */
18712 DSPROpnd, DSPROpnd, DSPROpnd,
18713 /* ADDU_PH_MMR2 */
18714 DSPROpnd, DSPROpnd, DSPROpnd,
18715 /* ADDU_QB */
18716 DSPROpnd, DSPROpnd, DSPROpnd,
18717 /* ADDU_QB_MM */
18718 DSPROpnd, DSPROpnd, DSPROpnd,
18719 /* ADDU_S_PH */
18720 DSPROpnd, DSPROpnd, DSPROpnd,
18721 /* ADDU_S_PH_MMR2 */
18722 DSPROpnd, DSPROpnd, DSPROpnd,
18723 /* ADDU_S_QB */
18724 DSPROpnd, DSPROpnd, DSPROpnd,
18725 /* ADDU_S_QB_MM */
18726 DSPROpnd, DSPROpnd, DSPROpnd,
18727 /* ADDVI_B */
18728 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
18729 /* ADDVI_D */
18730 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
18731 /* ADDVI_H */
18732 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
18733 /* ADDVI_W */
18734 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18735 /* ADDV_B */
18736 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18737 /* ADDV_D */
18738 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18739 /* ADDV_H */
18740 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18741 /* ADDV_W */
18742 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18743 /* ADDWC */
18744 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18745 /* ADDWC_MM */
18746 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18747 /* ADD_A_B */
18748 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18749 /* ADD_A_D */
18750 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18751 /* ADD_A_H */
18752 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18753 /* ADD_A_W */
18754 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18755 /* ADD_MM */
18756 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18757 /* ADD_MMR6 */
18758 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18759 /* ADDi */
18760 GPR32Opnd, GPR32Opnd, simm16_relaxed,
18761 /* ADDi_MM */
18762 GPR32Opnd, GPR32Opnd, simm16,
18763 /* ADDiu */
18764 GPR32Opnd, GPR32Opnd, simm16_relaxed,
18765 /* ADDiu_MM */
18766 GPR32Opnd, GPR32Opnd, simm16,
18767 /* ADDu */
18768 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18769 /* ADDu_MM */
18770 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18771 /* ALIGN */
18772 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,
18773 /* ALIGN_MMR6 */
18774 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2,
18775 /* ALUIPC */
18776 GPR32Opnd, simm16,
18777 /* ALUIPC_MMR6 */
18778 GPR32Opnd, simm16,
18779 /* AND */
18780 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18781 /* AND16_MM */
18782 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18783 /* AND16_MMR6 */
18784 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
18785 /* AND64 */
18786 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18787 /* ANDI16_MM */
18788 GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,
18789 /* ANDI16_MMR6 */
18790 GPRMM16Opnd, GPRMM16Opnd, uimm4_andi,
18791 /* ANDI_B */
18792 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
18793 /* ANDI_MMR6 */
18794 GPR32Opnd, GPR32Opnd, uimm16,
18795 /* AND_MM */
18796 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18797 /* AND_MMR6 */
18798 GPR32Opnd, GPR32Opnd, GPR32Opnd,
18799 /* AND_V */
18800 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18801 /* ANDi */
18802 GPR32Opnd, GPR32Opnd, uimm16,
18803 /* ANDi64 */
18804 GPR64Opnd, GPR64Opnd, uimm16_64,
18805 /* ANDi_MM */
18806 GPR32Opnd, GPR32Opnd, uimm16,
18807 /* APPEND */
18808 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
18809 /* APPEND_MMR2 */
18810 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
18811 /* ASUB_S_B */
18812 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18813 /* ASUB_S_D */
18814 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18815 /* ASUB_S_H */
18816 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18817 /* ASUB_S_W */
18818 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18819 /* ASUB_U_B */
18820 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18821 /* ASUB_U_D */
18822 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18823 /* ASUB_U_H */
18824 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18825 /* ASUB_U_W */
18826 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18827 /* AUI */
18828 GPR32Opnd, GPR32Opnd, uimm16,
18829 /* AUIPC */
18830 GPR32Opnd, simm16,
18831 /* AUIPC_MMR6 */
18832 GPR32Opnd, simm16,
18833 /* AUI_MMR6 */
18834 GPR32Opnd, GPR32Opnd, uimm16,
18835 /* AVER_S_B */
18836 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18837 /* AVER_S_D */
18838 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18839 /* AVER_S_H */
18840 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18841 /* AVER_S_W */
18842 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18843 /* AVER_U_B */
18844 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18845 /* AVER_U_D */
18846 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18847 /* AVER_U_H */
18848 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18849 /* AVER_U_W */
18850 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18851 /* AVE_S_B */
18852 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18853 /* AVE_S_D */
18854 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18855 /* AVE_S_H */
18856 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18857 /* AVE_S_W */
18858 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18859 /* AVE_U_B */
18860 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18861 /* AVE_U_D */
18862 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18863 /* AVE_U_H */
18864 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18865 /* AVE_U_W */
18866 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18867 /* AddiuRxImmX16 */
18868 CPU16Regs, simm16,
18869 /* AddiuRxPcImmX16 */
18870 CPU16Regs, simm16,
18871 /* AddiuRxRxImm16 */
18872 CPU16Regs, CPU16Regs, simm16,
18873 /* AddiuRxRxImmX16 */
18874 CPU16Regs, CPU16Regs, simm16,
18875 /* AddiuRxRyOffMemX16 */
18876 CPU16Regs, CPU16RegsPlusSP, simm16,
18877 /* AddiuSpImm16 */
18878 simm16,
18879 /* AddiuSpImmX16 */
18880 simm16,
18881 /* AdduRxRyRz16 */
18882 CPU16Regs, CPU16Regs, CPU16Regs,
18883 /* AndRxRxRy16 */
18884 CPU16Regs, CPU16Regs, CPU16Regs,
18885 /* B16_MM */
18886 brtarget10_mm,
18887 /* BADDu */
18888 GPR64Opnd, GPR64Opnd, GPR64Opnd,
18889 /* BAL */
18890 brtarget,
18891 /* BALC */
18892 brtarget26,
18893 /* BALC_MMR6 */
18894 brtarget26_mm,
18895 /* BALIGN */
18896 GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,
18897 /* BALIGN_MMR2 */
18898 GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd,
18899 /* BBIT0 */
18900 GPR64Opnd, uimm5_64_report_uimm6, brtarget,
18901 /* BBIT032 */
18902 GPR64Opnd, uimm5_64, brtarget,
18903 /* BBIT1 */
18904 GPR64Opnd, uimm5_64_report_uimm6, brtarget,
18905 /* BBIT132 */
18906 GPR64Opnd, uimm5_64, brtarget,
18907 /* BC */
18908 brtarget26,
18909 /* BC16_MMR6 */
18910 brtarget10_mm,
18911 /* BC1EQZ */
18912 FGR64Opnd, brtarget,
18913 /* BC1EQZC_MMR6 */
18914 FGR64Opnd, brtarget_mm,
18915 /* BC1F */
18916 FCCRegsOpnd, brtarget,
18917 /* BC1FL */
18918 FCCRegsOpnd, brtarget,
18919 /* BC1F_MM */
18920 FCCRegsOpnd, brtarget_mm,
18921 /* BC1NEZ */
18922 FGR64Opnd, brtarget,
18923 /* BC1NEZC_MMR6 */
18924 FGR64Opnd, brtarget_mm,
18925 /* BC1T */
18926 FCCRegsOpnd, brtarget,
18927 /* BC1TL */
18928 FCCRegsOpnd, brtarget,
18929 /* BC1T_MM */
18930 FCCRegsOpnd, brtarget_mm,
18931 /* BC2EQZ */
18932 COP2Opnd, brtarget,
18933 /* BC2EQZC_MMR6 */
18934 COP2Opnd, brtarget_mm,
18935 /* BC2NEZ */
18936 COP2Opnd, brtarget,
18937 /* BC2NEZC_MMR6 */
18938 COP2Opnd, brtarget_mm,
18939 /* BCLRI_B */
18940 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
18941 /* BCLRI_D */
18942 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
18943 /* BCLRI_H */
18944 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
18945 /* BCLRI_W */
18946 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
18947 /* BCLR_B */
18948 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
18949 /* BCLR_D */
18950 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
18951 /* BCLR_H */
18952 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
18953 /* BCLR_W */
18954 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
18955 /* BC_MMR6 */
18956 brtarget26_mm,
18957 /* BEQ */
18958 GPR32Opnd, GPR32Opnd, brtarget,
18959 /* BEQ64 */
18960 GPR64Opnd, GPR64Opnd, brtarget,
18961 /* BEQC */
18962 GPR32Opnd, GPR32Opnd, brtarget,
18963 /* BEQC64 */
18964 GPR64Opnd, GPR64Opnd, brtarget,
18965 /* BEQC_MMR6 */
18966 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18967 /* BEQL */
18968 GPR32Opnd, GPR32Opnd, brtarget,
18969 /* BEQZ16_MM */
18970 GPRMM16Opnd, brtarget7_mm,
18971 /* BEQZALC */
18972 GPR32Opnd, brtarget,
18973 /* BEQZALC_MMR6 */
18974 GPR32Opnd, brtarget_mm,
18975 /* BEQZC */
18976 GPR32Opnd, brtarget21,
18977 /* BEQZC16_MMR6 */
18978 GPRMM16Opnd, brtarget7_mm,
18979 /* BEQZC64 */
18980 GPR64Opnd, brtarget21,
18981 /* BEQZC_MM */
18982 GPR32Opnd, brtarget_mm,
18983 /* BEQZC_MMR6 */
18984 GPR32Opnd, brtarget21_mm,
18985 /* BEQ_MM */
18986 GPR32Opnd, GPR32Opnd, brtarget_mm,
18987 /* BGEC */
18988 GPR32Opnd, GPR32Opnd, brtarget,
18989 /* BGEC64 */
18990 GPR64Opnd, GPR64Opnd, brtarget,
18991 /* BGEC_MMR6 */
18992 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18993 /* BGEUC */
18994 GPR32Opnd, GPR32Opnd, brtarget,
18995 /* BGEUC64 */
18996 GPR64Opnd, GPR64Opnd, brtarget,
18997 /* BGEUC_MMR6 */
18998 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
18999 /* BGEZ */
19000 GPR32Opnd, brtarget,
19001 /* BGEZ64 */
19002 GPR64Opnd, brtarget,
19003 /* BGEZAL */
19004 GPR32Opnd, brtarget,
19005 /* BGEZALC */
19006 GPR32Opnd, brtarget,
19007 /* BGEZALC_MMR6 */
19008 GPR32Opnd, brtarget_mm,
19009 /* BGEZALL */
19010 GPR32Opnd, brtarget,
19011 /* BGEZALS_MM */
19012 GPR32Opnd, brtarget_mm,
19013 /* BGEZAL_MM */
19014 GPR32Opnd, brtarget_mm,
19015 /* BGEZC */
19016 GPR32Opnd, brtarget,
19017 /* BGEZC64 */
19018 GPR64Opnd, brtarget,
19019 /* BGEZC_MMR6 */
19020 GPR32Opnd, brtarget_lsl2_mm,
19021 /* BGEZL */
19022 GPR32Opnd, brtarget,
19023 /* BGEZ_MM */
19024 GPR32Opnd, brtarget_mm,
19025 /* BGTZ */
19026 GPR32Opnd, brtarget,
19027 /* BGTZ64 */
19028 GPR64Opnd, brtarget,
19029 /* BGTZALC */
19030 GPR32Opnd, brtarget,
19031 /* BGTZALC_MMR6 */
19032 GPR32Opnd, brtarget_mm,
19033 /* BGTZC */
19034 GPR32Opnd, brtarget,
19035 /* BGTZC64 */
19036 GPR64Opnd, brtarget,
19037 /* BGTZC_MMR6 */
19038 GPR32Opnd, brtarget_lsl2_mm,
19039 /* BGTZL */
19040 GPR32Opnd, brtarget,
19041 /* BGTZ_MM */
19042 GPR32Opnd, brtarget_mm,
19043 /* BINSLI_B */
19044 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
19045 /* BINSLI_D */
19046 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
19047 /* BINSLI_H */
19048 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
19049 /* BINSLI_W */
19050 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19051 /* BINSL_B */
19052 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19053 /* BINSL_D */
19054 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19055 /* BINSL_H */
19056 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19057 /* BINSL_W */
19058 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19059 /* BINSRI_B */
19060 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
19061 /* BINSRI_D */
19062 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
19063 /* BINSRI_H */
19064 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
19065 /* BINSRI_W */
19066 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19067 /* BINSR_B */
19068 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19069 /* BINSR_D */
19070 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19071 /* BINSR_H */
19072 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19073 /* BINSR_W */
19074 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19075 /* BITREV */
19076 GPR32Opnd, GPR32Opnd,
19077 /* BITREV_MM */
19078 GPR32Opnd, GPR32Opnd,
19079 /* BITSWAP */
19080 GPR32Opnd, GPR32Opnd,
19081 /* BITSWAP_MMR6 */
19082 GPR32Opnd, GPR32Opnd,
19083 /* BLEZ */
19084 GPR32Opnd, brtarget,
19085 /* BLEZ64 */
19086 GPR64Opnd, brtarget,
19087 /* BLEZALC */
19088 GPR32Opnd, brtarget,
19089 /* BLEZALC_MMR6 */
19090 GPR32Opnd, brtarget_mm,
19091 /* BLEZC */
19092 GPR32Opnd, brtarget,
19093 /* BLEZC64 */
19094 GPR64Opnd, brtarget,
19095 /* BLEZC_MMR6 */
19096 GPR32Opnd, brtarget_lsl2_mm,
19097 /* BLEZL */
19098 GPR32Opnd, brtarget,
19099 /* BLEZ_MM */
19100 GPR32Opnd, brtarget_mm,
19101 /* BLTC */
19102 GPR32Opnd, GPR32Opnd, brtarget,
19103 /* BLTC64 */
19104 GPR64Opnd, GPR64Opnd, brtarget,
19105 /* BLTC_MMR6 */
19106 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
19107 /* BLTUC */
19108 GPR32Opnd, GPR32Opnd, brtarget,
19109 /* BLTUC64 */
19110 GPR64Opnd, GPR64Opnd, brtarget,
19111 /* BLTUC_MMR6 */
19112 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
19113 /* BLTZ */
19114 GPR32Opnd, brtarget,
19115 /* BLTZ64 */
19116 GPR64Opnd, brtarget,
19117 /* BLTZAL */
19118 GPR32Opnd, brtarget,
19119 /* BLTZALC */
19120 GPR32Opnd, brtarget,
19121 /* BLTZALC_MMR6 */
19122 GPR32Opnd, brtarget_mm,
19123 /* BLTZALL */
19124 GPR32Opnd, brtarget,
19125 /* BLTZALS_MM */
19126 GPR32Opnd, brtarget_mm,
19127 /* BLTZAL_MM */
19128 GPR32Opnd, brtarget_mm,
19129 /* BLTZC */
19130 GPR32Opnd, brtarget,
19131 /* BLTZC64 */
19132 GPR64Opnd, brtarget,
19133 /* BLTZC_MMR6 */
19134 GPR32Opnd, brtarget_lsl2_mm,
19135 /* BLTZL */
19136 GPR32Opnd, brtarget,
19137 /* BLTZ_MM */
19138 GPR32Opnd, brtarget_mm,
19139 /* BMNZI_B */
19140 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
19141 /* BMNZ_V */
19142 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19143 /* BMZI_B */
19144 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
19145 /* BMZ_V */
19146 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19147 /* BNE */
19148 GPR32Opnd, GPR32Opnd, brtarget,
19149 /* BNE64 */
19150 GPR64Opnd, GPR64Opnd, brtarget,
19151 /* BNEC */
19152 GPR32Opnd, GPR32Opnd, brtarget,
19153 /* BNEC64 */
19154 GPR64Opnd, GPR64Opnd, brtarget,
19155 /* BNEC_MMR6 */
19156 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm,
19157 /* BNEGI_B */
19158 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
19159 /* BNEGI_D */
19160 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
19161 /* BNEGI_H */
19162 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
19163 /* BNEGI_W */
19164 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19165 /* BNEG_B */
19166 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19167 /* BNEG_D */
19168 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19169 /* BNEG_H */
19170 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19171 /* BNEG_W */
19172 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19173 /* BNEL */
19174 GPR32Opnd, GPR32Opnd, brtarget,
19175 /* BNEZ16_MM */
19176 GPRMM16Opnd, brtarget7_mm,
19177 /* BNEZALC */
19178 GPR32Opnd, brtarget,
19179 /* BNEZALC_MMR6 */
19180 GPR32Opnd, brtarget_mm,
19181 /* BNEZC */
19182 GPR32Opnd, brtarget21,
19183 /* BNEZC16_MMR6 */
19184 GPRMM16Opnd, brtarget7_mm,
19185 /* BNEZC64 */
19186 GPR64Opnd, brtarget21,
19187 /* BNEZC_MM */
19188 GPR32Opnd, brtarget_mm,
19189 /* BNEZC_MMR6 */
19190 GPR32Opnd, brtarget21_mm,
19191 /* BNE_MM */
19192 GPR32Opnd, GPR32Opnd, brtarget_mm,
19193 /* BNVC */
19194 GPR32Opnd, GPR32Opnd, brtarget,
19195 /* BNVC_MMR6 */
19196 GPR32Opnd, GPR32Opnd, brtargetr6,
19197 /* BNZ_B */
19198 MSA128BOpnd, brtarget,
19199 /* BNZ_D */
19200 MSA128DOpnd, brtarget,
19201 /* BNZ_H */
19202 MSA128HOpnd, brtarget,
19203 /* BNZ_V */
19204 MSA128BOpnd, brtarget,
19205 /* BNZ_W */
19206 MSA128WOpnd, brtarget,
19207 /* BOVC */
19208 GPR32Opnd, GPR32Opnd, brtarget,
19209 /* BOVC_MMR6 */
19210 GPR32Opnd, GPR32Opnd, brtargetr6,
19211 /* BPOSGE32 */
19212 brtarget,
19213 /* BPOSGE32C_MMR3 */
19214 brtarget1SImm16,
19215 /* BPOSGE32_MM */
19216 brtarget_mm,
19217 /* BREAK */
19218 uimm10, uimm10,
19219 /* BREAK16_MM */
19220 uimm4,
19221 /* BREAK16_MMR6 */
19222 uimm4,
19223 /* BREAK_MM */
19224 uimm10, uimm10,
19225 /* BREAK_MMR6 */
19226 uimm10, uimm10,
19227 /* BSELI_B */
19228 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
19229 /* BSEL_V */
19230 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19231 /* BSETI_B */
19232 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
19233 /* BSETI_D */
19234 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
19235 /* BSETI_H */
19236 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
19237 /* BSETI_W */
19238 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19239 /* BSET_B */
19240 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19241 /* BSET_D */
19242 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19243 /* BSET_H */
19244 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19245 /* BSET_W */
19246 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19247 /* BZ_B */
19248 MSA128BOpnd, brtarget,
19249 /* BZ_D */
19250 MSA128DOpnd, brtarget,
19251 /* BZ_H */
19252 MSA128HOpnd, brtarget,
19253 /* BZ_V */
19254 MSA128BOpnd, brtarget,
19255 /* BZ_W */
19256 MSA128WOpnd, brtarget,
19257 /* BeqzRxImm16 */
19258 CPU16Regs, brtarget,
19259 /* BeqzRxImmX16 */
19260 CPU16Regs, brtarget,
19261 /* Bimm16 */
19262 brtarget,
19263 /* BimmX16 */
19264 brtarget,
19265 /* BnezRxImm16 */
19266 CPU16Regs, brtarget,
19267 /* BnezRxImmX16 */
19268 CPU16Regs, brtarget,
19269 /* Break16 */
19270 /* Bteqz16 */
19271 simm16,
19272 /* BteqzX16 */
19273 simm16,
19274 /* Btnez16 */
19275 simm16,
19276 /* BtnezX16 */
19277 simm16,
19278 /* CACHE */
19279 -1, simm16, uimm5,
19280 /* CACHEE */
19281 -1, simm9, uimm5,
19282 /* CACHEE_MM */
19283 -1, simm9, uimm5,
19284 /* CACHE_MM */
19285 -1, simm12, uimm5,
19286 /* CACHE_MMR6 */
19287 -1, simm12, uimm5,
19288 /* CACHE_R6 */
19289 -1, simm9, uimm5,
19290 /* CEIL_L_D64 */
19291 FGR64Opnd, FGR64Opnd,
19292 /* CEIL_L_D_MMR6 */
19293 FGR64Opnd, FGR64Opnd,
19294 /* CEIL_L_S */
19295 FGR64Opnd, FGR32Opnd,
19296 /* CEIL_L_S_MMR6 */
19297 FGR64Opnd, FGR32Opnd,
19298 /* CEIL_W_D32 */
19299 FGR32Opnd, AFGR64Opnd,
19300 /* CEIL_W_D64 */
19301 FGR32Opnd, FGR64Opnd,
19302 /* CEIL_W_D_MMR6 */
19303 FGR32Opnd, AFGR64Opnd,
19304 /* CEIL_W_MM */
19305 FGR32Opnd, AFGR64Opnd,
19306 /* CEIL_W_S */
19307 FGR32Opnd, FGR32Opnd,
19308 /* CEIL_W_S_MM */
19309 FGR32Opnd, FGR32Opnd,
19310 /* CEIL_W_S_MMR6 */
19311 FGR32Opnd, FGR32Opnd,
19312 /* CEQI_B */
19313 MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
19314 /* CEQI_D */
19315 MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
19316 /* CEQI_H */
19317 MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
19318 /* CEQI_W */
19319 MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
19320 /* CEQ_B */
19321 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19322 /* CEQ_D */
19323 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19324 /* CEQ_H */
19325 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19326 /* CEQ_W */
19327 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19328 /* CFC1 */
19329 GPR32Opnd, CCROpnd,
19330 /* CFC1_MM */
19331 GPR32Opnd, CCROpnd,
19332 /* CFC2_MM */
19333 GPR32Opnd, COP2Opnd,
19334 /* CFCMSA */
19335 GPR32Opnd, MSA128CROpnd,
19336 /* CINS */
19337 GPR64Opnd, GPR64Opnd, uimm5, uimm5,
19338 /* CINS32 */
19339 GPR64Opnd, GPR64Opnd, uimm5, uimm5,
19340 /* CINS64_32 */
19341 GPR64Opnd, GPR32Opnd, uimm5, uimm5,
19342 /* CINS_i32 */
19343 GPR32Opnd, GPR32Opnd, uimm5, uimm5,
19344 /* CLASS_D */
19345 FGR64Opnd, FGR64Opnd,
19346 /* CLASS_D_MMR6 */
19347 FGR64Opnd, FGR64Opnd,
19348 /* CLASS_S */
19349 FGR32Opnd, FGR32Opnd,
19350 /* CLASS_S_MMR6 */
19351 FGR32Opnd, FGR32Opnd,
19352 /* CLEI_S_B */
19353 MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
19354 /* CLEI_S_D */
19355 MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
19356 /* CLEI_S_H */
19357 MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
19358 /* CLEI_S_W */
19359 MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
19360 /* CLEI_U_B */
19361 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
19362 /* CLEI_U_D */
19363 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
19364 /* CLEI_U_H */
19365 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
19366 /* CLEI_U_W */
19367 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19368 /* CLE_S_B */
19369 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19370 /* CLE_S_D */
19371 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19372 /* CLE_S_H */
19373 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19374 /* CLE_S_W */
19375 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19376 /* CLE_U_B */
19377 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19378 /* CLE_U_D */
19379 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19380 /* CLE_U_H */
19381 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19382 /* CLE_U_W */
19383 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19384 /* CLO */
19385 GPR32Opnd, GPR32Opnd,
19386 /* CLO_MM */
19387 GPR32Opnd, GPR32Opnd,
19388 /* CLO_MMR6 */
19389 GPR32Opnd, GPR32Opnd,
19390 /* CLO_R6 */
19391 GPR32Opnd, GPR32Opnd,
19392 /* CLTI_S_B */
19393 MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
19394 /* CLTI_S_D */
19395 MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
19396 /* CLTI_S_H */
19397 MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
19398 /* CLTI_S_W */
19399 MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
19400 /* CLTI_U_B */
19401 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
19402 /* CLTI_U_D */
19403 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
19404 /* CLTI_U_H */
19405 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
19406 /* CLTI_U_W */
19407 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
19408 /* CLT_S_B */
19409 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19410 /* CLT_S_D */
19411 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19412 /* CLT_S_H */
19413 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19414 /* CLT_S_W */
19415 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19416 /* CLT_U_B */
19417 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19418 /* CLT_U_D */
19419 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19420 /* CLT_U_H */
19421 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19422 /* CLT_U_W */
19423 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19424 /* CLZ */
19425 GPR32Opnd, GPR32Opnd,
19426 /* CLZ_MM */
19427 GPR32Opnd, GPR32Opnd,
19428 /* CLZ_MMR6 */
19429 GPR32Opnd, GPR32Opnd,
19430 /* CLZ_R6 */
19431 GPR32Opnd, GPR32Opnd,
19432 /* CMPGDU_EQ_QB */
19433 GPR32Opnd, DSPROpnd, DSPROpnd,
19434 /* CMPGDU_EQ_QB_MMR2 */
19435 GPR32Opnd, DSPROpnd, DSPROpnd,
19436 /* CMPGDU_LE_QB */
19437 GPR32Opnd, DSPROpnd, DSPROpnd,
19438 /* CMPGDU_LE_QB_MMR2 */
19439 GPR32Opnd, DSPROpnd, DSPROpnd,
19440 /* CMPGDU_LT_QB */
19441 GPR32Opnd, DSPROpnd, DSPROpnd,
19442 /* CMPGDU_LT_QB_MMR2 */
19443 GPR32Opnd, DSPROpnd, DSPROpnd,
19444 /* CMPGU_EQ_QB */
19445 GPR32Opnd, DSPROpnd, DSPROpnd,
19446 /* CMPGU_EQ_QB_MM */
19447 GPR32Opnd, DSPROpnd, DSPROpnd,
19448 /* CMPGU_LE_QB */
19449 GPR32Opnd, DSPROpnd, DSPROpnd,
19450 /* CMPGU_LE_QB_MM */
19451 GPR32Opnd, DSPROpnd, DSPROpnd,
19452 /* CMPGU_LT_QB */
19453 GPR32Opnd, DSPROpnd, DSPROpnd,
19454 /* CMPGU_LT_QB_MM */
19455 GPR32Opnd, DSPROpnd, DSPROpnd,
19456 /* CMPU_EQ_QB */
19457 DSPROpnd, DSPROpnd,
19458 /* CMPU_EQ_QB_MM */
19459 DSPROpnd, DSPROpnd,
19460 /* CMPU_LE_QB */
19461 DSPROpnd, DSPROpnd,
19462 /* CMPU_LE_QB_MM */
19463 DSPROpnd, DSPROpnd,
19464 /* CMPU_LT_QB */
19465 DSPROpnd, DSPROpnd,
19466 /* CMPU_LT_QB_MM */
19467 DSPROpnd, DSPROpnd,
19468 /* CMP_AF_D_MMR6 */
19469 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19470 /* CMP_AF_S_MMR6 */
19471 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19472 /* CMP_EQ_D */
19473 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19474 /* CMP_EQ_D_MMR6 */
19475 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19476 /* CMP_EQ_PH */
19477 DSPROpnd, DSPROpnd,
19478 /* CMP_EQ_PH_MM */
19479 DSPROpnd, DSPROpnd,
19480 /* CMP_EQ_S */
19481 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19482 /* CMP_EQ_S_MMR6 */
19483 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19484 /* CMP_F_D */
19485 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19486 /* CMP_F_S */
19487 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19488 /* CMP_LE_D */
19489 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19490 /* CMP_LE_D_MMR6 */
19491 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19492 /* CMP_LE_PH */
19493 DSPROpnd, DSPROpnd,
19494 /* CMP_LE_PH_MM */
19495 DSPROpnd, DSPROpnd,
19496 /* CMP_LE_S */
19497 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19498 /* CMP_LE_S_MMR6 */
19499 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19500 /* CMP_LT_D */
19501 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19502 /* CMP_LT_D_MMR6 */
19503 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19504 /* CMP_LT_PH */
19505 DSPROpnd, DSPROpnd,
19506 /* CMP_LT_PH_MM */
19507 DSPROpnd, DSPROpnd,
19508 /* CMP_LT_S */
19509 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19510 /* CMP_LT_S_MMR6 */
19511 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19512 /* CMP_SAF_D */
19513 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19514 /* CMP_SAF_D_MMR6 */
19515 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19516 /* CMP_SAF_S */
19517 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19518 /* CMP_SAF_S_MMR6 */
19519 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19520 /* CMP_SEQ_D */
19521 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19522 /* CMP_SEQ_D_MMR6 */
19523 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19524 /* CMP_SEQ_S */
19525 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19526 /* CMP_SEQ_S_MMR6 */
19527 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19528 /* CMP_SLE_D */
19529 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19530 /* CMP_SLE_D_MMR6 */
19531 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19532 /* CMP_SLE_S */
19533 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19534 /* CMP_SLE_S_MMR6 */
19535 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19536 /* CMP_SLT_D */
19537 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19538 /* CMP_SLT_D_MMR6 */
19539 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19540 /* CMP_SLT_S */
19541 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19542 /* CMP_SLT_S_MMR6 */
19543 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19544 /* CMP_SUEQ_D */
19545 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19546 /* CMP_SUEQ_D_MMR6 */
19547 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19548 /* CMP_SUEQ_S */
19549 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19550 /* CMP_SUEQ_S_MMR6 */
19551 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19552 /* CMP_SULE_D */
19553 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19554 /* CMP_SULE_D_MMR6 */
19555 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19556 /* CMP_SULE_S */
19557 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19558 /* CMP_SULE_S_MMR6 */
19559 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19560 /* CMP_SULT_D */
19561 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19562 /* CMP_SULT_D_MMR6 */
19563 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19564 /* CMP_SULT_S */
19565 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19566 /* CMP_SULT_S_MMR6 */
19567 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19568 /* CMP_SUN_D */
19569 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19570 /* CMP_SUN_D_MMR6 */
19571 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19572 /* CMP_SUN_S */
19573 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19574 /* CMP_SUN_S_MMR6 */
19575 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19576 /* CMP_UEQ_D */
19577 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19578 /* CMP_UEQ_D_MMR6 */
19579 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19580 /* CMP_UEQ_S */
19581 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19582 /* CMP_UEQ_S_MMR6 */
19583 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19584 /* CMP_ULE_D */
19585 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19586 /* CMP_ULE_D_MMR6 */
19587 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19588 /* CMP_ULE_S */
19589 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19590 /* CMP_ULE_S_MMR6 */
19591 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19592 /* CMP_ULT_D */
19593 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19594 /* CMP_ULT_D_MMR6 */
19595 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19596 /* CMP_ULT_S */
19597 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19598 /* CMP_ULT_S_MMR6 */
19599 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19600 /* CMP_UN_D */
19601 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19602 /* CMP_UN_D_MMR6 */
19603 FGRCCOpnd, FGR64Opnd, FGR64Opnd,
19604 /* CMP_UN_S */
19605 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19606 /* CMP_UN_S_MMR6 */
19607 FGRCCOpnd, FGR32Opnd, FGR32Opnd,
19608 /* COPY_S_B */
19609 GPR32Opnd, MSA128BOpnd, uimm4_ptr,
19610 /* COPY_S_D */
19611 GPR64Opnd, MSA128DOpnd, uimm1_ptr,
19612 /* COPY_S_H */
19613 GPR32Opnd, MSA128HOpnd, uimm3_ptr,
19614 /* COPY_S_W */
19615 GPR32Opnd, MSA128WOpnd, uimm2_ptr,
19616 /* COPY_U_B */
19617 GPR32Opnd, MSA128BOpnd, uimm4_ptr,
19618 /* COPY_U_H */
19619 GPR32Opnd, MSA128HOpnd, uimm3_ptr,
19620 /* COPY_U_W */
19621 GPR32Opnd, MSA128WOpnd, uimm2_ptr,
19622 /* CRC32B */
19623 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19624 /* CRC32CB */
19625 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19626 /* CRC32CD */
19627 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19628 /* CRC32CH */
19629 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19630 /* CRC32CW */
19631 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19632 /* CRC32D */
19633 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19634 /* CRC32H */
19635 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19636 /* CRC32W */
19637 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19638 /* CTC1 */
19639 CCROpnd, GPR32Opnd,
19640 /* CTC1_MM */
19641 CCROpnd, GPR32Opnd,
19642 /* CTC2_MM */
19643 COP2Opnd, GPR32Opnd,
19644 /* CTCMSA */
19645 MSA128CROpnd, GPR32Opnd,
19646 /* CVT_D32_S */
19647 AFGR64Opnd, FGR32Opnd,
19648 /* CVT_D32_S_MM */
19649 AFGR64Opnd, FGR32Opnd,
19650 /* CVT_D32_W */
19651 AFGR64Opnd, FGR32Opnd,
19652 /* CVT_D32_W_MM */
19653 AFGR64Opnd, FGR32Opnd,
19654 /* CVT_D64_L */
19655 FGR64Opnd, FGR64Opnd,
19656 /* CVT_D64_S */
19657 FGR64Opnd, FGR32Opnd,
19658 /* CVT_D64_S_MM */
19659 FGR64Opnd, FGR32Opnd,
19660 /* CVT_D64_W */
19661 FGR64Opnd, FGR32Opnd,
19662 /* CVT_D64_W_MM */
19663 FGR64Opnd, FGR32Opnd,
19664 /* CVT_D_L_MMR6 */
19665 FGR64Opnd, FGR64Opnd,
19666 /* CVT_L_D64 */
19667 FGR64Opnd, FGR64Opnd,
19668 /* CVT_L_D64_MM */
19669 FGR64Opnd, FGR64Opnd,
19670 /* CVT_L_D_MMR6 */
19671 FGR64Opnd, FGR64Opnd,
19672 /* CVT_L_S */
19673 FGR64Opnd, FGR32Opnd,
19674 /* CVT_L_S_MM */
19675 FGR64Opnd, FGR32Opnd,
19676 /* CVT_L_S_MMR6 */
19677 FGR64Opnd, FGR32Opnd,
19678 /* CVT_PS_PW64 */
19679 FGR64Opnd, FGR64Opnd,
19680 /* CVT_PS_S64 */
19681 FGR64Opnd, FGR32Opnd, FGR32Opnd,
19682 /* CVT_PW_PS64 */
19683 FGR64Opnd, FGR64Opnd,
19684 /* CVT_S_D32 */
19685 FGR32Opnd, AFGR64Opnd,
19686 /* CVT_S_D32_MM */
19687 FGR32Opnd, AFGR64Opnd,
19688 /* CVT_S_D64 */
19689 FGR32Opnd, FGR64Opnd,
19690 /* CVT_S_D64_MM */
19691 FGR32Opnd, FGR64Opnd,
19692 /* CVT_S_L */
19693 FGR32Opnd, FGR64Opnd,
19694 /* CVT_S_L_MMR6 */
19695 FGR64Opnd, FGR32Opnd,
19696 /* CVT_S_PL64 */
19697 FGR32Opnd, FGR64Opnd,
19698 /* CVT_S_PU64 */
19699 FGR32Opnd, FGR64Opnd,
19700 /* CVT_S_W */
19701 FGR32Opnd, FGR32Opnd,
19702 /* CVT_S_W_MM */
19703 FGR32Opnd, FGR32Opnd,
19704 /* CVT_S_W_MMR6 */
19705 FGR32Opnd, FGR32Opnd,
19706 /* CVT_W_D32 */
19707 FGR32Opnd, AFGR64Opnd,
19708 /* CVT_W_D32_MM */
19709 FGR32Opnd, AFGR64Opnd,
19710 /* CVT_W_D64 */
19711 FGR32Opnd, FGR64Opnd,
19712 /* CVT_W_D64_MM */
19713 FGR32Opnd, FGR64Opnd,
19714 /* CVT_W_S */
19715 FGR32Opnd, FGR32Opnd,
19716 /* CVT_W_S_MM */
19717 FGR32Opnd, FGR32Opnd,
19718 /* CVT_W_S_MMR6 */
19719 FGR32Opnd, FGR32Opnd,
19720 /* C_EQ_D32 */
19721 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19722 /* C_EQ_D32_MM */
19723 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19724 /* C_EQ_D64 */
19725 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19726 /* C_EQ_D64_MM */
19727 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19728 /* C_EQ_S */
19729 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19730 /* C_EQ_S_MM */
19731 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19732 /* C_F_D32 */
19733 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19734 /* C_F_D32_MM */
19735 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19736 /* C_F_D64 */
19737 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19738 /* C_F_D64_MM */
19739 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19740 /* C_F_S */
19741 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19742 /* C_F_S_MM */
19743 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19744 /* C_LE_D32 */
19745 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19746 /* C_LE_D32_MM */
19747 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19748 /* C_LE_D64 */
19749 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19750 /* C_LE_D64_MM */
19751 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19752 /* C_LE_S */
19753 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19754 /* C_LE_S_MM */
19755 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19756 /* C_LT_D32 */
19757 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19758 /* C_LT_D32_MM */
19759 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19760 /* C_LT_D64 */
19761 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19762 /* C_LT_D64_MM */
19763 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19764 /* C_LT_S */
19765 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19766 /* C_LT_S_MM */
19767 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19768 /* C_NGE_D32 */
19769 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19770 /* C_NGE_D32_MM */
19771 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19772 /* C_NGE_D64 */
19773 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19774 /* C_NGE_D64_MM */
19775 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19776 /* C_NGE_S */
19777 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19778 /* C_NGE_S_MM */
19779 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19780 /* C_NGLE_D32 */
19781 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19782 /* C_NGLE_D32_MM */
19783 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19784 /* C_NGLE_D64 */
19785 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19786 /* C_NGLE_D64_MM */
19787 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19788 /* C_NGLE_S */
19789 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19790 /* C_NGLE_S_MM */
19791 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19792 /* C_NGL_D32 */
19793 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19794 /* C_NGL_D32_MM */
19795 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19796 /* C_NGL_D64 */
19797 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19798 /* C_NGL_D64_MM */
19799 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19800 /* C_NGL_S */
19801 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19802 /* C_NGL_S_MM */
19803 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19804 /* C_NGT_D32 */
19805 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19806 /* C_NGT_D32_MM */
19807 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19808 /* C_NGT_D64 */
19809 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19810 /* C_NGT_D64_MM */
19811 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19812 /* C_NGT_S */
19813 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19814 /* C_NGT_S_MM */
19815 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19816 /* C_OLE_D32 */
19817 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19818 /* C_OLE_D32_MM */
19819 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19820 /* C_OLE_D64 */
19821 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19822 /* C_OLE_D64_MM */
19823 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19824 /* C_OLE_S */
19825 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19826 /* C_OLE_S_MM */
19827 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19828 /* C_OLT_D32 */
19829 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19830 /* C_OLT_D32_MM */
19831 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19832 /* C_OLT_D64 */
19833 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19834 /* C_OLT_D64_MM */
19835 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19836 /* C_OLT_S */
19837 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19838 /* C_OLT_S_MM */
19839 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19840 /* C_SEQ_D32 */
19841 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19842 /* C_SEQ_D32_MM */
19843 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19844 /* C_SEQ_D64 */
19845 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19846 /* C_SEQ_D64_MM */
19847 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19848 /* C_SEQ_S */
19849 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19850 /* C_SEQ_S_MM */
19851 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19852 /* C_SF_D32 */
19853 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19854 /* C_SF_D32_MM */
19855 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19856 /* C_SF_D64 */
19857 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19858 /* C_SF_D64_MM */
19859 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19860 /* C_SF_S */
19861 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19862 /* C_SF_S_MM */
19863 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19864 /* C_UEQ_D32 */
19865 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19866 /* C_UEQ_D32_MM */
19867 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19868 /* C_UEQ_D64 */
19869 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19870 /* C_UEQ_D64_MM */
19871 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19872 /* C_UEQ_S */
19873 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19874 /* C_UEQ_S_MM */
19875 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19876 /* C_ULE_D32 */
19877 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19878 /* C_ULE_D32_MM */
19879 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19880 /* C_ULE_D64 */
19881 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19882 /* C_ULE_D64_MM */
19883 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19884 /* C_ULE_S */
19885 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19886 /* C_ULE_S_MM */
19887 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19888 /* C_ULT_D32 */
19889 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19890 /* C_ULT_D32_MM */
19891 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19892 /* C_ULT_D64 */
19893 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19894 /* C_ULT_D64_MM */
19895 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19896 /* C_ULT_S */
19897 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19898 /* C_ULT_S_MM */
19899 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19900 /* C_UN_D32 */
19901 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19902 /* C_UN_D32_MM */
19903 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd,
19904 /* C_UN_D64 */
19905 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19906 /* C_UN_D64_MM */
19907 FCCRegsOpnd, FGR64Opnd, FGR64Opnd,
19908 /* C_UN_S */
19909 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19910 /* C_UN_S_MM */
19911 FCCRegsOpnd, FGR32Opnd, FGR32Opnd,
19912 /* CmpRxRy16 */
19913 CPU16Regs, CPU16Regs,
19914 /* CmpiRxImm16 */
19915 CPU16Regs, simm16,
19916 /* CmpiRxImmX16 */
19917 CPU16Regs, simm16,
19918 /* DADD */
19919 GPR64Opnd, GPR64Opnd, GPR64Opnd,
19920 /* DADDi */
19921 GPR64Opnd, GPR64Opnd, simm16_64,
19922 /* DADDiu */
19923 GPR64Opnd, GPR64Opnd, simm16_64,
19924 /* DADDu */
19925 GPR64Opnd, GPR64Opnd, GPR64Opnd,
19926 /* DAHI */
19927 GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,
19928 /* DALIGN */
19929 GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3,
19930 /* DATI */
19931 GPR64Opnd, GPR64Opnd, uimm16_altrelaxed,
19932 /* DAUI */
19933 GPR64Opnd, GPR64Opnd, uimm16,
19934 /* DBITSWAP */
19935 GPR64Opnd, GPR64Opnd,
19936 /* DCLO */
19937 GPR64Opnd, GPR64Opnd,
19938 /* DCLO_R6 */
19939 GPR64Opnd, GPR64Opnd,
19940 /* DCLZ */
19941 GPR64Opnd, GPR64Opnd,
19942 /* DCLZ_R6 */
19943 GPR64Opnd, GPR64Opnd,
19944 /* DDIV */
19945 GPR64Opnd, GPR64Opnd, GPR64Opnd,
19946 /* DDIVU */
19947 GPR64Opnd, GPR64Opnd, GPR64Opnd,
19948 /* DERET */
19949 /* DERET_MM */
19950 /* DERET_MMR6 */
19951 /* DEXT */
19952 GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6,
19953 /* DEXT64_32 */
19954 GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,
19955 /* DEXTM */
19956 GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33,
19957 /* DEXTU */
19958 GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1,
19959 /* DI */
19960 GPR32Opnd,
19961 /* DINS */
19962 GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd,
19963 /* DINSM */
19964 GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd,
19965 /* DINSU */
19966 GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd,
19967 /* DIV */
19968 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19969 /* DIVU */
19970 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19971 /* DIVU_MMR6 */
19972 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19973 /* DIV_MMR6 */
19974 GPR32Opnd, GPR32Opnd, GPR32Opnd,
19975 /* DIV_S_B */
19976 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19977 /* DIV_S_D */
19978 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19979 /* DIV_S_H */
19980 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19981 /* DIV_S_W */
19982 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19983 /* DIV_U_B */
19984 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
19985 /* DIV_U_D */
19986 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
19987 /* DIV_U_H */
19988 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
19989 /* DIV_U_W */
19990 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
19991 /* DI_MM */
19992 GPR32Opnd,
19993 /* DI_MMR6 */
19994 GPR32Opnd,
19995 /* DLSA */
19996 GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,
19997 /* DLSA_R6 */
19998 GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1,
19999 /* DMFC0 */
20000 GPR64Opnd, COP0Opnd, uimm3,
20001 /* DMFC1 */
20002 GPR64Opnd, FGR64Opnd,
20003 /* DMFC2 */
20004 GPR64Opnd, COP2Opnd, uimm3,
20005 /* DMFC2_OCTEON */
20006 GPR64Opnd, uimm16,
20007 /* DMFGC0 */
20008 GPR64Opnd, COP0Opnd, uimm3,
20009 /* DMOD */
20010 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20011 /* DMODU */
20012 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20013 /* DMT */
20014 GPR32Opnd,
20015 /* DMTC0 */
20016 COP0Opnd, GPR64Opnd, uimm3,
20017 /* DMTC1 */
20018 FGR64Opnd, GPR64Opnd,
20019 /* DMTC2 */
20020 COP2Opnd, GPR64Opnd, uimm3,
20021 /* DMTC2_OCTEON */
20022 GPR64Opnd, uimm16,
20023 /* DMTGC0 */
20024 COP0Opnd, GPR64Opnd, uimm3,
20025 /* DMUH */
20026 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20027 /* DMUHU */
20028 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20029 /* DMUL */
20030 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20031 /* DMULT */
20032 GPR64Opnd, GPR64Opnd,
20033 /* DMULTu */
20034 GPR64Opnd, GPR64Opnd,
20035 /* DMULU */
20036 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20037 /* DMUL_R6 */
20038 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20039 /* DOTP_S_D */
20040 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20041 /* DOTP_S_H */
20042 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20043 /* DOTP_S_W */
20044 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20045 /* DOTP_U_D */
20046 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20047 /* DOTP_U_H */
20048 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20049 /* DOTP_U_W */
20050 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20051 /* DPADD_S_D */
20052 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20053 /* DPADD_S_H */
20054 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20055 /* DPADD_S_W */
20056 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20057 /* DPADD_U_D */
20058 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20059 /* DPADD_U_H */
20060 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20061 /* DPADD_U_W */
20062 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20063 /* DPAQX_SA_W_PH */
20064 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20065 /* DPAQX_SA_W_PH_MMR2 */
20066 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20067 /* DPAQX_S_W_PH */
20068 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20069 /* DPAQX_S_W_PH_MMR2 */
20070 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20071 /* DPAQ_SA_L_W */
20072 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20073 /* DPAQ_SA_L_W_MM */
20074 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20075 /* DPAQ_S_W_PH */
20076 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20077 /* DPAQ_S_W_PH_MM */
20078 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20079 /* DPAU_H_QBL */
20080 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20081 /* DPAU_H_QBL_MM */
20082 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20083 /* DPAU_H_QBR */
20084 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20085 /* DPAU_H_QBR_MM */
20086 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20087 /* DPAX_W_PH */
20088 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20089 /* DPAX_W_PH_MMR2 */
20090 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20091 /* DPA_W_PH */
20092 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20093 /* DPA_W_PH_MMR2 */
20094 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20095 /* DPOP */
20096 GPR64Opnd, GPR64Opnd,
20097 /* DPSQX_SA_W_PH */
20098 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20099 /* DPSQX_SA_W_PH_MMR2 */
20100 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20101 /* DPSQX_S_W_PH */
20102 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20103 /* DPSQX_S_W_PH_MMR2 */
20104 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20105 /* DPSQ_SA_L_W */
20106 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20107 /* DPSQ_SA_L_W_MM */
20108 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20109 /* DPSQ_S_W_PH */
20110 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20111 /* DPSQ_S_W_PH_MM */
20112 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20113 /* DPSUB_S_D */
20114 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20115 /* DPSUB_S_H */
20116 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20117 /* DPSUB_S_W */
20118 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20119 /* DPSUB_U_D */
20120 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20121 /* DPSUB_U_H */
20122 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20123 /* DPSUB_U_W */
20124 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20125 /* DPSU_H_QBL */
20126 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20127 /* DPSU_H_QBL_MM */
20128 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20129 /* DPSU_H_QBR */
20130 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20131 /* DPSU_H_QBR_MM */
20132 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20133 /* DPSX_W_PH */
20134 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20135 /* DPSX_W_PH_MMR2 */
20136 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20137 /* DPS_W_PH */
20138 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20139 /* DPS_W_PH_MMR2 */
20140 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
20141 /* DROTR */
20142 GPR64Opnd, GPR64Opnd, uimm6,
20143 /* DROTR32 */
20144 GPR64Opnd, GPR64Opnd, uimm5,
20145 /* DROTRV */
20146 GPR64Opnd, GPR64Opnd, GPR32Opnd,
20147 /* DSBH */
20148 GPR64Opnd, GPR64Opnd,
20149 /* DSDIV */
20150 GPR64Opnd, GPR64Opnd,
20151 /* DSHD */
20152 GPR64Opnd, GPR64Opnd,
20153 /* DSLL */
20154 GPR64Opnd, GPR64Opnd, uimm6,
20155 /* DSLL32 */
20156 GPR64Opnd, GPR64Opnd, uimm5,
20157 /* DSLL64_32 */
20158 GPR64, GPR32,
20159 /* DSLLV */
20160 GPR64Opnd, GPR64Opnd, GPR32Opnd,
20161 /* DSRA */
20162 GPR64Opnd, GPR64Opnd, uimm6,
20163 /* DSRA32 */
20164 GPR64Opnd, GPR64Opnd, uimm5,
20165 /* DSRAV */
20166 GPR64Opnd, GPR64Opnd, GPR32Opnd,
20167 /* DSRL */
20168 GPR64Opnd, GPR64Opnd, uimm6,
20169 /* DSRL32 */
20170 GPR64Opnd, GPR64Opnd, uimm5,
20171 /* DSRLV */
20172 GPR64Opnd, GPR64Opnd, GPR32Opnd,
20173 /* DSUB */
20174 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20175 /* DSUBu */
20176 GPR64Opnd, GPR64Opnd, GPR64Opnd,
20177 /* DUDIV */
20178 GPR64Opnd, GPR64Opnd,
20179 /* DVP */
20180 GPR32Opnd,
20181 /* DVPE */
20182 GPR32Opnd,
20183 /* DVP_MMR6 */
20184 GPR32Opnd,
20185 /* DivRxRy16 */
20186 CPU16Regs, CPU16Regs,
20187 /* DivuRxRy16 */
20188 CPU16Regs, CPU16Regs,
20189 /* EHB */
20190 /* EHB_MM */
20191 /* EHB_MMR6 */
20192 /* EI */
20193 GPR32Opnd,
20194 /* EI_MM */
20195 GPR32Opnd,
20196 /* EI_MMR6 */
20197 GPR32Opnd,
20198 /* EMT */
20199 GPR32Opnd,
20200 /* ERET */
20201 /* ERETNC */
20202 /* ERETNC_MMR6 */
20203 /* ERET_MM */
20204 /* ERET_MMR6 */
20205 /* EVP */
20206 GPR32Opnd,
20207 /* EVPE */
20208 GPR32Opnd,
20209 /* EVP_MMR6 */
20210 GPR32Opnd,
20211 /* EXT */
20212 GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,
20213 /* EXTP */
20214 GPR32Opnd, ACC64DSPOpnd, uimm5,
20215 /* EXTPDP */
20216 GPR32Opnd, ACC64DSPOpnd, uimm5,
20217 /* EXTPDPV */
20218 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20219 /* EXTPDPV_MM */
20220 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20221 /* EXTPDP_MM */
20222 GPR32Opnd, ACC64DSPOpnd, uimm5,
20223 /* EXTPV */
20224 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20225 /* EXTPV_MM */
20226 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20227 /* EXTP_MM */
20228 GPR32Opnd, ACC64DSPOpnd, uimm5,
20229 /* EXTRV_RS_W */
20230 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20231 /* EXTRV_RS_W_MM */
20232 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20233 /* EXTRV_R_W */
20234 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20235 /* EXTRV_R_W_MM */
20236 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20237 /* EXTRV_S_H */
20238 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20239 /* EXTRV_S_H_MM */
20240 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20241 /* EXTRV_W */
20242 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20243 /* EXTRV_W_MM */
20244 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd,
20245 /* EXTR_RS_W */
20246 GPR32Opnd, ACC64DSPOpnd, uimm5,
20247 /* EXTR_RS_W_MM */
20248 GPR32Opnd, ACC64DSPOpnd, uimm5,
20249 /* EXTR_R_W */
20250 GPR32Opnd, ACC64DSPOpnd, uimm5,
20251 /* EXTR_R_W_MM */
20252 GPR32Opnd, ACC64DSPOpnd, uimm5,
20253 /* EXTR_S_H */
20254 GPR32Opnd, ACC64DSPOpnd, uimm5,
20255 /* EXTR_S_H_MM */
20256 GPR32Opnd, ACC64DSPOpnd, uimm5,
20257 /* EXTR_W */
20258 GPR32Opnd, ACC64DSPOpnd, uimm5,
20259 /* EXTR_W_MM */
20260 GPR32Opnd, ACC64DSPOpnd, uimm5,
20261 /* EXTS */
20262 GPR64Opnd, GPR64Opnd, uimm5, uimm5,
20263 /* EXTS32 */
20264 GPR64Opnd, GPR64Opnd, uimm5, uimm5,
20265 /* EXT_MM */
20266 GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,
20267 /* EXT_MMR6 */
20268 GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1,
20269 /* FABS_D32 */
20270 AFGR64Opnd, AFGR64Opnd,
20271 /* FABS_D32_MM */
20272 AFGR64Opnd, AFGR64Opnd,
20273 /* FABS_D64 */
20274 FGR64Opnd, FGR64Opnd,
20275 /* FABS_D64_MM */
20276 FGR64Opnd, FGR64Opnd,
20277 /* FABS_S */
20278 FGR32Opnd, FGR32Opnd,
20279 /* FABS_S_MM */
20280 FGR32Opnd, FGR32Opnd,
20281 /* FADD_D */
20282 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20283 /* FADD_D32 */
20284 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20285 /* FADD_D32_MM */
20286 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20287 /* FADD_D64 */
20288 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20289 /* FADD_D64_MM */
20290 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20291 /* FADD_PS64 */
20292 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20293 /* FADD_S */
20294 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20295 /* FADD_S_MM */
20296 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20297 /* FADD_S_MMR6 */
20298 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20299 /* FADD_W */
20300 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20301 /* FCAF_D */
20302 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20303 /* FCAF_W */
20304 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20305 /* FCEQ_D */
20306 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20307 /* FCEQ_W */
20308 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20309 /* FCLASS_D */
20310 MSA128DOpnd, MSA128DOpnd,
20311 /* FCLASS_W */
20312 MSA128WOpnd, MSA128WOpnd,
20313 /* FCLE_D */
20314 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20315 /* FCLE_W */
20316 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20317 /* FCLT_D */
20318 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20319 /* FCLT_W */
20320 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20321 /* FCMP_D32 */
20322 AFGR64, AFGR64, condcode,
20323 /* FCMP_D32_MM */
20324 AFGR64, AFGR64, condcode,
20325 /* FCMP_D64 */
20326 FGR64, FGR64, condcode,
20327 /* FCMP_S32 */
20328 FGR32, FGR32, condcode,
20329 /* FCMP_S32_MM */
20330 FGR32, FGR32, condcode,
20331 /* FCNE_D */
20332 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20333 /* FCNE_W */
20334 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20335 /* FCOR_D */
20336 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20337 /* FCOR_W */
20338 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20339 /* FCUEQ_D */
20340 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20341 /* FCUEQ_W */
20342 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20343 /* FCULE_D */
20344 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20345 /* FCULE_W */
20346 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20347 /* FCULT_D */
20348 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20349 /* FCULT_W */
20350 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20351 /* FCUNE_D */
20352 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20353 /* FCUNE_W */
20354 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20355 /* FCUN_D */
20356 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20357 /* FCUN_W */
20358 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20359 /* FDIV_D */
20360 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20361 /* FDIV_D32 */
20362 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20363 /* FDIV_D32_MM */
20364 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20365 /* FDIV_D64 */
20366 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20367 /* FDIV_D64_MM */
20368 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20369 /* FDIV_S */
20370 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20371 /* FDIV_S_MM */
20372 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20373 /* FDIV_S_MMR6 */
20374 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20375 /* FDIV_W */
20376 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20377 /* FEXDO_H */
20378 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,
20379 /* FEXDO_W */
20380 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,
20381 /* FEXP2_D */
20382 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20383 /* FEXP2_W */
20384 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20385 /* FEXUPL_D */
20386 MSA128DOpnd, MSA128WOpnd,
20387 /* FEXUPL_W */
20388 MSA128WOpnd, MSA128HOpnd,
20389 /* FEXUPR_D */
20390 MSA128DOpnd, MSA128WOpnd,
20391 /* FEXUPR_W */
20392 MSA128WOpnd, MSA128HOpnd,
20393 /* FFINT_S_D */
20394 MSA128DOpnd, MSA128DOpnd,
20395 /* FFINT_S_W */
20396 MSA128WOpnd, MSA128WOpnd,
20397 /* FFINT_U_D */
20398 MSA128DOpnd, MSA128DOpnd,
20399 /* FFINT_U_W */
20400 MSA128WOpnd, MSA128WOpnd,
20401 /* FFQL_D */
20402 MSA128DOpnd, MSA128WOpnd,
20403 /* FFQL_W */
20404 MSA128WOpnd, MSA128HOpnd,
20405 /* FFQR_D */
20406 MSA128DOpnd, MSA128WOpnd,
20407 /* FFQR_W */
20408 MSA128WOpnd, MSA128HOpnd,
20409 /* FILL_B */
20410 MSA128BOpnd, GPR32Opnd,
20411 /* FILL_D */
20412 MSA128DOpnd, GPR64Opnd,
20413 /* FILL_H */
20414 MSA128HOpnd, GPR32Opnd,
20415 /* FILL_W */
20416 MSA128WOpnd, GPR32Opnd,
20417 /* FLOG2_D */
20418 MSA128DOpnd, MSA128DOpnd,
20419 /* FLOG2_W */
20420 MSA128WOpnd, MSA128WOpnd,
20421 /* FLOOR_L_D64 */
20422 FGR64Opnd, FGR64Opnd,
20423 /* FLOOR_L_D_MMR6 */
20424 FGR64Opnd, FGR64Opnd,
20425 /* FLOOR_L_S */
20426 FGR64Opnd, FGR32Opnd,
20427 /* FLOOR_L_S_MMR6 */
20428 FGR64Opnd, FGR32Opnd,
20429 /* FLOOR_W_D32 */
20430 FGR32Opnd, AFGR64Opnd,
20431 /* FLOOR_W_D64 */
20432 FGR32Opnd, FGR64Opnd,
20433 /* FLOOR_W_D_MMR6 */
20434 FGR32Opnd, AFGR64Opnd,
20435 /* FLOOR_W_MM */
20436 FGR32Opnd, AFGR64Opnd,
20437 /* FLOOR_W_S */
20438 FGR32Opnd, FGR32Opnd,
20439 /* FLOOR_W_S_MM */
20440 FGR32Opnd, FGR32Opnd,
20441 /* FLOOR_W_S_MMR6 */
20442 FGR32Opnd, FGR32Opnd,
20443 /* FMADD_D */
20444 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20445 /* FMADD_W */
20446 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20447 /* FMAX_A_D */
20448 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20449 /* FMAX_A_W */
20450 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20451 /* FMAX_D */
20452 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20453 /* FMAX_W */
20454 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20455 /* FMIN_A_D */
20456 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20457 /* FMIN_A_W */
20458 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20459 /* FMIN_D */
20460 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20461 /* FMIN_W */
20462 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20463 /* FMOV_D32 */
20464 AFGR64Opnd, AFGR64Opnd,
20465 /* FMOV_D32_MM */
20466 AFGR64Opnd, AFGR64Opnd,
20467 /* FMOV_D64 */
20468 FGR64Opnd, FGR64Opnd,
20469 /* FMOV_D64_MM */
20470 FGR64Opnd, FGR64Opnd,
20471 /* FMOV_D_MMR6 */
20472 FGR64Opnd, FGR64Opnd,
20473 /* FMOV_S */
20474 FGR32Opnd, FGR32Opnd,
20475 /* FMOV_S_MM */
20476 FGR32Opnd, FGR32Opnd,
20477 /* FMOV_S_MMR6 */
20478 FGR32Opnd, FGR32Opnd,
20479 /* FMSUB_D */
20480 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20481 /* FMSUB_W */
20482 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20483 /* FMUL_D */
20484 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20485 /* FMUL_D32 */
20486 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20487 /* FMUL_D32_MM */
20488 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20489 /* FMUL_D64 */
20490 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20491 /* FMUL_D64_MM */
20492 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20493 /* FMUL_PS64 */
20494 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20495 /* FMUL_S */
20496 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20497 /* FMUL_S_MM */
20498 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20499 /* FMUL_S_MMR6 */
20500 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20501 /* FMUL_W */
20502 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20503 /* FNEG_D32 */
20504 AFGR64Opnd, AFGR64Opnd,
20505 /* FNEG_D32_MM */
20506 AFGR64Opnd, AFGR64Opnd,
20507 /* FNEG_D64 */
20508 FGR64Opnd, FGR64Opnd,
20509 /* FNEG_D64_MM */
20510 FGR64Opnd, FGR64Opnd,
20511 /* FNEG_S */
20512 FGR32Opnd, FGR32Opnd,
20513 /* FNEG_S_MM */
20514 FGR32Opnd, FGR32Opnd,
20515 /* FNEG_S_MMR6 */
20516 FGR32Opnd, FGR32Opnd,
20517 /* FORK */
20518 GPR32Opnd, GPR32Opnd, GPR32Opnd,
20519 /* FRCP_D */
20520 MSA128DOpnd, MSA128DOpnd,
20521 /* FRCP_W */
20522 MSA128WOpnd, MSA128WOpnd,
20523 /* FRINT_D */
20524 MSA128DOpnd, MSA128DOpnd,
20525 /* FRINT_W */
20526 MSA128WOpnd, MSA128WOpnd,
20527 /* FRSQRT_D */
20528 MSA128DOpnd, MSA128DOpnd,
20529 /* FRSQRT_W */
20530 MSA128WOpnd, MSA128WOpnd,
20531 /* FSAF_D */
20532 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20533 /* FSAF_W */
20534 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20535 /* FSEQ_D */
20536 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20537 /* FSEQ_W */
20538 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20539 /* FSLE_D */
20540 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20541 /* FSLE_W */
20542 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20543 /* FSLT_D */
20544 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20545 /* FSLT_W */
20546 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20547 /* FSNE_D */
20548 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20549 /* FSNE_W */
20550 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20551 /* FSOR_D */
20552 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20553 /* FSOR_W */
20554 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20555 /* FSQRT_D */
20556 MSA128DOpnd, MSA128DOpnd,
20557 /* FSQRT_D32 */
20558 AFGR64Opnd, AFGR64Opnd,
20559 /* FSQRT_D32_MM */
20560 AFGR64Opnd, AFGR64Opnd,
20561 /* FSQRT_D64 */
20562 FGR64Opnd, FGR64Opnd,
20563 /* FSQRT_D64_MM */
20564 FGR64Opnd, FGR64Opnd,
20565 /* FSQRT_S */
20566 FGR32Opnd, FGR32Opnd,
20567 /* FSQRT_S_MM */
20568 FGR32Opnd, FGR32Opnd,
20569 /* FSQRT_W */
20570 MSA128WOpnd, MSA128WOpnd,
20571 /* FSUB_D */
20572 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20573 /* FSUB_D32 */
20574 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20575 /* FSUB_D32_MM */
20576 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
20577 /* FSUB_D64 */
20578 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20579 /* FSUB_D64_MM */
20580 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20581 /* FSUB_PS64 */
20582 FGR64Opnd, FGR64Opnd, FGR64Opnd,
20583 /* FSUB_S */
20584 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20585 /* FSUB_S_MM */
20586 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20587 /* FSUB_S_MMR6 */
20588 FGR32Opnd, FGR32Opnd, FGR32Opnd,
20589 /* FSUB_W */
20590 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20591 /* FSUEQ_D */
20592 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20593 /* FSUEQ_W */
20594 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20595 /* FSULE_D */
20596 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20597 /* FSULE_W */
20598 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20599 /* FSULT_D */
20600 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20601 /* FSULT_W */
20602 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20603 /* FSUNE_D */
20604 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20605 /* FSUNE_W */
20606 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20607 /* FSUN_D */
20608 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20609 /* FSUN_W */
20610 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20611 /* FTINT_S_D */
20612 MSA128DOpnd, MSA128DOpnd,
20613 /* FTINT_S_W */
20614 MSA128WOpnd, MSA128WOpnd,
20615 /* FTINT_U_D */
20616 MSA128DOpnd, MSA128DOpnd,
20617 /* FTINT_U_W */
20618 MSA128WOpnd, MSA128WOpnd,
20619 /* FTQ_H */
20620 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd,
20621 /* FTQ_W */
20622 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd,
20623 /* FTRUNC_S_D */
20624 MSA128DOpnd, MSA128DOpnd,
20625 /* FTRUNC_S_W */
20626 MSA128WOpnd, MSA128WOpnd,
20627 /* FTRUNC_U_D */
20628 MSA128DOpnd, MSA128DOpnd,
20629 /* FTRUNC_U_W */
20630 MSA128WOpnd, MSA128WOpnd,
20631 /* GINVI */
20632 GPR32Opnd,
20633 /* GINVI_MMR6 */
20634 GPR32Opnd,
20635 /* GINVT */
20636 GPR32Opnd, uimm2,
20637 /* GINVT_MMR6 */
20638 GPR32Opnd, uimm2,
20639 /* HADD_S_D */
20640 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20641 /* HADD_S_H */
20642 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20643 /* HADD_S_W */
20644 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20645 /* HADD_U_D */
20646 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20647 /* HADD_U_H */
20648 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20649 /* HADD_U_W */
20650 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20651 /* HSUB_S_D */
20652 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20653 /* HSUB_S_H */
20654 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20655 /* HSUB_S_W */
20656 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20657 /* HSUB_U_D */
20658 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd,
20659 /* HSUB_U_H */
20660 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd,
20661 /* HSUB_U_W */
20662 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd,
20663 /* HYPCALL */
20664 uimm10,
20665 /* HYPCALL_MM */
20666 uimm10,
20667 /* ILVEV_B */
20668 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20669 /* ILVEV_D */
20670 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20671 /* ILVEV_H */
20672 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20673 /* ILVEV_W */
20674 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20675 /* ILVL_B */
20676 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20677 /* ILVL_D */
20678 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20679 /* ILVL_H */
20680 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20681 /* ILVL_W */
20682 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20683 /* ILVOD_B */
20684 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20685 /* ILVOD_D */
20686 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20687 /* ILVOD_H */
20688 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20689 /* ILVOD_W */
20690 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20691 /* ILVR_B */
20692 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
20693 /* ILVR_D */
20694 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
20695 /* ILVR_H */
20696 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
20697 /* ILVR_W */
20698 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
20699 /* INS */
20700 GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,
20701 /* INSERT_B */
20702 MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4,
20703 /* INSERT_D */
20704 MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1,
20705 /* INSERT_H */
20706 MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3,
20707 /* INSERT_W */
20708 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2,
20709 /* INSV */
20710 GPR32Opnd, GPR32Opnd, GPR32Opnd,
20711 /* INSVE_B */
20712 MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz,
20713 /* INSVE_D */
20714 MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz,
20715 /* INSVE_H */
20716 MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz,
20717 /* INSVE_W */
20718 MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz,
20719 /* INSV_MM */
20720 GPR32Opnd, GPR32Opnd, GPR32Opnd,
20721 /* INS_MM */
20722 GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,
20723 /* INS_MMR6 */
20724 GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd,
20725 /* J */
20726 jmptarget,
20727 /* JAL */
20728 calltarget,
20729 /* JALR */
20730 GPR32Opnd, GPR32Opnd,
20731 /* JALR16_MM */
20732 GPR32Opnd,
20733 /* JALR64 */
20734 GPR64Opnd, GPR64Opnd,
20735 /* JALRC16_MMR6 */
20736 GPR32Opnd,
20737 /* JALRC_HB_MMR6 */
20738 GPR32Opnd, GPR32Opnd,
20739 /* JALRC_MMR6 */
20740 GPR32Opnd, GPR32Opnd,
20741 /* JALRS16_MM */
20742 GPR32Opnd,
20743 /* JALRS_MM */
20744 GPR32Opnd, GPR32Opnd,
20745 /* JALR_HB */
20746 GPR32Opnd, GPR32Opnd,
20747 /* JALR_HB64 */
20748 GPR64Opnd, GPR64Opnd,
20749 /* JALR_MM */
20750 GPR32Opnd, GPR32Opnd,
20751 /* JALS_MM */
20752 calltarget_mm,
20753 /* JALX */
20754 calltarget,
20755 /* JALX_MM */
20756 calltarget,
20757 /* JAL_MM */
20758 calltarget_mm,
20759 /* JIALC */
20760 GPR32Opnd, calloffset16,
20761 /* JIALC64 */
20762 GPR64Opnd, calloffset16,
20763 /* JIALC_MMR6 */
20764 GPR32Opnd, calloffset16,
20765 /* JIC */
20766 GPR32Opnd, jmpoffset16,
20767 /* JIC64 */
20768 GPR64Opnd, jmpoffset16,
20769 /* JIC_MMR6 */
20770 GPR32Opnd, jmpoffset16,
20771 /* JR */
20772 GPR32Opnd,
20773 /* JR16_MM */
20774 GPR32Opnd,
20775 /* JR64 */
20776 GPR64Opnd,
20777 /* JRADDIUSP */
20778 uimm5_lsl2,
20779 /* JRC16_MM */
20780 GPR32Opnd,
20781 /* JRC16_MMR6 */
20782 GPR32Opnd,
20783 /* JRCADDIUSP_MMR6 */
20784 uimm5_lsl2,
20785 /* JR_HB */
20786 GPR32Opnd,
20787 /* JR_HB64 */
20788 GPR64Opnd,
20789 /* JR_HB64_R6 */
20790 GPR64Opnd,
20791 /* JR_HB_R6 */
20792 GPR32Opnd,
20793 /* JR_MM */
20794 GPR32Opnd,
20795 /* J_MM */
20796 jmptarget_mm,
20797 /* Jal16 */
20798 uimm26,
20799 /* JalB16 */
20800 uimm26,
20801 /* JrRa16 */
20802 /* JrcRa16 */
20803 /* JrcRx16 */
20804 CPU16Regs,
20805 /* JumpLinkReg16 */
20806 CPU16Regs,
20807 /* LB */
20808 GPR32Opnd, -1, simm16,
20809 /* LB64 */
20810 GPR64Opnd, -1, simm16,
20811 /* LBE */
20812 GPR32Opnd, -1, simm9,
20813 /* LBE_MM */
20814 GPR32Opnd, -1, simm16,
20815 /* LBU16_MM */
20816 GPRMM16Opnd, -1, simm4,
20817 /* LBUX */
20818 GPR32Opnd, -1, -1,
20819 /* LBUX_MM */
20820 GPR32Opnd, -1, -1,
20821 /* LBU_MMR6 */
20822 GPR32Opnd, -1, simm16,
20823 /* LB_MM */
20824 GPR32Opnd, -1, simm16,
20825 /* LB_MMR6 */
20826 GPR32Opnd, -1, simm16,
20827 /* LBu */
20828 GPR32Opnd, -1, simm16,
20829 /* LBu64 */
20830 GPR64Opnd, -1, simm16,
20831 /* LBuE */
20832 GPR32Opnd, -1, simm9,
20833 /* LBuE_MM */
20834 GPR32Opnd, -1, simm16,
20835 /* LBu_MM */
20836 GPR32Opnd, -1, simm16,
20837 /* LD */
20838 GPR64Opnd, -1, simm16,
20839 /* LDC1 */
20840 AFGR64Opnd, -1, simm16,
20841 /* LDC164 */
20842 FGR64Opnd, -1, simm16,
20843 /* LDC1_D64_MMR6 */
20844 FGR64Opnd, -1, simm16,
20845 /* LDC1_MM_D32 */
20846 AFGR64Opnd, -1, simm16,
20847 /* LDC1_MM_D64 */
20848 FGR64Opnd, -1, simm16,
20849 /* LDC2 */
20850 COP2Opnd, -1, simm16,
20851 /* LDC2_MMR6 */
20852 COP2Opnd, GPR32, simm11,
20853 /* LDC2_R6 */
20854 COP2Opnd, -1, simm11,
20855 /* LDC3 */
20856 COP3Opnd, -1, simm16,
20857 /* LDI_B */
20858 MSA128BOpnd, vsplat_simm10,
20859 /* LDI_D */
20860 MSA128DOpnd, vsplat_simm10,
20861 /* LDI_H */
20862 MSA128HOpnd, vsplat_simm10,
20863 /* LDI_W */
20864 MSA128WOpnd, vsplat_simm10,
20865 /* LDL */
20866 GPR64Opnd, -1, simm16, GPR64Opnd,
20867 /* LDPC */
20868 GPR64Opnd, simm18_lsl3,
20869 /* LDR */
20870 GPR64Opnd, -1, simm16, GPR64Opnd,
20871 /* LDXC1 */
20872 AFGR64Opnd, -1, -1,
20873 /* LDXC164 */
20874 FGR64Opnd, -1, -1,
20875 /* LD_B */
20876 MSA128BOpnd, -1, simm10,
20877 /* LD_D */
20878 MSA128DOpnd, -1, simm10_lsl3,
20879 /* LD_H */
20880 MSA128HOpnd, -1, simm10_lsl1,
20881 /* LD_W */
20882 MSA128WOpnd, -1, simm10_lsl2,
20883 /* LEA_ADDiu */
20884 GPR32Opnd, -1, simm16,
20885 /* LEA_ADDiu64 */
20886 GPR64Opnd, -1, simm16,
20887 /* LEA_ADDiu_MM */
20888 GPR32Opnd, -1, simm16,
20889 /* LH */
20890 GPR32Opnd, -1, simm16,
20891 /* LH64 */
20892 GPR64Opnd, -1, simm16,
20893 /* LHE */
20894 GPR32Opnd, -1, simm9,
20895 /* LHE_MM */
20896 GPR32Opnd, -1, simm9,
20897 /* LHU16_MM */
20898 GPRMM16Opnd, -1, simm4,
20899 /* LHX */
20900 GPR32Opnd, -1, -1,
20901 /* LHX_MM */
20902 GPR32Opnd, -1, -1,
20903 /* LH_MM */
20904 GPR32Opnd, -1, simm16,
20905 /* LHu */
20906 GPR32Opnd, -1, simm16,
20907 /* LHu64 */
20908 GPR64Opnd, -1, simm16,
20909 /* LHuE */
20910 GPR32Opnd, -1, simm9,
20911 /* LHuE_MM */
20912 GPR32Opnd, -1, simm9,
20913 /* LHu_MM */
20914 GPR32Opnd, -1, simm16,
20915 /* LI16_MM */
20916 GPRMM16Opnd, li16_imm,
20917 /* LI16_MMR6 */
20918 GPRMM16Opnd, li16_imm,
20919 /* LL */
20920 GPR32Opnd, -1, simm16,
20921 /* LL64 */
20922 GPR32Opnd, -1, simm16,
20923 /* LL64_R6 */
20924 GPR32Opnd, -1, simm9,
20925 /* LLD */
20926 GPR64Opnd, -1, simm16,
20927 /* LLD_R6 */
20928 GPR64Opnd, -1, simm9,
20929 /* LLE */
20930 GPR32Opnd, -1, simm9,
20931 /* LLE_MM */
20932 GPR32Opnd, -1, simm9,
20933 /* LL_MM */
20934 GPR32Opnd, -1, simm12,
20935 /* LL_MMR6 */
20936 GPR32Opnd, -1, simm9,
20937 /* LL_R6 */
20938 GPR32Opnd, -1, simm9,
20939 /* LSA */
20940 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,
20941 /* LSA_MMR6 */
20942 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,
20943 /* LSA_R6 */
20944 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1,
20945 /* LUI_MMR6 */
20946 GPR32Opnd, uimm16,
20947 /* LUXC1 */
20948 AFGR64Opnd, -1, -1,
20949 /* LUXC164 */
20950 FGR64Opnd, -1, -1,
20951 /* LUXC1_MM */
20952 FGR64Opnd, -1, -1,
20953 /* LUi */
20954 GPR32Opnd, uimm16_relaxed,
20955 /* LUi64 */
20956 GPR64Opnd, uimm16_64_relaxed,
20957 /* LUi_MM */
20958 GPR32Opnd, uimm16_relaxed,
20959 /* LW */
20960 GPR32Opnd, -1, simm16,
20961 /* LW16_MM */
20962 GPRMM16Opnd, -1, simm4,
20963 /* LW64 */
20964 GPR64Opnd, -1, simm16,
20965 /* LWC1 */
20966 FGR32Opnd, -1, simm16,
20967 /* LWC1_MM */
20968 FGR32Opnd, -1, simm16,
20969 /* LWC2 */
20970 COP2Opnd, -1, simm16,
20971 /* LWC2_MMR6 */
20972 COP2Opnd, GPR32, simm11,
20973 /* LWC2_R6 */
20974 COP2Opnd, -1, simm11,
20975 /* LWC3 */
20976 COP3Opnd, -1, simm16,
20977 /* LWDSP */
20978 DSPROpnd, -1, simm16,
20979 /* LWDSP_MM */
20980 DSPROpnd, -1, simm16,
20981 /* LWE */
20982 GPR32Opnd, -1, simm9,
20983 /* LWE_MM */
20984 GPR32Opnd, -1, simm9,
20985 /* LWGP_MM */
20986 GPRMM16Opnd, -1, simm7_lsl2,
20987 /* LWL */
20988 GPR32Opnd, -1, simm16, GPR32Opnd,
20989 /* LWL64 */
20990 GPR64Opnd, -1, simm16, GPR64Opnd,
20991 /* LWLE */
20992 GPR32Opnd, -1, simm9, GPR32Opnd,
20993 /* LWLE_MM */
20994 GPR32Opnd, -1, simm9, GPR32Opnd,
20995 /* LWL_MM */
20996 GPR32Opnd, -1, simm12, GPR32Opnd,
20997 /* LWM16_MM */
20998 reglist16, -1, uimm8,
20999 /* LWM16_MMR6 */
21000 reglist16, -1, uimm8,
21001 /* LWM32_MM */
21002 reglist, -1, simm12,
21003 /* LWPC */
21004 GPR32Opnd, simm19_lsl2,
21005 /* LWPC_MMR6 */
21006 GPR32Opnd, simm19_lsl2,
21007 /* LWP_MM */
21008 GPR32Opnd, GPR32Opnd, -1, simm12,
21009 /* LWR */
21010 GPR32Opnd, -1, simm16, GPR32Opnd,
21011 /* LWR64 */
21012 GPR64Opnd, -1, simm16, GPR64Opnd,
21013 /* LWRE */
21014 GPR32Opnd, -1, simm9, GPR32Opnd,
21015 /* LWRE_MM */
21016 GPR32Opnd, -1, simm9, GPR32Opnd,
21017 /* LWR_MM */
21018 GPR32Opnd, -1, simm12, GPR32Opnd,
21019 /* LWSP_MM */
21020 GPR32Opnd, -1, simm5,
21021 /* LWUPC */
21022 GPR32Opnd, simm19_lsl2,
21023 /* LWU_MM */
21024 GPR32Opnd, -1, simm12,
21025 /* LWX */
21026 GPR32Opnd, -1, -1,
21027 /* LWXC1 */
21028 FGR32Opnd, -1, -1,
21029 /* LWXC1_MM */
21030 FGR32Opnd, -1, -1,
21031 /* LWXS_MM */
21032 GPR32Opnd, -1, -1,
21033 /* LWX_MM */
21034 GPR32Opnd, -1, -1,
21035 /* LW_MM */
21036 GPR32Opnd, -1, simm16,
21037 /* LW_MMR6 */
21038 GPR32Opnd, -1, simm16,
21039 /* LWu */
21040 GPR64Opnd, -1, simm16,
21041 /* LbRxRyOffMemX16 */
21042 CPU16Regs, CPU16Regs, simm16,
21043 /* LbuRxRyOffMemX16 */
21044 CPU16Regs, CPU16Regs, simm16,
21045 /* LhRxRyOffMemX16 */
21046 CPU16Regs, CPU16Regs, simm16,
21047 /* LhuRxRyOffMemX16 */
21048 CPU16Regs, CPU16Regs, simm16,
21049 /* LiRxImm16 */
21050 CPU16Regs, simm16,
21051 /* LiRxImmAlignX16 */
21052 CPU16Regs, simm16,
21053 /* LiRxImmX16 */
21054 CPU16Regs, simm16,
21055 /* LwRxPcTcp16 */
21056 CPU16Regs, pcrel16, i32imm,
21057 /* LwRxPcTcpX16 */
21058 CPU16Regs, pcrel16, i32imm,
21059 /* LwRxRyOffMemX16 */
21060 CPU16Regs, CPU16Regs, simm16,
21061 /* LwRxSpImmX16 */
21062 CPU16Regs, CPU16RegsPlusSP, simm16,
21063 /* MADD */
21064 GPR32Opnd, GPR32Opnd,
21065 /* MADDF_D */
21066 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21067 /* MADDF_D_MMR6 */
21068 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21069 /* MADDF_S */
21070 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21071 /* MADDF_S_MMR6 */
21072 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21073 /* MADDR_Q_H */
21074 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21075 /* MADDR_Q_W */
21076 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21077 /* MADDU */
21078 GPR32Opnd, GPR32Opnd,
21079 /* MADDU_DSP */
21080 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21081 /* MADDU_DSP_MM */
21082 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21083 /* MADDU_MM */
21084 GPR32Opnd, GPR32Opnd,
21085 /* MADDV_B */
21086 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21087 /* MADDV_D */
21088 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21089 /* MADDV_H */
21090 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21091 /* MADDV_W */
21092 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21093 /* MADD_D32 */
21094 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21095 /* MADD_D32_MM */
21096 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21097 /* MADD_D64 */
21098 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21099 /* MADD_DSP */
21100 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21101 /* MADD_DSP_MM */
21102 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21103 /* MADD_MM */
21104 GPR32Opnd, GPR32Opnd,
21105 /* MADD_Q_H */
21106 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21107 /* MADD_Q_W */
21108 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21109 /* MADD_S */
21110 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21111 /* MADD_S_MM */
21112 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21113 /* MAQ_SA_W_PHL */
21114 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21115 /* MAQ_SA_W_PHL_MM */
21116 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21117 /* MAQ_SA_W_PHR */
21118 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21119 /* MAQ_SA_W_PHR_MM */
21120 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21121 /* MAQ_S_W_PHL */
21122 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21123 /* MAQ_S_W_PHL_MM */
21124 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21125 /* MAQ_S_W_PHR */
21126 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21127 /* MAQ_S_W_PHR_MM */
21128 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21129 /* MAXA_D */
21130 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21131 /* MAXA_D_MMR6 */
21132 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21133 /* MAXA_S */
21134 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21135 /* MAXA_S_MMR6 */
21136 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21137 /* MAXI_S_B */
21138 MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
21139 /* MAXI_S_D */
21140 MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
21141 /* MAXI_S_H */
21142 MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
21143 /* MAXI_S_W */
21144 MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
21145 /* MAXI_U_B */
21146 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
21147 /* MAXI_U_D */
21148 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
21149 /* MAXI_U_H */
21150 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
21151 /* MAXI_U_W */
21152 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
21153 /* MAX_A_B */
21154 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21155 /* MAX_A_D */
21156 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21157 /* MAX_A_H */
21158 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21159 /* MAX_A_W */
21160 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21161 /* MAX_D */
21162 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21163 /* MAX_D_MMR6 */
21164 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21165 /* MAX_S */
21166 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21167 /* MAX_S_B */
21168 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21169 /* MAX_S_D */
21170 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21171 /* MAX_S_H */
21172 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21173 /* MAX_S_MMR6 */
21174 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21175 /* MAX_S_W */
21176 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21177 /* MAX_U_B */
21178 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21179 /* MAX_U_D */
21180 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21181 /* MAX_U_H */
21182 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21183 /* MAX_U_W */
21184 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21185 /* MFC0 */
21186 GPR32Opnd, COP0Opnd, uimm3,
21187 /* MFC0_MMR6 */
21188 GPR32Opnd, COP0Opnd, uimm3,
21189 /* MFC1 */
21190 GPR32Opnd, FGR32Opnd,
21191 /* MFC1_D64 */
21192 GPR32Opnd, FGR64Opnd,
21193 /* MFC1_MM */
21194 GPR32Opnd, FGR32Opnd,
21195 /* MFC1_MMR6 */
21196 GPR32Opnd, FGR32Opnd,
21197 /* MFC2 */
21198 GPR32Opnd, COP2Opnd, uimm3,
21199 /* MFC2_MMR6 */
21200 GPR32Opnd, COP2Opnd,
21201 /* MFGC0 */
21202 GPR32Opnd, COP0Opnd, uimm3,
21203 /* MFGC0_MM */
21204 GPR32Opnd, COP0Opnd, uimm3,
21205 /* MFHC0_MMR6 */
21206 GPR32Opnd, COP0Opnd, uimm3,
21207 /* MFHC1_D32 */
21208 GPR32Opnd, AFGR64Opnd,
21209 /* MFHC1_D32_MM */
21210 GPR32Opnd, AFGR64Opnd,
21211 /* MFHC1_D64 */
21212 GPR32Opnd, FGR64Opnd,
21213 /* MFHC1_D64_MM */
21214 GPR32Opnd, FGR64Opnd,
21215 /* MFHC2_MMR6 */
21216 GPR32Opnd, COP2Opnd,
21217 /* MFHGC0 */
21218 GPR32Opnd, COP0Opnd, uimm3,
21219 /* MFHGC0_MM */
21220 GPR32Opnd, COP0Opnd, uimm3,
21221 /* MFHI */
21222 GPR32Opnd,
21223 /* MFHI16_MM */
21224 GPR32Opnd,
21225 /* MFHI64 */
21226 GPR64Opnd,
21227 /* MFHI_DSP */
21228 GPR32Opnd, ACC64DSPOpnd,
21229 /* MFHI_DSP_MM */
21230 GPR32Opnd, ACC64DSPOpnd,
21231 /* MFHI_MM */
21232 GPR32Opnd,
21233 /* MFLO */
21234 GPR32Opnd,
21235 /* MFLO16_MM */
21236 GPR32Opnd,
21237 /* MFLO64 */
21238 GPR64Opnd,
21239 /* MFLO_DSP */
21240 GPR32Opnd, ACC64DSPOpnd,
21241 /* MFLO_DSP_MM */
21242 GPR32Opnd, ACC64DSPOpnd,
21243 /* MFLO_MM */
21244 GPR32Opnd,
21245 /* MFTR */
21246 GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,
21247 /* MINA_D */
21248 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21249 /* MINA_D_MMR6 */
21250 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21251 /* MINA_S */
21252 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21253 /* MINA_S_MMR6 */
21254 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21255 /* MINI_S_B */
21256 MSA128BOpnd, MSA128BOpnd, vsplat_simm5,
21257 /* MINI_S_D */
21258 MSA128DOpnd, MSA128DOpnd, vsplat_simm5,
21259 /* MINI_S_H */
21260 MSA128HOpnd, MSA128HOpnd, vsplat_simm5,
21261 /* MINI_S_W */
21262 MSA128WOpnd, MSA128WOpnd, vsplat_simm5,
21263 /* MINI_U_B */
21264 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
21265 /* MINI_U_D */
21266 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
21267 /* MINI_U_H */
21268 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
21269 /* MINI_U_W */
21270 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
21271 /* MIN_A_B */
21272 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21273 /* MIN_A_D */
21274 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21275 /* MIN_A_H */
21276 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21277 /* MIN_A_W */
21278 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21279 /* MIN_D */
21280 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21281 /* MIN_D_MMR6 */
21282 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21283 /* MIN_S */
21284 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21285 /* MIN_S_B */
21286 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21287 /* MIN_S_D */
21288 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21289 /* MIN_S_H */
21290 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21291 /* MIN_S_MMR6 */
21292 FGR32Opnd, FGR32Opnd, FGR32Opnd,
21293 /* MIN_S_W */
21294 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21295 /* MIN_U_B */
21296 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21297 /* MIN_U_D */
21298 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21299 /* MIN_U_H */
21300 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21301 /* MIN_U_W */
21302 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21303 /* MOD */
21304 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21305 /* MODSUB */
21306 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21307 /* MODSUB_MM */
21308 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21309 /* MODU */
21310 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21311 /* MODU_MMR6 */
21312 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21313 /* MOD_MMR6 */
21314 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21315 /* MOD_S_B */
21316 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21317 /* MOD_S_D */
21318 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21319 /* MOD_S_H */
21320 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21321 /* MOD_S_W */
21322 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21323 /* MOD_U_B */
21324 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21325 /* MOD_U_D */
21326 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21327 /* MOD_U_H */
21328 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21329 /* MOD_U_W */
21330 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21331 /* MOVE16_MM */
21332 GPR32Opnd, GPR32Opnd,
21333 /* MOVE16_MMR6 */
21334 GPR32Opnd, GPR32Opnd,
21335 /* MOVEP_MM */
21336 GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,
21337 /* MOVEP_MMR6 */
21338 GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP,
21339 /* MOVE_V */
21340 MSA128BOpnd, MSA128BOpnd,
21341 /* MOVF_D32 */
21342 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21343 /* MOVF_D32_MM */
21344 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21345 /* MOVF_D64 */
21346 FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,
21347 /* MOVF_I */
21348 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21349 /* MOVF_I64 */
21350 GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,
21351 /* MOVF_I_MM */
21352 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21353 /* MOVF_S */
21354 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21355 /* MOVF_S_MM */
21356 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21357 /* MOVN_I64_D64 */
21358 FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,
21359 /* MOVN_I64_I */
21360 GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,
21361 /* MOVN_I64_I64 */
21362 GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,
21363 /* MOVN_I64_S */
21364 FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,
21365 /* MOVN_I_D32 */
21366 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21367 /* MOVN_I_D32_MM */
21368 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21369 /* MOVN_I_D64 */
21370 FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,
21371 /* MOVN_I_I */
21372 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21373 /* MOVN_I_I64 */
21374 GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,
21375 /* MOVN_I_MM */
21376 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21377 /* MOVN_I_S */
21378 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21379 /* MOVN_I_S_MM */
21380 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21381 /* MOVT_D32 */
21382 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21383 /* MOVT_D32_MM */
21384 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd,
21385 /* MOVT_D64 */
21386 FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd,
21387 /* MOVT_I */
21388 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21389 /* MOVT_I64 */
21390 GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd,
21391 /* MOVT_I_MM */
21392 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd,
21393 /* MOVT_S */
21394 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21395 /* MOVT_S_MM */
21396 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd,
21397 /* MOVZ_I64_D64 */
21398 FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd,
21399 /* MOVZ_I64_I */
21400 GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd,
21401 /* MOVZ_I64_I64 */
21402 GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd,
21403 /* MOVZ_I64_S */
21404 FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd,
21405 /* MOVZ_I_D32 */
21406 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21407 /* MOVZ_I_D32_MM */
21408 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd,
21409 /* MOVZ_I_D64 */
21410 FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd,
21411 /* MOVZ_I_I */
21412 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21413 /* MOVZ_I_I64 */
21414 GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd,
21415 /* MOVZ_I_MM */
21416 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd,
21417 /* MOVZ_I_S */
21418 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21419 /* MOVZ_I_S_MM */
21420 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd,
21421 /* MSUB */
21422 GPR32Opnd, GPR32Opnd,
21423 /* MSUBF_D */
21424 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21425 /* MSUBF_D_MMR6 */
21426 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21427 /* MSUBF_S */
21428 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21429 /* MSUBF_S_MMR6 */
21430 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21431 /* MSUBR_Q_H */
21432 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21433 /* MSUBR_Q_W */
21434 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21435 /* MSUBU */
21436 GPR32Opnd, GPR32Opnd,
21437 /* MSUBU_DSP */
21438 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21439 /* MSUBU_DSP_MM */
21440 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21441 /* MSUBU_MM */
21442 GPR32Opnd, GPR32Opnd,
21443 /* MSUBV_B */
21444 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21445 /* MSUBV_D */
21446 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21447 /* MSUBV_H */
21448 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21449 /* MSUBV_W */
21450 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21451 /* MSUB_D32 */
21452 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21453 /* MSUB_D32_MM */
21454 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21455 /* MSUB_D64 */
21456 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21457 /* MSUB_DSP */
21458 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21459 /* MSUB_DSP_MM */
21460 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21461 /* MSUB_MM */
21462 GPR32Opnd, GPR32Opnd,
21463 /* MSUB_Q_H */
21464 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21465 /* MSUB_Q_W */
21466 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21467 /* MSUB_S */
21468 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21469 /* MSUB_S_MM */
21470 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21471 /* MTC0 */
21472 COP0Opnd, GPR32Opnd, uimm3,
21473 /* MTC0_MMR6 */
21474 COP0Opnd, GPR32Opnd, uimm3,
21475 /* MTC1 */
21476 FGR32Opnd, GPR32Opnd,
21477 /* MTC1_D64 */
21478 FGR64Opnd, GPR32Opnd,
21479 /* MTC1_D64_MM */
21480 FGR64Opnd, GPR32Opnd,
21481 /* MTC1_MM */
21482 FGR32Opnd, GPR32Opnd,
21483 /* MTC1_MMR6 */
21484 FGR32Opnd, GPR32Opnd,
21485 /* MTC2 */
21486 COP2Opnd, GPR32Opnd, uimm3,
21487 /* MTC2_MMR6 */
21488 COP2Opnd, GPR32Opnd,
21489 /* MTGC0 */
21490 COP0Opnd, GPR32Opnd, uimm3,
21491 /* MTGC0_MM */
21492 COP0Opnd, GPR32Opnd, uimm3,
21493 /* MTHC0_MMR6 */
21494 COP0Opnd, GPR32Opnd, uimm3,
21495 /* MTHC1_D32 */
21496 AFGR64Opnd, AFGR64Opnd, GPR32Opnd,
21497 /* MTHC1_D32_MM */
21498 AFGR64Opnd, AFGR64Opnd, GPR32Opnd,
21499 /* MTHC1_D64 */
21500 FGR64Opnd, FGR64Opnd, GPR32Opnd,
21501 /* MTHC1_D64_MM */
21502 FGR64Opnd, FGR64Opnd, GPR32Opnd,
21503 /* MTHC2_MMR6 */
21504 COP2Opnd, GPR32Opnd,
21505 /* MTHGC0 */
21506 COP0Opnd, GPR32Opnd, uimm3,
21507 /* MTHGC0_MM */
21508 COP0Opnd, GPR32Opnd, uimm3,
21509 /* MTHI */
21510 GPR32Opnd,
21511 /* MTHI64 */
21512 GPR64Opnd,
21513 /* MTHI_DSP */
21514 HI32DSPOpnd, GPR32Opnd,
21515 /* MTHI_DSP_MM */
21516 HI32DSPOpnd, GPR32Opnd,
21517 /* MTHI_MM */
21518 GPR32Opnd,
21519 /* MTHLIP */
21520 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
21521 /* MTHLIP_MM */
21522 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
21523 /* MTLO */
21524 GPR32Opnd,
21525 /* MTLO64 */
21526 GPR64Opnd,
21527 /* MTLO_DSP */
21528 LO32DSPOpnd, GPR32Opnd,
21529 /* MTLO_DSP_MM */
21530 LO32DSPOpnd, GPR32Opnd,
21531 /* MTLO_MM */
21532 GPR32Opnd,
21533 /* MTM0 */
21534 GPR64Opnd,
21535 /* MTM1 */
21536 GPR64Opnd,
21537 /* MTM2 */
21538 GPR64Opnd,
21539 /* MTP0 */
21540 GPR64Opnd,
21541 /* MTP1 */
21542 GPR64Opnd,
21543 /* MTP2 */
21544 GPR64Opnd,
21545 /* MTTR */
21546 GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1,
21547 /* MUH */
21548 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21549 /* MUHU */
21550 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21551 /* MUHU_MMR6 */
21552 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21553 /* MUH_MMR6 */
21554 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21555 /* MUL */
21556 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21557 /* MULEQ_S_W_PHL */
21558 GPR32Opnd, DSPROpnd, DSPROpnd,
21559 /* MULEQ_S_W_PHL_MM */
21560 GPR32Opnd, DSPROpnd, DSPROpnd,
21561 /* MULEQ_S_W_PHR */
21562 GPR32Opnd, DSPROpnd, DSPROpnd,
21563 /* MULEQ_S_W_PHR_MM */
21564 GPR32Opnd, DSPROpnd, DSPROpnd,
21565 /* MULEU_S_PH_QBL */
21566 DSPROpnd, DSPROpnd, DSPROpnd,
21567 /* MULEU_S_PH_QBL_MM */
21568 DSPROpnd, DSPROpnd, DSPROpnd,
21569 /* MULEU_S_PH_QBR */
21570 DSPROpnd, DSPROpnd, DSPROpnd,
21571 /* MULEU_S_PH_QBR_MM */
21572 DSPROpnd, DSPROpnd, DSPROpnd,
21573 /* MULQ_RS_PH */
21574 DSPROpnd, DSPROpnd, DSPROpnd,
21575 /* MULQ_RS_PH_MM */
21576 DSPROpnd, DSPROpnd, DSPROpnd,
21577 /* MULQ_RS_W */
21578 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21579 /* MULQ_RS_W_MMR2 */
21580 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21581 /* MULQ_S_PH */
21582 DSPROpnd, DSPROpnd, DSPROpnd,
21583 /* MULQ_S_PH_MMR2 */
21584 DSPROpnd, DSPROpnd, DSPROpnd,
21585 /* MULQ_S_W */
21586 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21587 /* MULQ_S_W_MMR2 */
21588 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21589 /* MULR_PS64 */
21590 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21591 /* MULR_Q_H */
21592 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21593 /* MULR_Q_W */
21594 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21595 /* MULSAQ_S_W_PH */
21596 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21597 /* MULSAQ_S_W_PH_MM */
21598 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21599 /* MULSA_W_PH */
21600 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21601 /* MULSA_W_PH_MMR2 */
21602 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd,
21603 /* MULT */
21604 GPR32Opnd, GPR32Opnd,
21605 /* MULTU_DSP */
21606 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21607 /* MULTU_DSP_MM */
21608 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21609 /* MULT_DSP */
21610 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21611 /* MULT_DSP_MM */
21612 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd,
21613 /* MULT_MM */
21614 GPR32Opnd, GPR32Opnd,
21615 /* MULTu */
21616 GPR32Opnd, GPR32Opnd,
21617 /* MULTu_MM */
21618 GPR32Opnd, GPR32Opnd,
21619 /* MULU */
21620 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21621 /* MULU_MMR6 */
21622 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21623 /* MULV_B */
21624 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21625 /* MULV_D */
21626 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21627 /* MULV_H */
21628 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21629 /* MULV_W */
21630 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21631 /* MUL_MM */
21632 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21633 /* MUL_MMR6 */
21634 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21635 /* MUL_PH */
21636 DSPROpnd, DSPROpnd, DSPROpnd,
21637 /* MUL_PH_MMR2 */
21638 DSPROpnd, DSPROpnd, DSPROpnd,
21639 /* MUL_Q_H */
21640 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21641 /* MUL_Q_W */
21642 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21643 /* MUL_R6 */
21644 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21645 /* MUL_S_PH */
21646 DSPROpnd, DSPROpnd, DSPROpnd,
21647 /* MUL_S_PH_MMR2 */
21648 DSPROpnd, DSPROpnd, DSPROpnd,
21649 /* Mfhi16 */
21650 CPU16Regs,
21651 /* Mflo16 */
21652 CPU16Regs,
21653 /* Move32R16 */
21654 GPR32, CPU16Regs,
21655 /* MoveR3216 */
21656 CPU16Regs, GPR32,
21657 /* NAL */
21658 /* NLOC_B */
21659 MSA128BOpnd, MSA128BOpnd,
21660 /* NLOC_D */
21661 MSA128DOpnd, MSA128DOpnd,
21662 /* NLOC_H */
21663 MSA128HOpnd, MSA128HOpnd,
21664 /* NLOC_W */
21665 MSA128WOpnd, MSA128WOpnd,
21666 /* NLZC_B */
21667 MSA128BOpnd, MSA128BOpnd,
21668 /* NLZC_D */
21669 MSA128DOpnd, MSA128DOpnd,
21670 /* NLZC_H */
21671 MSA128HOpnd, MSA128HOpnd,
21672 /* NLZC_W */
21673 MSA128WOpnd, MSA128WOpnd,
21674 /* NMADD_D32 */
21675 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21676 /* NMADD_D32_MM */
21677 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21678 /* NMADD_D64 */
21679 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21680 /* NMADD_S */
21681 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21682 /* NMADD_S_MM */
21683 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21684 /* NMSUB_D32 */
21685 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21686 /* NMSUB_D32_MM */
21687 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd,
21688 /* NMSUB_D64 */
21689 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
21690 /* NMSUB_S */
21691 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21692 /* NMSUB_S_MM */
21693 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd,
21694 /* NOR */
21695 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21696 /* NOR64 */
21697 GPR64Opnd, GPR64Opnd, GPR64Opnd,
21698 /* NORI_B */
21699 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
21700 /* NOR_MM */
21701 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21702 /* NOR_MMR6 */
21703 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21704 /* NOR_V */
21705 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21706 /* NOT16_MM */
21707 GPRMM16Opnd, GPRMM16Opnd,
21708 /* NOT16_MMR6 */
21709 GPRMM16Opnd, GPRMM16Opnd,
21710 /* NegRxRy16 */
21711 CPU16Regs, CPU16Regs,
21712 /* NotRxRy16 */
21713 CPU16Regs, CPU16Regs,
21714 /* OR */
21715 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21716 /* OR16_MM */
21717 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
21718 /* OR16_MMR6 */
21719 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
21720 /* OR64 */
21721 GPR64Opnd, GPR64Opnd, GPR64Opnd,
21722 /* ORI_B */
21723 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
21724 /* ORI_MMR6 */
21725 GPR32Opnd, GPR32Opnd, uimm16,
21726 /* OR_MM */
21727 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21728 /* OR_MMR6 */
21729 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21730 /* OR_V */
21731 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21732 /* ORi */
21733 GPR32Opnd, GPR32Opnd, uimm16,
21734 /* ORi64 */
21735 GPR64Opnd, GPR64Opnd, uimm16_64,
21736 /* ORi_MM */
21737 GPR32Opnd, GPR32Opnd, uimm16,
21738 /* OrRxRxRy16 */
21739 CPU16Regs, CPU16Regs, CPU16Regs,
21740 /* PACKRL_PH */
21741 DSPROpnd, DSPROpnd, DSPROpnd,
21742 /* PACKRL_PH_MM */
21743 DSPROpnd, DSPROpnd, DSPROpnd,
21744 /* PAUSE */
21745 /* PAUSE_MM */
21746 /* PAUSE_MMR6 */
21747 /* PCKEV_B */
21748 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21749 /* PCKEV_D */
21750 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21751 /* PCKEV_H */
21752 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21753 /* PCKEV_W */
21754 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21755 /* PCKOD_B */
21756 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
21757 /* PCKOD_D */
21758 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
21759 /* PCKOD_H */
21760 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
21761 /* PCKOD_W */
21762 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
21763 /* PCNT_B */
21764 MSA128BOpnd, MSA128BOpnd,
21765 /* PCNT_D */
21766 MSA128DOpnd, MSA128DOpnd,
21767 /* PCNT_H */
21768 MSA128HOpnd, MSA128HOpnd,
21769 /* PCNT_W */
21770 MSA128WOpnd, MSA128WOpnd,
21771 /* PICK_PH */
21772 DSPROpnd, DSPROpnd, DSPROpnd,
21773 /* PICK_PH_MM */
21774 DSPROpnd, DSPROpnd, DSPROpnd,
21775 /* PICK_QB */
21776 DSPROpnd, DSPROpnd, DSPROpnd,
21777 /* PICK_QB_MM */
21778 DSPROpnd, DSPROpnd, DSPROpnd,
21779 /* PLL_PS64 */
21780 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21781 /* PLU_PS64 */
21782 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21783 /* POP */
21784 GPR32Opnd, GPR32Opnd,
21785 /* PRECEQU_PH_QBL */
21786 DSPROpnd, DSPROpnd,
21787 /* PRECEQU_PH_QBLA */
21788 DSPROpnd, DSPROpnd,
21789 /* PRECEQU_PH_QBLA_MM */
21790 DSPROpnd, DSPROpnd,
21791 /* PRECEQU_PH_QBL_MM */
21792 DSPROpnd, DSPROpnd,
21793 /* PRECEQU_PH_QBR */
21794 DSPROpnd, DSPROpnd,
21795 /* PRECEQU_PH_QBRA */
21796 DSPROpnd, DSPROpnd,
21797 /* PRECEQU_PH_QBRA_MM */
21798 DSPROpnd, DSPROpnd,
21799 /* PRECEQU_PH_QBR_MM */
21800 DSPROpnd, DSPROpnd,
21801 /* PRECEQ_W_PHL */
21802 GPR32Opnd, DSPROpnd,
21803 /* PRECEQ_W_PHL_MM */
21804 GPR32Opnd, DSPROpnd,
21805 /* PRECEQ_W_PHR */
21806 GPR32Opnd, DSPROpnd,
21807 /* PRECEQ_W_PHR_MM */
21808 GPR32Opnd, DSPROpnd,
21809 /* PRECEU_PH_QBL */
21810 DSPROpnd, DSPROpnd,
21811 /* PRECEU_PH_QBLA */
21812 DSPROpnd, DSPROpnd,
21813 /* PRECEU_PH_QBLA_MM */
21814 DSPROpnd, DSPROpnd,
21815 /* PRECEU_PH_QBL_MM */
21816 DSPROpnd, DSPROpnd,
21817 /* PRECEU_PH_QBR */
21818 DSPROpnd, DSPROpnd,
21819 /* PRECEU_PH_QBRA */
21820 DSPROpnd, DSPROpnd,
21821 /* PRECEU_PH_QBRA_MM */
21822 DSPROpnd, DSPROpnd,
21823 /* PRECEU_PH_QBR_MM */
21824 DSPROpnd, DSPROpnd,
21825 /* PRECRQU_S_QB_PH */
21826 DSPROpnd, DSPROpnd, DSPROpnd,
21827 /* PRECRQU_S_QB_PH_MM */
21828 DSPROpnd, DSPROpnd, DSPROpnd,
21829 /* PRECRQ_PH_W */
21830 DSPROpnd, GPR32Opnd, GPR32Opnd,
21831 /* PRECRQ_PH_W_MM */
21832 DSPROpnd, GPR32Opnd, GPR32Opnd,
21833 /* PRECRQ_QB_PH */
21834 DSPROpnd, DSPROpnd, DSPROpnd,
21835 /* PRECRQ_QB_PH_MM */
21836 DSPROpnd, DSPROpnd, DSPROpnd,
21837 /* PRECRQ_RS_PH_W */
21838 DSPROpnd, GPR32Opnd, GPR32Opnd,
21839 /* PRECRQ_RS_PH_W_MM */
21840 DSPROpnd, GPR32Opnd, GPR32Opnd,
21841 /* PRECR_QB_PH */
21842 DSPROpnd, DSPROpnd, DSPROpnd,
21843 /* PRECR_QB_PH_MMR2 */
21844 DSPROpnd, DSPROpnd, DSPROpnd,
21845 /* PRECR_SRA_PH_W */
21846 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21847 /* PRECR_SRA_PH_W_MMR2 */
21848 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21849 /* PRECR_SRA_R_PH_W */
21850 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21851 /* PRECR_SRA_R_PH_W_MMR2 */
21852 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd,
21853 /* PREF */
21854 -1, simm16, uimm5,
21855 /* PREFE */
21856 -1, simm9, uimm5,
21857 /* PREFE_MM */
21858 -1, simm9, uimm5,
21859 /* PREFX_MM */
21860 -1, -1, uimm5,
21861 /* PREF_MM */
21862 -1, simm12, uimm5,
21863 /* PREF_MMR6 */
21864 -1, simm12, uimm5,
21865 /* PREF_R6 */
21866 -1, simm9, uimm5,
21867 /* PREPEND */
21868 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
21869 /* PREPEND_MMR2 */
21870 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd,
21871 /* PUL_PS64 */
21872 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21873 /* PUU_PS64 */
21874 FGR64Opnd, FGR64Opnd, FGR64Opnd,
21875 /* RADDU_W_QB */
21876 GPR32Opnd, DSPROpnd,
21877 /* RADDU_W_QB_MM */
21878 GPR32Opnd, DSPROpnd,
21879 /* RDDSP */
21880 GPR32Opnd, uimm10,
21881 /* RDDSP_MM */
21882 GPR32Opnd, uimm7,
21883 /* RDHWR */
21884 GPR32Opnd, HWRegsOpnd, uimm8,
21885 /* RDHWR64 */
21886 GPR64Opnd, HWRegsOpnd, uimm8,
21887 /* RDHWR_MM */
21888 GPR32Opnd, HWRegsOpnd, uimm8,
21889 /* RDHWR_MMR6 */
21890 GPR32Opnd, HWRegsOpnd, uimm3,
21891 /* RDPGPR_MMR6 */
21892 GPR32Opnd, GPR32Opnd,
21893 /* RECIP_D32 */
21894 AFGR64Opnd, AFGR64Opnd,
21895 /* RECIP_D32_MM */
21896 AFGR64Opnd, AFGR64Opnd,
21897 /* RECIP_D64 */
21898 FGR64Opnd, FGR64Opnd,
21899 /* RECIP_D64_MM */
21900 FGR64Opnd, FGR64Opnd,
21901 /* RECIP_S */
21902 FGR32Opnd, FGR32Opnd,
21903 /* RECIP_S_MM */
21904 FGR32Opnd, FGR32Opnd,
21905 /* REPLV_PH */
21906 DSPROpnd, GPR32Opnd,
21907 /* REPLV_PH_MM */
21908 DSPROpnd, GPR32Opnd,
21909 /* REPLV_QB */
21910 DSPROpnd, GPR32Opnd,
21911 /* REPLV_QB_MM */
21912 DSPROpnd, GPR32Opnd,
21913 /* REPL_PH */
21914 DSPROpnd, simm10,
21915 /* REPL_PH_MM */
21916 DSPROpnd, simm10,
21917 /* REPL_QB */
21918 DSPROpnd, uimm8,
21919 /* REPL_QB_MM */
21920 DSPROpnd, uimm8,
21921 /* RINT_D */
21922 FGR64Opnd, FGR64Opnd,
21923 /* RINT_D_MMR6 */
21924 FGR64Opnd, FGR64Opnd,
21925 /* RINT_S */
21926 FGR32Opnd, FGR32Opnd,
21927 /* RINT_S_MMR6 */
21928 FGR32Opnd, FGR32Opnd,
21929 /* ROTR */
21930 GPR32Opnd, GPR32Opnd, uimm5,
21931 /* ROTRV */
21932 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21933 /* ROTRV_MM */
21934 GPR32Opnd, GPR32Opnd, GPR32Opnd,
21935 /* ROTR_MM */
21936 GPR32Opnd, GPR32Opnd, uimm5,
21937 /* ROUND_L_D64 */
21938 FGR64Opnd, FGR64Opnd,
21939 /* ROUND_L_D_MMR6 */
21940 FGR64Opnd, FGR64Opnd,
21941 /* ROUND_L_S */
21942 FGR64Opnd, FGR32Opnd,
21943 /* ROUND_L_S_MMR6 */
21944 FGR64Opnd, FGR32Opnd,
21945 /* ROUND_W_D32 */
21946 FGR32Opnd, AFGR64Opnd,
21947 /* ROUND_W_D64 */
21948 FGR32Opnd, FGR64Opnd,
21949 /* ROUND_W_D_MMR6 */
21950 FGR64Opnd, FGR64Opnd,
21951 /* ROUND_W_MM */
21952 FGR32Opnd, AFGR64Opnd,
21953 /* ROUND_W_S */
21954 FGR32Opnd, FGR32Opnd,
21955 /* ROUND_W_S_MM */
21956 FGR32Opnd, FGR32Opnd,
21957 /* ROUND_W_S_MMR6 */
21958 FGR32Opnd, FGR32Opnd,
21959 /* RSQRT_D32 */
21960 AFGR64Opnd, AFGR64Opnd,
21961 /* RSQRT_D32_MM */
21962 AFGR64Opnd, AFGR64Opnd,
21963 /* RSQRT_D64 */
21964 FGR64Opnd, FGR64Opnd,
21965 /* RSQRT_D64_MM */
21966 FGR64Opnd, FGR64Opnd,
21967 /* RSQRT_S */
21968 FGR32Opnd, FGR32Opnd,
21969 /* RSQRT_S_MM */
21970 FGR32Opnd, FGR32Opnd,
21971 /* Restore16 */
21972 /* RestoreX16 */
21973 /* SAA */
21974 GPR64Opnd, GPR64Opnd,
21975 /* SAAD */
21976 GPR64Opnd, GPR64Opnd,
21977 /* SAT_S_B */
21978 MSA128BOpnd, MSA128BOpnd, uimm3,
21979 /* SAT_S_D */
21980 MSA128DOpnd, MSA128DOpnd, uimm6,
21981 /* SAT_S_H */
21982 MSA128HOpnd, MSA128HOpnd, uimm4,
21983 /* SAT_S_W */
21984 MSA128WOpnd, MSA128WOpnd, uimm5,
21985 /* SAT_U_B */
21986 MSA128BOpnd, MSA128BOpnd, uimm3,
21987 /* SAT_U_D */
21988 MSA128DOpnd, MSA128DOpnd, uimm6,
21989 /* SAT_U_H */
21990 MSA128HOpnd, MSA128HOpnd, uimm4,
21991 /* SAT_U_W */
21992 MSA128WOpnd, MSA128WOpnd, uimm5,
21993 /* SB */
21994 GPR32Opnd, -1, simm16,
21995 /* SB16_MM */
21996 GPRMM16OpndZero, -1, simm4,
21997 /* SB16_MMR6 */
21998 GPRMM16OpndZero, -1, simm4,
21999 /* SB64 */
22000 GPR64Opnd, -1, simm16,
22001 /* SBE */
22002 GPR32Opnd, -1, simm9,
22003 /* SBE_MM */
22004 GPR32Opnd, -1, simm9,
22005 /* SB_MM */
22006 GPR32Opnd, -1, simm16,
22007 /* SB_MMR6 */
22008 GPR32Opnd, -1, simm16,
22009 /* SC */
22010 GPR32Opnd, GPR32Opnd, -1, simm16,
22011 /* SC64 */
22012 GPR32Opnd, GPR32Opnd, -1, simm16,
22013 /* SC64_R6 */
22014 GPR32Opnd, GPR32Opnd, -1, simm9,
22015 /* SCD */
22016 GPR64Opnd, GPR64Opnd, -1, simm16,
22017 /* SCD_R6 */
22018 GPR64Opnd, GPR64Opnd, -1, simm9,
22019 /* SCE */
22020 GPR32Opnd, GPR32Opnd, -1, simm9,
22021 /* SCE_MM */
22022 GPR32Opnd, GPR32Opnd, -1, simm9,
22023 /* SC_MM */
22024 GPR32Opnd, GPR32Opnd, -1, simm12,
22025 /* SC_MMR6 */
22026 GPR32Opnd, GPR32Opnd, -1, simm9,
22027 /* SC_R6 */
22028 GPR32Opnd, GPR32Opnd, -1, simm9,
22029 /* SD */
22030 GPR64Opnd, -1, simm16,
22031 /* SDBBP */
22032 uimm20,
22033 /* SDBBP16_MM */
22034 uimm4,
22035 /* SDBBP16_MMR6 */
22036 uimm4,
22037 /* SDBBP_MM */
22038 uimm10,
22039 /* SDBBP_MMR6 */
22040 uimm20,
22041 /* SDBBP_R6 */
22042 uimm20,
22043 /* SDC1 */
22044 AFGR64Opnd, -1, simm16,
22045 /* SDC164 */
22046 FGR64Opnd, -1, simm16,
22047 /* SDC1_D64_MMR6 */
22048 FGR64Opnd, -1, simm16,
22049 /* SDC1_MM_D32 */
22050 AFGR64Opnd, -1, simm16,
22051 /* SDC1_MM_D64 */
22052 FGR64Opnd, -1, simm16,
22053 /* SDC2 */
22054 COP2Opnd, -1, simm16,
22055 /* SDC2_MMR6 */
22056 COP2Opnd, GPR32, simm11,
22057 /* SDC2_R6 */
22058 COP2Opnd, -1, simm11,
22059 /* SDC3 */
22060 COP3Opnd, -1, simm16,
22061 /* SDIV */
22062 GPR32Opnd, GPR32Opnd,
22063 /* SDIV_MM */
22064 GPR32Opnd, GPR32Opnd,
22065 /* SDL */
22066 GPR64Opnd, -1, simm16,
22067 /* SDR */
22068 GPR64Opnd, -1, simm16,
22069 /* SDXC1 */
22070 AFGR64Opnd, -1, -1,
22071 /* SDXC164 */
22072 FGR64Opnd, -1, -1,
22073 /* SEB */
22074 GPR32Opnd, GPR32Opnd,
22075 /* SEB64 */
22076 GPR64Opnd, GPR64Opnd,
22077 /* SEB_MM */
22078 GPR32Opnd, GPR32Opnd,
22079 /* SEH */
22080 GPR32Opnd, GPR32Opnd,
22081 /* SEH64 */
22082 GPR64Opnd, GPR64Opnd,
22083 /* SEH_MM */
22084 GPR32Opnd, GPR32Opnd,
22085 /* SELEQZ */
22086 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22087 /* SELEQZ64 */
22088 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22089 /* SELEQZ_D */
22090 FGR64Opnd, FGR64Opnd, FGR64Opnd,
22091 /* SELEQZ_D_MMR6 */
22092 FGR64Opnd, FGR64Opnd, FGR64Opnd,
22093 /* SELEQZ_MMR6 */
22094 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22095 /* SELEQZ_S */
22096 FGR32Opnd, FGR32Opnd, FGR32Opnd,
22097 /* SELEQZ_S_MMR6 */
22098 FGR32Opnd, FGR32Opnd, FGR32Opnd,
22099 /* SELNEZ */
22100 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22101 /* SELNEZ64 */
22102 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22103 /* SELNEZ_D */
22104 FGR64Opnd, FGR64Opnd, FGR64Opnd,
22105 /* SELNEZ_D_MMR6 */
22106 FGR64Opnd, FGR64Opnd, FGR64Opnd,
22107 /* SELNEZ_MMR6 */
22108 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22109 /* SELNEZ_S */
22110 FGR32Opnd, FGR32Opnd, FGR32Opnd,
22111 /* SELNEZ_S_MMR6 */
22112 FGR32Opnd, FGR32Opnd, FGR32Opnd,
22113 /* SEL_D */
22114 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
22115 /* SEL_D_MMR6 */
22116 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd,
22117 /* SEL_S */
22118 FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,
22119 /* SEL_S_MMR6 */
22120 FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd,
22121 /* SEQ */
22122 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22123 /* SEQi */
22124 GPR64Opnd, GPR64Opnd, simm10_64,
22125 /* SH */
22126 GPR32Opnd, -1, simm16,
22127 /* SH16_MM */
22128 GPRMM16OpndZero, -1, simm4,
22129 /* SH16_MMR6 */
22130 GPRMM16OpndZero, -1, simm4,
22131 /* SH64 */
22132 GPR64Opnd, -1, simm16,
22133 /* SHE */
22134 GPR32Opnd, -1, simm9,
22135 /* SHE_MM */
22136 GPR32Opnd, -1, simm9,
22137 /* SHF_B */
22138 MSA128BOpnd, MSA128BOpnd, uimm8,
22139 /* SHF_H */
22140 MSA128HOpnd, MSA128HOpnd, uimm8,
22141 /* SHF_W */
22142 MSA128WOpnd, MSA128WOpnd, uimm8,
22143 /* SHILO */
22144 ACC64DSPOpnd, simm6, ACC64DSPOpnd,
22145 /* SHILOV */
22146 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
22147 /* SHILOV_MM */
22148 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd,
22149 /* SHILO_MM */
22150 ACC64DSPOpnd, simm6, ACC64DSPOpnd,
22151 /* SHLLV_PH */
22152 DSPROpnd, DSPROpnd, GPR32Opnd,
22153 /* SHLLV_PH_MM */
22154 DSPROpnd, DSPROpnd, GPR32Opnd,
22155 /* SHLLV_QB */
22156 DSPROpnd, DSPROpnd, GPR32Opnd,
22157 /* SHLLV_QB_MM */
22158 DSPROpnd, DSPROpnd, GPR32Opnd,
22159 /* SHLLV_S_PH */
22160 DSPROpnd, DSPROpnd, GPR32Opnd,
22161 /* SHLLV_S_PH_MM */
22162 DSPROpnd, DSPROpnd, GPR32Opnd,
22163 /* SHLLV_S_W */
22164 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22165 /* SHLLV_S_W_MM */
22166 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22167 /* SHLL_PH */
22168 DSPROpnd, DSPROpnd, uimm4,
22169 /* SHLL_PH_MM */
22170 DSPROpnd, DSPROpnd, uimm4,
22171 /* SHLL_QB */
22172 DSPROpnd, DSPROpnd, uimm3,
22173 /* SHLL_QB_MM */
22174 DSPROpnd, DSPROpnd, uimm3,
22175 /* SHLL_S_PH */
22176 DSPROpnd, DSPROpnd, uimm4,
22177 /* SHLL_S_PH_MM */
22178 DSPROpnd, DSPROpnd, uimm4,
22179 /* SHLL_S_W */
22180 GPR32Opnd, GPR32Opnd, uimm5,
22181 /* SHLL_S_W_MM */
22182 GPR32Opnd, GPR32Opnd, uimm5,
22183 /* SHRAV_PH */
22184 DSPROpnd, DSPROpnd, GPR32Opnd,
22185 /* SHRAV_PH_MM */
22186 DSPROpnd, DSPROpnd, GPR32Opnd,
22187 /* SHRAV_QB */
22188 DSPROpnd, DSPROpnd, GPR32Opnd,
22189 /* SHRAV_QB_MMR2 */
22190 DSPROpnd, DSPROpnd, GPR32Opnd,
22191 /* SHRAV_R_PH */
22192 DSPROpnd, DSPROpnd, GPR32Opnd,
22193 /* SHRAV_R_PH_MM */
22194 DSPROpnd, DSPROpnd, GPR32Opnd,
22195 /* SHRAV_R_QB */
22196 DSPROpnd, DSPROpnd, GPR32Opnd,
22197 /* SHRAV_R_QB_MMR2 */
22198 DSPROpnd, DSPROpnd, GPR32Opnd,
22199 /* SHRAV_R_W */
22200 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22201 /* SHRAV_R_W_MM */
22202 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22203 /* SHRA_PH */
22204 DSPROpnd, DSPROpnd, uimm4,
22205 /* SHRA_PH_MM */
22206 DSPROpnd, DSPROpnd, uimm4,
22207 /* SHRA_QB */
22208 DSPROpnd, DSPROpnd, uimm3,
22209 /* SHRA_QB_MMR2 */
22210 DSPROpnd, DSPROpnd, uimm3,
22211 /* SHRA_R_PH */
22212 DSPROpnd, DSPROpnd, uimm4,
22213 /* SHRA_R_PH_MM */
22214 DSPROpnd, DSPROpnd, uimm4,
22215 /* SHRA_R_QB */
22216 DSPROpnd, DSPROpnd, uimm3,
22217 /* SHRA_R_QB_MMR2 */
22218 DSPROpnd, DSPROpnd, uimm3,
22219 /* SHRA_R_W */
22220 GPR32Opnd, GPR32Opnd, uimm5,
22221 /* SHRA_R_W_MM */
22222 GPR32Opnd, GPR32Opnd, uimm5,
22223 /* SHRLV_PH */
22224 DSPROpnd, DSPROpnd, GPR32Opnd,
22225 /* SHRLV_PH_MMR2 */
22226 DSPROpnd, DSPROpnd, GPR32Opnd,
22227 /* SHRLV_QB */
22228 DSPROpnd, DSPROpnd, GPR32Opnd,
22229 /* SHRLV_QB_MM */
22230 DSPROpnd, DSPROpnd, GPR32Opnd,
22231 /* SHRL_PH */
22232 DSPROpnd, DSPROpnd, uimm4,
22233 /* SHRL_PH_MMR2 */
22234 DSPROpnd, DSPROpnd, uimm4,
22235 /* SHRL_QB */
22236 DSPROpnd, DSPROpnd, uimm3,
22237 /* SHRL_QB_MM */
22238 DSPROpnd, DSPROpnd, uimm3,
22239 /* SH_MM */
22240 GPR32Opnd, -1, simm16,
22241 /* SH_MMR6 */
22242 GPR32Opnd, -1, simm16,
22243 /* SIGRIE */
22244 uimm16,
22245 /* SIGRIE_MMR6 */
22246 uimm16,
22247 /* SLDI_B */
22248 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4,
22249 /* SLDI_D */
22250 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1,
22251 /* SLDI_H */
22252 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3,
22253 /* SLDI_W */
22254 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2,
22255 /* SLD_B */
22256 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd,
22257 /* SLD_D */
22258 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd,
22259 /* SLD_H */
22260 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd,
22261 /* SLD_W */
22262 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd,
22263 /* SLL */
22264 GPR32Opnd, GPR32Opnd, uimm5,
22265 /* SLL16_MM */
22266 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
22267 /* SLL16_MMR6 */
22268 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
22269 /* SLL64_32 */
22270 GPR64, GPR32,
22271 /* SLL64_64 */
22272 GPR64, GPR64,
22273 /* SLLI_B */
22274 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
22275 /* SLLI_D */
22276 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
22277 /* SLLI_H */
22278 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
22279 /* SLLI_W */
22280 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22281 /* SLLV */
22282 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22283 /* SLLV_MM */
22284 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22285 /* SLL_B */
22286 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22287 /* SLL_D */
22288 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22289 /* SLL_H */
22290 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22291 /* SLL_MM */
22292 GPR32Opnd, GPR32Opnd, uimm5,
22293 /* SLL_MMR6 */
22294 GPR32Opnd, GPR32Opnd, uimm5,
22295 /* SLL_W */
22296 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22297 /* SLT */
22298 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22299 /* SLT64 */
22300 GPR32Opnd, GPR64Opnd, GPR64Opnd,
22301 /* SLT_MM */
22302 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22303 /* SLTi */
22304 GPR32Opnd, GPR32Opnd, simm16,
22305 /* SLTi64 */
22306 GPR32Opnd, GPR64Opnd, simm16_64,
22307 /* SLTi_MM */
22308 GPR32Opnd, GPR32Opnd, simm16,
22309 /* SLTiu */
22310 GPR32Opnd, GPR32Opnd, simm16,
22311 /* SLTiu64 */
22312 GPR32Opnd, GPR64Opnd, simm16_64,
22313 /* SLTiu_MM */
22314 GPR32Opnd, GPR32Opnd, simm16,
22315 /* SLTu */
22316 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22317 /* SLTu64 */
22318 GPR32Opnd, GPR64Opnd, GPR64Opnd,
22319 /* SLTu_MM */
22320 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22321 /* SNE */
22322 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22323 /* SNEi */
22324 GPR64Opnd, GPR64Opnd, simm10_64,
22325 /* SPLATI_B */
22326 MSA128BOpnd, MSA128BOpnd, vsplat_uimm4,
22327 /* SPLATI_D */
22328 MSA128DOpnd, MSA128DOpnd, vsplat_uimm1,
22329 /* SPLATI_H */
22330 MSA128HOpnd, MSA128HOpnd, vsplat_uimm3,
22331 /* SPLATI_W */
22332 MSA128WOpnd, MSA128WOpnd, vsplat_uimm2,
22333 /* SPLAT_B */
22334 MSA128BOpnd, MSA128BOpnd, GPR32Opnd,
22335 /* SPLAT_D */
22336 MSA128DOpnd, MSA128DOpnd, GPR32Opnd,
22337 /* SPLAT_H */
22338 MSA128HOpnd, MSA128HOpnd, GPR32Opnd,
22339 /* SPLAT_W */
22340 MSA128WOpnd, MSA128WOpnd, GPR32Opnd,
22341 /* SRA */
22342 GPR32Opnd, GPR32Opnd, uimm5,
22343 /* SRAI_B */
22344 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
22345 /* SRAI_D */
22346 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
22347 /* SRAI_H */
22348 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
22349 /* SRAI_W */
22350 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22351 /* SRARI_B */
22352 MSA128BOpnd, MSA128BOpnd, uimm3,
22353 /* SRARI_D */
22354 MSA128DOpnd, MSA128DOpnd, uimm6,
22355 /* SRARI_H */
22356 MSA128HOpnd, MSA128HOpnd, uimm4,
22357 /* SRARI_W */
22358 MSA128WOpnd, MSA128WOpnd, uimm5,
22359 /* SRAR_B */
22360 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22361 /* SRAR_D */
22362 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22363 /* SRAR_H */
22364 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22365 /* SRAR_W */
22366 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22367 /* SRAV */
22368 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22369 /* SRAV_MM */
22370 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22371 /* SRA_B */
22372 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22373 /* SRA_D */
22374 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22375 /* SRA_H */
22376 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22377 /* SRA_MM */
22378 GPR32Opnd, GPR32Opnd, uimm5,
22379 /* SRA_W */
22380 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22381 /* SRL */
22382 GPR32Opnd, GPR32Opnd, uimm5,
22383 /* SRL16_MM */
22384 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
22385 /* SRL16_MMR6 */
22386 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift,
22387 /* SRLI_B */
22388 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3,
22389 /* SRLI_D */
22390 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6,
22391 /* SRLI_H */
22392 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4,
22393 /* SRLI_W */
22394 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22395 /* SRLRI_B */
22396 MSA128BOpnd, MSA128BOpnd, uimm3,
22397 /* SRLRI_D */
22398 MSA128DOpnd, MSA128DOpnd, uimm6,
22399 /* SRLRI_H */
22400 MSA128HOpnd, MSA128HOpnd, uimm4,
22401 /* SRLRI_W */
22402 MSA128WOpnd, MSA128WOpnd, uimm5,
22403 /* SRLR_B */
22404 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22405 /* SRLR_D */
22406 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22407 /* SRLR_H */
22408 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22409 /* SRLR_W */
22410 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22411 /* SRLV */
22412 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22413 /* SRLV_MM */
22414 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22415 /* SRL_B */
22416 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22417 /* SRL_D */
22418 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22419 /* SRL_H */
22420 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22421 /* SRL_MM */
22422 GPR32Opnd, GPR32Opnd, uimm5,
22423 /* SRL_W */
22424 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22425 /* SSNOP */
22426 /* SSNOP_MM */
22427 /* SSNOP_MMR6 */
22428 /* ST_B */
22429 MSA128BOpnd, -1, simm10,
22430 /* ST_D */
22431 MSA128DOpnd, -1, simm10_lsl3,
22432 /* ST_H */
22433 MSA128HOpnd, -1, simm10_lsl1,
22434 /* ST_W */
22435 MSA128WOpnd, -1, simm10_lsl2,
22436 /* SUB */
22437 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22438 /* SUBQH_PH */
22439 DSPROpnd, DSPROpnd, DSPROpnd,
22440 /* SUBQH_PH_MMR2 */
22441 DSPROpnd, DSPROpnd, DSPROpnd,
22442 /* SUBQH_R_PH */
22443 DSPROpnd, DSPROpnd, DSPROpnd,
22444 /* SUBQH_R_PH_MMR2 */
22445 DSPROpnd, DSPROpnd, DSPROpnd,
22446 /* SUBQH_R_W */
22447 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22448 /* SUBQH_R_W_MMR2 */
22449 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22450 /* SUBQH_W */
22451 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22452 /* SUBQH_W_MMR2 */
22453 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22454 /* SUBQ_PH */
22455 DSPROpnd, DSPROpnd, DSPROpnd,
22456 /* SUBQ_PH_MM */
22457 DSPROpnd, DSPROpnd, DSPROpnd,
22458 /* SUBQ_S_PH */
22459 DSPROpnd, DSPROpnd, DSPROpnd,
22460 /* SUBQ_S_PH_MM */
22461 DSPROpnd, DSPROpnd, DSPROpnd,
22462 /* SUBQ_S_W */
22463 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22464 /* SUBQ_S_W_MM */
22465 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22466 /* SUBSUS_U_B */
22467 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22468 /* SUBSUS_U_D */
22469 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22470 /* SUBSUS_U_H */
22471 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22472 /* SUBSUS_U_W */
22473 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22474 /* SUBSUU_S_B */
22475 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22476 /* SUBSUU_S_D */
22477 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22478 /* SUBSUU_S_H */
22479 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22480 /* SUBSUU_S_W */
22481 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22482 /* SUBS_S_B */
22483 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22484 /* SUBS_S_D */
22485 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22486 /* SUBS_S_H */
22487 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22488 /* SUBS_S_W */
22489 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22490 /* SUBS_U_B */
22491 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22492 /* SUBS_U_D */
22493 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22494 /* SUBS_U_H */
22495 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22496 /* SUBS_U_W */
22497 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22498 /* SUBU16_MM */
22499 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22500 /* SUBU16_MMR6 */
22501 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22502 /* SUBUH_QB */
22503 DSPROpnd, DSPROpnd, DSPROpnd,
22504 /* SUBUH_QB_MMR2 */
22505 DSPROpnd, DSPROpnd, DSPROpnd,
22506 /* SUBUH_R_QB */
22507 DSPROpnd, DSPROpnd, DSPROpnd,
22508 /* SUBUH_R_QB_MMR2 */
22509 DSPROpnd, DSPROpnd, DSPROpnd,
22510 /* SUBU_MMR6 */
22511 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22512 /* SUBU_PH */
22513 DSPROpnd, DSPROpnd, DSPROpnd,
22514 /* SUBU_PH_MMR2 */
22515 DSPROpnd, DSPROpnd, DSPROpnd,
22516 /* SUBU_QB */
22517 DSPROpnd, DSPROpnd, DSPROpnd,
22518 /* SUBU_QB_MM */
22519 DSPROpnd, DSPROpnd, DSPROpnd,
22520 /* SUBU_S_PH */
22521 DSPROpnd, DSPROpnd, DSPROpnd,
22522 /* SUBU_S_PH_MMR2 */
22523 DSPROpnd, DSPROpnd, DSPROpnd,
22524 /* SUBU_S_QB */
22525 DSPROpnd, DSPROpnd, DSPROpnd,
22526 /* SUBU_S_QB_MM */
22527 DSPROpnd, DSPROpnd, DSPROpnd,
22528 /* SUBVI_B */
22529 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5,
22530 /* SUBVI_D */
22531 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5,
22532 /* SUBVI_H */
22533 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5,
22534 /* SUBVI_W */
22535 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5,
22536 /* SUBV_B */
22537 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22538 /* SUBV_D */
22539 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22540 /* SUBV_H */
22541 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22542 /* SUBV_W */
22543 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22544 /* SUB_MM */
22545 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22546 /* SUB_MMR6 */
22547 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22548 /* SUBu */
22549 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22550 /* SUBu_MM */
22551 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22552 /* SUXC1 */
22553 AFGR64Opnd, -1, -1,
22554 /* SUXC164 */
22555 FGR64Opnd, -1, -1,
22556 /* SUXC1_MM */
22557 FGR64Opnd, -1, -1,
22558 /* SW */
22559 GPR32Opnd, -1, simm16,
22560 /* SW16_MM */
22561 GPRMM16OpndZero, -1, simm4,
22562 /* SW16_MMR6 */
22563 GPRMM16OpndZero, -1, simm4,
22564 /* SW64 */
22565 GPR64Opnd, -1, simm16,
22566 /* SWC1 */
22567 FGR32Opnd, -1, simm16,
22568 /* SWC1_MM */
22569 FGR32Opnd, -1, simm16,
22570 /* SWC2 */
22571 COP2Opnd, -1, simm16,
22572 /* SWC2_MMR6 */
22573 COP2Opnd, GPR32, simm11,
22574 /* SWC2_R6 */
22575 COP2Opnd, -1, simm11,
22576 /* SWC3 */
22577 COP3Opnd, -1, simm16,
22578 /* SWDSP */
22579 DSPROpnd, -1, simm16,
22580 /* SWDSP_MM */
22581 DSPROpnd, -1, simm16,
22582 /* SWE */
22583 GPR32Opnd, -1, simm9,
22584 /* SWE_MM */
22585 GPR32Opnd, -1, simm9,
22586 /* SWL */
22587 GPR32Opnd, -1, simm16,
22588 /* SWL64 */
22589 GPR64Opnd, -1, simm16,
22590 /* SWLE */
22591 GPR32Opnd, -1, simm9,
22592 /* SWLE_MM */
22593 GPR32Opnd, -1, simm9,
22594 /* SWL_MM */
22595 GPR32Opnd, -1, simm12,
22596 /* SWM16_MM */
22597 reglist16, -1, uimm8,
22598 /* SWM16_MMR6 */
22599 reglist16, -1, uimm8,
22600 /* SWM32_MM */
22601 reglist, -1, simm12,
22602 /* SWP_MM */
22603 GPR32Opnd, GPR32Opnd, -1, simm12,
22604 /* SWR */
22605 GPR32Opnd, -1, simm16,
22606 /* SWR64 */
22607 GPR64Opnd, -1, simm16,
22608 /* SWRE */
22609 GPR32Opnd, -1, simm9,
22610 /* SWRE_MM */
22611 GPR32Opnd, -1, simm9,
22612 /* SWR_MM */
22613 GPR32Opnd, -1, simm12,
22614 /* SWSP_MM */
22615 GPR32Opnd, -1, simm5,
22616 /* SWSP_MMR6 */
22617 GPR32Opnd, -1, simm5,
22618 /* SWXC1 */
22619 FGR32Opnd, -1, -1,
22620 /* SWXC1_MM */
22621 FGR32Opnd, -1, -1,
22622 /* SW_MM */
22623 GPR32Opnd, -1, simm16,
22624 /* SW_MMR6 */
22625 GPR32Opnd, -1, simm16,
22626 /* SYNC */
22627 uimm5,
22628 /* SYNCI */
22629 -1, simm16,
22630 /* SYNCI_MM */
22631 -1, simm16,
22632 /* SYNCI_MMR6 */
22633 -1, simm16,
22634 /* SYNC_MM */
22635 uimm5,
22636 /* SYNC_MMR6 */
22637 uimm5,
22638 /* SYSCALL */
22639 uimm20,
22640 /* SYSCALL_MM */
22641 uimm10,
22642 /* Save16 */
22643 /* SaveX16 */
22644 /* SbRxRyOffMemX16 */
22645 CPU16Regs, CPU16Regs, simm16,
22646 /* SebRx16 */
22647 CPU16Regs, CPU16Regs,
22648 /* SehRx16 */
22649 CPU16Regs, CPU16Regs,
22650 /* ShRxRyOffMemX16 */
22651 CPU16Regs, CPU16Regs, simm16,
22652 /* SllX16 */
22653 CPU16Regs, CPU16Regs, uimm5,
22654 /* SllvRxRy16 */
22655 CPU16Regs, CPU16Regs, CPU16Regs,
22656 /* SltRxRy16 */
22657 CPU16Regs, CPU16Regs,
22658 /* SltiRxImm16 */
22659 CPU16Regs, simm16,
22660 /* SltiRxImmX16 */
22661 CPU16Regs, simm16,
22662 /* SltiuRxImm16 */
22663 CPU16Regs, simm16,
22664 /* SltiuRxImmX16 */
22665 CPU16Regs, simm16,
22666 /* SltuRxRy16 */
22667 CPU16Regs, CPU16Regs,
22668 /* SraX16 */
22669 CPU16Regs, CPU16Regs, uimm5,
22670 /* SravRxRy16 */
22671 CPU16Regs, CPU16Regs, CPU16Regs,
22672 /* SrlX16 */
22673 CPU16Regs, CPU16Regs, uimm5,
22674 /* SrlvRxRy16 */
22675 CPU16Regs, CPU16Regs, CPU16Regs,
22676 /* SubuRxRyRz16 */
22677 CPU16Regs, CPU16Regs, CPU16Regs,
22678 /* SwRxRyOffMemX16 */
22679 CPU16Regs, CPU16Regs, simm16,
22680 /* SwRxSpImmX16 */
22681 CPU16Regs, CPU16RegsPlusSP, simm16,
22682 /* TEQ */
22683 GPR32Opnd, GPR32Opnd, uimm10,
22684 /* TEQI */
22685 GPR32Opnd, simm16,
22686 /* TEQI_MM */
22687 GPR32Opnd, simm16,
22688 /* TEQ_MM */
22689 GPR32Opnd, GPR32Opnd, uimm4,
22690 /* TGE */
22691 GPR32Opnd, GPR32Opnd, uimm10,
22692 /* TGEI */
22693 GPR32Opnd, simm16,
22694 /* TGEIU */
22695 GPR32Opnd, simm16,
22696 /* TGEIU_MM */
22697 GPR32Opnd, simm16,
22698 /* TGEI_MM */
22699 GPR32Opnd, simm16,
22700 /* TGEU */
22701 GPR32Opnd, GPR32Opnd, uimm10,
22702 /* TGEU_MM */
22703 GPR32Opnd, GPR32Opnd, uimm4,
22704 /* TGE_MM */
22705 GPR32Opnd, GPR32Opnd, uimm4,
22706 /* TLBGINV */
22707 /* TLBGINVF */
22708 /* TLBGINVF_MM */
22709 /* TLBGINV_MM */
22710 /* TLBGP */
22711 /* TLBGP_MM */
22712 /* TLBGR */
22713 /* TLBGR_MM */
22714 /* TLBGWI */
22715 /* TLBGWI_MM */
22716 /* TLBGWR */
22717 /* TLBGWR_MM */
22718 /* TLBINV */
22719 /* TLBINVF */
22720 /* TLBINVF_MMR6 */
22721 /* TLBINV_MMR6 */
22722 /* TLBP */
22723 /* TLBP_MM */
22724 /* TLBR */
22725 /* TLBR_MM */
22726 /* TLBWI */
22727 /* TLBWI_MM */
22728 /* TLBWR */
22729 /* TLBWR_MM */
22730 /* TLT */
22731 GPR32Opnd, GPR32Opnd, uimm10,
22732 /* TLTI */
22733 GPR32Opnd, simm16,
22734 /* TLTIU_MM */
22735 GPR32Opnd, simm16,
22736 /* TLTI_MM */
22737 GPR32Opnd, simm16,
22738 /* TLTU */
22739 GPR32Opnd, GPR32Opnd, uimm10,
22740 /* TLTU_MM */
22741 GPR32Opnd, GPR32Opnd, uimm4,
22742 /* TLT_MM */
22743 GPR32Opnd, GPR32Opnd, uimm4,
22744 /* TNE */
22745 GPR32Opnd, GPR32Opnd, uimm10,
22746 /* TNEI */
22747 GPR32Opnd, simm16,
22748 /* TNEI_MM */
22749 GPR32Opnd, simm16,
22750 /* TNE_MM */
22751 GPR32Opnd, GPR32Opnd, uimm4,
22752 /* TRUNC_L_D64 */
22753 FGR64Opnd, FGR64Opnd,
22754 /* TRUNC_L_D_MMR6 */
22755 FGR64Opnd, FGR64Opnd,
22756 /* TRUNC_L_S */
22757 FGR64Opnd, FGR32Opnd,
22758 /* TRUNC_L_S_MMR6 */
22759 FGR64Opnd, FGR32Opnd,
22760 /* TRUNC_W_D32 */
22761 FGR32Opnd, AFGR64Opnd,
22762 /* TRUNC_W_D64 */
22763 FGR32Opnd, FGR64Opnd,
22764 /* TRUNC_W_D_MMR6 */
22765 FGR32Opnd, FGR64Opnd,
22766 /* TRUNC_W_MM */
22767 FGR32Opnd, AFGR64Opnd,
22768 /* TRUNC_W_S */
22769 FGR32Opnd, FGR32Opnd,
22770 /* TRUNC_W_S_MM */
22771 FGR32Opnd, FGR32Opnd,
22772 /* TRUNC_W_S_MMR6 */
22773 FGR32Opnd, FGR32Opnd,
22774 /* TTLTIU */
22775 GPR32Opnd, simm16,
22776 /* UDIV */
22777 GPR32Opnd, GPR32Opnd,
22778 /* UDIV_MM */
22779 GPR32Opnd, GPR32Opnd,
22780 /* V3MULU */
22781 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22782 /* VMM0 */
22783 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22784 /* VMULU */
22785 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22786 /* VSHF_B */
22787 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22788 /* VSHF_D */
22789 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd,
22790 /* VSHF_H */
22791 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd,
22792 /* VSHF_W */
22793 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd,
22794 /* WAIT */
22795 /* WAIT_MM */
22796 uimm10,
22797 /* WAIT_MMR6 */
22798 uimm10,
22799 /* WRDSP */
22800 GPR32Opnd, uimm10,
22801 /* WRDSP_MM */
22802 GPR32Opnd, uimm7,
22803 /* WRPGPR_MMR6 */
22804 GPR32Opnd, GPR32Opnd,
22805 /* WSBH */
22806 GPR32Opnd, GPR32Opnd,
22807 /* WSBH_MM */
22808 GPR32Opnd, GPR32Opnd,
22809 /* WSBH_MMR6 */
22810 GPR32Opnd, GPR32Opnd,
22811 /* XOR */
22812 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22813 /* XOR16_MM */
22814 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22815 /* XOR16_MMR6 */
22816 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd,
22817 /* XOR64 */
22818 GPR64Opnd, GPR64Opnd, GPR64Opnd,
22819 /* XORI_B */
22820 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8,
22821 /* XORI_MMR6 */
22822 GPR32Opnd, GPR32Opnd, uimm16,
22823 /* XOR_MM */
22824 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22825 /* XOR_MMR6 */
22826 GPR32Opnd, GPR32Opnd, GPR32Opnd,
22827 /* XOR_V */
22828 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd,
22829 /* XORi */
22830 GPR32Opnd, GPR32Opnd, uimm16,
22831 /* XORi64 */
22832 GPR64Opnd, GPR64Opnd, uimm16_64,
22833 /* XORi_MM */
22834 GPR32Opnd, GPR32Opnd, uimm16,
22835 /* XorRxRxRy16 */
22836 CPU16Regs, CPU16Regs, CPU16Regs,
22837 /* YIELD */
22838 GPR32Opnd, GPR32Opnd,
22839 };
22840 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
22841}
22842} // end namespace Mips
22843} // end namespace llvm
22844#endif // GET_INSTRINFO_OPERAND_TYPE
22845
22846#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
22847#undef GET_INSTRINFO_MEM_OPERAND_SIZE
22848namespace llvm {
22849namespace Mips {
22850LLVM_READONLY
22851static int getMemOperandSize(int OpType) {
22852 switch (OpType) {
22853 default: return 0;
22854 }
22855}
22856} // end namespace Mips
22857} // end namespace llvm
22858#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
22859
22860#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
22861#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
22862namespace llvm {
22863namespace Mips {
22864LLVM_READONLY static unsigned
22865getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
22866 return LogicalOpIdx;
22867}
22868LLVM_READONLY static inline unsigned
22869getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
22870 auto S = 0U;
22871 for (auto i = 0U; i < LogicalOpIdx; ++i)
22872 S += getLogicalOperandSize(Opcode, i);
22873 return S;
22874}
22875} // end namespace Mips
22876} // end namespace llvm
22877#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
22878
22879#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
22880#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
22881namespace llvm {
22882namespace Mips {
22883LLVM_READONLY static int
22884getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
22885 return -1;
22886}
22887} // end namespace Mips
22888} // end namespace llvm
22889#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
22890
22891#ifdef GET_INSTRINFO_MC_HELPER_DECLS
22892#undef GET_INSTRINFO_MC_HELPER_DECLS
22893
22894namespace llvm {
22895class MCInst;
22896class FeatureBitset;
22897
22898namespace Mips_MC {
22899
22900void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
22901
22902} // end namespace Mips_MC
22903} // end namespace llvm
22904
22905#endif // GET_INSTRINFO_MC_HELPER_DECLS
22906
22907#ifdef GET_INSTRINFO_MC_HELPERS
22908#undef GET_INSTRINFO_MC_HELPERS
22909
22910namespace llvm {
22911namespace Mips_MC {
22912
22913} // end namespace Mips_MC
22914} // end namespace llvm
22915
22916#endif // GET_GENISTRINFO_MC_HELPERS
22917
22918#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
22919 defined(GET_AVAILABLE_OPCODE_CHECKER)
22920#define GET_COMPUTE_FEATURES
22921#endif
22922#ifdef GET_COMPUTE_FEATURES
22923#undef GET_COMPUTE_FEATURES
22924namespace llvm {
22925namespace Mips_MC {
22926
22927// Bits for subtarget features that participate in instruction matching.
22928enum SubtargetFeatureBits : uint8_t {
22929 Feature_HasMips2Bit = 11,
22930 Feature_HasMips3_32Bit = 14,
22931 Feature_HasMips3_32r2Bit = 15,
22932 Feature_HasMips3Bit = 12,
22933 Feature_NotMips3Bit = 47,
22934 Feature_HasMips4_32Bit = 16,
22935 Feature_NotMips4_32Bit = 48,
22936 Feature_HasMips4_32r2Bit = 17,
22937 Feature_HasMips5_32r2Bit = 18,
22938 Feature_HasMips32Bit = 19,
22939 Feature_HasMips32r2Bit = 20,
22940 Feature_HasMips32r5Bit = 21,
22941 Feature_HasMips32r6Bit = 22,
22942 Feature_NotMips32r6Bit = 49,
22943 Feature_IsGP64bitBit = 33,
22944 Feature_IsGP32bitBit = 32,
22945 Feature_IsPTR64bitBit = 37,
22946 Feature_IsPTR32bitBit = 36,
22947 Feature_HasMips64Bit = 23,
22948 Feature_NotMips64Bit = 50,
22949 Feature_HasMips64r2Bit = 24,
22950 Feature_HasMips64r5Bit = 25,
22951 Feature_HasMips64r6Bit = 26,
22952 Feature_NotMips64r6Bit = 51,
22953 Feature_InMips16ModeBit = 30,
22954 Feature_NotInMips16ModeBit = 46,
22955 Feature_HasCnMipsBit = 1,
22956 Feature_NotCnMipsBit = 42,
22957 Feature_HasCnMipsPBit = 2,
22958 Feature_NotCnMipsPBit = 43,
22959 Feature_IsSym32Bit = 39,
22960 Feature_IsSym64Bit = 40,
22961 Feature_HasStdEncBit = 27,
22962 Feature_InMicroMipsBit = 29,
22963 Feature_NotInMicroMipsBit = 45,
22964 Feature_HasEVABit = 6,
22965 Feature_HasMSABit = 8,
22966 Feature_HasMadd4Bit = 10,
22967 Feature_HasMTBit = 9,
22968 Feature_UseIndirectJumpsHazardBit = 52,
22969 Feature_NoIndirectJumpGuardsBit = 41,
22970 Feature_HasCRCBit = 0,
22971 Feature_HasVirtBit = 28,
22972 Feature_HasGINVBit = 7,
22973 Feature_IsFP64bitBit = 31,
22974 Feature_NotFP64bitBit = 44,
22975 Feature_IsSingleFloatBit = 38,
22976 Feature_IsNotSingleFloatBit = 34,
22977 Feature_IsNotSoftFloatBit = 35,
22978 Feature_HasMips3DBit = 13,
22979 Feature_HasDSPBit = 3,
22980 Feature_HasDSPR2Bit = 4,
22981 Feature_HasDSPR3Bit = 5,
22982};
22983
22984inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
22985 FeatureBitset Features;
22986 if (FB[Mips::FeatureMips2])
22987 Features.set(Feature_HasMips2Bit);
22988 if (FB[Mips::FeatureMips3_32])
22989 Features.set(Feature_HasMips3_32Bit);
22990 if (FB[Mips::FeatureMips3_32r2])
22991 Features.set(Feature_HasMips3_32r2Bit);
22992 if (FB[Mips::FeatureMips3])
22993 Features.set(Feature_HasMips3Bit);
22994 if (!FB[Mips::FeatureMips3])
22995 Features.set(Feature_NotMips3Bit);
22996 if (FB[Mips::FeatureMips4_32])
22997 Features.set(Feature_HasMips4_32Bit);
22998 if (!FB[Mips::FeatureMips4_32])
22999 Features.set(Feature_NotMips4_32Bit);
23000 if (FB[Mips::FeatureMips4_32r2])
23001 Features.set(Feature_HasMips4_32r2Bit);
23002 if (FB[Mips::FeatureMips5_32r2])
23003 Features.set(Feature_HasMips5_32r2Bit);
23004 if (FB[Mips::FeatureMips32])
23005 Features.set(Feature_HasMips32Bit);
23006 if (FB[Mips::FeatureMips32r2])
23007 Features.set(Feature_HasMips32r2Bit);
23008 if (FB[Mips::FeatureMips32r5])
23009 Features.set(Feature_HasMips32r5Bit);
23010 if (FB[Mips::FeatureMips32r6])
23011 Features.set(Feature_HasMips32r6Bit);
23012 if (!FB[Mips::FeatureMips32r6])
23013 Features.set(Feature_NotMips32r6Bit);
23014 if (FB[Mips::FeatureGP64Bit])
23015 Features.set(Feature_IsGP64bitBit);
23016 if (!FB[Mips::FeatureGP64Bit])
23017 Features.set(Feature_IsGP32bitBit);
23018 if (FB[Mips::FeaturePTR64Bit])
23019 Features.set(Feature_IsPTR64bitBit);
23020 if (!FB[Mips::FeaturePTR64Bit])
23021 Features.set(Feature_IsPTR32bitBit);
23022 if (FB[Mips::FeatureMips64])
23023 Features.set(Feature_HasMips64Bit);
23024 if (!FB[Mips::FeatureMips64])
23025 Features.set(Feature_NotMips64Bit);
23026 if (FB[Mips::FeatureMips64r2])
23027 Features.set(Feature_HasMips64r2Bit);
23028 if (FB[Mips::FeatureMips64r5])
23029 Features.set(Feature_HasMips64r5Bit);
23030 if (FB[Mips::FeatureMips64r6])
23031 Features.set(Feature_HasMips64r6Bit);
23032 if (!FB[Mips::FeatureMips64r6])
23033 Features.set(Feature_NotMips64r6Bit);
23034 if (FB[Mips::FeatureMips16])
23035 Features.set(Feature_InMips16ModeBit);
23036 if (!FB[Mips::FeatureMips16])
23037 Features.set(Feature_NotInMips16ModeBit);
23038 if (FB[Mips::FeatureCnMips])
23039 Features.set(Feature_HasCnMipsBit);
23040 if (!FB[Mips::FeatureCnMips])
23041 Features.set(Feature_NotCnMipsBit);
23042 if (FB[Mips::FeatureCnMipsP])
23043 Features.set(Feature_HasCnMipsPBit);
23044 if (!FB[Mips::FeatureCnMipsP])
23045 Features.set(Feature_NotCnMipsPBit);
23046 if (FB[Mips::FeatureSym32])
23047 Features.set(Feature_IsSym32Bit);
23048 if (!FB[Mips::FeatureSym32])
23049 Features.set(Feature_IsSym64Bit);
23050 if (!FB[Mips::FeatureMips16])
23051 Features.set(Feature_HasStdEncBit);
23052 if (FB[Mips::FeatureMicroMips])
23053 Features.set(Feature_InMicroMipsBit);
23054 if (!FB[Mips::FeatureMicroMips])
23055 Features.set(Feature_NotInMicroMipsBit);
23056 if (FB[Mips::FeatureEVA])
23057 Features.set(Feature_HasEVABit);
23058 if (FB[Mips::FeatureMSA])
23059 Features.set(Feature_HasMSABit);
23060 if (!FB[Mips::FeatureNoMadd4])
23061 Features.set(Feature_HasMadd4Bit);
23062 if (FB[Mips::FeatureMT])
23063 Features.set(Feature_HasMTBit);
23064 if (FB[Mips::FeatureUseIndirectJumpsHazard])
23065 Features.set(Feature_UseIndirectJumpsHazardBit);
23066 if (!FB[Mips::FeatureUseIndirectJumpsHazard])
23067 Features.set(Feature_NoIndirectJumpGuardsBit);
23068 if (FB[Mips::FeatureCRC])
23069 Features.set(Feature_HasCRCBit);
23070 if (FB[Mips::FeatureVirt])
23071 Features.set(Feature_HasVirtBit);
23072 if (FB[Mips::FeatureGINV])
23073 Features.set(Feature_HasGINVBit);
23074 if (FB[Mips::FeatureFP64Bit])
23075 Features.set(Feature_IsFP64bitBit);
23076 if (!FB[Mips::FeatureFP64Bit])
23077 Features.set(Feature_NotFP64bitBit);
23078 if (FB[Mips::FeatureSingleFloat])
23079 Features.set(Feature_IsSingleFloatBit);
23080 if (!FB[Mips::FeatureSingleFloat])
23081 Features.set(Feature_IsNotSingleFloatBit);
23082 if (!FB[Mips::FeatureSoftFloat])
23083 Features.set(Feature_IsNotSoftFloatBit);
23084 if (FB[Mips::FeatureMips3D])
23085 Features.set(Feature_HasMips3DBit);
23086 if (FB[Mips::FeatureDSP])
23087 Features.set(Feature_HasDSPBit);
23088 if (FB[Mips::FeatureDSPR2])
23089 Features.set(Feature_HasDSPR2Bit);
23090 if (FB[Mips::FeatureDSPR3])
23091 Features.set(Feature_HasDSPR3Bit);
23092 return Features;
23093}
23094
23095inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
23096 enum : uint8_t {
23097 CEFBS_None,
23098 CEFBS_HasCnMips,
23099 CEFBS_HasCnMipsP,
23100 CEFBS_HasDSP,
23101 CEFBS_HasDSPR2,
23102 CEFBS_HasMSA,
23103 CEFBS_HasMT,
23104 CEFBS_InMicroMips,
23105 CEFBS_InMips16Mode,
23106 CEFBS_IsGP32bit,
23107 CEFBS_IsGP64bit,
23108 CEFBS_IsNotSoftFloat,
23109 CEFBS_NotCnMips,
23110 CEFBS_NotInMips16Mode,
23111 CEFBS_HasDSP_NotInMicroMips,
23112 CEFBS_HasStdEnc_HasMSA,
23113 CEFBS_HasStdEnc_HasMips32,
23114 CEFBS_HasStdEnc_HasMips32r6,
23115 CEFBS_HasStdEnc_HasMips64,
23116 CEFBS_HasStdEnc_HasMips64r6,
23117 CEFBS_HasStdEnc_IsNotSoftFloat,
23118 CEFBS_HasStdEnc_NotInMicroMips,
23119 CEFBS_HasStdEnc_NotMips3,
23120 CEFBS_HasStdEnc_NotMips4_32,
23121 CEFBS_InMicroMips_HasDSP,
23122 CEFBS_InMicroMips_HasDSPR2,
23123 CEFBS_InMicroMips_HasDSPR3,
23124 CEFBS_InMicroMips_HasEVA,
23125 CEFBS_InMicroMips_HasMips32r6,
23126 CEFBS_InMicroMips_IsNotSoftFloat,
23127 CEFBS_InMicroMips_NotMips32r6,
23128 CEFBS_IsFP64bit_IsNotSoftFloat,
23129 CEFBS_IsGP32bit_NotInMicroMips,
23130 CEFBS_NotFP64bit_IsNotSoftFloat,
23131 CEFBS_NotInMips16Mode_HasDSP,
23132 CEFBS_NotInMips16Mode_IsGP64bit,
23133 CEFBS_NotInMips16Mode_IsNotSoftFloat,
23134 CEFBS_NotInMips16Mode_IsPTR64bit,
23135 CEFBS_HasMips3_NotMips64r6_NotCnMips,
23136 CEFBS_HasMips64_HasCnMips_NotInMicroMips,
23137 CEFBS_HasStdEnc_HasMSA_HasMips64,
23138 CEFBS_HasStdEnc_HasMT_NotInMicroMips,
23139 CEFBS_HasStdEnc_HasMips2_NotInMicroMips,
23140 CEFBS_HasStdEnc_HasMips3_NotInMicroMips,
23141 CEFBS_HasStdEnc_HasMips32_NotInMicroMips,
23142 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,
23143 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,
23144 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,
23145 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,
23146 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,
23147 CEFBS_HasStdEnc_HasMips64r5_HasVirt,
23148 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,
23149 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,
23150 CEFBS_HasStdEnc_IsGP64bit_HasMips3,
23151 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,
23152 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,
23153 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,
23154 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
23155 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,
23156 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,
23157 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,
23158 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,
23159 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,
23160 CEFBS_InMicroMips_HasMips32r5_HasVirt,
23161 CEFBS_InMicroMips_HasMips32r6_HasGINV,
23162 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,
23163 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
23164 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,
23165 CEFBS_InMicroMips_NotMips32r6_HasDSP,
23166 CEFBS_InMicroMips_NotMips32r6_HasEVA,
23167 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,
23168 CEFBS_InMicroMips_NotMips32r6_NotMips64r6,
23169 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,
23170 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,
23171 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,
23172 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,
23173 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,
23174 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,
23175 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
23176 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,
23177 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,
23178 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,
23179 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,
23180 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,
23181 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,
23182 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,
23183 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,
23184 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,
23185 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,
23186 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,
23187 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,
23188 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
23189 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
23190 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,
23191 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,
23192 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
23193 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,
23194 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,
23195 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,
23196 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,
23197 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,
23198 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,
23199 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,
23200 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,
23201 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,
23202 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
23203 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,
23204 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,
23205 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
23206 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
23207 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,
23208 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
23209 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
23210 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
23211 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
23212 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
23213 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
23214 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,
23215 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
23216 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
23217 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,
23218 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,
23219 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
23220 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
23221 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
23222 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23223 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,
23224 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,
23225 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23226 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,
23227 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23228 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
23229 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23230 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
23231 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
23232 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
23233 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23234 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
23235 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
23236 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
23237 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
23238 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
23239 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
23240 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,
23241 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23242 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23243 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23244 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23245 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23246 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23247 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23248 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
23249 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
23250 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
23251 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
23252 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
23253 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
23254 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
23255 };
23256
23257 static constexpr FeatureBitset FeatureBitsets[] = {
23258 {}, // CEFBS_None
23259 {Feature_HasCnMipsBit, },
23260 {Feature_HasCnMipsPBit, },
23261 {Feature_HasDSPBit, },
23262 {Feature_HasDSPR2Bit, },
23263 {Feature_HasMSABit, },
23264 {Feature_HasMTBit, },
23265 {Feature_InMicroMipsBit, },
23266 {Feature_InMips16ModeBit, },
23267 {Feature_IsGP32bitBit, },
23268 {Feature_IsGP64bitBit, },
23269 {Feature_IsNotSoftFloatBit, },
23270 {Feature_NotCnMipsBit, },
23271 {Feature_NotInMips16ModeBit, },
23272 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
23273 {Feature_HasStdEncBit, Feature_HasMSABit, },
23274 {Feature_HasStdEncBit, Feature_HasMips32Bit, },
23275 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, },
23276 {Feature_HasStdEncBit, Feature_HasMips64Bit, },
23277 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, },
23278 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
23279 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
23280 {Feature_HasStdEncBit, Feature_NotMips3Bit, },
23281 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
23282 {Feature_InMicroMipsBit, Feature_HasDSPBit, },
23283 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },
23284 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },
23285 {Feature_InMicroMipsBit, Feature_HasEVABit, },
23286 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },
23287 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
23288 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
23289 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
23290 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },
23291 {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23292 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, },
23293 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },
23294 {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },
23295 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },
23296 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },
23297 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },
23298 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },
23299 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },
23300 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },
23301 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },
23302 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },
23303 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },
23304 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },
23305 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
23306 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },
23307 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },
23308 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },
23309 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
23310 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
23311 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },
23312 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },
23313 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },
23314 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },
23315 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23316 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23317 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
23318 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23319 {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },
23320 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23321 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },
23322 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },
23323 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
23324 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
23325 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23326 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },
23327 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },
23328 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
23329 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23330 {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
23331 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
23332 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },
23333 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },
23334 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },
23335 {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
23336 {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23337 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23338 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
23339 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23340 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23341 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23342 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23343 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
23344 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
23345 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },
23346 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
23347 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },
23348 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23349 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23350 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23351 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23352 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
23353 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23354 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
23355 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
23356 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
23357 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23358 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23359 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
23360 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
23361 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
23362 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
23363 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23364 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23365 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23366 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23367 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23368 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23369 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23370 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
23371 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23372 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23373 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23374 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23375 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23376 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23377 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23378 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
23379 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23380 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23381 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23382 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23383 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23384 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
23385 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
23386 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23387 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
23388 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23389 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
23390 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23391 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23392 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23393 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
23394 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23395 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23396 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23397 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23398 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23399 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
23400 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
23401 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },
23402 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23403 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23404 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23405 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23406 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23407 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23408 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23409 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
23410 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
23411 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
23412 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
23413 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
23414 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
23415 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
23416 };
23417 static constexpr uint8_t RequiredFeaturesRefs[] = {
23418 CEFBS_None, // PHI = 0
23419 CEFBS_None, // INLINEASM = 1
23420 CEFBS_None, // INLINEASM_BR = 2
23421 CEFBS_None, // CFI_INSTRUCTION = 3
23422 CEFBS_None, // EH_LABEL = 4
23423 CEFBS_None, // GC_LABEL = 5
23424 CEFBS_None, // ANNOTATION_LABEL = 6
23425 CEFBS_None, // KILL = 7
23426 CEFBS_None, // EXTRACT_SUBREG = 8
23427 CEFBS_None, // INSERT_SUBREG = 9
23428 CEFBS_None, // IMPLICIT_DEF = 10
23429 CEFBS_None, // SUBREG_TO_REG = 11
23430 CEFBS_None, // COPY_TO_REGCLASS = 12
23431 CEFBS_None, // DBG_VALUE = 13
23432 CEFBS_None, // DBG_VALUE_LIST = 14
23433 CEFBS_None, // DBG_INSTR_REF = 15
23434 CEFBS_None, // DBG_PHI = 16
23435 CEFBS_None, // DBG_LABEL = 17
23436 CEFBS_None, // REG_SEQUENCE = 18
23437 CEFBS_None, // COPY = 19
23438 CEFBS_None, // BUNDLE = 20
23439 CEFBS_None, // LIFETIME_START = 21
23440 CEFBS_None, // LIFETIME_END = 22
23441 CEFBS_None, // PSEUDO_PROBE = 23
23442 CEFBS_None, // ARITH_FENCE = 24
23443 CEFBS_None, // STACKMAP = 25
23444 CEFBS_None, // FENTRY_CALL = 26
23445 CEFBS_None, // PATCHPOINT = 27
23446 CEFBS_None, // LOAD_STACK_GUARD = 28
23447 CEFBS_None, // PREALLOCATED_SETUP = 29
23448 CEFBS_None, // PREALLOCATED_ARG = 30
23449 CEFBS_None, // STATEPOINT = 31
23450 CEFBS_None, // LOCAL_ESCAPE = 32
23451 CEFBS_None, // FAULTING_OP = 33
23452 CEFBS_None, // PATCHABLE_OP = 34
23453 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
23454 CEFBS_None, // PATCHABLE_RET = 36
23455 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
23456 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
23457 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
23458 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
23459 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
23460 CEFBS_None, // MEMBARRIER = 42
23461 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
23462 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
23463 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
23464 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
23465 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
23466 CEFBS_None, // G_ASSERT_SEXT = 48
23467 CEFBS_None, // G_ASSERT_ZEXT = 49
23468 CEFBS_None, // G_ASSERT_ALIGN = 50
23469 CEFBS_None, // G_ADD = 51
23470 CEFBS_None, // G_SUB = 52
23471 CEFBS_None, // G_MUL = 53
23472 CEFBS_None, // G_SDIV = 54
23473 CEFBS_None, // G_UDIV = 55
23474 CEFBS_None, // G_SREM = 56
23475 CEFBS_None, // G_UREM = 57
23476 CEFBS_None, // G_SDIVREM = 58
23477 CEFBS_None, // G_UDIVREM = 59
23478 CEFBS_None, // G_AND = 60
23479 CEFBS_None, // G_OR = 61
23480 CEFBS_None, // G_XOR = 62
23481 CEFBS_None, // G_IMPLICIT_DEF = 63
23482 CEFBS_None, // G_PHI = 64
23483 CEFBS_None, // G_FRAME_INDEX = 65
23484 CEFBS_None, // G_GLOBAL_VALUE = 66
23485 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
23486 CEFBS_None, // G_CONSTANT_POOL = 68
23487 CEFBS_None, // G_EXTRACT = 69
23488 CEFBS_None, // G_UNMERGE_VALUES = 70
23489 CEFBS_None, // G_INSERT = 71
23490 CEFBS_None, // G_MERGE_VALUES = 72
23491 CEFBS_None, // G_BUILD_VECTOR = 73
23492 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
23493 CEFBS_None, // G_CONCAT_VECTORS = 75
23494 CEFBS_None, // G_PTRTOINT = 76
23495 CEFBS_None, // G_INTTOPTR = 77
23496 CEFBS_None, // G_BITCAST = 78
23497 CEFBS_None, // G_FREEZE = 79
23498 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
23499 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
23500 CEFBS_None, // G_INTRINSIC_TRUNC = 82
23501 CEFBS_None, // G_INTRINSIC_ROUND = 83
23502 CEFBS_None, // G_INTRINSIC_LRINT = 84
23503 CEFBS_None, // G_INTRINSIC_LLRINT = 85
23504 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
23505 CEFBS_None, // G_READCYCLECOUNTER = 87
23506 CEFBS_None, // G_READSTEADYCOUNTER = 88
23507 CEFBS_None, // G_LOAD = 89
23508 CEFBS_None, // G_SEXTLOAD = 90
23509 CEFBS_None, // G_ZEXTLOAD = 91
23510 CEFBS_None, // G_INDEXED_LOAD = 92
23511 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
23512 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
23513 CEFBS_None, // G_STORE = 95
23514 CEFBS_None, // G_INDEXED_STORE = 96
23515 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
23516 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
23517 CEFBS_None, // G_ATOMICRMW_XCHG = 99
23518 CEFBS_None, // G_ATOMICRMW_ADD = 100
23519 CEFBS_None, // G_ATOMICRMW_SUB = 101
23520 CEFBS_None, // G_ATOMICRMW_AND = 102
23521 CEFBS_None, // G_ATOMICRMW_NAND = 103
23522 CEFBS_None, // G_ATOMICRMW_OR = 104
23523 CEFBS_None, // G_ATOMICRMW_XOR = 105
23524 CEFBS_None, // G_ATOMICRMW_MAX = 106
23525 CEFBS_None, // G_ATOMICRMW_MIN = 107
23526 CEFBS_None, // G_ATOMICRMW_UMAX = 108
23527 CEFBS_None, // G_ATOMICRMW_UMIN = 109
23528 CEFBS_None, // G_ATOMICRMW_FADD = 110
23529 CEFBS_None, // G_ATOMICRMW_FSUB = 111
23530 CEFBS_None, // G_ATOMICRMW_FMAX = 112
23531 CEFBS_None, // G_ATOMICRMW_FMIN = 113
23532 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
23533 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
23534 CEFBS_None, // G_FENCE = 116
23535 CEFBS_None, // G_PREFETCH = 117
23536 CEFBS_None, // G_BRCOND = 118
23537 CEFBS_None, // G_BRINDIRECT = 119
23538 CEFBS_None, // G_INVOKE_REGION_START = 120
23539 CEFBS_None, // G_INTRINSIC = 121
23540 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
23541 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
23542 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
23543 CEFBS_None, // G_ANYEXT = 125
23544 CEFBS_None, // G_TRUNC = 126
23545 CEFBS_None, // G_CONSTANT = 127
23546 CEFBS_None, // G_FCONSTANT = 128
23547 CEFBS_None, // G_VASTART = 129
23548 CEFBS_None, // G_VAARG = 130
23549 CEFBS_None, // G_SEXT = 131
23550 CEFBS_None, // G_SEXT_INREG = 132
23551 CEFBS_None, // G_ZEXT = 133
23552 CEFBS_None, // G_SHL = 134
23553 CEFBS_None, // G_LSHR = 135
23554 CEFBS_None, // G_ASHR = 136
23555 CEFBS_None, // G_FSHL = 137
23556 CEFBS_None, // G_FSHR = 138
23557 CEFBS_None, // G_ROTR = 139
23558 CEFBS_None, // G_ROTL = 140
23559 CEFBS_None, // G_ICMP = 141
23560 CEFBS_None, // G_FCMP = 142
23561 CEFBS_None, // G_SCMP = 143
23562 CEFBS_None, // G_UCMP = 144
23563 CEFBS_None, // G_SELECT = 145
23564 CEFBS_None, // G_UADDO = 146
23565 CEFBS_None, // G_UADDE = 147
23566 CEFBS_None, // G_USUBO = 148
23567 CEFBS_None, // G_USUBE = 149
23568 CEFBS_None, // G_SADDO = 150
23569 CEFBS_None, // G_SADDE = 151
23570 CEFBS_None, // G_SSUBO = 152
23571 CEFBS_None, // G_SSUBE = 153
23572 CEFBS_None, // G_UMULO = 154
23573 CEFBS_None, // G_SMULO = 155
23574 CEFBS_None, // G_UMULH = 156
23575 CEFBS_None, // G_SMULH = 157
23576 CEFBS_None, // G_UADDSAT = 158
23577 CEFBS_None, // G_SADDSAT = 159
23578 CEFBS_None, // G_USUBSAT = 160
23579 CEFBS_None, // G_SSUBSAT = 161
23580 CEFBS_None, // G_USHLSAT = 162
23581 CEFBS_None, // G_SSHLSAT = 163
23582 CEFBS_None, // G_SMULFIX = 164
23583 CEFBS_None, // G_UMULFIX = 165
23584 CEFBS_None, // G_SMULFIXSAT = 166
23585 CEFBS_None, // G_UMULFIXSAT = 167
23586 CEFBS_None, // G_SDIVFIX = 168
23587 CEFBS_None, // G_UDIVFIX = 169
23588 CEFBS_None, // G_SDIVFIXSAT = 170
23589 CEFBS_None, // G_UDIVFIXSAT = 171
23590 CEFBS_None, // G_FADD = 172
23591 CEFBS_None, // G_FSUB = 173
23592 CEFBS_None, // G_FMUL = 174
23593 CEFBS_None, // G_FMA = 175
23594 CEFBS_None, // G_FMAD = 176
23595 CEFBS_None, // G_FDIV = 177
23596 CEFBS_None, // G_FREM = 178
23597 CEFBS_None, // G_FPOW = 179
23598 CEFBS_None, // G_FPOWI = 180
23599 CEFBS_None, // G_FEXP = 181
23600 CEFBS_None, // G_FEXP2 = 182
23601 CEFBS_None, // G_FEXP10 = 183
23602 CEFBS_None, // G_FLOG = 184
23603 CEFBS_None, // G_FLOG2 = 185
23604 CEFBS_None, // G_FLOG10 = 186
23605 CEFBS_None, // G_FLDEXP = 187
23606 CEFBS_None, // G_FFREXP = 188
23607 CEFBS_None, // G_FNEG = 189
23608 CEFBS_None, // G_FPEXT = 190
23609 CEFBS_None, // G_FPTRUNC = 191
23610 CEFBS_None, // G_FPTOSI = 192
23611 CEFBS_None, // G_FPTOUI = 193
23612 CEFBS_None, // G_SITOFP = 194
23613 CEFBS_None, // G_UITOFP = 195
23614 CEFBS_None, // G_FABS = 196
23615 CEFBS_None, // G_FCOPYSIGN = 197
23616 CEFBS_None, // G_IS_FPCLASS = 198
23617 CEFBS_None, // G_FCANONICALIZE = 199
23618 CEFBS_None, // G_FMINNUM = 200
23619 CEFBS_None, // G_FMAXNUM = 201
23620 CEFBS_None, // G_FMINNUM_IEEE = 202
23621 CEFBS_None, // G_FMAXNUM_IEEE = 203
23622 CEFBS_None, // G_FMINIMUM = 204
23623 CEFBS_None, // G_FMAXIMUM = 205
23624 CEFBS_None, // G_GET_FPENV = 206
23625 CEFBS_None, // G_SET_FPENV = 207
23626 CEFBS_None, // G_RESET_FPENV = 208
23627 CEFBS_None, // G_GET_FPMODE = 209
23628 CEFBS_None, // G_SET_FPMODE = 210
23629 CEFBS_None, // G_RESET_FPMODE = 211
23630 CEFBS_None, // G_PTR_ADD = 212
23631 CEFBS_None, // G_PTRMASK = 213
23632 CEFBS_None, // G_SMIN = 214
23633 CEFBS_None, // G_SMAX = 215
23634 CEFBS_None, // G_UMIN = 216
23635 CEFBS_None, // G_UMAX = 217
23636 CEFBS_None, // G_ABS = 218
23637 CEFBS_None, // G_LROUND = 219
23638 CEFBS_None, // G_LLROUND = 220
23639 CEFBS_None, // G_BR = 221
23640 CEFBS_None, // G_BRJT = 222
23641 CEFBS_None, // G_VSCALE = 223
23642 CEFBS_None, // G_INSERT_SUBVECTOR = 224
23643 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
23644 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
23645 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
23646 CEFBS_None, // G_SHUFFLE_VECTOR = 228
23647 CEFBS_None, // G_SPLAT_VECTOR = 229
23648 CEFBS_None, // G_VECTOR_COMPRESS = 230
23649 CEFBS_None, // G_CTTZ = 231
23650 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
23651 CEFBS_None, // G_CTLZ = 233
23652 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
23653 CEFBS_None, // G_CTPOP = 235
23654 CEFBS_None, // G_BSWAP = 236
23655 CEFBS_None, // G_BITREVERSE = 237
23656 CEFBS_None, // G_FCEIL = 238
23657 CEFBS_None, // G_FCOS = 239
23658 CEFBS_None, // G_FSIN = 240
23659 CEFBS_None, // G_FTAN = 241
23660 CEFBS_None, // G_FACOS = 242
23661 CEFBS_None, // G_FASIN = 243
23662 CEFBS_None, // G_FATAN = 244
23663 CEFBS_None, // G_FCOSH = 245
23664 CEFBS_None, // G_FSINH = 246
23665 CEFBS_None, // G_FTANH = 247
23666 CEFBS_None, // G_FSQRT = 248
23667 CEFBS_None, // G_FFLOOR = 249
23668 CEFBS_None, // G_FRINT = 250
23669 CEFBS_None, // G_FNEARBYINT = 251
23670 CEFBS_None, // G_ADDRSPACE_CAST = 252
23671 CEFBS_None, // G_BLOCK_ADDR = 253
23672 CEFBS_None, // G_JUMP_TABLE = 254
23673 CEFBS_None, // G_DYN_STACKALLOC = 255
23674 CEFBS_None, // G_STACKSAVE = 256
23675 CEFBS_None, // G_STACKRESTORE = 257
23676 CEFBS_None, // G_STRICT_FADD = 258
23677 CEFBS_None, // G_STRICT_FSUB = 259
23678 CEFBS_None, // G_STRICT_FMUL = 260
23679 CEFBS_None, // G_STRICT_FDIV = 261
23680 CEFBS_None, // G_STRICT_FREM = 262
23681 CEFBS_None, // G_STRICT_FMA = 263
23682 CEFBS_None, // G_STRICT_FSQRT = 264
23683 CEFBS_None, // G_STRICT_FLDEXP = 265
23684 CEFBS_None, // G_READ_REGISTER = 266
23685 CEFBS_None, // G_WRITE_REGISTER = 267
23686 CEFBS_None, // G_MEMCPY = 268
23687 CEFBS_None, // G_MEMCPY_INLINE = 269
23688 CEFBS_None, // G_MEMMOVE = 270
23689 CEFBS_None, // G_MEMSET = 271
23690 CEFBS_None, // G_BZERO = 272
23691 CEFBS_None, // G_TRAP = 273
23692 CEFBS_None, // G_DEBUGTRAP = 274
23693 CEFBS_None, // G_UBSANTRAP = 275
23694 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
23695 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
23696 CEFBS_None, // G_VECREDUCE_FADD = 278
23697 CEFBS_None, // G_VECREDUCE_FMUL = 279
23698 CEFBS_None, // G_VECREDUCE_FMAX = 280
23699 CEFBS_None, // G_VECREDUCE_FMIN = 281
23700 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
23701 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
23702 CEFBS_None, // G_VECREDUCE_ADD = 284
23703 CEFBS_None, // G_VECREDUCE_MUL = 285
23704 CEFBS_None, // G_VECREDUCE_AND = 286
23705 CEFBS_None, // G_VECREDUCE_OR = 287
23706 CEFBS_None, // G_VECREDUCE_XOR = 288
23707 CEFBS_None, // G_VECREDUCE_SMAX = 289
23708 CEFBS_None, // G_VECREDUCE_SMIN = 290
23709 CEFBS_None, // G_VECREDUCE_UMAX = 291
23710 CEFBS_None, // G_VECREDUCE_UMIN = 292
23711 CEFBS_None, // G_SBFX = 293
23712 CEFBS_None, // G_UBFX = 294
23713 CEFBS_None, // ABSMacro = 295
23714 CEFBS_None, // ADJCALLSTACKDOWN = 296
23715 CEFBS_None, // ADJCALLSTACKUP = 297
23716 CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 298
23717 CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 299
23718 CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 300
23719 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 301
23720 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 302
23721 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 303
23722 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 304
23723 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 305
23724 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 306
23725 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 307
23726 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 308
23727 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 309
23728 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 310
23729 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 311
23730 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 312
23731 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 313
23732 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 314
23733 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 315
23734 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 316
23735 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 317
23736 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 318
23737 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 319
23738 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 320
23739 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 321
23740 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 322
23741 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 323
23742 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 324
23743 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 325
23744 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 326
23745 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 327
23746 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 328
23747 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 329
23748 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 330
23749 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 331
23750 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 332
23751 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 333
23752 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 334
23753 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 335
23754 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 336
23755 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 337
23756 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 338
23757 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 339
23758 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 340
23759 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 341
23760 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 342
23761 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 343
23762 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 344
23763 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 345
23764 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 346
23765 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 347
23766 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 348
23767 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 349
23768 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 350
23769 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 351
23770 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 352
23771 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 353
23772 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 354
23773 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 355
23774 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 356
23775 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 357
23776 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 358
23777 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 359
23778 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 360
23779 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 361
23780 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 362
23781 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 363
23782 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 364
23783 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 365
23784 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 366
23785 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 367
23786 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 368
23787 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 369
23788 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 370
23789 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 371
23790 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 372
23791 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 373
23792 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 374
23793 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 375
23794 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 376
23795 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 377
23796 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 378
23797 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 379
23798 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 380
23799 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 381
23800 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 382
23801 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 383
23802 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 384
23803 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 385
23804 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 386
23805 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 387
23806 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 388
23807 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 389
23808 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 390
23809 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 391
23810 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 392
23811 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 393
23812 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 394
23813 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 395
23814 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 396
23815 CEFBS_HasStdEnc_NotInMicroMips, // B = 397
23816 CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 398
23817 CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 399
23818 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 400
23819 CEFBS_None, // BGE = 401
23820 CEFBS_None, // BGEImmMacro = 402
23821 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 403
23822 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 404
23823 CEFBS_None, // BGEU = 405
23824 CEFBS_None, // BGEUImmMacro = 406
23825 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 407
23826 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 408
23827 CEFBS_None, // BGT = 409
23828 CEFBS_None, // BGTImmMacro = 410
23829 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 411
23830 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 412
23831 CEFBS_None, // BGTU = 413
23832 CEFBS_None, // BGTUImmMacro = 414
23833 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 415
23834 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 416
23835 CEFBS_None, // BLE = 417
23836 CEFBS_None, // BLEImmMacro = 418
23837 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 419
23838 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 420
23839 CEFBS_None, // BLEU = 421
23840 CEFBS_None, // BLEUImmMacro = 422
23841 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 423
23842 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 424
23843 CEFBS_None, // BLT = 425
23844 CEFBS_None, // BLTImmMacro = 426
23845 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 427
23846 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 428
23847 CEFBS_None, // BLTU = 429
23848 CEFBS_None, // BLTUImmMacro = 430
23849 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 431
23850 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 432
23851 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 433
23852 CEFBS_None, // BPOSGE32_PSEUDO = 434
23853 CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 435
23854 CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 436
23855 CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 437
23856 CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 438
23857 CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 439
23858 CEFBS_InMicroMips_NotMips32r6, // B_MM = 440
23859 CEFBS_None, // B_MMR6_Pseudo = 441
23860 CEFBS_InMicroMips, // B_MM_Pseudo = 442
23861 CEFBS_None, // BeqImm = 443
23862 CEFBS_None, // BneImm = 444
23863 CEFBS_InMips16Mode, // BteqzT8CmpX16 = 445
23864 CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 446
23865 CEFBS_InMips16Mode, // BteqzT8SltX16 = 447
23866 CEFBS_InMips16Mode, // BteqzT8SltiX16 = 448
23867 CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 449
23868 CEFBS_InMips16Mode, // BteqzT8SltuX16 = 450
23869 CEFBS_InMips16Mode, // BtnezT8CmpX16 = 451
23870 CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 452
23871 CEFBS_InMips16Mode, // BtnezT8SltX16 = 453
23872 CEFBS_InMips16Mode, // BtnezT8SltiX16 = 454
23873 CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 455
23874 CEFBS_InMips16Mode, // BtnezT8SltuX16 = 456
23875 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 457
23876 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 458
23877 CEFBS_HasMT, // CFTC1 = 459
23878 CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 460
23879 CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 461
23880 CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 462
23881 CEFBS_HasMT, // CTTC1 = 463
23882 CEFBS_InMips16Mode, // Constant32 = 464
23883 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 465
23884 CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 466
23885 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 467
23886 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 468
23887 CEFBS_HasStdEnc_HasMips64, // DROL = 469
23888 CEFBS_HasStdEnc_HasMips64, // DROLImm = 470
23889 CEFBS_HasStdEnc_HasMips64, // DROR = 471
23890 CEFBS_HasStdEnc_HasMips64, // DRORImm = 472
23891 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 473
23892 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 474
23893 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 475
23894 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 476
23895 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 477
23896 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 478
23897 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 479
23898 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 480
23899 CEFBS_NotInMips16Mode, // ERet = 481
23900 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 482
23901 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 483
23902 CEFBS_HasStdEnc_HasMSA, // FABS_D = 484
23903 CEFBS_HasStdEnc_HasMSA, // FABS_W = 485
23904 CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 486
23905 CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 487
23906 CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 488
23907 CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 489
23908 CEFBS_InMips16Mode, // GotPrologue16 = 490
23909 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 491
23910 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 492
23911 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 493
23912 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 494
23913 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 495
23914 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 496
23915 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 497
23916 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 498
23917 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 499
23918 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 500
23919 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 501
23920 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 502
23921 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 503
23922 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 504
23923 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 505
23924 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 506
23925 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 507
23926 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 508
23927 CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 509
23928 CEFBS_None, // JalOneReg = 510
23929 CEFBS_None, // JalTwoReg = 511
23930 CEFBS_HasStdEnc_NotMips3, // LDMacro = 512
23931 CEFBS_NotInMips16Mode, // LDR_D = 513
23932 CEFBS_NotInMips16Mode, // LDR_W = 514
23933 CEFBS_HasMSA, // LD_F16 = 515
23934 CEFBS_NotInMips16Mode, // LOAD_ACC128 = 516
23935 CEFBS_NotInMips16Mode, // LOAD_ACC64 = 517
23936 CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 518
23937 CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 519
23938 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 520
23939 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 521
23940 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 522
23941 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 523
23942 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 524
23943 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 525
23944 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 526
23945 CEFBS_InMicroMips, // LWM_MM = 527
23946 CEFBS_None, // LoadAddrImm32 = 528
23947 CEFBS_None, // LoadAddrImm64 = 529
23948 CEFBS_None, // LoadAddrReg32 = 530
23949 CEFBS_None, // LoadAddrReg64 = 531
23950 CEFBS_None, // LoadImm32 = 532
23951 CEFBS_None, // LoadImm64 = 533
23952 CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 534
23953 CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 535
23954 CEFBS_None, // LoadImmDoubleGPR = 536
23955 CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 537
23956 CEFBS_None, // LoadImmSingleGPR = 538
23957 CEFBS_InMips16Mode, // LwConstant32 = 539
23958 CEFBS_HasMT, // MFTACX = 540
23959 CEFBS_HasMT, // MFTC0 = 541
23960 CEFBS_HasMT, // MFTC1 = 542
23961 CEFBS_HasMT, // MFTDSP = 543
23962 CEFBS_HasMT, // MFTGPR = 544
23963 CEFBS_HasMT, // MFTHC1 = 545
23964 CEFBS_HasMT, // MFTHI = 546
23965 CEFBS_HasMT, // MFTLO = 547
23966 CEFBS_None, // MIPSeh_return32 = 548
23967 CEFBS_None, // MIPSeh_return64 = 549
23968 CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 550
23969 CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 551
23970 CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 552
23971 CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 553
23972 CEFBS_HasMT, // MTTACX = 554
23973 CEFBS_HasMT, // MTTC0 = 555
23974 CEFBS_HasMT, // MTTC1 = 556
23975 CEFBS_HasMT, // MTTDSP = 557
23976 CEFBS_HasMT, // MTTGPR = 558
23977 CEFBS_HasMT, // MTTHC1 = 559
23978 CEFBS_HasMT, // MTTHI = 560
23979 CEFBS_HasMT, // MTTLO = 561
23980 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 562
23981 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 563
23982 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 564
23983 CEFBS_InMips16Mode, // MultRxRy16 = 565
23984 CEFBS_InMips16Mode, // MultRxRyRz16 = 566
23985 CEFBS_InMips16Mode, // MultuRxRy16 = 567
23986 CEFBS_InMips16Mode, // MultuRxRyRz16 = 568
23987 CEFBS_HasStdEnc_NotInMicroMips, // NOP = 569
23988 CEFBS_IsGP32bit, // NORImm = 570
23989 CEFBS_IsGP64bit, // NORImm64 = 571
23990 CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 572
23991 CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 573
23992 CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 574
23993 CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 575
23994 CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 576
23995 CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 577
23996 CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 578
23997 CEFBS_HasDSP, // PseudoCMPU_LE_QB = 579
23998 CEFBS_HasDSP, // PseudoCMPU_LT_QB = 580
23999 CEFBS_HasDSP, // PseudoCMP_EQ_PH = 581
24000 CEFBS_HasDSP, // PseudoCMP_LE_PH = 582
24001 CEFBS_HasDSP, // PseudoCMP_LT_PH = 583
24002 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 584
24003 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 585
24004 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 586
24005 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 587
24006 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 588
24007 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 589
24008 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 590
24009 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 591
24010 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 592
24011 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 593
24012 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 594
24013 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 595
24014 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 596
24015 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 597
24016 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 598
24017 CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 599
24018 CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 600
24019 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 601
24020 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 602
24021 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 603
24022 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 604
24023 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 605
24024 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 606
24025 CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 607
24026 CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 608
24027 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 609
24028 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 610
24029 CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 611
24030 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 612
24031 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 613
24032 CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 614
24033 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 615
24034 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 616
24035 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 617
24036 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 618
24037 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 619
24038 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 620
24039 CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 621
24040 CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 622
24041 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 623
24042 CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 624
24043 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 625
24044 CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 626
24045 CEFBS_HasDSP, // PseudoPICK_PH = 627
24046 CEFBS_HasDSP, // PseudoPICK_QB = 628
24047 CEFBS_None, // PseudoReturn = 629
24048 CEFBS_IsGP64bit, // PseudoReturn64 = 630
24049 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 631
24050 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 632
24051 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 633
24052 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 634
24053 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 635
24054 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 636
24055 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 637
24056 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 638
24057 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 639
24058 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 640
24059 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 641
24060 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 642
24061 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 643
24062 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 644
24063 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 645
24064 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 646
24065 CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 647
24066 CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 648
24067 CEFBS_None, // PseudoTRUNC_W_S = 649
24068 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 650
24069 CEFBS_None, // ROL = 651
24070 CEFBS_None, // ROLImm = 652
24071 CEFBS_None, // ROR = 653
24072 CEFBS_None, // RORImm = 654
24073 CEFBS_NotInMips16Mode, // RetRA = 655
24074 CEFBS_InMips16Mode, // RetRA16 = 656
24075 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 657
24076 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 658
24077 CEFBS_HasStdEnc_NotMips3, // SDMacro = 659
24078 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 660
24079 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 661
24080 CEFBS_NotCnMips, // SEQIMacro = 662
24081 CEFBS_NotCnMips, // SEQMacro = 663
24082 CEFBS_HasStdEnc_NotInMicroMips, // SGE = 664
24083 CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 665
24084 CEFBS_IsGP64bit, // SGEImm64 = 666
24085 CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 667
24086 CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 668
24087 CEFBS_IsGP64bit, // SGEUImm64 = 669
24088 CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 670
24089 CEFBS_IsGP64bit, // SGTImm64 = 671
24090 CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 672
24091 CEFBS_IsGP64bit, // SGTUImm64 = 673
24092 CEFBS_HasStdEnc_NotInMicroMips, // SLE = 674
24093 CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 675
24094 CEFBS_IsGP64bit, // SLEImm64 = 676
24095 CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 677
24096 CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 678
24097 CEFBS_IsGP64bit, // SLEUImm64 = 679
24098 CEFBS_IsGP64bit, // SLTImm64 = 680
24099 CEFBS_IsGP64bit, // SLTUImm64 = 681
24100 CEFBS_NotCnMips, // SNEIMacro = 682
24101 CEFBS_NotCnMips, // SNEMacro = 683
24102 CEFBS_None, // SNZ_B_PSEUDO = 684
24103 CEFBS_None, // SNZ_D_PSEUDO = 685
24104 CEFBS_None, // SNZ_H_PSEUDO = 686
24105 CEFBS_None, // SNZ_V_PSEUDO = 687
24106 CEFBS_None, // SNZ_W_PSEUDO = 688
24107 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 689
24108 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 690
24109 CEFBS_NotInMips16Mode, // STORE_ACC128 = 691
24110 CEFBS_NotInMips16Mode, // STORE_ACC64 = 692
24111 CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 693
24112 CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 694
24113 CEFBS_NotInMips16Mode, // STR_D = 695
24114 CEFBS_NotInMips16Mode, // STR_W = 696
24115 CEFBS_HasMSA, // ST_F16 = 697
24116 CEFBS_InMicroMips, // SWM_MM = 698
24117 CEFBS_None, // SZ_B_PSEUDO = 699
24118 CEFBS_None, // SZ_D_PSEUDO = 700
24119 CEFBS_None, // SZ_H_PSEUDO = 701
24120 CEFBS_None, // SZ_V_PSEUDO = 702
24121 CEFBS_None, // SZ_W_PSEUDO = 703
24122 CEFBS_HasCnMipsP, // SaaAddr = 704
24123 CEFBS_HasCnMipsP, // SaadAddr = 705
24124 CEFBS_InMips16Mode, // SelBeqZ = 706
24125 CEFBS_InMips16Mode, // SelBneZ = 707
24126 CEFBS_InMips16Mode, // SelTBteqZCmp = 708
24127 CEFBS_InMips16Mode, // SelTBteqZCmpi = 709
24128 CEFBS_InMips16Mode, // SelTBteqZSlt = 710
24129 CEFBS_InMips16Mode, // SelTBteqZSlti = 711
24130 CEFBS_InMips16Mode, // SelTBteqZSltiu = 712
24131 CEFBS_InMips16Mode, // SelTBteqZSltu = 713
24132 CEFBS_InMips16Mode, // SelTBtneZCmp = 714
24133 CEFBS_InMips16Mode, // SelTBtneZCmpi = 715
24134 CEFBS_InMips16Mode, // SelTBtneZSlt = 716
24135 CEFBS_InMips16Mode, // SelTBtneZSlti = 717
24136 CEFBS_InMips16Mode, // SelTBtneZSltiu = 718
24137 CEFBS_InMips16Mode, // SelTBtneZSltu = 719
24138 CEFBS_InMips16Mode, // SltCCRxRy16 = 720
24139 CEFBS_InMips16Mode, // SltiCCRxImmX16 = 721
24140 CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 722
24141 CEFBS_InMips16Mode, // SltuCCRxRy16 = 723
24142 CEFBS_InMips16Mode, // SltuRxRyRz16 = 724
24143 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 725
24144 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 726
24145 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 727
24146 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 728
24147 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 729
24148 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 730
24149 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 731
24150 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 732
24151 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 733
24152 CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 734
24153 CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 735
24154 CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 736
24155 CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 737
24156 CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 738
24157 CEFBS_InMicroMips, // TRAP_MM = 739
24158 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 740
24159 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 741
24160 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 742
24161 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 743
24162 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 744
24163 CEFBS_None, // Ulh = 745
24164 CEFBS_None, // Ulhu = 746
24165 CEFBS_None, // Ulw = 747
24166 CEFBS_None, // Ush = 748
24167 CEFBS_None, // Usw = 749
24168 CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 750
24169 CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 751
24170 CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 752
24171 CEFBS_HasDSP, // ABSQ_S_PH = 753
24172 CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 754
24173 CEFBS_HasDSPR2, // ABSQ_S_QB = 755
24174 CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 756
24175 CEFBS_HasDSP, // ABSQ_S_W = 757
24176 CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 758
24177 CEFBS_HasStdEnc_NotInMicroMips, // ADD = 759
24178 CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 760
24179 CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 761
24180 CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 762
24181 CEFBS_InMicroMips, // ADDIUR1SP_MM = 763
24182 CEFBS_InMicroMips, // ADDIUR2_MM = 764
24183 CEFBS_InMicroMips, // ADDIUS5_MM = 765
24184 CEFBS_InMicroMips, // ADDIUSP_MM = 766
24185 CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 767
24186 CEFBS_HasDSPR2, // ADDQH_PH = 768
24187 CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 769
24188 CEFBS_HasDSPR2, // ADDQH_R_PH = 770
24189 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 771
24190 CEFBS_HasDSPR2, // ADDQH_R_W = 772
24191 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 773
24192 CEFBS_HasDSPR2, // ADDQH_W = 774
24193 CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 775
24194 CEFBS_HasDSP, // ADDQ_PH = 776
24195 CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 777
24196 CEFBS_HasDSP, // ADDQ_S_PH = 778
24197 CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 779
24198 CEFBS_HasDSP, // ADDQ_S_W = 780
24199 CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 781
24200 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 782
24201 CEFBS_HasDSP, // ADDSC = 783
24202 CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 784
24203 CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 785
24204 CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 786
24205 CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 787
24206 CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 788
24207 CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 789
24208 CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 790
24209 CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 791
24210 CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 792
24211 CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 793
24212 CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 794
24213 CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 795
24214 CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 796
24215 CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 797
24216 CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 798
24217 CEFBS_HasDSPR2, // ADDUH_QB = 799
24218 CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 800
24219 CEFBS_HasDSPR2, // ADDUH_R_QB = 801
24220 CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 802
24221 CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 803
24222 CEFBS_HasDSPR2, // ADDU_PH = 804
24223 CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 805
24224 CEFBS_HasDSP, // ADDU_QB = 806
24225 CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 807
24226 CEFBS_HasDSPR2, // ADDU_S_PH = 808
24227 CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 809
24228 CEFBS_HasDSP, // ADDU_S_QB = 810
24229 CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 811
24230 CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 812
24231 CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 813
24232 CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 814
24233 CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 815
24234 CEFBS_HasStdEnc_HasMSA, // ADDV_B = 816
24235 CEFBS_HasStdEnc_HasMSA, // ADDV_D = 817
24236 CEFBS_HasStdEnc_HasMSA, // ADDV_H = 818
24237 CEFBS_HasStdEnc_HasMSA, // ADDV_W = 819
24238 CEFBS_HasDSP, // ADDWC = 820
24239 CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 821
24240 CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 822
24241 CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 823
24242 CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 824
24243 CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 825
24244 CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 826
24245 CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 827
24246 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 828
24247 CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 829
24248 CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 830
24249 CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 831
24250 CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 832
24251 CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 833
24252 CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 834
24253 CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 835
24254 CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 836
24255 CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 837
24256 CEFBS_HasStdEnc_NotInMicroMips, // AND = 838
24257 CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 839
24258 CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 840
24259 CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 841
24260 CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 842
24261 CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 843
24262 CEFBS_HasStdEnc_HasMSA, // ANDI_B = 844
24263 CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 845
24264 CEFBS_InMicroMips_NotMips32r6, // AND_MM = 846
24265 CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 847
24266 CEFBS_HasStdEnc_HasMSA, // AND_V = 848
24267 CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 849
24268 CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 850
24269 CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 851
24270 CEFBS_HasDSPR2, // APPEND = 852
24271 CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 853
24272 CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 854
24273 CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 855
24274 CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 856
24275 CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 857
24276 CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 858
24277 CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 859
24278 CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 860
24279 CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 861
24280 CEFBS_HasStdEnc_HasMips32r6, // AUI = 862
24281 CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 863
24282 CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 864
24283 CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 865
24284 CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 866
24285 CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 867
24286 CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 868
24287 CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 869
24288 CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 870
24289 CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 871
24290 CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 872
24291 CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 873
24292 CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 874
24293 CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 875
24294 CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 876
24295 CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 877
24296 CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 878
24297 CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 879
24298 CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 880
24299 CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 881
24300 CEFBS_InMips16Mode, // AddiuRxImmX16 = 882
24301 CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 883
24302 CEFBS_InMips16Mode, // AddiuRxRxImm16 = 884
24303 CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 885
24304 CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 886
24305 CEFBS_InMips16Mode, // AddiuSpImm16 = 887
24306 CEFBS_InMips16Mode, // AddiuSpImmX16 = 888
24307 CEFBS_InMips16Mode, // AdduRxRyRz16 = 889
24308 CEFBS_InMips16Mode, // AndRxRxRy16 = 890
24309 CEFBS_InMicroMips, // B16_MM = 891
24310 CEFBS_HasCnMips, // BADDu = 892
24311 CEFBS_HasStdEnc_HasMips32r6, // BAL = 893
24312 CEFBS_HasStdEnc_HasMips32r6, // BALC = 894
24313 CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 895
24314 CEFBS_HasDSPR2, // BALIGN = 896
24315 CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 897
24316 CEFBS_HasCnMips, // BBIT0 = 898
24317 CEFBS_HasCnMips, // BBIT032 = 899
24318 CEFBS_HasCnMips, // BBIT1 = 900
24319 CEFBS_HasCnMips, // BBIT132 = 901
24320 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 902
24321 CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 903
24322 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 904
24323 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 905
24324 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 906
24325 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 907
24326 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 908
24327 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 909
24328 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 910
24329 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 911
24330 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 912
24331 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 913
24332 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 914
24333 CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 915
24334 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 916
24335 CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 917
24336 CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 918
24337 CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 919
24338 CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 920
24339 CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 921
24340 CEFBS_HasStdEnc_HasMSA, // BCLR_B = 922
24341 CEFBS_HasStdEnc_HasMSA, // BCLR_D = 923
24342 CEFBS_HasStdEnc_HasMSA, // BCLR_H = 924
24343 CEFBS_HasStdEnc_HasMSA, // BCLR_W = 925
24344 CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 926
24345 CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 927
24346 CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 928
24347 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 929
24348 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 930
24349 CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 931
24350 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 932
24351 CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 933
24352 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 934
24353 CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 935
24354 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 936
24355 CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 937
24356 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 938
24357 CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 939
24358 CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 940
24359 CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 941
24360 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 942
24361 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 943
24362 CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 944
24363 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 945
24364 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 946
24365 CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 947
24366 CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 948
24367 CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 949
24368 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 950
24369 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 951
24370 CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 952
24371 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 953
24372 CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 954
24373 CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 955
24374 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 956
24375 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 957
24376 CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 958
24377 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 959
24378 CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 960
24379 CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 961
24380 CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 962
24381 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 963
24382 CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 964
24383 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 965
24384 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 966
24385 CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 967
24386 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 968
24387 CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 969
24388 CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 970
24389 CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 971
24390 CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 972
24391 CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 973
24392 CEFBS_HasStdEnc_HasMSA, // BINSL_B = 974
24393 CEFBS_HasStdEnc_HasMSA, // BINSL_D = 975
24394 CEFBS_HasStdEnc_HasMSA, // BINSL_H = 976
24395 CEFBS_HasStdEnc_HasMSA, // BINSL_W = 977
24396 CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 978
24397 CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 979
24398 CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 980
24399 CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 981
24400 CEFBS_HasStdEnc_HasMSA, // BINSR_B = 982
24401 CEFBS_HasStdEnc_HasMSA, // BINSR_D = 983
24402 CEFBS_HasStdEnc_HasMSA, // BINSR_H = 984
24403 CEFBS_HasStdEnc_HasMSA, // BINSR_W = 985
24404 CEFBS_HasDSP, // BITREV = 986
24405 CEFBS_InMicroMips_HasDSP, // BITREV_MM = 987
24406 CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 988
24407 CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 989
24408 CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 990
24409 CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 991
24410 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 992
24411 CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 993
24412 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 994
24413 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 995
24414 CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 996
24415 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 997
24416 CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 998
24417 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 999
24418 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 1000
24419 CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 1001
24420 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 1002
24421 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 1003
24422 CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 1004
24423 CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 1005
24424 CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 1006
24425 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 1007
24426 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 1008
24427 CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 1009
24428 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 1010
24429 CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 1011
24430 CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 1012
24431 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 1013
24432 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 1014
24433 CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 1015
24434 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 1016
24435 CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 1017
24436 CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 1018
24437 CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 1019
24438 CEFBS_HasStdEnc_HasMSA, // BMZI_B = 1020
24439 CEFBS_HasStdEnc_HasMSA, // BMZ_V = 1021
24440 CEFBS_HasStdEnc_NotInMicroMips, // BNE = 1022
24441 CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 1023
24442 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 1024
24443 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 1025
24444 CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 1026
24445 CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 1027
24446 CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 1028
24447 CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 1029
24448 CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 1030
24449 CEFBS_HasStdEnc_HasMSA, // BNEG_B = 1031
24450 CEFBS_HasStdEnc_HasMSA, // BNEG_D = 1032
24451 CEFBS_HasStdEnc_HasMSA, // BNEG_H = 1033
24452 CEFBS_HasStdEnc_HasMSA, // BNEG_W = 1034
24453 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 1035
24454 CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 1036
24455 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 1037
24456 CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 1038
24457 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1039
24458 CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1040
24459 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1041
24460 CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1042
24461 CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1043
24462 CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1044
24463 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1045
24464 CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1046
24465 CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1047
24466 CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1048
24467 CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1049
24468 CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1050
24469 CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1051
24470 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1052
24471 CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1053
24472 CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1054
24473 CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1055
24474 CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1056
24475 CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1057
24476 CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1058
24477 CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1059
24478 CEFBS_InMicroMips, // BREAK_MM = 1060
24479 CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1061
24480 CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1062
24481 CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1063
24482 CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1064
24483 CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1065
24484 CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1066
24485 CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1067
24486 CEFBS_HasStdEnc_HasMSA, // BSET_B = 1068
24487 CEFBS_HasStdEnc_HasMSA, // BSET_D = 1069
24488 CEFBS_HasStdEnc_HasMSA, // BSET_H = 1070
24489 CEFBS_HasStdEnc_HasMSA, // BSET_W = 1071
24490 CEFBS_HasStdEnc_HasMSA, // BZ_B = 1072
24491 CEFBS_HasStdEnc_HasMSA, // BZ_D = 1073
24492 CEFBS_HasStdEnc_HasMSA, // BZ_H = 1074
24493 CEFBS_HasStdEnc_HasMSA, // BZ_V = 1075
24494 CEFBS_HasStdEnc_HasMSA, // BZ_W = 1076
24495 CEFBS_InMips16Mode, // BeqzRxImm16 = 1077
24496 CEFBS_InMips16Mode, // BeqzRxImmX16 = 1078
24497 CEFBS_InMips16Mode, // Bimm16 = 1079
24498 CEFBS_InMips16Mode, // BimmX16 = 1080
24499 CEFBS_InMips16Mode, // BnezRxImm16 = 1081
24500 CEFBS_InMips16Mode, // BnezRxImmX16 = 1082
24501 CEFBS_InMips16Mode, // Break16 = 1083
24502 CEFBS_InMips16Mode, // Bteqz16 = 1084
24503 CEFBS_InMips16Mode, // BteqzX16 = 1085
24504 CEFBS_InMips16Mode, // Btnez16 = 1086
24505 CEFBS_InMips16Mode, // BtnezX16 = 1087
24506 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1088
24507 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1089
24508 CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1090
24509 CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1091
24510 CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1092
24511 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1093
24512 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1094
24513 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1095
24514 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1096
24515 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1097
24516 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1098
24517 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1099
24518 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1100
24519 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1101
24520 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1102
24521 CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1103
24522 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1104
24523 CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1105
24524 CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1106
24525 CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1107
24526 CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1108
24527 CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1109
24528 CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1110
24529 CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1111
24530 CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1112
24531 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1113
24532 CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1114
24533 CEFBS_InMicroMips, // CFC2_MM = 1115
24534 CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1116
24535 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1117
24536 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1118
24537 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1119
24538 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1120
24539 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1121
24540 CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1122
24541 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1123
24542 CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1124
24543 CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1125
24544 CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1126
24545 CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1127
24546 CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1128
24547 CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1129
24548 CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1130
24549 CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1131
24550 CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1132
24551 CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1133
24552 CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1134
24553 CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1135
24554 CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1136
24555 CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1137
24556 CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1138
24557 CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1139
24558 CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1140
24559 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1141
24560 CEFBS_InMicroMips, // CLO_MM = 1142
24561 CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1143
24562 CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1144
24563 CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1145
24564 CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1146
24565 CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1147
24566 CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1148
24567 CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1149
24568 CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1150
24569 CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1151
24570 CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1152
24571 CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1153
24572 CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1154
24573 CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1155
24574 CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1156
24575 CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1157
24576 CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1158
24577 CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1159
24578 CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1160
24579 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1161
24580 CEFBS_InMicroMips, // CLZ_MM = 1162
24581 CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1163
24582 CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1164
24583 CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1165
24584 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1166
24585 CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1167
24586 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1168
24587 CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1169
24588 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1170
24589 CEFBS_HasDSP, // CMPGU_EQ_QB = 1171
24590 CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1172
24591 CEFBS_HasDSP, // CMPGU_LE_QB = 1173
24592 CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1174
24593 CEFBS_HasDSP, // CMPGU_LT_QB = 1175
24594 CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1176
24595 CEFBS_HasDSP, // CMPU_EQ_QB = 1177
24596 CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1178
24597 CEFBS_HasDSP, // CMPU_LE_QB = 1179
24598 CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1180
24599 CEFBS_HasDSP, // CMPU_LT_QB = 1181
24600 CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1182
24601 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1183
24602 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1184
24603 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1185
24604 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1186
24605 CEFBS_HasDSP, // CMP_EQ_PH = 1187
24606 CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1188
24607 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1189
24608 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1190
24609 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1191
24610 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1192
24611 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1193
24612 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1194
24613 CEFBS_HasDSP, // CMP_LE_PH = 1195
24614 CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1196
24615 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1197
24616 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1198
24617 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1199
24618 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1200
24619 CEFBS_HasDSP, // CMP_LT_PH = 1201
24620 CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1202
24621 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1203
24622 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1204
24623 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1205
24624 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1206
24625 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1207
24626 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1208
24627 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1209
24628 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1210
24629 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1211
24630 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1212
24631 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1213
24632 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1214
24633 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1215
24634 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1216
24635 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1217
24636 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1218
24637 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1219
24638 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1220
24639 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1221
24640 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1222
24641 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1223
24642 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1224
24643 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1225
24644 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1226
24645 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1227
24646 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1228
24647 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1229
24648 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1230
24649 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1231
24650 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1232
24651 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1233
24652 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1234
24653 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1235
24654 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1236
24655 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1237
24656 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1238
24657 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1239
24658 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1240
24659 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1241
24660 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1242
24661 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1243
24662 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1244
24663 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1245
24664 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1246
24665 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1247
24666 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1248
24667 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1249
24668 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1250
24669 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1251
24670 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1252
24671 CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1253
24672 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1254
24673 CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1255
24674 CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1256
24675 CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1257
24676 CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1258
24677 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1259
24678 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1260
24679 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1261
24680 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1262
24681 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1263
24682 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1264
24683 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1265
24684 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1266
24685 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1267
24686 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1268
24687 CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1269
24688 CEFBS_InMicroMips, // CTC2_MM = 1270
24689 CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1271
24690 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1272
24691 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1273
24692 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1274
24693 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1275
24694 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1276
24695 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1277
24696 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1278
24697 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1279
24698 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1280
24699 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1281
24700 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1282
24701 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1283
24702 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1284
24703 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1285
24704 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1286
24705 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1287
24706 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1288
24707 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1289
24708 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1290
24709 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1291
24710 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1292
24711 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1293
24712 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1294
24713 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1295
24714 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1296
24715 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1297
24716 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1298
24717 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1299
24718 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1300
24719 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1301
24720 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1302
24721 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1303
24722 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1304
24723 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1305
24724 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1306
24725 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1307
24726 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1308
24727 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1309
24728 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1310
24729 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1311
24730 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1312
24731 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1313
24732 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1314
24733 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1315
24734 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1316
24735 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1317
24736 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1318
24737 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1319
24738 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1320
24739 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1321
24740 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1322
24741 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1323
24742 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1324
24743 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1325
24744 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1326
24745 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1327
24746 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1328
24747 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1329
24748 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1330
24749 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1331
24750 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1332
24751 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1333
24752 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1334
24753 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1335
24754 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1336
24755 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1337
24756 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1338
24757 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1339
24758 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1340
24759 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1341
24760 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1342
24761 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1343
24762 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1344
24763 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1345
24764 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1346
24765 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1347
24766 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1348
24767 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1349
24768 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1350
24769 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1351
24770 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1352
24771 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1353
24772 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1354
24773 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1355
24774 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1356
24775 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1357
24776 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1358
24777 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1359
24778 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1360
24779 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1361
24780 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1362
24781 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1363
24782 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1364
24783 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1365
24784 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1366
24785 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1367
24786 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1368
24787 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1369
24788 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1370
24789 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1371
24790 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1372
24791 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1373
24792 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1374
24793 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1375
24794 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1376
24795 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1377
24796 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1378
24797 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1379
24798 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1380
24799 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1381
24800 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1382
24801 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1383
24802 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1384
24803 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1385
24804 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1386
24805 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1387
24806 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1388
24807 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1389
24808 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1390
24809 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1391
24810 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1392
24811 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1393
24812 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1394
24813 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1395
24814 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1396
24815 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1397
24816 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1398
24817 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1399
24818 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1400
24819 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1401
24820 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1402
24821 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1403
24822 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1404
24823 CEFBS_InMips16Mode, // CmpRxRy16 = 1405
24824 CEFBS_InMips16Mode, // CmpiRxImm16 = 1406
24825 CEFBS_InMips16Mode, // CmpiRxImmX16 = 1407
24826 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1408
24827 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1409
24828 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1410
24829 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1411
24830 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1412
24831 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1413
24832 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1414
24833 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1415
24834 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1416
24835 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1417
24836 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1418
24837 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1419
24838 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1420
24839 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1421
24840 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1422
24841 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1423
24842 CEFBS_InMicroMips, // DERET_MM = 1424
24843 CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1425
24844 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1426
24845 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1427
24846 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1428
24847 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1429
24848 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1430
24849 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1431
24850 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1432
24851 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1433
24852 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1434
24853 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1435
24854 CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1436
24855 CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1437
24856 CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1438
24857 CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1439
24858 CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1440
24859 CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1441
24860 CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1442
24861 CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1443
24862 CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1444
24863 CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1445
24864 CEFBS_InMicroMips, // DI_MM = 1446
24865 CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1447
24866 CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1448
24867 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1449
24868 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1450
24869 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1451
24870 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1452
24871 CEFBS_HasCnMips, // DMFC2_OCTEON = 1453
24872 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1454
24873 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1455
24874 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1456
24875 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1457
24876 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1458
24877 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1459
24878 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1460
24879 CEFBS_HasCnMips, // DMTC2_OCTEON = 1461
24880 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1462
24881 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1463
24882 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1464
24883 CEFBS_HasCnMips, // DMUL = 1465
24884 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1466
24885 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1467
24886 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1468
24887 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1469
24888 CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1470
24889 CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1471
24890 CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1472
24891 CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1473
24892 CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1474
24893 CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1475
24894 CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1476
24895 CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1477
24896 CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1478
24897 CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1479
24898 CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1480
24899 CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1481
24900 CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1482
24901 CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1483
24902 CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1484
24903 CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1485
24904 CEFBS_HasDSP, // DPAQ_SA_L_W = 1486
24905 CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1487
24906 CEFBS_HasDSP, // DPAQ_S_W_PH = 1488
24907 CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1489
24908 CEFBS_HasDSP, // DPAU_H_QBL = 1490
24909 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1491
24910 CEFBS_HasDSP, // DPAU_H_QBR = 1492
24911 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1493
24912 CEFBS_HasDSPR2, // DPAX_W_PH = 1494
24913 CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1495
24914 CEFBS_HasDSPR2, // DPA_W_PH = 1496
24915 CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1497
24916 CEFBS_HasCnMips, // DPOP = 1498
24917 CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1499
24918 CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1500
24919 CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1501
24920 CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1502
24921 CEFBS_HasDSP, // DPSQ_SA_L_W = 1503
24922 CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1504
24923 CEFBS_HasDSP, // DPSQ_S_W_PH = 1505
24924 CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1506
24925 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1507
24926 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1508
24927 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1509
24928 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1510
24929 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1511
24930 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1512
24931 CEFBS_HasDSP, // DPSU_H_QBL = 1513
24932 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1514
24933 CEFBS_HasDSP, // DPSU_H_QBR = 1515
24934 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1516
24935 CEFBS_HasDSPR2, // DPSX_W_PH = 1517
24936 CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1518
24937 CEFBS_HasDSPR2, // DPS_W_PH = 1519
24938 CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1520
24939 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1521
24940 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1522
24941 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1523
24942 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1524
24943 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1525
24944 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1526
24945 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1527
24946 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1528
24947 CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1529
24948 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1530
24949 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1531
24950 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1532
24951 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1533
24952 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1534
24953 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1535
24954 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1536
24955 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1537
24956 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1538
24957 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1539
24958 CEFBS_HasStdEnc_HasMips32r6, // DVP = 1540
24959 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1541
24960 CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1542
24961 CEFBS_InMips16Mode, // DivRxRy16 = 1543
24962 CEFBS_InMips16Mode, // DivuRxRy16 = 1544
24963 CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1545
24964 CEFBS_InMicroMips, // EHB_MM = 1546
24965 CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1547
24966 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1548
24967 CEFBS_InMicroMips, // EI_MM = 1549
24968 CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1550
24969 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1551
24970 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1552
24971 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1553
24972 CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1554
24973 CEFBS_InMicroMips, // ERET_MM = 1555
24974 CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1556
24975 CEFBS_HasStdEnc_HasMips32r6, // EVP = 1557
24976 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1558
24977 CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1559
24978 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1560
24979 CEFBS_HasDSP, // EXTP = 1561
24980 CEFBS_HasDSP, // EXTPDP = 1562
24981 CEFBS_HasDSP, // EXTPDPV = 1563
24982 CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1564
24983 CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1565
24984 CEFBS_HasDSP, // EXTPV = 1566
24985 CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1567
24986 CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1568
24987 CEFBS_HasDSP, // EXTRV_RS_W = 1569
24988 CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1570
24989 CEFBS_HasDSP, // EXTRV_R_W = 1571
24990 CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1572
24991 CEFBS_HasDSP, // EXTRV_S_H = 1573
24992 CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1574
24993 CEFBS_HasDSP, // EXTRV_W = 1575
24994 CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1576
24995 CEFBS_HasDSP, // EXTR_RS_W = 1577
24996 CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1578
24997 CEFBS_HasDSP, // EXTR_R_W = 1579
24998 CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1580
24999 CEFBS_HasDSP, // EXTR_S_H = 1581
25000 CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1582
25001 CEFBS_HasDSP, // EXTR_W = 1583
25002 CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1584
25003 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1585
25004 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1586
25005 CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1587
25006 CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1588
25007 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1589
25008 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1590
25009 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1591
25010 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1592
25011 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1593
25012 CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1594
25013 CEFBS_HasStdEnc_HasMSA, // FADD_D = 1595
25014 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1596
25015 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1597
25016 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1598
25017 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1599
25018 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1600
25019 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1601
25020 CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1602
25021 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1603
25022 CEFBS_HasStdEnc_HasMSA, // FADD_W = 1604
25023 CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1605
25024 CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1606
25025 CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1607
25026 CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1608
25027 CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1609
25028 CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1610
25029 CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1611
25030 CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1612
25031 CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1613
25032 CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1614
25033 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1615
25034 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1616
25035 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1617
25036 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1618
25037 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1619
25038 CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1620
25039 CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1621
25040 CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1622
25041 CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1623
25042 CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1624
25043 CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1625
25044 CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1626
25045 CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1627
25046 CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1628
25047 CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1629
25048 CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1630
25049 CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1631
25050 CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1632
25051 CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1633
25052 CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1634
25053 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1635
25054 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1636
25055 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1637
25056 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1638
25057 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1639
25058 CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1640
25059 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1641
25060 CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1642
25061 CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1643
25062 CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1644
25063 CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1645
25064 CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1646
25065 CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1647
25066 CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1648
25067 CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1649
25068 CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1650
25069 CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1651
25070 CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1652
25071 CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1653
25072 CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1654
25073 CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1655
25074 CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1656
25075 CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1657
25076 CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1658
25077 CEFBS_HasStdEnc_HasMSA, // FILL_B = 1659
25078 CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1660
25079 CEFBS_HasStdEnc_HasMSA, // FILL_H = 1661
25080 CEFBS_HasStdEnc_HasMSA, // FILL_W = 1662
25081 CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1663
25082 CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1664
25083 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1665
25084 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1666
25085 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1667
25086 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1668
25087 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1669
25088 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1670
25089 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1671
25090 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1672
25091 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1673
25092 CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1674
25093 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1675
25094 CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1676
25095 CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1677
25096 CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1678
25097 CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1679
25098 CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1680
25099 CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1681
25100 CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1682
25101 CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1683
25102 CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1684
25103 CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1685
25104 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1686
25105 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1687
25106 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1688
25107 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1689
25108 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1690
25109 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1691
25110 CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1692
25111 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1693
25112 CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1694
25113 CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1695
25114 CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1696
25115 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1697
25116 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1698
25117 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1699
25118 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1700
25119 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1701
25120 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1702
25121 CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1703
25122 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1704
25123 CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1705
25124 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1706
25125 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1707
25126 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1708
25127 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1709
25128 CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1710
25129 CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1711
25130 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1712
25131 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1713
25132 CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1714
25133 CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1715
25134 CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1716
25135 CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1717
25136 CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1718
25137 CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1719
25138 CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1720
25139 CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1721
25140 CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1722
25141 CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1723
25142 CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1724
25143 CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1725
25144 CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1726
25145 CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1727
25146 CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1728
25147 CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1729
25148 CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1730
25149 CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1731
25150 CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1732
25151 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1733
25152 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1734
25153 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1735
25154 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1736
25155 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1737
25156 CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1738
25157 CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1739
25158 CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1740
25159 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1741
25160 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1742
25161 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1743
25162 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1744
25163 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1745
25164 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1746
25165 CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1747
25166 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1748
25167 CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1749
25168 CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1750
25169 CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1751
25170 CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1752
25171 CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1753
25172 CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1754
25173 CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1755
25174 CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1756
25175 CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1757
25176 CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1758
25177 CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1759
25178 CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1760
25179 CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1761
25180 CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1762
25181 CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1763
25182 CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1764
25183 CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1765
25184 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1766
25185 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1767
25186 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1768
25187 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1769
25188 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1770
25189 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1771
25190 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1772
25191 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1773
25192 CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1774
25193 CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1775
25194 CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1776
25195 CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1777
25196 CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1778
25197 CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1779
25198 CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1780
25199 CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1781
25200 CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1782
25201 CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1783
25202 CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1784
25203 CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1785
25204 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1786
25205 CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1787
25206 CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1788
25207 CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1789
25208 CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1790
25209 CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1791
25210 CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1792
25211 CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1793
25212 CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1794
25213 CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1795
25214 CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1796
25215 CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1797
25216 CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1798
25217 CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1799
25218 CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1800
25219 CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1801
25220 CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1802
25221 CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1803
25222 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1804
25223 CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1805
25224 CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1806
25225 CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1807
25226 CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1808
25227 CEFBS_HasDSP, // INSV = 1809
25228 CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1810
25229 CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1811
25230 CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1812
25231 CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1813
25232 CEFBS_InMicroMips_HasDSP, // INSV_MM = 1814
25233 CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1815
25234 CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1816
25235 CEFBS_HasStdEnc_NotInMicroMips, // J = 1817
25236 CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1818
25237 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1819
25238 CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1820
25239 CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1821
25240 CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1822
25241 CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1823
25242 CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1824
25243 CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1825
25244 CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1826
25245 CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1827
25246 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1828
25247 CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1829
25248 CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1830
25249 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1831
25250 CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1832
25251 CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1833
25252 CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1834
25253 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1835
25254 CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1836
25255 CEFBS_HasStdEnc_HasMips32r6, // JIC = 1837
25256 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1838
25257 CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1839
25258 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1840
25259 CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1841
25260 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1842
25261 CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1843
25262 CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1844
25263 CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1845
25264 CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1846
25265 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1847
25266 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1848
25267 CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1849
25268 CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1850
25269 CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1851
25270 CEFBS_InMicroMips_NotMips32r6, // J_MM = 1852
25271 CEFBS_InMips16Mode, // Jal16 = 1853
25272 CEFBS_InMips16Mode, // JalB16 = 1854
25273 CEFBS_InMips16Mode, // JrRa16 = 1855
25274 CEFBS_InMips16Mode, // JrcRa16 = 1856
25275 CEFBS_InMips16Mode, // JrcRx16 = 1857
25276 CEFBS_InMips16Mode, // JumpLinkReg16 = 1858
25277 CEFBS_HasStdEnc_NotInMicroMips, // LB = 1859
25278 CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1860
25279 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1861
25280 CEFBS_InMicroMips_HasEVA, // LBE_MM = 1862
25281 CEFBS_InMicroMips, // LBU16_MM = 1863
25282 CEFBS_HasDSP, // LBUX = 1864
25283 CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1865
25284 CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1866
25285 CEFBS_InMicroMips, // LB_MM = 1867
25286 CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1868
25287 CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1869
25288 CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1870
25289 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1871
25290 CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1872
25291 CEFBS_InMicroMips, // LBu_MM = 1873
25292 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1874
25293 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1875
25294 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1876
25295 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1877
25296 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1878
25297 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1879
25298 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1880
25299 CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1881
25300 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1882
25301 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1883
25302 CEFBS_HasStdEnc_HasMSA, // LDI_B = 1884
25303 CEFBS_HasStdEnc_HasMSA, // LDI_D = 1885
25304 CEFBS_HasStdEnc_HasMSA, // LDI_H = 1886
25305 CEFBS_HasStdEnc_HasMSA, // LDI_W = 1887
25306 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1888
25307 CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1889
25308 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1890
25309 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1891
25310 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1892
25311 CEFBS_HasStdEnc_HasMSA, // LD_B = 1893
25312 CEFBS_HasStdEnc_HasMSA, // LD_D = 1894
25313 CEFBS_HasStdEnc_HasMSA, // LD_H = 1895
25314 CEFBS_HasStdEnc_HasMSA, // LD_W = 1896
25315 CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1897
25316 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1898
25317 CEFBS_InMicroMips, // LEA_ADDiu_MM = 1899
25318 CEFBS_HasStdEnc_NotInMicroMips, // LH = 1900
25319 CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1901
25320 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1902
25321 CEFBS_InMicroMips_HasEVA, // LHE_MM = 1903
25322 CEFBS_InMicroMips, // LHU16_MM = 1904
25323 CEFBS_HasDSP, // LHX = 1905
25324 CEFBS_InMicroMips_HasDSP, // LHX_MM = 1906
25325 CEFBS_InMicroMips, // LH_MM = 1907
25326 CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1908
25327 CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1909
25328 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1910
25329 CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1911
25330 CEFBS_InMicroMips, // LHu_MM = 1912
25331 CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1913
25332 CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1914
25333 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1915
25334 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1916
25335 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1917
25336 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1918
25337 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1919
25338 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1920
25339 CEFBS_InMicroMips_HasEVA, // LLE_MM = 1921
25340 CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1922
25341 CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1923
25342 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1924
25343 CEFBS_HasStdEnc_HasMSA, // LSA = 1925
25344 CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1926
25345 CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1927
25346 CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1928
25347 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1929
25348 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1930
25349 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1931
25350 CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1932
25351 CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1933
25352 CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1934
25353 CEFBS_HasStdEnc_NotInMicroMips, // LW = 1935
25354 CEFBS_InMicroMips, // LW16_MM = 1936
25355 CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1937
25356 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1938
25357 CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1939
25358 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1940
25359 CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1941
25360 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1942
25361 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1943
25362 CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1944
25363 CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1945
25364 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1946
25365 CEFBS_InMicroMips_HasEVA, // LWE_MM = 1947
25366 CEFBS_InMicroMips, // LWGP_MM = 1948
25367 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1949
25368 CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1950
25369 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1951
25370 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1952
25371 CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1953
25372 CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1954
25373 CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1955
25374 CEFBS_InMicroMips, // LWM32_MM = 1956
25375 CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1957
25376 CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1958
25377 CEFBS_InMicroMips, // LWP_MM = 1959
25378 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1960
25379 CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1961
25380 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1962
25381 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1963
25382 CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1964
25383 CEFBS_InMicroMips, // LWSP_MM = 1965
25384 CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1966
25385 CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1967
25386 CEFBS_HasDSP, // LWX = 1968
25387 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1969
25388 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1970
25389 CEFBS_InMicroMips, // LWXS_MM = 1971
25390 CEFBS_InMicroMips_HasDSP, // LWX_MM = 1972
25391 CEFBS_InMicroMips, // LW_MM = 1973
25392 CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1974
25393 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1975
25394 CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1976
25395 CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1977
25396 CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1978
25397 CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1979
25398 CEFBS_InMips16Mode, // LiRxImm16 = 1980
25399 CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1981
25400 CEFBS_InMips16Mode, // LiRxImmX16 = 1982
25401 CEFBS_InMips16Mode, // LwRxPcTcp16 = 1983
25402 CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1984
25403 CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1985
25404 CEFBS_InMips16Mode, // LwRxSpImmX16 = 1986
25405 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1987
25406 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1988
25407 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1989
25408 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1990
25409 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1991
25410 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1992
25411 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1993
25412 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1994
25413 CEFBS_HasDSP, // MADDU_DSP = 1995
25414 CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1996
25415 CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1997
25416 CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1998
25417 CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1999
25418 CEFBS_HasStdEnc_HasMSA, // MADDV_H = 2000
25419 CEFBS_HasStdEnc_HasMSA, // MADDV_W = 2001
25420 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 2002
25421 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 2003
25422 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 2004
25423 CEFBS_HasDSP, // MADD_DSP = 2005
25424 CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 2006
25425 CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 2007
25426 CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 2008
25427 CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 2009
25428 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 2010
25429 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 2011
25430 CEFBS_HasDSP, // MAQ_SA_W_PHL = 2012
25431 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 2013
25432 CEFBS_HasDSP, // MAQ_SA_W_PHR = 2014
25433 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 2015
25434 CEFBS_HasDSP, // MAQ_S_W_PHL = 2016
25435 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 2017
25436 CEFBS_HasDSP, // MAQ_S_W_PHR = 2018
25437 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 2019
25438 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 2020
25439 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 2021
25440 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 2022
25441 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 2023
25442 CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 2024
25443 CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 2025
25444 CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 2026
25445 CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 2027
25446 CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 2028
25447 CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 2029
25448 CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 2030
25449 CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 2031
25450 CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 2032
25451 CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 2033
25452 CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 2034
25453 CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 2035
25454 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 2036
25455 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 2037
25456 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 2038
25457 CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2039
25458 CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2040
25459 CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2041
25460 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2042
25461 CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2043
25462 CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2044
25463 CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2045
25464 CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2046
25465 CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2047
25466 CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2048
25467 CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2049
25468 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2050
25469 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2051
25470 CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2052
25471 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2053
25472 CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2054
25473 CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2055
25474 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2056
25475 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2057
25476 CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2058
25477 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2059
25478 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2060
25479 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2061
25480 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2062
25481 CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2063
25482 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2064
25483 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2065
25484 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2066
25485 CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2067
25486 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2068
25487 CEFBS_HasDSP, // MFHI_DSP = 2069
25488 CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2070
25489 CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2071
25490 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2072
25491 CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2073
25492 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2074
25493 CEFBS_HasDSP, // MFLO_DSP = 2075
25494 CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2076
25495 CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2077
25496 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2078
25497 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2079
25498 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2080
25499 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2081
25500 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2082
25501 CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2083
25502 CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2084
25503 CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2085
25504 CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2086
25505 CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2087
25506 CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2088
25507 CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2089
25508 CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2090
25509 CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2091
25510 CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2092
25511 CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2093
25512 CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2094
25513 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2095
25514 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2096
25515 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2097
25516 CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2098
25517 CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2099
25518 CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2100
25519 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2101
25520 CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2102
25521 CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2103
25522 CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2104
25523 CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2105
25524 CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2106
25525 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2107
25526 CEFBS_HasDSP, // MODSUB = 2108
25527 CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2109
25528 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2110
25529 CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2111
25530 CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2112
25531 CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2113
25532 CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2114
25533 CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2115
25534 CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2116
25535 CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2117
25536 CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2118
25537 CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2119
25538 CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2120
25539 CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2121
25540 CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2122
25541 CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2123
25542 CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2124
25543 CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2125
25544 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2126
25545 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2127
25546 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2128
25547 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2129
25548 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2130
25549 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2131
25550 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2132
25551 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2133
25552 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2134
25553 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2135
25554 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2136
25555 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2137
25556 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2138
25557 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2139
25558 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2140
25559 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2141
25560 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2142
25561 CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2143
25562 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2144
25563 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2145
25564 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2146
25565 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2147
25566 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2148
25567 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2149
25568 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2150
25569 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2151
25570 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2152
25571 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2153
25572 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2154
25573 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2155
25574 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2156
25575 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2157
25576 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2158
25577 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2159
25578 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2160
25579 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2161
25580 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2162
25581 CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2163
25582 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2164
25583 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2165
25584 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2166
25585 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2167
25586 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2168
25587 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2169
25588 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2170
25589 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2171
25590 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2172
25591 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2173
25592 CEFBS_HasDSP, // MSUBU_DSP = 2174
25593 CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2175
25594 CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2176
25595 CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2177
25596 CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2178
25597 CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2179
25598 CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2180
25599 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2181
25600 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2182
25601 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2183
25602 CEFBS_HasDSP, // MSUB_DSP = 2184
25603 CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2185
25604 CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2186
25605 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2187
25606 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2188
25607 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2189
25608 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2190
25609 CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2191
25610 CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2192
25611 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2193
25612 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2194
25613 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2195
25614 CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2196
25615 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2197
25616 CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2198
25617 CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2199
25618 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2200
25619 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2201
25620 CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2202
25621 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2203
25622 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2204
25623 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2205
25624 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2206
25625 CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2207
25626 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2208
25627 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2209
25628 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2210
25629 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2211
25630 CEFBS_HasDSP, // MTHI_DSP = 2212
25631 CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2213
25632 CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2214
25633 CEFBS_HasDSP, // MTHLIP = 2215
25634 CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2216
25635 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2217
25636 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2218
25637 CEFBS_HasDSP, // MTLO_DSP = 2219
25638 CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2220
25639 CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2221
25640 CEFBS_HasCnMips, // MTM0 = 2222
25641 CEFBS_HasCnMips, // MTM1 = 2223
25642 CEFBS_HasCnMips, // MTM2 = 2224
25643 CEFBS_HasCnMips, // MTP0 = 2225
25644 CEFBS_HasCnMips, // MTP1 = 2226
25645 CEFBS_HasCnMips, // MTP2 = 2227
25646 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2228
25647 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2229
25648 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2230
25649 CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2231
25650 CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2232
25651 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2233
25652 CEFBS_HasDSP, // MULEQ_S_W_PHL = 2234
25653 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2235
25654 CEFBS_HasDSP, // MULEQ_S_W_PHR = 2236
25655 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2237
25656 CEFBS_HasDSP, // MULEU_S_PH_QBL = 2238
25657 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2239
25658 CEFBS_HasDSP, // MULEU_S_PH_QBR = 2240
25659 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2241
25660 CEFBS_HasDSP, // MULQ_RS_PH = 2242
25661 CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2243
25662 CEFBS_HasDSPR2, // MULQ_RS_W = 2244
25663 CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2245
25664 CEFBS_HasDSPR2, // MULQ_S_PH = 2246
25665 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2247
25666 CEFBS_HasDSPR2, // MULQ_S_W = 2248
25667 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2249
25668 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2250
25669 CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2251
25670 CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2252
25671 CEFBS_HasDSP, // MULSAQ_S_W_PH = 2253
25672 CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2254
25673 CEFBS_HasDSPR2, // MULSA_W_PH = 2255
25674 CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2256
25675 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2257
25676 CEFBS_HasDSP, // MULTU_DSP = 2258
25677 CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2259
25678 CEFBS_HasDSP, // MULT_DSP = 2260
25679 CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2261
25680 CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2262
25681 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2263
25682 CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2264
25683 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2265
25684 CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2266
25685 CEFBS_HasStdEnc_HasMSA, // MULV_B = 2267
25686 CEFBS_HasStdEnc_HasMSA, // MULV_D = 2268
25687 CEFBS_HasStdEnc_HasMSA, // MULV_H = 2269
25688 CEFBS_HasStdEnc_HasMSA, // MULV_W = 2270
25689 CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2271
25690 CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2272
25691 CEFBS_HasDSPR2, // MUL_PH = 2273
25692 CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2274
25693 CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2275
25694 CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2276
25695 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2277
25696 CEFBS_HasDSPR2, // MUL_S_PH = 2278
25697 CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2279
25698 CEFBS_InMips16Mode, // Mfhi16 = 2280
25699 CEFBS_InMips16Mode, // Mflo16 = 2281
25700 CEFBS_InMips16Mode, // Move32R16 = 2282
25701 CEFBS_InMips16Mode, // MoveR3216 = 2283
25702 CEFBS_HasStdEnc_HasMips32r6, // NAL = 2284
25703 CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2285
25704 CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2286
25705 CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2287
25706 CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2288
25707 CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2289
25708 CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2290
25709 CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2291
25710 CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2292
25711 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2293
25712 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2294
25713 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2295
25714 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2296
25715 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2297
25716 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2298
25717 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2299
25718 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2300
25719 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2301
25720 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2302
25721 CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2303
25722 CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2304
25723 CEFBS_HasStdEnc_HasMSA, // NORI_B = 2305
25724 CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2306
25725 CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2307
25726 CEFBS_HasStdEnc_HasMSA, // NOR_V = 2308
25727 CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2309
25728 CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2310
25729 CEFBS_InMips16Mode, // NegRxRy16 = 2311
25730 CEFBS_InMips16Mode, // NotRxRy16 = 2312
25731 CEFBS_HasStdEnc_NotInMicroMips, // OR = 2313
25732 CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2314
25733 CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2315
25734 CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2316
25735 CEFBS_HasStdEnc_HasMSA, // ORI_B = 2317
25736 CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2318
25737 CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2319
25738 CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2320
25739 CEFBS_HasStdEnc_HasMSA, // OR_V = 2321
25740 CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2322
25741 CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2323
25742 CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2324
25743 CEFBS_InMips16Mode, // OrRxRxRy16 = 2325
25744 CEFBS_HasDSP, // PACKRL_PH = 2326
25745 CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2327
25746 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2328
25747 CEFBS_InMicroMips, // PAUSE_MM = 2329
25748 CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2330
25749 CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2331
25750 CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2332
25751 CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2333
25752 CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2334
25753 CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2335
25754 CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2336
25755 CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2337
25756 CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2338
25757 CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2339
25758 CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2340
25759 CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2341
25760 CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2342
25761 CEFBS_HasDSP, // PICK_PH = 2343
25762 CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2344
25763 CEFBS_HasDSP, // PICK_QB = 2345
25764 CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2346
25765 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2347
25766 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2348
25767 CEFBS_HasCnMips, // POP = 2349
25768 CEFBS_HasDSP, // PRECEQU_PH_QBL = 2350
25769 CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2351
25770 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2352
25771 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2353
25772 CEFBS_HasDSP, // PRECEQU_PH_QBR = 2354
25773 CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2355
25774 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2356
25775 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2357
25776 CEFBS_HasDSP, // PRECEQ_W_PHL = 2358
25777 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2359
25778 CEFBS_HasDSP, // PRECEQ_W_PHR = 2360
25779 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2361
25780 CEFBS_HasDSP, // PRECEU_PH_QBL = 2362
25781 CEFBS_HasDSP, // PRECEU_PH_QBLA = 2363
25782 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2364
25783 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2365
25784 CEFBS_HasDSP, // PRECEU_PH_QBR = 2366
25785 CEFBS_HasDSP, // PRECEU_PH_QBRA = 2367
25786 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2368
25787 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2369
25788 CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2370
25789 CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2371
25790 CEFBS_HasDSP, // PRECRQ_PH_W = 2372
25791 CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2373
25792 CEFBS_HasDSP, // PRECRQ_QB_PH = 2374
25793 CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2375
25794 CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2376
25795 CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2377
25796 CEFBS_HasDSPR2, // PRECR_QB_PH = 2378
25797 CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2379
25798 CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2380
25799 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2381
25800 CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2382
25801 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2383
25802 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2384
25803 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2385
25804 CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2386
25805 CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2387
25806 CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2388
25807 CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2389
25808 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2390
25809 CEFBS_HasDSPR2, // PREPEND = 2391
25810 CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2392
25811 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2393
25812 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2394
25813 CEFBS_HasDSP, // RADDU_W_QB = 2395
25814 CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2396
25815 CEFBS_HasDSP, // RDDSP = 2397
25816 CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2398
25817 CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2399
25818 CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2400
25819 CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2401
25820 CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2402
25821 CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2403
25822 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2404
25823 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2405
25824 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2406
25825 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2407
25826 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2408
25827 CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2409
25828 CEFBS_HasDSP, // REPLV_PH = 2410
25829 CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2411
25830 CEFBS_HasDSP, // REPLV_QB = 2412
25831 CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2413
25832 CEFBS_HasDSP, // REPL_PH = 2414
25833 CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2415
25834 CEFBS_HasDSP, // REPL_QB = 2416
25835 CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2417
25836 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2418
25837 CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2419
25838 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2420
25839 CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2421
25840 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2422
25841 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2423
25842 CEFBS_InMicroMips, // ROTRV_MM = 2424
25843 CEFBS_InMicroMips, // ROTR_MM = 2425
25844 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2426
25845 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2427
25846 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2428
25847 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2429
25848 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2430
25849 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2431
25850 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2432
25851 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2433
25852 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2434
25853 CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2435
25854 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2436
25855 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2437
25856 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2438
25857 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2439
25858 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2440
25859 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2441
25860 CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2442
25861 CEFBS_InMips16Mode, // Restore16 = 2443
25862 CEFBS_InMips16Mode, // RestoreX16 = 2444
25863 CEFBS_HasCnMipsP, // SAA = 2445
25864 CEFBS_HasCnMipsP, // SAAD = 2446
25865 CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2447
25866 CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2448
25867 CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2449
25868 CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2450
25869 CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2451
25870 CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2452
25871 CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2453
25872 CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2454
25873 CEFBS_HasStdEnc_NotInMicroMips, // SB = 2455
25874 CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2456
25875 CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2457
25876 CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2458
25877 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2459
25878 CEFBS_InMicroMips_HasEVA, // SBE_MM = 2460
25879 CEFBS_InMicroMips, // SB_MM = 2461
25880 CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2462
25881 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2463
25882 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2464
25883 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2465
25884 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2466
25885 CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2467
25886 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2468
25887 CEFBS_InMicroMips_HasEVA, // SCE_MM = 2469
25888 CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2470
25889 CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2471
25890 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2472
25891 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2473
25892 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2474
25893 CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2475
25894 CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2476
25895 CEFBS_InMicroMips, // SDBBP_MM = 2477
25896 CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2478
25897 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2479
25898 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2480
25899 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2481
25900 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2482
25901 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2483
25902 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2484
25903 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2485
25904 CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2486
25905 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2487
25906 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2488
25907 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2489
25908 CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2490
25909 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2491
25910 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2492
25911 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2493
25912 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2494
25913 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2495
25914 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2496
25915 CEFBS_InMicroMips, // SEB_MM = 2497
25916 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2498
25917 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2499
25918 CEFBS_InMicroMips, // SEH_MM = 2500
25919 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2501
25920 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2502
25921 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2503
25922 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2504
25923 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2505
25924 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2506
25925 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2507
25926 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2508
25927 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2509
25928 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2510
25929 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2511
25930 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2512
25931 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2513
25932 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2514
25933 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2515
25934 CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2516
25935 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2517
25936 CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2518
25937 CEFBS_HasCnMips, // SEQ = 2519
25938 CEFBS_HasCnMips, // SEQi = 2520
25939 CEFBS_HasStdEnc_NotInMicroMips, // SH = 2521
25940 CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2522
25941 CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2523
25942 CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2524
25943 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2525
25944 CEFBS_InMicroMips_HasEVA, // SHE_MM = 2526
25945 CEFBS_HasStdEnc_HasMSA, // SHF_B = 2527
25946 CEFBS_HasStdEnc_HasMSA, // SHF_H = 2528
25947 CEFBS_HasStdEnc_HasMSA, // SHF_W = 2529
25948 CEFBS_HasDSP, // SHILO = 2530
25949 CEFBS_HasDSP, // SHILOV = 2531
25950 CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2532
25951 CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2533
25952 CEFBS_HasDSP, // SHLLV_PH = 2534
25953 CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2535
25954 CEFBS_HasDSP, // SHLLV_QB = 2536
25955 CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2537
25956 CEFBS_HasDSP, // SHLLV_S_PH = 2538
25957 CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2539
25958 CEFBS_HasDSP, // SHLLV_S_W = 2540
25959 CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2541
25960 CEFBS_HasDSP, // SHLL_PH = 2542
25961 CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2543
25962 CEFBS_HasDSP, // SHLL_QB = 2544
25963 CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2545
25964 CEFBS_HasDSP, // SHLL_S_PH = 2546
25965 CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2547
25966 CEFBS_HasDSP, // SHLL_S_W = 2548
25967 CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2549
25968 CEFBS_HasDSP, // SHRAV_PH = 2550
25969 CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2551
25970 CEFBS_HasDSPR2, // SHRAV_QB = 2552
25971 CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2553
25972 CEFBS_HasDSP, // SHRAV_R_PH = 2554
25973 CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2555
25974 CEFBS_HasDSPR2, // SHRAV_R_QB = 2556
25975 CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2557
25976 CEFBS_HasDSP, // SHRAV_R_W = 2558
25977 CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2559
25978 CEFBS_HasDSP, // SHRA_PH = 2560
25979 CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2561
25980 CEFBS_HasDSPR2, // SHRA_QB = 2562
25981 CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2563
25982 CEFBS_HasDSP, // SHRA_R_PH = 2564
25983 CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2565
25984 CEFBS_HasDSPR2, // SHRA_R_QB = 2566
25985 CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2567
25986 CEFBS_HasDSP, // SHRA_R_W = 2568
25987 CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2569
25988 CEFBS_HasDSPR2, // SHRLV_PH = 2570
25989 CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2571
25990 CEFBS_HasDSP, // SHRLV_QB = 2572
25991 CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2573
25992 CEFBS_HasDSPR2, // SHRL_PH = 2574
25993 CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2575
25994 CEFBS_HasDSP, // SHRL_QB = 2576
25995 CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2577
25996 CEFBS_InMicroMips, // SH_MM = 2578
25997 CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2579
25998 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2580
25999 CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2581
26000 CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2582
26001 CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2583
26002 CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2584
26003 CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2585
26004 CEFBS_HasStdEnc_HasMSA, // SLD_B = 2586
26005 CEFBS_HasStdEnc_HasMSA, // SLD_D = 2587
26006 CEFBS_HasStdEnc_HasMSA, // SLD_H = 2588
26007 CEFBS_HasStdEnc_HasMSA, // SLD_W = 2589
26008 CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2590
26009 CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2591
26010 CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2592
26011 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2593
26012 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2594
26013 CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2595
26014 CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2596
26015 CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2597
26016 CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2598
26017 CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2599
26018 CEFBS_InMicroMips, // SLLV_MM = 2600
26019 CEFBS_HasStdEnc_HasMSA, // SLL_B = 2601
26020 CEFBS_HasStdEnc_HasMSA, // SLL_D = 2602
26021 CEFBS_HasStdEnc_HasMSA, // SLL_H = 2603
26022 CEFBS_InMicroMips, // SLL_MM = 2604
26023 CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2605
26024 CEFBS_HasStdEnc_HasMSA, // SLL_W = 2606
26025 CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2607
26026 CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2608
26027 CEFBS_InMicroMips, // SLT_MM = 2609
26028 CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2610
26029 CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2611
26030 CEFBS_InMicroMips, // SLTi_MM = 2612
26031 CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2613
26032 CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2614
26033 CEFBS_InMicroMips, // SLTiu_MM = 2615
26034 CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2616
26035 CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2617
26036 CEFBS_InMicroMips, // SLTu_MM = 2618
26037 CEFBS_HasCnMips, // SNE = 2619
26038 CEFBS_HasCnMips, // SNEi = 2620
26039 CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2621
26040 CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2622
26041 CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2623
26042 CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2624
26043 CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2625
26044 CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2626
26045 CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2627
26046 CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2628
26047 CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2629
26048 CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2630
26049 CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2631
26050 CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2632
26051 CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2633
26052 CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2634
26053 CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2635
26054 CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2636
26055 CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2637
26056 CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2638
26057 CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2639
26058 CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2640
26059 CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2641
26060 CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2642
26061 CEFBS_InMicroMips, // SRAV_MM = 2643
26062 CEFBS_HasStdEnc_HasMSA, // SRA_B = 2644
26063 CEFBS_HasStdEnc_HasMSA, // SRA_D = 2645
26064 CEFBS_HasStdEnc_HasMSA, // SRA_H = 2646
26065 CEFBS_InMicroMips, // SRA_MM = 2647
26066 CEFBS_HasStdEnc_HasMSA, // SRA_W = 2648
26067 CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2649
26068 CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2650
26069 CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2651
26070 CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2652
26071 CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2653
26072 CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2654
26073 CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2655
26074 CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2656
26075 CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2657
26076 CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2658
26077 CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2659
26078 CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2660
26079 CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2661
26080 CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2662
26081 CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2663
26082 CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2664
26083 CEFBS_InMicroMips, // SRLV_MM = 2665
26084 CEFBS_HasStdEnc_HasMSA, // SRL_B = 2666
26085 CEFBS_HasStdEnc_HasMSA, // SRL_D = 2667
26086 CEFBS_HasStdEnc_HasMSA, // SRL_H = 2668
26087 CEFBS_InMicroMips, // SRL_MM = 2669
26088 CEFBS_HasStdEnc_HasMSA, // SRL_W = 2670
26089 CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2671
26090 CEFBS_InMicroMips, // SSNOP_MM = 2672
26091 CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2673
26092 CEFBS_HasStdEnc_HasMSA, // ST_B = 2674
26093 CEFBS_HasStdEnc_HasMSA, // ST_D = 2675
26094 CEFBS_HasStdEnc_HasMSA, // ST_H = 2676
26095 CEFBS_HasStdEnc_HasMSA, // ST_W = 2677
26096 CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2678
26097 CEFBS_HasDSPR2, // SUBQH_PH = 2679
26098 CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2680
26099 CEFBS_HasDSPR2, // SUBQH_R_PH = 2681
26100 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2682
26101 CEFBS_HasDSPR2, // SUBQH_R_W = 2683
26102 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2684
26103 CEFBS_HasDSPR2, // SUBQH_W = 2685
26104 CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2686
26105 CEFBS_HasDSP, // SUBQ_PH = 2687
26106 CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2688
26107 CEFBS_HasDSP, // SUBQ_S_PH = 2689
26108 CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2690
26109 CEFBS_HasDSP, // SUBQ_S_W = 2691
26110 CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2692
26111 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2693
26112 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2694
26113 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2695
26114 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2696
26115 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2697
26116 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2698
26117 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2699
26118 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2700
26119 CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2701
26120 CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2702
26121 CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2703
26122 CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2704
26123 CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2705
26124 CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2706
26125 CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2707
26126 CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2708
26127 CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2709
26128 CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2710
26129 CEFBS_HasDSPR2, // SUBUH_QB = 2711
26130 CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2712
26131 CEFBS_HasDSPR2, // SUBUH_R_QB = 2713
26132 CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2714
26133 CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2715
26134 CEFBS_HasDSPR2, // SUBU_PH = 2716
26135 CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2717
26136 CEFBS_HasDSP, // SUBU_QB = 2718
26137 CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2719
26138 CEFBS_HasDSPR2, // SUBU_S_PH = 2720
26139 CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2721
26140 CEFBS_HasDSP, // SUBU_S_QB = 2722
26141 CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2723
26142 CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2724
26143 CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2725
26144 CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2726
26145 CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2727
26146 CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2728
26147 CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2729
26148 CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2730
26149 CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2731
26150 CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2732
26151 CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2733
26152 CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2734
26153 CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2735
26154 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2736
26155 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2737
26156 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2738
26157 CEFBS_HasStdEnc_NotInMicroMips, // SW = 2739
26158 CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2740
26159 CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2741
26160 CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2742
26161 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2743
26162 CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2744
26163 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2745
26164 CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2746
26165 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2747
26166 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2748
26167 CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2749
26168 CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2750
26169 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2751
26170 CEFBS_InMicroMips_HasEVA, // SWE_MM = 2752
26171 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2753
26172 CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2754
26173 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2755
26174 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2756
26175 CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2757
26176 CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2758
26177 CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2759
26178 CEFBS_InMicroMips, // SWM32_MM = 2760
26179 CEFBS_InMicroMips, // SWP_MM = 2761
26180 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2762
26181 CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2763
26182 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2764
26183 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2765
26184 CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2766
26185 CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2767
26186 CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2768
26187 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2769
26188 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2770
26189 CEFBS_InMicroMips, // SW_MM = 2771
26190 CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2772
26191 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2773
26192 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2774
26193 CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2775
26194 CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2776
26195 CEFBS_InMicroMips, // SYNC_MM = 2777
26196 CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2778
26197 CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2779
26198 CEFBS_InMicroMips, // SYSCALL_MM = 2780
26199 CEFBS_InMips16Mode, // Save16 = 2781
26200 CEFBS_InMips16Mode, // SaveX16 = 2782
26201 CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2783
26202 CEFBS_InMips16Mode, // SebRx16 = 2784
26203 CEFBS_InMips16Mode, // SehRx16 = 2785
26204 CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2786
26205 CEFBS_InMips16Mode, // SllX16 = 2787
26206 CEFBS_InMips16Mode, // SllvRxRy16 = 2788
26207 CEFBS_InMips16Mode, // SltRxRy16 = 2789
26208 CEFBS_InMips16Mode, // SltiRxImm16 = 2790
26209 CEFBS_InMips16Mode, // SltiRxImmX16 = 2791
26210 CEFBS_InMips16Mode, // SltiuRxImm16 = 2792
26211 CEFBS_InMips16Mode, // SltiuRxImmX16 = 2793
26212 CEFBS_InMips16Mode, // SltuRxRy16 = 2794
26213 CEFBS_InMips16Mode, // SraX16 = 2795
26214 CEFBS_InMips16Mode, // SravRxRy16 = 2796
26215 CEFBS_InMips16Mode, // SrlX16 = 2797
26216 CEFBS_InMips16Mode, // SrlvRxRy16 = 2798
26217 CEFBS_InMips16Mode, // SubuRxRyRz16 = 2799
26218 CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2800
26219 CEFBS_InMips16Mode, // SwRxSpImmX16 = 2801
26220 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2802
26221 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2803
26222 CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2804
26223 CEFBS_InMicroMips, // TEQ_MM = 2805
26224 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2806
26225 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2807
26226 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2808
26227 CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2809
26228 CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2810
26229 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2811
26230 CEFBS_InMicroMips, // TGEU_MM = 2812
26231 CEFBS_InMicroMips, // TGE_MM = 2813
26232 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2814
26233 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2815
26234 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2816
26235 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2817
26236 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2818
26237 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2819
26238 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2820
26239 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2821
26240 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2822
26241 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2823
26242 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2824
26243 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2825
26244 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2826
26245 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2827
26246 CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2828
26247 CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2829
26248 CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2830
26249 CEFBS_InMicroMips, // TLBP_MM = 2831
26250 CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2832
26251 CEFBS_InMicroMips, // TLBR_MM = 2833
26252 CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2834
26253 CEFBS_InMicroMips, // TLBWI_MM = 2835
26254 CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2836
26255 CEFBS_InMicroMips, // TLBWR_MM = 2837
26256 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2838
26257 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2839
26258 CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2840
26259 CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2841
26260 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2842
26261 CEFBS_InMicroMips, // TLTU_MM = 2843
26262 CEFBS_InMicroMips, // TLT_MM = 2844
26263 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2845
26264 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2846
26265 CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2847
26266 CEFBS_InMicroMips, // TNE_MM = 2848
26267 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2849
26268 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2850
26269 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2851
26270 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2852
26271 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2853
26272 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2854
26273 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2855
26274 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2856
26275 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2857
26276 CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2858
26277 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2859
26278 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2860
26279 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2861
26280 CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2862
26281 CEFBS_HasCnMips, // V3MULU = 2863
26282 CEFBS_HasCnMips, // VMM0 = 2864
26283 CEFBS_HasCnMips, // VMULU = 2865
26284 CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2866
26285 CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2867
26286 CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2868
26287 CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2869
26288 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2870
26289 CEFBS_InMicroMips, // WAIT_MM = 2871
26290 CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2872
26291 CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2873
26292 CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2874
26293 CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2875
26294 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2876
26295 CEFBS_InMicroMips, // WSBH_MM = 2877
26296 CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2878
26297 CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2879
26298 CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2880
26299 CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2881
26300 CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2882
26301 CEFBS_HasStdEnc_HasMSA, // XORI_B = 2883
26302 CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2884
26303 CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2885
26304 CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2886
26305 CEFBS_HasStdEnc_HasMSA, // XOR_V = 2887
26306 CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2888
26307 CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2889
26308 CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2890
26309 CEFBS_InMips16Mode, // XorRxRxRy16 = 2891
26310 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2892
26311 };
26312
26313 assert(Opcode < 2893);
26314 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
26315}
26316
26317} // end namespace Mips_MC
26318} // end namespace llvm
26319#endif // GET_COMPUTE_FEATURES
26320
26321#ifdef GET_AVAILABLE_OPCODE_CHECKER
26322#undef GET_AVAILABLE_OPCODE_CHECKER
26323namespace llvm {
26324namespace Mips_MC {
26325bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
26326 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
26327 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
26328 FeatureBitset MissingFeatures =
26329 (AvailableFeatures & RequiredFeatures) ^
26330 RequiredFeatures;
26331 return !MissingFeatures.any();
26332}
26333} // end namespace Mips_MC
26334} // end namespace llvm
26335#endif // GET_AVAILABLE_OPCODE_CHECKER
26336
26337#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
26338#undef ENABLE_INSTR_PREDICATE_VERIFIER
26339#include <sstream>
26340
26341namespace llvm {
26342namespace Mips_MC {
26343
26344#ifndef NDEBUG
26345static const char *SubtargetFeatureNames[] = {
26346 "Feature_HasCRC",
26347 "Feature_HasCnMips",
26348 "Feature_HasCnMipsP",
26349 "Feature_HasDSP",
26350 "Feature_HasDSPR2",
26351 "Feature_HasDSPR3",
26352 "Feature_HasEVA",
26353 "Feature_HasGINV",
26354 "Feature_HasMSA",
26355 "Feature_HasMT",
26356 "Feature_HasMadd4",
26357 "Feature_HasMips2",
26358 "Feature_HasMips3",
26359 "Feature_HasMips3D",
26360 "Feature_HasMips3_32",
26361 "Feature_HasMips3_32r2",
26362 "Feature_HasMips4_32",
26363 "Feature_HasMips4_32r2",
26364 "Feature_HasMips5_32r2",
26365 "Feature_HasMips32",
26366 "Feature_HasMips32r2",
26367 "Feature_HasMips32r5",
26368 "Feature_HasMips32r6",
26369 "Feature_HasMips64",
26370 "Feature_HasMips64r2",
26371 "Feature_HasMips64r5",
26372 "Feature_HasMips64r6",
26373 "Feature_HasStdEnc",
26374 "Feature_HasVirt",
26375 "Feature_InMicroMips",
26376 "Feature_InMips16Mode",
26377 "Feature_IsFP64bit",
26378 "Feature_IsGP32bit",
26379 "Feature_IsGP64bit",
26380 "Feature_IsNotSingleFloat",
26381 "Feature_IsNotSoftFloat",
26382 "Feature_IsPTR32bit",
26383 "Feature_IsPTR64bit",
26384 "Feature_IsSingleFloat",
26385 "Feature_IsSym32",
26386 "Feature_IsSym64",
26387 "Feature_NoIndirectJumpGuards",
26388 "Feature_NotCnMips",
26389 "Feature_NotCnMipsP",
26390 "Feature_NotFP64bit",
26391 "Feature_NotInMicroMips",
26392 "Feature_NotInMips16Mode",
26393 "Feature_NotMips3",
26394 "Feature_NotMips4_32",
26395 "Feature_NotMips32r6",
26396 "Feature_NotMips64",
26397 "Feature_NotMips64r6",
26398 "Feature_UseIndirectJumpsHazard",
26399 nullptr
26400};
26401
26402#endif // NDEBUG
26403
26404void verifyInstructionPredicates(
26405 unsigned Opcode, const FeatureBitset &Features) {
26406#ifndef NDEBUG
26407 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
26408 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
26409 FeatureBitset MissingFeatures =
26410 (AvailableFeatures & RequiredFeatures) ^
26411 RequiredFeatures;
26412 if (MissingFeatures.any()) {
26413 std::ostringstream Msg;
26414 Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]
26415 << " instruction but the ";
26416 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
26417 if (MissingFeatures.test(i))
26418 Msg << SubtargetFeatureNames[i] << " ";
26419 Msg << "predicate(s) are not met";
26420 report_fatal_error(Msg.str().c_str());
26421 }
26422#endif // NDEBUG
26423}
26424} // end namespace Mips_MC
26425} // end namespace llvm
26426#endif // ENABLE_INSTR_PREDICATE_VERIFIER
26427
26428#ifdef GET_INSTRMAP_INFO
26429#undef GET_INSTRMAP_INFO
26430namespace llvm {
26431
26432namespace Mips {
26433
26434enum Arch {
26435 Arch_dsp,
26436 Arch_mmdsp,
26437 Arch_mipsr6,
26438 Arch_micromipsr6,
26439 Arch_se,
26440 Arch_micromips
26441};
26442
26443// Dsp2MicroMips
26444LLVM_READONLY
26445int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {
26446static const uint16_t Dsp2MicroMipsTable[][3] = {
26447 { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },
26448 { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },
26449 { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },
26450 { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },
26451 { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },
26452 { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },
26453 { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },
26454 { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },
26455 { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },
26456 { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },
26457 { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },
26458 { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },
26459 { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },
26460 { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },
26461 { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },
26462 { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },
26463 { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },
26464 { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },
26465 { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },
26466 { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },
26467 { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },
26468 { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },
26469 { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },
26470 { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },
26471 { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },
26472 { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },
26473 { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },
26474 { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },
26475 { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },
26476 { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },
26477 { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },
26478 { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },
26479 { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },
26480 { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },
26481 { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },
26482 { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },
26483 { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },
26484 { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },
26485 { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },
26486 { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },
26487 { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },
26488 { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },
26489 { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },
26490 { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },
26491 { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },
26492 { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },
26493 { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },
26494 { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },
26495 { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },
26496 { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },
26497 { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },
26498 { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },
26499 { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },
26500 { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },
26501 { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },
26502 { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },
26503 { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },
26504 { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },
26505 { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },
26506 { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },
26507 { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },
26508 { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },
26509 { Mips::INSV, Mips::INSV, Mips::INSV_MM },
26510 { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },
26511 { Mips::LHX, Mips::LHX, Mips::LHX_MM },
26512 { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },
26513 { Mips::LWX, Mips::LWX, Mips::LWX_MM },
26514 { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },
26515 { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },
26516 { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },
26517 { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },
26518 { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },
26519 { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },
26520 { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },
26521 { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },
26522 { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },
26523 { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },
26524 { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },
26525 { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },
26526 { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },
26527 { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },
26528 { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },
26529 { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },
26530 { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },
26531 { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },
26532 { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },
26533 { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },
26534 { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },
26535 { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },
26536 { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },
26537 { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },
26538 { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },
26539 { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },
26540 { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },
26541 { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },
26542 { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },
26543 { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },
26544 { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },
26545 { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },
26546 { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },
26547 { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },
26548 { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },
26549 { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },
26550 { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },
26551 { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },
26552 { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },
26553 { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },
26554 { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },
26555 { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },
26556 { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },
26557 { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },
26558 { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },
26559 { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },
26560 { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },
26561 { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },
26562 { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },
26563 { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },
26564 { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },
26565 { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },
26566 { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },
26567 { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },
26568 { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },
26569 { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },
26570 { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },
26571 { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },
26572 { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },
26573 { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },
26574 { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },
26575 { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },
26576 { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },
26577 { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },
26578 { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },
26579 { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },
26580 { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },
26581 { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },
26582 { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },
26583 { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },
26584 { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },
26585 { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },
26586 { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },
26587 { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },
26588 { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },
26589 { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },
26590 { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },
26591 { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },
26592 { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },
26593 { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },
26594 { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },
26595 { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },
26596 { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },
26597 { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },
26598 { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },
26599 { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },
26600 { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },
26601 { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },
26602 { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },
26603 { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },
26604 { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },
26605 { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },
26606 { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },
26607}; // End of Dsp2MicroMipsTable
26608
26609 unsigned mid;
26610 unsigned start = 0;
26611 unsigned end = 160;
26612 while (start < end) {
26613 mid = start + (end - start) / 2;
26614 if (Opcode == Dsp2MicroMipsTable[mid][0]) {
26615 break;
26616 }
26617 if (Opcode < Dsp2MicroMipsTable[mid][0])
26618 end = mid;
26619 else
26620 start = mid + 1;
26621 }
26622 if (start == end)
26623 return -1; // Instruction doesn't exist in this table.
26624
26625 if (inArch == Arch_dsp)
26626 return Dsp2MicroMipsTable[mid][1];
26627 if (inArch == Arch_mmdsp)
26628 return Dsp2MicroMipsTable[mid][2];
26629 return -1;}
26630
26631// MipsR62MicroMipsR6
26632LLVM_READONLY
26633int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
26634static const uint16_t MipsR62MicroMipsR6Table[][3] = {
26635 { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },
26636 { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },
26637 { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },
26638 { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },
26639 { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },
26640 { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },
26641 { Mips::BC, Mips::BC, Mips::BC_MMR6 },
26642 { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },
26643 { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },
26644 { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },
26645 { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },
26646 { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },
26647 { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },
26648 { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },
26649 { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },
26650 { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },
26651 { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },
26652 { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },
26653 { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },
26654 { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },
26655 { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },
26656 { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },
26657 { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },
26658 { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },
26659 { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },
26660 { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },
26661 { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },
26662 { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },
26663 { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },
26664 { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },
26665 { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },
26666 { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },
26667 { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },
26668 { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },
26669 { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },
26670 { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },
26671 { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },
26672 { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },
26673 { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },
26674 { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },
26675 { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },
26676 { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },
26677 { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },
26678 { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },
26679 { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },
26680 { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },
26681 { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },
26682 { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },
26683 { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },
26684 { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },
26685 { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },
26686 { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },
26687 { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },
26688 { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },
26689 { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },
26690 { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },
26691 { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },
26692 { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },
26693 { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },
26694 { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },
26695 { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },
26696 { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },
26697 { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },
26698 { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },
26699 { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },
26700 { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },
26701 { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },
26702 { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },
26703 { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },
26704 { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },
26705 { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },
26706 { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },
26707 { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },
26708 { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },
26709 { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },
26710 { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },
26711 { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },
26712 { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },
26713 { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },
26714 { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },
26715 { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },
26716 { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },
26717 { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },
26718 { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },
26719 { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },
26720 { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },
26721 { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },
26722 { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },
26723 { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },
26724 { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },
26725 { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },
26726 { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },
26727 { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },
26728 { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },
26729 { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },
26730 { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },
26731}; // End of MipsR62MicroMipsR6Table
26732
26733 unsigned mid;
26734 unsigned start = 0;
26735 unsigned end = 96;
26736 while (start < end) {
26737 mid = start + (end - start) / 2;
26738 if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {
26739 break;
26740 }
26741 if (Opcode < MipsR62MicroMipsR6Table[mid][0])
26742 end = mid;
26743 else
26744 start = mid + 1;
26745 }
26746 if (start == end)
26747 return -1; // Instruction doesn't exist in this table.
26748
26749 if (inArch == Arch_mipsr6)
26750 return MipsR62MicroMipsR6Table[mid][1];
26751 if (inArch == Arch_micromipsr6)
26752 return MipsR62MicroMipsR6Table[mid][2];
26753 return -1;}
26754
26755// Std2MicroMips
26756LLVM_READONLY
26757int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {
26758static const uint16_t Std2MicroMipsTable[][3] = {
26759 { Mips::ADD, Mips::ADD, Mips::ADD_MM },
26760 { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },
26761 { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },
26762 { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },
26763 { Mips::AND, Mips::AND, Mips::AND_MM },
26764 { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },
26765 { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },
26766 { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },
26767 { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },
26768 { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },
26769 { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },
26770 { Mips::BEQL, Mips::BEQL, (uint16_t)-1U },
26771 { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },
26772 { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },
26773 { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },
26774 { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },
26775 { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },
26776 { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },
26777 { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },
26778 { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },
26779 { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },
26780 { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },
26781 { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },
26782 { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },
26783 { Mips::BNE, Mips::BNE, Mips::BNE_MM },
26784 { Mips::BNEL, Mips::BNEL, (uint16_t)-1U },
26785 { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },
26786 { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },
26787 { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },
26788 { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },
26789 { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },
26790 { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },
26791 { Mips::CLO, Mips::CLO, Mips::CLO_MM },
26792 { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },
26793 { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },
26794 { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },
26795 { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },
26796 { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },
26797 { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },
26798 { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },
26799 { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },
26800 { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },
26801 { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },
26802 { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },
26803 { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },
26804 { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },
26805 { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },
26806 { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },
26807 { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },
26808 { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },
26809 { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },
26810 { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },
26811 { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },
26812 { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },
26813 { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },
26814 { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },
26815 { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },
26816 { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },
26817 { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },
26818 { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },
26819 { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },
26820 { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },
26821 { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },
26822 { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },
26823 { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },
26824 { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },
26825 { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },
26826 { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },
26827 { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },
26828 { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },
26829 { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },
26830 { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },
26831 { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },
26832 { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },
26833 { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },
26834 { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },
26835 { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },
26836 { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },
26837 { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },
26838 { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },
26839 { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },
26840 { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },
26841 { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },
26842 { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },
26843 { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },
26844 { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },
26845 { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },
26846 { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },
26847 { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },
26848 { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },
26849 { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },
26850 { Mips::DERET, Mips::DERET, Mips::DERET_MM },
26851 { Mips::DI, Mips::DI, Mips::DI_MM },
26852 { Mips::EHB, Mips::EHB, Mips::EHB_MM },
26853 { Mips::EI, Mips::EI, Mips::EI_MM },
26854 { Mips::ERET, Mips::ERET, Mips::ERET_MM },
26855 { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },
26856 { Mips::EXT, Mips::EXT, Mips::EXT_MM },
26857 { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },
26858 { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },
26859 { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },
26860 { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },
26861 { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },
26862 { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },
26863 { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },
26864 { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },
26865 { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },
26866 { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },
26867 { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },
26868 { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },
26869 { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },
26870 { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },
26871 { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },
26872 { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },
26873 { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },
26874 { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },
26875 { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },
26876 { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },
26877 { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },
26878 { Mips::INS, Mips::INS, Mips::INS_MM },
26879 { Mips::J, Mips::J, Mips::J_MM },
26880 { Mips::JAL, Mips::JAL, Mips::JAL_MM },
26881 { Mips::JALX, Mips::JALX, Mips::JALX_MM },
26882 { Mips::JR, Mips::JR, Mips::JR_MM },
26883 { Mips::LB, Mips::LB, Mips::LB_MM },
26884 { Mips::LBE, Mips::LBE, Mips::LBE_MM },
26885 { Mips::LBu, Mips::LBu, Mips::LBu_MM },
26886 { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },
26887 { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 },
26888 { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },
26889 { Mips::LH, Mips::LH, Mips::LH_MM },
26890 { Mips::LHE, Mips::LHE, Mips::LHE_MM },
26891 { Mips::LHu, Mips::LHu, Mips::LHu_MM },
26892 { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },
26893 { Mips::LLE, Mips::LLE, Mips::LLE_MM },
26894 { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },
26895 { Mips::LUi, Mips::LUi, Mips::LUi_MM },
26896 { Mips::LW, Mips::LW, Mips::LW_MM },
26897 { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },
26898 { Mips::LWE, Mips::LWE, Mips::LWE_MM },
26899 { Mips::LWL, Mips::LWL, Mips::LWL_MM },
26900 { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },
26901 { Mips::LWR, Mips::LWR, Mips::LWR_MM },
26902 { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },
26903 { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },
26904 { Mips::LWu, Mips::LWu, Mips::LWU_MM },
26905 { Mips::MADD, Mips::MADD, Mips::MADD_MM },
26906 { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },
26907 { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },
26908 { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },
26909 { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },
26910 { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },
26911 { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },
26912 { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },
26913 { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },
26914 { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },
26915 { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },
26916 { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },
26917 { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },
26918 { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },
26919 { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },
26920 { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },
26921 { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },
26922 { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },
26923 { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },
26924 { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },
26925 { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },
26926 { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },
26927 { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },
26928 { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },
26929 { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },
26930 { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },
26931 { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },
26932 { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },
26933 { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },
26934 { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },
26935 { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },
26936 { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },
26937 { Mips::MUL, Mips::MUL, Mips::MUL_MM },
26938 { Mips::MULT, Mips::MULT, Mips::MULT_MM },
26939 { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },
26940 { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },
26941 { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },
26942 { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },
26943 { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },
26944 { Mips::NOR, Mips::NOR, Mips::NOR_MM },
26945 { Mips::OR, Mips::OR, Mips::OR_MM },
26946 { Mips::ORi, Mips::ORi, Mips::ORi_MM },
26947 { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },
26948 { Mips::PREF, Mips::PREF, Mips::PREF_MM },
26949 { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },
26950 { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },
26951 { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },
26952 { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },
26953 { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },
26954 { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },
26955 { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },
26956 { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },
26957 { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },
26958 { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },
26959 { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },
26960 { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },
26961 { Mips::SB, Mips::SB, Mips::SB_MM },
26962 { Mips::SBE, Mips::SBE, Mips::SBE_MM },
26963 { Mips::SCE, Mips::SCE, Mips::SCE_MM },
26964 { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },
26965 { Mips::SDC1, Mips::SDC1, (uint16_t)-1U },
26966 { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },
26967 { Mips::SEB, Mips::SEB, Mips::SEB_MM },
26968 { Mips::SEH, Mips::SEH, Mips::SEH_MM },
26969 { Mips::SH, Mips::SH, Mips::SH_MM },
26970 { Mips::SHE, Mips::SHE, Mips::SHE_MM },
26971 { Mips::SLL, Mips::SLL, Mips::SLL_MM },
26972 { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },
26973 { Mips::SLT, Mips::SLT, Mips::SLT_MM },
26974 { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },
26975 { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },
26976 { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },
26977 { Mips::SRA, Mips::SRA, Mips::SRA_MM },
26978 { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },
26979 { Mips::SRL, Mips::SRL, Mips::SRL_MM },
26980 { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },
26981 { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },
26982 { Mips::SUB, Mips::SUB, Mips::SUB_MM },
26983 { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },
26984 { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },
26985 { Mips::SW, Mips::SW, Mips::SW_MM },
26986 { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },
26987 { Mips::SWE, Mips::SWE, Mips::SWE_MM },
26988 { Mips::SWL, Mips::SWL, Mips::SWL_MM },
26989 { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },
26990 { Mips::SWR, Mips::SWR, Mips::SWR_MM },
26991 { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },
26992 { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },
26993 { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },
26994 { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },
26995 { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },
26996 { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },
26997 { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },
26998 { Mips::TGE, Mips::TGE, Mips::TGE_MM },
26999 { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },
27000 { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },
27001 { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },
27002 { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },
27003 { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },
27004 { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },
27005 { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },
27006 { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },
27007 { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },
27008 { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },
27009 { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },
27010 { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },
27011 { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },
27012 { Mips::TLT, Mips::TLT, Mips::TLT_MM },
27013 { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },
27014 { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },
27015 { Mips::TNE, Mips::TNE, Mips::TNE_MM },
27016 { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },
27017 { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },
27018 { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },
27019 { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },
27020 { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },
27021 { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },
27022 { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },
27023 { Mips::XOR, Mips::XOR, Mips::XOR_MM },
27024 { Mips::XORi, Mips::XORi, Mips::XORi_MM },
27025}; // End of Std2MicroMipsTable
27026
27027 unsigned mid;
27028 unsigned start = 0;
27029 unsigned end = 266;
27030 while (start < end) {
27031 mid = start + (end - start) / 2;
27032 if (Opcode == Std2MicroMipsTable[mid][0]) {
27033 break;
27034 }
27035 if (Opcode < Std2MicroMipsTable[mid][0])
27036 end = mid;
27037 else
27038 start = mid + 1;
27039 }
27040 if (start == end)
27041 return -1; // Instruction doesn't exist in this table.
27042
27043 if (inArch == Arch_se)
27044 return Std2MicroMipsTable[mid][1];
27045 if (inArch == Arch_micromips)
27046 return Std2MicroMipsTable[mid][2];
27047 return -1;}
27048
27049// Std2MicroMipsR6
27050LLVM_READONLY
27051int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
27052static const uint16_t Std2MicroMipsR6Table[][3] = {
27053 { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },
27054 { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },
27055 { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },
27056 { Mips::AND, Mips::AND, Mips::AND_MMR6 },
27057 { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },
27058 { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },
27059 { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },
27060 { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },
27061 { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },
27062 { Mips::DI, Mips::DI, Mips::DI_MMR6 },
27063 { Mips::EI, Mips::EI, Mips::EI_MMR6 },
27064 { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },
27065 { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U },
27066 { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },
27067 { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },
27068 { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 },
27069 { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U },
27070 { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U },
27071 { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },
27072 { Mips::INS, Mips::INS, Mips::INS_MMR6 },
27073 { Mips::LDC1, Mips::LDC1, (uint16_t)-1U },
27074 { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },
27075 { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },
27076 { Mips::LW, Mips::LW, Mips::LW_MMR6 },
27077 { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },
27078 { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 },
27079 { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },
27080 { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },
27081 { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },
27082 { Mips::OR, Mips::OR, Mips::OR_MMR6 },
27083 { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },
27084 { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },
27085 { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },
27086 { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },
27087 { Mips::SB, Mips::SB, Mips::SB_MMR6 },
27088 { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },
27089 { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },
27090 { Mips::SEB, Mips::SEB, (uint16_t)-1U },
27091 { Mips::SEH, Mips::SEH, (uint16_t)-1U },
27092 { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },
27093 { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },
27094 { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },
27095 { Mips::SW, Mips::SW, Mips::SW_MMR6 },
27096 { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },
27097 { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },
27098 { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },
27099 { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },
27100 { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },
27101 { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },
27102 { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },
27103 { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },
27104}; // End of Std2MicroMipsR6Table
27105
27106 unsigned mid;
27107 unsigned start = 0;
27108 unsigned end = 51;
27109 while (start < end) {
27110 mid = start + (end - start) / 2;
27111 if (Opcode == Std2MicroMipsR6Table[mid][0]) {
27112 break;
27113 }
27114 if (Opcode < Std2MicroMipsR6Table[mid][0])
27115 end = mid;
27116 else
27117 start = mid + 1;
27118 }
27119 if (start == end)
27120 return -1; // Instruction doesn't exist in this table.
27121
27122 if (inArch == Arch_se)
27123 return Std2MicroMipsR6Table[mid][1];
27124 if (inArch == Arch_micromipsr6)
27125 return Std2MicroMipsR6Table[mid][2];
27126 return -1;}
27127
27128} // end namespace Mips
27129} // end namespace llvm
27130#endif // GET_INSTRMAP_INFO
27131
27132