1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
14#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15
16#include "llvm/Support/DataTypes.h"
17
18#include <memory>
19
20namespace llvm {
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectTargetWriter;
26class MCRegisterInfo;
27class MCSubtargetInfo;
28class MCTargetOptions;
29class StringRef;
30class Target;
31class Triple;
32
33MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
34 MCContext &Ctx);
35MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
36 MCContext &Ctx);
37
38MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
39 const MCRegisterInfo &MRI,
40 const MCTargetOptions &Options);
41
42std::unique_ptr<MCObjectTargetWriter>
43createMipsELFObjectWriter(const Triple &TT, bool IsN32);
44
45namespace MIPS_MC {
46StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
47}
48
49} // End llvm namespace
50
51// Defines symbolic names for Mips registers. This defines a mapping from
52// register name to register number.
53#define GET_REGINFO_ENUM
54#include "MipsGenRegisterInfo.inc"
55
56// Defines symbolic names for the Mips instructions.
57#define GET_INSTRINFO_ENUM
58#define GET_INSTRINFO_MC_HELPER_DECLS
59#include "MipsGenInstrInfo.inc"
60
61#define GET_SUBTARGETINFO_ENUM
62#include "MipsGenSubtargetInfo.inc"
63
64#endif
65