1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MipsMCRegisterClasses[];
17
18namespace Mips {
19enum {
20 NoRegister,
21 AT = 1,
22 DSPCCond = 2,
23 DSPCarry = 3,
24 DSPEFI = 4,
25 DSPOutFlag = 5,
26 DSPPos = 6,
27 DSPSCount = 7,
28 FP = 8,
29 GP = 9,
30 MSAAccess = 10,
31 MSACSR = 11,
32 MSAIR = 12,
33 MSAMap = 13,
34 MSAModify = 14,
35 MSARequest = 15,
36 MSASave = 16,
37 MSAUnmap = 17,
38 PC = 18,
39 RA = 19,
40 SP = 20,
41 ZERO = 21,
42 A0 = 22,
43 A1 = 23,
44 A2 = 24,
45 A3 = 25,
46 AC0 = 26,
47 AC1 = 27,
48 AC2 = 28,
49 AC3 = 29,
50 AT_64 = 30,
51 COP00 = 31,
52 COP01 = 32,
53 COP02 = 33,
54 COP03 = 34,
55 COP04 = 35,
56 COP05 = 36,
57 COP06 = 37,
58 COP07 = 38,
59 COP08 = 39,
60 COP09 = 40,
61 COP20 = 41,
62 COP21 = 42,
63 COP22 = 43,
64 COP23 = 44,
65 COP24 = 45,
66 COP25 = 46,
67 COP26 = 47,
68 COP27 = 48,
69 COP28 = 49,
70 COP29 = 50,
71 COP30 = 51,
72 COP31 = 52,
73 COP32 = 53,
74 COP33 = 54,
75 COP34 = 55,
76 COP35 = 56,
77 COP36 = 57,
78 COP37 = 58,
79 COP38 = 59,
80 COP39 = 60,
81 COP010 = 61,
82 COP011 = 62,
83 COP012 = 63,
84 COP013 = 64,
85 COP014 = 65,
86 COP015 = 66,
87 COP016 = 67,
88 COP017 = 68,
89 COP018 = 69,
90 COP019 = 70,
91 COP020 = 71,
92 COP021 = 72,
93 COP022 = 73,
94 COP023 = 74,
95 COP024 = 75,
96 COP025 = 76,
97 COP026 = 77,
98 COP027 = 78,
99 COP028 = 79,
100 COP029 = 80,
101 COP030 = 81,
102 COP031 = 82,
103 COP210 = 83,
104 COP211 = 84,
105 COP212 = 85,
106 COP213 = 86,
107 COP214 = 87,
108 COP215 = 88,
109 COP216 = 89,
110 COP217 = 90,
111 COP218 = 91,
112 COP219 = 92,
113 COP220 = 93,
114 COP221 = 94,
115 COP222 = 95,
116 COP223 = 96,
117 COP224 = 97,
118 COP225 = 98,
119 COP226 = 99,
120 COP227 = 100,
121 COP228 = 101,
122 COP229 = 102,
123 COP230 = 103,
124 COP231 = 104,
125 COP310 = 105,
126 COP311 = 106,
127 COP312 = 107,
128 COP313 = 108,
129 COP314 = 109,
130 COP315 = 110,
131 COP316 = 111,
132 COP317 = 112,
133 COP318 = 113,
134 COP319 = 114,
135 COP320 = 115,
136 COP321 = 116,
137 COP322 = 117,
138 COP323 = 118,
139 COP324 = 119,
140 COP325 = 120,
141 COP326 = 121,
142 COP327 = 122,
143 COP328 = 123,
144 COP329 = 124,
145 COP330 = 125,
146 COP331 = 126,
147 D0 = 127,
148 D1 = 128,
149 D2 = 129,
150 D3 = 130,
151 D4 = 131,
152 D5 = 132,
153 D6 = 133,
154 D7 = 134,
155 D8 = 135,
156 D9 = 136,
157 D10 = 137,
158 D11 = 138,
159 D12 = 139,
160 D13 = 140,
161 D14 = 141,
162 D15 = 142,
163 DSPOutFlag20 = 143,
164 DSPOutFlag21 = 144,
165 DSPOutFlag22 = 145,
166 DSPOutFlag23 = 146,
167 F0 = 147,
168 F1 = 148,
169 F2 = 149,
170 F3 = 150,
171 F4 = 151,
172 F5 = 152,
173 F6 = 153,
174 F7 = 154,
175 F8 = 155,
176 F9 = 156,
177 F10 = 157,
178 F11 = 158,
179 F12 = 159,
180 F13 = 160,
181 F14 = 161,
182 F15 = 162,
183 F16 = 163,
184 F17 = 164,
185 F18 = 165,
186 F19 = 166,
187 F20 = 167,
188 F21 = 168,
189 F22 = 169,
190 F23 = 170,
191 F24 = 171,
192 F25 = 172,
193 F26 = 173,
194 F27 = 174,
195 F28 = 175,
196 F29 = 176,
197 F30 = 177,
198 F31 = 178,
199 FCC0 = 179,
200 FCC1 = 180,
201 FCC2 = 181,
202 FCC3 = 182,
203 FCC4 = 183,
204 FCC5 = 184,
205 FCC6 = 185,
206 FCC7 = 186,
207 FCR0 = 187,
208 FCR1 = 188,
209 FCR2 = 189,
210 FCR3 = 190,
211 FCR4 = 191,
212 FCR5 = 192,
213 FCR6 = 193,
214 FCR7 = 194,
215 FCR8 = 195,
216 FCR9 = 196,
217 FCR10 = 197,
218 FCR11 = 198,
219 FCR12 = 199,
220 FCR13 = 200,
221 FCR14 = 201,
222 FCR15 = 202,
223 FCR16 = 203,
224 FCR17 = 204,
225 FCR18 = 205,
226 FCR19 = 206,
227 FCR20 = 207,
228 FCR21 = 208,
229 FCR22 = 209,
230 FCR23 = 210,
231 FCR24 = 211,
232 FCR25 = 212,
233 FCR26 = 213,
234 FCR27 = 214,
235 FCR28 = 215,
236 FCR29 = 216,
237 FCR30 = 217,
238 FCR31 = 218,
239 FP_64 = 219,
240 F_HI0 = 220,
241 F_HI1 = 221,
242 F_HI2 = 222,
243 F_HI3 = 223,
244 F_HI4 = 224,
245 F_HI5 = 225,
246 F_HI6 = 226,
247 F_HI7 = 227,
248 F_HI8 = 228,
249 F_HI9 = 229,
250 F_HI10 = 230,
251 F_HI11 = 231,
252 F_HI12 = 232,
253 F_HI13 = 233,
254 F_HI14 = 234,
255 F_HI15 = 235,
256 F_HI16 = 236,
257 F_HI17 = 237,
258 F_HI18 = 238,
259 F_HI19 = 239,
260 F_HI20 = 240,
261 F_HI21 = 241,
262 F_HI22 = 242,
263 F_HI23 = 243,
264 F_HI24 = 244,
265 F_HI25 = 245,
266 F_HI26 = 246,
267 F_HI27 = 247,
268 F_HI28 = 248,
269 F_HI29 = 249,
270 F_HI30 = 250,
271 F_HI31 = 251,
272 GP_64 = 252,
273 HI0 = 253,
274 HI1 = 254,
275 HI2 = 255,
276 HI3 = 256,
277 HWR0 = 257,
278 HWR1 = 258,
279 HWR2 = 259,
280 HWR3 = 260,
281 HWR4 = 261,
282 HWR5 = 262,
283 HWR6 = 263,
284 HWR7 = 264,
285 HWR8 = 265,
286 HWR9 = 266,
287 HWR10 = 267,
288 HWR11 = 268,
289 HWR12 = 269,
290 HWR13 = 270,
291 HWR14 = 271,
292 HWR15 = 272,
293 HWR16 = 273,
294 HWR17 = 274,
295 HWR18 = 275,
296 HWR19 = 276,
297 HWR20 = 277,
298 HWR21 = 278,
299 HWR22 = 279,
300 HWR23 = 280,
301 HWR24 = 281,
302 HWR25 = 282,
303 HWR26 = 283,
304 HWR27 = 284,
305 HWR28 = 285,
306 HWR29 = 286,
307 HWR30 = 287,
308 HWR31 = 288,
309 K0 = 289,
310 K1 = 290,
311 LO0 = 291,
312 LO1 = 292,
313 LO2 = 293,
314 LO3 = 294,
315 MPL0 = 295,
316 MPL1 = 296,
317 MPL2 = 297,
318 MSA8 = 298,
319 MSA9 = 299,
320 MSA10 = 300,
321 MSA11 = 301,
322 MSA12 = 302,
323 MSA13 = 303,
324 MSA14 = 304,
325 MSA15 = 305,
326 MSA16 = 306,
327 MSA17 = 307,
328 MSA18 = 308,
329 MSA19 = 309,
330 MSA20 = 310,
331 MSA21 = 311,
332 MSA22 = 312,
333 MSA23 = 313,
334 MSA24 = 314,
335 MSA25 = 315,
336 MSA26 = 316,
337 MSA27 = 317,
338 MSA28 = 318,
339 MSA29 = 319,
340 MSA30 = 320,
341 MSA31 = 321,
342 P0 = 322,
343 P1 = 323,
344 P2 = 324,
345 RA_64 = 325,
346 S0 = 326,
347 S1 = 327,
348 S2 = 328,
349 S3 = 329,
350 S4 = 330,
351 S5 = 331,
352 S6 = 332,
353 S7 = 333,
354 SP_64 = 334,
355 T0 = 335,
356 T1 = 336,
357 T2 = 337,
358 T3 = 338,
359 T4 = 339,
360 T5 = 340,
361 T6 = 341,
362 T7 = 342,
363 T8 = 343,
364 T9 = 344,
365 V0 = 345,
366 V1 = 346,
367 W0 = 347,
368 W1 = 348,
369 W2 = 349,
370 W3 = 350,
371 W4 = 351,
372 W5 = 352,
373 W6 = 353,
374 W7 = 354,
375 W8 = 355,
376 W9 = 356,
377 W10 = 357,
378 W11 = 358,
379 W12 = 359,
380 W13 = 360,
381 W14 = 361,
382 W15 = 362,
383 W16 = 363,
384 W17 = 364,
385 W18 = 365,
386 W19 = 366,
387 W20 = 367,
388 W21 = 368,
389 W22 = 369,
390 W23 = 370,
391 W24 = 371,
392 W25 = 372,
393 W26 = 373,
394 W27 = 374,
395 W28 = 375,
396 W29 = 376,
397 W30 = 377,
398 W31 = 378,
399 ZERO_64 = 379,
400 A0_64 = 380,
401 A1_64 = 381,
402 A2_64 = 382,
403 A3_64 = 383,
404 AC0_64 = 384,
405 D0_64 = 385,
406 D1_64 = 386,
407 D2_64 = 387,
408 D3_64 = 388,
409 D4_64 = 389,
410 D5_64 = 390,
411 D6_64 = 391,
412 D7_64 = 392,
413 D8_64 = 393,
414 D9_64 = 394,
415 D10_64 = 395,
416 D11_64 = 396,
417 D12_64 = 397,
418 D13_64 = 398,
419 D14_64 = 399,
420 D15_64 = 400,
421 D16_64 = 401,
422 D17_64 = 402,
423 D18_64 = 403,
424 D19_64 = 404,
425 D20_64 = 405,
426 D21_64 = 406,
427 D22_64 = 407,
428 D23_64 = 408,
429 D24_64 = 409,
430 D25_64 = 410,
431 D26_64 = 411,
432 D27_64 = 412,
433 D28_64 = 413,
434 D29_64 = 414,
435 D30_64 = 415,
436 D31_64 = 416,
437 DSPOutFlag16_19 = 417,
438 HI0_64 = 418,
439 K0_64 = 419,
440 K1_64 = 420,
441 LO0_64 = 421,
442 S0_64 = 422,
443 S1_64 = 423,
444 S2_64 = 424,
445 S3_64 = 425,
446 S4_64 = 426,
447 S5_64 = 427,
448 S6_64 = 428,
449 S7_64 = 429,
450 T0_64 = 430,
451 T1_64 = 431,
452 T2_64 = 432,
453 T3_64 = 433,
454 T4_64 = 434,
455 T5_64 = 435,
456 T6_64 = 436,
457 T7_64 = 437,
458 T8_64 = 438,
459 T9_64 = 439,
460 V0_64 = 440,
461 V1_64 = 441,
462 NUM_TARGET_REGS // 442
463};
464} // end namespace Mips
465
466// Register classes
467
468namespace Mips {
469enum {
470 MSA128F16RegClassID = 0,
471 CCRRegClassID = 1,
472 COP0RegClassID = 2,
473 COP2RegClassID = 3,
474 COP3RegClassID = 4,
475 DSPRRegClassID = 5,
476 FGR32RegClassID = 6,
477 FGRCCRegClassID = 7,
478 GPR32RegClassID = 8,
479 HWRegsRegClassID = 9,
480 MSACtrlRegClassID = 10,
481 GPR32NONZERORegClassID = 11,
482 CPU16RegsPlusSPRegClassID = 12,
483 CPU16RegsRegClassID = 13,
484 FCCRegClassID = 14,
485 GPRMM16RegClassID = 15,
486 GPRMM16MovePRegClassID = 16,
487 GPRMM16ZeroRegClassID = 17,
488 CPU16Regs_and_GPRMM16ZeroRegClassID = 18,
489 GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,
490 GPRMM16MovePPairSecondRegClassID = 20,
491 CPU16Regs_and_GPRMM16MovePRegClassID = 21,
492 GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,
493 HI32DSPRegClassID = 23,
494 LO32DSPRegClassID = 24,
495 CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,
496 GPRMM16MovePPairFirstRegClassID = 26,
497 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,
498 GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,
499 CPURARegRegClassID = 29,
500 CPUSPRegRegClassID = 30,
501 DSPCCRegClassID = 31,
502 GP32RegClassID = 32,
503 GPR32ZERORegClassID = 33,
504 HI32RegClassID = 34,
505 LO32RegClassID = 35,
506 SP32RegClassID = 36,
507 FGR64RegClassID = 37,
508 GPR64RegClassID = 38,
509 GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,
510 AFGR64RegClassID = 40,
511 GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,
512 GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,
513 GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,
514 GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,
515 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,
516 GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,
517 GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,
518 ACC64DSPRegClassID = 48,
519 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,
520 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,
521 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,
522 GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,
523 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,
524 OCTEON_MPLRegClassID = 54,
525 OCTEON_PRegClassID = 55,
526 GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,
527 ACC64RegClassID = 57,
528 GP64RegClassID = 58,
529 GPR64_with_sub_32_in_CPURARegRegClassID = 59,
530 GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,
531 HI64RegClassID = 61,
532 LO64RegClassID = 62,
533 SP64RegClassID = 63,
534 MSA128BRegClassID = 64,
535 MSA128DRegClassID = 65,
536 MSA128HRegClassID = 66,
537 MSA128WRegClassID = 67,
538 MSA128WEvensRegClassID = 68,
539 ACC128RegClassID = 69,
540
541};
542} // end namespace Mips
543
544
545// Subregister indices
546
547namespace Mips {
548enum : uint16_t {
549 NoSubRegister,
550 sub_32, // 1
551 sub_64, // 2
552 sub_dsp16_19, // 3
553 sub_dsp20, // 4
554 sub_dsp21, // 5
555 sub_dsp22, // 6
556 sub_dsp23, // 7
557 sub_hi, // 8
558 sub_lo, // 9
559 sub_hi_then_sub_32, // 10
560 sub_32_sub_hi_then_sub_32, // 11
561 NUM_TARGET_SUBREGS
562};
563} // end namespace Mips
564
565// Register pressure sets enum.
566namespace Mips {
567enum RegisterPressureSets {
568 DSPCC = 0,
569 GPR32ZERO = 1,
570 GPR64_with_sub_32_in_CPURAReg = 2,
571 HI32 = 3,
572 GPRMM16MovePPairFirst = 4,
573 CPU16Regs_and_GPRMM16MoveP = 5,
574 HI32DSP = 6,
575 LO32DSP = 7,
576 GPRMM16MovePPairSecond = 8,
577 GPRMM16MoveP = 9,
578 ACC64DSP = 10,
579 CPU16Regs = 11,
580 GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,
581 CPU16Regs_with_GPRMM16MovePPairSecond = 13,
582 CPU16Regs_with_GPRMM16MoveP = 14,
583 DSPR = 15,
584 FGR32 = 16,
585 MSA128WEvens = 17,
586 FGR32_with_MSA128WEvens = 18,
587 MSA128F16 = 19,
588};
589} // end namespace Mips
590
591} // end namespace llvm
592
593#endif // GET_REGINFO_ENUM
594
595/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
596|* *|
597|* MC Register Information *|
598|* *|
599|* Automatically generated file, do not edit! *|
600|* *|
601\*===----------------------------------------------------------------------===*/
602
603
604#ifdef GET_REGINFO_MC_DESC
605#undef GET_REGINFO_MC_DESC
606
607namespace llvm {
608
609extern const int16_t MipsRegDiffLists[] = {
610 /* 0 */ -412, 0,
611 /* 2 */ -358, 0,
612 /* 4 */ -314, 0,
613 /* 6 */ -306, 0,
614 /* 8 */ -265, 0,
615 /* 10 */ -243, 0,
616 /* 12 */ 37, -130, 127, -165, -227, 0,
617 /* 18 */ -211, 0,
618 /* 20 */ -165, 0,
619 /* 22 */ -141, 0,
620 /* 24 */ -140, 0,
621 /* 26 */ -139, 0,
622 /* 28 */ -138, 0,
623 /* 30 */ -130, 0,
624 /* 32 */ -96, 0,
625 /* 34 */ -95, 0,
626 /* 36 */ 165, -38, 0,
627 /* 39 */ -20, 258, -38, 0,
628 /* 43 */ -21, 259, -38, 0,
629 /* 47 */ -22, 260, -38, 0,
630 /* 51 */ -23, 261, -38, 0,
631 /* 55 */ -24, 262, -38, 0,
632 /* 59 */ -25, 263, -38, 0,
633 /* 63 */ -26, 264, -38, 0,
634 /* 67 */ -27, 265, -38, 0,
635 /* 71 */ -28, 266, -38, 0,
636 /* 75 */ -29, 267, -38, 0,
637 /* 79 */ -30, 268, -38, 0,
638 /* 83 */ -31, 269, -38, 0,
639 /* 87 */ -32, 270, -38, 0,
640 /* 91 */ -33, 271, -38, 0,
641 /* 95 */ -34, 272, -38, 0,
642 /* 99 */ -35, 273, -38, 0,
643 /* 103 */ -36, 274, -38, 0,
644 /* 107 */ -265, 395, -37, 0,
645 /* 111 */ -227, 392, -34, 0,
646 /* 115 */ -29, 0,
647 /* 117 */ 412, -274, 1, 1, 1, 0,
648 /* 123 */ 1, 1, 1, 1, 0,
649 /* 128 */ 20, 1, 0,
650 /* 131 */ 21, 1, 0,
651 /* 134 */ 22, 1, 0,
652 /* 137 */ 23, 1, 0,
653 /* 140 */ 24, 1, 0,
654 /* 143 */ 25, 1, 0,
655 /* 146 */ 26, 1, 0,
656 /* 149 */ 27, 1, 0,
657 /* 152 */ 28, 1, 0,
658 /* 155 */ 29, 1, 0,
659 /* 158 */ 30, 1, 0,
660 /* 161 */ 31, 1, 0,
661 /* 164 */ 32, 1, 0,
662 /* 167 */ 33, 1, 0,
663 /* 170 */ 34, 1, 0,
664 /* 173 */ 35, 1, 0,
665 /* 176 */ 29, 0,
666 /* 178 */ 72, 0,
667 /* 180 */ 38, -238, 73, 0,
668 /* 184 */ 95, 0,
669 /* 186 */ 96, 0,
670 /* 188 */ 130, 0,
671 /* 190 */ 211, 0,
672 /* 192 */ 243, 0,
673 /* 194 */ 306, 0,
674 /* 196 */ 314, 0,
675 /* 198 */ 358, 0,
676};
677
678extern const LaneBitmask MipsLaneMaskLists[] = {
679 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
680 /* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
681 /* 8 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
682 /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
683};
684
685extern const uint16_t MipsSubRegIdxLists[] = {
686 /* 0 */ 1, 0,
687 /* 2 */ 3, 4, 5, 6, 7, 0,
688 /* 8 */ 2, 9, 8, 0,
689 /* 12 */ 9, 1, 8, 10, 11, 0,
690};
691
692
693#ifdef __GNUC__
694#pragma GCC diagnostic push
695#pragma GCC diagnostic ignored "-Woverlength-strings"
696#endif
697extern const char MipsRegStrings[] = {
698 /* 0 */ "COP00\0"
699 /* 6 */ "COP010\0"
700 /* 13 */ "COP210\0"
701 /* 20 */ "COP310\0"
702 /* 27 */ "MSA10\0"
703 /* 33 */ "D10\0"
704 /* 37 */ "F10\0"
705 /* 41 */ "F_HI10\0"
706 /* 48 */ "FCR10\0"
707 /* 54 */ "HWR10\0"
708 /* 60 */ "W10\0"
709 /* 64 */ "COP020\0"
710 /* 71 */ "COP220\0"
711 /* 78 */ "COP320\0"
712 /* 85 */ "MSA20\0"
713 /* 91 */ "F20\0"
714 /* 95 */ "F_HI20\0"
715 /* 102 */ "COP20\0"
716 /* 108 */ "FCR20\0"
717 /* 114 */ "HWR20\0"
718 /* 120 */ "W20\0"
719 /* 124 */ "DSPOutFlag20\0"
720 /* 137 */ "COP030\0"
721 /* 144 */ "COP230\0"
722 /* 151 */ "COP330\0"
723 /* 158 */ "MSA30\0"
724 /* 164 */ "F30\0"
725 /* 168 */ "F_HI30\0"
726 /* 175 */ "COP30\0"
727 /* 181 */ "FCR30\0"
728 /* 187 */ "HWR30\0"
729 /* 193 */ "W30\0"
730 /* 197 */ "A0\0"
731 /* 200 */ "AC0\0"
732 /* 204 */ "FCC0\0"
733 /* 209 */ "D0\0"
734 /* 212 */ "F0\0"
735 /* 215 */ "F_HI0\0"
736 /* 221 */ "K0\0"
737 /* 224 */ "MPL0\0"
738 /* 229 */ "LO0\0"
739 /* 233 */ "P0\0"
740 /* 236 */ "FCR0\0"
741 /* 241 */ "HWR0\0"
742 /* 246 */ "S0\0"
743 /* 249 */ "T0\0"
744 /* 252 */ "V0\0"
745 /* 255 */ "W0\0"
746 /* 258 */ "COP01\0"
747 /* 264 */ "COP011\0"
748 /* 271 */ "COP211\0"
749 /* 278 */ "COP311\0"
750 /* 285 */ "MSA11\0"
751 /* 291 */ "D11\0"
752 /* 295 */ "F11\0"
753 /* 299 */ "F_HI11\0"
754 /* 306 */ "FCR11\0"
755 /* 312 */ "HWR11\0"
756 /* 318 */ "W11\0"
757 /* 322 */ "COP021\0"
758 /* 329 */ "COP221\0"
759 /* 336 */ "COP321\0"
760 /* 343 */ "MSA21\0"
761 /* 349 */ "F21\0"
762 /* 353 */ "F_HI21\0"
763 /* 360 */ "COP21\0"
764 /* 366 */ "FCR21\0"
765 /* 372 */ "HWR21\0"
766 /* 378 */ "W21\0"
767 /* 382 */ "DSPOutFlag21\0"
768 /* 395 */ "COP031\0"
769 /* 402 */ "COP231\0"
770 /* 409 */ "COP331\0"
771 /* 416 */ "MSA31\0"
772 /* 422 */ "F31\0"
773 /* 426 */ "F_HI31\0"
774 /* 433 */ "COP31\0"
775 /* 439 */ "FCR31\0"
776 /* 445 */ "HWR31\0"
777 /* 451 */ "W31\0"
778 /* 455 */ "A1\0"
779 /* 458 */ "AC1\0"
780 /* 462 */ "FCC1\0"
781 /* 467 */ "D1\0"
782 /* 470 */ "F1\0"
783 /* 473 */ "F_HI1\0"
784 /* 479 */ "K1\0"
785 /* 482 */ "MPL1\0"
786 /* 487 */ "LO1\0"
787 /* 491 */ "P1\0"
788 /* 494 */ "FCR1\0"
789 /* 499 */ "HWR1\0"
790 /* 504 */ "S1\0"
791 /* 507 */ "T1\0"
792 /* 510 */ "V1\0"
793 /* 513 */ "W1\0"
794 /* 516 */ "COP02\0"
795 /* 522 */ "COP012\0"
796 /* 529 */ "COP212\0"
797 /* 536 */ "COP312\0"
798 /* 543 */ "MSA12\0"
799 /* 549 */ "D12\0"
800 /* 553 */ "F12\0"
801 /* 557 */ "F_HI12\0"
802 /* 564 */ "FCR12\0"
803 /* 570 */ "HWR12\0"
804 /* 576 */ "W12\0"
805 /* 580 */ "COP022\0"
806 /* 587 */ "COP222\0"
807 /* 594 */ "COP322\0"
808 /* 601 */ "MSA22\0"
809 /* 607 */ "F22\0"
810 /* 611 */ "F_HI22\0"
811 /* 618 */ "COP22\0"
812 /* 624 */ "FCR22\0"
813 /* 630 */ "HWR22\0"
814 /* 636 */ "W22\0"
815 /* 640 */ "DSPOutFlag22\0"
816 /* 653 */ "COP32\0"
817 /* 659 */ "A2\0"
818 /* 662 */ "AC2\0"
819 /* 666 */ "FCC2\0"
820 /* 671 */ "D2\0"
821 /* 674 */ "F2\0"
822 /* 677 */ "F_HI2\0"
823 /* 683 */ "MPL2\0"
824 /* 688 */ "LO2\0"
825 /* 692 */ "P2\0"
826 /* 695 */ "FCR2\0"
827 /* 700 */ "HWR2\0"
828 /* 705 */ "S2\0"
829 /* 708 */ "T2\0"
830 /* 711 */ "W2\0"
831 /* 714 */ "COP03\0"
832 /* 720 */ "COP013\0"
833 /* 727 */ "COP213\0"
834 /* 734 */ "COP313\0"
835 /* 741 */ "MSA13\0"
836 /* 747 */ "D13\0"
837 /* 751 */ "F13\0"
838 /* 755 */ "F_HI13\0"
839 /* 762 */ "FCR13\0"
840 /* 768 */ "HWR13\0"
841 /* 774 */ "W13\0"
842 /* 778 */ "COP023\0"
843 /* 785 */ "COP223\0"
844 /* 792 */ "COP323\0"
845 /* 799 */ "MSA23\0"
846 /* 805 */ "F23\0"
847 /* 809 */ "F_HI23\0"
848 /* 816 */ "COP23\0"
849 /* 822 */ "FCR23\0"
850 /* 828 */ "HWR23\0"
851 /* 834 */ "W23\0"
852 /* 838 */ "DSPOutFlag23\0"
853 /* 851 */ "COP33\0"
854 /* 857 */ "A3\0"
855 /* 860 */ "AC3\0"
856 /* 864 */ "FCC3\0"
857 /* 869 */ "D3\0"
858 /* 872 */ "F3\0"
859 /* 875 */ "F_HI3\0"
860 /* 881 */ "LO3\0"
861 /* 885 */ "FCR3\0"
862 /* 890 */ "HWR3\0"
863 /* 895 */ "S3\0"
864 /* 898 */ "T3\0"
865 /* 901 */ "W3\0"
866 /* 904 */ "COP04\0"
867 /* 910 */ "COP014\0"
868 /* 917 */ "COP214\0"
869 /* 924 */ "COP314\0"
870 /* 931 */ "MSA14\0"
871 /* 937 */ "D14\0"
872 /* 941 */ "F14\0"
873 /* 945 */ "F_HI14\0"
874 /* 952 */ "FCR14\0"
875 /* 958 */ "HWR14\0"
876 /* 964 */ "W14\0"
877 /* 968 */ "COP024\0"
878 /* 975 */ "COP224\0"
879 /* 982 */ "COP324\0"
880 /* 989 */ "MSA24\0"
881 /* 995 */ "F24\0"
882 /* 999 */ "F_HI24\0"
883 /* 1006 */ "COP24\0"
884 /* 1012 */ "FCR24\0"
885 /* 1018 */ "HWR24\0"
886 /* 1024 */ "W24\0"
887 /* 1028 */ "COP34\0"
888 /* 1034 */ "D10_64\0"
889 /* 1041 */ "D20_64\0"
890 /* 1048 */ "D30_64\0"
891 /* 1055 */ "A0_64\0"
892 /* 1061 */ "AC0_64\0"
893 /* 1068 */ "D0_64\0"
894 /* 1074 */ "HI0_64\0"
895 /* 1081 */ "K0_64\0"
896 /* 1087 */ "LO0_64\0"
897 /* 1094 */ "S0_64\0"
898 /* 1100 */ "T0_64\0"
899 /* 1106 */ "V0_64\0"
900 /* 1112 */ "D11_64\0"
901 /* 1119 */ "D21_64\0"
902 /* 1126 */ "D31_64\0"
903 /* 1133 */ "A1_64\0"
904 /* 1139 */ "D1_64\0"
905 /* 1145 */ "K1_64\0"
906 /* 1151 */ "S1_64\0"
907 /* 1157 */ "T1_64\0"
908 /* 1163 */ "V1_64\0"
909 /* 1169 */ "D12_64\0"
910 /* 1176 */ "D22_64\0"
911 /* 1183 */ "A2_64\0"
912 /* 1189 */ "D2_64\0"
913 /* 1195 */ "S2_64\0"
914 /* 1201 */ "T2_64\0"
915 /* 1207 */ "D13_64\0"
916 /* 1214 */ "D23_64\0"
917 /* 1221 */ "A3_64\0"
918 /* 1227 */ "D3_64\0"
919 /* 1233 */ "S3_64\0"
920 /* 1239 */ "T3_64\0"
921 /* 1245 */ "D14_64\0"
922 /* 1252 */ "D24_64\0"
923 /* 1259 */ "D4_64\0"
924 /* 1265 */ "S4_64\0"
925 /* 1271 */ "T4_64\0"
926 /* 1277 */ "D15_64\0"
927 /* 1284 */ "D25_64\0"
928 /* 1291 */ "D5_64\0"
929 /* 1297 */ "S5_64\0"
930 /* 1303 */ "T5_64\0"
931 /* 1309 */ "D16_64\0"
932 /* 1316 */ "D26_64\0"
933 /* 1323 */ "D6_64\0"
934 /* 1329 */ "S6_64\0"
935 /* 1335 */ "T6_64\0"
936 /* 1341 */ "D17_64\0"
937 /* 1348 */ "D27_64\0"
938 /* 1355 */ "D7_64\0"
939 /* 1361 */ "S7_64\0"
940 /* 1367 */ "T7_64\0"
941 /* 1373 */ "D18_64\0"
942 /* 1380 */ "D28_64\0"
943 /* 1387 */ "D8_64\0"
944 /* 1393 */ "T8_64\0"
945 /* 1399 */ "D19_64\0"
946 /* 1406 */ "D29_64\0"
947 /* 1413 */ "D9_64\0"
948 /* 1419 */ "T9_64\0"
949 /* 1425 */ "RA_64\0"
950 /* 1431 */ "ZERO_64\0"
951 /* 1439 */ "FP_64\0"
952 /* 1445 */ "GP_64\0"
953 /* 1451 */ "SP_64\0"
954 /* 1457 */ "AT_64\0"
955 /* 1463 */ "FCC4\0"
956 /* 1468 */ "D4\0"
957 /* 1471 */ "F4\0"
958 /* 1474 */ "F_HI4\0"
959 /* 1480 */ "FCR4\0"
960 /* 1485 */ "HWR4\0"
961 /* 1490 */ "S4\0"
962 /* 1493 */ "T4\0"
963 /* 1496 */ "W4\0"
964 /* 1499 */ "COP05\0"
965 /* 1505 */ "COP015\0"
966 /* 1512 */ "COP215\0"
967 /* 1519 */ "COP315\0"
968 /* 1526 */ "MSA15\0"
969 /* 1532 */ "D15\0"
970 /* 1536 */ "F15\0"
971 /* 1540 */ "F_HI15\0"
972 /* 1547 */ "FCR15\0"
973 /* 1553 */ "HWR15\0"
974 /* 1559 */ "W15\0"
975 /* 1563 */ "COP025\0"
976 /* 1570 */ "COP225\0"
977 /* 1577 */ "COP325\0"
978 /* 1584 */ "MSA25\0"
979 /* 1590 */ "F25\0"
980 /* 1594 */ "F_HI25\0"
981 /* 1601 */ "COP25\0"
982 /* 1607 */ "FCR25\0"
983 /* 1613 */ "HWR25\0"
984 /* 1619 */ "W25\0"
985 /* 1623 */ "COP35\0"
986 /* 1629 */ "FCC5\0"
987 /* 1634 */ "D5\0"
988 /* 1637 */ "F5\0"
989 /* 1640 */ "F_HI5\0"
990 /* 1646 */ "FCR5\0"
991 /* 1651 */ "HWR5\0"
992 /* 1656 */ "S5\0"
993 /* 1659 */ "T5\0"
994 /* 1662 */ "W5\0"
995 /* 1665 */ "COP06\0"
996 /* 1671 */ "COP016\0"
997 /* 1678 */ "COP216\0"
998 /* 1685 */ "COP316\0"
999 /* 1692 */ "MSA16\0"
1000 /* 1698 */ "F16\0"
1001 /* 1702 */ "F_HI16\0"
1002 /* 1709 */ "FCR16\0"
1003 /* 1715 */ "HWR16\0"
1004 /* 1721 */ "W16\0"
1005 /* 1725 */ "COP026\0"
1006 /* 1732 */ "COP226\0"
1007 /* 1739 */ "COP326\0"
1008 /* 1746 */ "MSA26\0"
1009 /* 1752 */ "F26\0"
1010 /* 1756 */ "F_HI26\0"
1011 /* 1763 */ "COP26\0"
1012 /* 1769 */ "FCR26\0"
1013 /* 1775 */ "HWR26\0"
1014 /* 1781 */ "W26\0"
1015 /* 1785 */ "COP36\0"
1016 /* 1791 */ "FCC6\0"
1017 /* 1796 */ "D6\0"
1018 /* 1799 */ "F6\0"
1019 /* 1802 */ "F_HI6\0"
1020 /* 1808 */ "FCR6\0"
1021 /* 1813 */ "HWR6\0"
1022 /* 1818 */ "S6\0"
1023 /* 1821 */ "T6\0"
1024 /* 1824 */ "W6\0"
1025 /* 1827 */ "COP07\0"
1026 /* 1833 */ "COP017\0"
1027 /* 1840 */ "COP217\0"
1028 /* 1847 */ "COP317\0"
1029 /* 1854 */ "MSA17\0"
1030 /* 1860 */ "F17\0"
1031 /* 1864 */ "F_HI17\0"
1032 /* 1871 */ "FCR17\0"
1033 /* 1877 */ "HWR17\0"
1034 /* 1883 */ "W17\0"
1035 /* 1887 */ "COP027\0"
1036 /* 1894 */ "COP227\0"
1037 /* 1901 */ "COP327\0"
1038 /* 1908 */ "MSA27\0"
1039 /* 1914 */ "F27\0"
1040 /* 1918 */ "F_HI27\0"
1041 /* 1925 */ "COP27\0"
1042 /* 1931 */ "FCR27\0"
1043 /* 1937 */ "HWR27\0"
1044 /* 1943 */ "W27\0"
1045 /* 1947 */ "COP37\0"
1046 /* 1953 */ "FCC7\0"
1047 /* 1958 */ "D7\0"
1048 /* 1961 */ "F7\0"
1049 /* 1964 */ "F_HI7\0"
1050 /* 1970 */ "FCR7\0"
1051 /* 1975 */ "HWR7\0"
1052 /* 1980 */ "S7\0"
1053 /* 1983 */ "T7\0"
1054 /* 1986 */ "W7\0"
1055 /* 1989 */ "COP08\0"
1056 /* 1995 */ "COP018\0"
1057 /* 2002 */ "COP218\0"
1058 /* 2009 */ "COP318\0"
1059 /* 2016 */ "MSA18\0"
1060 /* 2022 */ "F18\0"
1061 /* 2026 */ "F_HI18\0"
1062 /* 2033 */ "FCR18\0"
1063 /* 2039 */ "HWR18\0"
1064 /* 2045 */ "W18\0"
1065 /* 2049 */ "COP028\0"
1066 /* 2056 */ "COP228\0"
1067 /* 2063 */ "COP328\0"
1068 /* 2070 */ "MSA28\0"
1069 /* 2076 */ "F28\0"
1070 /* 2080 */ "F_HI28\0"
1071 /* 2087 */ "COP28\0"
1072 /* 2093 */ "FCR28\0"
1073 /* 2099 */ "HWR28\0"
1074 /* 2105 */ "W28\0"
1075 /* 2109 */ "COP38\0"
1076 /* 2115 */ "MSA8\0"
1077 /* 2120 */ "D8\0"
1078 /* 2123 */ "F8\0"
1079 /* 2126 */ "F_HI8\0"
1080 /* 2132 */ "FCR8\0"
1081 /* 2137 */ "HWR8\0"
1082 /* 2142 */ "T8\0"
1083 /* 2145 */ "W8\0"
1084 /* 2148 */ "COP09\0"
1085 /* 2154 */ "COP019\0"
1086 /* 2161 */ "COP219\0"
1087 /* 2168 */ "COP319\0"
1088 /* 2175 */ "MSA19\0"
1089 /* 2181 */ "F19\0"
1090 /* 2185 */ "F_HI19\0"
1091 /* 2192 */ "FCR19\0"
1092 /* 2198 */ "HWR19\0"
1093 /* 2204 */ "W19\0"
1094 /* 2208 */ "DSPOutFlag16_19\0"
1095 /* 2224 */ "COP029\0"
1096 /* 2231 */ "COP229\0"
1097 /* 2238 */ "COP329\0"
1098 /* 2245 */ "MSA29\0"
1099 /* 2251 */ "F29\0"
1100 /* 2255 */ "F_HI29\0"
1101 /* 2262 */ "COP29\0"
1102 /* 2268 */ "FCR29\0"
1103 /* 2274 */ "HWR29\0"
1104 /* 2280 */ "W29\0"
1105 /* 2284 */ "COP39\0"
1106 /* 2290 */ "MSA9\0"
1107 /* 2295 */ "D9\0"
1108 /* 2298 */ "F9\0"
1109 /* 2301 */ "F_HI9\0"
1110 /* 2307 */ "FCR9\0"
1111 /* 2312 */ "HWR9\0"
1112 /* 2317 */ "T9\0"
1113 /* 2320 */ "W9\0"
1114 /* 2323 */ "RA\0"
1115 /* 2326 */ "PC\0"
1116 /* 2329 */ "DSPEFI\0"
1117 /* 2336 */ "ZERO\0"
1118 /* 2341 */ "FP\0"
1119 /* 2344 */ "GP\0"
1120 /* 2347 */ "SP\0"
1121 /* 2350 */ "MSAIR\0"
1122 /* 2356 */ "MSACSR\0"
1123 /* 2363 */ "AT\0"
1124 /* 2366 */ "DSPCCond\0"
1125 /* 2375 */ "MSASave\0"
1126 /* 2383 */ "DSPOutFlag\0"
1127 /* 2394 */ "MSAMap\0"
1128 /* 2401 */ "MSAUnmap\0"
1129 /* 2410 */ "DSPPos\0"
1130 /* 2417 */ "MSAAccess\0"
1131 /* 2427 */ "DSPSCount\0"
1132 /* 2437 */ "MSARequest\0"
1133 /* 2448 */ "MSAModify\0"
1134 /* 2458 */ "DSPCarry\0"
1135};
1136#ifdef __GNUC__
1137#pragma GCC diagnostic pop
1138#endif
1139
1140extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1141 { 5, 0, 0, 0, 0, 0, 0 },
1142 { 2363, 1, 176, 1, 4096, 11, 0 },
1143 { 2366, 1, 1, 1, 4097, 11, 0 },
1144 { 2458, 1, 1, 1, 4098, 11, 0 },
1145 { 2329, 1, 1, 1, 4099, 11, 0 },
1146 { 2383, 117, 1, 2, 503812, 2, 0 },
1147 { 2410, 1, 1, 1, 4105, 11, 0 },
1148 { 2427, 1, 1, 1, 4106, 11, 0 },
1149 { 2341, 1, 190, 1, 4107, 11, 0 },
1150 { 2344, 1, 192, 1, 4108, 11, 0 },
1151 { 2417, 1, 1, 1, 4109, 11, 0 },
1152 { 2356, 1, 1, 1, 4110, 11, 0 },
1153 { 2350, 1, 1, 1, 4111, 11, 0 },
1154 { 2394, 1, 1, 1, 4112, 11, 0 },
1155 { 2448, 1, 1, 1, 4113, 11, 0 },
1156 { 2437, 1, 1, 1, 4114, 11, 0 },
1157 { 2375, 1, 1, 1, 4115, 11, 0 },
1158 { 2401, 1, 1, 1, 4116, 11, 0 },
1159 { 2326, 1, 1, 1, 4117, 11, 0 },
1160 { 2323, 1, 194, 1, 4118, 11, 0 },
1161 { 2347, 1, 196, 1, 4119, 11, 0 },
1162 { 2336, 1, 198, 1, 4120, 11, 1 },
1163 { 197, 1, 198, 1, 4121, 11, 0 },
1164 { 455, 1, 198, 1, 4122, 11, 0 },
1165 { 659, 1, 198, 1, 4123, 11, 0 },
1166 { 857, 1, 198, 1, 4124, 11, 0 },
1167 { 200, 68, 198, 9, 495645, 8, 0 },
1168 { 458, 68, 1, 9, 495647, 8, 0 },
1169 { 662, 68, 1, 9, 495649, 8, 0 },
1170 { 860, 68, 1, 9, 495651, 8, 0 },
1171 { 1457, 115, 1, 0, 4096, 0, 0 },
1172 { 0, 1, 1, 1, 4133, 11, 0 },
1173 { 258, 1, 1, 1, 4134, 11, 0 },
1174 { 516, 1, 1, 1, 4135, 11, 0 },
1175 { 714, 1, 1, 1, 4136, 11, 0 },
1176 { 904, 1, 1, 1, 4137, 11, 0 },
1177 { 1499, 1, 1, 1, 4138, 11, 0 },
1178 { 1665, 1, 1, 1, 4139, 11, 0 },
1179 { 1827, 1, 1, 1, 4140, 11, 0 },
1180 { 1989, 1, 1, 1, 4141, 11, 0 },
1181 { 2148, 1, 1, 1, 4142, 11, 0 },
1182 { 102, 1, 1, 1, 4143, 11, 0 },
1183 { 360, 1, 1, 1, 4144, 11, 0 },
1184 { 618, 1, 1, 1, 4145, 11, 0 },
1185 { 816, 1, 1, 1, 4146, 11, 0 },
1186 { 1006, 1, 1, 1, 4147, 11, 0 },
1187 { 1601, 1, 1, 1, 4148, 11, 0 },
1188 { 1763, 1, 1, 1, 4149, 11, 0 },
1189 { 1925, 1, 1, 1, 4150, 11, 0 },
1190 { 2087, 1, 1, 1, 4151, 11, 0 },
1191 { 2262, 1, 1, 1, 4152, 11, 0 },
1192 { 175, 1, 1, 1, 4153, 11, 0 },
1193 { 433, 1, 1, 1, 4154, 11, 0 },
1194 { 653, 1, 1, 1, 4155, 11, 0 },
1195 { 851, 1, 1, 1, 4156, 11, 0 },
1196 { 1028, 1, 1, 1, 4157, 11, 0 },
1197 { 1623, 1, 1, 1, 4158, 11, 0 },
1198 { 1785, 1, 1, 1, 4159, 11, 0 },
1199 { 1947, 1, 1, 1, 4160, 11, 0 },
1200 { 2109, 1, 1, 1, 4161, 11, 0 },
1201 { 2284, 1, 1, 1, 4162, 11, 0 },
1202 { 6, 1, 1, 1, 4163, 11, 0 },
1203 { 264, 1, 1, 1, 4164, 11, 0 },
1204 { 522, 1, 1, 1, 4165, 11, 0 },
1205 { 720, 1, 1, 1, 4166, 11, 0 },
1206 { 910, 1, 1, 1, 4167, 11, 0 },
1207 { 1505, 1, 1, 1, 4168, 11, 0 },
1208 { 1671, 1, 1, 1, 4169, 11, 0 },
1209 { 1833, 1, 1, 1, 4170, 11, 0 },
1210 { 1995, 1, 1, 1, 4171, 11, 0 },
1211 { 2154, 1, 1, 1, 4172, 11, 0 },
1212 { 64, 1, 1, 1, 4173, 11, 0 },
1213 { 322, 1, 1, 1, 4174, 11, 0 },
1214 { 580, 1, 1, 1, 4175, 11, 0 },
1215 { 778, 1, 1, 1, 4176, 11, 0 },
1216 { 968, 1, 1, 1, 4177, 11, 0 },
1217 { 1563, 1, 1, 1, 4178, 11, 0 },
1218 { 1725, 1, 1, 1, 4179, 11, 0 },
1219 { 1887, 1, 1, 1, 4180, 11, 0 },
1220 { 2049, 1, 1, 1, 4181, 11, 0 },
1221 { 2224, 1, 1, 1, 4182, 11, 0 },
1222 { 137, 1, 1, 1, 4183, 11, 0 },
1223 { 395, 1, 1, 1, 4184, 11, 0 },
1224 { 13, 1, 1, 1, 4185, 11, 0 },
1225 { 271, 1, 1, 1, 4186, 11, 0 },
1226 { 529, 1, 1, 1, 4187, 11, 0 },
1227 { 727, 1, 1, 1, 4188, 11, 0 },
1228 { 917, 1, 1, 1, 4189, 11, 0 },
1229 { 1512, 1, 1, 1, 4190, 11, 0 },
1230 { 1678, 1, 1, 1, 4191, 11, 0 },
1231 { 1840, 1, 1, 1, 4192, 11, 0 },
1232 { 2002, 1, 1, 1, 4193, 11, 0 },
1233 { 2161, 1, 1, 1, 4194, 11, 0 },
1234 { 71, 1, 1, 1, 4195, 11, 0 },
1235 { 329, 1, 1, 1, 4196, 11, 0 },
1236 { 587, 1, 1, 1, 4197, 11, 0 },
1237 { 785, 1, 1, 1, 4198, 11, 0 },
1238 { 975, 1, 1, 1, 4199, 11, 0 },
1239 { 1570, 1, 1, 1, 4200, 11, 0 },
1240 { 1732, 1, 1, 1, 4201, 11, 0 },
1241 { 1894, 1, 1, 1, 4202, 11, 0 },
1242 { 2056, 1, 1, 1, 4203, 11, 0 },
1243 { 2231, 1, 1, 1, 4204, 11, 0 },
1244 { 144, 1, 1, 1, 4205, 11, 0 },
1245 { 402, 1, 1, 1, 4206, 11, 0 },
1246 { 20, 1, 1, 1, 4207, 11, 0 },
1247 { 278, 1, 1, 1, 4208, 11, 0 },
1248 { 536, 1, 1, 1, 4209, 11, 0 },
1249 { 734, 1, 1, 1, 4210, 11, 0 },
1250 { 924, 1, 1, 1, 4211, 11, 0 },
1251 { 1519, 1, 1, 1, 4212, 11, 0 },
1252 { 1685, 1, 1, 1, 4213, 11, 0 },
1253 { 1847, 1, 1, 1, 4214, 11, 0 },
1254 { 2009, 1, 1, 1, 4215, 11, 0 },
1255 { 2168, 1, 1, 1, 4216, 11, 0 },
1256 { 78, 1, 1, 1, 4217, 11, 0 },
1257 { 336, 1, 1, 1, 4218, 11, 0 },
1258 { 594, 1, 1, 1, 4219, 11, 0 },
1259 { 792, 1, 1, 1, 4220, 11, 0 },
1260 { 982, 1, 1, 1, 4221, 11, 0 },
1261 { 1577, 1, 1, 1, 4222, 11, 0 },
1262 { 1739, 1, 1, 1, 4223, 11, 0 },
1263 { 1901, 1, 1, 1, 4224, 11, 0 },
1264 { 2063, 1, 1, 1, 4225, 11, 0 },
1265 { 2238, 1, 1, 1, 4226, 11, 0 },
1266 { 151, 1, 1, 1, 4227, 11, 0 },
1267 { 409, 1, 1, 1, 4228, 11, 0 },
1268 { 209, 128, 1, 9, 495749, 8, 0 },
1269 { 467, 131, 1, 9, 495751, 8, 0 },
1270 { 671, 134, 1, 9, 495753, 8, 0 },
1271 { 869, 137, 1, 9, 495755, 8, 0 },
1272 { 1468, 140, 1, 9, 495757, 8, 0 },
1273 { 1634, 143, 1, 9, 495759, 8, 0 },
1274 { 1796, 146, 1, 9, 495761, 8, 0 },
1275 { 1958, 149, 1, 9, 495763, 8, 0 },
1276 { 2120, 152, 1, 9, 495765, 8, 0 },
1277 { 2295, 155, 1, 9, 495767, 8, 0 },
1278 { 33, 158, 1, 9, 495769, 8, 0 },
1279 { 291, 161, 1, 9, 495771, 8, 0 },
1280 { 549, 164, 1, 9, 495773, 8, 0 },
1281 { 747, 167, 1, 9, 495775, 8, 0 },
1282 { 937, 170, 1, 9, 495777, 8, 0 },
1283 { 1532, 173, 1, 9, 495779, 8, 0 },
1284 { 124, 1, 28, 1, 4101, 11, 0 },
1285 { 382, 1, 26, 1, 4102, 11, 0 },
1286 { 640, 1, 24, 1, 4103, 11, 0 },
1287 { 838, 1, 22, 1, 4104, 11, 0 },
1288 { 212, 1, 39, 1, 4229, 11, 0 },
1289 { 470, 1, 43, 1, 4230, 11, 0 },
1290 { 674, 1, 43, 1, 4231, 11, 0 },
1291 { 872, 1, 47, 1, 4232, 11, 0 },
1292 { 1471, 1, 47, 1, 4233, 11, 0 },
1293 { 1637, 1, 51, 1, 4234, 11, 0 },
1294 { 1799, 1, 51, 1, 4235, 11, 0 },
1295 { 1961, 1, 55, 1, 4236, 11, 0 },
1296 { 2123, 1, 55, 1, 4237, 11, 0 },
1297 { 2298, 1, 59, 1, 4238, 11, 0 },
1298 { 37, 1, 59, 1, 4239, 11, 0 },
1299 { 295, 1, 63, 1, 4240, 11, 0 },
1300 { 553, 1, 63, 1, 4241, 11, 0 },
1301 { 751, 1, 67, 1, 4242, 11, 0 },
1302 { 941, 1, 67, 1, 4243, 11, 0 },
1303 { 1536, 1, 71, 1, 4244, 11, 0 },
1304 { 1698, 1, 71, 1, 4245, 11, 0 },
1305 { 1860, 1, 75, 1, 4246, 11, 0 },
1306 { 2022, 1, 75, 1, 4247, 11, 0 },
1307 { 2181, 1, 79, 1, 4248, 11, 0 },
1308 { 91, 1, 79, 1, 4249, 11, 0 },
1309 { 349, 1, 83, 1, 4250, 11, 0 },
1310 { 607, 1, 83, 1, 4251, 11, 0 },
1311 { 805, 1, 87, 1, 4252, 11, 0 },
1312 { 995, 1, 87, 1, 4253, 11, 0 },
1313 { 1590, 1, 91, 1, 4254, 11, 0 },
1314 { 1752, 1, 91, 1, 4255, 11, 0 },
1315 { 1914, 1, 95, 1, 4256, 11, 0 },
1316 { 2076, 1, 95, 1, 4257, 11, 0 },
1317 { 2251, 1, 99, 1, 4258, 11, 0 },
1318 { 164, 1, 99, 1, 4259, 11, 0 },
1319 { 422, 1, 103, 1, 4260, 11, 0 },
1320 { 204, 1, 1, 1, 4261, 11, 0 },
1321 { 462, 1, 1, 1, 4262, 11, 0 },
1322 { 666, 1, 1, 1, 4263, 11, 0 },
1323 { 864, 1, 1, 1, 4264, 11, 0 },
1324 { 1463, 1, 1, 1, 4265, 11, 0 },
1325 { 1629, 1, 1, 1, 4266, 11, 0 },
1326 { 1791, 1, 1, 1, 4267, 11, 0 },
1327 { 1953, 1, 1, 1, 4268, 11, 0 },
1328 { 236, 1, 1, 1, 4269, 11, 0 },
1329 { 494, 1, 1, 1, 4270, 11, 0 },
1330 { 695, 1, 1, 1, 4271, 11, 0 },
1331 { 885, 1, 1, 1, 4272, 11, 0 },
1332 { 1480, 1, 1, 1, 4273, 11, 0 },
1333 { 1646, 1, 1, 1, 4274, 11, 0 },
1334 { 1808, 1, 1, 1, 4275, 11, 0 },
1335 { 1970, 1, 1, 1, 4276, 11, 0 },
1336 { 2132, 1, 1, 1, 4277, 11, 0 },
1337 { 2307, 1, 1, 1, 4278, 11, 0 },
1338 { 48, 1, 1, 1, 4279, 11, 0 },
1339 { 306, 1, 1, 1, 4280, 11, 0 },
1340 { 564, 1, 1, 1, 4281, 11, 0 },
1341 { 762, 1, 1, 1, 4282, 11, 0 },
1342 { 952, 1, 1, 1, 4283, 11, 0 },
1343 { 1547, 1, 1, 1, 4284, 11, 0 },
1344 { 1709, 1, 1, 1, 4285, 11, 0 },
1345 { 1871, 1, 1, 1, 4286, 11, 0 },
1346 { 2033, 1, 1, 1, 4287, 11, 0 },
1347 { 2192, 1, 1, 1, 4288, 11, 0 },
1348 { 108, 1, 1, 1, 4289, 11, 0 },
1349 { 366, 1, 1, 1, 4290, 11, 0 },
1350 { 624, 1, 1, 1, 4291, 11, 0 },
1351 { 822, 1, 1, 1, 4292, 11, 0 },
1352 { 1012, 1, 1, 1, 4293, 11, 0 },
1353 { 1607, 1, 1, 1, 4294, 11, 0 },
1354 { 1769, 1, 1, 1, 4295, 11, 0 },
1355 { 1931, 1, 1, 1, 4296, 11, 0 },
1356 { 2093, 1, 1, 1, 4297, 11, 0 },
1357 { 2268, 1, 1, 1, 4298, 11, 0 },
1358 { 181, 1, 1, 1, 4299, 11, 0 },
1359 { 439, 1, 1, 1, 4300, 11, 0 },
1360 { 1439, 18, 1, 0, 4107, 0, 0 },
1361 { 215, 1, 36, 1, 4301, 11, 0 },
1362 { 473, 1, 36, 1, 4302, 11, 0 },
1363 { 677, 1, 36, 1, 4303, 11, 0 },
1364 { 875, 1, 36, 1, 4304, 11, 0 },
1365 { 1474, 1, 36, 1, 4305, 11, 0 },
1366 { 1640, 1, 36, 1, 4306, 11, 0 },
1367 { 1802, 1, 36, 1, 4307, 11, 0 },
1368 { 1964, 1, 36, 1, 4308, 11, 0 },
1369 { 2126, 1, 36, 1, 4309, 11, 0 },
1370 { 2301, 1, 36, 1, 4310, 11, 0 },
1371 { 41, 1, 36, 1, 4311, 11, 0 },
1372 { 299, 1, 36, 1, 4312, 11, 0 },
1373 { 557, 1, 36, 1, 4313, 11, 0 },
1374 { 755, 1, 36, 1, 4314, 11, 0 },
1375 { 945, 1, 36, 1, 4315, 11, 0 },
1376 { 1540, 1, 36, 1, 4316, 11, 0 },
1377 { 1702, 1, 36, 1, 4317, 11, 0 },
1378 { 1864, 1, 36, 1, 4318, 11, 0 },
1379 { 2026, 1, 36, 1, 4319, 11, 0 },
1380 { 2185, 1, 36, 1, 4320, 11, 0 },
1381 { 95, 1, 36, 1, 4321, 11, 0 },
1382 { 353, 1, 36, 1, 4322, 11, 0 },
1383 { 611, 1, 36, 1, 4323, 11, 0 },
1384 { 809, 1, 36, 1, 4324, 11, 0 },
1385 { 999, 1, 36, 1, 4325, 11, 0 },
1386 { 1594, 1, 36, 1, 4326, 11, 0 },
1387 { 1756, 1, 36, 1, 4327, 11, 0 },
1388 { 1918, 1, 36, 1, 4328, 11, 0 },
1389 { 2080, 1, 36, 1, 4329, 11, 0 },
1390 { 2255, 1, 36, 1, 4330, 11, 0 },
1391 { 168, 1, 36, 1, 4331, 11, 0 },
1392 { 426, 1, 36, 1, 4332, 11, 0 },
1393 { 1445, 10, 1, 0, 4108, 0, 0 },
1394 { 217, 1, 111, 1, 4126, 11, 0 },
1395 { 475, 1, 16, 1, 4128, 11, 0 },
1396 { 679, 1, 16, 1, 4130, 11, 0 },
1397 { 877, 1, 16, 1, 4132, 11, 0 },
1398 { 241, 1, 1, 1, 4333, 11, 0 },
1399 { 499, 1, 1, 1, 4334, 11, 0 },
1400 { 700, 1, 1, 1, 4335, 11, 0 },
1401 { 890, 1, 1, 1, 4336, 11, 0 },
1402 { 1485, 1, 1, 1, 4337, 11, 0 },
1403 { 1651, 1, 1, 1, 4338, 11, 0 },
1404 { 1813, 1, 1, 1, 4339, 11, 0 },
1405 { 1975, 1, 1, 1, 4340, 11, 0 },
1406 { 2137, 1, 1, 1, 4341, 11, 0 },
1407 { 2312, 1, 1, 1, 4342, 11, 0 },
1408 { 54, 1, 1, 1, 4343, 11, 0 },
1409 { 312, 1, 1, 1, 4344, 11, 0 },
1410 { 570, 1, 1, 1, 4345, 11, 0 },
1411 { 768, 1, 1, 1, 4346, 11, 0 },
1412 { 958, 1, 1, 1, 4347, 11, 0 },
1413 { 1553, 1, 1, 1, 4348, 11, 0 },
1414 { 1715, 1, 1, 1, 4349, 11, 0 },
1415 { 1877, 1, 1, 1, 4350, 11, 0 },
1416 { 2039, 1, 1, 1, 4351, 11, 0 },
1417 { 2198, 1, 1, 1, 4352, 11, 0 },
1418 { 114, 1, 1, 1, 4353, 11, 0 },
1419 { 372, 1, 1, 1, 4354, 11, 0 },
1420 { 630, 1, 1, 1, 4355, 11, 0 },
1421 { 828, 1, 1, 1, 4356, 11, 0 },
1422 { 1018, 1, 1, 1, 4357, 11, 0 },
1423 { 1613, 1, 1, 1, 4358, 11, 0 },
1424 { 1775, 1, 1, 1, 4359, 11, 0 },
1425 { 1937, 1, 1, 1, 4360, 11, 0 },
1426 { 2099, 1, 1, 1, 4361, 11, 0 },
1427 { 2274, 1, 1, 1, 4362, 11, 0 },
1428 { 187, 1, 1, 1, 4363, 11, 0 },
1429 { 445, 1, 1, 1, 4364, 11, 0 },
1430 { 221, 1, 188, 1, 4365, 11, 0 },
1431 { 479, 1, 188, 1, 4366, 11, 0 },
1432 { 229, 1, 107, 1, 4125, 11, 0 },
1433 { 487, 1, 8, 1, 4127, 11, 0 },
1434 { 688, 1, 8, 1, 4129, 11, 0 },
1435 { 881, 1, 8, 1, 4131, 11, 0 },
1436 { 224, 1, 1, 1, 4367, 11, 0 },
1437 { 482, 1, 1, 1, 4368, 11, 0 },
1438 { 683, 1, 1, 1, 4369, 11, 0 },
1439 { 2115, 1, 1, 1, 4370, 11, 0 },
1440 { 2290, 1, 1, 1, 4371, 11, 0 },
1441 { 27, 1, 1, 1, 4372, 11, 0 },
1442 { 285, 1, 1, 1, 4373, 11, 0 },
1443 { 543, 1, 1, 1, 4374, 11, 0 },
1444 { 741, 1, 1, 1, 4375, 11, 0 },
1445 { 931, 1, 1, 1, 4376, 11, 0 },
1446 { 1526, 1, 1, 1, 4377, 11, 0 },
1447 { 1692, 1, 1, 1, 4378, 11, 0 },
1448 { 1854, 1, 1, 1, 4379, 11, 0 },
1449 { 2016, 1, 1, 1, 4380, 11, 0 },
1450 { 2175, 1, 1, 1, 4381, 11, 0 },
1451 { 85, 1, 1, 1, 4382, 11, 0 },
1452 { 343, 1, 1, 1, 4383, 11, 0 },
1453 { 601, 1, 1, 1, 4384, 11, 0 },
1454 { 799, 1, 1, 1, 4385, 11, 0 },
1455 { 989, 1, 1, 1, 4386, 11, 0 },
1456 { 1584, 1, 1, 1, 4387, 11, 0 },
1457 { 1746, 1, 1, 1, 4388, 11, 0 },
1458 { 1908, 1, 1, 1, 4389, 11, 0 },
1459 { 2070, 1, 1, 1, 4390, 11, 0 },
1460 { 2245, 1, 1, 1, 4391, 11, 0 },
1461 { 158, 1, 1, 1, 4392, 11, 0 },
1462 { 416, 1, 1, 1, 4393, 11, 0 },
1463 { 233, 1, 1, 1, 4394, 11, 0 },
1464 { 491, 1, 1, 1, 4395, 11, 0 },
1465 { 692, 1, 1, 1, 4396, 11, 0 },
1466 { 1425, 6, 1, 0, 4118, 0, 0 },
1467 { 246, 1, 186, 1, 4397, 11, 0 },
1468 { 504, 1, 186, 1, 4398, 11, 0 },
1469 { 705, 1, 186, 1, 4399, 11, 0 },
1470 { 895, 1, 186, 1, 4400, 11, 0 },
1471 { 1490, 1, 186, 1, 4401, 11, 0 },
1472 { 1656, 1, 186, 1, 4402, 11, 0 },
1473 { 1818, 1, 186, 1, 4403, 11, 0 },
1474 { 1980, 1, 186, 1, 4404, 11, 0 },
1475 { 1451, 4, 1, 0, 4119, 0, 0 },
1476 { 249, 1, 184, 1, 4405, 11, 0 },
1477 { 507, 1, 184, 1, 4406, 11, 0 },
1478 { 708, 1, 184, 1, 4407, 11, 0 },
1479 { 898, 1, 184, 1, 4408, 11, 0 },
1480 { 1493, 1, 184, 1, 4409, 11, 0 },
1481 { 1659, 1, 184, 1, 4410, 11, 0 },
1482 { 1821, 1, 184, 1, 4411, 11, 0 },
1483 { 1983, 1, 184, 1, 4412, 11, 0 },
1484 { 2142, 1, 184, 1, 4413, 11, 0 },
1485 { 2317, 1, 184, 1, 4414, 11, 0 },
1486 { 252, 1, 184, 1, 4415, 11, 0 },
1487 { 510, 1, 184, 1, 4416, 11, 0 },
1488 { 255, 180, 1, 8, 729221, 8, 0 },
1489 { 513, 180, 1, 8, 729222, 8, 0 },
1490 { 711, 180, 1, 8, 729223, 8, 0 },
1491 { 901, 180, 1, 8, 729224, 8, 0 },
1492 { 1496, 180, 1, 8, 729225, 8, 0 },
1493 { 1662, 180, 1, 8, 729226, 8, 0 },
1494 { 1824, 180, 1, 8, 729227, 8, 0 },
1495 { 1986, 180, 1, 8, 729228, 8, 0 },
1496 { 2145, 180, 1, 8, 729229, 8, 0 },
1497 { 2320, 180, 1, 8, 729230, 8, 0 },
1498 { 60, 180, 1, 8, 729231, 8, 0 },
1499 { 318, 180, 1, 8, 729232, 8, 0 },
1500 { 576, 180, 1, 8, 729233, 8, 0 },
1501 { 774, 180, 1, 8, 729234, 8, 0 },
1502 { 964, 180, 1, 8, 729235, 8, 0 },
1503 { 1559, 180, 1, 8, 729236, 8, 0 },
1504 { 1721, 180, 1, 8, 729237, 8, 0 },
1505 { 1883, 180, 1, 8, 729238, 8, 0 },
1506 { 2045, 180, 1, 8, 729239, 8, 0 },
1507 { 2204, 180, 1, 8, 729240, 8, 0 },
1508 { 120, 180, 1, 8, 729241, 8, 0 },
1509 { 378, 180, 1, 8, 729242, 8, 0 },
1510 { 636, 180, 1, 8, 729243, 8, 0 },
1511 { 834, 180, 1, 8, 729244, 8, 0 },
1512 { 1024, 180, 1, 8, 729245, 8, 0 },
1513 { 1619, 180, 1, 8, 729246, 8, 0 },
1514 { 1781, 180, 1, 8, 729247, 8, 0 },
1515 { 1943, 180, 1, 8, 729248, 8, 0 },
1516 { 2105, 180, 1, 8, 729249, 8, 0 },
1517 { 2280, 180, 1, 8, 729250, 8, 0 },
1518 { 193, 180, 1, 8, 729251, 8, 0 },
1519 { 451, 180, 1, 8, 729252, 8, 0 },
1520 { 1431, 2, 1, 0, 4120, 0, 1 },
1521 { 1055, 2, 1, 0, 4121, 0, 0 },
1522 { 1133, 2, 1, 0, 4122, 0, 0 },
1523 { 1183, 2, 1, 0, 4123, 0, 0 },
1524 { 1221, 2, 1, 0, 4124, 0, 0 },
1525 { 1061, 12, 1, 12, 495645, 8, 0 },
1526 { 1068, 181, 37, 9, 729221, 8, 0 },
1527 { 1139, 181, 37, 9, 729222, 8, 0 },
1528 { 1189, 181, 37, 9, 729223, 8, 0 },
1529 { 1227, 181, 37, 9, 729224, 8, 0 },
1530 { 1259, 181, 37, 9, 729225, 8, 0 },
1531 { 1291, 181, 37, 9, 729226, 8, 0 },
1532 { 1323, 181, 37, 9, 729227, 8, 0 },
1533 { 1355, 181, 37, 9, 729228, 8, 0 },
1534 { 1387, 181, 37, 9, 729229, 8, 0 },
1535 { 1413, 181, 37, 9, 729230, 8, 0 },
1536 { 1034, 181, 37, 9, 729231, 8, 0 },
1537 { 1112, 181, 37, 9, 729232, 8, 0 },
1538 { 1169, 181, 37, 9, 729233, 8, 0 },
1539 { 1207, 181, 37, 9, 729234, 8, 0 },
1540 { 1245, 181, 37, 9, 729235, 8, 0 },
1541 { 1277, 181, 37, 9, 729236, 8, 0 },
1542 { 1309, 181, 37, 9, 729237, 8, 0 },
1543 { 1341, 181, 37, 9, 729238, 8, 0 },
1544 { 1373, 181, 37, 9, 729239, 8, 0 },
1545 { 1399, 181, 37, 9, 729240, 8, 0 },
1546 { 1041, 181, 37, 9, 729241, 8, 0 },
1547 { 1119, 181, 37, 9, 729242, 8, 0 },
1548 { 1176, 181, 37, 9, 729243, 8, 0 },
1549 { 1214, 181, 37, 9, 729244, 8, 0 },
1550 { 1252, 181, 37, 9, 729245, 8, 0 },
1551 { 1284, 181, 37, 9, 729246, 8, 0 },
1552 { 1316, 181, 37, 9, 729247, 8, 0 },
1553 { 1348, 181, 37, 9, 729248, 8, 0 },
1554 { 1380, 181, 37, 9, 729249, 8, 0 },
1555 { 1406, 181, 37, 9, 729250, 8, 0 },
1556 { 1048, 181, 37, 9, 729251, 8, 0 },
1557 { 1126, 181, 37, 9, 729252, 8, 0 },
1558 { 2208, 1, 0, 1, 4100, 11, 0 },
1559 { 1074, 20, 113, 0, 4126, 0, 0 },
1560 { 1081, 30, 1, 0, 4365, 0, 0 },
1561 { 1145, 30, 1, 0, 4366, 0, 0 },
1562 { 1087, 30, 109, 0, 4125, 0, 0 },
1563 { 1094, 32, 1, 0, 4397, 0, 0 },
1564 { 1151, 32, 1, 0, 4398, 0, 0 },
1565 { 1195, 32, 1, 0, 4399, 0, 0 },
1566 { 1233, 32, 1, 0, 4400, 0, 0 },
1567 { 1265, 32, 1, 0, 4401, 0, 0 },
1568 { 1297, 32, 1, 0, 4402, 0, 0 },
1569 { 1329, 32, 1, 0, 4403, 0, 0 },
1570 { 1361, 32, 1, 0, 4404, 0, 0 },
1571 { 1100, 34, 1, 0, 4405, 0, 0 },
1572 { 1157, 34, 1, 0, 4406, 0, 0 },
1573 { 1201, 34, 1, 0, 4407, 0, 0 },
1574 { 1239, 34, 1, 0, 4408, 0, 0 },
1575 { 1271, 34, 1, 0, 4409, 0, 0 },
1576 { 1303, 34, 1, 0, 4410, 0, 0 },
1577 { 1335, 34, 1, 0, 4411, 0, 0 },
1578 { 1367, 34, 1, 0, 4412, 0, 0 },
1579 { 1393, 34, 1, 0, 4413, 0, 0 },
1580 { 1419, 34, 1, 0, 4414, 0, 0 },
1581 { 1106, 34, 1, 0, 4415, 0, 0 },
1582 { 1163, 34, 1, 0, 4416, 0, 0 },
1583};
1584
1585extern const MCPhysReg MipsRegUnitRoots[][2] = {
1586 { Mips::AT },
1587 { Mips::DSPCCond },
1588 { Mips::DSPCarry },
1589 { Mips::DSPEFI },
1590 { Mips::DSPOutFlag16_19 },
1591 { Mips::DSPOutFlag20 },
1592 { Mips::DSPOutFlag21 },
1593 { Mips::DSPOutFlag22 },
1594 { Mips::DSPOutFlag23 },
1595 { Mips::DSPPos },
1596 { Mips::DSPSCount },
1597 { Mips::FP },
1598 { Mips::GP },
1599 { Mips::MSAAccess },
1600 { Mips::MSACSR },
1601 { Mips::MSAIR },
1602 { Mips::MSAMap },
1603 { Mips::MSAModify },
1604 { Mips::MSARequest },
1605 { Mips::MSASave },
1606 { Mips::MSAUnmap },
1607 { Mips::PC },
1608 { Mips::RA },
1609 { Mips::SP },
1610 { Mips::ZERO },
1611 { Mips::A0 },
1612 { Mips::A1 },
1613 { Mips::A2 },
1614 { Mips::A3 },
1615 { Mips::LO0 },
1616 { Mips::HI0 },
1617 { Mips::LO1 },
1618 { Mips::HI1 },
1619 { Mips::LO2 },
1620 { Mips::HI2 },
1621 { Mips::LO3 },
1622 { Mips::HI3 },
1623 { Mips::COP00 },
1624 { Mips::COP01 },
1625 { Mips::COP02 },
1626 { Mips::COP03 },
1627 { Mips::COP04 },
1628 { Mips::COP05 },
1629 { Mips::COP06 },
1630 { Mips::COP07 },
1631 { Mips::COP08 },
1632 { Mips::COP09 },
1633 { Mips::COP20 },
1634 { Mips::COP21 },
1635 { Mips::COP22 },
1636 { Mips::COP23 },
1637 { Mips::COP24 },
1638 { Mips::COP25 },
1639 { Mips::COP26 },
1640 { Mips::COP27 },
1641 { Mips::COP28 },
1642 { Mips::COP29 },
1643 { Mips::COP30 },
1644 { Mips::COP31 },
1645 { Mips::COP32 },
1646 { Mips::COP33 },
1647 { Mips::COP34 },
1648 { Mips::COP35 },
1649 { Mips::COP36 },
1650 { Mips::COP37 },
1651 { Mips::COP38 },
1652 { Mips::COP39 },
1653 { Mips::COP010 },
1654 { Mips::COP011 },
1655 { Mips::COP012 },
1656 { Mips::COP013 },
1657 { Mips::COP014 },
1658 { Mips::COP015 },
1659 { Mips::COP016 },
1660 { Mips::COP017 },
1661 { Mips::COP018 },
1662 { Mips::COP019 },
1663 { Mips::COP020 },
1664 { Mips::COP021 },
1665 { Mips::COP022 },
1666 { Mips::COP023 },
1667 { Mips::COP024 },
1668 { Mips::COP025 },
1669 { Mips::COP026 },
1670 { Mips::COP027 },
1671 { Mips::COP028 },
1672 { Mips::COP029 },
1673 { Mips::COP030 },
1674 { Mips::COP031 },
1675 { Mips::COP210 },
1676 { Mips::COP211 },
1677 { Mips::COP212 },
1678 { Mips::COP213 },
1679 { Mips::COP214 },
1680 { Mips::COP215 },
1681 { Mips::COP216 },
1682 { Mips::COP217 },
1683 { Mips::COP218 },
1684 { Mips::COP219 },
1685 { Mips::COP220 },
1686 { Mips::COP221 },
1687 { Mips::COP222 },
1688 { Mips::COP223 },
1689 { Mips::COP224 },
1690 { Mips::COP225 },
1691 { Mips::COP226 },
1692 { Mips::COP227 },
1693 { Mips::COP228 },
1694 { Mips::COP229 },
1695 { Mips::COP230 },
1696 { Mips::COP231 },
1697 { Mips::COP310 },
1698 { Mips::COP311 },
1699 { Mips::COP312 },
1700 { Mips::COP313 },
1701 { Mips::COP314 },
1702 { Mips::COP315 },
1703 { Mips::COP316 },
1704 { Mips::COP317 },
1705 { Mips::COP318 },
1706 { Mips::COP319 },
1707 { Mips::COP320 },
1708 { Mips::COP321 },
1709 { Mips::COP322 },
1710 { Mips::COP323 },
1711 { Mips::COP324 },
1712 { Mips::COP325 },
1713 { Mips::COP326 },
1714 { Mips::COP327 },
1715 { Mips::COP328 },
1716 { Mips::COP329 },
1717 { Mips::COP330 },
1718 { Mips::COP331 },
1719 { Mips::F0 },
1720 { Mips::F1 },
1721 { Mips::F2 },
1722 { Mips::F3 },
1723 { Mips::F4 },
1724 { Mips::F5 },
1725 { Mips::F6 },
1726 { Mips::F7 },
1727 { Mips::F8 },
1728 { Mips::F9 },
1729 { Mips::F10 },
1730 { Mips::F11 },
1731 { Mips::F12 },
1732 { Mips::F13 },
1733 { Mips::F14 },
1734 { Mips::F15 },
1735 { Mips::F16 },
1736 { Mips::F17 },
1737 { Mips::F18 },
1738 { Mips::F19 },
1739 { Mips::F20 },
1740 { Mips::F21 },
1741 { Mips::F22 },
1742 { Mips::F23 },
1743 { Mips::F24 },
1744 { Mips::F25 },
1745 { Mips::F26 },
1746 { Mips::F27 },
1747 { Mips::F28 },
1748 { Mips::F29 },
1749 { Mips::F30 },
1750 { Mips::F31 },
1751 { Mips::FCC0 },
1752 { Mips::FCC1 },
1753 { Mips::FCC2 },
1754 { Mips::FCC3 },
1755 { Mips::FCC4 },
1756 { Mips::FCC5 },
1757 { Mips::FCC6 },
1758 { Mips::FCC7 },
1759 { Mips::FCR0 },
1760 { Mips::FCR1 },
1761 { Mips::FCR2 },
1762 { Mips::FCR3 },
1763 { Mips::FCR4 },
1764 { Mips::FCR5 },
1765 { Mips::FCR6 },
1766 { Mips::FCR7 },
1767 { Mips::FCR8 },
1768 { Mips::FCR9 },
1769 { Mips::FCR10 },
1770 { Mips::FCR11 },
1771 { Mips::FCR12 },
1772 { Mips::FCR13 },
1773 { Mips::FCR14 },
1774 { Mips::FCR15 },
1775 { Mips::FCR16 },
1776 { Mips::FCR17 },
1777 { Mips::FCR18 },
1778 { Mips::FCR19 },
1779 { Mips::FCR20 },
1780 { Mips::FCR21 },
1781 { Mips::FCR22 },
1782 { Mips::FCR23 },
1783 { Mips::FCR24 },
1784 { Mips::FCR25 },
1785 { Mips::FCR26 },
1786 { Mips::FCR27 },
1787 { Mips::FCR28 },
1788 { Mips::FCR29 },
1789 { Mips::FCR30 },
1790 { Mips::FCR31 },
1791 { Mips::F_HI0 },
1792 { Mips::F_HI1 },
1793 { Mips::F_HI2 },
1794 { Mips::F_HI3 },
1795 { Mips::F_HI4 },
1796 { Mips::F_HI5 },
1797 { Mips::F_HI6 },
1798 { Mips::F_HI7 },
1799 { Mips::F_HI8 },
1800 { Mips::F_HI9 },
1801 { Mips::F_HI10 },
1802 { Mips::F_HI11 },
1803 { Mips::F_HI12 },
1804 { Mips::F_HI13 },
1805 { Mips::F_HI14 },
1806 { Mips::F_HI15 },
1807 { Mips::F_HI16 },
1808 { Mips::F_HI17 },
1809 { Mips::F_HI18 },
1810 { Mips::F_HI19 },
1811 { Mips::F_HI20 },
1812 { Mips::F_HI21 },
1813 { Mips::F_HI22 },
1814 { Mips::F_HI23 },
1815 { Mips::F_HI24 },
1816 { Mips::F_HI25 },
1817 { Mips::F_HI26 },
1818 { Mips::F_HI27 },
1819 { Mips::F_HI28 },
1820 { Mips::F_HI29 },
1821 { Mips::F_HI30 },
1822 { Mips::F_HI31 },
1823 { Mips::HWR0 },
1824 { Mips::HWR1 },
1825 { Mips::HWR2 },
1826 { Mips::HWR3 },
1827 { Mips::HWR4 },
1828 { Mips::HWR5 },
1829 { Mips::HWR6 },
1830 { Mips::HWR7 },
1831 { Mips::HWR8 },
1832 { Mips::HWR9 },
1833 { Mips::HWR10 },
1834 { Mips::HWR11 },
1835 { Mips::HWR12 },
1836 { Mips::HWR13 },
1837 { Mips::HWR14 },
1838 { Mips::HWR15 },
1839 { Mips::HWR16 },
1840 { Mips::HWR17 },
1841 { Mips::HWR18 },
1842 { Mips::HWR19 },
1843 { Mips::HWR20 },
1844 { Mips::HWR21 },
1845 { Mips::HWR22 },
1846 { Mips::HWR23 },
1847 { Mips::HWR24 },
1848 { Mips::HWR25 },
1849 { Mips::HWR26 },
1850 { Mips::HWR27 },
1851 { Mips::HWR28 },
1852 { Mips::HWR29 },
1853 { Mips::HWR30 },
1854 { Mips::HWR31 },
1855 { Mips::K0 },
1856 { Mips::K1 },
1857 { Mips::MPL0 },
1858 { Mips::MPL1 },
1859 { Mips::MPL2 },
1860 { Mips::MSA8 },
1861 { Mips::MSA9 },
1862 { Mips::MSA10 },
1863 { Mips::MSA11 },
1864 { Mips::MSA12 },
1865 { Mips::MSA13 },
1866 { Mips::MSA14 },
1867 { Mips::MSA15 },
1868 { Mips::MSA16 },
1869 { Mips::MSA17 },
1870 { Mips::MSA18 },
1871 { Mips::MSA19 },
1872 { Mips::MSA20 },
1873 { Mips::MSA21 },
1874 { Mips::MSA22 },
1875 { Mips::MSA23 },
1876 { Mips::MSA24 },
1877 { Mips::MSA25 },
1878 { Mips::MSA26 },
1879 { Mips::MSA27 },
1880 { Mips::MSA28 },
1881 { Mips::MSA29 },
1882 { Mips::MSA30 },
1883 { Mips::MSA31 },
1884 { Mips::P0 },
1885 { Mips::P1 },
1886 { Mips::P2 },
1887 { Mips::S0 },
1888 { Mips::S1 },
1889 { Mips::S2 },
1890 { Mips::S3 },
1891 { Mips::S4 },
1892 { Mips::S5 },
1893 { Mips::S6 },
1894 { Mips::S7 },
1895 { Mips::T0 },
1896 { Mips::T1 },
1897 { Mips::T2 },
1898 { Mips::T3 },
1899 { Mips::T4 },
1900 { Mips::T5 },
1901 { Mips::T6 },
1902 { Mips::T7 },
1903 { Mips::T8 },
1904 { Mips::T9 },
1905 { Mips::V0 },
1906 { Mips::V1 },
1907};
1908
1909namespace { // Register classes...
1910 // MSA128F16 Register Class...
1911 const MCPhysReg MSA128F16[] = {
1912 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
1913 };
1914
1915 // MSA128F16 Bit set.
1916 const uint8_t MSA128F16Bits[] = {
1917 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1918 };
1919
1920 // CCR Register Class...
1921 const MCPhysReg CCR[] = {
1922 Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
1923 };
1924
1925 // CCR Bit set.
1926 const uint8_t CCRBits[] = {
1927 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1928 };
1929
1930 // COP0 Register Class...
1931 const MCPhysReg COP0[] = {
1932 Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
1933 };
1934
1935 // COP0 Bit set.
1936 const uint8_t COP0Bits[] = {
1937 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
1938 };
1939
1940 // COP2 Register Class...
1941 const MCPhysReg COP2[] = {
1942 Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
1943 };
1944
1945 // COP2 Bit set.
1946 const uint8_t COP2Bits[] = {
1947 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
1948 };
1949
1950 // COP3 Register Class...
1951 const MCPhysReg COP3[] = {
1952 Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
1953 };
1954
1955 // COP3 Bit set.
1956 const uint8_t COP3Bits[] = {
1957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1958 };
1959
1960 // DSPR Register Class...
1961 const MCPhysReg DSPR[] = {
1962 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1963 };
1964
1965 // DSPR Bit set.
1966 const uint8_t DSPRBits[] = {
1967 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
1968 };
1969
1970 // FGR32 Register Class...
1971 const MCPhysReg FGR32[] = {
1972 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1973 };
1974
1975 // FGR32 Bit set.
1976 const uint8_t FGR32Bits[] = {
1977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1978 };
1979
1980 // FGRCC Register Class...
1981 const MCPhysReg FGRCC[] = {
1982 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1983 };
1984
1985 // FGRCC Bit set.
1986 const uint8_t FGRCCBits[] = {
1987 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1988 };
1989
1990 // GPR32 Register Class...
1991 const MCPhysReg GPR32[] = {
1992 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1993 };
1994
1995 // GPR32 Bit set.
1996 const uint8_t GPR32Bits[] = {
1997 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
1998 };
1999
2000 // HWRegs Register Class...
2001 const MCPhysReg HWRegs[] = {
2002 Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
2003 };
2004
2005 // HWRegs Bit set.
2006 const uint8_t HWRegsBits[] = {
2007 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2008 };
2009
2010 // MSACtrl Register Class...
2011 const MCPhysReg MSACtrl[] = {
2012 Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,
2013 };
2014
2015 // MSACtrl Bit set.
2016 const uint8_t MSACtrlBits[] = {
2017 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,
2018 };
2019
2020 // GPR32NONZERO Register Class...
2021 const MCPhysReg GPR32NONZERO[] = {
2022 Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2023 };
2024
2025 // GPR32NONZERO Bit set.
2026 const uint8_t GPR32NONZEROBits[] = {
2027 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2028 };
2029
2030 // CPU16RegsPlusSP Register Class...
2031 const MCPhysReg CPU16RegsPlusSP[] = {
2032 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2033 };
2034
2035 // CPU16RegsPlusSP Bit set.
2036 const uint8_t CPU16RegsPlusSPBits[] = {
2037 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2038 };
2039
2040 // CPU16Regs Register Class...
2041 const MCPhysReg CPU16Regs[] = {
2042 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
2043 };
2044
2045 // CPU16Regs Bit set.
2046 const uint8_t CPU16RegsBits[] = {
2047 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2048 };
2049
2050 // FCC Register Class...
2051 const MCPhysReg FCC[] = {
2052 Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
2053 };
2054
2055 // FCC Bit set.
2056 const uint8_t FCCBits[] = {
2057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2058 };
2059
2060 // GPRMM16 Register Class...
2061 const MCPhysReg GPRMM16[] = {
2062 Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2063 };
2064
2065 // GPRMM16 Bit set.
2066 const uint8_t GPRMM16Bits[] = {
2067 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2068 };
2069
2070 // GPRMM16MoveP Register Class...
2071 const MCPhysReg GPRMM16MoveP[] = {
2072 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2073 };
2074
2075 // GPRMM16MoveP Bit set.
2076 const uint8_t GPRMM16MovePBits[] = {
2077 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2078 };
2079
2080 // GPRMM16Zero Register Class...
2081 const MCPhysReg GPRMM16Zero[] = {
2082 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2083 };
2084
2085 // GPRMM16Zero Bit set.
2086 const uint8_t GPRMM16ZeroBits[] = {
2087 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2088 };
2089
2090 // CPU16Regs_and_GPRMM16Zero Register Class...
2091 const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2092 Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2093 };
2094
2095 // CPU16Regs_and_GPRMM16Zero Bit set.
2096 const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2097 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2098 };
2099
2100 // GPR32NONZERO_and_GPRMM16MoveP Register Class...
2101 const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2102 Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2103 };
2104
2105 // GPR32NONZERO_and_GPRMM16MoveP Bit set.
2106 const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2108 };
2109
2110 // GPRMM16MovePPairSecond Register Class...
2111 const MCPhysReg GPRMM16MovePPairSecond[] = {
2112 Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,
2113 };
2114
2115 // GPRMM16MovePPairSecond Bit set.
2116 const uint8_t GPRMM16MovePPairSecondBits[] = {
2117 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2118 };
2119
2120 // CPU16Regs_and_GPRMM16MoveP Register Class...
2121 const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2122 Mips::S1, Mips::V0, Mips::V1, Mips::S0,
2123 };
2124
2125 // CPU16Regs_and_GPRMM16MoveP Bit set.
2126 const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2128 };
2129
2130 // GPRMM16MoveP_and_GPRMM16Zero Register Class...
2131 const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2132 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2133 };
2134
2135 // GPRMM16MoveP_and_GPRMM16Zero Bit set.
2136 const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2137 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2138 };
2139
2140 // HI32DSP Register Class...
2141 const MCPhysReg HI32DSP[] = {
2142 Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
2143 };
2144
2145 // HI32DSP Bit set.
2146 const uint8_t HI32DSPBits[] = {
2147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2148 };
2149
2150 // LO32DSP Register Class...
2151 const MCPhysReg LO32DSP[] = {
2152 Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
2153 };
2154
2155 // LO32DSP Bit set.
2156 const uint8_t LO32DSPBits[] = {
2157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2158 };
2159
2160 // CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2161 const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2162 Mips::A1, Mips::A2, Mips::A3,
2163 };
2164
2165 // CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2166 const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2167 0x00, 0x00, 0x80, 0x03,
2168 };
2169
2170 // GPRMM16MovePPairFirst Register Class...
2171 const MCPhysReg GPRMM16MovePPairFirst[] = {
2172 Mips::A0, Mips::A1, Mips::A2,
2173 };
2174
2175 // GPRMM16MovePPairFirst Bit set.
2176 const uint8_t GPRMM16MovePPairFirstBits[] = {
2177 0x00, 0x00, 0xc0, 0x01,
2178 };
2179
2180 // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2181 const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2182 Mips::S1, Mips::V0, Mips::V1,
2183 };
2184
2185 // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2186 const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2188 };
2189
2190 // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2191 const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2192 Mips::A1, Mips::A2,
2193 };
2194
2195 // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2196 const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2197 0x00, 0x00, 0x80, 0x01,
2198 };
2199
2200 // CPURAReg Register Class...
2201 const MCPhysReg CPURAReg[] = {
2202 Mips::RA,
2203 };
2204
2205 // CPURAReg Bit set.
2206 const uint8_t CPURARegBits[] = {
2207 0x00, 0x00, 0x08,
2208 };
2209
2210 // CPUSPReg Register Class...
2211 const MCPhysReg CPUSPReg[] = {
2212 Mips::SP,
2213 };
2214
2215 // CPUSPReg Bit set.
2216 const uint8_t CPUSPRegBits[] = {
2217 0x00, 0x00, 0x10,
2218 };
2219
2220 // DSPCC Register Class...
2221 const MCPhysReg DSPCC[] = {
2222 Mips::DSPCCond,
2223 };
2224
2225 // DSPCC Bit set.
2226 const uint8_t DSPCCBits[] = {
2227 0x04,
2228 };
2229
2230 // GP32 Register Class...
2231 const MCPhysReg GP32[] = {
2232 Mips::GP,
2233 };
2234
2235 // GP32 Bit set.
2236 const uint8_t GP32Bits[] = {
2237 0x00, 0x02,
2238 };
2239
2240 // GPR32ZERO Register Class...
2241 const MCPhysReg GPR32ZERO[] = {
2242 Mips::ZERO,
2243 };
2244
2245 // GPR32ZERO Bit set.
2246 const uint8_t GPR32ZEROBits[] = {
2247 0x00, 0x00, 0x20,
2248 };
2249
2250 // HI32 Register Class...
2251 const MCPhysReg HI32[] = {
2252 Mips::HI0,
2253 };
2254
2255 // HI32 Bit set.
2256 const uint8_t HI32Bits[] = {
2257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2258 };
2259
2260 // LO32 Register Class...
2261 const MCPhysReg LO32[] = {
2262 Mips::LO0,
2263 };
2264
2265 // LO32 Bit set.
2266 const uint8_t LO32Bits[] = {
2267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2268 };
2269
2270 // SP32 Register Class...
2271 const MCPhysReg SP32[] = {
2272 Mips::SP,
2273 };
2274
2275 // SP32 Bit set.
2276 const uint8_t SP32Bits[] = {
2277 0x00, 0x00, 0x10,
2278 };
2279
2280 // FGR64 Register Class...
2281 const MCPhysReg FGR64[] = {
2282 Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
2283 };
2284
2285 // FGR64 Bit set.
2286 const uint8_t FGR64Bits[] = {
2287 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2288 };
2289
2290 // GPR64 Register Class...
2291 const MCPhysReg GPR64[] = {
2292 Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2293 };
2294
2295 // GPR64 Bit set.
2296 const uint8_t GPR64Bits[] = {
2297 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2298 };
2299
2300 // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2301 const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2302 Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2303 };
2304
2305 // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2306 const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2307 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2308 };
2309
2310 // AFGR64 Register Class...
2311 const MCPhysReg AFGR64[] = {
2312 Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
2313 };
2314
2315 // AFGR64 Bit set.
2316 const uint8_t AFGR64Bits[] = {
2317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2318 };
2319
2320 // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2321 const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2322 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
2323 };
2324
2325 // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2326 const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2328 };
2329
2330 // GPR64_with_sub_32_in_CPU16Regs Register Class...
2331 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2332 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
2333 };
2334
2335 // GPR64_with_sub_32_in_CPU16Regs Bit set.
2336 const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2338 };
2339
2340 // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2341 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2342 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2343 };
2344
2345 // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2346 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2347 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2348 };
2349
2350 // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2351 const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2352 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2353 };
2354
2355 // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2356 const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2357 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2358 };
2359
2360 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2361 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2362 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2363 };
2364
2365 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2366 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2367 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2368 };
2369
2370 // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2371 const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2372 Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2373 };
2374
2375 // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2376 const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2378 };
2379
2380 // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
2381 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2382 Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,
2383 };
2384
2385 // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
2386 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
2387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2388 };
2389
2390 // ACC64DSP Register Class...
2391 const MCPhysReg ACC64DSP[] = {
2392 Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2393 };
2394
2395 // ACC64DSP Bit set.
2396 const uint8_t ACC64DSPBits[] = {
2397 0x00, 0x00, 0x00, 0x3c,
2398 };
2399
2400 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2401 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2402 Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
2403 };
2404
2405 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2406 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2407 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2408 };
2409
2410 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2411 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2412 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
2413 };
2414
2415 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2416 const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2417 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2418 };
2419
2420 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2421 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2422 Mips::A1_64, Mips::A2_64, Mips::A3_64,
2423 };
2424
2425 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2426 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2427 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2428 };
2429
2430 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
2431 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2432 Mips::A0_64, Mips::A1_64, Mips::A2_64,
2433 };
2434
2435 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
2436 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
2437 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2438 };
2439
2440 // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2441 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2442 Mips::V0_64, Mips::V1_64, Mips::S1_64,
2443 };
2444
2445 // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2446 const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2447 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2448 };
2449
2450 // OCTEON_MPL Register Class...
2451 const MCPhysReg OCTEON_MPL[] = {
2452 Mips::MPL0, Mips::MPL1, Mips::MPL2,
2453 };
2454
2455 // OCTEON_MPL Bit set.
2456 const uint8_t OCTEON_MPLBits[] = {
2457 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
2458 };
2459
2460 // OCTEON_P Register Class...
2461 const MCPhysReg OCTEON_P[] = {
2462 Mips::P0, Mips::P1, Mips::P2,
2463 };
2464
2465 // OCTEON_P Bit set.
2466 const uint8_t OCTEON_PBits[] = {
2467 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
2468 };
2469
2470 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2471 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2472 Mips::A1_64, Mips::A2_64,
2473 };
2474
2475 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2476 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2477 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2478 };
2479
2480 // ACC64 Register Class...
2481 const MCPhysReg ACC64[] = {
2482 Mips::AC0,
2483 };
2484
2485 // ACC64 Bit set.
2486 const uint8_t ACC64Bits[] = {
2487 0x00, 0x00, 0x00, 0x04,
2488 };
2489
2490 // GP64 Register Class...
2491 const MCPhysReg GP64[] = {
2492 Mips::GP_64,
2493 };
2494
2495 // GP64 Bit set.
2496 const uint8_t GP64Bits[] = {
2497 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2498 };
2499
2500 // GPR64_with_sub_32_in_CPURAReg Register Class...
2501 const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2502 Mips::RA_64,
2503 };
2504
2505 // GPR64_with_sub_32_in_CPURAReg Bit set.
2506 const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2507 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2508 };
2509
2510 // GPR64_with_sub_32_in_GPR32ZERO Register Class...
2511 const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2512 Mips::ZERO_64,
2513 };
2514
2515 // GPR64_with_sub_32_in_GPR32ZERO Bit set.
2516 const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2517 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2518 };
2519
2520 // HI64 Register Class...
2521 const MCPhysReg HI64[] = {
2522 Mips::HI0_64,
2523 };
2524
2525 // HI64 Bit set.
2526 const uint8_t HI64Bits[] = {
2527 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2528 };
2529
2530 // LO64 Register Class...
2531 const MCPhysReg LO64[] = {
2532 Mips::LO0_64,
2533 };
2534
2535 // LO64 Bit set.
2536 const uint8_t LO64Bits[] = {
2537 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2538 };
2539
2540 // SP64 Register Class...
2541 const MCPhysReg SP64[] = {
2542 Mips::SP_64,
2543 };
2544
2545 // SP64 Bit set.
2546 const uint8_t SP64Bits[] = {
2547 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2548 };
2549
2550 // MSA128B Register Class...
2551 const MCPhysReg MSA128B[] = {
2552 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2553 };
2554
2555 // MSA128B Bit set.
2556 const uint8_t MSA128BBits[] = {
2557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2558 };
2559
2560 // MSA128D Register Class...
2561 const MCPhysReg MSA128D[] = {
2562 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2563 };
2564
2565 // MSA128D Bit set.
2566 const uint8_t MSA128DBits[] = {
2567 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2568 };
2569
2570 // MSA128H Register Class...
2571 const MCPhysReg MSA128H[] = {
2572 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2573 };
2574
2575 // MSA128H Bit set.
2576 const uint8_t MSA128HBits[] = {
2577 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2578 };
2579
2580 // MSA128W Register Class...
2581 const MCPhysReg MSA128W[] = {
2582 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2583 };
2584
2585 // MSA128W Bit set.
2586 const uint8_t MSA128WBits[] = {
2587 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2588 };
2589
2590 // MSA128WEvens Register Class...
2591 const MCPhysReg MSA128WEvens[] = {
2592 Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
2593 };
2594
2595 // MSA128WEvens Bit set.
2596 const uint8_t MSA128WEvensBits[] = {
2597 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
2598 };
2599
2600 // ACC128 Register Class...
2601 const MCPhysReg ACC128[] = {
2602 Mips::AC0_64,
2603 };
2604
2605 // ACC128 Bit set.
2606 const uint8_t ACC128Bits[] = {
2607 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2608 };
2609
2610} // end anonymous namespace
2611
2612
2613#ifdef __GNUC__
2614#pragma GCC diagnostic push
2615#pragma GCC diagnostic ignored "-Woverlength-strings"
2616#endif
2617extern const char MipsRegClassStrings[] = {
2618 /* 0 */ "COP0\0"
2619 /* 5 */ "HI32\0"
2620 /* 10 */ "LO32\0"
2621 /* 15 */ "GP32\0"
2622 /* 20 */ "SP32\0"
2623 /* 25 */ "FGR32\0"
2624 /* 31 */ "GPR32\0"
2625 /* 37 */ "COP2\0"
2626 /* 42 */ "COP3\0"
2627 /* 47 */ "ACC64\0"
2628 /* 53 */ "HI64\0"
2629 /* 58 */ "LO64\0"
2630 /* 63 */ "GP64\0"
2631 /* 68 */ "SP64\0"
2632 /* 73 */ "AFGR64\0"
2633 /* 80 */ "GPR64\0"
2634 /* 86 */ "MSA128F16\0"
2635 /* 96 */ "GPRMM16\0"
2636 /* 104 */ "ACC128\0"
2637 /* 111 */ "MSA128B\0"
2638 /* 119 */ "FCC\0"
2639 /* 123 */ "DSPCC\0"
2640 /* 129 */ "FGRCC\0"
2641 /* 135 */ "MSA128D\0"
2642 /* 143 */ "MSA128H\0"
2643 /* 151 */ "OCTEON_MPL\0"
2644 /* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"
2645 /* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"
2646 /* 227 */ "HI32DSP\0"
2647 /* 235 */ "LO32DSP\0"
2648 /* 243 */ "ACC64DSP\0"
2649 /* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"
2650 /* 289 */ "OCTEON_P\0"
2651 /* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"
2652 /* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"
2653 /* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"
2654 /* 431 */ "CCR\0"
2655 /* 435 */ "DSPR\0"
2656 /* 440 */ "MSA128W\0"
2657 /* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"
2658 /* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"
2659 /* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"
2660 /* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"
2661 /* 650 */ "CPUSPReg\0"
2662 /* 659 */ "MSACtrl\0"
2663 /* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"
2664 /* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"
2665 /* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"
2666 /* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"
2667 /* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"
2668 /* 892 */ "HWRegs\0"
2669 /* 899 */ "MSA128WEvens\0"
2670 /* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"
2671};
2672#ifdef __GNUC__
2673#pragma GCC diagnostic pop
2674#endif
2675
2676extern const MCRegisterClass MipsMCRegisterClasses[] = {
2677 { MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true, false },
2678 { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false, false },
2679 { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false, false },
2680 { COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false, false },
2681 { COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false, false },
2682 { DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true, false },
2683 { FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true, false },
2684 { FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true, false },
2685 { GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true, false },
2686 { HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false, false },
2687 { MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false, false },
2688 { GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true, false },
2689 { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true, false },
2690 { CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true, false },
2691 { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false, false },
2692 { GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true, false },
2693 { GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true, false },
2694 { GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true, false },
2695 { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true, false },
2696 { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true, false },
2697 { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true, false },
2698 { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true, false },
2699 { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true, false },
2700 { HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true, false },
2701 { LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true, false },
2702 { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true, false },
2703 { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true, false },
2704 { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true, false },
2705 { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true, false },
2706 { CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false, false },
2707 { CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false, false },
2708 { DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true, false },
2709 { GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false, false },
2710 { GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true, false },
2711 { HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true, false },
2712 { LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true, false },
2713 { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false, false },
2714 { FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true, false },
2715 { GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true, false },
2716 { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true, false },
2717 { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true, false },
2718 { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true, false },
2719 { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true, false },
2720 { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true, false },
2721 { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true, false },
2722 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true, false },
2723 { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true, false },
2724 { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true, false },
2725 { ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true, false },
2726 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true, false },
2727 { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true, false },
2728 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true, false },
2729 { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true, false },
2730 { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true, false },
2731 { OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false, false },
2732 { OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false, false },
2733 { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true, false },
2734 { ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true, false },
2735 { GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false, false },
2736 { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true, false },
2737 { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true, false },
2738 { HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true, false },
2739 { LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true, false },
2740 { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false, false },
2741 { MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true, false },
2742 { MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true, false },
2743 { MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true, false },
2744 { MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true, false },
2745 { MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true, false },
2746 { ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true, false },
2747};
2748
2749// Mips Dwarf<->LLVM register mappings.
2750extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2751 { 0U, Mips::ZERO_64 },
2752 { 1U, Mips::AT_64 },
2753 { 2U, Mips::V0_64 },
2754 { 3U, Mips::V1_64 },
2755 { 4U, Mips::A0_64 },
2756 { 5U, Mips::A1_64 },
2757 { 6U, Mips::A2_64 },
2758 { 7U, Mips::A3_64 },
2759 { 8U, Mips::T0_64 },
2760 { 9U, Mips::T1_64 },
2761 { 10U, Mips::T2_64 },
2762 { 11U, Mips::T3_64 },
2763 { 12U, Mips::T4_64 },
2764 { 13U, Mips::T5_64 },
2765 { 14U, Mips::T6_64 },
2766 { 15U, Mips::T7_64 },
2767 { 16U, Mips::S0_64 },
2768 { 17U, Mips::S1_64 },
2769 { 18U, Mips::S2_64 },
2770 { 19U, Mips::S3_64 },
2771 { 20U, Mips::S4_64 },
2772 { 21U, Mips::S5_64 },
2773 { 22U, Mips::S6_64 },
2774 { 23U, Mips::S7_64 },
2775 { 24U, Mips::T8_64 },
2776 { 25U, Mips::T9_64 },
2777 { 26U, Mips::K0_64 },
2778 { 27U, Mips::K1_64 },
2779 { 28U, Mips::GP_64 },
2780 { 29U, Mips::SP_64 },
2781 { 30U, Mips::FP_64 },
2782 { 31U, Mips::RA_64 },
2783 { 32U, Mips::D0_64 },
2784 { 33U, Mips::D1_64 },
2785 { 34U, Mips::D2_64 },
2786 { 35U, Mips::D3_64 },
2787 { 36U, Mips::D4_64 },
2788 { 37U, Mips::D5_64 },
2789 { 38U, Mips::D6_64 },
2790 { 39U, Mips::D7_64 },
2791 { 40U, Mips::D8_64 },
2792 { 41U, Mips::D9_64 },
2793 { 42U, Mips::D10_64 },
2794 { 43U, Mips::D11_64 },
2795 { 44U, Mips::D12_64 },
2796 { 45U, Mips::D13_64 },
2797 { 46U, Mips::D14_64 },
2798 { 47U, Mips::D15_64 },
2799 { 48U, Mips::D16_64 },
2800 { 49U, Mips::D17_64 },
2801 { 50U, Mips::D18_64 },
2802 { 51U, Mips::D19_64 },
2803 { 52U, Mips::D20_64 },
2804 { 53U, Mips::D21_64 },
2805 { 54U, Mips::D22_64 },
2806 { 55U, Mips::D23_64 },
2807 { 56U, Mips::D24_64 },
2808 { 57U, Mips::D25_64 },
2809 { 58U, Mips::D26_64 },
2810 { 59U, Mips::D27_64 },
2811 { 60U, Mips::D28_64 },
2812 { 61U, Mips::D29_64 },
2813 { 62U, Mips::D30_64 },
2814 { 63U, Mips::D31_64 },
2815 { 64U, Mips::HI0 },
2816 { 65U, Mips::LO0 },
2817 { 176U, Mips::HI1 },
2818 { 177U, Mips::LO1 },
2819 { 178U, Mips::HI2 },
2820 { 179U, Mips::LO2 },
2821 { 180U, Mips::HI3 },
2822 { 181U, Mips::LO3 },
2823};
2824extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);
2825
2826extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2827 { 0U, Mips::ZERO_64 },
2828 { 1U, Mips::AT_64 },
2829 { 2U, Mips::V0_64 },
2830 { 3U, Mips::V1_64 },
2831 { 4U, Mips::A0_64 },
2832 { 5U, Mips::A1_64 },
2833 { 6U, Mips::A2_64 },
2834 { 7U, Mips::A3_64 },
2835 { 8U, Mips::T0_64 },
2836 { 9U, Mips::T1_64 },
2837 { 10U, Mips::T2_64 },
2838 { 11U, Mips::T3_64 },
2839 { 12U, Mips::T4_64 },
2840 { 13U, Mips::T5_64 },
2841 { 14U, Mips::T6_64 },
2842 { 15U, Mips::T7_64 },
2843 { 16U, Mips::S0_64 },
2844 { 17U, Mips::S1_64 },
2845 { 18U, Mips::S2_64 },
2846 { 19U, Mips::S3_64 },
2847 { 20U, Mips::S4_64 },
2848 { 21U, Mips::S5_64 },
2849 { 22U, Mips::S6_64 },
2850 { 23U, Mips::S7_64 },
2851 { 24U, Mips::T8_64 },
2852 { 25U, Mips::T9_64 },
2853 { 26U, Mips::K0_64 },
2854 { 27U, Mips::K1_64 },
2855 { 28U, Mips::GP_64 },
2856 { 29U, Mips::SP_64 },
2857 { 30U, Mips::FP_64 },
2858 { 31U, Mips::RA_64 },
2859 { 32U, Mips::D0_64 },
2860 { 33U, Mips::D1_64 },
2861 { 34U, Mips::D2_64 },
2862 { 35U, Mips::D3_64 },
2863 { 36U, Mips::D4_64 },
2864 { 37U, Mips::D5_64 },
2865 { 38U, Mips::D6_64 },
2866 { 39U, Mips::D7_64 },
2867 { 40U, Mips::D8_64 },
2868 { 41U, Mips::D9_64 },
2869 { 42U, Mips::D10_64 },
2870 { 43U, Mips::D11_64 },
2871 { 44U, Mips::D12_64 },
2872 { 45U, Mips::D13_64 },
2873 { 46U, Mips::D14_64 },
2874 { 47U, Mips::D15_64 },
2875 { 48U, Mips::D16_64 },
2876 { 49U, Mips::D17_64 },
2877 { 50U, Mips::D18_64 },
2878 { 51U, Mips::D19_64 },
2879 { 52U, Mips::D20_64 },
2880 { 53U, Mips::D21_64 },
2881 { 54U, Mips::D22_64 },
2882 { 55U, Mips::D23_64 },
2883 { 56U, Mips::D24_64 },
2884 { 57U, Mips::D25_64 },
2885 { 58U, Mips::D26_64 },
2886 { 59U, Mips::D27_64 },
2887 { 60U, Mips::D28_64 },
2888 { 61U, Mips::D29_64 },
2889 { 62U, Mips::D30_64 },
2890 { 63U, Mips::D31_64 },
2891 { 64U, Mips::HI0 },
2892 { 65U, Mips::LO0 },
2893 { 176U, Mips::HI1 },
2894 { 177U, Mips::LO1 },
2895 { 178U, Mips::HI2 },
2896 { 179U, Mips::LO2 },
2897 { 180U, Mips::HI3 },
2898 { 181U, Mips::LO3 },
2899};
2900extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);
2901
2902extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2903 { Mips::AT, 1U },
2904 { Mips::FP, 30U },
2905 { Mips::GP, 28U },
2906 { Mips::RA, 31U },
2907 { Mips::SP, 29U },
2908 { Mips::ZERO, 0U },
2909 { Mips::A0, 4U },
2910 { Mips::A1, 5U },
2911 { Mips::A2, 6U },
2912 { Mips::A3, 7U },
2913 { Mips::AT_64, 1U },
2914 { Mips::F0, 32U },
2915 { Mips::F1, 33U },
2916 { Mips::F2, 34U },
2917 { Mips::F3, 35U },
2918 { Mips::F4, 36U },
2919 { Mips::F5, 37U },
2920 { Mips::F6, 38U },
2921 { Mips::F7, 39U },
2922 { Mips::F8, 40U },
2923 { Mips::F9, 41U },
2924 { Mips::F10, 42U },
2925 { Mips::F11, 43U },
2926 { Mips::F12, 44U },
2927 { Mips::F13, 45U },
2928 { Mips::F14, 46U },
2929 { Mips::F15, 47U },
2930 { Mips::F16, 48U },
2931 { Mips::F17, 49U },
2932 { Mips::F18, 50U },
2933 { Mips::F19, 51U },
2934 { Mips::F20, 52U },
2935 { Mips::F21, 53U },
2936 { Mips::F22, 54U },
2937 { Mips::F23, 55U },
2938 { Mips::F24, 56U },
2939 { Mips::F25, 57U },
2940 { Mips::F26, 58U },
2941 { Mips::F27, 59U },
2942 { Mips::F28, 60U },
2943 { Mips::F29, 61U },
2944 { Mips::F30, 62U },
2945 { Mips::F31, 63U },
2946 { Mips::FP_64, 30U },
2947 { Mips::F_HI0, 32U },
2948 { Mips::F_HI1, 33U },
2949 { Mips::F_HI2, 34U },
2950 { Mips::F_HI3, 35U },
2951 { Mips::F_HI4, 36U },
2952 { Mips::F_HI5, 37U },
2953 { Mips::F_HI6, 38U },
2954 { Mips::F_HI7, 39U },
2955 { Mips::F_HI8, 40U },
2956 { Mips::F_HI9, 41U },
2957 { Mips::F_HI10, 42U },
2958 { Mips::F_HI11, 43U },
2959 { Mips::F_HI12, 44U },
2960 { Mips::F_HI13, 45U },
2961 { Mips::F_HI14, 46U },
2962 { Mips::F_HI15, 47U },
2963 { Mips::F_HI16, 48U },
2964 { Mips::F_HI17, 49U },
2965 { Mips::F_HI18, 50U },
2966 { Mips::F_HI19, 51U },
2967 { Mips::F_HI20, 52U },
2968 { Mips::F_HI21, 53U },
2969 { Mips::F_HI22, 54U },
2970 { Mips::F_HI23, 55U },
2971 { Mips::F_HI24, 56U },
2972 { Mips::F_HI25, 57U },
2973 { Mips::F_HI26, 58U },
2974 { Mips::F_HI27, 59U },
2975 { Mips::F_HI28, 60U },
2976 { Mips::F_HI29, 61U },
2977 { Mips::F_HI30, 62U },
2978 { Mips::F_HI31, 63U },
2979 { Mips::GP_64, 28U },
2980 { Mips::HI0, 64U },
2981 { Mips::HI1, 176U },
2982 { Mips::HI2, 178U },
2983 { Mips::HI3, 180U },
2984 { Mips::K0, 26U },
2985 { Mips::K1, 27U },
2986 { Mips::LO0, 65U },
2987 { Mips::LO1, 177U },
2988 { Mips::LO2, 179U },
2989 { Mips::LO3, 181U },
2990 { Mips::RA_64, 31U },
2991 { Mips::S0, 16U },
2992 { Mips::S1, 17U },
2993 { Mips::S2, 18U },
2994 { Mips::S3, 19U },
2995 { Mips::S4, 20U },
2996 { Mips::S5, 21U },
2997 { Mips::S6, 22U },
2998 { Mips::S7, 23U },
2999 { Mips::SP_64, 29U },
3000 { Mips::T0, 8U },
3001 { Mips::T1, 9U },
3002 { Mips::T2, 10U },
3003 { Mips::T3, 11U },
3004 { Mips::T4, 12U },
3005 { Mips::T5, 13U },
3006 { Mips::T6, 14U },
3007 { Mips::T7, 15U },
3008 { Mips::T8, 24U },
3009 { Mips::T9, 25U },
3010 { Mips::V0, 2U },
3011 { Mips::V1, 3U },
3012 { Mips::W0, 32U },
3013 { Mips::W1, 33U },
3014 { Mips::W2, 34U },
3015 { Mips::W3, 35U },
3016 { Mips::W4, 36U },
3017 { Mips::W5, 37U },
3018 { Mips::W6, 38U },
3019 { Mips::W7, 39U },
3020 { Mips::W8, 40U },
3021 { Mips::W9, 41U },
3022 { Mips::W10, 42U },
3023 { Mips::W11, 43U },
3024 { Mips::W12, 44U },
3025 { Mips::W13, 45U },
3026 { Mips::W14, 46U },
3027 { Mips::W15, 47U },
3028 { Mips::W16, 48U },
3029 { Mips::W17, 49U },
3030 { Mips::W18, 50U },
3031 { Mips::W19, 51U },
3032 { Mips::W20, 52U },
3033 { Mips::W21, 53U },
3034 { Mips::W22, 54U },
3035 { Mips::W23, 55U },
3036 { Mips::W24, 56U },
3037 { Mips::W25, 57U },
3038 { Mips::W26, 58U },
3039 { Mips::W27, 59U },
3040 { Mips::W28, 60U },
3041 { Mips::W29, 61U },
3042 { Mips::W30, 62U },
3043 { Mips::W31, 63U },
3044 { Mips::ZERO_64, 0U },
3045 { Mips::A0_64, 4U },
3046 { Mips::A1_64, 5U },
3047 { Mips::A2_64, 6U },
3048 { Mips::A3_64, 7U },
3049 { Mips::D0_64, 32U },
3050 { Mips::D1_64, 33U },
3051 { Mips::D2_64, 34U },
3052 { Mips::D3_64, 35U },
3053 { Mips::D4_64, 36U },
3054 { Mips::D5_64, 37U },
3055 { Mips::D6_64, 38U },
3056 { Mips::D7_64, 39U },
3057 { Mips::D8_64, 40U },
3058 { Mips::D9_64, 41U },
3059 { Mips::D10_64, 42U },
3060 { Mips::D11_64, 43U },
3061 { Mips::D12_64, 44U },
3062 { Mips::D13_64, 45U },
3063 { Mips::D14_64, 46U },
3064 { Mips::D15_64, 47U },
3065 { Mips::D16_64, 48U },
3066 { Mips::D17_64, 49U },
3067 { Mips::D18_64, 50U },
3068 { Mips::D19_64, 51U },
3069 { Mips::D20_64, 52U },
3070 { Mips::D21_64, 53U },
3071 { Mips::D22_64, 54U },
3072 { Mips::D23_64, 55U },
3073 { Mips::D24_64, 56U },
3074 { Mips::D25_64, 57U },
3075 { Mips::D26_64, 58U },
3076 { Mips::D27_64, 59U },
3077 { Mips::D28_64, 60U },
3078 { Mips::D29_64, 61U },
3079 { Mips::D30_64, 62U },
3080 { Mips::D31_64, 63U },
3081 { Mips::K0_64, 26U },
3082 { Mips::K1_64, 27U },
3083 { Mips::S0_64, 16U },
3084 { Mips::S1_64, 17U },
3085 { Mips::S2_64, 18U },
3086 { Mips::S3_64, 19U },
3087 { Mips::S4_64, 20U },
3088 { Mips::S5_64, 21U },
3089 { Mips::S6_64, 22U },
3090 { Mips::S7_64, 23U },
3091 { Mips::T0_64, 8U },
3092 { Mips::T1_64, 9U },
3093 { Mips::T2_64, 10U },
3094 { Mips::T3_64, 11U },
3095 { Mips::T4_64, 12U },
3096 { Mips::T5_64, 13U },
3097 { Mips::T6_64, 14U },
3098 { Mips::T7_64, 15U },
3099 { Mips::T8_64, 24U },
3100 { Mips::T9_64, 25U },
3101 { Mips::V0_64, 2U },
3102 { Mips::V1_64, 3U },
3103};
3104extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);
3105
3106extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3107 { Mips::AT, 1U },
3108 { Mips::FP, 30U },
3109 { Mips::GP, 28U },
3110 { Mips::RA, 31U },
3111 { Mips::SP, 29U },
3112 { Mips::ZERO, 0U },
3113 { Mips::A0, 4U },
3114 { Mips::A1, 5U },
3115 { Mips::A2, 6U },
3116 { Mips::A3, 7U },
3117 { Mips::AT_64, 1U },
3118 { Mips::F0, 32U },
3119 { Mips::F1, 33U },
3120 { Mips::F2, 34U },
3121 { Mips::F3, 35U },
3122 { Mips::F4, 36U },
3123 { Mips::F5, 37U },
3124 { Mips::F6, 38U },
3125 { Mips::F7, 39U },
3126 { Mips::F8, 40U },
3127 { Mips::F9, 41U },
3128 { Mips::F10, 42U },
3129 { Mips::F11, 43U },
3130 { Mips::F12, 44U },
3131 { Mips::F13, 45U },
3132 { Mips::F14, 46U },
3133 { Mips::F15, 47U },
3134 { Mips::F16, 48U },
3135 { Mips::F17, 49U },
3136 { Mips::F18, 50U },
3137 { Mips::F19, 51U },
3138 { Mips::F20, 52U },
3139 { Mips::F21, 53U },
3140 { Mips::F22, 54U },
3141 { Mips::F23, 55U },
3142 { Mips::F24, 56U },
3143 { Mips::F25, 57U },
3144 { Mips::F26, 58U },
3145 { Mips::F27, 59U },
3146 { Mips::F28, 60U },
3147 { Mips::F29, 61U },
3148 { Mips::F30, 62U },
3149 { Mips::F31, 63U },
3150 { Mips::FP_64, 30U },
3151 { Mips::F_HI0, 32U },
3152 { Mips::F_HI1, 33U },
3153 { Mips::F_HI2, 34U },
3154 { Mips::F_HI3, 35U },
3155 { Mips::F_HI4, 36U },
3156 { Mips::F_HI5, 37U },
3157 { Mips::F_HI6, 38U },
3158 { Mips::F_HI7, 39U },
3159 { Mips::F_HI8, 40U },
3160 { Mips::F_HI9, 41U },
3161 { Mips::F_HI10, 42U },
3162 { Mips::F_HI11, 43U },
3163 { Mips::F_HI12, 44U },
3164 { Mips::F_HI13, 45U },
3165 { Mips::F_HI14, 46U },
3166 { Mips::F_HI15, 47U },
3167 { Mips::F_HI16, 48U },
3168 { Mips::F_HI17, 49U },
3169 { Mips::F_HI18, 50U },
3170 { Mips::F_HI19, 51U },
3171 { Mips::F_HI20, 52U },
3172 { Mips::F_HI21, 53U },
3173 { Mips::F_HI22, 54U },
3174 { Mips::F_HI23, 55U },
3175 { Mips::F_HI24, 56U },
3176 { Mips::F_HI25, 57U },
3177 { Mips::F_HI26, 58U },
3178 { Mips::F_HI27, 59U },
3179 { Mips::F_HI28, 60U },
3180 { Mips::F_HI29, 61U },
3181 { Mips::F_HI30, 62U },
3182 { Mips::F_HI31, 63U },
3183 { Mips::GP_64, 28U },
3184 { Mips::HI0, 64U },
3185 { Mips::HI1, 176U },
3186 { Mips::HI2, 178U },
3187 { Mips::HI3, 180U },
3188 { Mips::K0, 26U },
3189 { Mips::K1, 27U },
3190 { Mips::LO0, 65U },
3191 { Mips::LO1, 177U },
3192 { Mips::LO2, 179U },
3193 { Mips::LO3, 181U },
3194 { Mips::RA_64, 31U },
3195 { Mips::S0, 16U },
3196 { Mips::S1, 17U },
3197 { Mips::S2, 18U },
3198 { Mips::S3, 19U },
3199 { Mips::S4, 20U },
3200 { Mips::S5, 21U },
3201 { Mips::S6, 22U },
3202 { Mips::S7, 23U },
3203 { Mips::SP_64, 29U },
3204 { Mips::T0, 8U },
3205 { Mips::T1, 9U },
3206 { Mips::T2, 10U },
3207 { Mips::T3, 11U },
3208 { Mips::T4, 12U },
3209 { Mips::T5, 13U },
3210 { Mips::T6, 14U },
3211 { Mips::T7, 15U },
3212 { Mips::T8, 24U },
3213 { Mips::T9, 25U },
3214 { Mips::V0, 2U },
3215 { Mips::V1, 3U },
3216 { Mips::W0, 32U },
3217 { Mips::W1, 33U },
3218 { Mips::W2, 34U },
3219 { Mips::W3, 35U },
3220 { Mips::W4, 36U },
3221 { Mips::W5, 37U },
3222 { Mips::W6, 38U },
3223 { Mips::W7, 39U },
3224 { Mips::W8, 40U },
3225 { Mips::W9, 41U },
3226 { Mips::W10, 42U },
3227 { Mips::W11, 43U },
3228 { Mips::W12, 44U },
3229 { Mips::W13, 45U },
3230 { Mips::W14, 46U },
3231 { Mips::W15, 47U },
3232 { Mips::W16, 48U },
3233 { Mips::W17, 49U },
3234 { Mips::W18, 50U },
3235 { Mips::W19, 51U },
3236 { Mips::W20, 52U },
3237 { Mips::W21, 53U },
3238 { Mips::W22, 54U },
3239 { Mips::W23, 55U },
3240 { Mips::W24, 56U },
3241 { Mips::W25, 57U },
3242 { Mips::W26, 58U },
3243 { Mips::W27, 59U },
3244 { Mips::W28, 60U },
3245 { Mips::W29, 61U },
3246 { Mips::W30, 62U },
3247 { Mips::W31, 63U },
3248 { Mips::ZERO_64, 0U },
3249 { Mips::A0_64, 4U },
3250 { Mips::A1_64, 5U },
3251 { Mips::A2_64, 6U },
3252 { Mips::A3_64, 7U },
3253 { Mips::D0_64, 32U },
3254 { Mips::D1_64, 33U },
3255 { Mips::D2_64, 34U },
3256 { Mips::D3_64, 35U },
3257 { Mips::D4_64, 36U },
3258 { Mips::D5_64, 37U },
3259 { Mips::D6_64, 38U },
3260 { Mips::D7_64, 39U },
3261 { Mips::D8_64, 40U },
3262 { Mips::D9_64, 41U },
3263 { Mips::D10_64, 42U },
3264 { Mips::D11_64, 43U },
3265 { Mips::D12_64, 44U },
3266 { Mips::D13_64, 45U },
3267 { Mips::D14_64, 46U },
3268 { Mips::D15_64, 47U },
3269 { Mips::D16_64, 48U },
3270 { Mips::D17_64, 49U },
3271 { Mips::D18_64, 50U },
3272 { Mips::D19_64, 51U },
3273 { Mips::D20_64, 52U },
3274 { Mips::D21_64, 53U },
3275 { Mips::D22_64, 54U },
3276 { Mips::D23_64, 55U },
3277 { Mips::D24_64, 56U },
3278 { Mips::D25_64, 57U },
3279 { Mips::D26_64, 58U },
3280 { Mips::D27_64, 59U },
3281 { Mips::D28_64, 60U },
3282 { Mips::D29_64, 61U },
3283 { Mips::D30_64, 62U },
3284 { Mips::D31_64, 63U },
3285 { Mips::K0_64, 26U },
3286 { Mips::K1_64, 27U },
3287 { Mips::S0_64, 16U },
3288 { Mips::S1_64, 17U },
3289 { Mips::S2_64, 18U },
3290 { Mips::S3_64, 19U },
3291 { Mips::S4_64, 20U },
3292 { Mips::S5_64, 21U },
3293 { Mips::S6_64, 22U },
3294 { Mips::S7_64, 23U },
3295 { Mips::T0_64, 8U },
3296 { Mips::T1_64, 9U },
3297 { Mips::T2_64, 10U },
3298 { Mips::T3_64, 11U },
3299 { Mips::T4_64, 12U },
3300 { Mips::T5_64, 13U },
3301 { Mips::T6_64, 14U },
3302 { Mips::T7_64, 15U },
3303 { Mips::T8_64, 24U },
3304 { Mips::T9_64, 25U },
3305 { Mips::V0_64, 2U },
3306 { Mips::V1_64, 3U },
3307};
3308extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);
3309
3310extern const uint16_t MipsRegEncodingTable[] = {
3311 0,
3312 1,
3313 0,
3314 0,
3315 0,
3316 0,
3317 0,
3318 0,
3319 30,
3320 28,
3321 2,
3322 1,
3323 0,
3324 6,
3325 4,
3326 5,
3327 3,
3328 7,
3329 0,
3330 31,
3331 29,
3332 0,
3333 4,
3334 5,
3335 6,
3336 7,
3337 0,
3338 1,
3339 2,
3340 3,
3341 1,
3342 0,
3343 1,
3344 2,
3345 3,
3346 4,
3347 5,
3348 6,
3349 7,
3350 8,
3351 9,
3352 0,
3353 1,
3354 2,
3355 3,
3356 4,
3357 5,
3358 6,
3359 7,
3360 8,
3361 9,
3362 0,
3363 1,
3364 2,
3365 3,
3366 4,
3367 5,
3368 6,
3369 7,
3370 8,
3371 9,
3372 10,
3373 11,
3374 12,
3375 13,
3376 14,
3377 15,
3378 16,
3379 17,
3380 18,
3381 19,
3382 20,
3383 21,
3384 22,
3385 23,
3386 24,
3387 25,
3388 26,
3389 27,
3390 28,
3391 29,
3392 30,
3393 31,
3394 10,
3395 11,
3396 12,
3397 13,
3398 14,
3399 15,
3400 16,
3401 17,
3402 18,
3403 19,
3404 20,
3405 21,
3406 22,
3407 23,
3408 24,
3409 25,
3410 26,
3411 27,
3412 28,
3413 29,
3414 30,
3415 31,
3416 10,
3417 11,
3418 12,
3419 13,
3420 14,
3421 15,
3422 16,
3423 17,
3424 18,
3425 19,
3426 20,
3427 21,
3428 22,
3429 23,
3430 24,
3431 25,
3432 26,
3433 27,
3434 28,
3435 29,
3436 30,
3437 31,
3438 0,
3439 2,
3440 4,
3441 6,
3442 8,
3443 10,
3444 12,
3445 14,
3446 16,
3447 18,
3448 20,
3449 22,
3450 24,
3451 26,
3452 28,
3453 30,
3454 0,
3455 0,
3456 0,
3457 0,
3458 0,
3459 1,
3460 2,
3461 3,
3462 4,
3463 5,
3464 6,
3465 7,
3466 8,
3467 9,
3468 10,
3469 11,
3470 12,
3471 13,
3472 14,
3473 15,
3474 16,
3475 17,
3476 18,
3477 19,
3478 20,
3479 21,
3480 22,
3481 23,
3482 24,
3483 25,
3484 26,
3485 27,
3486 28,
3487 29,
3488 30,
3489 31,
3490 0,
3491 1,
3492 2,
3493 3,
3494 4,
3495 5,
3496 6,
3497 7,
3498 0,
3499 1,
3500 2,
3501 3,
3502 4,
3503 5,
3504 6,
3505 7,
3506 8,
3507 9,
3508 10,
3509 11,
3510 12,
3511 13,
3512 14,
3513 15,
3514 16,
3515 17,
3516 18,
3517 19,
3518 20,
3519 21,
3520 22,
3521 23,
3522 24,
3523 25,
3524 26,
3525 27,
3526 28,
3527 29,
3528 30,
3529 31,
3530 30,
3531 0,
3532 1,
3533 2,
3534 3,
3535 4,
3536 5,
3537 6,
3538 7,
3539 8,
3540 9,
3541 10,
3542 11,
3543 12,
3544 13,
3545 14,
3546 15,
3547 16,
3548 17,
3549 18,
3550 19,
3551 20,
3552 21,
3553 22,
3554 23,
3555 24,
3556 25,
3557 26,
3558 27,
3559 28,
3560 29,
3561 30,
3562 31,
3563 28,
3564 0,
3565 1,
3566 2,
3567 3,
3568 0,
3569 1,
3570 2,
3571 3,
3572 4,
3573 5,
3574 6,
3575 7,
3576 8,
3577 9,
3578 10,
3579 11,
3580 12,
3581 13,
3582 14,
3583 15,
3584 16,
3585 17,
3586 18,
3587 19,
3588 20,
3589 21,
3590 22,
3591 23,
3592 24,
3593 25,
3594 26,
3595 27,
3596 28,
3597 29,
3598 30,
3599 31,
3600 26,
3601 27,
3602 0,
3603 1,
3604 2,
3605 3,
3606 0,
3607 1,
3608 2,
3609 8,
3610 9,
3611 10,
3612 11,
3613 12,
3614 13,
3615 14,
3616 15,
3617 16,
3618 17,
3619 18,
3620 19,
3621 20,
3622 21,
3623 22,
3624 23,
3625 24,
3626 25,
3627 26,
3628 27,
3629 28,
3630 29,
3631 30,
3632 31,
3633 0,
3634 1,
3635 2,
3636 31,
3637 16,
3638 17,
3639 18,
3640 19,
3641 20,
3642 21,
3643 22,
3644 23,
3645 29,
3646 8,
3647 9,
3648 10,
3649 11,
3650 12,
3651 13,
3652 14,
3653 15,
3654 24,
3655 25,
3656 2,
3657 3,
3658 0,
3659 1,
3660 2,
3661 3,
3662 4,
3663 5,
3664 6,
3665 7,
3666 8,
3667 9,
3668 10,
3669 11,
3670 12,
3671 13,
3672 14,
3673 15,
3674 16,
3675 17,
3676 18,
3677 19,
3678 20,
3679 21,
3680 22,
3681 23,
3682 24,
3683 25,
3684 26,
3685 27,
3686 28,
3687 29,
3688 30,
3689 31,
3690 0,
3691 4,
3692 5,
3693 6,
3694 7,
3695 0,
3696 0,
3697 1,
3698 2,
3699 3,
3700 4,
3701 5,
3702 6,
3703 7,
3704 8,
3705 9,
3706 10,
3707 11,
3708 12,
3709 13,
3710 14,
3711 15,
3712 16,
3713 17,
3714 18,
3715 19,
3716 20,
3717 21,
3718 22,
3719 23,
3720 24,
3721 25,
3722 26,
3723 27,
3724 28,
3725 29,
3726 30,
3727 31,
3728 0,
3729 0,
3730 26,
3731 27,
3732 0,
3733 16,
3734 17,
3735 18,
3736 19,
3737 20,
3738 21,
3739 22,
3740 23,
3741 8,
3742 9,
3743 10,
3744 11,
3745 12,
3746 13,
3747 14,
3748 15,
3749 24,
3750 25,
3751 2,
3752 3,
3753};
3754static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3755 RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3756MipsRegEncodingTable);
3757
3758 switch (DwarfFlavour) {
3759 default:
3760 llvm_unreachable("Unknown DWARF flavour");
3761 case 0:
3762 RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3763 break;
3764 }
3765 switch (EHFlavour) {
3766 default:
3767 llvm_unreachable("Unknown DWARF flavour");
3768 case 0:
3769 RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3770 break;
3771 }
3772 switch (DwarfFlavour) {
3773 default:
3774 llvm_unreachable("Unknown DWARF flavour");
3775 case 0:
3776 RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3777 break;
3778 }
3779 switch (EHFlavour) {
3780 default:
3781 llvm_unreachable("Unknown DWARF flavour");
3782 case 0:
3783 RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3784 break;
3785 }
3786}
3787
3788} // end namespace llvm
3789
3790#endif // GET_REGINFO_MC_DESC
3791
3792/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3793|* *|
3794|* Register Information Header Fragment *|
3795|* *|
3796|* Automatically generated file, do not edit! *|
3797|* *|
3798\*===----------------------------------------------------------------------===*/
3799
3800
3801#ifdef GET_REGINFO_HEADER
3802#undef GET_REGINFO_HEADER
3803
3804#include "llvm/CodeGen/TargetRegisterInfo.h"
3805
3806namespace llvm {
3807
3808class MipsFrameLowering;
3809
3810struct MipsGenRegisterInfo : public TargetRegisterInfo {
3811 explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3812 unsigned PC = 0, unsigned HwMode = 0);
3813 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3814 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3815 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3816 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
3817 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
3818 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3819 unsigned getRegUnitWeight(unsigned RegUnit) const override;
3820 unsigned getNumRegPressureSets() const override;
3821 const char *getRegPressureSetName(unsigned Idx) const override;
3822 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3823 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3824 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3825 ArrayRef<const char *> getRegMaskNames() const override;
3826 ArrayRef<const uint32_t *> getRegMasks() const override;
3827 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
3828 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
3829 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
3830 bool isConstantPhysReg(MCRegister PhysReg) const override final;
3831 /// Devirtualized TargetFrameLowering.
3832 static const MipsFrameLowering *getFrameLowering(
3833 const MachineFunction &MF);
3834};
3835
3836namespace Mips { // Register classes
3837 extern const TargetRegisterClass MSA128F16RegClass;
3838 extern const TargetRegisterClass CCRRegClass;
3839 extern const TargetRegisterClass COP0RegClass;
3840 extern const TargetRegisterClass COP2RegClass;
3841 extern const TargetRegisterClass COP3RegClass;
3842 extern const TargetRegisterClass DSPRRegClass;
3843 extern const TargetRegisterClass FGR32RegClass;
3844 extern const TargetRegisterClass FGRCCRegClass;
3845 extern const TargetRegisterClass GPR32RegClass;
3846 extern const TargetRegisterClass HWRegsRegClass;
3847 extern const TargetRegisterClass MSACtrlRegClass;
3848 extern const TargetRegisterClass GPR32NONZERORegClass;
3849 extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3850 extern const TargetRegisterClass CPU16RegsRegClass;
3851 extern const TargetRegisterClass FCCRegClass;
3852 extern const TargetRegisterClass GPRMM16RegClass;
3853 extern const TargetRegisterClass GPRMM16MovePRegClass;
3854 extern const TargetRegisterClass GPRMM16ZeroRegClass;
3855 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3856 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3857 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3858 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3859 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3860 extern const TargetRegisterClass HI32DSPRegClass;
3861 extern const TargetRegisterClass LO32DSPRegClass;
3862 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3863 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3864 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3865 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3866 extern const TargetRegisterClass CPURARegRegClass;
3867 extern const TargetRegisterClass CPUSPRegRegClass;
3868 extern const TargetRegisterClass DSPCCRegClass;
3869 extern const TargetRegisterClass GP32RegClass;
3870 extern const TargetRegisterClass GPR32ZERORegClass;
3871 extern const TargetRegisterClass HI32RegClass;
3872 extern const TargetRegisterClass LO32RegClass;
3873 extern const TargetRegisterClass SP32RegClass;
3874 extern const TargetRegisterClass FGR64RegClass;
3875 extern const TargetRegisterClass GPR64RegClass;
3876 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3877 extern const TargetRegisterClass AFGR64RegClass;
3878 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3879 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3880 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3881 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3882 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3883 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3884 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3885 extern const TargetRegisterClass ACC64DSPRegClass;
3886 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3887 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3888 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3889 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3890 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3891 extern const TargetRegisterClass OCTEON_MPLRegClass;
3892 extern const TargetRegisterClass OCTEON_PRegClass;
3893 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3894 extern const TargetRegisterClass ACC64RegClass;
3895 extern const TargetRegisterClass GP64RegClass;
3896 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3897 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3898 extern const TargetRegisterClass HI64RegClass;
3899 extern const TargetRegisterClass LO64RegClass;
3900 extern const TargetRegisterClass SP64RegClass;
3901 extern const TargetRegisterClass MSA128BRegClass;
3902 extern const TargetRegisterClass MSA128DRegClass;
3903 extern const TargetRegisterClass MSA128HRegClass;
3904 extern const TargetRegisterClass MSA128WRegClass;
3905 extern const TargetRegisterClass MSA128WEvensRegClass;
3906 extern const TargetRegisterClass ACC128RegClass;
3907} // end namespace Mips
3908
3909} // end namespace llvm
3910
3911#endif // GET_REGINFO_HEADER
3912
3913/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3914|* *|
3915|* Target Register and Register Classes Information *|
3916|* *|
3917|* Automatically generated file, do not edit! *|
3918|* *|
3919\*===----------------------------------------------------------------------===*/
3920
3921
3922#ifdef GET_REGINFO_TARGET_DESC
3923#undef GET_REGINFO_TARGET_DESC
3924
3925namespace llvm {
3926
3927extern const MCRegisterClass MipsMCRegisterClasses[];
3928
3929static const MVT::SimpleValueType VTLists[] = {
3930 /* 0 */ MVT::i32, MVT::Other,
3931 /* 2 */ MVT::i64, MVT::Other,
3932 /* 4 */ MVT::f16, MVT::Other,
3933 /* 6 */ MVT::f32, MVT::Other,
3934 /* 8 */ MVT::f64, MVT::Other,
3935 /* 10 */ MVT::v16i8, MVT::Other,
3936 /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3937 /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3938 /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3939 /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3940 /* 24 */ MVT::Untyped, MVT::Other,
3941};
3942
3943static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3944
3945static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
3946 { 65535, 65535 },
3947 { 0, 32 }, // sub_32
3948 { 0, 64 }, // sub_64
3949 { 16, 4 }, // sub_dsp16_19
3950 { 20, 1 }, // sub_dsp20
3951 { 21, 1 }, // sub_dsp21
3952 { 22, 1 }, // sub_dsp22
3953 { 23, 1 }, // sub_dsp23
3954 { 32, 32 }, // sub_hi
3955 { 0, 32 }, // sub_lo
3956 { 32, 32 }, // sub_hi_then_sub_32
3957 { 0, 64 }, // sub_32_sub_hi_then_sub_32
3958};
3959
3960
3961static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3962 LaneBitmask::getAll(),
3963 LaneBitmask(0x0000000000000001), // sub_32
3964 LaneBitmask(0x0000000000000041), // sub_64
3965 LaneBitmask(0x0000000000000002), // sub_dsp16_19
3966 LaneBitmask(0x0000000000000004), // sub_dsp20
3967 LaneBitmask(0x0000000000000008), // sub_dsp21
3968 LaneBitmask(0x0000000000000010), // sub_dsp22
3969 LaneBitmask(0x0000000000000020), // sub_dsp23
3970 LaneBitmask(0x0000000000000040), // sub_hi
3971 LaneBitmask(0x0000000000000001), // sub_lo
3972 LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
3973 LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
3974 };
3975
3976
3977
3978static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3979 // Mode = 0 (Default)
3980 { 16, 16, 128, /*VTLists+*/4 }, // MSA128F16
3981 { 32, 32, 32, /*VTLists+*/0 }, // CCR
3982 { 32, 32, 32, /*VTLists+*/0 }, // COP0
3983 { 32, 32, 32, /*VTLists+*/0 }, // COP2
3984 { 32, 32, 32, /*VTLists+*/0 }, // COP3
3985 { 32, 32, 32, /*VTLists+*/12 }, // DSPR
3986 { 32, 32, 32, /*VTLists+*/6 }, // FGR32
3987 { 32, 32, 32, /*VTLists+*/0 }, // FGRCC
3988 { 32, 32, 32, /*VTLists+*/0 }, // GPR32
3989 { 32, 32, 32, /*VTLists+*/0 }, // HWRegs
3990 { 32, 32, 32, /*VTLists+*/0 }, // MSACtrl
3991 { 32, 32, 32, /*VTLists+*/0 }, // GPR32NONZERO
3992 { 32, 32, 32, /*VTLists+*/0 }, // CPU16RegsPlusSP
3993 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs
3994 { 32, 32, 32, /*VTLists+*/0 }, // FCC
3995 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16
3996 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MoveP
3997 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16Zero
3998 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs_and_GPRMM16Zero
3999 { 32, 32, 32, /*VTLists+*/0 }, // GPR32NONZERO_and_GPRMM16MoveP
4000 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MovePPairSecond
4001 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs_and_GPRMM16MoveP
4002 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MoveP_and_GPRMM16Zero
4003 { 32, 32, 32, /*VTLists+*/0 }, // HI32DSP
4004 { 32, 32, 32, /*VTLists+*/0 }, // LO32DSP
4005 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs_and_GPRMM16MovePPairSecond
4006 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MovePPairFirst
4007 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4008 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4009 { 32, 32, 32, /*VTLists+*/0 }, // CPURAReg
4010 { 32, 32, 32, /*VTLists+*/0 }, // CPUSPReg
4011 { 32, 32, 32, /*VTLists+*/12 }, // DSPCC
4012 { 32, 32, 32, /*VTLists+*/0 }, // GP32
4013 { 32, 32, 32, /*VTLists+*/0 }, // GPR32ZERO
4014 { 32, 32, 32, /*VTLists+*/0 }, // HI32
4015 { 32, 32, 32, /*VTLists+*/0 }, // LO32
4016 { 32, 32, 32, /*VTLists+*/0 }, // SP32
4017 { 64, 64, 64, /*VTLists+*/8 }, // FGR64
4018 { 64, 64, 64, /*VTLists+*/2 }, // GPR64
4019 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPR32NONZERO
4020 { 64, 64, 64, /*VTLists+*/8 }, // AFGR64
4021 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
4022 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs
4023 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MoveP
4024 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16Zero
4025 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4026 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4027 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4028 { 64, 64, 64, /*VTLists+*/24 }, // ACC64DSP
4029 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4030 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4031 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4032 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4033 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4034 { 64, 64, 64, /*VTLists+*/2 }, // OCTEON_MPL
4035 { 64, 64, 64, /*VTLists+*/2 }, // OCTEON_P
4036 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4037 { 64, 64, 64, /*VTLists+*/24 }, // ACC64
4038 { 64, 64, 64, /*VTLists+*/2 }, // GP64
4039 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPURAReg
4040 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPR32ZERO
4041 { 64, 64, 64, /*VTLists+*/2 }, // HI64
4042 { 64, 64, 64, /*VTLists+*/2 }, // LO64
4043 { 64, 64, 64, /*VTLists+*/2 }, // SP64
4044 { 128, 128, 128, /*VTLists+*/10 }, // MSA128B
4045 { 128, 128, 128, /*VTLists+*/21 }, // MSA128D
4046 { 128, 128, 128, /*VTLists+*/15 }, // MSA128H
4047 { 128, 128, 128, /*VTLists+*/18 }, // MSA128W
4048 { 128, 128, 128, /*VTLists+*/18 }, // MSA128WEvens
4049 { 128, 128, 128, /*VTLists+*/24 }, // ACC128
4050};
4051
4052static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4053
4054static const uint32_t MSA128F16SubClassMask[] = {
4055 0x00000001, 0x00000000, 0x0000001f,
4056};
4057
4058static const uint32_t CCRSubClassMask[] = {
4059 0x00000002, 0x00000000, 0x00000000,
4060};
4061
4062static const uint32_t COP0SubClassMask[] = {
4063 0x00000004, 0x00000000, 0x00000000,
4064};
4065
4066static const uint32_t COP2SubClassMask[] = {
4067 0x00000008, 0x00000000, 0x00000000,
4068};
4069
4070static const uint32_t COP3SubClassMask[] = {
4071 0x00000010, 0x00000000, 0x00000000,
4072};
4073
4074static const uint32_t DSPRSubClassMask[] = {
4075 0x7e7fb920, 0x00000013, 0x00000000,
4076 0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4077};
4078
4079static const uint32_t FGR32SubClassMask[] = {
4080 0x000000c0, 0x00000000, 0x00000000,
4081 0x00000000, 0x00000100, 0x00000000, // sub_hi
4082 0x00000001, 0x00000120, 0x0000001f, // sub_lo
4083};
4084
4085static const uint32_t FGRCCSubClassMask[] = {
4086 0x000000c0, 0x00000000, 0x00000000,
4087 0x00000000, 0x00000100, 0x00000000, // sub_hi
4088 0x00000001, 0x00000120, 0x0000001f, // sub_lo
4089};
4090
4091static const uint32_t GPR32SubClassMask[] = {
4092 0x7e7fb900, 0x00000013, 0x00000000,
4093 0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4094};
4095
4096static const uint32_t HWRegsSubClassMask[] = {
4097 0x00000200, 0x00000000, 0x00000000,
4098};
4099
4100static const uint32_t MSACtrlSubClassMask[] = {
4101 0x00000400, 0x00000000, 0x00000000,
4102};
4103
4104static const uint32_t GPR32NONZEROSubClassMask[] = {
4105 0x7e3cb800, 0x00000011, 0x00000000,
4106 0x00000000, 0x8d3ae680, 0x00000000, // sub_32
4107};
4108
4109static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4110 0x5e24b000, 0x00000010, 0x00000000,
4111 0x00000000, 0x813a2600, 0x00000000, // sub_32
4112};
4113
4114static const uint32_t CPU16RegsSubClassMask[] = {
4115 0x1e24a000, 0x00000000, 0x00000000,
4116 0x00000000, 0x013a2400, 0x00000000, // sub_32
4117};
4118
4119static const uint32_t FCCSubClassMask[] = {
4120 0x00004000, 0x00000000, 0x00000000,
4121};
4122
4123static const uint32_t GPRMM16SubClassMask[] = {
4124 0x1e248000, 0x00000000, 0x00000000,
4125 0x00000000, 0x013a2400, 0x00000000, // sub_32
4126};
4127
4128static const uint32_t GPRMM16MovePSubClassMask[] = {
4129 0x08690000, 0x00000002, 0x00000000,
4130 0x00000000, 0x10264800, 0x00000000, // sub_32
4131};
4132
4133static const uint32_t GPRMM16ZeroSubClassMask[] = {
4134 0x1e460000, 0x00000002, 0x00000000,
4135 0x00000000, 0x113c3000, 0x00000000, // sub_32
4136};
4137
4138static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4139 0x1e040000, 0x00000000, 0x00000000,
4140 0x00000000, 0x01382000, 0x00000000, // sub_32
4141};
4142
4143static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4144 0x08280000, 0x00000000, 0x00000000,
4145 0x00000000, 0x00224000, 0x00000000, // sub_32
4146};
4147
4148static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
4149 0x12100000, 0x00000000, 0x00000000,
4150 0x00000000, 0x01088000, 0x00000000, // sub_32
4151};
4152
4153static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4154 0x08200000, 0x00000000, 0x00000000,
4155 0x00000000, 0x00220000, 0x00000000, // sub_32
4156};
4157
4158static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4159 0x08400000, 0x00000002, 0x00000000,
4160 0x00000000, 0x10240000, 0x00000000, // sub_32
4161};
4162
4163static const uint32_t HI32DSPSubClassMask[] = {
4164 0x00800000, 0x00000004, 0x00000000,
4165 0x00000000, 0x20000000, 0x00000000, // sub_32
4166 0x00000000, 0x02010000, 0x00000000, // sub_hi
4167 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4168};
4169
4170static const uint32_t LO32DSPSubClassMask[] = {
4171 0x01000000, 0x00000008, 0x00000000,
4172 0x00000000, 0x40000000, 0x00000020, // sub_32
4173 0x00000000, 0x02010000, 0x00000000, // sub_lo
4174};
4175
4176static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4177 0x12000000, 0x00000000, 0x00000000,
4178 0x00000000, 0x01080000, 0x00000000, // sub_32
4179};
4180
4181static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
4182 0x14000000, 0x00000000, 0x00000000,
4183 0x00000000, 0x01100000, 0x00000000, // sub_32
4184};
4185
4186static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4187 0x08000000, 0x00000000, 0x00000000,
4188 0x00000000, 0x00200000, 0x00000000, // sub_32
4189};
4190
4191static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4192 0x10000000, 0x00000000, 0x00000000,
4193 0x00000000, 0x01000000, 0x00000000, // sub_32
4194};
4195
4196static const uint32_t CPURARegSubClassMask[] = {
4197 0x20000000, 0x00000000, 0x00000000,
4198 0x00000000, 0x08000000, 0x00000000, // sub_32
4199};
4200
4201static const uint32_t CPUSPRegSubClassMask[] = {
4202 0x40000000, 0x00000010, 0x00000000,
4203 0x00000000, 0x80000000, 0x00000000, // sub_32
4204};
4205
4206static const uint32_t DSPCCSubClassMask[] = {
4207 0x80000000, 0x00000000, 0x00000000,
4208};
4209
4210static const uint32_t GP32SubClassMask[] = {
4211 0x00000000, 0x00000001, 0x00000000,
4212 0x00000000, 0x04000000, 0x00000000, // sub_32
4213};
4214
4215static const uint32_t GPR32ZEROSubClassMask[] = {
4216 0x00000000, 0x00000002, 0x00000000,
4217 0x00000000, 0x10000000, 0x00000000, // sub_32
4218};
4219
4220static const uint32_t HI32SubClassMask[] = {
4221 0x00000000, 0x00000004, 0x00000000,
4222 0x00000000, 0x20000000, 0x00000000, // sub_32
4223 0x00000000, 0x02000000, 0x00000000, // sub_hi
4224 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4225};
4226
4227static const uint32_t LO32SubClassMask[] = {
4228 0x00000000, 0x00000008, 0x00000000,
4229 0x00000000, 0x40000000, 0x00000020, // sub_32
4230 0x00000000, 0x02000000, 0x00000000, // sub_lo
4231};
4232
4233static const uint32_t SP32SubClassMask[] = {
4234 0x00000000, 0x00000010, 0x00000000,
4235 0x00000000, 0x80000000, 0x00000000, // sub_32
4236};
4237
4238static const uint32_t FGR64SubClassMask[] = {
4239 0x00000000, 0x00000020, 0x00000000,
4240 0x00000001, 0x00000000, 0x0000001f, // sub_64
4241};
4242
4243static const uint32_t GPR64SubClassMask[] = {
4244 0x00000000, 0x9d3efec0, 0x00000000,
4245};
4246
4247static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4248 0x00000000, 0x8d3ae680, 0x00000000,
4249};
4250
4251static const uint32_t AFGR64SubClassMask[] = {
4252 0x00000000, 0x00000100, 0x00000000,
4253};
4254
4255static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4256 0x00000000, 0x813a2600, 0x00000000,
4257};
4258
4259static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4260 0x00000000, 0x013a2400, 0x00000000,
4261};
4262
4263static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4264 0x00000000, 0x10264800, 0x00000000,
4265};
4266
4267static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4268 0x00000000, 0x113c3000, 0x00000000,
4269};
4270
4271static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4272 0x00000000, 0x01382000, 0x00000000,
4273};
4274
4275static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4276 0x00000000, 0x00224000, 0x00000000,
4277};
4278
4279static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
4280 0x00000000, 0x01088000, 0x00000000,
4281};
4282
4283static const uint32_t ACC64DSPSubClassMask[] = {
4284 0x00000000, 0x02010000, 0x00000000,
4285 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4286};
4287
4288static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4289 0x00000000, 0x00220000, 0x00000000,
4290};
4291
4292static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4293 0x00000000, 0x10240000, 0x00000000,
4294};
4295
4296static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4297 0x00000000, 0x01080000, 0x00000000,
4298};
4299
4300static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
4301 0x00000000, 0x01100000, 0x00000000,
4302};
4303
4304static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4305 0x00000000, 0x00200000, 0x00000000,
4306};
4307
4308static const uint32_t OCTEON_MPLSubClassMask[] = {
4309 0x00000000, 0x00400000, 0x00000000,
4310};
4311
4312static const uint32_t OCTEON_PSubClassMask[] = {
4313 0x00000000, 0x00800000, 0x00000000,
4314};
4315
4316static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4317 0x00000000, 0x01000000, 0x00000000,
4318};
4319
4320static const uint32_t ACC64SubClassMask[] = {
4321 0x00000000, 0x02000000, 0x00000000,
4322 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4323};
4324
4325static const uint32_t GP64SubClassMask[] = {
4326 0x00000000, 0x04000000, 0x00000000,
4327};
4328
4329static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4330 0x00000000, 0x08000000, 0x00000000,
4331};
4332
4333static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4334 0x00000000, 0x10000000, 0x00000000,
4335};
4336
4337static const uint32_t HI64SubClassMask[] = {
4338 0x00000000, 0x20000000, 0x00000000,
4339 0x00000000, 0x00000000, 0x00000020, // sub_hi
4340};
4341
4342static const uint32_t LO64SubClassMask[] = {
4343 0x00000000, 0x40000000, 0x00000000,
4344 0x00000000, 0x00000000, 0x00000020, // sub_lo
4345};
4346
4347static const uint32_t SP64SubClassMask[] = {
4348 0x00000000, 0x80000000, 0x00000000,
4349};
4350
4351static const uint32_t MSA128BSubClassMask[] = {
4352 0x00000000, 0x00000000, 0x0000001f,
4353};
4354
4355static const uint32_t MSA128DSubClassMask[] = {
4356 0x00000000, 0x00000000, 0x0000001f,
4357};
4358
4359static const uint32_t MSA128HSubClassMask[] = {
4360 0x00000000, 0x00000000, 0x0000001f,
4361};
4362
4363static const uint32_t MSA128WSubClassMask[] = {
4364 0x00000000, 0x00000000, 0x0000001f,
4365};
4366
4367static const uint32_t MSA128WEvensSubClassMask[] = {
4368 0x00000000, 0x00000000, 0x00000010,
4369};
4370
4371static const uint32_t ACC128SubClassMask[] = {
4372 0x00000000, 0x00000000, 0x00000020,
4373};
4374
4375static const uint16_t SuperRegIdxSeqs[] = {
4376 /* 0 */ 1, 0,
4377 /* 2 */ 2, 0,
4378 /* 4 */ 8, 0,
4379 /* 6 */ 1, 9, 0,
4380 /* 9 */ 8, 9, 0,
4381 /* 12 */ 1, 8, 10, 0,
4382 /* 16 */ 11, 0,
4383};
4384
4385static const TargetRegisterClass *const FGR32Superclasses[] = {
4386 &Mips::FGRCCRegClass,
4387 nullptr
4388};
4389
4390static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4391 &Mips::FGR32RegClass,
4392 nullptr
4393};
4394
4395static const TargetRegisterClass *const GPR32Superclasses[] = {
4396 &Mips::DSPRRegClass,
4397 nullptr
4398};
4399
4400static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4401 &Mips::DSPRRegClass,
4402 &Mips::GPR32RegClass,
4403 nullptr
4404};
4405
4406static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4407 &Mips::DSPRRegClass,
4408 &Mips::GPR32RegClass,
4409 &Mips::GPR32NONZERORegClass,
4410 nullptr
4411};
4412
4413static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4414 &Mips::DSPRRegClass,
4415 &Mips::GPR32RegClass,
4416 &Mips::GPR32NONZERORegClass,
4417 &Mips::CPU16RegsPlusSPRegClass,
4418 nullptr
4419};
4420
4421static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4422 &Mips::DSPRRegClass,
4423 &Mips::GPR32RegClass,
4424 &Mips::GPR32NONZERORegClass,
4425 &Mips::CPU16RegsPlusSPRegClass,
4426 &Mips::CPU16RegsRegClass,
4427 nullptr
4428};
4429
4430static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4431 &Mips::DSPRRegClass,
4432 &Mips::GPR32RegClass,
4433 nullptr
4434};
4435
4436static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4437 &Mips::DSPRRegClass,
4438 &Mips::GPR32RegClass,
4439 nullptr
4440};
4441
4442static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4443 &Mips::DSPRRegClass,
4444 &Mips::GPR32RegClass,
4445 &Mips::GPR32NONZERORegClass,
4446 &Mips::CPU16RegsPlusSPRegClass,
4447 &Mips::CPU16RegsRegClass,
4448 &Mips::GPRMM16RegClass,
4449 &Mips::GPRMM16ZeroRegClass,
4450 nullptr
4451};
4452
4453static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4454 &Mips::DSPRRegClass,
4455 &Mips::GPR32RegClass,
4456 &Mips::GPR32NONZERORegClass,
4457 &Mips::GPRMM16MovePRegClass,
4458 nullptr
4459};
4460
4461static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
4462 &Mips::DSPRRegClass,
4463 &Mips::GPR32RegClass,
4464 &Mips::GPR32NONZERORegClass,
4465 nullptr
4466};
4467
4468static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4469 &Mips::DSPRRegClass,
4470 &Mips::GPR32RegClass,
4471 &Mips::GPR32NONZERORegClass,
4472 &Mips::CPU16RegsPlusSPRegClass,
4473 &Mips::CPU16RegsRegClass,
4474 &Mips::GPRMM16RegClass,
4475 &Mips::GPRMM16MovePRegClass,
4476 &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4477 nullptr
4478};
4479
4480static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4481 &Mips::DSPRRegClass,
4482 &Mips::GPR32RegClass,
4483 &Mips::GPRMM16MovePRegClass,
4484 &Mips::GPRMM16ZeroRegClass,
4485 nullptr
4486};
4487
4488static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4489 &Mips::DSPRRegClass,
4490 &Mips::GPR32RegClass,
4491 &Mips::GPR32NONZERORegClass,
4492 &Mips::CPU16RegsPlusSPRegClass,
4493 &Mips::CPU16RegsRegClass,
4494 &Mips::GPRMM16RegClass,
4495 &Mips::GPRMM16ZeroRegClass,
4496 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4497 &Mips::GPRMM16MovePPairSecondRegClass,
4498 nullptr
4499};
4500
4501static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
4502 &Mips::DSPRRegClass,
4503 &Mips::GPR32RegClass,
4504 &Mips::GPR32NONZERORegClass,
4505 &Mips::CPU16RegsPlusSPRegClass,
4506 &Mips::CPU16RegsRegClass,
4507 &Mips::GPRMM16RegClass,
4508 &Mips::GPRMM16ZeroRegClass,
4509 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4510 nullptr
4511};
4512
4513static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4514 &Mips::DSPRRegClass,
4515 &Mips::GPR32RegClass,
4516 &Mips::GPR32NONZERORegClass,
4517 &Mips::CPU16RegsPlusSPRegClass,
4518 &Mips::CPU16RegsRegClass,
4519 &Mips::GPRMM16RegClass,
4520 &Mips::GPRMM16MovePRegClass,
4521 &Mips::GPRMM16ZeroRegClass,
4522 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4523 &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4524 &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
4525 &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4526 nullptr
4527};
4528
4529static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4530 &Mips::DSPRRegClass,
4531 &Mips::GPR32RegClass,
4532 &Mips::GPR32NONZERORegClass,
4533 &Mips::CPU16RegsPlusSPRegClass,
4534 &Mips::CPU16RegsRegClass,
4535 &Mips::GPRMM16RegClass,
4536 &Mips::GPRMM16ZeroRegClass,
4537 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4538 &Mips::GPRMM16MovePPairSecondRegClass,
4539 &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4540 &Mips::GPRMM16MovePPairFirstRegClass,
4541 nullptr
4542};
4543
4544static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4545 &Mips::DSPRRegClass,
4546 &Mips::GPR32RegClass,
4547 &Mips::GPR32NONZERORegClass,
4548 nullptr
4549};
4550
4551static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4552 &Mips::DSPRRegClass,
4553 &Mips::GPR32RegClass,
4554 &Mips::GPR32NONZERORegClass,
4555 &Mips::CPU16RegsPlusSPRegClass,
4556 nullptr
4557};
4558
4559static const TargetRegisterClass *const GP32Superclasses[] = {
4560 &Mips::DSPRRegClass,
4561 &Mips::GPR32RegClass,
4562 &Mips::GPR32NONZERORegClass,
4563 nullptr
4564};
4565
4566static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4567 &Mips::DSPRRegClass,
4568 &Mips::GPR32RegClass,
4569 &Mips::GPRMM16MovePRegClass,
4570 &Mips::GPRMM16ZeroRegClass,
4571 &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4572 nullptr
4573};
4574
4575static const TargetRegisterClass *const HI32Superclasses[] = {
4576 &Mips::HI32DSPRegClass,
4577 nullptr
4578};
4579
4580static const TargetRegisterClass *const LO32Superclasses[] = {
4581 &Mips::LO32DSPRegClass,
4582 nullptr
4583};
4584
4585static const TargetRegisterClass *const SP32Superclasses[] = {
4586 &Mips::DSPRRegClass,
4587 &Mips::GPR32RegClass,
4588 &Mips::GPR32NONZERORegClass,
4589 &Mips::CPU16RegsPlusSPRegClass,
4590 &Mips::CPUSPRegRegClass,
4591 nullptr
4592};
4593
4594static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4595 &Mips::GPR64RegClass,
4596 nullptr
4597};
4598
4599static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4600 &Mips::GPR64RegClass,
4601 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4602 nullptr
4603};
4604
4605static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4606 &Mips::GPR64RegClass,
4607 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4608 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4609 nullptr
4610};
4611
4612static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4613 &Mips::GPR64RegClass,
4614 nullptr
4615};
4616
4617static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4618 &Mips::GPR64RegClass,
4619 nullptr
4620};
4621
4622static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4623 &Mips::GPR64RegClass,
4624 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4625 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4626 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4627 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4628 nullptr
4629};
4630
4631static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4632 &Mips::GPR64RegClass,
4633 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4634 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4635 nullptr
4636};
4637
4638static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4639 &Mips::GPR64RegClass,
4640 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4641 nullptr
4642};
4643
4644static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4645 &Mips::GPR64RegClass,
4646 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4647 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4648 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4649 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4650 &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4651 nullptr
4652};
4653
4654static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4655 &Mips::GPR64RegClass,
4656 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4657 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4658 nullptr
4659};
4660
4661static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4662 &Mips::GPR64RegClass,
4663 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4664 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4665 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4666 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4667 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4668 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4669 nullptr
4670};
4671
4672static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4673 &Mips::GPR64RegClass,
4674 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4675 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4676 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4677 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4678 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4679 nullptr
4680};
4681
4682static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4683 &Mips::GPR64RegClass,
4684 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4685 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4686 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4687 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4688 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4689 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4690 &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4691 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
4692 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4693 nullptr
4694};
4695
4696static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4697 &Mips::GPR64RegClass,
4698 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4699 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4700 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4701 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4702 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4703 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4704 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4705 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
4706 nullptr
4707};
4708
4709static const TargetRegisterClass *const ACC64Superclasses[] = {
4710 &Mips::ACC64DSPRegClass,
4711 nullptr
4712};
4713
4714static const TargetRegisterClass *const GP64Superclasses[] = {
4715 &Mips::GPR64RegClass,
4716 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4717 nullptr
4718};
4719
4720static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4721 &Mips::GPR64RegClass,
4722 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4723 nullptr
4724};
4725
4726static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4727 &Mips::GPR64RegClass,
4728 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4729 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4730 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4731 nullptr
4732};
4733
4734static const TargetRegisterClass *const SP64Superclasses[] = {
4735 &Mips::GPR64RegClass,
4736 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4737 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4738 nullptr
4739};
4740
4741static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4742 &Mips::MSA128F16RegClass,
4743 &Mips::MSA128DRegClass,
4744 &Mips::MSA128HRegClass,
4745 &Mips::MSA128WRegClass,
4746 nullptr
4747};
4748
4749static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4750 &Mips::MSA128F16RegClass,
4751 &Mips::MSA128BRegClass,
4752 &Mips::MSA128HRegClass,
4753 &Mips::MSA128WRegClass,
4754 nullptr
4755};
4756
4757static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4758 &Mips::MSA128F16RegClass,
4759 &Mips::MSA128BRegClass,
4760 &Mips::MSA128DRegClass,
4761 &Mips::MSA128WRegClass,
4762 nullptr
4763};
4764
4765static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4766 &Mips::MSA128F16RegClass,
4767 &Mips::MSA128BRegClass,
4768 &Mips::MSA128DRegClass,
4769 &Mips::MSA128HRegClass,
4770 nullptr
4771};
4772
4773static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4774 &Mips::MSA128F16RegClass,
4775 &Mips::MSA128BRegClass,
4776 &Mips::MSA128DRegClass,
4777 &Mips::MSA128HRegClass,
4778 &Mips::MSA128WRegClass,
4779 nullptr
4780};
4781
4782
4783static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {
4784 const auto & S = MF.getSubtarget<MipsSubtarget>();
4785 return S.isABI_O32() && !S.useOddSPReg();
4786 }
4787
4788static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF) {
4789 static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
4790 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4791 const ArrayRef<MCPhysReg> Order[] = {
4792 ArrayRef(MCR.begin(), MCR.getNumRegs()),
4793 ArrayRef(AltOrder1)
4794 };
4795 const unsigned Select = FGR32AltOrderSelect(MF);
4796 assert(Select < 2);
4797 return Order[Select];
4798}
4799
4800static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {
4801 const auto & S = MF.getSubtarget<MipsSubtarget>();
4802 return S.isABI_O32() && !S.useOddSPReg();
4803 }
4804
4805static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF) {
4806 static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
4807 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
4808 const ArrayRef<MCPhysReg> Order[] = {
4809 ArrayRef(MCR.begin(), MCR.getNumRegs()),
4810 ArrayRef(AltOrder1)
4811 };
4812 const unsigned Select = FGR64AltOrderSelect(MF);
4813 assert(Select < 2);
4814 return Order[Select];
4815}
4816
4817namespace Mips { // Register class instances
4818 extern const TargetRegisterClass MSA128F16RegClass = {
4819 &MipsMCRegisterClasses[MSA128F16RegClassID],
4820 MSA128F16SubClassMask,
4821 SuperRegIdxSeqs + 1,
4822 LaneBitmask(0x0000000000000041),
4823 0,
4824 false,
4825 0x00, /* TSFlags */
4826 true, /* HasDisjunctSubRegs */
4827 false, /* CoveredBySubRegs */
4828 NullRegClasses,
4829 nullptr
4830 };
4831
4832 extern const TargetRegisterClass CCRRegClass = {
4833 &MipsMCRegisterClasses[CCRRegClassID],
4834 CCRSubClassMask,
4835 SuperRegIdxSeqs + 1,
4836 LaneBitmask(0x0000000000000001),
4837 0,
4838 false,
4839 0x00, /* TSFlags */
4840 false, /* HasDisjunctSubRegs */
4841 false, /* CoveredBySubRegs */
4842 NullRegClasses,
4843 nullptr
4844 };
4845
4846 extern const TargetRegisterClass COP0RegClass = {
4847 &MipsMCRegisterClasses[COP0RegClassID],
4848 COP0SubClassMask,
4849 SuperRegIdxSeqs + 1,
4850 LaneBitmask(0x0000000000000001),
4851 0,
4852 false,
4853 0x00, /* TSFlags */
4854 false, /* HasDisjunctSubRegs */
4855 false, /* CoveredBySubRegs */
4856 NullRegClasses,
4857 nullptr
4858 };
4859
4860 extern const TargetRegisterClass COP2RegClass = {
4861 &MipsMCRegisterClasses[COP2RegClassID],
4862 COP2SubClassMask,
4863 SuperRegIdxSeqs + 1,
4864 LaneBitmask(0x0000000000000001),
4865 0,
4866 false,
4867 0x00, /* TSFlags */
4868 false, /* HasDisjunctSubRegs */
4869 false, /* CoveredBySubRegs */
4870 NullRegClasses,
4871 nullptr
4872 };
4873
4874 extern const TargetRegisterClass COP3RegClass = {
4875 &MipsMCRegisterClasses[COP3RegClassID],
4876 COP3SubClassMask,
4877 SuperRegIdxSeqs + 1,
4878 LaneBitmask(0x0000000000000001),
4879 0,
4880 false,
4881 0x00, /* TSFlags */
4882 false, /* HasDisjunctSubRegs */
4883 false, /* CoveredBySubRegs */
4884 NullRegClasses,
4885 nullptr
4886 };
4887
4888 extern const TargetRegisterClass DSPRRegClass = {
4889 &MipsMCRegisterClasses[DSPRRegClassID],
4890 DSPRSubClassMask,
4891 SuperRegIdxSeqs + 0,
4892 LaneBitmask(0x0000000000000001),
4893 0,
4894 false,
4895 0x00, /* TSFlags */
4896 false, /* HasDisjunctSubRegs */
4897 false, /* CoveredBySubRegs */
4898 NullRegClasses,
4899 nullptr
4900 };
4901
4902 extern const TargetRegisterClass FGR32RegClass = {
4903 &MipsMCRegisterClasses[FGR32RegClassID],
4904 FGR32SubClassMask,
4905 SuperRegIdxSeqs + 9,
4906 LaneBitmask(0x0000000000000001),
4907 0,
4908 false,
4909 0x00, /* TSFlags */
4910 false, /* HasDisjunctSubRegs */
4911 false, /* CoveredBySubRegs */
4912 FGR32Superclasses,
4913 FGR32GetRawAllocationOrder
4914 };
4915
4916 extern const TargetRegisterClass FGRCCRegClass = {
4917 &MipsMCRegisterClasses[FGRCCRegClassID],
4918 FGRCCSubClassMask,
4919 SuperRegIdxSeqs + 9,
4920 LaneBitmask(0x0000000000000001),
4921 0,
4922 false,
4923 0x00, /* TSFlags */
4924 false, /* HasDisjunctSubRegs */
4925 false, /* CoveredBySubRegs */
4926 FGRCCSuperclasses,
4927 nullptr
4928 };
4929
4930 extern const TargetRegisterClass GPR32RegClass = {
4931 &MipsMCRegisterClasses[GPR32RegClassID],
4932 GPR32SubClassMask,
4933 SuperRegIdxSeqs + 0,
4934 LaneBitmask(0x0000000000000001),
4935 0,
4936 false,
4937 0x00, /* TSFlags */
4938 false, /* HasDisjunctSubRegs */
4939 false, /* CoveredBySubRegs */
4940 GPR32Superclasses,
4941 nullptr
4942 };
4943
4944 extern const TargetRegisterClass HWRegsRegClass = {
4945 &MipsMCRegisterClasses[HWRegsRegClassID],
4946 HWRegsSubClassMask,
4947 SuperRegIdxSeqs + 1,
4948 LaneBitmask(0x0000000000000001),
4949 0,
4950 false,
4951 0x00, /* TSFlags */
4952 false, /* HasDisjunctSubRegs */
4953 false, /* CoveredBySubRegs */
4954 NullRegClasses,
4955 nullptr
4956 };
4957
4958 extern const TargetRegisterClass MSACtrlRegClass = {
4959 &MipsMCRegisterClasses[MSACtrlRegClassID],
4960 MSACtrlSubClassMask,
4961 SuperRegIdxSeqs + 1,
4962 LaneBitmask(0x0000000000000001),
4963 0,
4964 false,
4965 0x00, /* TSFlags */
4966 false, /* HasDisjunctSubRegs */
4967 false, /* CoveredBySubRegs */
4968 NullRegClasses,
4969 nullptr
4970 };
4971
4972 extern const TargetRegisterClass GPR32NONZERORegClass = {
4973 &MipsMCRegisterClasses[GPR32NONZERORegClassID],
4974 GPR32NONZEROSubClassMask,
4975 SuperRegIdxSeqs + 0,
4976 LaneBitmask(0x0000000000000001),
4977 0,
4978 false,
4979 0x00, /* TSFlags */
4980 false, /* HasDisjunctSubRegs */
4981 false, /* CoveredBySubRegs */
4982 GPR32NONZEROSuperclasses,
4983 nullptr
4984 };
4985
4986 extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4987 &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
4988 CPU16RegsPlusSPSubClassMask,
4989 SuperRegIdxSeqs + 0,
4990 LaneBitmask(0x0000000000000001),
4991 0,
4992 false,
4993 0x00, /* TSFlags */
4994 false, /* HasDisjunctSubRegs */
4995 false, /* CoveredBySubRegs */
4996 CPU16RegsPlusSPSuperclasses,
4997 nullptr
4998 };
4999
5000 extern const TargetRegisterClass CPU16RegsRegClass = {
5001 &MipsMCRegisterClasses[CPU16RegsRegClassID],
5002 CPU16RegsSubClassMask,
5003 SuperRegIdxSeqs + 0,
5004 LaneBitmask(0x0000000000000001),
5005 0,
5006 false,
5007 0x00, /* TSFlags */
5008 false, /* HasDisjunctSubRegs */
5009 false, /* CoveredBySubRegs */
5010 CPU16RegsSuperclasses,
5011 nullptr
5012 };
5013
5014 extern const TargetRegisterClass FCCRegClass = {
5015 &MipsMCRegisterClasses[FCCRegClassID],
5016 FCCSubClassMask,
5017 SuperRegIdxSeqs + 1,
5018 LaneBitmask(0x0000000000000001),
5019 0,
5020 false,
5021 0x00, /* TSFlags */
5022 false, /* HasDisjunctSubRegs */
5023 false, /* CoveredBySubRegs */
5024 NullRegClasses,
5025 nullptr
5026 };
5027
5028 extern const TargetRegisterClass GPRMM16RegClass = {
5029 &MipsMCRegisterClasses[GPRMM16RegClassID],
5030 GPRMM16SubClassMask,
5031 SuperRegIdxSeqs + 0,
5032 LaneBitmask(0x0000000000000001),
5033 0,
5034 false,
5035 0x00, /* TSFlags */
5036 false, /* HasDisjunctSubRegs */
5037 false, /* CoveredBySubRegs */
5038 GPRMM16Superclasses,
5039 nullptr
5040 };
5041
5042 extern const TargetRegisterClass GPRMM16MovePRegClass = {
5043 &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
5044 GPRMM16MovePSubClassMask,
5045 SuperRegIdxSeqs + 0,
5046 LaneBitmask(0x0000000000000001),
5047 0,
5048 false,
5049 0x00, /* TSFlags */
5050 false, /* HasDisjunctSubRegs */
5051 false, /* CoveredBySubRegs */
5052 GPRMM16MovePSuperclasses,
5053 nullptr
5054 };
5055
5056 extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5057 &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
5058 GPRMM16ZeroSubClassMask,
5059 SuperRegIdxSeqs + 0,
5060 LaneBitmask(0x0000000000000001),
5061 0,
5062 false,
5063 0x00, /* TSFlags */
5064 false, /* HasDisjunctSubRegs */
5065 false, /* CoveredBySubRegs */
5066 GPRMM16ZeroSuperclasses,
5067 nullptr
5068 };
5069
5070 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5071 &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
5072 CPU16Regs_and_GPRMM16ZeroSubClassMask,
5073 SuperRegIdxSeqs + 0,
5074 LaneBitmask(0x0000000000000001),
5075 0,
5076 false,
5077 0x00, /* TSFlags */
5078 false, /* HasDisjunctSubRegs */
5079 false, /* CoveredBySubRegs */
5080 CPU16Regs_and_GPRMM16ZeroSuperclasses,
5081 nullptr
5082 };
5083
5084 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5085 &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5086 GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5087 SuperRegIdxSeqs + 0,
5088 LaneBitmask(0x0000000000000001),
5089 0,
5090 false,
5091 0x00, /* TSFlags */
5092 false, /* HasDisjunctSubRegs */
5093 false, /* CoveredBySubRegs */
5094 GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5095 nullptr
5096 };
5097
5098 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5099 &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
5100 GPRMM16MovePPairSecondSubClassMask,
5101 SuperRegIdxSeqs + 0,
5102 LaneBitmask(0x0000000000000001),
5103 0,
5104 false,
5105 0x00, /* TSFlags */
5106 false, /* HasDisjunctSubRegs */
5107 false, /* CoveredBySubRegs */
5108 GPRMM16MovePPairSecondSuperclasses,
5109 nullptr
5110 };
5111
5112 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5113 &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5114 CPU16Regs_and_GPRMM16MovePSubClassMask,
5115 SuperRegIdxSeqs + 0,
5116 LaneBitmask(0x0000000000000001),
5117 0,
5118 false,
5119 0x00, /* TSFlags */
5120 false, /* HasDisjunctSubRegs */
5121 false, /* CoveredBySubRegs */
5122 CPU16Regs_and_GPRMM16MovePSuperclasses,
5123 nullptr
5124 };
5125
5126 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5127 &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5128 GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5129 SuperRegIdxSeqs + 0,
5130 LaneBitmask(0x0000000000000001),
5131 0,
5132 false,
5133 0x00, /* TSFlags */
5134 false, /* HasDisjunctSubRegs */
5135 false, /* CoveredBySubRegs */
5136 GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5137 nullptr
5138 };
5139
5140 extern const TargetRegisterClass HI32DSPRegClass = {
5141 &MipsMCRegisterClasses[HI32DSPRegClassID],
5142 HI32DSPSubClassMask,
5143 SuperRegIdxSeqs + 12,
5144 LaneBitmask(0x0000000000000001),
5145 0,
5146 false,
5147 0x00, /* TSFlags */
5148 false, /* HasDisjunctSubRegs */
5149 false, /* CoveredBySubRegs */
5150 NullRegClasses,
5151 nullptr
5152 };
5153
5154 extern const TargetRegisterClass LO32DSPRegClass = {
5155 &MipsMCRegisterClasses[LO32DSPRegClassID],
5156 LO32DSPSubClassMask,
5157 SuperRegIdxSeqs + 6,
5158 LaneBitmask(0x0000000000000001),
5159 0,
5160 false,
5161 0x00, /* TSFlags */
5162 false, /* HasDisjunctSubRegs */
5163 false, /* CoveredBySubRegs */
5164 NullRegClasses,
5165 nullptr
5166 };
5167
5168 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5169 &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5170 CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5171 SuperRegIdxSeqs + 0,
5172 LaneBitmask(0x0000000000000001),
5173 0,
5174 false,
5175 0x00, /* TSFlags */
5176 false, /* HasDisjunctSubRegs */
5177 false, /* CoveredBySubRegs */
5178 CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5179 nullptr
5180 };
5181
5182 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5183 &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
5184 GPRMM16MovePPairFirstSubClassMask,
5185 SuperRegIdxSeqs + 0,
5186 LaneBitmask(0x0000000000000001),
5187 0,
5188 false,
5189 0x00, /* TSFlags */
5190 false, /* HasDisjunctSubRegs */
5191 false, /* CoveredBySubRegs */
5192 GPRMM16MovePPairFirstSuperclasses,
5193 nullptr
5194 };
5195
5196 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5197 &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5198 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5199 SuperRegIdxSeqs + 0,
5200 LaneBitmask(0x0000000000000001),
5201 0,
5202 false,
5203 0x00, /* TSFlags */
5204 false, /* HasDisjunctSubRegs */
5205 false, /* CoveredBySubRegs */
5206 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5207 nullptr
5208 };
5209
5210 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5211 &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5212 GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5213 SuperRegIdxSeqs + 0,
5214 LaneBitmask(0x0000000000000001),
5215 0,
5216 false,
5217 0x00, /* TSFlags */
5218 false, /* HasDisjunctSubRegs */
5219 false, /* CoveredBySubRegs */
5220 GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5221 nullptr
5222 };
5223
5224 extern const TargetRegisterClass CPURARegRegClass = {
5225 &MipsMCRegisterClasses[CPURARegRegClassID],
5226 CPURARegSubClassMask,
5227 SuperRegIdxSeqs + 0,
5228 LaneBitmask(0x0000000000000001),
5229 0,
5230 false,
5231 0x00, /* TSFlags */
5232 false, /* HasDisjunctSubRegs */
5233 false, /* CoveredBySubRegs */
5234 CPURARegSuperclasses,
5235 nullptr
5236 };
5237
5238 extern const TargetRegisterClass CPUSPRegRegClass = {
5239 &MipsMCRegisterClasses[CPUSPRegRegClassID],
5240 CPUSPRegSubClassMask,
5241 SuperRegIdxSeqs + 0,
5242 LaneBitmask(0x0000000000000001),
5243 0,
5244 false,
5245 0x00, /* TSFlags */
5246 false, /* HasDisjunctSubRegs */
5247 false, /* CoveredBySubRegs */
5248 CPUSPRegSuperclasses,
5249 nullptr
5250 };
5251
5252 extern const TargetRegisterClass DSPCCRegClass = {
5253 &MipsMCRegisterClasses[DSPCCRegClassID],
5254 DSPCCSubClassMask,
5255 SuperRegIdxSeqs + 1,
5256 LaneBitmask(0x0000000000000001),
5257 0,
5258 false,
5259 0x00, /* TSFlags */
5260 false, /* HasDisjunctSubRegs */
5261 false, /* CoveredBySubRegs */
5262 NullRegClasses,
5263 nullptr
5264 };
5265
5266 extern const TargetRegisterClass GP32RegClass = {
5267 &MipsMCRegisterClasses[GP32RegClassID],
5268 GP32SubClassMask,
5269 SuperRegIdxSeqs + 0,
5270 LaneBitmask(0x0000000000000001),
5271 0,
5272 false,
5273 0x00, /* TSFlags */
5274 false, /* HasDisjunctSubRegs */
5275 false, /* CoveredBySubRegs */
5276 GP32Superclasses,
5277 nullptr
5278 };
5279
5280 extern const TargetRegisterClass GPR32ZERORegClass = {
5281 &MipsMCRegisterClasses[GPR32ZERORegClassID],
5282 GPR32ZEROSubClassMask,
5283 SuperRegIdxSeqs + 0,
5284 LaneBitmask(0x0000000000000001),
5285 0,
5286 false,
5287 0x00, /* TSFlags */
5288 false, /* HasDisjunctSubRegs */
5289 false, /* CoveredBySubRegs */
5290 GPR32ZEROSuperclasses,
5291 nullptr
5292 };
5293
5294 extern const TargetRegisterClass HI32RegClass = {
5295 &MipsMCRegisterClasses[HI32RegClassID],
5296 HI32SubClassMask,
5297 SuperRegIdxSeqs + 12,
5298 LaneBitmask(0x0000000000000001),
5299 0,
5300 false,
5301 0x00, /* TSFlags */
5302 false, /* HasDisjunctSubRegs */
5303 false, /* CoveredBySubRegs */
5304 HI32Superclasses,
5305 nullptr
5306 };
5307
5308 extern const TargetRegisterClass LO32RegClass = {
5309 &MipsMCRegisterClasses[LO32RegClassID],
5310 LO32SubClassMask,
5311 SuperRegIdxSeqs + 6,
5312 LaneBitmask(0x0000000000000001),
5313 0,
5314 false,
5315 0x00, /* TSFlags */
5316 false, /* HasDisjunctSubRegs */
5317 false, /* CoveredBySubRegs */
5318 LO32Superclasses,
5319 nullptr
5320 };
5321
5322 extern const TargetRegisterClass SP32RegClass = {
5323 &MipsMCRegisterClasses[SP32RegClassID],
5324 SP32SubClassMask,
5325 SuperRegIdxSeqs + 0,
5326 LaneBitmask(0x0000000000000001),
5327 0,
5328 false,
5329 0x00, /* TSFlags */
5330 false, /* HasDisjunctSubRegs */
5331 false, /* CoveredBySubRegs */
5332 SP32Superclasses,
5333 nullptr
5334 };
5335
5336 extern const TargetRegisterClass FGR64RegClass = {
5337 &MipsMCRegisterClasses[FGR64RegClassID],
5338 FGR64SubClassMask,
5339 SuperRegIdxSeqs + 2,
5340 LaneBitmask(0x0000000000000041),
5341 0,
5342 false,
5343 0x00, /* TSFlags */
5344 true, /* HasDisjunctSubRegs */
5345 true, /* CoveredBySubRegs */
5346 NullRegClasses,
5347 FGR64GetRawAllocationOrder
5348 };
5349
5350 extern const TargetRegisterClass GPR64RegClass = {
5351 &MipsMCRegisterClasses[GPR64RegClassID],
5352 GPR64SubClassMask,
5353 SuperRegIdxSeqs + 1,
5354 LaneBitmask(0x0000000000000001),
5355 0,
5356 false,
5357 0x00, /* TSFlags */
5358 false, /* HasDisjunctSubRegs */
5359 false, /* CoveredBySubRegs */
5360 NullRegClasses,
5361 nullptr
5362 };
5363
5364 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5365 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5366 GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5367 SuperRegIdxSeqs + 1,
5368 LaneBitmask(0x0000000000000001),
5369 0,
5370 false,
5371 0x00, /* TSFlags */
5372 false, /* HasDisjunctSubRegs */
5373 false, /* CoveredBySubRegs */
5374 GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
5375 nullptr
5376 };
5377
5378 extern const TargetRegisterClass AFGR64RegClass = {
5379 &MipsMCRegisterClasses[AFGR64RegClassID],
5380 AFGR64SubClassMask,
5381 SuperRegIdxSeqs + 1,
5382 LaneBitmask(0x0000000000000041),
5383 0,
5384 false,
5385 0x00, /* TSFlags */
5386 true, /* HasDisjunctSubRegs */
5387 true, /* CoveredBySubRegs */
5388 NullRegClasses,
5389 nullptr
5390 };
5391
5392 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5393 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5394 GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5395 SuperRegIdxSeqs + 1,
5396 LaneBitmask(0x0000000000000001),
5397 0,
5398 false,
5399 0x00, /* TSFlags */
5400 false, /* HasDisjunctSubRegs */
5401 false, /* CoveredBySubRegs */
5402 GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
5403 nullptr
5404 };
5405
5406 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5407 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
5408 GPR64_with_sub_32_in_CPU16RegsSubClassMask,
5409 SuperRegIdxSeqs + 1,
5410 LaneBitmask(0x0000000000000001),
5411 0,
5412 false,
5413 0x00, /* TSFlags */
5414 false, /* HasDisjunctSubRegs */
5415 false, /* CoveredBySubRegs */
5416 GPR64_with_sub_32_in_CPU16RegsSuperclasses,
5417 nullptr
5418 };
5419
5420 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5421 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
5422 GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
5423 SuperRegIdxSeqs + 1,
5424 LaneBitmask(0x0000000000000001),
5425 0,
5426 false,
5427 0x00, /* TSFlags */
5428 false, /* HasDisjunctSubRegs */
5429 false, /* CoveredBySubRegs */
5430 GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
5431 nullptr
5432 };
5433
5434 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5435 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
5436 GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
5437 SuperRegIdxSeqs + 1,
5438 LaneBitmask(0x0000000000000001),
5439 0,
5440 false,
5441 0x00, /* TSFlags */
5442 false, /* HasDisjunctSubRegs */
5443 false, /* CoveredBySubRegs */
5444 GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
5445 nullptr
5446 };
5447
5448 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5449 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
5450 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5451 SuperRegIdxSeqs + 1,
5452 LaneBitmask(0x0000000000000001),
5453 0,
5454 false,
5455 0x00, /* TSFlags */
5456 false, /* HasDisjunctSubRegs */
5457 false, /* CoveredBySubRegs */
5458 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5459 nullptr
5460 };
5461
5462 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5463 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
5464 GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5465 SuperRegIdxSeqs + 1,
5466 LaneBitmask(0x0000000000000001),
5467 0,
5468 false,
5469 0x00, /* TSFlags */
5470 false, /* HasDisjunctSubRegs */
5471 false, /* CoveredBySubRegs */
5472 GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5473 nullptr
5474 };
5475
5476 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
5477 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
5478 GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
5479 SuperRegIdxSeqs + 1,
5480 LaneBitmask(0x0000000000000001),
5481 0,
5482 false,
5483 0x00, /* TSFlags */
5484 false, /* HasDisjunctSubRegs */
5485 false, /* CoveredBySubRegs */
5486 GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,
5487 nullptr
5488 };
5489
5490 extern const TargetRegisterClass ACC64DSPRegClass = {
5491 &MipsMCRegisterClasses[ACC64DSPRegClassID],
5492 ACC64DSPSubClassMask,
5493 SuperRegIdxSeqs + 16,
5494 LaneBitmask(0x0000000000000041),
5495 0,
5496 false,
5497 0x00, /* TSFlags */
5498 true, /* HasDisjunctSubRegs */
5499 true, /* CoveredBySubRegs */
5500 NullRegClasses,
5501 nullptr
5502 };
5503
5504 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5505 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
5506 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
5507 SuperRegIdxSeqs + 1,
5508 LaneBitmask(0x0000000000000001),
5509 0,
5510 false,
5511 0x00, /* TSFlags */
5512 false, /* HasDisjunctSubRegs */
5513 false, /* CoveredBySubRegs */
5514 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
5515 nullptr
5516 };
5517
5518 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5519 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5520 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5521 SuperRegIdxSeqs + 1,
5522 LaneBitmask(0x0000000000000001),
5523 0,
5524 false,
5525 0x00, /* TSFlags */
5526 false, /* HasDisjunctSubRegs */
5527 false, /* CoveredBySubRegs */
5528 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5529 nullptr
5530 };
5531
5532 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5533 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5534 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5535 SuperRegIdxSeqs + 1,
5536 LaneBitmask(0x0000000000000001),
5537 0,
5538 false,
5539 0x00, /* TSFlags */
5540 false, /* HasDisjunctSubRegs */
5541 false, /* CoveredBySubRegs */
5542 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5543 nullptr
5544 };
5545
5546 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
5547 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
5548 GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
5549 SuperRegIdxSeqs + 1,
5550 LaneBitmask(0x0000000000000001),
5551 0,
5552 false,
5553 0x00, /* TSFlags */
5554 false, /* HasDisjunctSubRegs */
5555 false, /* CoveredBySubRegs */
5556 GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,
5557 nullptr
5558 };
5559
5560 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5561 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5562 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5563 SuperRegIdxSeqs + 1,
5564 LaneBitmask(0x0000000000000001),
5565 0,
5566 false,
5567 0x00, /* TSFlags */
5568 false, /* HasDisjunctSubRegs */
5569 false, /* CoveredBySubRegs */
5570 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5571 nullptr
5572 };
5573
5574 extern const TargetRegisterClass OCTEON_MPLRegClass = {
5575 &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
5576 OCTEON_MPLSubClassMask,
5577 SuperRegIdxSeqs + 1,
5578 LaneBitmask(0x0000000000000001),
5579 0,
5580 false,
5581 0x00, /* TSFlags */
5582 false, /* HasDisjunctSubRegs */
5583 false, /* CoveredBySubRegs */
5584 NullRegClasses,
5585 nullptr
5586 };
5587
5588 extern const TargetRegisterClass OCTEON_PRegClass = {
5589 &MipsMCRegisterClasses[OCTEON_PRegClassID],
5590 OCTEON_PSubClassMask,
5591 SuperRegIdxSeqs + 1,
5592 LaneBitmask(0x0000000000000001),
5593 0,
5594 false,
5595 0x00, /* TSFlags */
5596 false, /* HasDisjunctSubRegs */
5597 false, /* CoveredBySubRegs */
5598 NullRegClasses,
5599 nullptr
5600 };
5601
5602 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5603 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5604 GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5605 SuperRegIdxSeqs + 1,
5606 LaneBitmask(0x0000000000000001),
5607 0,
5608 false,
5609 0x00, /* TSFlags */
5610 false, /* HasDisjunctSubRegs */
5611 false, /* CoveredBySubRegs */
5612 GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5613 nullptr
5614 };
5615
5616 extern const TargetRegisterClass ACC64RegClass = {
5617 &MipsMCRegisterClasses[ACC64RegClassID],
5618 ACC64SubClassMask,
5619 SuperRegIdxSeqs + 16,
5620 LaneBitmask(0x0000000000000041),
5621 0,
5622 false,
5623 0x00, /* TSFlags */
5624 true, /* HasDisjunctSubRegs */
5625 true, /* CoveredBySubRegs */
5626 ACC64Superclasses,
5627 nullptr
5628 };
5629
5630 extern const TargetRegisterClass GP64RegClass = {
5631 &MipsMCRegisterClasses[GP64RegClassID],
5632 GP64SubClassMask,
5633 SuperRegIdxSeqs + 1,
5634 LaneBitmask(0x0000000000000001),
5635 0,
5636 false,
5637 0x00, /* TSFlags */
5638 false, /* HasDisjunctSubRegs */
5639 false, /* CoveredBySubRegs */
5640 GP64Superclasses,
5641 nullptr
5642 };
5643
5644 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5645 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
5646 GPR64_with_sub_32_in_CPURARegSubClassMask,
5647 SuperRegIdxSeqs + 1,
5648 LaneBitmask(0x0000000000000001),
5649 0,
5650 false,
5651 0x00, /* TSFlags */
5652 false, /* HasDisjunctSubRegs */
5653 false, /* CoveredBySubRegs */
5654 GPR64_with_sub_32_in_CPURARegSuperclasses,
5655 nullptr
5656 };
5657
5658 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5659 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
5660 GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
5661 SuperRegIdxSeqs + 1,
5662 LaneBitmask(0x0000000000000001),
5663 0,
5664 false,
5665 0x00, /* TSFlags */
5666 false, /* HasDisjunctSubRegs */
5667 false, /* CoveredBySubRegs */
5668 GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
5669 nullptr
5670 };
5671
5672 extern const TargetRegisterClass HI64RegClass = {
5673 &MipsMCRegisterClasses[HI64RegClassID],
5674 HI64SubClassMask,
5675 SuperRegIdxSeqs + 4,
5676 LaneBitmask(0x0000000000000001),
5677 0,
5678 false,
5679 0x00, /* TSFlags */
5680 false, /* HasDisjunctSubRegs */
5681 false, /* CoveredBySubRegs */
5682 NullRegClasses,
5683 nullptr
5684 };
5685
5686 extern const TargetRegisterClass LO64RegClass = {
5687 &MipsMCRegisterClasses[LO64RegClassID],
5688 LO64SubClassMask,
5689 SuperRegIdxSeqs + 7,
5690 LaneBitmask(0x0000000000000001),
5691 0,
5692 false,
5693 0x00, /* TSFlags */
5694 false, /* HasDisjunctSubRegs */
5695 false, /* CoveredBySubRegs */
5696 NullRegClasses,
5697 nullptr
5698 };
5699
5700 extern const TargetRegisterClass SP64RegClass = {
5701 &MipsMCRegisterClasses[SP64RegClassID],
5702 SP64SubClassMask,
5703 SuperRegIdxSeqs + 1,
5704 LaneBitmask(0x0000000000000001),
5705 0,
5706 false,
5707 0x00, /* TSFlags */
5708 false, /* HasDisjunctSubRegs */
5709 false, /* CoveredBySubRegs */
5710 SP64Superclasses,
5711 nullptr
5712 };
5713
5714 extern const TargetRegisterClass MSA128BRegClass = {
5715 &MipsMCRegisterClasses[MSA128BRegClassID],
5716 MSA128BSubClassMask,
5717 SuperRegIdxSeqs + 1,
5718 LaneBitmask(0x0000000000000041),
5719 0,
5720 false,
5721 0x00, /* TSFlags */
5722 true, /* HasDisjunctSubRegs */
5723 false, /* CoveredBySubRegs */
5724 MSA128BSuperclasses,
5725 nullptr
5726 };
5727
5728 extern const TargetRegisterClass MSA128DRegClass = {
5729 &MipsMCRegisterClasses[MSA128DRegClassID],
5730 MSA128DSubClassMask,
5731 SuperRegIdxSeqs + 1,
5732 LaneBitmask(0x0000000000000041),
5733 0,
5734 false,
5735 0x00, /* TSFlags */
5736 true, /* HasDisjunctSubRegs */
5737 false, /* CoveredBySubRegs */
5738 MSA128DSuperclasses,
5739 nullptr
5740 };
5741
5742 extern const TargetRegisterClass MSA128HRegClass = {
5743 &MipsMCRegisterClasses[MSA128HRegClassID],
5744 MSA128HSubClassMask,
5745 SuperRegIdxSeqs + 1,
5746 LaneBitmask(0x0000000000000041),
5747 0,
5748 false,
5749 0x00, /* TSFlags */
5750 true, /* HasDisjunctSubRegs */
5751 false, /* CoveredBySubRegs */
5752 MSA128HSuperclasses,
5753 nullptr
5754 };
5755
5756 extern const TargetRegisterClass MSA128WRegClass = {
5757 &MipsMCRegisterClasses[MSA128WRegClassID],
5758 MSA128WSubClassMask,
5759 SuperRegIdxSeqs + 1,
5760 LaneBitmask(0x0000000000000041),
5761 0,
5762 false,
5763 0x00, /* TSFlags */
5764 true, /* HasDisjunctSubRegs */
5765 false, /* CoveredBySubRegs */
5766 MSA128WSuperclasses,
5767 nullptr
5768 };
5769
5770 extern const TargetRegisterClass MSA128WEvensRegClass = {
5771 &MipsMCRegisterClasses[MSA128WEvensRegClassID],
5772 MSA128WEvensSubClassMask,
5773 SuperRegIdxSeqs + 1,
5774 LaneBitmask(0x0000000000000041),
5775 0,
5776 false,
5777 0x00, /* TSFlags */
5778 true, /* HasDisjunctSubRegs */
5779 false, /* CoveredBySubRegs */
5780 MSA128WEvensSuperclasses,
5781 nullptr
5782 };
5783
5784 extern const TargetRegisterClass ACC128RegClass = {
5785 &MipsMCRegisterClasses[ACC128RegClassID],
5786 ACC128SubClassMask,
5787 SuperRegIdxSeqs + 1,
5788 LaneBitmask(0x0000000000000041),
5789 0,
5790 false,
5791 0x00, /* TSFlags */
5792 true, /* HasDisjunctSubRegs */
5793 true, /* CoveredBySubRegs */
5794 NullRegClasses,
5795 nullptr
5796 };
5797
5798} // end namespace Mips
5799
5800namespace {
5801 const TargetRegisterClass *const RegisterClasses[] = {
5802 &Mips::MSA128F16RegClass,
5803 &Mips::CCRRegClass,
5804 &Mips::COP0RegClass,
5805 &Mips::COP2RegClass,
5806 &Mips::COP3RegClass,
5807 &Mips::DSPRRegClass,
5808 &Mips::FGR32RegClass,
5809 &Mips::FGRCCRegClass,
5810 &Mips::GPR32RegClass,
5811 &Mips::HWRegsRegClass,
5812 &Mips::MSACtrlRegClass,
5813 &Mips::GPR32NONZERORegClass,
5814 &Mips::CPU16RegsPlusSPRegClass,
5815 &Mips::CPU16RegsRegClass,
5816 &Mips::FCCRegClass,
5817 &Mips::GPRMM16RegClass,
5818 &Mips::GPRMM16MovePRegClass,
5819 &Mips::GPRMM16ZeroRegClass,
5820 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
5821 &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
5822 &Mips::GPRMM16MovePPairSecondRegClass,
5823 &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
5824 &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5825 &Mips::HI32DSPRegClass,
5826 &Mips::LO32DSPRegClass,
5827 &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5828 &Mips::GPRMM16MovePPairFirstRegClass,
5829 &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5830 &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5831 &Mips::CPURARegRegClass,
5832 &Mips::CPUSPRegRegClass,
5833 &Mips::DSPCCRegClass,
5834 &Mips::GP32RegClass,
5835 &Mips::GPR32ZERORegClass,
5836 &Mips::HI32RegClass,
5837 &Mips::LO32RegClass,
5838 &Mips::SP32RegClass,
5839 &Mips::FGR64RegClass,
5840 &Mips::GPR64RegClass,
5841 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
5842 &Mips::AFGR64RegClass,
5843 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
5844 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
5845 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
5846 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
5847 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
5848 &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
5849 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
5850 &Mips::ACC64DSPRegClass,
5851 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
5852 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5853 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5854 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
5855 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5856 &Mips::OCTEON_MPLRegClass,
5857 &Mips::OCTEON_PRegClass,
5858 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5859 &Mips::ACC64RegClass,
5860 &Mips::GP64RegClass,
5861 &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
5862 &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
5863 &Mips::HI64RegClass,
5864 &Mips::LO64RegClass,
5865 &Mips::SP64RegClass,
5866 &Mips::MSA128BRegClass,
5867 &Mips::MSA128DRegClass,
5868 &Mips::MSA128HRegClass,
5869 &Mips::MSA128WRegClass,
5870 &Mips::MSA128WEvensRegClass,
5871 &Mips::ACC128RegClass,
5872 };
5873} // end anonymous namespace
5874
5875static const uint8_t CostPerUseTable[] = {
58760, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
5877
5878
5879static const bool InAllocatableClassTable[] = {
5880false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
5881
5882
5883static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
5884CostPerUseTable, 1, InAllocatableClassTable};
5885
5886unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
5887 static const uint8_t RowMap[11] = {
5888 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
5889 };
5890 static const uint8_t Rows[2][11] = {
5891 { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
5892 { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
5893 };
5894
5895 --IdxA; assert(IdxA < 11); (void) IdxA;
5896 --IdxB; assert(IdxB < 11);
5897 return Rows[RowMap[IdxA]][IdxB];
5898}
5899
5900 struct MaskRolOp {
5901 LaneBitmask Mask;
5902 uint8_t RotateLeft;
5903 };
5904 static const MaskRolOp LaneMaskComposeSequences[] = {
5905 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
5906 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
5907 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
5908 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
5909 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
5910 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
5911 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12
5912 };
5913 static const uint8_t CompositeSequences[] = {
5914 0, // to sub_32
5915 0, // to sub_64
5916 2, // to sub_dsp16_19
5917 4, // to sub_dsp20
5918 6, // to sub_dsp21
5919 8, // to sub_dsp22
5920 10, // to sub_dsp23
5921 12, // to sub_hi
5922 0, // to sub_lo
5923 12, // to sub_hi_then_sub_32
5924 0 // to sub_32_sub_hi_then_sub_32
5925 };
5926
5927LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5928 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5929 LaneBitmask Result;
5930 for (const MaskRolOp *Ops =
5931 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5932 Ops->Mask.any(); ++Ops) {
5933 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
5934 if (unsigned S = Ops->RotateLeft)
5935 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
5936 else
5937 Result |= LaneBitmask(M);
5938 }
5939 return Result;
5940}
5941
5942LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5943 LaneMask &= getSubRegIndexLaneMask(IdxA);
5944 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5945 LaneBitmask Result;
5946 for (const MaskRolOp *Ops =
5947 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5948 Ops->Mask.any(); ++Ops) {
5949 LaneBitmask::Type M = LaneMask.getAsInteger();
5950 if (unsigned S = Ops->RotateLeft)
5951 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
5952 else
5953 Result |= LaneBitmask(M);
5954 }
5955 return Result;
5956}
5957
5958const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5959 static const uint8_t Table[70][11] = {
5960 { // MSA128F16
5961 0, // sub_32
5962 1, // sub_64 -> MSA128F16
5963 0, // sub_dsp16_19
5964 0, // sub_dsp20
5965 0, // sub_dsp21
5966 0, // sub_dsp22
5967 0, // sub_dsp23
5968 1, // sub_hi -> MSA128F16
5969 1, // sub_lo -> MSA128F16
5970 0, // sub_hi_then_sub_32
5971 0, // sub_32_sub_hi_then_sub_32
5972 },
5973 { // CCR
5974 0, // sub_32
5975 0, // sub_64
5976 0, // sub_dsp16_19
5977 0, // sub_dsp20
5978 0, // sub_dsp21
5979 0, // sub_dsp22
5980 0, // sub_dsp23
5981 0, // sub_hi
5982 0, // sub_lo
5983 0, // sub_hi_then_sub_32
5984 0, // sub_32_sub_hi_then_sub_32
5985 },
5986 { // COP0
5987 0, // sub_32
5988 0, // sub_64
5989 0, // sub_dsp16_19
5990 0, // sub_dsp20
5991 0, // sub_dsp21
5992 0, // sub_dsp22
5993 0, // sub_dsp23
5994 0, // sub_hi
5995 0, // sub_lo
5996 0, // sub_hi_then_sub_32
5997 0, // sub_32_sub_hi_then_sub_32
5998 },
5999 { // COP2
6000 0, // sub_32
6001 0, // sub_64
6002 0, // sub_dsp16_19
6003 0, // sub_dsp20
6004 0, // sub_dsp21
6005 0, // sub_dsp22
6006 0, // sub_dsp23
6007 0, // sub_hi
6008 0, // sub_lo
6009 0, // sub_hi_then_sub_32
6010 0, // sub_32_sub_hi_then_sub_32
6011 },
6012 { // COP3
6013 0, // sub_32
6014 0, // sub_64
6015 0, // sub_dsp16_19
6016 0, // sub_dsp20
6017 0, // sub_dsp21
6018 0, // sub_dsp22
6019 0, // sub_dsp23
6020 0, // sub_hi
6021 0, // sub_lo
6022 0, // sub_hi_then_sub_32
6023 0, // sub_32_sub_hi_then_sub_32
6024 },
6025 { // DSPR
6026 0, // sub_32
6027 0, // sub_64
6028 0, // sub_dsp16_19
6029 0, // sub_dsp20
6030 0, // sub_dsp21
6031 0, // sub_dsp22
6032 0, // sub_dsp23
6033 0, // sub_hi
6034 0, // sub_lo
6035 0, // sub_hi_then_sub_32
6036 0, // sub_32_sub_hi_then_sub_32
6037 },
6038 { // FGR32
6039 0, // sub_32
6040 0, // sub_64
6041 0, // sub_dsp16_19
6042 0, // sub_dsp20
6043 0, // sub_dsp21
6044 0, // sub_dsp22
6045 0, // sub_dsp23
6046 0, // sub_hi
6047 0, // sub_lo
6048 0, // sub_hi_then_sub_32
6049 0, // sub_32_sub_hi_then_sub_32
6050 },
6051 { // FGRCC
6052 0, // sub_32
6053 0, // sub_64
6054 0, // sub_dsp16_19
6055 0, // sub_dsp20
6056 0, // sub_dsp21
6057 0, // sub_dsp22
6058 0, // sub_dsp23
6059 0, // sub_hi
6060 0, // sub_lo
6061 0, // sub_hi_then_sub_32
6062 0, // sub_32_sub_hi_then_sub_32
6063 },
6064 { // GPR32
6065 0, // sub_32
6066 0, // sub_64
6067 0, // sub_dsp16_19
6068 0, // sub_dsp20
6069 0, // sub_dsp21
6070 0, // sub_dsp22
6071 0, // sub_dsp23
6072 0, // sub_hi
6073 0, // sub_lo
6074 0, // sub_hi_then_sub_32
6075 0, // sub_32_sub_hi_then_sub_32
6076 },
6077 { // HWRegs
6078 0, // sub_32
6079 0, // sub_64
6080 0, // sub_dsp16_19
6081 0, // sub_dsp20
6082 0, // sub_dsp21
6083 0, // sub_dsp22
6084 0, // sub_dsp23
6085 0, // sub_hi
6086 0, // sub_lo
6087 0, // sub_hi_then_sub_32
6088 0, // sub_32_sub_hi_then_sub_32
6089 },
6090 { // MSACtrl
6091 0, // sub_32
6092 0, // sub_64
6093 0, // sub_dsp16_19
6094 0, // sub_dsp20
6095 0, // sub_dsp21
6096 0, // sub_dsp22
6097 0, // sub_dsp23
6098 0, // sub_hi
6099 0, // sub_lo
6100 0, // sub_hi_then_sub_32
6101 0, // sub_32_sub_hi_then_sub_32
6102 },
6103 { // GPR32NONZERO
6104 0, // sub_32
6105 0, // sub_64
6106 0, // sub_dsp16_19
6107 0, // sub_dsp20
6108 0, // sub_dsp21
6109 0, // sub_dsp22
6110 0, // sub_dsp23
6111 0, // sub_hi
6112 0, // sub_lo
6113 0, // sub_hi_then_sub_32
6114 0, // sub_32_sub_hi_then_sub_32
6115 },
6116 { // CPU16RegsPlusSP
6117 0, // sub_32
6118 0, // sub_64
6119 0, // sub_dsp16_19
6120 0, // sub_dsp20
6121 0, // sub_dsp21
6122 0, // sub_dsp22
6123 0, // sub_dsp23
6124 0, // sub_hi
6125 0, // sub_lo
6126 0, // sub_hi_then_sub_32
6127 0, // sub_32_sub_hi_then_sub_32
6128 },
6129 { // CPU16Regs
6130 0, // sub_32
6131 0, // sub_64
6132 0, // sub_dsp16_19
6133 0, // sub_dsp20
6134 0, // sub_dsp21
6135 0, // sub_dsp22
6136 0, // sub_dsp23
6137 0, // sub_hi
6138 0, // sub_lo
6139 0, // sub_hi_then_sub_32
6140 0, // sub_32_sub_hi_then_sub_32
6141 },
6142 { // FCC
6143 0, // sub_32
6144 0, // sub_64
6145 0, // sub_dsp16_19
6146 0, // sub_dsp20
6147 0, // sub_dsp21
6148 0, // sub_dsp22
6149 0, // sub_dsp23
6150 0, // sub_hi
6151 0, // sub_lo
6152 0, // sub_hi_then_sub_32
6153 0, // sub_32_sub_hi_then_sub_32
6154 },
6155 { // GPRMM16
6156 0, // sub_32
6157 0, // sub_64
6158 0, // sub_dsp16_19
6159 0, // sub_dsp20
6160 0, // sub_dsp21
6161 0, // sub_dsp22
6162 0, // sub_dsp23
6163 0, // sub_hi
6164 0, // sub_lo
6165 0, // sub_hi_then_sub_32
6166 0, // sub_32_sub_hi_then_sub_32
6167 },
6168 { // GPRMM16MoveP
6169 0, // sub_32
6170 0, // sub_64
6171 0, // sub_dsp16_19
6172 0, // sub_dsp20
6173 0, // sub_dsp21
6174 0, // sub_dsp22
6175 0, // sub_dsp23
6176 0, // sub_hi
6177 0, // sub_lo
6178 0, // sub_hi_then_sub_32
6179 0, // sub_32_sub_hi_then_sub_32
6180 },
6181 { // GPRMM16Zero
6182 0, // sub_32
6183 0, // sub_64
6184 0, // sub_dsp16_19
6185 0, // sub_dsp20
6186 0, // sub_dsp21
6187 0, // sub_dsp22
6188 0, // sub_dsp23
6189 0, // sub_hi
6190 0, // sub_lo
6191 0, // sub_hi_then_sub_32
6192 0, // sub_32_sub_hi_then_sub_32
6193 },
6194 { // CPU16Regs_and_GPRMM16Zero
6195 0, // sub_32
6196 0, // sub_64
6197 0, // sub_dsp16_19
6198 0, // sub_dsp20
6199 0, // sub_dsp21
6200 0, // sub_dsp22
6201 0, // sub_dsp23
6202 0, // sub_hi
6203 0, // sub_lo
6204 0, // sub_hi_then_sub_32
6205 0, // sub_32_sub_hi_then_sub_32
6206 },
6207 { // GPR32NONZERO_and_GPRMM16MoveP
6208 0, // sub_32
6209 0, // sub_64
6210 0, // sub_dsp16_19
6211 0, // sub_dsp20
6212 0, // sub_dsp21
6213 0, // sub_dsp22
6214 0, // sub_dsp23
6215 0, // sub_hi
6216 0, // sub_lo
6217 0, // sub_hi_then_sub_32
6218 0, // sub_32_sub_hi_then_sub_32
6219 },
6220 { // GPRMM16MovePPairSecond
6221 0, // sub_32
6222 0, // sub_64
6223 0, // sub_dsp16_19
6224 0, // sub_dsp20
6225 0, // sub_dsp21
6226 0, // sub_dsp22
6227 0, // sub_dsp23
6228 0, // sub_hi
6229 0, // sub_lo
6230 0, // sub_hi_then_sub_32
6231 0, // sub_32_sub_hi_then_sub_32
6232 },
6233 { // CPU16Regs_and_GPRMM16MoveP
6234 0, // sub_32
6235 0, // sub_64
6236 0, // sub_dsp16_19
6237 0, // sub_dsp20
6238 0, // sub_dsp21
6239 0, // sub_dsp22
6240 0, // sub_dsp23
6241 0, // sub_hi
6242 0, // sub_lo
6243 0, // sub_hi_then_sub_32
6244 0, // sub_32_sub_hi_then_sub_32
6245 },
6246 { // GPRMM16MoveP_and_GPRMM16Zero
6247 0, // sub_32
6248 0, // sub_64
6249 0, // sub_dsp16_19
6250 0, // sub_dsp20
6251 0, // sub_dsp21
6252 0, // sub_dsp22
6253 0, // sub_dsp23
6254 0, // sub_hi
6255 0, // sub_lo
6256 0, // sub_hi_then_sub_32
6257 0, // sub_32_sub_hi_then_sub_32
6258 },
6259 { // HI32DSP
6260 0, // sub_32
6261 0, // sub_64
6262 0, // sub_dsp16_19
6263 0, // sub_dsp20
6264 0, // sub_dsp21
6265 0, // sub_dsp22
6266 0, // sub_dsp23
6267 0, // sub_hi
6268 0, // sub_lo
6269 0, // sub_hi_then_sub_32
6270 0, // sub_32_sub_hi_then_sub_32
6271 },
6272 { // LO32DSP
6273 0, // sub_32
6274 0, // sub_64
6275 0, // sub_dsp16_19
6276 0, // sub_dsp20
6277 0, // sub_dsp21
6278 0, // sub_dsp22
6279 0, // sub_dsp23
6280 0, // sub_hi
6281 0, // sub_lo
6282 0, // sub_hi_then_sub_32
6283 0, // sub_32_sub_hi_then_sub_32
6284 },
6285 { // CPU16Regs_and_GPRMM16MovePPairSecond
6286 0, // sub_32
6287 0, // sub_64
6288 0, // sub_dsp16_19
6289 0, // sub_dsp20
6290 0, // sub_dsp21
6291 0, // sub_dsp22
6292 0, // sub_dsp23
6293 0, // sub_hi
6294 0, // sub_lo
6295 0, // sub_hi_then_sub_32
6296 0, // sub_32_sub_hi_then_sub_32
6297 },
6298 { // GPRMM16MovePPairFirst
6299 0, // sub_32
6300 0, // sub_64
6301 0, // sub_dsp16_19
6302 0, // sub_dsp20
6303 0, // sub_dsp21
6304 0, // sub_dsp22
6305 0, // sub_dsp23
6306 0, // sub_hi
6307 0, // sub_lo
6308 0, // sub_hi_then_sub_32
6309 0, // sub_32_sub_hi_then_sub_32
6310 },
6311 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6312 0, // sub_32
6313 0, // sub_64
6314 0, // sub_dsp16_19
6315 0, // sub_dsp20
6316 0, // sub_dsp21
6317 0, // sub_dsp22
6318 0, // sub_dsp23
6319 0, // sub_hi
6320 0, // sub_lo
6321 0, // sub_hi_then_sub_32
6322 0, // sub_32_sub_hi_then_sub_32
6323 },
6324 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6325 0, // sub_32
6326 0, // sub_64
6327 0, // sub_dsp16_19
6328 0, // sub_dsp20
6329 0, // sub_dsp21
6330 0, // sub_dsp22
6331 0, // sub_dsp23
6332 0, // sub_hi
6333 0, // sub_lo
6334 0, // sub_hi_then_sub_32
6335 0, // sub_32_sub_hi_then_sub_32
6336 },
6337 { // CPURAReg
6338 0, // sub_32
6339 0, // sub_64
6340 0, // sub_dsp16_19
6341 0, // sub_dsp20
6342 0, // sub_dsp21
6343 0, // sub_dsp22
6344 0, // sub_dsp23
6345 0, // sub_hi
6346 0, // sub_lo
6347 0, // sub_hi_then_sub_32
6348 0, // sub_32_sub_hi_then_sub_32
6349 },
6350 { // CPUSPReg
6351 0, // sub_32
6352 0, // sub_64
6353 0, // sub_dsp16_19
6354 0, // sub_dsp20
6355 0, // sub_dsp21
6356 0, // sub_dsp22
6357 0, // sub_dsp23
6358 0, // sub_hi
6359 0, // sub_lo
6360 0, // sub_hi_then_sub_32
6361 0, // sub_32_sub_hi_then_sub_32
6362 },
6363 { // DSPCC
6364 0, // sub_32
6365 0, // sub_64
6366 0, // sub_dsp16_19
6367 0, // sub_dsp20
6368 0, // sub_dsp21
6369 0, // sub_dsp22
6370 0, // sub_dsp23
6371 0, // sub_hi
6372 0, // sub_lo
6373 0, // sub_hi_then_sub_32
6374 0, // sub_32_sub_hi_then_sub_32
6375 },
6376 { // GP32
6377 0, // sub_32
6378 0, // sub_64
6379 0, // sub_dsp16_19
6380 0, // sub_dsp20
6381 0, // sub_dsp21
6382 0, // sub_dsp22
6383 0, // sub_dsp23
6384 0, // sub_hi
6385 0, // sub_lo
6386 0, // sub_hi_then_sub_32
6387 0, // sub_32_sub_hi_then_sub_32
6388 },
6389 { // GPR32ZERO
6390 0, // sub_32
6391 0, // sub_64
6392 0, // sub_dsp16_19
6393 0, // sub_dsp20
6394 0, // sub_dsp21
6395 0, // sub_dsp22
6396 0, // sub_dsp23
6397 0, // sub_hi
6398 0, // sub_lo
6399 0, // sub_hi_then_sub_32
6400 0, // sub_32_sub_hi_then_sub_32
6401 },
6402 { // HI32
6403 0, // sub_32
6404 0, // sub_64
6405 0, // sub_dsp16_19
6406 0, // sub_dsp20
6407 0, // sub_dsp21
6408 0, // sub_dsp22
6409 0, // sub_dsp23
6410 0, // sub_hi
6411 0, // sub_lo
6412 0, // sub_hi_then_sub_32
6413 0, // sub_32_sub_hi_then_sub_32
6414 },
6415 { // LO32
6416 0, // sub_32
6417 0, // sub_64
6418 0, // sub_dsp16_19
6419 0, // sub_dsp20
6420 0, // sub_dsp21
6421 0, // sub_dsp22
6422 0, // sub_dsp23
6423 0, // sub_hi
6424 0, // sub_lo
6425 0, // sub_hi_then_sub_32
6426 0, // sub_32_sub_hi_then_sub_32
6427 },
6428 { // SP32
6429 0, // sub_32
6430 0, // sub_64
6431 0, // sub_dsp16_19
6432 0, // sub_dsp20
6433 0, // sub_dsp21
6434 0, // sub_dsp22
6435 0, // sub_dsp23
6436 0, // sub_hi
6437 0, // sub_lo
6438 0, // sub_hi_then_sub_32
6439 0, // sub_32_sub_hi_then_sub_32
6440 },
6441 { // FGR64
6442 0, // sub_32
6443 0, // sub_64
6444 0, // sub_dsp16_19
6445 0, // sub_dsp20
6446 0, // sub_dsp21
6447 0, // sub_dsp22
6448 0, // sub_dsp23
6449 38, // sub_hi -> FGR64
6450 38, // sub_lo -> FGR64
6451 0, // sub_hi_then_sub_32
6452 0, // sub_32_sub_hi_then_sub_32
6453 },
6454 { // GPR64
6455 39, // sub_32 -> GPR64
6456 0, // sub_64
6457 0, // sub_dsp16_19
6458 0, // sub_dsp20
6459 0, // sub_dsp21
6460 0, // sub_dsp22
6461 0, // sub_dsp23
6462 0, // sub_hi
6463 0, // sub_lo
6464 0, // sub_hi_then_sub_32
6465 0, // sub_32_sub_hi_then_sub_32
6466 },
6467 { // GPR64_with_sub_32_in_GPR32NONZERO
6468 40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
6469 0, // sub_64
6470 0, // sub_dsp16_19
6471 0, // sub_dsp20
6472 0, // sub_dsp21
6473 0, // sub_dsp22
6474 0, // sub_dsp23
6475 0, // sub_hi
6476 0, // sub_lo
6477 0, // sub_hi_then_sub_32
6478 0, // sub_32_sub_hi_then_sub_32
6479 },
6480 { // AFGR64
6481 0, // sub_32
6482 0, // sub_64
6483 0, // sub_dsp16_19
6484 0, // sub_dsp20
6485 0, // sub_dsp21
6486 0, // sub_dsp22
6487 0, // sub_dsp23
6488 41, // sub_hi -> AFGR64
6489 41, // sub_lo -> AFGR64
6490 0, // sub_hi_then_sub_32
6491 0, // sub_32_sub_hi_then_sub_32
6492 },
6493 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
6494 42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
6495 0, // sub_64
6496 0, // sub_dsp16_19
6497 0, // sub_dsp20
6498 0, // sub_dsp21
6499 0, // sub_dsp22
6500 0, // sub_dsp23
6501 0, // sub_hi
6502 0, // sub_lo
6503 0, // sub_hi_then_sub_32
6504 0, // sub_32_sub_hi_then_sub_32
6505 },
6506 { // GPR64_with_sub_32_in_CPU16Regs
6507 43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
6508 0, // sub_64
6509 0, // sub_dsp16_19
6510 0, // sub_dsp20
6511 0, // sub_dsp21
6512 0, // sub_dsp22
6513 0, // sub_dsp23
6514 0, // sub_hi
6515 0, // sub_lo
6516 0, // sub_hi_then_sub_32
6517 0, // sub_32_sub_hi_then_sub_32
6518 },
6519 { // GPR64_with_sub_32_in_GPRMM16MoveP
6520 44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
6521 0, // sub_64
6522 0, // sub_dsp16_19
6523 0, // sub_dsp20
6524 0, // sub_dsp21
6525 0, // sub_dsp22
6526 0, // sub_dsp23
6527 0, // sub_hi
6528 0, // sub_lo
6529 0, // sub_hi_then_sub_32
6530 0, // sub_32_sub_hi_then_sub_32
6531 },
6532 { // GPR64_with_sub_32_in_GPRMM16Zero
6533 45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
6534 0, // sub_64
6535 0, // sub_dsp16_19
6536 0, // sub_dsp20
6537 0, // sub_dsp21
6538 0, // sub_dsp22
6539 0, // sub_dsp23
6540 0, // sub_hi
6541 0, // sub_lo
6542 0, // sub_hi_then_sub_32
6543 0, // sub_32_sub_hi_then_sub_32
6544 },
6545 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6546 46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6547 0, // sub_64
6548 0, // sub_dsp16_19
6549 0, // sub_dsp20
6550 0, // sub_dsp21
6551 0, // sub_dsp22
6552 0, // sub_dsp23
6553 0, // sub_hi
6554 0, // sub_lo
6555 0, // sub_hi_then_sub_32
6556 0, // sub_32_sub_hi_then_sub_32
6557 },
6558 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6559 47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6560 0, // sub_64
6561 0, // sub_dsp16_19
6562 0, // sub_dsp20
6563 0, // sub_dsp21
6564 0, // sub_dsp22
6565 0, // sub_dsp23
6566 0, // sub_hi
6567 0, // sub_lo
6568 0, // sub_hi_then_sub_32
6569 0, // sub_32_sub_hi_then_sub_32
6570 },
6571 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6572 48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6573 0, // sub_64
6574 0, // sub_dsp16_19
6575 0, // sub_dsp20
6576 0, // sub_dsp21
6577 0, // sub_dsp22
6578 0, // sub_dsp23
6579 0, // sub_hi
6580 0, // sub_lo
6581 0, // sub_hi_then_sub_32
6582 0, // sub_32_sub_hi_then_sub_32
6583 },
6584 { // ACC64DSP
6585 0, // sub_32
6586 0, // sub_64
6587 0, // sub_dsp16_19
6588 0, // sub_dsp20
6589 0, // sub_dsp21
6590 0, // sub_dsp22
6591 0, // sub_dsp23
6592 49, // sub_hi -> ACC64DSP
6593 49, // sub_lo -> ACC64DSP
6594 0, // sub_hi_then_sub_32
6595 0, // sub_32_sub_hi_then_sub_32
6596 },
6597 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6598 50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6599 0, // sub_64
6600 0, // sub_dsp16_19
6601 0, // sub_dsp20
6602 0, // sub_dsp21
6603 0, // sub_dsp22
6604 0, // sub_dsp23
6605 0, // sub_hi
6606 0, // sub_lo
6607 0, // sub_hi_then_sub_32
6608 0, // sub_32_sub_hi_then_sub_32
6609 },
6610 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6611 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6612 0, // sub_64
6613 0, // sub_dsp16_19
6614 0, // sub_dsp20
6615 0, // sub_dsp21
6616 0, // sub_dsp22
6617 0, // sub_dsp23
6618 0, // sub_hi
6619 0, // sub_lo
6620 0, // sub_hi_then_sub_32
6621 0, // sub_32_sub_hi_then_sub_32
6622 },
6623 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6624 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6625 0, // sub_64
6626 0, // sub_dsp16_19
6627 0, // sub_dsp20
6628 0, // sub_dsp21
6629 0, // sub_dsp22
6630 0, // sub_dsp23
6631 0, // sub_hi
6632 0, // sub_lo
6633 0, // sub_hi_then_sub_32
6634 0, // sub_32_sub_hi_then_sub_32
6635 },
6636 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6637 53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6638 0, // sub_64
6639 0, // sub_dsp16_19
6640 0, // sub_dsp20
6641 0, // sub_dsp21
6642 0, // sub_dsp22
6643 0, // sub_dsp23
6644 0, // sub_hi
6645 0, // sub_lo
6646 0, // sub_hi_then_sub_32
6647 0, // sub_32_sub_hi_then_sub_32
6648 },
6649 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6650 54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6651 0, // sub_64
6652 0, // sub_dsp16_19
6653 0, // sub_dsp20
6654 0, // sub_dsp21
6655 0, // sub_dsp22
6656 0, // sub_dsp23
6657 0, // sub_hi
6658 0, // sub_lo
6659 0, // sub_hi_then_sub_32
6660 0, // sub_32_sub_hi_then_sub_32
6661 },
6662 { // OCTEON_MPL
6663 0, // sub_32
6664 0, // sub_64
6665 0, // sub_dsp16_19
6666 0, // sub_dsp20
6667 0, // sub_dsp21
6668 0, // sub_dsp22
6669 0, // sub_dsp23
6670 0, // sub_hi
6671 0, // sub_lo
6672 0, // sub_hi_then_sub_32
6673 0, // sub_32_sub_hi_then_sub_32
6674 },
6675 { // OCTEON_P
6676 0, // sub_32
6677 0, // sub_64
6678 0, // sub_dsp16_19
6679 0, // sub_dsp20
6680 0, // sub_dsp21
6681 0, // sub_dsp22
6682 0, // sub_dsp23
6683 0, // sub_hi
6684 0, // sub_lo
6685 0, // sub_hi_then_sub_32
6686 0, // sub_32_sub_hi_then_sub_32
6687 },
6688 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6689 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6690 0, // sub_64
6691 0, // sub_dsp16_19
6692 0, // sub_dsp20
6693 0, // sub_dsp21
6694 0, // sub_dsp22
6695 0, // sub_dsp23
6696 0, // sub_hi
6697 0, // sub_lo
6698 0, // sub_hi_then_sub_32
6699 0, // sub_32_sub_hi_then_sub_32
6700 },
6701 { // ACC64
6702 0, // sub_32
6703 0, // sub_64
6704 0, // sub_dsp16_19
6705 0, // sub_dsp20
6706 0, // sub_dsp21
6707 0, // sub_dsp22
6708 0, // sub_dsp23
6709 58, // sub_hi -> ACC64
6710 58, // sub_lo -> ACC64
6711 0, // sub_hi_then_sub_32
6712 0, // sub_32_sub_hi_then_sub_32
6713 },
6714 { // GP64
6715 59, // sub_32 -> GP64
6716 0, // sub_64
6717 0, // sub_dsp16_19
6718 0, // sub_dsp20
6719 0, // sub_dsp21
6720 0, // sub_dsp22
6721 0, // sub_dsp23
6722 0, // sub_hi
6723 0, // sub_lo
6724 0, // sub_hi_then_sub_32
6725 0, // sub_32_sub_hi_then_sub_32
6726 },
6727 { // GPR64_with_sub_32_in_CPURAReg
6728 60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
6729 0, // sub_64
6730 0, // sub_dsp16_19
6731 0, // sub_dsp20
6732 0, // sub_dsp21
6733 0, // sub_dsp22
6734 0, // sub_dsp23
6735 0, // sub_hi
6736 0, // sub_lo
6737 0, // sub_hi_then_sub_32
6738 0, // sub_32_sub_hi_then_sub_32
6739 },
6740 { // GPR64_with_sub_32_in_GPR32ZERO
6741 61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
6742 0, // sub_64
6743 0, // sub_dsp16_19
6744 0, // sub_dsp20
6745 0, // sub_dsp21
6746 0, // sub_dsp22
6747 0, // sub_dsp23
6748 0, // sub_hi
6749 0, // sub_lo
6750 0, // sub_hi_then_sub_32
6751 0, // sub_32_sub_hi_then_sub_32
6752 },
6753 { // HI64
6754 62, // sub_32 -> HI64
6755 0, // sub_64
6756 0, // sub_dsp16_19
6757 0, // sub_dsp20
6758 0, // sub_dsp21
6759 0, // sub_dsp22
6760 0, // sub_dsp23
6761 0, // sub_hi
6762 0, // sub_lo
6763 0, // sub_hi_then_sub_32
6764 0, // sub_32_sub_hi_then_sub_32
6765 },
6766 { // LO64
6767 63, // sub_32 -> LO64
6768 0, // sub_64
6769 0, // sub_dsp16_19
6770 0, // sub_dsp20
6771 0, // sub_dsp21
6772 0, // sub_dsp22
6773 0, // sub_dsp23
6774 0, // sub_hi
6775 0, // sub_lo
6776 0, // sub_hi_then_sub_32
6777 0, // sub_32_sub_hi_then_sub_32
6778 },
6779 { // SP64
6780 64, // sub_32 -> SP64
6781 0, // sub_64
6782 0, // sub_dsp16_19
6783 0, // sub_dsp20
6784 0, // sub_dsp21
6785 0, // sub_dsp22
6786 0, // sub_dsp23
6787 0, // sub_hi
6788 0, // sub_lo
6789 0, // sub_hi_then_sub_32
6790 0, // sub_32_sub_hi_then_sub_32
6791 },
6792 { // MSA128B
6793 0, // sub_32
6794 65, // sub_64 -> MSA128B
6795 0, // sub_dsp16_19
6796 0, // sub_dsp20
6797 0, // sub_dsp21
6798 0, // sub_dsp22
6799 0, // sub_dsp23
6800 65, // sub_hi -> MSA128B
6801 65, // sub_lo -> MSA128B
6802 0, // sub_hi_then_sub_32
6803 0, // sub_32_sub_hi_then_sub_32
6804 },
6805 { // MSA128D
6806 0, // sub_32
6807 66, // sub_64 -> MSA128D
6808 0, // sub_dsp16_19
6809 0, // sub_dsp20
6810 0, // sub_dsp21
6811 0, // sub_dsp22
6812 0, // sub_dsp23
6813 66, // sub_hi -> MSA128D
6814 66, // sub_lo -> MSA128D
6815 0, // sub_hi_then_sub_32
6816 0, // sub_32_sub_hi_then_sub_32
6817 },
6818 { // MSA128H
6819 0, // sub_32
6820 67, // sub_64 -> MSA128H
6821 0, // sub_dsp16_19
6822 0, // sub_dsp20
6823 0, // sub_dsp21
6824 0, // sub_dsp22
6825 0, // sub_dsp23
6826 67, // sub_hi -> MSA128H
6827 67, // sub_lo -> MSA128H
6828 0, // sub_hi_then_sub_32
6829 0, // sub_32_sub_hi_then_sub_32
6830 },
6831 { // MSA128W
6832 0, // sub_32
6833 68, // sub_64 -> MSA128W
6834 0, // sub_dsp16_19
6835 0, // sub_dsp20
6836 0, // sub_dsp21
6837 0, // sub_dsp22
6838 0, // sub_dsp23
6839 68, // sub_hi -> MSA128W
6840 68, // sub_lo -> MSA128W
6841 0, // sub_hi_then_sub_32
6842 0, // sub_32_sub_hi_then_sub_32
6843 },
6844 { // MSA128WEvens
6845 0, // sub_32
6846 69, // sub_64 -> MSA128WEvens
6847 0, // sub_dsp16_19
6848 0, // sub_dsp20
6849 0, // sub_dsp21
6850 0, // sub_dsp22
6851 0, // sub_dsp23
6852 69, // sub_hi -> MSA128WEvens
6853 69, // sub_lo -> MSA128WEvens
6854 0, // sub_hi_then_sub_32
6855 0, // sub_32_sub_hi_then_sub_32
6856 },
6857 { // ACC128
6858 70, // sub_32 -> ACC128
6859 0, // sub_64
6860 0, // sub_dsp16_19
6861 0, // sub_dsp20
6862 0, // sub_dsp21
6863 0, // sub_dsp22
6864 0, // sub_dsp23
6865 70, // sub_hi -> ACC128
6866 70, // sub_lo -> ACC128
6867 70, // sub_hi_then_sub_32 -> ACC128
6868 70, // sub_32_sub_hi_then_sub_32 -> ACC128
6869 },
6870 };
6871 assert(RC && "Missing regclass");
6872 if (!Idx) return RC;
6873 --Idx;
6874 assert(Idx < 11 && "Bad subreg");
6875 unsigned TV = Table[RC->getID()][Idx];
6876 return TV ? getRegClass(TV - 1) : nullptr;
6877}
6878
6879const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
6880 static const uint8_t Table[70][11] = {
6881 { // MSA128F16
6882 0, // MSA128F16:sub_32
6883 38, // MSA128F16:sub_64 -> FGR64
6884 0, // MSA128F16:sub_dsp16_19
6885 0, // MSA128F16:sub_dsp20
6886 0, // MSA128F16:sub_dsp21
6887 0, // MSA128F16:sub_dsp22
6888 0, // MSA128F16:sub_dsp23
6889 0, // MSA128F16:sub_hi
6890 7, // MSA128F16:sub_lo -> FGR32
6891 0, // MSA128F16:sub_hi_then_sub_32
6892 0, // MSA128F16:sub_32_sub_hi_then_sub_32
6893 },
6894 { // CCR
6895 0, // CCR:sub_32
6896 0, // CCR:sub_64
6897 0, // CCR:sub_dsp16_19
6898 0, // CCR:sub_dsp20
6899 0, // CCR:sub_dsp21
6900 0, // CCR:sub_dsp22
6901 0, // CCR:sub_dsp23
6902 0, // CCR:sub_hi
6903 0, // CCR:sub_lo
6904 0, // CCR:sub_hi_then_sub_32
6905 0, // CCR:sub_32_sub_hi_then_sub_32
6906 },
6907 { // COP0
6908 0, // COP0:sub_32
6909 0, // COP0:sub_64
6910 0, // COP0:sub_dsp16_19
6911 0, // COP0:sub_dsp20
6912 0, // COP0:sub_dsp21
6913 0, // COP0:sub_dsp22
6914 0, // COP0:sub_dsp23
6915 0, // COP0:sub_hi
6916 0, // COP0:sub_lo
6917 0, // COP0:sub_hi_then_sub_32
6918 0, // COP0:sub_32_sub_hi_then_sub_32
6919 },
6920 { // COP2
6921 0, // COP2:sub_32
6922 0, // COP2:sub_64
6923 0, // COP2:sub_dsp16_19
6924 0, // COP2:sub_dsp20
6925 0, // COP2:sub_dsp21
6926 0, // COP2:sub_dsp22
6927 0, // COP2:sub_dsp23
6928 0, // COP2:sub_hi
6929 0, // COP2:sub_lo
6930 0, // COP2:sub_hi_then_sub_32
6931 0, // COP2:sub_32_sub_hi_then_sub_32
6932 },
6933 { // COP3
6934 0, // COP3:sub_32
6935 0, // COP3:sub_64
6936 0, // COP3:sub_dsp16_19
6937 0, // COP3:sub_dsp20
6938 0, // COP3:sub_dsp21
6939 0, // COP3:sub_dsp22
6940 0, // COP3:sub_dsp23
6941 0, // COP3:sub_hi
6942 0, // COP3:sub_lo
6943 0, // COP3:sub_hi_then_sub_32
6944 0, // COP3:sub_32_sub_hi_then_sub_32
6945 },
6946 { // DSPR
6947 0, // DSPR:sub_32
6948 0, // DSPR:sub_64
6949 0, // DSPR:sub_dsp16_19
6950 0, // DSPR:sub_dsp20
6951 0, // DSPR:sub_dsp21
6952 0, // DSPR:sub_dsp22
6953 0, // DSPR:sub_dsp23
6954 0, // DSPR:sub_hi
6955 0, // DSPR:sub_lo
6956 0, // DSPR:sub_hi_then_sub_32
6957 0, // DSPR:sub_32_sub_hi_then_sub_32
6958 },
6959 { // FGR32
6960 0, // FGR32:sub_32
6961 0, // FGR32:sub_64
6962 0, // FGR32:sub_dsp16_19
6963 0, // FGR32:sub_dsp20
6964 0, // FGR32:sub_dsp21
6965 0, // FGR32:sub_dsp22
6966 0, // FGR32:sub_dsp23
6967 0, // FGR32:sub_hi
6968 0, // FGR32:sub_lo
6969 0, // FGR32:sub_hi_then_sub_32
6970 0, // FGR32:sub_32_sub_hi_then_sub_32
6971 },
6972 { // FGRCC
6973 0, // FGRCC:sub_32
6974 0, // FGRCC:sub_64
6975 0, // FGRCC:sub_dsp16_19
6976 0, // FGRCC:sub_dsp20
6977 0, // FGRCC:sub_dsp21
6978 0, // FGRCC:sub_dsp22
6979 0, // FGRCC:sub_dsp23
6980 0, // FGRCC:sub_hi
6981 0, // FGRCC:sub_lo
6982 0, // FGRCC:sub_hi_then_sub_32
6983 0, // FGRCC:sub_32_sub_hi_then_sub_32
6984 },
6985 { // GPR32
6986 0, // GPR32:sub_32
6987 0, // GPR32:sub_64
6988 0, // GPR32:sub_dsp16_19
6989 0, // GPR32:sub_dsp20
6990 0, // GPR32:sub_dsp21
6991 0, // GPR32:sub_dsp22
6992 0, // GPR32:sub_dsp23
6993 0, // GPR32:sub_hi
6994 0, // GPR32:sub_lo
6995 0, // GPR32:sub_hi_then_sub_32
6996 0, // GPR32:sub_32_sub_hi_then_sub_32
6997 },
6998 { // HWRegs
6999 0, // HWRegs:sub_32
7000 0, // HWRegs:sub_64
7001 0, // HWRegs:sub_dsp16_19
7002 0, // HWRegs:sub_dsp20
7003 0, // HWRegs:sub_dsp21
7004 0, // HWRegs:sub_dsp22
7005 0, // HWRegs:sub_dsp23
7006 0, // HWRegs:sub_hi
7007 0, // HWRegs:sub_lo
7008 0, // HWRegs:sub_hi_then_sub_32
7009 0, // HWRegs:sub_32_sub_hi_then_sub_32
7010 },
7011 { // MSACtrl
7012 0, // MSACtrl:sub_32
7013 0, // MSACtrl:sub_64
7014 0, // MSACtrl:sub_dsp16_19
7015 0, // MSACtrl:sub_dsp20
7016 0, // MSACtrl:sub_dsp21
7017 0, // MSACtrl:sub_dsp22
7018 0, // MSACtrl:sub_dsp23
7019 0, // MSACtrl:sub_hi
7020 0, // MSACtrl:sub_lo
7021 0, // MSACtrl:sub_hi_then_sub_32
7022 0, // MSACtrl:sub_32_sub_hi_then_sub_32
7023 },
7024 { // GPR32NONZERO
7025 0, // GPR32NONZERO:sub_32
7026 0, // GPR32NONZERO:sub_64
7027 0, // GPR32NONZERO:sub_dsp16_19
7028 0, // GPR32NONZERO:sub_dsp20
7029 0, // GPR32NONZERO:sub_dsp21
7030 0, // GPR32NONZERO:sub_dsp22
7031 0, // GPR32NONZERO:sub_dsp23
7032 0, // GPR32NONZERO:sub_hi
7033 0, // GPR32NONZERO:sub_lo
7034 0, // GPR32NONZERO:sub_hi_then_sub_32
7035 0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
7036 },
7037 { // CPU16RegsPlusSP
7038 0, // CPU16RegsPlusSP:sub_32
7039 0, // CPU16RegsPlusSP:sub_64
7040 0, // CPU16RegsPlusSP:sub_dsp16_19
7041 0, // CPU16RegsPlusSP:sub_dsp20
7042 0, // CPU16RegsPlusSP:sub_dsp21
7043 0, // CPU16RegsPlusSP:sub_dsp22
7044 0, // CPU16RegsPlusSP:sub_dsp23
7045 0, // CPU16RegsPlusSP:sub_hi
7046 0, // CPU16RegsPlusSP:sub_lo
7047 0, // CPU16RegsPlusSP:sub_hi_then_sub_32
7048 0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7049 },
7050 { // CPU16Regs
7051 0, // CPU16Regs:sub_32
7052 0, // CPU16Regs:sub_64
7053 0, // CPU16Regs:sub_dsp16_19
7054 0, // CPU16Regs:sub_dsp20
7055 0, // CPU16Regs:sub_dsp21
7056 0, // CPU16Regs:sub_dsp22
7057 0, // CPU16Regs:sub_dsp23
7058 0, // CPU16Regs:sub_hi
7059 0, // CPU16Regs:sub_lo
7060 0, // CPU16Regs:sub_hi_then_sub_32
7061 0, // CPU16Regs:sub_32_sub_hi_then_sub_32
7062 },
7063 { // FCC
7064 0, // FCC:sub_32
7065 0, // FCC:sub_64
7066 0, // FCC:sub_dsp16_19
7067 0, // FCC:sub_dsp20
7068 0, // FCC:sub_dsp21
7069 0, // FCC:sub_dsp22
7070 0, // FCC:sub_dsp23
7071 0, // FCC:sub_hi
7072 0, // FCC:sub_lo
7073 0, // FCC:sub_hi_then_sub_32
7074 0, // FCC:sub_32_sub_hi_then_sub_32
7075 },
7076 { // GPRMM16
7077 0, // GPRMM16:sub_32
7078 0, // GPRMM16:sub_64
7079 0, // GPRMM16:sub_dsp16_19
7080 0, // GPRMM16:sub_dsp20
7081 0, // GPRMM16:sub_dsp21
7082 0, // GPRMM16:sub_dsp22
7083 0, // GPRMM16:sub_dsp23
7084 0, // GPRMM16:sub_hi
7085 0, // GPRMM16:sub_lo
7086 0, // GPRMM16:sub_hi_then_sub_32
7087 0, // GPRMM16:sub_32_sub_hi_then_sub_32
7088 },
7089 { // GPRMM16MoveP
7090 0, // GPRMM16MoveP:sub_32
7091 0, // GPRMM16MoveP:sub_64
7092 0, // GPRMM16MoveP:sub_dsp16_19
7093 0, // GPRMM16MoveP:sub_dsp20
7094 0, // GPRMM16MoveP:sub_dsp21
7095 0, // GPRMM16MoveP:sub_dsp22
7096 0, // GPRMM16MoveP:sub_dsp23
7097 0, // GPRMM16MoveP:sub_hi
7098 0, // GPRMM16MoveP:sub_lo
7099 0, // GPRMM16MoveP:sub_hi_then_sub_32
7100 0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7101 },
7102 { // GPRMM16Zero
7103 0, // GPRMM16Zero:sub_32
7104 0, // GPRMM16Zero:sub_64
7105 0, // GPRMM16Zero:sub_dsp16_19
7106 0, // GPRMM16Zero:sub_dsp20
7107 0, // GPRMM16Zero:sub_dsp21
7108 0, // GPRMM16Zero:sub_dsp22
7109 0, // GPRMM16Zero:sub_dsp23
7110 0, // GPRMM16Zero:sub_hi
7111 0, // GPRMM16Zero:sub_lo
7112 0, // GPRMM16Zero:sub_hi_then_sub_32
7113 0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
7114 },
7115 { // CPU16Regs_and_GPRMM16Zero
7116 0, // CPU16Regs_and_GPRMM16Zero:sub_32
7117 0, // CPU16Regs_and_GPRMM16Zero:sub_64
7118 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7119 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
7120 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
7121 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
7122 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
7123 0, // CPU16Regs_and_GPRMM16Zero:sub_hi
7124 0, // CPU16Regs_and_GPRMM16Zero:sub_lo
7125 0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7126 0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7127 },
7128 { // GPR32NONZERO_and_GPRMM16MoveP
7129 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
7130 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
7131 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7132 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7133 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7134 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7135 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7136 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7137 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7138 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7139 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7140 },
7141 { // GPRMM16MovePPairSecond
7142 0, // GPRMM16MovePPairSecond:sub_32
7143 0, // GPRMM16MovePPairSecond:sub_64
7144 0, // GPRMM16MovePPairSecond:sub_dsp16_19
7145 0, // GPRMM16MovePPairSecond:sub_dsp20
7146 0, // GPRMM16MovePPairSecond:sub_dsp21
7147 0, // GPRMM16MovePPairSecond:sub_dsp22
7148 0, // GPRMM16MovePPairSecond:sub_dsp23
7149 0, // GPRMM16MovePPairSecond:sub_hi
7150 0, // GPRMM16MovePPairSecond:sub_lo
7151 0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
7152 0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7153 },
7154 { // CPU16Regs_and_GPRMM16MoveP
7155 0, // CPU16Regs_and_GPRMM16MoveP:sub_32
7156 0, // CPU16Regs_and_GPRMM16MoveP:sub_64
7157 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7158 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7159 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7160 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7161 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7162 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi
7163 0, // CPU16Regs_and_GPRMM16MoveP:sub_lo
7164 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7165 0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7166 },
7167 { // GPRMM16MoveP_and_GPRMM16Zero
7168 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
7169 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
7170 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7171 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7172 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7173 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7174 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7175 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7176 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7177 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7178 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7179 },
7180 { // HI32DSP
7181 0, // HI32DSP:sub_32
7182 0, // HI32DSP:sub_64
7183 0, // HI32DSP:sub_dsp16_19
7184 0, // HI32DSP:sub_dsp20
7185 0, // HI32DSP:sub_dsp21
7186 0, // HI32DSP:sub_dsp22
7187 0, // HI32DSP:sub_dsp23
7188 0, // HI32DSP:sub_hi
7189 0, // HI32DSP:sub_lo
7190 0, // HI32DSP:sub_hi_then_sub_32
7191 0, // HI32DSP:sub_32_sub_hi_then_sub_32
7192 },
7193 { // LO32DSP
7194 0, // LO32DSP:sub_32
7195 0, // LO32DSP:sub_64
7196 0, // LO32DSP:sub_dsp16_19
7197 0, // LO32DSP:sub_dsp20
7198 0, // LO32DSP:sub_dsp21
7199 0, // LO32DSP:sub_dsp22
7200 0, // LO32DSP:sub_dsp23
7201 0, // LO32DSP:sub_hi
7202 0, // LO32DSP:sub_lo
7203 0, // LO32DSP:sub_hi_then_sub_32
7204 0, // LO32DSP:sub_32_sub_hi_then_sub_32
7205 },
7206 { // CPU16Regs_and_GPRMM16MovePPairSecond
7207 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
7208 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7209 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7210 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7211 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7212 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7213 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7214 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7215 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7216 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7217 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7218 },
7219 { // GPRMM16MovePPairFirst
7220 0, // GPRMM16MovePPairFirst:sub_32
7221 0, // GPRMM16MovePPairFirst:sub_64
7222 0, // GPRMM16MovePPairFirst:sub_dsp16_19
7223 0, // GPRMM16MovePPairFirst:sub_dsp20
7224 0, // GPRMM16MovePPairFirst:sub_dsp21
7225 0, // GPRMM16MovePPairFirst:sub_dsp22
7226 0, // GPRMM16MovePPairFirst:sub_dsp23
7227 0, // GPRMM16MovePPairFirst:sub_hi
7228 0, // GPRMM16MovePPairFirst:sub_lo
7229 0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
7230 0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7231 },
7232 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7233 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
7234 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7235 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7236 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7237 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7238 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7239 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7240 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7241 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7242 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7243 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7244 },
7245 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7246 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
7247 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7248 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7249 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7250 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7251 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7252 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7253 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7254 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7255 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7256 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7257 },
7258 { // CPURAReg
7259 0, // CPURAReg:sub_32
7260 0, // CPURAReg:sub_64
7261 0, // CPURAReg:sub_dsp16_19
7262 0, // CPURAReg:sub_dsp20
7263 0, // CPURAReg:sub_dsp21
7264 0, // CPURAReg:sub_dsp22
7265 0, // CPURAReg:sub_dsp23
7266 0, // CPURAReg:sub_hi
7267 0, // CPURAReg:sub_lo
7268 0, // CPURAReg:sub_hi_then_sub_32
7269 0, // CPURAReg:sub_32_sub_hi_then_sub_32
7270 },
7271 { // CPUSPReg
7272 0, // CPUSPReg:sub_32
7273 0, // CPUSPReg:sub_64
7274 0, // CPUSPReg:sub_dsp16_19
7275 0, // CPUSPReg:sub_dsp20
7276 0, // CPUSPReg:sub_dsp21
7277 0, // CPUSPReg:sub_dsp22
7278 0, // CPUSPReg:sub_dsp23
7279 0, // CPUSPReg:sub_hi
7280 0, // CPUSPReg:sub_lo
7281 0, // CPUSPReg:sub_hi_then_sub_32
7282 0, // CPUSPReg:sub_32_sub_hi_then_sub_32
7283 },
7284 { // DSPCC
7285 0, // DSPCC:sub_32
7286 0, // DSPCC:sub_64
7287 0, // DSPCC:sub_dsp16_19
7288 0, // DSPCC:sub_dsp20
7289 0, // DSPCC:sub_dsp21
7290 0, // DSPCC:sub_dsp22
7291 0, // DSPCC:sub_dsp23
7292 0, // DSPCC:sub_hi
7293 0, // DSPCC:sub_lo
7294 0, // DSPCC:sub_hi_then_sub_32
7295 0, // DSPCC:sub_32_sub_hi_then_sub_32
7296 },
7297 { // GP32
7298 0, // GP32:sub_32
7299 0, // GP32:sub_64
7300 0, // GP32:sub_dsp16_19
7301 0, // GP32:sub_dsp20
7302 0, // GP32:sub_dsp21
7303 0, // GP32:sub_dsp22
7304 0, // GP32:sub_dsp23
7305 0, // GP32:sub_hi
7306 0, // GP32:sub_lo
7307 0, // GP32:sub_hi_then_sub_32
7308 0, // GP32:sub_32_sub_hi_then_sub_32
7309 },
7310 { // GPR32ZERO
7311 0, // GPR32ZERO:sub_32
7312 0, // GPR32ZERO:sub_64
7313 0, // GPR32ZERO:sub_dsp16_19
7314 0, // GPR32ZERO:sub_dsp20
7315 0, // GPR32ZERO:sub_dsp21
7316 0, // GPR32ZERO:sub_dsp22
7317 0, // GPR32ZERO:sub_dsp23
7318 0, // GPR32ZERO:sub_hi
7319 0, // GPR32ZERO:sub_lo
7320 0, // GPR32ZERO:sub_hi_then_sub_32
7321 0, // GPR32ZERO:sub_32_sub_hi_then_sub_32
7322 },
7323 { // HI32
7324 0, // HI32:sub_32
7325 0, // HI32:sub_64
7326 0, // HI32:sub_dsp16_19
7327 0, // HI32:sub_dsp20
7328 0, // HI32:sub_dsp21
7329 0, // HI32:sub_dsp22
7330 0, // HI32:sub_dsp23
7331 0, // HI32:sub_hi
7332 0, // HI32:sub_lo
7333 0, // HI32:sub_hi_then_sub_32
7334 0, // HI32:sub_32_sub_hi_then_sub_32
7335 },
7336 { // LO32
7337 0, // LO32:sub_32
7338 0, // LO32:sub_64
7339 0, // LO32:sub_dsp16_19
7340 0, // LO32:sub_dsp20
7341 0, // LO32:sub_dsp21
7342 0, // LO32:sub_dsp22
7343 0, // LO32:sub_dsp23
7344 0, // LO32:sub_hi
7345 0, // LO32:sub_lo
7346 0, // LO32:sub_hi_then_sub_32
7347 0, // LO32:sub_32_sub_hi_then_sub_32
7348 },
7349 { // SP32
7350 0, // SP32:sub_32
7351 0, // SP32:sub_64
7352 0, // SP32:sub_dsp16_19
7353 0, // SP32:sub_dsp20
7354 0, // SP32:sub_dsp21
7355 0, // SP32:sub_dsp22
7356 0, // SP32:sub_dsp23
7357 0, // SP32:sub_hi
7358 0, // SP32:sub_lo
7359 0, // SP32:sub_hi_then_sub_32
7360 0, // SP32:sub_32_sub_hi_then_sub_32
7361 },
7362 { // FGR64
7363 0, // FGR64:sub_32
7364 0, // FGR64:sub_64
7365 0, // FGR64:sub_dsp16_19
7366 0, // FGR64:sub_dsp20
7367 0, // FGR64:sub_dsp21
7368 0, // FGR64:sub_dsp22
7369 0, // FGR64:sub_dsp23
7370 0, // FGR64:sub_hi
7371 7, // FGR64:sub_lo -> FGR32
7372 0, // FGR64:sub_hi_then_sub_32
7373 0, // FGR64:sub_32_sub_hi_then_sub_32
7374 },
7375 { // GPR64
7376 6, // GPR64:sub_32 -> DSPR
7377 0, // GPR64:sub_64
7378 0, // GPR64:sub_dsp16_19
7379 0, // GPR64:sub_dsp20
7380 0, // GPR64:sub_dsp21
7381 0, // GPR64:sub_dsp22
7382 0, // GPR64:sub_dsp23
7383 0, // GPR64:sub_hi
7384 0, // GPR64:sub_lo
7385 0, // GPR64:sub_hi_then_sub_32
7386 0, // GPR64:sub_32_sub_hi_then_sub_32
7387 },
7388 { // GPR64_with_sub_32_in_GPR32NONZERO
7389 12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
7390 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
7391 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
7392 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
7393 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
7394 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
7395 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
7396 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
7397 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
7398 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
7399 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
7400 },
7401 { // AFGR64
7402 0, // AFGR64:sub_32
7403 0, // AFGR64:sub_64
7404 0, // AFGR64:sub_dsp16_19
7405 0, // AFGR64:sub_dsp20
7406 0, // AFGR64:sub_dsp21
7407 0, // AFGR64:sub_dsp22
7408 0, // AFGR64:sub_dsp23
7409 8, // AFGR64:sub_hi -> FGRCC
7410 8, // AFGR64:sub_lo -> FGRCC
7411 0, // AFGR64:sub_hi_then_sub_32
7412 0, // AFGR64:sub_32_sub_hi_then_sub_32
7413 },
7414 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
7415 13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
7416 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
7417 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
7418 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
7419 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
7420 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
7421 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
7422 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
7423 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
7424 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
7425 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7426 },
7427 { // GPR64_with_sub_32_in_CPU16Regs
7428 14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
7429 0, // GPR64_with_sub_32_in_CPU16Regs:sub_64
7430 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
7431 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
7432 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
7433 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
7434 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
7435 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
7436 0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
7437 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
7438 0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
7439 },
7440 { // GPR64_with_sub_32_in_GPRMM16MoveP
7441 17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
7442 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
7443 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
7444 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
7445 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
7446 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
7447 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
7448 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
7449 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
7450 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
7451 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7452 },
7453 { // GPR64_with_sub_32_in_GPRMM16Zero
7454 18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
7455 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
7456 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
7457 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
7458 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
7459 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
7460 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
7461 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
7462 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
7463 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
7464 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7465 },
7466 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7467 19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
7468 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
7469 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7470 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7471 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7472 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7473 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7474 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
7475 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
7476 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7477 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7478 },
7479 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7480 20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
7481 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
7482 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7483 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7484 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7485 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7486 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7487 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7488 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7489 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7490 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7491 },
7492 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7493 21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
7494 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
7495 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
7496 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
7497 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
7498 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
7499 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
7500 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
7501 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
7502 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7503 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7504 },
7505 { // ACC64DSP
7506 0, // ACC64DSP:sub_32
7507 0, // ACC64DSP:sub_64
7508 0, // ACC64DSP:sub_dsp16_19
7509 0, // ACC64DSP:sub_dsp20
7510 0, // ACC64DSP:sub_dsp21
7511 0, // ACC64DSP:sub_dsp22
7512 0, // ACC64DSP:sub_dsp23
7513 24, // ACC64DSP:sub_hi -> HI32DSP
7514 25, // ACC64DSP:sub_lo -> LO32DSP
7515 0, // ACC64DSP:sub_hi_then_sub_32
7516 0, // ACC64DSP:sub_32_sub_hi_then_sub_32
7517 },
7518 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7519 22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
7520 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
7521 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7522 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7523 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7524 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7525 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7526 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
7527 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
7528 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7529 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7530 },
7531 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7532 23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
7533 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
7534 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7535 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7536 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7537 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7538 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7539 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7540 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7541 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7542 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7543 },
7544 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7545 26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
7546 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7547 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7548 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7549 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7550 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7551 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7552 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7553 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7554 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7555 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7556 },
7557 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7558 27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
7559 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
7560 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
7561 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
7562 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
7563 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
7564 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
7565 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
7566 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
7567 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
7568 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7569 },
7570 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7571 28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7572 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7573 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7574 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7575 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7576 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7577 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7578 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7579 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7580 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7581 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7582 },
7583 { // OCTEON_MPL
7584 0, // OCTEON_MPL:sub_32
7585 0, // OCTEON_MPL:sub_64
7586 0, // OCTEON_MPL:sub_dsp16_19
7587 0, // OCTEON_MPL:sub_dsp20
7588 0, // OCTEON_MPL:sub_dsp21
7589 0, // OCTEON_MPL:sub_dsp22
7590 0, // OCTEON_MPL:sub_dsp23
7591 0, // OCTEON_MPL:sub_hi
7592 0, // OCTEON_MPL:sub_lo
7593 0, // OCTEON_MPL:sub_hi_then_sub_32
7594 0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
7595 },
7596 { // OCTEON_P
7597 0, // OCTEON_P:sub_32
7598 0, // OCTEON_P:sub_64
7599 0, // OCTEON_P:sub_dsp16_19
7600 0, // OCTEON_P:sub_dsp20
7601 0, // OCTEON_P:sub_dsp21
7602 0, // OCTEON_P:sub_dsp22
7603 0, // OCTEON_P:sub_dsp23
7604 0, // OCTEON_P:sub_hi
7605 0, // OCTEON_P:sub_lo
7606 0, // OCTEON_P:sub_hi_then_sub_32
7607 0, // OCTEON_P:sub_32_sub_hi_then_sub_32
7608 },
7609 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7610 29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7611 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7612 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7613 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7614 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7615 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7616 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7617 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7618 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7619 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7620 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7621 },
7622 { // ACC64
7623 0, // ACC64:sub_32
7624 0, // ACC64:sub_64
7625 0, // ACC64:sub_dsp16_19
7626 0, // ACC64:sub_dsp20
7627 0, // ACC64:sub_dsp21
7628 0, // ACC64:sub_dsp22
7629 0, // ACC64:sub_dsp23
7630 35, // ACC64:sub_hi -> HI32
7631 36, // ACC64:sub_lo -> LO32
7632 0, // ACC64:sub_hi_then_sub_32
7633 0, // ACC64:sub_32_sub_hi_then_sub_32
7634 },
7635 { // GP64
7636 33, // GP64:sub_32 -> GP32
7637 0, // GP64:sub_64
7638 0, // GP64:sub_dsp16_19
7639 0, // GP64:sub_dsp20
7640 0, // GP64:sub_dsp21
7641 0, // GP64:sub_dsp22
7642 0, // GP64:sub_dsp23
7643 0, // GP64:sub_hi
7644 0, // GP64:sub_lo
7645 0, // GP64:sub_hi_then_sub_32
7646 0, // GP64:sub_32_sub_hi_then_sub_32
7647 },
7648 { // GPR64_with_sub_32_in_CPURAReg
7649 30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
7650 0, // GPR64_with_sub_32_in_CPURAReg:sub_64
7651 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
7652 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
7653 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
7654 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
7655 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
7656 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi
7657 0, // GPR64_with_sub_32_in_CPURAReg:sub_lo
7658 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
7659 0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
7660 },
7661 { // GPR64_with_sub_32_in_GPR32ZERO
7662 34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
7663 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
7664 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
7665 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
7666 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
7667 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
7668 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
7669 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
7670 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
7671 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
7672 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
7673 },
7674 { // HI64
7675 35, // HI64:sub_32 -> HI32
7676 0, // HI64:sub_64
7677 0, // HI64:sub_dsp16_19
7678 0, // HI64:sub_dsp20
7679 0, // HI64:sub_dsp21
7680 0, // HI64:sub_dsp22
7681 0, // HI64:sub_dsp23
7682 0, // HI64:sub_hi
7683 0, // HI64:sub_lo
7684 0, // HI64:sub_hi_then_sub_32
7685 0, // HI64:sub_32_sub_hi_then_sub_32
7686 },
7687 { // LO64
7688 36, // LO64:sub_32 -> LO32
7689 0, // LO64:sub_64
7690 0, // LO64:sub_dsp16_19
7691 0, // LO64:sub_dsp20
7692 0, // LO64:sub_dsp21
7693 0, // LO64:sub_dsp22
7694 0, // LO64:sub_dsp23
7695 0, // LO64:sub_hi
7696 0, // LO64:sub_lo
7697 0, // LO64:sub_hi_then_sub_32
7698 0, // LO64:sub_32_sub_hi_then_sub_32
7699 },
7700 { // SP64
7701 31, // SP64:sub_32 -> CPUSPReg
7702 0, // SP64:sub_64
7703 0, // SP64:sub_dsp16_19
7704 0, // SP64:sub_dsp20
7705 0, // SP64:sub_dsp21
7706 0, // SP64:sub_dsp22
7707 0, // SP64:sub_dsp23
7708 0, // SP64:sub_hi
7709 0, // SP64:sub_lo
7710 0, // SP64:sub_hi_then_sub_32
7711 0, // SP64:sub_32_sub_hi_then_sub_32
7712 },
7713 { // MSA128B
7714 0, // MSA128B:sub_32
7715 38, // MSA128B:sub_64 -> FGR64
7716 0, // MSA128B:sub_dsp16_19
7717 0, // MSA128B:sub_dsp20
7718 0, // MSA128B:sub_dsp21
7719 0, // MSA128B:sub_dsp22
7720 0, // MSA128B:sub_dsp23
7721 0, // MSA128B:sub_hi
7722 7, // MSA128B:sub_lo -> FGR32
7723 0, // MSA128B:sub_hi_then_sub_32
7724 0, // MSA128B:sub_32_sub_hi_then_sub_32
7725 },
7726 { // MSA128D
7727 0, // MSA128D:sub_32
7728 38, // MSA128D:sub_64 -> FGR64
7729 0, // MSA128D:sub_dsp16_19
7730 0, // MSA128D:sub_dsp20
7731 0, // MSA128D:sub_dsp21
7732 0, // MSA128D:sub_dsp22
7733 0, // MSA128D:sub_dsp23
7734 0, // MSA128D:sub_hi
7735 7, // MSA128D:sub_lo -> FGR32
7736 0, // MSA128D:sub_hi_then_sub_32
7737 0, // MSA128D:sub_32_sub_hi_then_sub_32
7738 },
7739 { // MSA128H
7740 0, // MSA128H:sub_32
7741 38, // MSA128H:sub_64 -> FGR64
7742 0, // MSA128H:sub_dsp16_19
7743 0, // MSA128H:sub_dsp20
7744 0, // MSA128H:sub_dsp21
7745 0, // MSA128H:sub_dsp22
7746 0, // MSA128H:sub_dsp23
7747 0, // MSA128H:sub_hi
7748 7, // MSA128H:sub_lo -> FGR32
7749 0, // MSA128H:sub_hi_then_sub_32
7750 0, // MSA128H:sub_32_sub_hi_then_sub_32
7751 },
7752 { // MSA128W
7753 0, // MSA128W:sub_32
7754 38, // MSA128W:sub_64 -> FGR64
7755 0, // MSA128W:sub_dsp16_19
7756 0, // MSA128W:sub_dsp20
7757 0, // MSA128W:sub_dsp21
7758 0, // MSA128W:sub_dsp22
7759 0, // MSA128W:sub_dsp23
7760 0, // MSA128W:sub_hi
7761 7, // MSA128W:sub_lo -> FGR32
7762 0, // MSA128W:sub_hi_then_sub_32
7763 0, // MSA128W:sub_32_sub_hi_then_sub_32
7764 },
7765 { // MSA128WEvens
7766 0, // MSA128WEvens:sub_32
7767 38, // MSA128WEvens:sub_64 -> FGR64
7768 0, // MSA128WEvens:sub_dsp16_19
7769 0, // MSA128WEvens:sub_dsp20
7770 0, // MSA128WEvens:sub_dsp21
7771 0, // MSA128WEvens:sub_dsp22
7772 0, // MSA128WEvens:sub_dsp23
7773 0, // MSA128WEvens:sub_hi
7774 8, // MSA128WEvens:sub_lo -> FGRCC
7775 0, // MSA128WEvens:sub_hi_then_sub_32
7776 0, // MSA128WEvens:sub_32_sub_hi_then_sub_32
7777 },
7778 { // ACC128
7779 36, // ACC128:sub_32 -> LO32
7780 0, // ACC128:sub_64
7781 0, // ACC128:sub_dsp16_19
7782 0, // ACC128:sub_dsp20
7783 0, // ACC128:sub_dsp21
7784 0, // ACC128:sub_dsp22
7785 0, // ACC128:sub_dsp23
7786 62, // ACC128:sub_hi -> HI64
7787 63, // ACC128:sub_lo -> LO64
7788 35, // ACC128:sub_hi_then_sub_32 -> HI32
7789 58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
7790 },
7791 };
7792 assert(RC && "Missing regclass");
7793 if (!Idx) return RC;
7794 --Idx;
7795 assert(Idx < 11 && "Bad subreg");
7796 unsigned TV = Table[RC->getID()][Idx];
7797 return TV ? getRegClass(TV - 1) : nullptr;
7798}
7799
7800/// Get the weight in units of pressure for this register class.
7801const RegClassWeight &MipsGenRegisterInfo::
7802getRegClassWeight(const TargetRegisterClass *RC) const {
7803 static const RegClassWeight RCWeightTable[] = {
7804 {2, 64}, // MSA128F16
7805 {0, 0}, // CCR
7806 {0, 0}, // COP0
7807 {0, 0}, // COP2
7808 {0, 0}, // COP3
7809 {1, 32}, // DSPR
7810 {1, 32}, // FGR32
7811 {1, 32}, // FGRCC
7812 {1, 32}, // GPR32
7813 {0, 0}, // HWRegs
7814 {0, 0}, // MSACtrl
7815 {1, 31}, // GPR32NONZERO
7816 {1, 9}, // CPU16RegsPlusSP
7817 {1, 8}, // CPU16Regs
7818 {0, 0}, // FCC
7819 {1, 8}, // GPRMM16
7820 {1, 8}, // GPRMM16MoveP
7821 {1, 8}, // GPRMM16Zero
7822 {1, 7}, // CPU16Regs_and_GPRMM16Zero
7823 {1, 7}, // GPR32NONZERO_and_GPRMM16MoveP
7824 {1, 5}, // GPRMM16MovePPairSecond
7825 {1, 4}, // CPU16Regs_and_GPRMM16MoveP
7826 {1, 4}, // GPRMM16MoveP_and_GPRMM16Zero
7827 {1, 4}, // HI32DSP
7828 {1, 4}, // LO32DSP
7829 {1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond
7830 {1, 3}, // GPRMM16MovePPairFirst
7831 {1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7832 {1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7833 {1, 1}, // CPURAReg
7834 {1, 1}, // CPUSPReg
7835 {1, 1}, // DSPCC
7836 {1, 1}, // GP32
7837 {1, 1}, // GPR32ZERO
7838 {1, 1}, // HI32
7839 {1, 1}, // LO32
7840 {1, 1}, // SP32
7841 {2, 64}, // FGR64
7842 {1, 32}, // GPR64
7843 {1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO
7844 {2, 32}, // AFGR64
7845 {1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
7846 {1, 8}, // GPR64_with_sub_32_in_CPU16Regs
7847 {1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP
7848 {1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero
7849 {1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7850 {1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7851 {1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7852 {2, 8}, // ACC64DSP
7853 {1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7854 {1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7855 {1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7856 {1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7857 {1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7858 {0, 0}, // OCTEON_MPL
7859 {0, 0}, // OCTEON_P
7860 {1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7861 {2, 2}, // ACC64
7862 {1, 1}, // GP64
7863 {1, 1}, // GPR64_with_sub_32_in_CPURAReg
7864 {1, 1}, // GPR64_with_sub_32_in_GPR32ZERO
7865 {1, 1}, // HI64
7866 {1, 1}, // LO64
7867 {1, 1}, // SP64
7868 {2, 64}, // MSA128B
7869 {2, 64}, // MSA128D
7870 {2, 64}, // MSA128H
7871 {2, 64}, // MSA128W
7872 {2, 32}, // MSA128WEvens
7873 {2, 2}, // ACC128
7874 };
7875 return RCWeightTable[RC->getID()];
7876}
7877
7878/// Get the weight in units of pressure for this register unit.
7879unsigned MipsGenRegisterInfo::
7880getRegUnitWeight(unsigned RegUnit) const {
7881 assert(RegUnit < 321 && "invalid register unit");
7882 // All register units have unit weight.
7883 return 1;
7884}
7885
7886
7887// Get the number of dimensions of register pressure.
7888unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
7889 return 20;
7890}
7891
7892// Get the name of this register unit pressure set.
7893const char *MipsGenRegisterInfo::
7894getRegPressureSetName(unsigned Idx) const {
7895 static const char *PressureNameTable[] = {
7896 "DSPCC",
7897 "GPR32ZERO",
7898 "GPR64_with_sub_32_in_CPURAReg",
7899 "HI32",
7900 "GPRMM16MovePPairFirst",
7901 "CPU16Regs_and_GPRMM16MoveP",
7902 "HI32DSP",
7903 "LO32DSP",
7904 "GPRMM16MovePPairSecond",
7905 "GPRMM16MoveP",
7906 "ACC64DSP",
7907 "CPU16Regs",
7908 "GPRMM16Zero_with_GPRMM16MovePPairSecond",
7909 "CPU16Regs_with_GPRMM16MovePPairSecond",
7910 "CPU16Regs_with_GPRMM16MoveP",
7911 "DSPR",
7912 "FGR32",
7913 "MSA128WEvens",
7914 "FGR32_with_MSA128WEvens",
7915 "MSA128F16",
7916 };
7917 return PressureNameTable[Idx];
7918}
7919
7920// Get the register unit pressure limit for this dimension.
7921// This limit must be adjusted dynamically for reserved registers.
7922unsigned MipsGenRegisterInfo::
7923getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
7924 static const uint8_t PressureLimitTable[] = {
7925 1, // 0: DSPCC
7926 1, // 1: GPR32ZERO
7927 1, // 2: GPR64_with_sub_32_in_CPURAReg
7928 2, // 3: HI32
7929 3, // 4: GPRMM16MovePPairFirst
7930 5, // 5: CPU16Regs_and_GPRMM16MoveP
7931 5, // 6: HI32DSP
7932 5, // 7: LO32DSP
7933 6, // 8: GPRMM16MovePPairSecond
7934 8, // 9: GPRMM16MoveP
7935 8, // 10: ACC64DSP
7936 10, // 11: CPU16Regs
7937 10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
7938 11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
7939 13, // 14: CPU16Regs_with_GPRMM16MoveP
7940 32, // 15: DSPR
7941 32, // 16: FGR32
7942 32, // 17: MSA128WEvens
7943 48, // 18: FGR32_with_MSA128WEvens
7944 64, // 19: MSA128F16
7945 };
7946 return PressureLimitTable[Idx];
7947}
7948
7949/// Table of pressure sets per register class or unit.
7950static const int RCSetsTable[] = {
7951 /* 0 */ 0, -1,
7952 /* 2 */ 6, 10, -1,
7953 /* 5 */ 3, 6, 7, 10, -1,
7954 /* 10 */ 2, 15, -1,
7955 /* 13 */ 8, 12, 13, 15, -1,
7956 /* 18 */ 9, 14, 15, -1,
7957 /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
7958 /* 30 */ 5, 9, 11, 13, 14, 15, -1,
7959 /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
7960 /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
7961 /* 53 */ 16, 18, 19, -1,
7962 /* 57 */ 16, 17, 18, 19, -1,
7963};
7964
7965/// Get the dimensions of register pressure impacted by this register class.
7966/// Returns a -1 terminated array of pressure set IDs
7967const int *MipsGenRegisterInfo::
7968getRegClassPressureSets(const TargetRegisterClass *RC) const {
7969 static const uint8_t RCSetStartTable[] = {
7970 55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
7971 return &RCSetsTable[RCSetStartTable[RC->getID()]];
7972}
7973
7974/// Get the dimensions of register pressure impacted by this register unit.
7975/// Returns a -1 terminated array of pressure set IDs
7976const int *MipsGenRegisterInfo::
7977getRegUnitPressureSets(unsigned RegUnit) const {
7978 assert(RegUnit < 321 && "invalid register unit");
7979 static const uint8_t RUSetStartTable[] = {
7980 11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
7981 return &RCSetsTable[RUSetStartTable[RegUnit]];
7982}
7983
7984extern const MCRegisterDesc MipsRegDesc[];
7985extern const int16_t MipsRegDiffLists[];
7986extern const LaneBitmask MipsLaneMaskLists[];
7987extern const char MipsRegStrings[];
7988extern const char MipsRegClassStrings[];
7989extern const MCPhysReg MipsRegUnitRoots[][2];
7990extern const uint16_t MipsSubRegIdxLists[];
7991extern const uint16_t MipsRegEncodingTable[];
7992// Mips Dwarf<->LLVM register mappings.
7993extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
7994extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
7995
7996extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
7997extern const unsigned MipsEHFlavour0Dwarf2LSize;
7998
7999extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
8000extern const unsigned MipsDwarfFlavour0L2DwarfSize;
8001
8002extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
8003extern const unsigned MipsEHFlavour0L2DwarfSize;
8004
8005MipsGenRegisterInfo::
8006MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
8007 unsigned PC, unsigned HwMode)
8008 : TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,
8009 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
8010 LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, VTLists, HwMode) {
8011 InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
8012 MipsMCRegisterClasses, 70,
8013 MipsRegUnitRoots,
8014 321,
8015 MipsRegDiffLists,
8016 MipsLaneMaskLists,
8017 MipsRegStrings,
8018 MipsRegClassStrings,
8019 MipsSubRegIdxLists,
8020 12,
8021 MipsRegEncodingTable);
8022
8023 switch (DwarfFlavour) {
8024 default:
8025 llvm_unreachable("Unknown DWARF flavour");
8026 case 0:
8027 mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
8028 break;
8029 }
8030 switch (EHFlavour) {
8031 default:
8032 llvm_unreachable("Unknown DWARF flavour");
8033 case 0:
8034 mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
8035 break;
8036 }
8037 switch (DwarfFlavour) {
8038 default:
8039 llvm_unreachable("Unknown DWARF flavour");
8040 case 0:
8041 mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
8042 break;
8043 }
8044 switch (EHFlavour) {
8045 default:
8046 llvm_unreachable("Unknown DWARF flavour");
8047 case 0:
8048 mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
8049 break;
8050 }
8051}
8052
8053static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
8054static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8055static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
8056static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8057static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
8058static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
8059static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
8060static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
8061static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
8062static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
8063static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8064static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
8065static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8066static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
8067static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8068static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8069static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8070static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
8071static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8072static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8073static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8074static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8075
8076
8077ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
8078 static const uint32_t *const Masks[] = {
8079 CSR_Interrupt_32_RegMask,
8080 CSR_Interrupt_32R6_RegMask,
8081 CSR_Interrupt_64_RegMask,
8082 CSR_Interrupt_64R6_RegMask,
8083 CSR_Mips16RetHelper_RegMask,
8084 CSR_N32_RegMask,
8085 CSR_N64_RegMask,
8086 CSR_O32_RegMask,
8087 CSR_O32_FP64_RegMask,
8088 CSR_O32_FPXX_RegMask,
8089 CSR_SingleFloatOnly_RegMask,
8090 };
8091 return ArrayRef(Masks);
8092}
8093
8094bool MipsGenRegisterInfo::
8095isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8096 return
8097 false;
8098}
8099
8100bool MipsGenRegisterInfo::
8101isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8102 return
8103 false;
8104}
8105
8106bool MipsGenRegisterInfo::
8107isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8108 return
8109 false;
8110}
8111
8112bool MipsGenRegisterInfo::
8113isConstantPhysReg(MCRegister PhysReg) const {
8114 return
8115 PhysReg == Mips::ZERO ||
8116 PhysReg == Mips::ZERO_64 ||
8117 false;
8118}
8119
8120ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
8121 static const char *Names[] = {
8122 "CSR_Interrupt_32",
8123 "CSR_Interrupt_32R6",
8124 "CSR_Interrupt_64",
8125 "CSR_Interrupt_64R6",
8126 "CSR_Mips16RetHelper",
8127 "CSR_N32",
8128 "CSR_N64",
8129 "CSR_O32",
8130 "CSR_O32_FP64",
8131 "CSR_O32_FPXX",
8132 "CSR_SingleFloatOnly",
8133 };
8134 return ArrayRef(Names);
8135}
8136
8137const MipsFrameLowering *
8138MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
8139 return static_cast<const MipsFrameLowering *>(
8140 MF.getSubtarget().getFrameLowering());
8141}
8142
8143} // end namespace llvm
8144
8145#endif // GET_REGINFO_TARGET_DESC
8146
8147