1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(2080375378), // ABSQ_S_PH
767 UINT64_C(4412), // ABSQ_S_PH_MM
768 UINT64_C(2080374866), // ABSQ_S_QB
769 UINT64_C(316), // ABSQ_S_QB_MMR2
770 UINT64_C(2080375890), // ABSQ_S_W
771 UINT64_C(8508), // ABSQ_S_W_MM
772 UINT64_C(32), // ADD
773 UINT64_C(3959422976), // ADDIUPC
774 UINT64_C(2013265920), // ADDIUPC_MM
775 UINT64_C(2013265920), // ADDIUPC_MMR6
776 UINT64_C(27649), // ADDIUR1SP_MM
777 UINT64_C(27648), // ADDIUR2_MM
778 UINT64_C(19456), // ADDIUS5_MM
779 UINT64_C(19457), // ADDIUSP_MM
780 UINT64_C(805306368), // ADDIU_MMR6
781 UINT64_C(2080375320), // ADDQH_PH
782 UINT64_C(77), // ADDQH_PH_MMR2
783 UINT64_C(2080375448), // ADDQH_R_PH
784 UINT64_C(1101), // ADDQH_R_PH_MMR2
785 UINT64_C(2080375960), // ADDQH_R_W
786 UINT64_C(1165), // ADDQH_R_W_MMR2
787 UINT64_C(2080375832), // ADDQH_W
788 UINT64_C(141), // ADDQH_W_MMR2
789 UINT64_C(2080375440), // ADDQ_PH
790 UINT64_C(13), // ADDQ_PH_MM
791 UINT64_C(2080375696), // ADDQ_S_PH
792 UINT64_C(1037), // ADDQ_S_PH_MM
793 UINT64_C(2080376208), // ADDQ_S_W
794 UINT64_C(773), // ADDQ_S_W_MM
795 UINT64_C(1186988056), // ADDR_PS64
796 UINT64_C(2080375824), // ADDSC
797 UINT64_C(901), // ADDSC_MM
798 UINT64_C(2021654544), // ADDS_A_B
799 UINT64_C(2027946000), // ADDS_A_D
800 UINT64_C(2023751696), // ADDS_A_H
801 UINT64_C(2025848848), // ADDS_A_W
802 UINT64_C(2030043152), // ADDS_S_B
803 UINT64_C(2036334608), // ADDS_S_D
804 UINT64_C(2032140304), // ADDS_S_H
805 UINT64_C(2034237456), // ADDS_S_W
806 UINT64_C(2038431760), // ADDS_U_B
807 UINT64_C(2044723216), // ADDS_U_D
808 UINT64_C(2040528912), // ADDS_U_H
809 UINT64_C(2042626064), // ADDS_U_W
810 UINT64_C(1024), // ADDU16_MM
811 UINT64_C(1024), // ADDU16_MMR6
812 UINT64_C(2080374808), // ADDUH_QB
813 UINT64_C(333), // ADDUH_QB_MMR2
814 UINT64_C(2080374936), // ADDUH_R_QB
815 UINT64_C(1357), // ADDUH_R_QB_MMR2
816 UINT64_C(336), // ADDU_MMR6
817 UINT64_C(2080375312), // ADDU_PH
818 UINT64_C(269), // ADDU_PH_MMR2
819 UINT64_C(2080374800), // ADDU_QB
820 UINT64_C(205), // ADDU_QB_MM
821 UINT64_C(2080375568), // ADDU_S_PH
822 UINT64_C(1293), // ADDU_S_PH_MMR2
823 UINT64_C(2080375056), // ADDU_S_QB
824 UINT64_C(1229), // ADDU_S_QB_MM
825 UINT64_C(2013265926), // ADDVI_B
826 UINT64_C(2019557382), // ADDVI_D
827 UINT64_C(2015363078), // ADDVI_H
828 UINT64_C(2017460230), // ADDVI_W
829 UINT64_C(2013265934), // ADDV_B
830 UINT64_C(2019557390), // ADDV_D
831 UINT64_C(2015363086), // ADDV_H
832 UINT64_C(2017460238), // ADDV_W
833 UINT64_C(2080375888), // ADDWC
834 UINT64_C(965), // ADDWC_MM
835 UINT64_C(2013265936), // ADD_A_B
836 UINT64_C(2019557392), // ADD_A_D
837 UINT64_C(2015363088), // ADD_A_H
838 UINT64_C(2017460240), // ADD_A_W
839 UINT64_C(272), // ADD_MM
840 UINT64_C(272), // ADD_MMR6
841 UINT64_C(536870912), // ADDi
842 UINT64_C(268435456), // ADDi_MM
843 UINT64_C(603979776), // ADDiu
844 UINT64_C(805306368), // ADDiu_MM
845 UINT64_C(33), // ADDu
846 UINT64_C(336), // ADDu_MM
847 UINT64_C(2080375328), // ALIGN
848 UINT64_C(31), // ALIGN_MMR6
849 UINT64_C(3961454592), // ALUIPC
850 UINT64_C(2015297536), // ALUIPC_MMR6
851 UINT64_C(36), // AND
852 UINT64_C(17536), // AND16_MM
853 UINT64_C(17409), // AND16_MMR6
854 UINT64_C(36), // AND64
855 UINT64_C(11264), // ANDI16_MM
856 UINT64_C(11264), // ANDI16_MMR6
857 UINT64_C(2013265920), // ANDI_B
858 UINT64_C(3489660928), // ANDI_MMR6
859 UINT64_C(592), // AND_MM
860 UINT64_C(592), // AND_MMR6
861 UINT64_C(2013265950), // AND_V
862 UINT64_C(805306368), // ANDi
863 UINT64_C(805306368), // ANDi64
864 UINT64_C(3489660928), // ANDi_MM
865 UINT64_C(2080374833), // APPEND
866 UINT64_C(533), // APPEND_MMR2
867 UINT64_C(2046820369), // ASUB_S_B
868 UINT64_C(2053111825), // ASUB_S_D
869 UINT64_C(2048917521), // ASUB_S_H
870 UINT64_C(2051014673), // ASUB_S_W
871 UINT64_C(2055208977), // ASUB_U_B
872 UINT64_C(2061500433), // ASUB_U_D
873 UINT64_C(2057306129), // ASUB_U_H
874 UINT64_C(2059403281), // ASUB_U_W
875 UINT64_C(1006632960), // AUI
876 UINT64_C(3961389056), // AUIPC
877 UINT64_C(2015232000), // AUIPC_MMR6
878 UINT64_C(268435456), // AUI_MMR6
879 UINT64_C(2063597584), // AVER_S_B
880 UINT64_C(2069889040), // AVER_S_D
881 UINT64_C(2065694736), // AVER_S_H
882 UINT64_C(2067791888), // AVER_S_W
883 UINT64_C(2071986192), // AVER_U_B
884 UINT64_C(2078277648), // AVER_U_D
885 UINT64_C(2074083344), // AVER_U_H
886 UINT64_C(2076180496), // AVER_U_W
887 UINT64_C(2046820368), // AVE_S_B
888 UINT64_C(2053111824), // AVE_S_D
889 UINT64_C(2048917520), // AVE_S_H
890 UINT64_C(2051014672), // AVE_S_W
891 UINT64_C(2055208976), // AVE_U_B
892 UINT64_C(2061500432), // AVE_U_D
893 UINT64_C(2057306128), // AVE_U_H
894 UINT64_C(2059403280), // AVE_U_W
895 UINT64_C(4026550272), // AddiuRxImmX16
896 UINT64_C(4026533888), // AddiuRxPcImmX16
897 UINT64_C(18432), // AddiuRxRxImm16
898 UINT64_C(4026550272), // AddiuRxRxImmX16
899 UINT64_C(4026548224), // AddiuRxRyOffMemX16
900 UINT64_C(25344), // AddiuSpImm16
901 UINT64_C(4026544896), // AddiuSpImmX16
902 UINT64_C(57345), // AdduRxRyRz16
903 UINT64_C(59404), // AndRxRxRy16
904 UINT64_C(52224), // B16_MM
905 UINT64_C(1879048232), // BADDu
906 UINT64_C(68222976), // BAL
907 UINT64_C(3892314112), // BALC
908 UINT64_C(3019898880), // BALC_MMR6
909 UINT64_C(2080375857), // BALIGN
910 UINT64_C(2236), // BALIGN_MMR2
911 UINT64_C(3355443200), // BBIT0
912 UINT64_C(3623878656), // BBIT032
913 UINT64_C(3892314112), // BBIT1
914 UINT64_C(4160749568), // BBIT132
915 UINT64_C(3355443200), // BC
916 UINT64_C(52224), // BC16_MMR6
917 UINT64_C(1159725056), // BC1EQZ
918 UINT64_C(1090519040), // BC1EQZC_MMR6
919 UINT64_C(1157627904), // BC1F
920 UINT64_C(1157758976), // BC1FL
921 UINT64_C(1132462080), // BC1F_MM
922 UINT64_C(1168113664), // BC1NEZ
923 UINT64_C(1092616192), // BC1NEZC_MMR6
924 UINT64_C(1157693440), // BC1T
925 UINT64_C(1157824512), // BC1TL
926 UINT64_C(1134559232), // BC1T_MM
927 UINT64_C(1226833920), // BC2EQZ
928 UINT64_C(1094713344), // BC2EQZC_MMR6
929 UINT64_C(1235222528), // BC2NEZ
930 UINT64_C(1096810496), // BC2NEZC_MMR6
931 UINT64_C(2045771785), // BCLRI_B
932 UINT64_C(2038431753), // BCLRI_D
933 UINT64_C(2044723209), // BCLRI_H
934 UINT64_C(2042626057), // BCLRI_W
935 UINT64_C(2038431757), // BCLR_B
936 UINT64_C(2044723213), // BCLR_D
937 UINT64_C(2040528909), // BCLR_H
938 UINT64_C(2042626061), // BCLR_W
939 UINT64_C(2483027968), // BC_MMR6
940 UINT64_C(268435456), // BEQ
941 UINT64_C(268435456), // BEQ64
942 UINT64_C(536870912), // BEQC
943 UINT64_C(536870912), // BEQC64
944 UINT64_C(1946157056), // BEQC_MMR6
945 UINT64_C(1342177280), // BEQL
946 UINT64_C(35840), // BEQZ16_MM
947 UINT64_C(536870912), // BEQZALC
948 UINT64_C(1946157056), // BEQZALC_MMR6
949 UINT64_C(3623878656), // BEQZC
950 UINT64_C(35840), // BEQZC16_MMR6
951 UINT64_C(3623878656), // BEQZC64
952 UINT64_C(1088421888), // BEQZC_MM
953 UINT64_C(2147483648), // BEQZC_MMR6
954 UINT64_C(2483027968), // BEQ_MM
955 UINT64_C(1476395008), // BGEC
956 UINT64_C(1476395008), // BGEC64
957 UINT64_C(4093640704), // BGEC_MMR6
958 UINT64_C(402653184), // BGEUC
959 UINT64_C(402653184), // BGEUC64
960 UINT64_C(3221225472), // BGEUC_MMR6
961 UINT64_C(67174400), // BGEZ
962 UINT64_C(67174400), // BGEZ64
963 UINT64_C(68222976), // BGEZAL
964 UINT64_C(402653184), // BGEZALC
965 UINT64_C(3221225472), // BGEZALC_MMR6
966 UINT64_C(68354048), // BGEZALL
967 UINT64_C(1113587712), // BGEZALS_MM
968 UINT64_C(1080033280), // BGEZAL_MM
969 UINT64_C(1476395008), // BGEZC
970 UINT64_C(1476395008), // BGEZC64
971 UINT64_C(4093640704), // BGEZC_MMR6
972 UINT64_C(67305472), // BGEZL
973 UINT64_C(1077936128), // BGEZ_MM
974 UINT64_C(469762048), // BGTZ
975 UINT64_C(469762048), // BGTZ64
976 UINT64_C(469762048), // BGTZALC
977 UINT64_C(3758096384), // BGTZALC_MMR6
978 UINT64_C(1543503872), // BGTZC
979 UINT64_C(1543503872), // BGTZC64
980 UINT64_C(3556769792), // BGTZC_MMR6
981 UINT64_C(1543503872), // BGTZL
982 UINT64_C(1086324736), // BGTZ_MM
983 UINT64_C(2070937609), // BINSLI_B
984 UINT64_C(2063597577), // BINSLI_D
985 UINT64_C(2069889033), // BINSLI_H
986 UINT64_C(2067791881), // BINSLI_W
987 UINT64_C(2063597581), // BINSL_B
988 UINT64_C(2069889037), // BINSL_D
989 UINT64_C(2065694733), // BINSL_H
990 UINT64_C(2067791885), // BINSL_W
991 UINT64_C(2079326217), // BINSRI_B
992 UINT64_C(2071986185), // BINSRI_D
993 UINT64_C(2078277641), // BINSRI_H
994 UINT64_C(2076180489), // BINSRI_W
995 UINT64_C(2071986189), // BINSR_B
996 UINT64_C(2078277645), // BINSR_D
997 UINT64_C(2074083341), // BINSR_H
998 UINT64_C(2076180493), // BINSR_W
999 UINT64_C(2080376530), // BITREV
1000 UINT64_C(12604), // BITREV_MM
1001 UINT64_C(2080374816), // BITSWAP
1002 UINT64_C(2876), // BITSWAP_MMR6
1003 UINT64_C(402653184), // BLEZ
1004 UINT64_C(402653184), // BLEZ64
1005 UINT64_C(402653184), // BLEZALC
1006 UINT64_C(3221225472), // BLEZALC_MMR6
1007 UINT64_C(1476395008), // BLEZC
1008 UINT64_C(1476395008), // BLEZC64
1009 UINT64_C(4093640704), // BLEZC_MMR6
1010 UINT64_C(1476395008), // BLEZL
1011 UINT64_C(1082130432), // BLEZ_MM
1012 UINT64_C(1543503872), // BLTC
1013 UINT64_C(1543503872), // BLTC64
1014 UINT64_C(3556769792), // BLTC_MMR6
1015 UINT64_C(469762048), // BLTUC
1016 UINT64_C(469762048), // BLTUC64
1017 UINT64_C(3758096384), // BLTUC_MMR6
1018 UINT64_C(67108864), // BLTZ
1019 UINT64_C(67108864), // BLTZ64
1020 UINT64_C(68157440), // BLTZAL
1021 UINT64_C(469762048), // BLTZALC
1022 UINT64_C(3758096384), // BLTZALC_MMR6
1023 UINT64_C(68288512), // BLTZALL
1024 UINT64_C(1109393408), // BLTZALS_MM
1025 UINT64_C(1075838976), // BLTZAL_MM
1026 UINT64_C(1543503872), // BLTZC
1027 UINT64_C(1543503872), // BLTZC64
1028 UINT64_C(3556769792), // BLTZC_MMR6
1029 UINT64_C(67239936), // BLTZL
1030 UINT64_C(1073741824), // BLTZ_MM
1031 UINT64_C(2013265921), // BMNZI_B
1032 UINT64_C(2021654558), // BMNZ_V
1033 UINT64_C(2030043137), // BMZI_B
1034 UINT64_C(2023751710), // BMZ_V
1035 UINT64_C(335544320), // BNE
1036 UINT64_C(335544320), // BNE64
1037 UINT64_C(1610612736), // BNEC
1038 UINT64_C(1610612736), // BNEC64
1039 UINT64_C(2080374784), // BNEC_MMR6
1040 UINT64_C(2062549001), // BNEGI_B
1041 UINT64_C(2055208969), // BNEGI_D
1042 UINT64_C(2061500425), // BNEGI_H
1043 UINT64_C(2059403273), // BNEGI_W
1044 UINT64_C(2055208973), // BNEG_B
1045 UINT64_C(2061500429), // BNEG_D
1046 UINT64_C(2057306125), // BNEG_H
1047 UINT64_C(2059403277), // BNEG_W
1048 UINT64_C(1409286144), // BNEL
1049 UINT64_C(44032), // BNEZ16_MM
1050 UINT64_C(1610612736), // BNEZALC
1051 UINT64_C(2080374784), // BNEZALC_MMR6
1052 UINT64_C(4160749568), // BNEZC
1053 UINT64_C(44032), // BNEZC16_MMR6
1054 UINT64_C(4160749568), // BNEZC64
1055 UINT64_C(1084227584), // BNEZC_MM
1056 UINT64_C(2684354560), // BNEZC_MMR6
1057 UINT64_C(3019898880), // BNE_MM
1058 UINT64_C(1610612736), // BNVC
1059 UINT64_C(2080374784), // BNVC_MMR6
1060 UINT64_C(1199570944), // BNZ_B
1061 UINT64_C(1205862400), // BNZ_D
1062 UINT64_C(1201668096), // BNZ_H
1063 UINT64_C(1172307968), // BNZ_V
1064 UINT64_C(1203765248), // BNZ_W
1065 UINT64_C(536870912), // BOVC
1066 UINT64_C(1946157056), // BOVC_MMR6
1067 UINT64_C(68943872), // BPOSGE32
1068 UINT64_C(1126170624), // BPOSGE32C_MMR3
1069 UINT64_C(1130364928), // BPOSGE32_MM
1070 UINT64_C(13), // BREAK
1071 UINT64_C(18048), // BREAK16_MM
1072 UINT64_C(17435), // BREAK16_MMR6
1073 UINT64_C(7), // BREAK_MM
1074 UINT64_C(7), // BREAK_MMR6
1075 UINT64_C(2046820353), // BSELI_B
1076 UINT64_C(2025848862), // BSEL_V
1077 UINT64_C(2054160393), // BSETI_B
1078 UINT64_C(2046820361), // BSETI_D
1079 UINT64_C(2053111817), // BSETI_H
1080 UINT64_C(2051014665), // BSETI_W
1081 UINT64_C(2046820365), // BSET_B
1082 UINT64_C(2053111821), // BSET_D
1083 UINT64_C(2048917517), // BSET_H
1084 UINT64_C(2051014669), // BSET_W
1085 UINT64_C(1191182336), // BZ_B
1086 UINT64_C(1197473792), // BZ_D
1087 UINT64_C(1193279488), // BZ_H
1088 UINT64_C(1163919360), // BZ_V
1089 UINT64_C(1195376640), // BZ_W
1090 UINT64_C(8192), // BeqzRxImm16
1091 UINT64_C(4026540032), // BeqzRxImmX16
1092 UINT64_C(4096), // Bimm16
1093 UINT64_C(4026535936), // BimmX16
1094 UINT64_C(10240), // BnezRxImm16
1095 UINT64_C(4026542080), // BnezRxImmX16
1096 UINT64_C(59397), // Break16
1097 UINT64_C(24576), // Bteqz16
1098 UINT64_C(4026544128), // BteqzX16
1099 UINT64_C(24832), // Btnez16
1100 UINT64_C(4026544384), // BtnezX16
1101 UINT64_C(3154116608), // CACHE
1102 UINT64_C(2080374811), // CACHEE
1103 UINT64_C(1610655232), // CACHEE_MM
1104 UINT64_C(536895488), // CACHE_MM
1105 UINT64_C(536895488), // CACHE_MMR6
1106 UINT64_C(2080374821), // CACHE_R6
1107 UINT64_C(1176502282), // CEIL_L_D64
1108 UINT64_C(1409307451), // CEIL_L_D_MMR6
1109 UINT64_C(1174405130), // CEIL_L_S
1110 UINT64_C(1409291067), // CEIL_L_S_MMR6
1111 UINT64_C(1176502286), // CEIL_W_D32
1112 UINT64_C(1176502286), // CEIL_W_D64
1113 UINT64_C(1409309499), // CEIL_W_D_MMR6
1114 UINT64_C(1409309499), // CEIL_W_MM
1115 UINT64_C(1174405134), // CEIL_W_S
1116 UINT64_C(1409293115), // CEIL_W_S_MM
1117 UINT64_C(1409293115), // CEIL_W_S_MMR6
1118 UINT64_C(2013265927), // CEQI_B
1119 UINT64_C(2019557383), // CEQI_D
1120 UINT64_C(2015363079), // CEQI_H
1121 UINT64_C(2017460231), // CEQI_W
1122 UINT64_C(2013265935), // CEQ_B
1123 UINT64_C(2019557391), // CEQ_D
1124 UINT64_C(2015363087), // CEQ_H
1125 UINT64_C(2017460239), // CEQ_W
1126 UINT64_C(1145044992), // CFC1
1127 UINT64_C(1409290299), // CFC1_MM
1128 UINT64_C(52540), // CFC2_MM
1129 UINT64_C(2021523481), // CFCMSA
1130 UINT64_C(1879048242), // CINS
1131 UINT64_C(1879048243), // CINS32
1132 UINT64_C(1879048242), // CINS64_32
1133 UINT64_C(1879048242), // CINS_i32
1134 UINT64_C(1176502299), // CLASS_D
1135 UINT64_C(1409286752), // CLASS_D_MMR6
1136 UINT64_C(1174405147), // CLASS_S
1137 UINT64_C(1409286240), // CLASS_S_MMR6
1138 UINT64_C(2046820359), // CLEI_S_B
1139 UINT64_C(2053111815), // CLEI_S_D
1140 UINT64_C(2048917511), // CLEI_S_H
1141 UINT64_C(2051014663), // CLEI_S_W
1142 UINT64_C(2055208967), // CLEI_U_B
1143 UINT64_C(2061500423), // CLEI_U_D
1144 UINT64_C(2057306119), // CLEI_U_H
1145 UINT64_C(2059403271), // CLEI_U_W
1146 UINT64_C(2046820367), // CLE_S_B
1147 UINT64_C(2053111823), // CLE_S_D
1148 UINT64_C(2048917519), // CLE_S_H
1149 UINT64_C(2051014671), // CLE_S_W
1150 UINT64_C(2055208975), // CLE_U_B
1151 UINT64_C(2061500431), // CLE_U_D
1152 UINT64_C(2057306127), // CLE_U_H
1153 UINT64_C(2059403279), // CLE_U_W
1154 UINT64_C(1879048225), // CLO
1155 UINT64_C(19260), // CLO_MM
1156 UINT64_C(19260), // CLO_MMR6
1157 UINT64_C(81), // CLO_R6
1158 UINT64_C(2030043143), // CLTI_S_B
1159 UINT64_C(2036334599), // CLTI_S_D
1160 UINT64_C(2032140295), // CLTI_S_H
1161 UINT64_C(2034237447), // CLTI_S_W
1162 UINT64_C(2038431751), // CLTI_U_B
1163 UINT64_C(2044723207), // CLTI_U_D
1164 UINT64_C(2040528903), // CLTI_U_H
1165 UINT64_C(2042626055), // CLTI_U_W
1166 UINT64_C(2030043151), // CLT_S_B
1167 UINT64_C(2036334607), // CLT_S_D
1168 UINT64_C(2032140303), // CLT_S_H
1169 UINT64_C(2034237455), // CLT_S_W
1170 UINT64_C(2038431759), // CLT_U_B
1171 UINT64_C(2044723215), // CLT_U_D
1172 UINT64_C(2040528911), // CLT_U_H
1173 UINT64_C(2042626063), // CLT_U_W
1174 UINT64_C(1879048224), // CLZ
1175 UINT64_C(23356), // CLZ_MM
1176 UINT64_C(80), // CLZ_MMR6
1177 UINT64_C(80), // CLZ_R6
1178 UINT64_C(2080376337), // CMPGDU_EQ_QB
1179 UINT64_C(389), // CMPGDU_EQ_QB_MMR2
1180 UINT64_C(2080376465), // CMPGDU_LE_QB
1181 UINT64_C(517), // CMPGDU_LE_QB_MMR2
1182 UINT64_C(2080376401), // CMPGDU_LT_QB
1183 UINT64_C(453), // CMPGDU_LT_QB_MMR2
1184 UINT64_C(2080375057), // CMPGU_EQ_QB
1185 UINT64_C(1476395205), // CMPGU_EQ_QB_MM
1186 UINT64_C(2080375185), // CMPGU_LE_QB
1187 UINT64_C(1476395333), // CMPGU_LE_QB_MM
1188 UINT64_C(2080375121), // CMPGU_LT_QB
1189 UINT64_C(1476395269), // CMPGU_LT_QB_MM
1190 UINT64_C(2080374801), // CMPU_EQ_QB
1191 UINT64_C(581), // CMPU_EQ_QB_MM
1192 UINT64_C(2080374929), // CMPU_LE_QB
1193 UINT64_C(709), // CMPU_LE_QB_MM
1194 UINT64_C(2080374865), // CMPU_LT_QB
1195 UINT64_C(645), // CMPU_LT_QB_MM
1196 UINT64_C(1409286165), // CMP_AF_D_MMR6
1197 UINT64_C(1409286149), // CMP_AF_S_MMR6
1198 UINT64_C(1184890882), // CMP_EQ_D
1199 UINT64_C(1409286293), // CMP_EQ_D_MMR6
1200 UINT64_C(2080375313), // CMP_EQ_PH
1201 UINT64_C(5), // CMP_EQ_PH_MM
1202 UINT64_C(1182793730), // CMP_EQ_S
1203 UINT64_C(1409286277), // CMP_EQ_S_MMR6
1204 UINT64_C(1184890880), // CMP_F_D
1205 UINT64_C(1182793728), // CMP_F_S
1206 UINT64_C(1184890886), // CMP_LE_D
1207 UINT64_C(1409286549), // CMP_LE_D_MMR6
1208 UINT64_C(2080375441), // CMP_LE_PH
1209 UINT64_C(133), // CMP_LE_PH_MM
1210 UINT64_C(1182793734), // CMP_LE_S
1211 UINT64_C(1409286533), // CMP_LE_S_MMR6
1212 UINT64_C(1184890884), // CMP_LT_D
1213 UINT64_C(1409286421), // CMP_LT_D_MMR6
1214 UINT64_C(2080375377), // CMP_LT_PH
1215 UINT64_C(69), // CMP_LT_PH_MM
1216 UINT64_C(1182793732), // CMP_LT_S
1217 UINT64_C(1409286405), // CMP_LT_S_MMR6
1218 UINT64_C(1184890888), // CMP_SAF_D
1219 UINT64_C(1409286677), // CMP_SAF_D_MMR6
1220 UINT64_C(1182793736), // CMP_SAF_S
1221 UINT64_C(1409286661), // CMP_SAF_S_MMR6
1222 UINT64_C(1184890890), // CMP_SEQ_D
1223 UINT64_C(1409286805), // CMP_SEQ_D_MMR6
1224 UINT64_C(1182793738), // CMP_SEQ_S
1225 UINT64_C(1409286789), // CMP_SEQ_S_MMR6
1226 UINT64_C(1184890894), // CMP_SLE_D
1227 UINT64_C(1409287061), // CMP_SLE_D_MMR6
1228 UINT64_C(1182793742), // CMP_SLE_S
1229 UINT64_C(1409287045), // CMP_SLE_S_MMR6
1230 UINT64_C(1184890892), // CMP_SLT_D
1231 UINT64_C(1409286933), // CMP_SLT_D_MMR6
1232 UINT64_C(1182793740), // CMP_SLT_S
1233 UINT64_C(1409286917), // CMP_SLT_S_MMR6
1234 UINT64_C(1184890891), // CMP_SUEQ_D
1235 UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
1236 UINT64_C(1182793739), // CMP_SUEQ_S
1237 UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
1238 UINT64_C(1184890895), // CMP_SULE_D
1239 UINT64_C(1409287125), // CMP_SULE_D_MMR6
1240 UINT64_C(1182793743), // CMP_SULE_S
1241 UINT64_C(1409287109), // CMP_SULE_S_MMR6
1242 UINT64_C(1184890893), // CMP_SULT_D
1243 UINT64_C(1409286997), // CMP_SULT_D_MMR6
1244 UINT64_C(1182793741), // CMP_SULT_S
1245 UINT64_C(1409286981), // CMP_SULT_S_MMR6
1246 UINT64_C(1184890889), // CMP_SUN_D
1247 UINT64_C(1409286741), // CMP_SUN_D_MMR6
1248 UINT64_C(1182793737), // CMP_SUN_S
1249 UINT64_C(1409286725), // CMP_SUN_S_MMR6
1250 UINT64_C(1184890883), // CMP_UEQ_D
1251 UINT64_C(1409286357), // CMP_UEQ_D_MMR6
1252 UINT64_C(1182793731), // CMP_UEQ_S
1253 UINT64_C(1409286341), // CMP_UEQ_S_MMR6
1254 UINT64_C(1184890887), // CMP_ULE_D
1255 UINT64_C(1409286613), // CMP_ULE_D_MMR6
1256 UINT64_C(1182793735), // CMP_ULE_S
1257 UINT64_C(1409286597), // CMP_ULE_S_MMR6
1258 UINT64_C(1184890885), // CMP_ULT_D
1259 UINT64_C(1409286485), // CMP_ULT_D_MMR6
1260 UINT64_C(1182793733), // CMP_ULT_S
1261 UINT64_C(1409286469), // CMP_ULT_S_MMR6
1262 UINT64_C(1184890881), // CMP_UN_D
1263 UINT64_C(1409286229), // CMP_UN_D_MMR6
1264 UINT64_C(1182793729), // CMP_UN_S
1265 UINT64_C(1409286213), // CMP_UN_S_MMR6
1266 UINT64_C(2021654553), // COPY_S_B
1267 UINT64_C(2025324569), // COPY_S_D
1268 UINT64_C(2023751705), // COPY_S_H
1269 UINT64_C(2024800281), // COPY_S_W
1270 UINT64_C(2025848857), // COPY_U_B
1271 UINT64_C(2027946009), // COPY_U_H
1272 UINT64_C(2028994585), // COPY_U_W
1273 UINT64_C(2080374799), // CRC32B
1274 UINT64_C(2080375055), // CRC32CB
1275 UINT64_C(2080375247), // CRC32CD
1276 UINT64_C(2080375119), // CRC32CH
1277 UINT64_C(2080375183), // CRC32CW
1278 UINT64_C(2080374991), // CRC32D
1279 UINT64_C(2080374863), // CRC32H
1280 UINT64_C(2080374927), // CRC32W
1281 UINT64_C(1153433600), // CTC1
1282 UINT64_C(1409292347), // CTC1_MM
1283 UINT64_C(56636), // CTC2_MM
1284 UINT64_C(2017329177), // CTCMSA
1285 UINT64_C(1174405153), // CVT_D32_S
1286 UINT64_C(1409291131), // CVT_D32_S_MM
1287 UINT64_C(1182793761), // CVT_D32_W
1288 UINT64_C(1409299323), // CVT_D32_W_MM
1289 UINT64_C(1184890913), // CVT_D64_L
1290 UINT64_C(1174405153), // CVT_D64_S
1291 UINT64_C(1409291131), // CVT_D64_S_MM
1292 UINT64_C(1182793761), // CVT_D64_W
1293 UINT64_C(1409299323), // CVT_D64_W_MM
1294 UINT64_C(1409307515), // CVT_D_L_MMR6
1295 UINT64_C(1176502309), // CVT_L_D64
1296 UINT64_C(1409302843), // CVT_L_D64_MM
1297 UINT64_C(1409302843), // CVT_L_D_MMR6
1298 UINT64_C(1174405157), // CVT_L_S
1299 UINT64_C(1409286459), // CVT_L_S_MM
1300 UINT64_C(1409286459), // CVT_L_S_MMR6
1301 UINT64_C(1182793766), // CVT_PS_PW64
1302 UINT64_C(1174405158), // CVT_PS_S64
1303 UINT64_C(1186988068), // CVT_PW_PS64
1304 UINT64_C(1176502304), // CVT_S_D32
1305 UINT64_C(1409293179), // CVT_S_D32_MM
1306 UINT64_C(1176502304), // CVT_S_D64
1307 UINT64_C(1409293179), // CVT_S_D64_MM
1308 UINT64_C(1184890912), // CVT_S_L
1309 UINT64_C(1409309563), // CVT_S_L_MMR6
1310 UINT64_C(1186988072), // CVT_S_PL64
1311 UINT64_C(1186988064), // CVT_S_PU64
1312 UINT64_C(1182793760), // CVT_S_W
1313 UINT64_C(1409301371), // CVT_S_W_MM
1314 UINT64_C(1409301371), // CVT_S_W_MMR6
1315 UINT64_C(1176502308), // CVT_W_D32
1316 UINT64_C(1409304891), // CVT_W_D32_MM
1317 UINT64_C(1176502308), // CVT_W_D64
1318 UINT64_C(1409304891), // CVT_W_D64_MM
1319 UINT64_C(1174405156), // CVT_W_S
1320 UINT64_C(1409288507), // CVT_W_S_MM
1321 UINT64_C(1409288507), // CVT_W_S_MMR6
1322 UINT64_C(1176502322), // C_EQ_D32
1323 UINT64_C(1409287356), // C_EQ_D32_MM
1324 UINT64_C(1176502322), // C_EQ_D64
1325 UINT64_C(1409287356), // C_EQ_D64_MM
1326 UINT64_C(1174405170), // C_EQ_S
1327 UINT64_C(1409286332), // C_EQ_S_MM
1328 UINT64_C(1176502320), // C_F_D32
1329 UINT64_C(1409287228), // C_F_D32_MM
1330 UINT64_C(1176502320), // C_F_D64
1331 UINT64_C(1409287228), // C_F_D64_MM
1332 UINT64_C(1174405168), // C_F_S
1333 UINT64_C(1409286204), // C_F_S_MM
1334 UINT64_C(1176502334), // C_LE_D32
1335 UINT64_C(1409288124), // C_LE_D32_MM
1336 UINT64_C(1176502334), // C_LE_D64
1337 UINT64_C(1409288124), // C_LE_D64_MM
1338 UINT64_C(1174405182), // C_LE_S
1339 UINT64_C(1409287100), // C_LE_S_MM
1340 UINT64_C(1176502332), // C_LT_D32
1341 UINT64_C(1409287996), // C_LT_D32_MM
1342 UINT64_C(1176502332), // C_LT_D64
1343 UINT64_C(1409287996), // C_LT_D64_MM
1344 UINT64_C(1174405180), // C_LT_S
1345 UINT64_C(1409286972), // C_LT_S_MM
1346 UINT64_C(1176502333), // C_NGE_D32
1347 UINT64_C(1409288060), // C_NGE_D32_MM
1348 UINT64_C(1176502333), // C_NGE_D64
1349 UINT64_C(1409288060), // C_NGE_D64_MM
1350 UINT64_C(1174405181), // C_NGE_S
1351 UINT64_C(1409287036), // C_NGE_S_MM
1352 UINT64_C(1176502329), // C_NGLE_D32
1353 UINT64_C(1409287804), // C_NGLE_D32_MM
1354 UINT64_C(1176502329), // C_NGLE_D64
1355 UINT64_C(1409287804), // C_NGLE_D64_MM
1356 UINT64_C(1174405177), // C_NGLE_S
1357 UINT64_C(1409286780), // C_NGLE_S_MM
1358 UINT64_C(1176502331), // C_NGL_D32
1359 UINT64_C(1409287932), // C_NGL_D32_MM
1360 UINT64_C(1176502331), // C_NGL_D64
1361 UINT64_C(1409287932), // C_NGL_D64_MM
1362 UINT64_C(1174405179), // C_NGL_S
1363 UINT64_C(1409286908), // C_NGL_S_MM
1364 UINT64_C(1176502335), // C_NGT_D32
1365 UINT64_C(1409288188), // C_NGT_D32_MM
1366 UINT64_C(1176502335), // C_NGT_D64
1367 UINT64_C(1409288188), // C_NGT_D64_MM
1368 UINT64_C(1174405183), // C_NGT_S
1369 UINT64_C(1409287164), // C_NGT_S_MM
1370 UINT64_C(1176502326), // C_OLE_D32
1371 UINT64_C(1409287612), // C_OLE_D32_MM
1372 UINT64_C(1176502326), // C_OLE_D64
1373 UINT64_C(1409287612), // C_OLE_D64_MM
1374 UINT64_C(1174405174), // C_OLE_S
1375 UINT64_C(1409286588), // C_OLE_S_MM
1376 UINT64_C(1176502324), // C_OLT_D32
1377 UINT64_C(1409287484), // C_OLT_D32_MM
1378 UINT64_C(1176502324), // C_OLT_D64
1379 UINT64_C(1409287484), // C_OLT_D64_MM
1380 UINT64_C(1174405172), // C_OLT_S
1381 UINT64_C(1409286460), // C_OLT_S_MM
1382 UINT64_C(1176502330), // C_SEQ_D32
1383 UINT64_C(1409287868), // C_SEQ_D32_MM
1384 UINT64_C(1176502330), // C_SEQ_D64
1385 UINT64_C(1409287868), // C_SEQ_D64_MM
1386 UINT64_C(1174405178), // C_SEQ_S
1387 UINT64_C(1409286844), // C_SEQ_S_MM
1388 UINT64_C(1176502328), // C_SF_D32
1389 UINT64_C(1409287740), // C_SF_D32_MM
1390 UINT64_C(1176502328), // C_SF_D64
1391 UINT64_C(1409287740), // C_SF_D64_MM
1392 UINT64_C(1174405176), // C_SF_S
1393 UINT64_C(1409286716), // C_SF_S_MM
1394 UINT64_C(1176502323), // C_UEQ_D32
1395 UINT64_C(1409287420), // C_UEQ_D32_MM
1396 UINT64_C(1176502323), // C_UEQ_D64
1397 UINT64_C(1409287420), // C_UEQ_D64_MM
1398 UINT64_C(1174405171), // C_UEQ_S
1399 UINT64_C(1409286396), // C_UEQ_S_MM
1400 UINT64_C(1176502327), // C_ULE_D32
1401 UINT64_C(1409287676), // C_ULE_D32_MM
1402 UINT64_C(1176502327), // C_ULE_D64
1403 UINT64_C(1409287676), // C_ULE_D64_MM
1404 UINT64_C(1174405175), // C_ULE_S
1405 UINT64_C(1409286652), // C_ULE_S_MM
1406 UINT64_C(1176502325), // C_ULT_D32
1407 UINT64_C(1409287548), // C_ULT_D32_MM
1408 UINT64_C(1176502325), // C_ULT_D64
1409 UINT64_C(1409287548), // C_ULT_D64_MM
1410 UINT64_C(1174405173), // C_ULT_S
1411 UINT64_C(1409286524), // C_ULT_S_MM
1412 UINT64_C(1176502321), // C_UN_D32
1413 UINT64_C(1409287292), // C_UN_D32_MM
1414 UINT64_C(1176502321), // C_UN_D64
1415 UINT64_C(1409287292), // C_UN_D64_MM
1416 UINT64_C(1174405169), // C_UN_S
1417 UINT64_C(1409286268), // C_UN_S_MM
1418 UINT64_C(59402), // CmpRxRy16
1419 UINT64_C(28672), // CmpiRxImm16
1420 UINT64_C(4026560512), // CmpiRxImmX16
1421 UINT64_C(44), // DADD
1422 UINT64_C(1610612736), // DADDi
1423 UINT64_C(1677721600), // DADDiu
1424 UINT64_C(45), // DADDu
1425 UINT64_C(67502080), // DAHI
1426 UINT64_C(2080375332), // DALIGN
1427 UINT64_C(69074944), // DATI
1428 UINT64_C(1946157056), // DAUI
1429 UINT64_C(2080374820), // DBITSWAP
1430 UINT64_C(1879048229), // DCLO
1431 UINT64_C(83), // DCLO_R6
1432 UINT64_C(1879048228), // DCLZ
1433 UINT64_C(82), // DCLZ_R6
1434 UINT64_C(158), // DDIV
1435 UINT64_C(159), // DDIVU
1436 UINT64_C(1107296287), // DERET
1437 UINT64_C(58236), // DERET_MM
1438 UINT64_C(58236), // DERET_MMR6
1439 UINT64_C(2080374787), // DEXT
1440 UINT64_C(2080374787), // DEXT64_32
1441 UINT64_C(2080374785), // DEXTM
1442 UINT64_C(2080374786), // DEXTU
1443 UINT64_C(1096835072), // DI
1444 UINT64_C(2080374791), // DINS
1445 UINT64_C(2080374789), // DINSM
1446 UINT64_C(2080374790), // DINSU
1447 UINT64_C(154), // DIV
1448 UINT64_C(155), // DIVU
1449 UINT64_C(408), // DIVU_MMR6
1450 UINT64_C(280), // DIV_MMR6
1451 UINT64_C(2046820370), // DIV_S_B
1452 UINT64_C(2053111826), // DIV_S_D
1453 UINT64_C(2048917522), // DIV_S_H
1454 UINT64_C(2051014674), // DIV_S_W
1455 UINT64_C(2055208978), // DIV_U_B
1456 UINT64_C(2061500434), // DIV_U_D
1457 UINT64_C(2057306130), // DIV_U_H
1458 UINT64_C(2059403282), // DIV_U_W
1459 UINT64_C(18300), // DI_MM
1460 UINT64_C(18300), // DI_MMR6
1461 UINT64_C(21), // DLSA
1462 UINT64_C(21), // DLSA_R6
1463 UINT64_C(1075838976), // DMFC0
1464 UINT64_C(1142947840), // DMFC1
1465 UINT64_C(1210056704), // DMFC2
1466 UINT64_C(1210056704), // DMFC2_OCTEON
1467 UINT64_C(1080033536), // DMFGC0
1468 UINT64_C(222), // DMOD
1469 UINT64_C(223), // DMODU
1470 UINT64_C(1096813505), // DMT
1471 UINT64_C(1084227584), // DMTC0
1472 UINT64_C(1151336448), // DMTC1
1473 UINT64_C(1218445312), // DMTC2
1474 UINT64_C(1218445312), // DMTC2_OCTEON
1475 UINT64_C(1080034048), // DMTGC0
1476 UINT64_C(220), // DMUH
1477 UINT64_C(221), // DMUHU
1478 UINT64_C(1879048195), // DMUL
1479 UINT64_C(28), // DMULT
1480 UINT64_C(29), // DMULTu
1481 UINT64_C(157), // DMULU
1482 UINT64_C(156), // DMUL_R6
1483 UINT64_C(2019557395), // DOTP_S_D
1484 UINT64_C(2015363091), // DOTP_S_H
1485 UINT64_C(2017460243), // DOTP_S_W
1486 UINT64_C(2027946003), // DOTP_U_D
1487 UINT64_C(2023751699), // DOTP_U_H
1488 UINT64_C(2025848851), // DOTP_U_W
1489 UINT64_C(2036334611), // DPADD_S_D
1490 UINT64_C(2032140307), // DPADD_S_H
1491 UINT64_C(2034237459), // DPADD_S_W
1492 UINT64_C(2044723219), // DPADD_U_D
1493 UINT64_C(2040528915), // DPADD_U_H
1494 UINT64_C(2042626067), // DPADD_U_W
1495 UINT64_C(2080376496), // DPAQX_SA_W_PH
1496 UINT64_C(12988), // DPAQX_SA_W_PH_MMR2
1497 UINT64_C(2080376368), // DPAQX_S_W_PH
1498 UINT64_C(8892), // DPAQX_S_W_PH_MMR2
1499 UINT64_C(2080375600), // DPAQ_SA_L_W
1500 UINT64_C(4796), // DPAQ_SA_L_W_MM
1501 UINT64_C(2080375088), // DPAQ_S_W_PH
1502 UINT64_C(700), // DPAQ_S_W_PH_MM
1503 UINT64_C(2080375024), // DPAU_H_QBL
1504 UINT64_C(8380), // DPAU_H_QBL_MM
1505 UINT64_C(2080375280), // DPAU_H_QBR
1506 UINT64_C(12476), // DPAU_H_QBR_MM
1507 UINT64_C(2080375344), // DPAX_W_PH
1508 UINT64_C(4284), // DPAX_W_PH_MMR2
1509 UINT64_C(2080374832), // DPA_W_PH
1510 UINT64_C(188), // DPA_W_PH_MMR2
1511 UINT64_C(1879048237), // DPOP
1512 UINT64_C(2080376560), // DPSQX_SA_W_PH
1513 UINT64_C(14012), // DPSQX_SA_W_PH_MMR2
1514 UINT64_C(2080376432), // DPSQX_S_W_PH
1515 UINT64_C(9916), // DPSQX_S_W_PH_MMR2
1516 UINT64_C(2080375664), // DPSQ_SA_L_W
1517 UINT64_C(5820), // DPSQ_SA_L_W_MM
1518 UINT64_C(2080375152), // DPSQ_S_W_PH
1519 UINT64_C(1724), // DPSQ_S_W_PH_MM
1520 UINT64_C(2053111827), // DPSUB_S_D
1521 UINT64_C(2048917523), // DPSUB_S_H
1522 UINT64_C(2051014675), // DPSUB_S_W
1523 UINT64_C(2061500435), // DPSUB_U_D
1524 UINT64_C(2057306131), // DPSUB_U_H
1525 UINT64_C(2059403283), // DPSUB_U_W
1526 UINT64_C(2080375536), // DPSU_H_QBL
1527 UINT64_C(9404), // DPSU_H_QBL_MM
1528 UINT64_C(2080375792), // DPSU_H_QBR
1529 UINT64_C(13500), // DPSU_H_QBR_MM
1530 UINT64_C(2080375408), // DPSX_W_PH
1531 UINT64_C(5308), // DPSX_W_PH_MMR2
1532 UINT64_C(2080374896), // DPS_W_PH
1533 UINT64_C(1212), // DPS_W_PH_MMR2
1534 UINT64_C(2097210), // DROTR
1535 UINT64_C(2097214), // DROTR32
1536 UINT64_C(86), // DROTRV
1537 UINT64_C(2080374948), // DSBH
1538 UINT64_C(30), // DSDIV
1539 UINT64_C(2080375140), // DSHD
1540 UINT64_C(56), // DSLL
1541 UINT64_C(60), // DSLL32
1542 UINT64_C(60), // DSLL64_32
1543 UINT64_C(20), // DSLLV
1544 UINT64_C(59), // DSRA
1545 UINT64_C(63), // DSRA32
1546 UINT64_C(23), // DSRAV
1547 UINT64_C(58), // DSRL
1548 UINT64_C(62), // DSRL32
1549 UINT64_C(22), // DSRLV
1550 UINT64_C(46), // DSUB
1551 UINT64_C(47), // DSUBu
1552 UINT64_C(31), // DUDIV
1553 UINT64_C(1096810532), // DVP
1554 UINT64_C(1096810497), // DVPE
1555 UINT64_C(6524), // DVP_MMR6
1556 UINT64_C(59418), // DivRxRy16
1557 UINT64_C(59419), // DivuRxRy16
1558 UINT64_C(192), // EHB
1559 UINT64_C(6144), // EHB_MM
1560 UINT64_C(6144), // EHB_MMR6
1561 UINT64_C(1096835104), // EI
1562 UINT64_C(22396), // EI_MM
1563 UINT64_C(22396), // EI_MMR6
1564 UINT64_C(1096813537), // EMT
1565 UINT64_C(1107296280), // ERET
1566 UINT64_C(1107296344), // ERETNC
1567 UINT64_C(127868), // ERETNC_MMR6
1568 UINT64_C(62332), // ERET_MM
1569 UINT64_C(62332), // ERET_MMR6
1570 UINT64_C(1096810500), // EVP
1571 UINT64_C(1096810529), // EVPE
1572 UINT64_C(14716), // EVP_MMR6
1573 UINT64_C(2080374784), // EXT
1574 UINT64_C(2080374968), // EXTP
1575 UINT64_C(2080375480), // EXTPDP
1576 UINT64_C(2080375544), // EXTPDPV
1577 UINT64_C(14524), // EXTPDPV_MM
1578 UINT64_C(13948), // EXTPDP_MM
1579 UINT64_C(2080375032), // EXTPV
1580 UINT64_C(10428), // EXTPV_MM
1581 UINT64_C(9852), // EXTP_MM
1582 UINT64_C(2080375288), // EXTRV_RS_W
1583 UINT64_C(11964), // EXTRV_RS_W_MM
1584 UINT64_C(2080375160), // EXTRV_R_W
1585 UINT64_C(7868), // EXTRV_R_W_MM
1586 UINT64_C(2080375800), // EXTRV_S_H
1587 UINT64_C(16060), // EXTRV_S_H_MM
1588 UINT64_C(2080374904), // EXTRV_W
1589 UINT64_C(3772), // EXTRV_W_MM
1590 UINT64_C(2080375224), // EXTR_RS_W
1591 UINT64_C(11900), // EXTR_RS_W_MM
1592 UINT64_C(2080375096), // EXTR_R_W
1593 UINT64_C(7804), // EXTR_R_W_MM
1594 UINT64_C(2080375736), // EXTR_S_H
1595 UINT64_C(15996), // EXTR_S_H_MM
1596 UINT64_C(2080374840), // EXTR_W
1597 UINT64_C(3708), // EXTR_W_MM
1598 UINT64_C(1879048250), // EXTS
1599 UINT64_C(1879048251), // EXTS32
1600 UINT64_C(44), // EXT_MM
1601 UINT64_C(44), // EXT_MMR6
1602 UINT64_C(1176502277), // FABS_D32
1603 UINT64_C(1409295227), // FABS_D32_MM
1604 UINT64_C(1176502277), // FABS_D64
1605 UINT64_C(1409295227), // FABS_D64_MM
1606 UINT64_C(1174405125), // FABS_S
1607 UINT64_C(1409287035), // FABS_S_MM
1608 UINT64_C(2015363099), // FADD_D
1609 UINT64_C(1176502272), // FADD_D32
1610 UINT64_C(1409286448), // FADD_D32_MM
1611 UINT64_C(1176502272), // FADD_D64
1612 UINT64_C(1409286448), // FADD_D64_MM
1613 UINT64_C(1186988032), // FADD_PS64
1614 UINT64_C(1174405120), // FADD_S
1615 UINT64_C(1409286192), // FADD_S_MM
1616 UINT64_C(1409286192), // FADD_S_MMR6
1617 UINT64_C(2013265947), // FADD_W
1618 UINT64_C(2015363098), // FCAF_D
1619 UINT64_C(2013265946), // FCAF_W
1620 UINT64_C(2023751706), // FCEQ_D
1621 UINT64_C(2021654554), // FCEQ_W
1622 UINT64_C(2065760286), // FCLASS_D
1623 UINT64_C(2065694750), // FCLASS_W
1624 UINT64_C(2040528922), // FCLE_D
1625 UINT64_C(2038431770), // FCLE_W
1626 UINT64_C(2032140314), // FCLT_D
1627 UINT64_C(2030043162), // FCLT_W
1628 UINT64_C(1176502320), // FCMP_D32
1629 UINT64_C(1409287228), // FCMP_D32_MM
1630 UINT64_C(1176502320), // FCMP_D64
1631 UINT64_C(1174405168), // FCMP_S32
1632 UINT64_C(1409286204), // FCMP_S32_MM
1633 UINT64_C(2027946012), // FCNE_D
1634 UINT64_C(2025848860), // FCNE_W
1635 UINT64_C(2019557404), // FCOR_D
1636 UINT64_C(2017460252), // FCOR_W
1637 UINT64_C(2027946010), // FCUEQ_D
1638 UINT64_C(2025848858), // FCUEQ_W
1639 UINT64_C(2044723226), // FCULE_D
1640 UINT64_C(2042626074), // FCULE_W
1641 UINT64_C(2036334618), // FCULT_D
1642 UINT64_C(2034237466), // FCULT_W
1643 UINT64_C(2023751708), // FCUNE_D
1644 UINT64_C(2021654556), // FCUNE_W
1645 UINT64_C(2019557402), // FCUN_D
1646 UINT64_C(2017460250), // FCUN_W
1647 UINT64_C(2027946011), // FDIV_D
1648 UINT64_C(1176502275), // FDIV_D32
1649 UINT64_C(1409286640), // FDIV_D32_MM
1650 UINT64_C(1176502275), // FDIV_D64
1651 UINT64_C(1409286640), // FDIV_D64_MM
1652 UINT64_C(1174405123), // FDIV_S
1653 UINT64_C(1409286384), // FDIV_S_MM
1654 UINT64_C(1409286384), // FDIV_S_MMR6
1655 UINT64_C(2025848859), // FDIV_W
1656 UINT64_C(2046820379), // FEXDO_H
1657 UINT64_C(2048917531), // FEXDO_W
1658 UINT64_C(2044723227), // FEXP2_D
1659 UINT64_C(2042626075), // FEXP2_W
1660 UINT64_C(2066808862), // FEXUPL_D
1661 UINT64_C(2066743326), // FEXUPL_W
1662 UINT64_C(2066939934), // FEXUPR_D
1663 UINT64_C(2066874398), // FEXUPR_W
1664 UINT64_C(2067595294), // FFINT_S_D
1665 UINT64_C(2067529758), // FFINT_S_W
1666 UINT64_C(2067726366), // FFINT_U_D
1667 UINT64_C(2067660830), // FFINT_U_W
1668 UINT64_C(2067071006), // FFQL_D
1669 UINT64_C(2067005470), // FFQL_W
1670 UINT64_C(2067202078), // FFQR_D
1671 UINT64_C(2067136542), // FFQR_W
1672 UINT64_C(2063597598), // FILL_B
1673 UINT64_C(2063794206), // FILL_D
1674 UINT64_C(2063663134), // FILL_H
1675 UINT64_C(2063728670), // FILL_W
1676 UINT64_C(2066677790), // FLOG2_D
1677 UINT64_C(2066612254), // FLOG2_W
1678 UINT64_C(1176502283), // FLOOR_L_D64
1679 UINT64_C(1409303355), // FLOOR_L_D_MMR6
1680 UINT64_C(1174405131), // FLOOR_L_S
1681 UINT64_C(1409286971), // FLOOR_L_S_MMR6
1682 UINT64_C(1176502287), // FLOOR_W_D32
1683 UINT64_C(1176502287), // FLOOR_W_D64
1684 UINT64_C(1409305403), // FLOOR_W_D_MMR6
1685 UINT64_C(1409305403), // FLOOR_W_MM
1686 UINT64_C(1174405135), // FLOOR_W_S
1687 UINT64_C(1409289019), // FLOOR_W_S_MM
1688 UINT64_C(1409289019), // FLOOR_W_S_MMR6
1689 UINT64_C(2032140315), // FMADD_D
1690 UINT64_C(2030043163), // FMADD_W
1691 UINT64_C(2078277659), // FMAX_A_D
1692 UINT64_C(2076180507), // FMAX_A_W
1693 UINT64_C(2074083355), // FMAX_D
1694 UINT64_C(2071986203), // FMAX_W
1695 UINT64_C(2069889051), // FMIN_A_D
1696 UINT64_C(2067791899), // FMIN_A_W
1697 UINT64_C(2065694747), // FMIN_D
1698 UINT64_C(2063597595), // FMIN_W
1699 UINT64_C(1176502278), // FMOV_D32
1700 UINT64_C(1409294459), // FMOV_D32_MM
1701 UINT64_C(1176502278), // FMOV_D64
1702 UINT64_C(1409294459), // FMOV_D64_MM
1703 UINT64_C(1409294459), // FMOV_D_MMR6
1704 UINT64_C(1174405126), // FMOV_S
1705 UINT64_C(1409286267), // FMOV_S_MM
1706 UINT64_C(1409286267), // FMOV_S_MMR6
1707 UINT64_C(2036334619), // FMSUB_D
1708 UINT64_C(2034237467), // FMSUB_W
1709 UINT64_C(2023751707), // FMUL_D
1710 UINT64_C(1176502274), // FMUL_D32
1711 UINT64_C(1409286576), // FMUL_D32_MM
1712 UINT64_C(1176502274), // FMUL_D64
1713 UINT64_C(1409286576), // FMUL_D64_MM
1714 UINT64_C(1186988034), // FMUL_PS64
1715 UINT64_C(1174405122), // FMUL_S
1716 UINT64_C(1409286320), // FMUL_S_MM
1717 UINT64_C(1409286320), // FMUL_S_MMR6
1718 UINT64_C(2021654555), // FMUL_W
1719 UINT64_C(1176502279), // FNEG_D32
1720 UINT64_C(1409297275), // FNEG_D32_MM
1721 UINT64_C(1176502279), // FNEG_D64
1722 UINT64_C(1409297275), // FNEG_D64_MM
1723 UINT64_C(1174405127), // FNEG_S
1724 UINT64_C(1409289083), // FNEG_S_MM
1725 UINT64_C(1409289083), // FNEG_S_MMR6
1726 UINT64_C(2080374792), // FORK
1727 UINT64_C(2066415646), // FRCP_D
1728 UINT64_C(2066350110), // FRCP_W
1729 UINT64_C(2066546718), // FRINT_D
1730 UINT64_C(2066481182), // FRINT_W
1731 UINT64_C(2066284574), // FRSQRT_D
1732 UINT64_C(2066219038), // FRSQRT_W
1733 UINT64_C(2048917530), // FSAF_D
1734 UINT64_C(2046820378), // FSAF_W
1735 UINT64_C(2057306138), // FSEQ_D
1736 UINT64_C(2055208986), // FSEQ_W
1737 UINT64_C(2074083354), // FSLE_D
1738 UINT64_C(2071986202), // FSLE_W
1739 UINT64_C(2065694746), // FSLT_D
1740 UINT64_C(2063597594), // FSLT_W
1741 UINT64_C(2061500444), // FSNE_D
1742 UINT64_C(2059403292), // FSNE_W
1743 UINT64_C(2053111836), // FSOR_D
1744 UINT64_C(2051014684), // FSOR_W
1745 UINT64_C(2066153502), // FSQRT_D
1746 UINT64_C(1176502276), // FSQRT_D32
1747 UINT64_C(1409305147), // FSQRT_D32_MM
1748 UINT64_C(1176502276), // FSQRT_D64
1749 UINT64_C(1409305147), // FSQRT_D64_MM
1750 UINT64_C(1174405124), // FSQRT_S
1751 UINT64_C(1409288763), // FSQRT_S_MM
1752 UINT64_C(2066087966), // FSQRT_W
1753 UINT64_C(2019557403), // FSUB_D
1754 UINT64_C(1176502273), // FSUB_D32
1755 UINT64_C(1409286512), // FSUB_D32_MM
1756 UINT64_C(1176502273), // FSUB_D64
1757 UINT64_C(1409286512), // FSUB_D64_MM
1758 UINT64_C(1186988033), // FSUB_PS64
1759 UINT64_C(1174405121), // FSUB_S
1760 UINT64_C(1409286256), // FSUB_S_MM
1761 UINT64_C(1409286256), // FSUB_S_MMR6
1762 UINT64_C(2017460251), // FSUB_W
1763 UINT64_C(2061500442), // FSUEQ_D
1764 UINT64_C(2059403290), // FSUEQ_W
1765 UINT64_C(2078277658), // FSULE_D
1766 UINT64_C(2076180506), // FSULE_W
1767 UINT64_C(2069889050), // FSULT_D
1768 UINT64_C(2067791898), // FSULT_W
1769 UINT64_C(2057306140), // FSUNE_D
1770 UINT64_C(2055208988), // FSUNE_W
1771 UINT64_C(2053111834), // FSUN_D
1772 UINT64_C(2051014682), // FSUN_W
1773 UINT64_C(2067333150), // FTINT_S_D
1774 UINT64_C(2067267614), // FTINT_S_W
1775 UINT64_C(2067464222), // FTINT_U_D
1776 UINT64_C(2067398686), // FTINT_U_W
1777 UINT64_C(2055208987), // FTQ_H
1778 UINT64_C(2057306139), // FTQ_W
1779 UINT64_C(2065891358), // FTRUNC_S_D
1780 UINT64_C(2065825822), // FTRUNC_S_W
1781 UINT64_C(2066022430), // FTRUNC_U_D
1782 UINT64_C(2065956894), // FTRUNC_U_W
1783 UINT64_C(2080374845), // GINVI
1784 UINT64_C(24956), // GINVI_MMR6
1785 UINT64_C(2080374973), // GINVT
1786 UINT64_C(29052), // GINVT_MMR6
1787 UINT64_C(2053111829), // HADD_S_D
1788 UINT64_C(2048917525), // HADD_S_H
1789 UINT64_C(2051014677), // HADD_S_W
1790 UINT64_C(2061500437), // HADD_U_D
1791 UINT64_C(2057306133), // HADD_U_H
1792 UINT64_C(2059403285), // HADD_U_W
1793 UINT64_C(2069889045), // HSUB_S_D
1794 UINT64_C(2065694741), // HSUB_S_H
1795 UINT64_C(2067791893), // HSUB_S_W
1796 UINT64_C(2078277653), // HSUB_U_D
1797 UINT64_C(2074083349), // HSUB_U_H
1798 UINT64_C(2076180501), // HSUB_U_W
1799 UINT64_C(1107296296), // HYPCALL
1800 UINT64_C(50044), // HYPCALL_MM
1801 UINT64_C(2063597588), // ILVEV_B
1802 UINT64_C(2069889044), // ILVEV_D
1803 UINT64_C(2065694740), // ILVEV_H
1804 UINT64_C(2067791892), // ILVEV_W
1805 UINT64_C(2046820372), // ILVL_B
1806 UINT64_C(2053111828), // ILVL_D
1807 UINT64_C(2048917524), // ILVL_H
1808 UINT64_C(2051014676), // ILVL_W
1809 UINT64_C(2071986196), // ILVOD_B
1810 UINT64_C(2078277652), // ILVOD_D
1811 UINT64_C(2074083348), // ILVOD_H
1812 UINT64_C(2076180500), // ILVOD_W
1813 UINT64_C(2055208980), // ILVR_B
1814 UINT64_C(2061500436), // ILVR_D
1815 UINT64_C(2057306132), // ILVR_H
1816 UINT64_C(2059403284), // ILVR_W
1817 UINT64_C(2080374788), // INS
1818 UINT64_C(2030043161), // INSERT_B
1819 UINT64_C(2033713177), // INSERT_D
1820 UINT64_C(2032140313), // INSERT_H
1821 UINT64_C(2033188889), // INSERT_W
1822 UINT64_C(2080374796), // INSV
1823 UINT64_C(2034237465), // INSVE_B
1824 UINT64_C(2037907481), // INSVE_D
1825 UINT64_C(2036334617), // INSVE_H
1826 UINT64_C(2037383193), // INSVE_W
1827 UINT64_C(16700), // INSV_MM
1828 UINT64_C(12), // INS_MM
1829 UINT64_C(12), // INS_MMR6
1830 UINT64_C(134217728), // J
1831 UINT64_C(201326592), // JAL
1832 UINT64_C(9), // JALR
1833 UINT64_C(17856), // JALR16_MM
1834 UINT64_C(9), // JALR64
1835 UINT64_C(17419), // JALRC16_MMR6
1836 UINT64_C(7996), // JALRC_HB_MMR6
1837 UINT64_C(3900), // JALRC_MMR6
1838 UINT64_C(17888), // JALRS16_MM
1839 UINT64_C(20284), // JALRS_MM
1840 UINT64_C(1033), // JALR_HB
1841 UINT64_C(1033), // JALR_HB64
1842 UINT64_C(3900), // JALR_MM
1843 UINT64_C(1946157056), // JALS_MM
1844 UINT64_C(1946157056), // JALX
1845 UINT64_C(4026531840), // JALX_MM
1846 UINT64_C(4093640704), // JAL_MM
1847 UINT64_C(4160749568), // JIALC
1848 UINT64_C(4160749568), // JIALC64
1849 UINT64_C(2147483648), // JIALC_MMR6
1850 UINT64_C(3623878656), // JIC
1851 UINT64_C(3623878656), // JIC64
1852 UINT64_C(2684354560), // JIC_MMR6
1853 UINT64_C(8), // JR
1854 UINT64_C(17792), // JR16_MM
1855 UINT64_C(8), // JR64
1856 UINT64_C(18176), // JRADDIUSP
1857 UINT64_C(17824), // JRC16_MM
1858 UINT64_C(17411), // JRC16_MMR6
1859 UINT64_C(17427), // JRCADDIUSP_MMR6
1860 UINT64_C(1032), // JR_HB
1861 UINT64_C(1032), // JR_HB64
1862 UINT64_C(1033), // JR_HB64_R6
1863 UINT64_C(1033), // JR_HB_R6
1864 UINT64_C(3900), // JR_MM
1865 UINT64_C(3556769792), // J_MM
1866 UINT64_C(402653184), // Jal16
1867 UINT64_C(402653184), // JalB16
1868 UINT64_C(59424), // JrRa16
1869 UINT64_C(59616), // JrcRa16
1870 UINT64_C(59584), // JrcRx16
1871 UINT64_C(59392), // JumpLinkReg16
1872 UINT64_C(2147483648), // LB
1873 UINT64_C(2147483648), // LB64
1874 UINT64_C(2080374828), // LBE
1875 UINT64_C(1610639360), // LBE_MM
1876 UINT64_C(2048), // LBU16_MM
1877 UINT64_C(2080375178), // LBUX
1878 UINT64_C(549), // LBUX_MM
1879 UINT64_C(335544320), // LBU_MMR6
1880 UINT64_C(469762048), // LB_MM
1881 UINT64_C(469762048), // LB_MMR6
1882 UINT64_C(2415919104), // LBu
1883 UINT64_C(2415919104), // LBu64
1884 UINT64_C(2080374824), // LBuE
1885 UINT64_C(1610637312), // LBuE_MM
1886 UINT64_C(335544320), // LBu_MM
1887 UINT64_C(3690987520), // LD
1888 UINT64_C(3556769792), // LDC1
1889 UINT64_C(3556769792), // LDC164
1890 UINT64_C(3154116608), // LDC1_D64_MMR6
1891 UINT64_C(3154116608), // LDC1_MM_D32
1892 UINT64_C(3154116608), // LDC1_MM_D64
1893 UINT64_C(3623878656), // LDC2
1894 UINT64_C(536879104), // LDC2_MMR6
1895 UINT64_C(1237319680), // LDC2_R6
1896 UINT64_C(3690987520), // LDC3
1897 UINT64_C(2063597575), // LDI_B
1898 UINT64_C(2069889031), // LDI_D
1899 UINT64_C(2065694727), // LDI_H
1900 UINT64_C(2067791879), // LDI_W
1901 UINT64_C(1744830464), // LDL
1902 UINT64_C(3960995840), // LDPC
1903 UINT64_C(1811939328), // LDR
1904 UINT64_C(1275068417), // LDXC1
1905 UINT64_C(1275068417), // LDXC164
1906 UINT64_C(2013265952), // LD_B
1907 UINT64_C(2013265955), // LD_D
1908 UINT64_C(2013265953), // LD_H
1909 UINT64_C(2013265954), // LD_W
1910 UINT64_C(603979776), // LEA_ADDiu
1911 UINT64_C(1677721600), // LEA_ADDiu64
1912 UINT64_C(805306368), // LEA_ADDiu_MM
1913 UINT64_C(2214592512), // LH
1914 UINT64_C(2214592512), // LH64
1915 UINT64_C(2080374829), // LHE
1916 UINT64_C(1610639872), // LHE_MM
1917 UINT64_C(10240), // LHU16_MM
1918 UINT64_C(2080375050), // LHX
1919 UINT64_C(357), // LHX_MM
1920 UINT64_C(1006632960), // LH_MM
1921 UINT64_C(2483027968), // LHu
1922 UINT64_C(2483027968), // LHu64
1923 UINT64_C(2080374825), // LHuE
1924 UINT64_C(1610637824), // LHuE_MM
1925 UINT64_C(872415232), // LHu_MM
1926 UINT64_C(60416), // LI16_MM
1927 UINT64_C(60416), // LI16_MMR6
1928 UINT64_C(3221225472), // LL
1929 UINT64_C(3221225472), // LL64
1930 UINT64_C(2080374838), // LL64_R6
1931 UINT64_C(3489660928), // LLD
1932 UINT64_C(2080374839), // LLD_R6
1933 UINT64_C(2080374830), // LLE
1934 UINT64_C(1610640384), // LLE_MM
1935 UINT64_C(1610625024), // LL_MM
1936 UINT64_C(1610625024), // LL_MMR6
1937 UINT64_C(2080374838), // LL_R6
1938 UINT64_C(5), // LSA
1939 UINT64_C(15), // LSA_MMR6
1940 UINT64_C(5), // LSA_R6
1941 UINT64_C(268435456), // LUI_MMR6
1942 UINT64_C(1275068421), // LUXC1
1943 UINT64_C(1275068421), // LUXC164
1944 UINT64_C(1409286472), // LUXC1_MM
1945 UINT64_C(1006632960), // LUi
1946 UINT64_C(1006632960), // LUi64
1947 UINT64_C(1101004800), // LUi_MM
1948 UINT64_C(2348810240), // LW
1949 UINT64_C(26624), // LW16_MM
1950 UINT64_C(2348810240), // LW64
1951 UINT64_C(3288334336), // LWC1
1952 UINT64_C(2617245696), // LWC1_MM
1953 UINT64_C(3355443200), // LWC2
1954 UINT64_C(536870912), // LWC2_MMR6
1955 UINT64_C(1228931072), // LWC2_R6
1956 UINT64_C(3422552064), // LWC3
1957 UINT64_C(2348810240), // LWDSP
1958 UINT64_C(4227858432), // LWDSP_MM
1959 UINT64_C(2080374831), // LWE
1960 UINT64_C(1610640896), // LWE_MM
1961 UINT64_C(25600), // LWGP_MM
1962 UINT64_C(2281701376), // LWL
1963 UINT64_C(2281701376), // LWL64
1964 UINT64_C(2080374809), // LWLE
1965 UINT64_C(1610638336), // LWLE_MM
1966 UINT64_C(1610612736), // LWL_MM
1967 UINT64_C(17664), // LWM16_MM
1968 UINT64_C(17410), // LWM16_MMR6
1969 UINT64_C(536891392), // LWM32_MM
1970 UINT64_C(3959947264), // LWPC
1971 UINT64_C(2013790208), // LWPC_MMR6
1972 UINT64_C(536875008), // LWP_MM
1973 UINT64_C(2550136832), // LWR
1974 UINT64_C(2550136832), // LWR64
1975 UINT64_C(2080374810), // LWRE
1976 UINT64_C(1610638848), // LWRE_MM
1977 UINT64_C(1610616832), // LWR_MM
1978 UINT64_C(18432), // LWSP_MM
1979 UINT64_C(3960471552), // LWUPC
1980 UINT64_C(1610670080), // LWU_MM
1981 UINT64_C(2080374794), // LWX
1982 UINT64_C(1275068416), // LWXC1
1983 UINT64_C(1409286216), // LWXC1_MM
1984 UINT64_C(280), // LWXS_MM
1985 UINT64_C(421), // LWX_MM
1986 UINT64_C(4227858432), // LW_MM
1987 UINT64_C(4227858432), // LW_MMR6
1988 UINT64_C(2617245696), // LWu
1989 UINT64_C(4026570752), // LbRxRyOffMemX16
1990 UINT64_C(4026572800), // LbuRxRyOffMemX16
1991 UINT64_C(4026572800), // LhRxRyOffMemX16
1992 UINT64_C(4026572800), // LhuRxRyOffMemX16
1993 UINT64_C(26624), // LiRxImm16
1994 UINT64_C(4026558464), // LiRxImmAlignX16
1995 UINT64_C(4026558464), // LiRxImmX16
1996 UINT64_C(45056), // LwRxPcTcp16
1997 UINT64_C(4026576896), // LwRxPcTcpX16
1998 UINT64_C(4026570752), // LwRxRyOffMemX16
1999 UINT64_C(4026568704), // LwRxSpImmX16
2000 UINT64_C(1879048192), // MADD
2001 UINT64_C(1176502296), // MADDF_D
2002 UINT64_C(1409287096), // MADDF_D_MMR6
2003 UINT64_C(1174405144), // MADDF_S
2004 UINT64_C(1409286584), // MADDF_S_MMR6
2005 UINT64_C(2067791900), // MADDR_Q_H
2006 UINT64_C(2069889052), // MADDR_Q_W
2007 UINT64_C(1879048193), // MADDU
2008 UINT64_C(1879048193), // MADDU_DSP
2009 UINT64_C(6844), // MADDU_DSP_MM
2010 UINT64_C(56124), // MADDU_MM
2011 UINT64_C(2021654546), // MADDV_B
2012 UINT64_C(2027946002), // MADDV_D
2013 UINT64_C(2023751698), // MADDV_H
2014 UINT64_C(2025848850), // MADDV_W
2015 UINT64_C(1275068449), // MADD_D32
2016 UINT64_C(1409286153), // MADD_D32_MM
2017 UINT64_C(1275068449), // MADD_D64
2018 UINT64_C(1879048192), // MADD_DSP
2019 UINT64_C(2748), // MADD_DSP_MM
2020 UINT64_C(52028), // MADD_MM
2021 UINT64_C(2034237468), // MADD_Q_H
2022 UINT64_C(2036334620), // MADD_Q_W
2023 UINT64_C(1275068448), // MADD_S
2024 UINT64_C(1409286145), // MADD_S_MM
2025 UINT64_C(2080375856), // MAQ_SA_W_PHL
2026 UINT64_C(14972), // MAQ_SA_W_PHL_MM
2027 UINT64_C(2080375984), // MAQ_SA_W_PHR
2028 UINT64_C(10876), // MAQ_SA_W_PHR_MM
2029 UINT64_C(2080376112), // MAQ_S_W_PHL
2030 UINT64_C(6780), // MAQ_S_W_PHL_MM
2031 UINT64_C(2080376240), // MAQ_S_W_PHR
2032 UINT64_C(2684), // MAQ_S_W_PHR_MM
2033 UINT64_C(1176502303), // MAXA_D
2034 UINT64_C(1409286699), // MAXA_D_MMR6
2035 UINT64_C(1174405151), // MAXA_S
2036 UINT64_C(1409286187), // MAXA_S_MMR6
2037 UINT64_C(2030043142), // MAXI_S_B
2038 UINT64_C(2036334598), // MAXI_S_D
2039 UINT64_C(2032140294), // MAXI_S_H
2040 UINT64_C(2034237446), // MAXI_S_W
2041 UINT64_C(2038431750), // MAXI_U_B
2042 UINT64_C(2044723206), // MAXI_U_D
2043 UINT64_C(2040528902), // MAXI_U_H
2044 UINT64_C(2042626054), // MAXI_U_W
2045 UINT64_C(2063597582), // MAX_A_B
2046 UINT64_C(2069889038), // MAX_A_D
2047 UINT64_C(2065694734), // MAX_A_H
2048 UINT64_C(2067791886), // MAX_A_W
2049 UINT64_C(1176502302), // MAX_D
2050 UINT64_C(1409286667), // MAX_D_MMR6
2051 UINT64_C(1174405150), // MAX_S
2052 UINT64_C(2030043150), // MAX_S_B
2053 UINT64_C(2036334606), // MAX_S_D
2054 UINT64_C(2032140302), // MAX_S_H
2055 UINT64_C(1409286155), // MAX_S_MMR6
2056 UINT64_C(2034237454), // MAX_S_W
2057 UINT64_C(2038431758), // MAX_U_B
2058 UINT64_C(2044723214), // MAX_U_D
2059 UINT64_C(2040528910), // MAX_U_H
2060 UINT64_C(2042626062), // MAX_U_W
2061 UINT64_C(1073741824), // MFC0
2062 UINT64_C(252), // MFC0_MMR6
2063 UINT64_C(1140850688), // MFC1
2064 UINT64_C(1140850688), // MFC1_D64
2065 UINT64_C(1409294395), // MFC1_MM
2066 UINT64_C(1409294395), // MFC1_MMR6
2067 UINT64_C(1207959552), // MFC2
2068 UINT64_C(19772), // MFC2_MMR6
2069 UINT64_C(1080033280), // MFGC0
2070 UINT64_C(1276), // MFGC0_MM
2071 UINT64_C(244), // MFHC0_MMR6
2072 UINT64_C(1147142144), // MFHC1_D32
2073 UINT64_C(1409298491), // MFHC1_D32_MM
2074 UINT64_C(1147142144), // MFHC1_D64
2075 UINT64_C(1409298491), // MFHC1_D64_MM
2076 UINT64_C(36156), // MFHC2_MMR6
2077 UINT64_C(1080034304), // MFHGC0
2078 UINT64_C(1268), // MFHGC0_MM
2079 UINT64_C(16), // MFHI
2080 UINT64_C(17920), // MFHI16_MM
2081 UINT64_C(16), // MFHI64
2082 UINT64_C(16), // MFHI_DSP
2083 UINT64_C(124), // MFHI_DSP_MM
2084 UINT64_C(3452), // MFHI_MM
2085 UINT64_C(18), // MFLO
2086 UINT64_C(17984), // MFLO16_MM
2087 UINT64_C(18), // MFLO64
2088 UINT64_C(18), // MFLO_DSP
2089 UINT64_C(4220), // MFLO_DSP_MM
2090 UINT64_C(7548), // MFLO_MM
2091 UINT64_C(1090519040), // MFTR
2092 UINT64_C(1176502301), // MINA_D
2093 UINT64_C(1409286691), // MINA_D_MMR6
2094 UINT64_C(1174405149), // MINA_S
2095 UINT64_C(1409286179), // MINA_S_MMR6
2096 UINT64_C(2046820358), // MINI_S_B
2097 UINT64_C(2053111814), // MINI_S_D
2098 UINT64_C(2048917510), // MINI_S_H
2099 UINT64_C(2051014662), // MINI_S_W
2100 UINT64_C(2055208966), // MINI_U_B
2101 UINT64_C(2061500422), // MINI_U_D
2102 UINT64_C(2057306118), // MINI_U_H
2103 UINT64_C(2059403270), // MINI_U_W
2104 UINT64_C(2071986190), // MIN_A_B
2105 UINT64_C(2078277646), // MIN_A_D
2106 UINT64_C(2074083342), // MIN_A_H
2107 UINT64_C(2076180494), // MIN_A_W
2108 UINT64_C(1176502300), // MIN_D
2109 UINT64_C(1409286659), // MIN_D_MMR6
2110 UINT64_C(1174405148), // MIN_S
2111 UINT64_C(2046820366), // MIN_S_B
2112 UINT64_C(2053111822), // MIN_S_D
2113 UINT64_C(2048917518), // MIN_S_H
2114 UINT64_C(1409286147), // MIN_S_MMR6
2115 UINT64_C(2051014670), // MIN_S_W
2116 UINT64_C(2055208974), // MIN_U_B
2117 UINT64_C(2061500430), // MIN_U_D
2118 UINT64_C(2057306126), // MIN_U_H
2119 UINT64_C(2059403278), // MIN_U_W
2120 UINT64_C(218), // MOD
2121 UINT64_C(2080375952), // MODSUB
2122 UINT64_C(661), // MODSUB_MM
2123 UINT64_C(219), // MODU
2124 UINT64_C(472), // MODU_MMR6
2125 UINT64_C(344), // MOD_MMR6
2126 UINT64_C(2063597586), // MOD_S_B
2127 UINT64_C(2069889042), // MOD_S_D
2128 UINT64_C(2065694738), // MOD_S_H
2129 UINT64_C(2067791890), // MOD_S_W
2130 UINT64_C(2071986194), // MOD_U_B
2131 UINT64_C(2078277650), // MOD_U_D
2132 UINT64_C(2074083346), // MOD_U_H
2133 UINT64_C(2076180498), // MOD_U_W
2134 UINT64_C(3072), // MOVE16_MM
2135 UINT64_C(3072), // MOVE16_MMR6
2136 UINT64_C(33792), // MOVEP_MM
2137 UINT64_C(17412), // MOVEP_MMR6
2138 UINT64_C(2025717785), // MOVE_V
2139 UINT64_C(1176502289), // MOVF_D32
2140 UINT64_C(1409286688), // MOVF_D32_MM
2141 UINT64_C(1176502289), // MOVF_D64
2142 UINT64_C(1), // MOVF_I
2143 UINT64_C(1), // MOVF_I64
2144 UINT64_C(1409286523), // MOVF_I_MM
2145 UINT64_C(1174405137), // MOVF_S
2146 UINT64_C(1409286176), // MOVF_S_MM
2147 UINT64_C(1176502291), // MOVN_I64_D64
2148 UINT64_C(11), // MOVN_I64_I
2149 UINT64_C(11), // MOVN_I64_I64
2150 UINT64_C(1174405139), // MOVN_I64_S
2151 UINT64_C(1176502291), // MOVN_I_D32
2152 UINT64_C(1409286456), // MOVN_I_D32_MM
2153 UINT64_C(1176502291), // MOVN_I_D64
2154 UINT64_C(11), // MOVN_I_I
2155 UINT64_C(11), // MOVN_I_I64
2156 UINT64_C(24), // MOVN_I_MM
2157 UINT64_C(1174405139), // MOVN_I_S
2158 UINT64_C(1409286200), // MOVN_I_S_MM
2159 UINT64_C(1176567825), // MOVT_D32
2160 UINT64_C(1409286752), // MOVT_D32_MM
2161 UINT64_C(1176567825), // MOVT_D64
2162 UINT64_C(65537), // MOVT_I
2163 UINT64_C(65537), // MOVT_I64
2164 UINT64_C(1409288571), // MOVT_I_MM
2165 UINT64_C(1174470673), // MOVT_S
2166 UINT64_C(1409286240), // MOVT_S_MM
2167 UINT64_C(1176502290), // MOVZ_I64_D64
2168 UINT64_C(10), // MOVZ_I64_I
2169 UINT64_C(10), // MOVZ_I64_I64
2170 UINT64_C(1174405138), // MOVZ_I64_S
2171 UINT64_C(1176502290), // MOVZ_I_D32
2172 UINT64_C(1409286520), // MOVZ_I_D32_MM
2173 UINT64_C(1176502290), // MOVZ_I_D64
2174 UINT64_C(10), // MOVZ_I_I
2175 UINT64_C(10), // MOVZ_I_I64
2176 UINT64_C(88), // MOVZ_I_MM
2177 UINT64_C(1174405138), // MOVZ_I_S
2178 UINT64_C(1409286264), // MOVZ_I_S_MM
2179 UINT64_C(1879048196), // MSUB
2180 UINT64_C(1176502297), // MSUBF_D
2181 UINT64_C(1409287160), // MSUBF_D_MMR6
2182 UINT64_C(1174405145), // MSUBF_S
2183 UINT64_C(1409286648), // MSUBF_S_MMR6
2184 UINT64_C(2071986204), // MSUBR_Q_H
2185 UINT64_C(2074083356), // MSUBR_Q_W
2186 UINT64_C(1879048197), // MSUBU
2187 UINT64_C(1879048197), // MSUBU_DSP
2188 UINT64_C(15036), // MSUBU_DSP_MM
2189 UINT64_C(64316), // MSUBU_MM
2190 UINT64_C(2030043154), // MSUBV_B
2191 UINT64_C(2036334610), // MSUBV_D
2192 UINT64_C(2032140306), // MSUBV_H
2193 UINT64_C(2034237458), // MSUBV_W
2194 UINT64_C(1275068457), // MSUB_D32
2195 UINT64_C(1409286185), // MSUB_D32_MM
2196 UINT64_C(1275068457), // MSUB_D64
2197 UINT64_C(1879048196), // MSUB_DSP
2198 UINT64_C(10940), // MSUB_DSP_MM
2199 UINT64_C(60220), // MSUB_MM
2200 UINT64_C(2038431772), // MSUB_Q_H
2201 UINT64_C(2040528924), // MSUB_Q_W
2202 UINT64_C(1275068456), // MSUB_S
2203 UINT64_C(1409286177), // MSUB_S_MM
2204 UINT64_C(1082130432), // MTC0
2205 UINT64_C(764), // MTC0_MMR6
2206 UINT64_C(1149239296), // MTC1
2207 UINT64_C(1149239296), // MTC1_D64
2208 UINT64_C(1409296443), // MTC1_D64_MM
2209 UINT64_C(1409296443), // MTC1_MM
2210 UINT64_C(1409296443), // MTC1_MMR6
2211 UINT64_C(1216348160), // MTC2
2212 UINT64_C(23868), // MTC2_MMR6
2213 UINT64_C(1080033792), // MTGC0
2214 UINT64_C(1788), // MTGC0_MM
2215 UINT64_C(756), // MTHC0_MMR6
2216 UINT64_C(1155530752), // MTHC1_D32
2217 UINT64_C(1409300539), // MTHC1_D32_MM
2218 UINT64_C(1155530752), // MTHC1_D64
2219 UINT64_C(1409300539), // MTHC1_D64_MM
2220 UINT64_C(40252), // MTHC2_MMR6
2221 UINT64_C(1080034816), // MTHGC0
2222 UINT64_C(1780), // MTHGC0_MM
2223 UINT64_C(17), // MTHI
2224 UINT64_C(17), // MTHI64
2225 UINT64_C(17), // MTHI_DSP
2226 UINT64_C(8316), // MTHI_DSP_MM
2227 UINT64_C(11644), // MTHI_MM
2228 UINT64_C(2080376824), // MTHLIP
2229 UINT64_C(636), // MTHLIP_MM
2230 UINT64_C(19), // MTLO
2231 UINT64_C(19), // MTLO64
2232 UINT64_C(19), // MTLO_DSP
2233 UINT64_C(12412), // MTLO_DSP_MM
2234 UINT64_C(15740), // MTLO_MM
2235 UINT64_C(1879048200), // MTM0
2236 UINT64_C(1879048204), // MTM1
2237 UINT64_C(1879048205), // MTM2
2238 UINT64_C(1879048201), // MTP0
2239 UINT64_C(1879048202), // MTP1
2240 UINT64_C(1879048203), // MTP2
2241 UINT64_C(1098907648), // MTTR
2242 UINT64_C(216), // MUH
2243 UINT64_C(217), // MUHU
2244 UINT64_C(216), // MUHU_MMR6
2245 UINT64_C(88), // MUH_MMR6
2246 UINT64_C(1879048194), // MUL
2247 UINT64_C(2080376592), // MULEQ_S_W_PHL
2248 UINT64_C(37), // MULEQ_S_W_PHL_MM
2249 UINT64_C(2080376656), // MULEQ_S_W_PHR
2250 UINT64_C(101), // MULEQ_S_W_PHR_MM
2251 UINT64_C(2080375184), // MULEU_S_PH_QBL
2252 UINT64_C(149), // MULEU_S_PH_QBL_MM
2253 UINT64_C(2080375248), // MULEU_S_PH_QBR
2254 UINT64_C(213), // MULEU_S_PH_QBR_MM
2255 UINT64_C(2080376784), // MULQ_RS_PH
2256 UINT64_C(277), // MULQ_RS_PH_MM
2257 UINT64_C(2080376280), // MULQ_RS_W
2258 UINT64_C(405), // MULQ_RS_W_MMR2
2259 UINT64_C(2080376720), // MULQ_S_PH
2260 UINT64_C(341), // MULQ_S_PH_MMR2
2261 UINT64_C(2080376216), // MULQ_S_W
2262 UINT64_C(469), // MULQ_S_W_MMR2
2263 UINT64_C(1186988058), // MULR_PS64
2264 UINT64_C(2063597596), // MULR_Q_H
2265 UINT64_C(2065694748), // MULR_Q_W
2266 UINT64_C(2080375216), // MULSAQ_S_W_PH
2267 UINT64_C(15548), // MULSAQ_S_W_PH_MM
2268 UINT64_C(2080374960), // MULSA_W_PH
2269 UINT64_C(11452), // MULSA_W_PH_MMR2
2270 UINT64_C(24), // MULT
2271 UINT64_C(25), // MULTU_DSP
2272 UINT64_C(7356), // MULTU_DSP_MM
2273 UINT64_C(24), // MULT_DSP
2274 UINT64_C(3260), // MULT_DSP_MM
2275 UINT64_C(35644), // MULT_MM
2276 UINT64_C(25), // MULTu
2277 UINT64_C(39740), // MULTu_MM
2278 UINT64_C(153), // MULU
2279 UINT64_C(152), // MULU_MMR6
2280 UINT64_C(2013265938), // MULV_B
2281 UINT64_C(2019557394), // MULV_D
2282 UINT64_C(2015363090), // MULV_H
2283 UINT64_C(2017460242), // MULV_W
2284 UINT64_C(528), // MUL_MM
2285 UINT64_C(24), // MUL_MMR6
2286 UINT64_C(2080375576), // MUL_PH
2287 UINT64_C(45), // MUL_PH_MMR2
2288 UINT64_C(2030043164), // MUL_Q_H
2289 UINT64_C(2032140316), // MUL_Q_W
2290 UINT64_C(152), // MUL_R6
2291 UINT64_C(2080375704), // MUL_S_PH
2292 UINT64_C(1069), // MUL_S_PH_MMR2
2293 UINT64_C(59408), // Mfhi16
2294 UINT64_C(59410), // Mflo16
2295 UINT64_C(25856), // Move32R16
2296 UINT64_C(26368), // MoveR3216
2297 UINT64_C(68157440), // NAL
2298 UINT64_C(2064121886), // NLOC_B
2299 UINT64_C(2064318494), // NLOC_D
2300 UINT64_C(2064187422), // NLOC_H
2301 UINT64_C(2064252958), // NLOC_W
2302 UINT64_C(2064384030), // NLZC_B
2303 UINT64_C(2064580638), // NLZC_D
2304 UINT64_C(2064449566), // NLZC_H
2305 UINT64_C(2064515102), // NLZC_W
2306 UINT64_C(1275068465), // NMADD_D32
2307 UINT64_C(1409286154), // NMADD_D32_MM
2308 UINT64_C(1275068465), // NMADD_D64
2309 UINT64_C(1275068464), // NMADD_S
2310 UINT64_C(1409286146), // NMADD_S_MM
2311 UINT64_C(1275068473), // NMSUB_D32
2312 UINT64_C(1409286186), // NMSUB_D32_MM
2313 UINT64_C(1275068473), // NMSUB_D64
2314 UINT64_C(1275068472), // NMSUB_S
2315 UINT64_C(1409286178), // NMSUB_S_MM
2316 UINT64_C(39), // NOR
2317 UINT64_C(39), // NOR64
2318 UINT64_C(2046820352), // NORI_B
2319 UINT64_C(720), // NOR_MM
2320 UINT64_C(720), // NOR_MMR6
2321 UINT64_C(2017460254), // NOR_V
2322 UINT64_C(17408), // NOT16_MM
2323 UINT64_C(17408), // NOT16_MMR6
2324 UINT64_C(59421), // NegRxRy16
2325 UINT64_C(59407), // NotRxRy16
2326 UINT64_C(37), // OR
2327 UINT64_C(17600), // OR16_MM
2328 UINT64_C(17417), // OR16_MMR6
2329 UINT64_C(37), // OR64
2330 UINT64_C(2030043136), // ORI_B
2331 UINT64_C(1342177280), // ORI_MMR6
2332 UINT64_C(656), // OR_MM
2333 UINT64_C(656), // OR_MMR6
2334 UINT64_C(2015363102), // OR_V
2335 UINT64_C(872415232), // ORi
2336 UINT64_C(872415232), // ORi64
2337 UINT64_C(1342177280), // ORi_MM
2338 UINT64_C(59405), // OrRxRxRy16
2339 UINT64_C(2080375697), // PACKRL_PH
2340 UINT64_C(429), // PACKRL_PH_MM
2341 UINT64_C(320), // PAUSE
2342 UINT64_C(10240), // PAUSE_MM
2343 UINT64_C(10240), // PAUSE_MMR6
2344 UINT64_C(2030043156), // PCKEV_B
2345 UINT64_C(2036334612), // PCKEV_D
2346 UINT64_C(2032140308), // PCKEV_H
2347 UINT64_C(2034237460), // PCKEV_W
2348 UINT64_C(2038431764), // PCKOD_B
2349 UINT64_C(2044723220), // PCKOD_D
2350 UINT64_C(2040528916), // PCKOD_H
2351 UINT64_C(2042626068), // PCKOD_W
2352 UINT64_C(2063859742), // PCNT_B
2353 UINT64_C(2064056350), // PCNT_D
2354 UINT64_C(2063925278), // PCNT_H
2355 UINT64_C(2063990814), // PCNT_W
2356 UINT64_C(2080375505), // PICK_PH
2357 UINT64_C(557), // PICK_PH_MM
2358 UINT64_C(2080374993), // PICK_QB
2359 UINT64_C(493), // PICK_QB_MM
2360 UINT64_C(1186988076), // PLL_PS64
2361 UINT64_C(1186988077), // PLU_PS64
2362 UINT64_C(1879048236), // POP
2363 UINT64_C(2080375058), // PRECEQU_PH_QBL
2364 UINT64_C(2080375186), // PRECEQU_PH_QBLA
2365 UINT64_C(29500), // PRECEQU_PH_QBLA_MM
2366 UINT64_C(28988), // PRECEQU_PH_QBL_MM
2367 UINT64_C(2080375122), // PRECEQU_PH_QBR
2368 UINT64_C(2080375250), // PRECEQU_PH_QBRA
2369 UINT64_C(37692), // PRECEQU_PH_QBRA_MM
2370 UINT64_C(37180), // PRECEQU_PH_QBR_MM
2371 UINT64_C(2080375570), // PRECEQ_W_PHL
2372 UINT64_C(20796), // PRECEQ_W_PHL_MM
2373 UINT64_C(2080375634), // PRECEQ_W_PHR
2374 UINT64_C(24892), // PRECEQ_W_PHR_MM
2375 UINT64_C(2080376594), // PRECEU_PH_QBL
2376 UINT64_C(2080376722), // PRECEU_PH_QBLA
2377 UINT64_C(45884), // PRECEU_PH_QBLA_MM
2378 UINT64_C(45372), // PRECEU_PH_QBL_MM
2379 UINT64_C(2080376658), // PRECEU_PH_QBR
2380 UINT64_C(2080376786), // PRECEU_PH_QBRA
2381 UINT64_C(54076), // PRECEU_PH_QBRA_MM
2382 UINT64_C(53564), // PRECEU_PH_QBR_MM
2383 UINT64_C(2080375761), // PRECRQU_S_QB_PH
2384 UINT64_C(365), // PRECRQU_S_QB_PH_MM
2385 UINT64_C(2080376081), // PRECRQ_PH_W
2386 UINT64_C(237), // PRECRQ_PH_W_MM
2387 UINT64_C(2080375569), // PRECRQ_QB_PH
2388 UINT64_C(173), // PRECRQ_QB_PH_MM
2389 UINT64_C(2080376145), // PRECRQ_RS_PH_W
2390 UINT64_C(301), // PRECRQ_RS_PH_W_MM
2391 UINT64_C(2080375633), // PRECR_QB_PH
2392 UINT64_C(109), // PRECR_QB_PH_MMR2
2393 UINT64_C(2080376721), // PRECR_SRA_PH_W
2394 UINT64_C(973), // PRECR_SRA_PH_W_MMR2
2395 UINT64_C(2080376785), // PRECR_SRA_R_PH_W
2396 UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
2397 UINT64_C(3422552064), // PREF
2398 UINT64_C(2080374819), // PREFE
2399 UINT64_C(1610654720), // PREFE_MM
2400 UINT64_C(1409286560), // PREFX_MM
2401 UINT64_C(1610620928), // PREF_MM
2402 UINT64_C(1610620928), // PREF_MMR6
2403 UINT64_C(2080374837), // PREF_R6
2404 UINT64_C(2080374897), // PREPEND
2405 UINT64_C(597), // PREPEND_MMR2
2406 UINT64_C(1186988078), // PUL_PS64
2407 UINT64_C(1186988079), // PUU_PS64
2408 UINT64_C(2080376080), // RADDU_W_QB
2409 UINT64_C(61756), // RADDU_W_QB_MM
2410 UINT64_C(2080375992), // RDDSP
2411 UINT64_C(1660), // RDDSP_MM
2412 UINT64_C(2080374843), // RDHWR
2413 UINT64_C(2080374843), // RDHWR64
2414 UINT64_C(27452), // RDHWR_MM
2415 UINT64_C(448), // RDHWR_MMR6
2416 UINT64_C(57724), // RDPGPR_MMR6
2417 UINT64_C(1176502293), // RECIP_D32
2418 UINT64_C(1409307195), // RECIP_D32_MM
2419 UINT64_C(1176502293), // RECIP_D64
2420 UINT64_C(1409307195), // RECIP_D64_MM
2421 UINT64_C(1174405141), // RECIP_S
2422 UINT64_C(1409290811), // RECIP_S_MM
2423 UINT64_C(2080375506), // REPLV_PH
2424 UINT64_C(828), // REPLV_PH_MM
2425 UINT64_C(2080374994), // REPLV_QB
2426 UINT64_C(4924), // REPLV_QB_MM
2427 UINT64_C(2080375442), // REPL_PH
2428 UINT64_C(61), // REPL_PH_MM
2429 UINT64_C(2080374930), // REPL_QB
2430 UINT64_C(1532), // REPL_QB_MM
2431 UINT64_C(1176502298), // RINT_D
2432 UINT64_C(1409286688), // RINT_D_MMR6
2433 UINT64_C(1174405146), // RINT_S
2434 UINT64_C(1409286176), // RINT_S_MMR6
2435 UINT64_C(2097154), // ROTR
2436 UINT64_C(70), // ROTRV
2437 UINT64_C(208), // ROTRV_MM
2438 UINT64_C(192), // ROTR_MM
2439 UINT64_C(1176502280), // ROUND_L_D64
2440 UINT64_C(1409315643), // ROUND_L_D_MMR6
2441 UINT64_C(1174405128), // ROUND_L_S
2442 UINT64_C(1409299259), // ROUND_L_S_MMR6
2443 UINT64_C(1176502284), // ROUND_W_D32
2444 UINT64_C(1176502284), // ROUND_W_D64
2445 UINT64_C(1409317691), // ROUND_W_D_MMR6
2446 UINT64_C(1409317691), // ROUND_W_MM
2447 UINT64_C(1174405132), // ROUND_W_S
2448 UINT64_C(1409301307), // ROUND_W_S_MM
2449 UINT64_C(1409301307), // ROUND_W_S_MMR6
2450 UINT64_C(1176502294), // RSQRT_D32
2451 UINT64_C(1409303099), // RSQRT_D32_MM
2452 UINT64_C(1176502294), // RSQRT_D64
2453 UINT64_C(1409303099), // RSQRT_D64_MM
2454 UINT64_C(1174405142), // RSQRT_S
2455 UINT64_C(1409286715), // RSQRT_S_MM
2456 UINT64_C(25728), // Restore16
2457 UINT64_C(25728), // RestoreX16
2458 UINT64_C(1879048216), // SAA
2459 UINT64_C(1879048217), // SAAD
2460 UINT64_C(2020605962), // SAT_S_B
2461 UINT64_C(2013265930), // SAT_S_D
2462 UINT64_C(2019557386), // SAT_S_H
2463 UINT64_C(2017460234), // SAT_S_W
2464 UINT64_C(2028994570), // SAT_U_B
2465 UINT64_C(2021654538), // SAT_U_D
2466 UINT64_C(2027945994), // SAT_U_H
2467 UINT64_C(2025848842), // SAT_U_W
2468 UINT64_C(2684354560), // SB
2469 UINT64_C(34816), // SB16_MM
2470 UINT64_C(34816), // SB16_MMR6
2471 UINT64_C(2684354560), // SB64
2472 UINT64_C(2080374812), // SBE
2473 UINT64_C(1610655744), // SBE_MM
2474 UINT64_C(402653184), // SB_MM
2475 UINT64_C(402653184), // SB_MMR6
2476 UINT64_C(3758096384), // SC
2477 UINT64_C(3758096384), // SC64
2478 UINT64_C(2080374822), // SC64_R6
2479 UINT64_C(4026531840), // SCD
2480 UINT64_C(2080374823), // SCD_R6
2481 UINT64_C(2080374814), // SCE
2482 UINT64_C(1610656768), // SCE_MM
2483 UINT64_C(1610657792), // SC_MM
2484 UINT64_C(1610657792), // SC_MMR6
2485 UINT64_C(2080374822), // SC_R6
2486 UINT64_C(4227858432), // SD
2487 UINT64_C(1879048255), // SDBBP
2488 UINT64_C(18112), // SDBBP16_MM
2489 UINT64_C(17467), // SDBBP16_MMR6
2490 UINT64_C(56188), // SDBBP_MM
2491 UINT64_C(56188), // SDBBP_MMR6
2492 UINT64_C(14), // SDBBP_R6
2493 UINT64_C(4093640704), // SDC1
2494 UINT64_C(4093640704), // SDC164
2495 UINT64_C(3087007744), // SDC1_D64_MMR6
2496 UINT64_C(3087007744), // SDC1_MM_D32
2497 UINT64_C(3087007744), // SDC1_MM_D64
2498 UINT64_C(4160749568), // SDC2
2499 UINT64_C(536911872), // SDC2_MMR6
2500 UINT64_C(1239416832), // SDC2_R6
2501 UINT64_C(4227858432), // SDC3
2502 UINT64_C(26), // SDIV
2503 UINT64_C(43836), // SDIV_MM
2504 UINT64_C(2952790016), // SDL
2505 UINT64_C(3019898880), // SDR
2506 UINT64_C(1275068425), // SDXC1
2507 UINT64_C(1275068425), // SDXC164
2508 UINT64_C(2080375840), // SEB
2509 UINT64_C(2080375840), // SEB64
2510 UINT64_C(11068), // SEB_MM
2511 UINT64_C(2080376352), // SEH
2512 UINT64_C(2080376352), // SEH64
2513 UINT64_C(15164), // SEH_MM
2514 UINT64_C(53), // SELEQZ
2515 UINT64_C(53), // SELEQZ64
2516 UINT64_C(1176502292), // SELEQZ_D
2517 UINT64_C(1409286712), // SELEQZ_D_MMR6
2518 UINT64_C(320), // SELEQZ_MMR6
2519 UINT64_C(1174405140), // SELEQZ_S
2520 UINT64_C(1409286200), // SELEQZ_S_MMR6
2521 UINT64_C(55), // SELNEZ
2522 UINT64_C(55), // SELNEZ64
2523 UINT64_C(1176502295), // SELNEZ_D
2524 UINT64_C(1409286776), // SELNEZ_D_MMR6
2525 UINT64_C(384), // SELNEZ_MMR6
2526 UINT64_C(1174405143), // SELNEZ_S
2527 UINT64_C(1409286264), // SELNEZ_S_MMR6
2528 UINT64_C(1176502288), // SEL_D
2529 UINT64_C(1409286840), // SEL_D_MMR6
2530 UINT64_C(1174405136), // SEL_S
2531 UINT64_C(1409286328), // SEL_S_MMR6
2532 UINT64_C(1879048234), // SEQ
2533 UINT64_C(1879048238), // SEQi
2534 UINT64_C(2751463424), // SH
2535 UINT64_C(43008), // SH16_MM
2536 UINT64_C(43008), // SH16_MMR6
2537 UINT64_C(2751463424), // SH64
2538 UINT64_C(2080374813), // SHE
2539 UINT64_C(1610656256), // SHE_MM
2540 UINT64_C(2013265922), // SHF_B
2541 UINT64_C(2030043138), // SHF_H
2542 UINT64_C(2046820354), // SHF_W
2543 UINT64_C(2080376504), // SHILO
2544 UINT64_C(2080376568), // SHILOV
2545 UINT64_C(4732), // SHILOV_MM
2546 UINT64_C(29), // SHILO_MM
2547 UINT64_C(2080375443), // SHLLV_PH
2548 UINT64_C(14), // SHLLV_PH_MM
2549 UINT64_C(2080374931), // SHLLV_QB
2550 UINT64_C(917), // SHLLV_QB_MM
2551 UINT64_C(2080375699), // SHLLV_S_PH
2552 UINT64_C(1038), // SHLLV_S_PH_MM
2553 UINT64_C(2080376211), // SHLLV_S_W
2554 UINT64_C(981), // SHLLV_S_W_MM
2555 UINT64_C(2080375315), // SHLL_PH
2556 UINT64_C(949), // SHLL_PH_MM
2557 UINT64_C(2080374803), // SHLL_QB
2558 UINT64_C(2172), // SHLL_QB_MM
2559 UINT64_C(2080375571), // SHLL_S_PH
2560 UINT64_C(2997), // SHLL_S_PH_MM
2561 UINT64_C(2080376083), // SHLL_S_W
2562 UINT64_C(1013), // SHLL_S_W_MM
2563 UINT64_C(2080375507), // SHRAV_PH
2564 UINT64_C(397), // SHRAV_PH_MM
2565 UINT64_C(2080375187), // SHRAV_QB
2566 UINT64_C(461), // SHRAV_QB_MMR2
2567 UINT64_C(2080375763), // SHRAV_R_PH
2568 UINT64_C(1421), // SHRAV_R_PH_MM
2569 UINT64_C(2080375251), // SHRAV_R_QB
2570 UINT64_C(1485), // SHRAV_R_QB_MMR2
2571 UINT64_C(2080376275), // SHRAV_R_W
2572 UINT64_C(725), // SHRAV_R_W_MM
2573 UINT64_C(2080375379), // SHRA_PH
2574 UINT64_C(821), // SHRA_PH_MM
2575 UINT64_C(2080375059), // SHRA_QB
2576 UINT64_C(508), // SHRA_QB_MMR2
2577 UINT64_C(2080375635), // SHRA_R_PH
2578 UINT64_C(1845), // SHRA_R_PH_MM
2579 UINT64_C(2080375123), // SHRA_R_QB
2580 UINT64_C(4604), // SHRA_R_QB_MMR2
2581 UINT64_C(2080376147), // SHRA_R_W
2582 UINT64_C(757), // SHRA_R_W_MM
2583 UINT64_C(2080376531), // SHRLV_PH
2584 UINT64_C(789), // SHRLV_PH_MMR2
2585 UINT64_C(2080374995), // SHRLV_QB
2586 UINT64_C(853), // SHRLV_QB_MM
2587 UINT64_C(2080376403), // SHRL_PH
2588 UINT64_C(1020), // SHRL_PH_MMR2
2589 UINT64_C(2080374867), // SHRL_QB
2590 UINT64_C(6268), // SHRL_QB_MM
2591 UINT64_C(939524096), // SH_MM
2592 UINT64_C(939524096), // SH_MMR6
2593 UINT64_C(68616192), // SIGRIE
2594 UINT64_C(63), // SIGRIE_MMR6
2595 UINT64_C(2013265945), // SLDI_B
2596 UINT64_C(2016935961), // SLDI_D
2597 UINT64_C(2015363097), // SLDI_H
2598 UINT64_C(2016411673), // SLDI_W
2599 UINT64_C(2013265940), // SLD_B
2600 UINT64_C(2019557396), // SLD_D
2601 UINT64_C(2015363092), // SLD_H
2602 UINT64_C(2017460244), // SLD_W
2603 UINT64_C(0), // SLL
2604 UINT64_C(9216), // SLL16_MM
2605 UINT64_C(9216), // SLL16_MMR6
2606 UINT64_C(0), // SLL64_32
2607 UINT64_C(0), // SLL64_64
2608 UINT64_C(2020605961), // SLLI_B
2609 UINT64_C(2013265929), // SLLI_D
2610 UINT64_C(2019557385), // SLLI_H
2611 UINT64_C(2017460233), // SLLI_W
2612 UINT64_C(4), // SLLV
2613 UINT64_C(16), // SLLV_MM
2614 UINT64_C(2013265933), // SLL_B
2615 UINT64_C(2019557389), // SLL_D
2616 UINT64_C(2015363085), // SLL_H
2617 UINT64_C(0), // SLL_MM
2618 UINT64_C(0), // SLL_MMR6
2619 UINT64_C(2017460237), // SLL_W
2620 UINT64_C(42), // SLT
2621 UINT64_C(42), // SLT64
2622 UINT64_C(848), // SLT_MM
2623 UINT64_C(671088640), // SLTi
2624 UINT64_C(671088640), // SLTi64
2625 UINT64_C(2415919104), // SLTi_MM
2626 UINT64_C(738197504), // SLTiu
2627 UINT64_C(738197504), // SLTiu64
2628 UINT64_C(2952790016), // SLTiu_MM
2629 UINT64_C(43), // SLTu
2630 UINT64_C(43), // SLTu64
2631 UINT64_C(912), // SLTu_MM
2632 UINT64_C(1879048235), // SNE
2633 UINT64_C(1879048239), // SNEi
2634 UINT64_C(2017460249), // SPLATI_B
2635 UINT64_C(2021130265), // SPLATI_D
2636 UINT64_C(2019557401), // SPLATI_H
2637 UINT64_C(2020605977), // SPLATI_W
2638 UINT64_C(2021654548), // SPLAT_B
2639 UINT64_C(2027946004), // SPLAT_D
2640 UINT64_C(2023751700), // SPLAT_H
2641 UINT64_C(2025848852), // SPLAT_W
2642 UINT64_C(3), // SRA
2643 UINT64_C(2028994569), // SRAI_B
2644 UINT64_C(2021654537), // SRAI_D
2645 UINT64_C(2027945993), // SRAI_H
2646 UINT64_C(2025848841), // SRAI_W
2647 UINT64_C(2037383178), // SRARI_B
2648 UINT64_C(2030043146), // SRARI_D
2649 UINT64_C(2036334602), // SRARI_H
2650 UINT64_C(2034237450), // SRARI_W
2651 UINT64_C(2021654549), // SRAR_B
2652 UINT64_C(2027946005), // SRAR_D
2653 UINT64_C(2023751701), // SRAR_H
2654 UINT64_C(2025848853), // SRAR_W
2655 UINT64_C(7), // SRAV
2656 UINT64_C(144), // SRAV_MM
2657 UINT64_C(2021654541), // SRA_B
2658 UINT64_C(2027945997), // SRA_D
2659 UINT64_C(2023751693), // SRA_H
2660 UINT64_C(128), // SRA_MM
2661 UINT64_C(2025848845), // SRA_W
2662 UINT64_C(2), // SRL
2663 UINT64_C(9217), // SRL16_MM
2664 UINT64_C(9217), // SRL16_MMR6
2665 UINT64_C(2037383177), // SRLI_B
2666 UINT64_C(2030043145), // SRLI_D
2667 UINT64_C(2036334601), // SRLI_H
2668 UINT64_C(2034237449), // SRLI_W
2669 UINT64_C(2045771786), // SRLRI_B
2670 UINT64_C(2038431754), // SRLRI_D
2671 UINT64_C(2044723210), // SRLRI_H
2672 UINT64_C(2042626058), // SRLRI_W
2673 UINT64_C(2030043157), // SRLR_B
2674 UINT64_C(2036334613), // SRLR_D
2675 UINT64_C(2032140309), // SRLR_H
2676 UINT64_C(2034237461), // SRLR_W
2677 UINT64_C(6), // SRLV
2678 UINT64_C(80), // SRLV_MM
2679 UINT64_C(2030043149), // SRL_B
2680 UINT64_C(2036334605), // SRL_D
2681 UINT64_C(2032140301), // SRL_H
2682 UINT64_C(64), // SRL_MM
2683 UINT64_C(2034237453), // SRL_W
2684 UINT64_C(64), // SSNOP
2685 UINT64_C(2048), // SSNOP_MM
2686 UINT64_C(2048), // SSNOP_MMR6
2687 UINT64_C(2013265956), // ST_B
2688 UINT64_C(2013265959), // ST_D
2689 UINT64_C(2013265957), // ST_H
2690 UINT64_C(2013265958), // ST_W
2691 UINT64_C(34), // SUB
2692 UINT64_C(2080375384), // SUBQH_PH
2693 UINT64_C(589), // SUBQH_PH_MMR2
2694 UINT64_C(2080375512), // SUBQH_R_PH
2695 UINT64_C(1613), // SUBQH_R_PH_MMR2
2696 UINT64_C(2080376024), // SUBQH_R_W
2697 UINT64_C(1677), // SUBQH_R_W_MMR2
2698 UINT64_C(2080375896), // SUBQH_W
2699 UINT64_C(653), // SUBQH_W_MMR2
2700 UINT64_C(2080375504), // SUBQ_PH
2701 UINT64_C(525), // SUBQ_PH_MM
2702 UINT64_C(2080375760), // SUBQ_S_PH
2703 UINT64_C(1549), // SUBQ_S_PH_MM
2704 UINT64_C(2080376272), // SUBQ_S_W
2705 UINT64_C(837), // SUBQ_S_W_MM
2706 UINT64_C(2030043153), // SUBSUS_U_B
2707 UINT64_C(2036334609), // SUBSUS_U_D
2708 UINT64_C(2032140305), // SUBSUS_U_H
2709 UINT64_C(2034237457), // SUBSUS_U_W
2710 UINT64_C(2038431761), // SUBSUU_S_B
2711 UINT64_C(2044723217), // SUBSUU_S_D
2712 UINT64_C(2040528913), // SUBSUU_S_H
2713 UINT64_C(2042626065), // SUBSUU_S_W
2714 UINT64_C(2013265937), // SUBS_S_B
2715 UINT64_C(2019557393), // SUBS_S_D
2716 UINT64_C(2015363089), // SUBS_S_H
2717 UINT64_C(2017460241), // SUBS_S_W
2718 UINT64_C(2021654545), // SUBS_U_B
2719 UINT64_C(2027946001), // SUBS_U_D
2720 UINT64_C(2023751697), // SUBS_U_H
2721 UINT64_C(2025848849), // SUBS_U_W
2722 UINT64_C(1025), // SUBU16_MM
2723 UINT64_C(1025), // SUBU16_MMR6
2724 UINT64_C(2080374872), // SUBUH_QB
2725 UINT64_C(845), // SUBUH_QB_MMR2
2726 UINT64_C(2080375000), // SUBUH_R_QB
2727 UINT64_C(1869), // SUBUH_R_QB_MMR2
2728 UINT64_C(464), // SUBU_MMR6
2729 UINT64_C(2080375376), // SUBU_PH
2730 UINT64_C(781), // SUBU_PH_MMR2
2731 UINT64_C(2080374864), // SUBU_QB
2732 UINT64_C(717), // SUBU_QB_MM
2733 UINT64_C(2080375632), // SUBU_S_PH
2734 UINT64_C(1805), // SUBU_S_PH_MMR2
2735 UINT64_C(2080375120), // SUBU_S_QB
2736 UINT64_C(1741), // SUBU_S_QB_MM
2737 UINT64_C(2021654534), // SUBVI_B
2738 UINT64_C(2027945990), // SUBVI_D
2739 UINT64_C(2023751686), // SUBVI_H
2740 UINT64_C(2025848838), // SUBVI_W
2741 UINT64_C(2021654542), // SUBV_B
2742 UINT64_C(2027945998), // SUBV_D
2743 UINT64_C(2023751694), // SUBV_H
2744 UINT64_C(2025848846), // SUBV_W
2745 UINT64_C(400), // SUB_MM
2746 UINT64_C(400), // SUB_MMR6
2747 UINT64_C(35), // SUBu
2748 UINT64_C(464), // SUBu_MM
2749 UINT64_C(1275068429), // SUXC1
2750 UINT64_C(1275068429), // SUXC164
2751 UINT64_C(1409286536), // SUXC1_MM
2752 UINT64_C(2885681152), // SW
2753 UINT64_C(59392), // SW16_MM
2754 UINT64_C(59392), // SW16_MMR6
2755 UINT64_C(2885681152), // SW64
2756 UINT64_C(3825205248), // SWC1
2757 UINT64_C(2550136832), // SWC1_MM
2758 UINT64_C(3892314112), // SWC2
2759 UINT64_C(536903680), // SWC2_MMR6
2760 UINT64_C(1231028224), // SWC2_R6
2761 UINT64_C(3959422976), // SWC3
2762 UINT64_C(2885681152), // SWDSP
2763 UINT64_C(4160749568), // SWDSP_MM
2764 UINT64_C(2080374815), // SWE
2765 UINT64_C(1610657280), // SWE_MM
2766 UINT64_C(2818572288), // SWL
2767 UINT64_C(2818572288), // SWL64
2768 UINT64_C(2080374817), // SWLE
2769 UINT64_C(1610653696), // SWLE_MM
2770 UINT64_C(1610645504), // SWL_MM
2771 UINT64_C(17728), // SWM16_MM
2772 UINT64_C(17418), // SWM16_MMR6
2773 UINT64_C(536924160), // SWM32_MM
2774 UINT64_C(536907776), // SWP_MM
2775 UINT64_C(3087007744), // SWR
2776 UINT64_C(3087007744), // SWR64
2777 UINT64_C(2080374818), // SWRE
2778 UINT64_C(1610654208), // SWRE_MM
2779 UINT64_C(1610649600), // SWR_MM
2780 UINT64_C(51200), // SWSP_MM
2781 UINT64_C(51200), // SWSP_MMR6
2782 UINT64_C(1275068424), // SWXC1
2783 UINT64_C(1409286280), // SWXC1_MM
2784 UINT64_C(4160749568), // SW_MM
2785 UINT64_C(4160749568), // SW_MMR6
2786 UINT64_C(15), // SYNC
2787 UINT64_C(69140480), // SYNCI
2788 UINT64_C(1107296256), // SYNCI_MM
2789 UINT64_C(1098907648), // SYNCI_MMR6
2790 UINT64_C(27516), // SYNC_MM
2791 UINT64_C(27516), // SYNC_MMR6
2792 UINT64_C(12), // SYSCALL
2793 UINT64_C(35708), // SYSCALL_MM
2794 UINT64_C(25728), // Save16
2795 UINT64_C(25728), // SaveX16
2796 UINT64_C(4026580992), // SbRxRyOffMemX16
2797 UINT64_C(59537), // SebRx16
2798 UINT64_C(59569), // SehRx16
2799 UINT64_C(4026583040), // ShRxRyOffMemX16
2800 UINT64_C(4026544128), // SllX16
2801 UINT64_C(59396), // SllvRxRy16
2802 UINT64_C(59394), // SltRxRy16
2803 UINT64_C(20480), // SltiRxImm16
2804 UINT64_C(4026552320), // SltiRxImmX16
2805 UINT64_C(22528), // SltiuRxImm16
2806 UINT64_C(4026554368), // SltiuRxImmX16
2807 UINT64_C(59395), // SltuRxRy16
2808 UINT64_C(4026544131), // SraX16
2809 UINT64_C(59399), // SravRxRy16
2810 UINT64_C(4026544130), // SrlX16
2811 UINT64_C(59398), // SrlvRxRy16
2812 UINT64_C(57347), // SubuRxRyRz16
2813 UINT64_C(4026587136), // SwRxRyOffMemX16
2814 UINT64_C(4026585088), // SwRxSpImmX16
2815 UINT64_C(52), // TEQ
2816 UINT64_C(67895296), // TEQI
2817 UINT64_C(1103101952), // TEQI_MM
2818 UINT64_C(60), // TEQ_MM
2819 UINT64_C(48), // TGE
2820 UINT64_C(67633152), // TGEI
2821 UINT64_C(67698688), // TGEIU
2822 UINT64_C(1096810496), // TGEIU_MM
2823 UINT64_C(1092616192), // TGEI_MM
2824 UINT64_C(49), // TGEU
2825 UINT64_C(1084), // TGEU_MM
2826 UINT64_C(572), // TGE_MM
2827 UINT64_C(1107296267), // TLBGINV
2828 UINT64_C(1107296268), // TLBGINVF
2829 UINT64_C(20860), // TLBGINVF_MM
2830 UINT64_C(16764), // TLBGINV_MM
2831 UINT64_C(1107296272), // TLBGP
2832 UINT64_C(380), // TLBGP_MM
2833 UINT64_C(1107296265), // TLBGR
2834 UINT64_C(4476), // TLBGR_MM
2835 UINT64_C(1107296266), // TLBGWI
2836 UINT64_C(8572), // TLBGWI_MM
2837 UINT64_C(1107296270), // TLBGWR
2838 UINT64_C(12668), // TLBGWR_MM
2839 UINT64_C(1107296259), // TLBINV
2840 UINT64_C(1107296260), // TLBINVF
2841 UINT64_C(21372), // TLBINVF_MMR6
2842 UINT64_C(17276), // TLBINV_MMR6
2843 UINT64_C(1107296264), // TLBP
2844 UINT64_C(892), // TLBP_MM
2845 UINT64_C(1107296257), // TLBR
2846 UINT64_C(4988), // TLBR_MM
2847 UINT64_C(1107296258), // TLBWI
2848 UINT64_C(9084), // TLBWI_MM
2849 UINT64_C(1107296262), // TLBWR
2850 UINT64_C(13180), // TLBWR_MM
2851 UINT64_C(50), // TLT
2852 UINT64_C(67764224), // TLTI
2853 UINT64_C(1094713344), // TLTIU_MM
2854 UINT64_C(1090519040), // TLTI_MM
2855 UINT64_C(51), // TLTU
2856 UINT64_C(2620), // TLTU_MM
2857 UINT64_C(2108), // TLT_MM
2858 UINT64_C(54), // TNE
2859 UINT64_C(68026368), // TNEI
2860 UINT64_C(1098907648), // TNEI_MM
2861 UINT64_C(3132), // TNE_MM
2862 UINT64_C(1176502281), // TRUNC_L_D64
2863 UINT64_C(1409311547), // TRUNC_L_D_MMR6
2864 UINT64_C(1174405129), // TRUNC_L_S
2865 UINT64_C(1409295163), // TRUNC_L_S_MMR6
2866 UINT64_C(1176502285), // TRUNC_W_D32
2867 UINT64_C(1176502285), // TRUNC_W_D64
2868 UINT64_C(1409313595), // TRUNC_W_D_MMR6
2869 UINT64_C(1409313595), // TRUNC_W_MM
2870 UINT64_C(1174405133), // TRUNC_W_S
2871 UINT64_C(1409297211), // TRUNC_W_S_MM
2872 UINT64_C(1409297211), // TRUNC_W_S_MMR6
2873 UINT64_C(67829760), // TTLTIU
2874 UINT64_C(27), // UDIV
2875 UINT64_C(47932), // UDIV_MM
2876 UINT64_C(1879048209), // V3MULU
2877 UINT64_C(1879048208), // VMM0
2878 UINT64_C(1879048207), // VMULU
2879 UINT64_C(2013265941), // VSHF_B
2880 UINT64_C(2019557397), // VSHF_D
2881 UINT64_C(2015363093), // VSHF_H
2882 UINT64_C(2017460245), // VSHF_W
2883 UINT64_C(1107296288), // WAIT
2884 UINT64_C(37756), // WAIT_MM
2885 UINT64_C(37756), // WAIT_MMR6
2886 UINT64_C(2080376056), // WRDSP
2887 UINT64_C(5756), // WRDSP_MM
2888 UINT64_C(61820), // WRPGPR_MMR6
2889 UINT64_C(2080374944), // WSBH
2890 UINT64_C(31548), // WSBH_MM
2891 UINT64_C(31548), // WSBH_MMR6
2892 UINT64_C(38), // XOR
2893 UINT64_C(17472), // XOR16_MM
2894 UINT64_C(17416), // XOR16_MMR6
2895 UINT64_C(38), // XOR64
2896 UINT64_C(2063597568), // XORI_B
2897 UINT64_C(1879048192), // XORI_MMR6
2898 UINT64_C(784), // XOR_MM
2899 UINT64_C(784), // XOR_MMR6
2900 UINT64_C(2019557406), // XOR_V
2901 UINT64_C(939524096), // XORi
2902 UINT64_C(939524096), // XORi64
2903 UINT64_C(1879048192), // XORi_MM
2904 UINT64_C(59406), // XorRxRxRy16
2905 UINT64_C(2080374793), // YIELD
2906 UINT64_C(0)
2907 };
2908 const unsigned opcode = MI.getOpcode();
2909 uint64_t Value = InstBits[opcode];
2910 uint64_t op = 0;
2911 (void)op; // suppress warning
2912 switch (opcode) {
2913 case Mips::Break16:
2914 case Mips::DERET:
2915 case Mips::DERET_MM:
2916 case Mips::DERET_MMR6:
2917 case Mips::EHB:
2918 case Mips::EHB_MM:
2919 case Mips::EHB_MMR6:
2920 case Mips::ERET:
2921 case Mips::ERETNC:
2922 case Mips::ERETNC_MMR6:
2923 case Mips::ERET_MM:
2924 case Mips::ERET_MMR6:
2925 case Mips::JrRa16:
2926 case Mips::JrcRa16:
2927 case Mips::JrcRx16:
2928 case Mips::NAL:
2929 case Mips::PAUSE:
2930 case Mips::PAUSE_MM:
2931 case Mips::PAUSE_MMR6:
2932 case Mips::Restore16:
2933 case Mips::RestoreX16:
2934 case Mips::SSNOP:
2935 case Mips::SSNOP_MM:
2936 case Mips::SSNOP_MMR6:
2937 case Mips::Save16:
2938 case Mips::SaveX16:
2939 case Mips::TLBGINV:
2940 case Mips::TLBGINVF:
2941 case Mips::TLBGINVF_MM:
2942 case Mips::TLBGINV_MM:
2943 case Mips::TLBGP:
2944 case Mips::TLBGP_MM:
2945 case Mips::TLBGR:
2946 case Mips::TLBGR_MM:
2947 case Mips::TLBGWI:
2948 case Mips::TLBGWI_MM:
2949 case Mips::TLBGWR:
2950 case Mips::TLBGWR_MM:
2951 case Mips::TLBINV:
2952 case Mips::TLBINVF:
2953 case Mips::TLBINVF_MMR6:
2954 case Mips::TLBINV_MMR6:
2955 case Mips::TLBP:
2956 case Mips::TLBP_MM:
2957 case Mips::TLBR:
2958 case Mips::TLBR_MM:
2959 case Mips::TLBWI:
2960 case Mips::TLBWI_MM:
2961 case Mips::TLBWR:
2962 case Mips::TLBWR_MM:
2963 case Mips::WAIT: {
2964 break;
2965 }
2966 case Mips::MTHLIP:
2967 case Mips::SHILOV: {
2968 // op: ac
2969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2970 op &= UINT64_C(3);
2971 op <<= 11;
2972 Value |= op;
2973 // op: rs
2974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2975 op &= UINT64_C(31);
2976 op <<= 21;
2977 Value |= op;
2978 break;
2979 }
2980 case Mips::DPAQX_SA_W_PH:
2981 case Mips::DPAQX_S_W_PH:
2982 case Mips::DPAQ_SA_L_W:
2983 case Mips::DPAQ_S_W_PH:
2984 case Mips::DPAU_H_QBL:
2985 case Mips::DPAU_H_QBR:
2986 case Mips::DPAX_W_PH:
2987 case Mips::DPA_W_PH:
2988 case Mips::DPSQX_SA_W_PH:
2989 case Mips::DPSQX_S_W_PH:
2990 case Mips::DPSQ_SA_L_W:
2991 case Mips::DPSQ_S_W_PH:
2992 case Mips::DPSU_H_QBL:
2993 case Mips::DPSU_H_QBR:
2994 case Mips::DPSX_W_PH:
2995 case Mips::DPS_W_PH:
2996 case Mips::MADDU_DSP:
2997 case Mips::MADD_DSP:
2998 case Mips::MAQ_SA_W_PHL:
2999 case Mips::MAQ_SA_W_PHR:
3000 case Mips::MAQ_S_W_PHL:
3001 case Mips::MAQ_S_W_PHR:
3002 case Mips::MSUBU_DSP:
3003 case Mips::MSUB_DSP:
3004 case Mips::MULSAQ_S_W_PH:
3005 case Mips::MULSA_W_PH:
3006 case Mips::MULTU_DSP:
3007 case Mips::MULT_DSP: {
3008 // op: ac
3009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3010 op &= UINT64_C(3);
3011 op <<= 11;
3012 Value |= op;
3013 // op: rs
3014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3015 op &= UINT64_C(31);
3016 op <<= 21;
3017 Value |= op;
3018 // op: rt
3019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3020 op &= UINT64_C(31);
3021 op <<= 16;
3022 Value |= op;
3023 break;
3024 }
3025 case Mips::SHILO: {
3026 // op: ac
3027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3028 op &= UINT64_C(3);
3029 op <<= 11;
3030 Value |= op;
3031 // op: shift
3032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3033 op &= UINT64_C(63);
3034 op <<= 20;
3035 Value |= op;
3036 break;
3037 }
3038 case Mips::CACHEE:
3039 case Mips::CACHE_R6:
3040 case Mips::PREFE:
3041 case Mips::PREF_R6: {
3042 // op: addr
3043 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
3044 Value |= (op & UINT64_C(2031616)) << 5;
3045 Value |= (op & UINT64_C(511)) << 7;
3046 // op: hint
3047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3048 op &= UINT64_C(31);
3049 op <<= 16;
3050 Value |= op;
3051 break;
3052 }
3053 case Mips::SYNCI: {
3054 // op: addr
3055 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
3056 Value |= (op & UINT64_C(2031616)) << 5;
3057 Value |= (op & UINT64_C(65535));
3058 break;
3059 }
3060 case Mips::CACHE:
3061 case Mips::PREF: {
3062 // op: addr
3063 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
3064 Value |= (op & UINT64_C(2031616)) << 5;
3065 Value |= (op & UINT64_C(65535));
3066 // op: hint
3067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3068 op &= UINT64_C(31);
3069 op <<= 16;
3070 Value |= op;
3071 break;
3072 }
3073 case Mips::LD_B:
3074 case Mips::ST_B: {
3075 // op: addr
3076 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
3077 Value |= (op & UINT64_C(1023)) << 16;
3078 Value |= (op & UINT64_C(2031616)) >> 5;
3079 // op: wd
3080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3081 op &= UINT64_C(31);
3082 op <<= 6;
3083 Value |= op;
3084 break;
3085 }
3086 case Mips::LBE:
3087 case Mips::LBuE:
3088 case Mips::LHE:
3089 case Mips::LHuE:
3090 case Mips::LLE:
3091 case Mips::LWE:
3092 case Mips::LWLE:
3093 case Mips::LWRE:
3094 case Mips::SBE:
3095 case Mips::SHE:
3096 case Mips::SWE:
3097 case Mips::SWLE:
3098 case Mips::SWRE: {
3099 // op: addr
3100 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
3101 Value |= (op & UINT64_C(2031616)) << 5;
3102 Value |= (op & UINT64_C(511)) << 7;
3103 // op: rt
3104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3105 op &= UINT64_C(31);
3106 op <<= 16;
3107 Value |= op;
3108 break;
3109 }
3110 case Mips::SCE: {
3111 // op: addr
3112 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
3113 Value |= (op & UINT64_C(2031616)) << 5;
3114 Value |= (op & UINT64_C(511)) << 7;
3115 // op: rt
3116 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3117 op &= UINT64_C(31);
3118 op <<= 16;
3119 Value |= op;
3120 break;
3121 }
3122 case Mips::LD_H:
3123 case Mips::ST_H: {
3124 // op: addr
3125 op = getMemEncoding<1>(MI, OpNo: 1, Fixups, STI);
3126 Value |= (op & UINT64_C(1023)) << 16;
3127 Value |= (op & UINT64_C(2031616)) >> 5;
3128 // op: wd
3129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3130 op &= UINT64_C(31);
3131 op <<= 6;
3132 Value |= op;
3133 break;
3134 }
3135 case Mips::LD_W:
3136 case Mips::ST_W: {
3137 // op: addr
3138 op = getMemEncoding<2>(MI, OpNo: 1, Fixups, STI);
3139 Value |= (op & UINT64_C(1023)) << 16;
3140 Value |= (op & UINT64_C(2031616)) >> 5;
3141 // op: wd
3142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3143 op &= UINT64_C(31);
3144 op <<= 6;
3145 Value |= op;
3146 break;
3147 }
3148 case Mips::LD_D:
3149 case Mips::ST_D: {
3150 // op: addr
3151 op = getMemEncoding<3>(MI, OpNo: 1, Fixups, STI);
3152 Value |= (op & UINT64_C(1023)) << 16;
3153 Value |= (op & UINT64_C(2031616)) >> 5;
3154 // op: wd
3155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3156 op &= UINT64_C(31);
3157 op <<= 6;
3158 Value |= op;
3159 break;
3160 }
3161 case Mips::CACHE_MM:
3162 case Mips::CACHE_MMR6:
3163 case Mips::PREF_MM:
3164 case Mips::PREF_MMR6: {
3165 // op: addr
3166 op = getMemEncodingMMImm12(MI, OpNo: 0, Fixups, STI);
3167 Value |= (op & UINT64_C(2031616));
3168 Value |= (op & UINT64_C(4095));
3169 // op: hint
3170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3171 op &= UINT64_C(31);
3172 op <<= 21;
3173 Value |= op;
3174 break;
3175 }
3176 case Mips::SYNCI_MM:
3177 case Mips::SYNCI_MMR6: {
3178 // op: addr
3179 op = getMemEncodingMMImm16(MI, OpNo: 0, Fixups, STI);
3180 op &= UINT64_C(2097151);
3181 Value |= op;
3182 break;
3183 }
3184 case Mips::LBU_MMR6:
3185 case Mips::LB_MMR6: {
3186 // op: addr
3187 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
3188 op &= UINT64_C(2097151);
3189 Value |= op;
3190 // op: rt
3191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3192 op &= UINT64_C(31);
3193 op <<= 21;
3194 Value |= op;
3195 break;
3196 }
3197 case Mips::CACHEE_MM:
3198 case Mips::PREFE_MM: {
3199 // op: addr
3200 op = getMemEncodingMMImm9(MI, OpNo: 0, Fixups, STI);
3201 Value |= (op & UINT64_C(2031616));
3202 Value |= (op & UINT64_C(511));
3203 // op: hint
3204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3205 op &= UINT64_C(31);
3206 op <<= 21;
3207 Value |= op;
3208 break;
3209 }
3210 case Mips::HYPCALL: {
3211 // op: code_
3212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3213 op &= UINT64_C(1023);
3214 op <<= 11;
3215 Value |= op;
3216 break;
3217 }
3218 case Mips::HYPCALL_MM:
3219 case Mips::SDBBP_MM:
3220 case Mips::SDBBP_MMR6:
3221 case Mips::SYSCALL_MM:
3222 case Mips::WAIT_MM:
3223 case Mips::WAIT_MMR6: {
3224 // op: code_
3225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3226 op &= UINT64_C(1023);
3227 op <<= 16;
3228 Value |= op;
3229 break;
3230 }
3231 case Mips::SDBBP:
3232 case Mips::SDBBP_R6:
3233 case Mips::SYSCALL: {
3234 // op: code_
3235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3236 op &= UINT64_C(1048575);
3237 op <<= 6;
3238 Value |= op;
3239 break;
3240 }
3241 case Mips::BREAK16_MM:
3242 case Mips::SDBBP16_MM: {
3243 // op: code_
3244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3245 op &= UINT64_C(15);
3246 Value |= op;
3247 break;
3248 }
3249 case Mips::BREAK16_MMR6:
3250 case Mips::SDBBP16_MMR6: {
3251 // op: code_
3252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3253 op &= UINT64_C(15);
3254 op <<= 6;
3255 Value |= op;
3256 break;
3257 }
3258 case Mips::SIGRIE: {
3259 // op: code_
3260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3261 op &= UINT64_C(65535);
3262 Value |= op;
3263 break;
3264 }
3265 case Mips::SIGRIE_MMR6: {
3266 // op: code_
3267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3268 op &= UINT64_C(65535);
3269 op <<= 6;
3270 Value |= op;
3271 break;
3272 }
3273 case Mips::BREAK:
3274 case Mips::BREAK_MM:
3275 case Mips::BREAK_MMR6: {
3276 // op: code_1
3277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3278 op &= UINT64_C(1023);
3279 op <<= 16;
3280 Value |= op;
3281 // op: code_2
3282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3283 op &= UINT64_C(1023);
3284 op <<= 6;
3285 Value |= op;
3286 break;
3287 }
3288 case Mips::BC2EQZ:
3289 case Mips::BC2NEZ: {
3290 // op: ct
3291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3292 op &= UINT64_C(31);
3293 op <<= 16;
3294 Value |= op;
3295 // op: offset
3296 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3297 op &= UINT64_C(65535);
3298 Value |= op;
3299 break;
3300 }
3301 case Mips::BC1F:
3302 case Mips::BC1FL:
3303 case Mips::BC1T:
3304 case Mips::BC1TL: {
3305 // op: fcc
3306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3307 op &= UINT64_C(7);
3308 op <<= 18;
3309 Value |= op;
3310 // op: offset
3311 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3312 op &= UINT64_C(65535);
3313 Value |= op;
3314 break;
3315 }
3316 case Mips::BC1F_MM:
3317 case Mips::BC1T_MM: {
3318 // op: fcc
3319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3320 op &= UINT64_C(7);
3321 op <<= 18;
3322 Value |= op;
3323 // op: offset
3324 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
3325 op &= UINT64_C(65535);
3326 Value |= op;
3327 break;
3328 }
3329 case Mips::LUXC1_MM:
3330 case Mips::LWXC1_MM: {
3331 // op: fd
3332 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3333 op &= UINT64_C(31);
3334 op <<= 11;
3335 Value |= op;
3336 // op: base
3337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3338 op &= UINT64_C(31);
3339 op <<= 16;
3340 Value |= op;
3341 // op: index
3342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3343 op &= UINT64_C(31);
3344 op <<= 21;
3345 Value |= op;
3346 break;
3347 }
3348 case Mips::MOVN_I_D32_MM:
3349 case Mips::MOVN_I_S_MM:
3350 case Mips::MOVZ_I_D32_MM:
3351 case Mips::MOVZ_I_S_MM: {
3352 // op: fd
3353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3354 op &= UINT64_C(31);
3355 op <<= 11;
3356 Value |= op;
3357 // op: fs
3358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3359 op &= UINT64_C(31);
3360 op <<= 16;
3361 Value |= op;
3362 // op: rt
3363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3364 op &= UINT64_C(31);
3365 op <<= 21;
3366 Value |= op;
3367 break;
3368 }
3369 case Mips::CEIL_W_MM:
3370 case Mips::CEIL_W_S_MM:
3371 case Mips::CVT_D32_S_MM:
3372 case Mips::CVT_D32_W_MM:
3373 case Mips::CVT_D64_S_MM:
3374 case Mips::CVT_D64_W_MM:
3375 case Mips::CVT_L_D64_MM:
3376 case Mips::CVT_L_S_MM:
3377 case Mips::CVT_S_D32_MM:
3378 case Mips::CVT_S_D64_MM:
3379 case Mips::CVT_S_W_MM:
3380 case Mips::CVT_W_D32_MM:
3381 case Mips::CVT_W_D64_MM:
3382 case Mips::CVT_W_S_MM:
3383 case Mips::FABS_D32_MM:
3384 case Mips::FABS_D64_MM:
3385 case Mips::FABS_S_MM:
3386 case Mips::FLOOR_W_MM:
3387 case Mips::FLOOR_W_S_MM:
3388 case Mips::FMOV_D32_MM:
3389 case Mips::FMOV_D64_MM:
3390 case Mips::FMOV_S_MM:
3391 case Mips::FNEG_D32_MM:
3392 case Mips::FNEG_D64_MM:
3393 case Mips::FNEG_S_MM:
3394 case Mips::FSQRT_D32_MM:
3395 case Mips::FSQRT_D64_MM:
3396 case Mips::FSQRT_S_MM:
3397 case Mips::RECIP_D32_MM:
3398 case Mips::RECIP_D64_MM:
3399 case Mips::RECIP_S_MM:
3400 case Mips::ROUND_W_MM:
3401 case Mips::ROUND_W_S_MM:
3402 case Mips::RSQRT_D32_MM:
3403 case Mips::RSQRT_D64_MM:
3404 case Mips::RSQRT_S_MM:
3405 case Mips::TRUNC_W_MM:
3406 case Mips::TRUNC_W_S_MM: {
3407 // op: fd
3408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3409 op &= UINT64_C(31);
3410 op <<= 21;
3411 Value |= op;
3412 // op: fs
3413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3414 op &= UINT64_C(31);
3415 op <<= 16;
3416 Value |= op;
3417 break;
3418 }
3419 case Mips::MOVF_D32_MM:
3420 case Mips::MOVF_S_MM:
3421 case Mips::MOVT_D32_MM:
3422 case Mips::MOVT_S_MM: {
3423 // op: fd
3424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3425 op &= UINT64_C(31);
3426 op <<= 21;
3427 Value |= op;
3428 // op: fs
3429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3430 op &= UINT64_C(31);
3431 op <<= 16;
3432 Value |= op;
3433 // op: fcc
3434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3435 op &= UINT64_C(7);
3436 op <<= 13;
3437 Value |= op;
3438 break;
3439 }
3440 case Mips::LDXC1:
3441 case Mips::LDXC164:
3442 case Mips::LUXC1:
3443 case Mips::LUXC164:
3444 case Mips::LWXC1: {
3445 // op: fd
3446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3447 op &= UINT64_C(31);
3448 op <<= 6;
3449 Value |= op;
3450 // op: base
3451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3452 op &= UINT64_C(31);
3453 op <<= 21;
3454 Value |= op;
3455 // op: index
3456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3457 op &= UINT64_C(31);
3458 op <<= 16;
3459 Value |= op;
3460 break;
3461 }
3462 case Mips::MADD_D32:
3463 case Mips::MADD_D64:
3464 case Mips::MADD_S:
3465 case Mips::MSUB_D32:
3466 case Mips::MSUB_D64:
3467 case Mips::MSUB_S:
3468 case Mips::NMADD_D32:
3469 case Mips::NMADD_D64:
3470 case Mips::NMADD_S:
3471 case Mips::NMSUB_D32:
3472 case Mips::NMSUB_D64:
3473 case Mips::NMSUB_S: {
3474 // op: fd
3475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3476 op &= UINT64_C(31);
3477 op <<= 6;
3478 Value |= op;
3479 // op: fr
3480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3481 op &= UINT64_C(31);
3482 op <<= 21;
3483 Value |= op;
3484 // op: fs
3485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3486 op &= UINT64_C(31);
3487 op <<= 11;
3488 Value |= op;
3489 // op: ft
3490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3491 op &= UINT64_C(31);
3492 op <<= 16;
3493 Value |= op;
3494 break;
3495 }
3496 case Mips::CEIL_L_D64:
3497 case Mips::CEIL_L_S:
3498 case Mips::CEIL_W_D32:
3499 case Mips::CEIL_W_D64:
3500 case Mips::CEIL_W_S:
3501 case Mips::CVT_D32_S:
3502 case Mips::CVT_D32_W:
3503 case Mips::CVT_D64_L:
3504 case Mips::CVT_D64_S:
3505 case Mips::CVT_D64_W:
3506 case Mips::CVT_L_D64:
3507 case Mips::CVT_L_S:
3508 case Mips::CVT_PS_PW64:
3509 case Mips::CVT_PW_PS64:
3510 case Mips::CVT_S_D32:
3511 case Mips::CVT_S_D64:
3512 case Mips::CVT_S_L:
3513 case Mips::CVT_S_PL64:
3514 case Mips::CVT_S_PU64:
3515 case Mips::CVT_S_W:
3516 case Mips::CVT_W_D32:
3517 case Mips::CVT_W_D64:
3518 case Mips::CVT_W_S:
3519 case Mips::FABS_D32:
3520 case Mips::FABS_D64:
3521 case Mips::FABS_S:
3522 case Mips::FLOOR_L_D64:
3523 case Mips::FLOOR_L_S:
3524 case Mips::FLOOR_W_D32:
3525 case Mips::FLOOR_W_D64:
3526 case Mips::FLOOR_W_S:
3527 case Mips::FMOV_D32:
3528 case Mips::FMOV_D64:
3529 case Mips::FMOV_S:
3530 case Mips::FNEG_D32:
3531 case Mips::FNEG_D64:
3532 case Mips::FNEG_S:
3533 case Mips::FSQRT_D32:
3534 case Mips::FSQRT_D64:
3535 case Mips::FSQRT_S:
3536 case Mips::RECIP_D32:
3537 case Mips::RECIP_D64:
3538 case Mips::RECIP_S:
3539 case Mips::ROUND_L_D64:
3540 case Mips::ROUND_L_S:
3541 case Mips::ROUND_W_D32:
3542 case Mips::ROUND_W_D64:
3543 case Mips::ROUND_W_S:
3544 case Mips::RSQRT_D32:
3545 case Mips::RSQRT_D64:
3546 case Mips::RSQRT_S:
3547 case Mips::TRUNC_L_D64:
3548 case Mips::TRUNC_L_S:
3549 case Mips::TRUNC_W_D32:
3550 case Mips::TRUNC_W_D64:
3551 case Mips::TRUNC_W_S: {
3552 // op: fd
3553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3554 op &= UINT64_C(31);
3555 op <<= 6;
3556 Value |= op;
3557 // op: fs
3558 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3559 op &= UINT64_C(31);
3560 op <<= 11;
3561 Value |= op;
3562 break;
3563 }
3564 case Mips::MOVF_D32:
3565 case Mips::MOVF_D64:
3566 case Mips::MOVF_S:
3567 case Mips::MOVT_D32:
3568 case Mips::MOVT_D64:
3569 case Mips::MOVT_S: {
3570 // op: fd
3571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3572 op &= UINT64_C(31);
3573 op <<= 6;
3574 Value |= op;
3575 // op: fs
3576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3577 op &= UINT64_C(31);
3578 op <<= 11;
3579 Value |= op;
3580 // op: fcc
3581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3582 op &= UINT64_C(7);
3583 op <<= 18;
3584 Value |= op;
3585 break;
3586 }
3587 case Mips::ADDR_PS64:
3588 case Mips::CMP_EQ_D:
3589 case Mips::CMP_EQ_S:
3590 case Mips::CMP_F_D:
3591 case Mips::CMP_F_S:
3592 case Mips::CMP_LE_D:
3593 case Mips::CMP_LE_S:
3594 case Mips::CMP_LT_D:
3595 case Mips::CMP_LT_S:
3596 case Mips::CMP_SAF_D:
3597 case Mips::CMP_SAF_S:
3598 case Mips::CMP_SEQ_D:
3599 case Mips::CMP_SEQ_S:
3600 case Mips::CMP_SLE_D:
3601 case Mips::CMP_SLE_S:
3602 case Mips::CMP_SLT_D:
3603 case Mips::CMP_SLT_S:
3604 case Mips::CMP_SUEQ_D:
3605 case Mips::CMP_SUEQ_S:
3606 case Mips::CMP_SULE_D:
3607 case Mips::CMP_SULE_S:
3608 case Mips::CMP_SULT_D:
3609 case Mips::CMP_SULT_S:
3610 case Mips::CMP_SUN_D:
3611 case Mips::CMP_SUN_S:
3612 case Mips::CMP_UEQ_D:
3613 case Mips::CMP_UEQ_S:
3614 case Mips::CMP_ULE_D:
3615 case Mips::CMP_ULE_S:
3616 case Mips::CMP_ULT_D:
3617 case Mips::CMP_ULT_S:
3618 case Mips::CMP_UN_D:
3619 case Mips::CMP_UN_S:
3620 case Mips::CVT_PS_S64:
3621 case Mips::FADD_D32:
3622 case Mips::FADD_D64:
3623 case Mips::FADD_PS64:
3624 case Mips::FADD_S:
3625 case Mips::FDIV_D32:
3626 case Mips::FDIV_D64:
3627 case Mips::FDIV_S:
3628 case Mips::FMUL_D32:
3629 case Mips::FMUL_D64:
3630 case Mips::FMUL_PS64:
3631 case Mips::FMUL_S:
3632 case Mips::FSUB_D32:
3633 case Mips::FSUB_D64:
3634 case Mips::FSUB_PS64:
3635 case Mips::FSUB_S:
3636 case Mips::MULR_PS64:
3637 case Mips::PLL_PS64:
3638 case Mips::PLU_PS64:
3639 case Mips::PUL_PS64:
3640 case Mips::PUU_PS64: {
3641 // op: fd
3642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3643 op &= UINT64_C(31);
3644 op <<= 6;
3645 Value |= op;
3646 // op: fs
3647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3648 op &= UINT64_C(31);
3649 op <<= 11;
3650 Value |= op;
3651 // op: ft
3652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3653 op &= UINT64_C(31);
3654 op <<= 16;
3655 Value |= op;
3656 break;
3657 }
3658 case Mips::MOVN_I64_D64:
3659 case Mips::MOVN_I64_S:
3660 case Mips::MOVN_I_D32:
3661 case Mips::MOVN_I_D64:
3662 case Mips::MOVN_I_S:
3663 case Mips::MOVZ_I64_D64:
3664 case Mips::MOVZ_I64_S:
3665 case Mips::MOVZ_I_D32:
3666 case Mips::MOVZ_I_D64:
3667 case Mips::MOVZ_I_S: {
3668 // op: fd
3669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3670 op &= UINT64_C(31);
3671 op <<= 6;
3672 Value |= op;
3673 // op: fs
3674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3675 op &= UINT64_C(31);
3676 op <<= 11;
3677 Value |= op;
3678 // op: rt
3679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3680 op &= UINT64_C(31);
3681 op <<= 16;
3682 Value |= op;
3683 break;
3684 }
3685 case Mips::SUXC1_MM:
3686 case Mips::SWXC1_MM: {
3687 // op: fs
3688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3689 op &= UINT64_C(31);
3690 op <<= 11;
3691 Value |= op;
3692 // op: base
3693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3694 op &= UINT64_C(31);
3695 op <<= 16;
3696 Value |= op;
3697 // op: index
3698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3699 op &= UINT64_C(31);
3700 op <<= 21;
3701 Value |= op;
3702 break;
3703 }
3704 case Mips::SDXC1:
3705 case Mips::SDXC164:
3706 case Mips::SUXC1:
3707 case Mips::SUXC164:
3708 case Mips::SWXC1: {
3709 // op: fs
3710 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3711 op &= UINT64_C(31);
3712 op <<= 11;
3713 Value |= op;
3714 // op: base
3715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3716 op &= UINT64_C(31);
3717 op <<= 21;
3718 Value |= op;
3719 // op: index
3720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3721 op &= UINT64_C(31);
3722 op <<= 16;
3723 Value |= op;
3724 break;
3725 }
3726 case Mips::FCMP_D32:
3727 case Mips::FCMP_D64:
3728 case Mips::FCMP_S32: {
3729 // op: fs
3730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3731 op &= UINT64_C(31);
3732 op <<= 11;
3733 Value |= op;
3734 // op: ft
3735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3736 op &= UINT64_C(31);
3737 op <<= 16;
3738 Value |= op;
3739 // op: cond
3740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3741 op &= UINT64_C(15);
3742 Value |= op;
3743 break;
3744 }
3745 case Mips::FCMP_D32_MM:
3746 case Mips::FCMP_S32_MM: {
3747 // op: fs
3748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3749 op &= UINT64_C(31);
3750 op <<= 16;
3751 Value |= op;
3752 // op: ft
3753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3754 op &= UINT64_C(31);
3755 op <<= 21;
3756 Value |= op;
3757 // op: cond
3758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3759 op &= UINT64_C(15);
3760 op <<= 6;
3761 Value |= op;
3762 break;
3763 }
3764 case Mips::CLASS_D:
3765 case Mips::CLASS_S:
3766 case Mips::RINT_D:
3767 case Mips::RINT_S: {
3768 // op: fs
3769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3770 op &= UINT64_C(31);
3771 op <<= 11;
3772 Value |= op;
3773 // op: fd
3774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3775 op &= UINT64_C(31);
3776 op <<= 6;
3777 Value |= op;
3778 break;
3779 }
3780 case Mips::C_EQ_D32:
3781 case Mips::C_EQ_D64:
3782 case Mips::C_EQ_S:
3783 case Mips::C_F_D32:
3784 case Mips::C_F_D64:
3785 case Mips::C_F_S:
3786 case Mips::C_LE_D32:
3787 case Mips::C_LE_D64:
3788 case Mips::C_LE_S:
3789 case Mips::C_LT_D32:
3790 case Mips::C_LT_D64:
3791 case Mips::C_LT_S:
3792 case Mips::C_NGE_D32:
3793 case Mips::C_NGE_D64:
3794 case Mips::C_NGE_S:
3795 case Mips::C_NGLE_D32:
3796 case Mips::C_NGLE_D64:
3797 case Mips::C_NGLE_S:
3798 case Mips::C_NGL_D32:
3799 case Mips::C_NGL_D64:
3800 case Mips::C_NGL_S:
3801 case Mips::C_NGT_D32:
3802 case Mips::C_NGT_D64:
3803 case Mips::C_NGT_S:
3804 case Mips::C_OLE_D32:
3805 case Mips::C_OLE_D64:
3806 case Mips::C_OLE_S:
3807 case Mips::C_OLT_D32:
3808 case Mips::C_OLT_D64:
3809 case Mips::C_OLT_S:
3810 case Mips::C_SEQ_D32:
3811 case Mips::C_SEQ_D64:
3812 case Mips::C_SEQ_S:
3813 case Mips::C_SF_D32:
3814 case Mips::C_SF_D64:
3815 case Mips::C_SF_S:
3816 case Mips::C_UEQ_D32:
3817 case Mips::C_UEQ_D64:
3818 case Mips::C_UEQ_S:
3819 case Mips::C_ULE_D32:
3820 case Mips::C_ULE_D64:
3821 case Mips::C_ULE_S:
3822 case Mips::C_ULT_D32:
3823 case Mips::C_ULT_D64:
3824 case Mips::C_ULT_S:
3825 case Mips::C_UN_D32:
3826 case Mips::C_UN_D64:
3827 case Mips::C_UN_S: {
3828 // op: fs
3829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3830 op &= UINT64_C(31);
3831 op <<= 11;
3832 Value |= op;
3833 // op: ft
3834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3835 op &= UINT64_C(31);
3836 op <<= 16;
3837 Value |= op;
3838 // op: fcc
3839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3840 op &= UINT64_C(7);
3841 op <<= 8;
3842 Value |= op;
3843 break;
3844 }
3845 case Mips::C_EQ_D32_MM:
3846 case Mips::C_EQ_D64_MM:
3847 case Mips::C_EQ_S_MM:
3848 case Mips::C_F_D32_MM:
3849 case Mips::C_F_D64_MM:
3850 case Mips::C_F_S_MM:
3851 case Mips::C_LE_D32_MM:
3852 case Mips::C_LE_D64_MM:
3853 case Mips::C_LE_S_MM:
3854 case Mips::C_LT_D32_MM:
3855 case Mips::C_LT_D64_MM:
3856 case Mips::C_LT_S_MM:
3857 case Mips::C_NGE_D32_MM:
3858 case Mips::C_NGE_D64_MM:
3859 case Mips::C_NGE_S_MM:
3860 case Mips::C_NGLE_D32_MM:
3861 case Mips::C_NGLE_D64_MM:
3862 case Mips::C_NGLE_S_MM:
3863 case Mips::C_NGL_D32_MM:
3864 case Mips::C_NGL_D64_MM:
3865 case Mips::C_NGL_S_MM:
3866 case Mips::C_NGT_D32_MM:
3867 case Mips::C_NGT_D64_MM:
3868 case Mips::C_NGT_S_MM:
3869 case Mips::C_OLE_D32_MM:
3870 case Mips::C_OLE_D64_MM:
3871 case Mips::C_OLE_S_MM:
3872 case Mips::C_OLT_D32_MM:
3873 case Mips::C_OLT_D64_MM:
3874 case Mips::C_OLT_S_MM:
3875 case Mips::C_SEQ_D32_MM:
3876 case Mips::C_SEQ_D64_MM:
3877 case Mips::C_SEQ_S_MM:
3878 case Mips::C_SF_D32_MM:
3879 case Mips::C_SF_D64_MM:
3880 case Mips::C_SF_S_MM:
3881 case Mips::C_UEQ_D32_MM:
3882 case Mips::C_UEQ_D64_MM:
3883 case Mips::C_UEQ_S_MM:
3884 case Mips::C_ULE_D32_MM:
3885 case Mips::C_ULE_D64_MM:
3886 case Mips::C_ULE_S_MM:
3887 case Mips::C_ULT_D32_MM:
3888 case Mips::C_ULT_D64_MM:
3889 case Mips::C_ULT_S_MM:
3890 case Mips::C_UN_D32_MM:
3891 case Mips::C_UN_D64_MM:
3892 case Mips::C_UN_S_MM: {
3893 // op: fs
3894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3895 op &= UINT64_C(31);
3896 op <<= 16;
3897 Value |= op;
3898 // op: ft
3899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3900 op &= UINT64_C(31);
3901 op <<= 21;
3902 Value |= op;
3903 // op: fcc
3904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3905 op &= UINT64_C(7);
3906 op <<= 13;
3907 Value |= op;
3908 break;
3909 }
3910 case Mips::CLASS_D_MMR6:
3911 case Mips::CLASS_S_MMR6:
3912 case Mips::RINT_D_MMR6:
3913 case Mips::RINT_S_MMR6: {
3914 // op: fs
3915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3916 op &= UINT64_C(31);
3917 op <<= 21;
3918 Value |= op;
3919 // op: fd
3920 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3921 op &= UINT64_C(31);
3922 op <<= 16;
3923 Value |= op;
3924 break;
3925 }
3926 case Mips::BC1EQZ:
3927 case Mips::BC1NEZ: {
3928 // op: ft
3929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3930 op &= UINT64_C(31);
3931 op <<= 16;
3932 Value |= op;
3933 // op: offset
3934 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3935 op &= UINT64_C(65535);
3936 Value |= op;
3937 break;
3938 }
3939 case Mips::LDC1_D64_MMR6:
3940 case Mips::SDC1_D64_MMR6: {
3941 // op: ft
3942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3943 op &= UINT64_C(31);
3944 op <<= 21;
3945 Value |= op;
3946 // op: addr
3947 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
3948 op &= UINT64_C(2097151);
3949 Value |= op;
3950 break;
3951 }
3952 case Mips::CEIL_L_D_MMR6:
3953 case Mips::CEIL_L_S_MMR6:
3954 case Mips::CEIL_W_D_MMR6:
3955 case Mips::CEIL_W_S_MMR6:
3956 case Mips::CVT_D_L_MMR6:
3957 case Mips::CVT_L_D_MMR6:
3958 case Mips::CVT_L_S_MMR6:
3959 case Mips::CVT_S_L_MMR6:
3960 case Mips::CVT_S_W_MMR6:
3961 case Mips::CVT_W_S_MMR6:
3962 case Mips::FLOOR_L_D_MMR6:
3963 case Mips::FLOOR_L_S_MMR6:
3964 case Mips::FLOOR_W_D_MMR6:
3965 case Mips::FLOOR_W_S_MMR6:
3966 case Mips::FMOV_D_MMR6:
3967 case Mips::FMOV_S_MMR6:
3968 case Mips::FNEG_S_MMR6:
3969 case Mips::ROUND_L_D_MMR6:
3970 case Mips::ROUND_L_S_MMR6:
3971 case Mips::ROUND_W_D_MMR6:
3972 case Mips::ROUND_W_S_MMR6:
3973 case Mips::TRUNC_L_D_MMR6:
3974 case Mips::TRUNC_L_S_MMR6:
3975 case Mips::TRUNC_W_D_MMR6:
3976 case Mips::TRUNC_W_S_MMR6: {
3977 // op: ft
3978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3979 op &= UINT64_C(31);
3980 op <<= 21;
3981 Value |= op;
3982 // op: fs
3983 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3984 op &= UINT64_C(31);
3985 op <<= 16;
3986 Value |= op;
3987 break;
3988 }
3989 case Mips::FADD_S_MMR6:
3990 case Mips::FDIV_S_MMR6:
3991 case Mips::FMUL_S_MMR6:
3992 case Mips::FSUB_S_MMR6: {
3993 // op: ft
3994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3995 op &= UINT64_C(31);
3996 op <<= 21;
3997 Value |= op;
3998 // op: fs
3999 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4000 op &= UINT64_C(31);
4001 op <<= 16;
4002 Value |= op;
4003 // op: fd
4004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4005 op &= UINT64_C(31);
4006 op <<= 11;
4007 Value |= op;
4008 break;
4009 }
4010 case Mips::MAXA_D:
4011 case Mips::MAXA_S:
4012 case Mips::MAX_D:
4013 case Mips::MAX_S:
4014 case Mips::MINA_D:
4015 case Mips::MINA_S:
4016 case Mips::MIN_D:
4017 case Mips::MIN_S:
4018 case Mips::SELEQZ_D:
4019 case Mips::SELEQZ_S:
4020 case Mips::SELNEZ_D:
4021 case Mips::SELNEZ_S: {
4022 // op: ft
4023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4024 op &= UINT64_C(31);
4025 op <<= 16;
4026 Value |= op;
4027 // op: fs
4028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4029 op &= UINT64_C(31);
4030 op <<= 11;
4031 Value |= op;
4032 // op: fd
4033 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4034 op &= UINT64_C(31);
4035 op <<= 6;
4036 Value |= op;
4037 break;
4038 }
4039 case Mips::CMP_AF_D_MMR6:
4040 case Mips::CMP_AF_S_MMR6:
4041 case Mips::CMP_EQ_D_MMR6:
4042 case Mips::CMP_EQ_S_MMR6:
4043 case Mips::CMP_LE_D_MMR6:
4044 case Mips::CMP_LE_S_MMR6:
4045 case Mips::CMP_LT_D_MMR6:
4046 case Mips::CMP_LT_S_MMR6:
4047 case Mips::CMP_SAF_D_MMR6:
4048 case Mips::CMP_SAF_S_MMR6:
4049 case Mips::CMP_SEQ_D_MMR6:
4050 case Mips::CMP_SEQ_S_MMR6:
4051 case Mips::CMP_SLE_D_MMR6:
4052 case Mips::CMP_SLE_S_MMR6:
4053 case Mips::CMP_SLT_D_MMR6:
4054 case Mips::CMP_SLT_S_MMR6:
4055 case Mips::CMP_SUEQ_D_MMR6:
4056 case Mips::CMP_SUEQ_S_MMR6:
4057 case Mips::CMP_SULE_D_MMR6:
4058 case Mips::CMP_SULE_S_MMR6:
4059 case Mips::CMP_SULT_D_MMR6:
4060 case Mips::CMP_SULT_S_MMR6:
4061 case Mips::CMP_SUN_D_MMR6:
4062 case Mips::CMP_SUN_S_MMR6:
4063 case Mips::CMP_UEQ_D_MMR6:
4064 case Mips::CMP_UEQ_S_MMR6:
4065 case Mips::CMP_ULE_D_MMR6:
4066 case Mips::CMP_ULE_S_MMR6:
4067 case Mips::CMP_ULT_D_MMR6:
4068 case Mips::CMP_ULT_S_MMR6:
4069 case Mips::CMP_UN_D_MMR6:
4070 case Mips::CMP_UN_S_MMR6:
4071 case Mips::FADD_D32_MM:
4072 case Mips::FADD_D64_MM:
4073 case Mips::FADD_S_MM:
4074 case Mips::FDIV_D32_MM:
4075 case Mips::FDIV_D64_MM:
4076 case Mips::FDIV_S_MM:
4077 case Mips::FMUL_D32_MM:
4078 case Mips::FMUL_D64_MM:
4079 case Mips::FMUL_S_MM:
4080 case Mips::FSUB_D32_MM:
4081 case Mips::FSUB_D64_MM:
4082 case Mips::FSUB_S_MM:
4083 case Mips::MAXA_D_MMR6:
4084 case Mips::MAXA_S_MMR6:
4085 case Mips::MAX_D_MMR6:
4086 case Mips::MAX_S_MMR6:
4087 case Mips::MINA_D_MMR6:
4088 case Mips::MINA_S_MMR6:
4089 case Mips::MIN_D_MMR6:
4090 case Mips::MIN_S_MMR6:
4091 case Mips::SELEQZ_D_MMR6:
4092 case Mips::SELEQZ_S_MMR6:
4093 case Mips::SELNEZ_D_MMR6:
4094 case Mips::SELNEZ_S_MMR6: {
4095 // op: ft
4096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4097 op &= UINT64_C(31);
4098 op <<= 21;
4099 Value |= op;
4100 // op: fs
4101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4102 op &= UINT64_C(31);
4103 op <<= 16;
4104 Value |= op;
4105 // op: fd
4106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4107 op &= UINT64_C(31);
4108 op <<= 11;
4109 Value |= op;
4110 break;
4111 }
4112 case Mips::MADDF_D:
4113 case Mips::MADDF_S:
4114 case Mips::MSUBF_D:
4115 case Mips::MSUBF_S:
4116 case Mips::SEL_D:
4117 case Mips::SEL_S: {
4118 // op: ft
4119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4120 op &= UINT64_C(31);
4121 op <<= 16;
4122 Value |= op;
4123 // op: fs
4124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4125 op &= UINT64_C(31);
4126 op <<= 11;
4127 Value |= op;
4128 // op: fd
4129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4130 op &= UINT64_C(31);
4131 op <<= 6;
4132 Value |= op;
4133 break;
4134 }
4135 case Mips::MADDF_D_MMR6:
4136 case Mips::MADDF_S_MMR6:
4137 case Mips::MSUBF_D_MMR6:
4138 case Mips::MSUBF_S_MMR6:
4139 case Mips::SEL_D_MMR6:
4140 case Mips::SEL_S_MMR6: {
4141 // op: ft
4142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4143 op &= UINT64_C(31);
4144 op <<= 21;
4145 Value |= op;
4146 // op: fs
4147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4148 op &= UINT64_C(31);
4149 op <<= 16;
4150 Value |= op;
4151 // op: fd
4152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4153 op &= UINT64_C(31);
4154 op <<= 11;
4155 Value |= op;
4156 break;
4157 }
4158 case Mips::MADD_D32_MM:
4159 case Mips::MADD_S_MM:
4160 case Mips::MSUB_D32_MM:
4161 case Mips::MSUB_S_MM:
4162 case Mips::NMADD_D32_MM:
4163 case Mips::NMADD_S_MM:
4164 case Mips::NMSUB_D32_MM:
4165 case Mips::NMSUB_S_MM: {
4166 // op: ft
4167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4168 op &= UINT64_C(31);
4169 op <<= 21;
4170 Value |= op;
4171 // op: fs
4172 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4173 op &= UINT64_C(31);
4174 op <<= 16;
4175 Value |= op;
4176 // op: fd
4177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4178 op &= UINT64_C(31);
4179 op <<= 11;
4180 Value |= op;
4181 // op: fr
4182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4183 op &= UINT64_C(31);
4184 op <<= 6;
4185 Value |= op;
4186 break;
4187 }
4188 case Mips::ADDVI_B:
4189 case Mips::ADDVI_D:
4190 case Mips::ADDVI_H:
4191 case Mips::ADDVI_W:
4192 case Mips::CEQI_B:
4193 case Mips::CEQI_D:
4194 case Mips::CEQI_H:
4195 case Mips::CEQI_W:
4196 case Mips::CLEI_S_B:
4197 case Mips::CLEI_S_D:
4198 case Mips::CLEI_S_H:
4199 case Mips::CLEI_S_W:
4200 case Mips::CLEI_U_B:
4201 case Mips::CLEI_U_D:
4202 case Mips::CLEI_U_H:
4203 case Mips::CLEI_U_W:
4204 case Mips::CLTI_S_B:
4205 case Mips::CLTI_S_D:
4206 case Mips::CLTI_S_H:
4207 case Mips::CLTI_S_W:
4208 case Mips::CLTI_U_B:
4209 case Mips::CLTI_U_D:
4210 case Mips::CLTI_U_H:
4211 case Mips::CLTI_U_W:
4212 case Mips::MAXI_S_B:
4213 case Mips::MAXI_S_D:
4214 case Mips::MAXI_S_H:
4215 case Mips::MAXI_S_W:
4216 case Mips::MAXI_U_B:
4217 case Mips::MAXI_U_D:
4218 case Mips::MAXI_U_H:
4219 case Mips::MAXI_U_W:
4220 case Mips::MINI_S_B:
4221 case Mips::MINI_S_D:
4222 case Mips::MINI_S_H:
4223 case Mips::MINI_S_W:
4224 case Mips::MINI_U_B:
4225 case Mips::MINI_U_D:
4226 case Mips::MINI_U_H:
4227 case Mips::MINI_U_W:
4228 case Mips::SUBVI_B:
4229 case Mips::SUBVI_D:
4230 case Mips::SUBVI_H:
4231 case Mips::SUBVI_W: {
4232 // op: imm
4233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4234 op &= UINT64_C(31);
4235 op <<= 16;
4236 Value |= op;
4237 // op: ws
4238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4239 op &= UINT64_C(31);
4240 op <<= 11;
4241 Value |= op;
4242 // op: wd
4243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4244 op &= UINT64_C(31);
4245 op <<= 6;
4246 Value |= op;
4247 break;
4248 }
4249 case Mips::ADDIUSP_MM: {
4250 // op: imm
4251 op = getSImm9AddiuspValue(MI, OpNo: 0, Fixups, STI);
4252 op &= UINT64_C(511);
4253 op <<= 1;
4254 Value |= op;
4255 break;
4256 }
4257 case Mips::JRADDIUSP: {
4258 // op: imm
4259 op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI);
4260 op &= UINT64_C(31);
4261 Value |= op;
4262 break;
4263 }
4264 case Mips::JRCADDIUSP_MMR6: {
4265 // op: imm
4266 op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI);
4267 op &= UINT64_C(31);
4268 op <<= 5;
4269 Value |= op;
4270 break;
4271 }
4272 case Mips::Bimm16: {
4273 // op: imm11
4274 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
4275 op &= UINT64_C(2047);
4276 Value |= op;
4277 break;
4278 }
4279 case Mips::AddiuRxRyOffMemX16: {
4280 // op: imm15
4281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4282 Value |= (op & UINT64_C(2032)) << 16;
4283 Value |= (op & UINT64_C(30720)) << 5;
4284 Value |= (op & UINT64_C(15));
4285 // op: rx
4286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4287 op &= UINT64_C(7);
4288 op <<= 8;
4289 Value |= op;
4290 // op: ry
4291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4292 op &= UINT64_C(7);
4293 op <<= 5;
4294 Value |= op;
4295 break;
4296 }
4297 case Mips::BimmX16: {
4298 // op: imm16
4299 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
4300 Value |= (op & UINT64_C(2016)) << 16;
4301 Value |= (op & UINT64_C(63488)) << 5;
4302 Value |= (op & UINT64_C(31));
4303 break;
4304 }
4305 case Mips::BeqzRxImmX16:
4306 case Mips::BnezRxImmX16: {
4307 // op: imm16
4308 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
4309 Value |= (op & UINT64_C(2016)) << 16;
4310 Value |= (op & UINT64_C(63488)) << 5;
4311 Value |= (op & UINT64_C(31));
4312 // op: rx
4313 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4314 op &= UINT64_C(7);
4315 op <<= 8;
4316 Value |= op;
4317 break;
4318 }
4319 case Mips::AddiuSpImmX16:
4320 case Mips::BteqzX16:
4321 case Mips::BtnezX16: {
4322 // op: imm16
4323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4324 Value |= (op & UINT64_C(2016)) << 16;
4325 Value |= (op & UINT64_C(63488)) << 5;
4326 Value |= (op & UINT64_C(31));
4327 break;
4328 }
4329 case Mips::AddiuRxImmX16:
4330 case Mips::AddiuRxPcImmX16:
4331 case Mips::CmpiRxImmX16:
4332 case Mips::LiRxImmAlignX16:
4333 case Mips::LiRxImmX16:
4334 case Mips::LwRxPcTcpX16:
4335 case Mips::SltiRxImmX16:
4336 case Mips::SltiuRxImmX16: {
4337 // op: imm16
4338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4339 Value |= (op & UINT64_C(2016)) << 16;
4340 Value |= (op & UINT64_C(63488)) << 5;
4341 Value |= (op & UINT64_C(31));
4342 // op: rx
4343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4344 op &= UINT64_C(7);
4345 op <<= 8;
4346 Value |= op;
4347 break;
4348 }
4349 case Mips::AddiuRxRxImmX16: {
4350 // op: imm16
4351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4352 Value |= (op & UINT64_C(2016)) << 16;
4353 Value |= (op & UINT64_C(63488)) << 5;
4354 Value |= (op & UINT64_C(31));
4355 // op: rx
4356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4357 op &= UINT64_C(7);
4358 op <<= 8;
4359 Value |= op;
4360 break;
4361 }
4362 case Mips::LbRxRyOffMemX16:
4363 case Mips::LbuRxRyOffMemX16:
4364 case Mips::LhRxRyOffMemX16:
4365 case Mips::LhuRxRyOffMemX16:
4366 case Mips::LwRxRyOffMemX16:
4367 case Mips::LwRxSpImmX16:
4368 case Mips::SbRxRyOffMemX16:
4369 case Mips::ShRxRyOffMemX16:
4370 case Mips::SwRxRyOffMemX16:
4371 case Mips::SwRxSpImmX16: {
4372 // op: imm16
4373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4374 Value |= (op & UINT64_C(2016)) << 16;
4375 Value |= (op & UINT64_C(63488)) << 5;
4376 Value |= (op & UINT64_C(31));
4377 // op: rx
4378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4379 op &= UINT64_C(7);
4380 op <<= 8;
4381 Value |= op;
4382 // op: ry
4383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4384 op &= UINT64_C(7);
4385 op <<= 5;
4386 Value |= op;
4387 break;
4388 }
4389 case Mips::Jal16:
4390 case Mips::JalB16: {
4391 // op: imm26
4392 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4393 Value |= (op & UINT64_C(2031616)) << 5;
4394 Value |= (op & UINT64_C(65011712)) >> 5;
4395 Value |= (op & UINT64_C(65535));
4396 break;
4397 }
4398 case Mips::AddiuSpImm16:
4399 case Mips::Bteqz16:
4400 case Mips::Btnez16: {
4401 // op: imm8
4402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4403 op &= UINT64_C(255);
4404 Value |= op;
4405 break;
4406 }
4407 case Mips::PREFX_MM: {
4408 // op: index
4409 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4410 op &= UINT64_C(31);
4411 op <<= 21;
4412 Value |= op;
4413 // op: base
4414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4415 op &= UINT64_C(31);
4416 op <<= 16;
4417 Value |= op;
4418 // op: hint
4419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4420 op &= UINT64_C(31);
4421 op <<= 11;
4422 Value |= op;
4423 break;
4424 }
4425 case Mips::LBUX_MM:
4426 case Mips::LHX_MM:
4427 case Mips::LWX_MM: {
4428 // op: index
4429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4430 op &= UINT64_C(31);
4431 op <<= 21;
4432 Value |= op;
4433 // op: base
4434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4435 op &= UINT64_C(31);
4436 op <<= 16;
4437 Value |= op;
4438 // op: rd
4439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4440 op &= UINT64_C(31);
4441 op <<= 11;
4442 Value |= op;
4443 break;
4444 }
4445 case Mips::COPY_S_D: {
4446 // op: n
4447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4448 op &= UINT64_C(1);
4449 op <<= 16;
4450 Value |= op;
4451 // op: ws
4452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4453 op &= UINT64_C(31);
4454 op <<= 11;
4455 Value |= op;
4456 // op: rd
4457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4458 op &= UINT64_C(31);
4459 op <<= 6;
4460 Value |= op;
4461 break;
4462 }
4463 case Mips::SPLATI_D: {
4464 // op: n
4465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4466 op &= UINT64_C(1);
4467 op <<= 16;
4468 Value |= op;
4469 // op: ws
4470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4471 op &= UINT64_C(31);
4472 op <<= 11;
4473 Value |= op;
4474 // op: wd
4475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4476 op &= UINT64_C(31);
4477 op <<= 6;
4478 Value |= op;
4479 break;
4480 }
4481 case Mips::INSVE_D: {
4482 // op: n
4483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4484 op &= UINT64_C(1);
4485 op <<= 16;
4486 Value |= op;
4487 // op: ws
4488 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4489 op &= UINT64_C(31);
4490 op <<= 11;
4491 Value |= op;
4492 // op: wd
4493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4494 op &= UINT64_C(31);
4495 op <<= 6;
4496 Value |= op;
4497 break;
4498 }
4499 case Mips::COPY_S_B:
4500 case Mips::COPY_U_B: {
4501 // op: n
4502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4503 op &= UINT64_C(15);
4504 op <<= 16;
4505 Value |= op;
4506 // op: ws
4507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4508 op &= UINT64_C(31);
4509 op <<= 11;
4510 Value |= op;
4511 // op: rd
4512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4513 op &= UINT64_C(31);
4514 op <<= 6;
4515 Value |= op;
4516 break;
4517 }
4518 case Mips::SPLATI_B: {
4519 // op: n
4520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4521 op &= UINT64_C(15);
4522 op <<= 16;
4523 Value |= op;
4524 // op: ws
4525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4526 op &= UINT64_C(31);
4527 op <<= 11;
4528 Value |= op;
4529 // op: wd
4530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4531 op &= UINT64_C(31);
4532 op <<= 6;
4533 Value |= op;
4534 break;
4535 }
4536 case Mips::INSVE_B: {
4537 // op: n
4538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4539 op &= UINT64_C(15);
4540 op <<= 16;
4541 Value |= op;
4542 // op: ws
4543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4544 op &= UINT64_C(31);
4545 op <<= 11;
4546 Value |= op;
4547 // op: wd
4548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4549 op &= UINT64_C(31);
4550 op <<= 6;
4551 Value |= op;
4552 break;
4553 }
4554 case Mips::COPY_S_W:
4555 case Mips::COPY_U_W: {
4556 // op: n
4557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4558 op &= UINT64_C(3);
4559 op <<= 16;
4560 Value |= op;
4561 // op: ws
4562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4563 op &= UINT64_C(31);
4564 op <<= 11;
4565 Value |= op;
4566 // op: rd
4567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4568 op &= UINT64_C(31);
4569 op <<= 6;
4570 Value |= op;
4571 break;
4572 }
4573 case Mips::SPLATI_W: {
4574 // op: n
4575 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4576 op &= UINT64_C(3);
4577 op <<= 16;
4578 Value |= op;
4579 // op: ws
4580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4581 op &= UINT64_C(31);
4582 op <<= 11;
4583 Value |= op;
4584 // op: wd
4585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4586 op &= UINT64_C(31);
4587 op <<= 6;
4588 Value |= op;
4589 break;
4590 }
4591 case Mips::INSVE_W: {
4592 // op: n
4593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4594 op &= UINT64_C(3);
4595 op <<= 16;
4596 Value |= op;
4597 // op: ws
4598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4599 op &= UINT64_C(31);
4600 op <<= 11;
4601 Value |= op;
4602 // op: wd
4603 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4604 op &= UINT64_C(31);
4605 op <<= 6;
4606 Value |= op;
4607 break;
4608 }
4609 case Mips::COPY_S_H:
4610 case Mips::COPY_U_H: {
4611 // op: n
4612 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4613 op &= UINT64_C(7);
4614 op <<= 16;
4615 Value |= op;
4616 // op: ws
4617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4618 op &= UINT64_C(31);
4619 op <<= 11;
4620 Value |= op;
4621 // op: rd
4622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4623 op &= UINT64_C(31);
4624 op <<= 6;
4625 Value |= op;
4626 break;
4627 }
4628 case Mips::SPLATI_H: {
4629 // op: n
4630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4631 op &= UINT64_C(7);
4632 op <<= 16;
4633 Value |= op;
4634 // op: ws
4635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4636 op &= UINT64_C(31);
4637 op <<= 11;
4638 Value |= op;
4639 // op: wd
4640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4641 op &= UINT64_C(31);
4642 op <<= 6;
4643 Value |= op;
4644 break;
4645 }
4646 case Mips::INSVE_H: {
4647 // op: n
4648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4649 op &= UINT64_C(7);
4650 op <<= 16;
4651 Value |= op;
4652 // op: ws
4653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4654 op &= UINT64_C(31);
4655 op <<= 11;
4656 Value |= op;
4657 // op: wd
4658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4659 op &= UINT64_C(31);
4660 op <<= 6;
4661 Value |= op;
4662 break;
4663 }
4664 case Mips::INSERT_D: {
4665 // op: n
4666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4667 op &= UINT64_C(1);
4668 op <<= 16;
4669 Value |= op;
4670 // op: rs
4671 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4672 op &= UINT64_C(31);
4673 op <<= 11;
4674 Value |= op;
4675 // op: wd
4676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4677 op &= UINT64_C(31);
4678 op <<= 6;
4679 Value |= op;
4680 break;
4681 }
4682 case Mips::SLDI_D: {
4683 // op: n
4684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4685 op &= UINT64_C(1);
4686 op <<= 16;
4687 Value |= op;
4688 // op: ws
4689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4690 op &= UINT64_C(31);
4691 op <<= 11;
4692 Value |= op;
4693 // op: wd
4694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4695 op &= UINT64_C(31);
4696 op <<= 6;
4697 Value |= op;
4698 break;
4699 }
4700 case Mips::INSERT_B: {
4701 // op: n
4702 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4703 op &= UINT64_C(15);
4704 op <<= 16;
4705 Value |= op;
4706 // op: rs
4707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4708 op &= UINT64_C(31);
4709 op <<= 11;
4710 Value |= op;
4711 // op: wd
4712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4713 op &= UINT64_C(31);
4714 op <<= 6;
4715 Value |= op;
4716 break;
4717 }
4718 case Mips::SLDI_B: {
4719 // op: n
4720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4721 op &= UINT64_C(15);
4722 op <<= 16;
4723 Value |= op;
4724 // op: ws
4725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4726 op &= UINT64_C(31);
4727 op <<= 11;
4728 Value |= op;
4729 // op: wd
4730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4731 op &= UINT64_C(31);
4732 op <<= 6;
4733 Value |= op;
4734 break;
4735 }
4736 case Mips::INSERT_W: {
4737 // op: n
4738 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4739 op &= UINT64_C(3);
4740 op <<= 16;
4741 Value |= op;
4742 // op: rs
4743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4744 op &= UINT64_C(31);
4745 op <<= 11;
4746 Value |= op;
4747 // op: wd
4748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4749 op &= UINT64_C(31);
4750 op <<= 6;
4751 Value |= op;
4752 break;
4753 }
4754 case Mips::SLDI_W: {
4755 // op: n
4756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4757 op &= UINT64_C(3);
4758 op <<= 16;
4759 Value |= op;
4760 // op: ws
4761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4762 op &= UINT64_C(31);
4763 op <<= 11;
4764 Value |= op;
4765 // op: wd
4766 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4767 op &= UINT64_C(31);
4768 op <<= 6;
4769 Value |= op;
4770 break;
4771 }
4772 case Mips::INSERT_H: {
4773 // op: n
4774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4775 op &= UINT64_C(7);
4776 op <<= 16;
4777 Value |= op;
4778 // op: rs
4779 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4780 op &= UINT64_C(31);
4781 op <<= 11;
4782 Value |= op;
4783 // op: wd
4784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4785 op &= UINT64_C(31);
4786 op <<= 6;
4787 Value |= op;
4788 break;
4789 }
4790 case Mips::SLDI_H: {
4791 // op: n
4792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4793 op &= UINT64_C(7);
4794 op <<= 16;
4795 Value |= op;
4796 // op: ws
4797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4798 op &= UINT64_C(31);
4799 op <<= 11;
4800 Value |= op;
4801 // op: wd
4802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4803 op &= UINT64_C(31);
4804 op <<= 6;
4805 Value |= op;
4806 break;
4807 }
4808 case Mips::BALC:
4809 case Mips::BC: {
4810 // op: offset
4811 op = getBranchTarget26OpValue(MI, OpNo: 0, Fixups, STI);
4812 op &= UINT64_C(67108863);
4813 Value |= op;
4814 break;
4815 }
4816 case Mips::BALC_MMR6:
4817 case Mips::BC_MMR6: {
4818 // op: offset
4819 op = getBranchTarget26OpValueMM(MI, OpNo: 0, Fixups, STI);
4820 op &= UINT64_C(67108863);
4821 Value |= op;
4822 break;
4823 }
4824 case Mips::BAL:
4825 case Mips::BPOSGE32: {
4826 // op: offset
4827 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
4828 op &= UINT64_C(65535);
4829 Value |= op;
4830 break;
4831 }
4832 case Mips::BNZ_B:
4833 case Mips::BNZ_D:
4834 case Mips::BNZ_H:
4835 case Mips::BNZ_V:
4836 case Mips::BNZ_W:
4837 case Mips::BZ_B:
4838 case Mips::BZ_D:
4839 case Mips::BZ_H:
4840 case Mips::BZ_V:
4841 case Mips::BZ_W: {
4842 // op: offset
4843 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
4844 op &= UINT64_C(65535);
4845 Value |= op;
4846 // op: wt
4847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4848 op &= UINT64_C(31);
4849 op <<= 16;
4850 Value |= op;
4851 break;
4852 }
4853 case Mips::BPOSGE32C_MMR3: {
4854 // op: offset
4855 op = getBranchTargetOpValue1SImm16(MI, OpNo: 0, Fixups, STI);
4856 op &= UINT64_C(65535);
4857 Value |= op;
4858 break;
4859 }
4860 case Mips::BPOSGE32_MM: {
4861 // op: offset
4862 op = getBranchTargetOpValueMM(MI, OpNo: 0, Fixups, STI);
4863 op &= UINT64_C(65535);
4864 Value |= op;
4865 break;
4866 }
4867 case Mips::B16_MM:
4868 case Mips::BC16_MMR6: {
4869 // op: offset
4870 op = getBranchTargetOpValueMMPC10(MI, OpNo: 0, Fixups, STI);
4871 op &= UINT64_C(1023);
4872 Value |= op;
4873 break;
4874 }
4875 case Mips::Move32R16: {
4876 // op: r32
4877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4878 Value |= (op & UINT64_C(7)) << 5;
4879 Value |= (op & UINT64_C(24));
4880 // op: rz
4881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4882 op &= UINT64_C(7);
4883 Value |= op;
4884 break;
4885 }
4886 case Mips::CLO:
4887 case Mips::CLZ:
4888 case Mips::DCLO:
4889 case Mips::DCLZ: {
4890 // op: rd
4891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4892 Value |= (op & UINT64_C(31)) << 16;
4893 Value |= (op & UINT64_C(31)) << 11;
4894 // op: rs
4895 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4896 op &= UINT64_C(31);
4897 op <<= 21;
4898 Value |= op;
4899 break;
4900 }
4901 case Mips::MFHI16_MM:
4902 case Mips::MFLO16_MM: {
4903 // op: rd
4904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4905 op &= UINT64_C(31);
4906 Value |= op;
4907 break;
4908 }
4909 case Mips::MFHI:
4910 case Mips::MFHI64:
4911 case Mips::MFLO:
4912 case Mips::MFLO64: {
4913 // op: rd
4914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4915 op &= UINT64_C(31);
4916 op <<= 11;
4917 Value |= op;
4918 break;
4919 }
4920 case Mips::MFHI_DSP:
4921 case Mips::MFLO_DSP: {
4922 // op: rd
4923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4924 op &= UINT64_C(31);
4925 op <<= 11;
4926 Value |= op;
4927 // op: ac
4928 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4929 op &= UINT64_C(3);
4930 op <<= 21;
4931 Value |= op;
4932 break;
4933 }
4934 case Mips::LWXS_MM: {
4935 // op: rd
4936 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4937 op &= UINT64_C(31);
4938 op <<= 11;
4939 Value |= op;
4940 // op: base
4941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4942 op &= UINT64_C(31);
4943 op <<= 16;
4944 Value |= op;
4945 // op: index
4946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4947 op &= UINT64_C(31);
4948 op <<= 21;
4949 Value |= op;
4950 break;
4951 }
4952 case Mips::LBUX:
4953 case Mips::LHX:
4954 case Mips::LWX: {
4955 // op: rd
4956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4957 op &= UINT64_C(31);
4958 op <<= 11;
4959 Value |= op;
4960 // op: base
4961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4962 op &= UINT64_C(31);
4963 op <<= 21;
4964 Value |= op;
4965 // op: index
4966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4967 op &= UINT64_C(31);
4968 op <<= 16;
4969 Value |= op;
4970 break;
4971 }
4972 case Mips::REPL_PH:
4973 case Mips::REPL_PH_MM:
4974 case Mips::REPL_QB: {
4975 // op: rd
4976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4977 op &= UINT64_C(31);
4978 op <<= 11;
4979 Value |= op;
4980 // op: imm
4981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4982 op &= UINT64_C(1023);
4983 op <<= 16;
4984 Value |= op;
4985 break;
4986 }
4987 case Mips::RDDSP: {
4988 // op: rd
4989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4990 op &= UINT64_C(31);
4991 op <<= 11;
4992 Value |= op;
4993 // op: mask
4994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4995 op &= UINT64_C(1023);
4996 op <<= 16;
4997 Value |= op;
4998 break;
4999 }
5000 case Mips::ADDQH_PH_MMR2:
5001 case Mips::ADDQH_R_PH_MMR2:
5002 case Mips::ADDQH_R_W_MMR2:
5003 case Mips::ADDQH_W_MMR2:
5004 case Mips::ADDQ_PH_MM:
5005 case Mips::ADDQ_S_PH_MM:
5006 case Mips::ADDQ_S_W_MM:
5007 case Mips::ADDSC_MM:
5008 case Mips::ADDUH_QB_MMR2:
5009 case Mips::ADDUH_R_QB_MMR2:
5010 case Mips::ADDU_PH_MMR2:
5011 case Mips::ADDU_QB_MM:
5012 case Mips::ADDU_S_PH_MMR2:
5013 case Mips::ADDU_S_QB_MM:
5014 case Mips::ADDWC_MM:
5015 case Mips::CMPGDU_EQ_QB_MMR2:
5016 case Mips::CMPGDU_LE_QB_MMR2:
5017 case Mips::CMPGDU_LT_QB_MMR2:
5018 case Mips::MODSUB_MM:
5019 case Mips::MULEQ_S_W_PHL_MM:
5020 case Mips::MULEQ_S_W_PHR_MM:
5021 case Mips::MULEU_S_PH_QBL_MM:
5022 case Mips::MULEU_S_PH_QBR_MM:
5023 case Mips::MULQ_RS_PH_MM:
5024 case Mips::MULQ_RS_W_MMR2:
5025 case Mips::MULQ_S_PH_MMR2:
5026 case Mips::MULQ_S_W_MMR2:
5027 case Mips::MUL_PH_MMR2:
5028 case Mips::MUL_S_PH_MMR2:
5029 case Mips::PACKRL_PH_MM:
5030 case Mips::PICK_PH_MM:
5031 case Mips::PICK_QB_MM:
5032 case Mips::PRECRQU_S_QB_PH_MM:
5033 case Mips::PRECRQ_PH_W_MM:
5034 case Mips::PRECRQ_QB_PH_MM:
5035 case Mips::PRECRQ_RS_PH_W_MM:
5036 case Mips::PRECR_QB_PH_MMR2:
5037 case Mips::SELEQZ_MMR6:
5038 case Mips::SELNEZ_MMR6:
5039 case Mips::SUBQH_PH_MMR2:
5040 case Mips::SUBQH_R_PH_MMR2:
5041 case Mips::SUBQH_R_W_MMR2:
5042 case Mips::SUBQH_W_MMR2:
5043 case Mips::SUBQ_PH_MM:
5044 case Mips::SUBQ_S_PH_MM:
5045 case Mips::SUBQ_S_W_MM:
5046 case Mips::SUBUH_QB_MMR2:
5047 case Mips::SUBUH_R_QB_MMR2:
5048 case Mips::SUBU_PH_MMR2:
5049 case Mips::SUBU_QB_MM:
5050 case Mips::SUBU_S_PH_MMR2:
5051 case Mips::SUBU_S_QB_MM: {
5052 // op: rd
5053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5054 op &= UINT64_C(31);
5055 op <<= 11;
5056 Value |= op;
5057 // op: rs
5058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5059 op &= UINT64_C(31);
5060 op <<= 16;
5061 Value |= op;
5062 // op: rt
5063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5064 op &= UINT64_C(31);
5065 op <<= 21;
5066 Value |= op;
5067 break;
5068 }
5069 case Mips::LSA_MMR6: {
5070 // op: rd
5071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5072 op &= UINT64_C(31);
5073 op <<= 11;
5074 Value |= op;
5075 // op: rs
5076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5077 op &= UINT64_C(31);
5078 op <<= 16;
5079 Value |= op;
5080 // op: rt
5081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5082 op &= UINT64_C(31);
5083 op <<= 21;
5084 Value |= op;
5085 // op: imm2
5086 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
5087 op &= UINT64_C(3);
5088 op <<= 9;
5089 Value |= op;
5090 break;
5091 }
5092 case Mips::CLO_R6:
5093 case Mips::CLZ_R6:
5094 case Mips::DCLO_R6:
5095 case Mips::DCLZ_R6:
5096 case Mips::DPOP:
5097 case Mips::JALR:
5098 case Mips::JALR64:
5099 case Mips::JALR_HB:
5100 case Mips::JALR_HB64:
5101 case Mips::POP:
5102 case Mips::RADDU_W_QB: {
5103 // op: rd
5104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5105 op &= UINT64_C(31);
5106 op <<= 11;
5107 Value |= op;
5108 // op: rs
5109 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5110 op &= UINT64_C(31);
5111 op <<= 21;
5112 Value |= op;
5113 break;
5114 }
5115 case Mips::MOVF_I:
5116 case Mips::MOVF_I64:
5117 case Mips::MOVT_I:
5118 case Mips::MOVT_I64: {
5119 // op: rd
5120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5121 op &= UINT64_C(31);
5122 op <<= 11;
5123 Value |= op;
5124 // op: rs
5125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5126 op &= UINT64_C(31);
5127 op <<= 21;
5128 Value |= op;
5129 // op: fcc
5130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5131 op &= UINT64_C(7);
5132 op <<= 18;
5133 Value |= op;
5134 break;
5135 }
5136 case Mips::ADD:
5137 case Mips::ADDQH_PH:
5138 case Mips::ADDQH_R_PH:
5139 case Mips::ADDQH_R_W:
5140 case Mips::ADDQH_W:
5141 case Mips::ADDQ_PH:
5142 case Mips::ADDQ_S_PH:
5143 case Mips::ADDQ_S_W:
5144 case Mips::ADDSC:
5145 case Mips::ADDUH_QB:
5146 case Mips::ADDUH_R_QB:
5147 case Mips::ADDU_PH:
5148 case Mips::ADDU_QB:
5149 case Mips::ADDU_S_PH:
5150 case Mips::ADDU_S_QB:
5151 case Mips::ADDWC:
5152 case Mips::ADDu:
5153 case Mips::AND:
5154 case Mips::AND64:
5155 case Mips::BADDu:
5156 case Mips::DADD:
5157 case Mips::DADDu:
5158 case Mips::DDIV:
5159 case Mips::DDIVU:
5160 case Mips::DIV:
5161 case Mips::DIVU:
5162 case Mips::DMOD:
5163 case Mips::DMODU:
5164 case Mips::DMUH:
5165 case Mips::DMUHU:
5166 case Mips::DMUL:
5167 case Mips::DMULU:
5168 case Mips::DMUL_R6:
5169 case Mips::DSUB:
5170 case Mips::DSUBu:
5171 case Mips::MOD:
5172 case Mips::MODSUB:
5173 case Mips::MODU:
5174 case Mips::MOVN_I64_I:
5175 case Mips::MOVN_I64_I64:
5176 case Mips::MOVN_I_I:
5177 case Mips::MOVN_I_I64:
5178 case Mips::MOVZ_I64_I:
5179 case Mips::MOVZ_I64_I64:
5180 case Mips::MOVZ_I_I:
5181 case Mips::MOVZ_I_I64:
5182 case Mips::MUH:
5183 case Mips::MUHU:
5184 case Mips::MUL:
5185 case Mips::MULEQ_S_W_PHL:
5186 case Mips::MULEQ_S_W_PHR:
5187 case Mips::MULEU_S_PH_QBL:
5188 case Mips::MULEU_S_PH_QBR:
5189 case Mips::MULQ_RS_PH:
5190 case Mips::MULQ_RS_W:
5191 case Mips::MULQ_S_PH:
5192 case Mips::MULQ_S_W:
5193 case Mips::MULU:
5194 case Mips::MUL_PH:
5195 case Mips::MUL_R6:
5196 case Mips::MUL_S_PH:
5197 case Mips::NOR:
5198 case Mips::NOR64:
5199 case Mips::OR:
5200 case Mips::OR64:
5201 case Mips::SELEQZ:
5202 case Mips::SELEQZ64:
5203 case Mips::SELNEZ:
5204 case Mips::SELNEZ64:
5205 case Mips::SEQ:
5206 case Mips::SLT:
5207 case Mips::SLT64:
5208 case Mips::SLTu:
5209 case Mips::SLTu64:
5210 case Mips::SNE:
5211 case Mips::SUB:
5212 case Mips::SUBQH_PH:
5213 case Mips::SUBQH_R_PH:
5214 case Mips::SUBQH_R_W:
5215 case Mips::SUBQH_W:
5216 case Mips::SUBQ_PH:
5217 case Mips::SUBQ_S_PH:
5218 case Mips::SUBQ_S_W:
5219 case Mips::SUBUH_QB:
5220 case Mips::SUBUH_R_QB:
5221 case Mips::SUBU_PH:
5222 case Mips::SUBU_QB:
5223 case Mips::SUBU_S_PH:
5224 case Mips::SUBU_S_QB:
5225 case Mips::SUBu:
5226 case Mips::V3MULU:
5227 case Mips::VMM0:
5228 case Mips::VMULU:
5229 case Mips::XOR:
5230 case Mips::XOR64: {
5231 // op: rd
5232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5233 op &= UINT64_C(31);
5234 op <<= 11;
5235 Value |= op;
5236 // op: rs
5237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5238 op &= UINT64_C(31);
5239 op <<= 21;
5240 Value |= op;
5241 // op: rt
5242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5243 op &= UINT64_C(31);
5244 op <<= 16;
5245 Value |= op;
5246 break;
5247 }
5248 case Mips::ALIGN: {
5249 // op: rd
5250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5251 op &= UINT64_C(31);
5252 op <<= 11;
5253 Value |= op;
5254 // op: rs
5255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5256 op &= UINT64_C(31);
5257 op <<= 21;
5258 Value |= op;
5259 // op: rt
5260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5261 op &= UINT64_C(31);
5262 op <<= 16;
5263 Value |= op;
5264 // op: bp
5265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5266 op &= UINT64_C(3);
5267 op <<= 6;
5268 Value |= op;
5269 break;
5270 }
5271 case Mips::ALIGN_MMR6: {
5272 // op: rd
5273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5274 op &= UINT64_C(31);
5275 op <<= 11;
5276 Value |= op;
5277 // op: rs
5278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5279 op &= UINT64_C(31);
5280 op <<= 21;
5281 Value |= op;
5282 // op: rt
5283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5284 op &= UINT64_C(31);
5285 op <<= 16;
5286 Value |= op;
5287 // op: bp
5288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5289 op &= UINT64_C(3);
5290 op <<= 9;
5291 Value |= op;
5292 break;
5293 }
5294 case Mips::DALIGN: {
5295 // op: rd
5296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5297 op &= UINT64_C(31);
5298 op <<= 11;
5299 Value |= op;
5300 // op: rs
5301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5302 op &= UINT64_C(31);
5303 op <<= 21;
5304 Value |= op;
5305 // op: rt
5306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5307 op &= UINT64_C(31);
5308 op <<= 16;
5309 Value |= op;
5310 // op: bp
5311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5312 op &= UINT64_C(7);
5313 op <<= 6;
5314 Value |= op;
5315 break;
5316 }
5317 case Mips::DLSA_R6:
5318 case Mips::LSA_R6: {
5319 // op: rd
5320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5321 op &= UINT64_C(31);
5322 op <<= 11;
5323 Value |= op;
5324 // op: rs
5325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5326 op &= UINT64_C(31);
5327 op <<= 21;
5328 Value |= op;
5329 // op: rt
5330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5331 op &= UINT64_C(31);
5332 op <<= 16;
5333 Value |= op;
5334 // op: imm2
5335 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
5336 op &= UINT64_C(3);
5337 op <<= 6;
5338 Value |= op;
5339 break;
5340 }
5341 case Mips::SHLLV_PH_MM:
5342 case Mips::SHLLV_QB_MM:
5343 case Mips::SHLLV_S_PH_MM:
5344 case Mips::SHLLV_S_W_MM:
5345 case Mips::SHRAV_PH_MM:
5346 case Mips::SHRAV_QB_MMR2:
5347 case Mips::SHRAV_R_PH_MM:
5348 case Mips::SHRAV_R_QB_MMR2:
5349 case Mips::SHRAV_R_W_MM:
5350 case Mips::SHRLV_PH_MMR2:
5351 case Mips::SHRLV_QB_MM: {
5352 // op: rd
5353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5354 op &= UINT64_C(31);
5355 op <<= 11;
5356 Value |= op;
5357 // op: rs
5358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5359 op &= UINT64_C(31);
5360 op <<= 16;
5361 Value |= op;
5362 // op: rt
5363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5364 op &= UINT64_C(31);
5365 op <<= 21;
5366 Value |= op;
5367 break;
5368 }
5369 case Mips::ABSQ_S_PH:
5370 case Mips::ABSQ_S_QB:
5371 case Mips::ABSQ_S_W:
5372 case Mips::BITREV:
5373 case Mips::BITSWAP:
5374 case Mips::DBITSWAP:
5375 case Mips::DSBH:
5376 case Mips::DSHD:
5377 case Mips::DSLL64_32:
5378 case Mips::PRECEQU_PH_QBL:
5379 case Mips::PRECEQU_PH_QBLA:
5380 case Mips::PRECEQU_PH_QBR:
5381 case Mips::PRECEQU_PH_QBRA:
5382 case Mips::PRECEQ_W_PHL:
5383 case Mips::PRECEQ_W_PHR:
5384 case Mips::PRECEU_PH_QBL:
5385 case Mips::PRECEU_PH_QBLA:
5386 case Mips::PRECEU_PH_QBR:
5387 case Mips::PRECEU_PH_QBRA:
5388 case Mips::REPLV_PH:
5389 case Mips::REPLV_QB:
5390 case Mips::SEB:
5391 case Mips::SEB64:
5392 case Mips::SEH:
5393 case Mips::SEH64:
5394 case Mips::SLL64_32:
5395 case Mips::SLL64_64:
5396 case Mips::WSBH: {
5397 // op: rd
5398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5399 op &= UINT64_C(31);
5400 op <<= 11;
5401 Value |= op;
5402 // op: rt
5403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5404 op &= UINT64_C(31);
5405 op <<= 16;
5406 Value |= op;
5407 break;
5408 }
5409 case Mips::DROTRV:
5410 case Mips::DSLLV:
5411 case Mips::DSRAV:
5412 case Mips::DSRLV:
5413 case Mips::ROTRV:
5414 case Mips::SLLV:
5415 case Mips::SRAV:
5416 case Mips::SRLV: {
5417 // op: rd
5418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5419 op &= UINT64_C(31);
5420 op <<= 11;
5421 Value |= op;
5422 // op: rt
5423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5424 op &= UINT64_C(31);
5425 op <<= 16;
5426 Value |= op;
5427 // op: rs
5428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5429 op &= UINT64_C(31);
5430 op <<= 21;
5431 Value |= op;
5432 break;
5433 }
5434 case Mips::SHLLV_PH:
5435 case Mips::SHLLV_QB:
5436 case Mips::SHLLV_S_PH:
5437 case Mips::SHLLV_S_W:
5438 case Mips::SHLL_PH:
5439 case Mips::SHLL_QB:
5440 case Mips::SHLL_S_PH:
5441 case Mips::SHLL_S_W:
5442 case Mips::SHRAV_PH:
5443 case Mips::SHRAV_QB:
5444 case Mips::SHRAV_R_PH:
5445 case Mips::SHRAV_R_QB:
5446 case Mips::SHRAV_R_W:
5447 case Mips::SHRA_PH:
5448 case Mips::SHRA_QB:
5449 case Mips::SHRA_R_PH:
5450 case Mips::SHRA_R_QB:
5451 case Mips::SHRA_R_W:
5452 case Mips::SHRLV_PH:
5453 case Mips::SHRLV_QB:
5454 case Mips::SHRL_PH:
5455 case Mips::SHRL_QB: {
5456 // op: rd
5457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5458 op &= UINT64_C(31);
5459 op <<= 11;
5460 Value |= op;
5461 // op: rt
5462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5463 op &= UINT64_C(31);
5464 op <<= 16;
5465 Value |= op;
5466 // op: rs_sa
5467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5468 op &= UINT64_C(31);
5469 op <<= 21;
5470 Value |= op;
5471 break;
5472 }
5473 case Mips::DROTR:
5474 case Mips::DROTR32:
5475 case Mips::DSLL:
5476 case Mips::DSLL32:
5477 case Mips::DSRA:
5478 case Mips::DSRA32:
5479 case Mips::DSRL:
5480 case Mips::DSRL32:
5481 case Mips::ROTR:
5482 case Mips::SLL:
5483 case Mips::SRA:
5484 case Mips::SRL: {
5485 // op: rd
5486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5487 op &= UINT64_C(31);
5488 op <<= 11;
5489 Value |= op;
5490 // op: rt
5491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5492 op &= UINT64_C(31);
5493 op <<= 16;
5494 Value |= op;
5495 // op: shamt
5496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5497 op &= UINT64_C(31);
5498 op <<= 6;
5499 Value |= op;
5500 break;
5501 }
5502 case Mips::ROTRV_MM:
5503 case Mips::SLLV_MM:
5504 case Mips::SRAV_MM:
5505 case Mips::SRLV_MM: {
5506 // op: rd
5507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5508 op &= UINT64_C(31);
5509 op <<= 11;
5510 Value |= op;
5511 // op: rt
5512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5513 op &= UINT64_C(31);
5514 op <<= 21;
5515 Value |= op;
5516 // op: rs
5517 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5518 op &= UINT64_C(31);
5519 op <<= 16;
5520 Value |= op;
5521 break;
5522 }
5523 case Mips::ADDU_MMR6:
5524 case Mips::ADD_MMR6:
5525 case Mips::AND_MMR6:
5526 case Mips::DIVU_MMR6:
5527 case Mips::DIV_MMR6:
5528 case Mips::MODU_MMR6:
5529 case Mips::MOD_MMR6:
5530 case Mips::MUHU_MMR6:
5531 case Mips::MUH_MMR6:
5532 case Mips::MULU_MMR6:
5533 case Mips::MUL_MMR6:
5534 case Mips::NOR_MMR6:
5535 case Mips::OR_MMR6:
5536 case Mips::SUBU_MMR6:
5537 case Mips::SUB_MMR6:
5538 case Mips::XOR_MMR6: {
5539 // op: rd
5540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5541 op &= UINT64_C(31);
5542 op <<= 11;
5543 Value |= op;
5544 // op: rt
5545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5546 op &= UINT64_C(31);
5547 op <<= 21;
5548 Value |= op;
5549 // op: rs
5550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5551 op &= UINT64_C(31);
5552 op <<= 16;
5553 Value |= op;
5554 break;
5555 }
5556 case Mips::MFHI_MM:
5557 case Mips::MFLO_MM: {
5558 // op: rd
5559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5560 op &= UINT64_C(31);
5561 op <<= 16;
5562 Value |= op;
5563 break;
5564 }
5565 case Mips::BITSWAP_MMR6: {
5566 // op: rd
5567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5568 op &= UINT64_C(31);
5569 op <<= 16;
5570 Value |= op;
5571 // op: rt
5572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5573 op &= UINT64_C(31);
5574 op <<= 21;
5575 Value |= op;
5576 break;
5577 }
5578 case Mips::CLO_MM:
5579 case Mips::CLZ_MM: {
5580 // op: rd
5581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5582 op &= UINT64_C(31);
5583 op <<= 21;
5584 Value |= op;
5585 // op: rs
5586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5587 op &= UINT64_C(31);
5588 op <<= 16;
5589 Value |= op;
5590 break;
5591 }
5592 case Mips::MOVF_I_MM:
5593 case Mips::MOVT_I_MM: {
5594 // op: rd
5595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5596 op &= UINT64_C(31);
5597 op <<= 21;
5598 Value |= op;
5599 // op: rs
5600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5601 op &= UINT64_C(31);
5602 op <<= 16;
5603 Value |= op;
5604 // op: fcc
5605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5606 op &= UINT64_C(7);
5607 op <<= 13;
5608 Value |= op;
5609 break;
5610 }
5611 case Mips::SEB_MM:
5612 case Mips::SEH_MM:
5613 case Mips::WSBH_MM: {
5614 // op: rd
5615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5616 op &= UINT64_C(31);
5617 op <<= 21;
5618 Value |= op;
5619 // op: rt
5620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5621 op &= UINT64_C(31);
5622 op <<= 16;
5623 Value |= op;
5624 break;
5625 }
5626 case Mips::ROTR_MM:
5627 case Mips::SLL_MM:
5628 case Mips::SLL_MMR6:
5629 case Mips::SRA_MM:
5630 case Mips::SRL_MM: {
5631 // op: rd
5632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5633 op &= UINT64_C(31);
5634 op <<= 21;
5635 Value |= op;
5636 // op: rt
5637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5638 op &= UINT64_C(31);
5639 op <<= 16;
5640 Value |= op;
5641 // op: shamt
5642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5643 op &= UINT64_C(31);
5644 op <<= 11;
5645 Value |= op;
5646 break;
5647 }
5648 case Mips::CFCMSA: {
5649 // op: rd
5650 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5651 op &= UINT64_C(31);
5652 op <<= 6;
5653 Value |= op;
5654 // op: cs
5655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5656 op &= UINT64_C(31);
5657 op <<= 11;
5658 Value |= op;
5659 break;
5660 }
5661 case Mips::LI16_MM:
5662 case Mips::LI16_MMR6: {
5663 // op: rd
5664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5665 op &= UINT64_C(7);
5666 op <<= 7;
5667 Value |= op;
5668 // op: imm
5669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5670 op &= UINT64_C(127);
5671 Value |= op;
5672 break;
5673 }
5674 case Mips::ADDIUR1SP_MM: {
5675 // op: rd
5676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5677 op &= UINT64_C(7);
5678 op <<= 7;
5679 Value |= op;
5680 // op: imm
5681 op = getUImm6Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
5682 op &= UINT64_C(63);
5683 op <<= 1;
5684 Value |= op;
5685 break;
5686 }
5687 case Mips::ADDIUR2_MM: {
5688 // op: rd
5689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5690 op &= UINT64_C(7);
5691 op <<= 7;
5692 Value |= op;
5693 // op: rs
5694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5695 op &= UINT64_C(7);
5696 op <<= 4;
5697 Value |= op;
5698 // op: imm
5699 op = getSImm3Lsa2Value(MI, OpNo: 2, Fixups, STI);
5700 op &= UINT64_C(7);
5701 op <<= 1;
5702 Value |= op;
5703 break;
5704 }
5705 case Mips::ANDI16_MM:
5706 case Mips::ANDI16_MMR6: {
5707 // op: rd
5708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5709 op &= UINT64_C(7);
5710 op <<= 7;
5711 Value |= op;
5712 // op: rs
5713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5714 op &= UINT64_C(7);
5715 op <<= 4;
5716 Value |= op;
5717 // op: imm
5718 op = getUImm4AndValue(MI, OpNo: 2, Fixups, STI);
5719 op &= UINT64_C(15);
5720 Value |= op;
5721 break;
5722 }
5723 case Mips::SLL16_MM:
5724 case Mips::SLL16_MMR6:
5725 case Mips::SRL16_MM:
5726 case Mips::SRL16_MMR6: {
5727 // op: rd
5728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5729 op &= UINT64_C(7);
5730 op <<= 7;
5731 Value |= op;
5732 // op: rt
5733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5734 op &= UINT64_C(7);
5735 op <<= 4;
5736 Value |= op;
5737 // op: shamt
5738 op = getUImm3Mod8Encoding(MI, OpNo: 2, Fixups, STI);
5739 op &= UINT64_C(7);
5740 op <<= 1;
5741 Value |= op;
5742 break;
5743 }
5744 case Mips::ADDU16_MM:
5745 case Mips::SUBU16_MM: {
5746 // op: rd
5747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5748 op &= UINT64_C(7);
5749 op <<= 7;
5750 Value |= op;
5751 // op: rt
5752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5753 op &= UINT64_C(7);
5754 op <<= 4;
5755 Value |= op;
5756 // op: rs
5757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5758 op &= UINT64_C(7);
5759 op <<= 1;
5760 Value |= op;
5761 break;
5762 }
5763 case Mips::ADDIUS5_MM: {
5764 // op: rd
5765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5766 op &= UINT64_C(31);
5767 op <<= 5;
5768 Value |= op;
5769 // op: imm
5770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5771 op &= UINT64_C(15);
5772 op <<= 1;
5773 Value |= op;
5774 break;
5775 }
5776 case Mips::JALR16_MM:
5777 case Mips::JALRS16_MM:
5778 case Mips::JR16_MM:
5779 case Mips::JRC16_MM: {
5780 // op: rs
5781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5782 op &= UINT64_C(31);
5783 Value |= op;
5784 break;
5785 }
5786 case Mips::DVP_MMR6:
5787 case Mips::EVP_MMR6:
5788 case Mips::GINVI_MMR6:
5789 case Mips::JR_MM:
5790 case Mips::MTHI_MM:
5791 case Mips::MTLO_MM: {
5792 // op: rs
5793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5794 op &= UINT64_C(31);
5795 op <<= 16;
5796 Value |= op;
5797 break;
5798 }
5799 case Mips::MFHI_DSP_MM:
5800 case Mips::MFLO_DSP_MM: {
5801 // op: rs
5802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5803 op &= UINT64_C(31);
5804 op <<= 16;
5805 Value |= op;
5806 // op: ac
5807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5808 op &= UINT64_C(3);
5809 op <<= 14;
5810 Value |= op;
5811 break;
5812 }
5813 case Mips::TEQI_MM:
5814 case Mips::TGEIU_MM:
5815 case Mips::TGEI_MM:
5816 case Mips::TLTIU_MM:
5817 case Mips::TLTI_MM:
5818 case Mips::TNEI_MM: {
5819 // op: rs
5820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5821 op &= UINT64_C(31);
5822 op <<= 16;
5823 Value |= op;
5824 // op: imm16
5825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5826 op &= UINT64_C(65535);
5827 Value |= op;
5828 break;
5829 }
5830 case Mips::BEQZC_MM:
5831 case Mips::BGEZALS_MM:
5832 case Mips::BGEZAL_MM:
5833 case Mips::BGEZ_MM:
5834 case Mips::BGTZ_MM:
5835 case Mips::BLEZ_MM:
5836 case Mips::BLTZALS_MM:
5837 case Mips::BLTZAL_MM:
5838 case Mips::BLTZ_MM:
5839 case Mips::BNEZC_MM: {
5840 // op: rs
5841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5842 op &= UINT64_C(31);
5843 op <<= 16;
5844 Value |= op;
5845 // op: offset
5846 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
5847 op &= UINT64_C(65535);
5848 Value |= op;
5849 break;
5850 }
5851 case Mips::MADDU_MM:
5852 case Mips::MADD_MM:
5853 case Mips::MSUBU_MM:
5854 case Mips::MSUB_MM:
5855 case Mips::MULT_MM:
5856 case Mips::MULTu_MM:
5857 case Mips::SDIV_MM:
5858 case Mips::UDIV_MM: {
5859 // op: rs
5860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5861 op &= UINT64_C(31);
5862 op <<= 16;
5863 Value |= op;
5864 // op: rt
5865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5866 op &= UINT64_C(31);
5867 op <<= 21;
5868 Value |= op;
5869 break;
5870 }
5871 case Mips::TEQ_MM:
5872 case Mips::TGEU_MM:
5873 case Mips::TGE_MM:
5874 case Mips::TLTU_MM:
5875 case Mips::TLT_MM:
5876 case Mips::TNE_MM: {
5877 // op: rs
5878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5879 op &= UINT64_C(31);
5880 op <<= 16;
5881 Value |= op;
5882 // op: rt
5883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5884 op &= UINT64_C(31);
5885 op <<= 21;
5886 Value |= op;
5887 // op: code_
5888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5889 op &= UINT64_C(15);
5890 op <<= 12;
5891 Value |= op;
5892 break;
5893 }
5894 case Mips::BEQ_MM:
5895 case Mips::BNE_MM: {
5896 // op: rs
5897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5898 op &= UINT64_C(31);
5899 op <<= 16;
5900 Value |= op;
5901 // op: rt
5902 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5903 op &= UINT64_C(31);
5904 op <<= 21;
5905 Value |= op;
5906 // op: offset
5907 op = getBranchTargetOpValueMM(MI, OpNo: 2, Fixups, STI);
5908 op &= UINT64_C(65535);
5909 Value |= op;
5910 break;
5911 }
5912 case Mips::GINVT_MMR6: {
5913 // op: rs
5914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5915 op &= UINT64_C(31);
5916 op <<= 16;
5917 Value |= op;
5918 // op: type
5919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5920 op &= UINT64_C(3);
5921 op <<= 9;
5922 Value |= op;
5923 break;
5924 }
5925 case Mips::GINVI:
5926 case Mips::JR:
5927 case Mips::JR64:
5928 case Mips::JR_HB:
5929 case Mips::JR_HB64:
5930 case Mips::JR_HB64_R6:
5931 case Mips::JR_HB_R6:
5932 case Mips::MTHI:
5933 case Mips::MTHI64:
5934 case Mips::MTLO:
5935 case Mips::MTLO64:
5936 case Mips::MTM0:
5937 case Mips::MTM1:
5938 case Mips::MTM2:
5939 case Mips::MTP0:
5940 case Mips::MTP1:
5941 case Mips::MTP2: {
5942 // op: rs
5943 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5944 op &= UINT64_C(31);
5945 op <<= 21;
5946 Value |= op;
5947 break;
5948 }
5949 case Mips::ALUIPC:
5950 case Mips::AUIPC: {
5951 // op: rs
5952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5953 op &= UINT64_C(31);
5954 op <<= 21;
5955 Value |= op;
5956 // op: imm
5957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5958 op &= UINT64_C(65535);
5959 Value |= op;
5960 break;
5961 }
5962 case Mips::DAHI:
5963 case Mips::DATI: {
5964 // op: rs
5965 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5966 op &= UINT64_C(31);
5967 op <<= 21;
5968 Value |= op;
5969 // op: imm
5970 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5971 op &= UINT64_C(65535);
5972 Value |= op;
5973 break;
5974 }
5975 case Mips::LDPC: {
5976 // op: rs
5977 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5978 op &= UINT64_C(31);
5979 op <<= 21;
5980 Value |= op;
5981 // op: imm
5982 op = getSimm18Lsl3Encoding(MI, OpNo: 1, Fixups, STI);
5983 op &= UINT64_C(262143);
5984 Value |= op;
5985 break;
5986 }
5987 case Mips::ADDIUPC:
5988 case Mips::LWPC:
5989 case Mips::LWUPC: {
5990 // op: rs
5991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5992 op &= UINT64_C(31);
5993 op <<= 21;
5994 Value |= op;
5995 // op: imm
5996 op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
5997 op &= UINT64_C(524287);
5998 Value |= op;
5999 break;
6000 }
6001 case Mips::TEQI:
6002 case Mips::TGEI:
6003 case Mips::TGEIU:
6004 case Mips::TLTI:
6005 case Mips::TNEI:
6006 case Mips::TTLTIU: {
6007 // op: rs
6008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6009 op &= UINT64_C(31);
6010 op <<= 21;
6011 Value |= op;
6012 // op: imm16
6013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6014 op &= UINT64_C(65535);
6015 Value |= op;
6016 break;
6017 }
6018 case Mips::WRDSP: {
6019 // op: rs
6020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6021 op &= UINT64_C(31);
6022 op <<= 21;
6023 Value |= op;
6024 // op: mask
6025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6026 op &= UINT64_C(1023);
6027 op <<= 11;
6028 Value |= op;
6029 break;
6030 }
6031 case Mips::BEQZC:
6032 case Mips::BEQZC64:
6033 case Mips::BNEZC:
6034 case Mips::BNEZC64: {
6035 // op: rs
6036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6037 op &= UINT64_C(31);
6038 op <<= 21;
6039 Value |= op;
6040 // op: offset
6041 op = getBranchTarget21OpValue(MI, OpNo: 1, Fixups, STI);
6042 op &= UINT64_C(2097151);
6043 Value |= op;
6044 break;
6045 }
6046 case Mips::BEQZC_MMR6:
6047 case Mips::BNEZC_MMR6: {
6048 // op: rs
6049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6050 op &= UINT64_C(31);
6051 op <<= 21;
6052 Value |= op;
6053 // op: offset
6054 op = getBranchTarget21OpValueMM(MI, OpNo: 1, Fixups, STI);
6055 op &= UINT64_C(2097151);
6056 Value |= op;
6057 break;
6058 }
6059 case Mips::BGEZ:
6060 case Mips::BGEZ64:
6061 case Mips::BGEZAL:
6062 case Mips::BGEZALL:
6063 case Mips::BGEZL:
6064 case Mips::BGTZ:
6065 case Mips::BGTZ64:
6066 case Mips::BGTZL:
6067 case Mips::BLEZ:
6068 case Mips::BLEZ64:
6069 case Mips::BLEZL:
6070 case Mips::BLTZ:
6071 case Mips::BLTZ64:
6072 case Mips::BLTZAL:
6073 case Mips::BLTZALL:
6074 case Mips::BLTZL: {
6075 // op: rs
6076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6077 op &= UINT64_C(31);
6078 op <<= 21;
6079 Value |= op;
6080 // op: offset
6081 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6082 op &= UINT64_C(65535);
6083 Value |= op;
6084 break;
6085 }
6086 case Mips::BBIT0:
6087 case Mips::BBIT1:
6088 case Mips::BBIT032:
6089 case Mips::BBIT132: {
6090 // op: rs
6091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6092 op &= UINT64_C(31);
6093 op <<= 21;
6094 Value |= op;
6095 // op: p
6096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6097 op &= UINT64_C(31);
6098 op <<= 16;
6099 Value |= op;
6100 // op: offset
6101 op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI);
6102 op &= UINT64_C(65535);
6103 Value |= op;
6104 break;
6105 }
6106 case Mips::CMPU_EQ_QB:
6107 case Mips::CMPU_LE_QB:
6108 case Mips::CMPU_LT_QB:
6109 case Mips::CMP_EQ_PH:
6110 case Mips::CMP_LE_PH:
6111 case Mips::CMP_LT_PH:
6112 case Mips::DMULT:
6113 case Mips::DMULTu:
6114 case Mips::DSDIV:
6115 case Mips::DUDIV:
6116 case Mips::MADD:
6117 case Mips::MADDU:
6118 case Mips::MSUB:
6119 case Mips::MSUBU:
6120 case Mips::MULT:
6121 case Mips::MULTu:
6122 case Mips::SDIV:
6123 case Mips::UDIV: {
6124 // op: rs
6125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6126 op &= UINT64_C(31);
6127 op <<= 21;
6128 Value |= op;
6129 // op: rt
6130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6131 op &= UINT64_C(31);
6132 op <<= 16;
6133 Value |= op;
6134 break;
6135 }
6136 case Mips::TEQ:
6137 case Mips::TGE:
6138 case Mips::TGEU:
6139 case Mips::TLT:
6140 case Mips::TLTU:
6141 case Mips::TNE: {
6142 // op: rs
6143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6144 op &= UINT64_C(31);
6145 op <<= 21;
6146 Value |= op;
6147 // op: rt
6148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6149 op &= UINT64_C(31);
6150 op <<= 16;
6151 Value |= op;
6152 // op: code_
6153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6154 op &= UINT64_C(1023);
6155 op <<= 6;
6156 Value |= op;
6157 break;
6158 }
6159 case Mips::BEQ:
6160 case Mips::BEQ64:
6161 case Mips::BEQC:
6162 case Mips::BEQC64:
6163 case Mips::BEQL:
6164 case Mips::BGEC:
6165 case Mips::BGEC64:
6166 case Mips::BGEUC:
6167 case Mips::BGEUC64:
6168 case Mips::BLTC:
6169 case Mips::BLTC64:
6170 case Mips::BLTUC:
6171 case Mips::BLTUC64:
6172 case Mips::BNE:
6173 case Mips::BNE64:
6174 case Mips::BNEC:
6175 case Mips::BNEC64:
6176 case Mips::BNEL:
6177 case Mips::BNVC:
6178 case Mips::BOVC: {
6179 // op: rs
6180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6181 op &= UINT64_C(31);
6182 op <<= 21;
6183 Value |= op;
6184 // op: rt
6185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6186 op &= UINT64_C(31);
6187 op <<= 16;
6188 Value |= op;
6189 // op: offset
6190 op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI);
6191 op &= UINT64_C(65535);
6192 Value |= op;
6193 break;
6194 }
6195 case Mips::FORK: {
6196 // op: rs
6197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6198 op &= UINT64_C(31);
6199 op <<= 21;
6200 Value |= op;
6201 // op: rt
6202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6203 op &= UINT64_C(31);
6204 op <<= 16;
6205 Value |= op;
6206 // op: rd
6207 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6208 op &= UINT64_C(31);
6209 op <<= 11;
6210 Value |= op;
6211 break;
6212 }
6213 case Mips::GINVT: {
6214 // op: rs
6215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6216 op &= UINT64_C(31);
6217 op <<= 21;
6218 Value |= op;
6219 // op: type_
6220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6221 op &= UINT64_C(3);
6222 op <<= 8;
6223 Value |= op;
6224 break;
6225 }
6226 case Mips::JALRC16_MMR6:
6227 case Mips::JRC16_MMR6: {
6228 // op: rs
6229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6230 op &= UINT64_C(31);
6231 op <<= 5;
6232 Value |= op;
6233 break;
6234 }
6235 case Mips::ADDIUPC_MM: {
6236 // op: rs
6237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6238 op &= UINT64_C(7);
6239 op <<= 23;
6240 Value |= op;
6241 // op: imm
6242 op = getSimm23Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
6243 op &= UINT64_C(8388607);
6244 Value |= op;
6245 break;
6246 }
6247 case Mips::BEQZ16_MM:
6248 case Mips::BEQZC16_MMR6:
6249 case Mips::BNEZ16_MM:
6250 case Mips::BNEZC16_MMR6: {
6251 // op: rs
6252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6253 op &= UINT64_C(7);
6254 op <<= 7;
6255 Value |= op;
6256 // op: offset
6257 op = getBranchTarget7OpValueMM(MI, OpNo: 1, Fixups, STI);
6258 op &= UINT64_C(127);
6259 Value |= op;
6260 break;
6261 }
6262 case Mips::MOVE16_MM:
6263 case Mips::MOVE16_MMR6: {
6264 // op: rs
6265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6266 op &= UINT64_C(31);
6267 Value |= op;
6268 // op: rd
6269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6270 op &= UINT64_C(31);
6271 op <<= 5;
6272 Value |= op;
6273 break;
6274 }
6275 case Mips::CTCMSA: {
6276 // op: rs
6277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6278 op &= UINT64_C(31);
6279 op <<= 11;
6280 Value |= op;
6281 // op: cd
6282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6283 op &= UINT64_C(31);
6284 op <<= 6;
6285 Value |= op;
6286 break;
6287 }
6288 case Mips::FILL_B:
6289 case Mips::FILL_D:
6290 case Mips::FILL_H:
6291 case Mips::FILL_W: {
6292 // op: rs
6293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6294 op &= UINT64_C(31);
6295 op <<= 11;
6296 Value |= op;
6297 // op: wd
6298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6299 op &= UINT64_C(31);
6300 op <<= 6;
6301 Value |= op;
6302 break;
6303 }
6304 case Mips::MTHI_DSP_MM:
6305 case Mips::MTHLIP_MM:
6306 case Mips::MTLO_DSP_MM:
6307 case Mips::SHILOV_MM: {
6308 // op: rs
6309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6310 op &= UINT64_C(31);
6311 op <<= 16;
6312 Value |= op;
6313 // op: ac
6314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6315 op &= UINT64_C(3);
6316 op <<= 14;
6317 Value |= op;
6318 break;
6319 }
6320 case Mips::JALRS_MM:
6321 case Mips::JALR_MM: {
6322 // op: rs
6323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6324 op &= UINT64_C(31);
6325 op <<= 16;
6326 Value |= op;
6327 // op: rd
6328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6329 op &= UINT64_C(31);
6330 op <<= 21;
6331 Value |= op;
6332 break;
6333 }
6334 case Mips::CLO_MMR6: {
6335 // op: rs
6336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6337 op &= UINT64_C(31);
6338 op <<= 16;
6339 Value |= op;
6340 // op: rt
6341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6342 op &= UINT64_C(31);
6343 op <<= 21;
6344 Value |= op;
6345 break;
6346 }
6347 case Mips::AUI_MMR6: {
6348 // op: rs
6349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6350 op &= UINT64_C(31);
6351 op <<= 16;
6352 Value |= op;
6353 // op: rt
6354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6355 op &= UINT64_C(31);
6356 op <<= 21;
6357 Value |= op;
6358 // op: imm
6359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6360 op &= UINT64_C(65535);
6361 Value |= op;
6362 break;
6363 }
6364 case Mips::ADDi_MM:
6365 case Mips::ADDiu_MM:
6366 case Mips::ANDi_MM:
6367 case Mips::ORi_MM:
6368 case Mips::XORi_MM: {
6369 // op: rs
6370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6371 op &= UINT64_C(31);
6372 op <<= 16;
6373 Value |= op;
6374 // op: rt
6375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6376 op &= UINT64_C(31);
6377 op <<= 21;
6378 Value |= op;
6379 // op: imm16
6380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6381 op &= UINT64_C(65535);
6382 Value |= op;
6383 break;
6384 }
6385 case Mips::MTHI_DSP:
6386 case Mips::MTLO_DSP: {
6387 // op: rs
6388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6389 op &= UINT64_C(31);
6390 op <<= 21;
6391 Value |= op;
6392 // op: ac
6393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6394 op &= UINT64_C(3);
6395 op <<= 11;
6396 Value |= op;
6397 break;
6398 }
6399 case Mips::YIELD: {
6400 // op: rs
6401 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6402 op &= UINT64_C(31);
6403 op <<= 21;
6404 Value |= op;
6405 // op: rd
6406 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6407 op &= UINT64_C(31);
6408 op <<= 11;
6409 Value |= op;
6410 break;
6411 }
6412 case Mips::CLZ_MMR6: {
6413 // op: rs
6414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6415 op &= UINT64_C(31);
6416 op <<= 21;
6417 Value |= op;
6418 // op: rt
6419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6420 op &= UINT64_C(31);
6421 op <<= 11;
6422 Value |= op;
6423 break;
6424 }
6425 case Mips::AUI:
6426 case Mips::DAUI: {
6427 // op: rs
6428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6429 op &= UINT64_C(31);
6430 op <<= 21;
6431 Value |= op;
6432 // op: rt
6433 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6434 op &= UINT64_C(31);
6435 op <<= 16;
6436 Value |= op;
6437 // op: imm
6438 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6439 op &= UINT64_C(65535);
6440 Value |= op;
6441 break;
6442 }
6443 case Mips::SEQi:
6444 case Mips::SNEi: {
6445 // op: rs
6446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6447 op &= UINT64_C(31);
6448 op <<= 21;
6449 Value |= op;
6450 // op: rt
6451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6452 op &= UINT64_C(31);
6453 op <<= 16;
6454 Value |= op;
6455 // op: imm10
6456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6457 op &= UINT64_C(1023);
6458 op <<= 6;
6459 Value |= op;
6460 break;
6461 }
6462 case Mips::ADDi:
6463 case Mips::ADDiu:
6464 case Mips::ANDi:
6465 case Mips::ANDi64:
6466 case Mips::DADDi:
6467 case Mips::DADDiu:
6468 case Mips::ORi:
6469 case Mips::ORi64:
6470 case Mips::XORi:
6471 case Mips::XORi64: {
6472 // op: rs
6473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6474 op &= UINT64_C(31);
6475 op <<= 21;
6476 Value |= op;
6477 // op: rt
6478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6479 op &= UINT64_C(31);
6480 op <<= 16;
6481 Value |= op;
6482 // op: imm16
6483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6484 op &= UINT64_C(65535);
6485 Value |= op;
6486 break;
6487 }
6488 case Mips::PRECR_SRA_PH_W:
6489 case Mips::PRECR_SRA_R_PH_W: {
6490 // op: rs
6491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6492 op &= UINT64_C(31);
6493 op <<= 21;
6494 Value |= op;
6495 // op: rt
6496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6497 op &= UINT64_C(31);
6498 op <<= 16;
6499 Value |= op;
6500 // op: sa
6501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6502 op &= UINT64_C(31);
6503 op <<= 11;
6504 Value |= op;
6505 break;
6506 }
6507 case Mips::CRC32B:
6508 case Mips::CRC32CB:
6509 case Mips::CRC32CD:
6510 case Mips::CRC32CH:
6511 case Mips::CRC32CW:
6512 case Mips::CRC32D:
6513 case Mips::CRC32H:
6514 case Mips::CRC32W: {
6515 // op: rs
6516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6517 op &= UINT64_C(31);
6518 op <<= 21;
6519 Value |= op;
6520 // op: rt
6521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6522 op &= UINT64_C(31);
6523 op <<= 16;
6524 Value |= op;
6525 break;
6526 }
6527 case Mips::CMPGDU_EQ_QB:
6528 case Mips::CMPGDU_LE_QB:
6529 case Mips::CMPGDU_LT_QB:
6530 case Mips::CMPGU_EQ_QB:
6531 case Mips::CMPGU_LE_QB:
6532 case Mips::CMPGU_LT_QB:
6533 case Mips::PACKRL_PH:
6534 case Mips::PICK_PH:
6535 case Mips::PICK_QB:
6536 case Mips::PRECRQU_S_QB_PH:
6537 case Mips::PRECRQ_PH_W:
6538 case Mips::PRECRQ_QB_PH:
6539 case Mips::PRECRQ_RS_PH_W:
6540 case Mips::PRECR_QB_PH: {
6541 // op: rs
6542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6543 op &= UINT64_C(31);
6544 op <<= 21;
6545 Value |= op;
6546 // op: rt
6547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6548 op &= UINT64_C(31);
6549 op <<= 16;
6550 Value |= op;
6551 // op: rd
6552 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6553 op &= UINT64_C(31);
6554 op <<= 11;
6555 Value |= op;
6556 break;
6557 }
6558 case Mips::DLSA:
6559 case Mips::LSA: {
6560 // op: rs
6561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6562 op &= UINT64_C(31);
6563 op <<= 21;
6564 Value |= op;
6565 // op: rt
6566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6567 op &= UINT64_C(31);
6568 op <<= 16;
6569 Value |= op;
6570 // op: rd
6571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6572 op &= UINT64_C(31);
6573 op <<= 11;
6574 Value |= op;
6575 // op: sa
6576 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
6577 op &= UINT64_C(3);
6578 op <<= 6;
6579 Value |= op;
6580 break;
6581 }
6582 case Mips::ADDU16_MMR6:
6583 case Mips::SUBU16_MMR6: {
6584 // op: rs
6585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6586 op &= UINT64_C(7);
6587 op <<= 7;
6588 Value |= op;
6589 // op: rt
6590 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6591 op &= UINT64_C(7);
6592 op <<= 4;
6593 Value |= op;
6594 // op: rd
6595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6596 op &= UINT64_C(7);
6597 op <<= 1;
6598 Value |= op;
6599 break;
6600 }
6601 case Mips::BGEZALC:
6602 case Mips::BGEZC:
6603 case Mips::BGEZC64:
6604 case Mips::BLTZALC:
6605 case Mips::BLTZC:
6606 case Mips::BLTZC64: {
6607 // op: rt
6608 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6609 Value |= (op & UINT64_C(31)) << 21;
6610 Value |= (op & UINT64_C(31)) << 16;
6611 // op: offset
6612 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6613 op &= UINT64_C(65535);
6614 Value |= op;
6615 break;
6616 }
6617 case Mips::BGEZC_MMR6:
6618 case Mips::BLTZC_MMR6: {
6619 // op: rt
6620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6621 Value |= (op & UINT64_C(31)) << 21;
6622 Value |= (op & UINT64_C(31)) << 16;
6623 // op: offset
6624 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI);
6625 op &= UINT64_C(65535);
6626 Value |= op;
6627 break;
6628 }
6629 case Mips::BGEZALC_MMR6:
6630 case Mips::BLTZALC_MMR6: {
6631 // op: rt
6632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6633 Value |= (op & UINT64_C(31)) << 21;
6634 Value |= (op & UINT64_C(31)) << 16;
6635 // op: offset
6636 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
6637 op &= UINT64_C(65535);
6638 Value |= op;
6639 break;
6640 }
6641 case Mips::DI:
6642 case Mips::DI_MM:
6643 case Mips::DI_MMR6:
6644 case Mips::DMT:
6645 case Mips::DVP:
6646 case Mips::DVPE:
6647 case Mips::EI:
6648 case Mips::EI_MM:
6649 case Mips::EI_MMR6:
6650 case Mips::EMT:
6651 case Mips::EVP:
6652 case Mips::EVPE: {
6653 // op: rt
6654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6655 op &= UINT64_C(31);
6656 op <<= 16;
6657 Value |= op;
6658 break;
6659 }
6660 case Mips::EXTP:
6661 case Mips::EXTPDP:
6662 case Mips::EXTPDPV:
6663 case Mips::EXTPV:
6664 case Mips::EXTRV_RS_W:
6665 case Mips::EXTRV_R_W:
6666 case Mips::EXTRV_S_H:
6667 case Mips::EXTRV_W:
6668 case Mips::EXTR_RS_W:
6669 case Mips::EXTR_R_W:
6670 case Mips::EXTR_S_H:
6671 case Mips::EXTR_W: {
6672 // op: rt
6673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6674 op &= UINT64_C(31);
6675 op <<= 16;
6676 Value |= op;
6677 // op: ac
6678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6679 op &= UINT64_C(3);
6680 op <<= 11;
6681 Value |= op;
6682 // op: shift_rs
6683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6684 op &= UINT64_C(31);
6685 op <<= 21;
6686 Value |= op;
6687 break;
6688 }
6689 case Mips::LL64_R6:
6690 case Mips::LLD_R6:
6691 case Mips::LL_R6: {
6692 // op: rt
6693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6694 op &= UINT64_C(31);
6695 op <<= 16;
6696 Value |= op;
6697 // op: addr
6698 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
6699 Value |= (op & UINT64_C(2031616)) << 5;
6700 Value |= (op & UINT64_C(511)) << 7;
6701 break;
6702 }
6703 case Mips::LB:
6704 case Mips::LB64:
6705 case Mips::LBu:
6706 case Mips::LBu64:
6707 case Mips::LD:
6708 case Mips::LDC1:
6709 case Mips::LDC2:
6710 case Mips::LDC3:
6711 case Mips::LDC164:
6712 case Mips::LDL:
6713 case Mips::LDR:
6714 case Mips::LEA_ADDiu:
6715 case Mips::LEA_ADDiu64:
6716 case Mips::LH:
6717 case Mips::LH64:
6718 case Mips::LHu:
6719 case Mips::LHu64:
6720 case Mips::LL:
6721 case Mips::LL64:
6722 case Mips::LLD:
6723 case Mips::LW:
6724 case Mips::LW64:
6725 case Mips::LWC1:
6726 case Mips::LWC2:
6727 case Mips::LWC3:
6728 case Mips::LWDSP:
6729 case Mips::LWL:
6730 case Mips::LWL64:
6731 case Mips::LWR:
6732 case Mips::LWR64:
6733 case Mips::LWu:
6734 case Mips::SB:
6735 case Mips::SB64:
6736 case Mips::SD:
6737 case Mips::SDC1:
6738 case Mips::SDC2:
6739 case Mips::SDC3:
6740 case Mips::SDC164:
6741 case Mips::SDL:
6742 case Mips::SDR:
6743 case Mips::SH:
6744 case Mips::SH64:
6745 case Mips::SW:
6746 case Mips::SW64:
6747 case Mips::SWC1:
6748 case Mips::SWC2:
6749 case Mips::SWC3:
6750 case Mips::SWDSP:
6751 case Mips::SWL:
6752 case Mips::SWL64:
6753 case Mips::SWR:
6754 case Mips::SWR64: {
6755 // op: rt
6756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6757 op &= UINT64_C(31);
6758 op <<= 16;
6759 Value |= op;
6760 // op: addr
6761 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
6762 Value |= (op & UINT64_C(2031616)) << 5;
6763 Value |= (op & UINT64_C(65535));
6764 break;
6765 }
6766 case Mips::LDC2_R6:
6767 case Mips::LWC2_R6:
6768 case Mips::SDC2_R6:
6769 case Mips::SWC2_R6: {
6770 // op: rt
6771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6772 op &= UINT64_C(31);
6773 op <<= 16;
6774 Value |= op;
6775 // op: addr
6776 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
6777 Value |= (op & UINT64_C(2031616)) >> 5;
6778 Value |= (op & UINT64_C(2047));
6779 break;
6780 }
6781 case Mips::CFC1:
6782 case Mips::DMFC1:
6783 case Mips::MFC1:
6784 case Mips::MFC1_D64:
6785 case Mips::MFHC1_D32:
6786 case Mips::MFHC1_D64: {
6787 // op: rt
6788 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6789 op &= UINT64_C(31);
6790 op <<= 16;
6791 Value |= op;
6792 // op: fs
6793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6794 op &= UINT64_C(31);
6795 op <<= 11;
6796 Value |= op;
6797 break;
6798 }
6799 case Mips::DMFC2_OCTEON:
6800 case Mips::DMTC2_OCTEON:
6801 case Mips::LUi:
6802 case Mips::LUi64:
6803 case Mips::LUi_MM: {
6804 // op: rt
6805 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6806 op &= UINT64_C(31);
6807 op <<= 16;
6808 Value |= op;
6809 // op: imm16
6810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6811 op &= UINT64_C(65535);
6812 Value |= op;
6813 break;
6814 }
6815 case Mips::BEQZALC:
6816 case Mips::BGTZALC:
6817 case Mips::BGTZC:
6818 case Mips::BGTZC64:
6819 case Mips::BLEZALC:
6820 case Mips::BLEZC:
6821 case Mips::BLEZC64:
6822 case Mips::BNEZALC: {
6823 // op: rt
6824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6825 op &= UINT64_C(31);
6826 op <<= 16;
6827 Value |= op;
6828 // op: offset
6829 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6830 op &= UINT64_C(65535);
6831 Value |= op;
6832 break;
6833 }
6834 case Mips::BC1EQZC_MMR6:
6835 case Mips::BC1NEZC_MMR6:
6836 case Mips::BC2EQZC_MMR6:
6837 case Mips::BC2NEZC_MMR6: {
6838 // op: rt
6839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6840 op &= UINT64_C(31);
6841 op <<= 16;
6842 Value |= op;
6843 // op: offset
6844 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
6845 op &= UINT64_C(65535);
6846 Value |= op;
6847 break;
6848 }
6849 case Mips::JIALC:
6850 case Mips::JIALC64:
6851 case Mips::JIALC_MMR6:
6852 case Mips::JIC:
6853 case Mips::JIC64:
6854 case Mips::JIC_MMR6: {
6855 // op: rt
6856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6857 op &= UINT64_C(31);
6858 op <<= 16;
6859 Value |= op;
6860 // op: offset
6861 op = getJumpOffset16OpValue(MI, OpNo: 1, Fixups, STI);
6862 op &= UINT64_C(65535);
6863 Value |= op;
6864 break;
6865 }
6866 case Mips::DMFC0:
6867 case Mips::DMFC2:
6868 case Mips::DMFGC0:
6869 case Mips::MFC0:
6870 case Mips::MFC2:
6871 case Mips::MFGC0:
6872 case Mips::MFHGC0: {
6873 // op: rt
6874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6875 op &= UINT64_C(31);
6876 op <<= 16;
6877 Value |= op;
6878 // op: rd
6879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6880 op &= UINT64_C(31);
6881 op <<= 11;
6882 Value |= op;
6883 // op: sel
6884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6885 op &= UINT64_C(7);
6886 Value |= op;
6887 break;
6888 }
6889 case Mips::RDHWR:
6890 case Mips::RDHWR64: {
6891 // op: rt
6892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6893 op &= UINT64_C(31);
6894 op <<= 16;
6895 Value |= op;
6896 // op: rd
6897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6898 op &= UINT64_C(31);
6899 op <<= 11;
6900 Value |= op;
6901 // op: sel
6902 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6903 op &= UINT64_C(7);
6904 op <<= 6;
6905 Value |= op;
6906 break;
6907 }
6908 case Mips::SAA:
6909 case Mips::SAAD: {
6910 // op: rt
6911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6912 op &= UINT64_C(31);
6913 op <<= 16;
6914 Value |= op;
6915 // op: rs
6916 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6917 op &= UINT64_C(31);
6918 op <<= 21;
6919 Value |= op;
6920 break;
6921 }
6922 case Mips::SLTi:
6923 case Mips::SLTi64:
6924 case Mips::SLTiu:
6925 case Mips::SLTiu64: {
6926 // op: rt
6927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6928 op &= UINT64_C(31);
6929 op <<= 16;
6930 Value |= op;
6931 // op: rs
6932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6933 op &= UINT64_C(31);
6934 op <<= 21;
6935 Value |= op;
6936 // op: imm16
6937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6938 op &= UINT64_C(65535);
6939 Value |= op;
6940 break;
6941 }
6942 case Mips::CINS:
6943 case Mips::CINS32:
6944 case Mips::CINS64_32:
6945 case Mips::CINS_i32:
6946 case Mips::EXTS:
6947 case Mips::EXTS32: {
6948 // op: rt
6949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6950 op &= UINT64_C(31);
6951 op <<= 16;
6952 Value |= op;
6953 // op: rs
6954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6955 op &= UINT64_C(31);
6956 op <<= 21;
6957 Value |= op;
6958 // op: pos
6959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6960 op &= UINT64_C(31);
6961 op <<= 6;
6962 Value |= op;
6963 // op: lenm1
6964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6965 op &= UINT64_C(31);
6966 op <<= 11;
6967 Value |= op;
6968 break;
6969 }
6970 case Mips::DINS:
6971 case Mips::DINSM:
6972 case Mips::DINSU:
6973 case Mips::INS: {
6974 // op: rt
6975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6976 op &= UINT64_C(31);
6977 op <<= 16;
6978 Value |= op;
6979 // op: rs
6980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6981 op &= UINT64_C(31);
6982 op <<= 21;
6983 Value |= op;
6984 // op: pos
6985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6986 op &= UINT64_C(31);
6987 op <<= 6;
6988 Value |= op;
6989 // op: size
6990 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
6991 op &= UINT64_C(31);
6992 op <<= 11;
6993 Value |= op;
6994 break;
6995 }
6996 case Mips::DEXT:
6997 case Mips::DEXT64_32:
6998 case Mips::DEXTM:
6999 case Mips::DEXTU:
7000 case Mips::EXT: {
7001 // op: rt
7002 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7003 op &= UINT64_C(31);
7004 op <<= 16;
7005 Value |= op;
7006 // op: rs
7007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7008 op &= UINT64_C(31);
7009 op <<= 21;
7010 Value |= op;
7011 // op: pos
7012 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7013 op &= UINT64_C(31);
7014 op <<= 6;
7015 Value |= op;
7016 // op: size
7017 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
7018 op &= UINT64_C(31);
7019 op <<= 11;
7020 Value |= op;
7021 break;
7022 }
7023 case Mips::APPEND:
7024 case Mips::BALIGN:
7025 case Mips::PREPEND: {
7026 // op: rt
7027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7028 op &= UINT64_C(31);
7029 op <<= 16;
7030 Value |= op;
7031 // op: rs
7032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7033 op &= UINT64_C(31);
7034 op <<= 21;
7035 Value |= op;
7036 // op: sa
7037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7038 op &= UINT64_C(31);
7039 op <<= 11;
7040 Value |= op;
7041 break;
7042 }
7043 case Mips::INSV: {
7044 // op: rt
7045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7046 op &= UINT64_C(31);
7047 op <<= 16;
7048 Value |= op;
7049 // op: rs
7050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7051 op &= UINT64_C(31);
7052 op <<= 21;
7053 Value |= op;
7054 break;
7055 }
7056 case Mips::LWU_MM: {
7057 // op: rt
7058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7059 op &= UINT64_C(31);
7060 op <<= 21;
7061 Value |= op;
7062 // op: addr
7063 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
7064 Value |= (op & UINT64_C(2031616));
7065 Value |= (op & UINT64_C(4095));
7066 break;
7067 }
7068 case Mips::LBE_MM:
7069 case Mips::LBuE_MM:
7070 case Mips::LHE_MM:
7071 case Mips::LHuE_MM:
7072 case Mips::LLE_MM:
7073 case Mips::LWE_MM:
7074 case Mips::SBE_MM:
7075 case Mips::SHE_MM:
7076 case Mips::SWE_MM: {
7077 // op: rt
7078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7079 op &= UINT64_C(31);
7080 op <<= 21;
7081 Value |= op;
7082 // op: addr
7083 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
7084 Value |= (op & UINT64_C(2031616));
7085 Value |= (op & UINT64_C(511));
7086 break;
7087 }
7088 case Mips::LEA_ADDiu_MM:
7089 case Mips::LH_MM:
7090 case Mips::LHu_MM:
7091 case Mips::LWDSP_MM:
7092 case Mips::LW_MM:
7093 case Mips::LW_MMR6:
7094 case Mips::SB_MM:
7095 case Mips::SB_MMR6:
7096 case Mips::SH_MM:
7097 case Mips::SH_MMR6:
7098 case Mips::SWDSP_MM:
7099 case Mips::SW_MM:
7100 case Mips::SW_MMR6: {
7101 // op: rt
7102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7103 op &= UINT64_C(31);
7104 op <<= 21;
7105 Value |= op;
7106 // op: addr
7107 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
7108 op &= UINT64_C(2097151);
7109 Value |= op;
7110 break;
7111 }
7112 case Mips::LWP_MM:
7113 case Mips::SWP_MM: {
7114 // op: rt
7115 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7116 op &= UINT64_C(31);
7117 op <<= 21;
7118 Value |= op;
7119 // op: addr
7120 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7121 Value |= (op & UINT64_C(2031616));
7122 Value |= (op & UINT64_C(4095));
7123 break;
7124 }
7125 case Mips::LDC2_MMR6:
7126 case Mips::LWC2_MMR6:
7127 case Mips::SDC2_MMR6:
7128 case Mips::SWC2_MMR6: {
7129 // op: rt
7130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7131 op &= UINT64_C(31);
7132 op <<= 21;
7133 Value |= op;
7134 // op: addr
7135 op = getMemEncodingMMImm11(MI, OpNo: 1, Fixups, STI);
7136 Value |= (op & UINT64_C(2031616));
7137 Value |= (op & UINT64_C(2047));
7138 break;
7139 }
7140 case Mips::LL_MM:
7141 case Mips::LWL_MM:
7142 case Mips::LWR_MM:
7143 case Mips::SWL_MM:
7144 case Mips::SWR_MM: {
7145 // op: rt
7146 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7147 op &= UINT64_C(31);
7148 op <<= 21;
7149 Value |= op;
7150 // op: addr
7151 op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI);
7152 Value |= (op & UINT64_C(2031616));
7153 Value |= (op & UINT64_C(4095));
7154 break;
7155 }
7156 case Mips::LB_MM:
7157 case Mips::LBu_MM:
7158 case Mips::LDC1_MM_D32:
7159 case Mips::LDC1_MM_D64:
7160 case Mips::LWC1_MM:
7161 case Mips::SDC1_MM_D32:
7162 case Mips::SDC1_MM_D64:
7163 case Mips::SWC1_MM: {
7164 // op: rt
7165 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7166 op &= UINT64_C(31);
7167 op <<= 21;
7168 Value |= op;
7169 // op: addr
7170 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
7171 op &= UINT64_C(2097151);
7172 Value |= op;
7173 break;
7174 }
7175 case Mips::LL_MMR6:
7176 case Mips::LWLE_MM:
7177 case Mips::LWRE_MM:
7178 case Mips::SWLE_MM:
7179 case Mips::SWRE_MM: {
7180 // op: rt
7181 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7182 op &= UINT64_C(31);
7183 op <<= 21;
7184 Value |= op;
7185 // op: addr
7186 op = getMemEncodingMMImm9(MI, OpNo: 1, Fixups, STI);
7187 Value |= (op & UINT64_C(2031616));
7188 Value |= (op & UINT64_C(511));
7189 break;
7190 }
7191 case Mips::CFC1_MM:
7192 case Mips::MFC1_MM:
7193 case Mips::MFC1_MMR6:
7194 case Mips::MFHC1_D32_MM:
7195 case Mips::MFHC1_D64_MM: {
7196 // op: rt
7197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7198 op &= UINT64_C(31);
7199 op <<= 21;
7200 Value |= op;
7201 // op: fs
7202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7203 op &= UINT64_C(31);
7204 op <<= 16;
7205 Value |= op;
7206 break;
7207 }
7208 case Mips::REPL_QB_MM: {
7209 // op: rt
7210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7211 op &= UINT64_C(31);
7212 op <<= 21;
7213 Value |= op;
7214 // op: imm
7215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7216 op &= UINT64_C(255);
7217 op <<= 13;
7218 Value |= op;
7219 break;
7220 }
7221 case Mips::ALUIPC_MMR6:
7222 case Mips::AUIPC_MMR6: {
7223 // op: rt
7224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7225 op &= UINT64_C(31);
7226 op <<= 21;
7227 Value |= op;
7228 // op: imm
7229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7230 op &= UINT64_C(65535);
7231 Value |= op;
7232 break;
7233 }
7234 case Mips::EXTPDP_MM:
7235 case Mips::EXTP_MM:
7236 case Mips::EXTR_RS_W_MM:
7237 case Mips::EXTR_R_W_MM:
7238 case Mips::EXTR_S_H_MM:
7239 case Mips::EXTR_W_MM: {
7240 // op: rt
7241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7242 op &= UINT64_C(31);
7243 op <<= 21;
7244 Value |= op;
7245 // op: imm
7246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7247 op &= UINT64_C(31);
7248 op <<= 16;
7249 Value |= op;
7250 // op: ac
7251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7252 op &= UINT64_C(3);
7253 op <<= 14;
7254 Value |= op;
7255 break;
7256 }
7257 case Mips::ADDIUPC_MMR6:
7258 case Mips::LWPC_MMR6: {
7259 // op: rt
7260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7261 op &= UINT64_C(31);
7262 op <<= 21;
7263 Value |= op;
7264 // op: imm
7265 op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
7266 op &= UINT64_C(524287);
7267 Value |= op;
7268 break;
7269 }
7270 case Mips::LUI_MMR6: {
7271 // op: rt
7272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7273 op &= UINT64_C(31);
7274 op <<= 21;
7275 Value |= op;
7276 // op: imm16
7277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7278 op &= UINT64_C(65535);
7279 Value |= op;
7280 break;
7281 }
7282 case Mips::CFC2_MM:
7283 case Mips::MFC2_MMR6:
7284 case Mips::MFHC2_MMR6: {
7285 // op: rt
7286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7287 op &= UINT64_C(31);
7288 op <<= 21;
7289 Value |= op;
7290 // op: impl
7291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7292 op &= UINT64_C(31);
7293 op <<= 16;
7294 Value |= op;
7295 break;
7296 }
7297 case Mips::RDDSP_MM:
7298 case Mips::WRDSP_MM: {
7299 // op: rt
7300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7301 op &= UINT64_C(31);
7302 op <<= 21;
7303 Value |= op;
7304 // op: mask
7305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7306 op &= UINT64_C(127);
7307 op <<= 14;
7308 Value |= op;
7309 break;
7310 }
7311 case Mips::BGTZC_MMR6:
7312 case Mips::BLEZC_MMR6: {
7313 // op: rt
7314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7315 op &= UINT64_C(31);
7316 op <<= 21;
7317 Value |= op;
7318 // op: offset
7319 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI);
7320 op &= UINT64_C(65535);
7321 Value |= op;
7322 break;
7323 }
7324 case Mips::BEQZALC_MMR6:
7325 case Mips::BGTZALC_MMR6:
7326 case Mips::BLEZALC_MMR6:
7327 case Mips::BNEZALC_MMR6: {
7328 // op: rt
7329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7330 op &= UINT64_C(31);
7331 op <<= 21;
7332 Value |= op;
7333 // op: offset
7334 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
7335 op &= UINT64_C(65535);
7336 Value |= op;
7337 break;
7338 }
7339 case Mips::RDHWR_MM:
7340 case Mips::RDPGPR_MMR6: {
7341 // op: rt
7342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7343 op &= UINT64_C(31);
7344 op <<= 21;
7345 Value |= op;
7346 // op: rd
7347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7348 op &= UINT64_C(31);
7349 op <<= 16;
7350 Value |= op;
7351 break;
7352 }
7353 case Mips::ABSQ_S_PH_MM:
7354 case Mips::ABSQ_S_QB_MMR2:
7355 case Mips::ABSQ_S_W_MM:
7356 case Mips::BITREV_MM:
7357 case Mips::JALRC_HB_MMR6:
7358 case Mips::JALRC_MMR6:
7359 case Mips::PRECEQU_PH_QBLA_MM:
7360 case Mips::PRECEQU_PH_QBL_MM:
7361 case Mips::PRECEQU_PH_QBRA_MM:
7362 case Mips::PRECEQU_PH_QBR_MM:
7363 case Mips::PRECEQ_W_PHL_MM:
7364 case Mips::PRECEQ_W_PHR_MM:
7365 case Mips::PRECEU_PH_QBLA_MM:
7366 case Mips::PRECEU_PH_QBL_MM:
7367 case Mips::PRECEU_PH_QBRA_MM:
7368 case Mips::PRECEU_PH_QBR_MM:
7369 case Mips::RADDU_W_QB_MM:
7370 case Mips::REPLV_PH_MM:
7371 case Mips::REPLV_QB_MM:
7372 case Mips::WRPGPR_MMR6:
7373 case Mips::WSBH_MMR6: {
7374 // op: rt
7375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7376 op &= UINT64_C(31);
7377 op <<= 21;
7378 Value |= op;
7379 // op: rs
7380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7381 op &= UINT64_C(31);
7382 op <<= 16;
7383 Value |= op;
7384 break;
7385 }
7386 case Mips::BALIGN_MMR2: {
7387 // op: rt
7388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7389 op &= UINT64_C(31);
7390 op <<= 21;
7391 Value |= op;
7392 // op: rs
7393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7394 op &= UINT64_C(31);
7395 op <<= 16;
7396 Value |= op;
7397 // op: bp
7398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7399 op &= UINT64_C(3);
7400 op <<= 14;
7401 Value |= op;
7402 break;
7403 }
7404 case Mips::ADDIU_MMR6:
7405 case Mips::ANDI_MMR6:
7406 case Mips::ORI_MMR6:
7407 case Mips::SLTi_MM:
7408 case Mips::SLTiu_MM:
7409 case Mips::XORI_MMR6: {
7410 // op: rt
7411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7412 op &= UINT64_C(31);
7413 op <<= 21;
7414 Value |= op;
7415 // op: rs
7416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7417 op &= UINT64_C(31);
7418 op <<= 16;
7419 Value |= op;
7420 // op: imm16
7421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7422 op &= UINT64_C(65535);
7423 Value |= op;
7424 break;
7425 }
7426 case Mips::BNVC_MMR6:
7427 case Mips::BOVC_MMR6: {
7428 // op: rt
7429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7430 op &= UINT64_C(31);
7431 op <<= 21;
7432 Value |= op;
7433 // op: rs
7434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7435 op &= UINT64_C(31);
7436 op <<= 16;
7437 Value |= op;
7438 // op: offset
7439 op = getBranchTargetOpValueMMR6(MI, OpNo: 2, Fixups, STI);
7440 op &= UINT64_C(65535);
7441 Value |= op;
7442 break;
7443 }
7444 case Mips::INS_MM: {
7445 // op: rt
7446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7447 op &= UINT64_C(31);
7448 op <<= 21;
7449 Value |= op;
7450 // op: rs
7451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7452 op &= UINT64_C(31);
7453 op <<= 16;
7454 Value |= op;
7455 // op: pos
7456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7457 op &= UINT64_C(31);
7458 op <<= 6;
7459 Value |= op;
7460 // op: size
7461 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
7462 op &= UINT64_C(31);
7463 op <<= 11;
7464 Value |= op;
7465 break;
7466 }
7467 case Mips::EXT_MM: {
7468 // op: rt
7469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7470 op &= UINT64_C(31);
7471 op <<= 21;
7472 Value |= op;
7473 // op: rs
7474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7475 op &= UINT64_C(31);
7476 op <<= 16;
7477 Value |= op;
7478 // op: pos
7479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7480 op &= UINT64_C(31);
7481 op <<= 6;
7482 Value |= op;
7483 // op: size
7484 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
7485 op &= UINT64_C(31);
7486 op <<= 11;
7487 Value |= op;
7488 break;
7489 }
7490 case Mips::SHLL_PH_MM:
7491 case Mips::SHLL_S_PH_MM:
7492 case Mips::SHRA_PH_MM:
7493 case Mips::SHRA_R_PH_MM:
7494 case Mips::SHRL_PH_MMR2: {
7495 // op: rt
7496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7497 op &= UINT64_C(31);
7498 op <<= 21;
7499 Value |= op;
7500 // op: rs
7501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7502 op &= UINT64_C(31);
7503 op <<= 16;
7504 Value |= op;
7505 // op: sa
7506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7507 op &= UINT64_C(15);
7508 op <<= 12;
7509 Value |= op;
7510 break;
7511 }
7512 case Mips::APPEND_MMR2:
7513 case Mips::PRECR_SRA_PH_W_MMR2:
7514 case Mips::PRECR_SRA_R_PH_W_MMR2:
7515 case Mips::PREPEND_MMR2:
7516 case Mips::SHLL_S_W_MM:
7517 case Mips::SHRA_R_W_MM: {
7518 // op: rt
7519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7520 op &= UINT64_C(31);
7521 op <<= 21;
7522 Value |= op;
7523 // op: rs
7524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7525 op &= UINT64_C(31);
7526 op <<= 16;
7527 Value |= op;
7528 // op: sa
7529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7530 op &= UINT64_C(31);
7531 op <<= 11;
7532 Value |= op;
7533 break;
7534 }
7535 case Mips::SHLL_QB_MM:
7536 case Mips::SHRA_QB_MMR2:
7537 case Mips::SHRA_R_QB_MMR2:
7538 case Mips::SHRL_QB_MM: {
7539 // op: rt
7540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7541 op &= UINT64_C(31);
7542 op <<= 21;
7543 Value |= op;
7544 // op: rs
7545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7546 op &= UINT64_C(31);
7547 op <<= 16;
7548 Value |= op;
7549 // op: sa
7550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7551 op &= UINT64_C(7);
7552 op <<= 13;
7553 Value |= op;
7554 break;
7555 }
7556 case Mips::MFC0_MMR6:
7557 case Mips::MFGC0_MM:
7558 case Mips::MFHC0_MMR6:
7559 case Mips::MFHGC0_MM:
7560 case Mips::RDHWR_MMR6: {
7561 // op: rt
7562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7563 op &= UINT64_C(31);
7564 op <<= 21;
7565 Value |= op;
7566 // op: rs
7567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7568 op &= UINT64_C(31);
7569 op <<= 16;
7570 Value |= op;
7571 // op: sel
7572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7573 op &= UINT64_C(7);
7574 op <<= 11;
7575 Value |= op;
7576 break;
7577 }
7578 case Mips::INS_MMR6: {
7579 // op: rt
7580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7581 op &= UINT64_C(31);
7582 op <<= 21;
7583 Value |= op;
7584 // op: rs
7585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7586 op &= UINT64_C(31);
7587 op <<= 16;
7588 Value |= op;
7589 // op: size
7590 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
7591 op &= UINT64_C(31);
7592 op <<= 11;
7593 Value |= op;
7594 // op: pos
7595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7596 op &= UINT64_C(31);
7597 op <<= 6;
7598 Value |= op;
7599 break;
7600 }
7601 case Mips::EXT_MMR6: {
7602 // op: rt
7603 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7604 op &= UINT64_C(31);
7605 op <<= 21;
7606 Value |= op;
7607 // op: rs
7608 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7609 op &= UINT64_C(31);
7610 op <<= 16;
7611 Value |= op;
7612 // op: size
7613 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
7614 op &= UINT64_C(31);
7615 op <<= 11;
7616 Value |= op;
7617 // op: pos
7618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7619 op &= UINT64_C(31);
7620 op <<= 6;
7621 Value |= op;
7622 break;
7623 }
7624 case Mips::INSV_MM: {
7625 // op: rt
7626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7627 op &= UINT64_C(31);
7628 op <<= 21;
7629 Value |= op;
7630 // op: rs
7631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7632 op &= UINT64_C(31);
7633 op <<= 16;
7634 Value |= op;
7635 break;
7636 }
7637 case Mips::EXTPDPV_MM:
7638 case Mips::EXTPV_MM:
7639 case Mips::EXTRV_RS_W_MM:
7640 case Mips::EXTRV_R_W_MM:
7641 case Mips::EXTRV_S_H_MM:
7642 case Mips::EXTRV_W_MM: {
7643 // op: rt
7644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7645 op &= UINT64_C(31);
7646 op <<= 21;
7647 Value |= op;
7648 // op: rs
7649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7650 op &= UINT64_C(31);
7651 op <<= 16;
7652 Value |= op;
7653 // op: ac
7654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7655 op &= UINT64_C(3);
7656 op <<= 14;
7657 Value |= op;
7658 break;
7659 }
7660 case Mips::LWSP_MM:
7661 case Mips::SWSP_MM:
7662 case Mips::SWSP_MMR6: {
7663 // op: rt
7664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7665 op &= UINT64_C(31);
7666 op <<= 5;
7667 Value |= op;
7668 // op: offset
7669 op = getMemEncodingMMSPImm5Lsl2(MI, OpNo: 1, Fixups, STI);
7670 op &= UINT64_C(31);
7671 Value |= op;
7672 break;
7673 }
7674 case Mips::NOT16_MM: {
7675 // op: rt
7676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7677 op &= UINT64_C(7);
7678 op <<= 3;
7679 Value |= op;
7680 // op: rs
7681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7682 op &= UINT64_C(7);
7683 Value |= op;
7684 break;
7685 }
7686 case Mips::LBU16_MM:
7687 case Mips::SB16_MM:
7688 case Mips::SB16_MMR6: {
7689 // op: rt
7690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7691 op &= UINT64_C(7);
7692 op <<= 7;
7693 Value |= op;
7694 // op: addr
7695 op = getMemEncodingMMImm4(MI, OpNo: 1, Fixups, STI);
7696 op &= UINT64_C(127);
7697 Value |= op;
7698 break;
7699 }
7700 case Mips::LHU16_MM:
7701 case Mips::SH16_MM:
7702 case Mips::SH16_MMR6: {
7703 // op: rt
7704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7705 op &= UINT64_C(7);
7706 op <<= 7;
7707 Value |= op;
7708 // op: addr
7709 op = getMemEncodingMMImm4Lsl1(MI, OpNo: 1, Fixups, STI);
7710 op &= UINT64_C(127);
7711 Value |= op;
7712 break;
7713 }
7714 case Mips::LW16_MM:
7715 case Mips::SW16_MM:
7716 case Mips::SW16_MMR6: {
7717 // op: rt
7718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7719 op &= UINT64_C(7);
7720 op <<= 7;
7721 Value |= op;
7722 // op: addr
7723 op = getMemEncodingMMImm4Lsl2(MI, OpNo: 1, Fixups, STI);
7724 op &= UINT64_C(127);
7725 Value |= op;
7726 break;
7727 }
7728 case Mips::LWGP_MM: {
7729 // op: rt
7730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7731 op &= UINT64_C(7);
7732 op <<= 7;
7733 Value |= op;
7734 // op: offset
7735 op = getMemEncodingMMGPImm7Lsl2(MI, OpNo: 1, Fixups, STI);
7736 op &= UINT64_C(127);
7737 Value |= op;
7738 break;
7739 }
7740 case Mips::NOT16_MMR6: {
7741 // op: rt
7742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7743 op &= UINT64_C(7);
7744 op <<= 7;
7745 Value |= op;
7746 // op: rs
7747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7748 op &= UINT64_C(7);
7749 op <<= 4;
7750 Value |= op;
7751 break;
7752 }
7753 case Mips::SC64_R6:
7754 case Mips::SCD_R6:
7755 case Mips::SC_R6: {
7756 // op: rt
7757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7758 op &= UINT64_C(31);
7759 op <<= 16;
7760 Value |= op;
7761 // op: addr
7762 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7763 Value |= (op & UINT64_C(2031616)) << 5;
7764 Value |= (op & UINT64_C(511)) << 7;
7765 break;
7766 }
7767 case Mips::SC:
7768 case Mips::SC64:
7769 case Mips::SCD: {
7770 // op: rt
7771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7772 op &= UINT64_C(31);
7773 op <<= 16;
7774 Value |= op;
7775 // op: addr
7776 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7777 Value |= (op & UINT64_C(2031616)) << 5;
7778 Value |= (op & UINT64_C(65535));
7779 break;
7780 }
7781 case Mips::CTC1:
7782 case Mips::DMTC1:
7783 case Mips::MTC1:
7784 case Mips::MTC1_D64: {
7785 // op: rt
7786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7787 op &= UINT64_C(31);
7788 op <<= 16;
7789 Value |= op;
7790 // op: fs
7791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7792 op &= UINT64_C(31);
7793 op <<= 11;
7794 Value |= op;
7795 break;
7796 }
7797 case Mips::DMTC0:
7798 case Mips::DMTC2:
7799 case Mips::DMTGC0:
7800 case Mips::MTC0:
7801 case Mips::MTC2:
7802 case Mips::MTGC0:
7803 case Mips::MTHGC0: {
7804 // op: rt
7805 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7806 op &= UINT64_C(31);
7807 op <<= 16;
7808 Value |= op;
7809 // op: rd
7810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7811 op &= UINT64_C(31);
7812 op <<= 11;
7813 Value |= op;
7814 // op: sel
7815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7816 op &= UINT64_C(7);
7817 Value |= op;
7818 break;
7819 }
7820 case Mips::MFTR:
7821 case Mips::MTTR: {
7822 // op: rt
7823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7824 op &= UINT64_C(31);
7825 op <<= 16;
7826 Value |= op;
7827 // op: rd
7828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7829 op &= UINT64_C(31);
7830 op <<= 11;
7831 Value |= op;
7832 // op: u
7833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7834 op &= UINT64_C(1);
7835 op <<= 5;
7836 Value |= op;
7837 // op: h
7838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7839 op &= UINT64_C(1);
7840 op <<= 4;
7841 Value |= op;
7842 // op: sel
7843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7844 op &= UINT64_C(7);
7845 Value |= op;
7846 break;
7847 }
7848 case Mips::SCE_MM: {
7849 // op: rt
7850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7851 op &= UINT64_C(31);
7852 op <<= 21;
7853 Value |= op;
7854 // op: addr
7855 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7856 Value |= (op & UINT64_C(2031616));
7857 Value |= (op & UINT64_C(511));
7858 break;
7859 }
7860 case Mips::SC_MM: {
7861 // op: rt
7862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7863 op &= UINT64_C(31);
7864 op <<= 21;
7865 Value |= op;
7866 // op: addr
7867 op = getMemEncodingMMImm12(MI, OpNo: 2, Fixups, STI);
7868 Value |= (op & UINT64_C(2031616));
7869 Value |= (op & UINT64_C(4095));
7870 break;
7871 }
7872 case Mips::SC_MMR6: {
7873 // op: rt
7874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7875 op &= UINT64_C(31);
7876 op <<= 21;
7877 Value |= op;
7878 // op: addr
7879 op = getMemEncodingMMImm9(MI, OpNo: 2, Fixups, STI);
7880 Value |= (op & UINT64_C(2031616));
7881 Value |= (op & UINT64_C(511));
7882 break;
7883 }
7884 case Mips::CTC1_MM:
7885 case Mips::MTC1_D64_MM:
7886 case Mips::MTC1_MM:
7887 case Mips::MTC1_MMR6: {
7888 // op: rt
7889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7890 op &= UINT64_C(31);
7891 op <<= 21;
7892 Value |= op;
7893 // op: fs
7894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7895 op &= UINT64_C(31);
7896 op <<= 16;
7897 Value |= op;
7898 break;
7899 }
7900 case Mips::CTC2_MM:
7901 case Mips::MTC2_MMR6:
7902 case Mips::MTHC2_MMR6: {
7903 // op: rt
7904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7905 op &= UINT64_C(31);
7906 op <<= 21;
7907 Value |= op;
7908 // op: impl
7909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7910 op &= UINT64_C(31);
7911 op <<= 16;
7912 Value |= op;
7913 break;
7914 }
7915 case Mips::CMPU_EQ_QB_MM:
7916 case Mips::CMPU_LE_QB_MM:
7917 case Mips::CMPU_LT_QB_MM:
7918 case Mips::CMP_EQ_PH_MM:
7919 case Mips::CMP_LE_PH_MM:
7920 case Mips::CMP_LT_PH_MM: {
7921 // op: rt
7922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7923 op &= UINT64_C(31);
7924 op <<= 21;
7925 Value |= op;
7926 // op: rs
7927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7928 op &= UINT64_C(31);
7929 op <<= 16;
7930 Value |= op;
7931 break;
7932 }
7933 case Mips::BEQC_MMR6:
7934 case Mips::BGEC_MMR6:
7935 case Mips::BGEUC_MMR6:
7936 case Mips::BLTC_MMR6:
7937 case Mips::BLTUC_MMR6:
7938 case Mips::BNEC_MMR6: {
7939 // op: rt
7940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7941 op &= UINT64_C(31);
7942 op <<= 21;
7943 Value |= op;
7944 // op: rs
7945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7946 op &= UINT64_C(31);
7947 op <<= 16;
7948 Value |= op;
7949 // op: offset
7950 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 2, Fixups, STI);
7951 op &= UINT64_C(65535);
7952 Value |= op;
7953 break;
7954 }
7955 case Mips::MTC0_MMR6:
7956 case Mips::MTGC0_MM:
7957 case Mips::MTHC0_MMR6:
7958 case Mips::MTHGC0_MM: {
7959 // op: rt
7960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7961 op &= UINT64_C(31);
7962 op <<= 21;
7963 Value |= op;
7964 // op: rs
7965 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7966 op &= UINT64_C(31);
7967 op <<= 16;
7968 Value |= op;
7969 // op: sel
7970 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7971 op &= UINT64_C(7);
7972 op <<= 11;
7973 Value |= op;
7974 break;
7975 }
7976 case Mips::MTHC1_D32:
7977 case Mips::MTHC1_D64: {
7978 // op: rt
7979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7980 op &= UINT64_C(31);
7981 op <<= 16;
7982 Value |= op;
7983 // op: fs
7984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7985 op &= UINT64_C(31);
7986 op <<= 11;
7987 Value |= op;
7988 break;
7989 }
7990 case Mips::SPLAT_B:
7991 case Mips::SPLAT_D:
7992 case Mips::SPLAT_H:
7993 case Mips::SPLAT_W: {
7994 // op: rt
7995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7996 op &= UINT64_C(31);
7997 op <<= 16;
7998 Value |= op;
7999 // op: ws
8000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8001 op &= UINT64_C(31);
8002 op <<= 11;
8003 Value |= op;
8004 // op: wd
8005 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8006 op &= UINT64_C(31);
8007 op <<= 6;
8008 Value |= op;
8009 break;
8010 }
8011 case Mips::MTHC1_D32_MM:
8012 case Mips::MTHC1_D64_MM: {
8013 // op: rt
8014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8015 op &= UINT64_C(31);
8016 op <<= 21;
8017 Value |= op;
8018 // op: fs
8019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8020 op &= UINT64_C(31);
8021 op <<= 16;
8022 Value |= op;
8023 break;
8024 }
8025 case Mips::DPAQX_SA_W_PH_MMR2:
8026 case Mips::DPAQX_S_W_PH_MMR2:
8027 case Mips::DPAQ_SA_L_W_MM:
8028 case Mips::DPAQ_S_W_PH_MM:
8029 case Mips::DPAU_H_QBL_MM:
8030 case Mips::DPAU_H_QBR_MM:
8031 case Mips::DPAX_W_PH_MMR2:
8032 case Mips::DPA_W_PH_MMR2:
8033 case Mips::DPSQX_SA_W_PH_MMR2:
8034 case Mips::DPSQX_S_W_PH_MMR2:
8035 case Mips::DPSQ_SA_L_W_MM:
8036 case Mips::DPSQ_S_W_PH_MM:
8037 case Mips::DPSU_H_QBL_MM:
8038 case Mips::DPSU_H_QBR_MM:
8039 case Mips::DPSX_W_PH_MMR2:
8040 case Mips::DPS_W_PH_MMR2:
8041 case Mips::MADDU_DSP_MM:
8042 case Mips::MADD_DSP_MM:
8043 case Mips::MAQ_SA_W_PHL_MM:
8044 case Mips::MAQ_SA_W_PHR_MM:
8045 case Mips::MAQ_S_W_PHL_MM:
8046 case Mips::MAQ_S_W_PHR_MM:
8047 case Mips::MSUBU_DSP_MM:
8048 case Mips::MSUB_DSP_MM:
8049 case Mips::MULSAQ_S_W_PH_MM:
8050 case Mips::MULSA_W_PH_MMR2:
8051 case Mips::MULTU_DSP_MM:
8052 case Mips::MULT_DSP_MM: {
8053 // op: rt
8054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8055 op &= UINT64_C(31);
8056 op <<= 21;
8057 Value |= op;
8058 // op: rs
8059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8060 op &= UINT64_C(31);
8061 op <<= 16;
8062 Value |= op;
8063 // op: ac
8064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8065 op &= UINT64_C(3);
8066 op <<= 14;
8067 Value |= op;
8068 break;
8069 }
8070 case Mips::ADD_MM:
8071 case Mips::ADDu_MM:
8072 case Mips::AND_MM:
8073 case Mips::CMPGU_EQ_QB_MM:
8074 case Mips::CMPGU_LE_QB_MM:
8075 case Mips::CMPGU_LT_QB_MM:
8076 case Mips::MOVN_I_MM:
8077 case Mips::MOVZ_I_MM:
8078 case Mips::MUL_MM:
8079 case Mips::NOR_MM:
8080 case Mips::OR_MM:
8081 case Mips::SLT_MM:
8082 case Mips::SLTu_MM:
8083 case Mips::SUB_MM:
8084 case Mips::SUBu_MM:
8085 case Mips::XOR_MM: {
8086 // op: rt
8087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8088 op &= UINT64_C(31);
8089 op <<= 21;
8090 Value |= op;
8091 // op: rs
8092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8093 op &= UINT64_C(31);
8094 op <<= 16;
8095 Value |= op;
8096 // op: rd
8097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8098 op &= UINT64_C(31);
8099 op <<= 11;
8100 Value |= op;
8101 break;
8102 }
8103 case Mips::AND16_MM:
8104 case Mips::OR16_MM:
8105 case Mips::XOR16_MM: {
8106 // op: rt
8107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8108 op &= UINT64_C(7);
8109 op <<= 3;
8110 Value |= op;
8111 // op: rs
8112 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8113 op &= UINT64_C(7);
8114 Value |= op;
8115 break;
8116 }
8117 case Mips::AND16_MMR6:
8118 case Mips::OR16_MMR6:
8119 case Mips::XOR16_MMR6: {
8120 // op: rt
8121 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8122 op &= UINT64_C(7);
8123 op <<= 7;
8124 Value |= op;
8125 // op: rs
8126 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8127 op &= UINT64_C(7);
8128 op <<= 4;
8129 Value |= op;
8130 break;
8131 }
8132 case Mips::SLD_B:
8133 case Mips::SLD_D:
8134 case Mips::SLD_H:
8135 case Mips::SLD_W: {
8136 // op: rt
8137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8138 op &= UINT64_C(31);
8139 op <<= 16;
8140 Value |= op;
8141 // op: ws
8142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8143 op &= UINT64_C(31);
8144 op <<= 11;
8145 Value |= op;
8146 // op: wd
8147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8148 op &= UINT64_C(31);
8149 op <<= 6;
8150 Value |= op;
8151 break;
8152 }
8153 case Mips::MOVEP_MMR6: {
8154 // op: rt
8155 op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI);
8156 op &= UINT64_C(7);
8157 op <<= 4;
8158 Value |= op;
8159 // op: rs
8160 op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI);
8161 Value |= (op & UINT64_C(4)) << 1;
8162 Value |= (op & UINT64_C(3));
8163 break;
8164 }
8165 case Mips::MOVEP_MM: {
8166 // op: rt
8167 op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI);
8168 op &= UINT64_C(7);
8169 op <<= 4;
8170 Value |= op;
8171 // op: rs
8172 op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI);
8173 op &= UINT64_C(7);
8174 op <<= 1;
8175 Value |= op;
8176 break;
8177 }
8178 case Mips::LWM32_MM:
8179 case Mips::SWM32_MM: {
8180 // op: rt
8181 op = getRegisterListOpValue(MI, OpNo: 0, Fixups, STI);
8182 op &= UINT64_C(31);
8183 op <<= 21;
8184 Value |= op;
8185 // op: addr
8186 op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI);
8187 Value |= (op & UINT64_C(2031616));
8188 Value |= (op & UINT64_C(4095));
8189 break;
8190 }
8191 case Mips::LWM16_MM:
8192 case Mips::SWM16_MM: {
8193 // op: rt
8194 op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI);
8195 op &= UINT64_C(3);
8196 op <<= 4;
8197 Value |= op;
8198 // op: addr
8199 op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI);
8200 op &= UINT64_C(15);
8201 Value |= op;
8202 break;
8203 }
8204 case Mips::LWM16_MMR6:
8205 case Mips::SWM16_MMR6: {
8206 // op: rt
8207 op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI);
8208 op &= UINT64_C(3);
8209 op <<= 8;
8210 Value |= op;
8211 // op: addr
8212 op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI);
8213 op &= UINT64_C(15);
8214 op <<= 4;
8215 Value |= op;
8216 break;
8217 }
8218 case Mips::JumpLinkReg16:
8219 case Mips::Mfhi16:
8220 case Mips::Mflo16:
8221 case Mips::SebRx16:
8222 case Mips::SehRx16: {
8223 // op: rx
8224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8225 op &= UINT64_C(7);
8226 op <<= 8;
8227 Value |= op;
8228 break;
8229 }
8230 case Mips::BeqzRxImm16:
8231 case Mips::BnezRxImm16: {
8232 // op: rx
8233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8234 op &= UINT64_C(7);
8235 op <<= 8;
8236 Value |= op;
8237 // op: imm8
8238 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
8239 op &= UINT64_C(255);
8240 Value |= op;
8241 break;
8242 }
8243 case Mips::CmpiRxImm16:
8244 case Mips::LiRxImm16:
8245 case Mips::LwRxPcTcp16:
8246 case Mips::SltiRxImm16:
8247 case Mips::SltiuRxImm16: {
8248 // op: rx
8249 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8250 op &= UINT64_C(7);
8251 op <<= 8;
8252 Value |= op;
8253 // op: imm8
8254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8255 op &= UINT64_C(255);
8256 Value |= op;
8257 break;
8258 }
8259 case Mips::AddiuRxRxImm16: {
8260 // op: rx
8261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8262 op &= UINT64_C(7);
8263 op <<= 8;
8264 Value |= op;
8265 // op: imm8
8266 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8267 op &= UINT64_C(255);
8268 Value |= op;
8269 break;
8270 }
8271 case Mips::CmpRxRy16:
8272 case Mips::DivRxRy16:
8273 case Mips::DivuRxRy16:
8274 case Mips::NegRxRy16:
8275 case Mips::NotRxRy16:
8276 case Mips::SltRxRy16:
8277 case Mips::SltuRxRy16: {
8278 // op: rx
8279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8280 op &= UINT64_C(7);
8281 op <<= 8;
8282 Value |= op;
8283 // op: ry
8284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8285 op &= UINT64_C(7);
8286 op <<= 5;
8287 Value |= op;
8288 break;
8289 }
8290 case Mips::AndRxRxRy16:
8291 case Mips::OrRxRxRy16:
8292 case Mips::SllvRxRy16:
8293 case Mips::SravRxRy16:
8294 case Mips::SrlvRxRy16:
8295 case Mips::XorRxRxRy16: {
8296 // op: rx
8297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8298 op &= UINT64_C(7);
8299 op <<= 8;
8300 Value |= op;
8301 // op: ry
8302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8303 op &= UINT64_C(7);
8304 op <<= 5;
8305 Value |= op;
8306 break;
8307 }
8308 case Mips::AdduRxRyRz16:
8309 case Mips::SubuRxRyRz16: {
8310 // op: rx
8311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8312 op &= UINT64_C(7);
8313 op <<= 8;
8314 Value |= op;
8315 // op: ry
8316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8317 op &= UINT64_C(7);
8318 op <<= 5;
8319 Value |= op;
8320 // op: rz
8321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8322 op &= UINT64_C(7);
8323 op <<= 2;
8324 Value |= op;
8325 break;
8326 }
8327 case Mips::MoveR3216: {
8328 // op: ry
8329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8330 op &= UINT64_C(15);
8331 op <<= 4;
8332 Value |= op;
8333 // op: r32
8334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8335 op &= UINT64_C(15);
8336 Value |= op;
8337 break;
8338 }
8339 case Mips::LDI_B:
8340 case Mips::LDI_D:
8341 case Mips::LDI_H:
8342 case Mips::LDI_W: {
8343 // op: s10
8344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8345 op &= UINT64_C(1023);
8346 op <<= 11;
8347 Value |= op;
8348 // op: wd
8349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8350 op &= UINT64_C(31);
8351 op <<= 6;
8352 Value |= op;
8353 break;
8354 }
8355 case Mips::SllX16:
8356 case Mips::SraX16:
8357 case Mips::SrlX16: {
8358 // op: sa6
8359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8360 Value |= (op & UINT64_C(31)) << 22;
8361 Value |= (op & UINT64_C(32)) << 16;
8362 // op: rx
8363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8364 op &= UINT64_C(7);
8365 op <<= 8;
8366 Value |= op;
8367 // op: ry
8368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8369 op &= UINT64_C(7);
8370 op <<= 5;
8371 Value |= op;
8372 break;
8373 }
8374 case Mips::SHILO_MM: {
8375 // op: shift
8376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8377 op &= UINT64_C(63);
8378 op <<= 16;
8379 Value |= op;
8380 // op: ac
8381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8382 op &= UINT64_C(3);
8383 op <<= 14;
8384 Value |= op;
8385 break;
8386 }
8387 case Mips::SYNC_MM:
8388 case Mips::SYNC_MMR6: {
8389 // op: stype
8390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8391 op &= UINT64_C(31);
8392 op <<= 16;
8393 Value |= op;
8394 break;
8395 }
8396 case Mips::SYNC: {
8397 // op: stype
8398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8399 op &= UINT64_C(31);
8400 op <<= 6;
8401 Value |= op;
8402 break;
8403 }
8404 case Mips::J:
8405 case Mips::JAL:
8406 case Mips::JALX:
8407 case Mips::JALX_MM: {
8408 // op: target
8409 op = getJumpTargetOpValue(MI, OpNo: 0, Fixups, STI);
8410 op &= UINT64_C(67108863);
8411 Value |= op;
8412 break;
8413 }
8414 case Mips::JALS_MM:
8415 case Mips::JAL_MM:
8416 case Mips::J_MM: {
8417 // op: target
8418 op = getJumpTargetOpValueMM(MI, OpNo: 0, Fixups, STI);
8419 op &= UINT64_C(67108863);
8420 Value |= op;
8421 break;
8422 }
8423 case Mips::ANDI_B:
8424 case Mips::NORI_B:
8425 case Mips::ORI_B:
8426 case Mips::SHF_B:
8427 case Mips::SHF_H:
8428 case Mips::SHF_W:
8429 case Mips::XORI_B: {
8430 // op: u8
8431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8432 op &= UINT64_C(255);
8433 op <<= 16;
8434 Value |= op;
8435 // op: ws
8436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8437 op &= UINT64_C(31);
8438 op <<= 11;
8439 Value |= op;
8440 // op: wd
8441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8442 op &= UINT64_C(31);
8443 op <<= 6;
8444 Value |= op;
8445 break;
8446 }
8447 case Mips::BMNZI_B:
8448 case Mips::BMZI_B:
8449 case Mips::BSELI_B: {
8450 // op: u8
8451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8452 op &= UINT64_C(255);
8453 op <<= 16;
8454 Value |= op;
8455 // op: ws
8456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8457 op &= UINT64_C(31);
8458 op <<= 11;
8459 Value |= op;
8460 // op: wd
8461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8462 op &= UINT64_C(31);
8463 op <<= 6;
8464 Value |= op;
8465 break;
8466 }
8467 case Mips::FCLASS_D:
8468 case Mips::FCLASS_W:
8469 case Mips::FEXUPL_D:
8470 case Mips::FEXUPL_W:
8471 case Mips::FEXUPR_D:
8472 case Mips::FEXUPR_W:
8473 case Mips::FFINT_S_D:
8474 case Mips::FFINT_S_W:
8475 case Mips::FFINT_U_D:
8476 case Mips::FFINT_U_W:
8477 case Mips::FFQL_D:
8478 case Mips::FFQL_W:
8479 case Mips::FFQR_D:
8480 case Mips::FFQR_W:
8481 case Mips::FLOG2_D:
8482 case Mips::FLOG2_W:
8483 case Mips::FRCP_D:
8484 case Mips::FRCP_W:
8485 case Mips::FRINT_D:
8486 case Mips::FRINT_W:
8487 case Mips::FRSQRT_D:
8488 case Mips::FRSQRT_W:
8489 case Mips::FSQRT_D:
8490 case Mips::FSQRT_W:
8491 case Mips::FTINT_S_D:
8492 case Mips::FTINT_S_W:
8493 case Mips::FTINT_U_D:
8494 case Mips::FTINT_U_W:
8495 case Mips::FTRUNC_S_D:
8496 case Mips::FTRUNC_S_W:
8497 case Mips::FTRUNC_U_D:
8498 case Mips::FTRUNC_U_W:
8499 case Mips::MOVE_V:
8500 case Mips::NLOC_B:
8501 case Mips::NLOC_D:
8502 case Mips::NLOC_H:
8503 case Mips::NLOC_W:
8504 case Mips::NLZC_B:
8505 case Mips::NLZC_D:
8506 case Mips::NLZC_H:
8507 case Mips::NLZC_W:
8508 case Mips::PCNT_B:
8509 case Mips::PCNT_D:
8510 case Mips::PCNT_H:
8511 case Mips::PCNT_W: {
8512 // op: ws
8513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8514 op &= UINT64_C(31);
8515 op <<= 11;
8516 Value |= op;
8517 // op: wd
8518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8519 op &= UINT64_C(31);
8520 op <<= 6;
8521 Value |= op;
8522 break;
8523 }
8524 case Mips::BCLRI_H:
8525 case Mips::BNEGI_H:
8526 case Mips::BSETI_H:
8527 case Mips::SAT_S_H:
8528 case Mips::SAT_U_H:
8529 case Mips::SLLI_H:
8530 case Mips::SRAI_H:
8531 case Mips::SRARI_H:
8532 case Mips::SRLI_H:
8533 case Mips::SRLRI_H: {
8534 // op: ws
8535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8536 op &= UINT64_C(31);
8537 op <<= 11;
8538 Value |= op;
8539 // op: wd
8540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8541 op &= UINT64_C(31);
8542 op <<= 6;
8543 Value |= op;
8544 // op: m
8545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8546 op &= UINT64_C(15);
8547 op <<= 16;
8548 Value |= op;
8549 break;
8550 }
8551 case Mips::BCLRI_W:
8552 case Mips::BNEGI_W:
8553 case Mips::BSETI_W:
8554 case Mips::SAT_S_W:
8555 case Mips::SAT_U_W:
8556 case Mips::SLLI_W:
8557 case Mips::SRAI_W:
8558 case Mips::SRARI_W:
8559 case Mips::SRLI_W:
8560 case Mips::SRLRI_W: {
8561 // op: ws
8562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8563 op &= UINT64_C(31);
8564 op <<= 11;
8565 Value |= op;
8566 // op: wd
8567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8568 op &= UINT64_C(31);
8569 op <<= 6;
8570 Value |= op;
8571 // op: m
8572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8573 op &= UINT64_C(31);
8574 op <<= 16;
8575 Value |= op;
8576 break;
8577 }
8578 case Mips::BCLRI_D:
8579 case Mips::BNEGI_D:
8580 case Mips::BSETI_D:
8581 case Mips::SAT_S_D:
8582 case Mips::SAT_U_D:
8583 case Mips::SLLI_D:
8584 case Mips::SRAI_D:
8585 case Mips::SRARI_D:
8586 case Mips::SRLI_D:
8587 case Mips::SRLRI_D: {
8588 // op: ws
8589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8590 op &= UINT64_C(31);
8591 op <<= 11;
8592 Value |= op;
8593 // op: wd
8594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8595 op &= UINT64_C(31);
8596 op <<= 6;
8597 Value |= op;
8598 // op: m
8599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8600 op &= UINT64_C(63);
8601 op <<= 16;
8602 Value |= op;
8603 break;
8604 }
8605 case Mips::BCLRI_B:
8606 case Mips::BNEGI_B:
8607 case Mips::BSETI_B:
8608 case Mips::SAT_S_B:
8609 case Mips::SAT_U_B:
8610 case Mips::SLLI_B:
8611 case Mips::SRAI_B:
8612 case Mips::SRARI_B:
8613 case Mips::SRLI_B:
8614 case Mips::SRLRI_B: {
8615 // op: ws
8616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8617 op &= UINT64_C(31);
8618 op <<= 11;
8619 Value |= op;
8620 // op: wd
8621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8622 op &= UINT64_C(31);
8623 op <<= 6;
8624 Value |= op;
8625 // op: m
8626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8627 op &= UINT64_C(7);
8628 op <<= 16;
8629 Value |= op;
8630 break;
8631 }
8632 case Mips::BINSLI_H:
8633 case Mips::BINSRI_H: {
8634 // op: ws
8635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8636 op &= UINT64_C(31);
8637 op <<= 11;
8638 Value |= op;
8639 // op: wd
8640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8641 op &= UINT64_C(31);
8642 op <<= 6;
8643 Value |= op;
8644 // op: m
8645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8646 op &= UINT64_C(15);
8647 op <<= 16;
8648 Value |= op;
8649 break;
8650 }
8651 case Mips::BINSLI_W:
8652 case Mips::BINSRI_W: {
8653 // op: ws
8654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8655 op &= UINT64_C(31);
8656 op <<= 11;
8657 Value |= op;
8658 // op: wd
8659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8660 op &= UINT64_C(31);
8661 op <<= 6;
8662 Value |= op;
8663 // op: m
8664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8665 op &= UINT64_C(31);
8666 op <<= 16;
8667 Value |= op;
8668 break;
8669 }
8670 case Mips::BINSLI_D:
8671 case Mips::BINSRI_D: {
8672 // op: ws
8673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8674 op &= UINT64_C(31);
8675 op <<= 11;
8676 Value |= op;
8677 // op: wd
8678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8679 op &= UINT64_C(31);
8680 op <<= 6;
8681 Value |= op;
8682 // op: m
8683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8684 op &= UINT64_C(63);
8685 op <<= 16;
8686 Value |= op;
8687 break;
8688 }
8689 case Mips::BINSLI_B:
8690 case Mips::BINSRI_B: {
8691 // op: ws
8692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8693 op &= UINT64_C(31);
8694 op <<= 11;
8695 Value |= op;
8696 // op: wd
8697 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8698 op &= UINT64_C(31);
8699 op <<= 6;
8700 Value |= op;
8701 // op: m
8702 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8703 op &= UINT64_C(7);
8704 op <<= 16;
8705 Value |= op;
8706 break;
8707 }
8708 case Mips::ADDS_A_B:
8709 case Mips::ADDS_A_D:
8710 case Mips::ADDS_A_H:
8711 case Mips::ADDS_A_W:
8712 case Mips::ADDS_S_B:
8713 case Mips::ADDS_S_D:
8714 case Mips::ADDS_S_H:
8715 case Mips::ADDS_S_W:
8716 case Mips::ADDS_U_B:
8717 case Mips::ADDS_U_D:
8718 case Mips::ADDS_U_H:
8719 case Mips::ADDS_U_W:
8720 case Mips::ADDV_B:
8721 case Mips::ADDV_D:
8722 case Mips::ADDV_H:
8723 case Mips::ADDV_W:
8724 case Mips::ADD_A_B:
8725 case Mips::ADD_A_D:
8726 case Mips::ADD_A_H:
8727 case Mips::ADD_A_W:
8728 case Mips::AND_V:
8729 case Mips::ASUB_S_B:
8730 case Mips::ASUB_S_D:
8731 case Mips::ASUB_S_H:
8732 case Mips::ASUB_S_W:
8733 case Mips::ASUB_U_B:
8734 case Mips::ASUB_U_D:
8735 case Mips::ASUB_U_H:
8736 case Mips::ASUB_U_W:
8737 case Mips::AVER_S_B:
8738 case Mips::AVER_S_D:
8739 case Mips::AVER_S_H:
8740 case Mips::AVER_S_W:
8741 case Mips::AVER_U_B:
8742 case Mips::AVER_U_D:
8743 case Mips::AVER_U_H:
8744 case Mips::AVER_U_W:
8745 case Mips::AVE_S_B:
8746 case Mips::AVE_S_D:
8747 case Mips::AVE_S_H:
8748 case Mips::AVE_S_W:
8749 case Mips::AVE_U_B:
8750 case Mips::AVE_U_D:
8751 case Mips::AVE_U_H:
8752 case Mips::AVE_U_W:
8753 case Mips::BCLR_B:
8754 case Mips::BCLR_D:
8755 case Mips::BCLR_H:
8756 case Mips::BCLR_W:
8757 case Mips::BNEG_B:
8758 case Mips::BNEG_D:
8759 case Mips::BNEG_H:
8760 case Mips::BNEG_W:
8761 case Mips::BSET_B:
8762 case Mips::BSET_D:
8763 case Mips::BSET_H:
8764 case Mips::BSET_W:
8765 case Mips::CEQ_B:
8766 case Mips::CEQ_D:
8767 case Mips::CEQ_H:
8768 case Mips::CEQ_W:
8769 case Mips::CLE_S_B:
8770 case Mips::CLE_S_D:
8771 case Mips::CLE_S_H:
8772 case Mips::CLE_S_W:
8773 case Mips::CLE_U_B:
8774 case Mips::CLE_U_D:
8775 case Mips::CLE_U_H:
8776 case Mips::CLE_U_W:
8777 case Mips::CLT_S_B:
8778 case Mips::CLT_S_D:
8779 case Mips::CLT_S_H:
8780 case Mips::CLT_S_W:
8781 case Mips::CLT_U_B:
8782 case Mips::CLT_U_D:
8783 case Mips::CLT_U_H:
8784 case Mips::CLT_U_W:
8785 case Mips::DIV_S_B:
8786 case Mips::DIV_S_D:
8787 case Mips::DIV_S_H:
8788 case Mips::DIV_S_W:
8789 case Mips::DIV_U_B:
8790 case Mips::DIV_U_D:
8791 case Mips::DIV_U_H:
8792 case Mips::DIV_U_W:
8793 case Mips::DOTP_S_D:
8794 case Mips::DOTP_S_H:
8795 case Mips::DOTP_S_W:
8796 case Mips::DOTP_U_D:
8797 case Mips::DOTP_U_H:
8798 case Mips::DOTP_U_W:
8799 case Mips::FADD_D:
8800 case Mips::FADD_W:
8801 case Mips::FCAF_D:
8802 case Mips::FCAF_W:
8803 case Mips::FCEQ_D:
8804 case Mips::FCEQ_W:
8805 case Mips::FCLE_D:
8806 case Mips::FCLE_W:
8807 case Mips::FCLT_D:
8808 case Mips::FCLT_W:
8809 case Mips::FCNE_D:
8810 case Mips::FCNE_W:
8811 case Mips::FCOR_D:
8812 case Mips::FCOR_W:
8813 case Mips::FCUEQ_D:
8814 case Mips::FCUEQ_W:
8815 case Mips::FCULE_D:
8816 case Mips::FCULE_W:
8817 case Mips::FCULT_D:
8818 case Mips::FCULT_W:
8819 case Mips::FCUNE_D:
8820 case Mips::FCUNE_W:
8821 case Mips::FCUN_D:
8822 case Mips::FCUN_W:
8823 case Mips::FDIV_D:
8824 case Mips::FDIV_W:
8825 case Mips::FEXDO_H:
8826 case Mips::FEXDO_W:
8827 case Mips::FEXP2_D:
8828 case Mips::FEXP2_W:
8829 case Mips::FMAX_A_D:
8830 case Mips::FMAX_A_W:
8831 case Mips::FMAX_D:
8832 case Mips::FMAX_W:
8833 case Mips::FMIN_A_D:
8834 case Mips::FMIN_A_W:
8835 case Mips::FMIN_D:
8836 case Mips::FMIN_W:
8837 case Mips::FMUL_D:
8838 case Mips::FMUL_W:
8839 case Mips::FSAF_D:
8840 case Mips::FSAF_W:
8841 case Mips::FSEQ_D:
8842 case Mips::FSEQ_W:
8843 case Mips::FSLE_D:
8844 case Mips::FSLE_W:
8845 case Mips::FSLT_D:
8846 case Mips::FSLT_W:
8847 case Mips::FSNE_D:
8848 case Mips::FSNE_W:
8849 case Mips::FSOR_D:
8850 case Mips::FSOR_W:
8851 case Mips::FSUB_D:
8852 case Mips::FSUB_W:
8853 case Mips::FSUEQ_D:
8854 case Mips::FSUEQ_W:
8855 case Mips::FSULE_D:
8856 case Mips::FSULE_W:
8857 case Mips::FSULT_D:
8858 case Mips::FSULT_W:
8859 case Mips::FSUNE_D:
8860 case Mips::FSUNE_W:
8861 case Mips::FSUN_D:
8862 case Mips::FSUN_W:
8863 case Mips::FTQ_H:
8864 case Mips::FTQ_W:
8865 case Mips::HADD_S_D:
8866 case Mips::HADD_S_H:
8867 case Mips::HADD_S_W:
8868 case Mips::HADD_U_D:
8869 case Mips::HADD_U_H:
8870 case Mips::HADD_U_W:
8871 case Mips::HSUB_S_D:
8872 case Mips::HSUB_S_H:
8873 case Mips::HSUB_S_W:
8874 case Mips::HSUB_U_D:
8875 case Mips::HSUB_U_H:
8876 case Mips::HSUB_U_W:
8877 case Mips::ILVEV_B:
8878 case Mips::ILVEV_D:
8879 case Mips::ILVEV_H:
8880 case Mips::ILVEV_W:
8881 case Mips::ILVL_B:
8882 case Mips::ILVL_D:
8883 case Mips::ILVL_H:
8884 case Mips::ILVL_W:
8885 case Mips::ILVOD_B:
8886 case Mips::ILVOD_D:
8887 case Mips::ILVOD_H:
8888 case Mips::ILVOD_W:
8889 case Mips::ILVR_B:
8890 case Mips::ILVR_D:
8891 case Mips::ILVR_H:
8892 case Mips::ILVR_W:
8893 case Mips::MAX_A_B:
8894 case Mips::MAX_A_D:
8895 case Mips::MAX_A_H:
8896 case Mips::MAX_A_W:
8897 case Mips::MAX_S_B:
8898 case Mips::MAX_S_D:
8899 case Mips::MAX_S_H:
8900 case Mips::MAX_S_W:
8901 case Mips::MAX_U_B:
8902 case Mips::MAX_U_D:
8903 case Mips::MAX_U_H:
8904 case Mips::MAX_U_W:
8905 case Mips::MIN_A_B:
8906 case Mips::MIN_A_D:
8907 case Mips::MIN_A_H:
8908 case Mips::MIN_A_W:
8909 case Mips::MIN_S_B:
8910 case Mips::MIN_S_D:
8911 case Mips::MIN_S_H:
8912 case Mips::MIN_S_W:
8913 case Mips::MIN_U_B:
8914 case Mips::MIN_U_D:
8915 case Mips::MIN_U_H:
8916 case Mips::MIN_U_W:
8917 case Mips::MOD_S_B:
8918 case Mips::MOD_S_D:
8919 case Mips::MOD_S_H:
8920 case Mips::MOD_S_W:
8921 case Mips::MOD_U_B:
8922 case Mips::MOD_U_D:
8923 case Mips::MOD_U_H:
8924 case Mips::MOD_U_W:
8925 case Mips::MULR_Q_H:
8926 case Mips::MULR_Q_W:
8927 case Mips::MULV_B:
8928 case Mips::MULV_D:
8929 case Mips::MULV_H:
8930 case Mips::MULV_W:
8931 case Mips::MUL_Q_H:
8932 case Mips::MUL_Q_W:
8933 case Mips::NOR_V:
8934 case Mips::OR_V:
8935 case Mips::PCKEV_B:
8936 case Mips::PCKEV_D:
8937 case Mips::PCKEV_H:
8938 case Mips::PCKEV_W:
8939 case Mips::PCKOD_B:
8940 case Mips::PCKOD_D:
8941 case Mips::PCKOD_H:
8942 case Mips::PCKOD_W:
8943 case Mips::SLL_B:
8944 case Mips::SLL_D:
8945 case Mips::SLL_H:
8946 case Mips::SLL_W:
8947 case Mips::SRAR_B:
8948 case Mips::SRAR_D:
8949 case Mips::SRAR_H:
8950 case Mips::SRAR_W:
8951 case Mips::SRA_B:
8952 case Mips::SRA_D:
8953 case Mips::SRA_H:
8954 case Mips::SRA_W:
8955 case Mips::SRLR_B:
8956 case Mips::SRLR_D:
8957 case Mips::SRLR_H:
8958 case Mips::SRLR_W:
8959 case Mips::SRL_B:
8960 case Mips::SRL_D:
8961 case Mips::SRL_H:
8962 case Mips::SRL_W:
8963 case Mips::SUBSUS_U_B:
8964 case Mips::SUBSUS_U_D:
8965 case Mips::SUBSUS_U_H:
8966 case Mips::SUBSUS_U_W:
8967 case Mips::SUBSUU_S_B:
8968 case Mips::SUBSUU_S_D:
8969 case Mips::SUBSUU_S_H:
8970 case Mips::SUBSUU_S_W:
8971 case Mips::SUBS_S_B:
8972 case Mips::SUBS_S_D:
8973 case Mips::SUBS_S_H:
8974 case Mips::SUBS_S_W:
8975 case Mips::SUBS_U_B:
8976 case Mips::SUBS_U_D:
8977 case Mips::SUBS_U_H:
8978 case Mips::SUBS_U_W:
8979 case Mips::SUBV_B:
8980 case Mips::SUBV_D:
8981 case Mips::SUBV_H:
8982 case Mips::SUBV_W:
8983 case Mips::XOR_V: {
8984 // op: wt
8985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8986 op &= UINT64_C(31);
8987 op <<= 16;
8988 Value |= op;
8989 // op: ws
8990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8991 op &= UINT64_C(31);
8992 op <<= 11;
8993 Value |= op;
8994 // op: wd
8995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8996 op &= UINT64_C(31);
8997 op <<= 6;
8998 Value |= op;
8999 break;
9000 }
9001 case Mips::BINSL_B:
9002 case Mips::BINSL_D:
9003 case Mips::BINSL_H:
9004 case Mips::BINSL_W:
9005 case Mips::BINSR_B:
9006 case Mips::BINSR_D:
9007 case Mips::BINSR_H:
9008 case Mips::BINSR_W:
9009 case Mips::BMNZ_V:
9010 case Mips::BMZ_V:
9011 case Mips::BSEL_V:
9012 case Mips::DPADD_S_D:
9013 case Mips::DPADD_S_H:
9014 case Mips::DPADD_S_W:
9015 case Mips::DPADD_U_D:
9016 case Mips::DPADD_U_H:
9017 case Mips::DPADD_U_W:
9018 case Mips::DPSUB_S_D:
9019 case Mips::DPSUB_S_H:
9020 case Mips::DPSUB_S_W:
9021 case Mips::DPSUB_U_D:
9022 case Mips::DPSUB_U_H:
9023 case Mips::DPSUB_U_W:
9024 case Mips::FMADD_D:
9025 case Mips::FMADD_W:
9026 case Mips::FMSUB_D:
9027 case Mips::FMSUB_W:
9028 case Mips::MADDR_Q_H:
9029 case Mips::MADDR_Q_W:
9030 case Mips::MADDV_B:
9031 case Mips::MADDV_D:
9032 case Mips::MADDV_H:
9033 case Mips::MADDV_W:
9034 case Mips::MADD_Q_H:
9035 case Mips::MADD_Q_W:
9036 case Mips::MSUBR_Q_H:
9037 case Mips::MSUBR_Q_W:
9038 case Mips::MSUBV_B:
9039 case Mips::MSUBV_D:
9040 case Mips::MSUBV_H:
9041 case Mips::MSUBV_W:
9042 case Mips::MSUB_Q_H:
9043 case Mips::MSUB_Q_W:
9044 case Mips::VSHF_B:
9045 case Mips::VSHF_D:
9046 case Mips::VSHF_H:
9047 case Mips::VSHF_W: {
9048 // op: wt
9049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9050 op &= UINT64_C(31);
9051 op <<= 16;
9052 Value |= op;
9053 // op: ws
9054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9055 op &= UINT64_C(31);
9056 op <<= 11;
9057 Value |= op;
9058 // op: wd
9059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9060 op &= UINT64_C(31);
9061 op <<= 6;
9062 Value |= op;
9063 break;
9064 }
9065 default:
9066 std::string msg;
9067 raw_string_ostream Msg(msg);
9068 Msg << "Not supported instr: " << MI;
9069 report_fatal_error(reason: Msg.str().c_str());
9070 }
9071 return Value;
9072}
9073
9074#ifdef GET_OPERAND_BIT_OFFSET
9075#undef GET_OPERAND_BIT_OFFSET
9076
9077uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
9078 unsigned OpNum,
9079 const MCSubtargetInfo &STI) const {
9080 switch (MI.getOpcode()) {
9081 case Mips::Break16:
9082 case Mips::DERET:
9083 case Mips::DERET_MM:
9084 case Mips::DERET_MMR6:
9085 case Mips::EHB:
9086 case Mips::EHB_MM:
9087 case Mips::EHB_MMR6:
9088 case Mips::ERET:
9089 case Mips::ERETNC:
9090 case Mips::ERETNC_MMR6:
9091 case Mips::ERET_MM:
9092 case Mips::ERET_MMR6:
9093 case Mips::JrRa16:
9094 case Mips::JrcRa16:
9095 case Mips::JrcRx16:
9096 case Mips::NAL:
9097 case Mips::PAUSE:
9098 case Mips::PAUSE_MM:
9099 case Mips::PAUSE_MMR6:
9100 case Mips::Restore16:
9101 case Mips::RestoreX16:
9102 case Mips::SSNOP:
9103 case Mips::SSNOP_MM:
9104 case Mips::SSNOP_MMR6:
9105 case Mips::Save16:
9106 case Mips::SaveX16:
9107 case Mips::TLBGINV:
9108 case Mips::TLBGINVF:
9109 case Mips::TLBGINVF_MM:
9110 case Mips::TLBGINV_MM:
9111 case Mips::TLBGP:
9112 case Mips::TLBGP_MM:
9113 case Mips::TLBGR:
9114 case Mips::TLBGR_MM:
9115 case Mips::TLBGWI:
9116 case Mips::TLBGWI_MM:
9117 case Mips::TLBGWR:
9118 case Mips::TLBGWR_MM:
9119 case Mips::TLBINV:
9120 case Mips::TLBINVF:
9121 case Mips::TLBINVF_MMR6:
9122 case Mips::TLBINV_MMR6:
9123 case Mips::TLBP:
9124 case Mips::TLBP_MM:
9125 case Mips::TLBR:
9126 case Mips::TLBR_MM:
9127 case Mips::TLBWI:
9128 case Mips::TLBWI_MM:
9129 case Mips::TLBWR:
9130 case Mips::TLBWR_MM:
9131 case Mips::WAIT: {
9132 break;
9133 }
9134 case Mips::DPAQX_SA_W_PH:
9135 case Mips::DPAQX_S_W_PH:
9136 case Mips::DPAQ_SA_L_W:
9137 case Mips::DPAQ_S_W_PH:
9138 case Mips::DPAU_H_QBL:
9139 case Mips::DPAU_H_QBR:
9140 case Mips::DPAX_W_PH:
9141 case Mips::DPA_W_PH:
9142 case Mips::DPSQX_SA_W_PH:
9143 case Mips::DPSQX_S_W_PH:
9144 case Mips::DPSQ_SA_L_W:
9145 case Mips::DPSQ_S_W_PH:
9146 case Mips::DPSU_H_QBL:
9147 case Mips::DPSU_H_QBR:
9148 case Mips::DPSX_W_PH:
9149 case Mips::DPS_W_PH:
9150 case Mips::MADDU_DSP:
9151 case Mips::MADD_DSP:
9152 case Mips::MAQ_SA_W_PHL:
9153 case Mips::MAQ_SA_W_PHR:
9154 case Mips::MAQ_S_W_PHL:
9155 case Mips::MAQ_S_W_PHR:
9156 case Mips::MSUBU_DSP:
9157 case Mips::MSUB_DSP:
9158 case Mips::MULSAQ_S_W_PH:
9159 case Mips::MULSA_W_PH:
9160 case Mips::MULTU_DSP:
9161 case Mips::MULT_DSP: {
9162 switch (OpNum) {
9163 case 0:
9164 // op: ac
9165 return 11;
9166 case 1:
9167 // op: rs
9168 return 21;
9169 case 2:
9170 // op: rt
9171 return 16;
9172 }
9173 break;
9174 }
9175 case Mips::MTHLIP:
9176 case Mips::SHILOV: {
9177 switch (OpNum) {
9178 case 0:
9179 // op: ac
9180 return 11;
9181 case 1:
9182 // op: rs
9183 return 21;
9184 }
9185 break;
9186 }
9187 case Mips::SHILO: {
9188 switch (OpNum) {
9189 case 0:
9190 // op: ac
9191 return 11;
9192 case 1:
9193 // op: shift
9194 return 20;
9195 }
9196 break;
9197 }
9198 case Mips::CACHE:
9199 case Mips::PREF: {
9200 switch (OpNum) {
9201 case 0:
9202 // op: addr
9203 return 0;
9204 case 2:
9205 // op: hint
9206 return 16;
9207 }
9208 break;
9209 }
9210 case Mips::CACHEE_MM:
9211 case Mips::CACHE_MM:
9212 case Mips::CACHE_MMR6:
9213 case Mips::PREFE_MM:
9214 case Mips::PREF_MM:
9215 case Mips::PREF_MMR6: {
9216 switch (OpNum) {
9217 case 0:
9218 // op: addr
9219 return 0;
9220 case 2:
9221 // op: hint
9222 return 21;
9223 }
9224 break;
9225 }
9226 case Mips::SYNCI:
9227 case Mips::SYNCI_MM:
9228 case Mips::SYNCI_MMR6: {
9229 switch (OpNum) {
9230 case 0:
9231 // op: addr
9232 return 0;
9233 }
9234 break;
9235 }
9236 case Mips::CACHEE:
9237 case Mips::CACHE_R6:
9238 case Mips::PREFE:
9239 case Mips::PREF_R6: {
9240 switch (OpNum) {
9241 case 0:
9242 // op: addr
9243 return 7;
9244 case 2:
9245 // op: hint
9246 return 16;
9247 }
9248 break;
9249 }
9250 case Mips::BREAK16_MM:
9251 case Mips::SDBBP16_MM:
9252 case Mips::SIGRIE: {
9253 switch (OpNum) {
9254 case 0:
9255 // op: code_
9256 return 0;
9257 }
9258 break;
9259 }
9260 case Mips::HYPCALL: {
9261 switch (OpNum) {
9262 case 0:
9263 // op: code_
9264 return 11;
9265 }
9266 break;
9267 }
9268 case Mips::HYPCALL_MM:
9269 case Mips::SDBBP_MM:
9270 case Mips::SDBBP_MMR6:
9271 case Mips::SYSCALL_MM:
9272 case Mips::WAIT_MM:
9273 case Mips::WAIT_MMR6: {
9274 switch (OpNum) {
9275 case 0:
9276 // op: code_
9277 return 16;
9278 }
9279 break;
9280 }
9281 case Mips::BREAK16_MMR6:
9282 case Mips::SDBBP:
9283 case Mips::SDBBP16_MMR6:
9284 case Mips::SDBBP_R6:
9285 case Mips::SIGRIE_MMR6:
9286 case Mips::SYSCALL: {
9287 switch (OpNum) {
9288 case 0:
9289 // op: code_
9290 return 6;
9291 }
9292 break;
9293 }
9294 case Mips::BREAK:
9295 case Mips::BREAK_MM:
9296 case Mips::BREAK_MMR6: {
9297 switch (OpNum) {
9298 case 0:
9299 // op: code_1
9300 return 16;
9301 case 1:
9302 // op: code_2
9303 return 6;
9304 }
9305 break;
9306 }
9307 case Mips::BC2EQZ:
9308 case Mips::BC2NEZ: {
9309 switch (OpNum) {
9310 case 0:
9311 // op: ct
9312 return 16;
9313 case 1:
9314 // op: offset
9315 return 0;
9316 }
9317 break;
9318 }
9319 case Mips::BC1F:
9320 case Mips::BC1FL:
9321 case Mips::BC1F_MM:
9322 case Mips::BC1T:
9323 case Mips::BC1TL:
9324 case Mips::BC1T_MM: {
9325 switch (OpNum) {
9326 case 0:
9327 // op: fcc
9328 return 18;
9329 case 1:
9330 // op: offset
9331 return 0;
9332 }
9333 break;
9334 }
9335 case Mips::LUXC1_MM:
9336 case Mips::LWXC1_MM: {
9337 switch (OpNum) {
9338 case 0:
9339 // op: fd
9340 return 11;
9341 case 1:
9342 // op: base
9343 return 16;
9344 case 2:
9345 // op: index
9346 return 21;
9347 }
9348 break;
9349 }
9350 case Mips::MOVN_I_D32_MM:
9351 case Mips::MOVN_I_S_MM:
9352 case Mips::MOVZ_I_D32_MM:
9353 case Mips::MOVZ_I_S_MM: {
9354 switch (OpNum) {
9355 case 0:
9356 // op: fd
9357 return 11;
9358 case 1:
9359 // op: fs
9360 return 16;
9361 case 2:
9362 // op: rt
9363 return 21;
9364 }
9365 break;
9366 }
9367 case Mips::MOVF_D32_MM:
9368 case Mips::MOVF_S_MM:
9369 case Mips::MOVT_D32_MM:
9370 case Mips::MOVT_S_MM: {
9371 switch (OpNum) {
9372 case 0:
9373 // op: fd
9374 return 21;
9375 case 1:
9376 // op: fs
9377 return 16;
9378 case 2:
9379 // op: fcc
9380 return 13;
9381 }
9382 break;
9383 }
9384 case Mips::CEIL_W_MM:
9385 case Mips::CEIL_W_S_MM:
9386 case Mips::CVT_D32_S_MM:
9387 case Mips::CVT_D32_W_MM:
9388 case Mips::CVT_D64_S_MM:
9389 case Mips::CVT_D64_W_MM:
9390 case Mips::CVT_L_D64_MM:
9391 case Mips::CVT_L_S_MM:
9392 case Mips::CVT_S_D32_MM:
9393 case Mips::CVT_S_D64_MM:
9394 case Mips::CVT_S_W_MM:
9395 case Mips::CVT_W_D32_MM:
9396 case Mips::CVT_W_D64_MM:
9397 case Mips::CVT_W_S_MM:
9398 case Mips::FABS_D32_MM:
9399 case Mips::FABS_D64_MM:
9400 case Mips::FABS_S_MM:
9401 case Mips::FLOOR_W_MM:
9402 case Mips::FLOOR_W_S_MM:
9403 case Mips::FMOV_D32_MM:
9404 case Mips::FMOV_D64_MM:
9405 case Mips::FMOV_S_MM:
9406 case Mips::FNEG_D32_MM:
9407 case Mips::FNEG_D64_MM:
9408 case Mips::FNEG_S_MM:
9409 case Mips::FSQRT_D32_MM:
9410 case Mips::FSQRT_D64_MM:
9411 case Mips::FSQRT_S_MM:
9412 case Mips::RECIP_D32_MM:
9413 case Mips::RECIP_D64_MM:
9414 case Mips::RECIP_S_MM:
9415 case Mips::ROUND_W_MM:
9416 case Mips::ROUND_W_S_MM:
9417 case Mips::RSQRT_D32_MM:
9418 case Mips::RSQRT_D64_MM:
9419 case Mips::RSQRT_S_MM:
9420 case Mips::TRUNC_W_MM:
9421 case Mips::TRUNC_W_S_MM: {
9422 switch (OpNum) {
9423 case 0:
9424 // op: fd
9425 return 21;
9426 case 1:
9427 // op: fs
9428 return 16;
9429 }
9430 break;
9431 }
9432 case Mips::LDXC1:
9433 case Mips::LDXC164:
9434 case Mips::LUXC1:
9435 case Mips::LUXC164:
9436 case Mips::LWXC1: {
9437 switch (OpNum) {
9438 case 0:
9439 // op: fd
9440 return 6;
9441 case 1:
9442 // op: base
9443 return 21;
9444 case 2:
9445 // op: index
9446 return 16;
9447 }
9448 break;
9449 }
9450 case Mips::MADD_D32:
9451 case Mips::MADD_D64:
9452 case Mips::MADD_S:
9453 case Mips::MSUB_D32:
9454 case Mips::MSUB_D64:
9455 case Mips::MSUB_S:
9456 case Mips::NMADD_D32:
9457 case Mips::NMADD_D64:
9458 case Mips::NMADD_S:
9459 case Mips::NMSUB_D32:
9460 case Mips::NMSUB_D64:
9461 case Mips::NMSUB_S: {
9462 switch (OpNum) {
9463 case 0:
9464 // op: fd
9465 return 6;
9466 case 1:
9467 // op: fr
9468 return 21;
9469 case 2:
9470 // op: fs
9471 return 11;
9472 case 3:
9473 // op: ft
9474 return 16;
9475 }
9476 break;
9477 }
9478 case Mips::MOVF_D32:
9479 case Mips::MOVF_D64:
9480 case Mips::MOVF_S:
9481 case Mips::MOVT_D32:
9482 case Mips::MOVT_D64:
9483 case Mips::MOVT_S: {
9484 switch (OpNum) {
9485 case 0:
9486 // op: fd
9487 return 6;
9488 case 1:
9489 // op: fs
9490 return 11;
9491 case 2:
9492 // op: fcc
9493 return 18;
9494 }
9495 break;
9496 }
9497 case Mips::ADDR_PS64:
9498 case Mips::CMP_EQ_D:
9499 case Mips::CMP_EQ_S:
9500 case Mips::CMP_F_D:
9501 case Mips::CMP_F_S:
9502 case Mips::CMP_LE_D:
9503 case Mips::CMP_LE_S:
9504 case Mips::CMP_LT_D:
9505 case Mips::CMP_LT_S:
9506 case Mips::CMP_SAF_D:
9507 case Mips::CMP_SAF_S:
9508 case Mips::CMP_SEQ_D:
9509 case Mips::CMP_SEQ_S:
9510 case Mips::CMP_SLE_D:
9511 case Mips::CMP_SLE_S:
9512 case Mips::CMP_SLT_D:
9513 case Mips::CMP_SLT_S:
9514 case Mips::CMP_SUEQ_D:
9515 case Mips::CMP_SUEQ_S:
9516 case Mips::CMP_SULE_D:
9517 case Mips::CMP_SULE_S:
9518 case Mips::CMP_SULT_D:
9519 case Mips::CMP_SULT_S:
9520 case Mips::CMP_SUN_D:
9521 case Mips::CMP_SUN_S:
9522 case Mips::CMP_UEQ_D:
9523 case Mips::CMP_UEQ_S:
9524 case Mips::CMP_ULE_D:
9525 case Mips::CMP_ULE_S:
9526 case Mips::CMP_ULT_D:
9527 case Mips::CMP_ULT_S:
9528 case Mips::CMP_UN_D:
9529 case Mips::CMP_UN_S:
9530 case Mips::CVT_PS_S64:
9531 case Mips::FADD_D32:
9532 case Mips::FADD_D64:
9533 case Mips::FADD_PS64:
9534 case Mips::FADD_S:
9535 case Mips::FDIV_D32:
9536 case Mips::FDIV_D64:
9537 case Mips::FDIV_S:
9538 case Mips::FMUL_D32:
9539 case Mips::FMUL_D64:
9540 case Mips::FMUL_PS64:
9541 case Mips::FMUL_S:
9542 case Mips::FSUB_D32:
9543 case Mips::FSUB_D64:
9544 case Mips::FSUB_PS64:
9545 case Mips::FSUB_S:
9546 case Mips::MULR_PS64:
9547 case Mips::PLL_PS64:
9548 case Mips::PLU_PS64:
9549 case Mips::PUL_PS64:
9550 case Mips::PUU_PS64: {
9551 switch (OpNum) {
9552 case 0:
9553 // op: fd
9554 return 6;
9555 case 1:
9556 // op: fs
9557 return 11;
9558 case 2:
9559 // op: ft
9560 return 16;
9561 }
9562 break;
9563 }
9564 case Mips::MOVN_I64_D64:
9565 case Mips::MOVN_I64_S:
9566 case Mips::MOVN_I_D32:
9567 case Mips::MOVN_I_D64:
9568 case Mips::MOVN_I_S:
9569 case Mips::MOVZ_I64_D64:
9570 case Mips::MOVZ_I64_S:
9571 case Mips::MOVZ_I_D32:
9572 case Mips::MOVZ_I_D64:
9573 case Mips::MOVZ_I_S: {
9574 switch (OpNum) {
9575 case 0:
9576 // op: fd
9577 return 6;
9578 case 1:
9579 // op: fs
9580 return 11;
9581 case 2:
9582 // op: rt
9583 return 16;
9584 }
9585 break;
9586 }
9587 case Mips::CEIL_L_D64:
9588 case Mips::CEIL_L_S:
9589 case Mips::CEIL_W_D32:
9590 case Mips::CEIL_W_D64:
9591 case Mips::CEIL_W_S:
9592 case Mips::CVT_D32_S:
9593 case Mips::CVT_D32_W:
9594 case Mips::CVT_D64_L:
9595 case Mips::CVT_D64_S:
9596 case Mips::CVT_D64_W:
9597 case Mips::CVT_L_D64:
9598 case Mips::CVT_L_S:
9599 case Mips::CVT_PS_PW64:
9600 case Mips::CVT_PW_PS64:
9601 case Mips::CVT_S_D32:
9602 case Mips::CVT_S_D64:
9603 case Mips::CVT_S_L:
9604 case Mips::CVT_S_PL64:
9605 case Mips::CVT_S_PU64:
9606 case Mips::CVT_S_W:
9607 case Mips::CVT_W_D32:
9608 case Mips::CVT_W_D64:
9609 case Mips::CVT_W_S:
9610 case Mips::FABS_D32:
9611 case Mips::FABS_D64:
9612 case Mips::FABS_S:
9613 case Mips::FLOOR_L_D64:
9614 case Mips::FLOOR_L_S:
9615 case Mips::FLOOR_W_D32:
9616 case Mips::FLOOR_W_D64:
9617 case Mips::FLOOR_W_S:
9618 case Mips::FMOV_D32:
9619 case Mips::FMOV_D64:
9620 case Mips::FMOV_S:
9621 case Mips::FNEG_D32:
9622 case Mips::FNEG_D64:
9623 case Mips::FNEG_S:
9624 case Mips::FSQRT_D32:
9625 case Mips::FSQRT_D64:
9626 case Mips::FSQRT_S:
9627 case Mips::RECIP_D32:
9628 case Mips::RECIP_D64:
9629 case Mips::RECIP_S:
9630 case Mips::ROUND_L_D64:
9631 case Mips::ROUND_L_S:
9632 case Mips::ROUND_W_D32:
9633 case Mips::ROUND_W_D64:
9634 case Mips::ROUND_W_S:
9635 case Mips::RSQRT_D32:
9636 case Mips::RSQRT_D64:
9637 case Mips::RSQRT_S:
9638 case Mips::TRUNC_L_D64:
9639 case Mips::TRUNC_L_S:
9640 case Mips::TRUNC_W_D32:
9641 case Mips::TRUNC_W_D64:
9642 case Mips::TRUNC_W_S: {
9643 switch (OpNum) {
9644 case 0:
9645 // op: fd
9646 return 6;
9647 case 1:
9648 // op: fs
9649 return 11;
9650 }
9651 break;
9652 }
9653 case Mips::SUXC1_MM:
9654 case Mips::SWXC1_MM: {
9655 switch (OpNum) {
9656 case 0:
9657 // op: fs
9658 return 11;
9659 case 1:
9660 // op: base
9661 return 16;
9662 case 2:
9663 // op: index
9664 return 21;
9665 }
9666 break;
9667 }
9668 case Mips::SDXC1:
9669 case Mips::SDXC164:
9670 case Mips::SUXC1:
9671 case Mips::SUXC164:
9672 case Mips::SWXC1: {
9673 switch (OpNum) {
9674 case 0:
9675 // op: fs
9676 return 11;
9677 case 1:
9678 // op: base
9679 return 21;
9680 case 2:
9681 // op: index
9682 return 16;
9683 }
9684 break;
9685 }
9686 case Mips::FCMP_D32:
9687 case Mips::FCMP_D64:
9688 case Mips::FCMP_S32: {
9689 switch (OpNum) {
9690 case 0:
9691 // op: fs
9692 return 11;
9693 case 1:
9694 // op: ft
9695 return 16;
9696 case 2:
9697 // op: cond
9698 return 0;
9699 }
9700 break;
9701 }
9702 case Mips::FCMP_D32_MM:
9703 case Mips::FCMP_S32_MM: {
9704 switch (OpNum) {
9705 case 0:
9706 // op: fs
9707 return 16;
9708 case 1:
9709 // op: ft
9710 return 21;
9711 case 2:
9712 // op: cond
9713 return 6;
9714 }
9715 break;
9716 }
9717 case Mips::BC1EQZ:
9718 case Mips::BC1NEZ: {
9719 switch (OpNum) {
9720 case 0:
9721 // op: ft
9722 return 16;
9723 case 1:
9724 // op: offset
9725 return 0;
9726 }
9727 break;
9728 }
9729 case Mips::LDC1_D64_MMR6:
9730 case Mips::SDC1_D64_MMR6: {
9731 switch (OpNum) {
9732 case 0:
9733 // op: ft
9734 return 21;
9735 case 1:
9736 // op: addr
9737 return 0;
9738 }
9739 break;
9740 }
9741 case Mips::CEIL_L_D_MMR6:
9742 case Mips::CEIL_L_S_MMR6:
9743 case Mips::CEIL_W_D_MMR6:
9744 case Mips::CEIL_W_S_MMR6:
9745 case Mips::CVT_D_L_MMR6:
9746 case Mips::CVT_L_D_MMR6:
9747 case Mips::CVT_L_S_MMR6:
9748 case Mips::CVT_S_L_MMR6:
9749 case Mips::CVT_S_W_MMR6:
9750 case Mips::CVT_W_S_MMR6:
9751 case Mips::FLOOR_L_D_MMR6:
9752 case Mips::FLOOR_L_S_MMR6:
9753 case Mips::FLOOR_W_D_MMR6:
9754 case Mips::FLOOR_W_S_MMR6:
9755 case Mips::FMOV_D_MMR6:
9756 case Mips::FMOV_S_MMR6:
9757 case Mips::FNEG_S_MMR6:
9758 case Mips::ROUND_L_D_MMR6:
9759 case Mips::ROUND_L_S_MMR6:
9760 case Mips::ROUND_W_D_MMR6:
9761 case Mips::ROUND_W_S_MMR6:
9762 case Mips::TRUNC_L_D_MMR6:
9763 case Mips::TRUNC_L_S_MMR6:
9764 case Mips::TRUNC_W_D_MMR6:
9765 case Mips::TRUNC_W_S_MMR6: {
9766 switch (OpNum) {
9767 case 0:
9768 // op: ft
9769 return 21;
9770 case 1:
9771 // op: fs
9772 return 16;
9773 }
9774 break;
9775 }
9776 case Mips::JRADDIUSP: {
9777 switch (OpNum) {
9778 case 0:
9779 // op: imm
9780 return 0;
9781 }
9782 break;
9783 }
9784 case Mips::ADDIUSP_MM: {
9785 switch (OpNum) {
9786 case 0:
9787 // op: imm
9788 return 1;
9789 }
9790 break;
9791 }
9792 case Mips::JRCADDIUSP_MMR6: {
9793 switch (OpNum) {
9794 case 0:
9795 // op: imm
9796 return 5;
9797 }
9798 break;
9799 }
9800 case Mips::Bimm16: {
9801 switch (OpNum) {
9802 case 0:
9803 // op: imm11
9804 return 0;
9805 }
9806 break;
9807 }
9808 case Mips::AddiuSpImmX16:
9809 case Mips::BimmX16:
9810 case Mips::BteqzX16:
9811 case Mips::BtnezX16: {
9812 switch (OpNum) {
9813 case 0:
9814 // op: imm16
9815 return 0;
9816 }
9817 break;
9818 }
9819 case Mips::Jal16:
9820 case Mips::JalB16: {
9821 switch (OpNum) {
9822 case 0:
9823 // op: imm26
9824 return 0;
9825 }
9826 break;
9827 }
9828 case Mips::AddiuSpImm16:
9829 case Mips::Bteqz16:
9830 case Mips::Btnez16: {
9831 switch (OpNum) {
9832 case 0:
9833 // op: imm8
9834 return 0;
9835 }
9836 break;
9837 }
9838 case Mips::B16_MM:
9839 case Mips::BAL:
9840 case Mips::BALC:
9841 case Mips::BALC_MMR6:
9842 case Mips::BC:
9843 case Mips::BC16_MMR6:
9844 case Mips::BC_MMR6:
9845 case Mips::BPOSGE32:
9846 case Mips::BPOSGE32C_MMR3:
9847 case Mips::BPOSGE32_MM: {
9848 switch (OpNum) {
9849 case 0:
9850 // op: offset
9851 return 0;
9852 }
9853 break;
9854 }
9855 case Mips::Move32R16: {
9856 switch (OpNum) {
9857 case 0:
9858 // op: r32
9859 return 3;
9860 case 1:
9861 // op: rz
9862 return 0;
9863 }
9864 break;
9865 }
9866 case Mips::MFHI16_MM:
9867 case Mips::MFLO16_MM: {
9868 switch (OpNum) {
9869 case 0:
9870 // op: rd
9871 return 0;
9872 }
9873 break;
9874 }
9875 case Mips::MFHI_DSP:
9876 case Mips::MFLO_DSP: {
9877 switch (OpNum) {
9878 case 0:
9879 // op: rd
9880 return 11;
9881 case 1:
9882 // op: ac
9883 return 21;
9884 }
9885 break;
9886 }
9887 case Mips::LWXS_MM: {
9888 switch (OpNum) {
9889 case 0:
9890 // op: rd
9891 return 11;
9892 case 1:
9893 // op: base
9894 return 16;
9895 case 2:
9896 // op: index
9897 return 21;
9898 }
9899 break;
9900 }
9901 case Mips::LBUX:
9902 case Mips::LHX:
9903 case Mips::LWX: {
9904 switch (OpNum) {
9905 case 0:
9906 // op: rd
9907 return 11;
9908 case 1:
9909 // op: base
9910 return 21;
9911 case 2:
9912 // op: index
9913 return 16;
9914 }
9915 break;
9916 }
9917 case Mips::REPL_PH:
9918 case Mips::REPL_PH_MM:
9919 case Mips::REPL_QB: {
9920 switch (OpNum) {
9921 case 0:
9922 // op: rd
9923 return 11;
9924 case 1:
9925 // op: imm
9926 return 16;
9927 }
9928 break;
9929 }
9930 case Mips::RDDSP: {
9931 switch (OpNum) {
9932 case 0:
9933 // op: rd
9934 return 11;
9935 case 1:
9936 // op: mask
9937 return 16;
9938 }
9939 break;
9940 }
9941 case Mips::LSA_MMR6: {
9942 switch (OpNum) {
9943 case 0:
9944 // op: rd
9945 return 11;
9946 case 1:
9947 // op: rs
9948 return 16;
9949 case 2:
9950 // op: rt
9951 return 21;
9952 case 3:
9953 // op: imm2
9954 return 9;
9955 }
9956 break;
9957 }
9958 case Mips::ADDQH_PH_MMR2:
9959 case Mips::ADDQH_R_PH_MMR2:
9960 case Mips::ADDQH_R_W_MMR2:
9961 case Mips::ADDQH_W_MMR2:
9962 case Mips::ADDQ_PH_MM:
9963 case Mips::ADDQ_S_PH_MM:
9964 case Mips::ADDQ_S_W_MM:
9965 case Mips::ADDSC_MM:
9966 case Mips::ADDUH_QB_MMR2:
9967 case Mips::ADDUH_R_QB_MMR2:
9968 case Mips::ADDU_PH_MMR2:
9969 case Mips::ADDU_QB_MM:
9970 case Mips::ADDU_S_PH_MMR2:
9971 case Mips::ADDU_S_QB_MM:
9972 case Mips::ADDWC_MM:
9973 case Mips::CMPGDU_EQ_QB_MMR2:
9974 case Mips::CMPGDU_LE_QB_MMR2:
9975 case Mips::CMPGDU_LT_QB_MMR2:
9976 case Mips::MODSUB_MM:
9977 case Mips::MULEQ_S_W_PHL_MM:
9978 case Mips::MULEQ_S_W_PHR_MM:
9979 case Mips::MULEU_S_PH_QBL_MM:
9980 case Mips::MULEU_S_PH_QBR_MM:
9981 case Mips::MULQ_RS_PH_MM:
9982 case Mips::MULQ_RS_W_MMR2:
9983 case Mips::MULQ_S_PH_MMR2:
9984 case Mips::MULQ_S_W_MMR2:
9985 case Mips::MUL_PH_MMR2:
9986 case Mips::MUL_S_PH_MMR2:
9987 case Mips::PACKRL_PH_MM:
9988 case Mips::PICK_PH_MM:
9989 case Mips::PICK_QB_MM:
9990 case Mips::PRECRQU_S_QB_PH_MM:
9991 case Mips::PRECRQ_PH_W_MM:
9992 case Mips::PRECRQ_QB_PH_MM:
9993 case Mips::PRECRQ_RS_PH_W_MM:
9994 case Mips::PRECR_QB_PH_MMR2:
9995 case Mips::SELEQZ_MMR6:
9996 case Mips::SELNEZ_MMR6:
9997 case Mips::SUBQH_PH_MMR2:
9998 case Mips::SUBQH_R_PH_MMR2:
9999 case Mips::SUBQH_R_W_MMR2:
10000 case Mips::SUBQH_W_MMR2:
10001 case Mips::SUBQ_PH_MM:
10002 case Mips::SUBQ_S_PH_MM:
10003 case Mips::SUBQ_S_W_MM:
10004 case Mips::SUBUH_QB_MMR2:
10005 case Mips::SUBUH_R_QB_MMR2:
10006 case Mips::SUBU_PH_MMR2:
10007 case Mips::SUBU_QB_MM:
10008 case Mips::SUBU_S_PH_MMR2:
10009 case Mips::SUBU_S_QB_MM: {
10010 switch (OpNum) {
10011 case 0:
10012 // op: rd
10013 return 11;
10014 case 1:
10015 // op: rs
10016 return 16;
10017 case 2:
10018 // op: rt
10019 return 21;
10020 }
10021 break;
10022 }
10023 case Mips::MOVF_I:
10024 case Mips::MOVF_I64:
10025 case Mips::MOVT_I:
10026 case Mips::MOVT_I64: {
10027 switch (OpNum) {
10028 case 0:
10029 // op: rd
10030 return 11;
10031 case 1:
10032 // op: rs
10033 return 21;
10034 case 2:
10035 // op: fcc
10036 return 18;
10037 }
10038 break;
10039 }
10040 case Mips::ALIGN:
10041 case Mips::DALIGN: {
10042 switch (OpNum) {
10043 case 0:
10044 // op: rd
10045 return 11;
10046 case 1:
10047 // op: rs
10048 return 21;
10049 case 2:
10050 // op: rt
10051 return 16;
10052 case 3:
10053 // op: bp
10054 return 6;
10055 }
10056 break;
10057 }
10058 case Mips::ALIGN_MMR6: {
10059 switch (OpNum) {
10060 case 0:
10061 // op: rd
10062 return 11;
10063 case 1:
10064 // op: rs
10065 return 21;
10066 case 2:
10067 // op: rt
10068 return 16;
10069 case 3:
10070 // op: bp
10071 return 9;
10072 }
10073 break;
10074 }
10075 case Mips::DLSA_R6:
10076 case Mips::LSA_R6: {
10077 switch (OpNum) {
10078 case 0:
10079 // op: rd
10080 return 11;
10081 case 1:
10082 // op: rs
10083 return 21;
10084 case 2:
10085 // op: rt
10086 return 16;
10087 case 3:
10088 // op: imm2
10089 return 6;
10090 }
10091 break;
10092 }
10093 case Mips::ADD:
10094 case Mips::ADDQH_PH:
10095 case Mips::ADDQH_R_PH:
10096 case Mips::ADDQH_R_W:
10097 case Mips::ADDQH_W:
10098 case Mips::ADDQ_PH:
10099 case Mips::ADDQ_S_PH:
10100 case Mips::ADDQ_S_W:
10101 case Mips::ADDSC:
10102 case Mips::ADDUH_QB:
10103 case Mips::ADDUH_R_QB:
10104 case Mips::ADDU_PH:
10105 case Mips::ADDU_QB:
10106 case Mips::ADDU_S_PH:
10107 case Mips::ADDU_S_QB:
10108 case Mips::ADDWC:
10109 case Mips::ADDu:
10110 case Mips::AND:
10111 case Mips::AND64:
10112 case Mips::BADDu:
10113 case Mips::DADD:
10114 case Mips::DADDu:
10115 case Mips::DDIV:
10116 case Mips::DDIVU:
10117 case Mips::DIV:
10118 case Mips::DIVU:
10119 case Mips::DMOD:
10120 case Mips::DMODU:
10121 case Mips::DMUH:
10122 case Mips::DMUHU:
10123 case Mips::DMUL:
10124 case Mips::DMULU:
10125 case Mips::DMUL_R6:
10126 case Mips::DSUB:
10127 case Mips::DSUBu:
10128 case Mips::MOD:
10129 case Mips::MODSUB:
10130 case Mips::MODU:
10131 case Mips::MOVN_I64_I:
10132 case Mips::MOVN_I64_I64:
10133 case Mips::MOVN_I_I:
10134 case Mips::MOVN_I_I64:
10135 case Mips::MOVZ_I64_I:
10136 case Mips::MOVZ_I64_I64:
10137 case Mips::MOVZ_I_I:
10138 case Mips::MOVZ_I_I64:
10139 case Mips::MUH:
10140 case Mips::MUHU:
10141 case Mips::MUL:
10142 case Mips::MULEQ_S_W_PHL:
10143 case Mips::MULEQ_S_W_PHR:
10144 case Mips::MULEU_S_PH_QBL:
10145 case Mips::MULEU_S_PH_QBR:
10146 case Mips::MULQ_RS_PH:
10147 case Mips::MULQ_RS_W:
10148 case Mips::MULQ_S_PH:
10149 case Mips::MULQ_S_W:
10150 case Mips::MULU:
10151 case Mips::MUL_PH:
10152 case Mips::MUL_R6:
10153 case Mips::MUL_S_PH:
10154 case Mips::NOR:
10155 case Mips::NOR64:
10156 case Mips::OR:
10157 case Mips::OR64:
10158 case Mips::SELEQZ:
10159 case Mips::SELEQZ64:
10160 case Mips::SELNEZ:
10161 case Mips::SELNEZ64:
10162 case Mips::SEQ:
10163 case Mips::SLT:
10164 case Mips::SLT64:
10165 case Mips::SLTu:
10166 case Mips::SLTu64:
10167 case Mips::SNE:
10168 case Mips::SUB:
10169 case Mips::SUBQH_PH:
10170 case Mips::SUBQH_R_PH:
10171 case Mips::SUBQH_R_W:
10172 case Mips::SUBQH_W:
10173 case Mips::SUBQ_PH:
10174 case Mips::SUBQ_S_PH:
10175 case Mips::SUBQ_S_W:
10176 case Mips::SUBUH_QB:
10177 case Mips::SUBUH_R_QB:
10178 case Mips::SUBU_PH:
10179 case Mips::SUBU_QB:
10180 case Mips::SUBU_S_PH:
10181 case Mips::SUBU_S_QB:
10182 case Mips::SUBu:
10183 case Mips::V3MULU:
10184 case Mips::VMM0:
10185 case Mips::VMULU:
10186 case Mips::XOR:
10187 case Mips::XOR64: {
10188 switch (OpNum) {
10189 case 0:
10190 // op: rd
10191 return 11;
10192 case 1:
10193 // op: rs
10194 return 21;
10195 case 2:
10196 // op: rt
10197 return 16;
10198 }
10199 break;
10200 }
10201 case Mips::CLO:
10202 case Mips::CLO_R6:
10203 case Mips::CLZ:
10204 case Mips::CLZ_R6:
10205 case Mips::DCLO:
10206 case Mips::DCLO_R6:
10207 case Mips::DCLZ:
10208 case Mips::DCLZ_R6:
10209 case Mips::DPOP:
10210 case Mips::JALR:
10211 case Mips::JALR64:
10212 case Mips::JALR_HB:
10213 case Mips::JALR_HB64:
10214 case Mips::POP:
10215 case Mips::RADDU_W_QB: {
10216 switch (OpNum) {
10217 case 0:
10218 // op: rd
10219 return 11;
10220 case 1:
10221 // op: rs
10222 return 21;
10223 }
10224 break;
10225 }
10226 case Mips::DROTRV:
10227 case Mips::DSLLV:
10228 case Mips::DSRAV:
10229 case Mips::DSRLV:
10230 case Mips::ROTRV:
10231 case Mips::SLLV:
10232 case Mips::SRAV:
10233 case Mips::SRLV: {
10234 switch (OpNum) {
10235 case 0:
10236 // op: rd
10237 return 11;
10238 case 1:
10239 // op: rt
10240 return 16;
10241 case 2:
10242 // op: rs
10243 return 21;
10244 }
10245 break;
10246 }
10247 case Mips::SHLLV_PH:
10248 case Mips::SHLLV_QB:
10249 case Mips::SHLLV_S_PH:
10250 case Mips::SHLLV_S_W:
10251 case Mips::SHLL_PH:
10252 case Mips::SHLL_QB:
10253 case Mips::SHLL_S_PH:
10254 case Mips::SHLL_S_W:
10255 case Mips::SHRAV_PH:
10256 case Mips::SHRAV_QB:
10257 case Mips::SHRAV_R_PH:
10258 case Mips::SHRAV_R_QB:
10259 case Mips::SHRAV_R_W:
10260 case Mips::SHRA_PH:
10261 case Mips::SHRA_QB:
10262 case Mips::SHRA_R_PH:
10263 case Mips::SHRA_R_QB:
10264 case Mips::SHRA_R_W:
10265 case Mips::SHRLV_PH:
10266 case Mips::SHRLV_QB:
10267 case Mips::SHRL_PH:
10268 case Mips::SHRL_QB: {
10269 switch (OpNum) {
10270 case 0:
10271 // op: rd
10272 return 11;
10273 case 1:
10274 // op: rt
10275 return 16;
10276 case 2:
10277 // op: rs_sa
10278 return 21;
10279 }
10280 break;
10281 }
10282 case Mips::DROTR:
10283 case Mips::DROTR32:
10284 case Mips::DSLL:
10285 case Mips::DSLL32:
10286 case Mips::DSRA:
10287 case Mips::DSRA32:
10288 case Mips::DSRL:
10289 case Mips::DSRL32:
10290 case Mips::ROTR:
10291 case Mips::SLL:
10292 case Mips::SRA:
10293 case Mips::SRL: {
10294 switch (OpNum) {
10295 case 0:
10296 // op: rd
10297 return 11;
10298 case 1:
10299 // op: rt
10300 return 16;
10301 case 2:
10302 // op: shamt
10303 return 6;
10304 }
10305 break;
10306 }
10307 case Mips::ABSQ_S_PH:
10308 case Mips::ABSQ_S_QB:
10309 case Mips::ABSQ_S_W:
10310 case Mips::BITREV:
10311 case Mips::BITSWAP:
10312 case Mips::DBITSWAP:
10313 case Mips::DSBH:
10314 case Mips::DSHD:
10315 case Mips::DSLL64_32:
10316 case Mips::PRECEQU_PH_QBL:
10317 case Mips::PRECEQU_PH_QBLA:
10318 case Mips::PRECEQU_PH_QBR:
10319 case Mips::PRECEQU_PH_QBRA:
10320 case Mips::PRECEQ_W_PHL:
10321 case Mips::PRECEQ_W_PHR:
10322 case Mips::PRECEU_PH_QBL:
10323 case Mips::PRECEU_PH_QBLA:
10324 case Mips::PRECEU_PH_QBR:
10325 case Mips::PRECEU_PH_QBRA:
10326 case Mips::REPLV_PH:
10327 case Mips::REPLV_QB:
10328 case Mips::SEB:
10329 case Mips::SEB64:
10330 case Mips::SEH:
10331 case Mips::SEH64:
10332 case Mips::SLL64_32:
10333 case Mips::SLL64_64:
10334 case Mips::WSBH: {
10335 switch (OpNum) {
10336 case 0:
10337 // op: rd
10338 return 11;
10339 case 1:
10340 // op: rt
10341 return 16;
10342 }
10343 break;
10344 }
10345 case Mips::ROTRV_MM:
10346 case Mips::SLLV_MM:
10347 case Mips::SRAV_MM:
10348 case Mips::SRLV_MM: {
10349 switch (OpNum) {
10350 case 0:
10351 // op: rd
10352 return 11;
10353 case 1:
10354 // op: rt
10355 return 21;
10356 case 2:
10357 // op: rs
10358 return 16;
10359 }
10360 break;
10361 }
10362 case Mips::SHLLV_PH_MM:
10363 case Mips::SHLLV_QB_MM:
10364 case Mips::SHLLV_S_PH_MM:
10365 case Mips::SHLLV_S_W_MM:
10366 case Mips::SHRAV_PH_MM:
10367 case Mips::SHRAV_QB_MMR2:
10368 case Mips::SHRAV_R_PH_MM:
10369 case Mips::SHRAV_R_QB_MMR2:
10370 case Mips::SHRAV_R_W_MM:
10371 case Mips::SHRLV_PH_MMR2:
10372 case Mips::SHRLV_QB_MM: {
10373 switch (OpNum) {
10374 case 0:
10375 // op: rd
10376 return 11;
10377 case 2:
10378 // op: rs
10379 return 16;
10380 case 1:
10381 // op: rt
10382 return 21;
10383 }
10384 break;
10385 }
10386 case Mips::ADDU_MMR6:
10387 case Mips::ADD_MMR6:
10388 case Mips::AND_MMR6:
10389 case Mips::DIVU_MMR6:
10390 case Mips::DIV_MMR6:
10391 case Mips::MODU_MMR6:
10392 case Mips::MOD_MMR6:
10393 case Mips::MUHU_MMR6:
10394 case Mips::MUH_MMR6:
10395 case Mips::MULU_MMR6:
10396 case Mips::MUL_MMR6:
10397 case Mips::NOR_MMR6:
10398 case Mips::OR_MMR6:
10399 case Mips::SUBU_MMR6:
10400 case Mips::SUB_MMR6:
10401 case Mips::XOR_MMR6: {
10402 switch (OpNum) {
10403 case 0:
10404 // op: rd
10405 return 11;
10406 case 2:
10407 // op: rt
10408 return 21;
10409 case 1:
10410 // op: rs
10411 return 16;
10412 }
10413 break;
10414 }
10415 case Mips::MFHI:
10416 case Mips::MFHI64:
10417 case Mips::MFLO:
10418 case Mips::MFLO64: {
10419 switch (OpNum) {
10420 case 0:
10421 // op: rd
10422 return 11;
10423 }
10424 break;
10425 }
10426 case Mips::BITSWAP_MMR6: {
10427 switch (OpNum) {
10428 case 0:
10429 // op: rd
10430 return 16;
10431 case 1:
10432 // op: rt
10433 return 21;
10434 }
10435 break;
10436 }
10437 case Mips::MFHI_MM:
10438 case Mips::MFLO_MM: {
10439 switch (OpNum) {
10440 case 0:
10441 // op: rd
10442 return 16;
10443 }
10444 break;
10445 }
10446 case Mips::MOVF_I_MM:
10447 case Mips::MOVT_I_MM: {
10448 switch (OpNum) {
10449 case 0:
10450 // op: rd
10451 return 21;
10452 case 1:
10453 // op: rs
10454 return 16;
10455 case 2:
10456 // op: fcc
10457 return 13;
10458 }
10459 break;
10460 }
10461 case Mips::CLO_MM:
10462 case Mips::CLZ_MM: {
10463 switch (OpNum) {
10464 case 0:
10465 // op: rd
10466 return 21;
10467 case 1:
10468 // op: rs
10469 return 16;
10470 }
10471 break;
10472 }
10473 case Mips::ROTR_MM:
10474 case Mips::SLL_MM:
10475 case Mips::SLL_MMR6:
10476 case Mips::SRA_MM:
10477 case Mips::SRL_MM: {
10478 switch (OpNum) {
10479 case 0:
10480 // op: rd
10481 return 21;
10482 case 1:
10483 // op: rt
10484 return 16;
10485 case 2:
10486 // op: shamt
10487 return 11;
10488 }
10489 break;
10490 }
10491 case Mips::SEB_MM:
10492 case Mips::SEH_MM:
10493 case Mips::WSBH_MM: {
10494 switch (OpNum) {
10495 case 0:
10496 // op: rd
10497 return 21;
10498 case 1:
10499 // op: rt
10500 return 16;
10501 }
10502 break;
10503 }
10504 case Mips::CFCMSA: {
10505 switch (OpNum) {
10506 case 0:
10507 // op: rd
10508 return 6;
10509 case 1:
10510 // op: cs
10511 return 11;
10512 }
10513 break;
10514 }
10515 case Mips::LI16_MM:
10516 case Mips::LI16_MMR6: {
10517 switch (OpNum) {
10518 case 0:
10519 // op: rd
10520 return 7;
10521 case 1:
10522 // op: imm
10523 return 0;
10524 }
10525 break;
10526 }
10527 case Mips::ADDIUR1SP_MM: {
10528 switch (OpNum) {
10529 case 0:
10530 // op: rd
10531 return 7;
10532 case 1:
10533 // op: imm
10534 return 1;
10535 }
10536 break;
10537 }
10538 case Mips::ANDI16_MM:
10539 case Mips::ANDI16_MMR6: {
10540 switch (OpNum) {
10541 case 0:
10542 // op: rd
10543 return 7;
10544 case 1:
10545 // op: rs
10546 return 4;
10547 case 2:
10548 // op: imm
10549 return 0;
10550 }
10551 break;
10552 }
10553 case Mips::ADDIUR2_MM: {
10554 switch (OpNum) {
10555 case 0:
10556 // op: rd
10557 return 7;
10558 case 1:
10559 // op: rs
10560 return 4;
10561 case 2:
10562 // op: imm
10563 return 1;
10564 }
10565 break;
10566 }
10567 case Mips::SLL16_MM:
10568 case Mips::SLL16_MMR6:
10569 case Mips::SRL16_MM:
10570 case Mips::SRL16_MMR6: {
10571 switch (OpNum) {
10572 case 0:
10573 // op: rd
10574 return 7;
10575 case 1:
10576 // op: rt
10577 return 4;
10578 case 2:
10579 // op: shamt
10580 return 1;
10581 }
10582 break;
10583 }
10584 case Mips::ADDU16_MM:
10585 case Mips::SUBU16_MM: {
10586 switch (OpNum) {
10587 case 0:
10588 // op: rd
10589 return 7;
10590 case 2:
10591 // op: rt
10592 return 4;
10593 case 1:
10594 // op: rs
10595 return 1;
10596 }
10597 break;
10598 }
10599 case Mips::JALR16_MM:
10600 case Mips::JALRS16_MM:
10601 case Mips::JR16_MM:
10602 case Mips::JRC16_MM: {
10603 switch (OpNum) {
10604 case 0:
10605 // op: rs
10606 return 0;
10607 }
10608 break;
10609 }
10610 case Mips::MFHI_DSP_MM:
10611 case Mips::MFLO_DSP_MM: {
10612 switch (OpNum) {
10613 case 0:
10614 // op: rs
10615 return 16;
10616 case 1:
10617 // op: ac
10618 return 14;
10619 }
10620 break;
10621 }
10622 case Mips::TEQI_MM:
10623 case Mips::TGEIU_MM:
10624 case Mips::TGEI_MM:
10625 case Mips::TLTIU_MM:
10626 case Mips::TLTI_MM:
10627 case Mips::TNEI_MM: {
10628 switch (OpNum) {
10629 case 0:
10630 // op: rs
10631 return 16;
10632 case 1:
10633 // op: imm16
10634 return 0;
10635 }
10636 break;
10637 }
10638 case Mips::BEQZC_MM:
10639 case Mips::BGEZALS_MM:
10640 case Mips::BGEZAL_MM:
10641 case Mips::BGEZ_MM:
10642 case Mips::BGTZ_MM:
10643 case Mips::BLEZ_MM:
10644 case Mips::BLTZALS_MM:
10645 case Mips::BLTZAL_MM:
10646 case Mips::BLTZ_MM:
10647 case Mips::BNEZC_MM: {
10648 switch (OpNum) {
10649 case 0:
10650 // op: rs
10651 return 16;
10652 case 1:
10653 // op: offset
10654 return 0;
10655 }
10656 break;
10657 }
10658 case Mips::TEQ_MM:
10659 case Mips::TGEU_MM:
10660 case Mips::TGE_MM:
10661 case Mips::TLTU_MM:
10662 case Mips::TLT_MM:
10663 case Mips::TNE_MM: {
10664 switch (OpNum) {
10665 case 0:
10666 // op: rs
10667 return 16;
10668 case 1:
10669 // op: rt
10670 return 21;
10671 case 2:
10672 // op: code_
10673 return 12;
10674 }
10675 break;
10676 }
10677 case Mips::BEQ_MM:
10678 case Mips::BNE_MM: {
10679 switch (OpNum) {
10680 case 0:
10681 // op: rs
10682 return 16;
10683 case 1:
10684 // op: rt
10685 return 21;
10686 case 2:
10687 // op: offset
10688 return 0;
10689 }
10690 break;
10691 }
10692 case Mips::MADDU_MM:
10693 case Mips::MADD_MM:
10694 case Mips::MSUBU_MM:
10695 case Mips::MSUB_MM:
10696 case Mips::MULT_MM:
10697 case Mips::MULTu_MM:
10698 case Mips::SDIV_MM:
10699 case Mips::UDIV_MM: {
10700 switch (OpNum) {
10701 case 0:
10702 // op: rs
10703 return 16;
10704 case 1:
10705 // op: rt
10706 return 21;
10707 }
10708 break;
10709 }
10710 case Mips::GINVT_MMR6: {
10711 switch (OpNum) {
10712 case 0:
10713 // op: rs
10714 return 16;
10715 case 1:
10716 // op: type
10717 return 9;
10718 }
10719 break;
10720 }
10721 case Mips::DVP_MMR6:
10722 case Mips::EVP_MMR6:
10723 case Mips::GINVI_MMR6:
10724 case Mips::JR_MM:
10725 case Mips::MTHI_MM:
10726 case Mips::MTLO_MM: {
10727 switch (OpNum) {
10728 case 0:
10729 // op: rs
10730 return 16;
10731 }
10732 break;
10733 }
10734 case Mips::ADDIUPC:
10735 case Mips::ALUIPC:
10736 case Mips::AUIPC:
10737 case Mips::LDPC:
10738 case Mips::LWPC:
10739 case Mips::LWUPC: {
10740 switch (OpNum) {
10741 case 0:
10742 // op: rs
10743 return 21;
10744 case 1:
10745 // op: imm
10746 return 0;
10747 }
10748 break;
10749 }
10750 case Mips::TEQI:
10751 case Mips::TGEI:
10752 case Mips::TGEIU:
10753 case Mips::TLTI:
10754 case Mips::TNEI:
10755 case Mips::TTLTIU: {
10756 switch (OpNum) {
10757 case 0:
10758 // op: rs
10759 return 21;
10760 case 1:
10761 // op: imm16
10762 return 0;
10763 }
10764 break;
10765 }
10766 case Mips::WRDSP: {
10767 switch (OpNum) {
10768 case 0:
10769 // op: rs
10770 return 21;
10771 case 1:
10772 // op: mask
10773 return 11;
10774 }
10775 break;
10776 }
10777 case Mips::BEQZC:
10778 case Mips::BEQZC64:
10779 case Mips::BEQZC_MMR6:
10780 case Mips::BGEZ:
10781 case Mips::BGEZ64:
10782 case Mips::BGEZAL:
10783 case Mips::BGEZALL:
10784 case Mips::BGEZL:
10785 case Mips::BGTZ:
10786 case Mips::BGTZ64:
10787 case Mips::BGTZL:
10788 case Mips::BLEZ:
10789 case Mips::BLEZ64:
10790 case Mips::BLEZL:
10791 case Mips::BLTZ:
10792 case Mips::BLTZ64:
10793 case Mips::BLTZAL:
10794 case Mips::BLTZALL:
10795 case Mips::BLTZL:
10796 case Mips::BNEZC:
10797 case Mips::BNEZC64:
10798 case Mips::BNEZC_MMR6: {
10799 switch (OpNum) {
10800 case 0:
10801 // op: rs
10802 return 21;
10803 case 1:
10804 // op: offset
10805 return 0;
10806 }
10807 break;
10808 }
10809 case Mips::BBIT0:
10810 case Mips::BBIT1:
10811 case Mips::BBIT032:
10812 case Mips::BBIT132: {
10813 switch (OpNum) {
10814 case 0:
10815 // op: rs
10816 return 21;
10817 case 1:
10818 // op: p
10819 return 16;
10820 case 2:
10821 // op: offset
10822 return 0;
10823 }
10824 break;
10825 }
10826 case Mips::TEQ:
10827 case Mips::TGE:
10828 case Mips::TGEU:
10829 case Mips::TLT:
10830 case Mips::TLTU:
10831 case Mips::TNE: {
10832 switch (OpNum) {
10833 case 0:
10834 // op: rs
10835 return 21;
10836 case 1:
10837 // op: rt
10838 return 16;
10839 case 2:
10840 // op: code_
10841 return 6;
10842 }
10843 break;
10844 }
10845 case Mips::BEQ:
10846 case Mips::BEQ64:
10847 case Mips::BEQC:
10848 case Mips::BEQC64:
10849 case Mips::BEQL:
10850 case Mips::BGEC:
10851 case Mips::BGEC64:
10852 case Mips::BGEUC:
10853 case Mips::BGEUC64:
10854 case Mips::BLTC:
10855 case Mips::BLTC64:
10856 case Mips::BLTUC:
10857 case Mips::BLTUC64:
10858 case Mips::BNE:
10859 case Mips::BNE64:
10860 case Mips::BNEC:
10861 case Mips::BNEC64:
10862 case Mips::BNEL:
10863 case Mips::BNVC:
10864 case Mips::BOVC: {
10865 switch (OpNum) {
10866 case 0:
10867 // op: rs
10868 return 21;
10869 case 1:
10870 // op: rt
10871 return 16;
10872 case 2:
10873 // op: offset
10874 return 0;
10875 }
10876 break;
10877 }
10878 case Mips::CMPU_EQ_QB:
10879 case Mips::CMPU_LE_QB:
10880 case Mips::CMPU_LT_QB:
10881 case Mips::CMP_EQ_PH:
10882 case Mips::CMP_LE_PH:
10883 case Mips::CMP_LT_PH:
10884 case Mips::DMULT:
10885 case Mips::DMULTu:
10886 case Mips::DSDIV:
10887 case Mips::DUDIV:
10888 case Mips::MADD:
10889 case Mips::MADDU:
10890 case Mips::MSUB:
10891 case Mips::MSUBU:
10892 case Mips::MULT:
10893 case Mips::MULTu:
10894 case Mips::SDIV:
10895 case Mips::UDIV: {
10896 switch (OpNum) {
10897 case 0:
10898 // op: rs
10899 return 21;
10900 case 1:
10901 // op: rt
10902 return 16;
10903 }
10904 break;
10905 }
10906 case Mips::GINVT: {
10907 switch (OpNum) {
10908 case 0:
10909 // op: rs
10910 return 21;
10911 case 1:
10912 // op: type_
10913 return 8;
10914 }
10915 break;
10916 }
10917 case Mips::DAHI:
10918 case Mips::DATI: {
10919 switch (OpNum) {
10920 case 0:
10921 // op: rs
10922 return 21;
10923 case 2:
10924 // op: imm
10925 return 0;
10926 }
10927 break;
10928 }
10929 case Mips::FORK: {
10930 switch (OpNum) {
10931 case 0:
10932 // op: rs
10933 return 21;
10934 case 2:
10935 // op: rt
10936 return 16;
10937 case 1:
10938 // op: rd
10939 return 11;
10940 }
10941 break;
10942 }
10943 case Mips::GINVI:
10944 case Mips::JR:
10945 case Mips::JR64:
10946 case Mips::JR_HB:
10947 case Mips::JR_HB64:
10948 case Mips::JR_HB64_R6:
10949 case Mips::JR_HB_R6:
10950 case Mips::MTHI:
10951 case Mips::MTHI64:
10952 case Mips::MTLO:
10953 case Mips::MTLO64:
10954 case Mips::MTM0:
10955 case Mips::MTM1:
10956 case Mips::MTM2:
10957 case Mips::MTP0:
10958 case Mips::MTP1:
10959 case Mips::MTP2: {
10960 switch (OpNum) {
10961 case 0:
10962 // op: rs
10963 return 21;
10964 }
10965 break;
10966 }
10967 case Mips::ADDIUPC_MM: {
10968 switch (OpNum) {
10969 case 0:
10970 // op: rs
10971 return 23;
10972 case 1:
10973 // op: imm
10974 return 0;
10975 }
10976 break;
10977 }
10978 case Mips::JALRC16_MMR6:
10979 case Mips::JRC16_MMR6: {
10980 switch (OpNum) {
10981 case 0:
10982 // op: rs
10983 return 5;
10984 }
10985 break;
10986 }
10987 case Mips::BEQZ16_MM:
10988 case Mips::BEQZC16_MMR6:
10989 case Mips::BNEZ16_MM:
10990 case Mips::BNEZC16_MMR6: {
10991 switch (OpNum) {
10992 case 0:
10993 // op: rs
10994 return 7;
10995 case 1:
10996 // op: offset
10997 return 0;
10998 }
10999 break;
11000 }
11001 case Mips::EXTP:
11002 case Mips::EXTPDP:
11003 case Mips::EXTPDPV:
11004 case Mips::EXTPV:
11005 case Mips::EXTRV_RS_W:
11006 case Mips::EXTRV_R_W:
11007 case Mips::EXTRV_S_H:
11008 case Mips::EXTRV_W:
11009 case Mips::EXTR_RS_W:
11010 case Mips::EXTR_R_W:
11011 case Mips::EXTR_S_H:
11012 case Mips::EXTR_W: {
11013 switch (OpNum) {
11014 case 0:
11015 // op: rt
11016 return 16;
11017 case 1:
11018 // op: ac
11019 return 11;
11020 case 2:
11021 // op: shift_rs
11022 return 21;
11023 }
11024 break;
11025 }
11026 case Mips::LB:
11027 case Mips::LB64:
11028 case Mips::LBu:
11029 case Mips::LBu64:
11030 case Mips::LD:
11031 case Mips::LDC1:
11032 case Mips::LDC2:
11033 case Mips::LDC2_R6:
11034 case Mips::LDC3:
11035 case Mips::LDC164:
11036 case Mips::LDL:
11037 case Mips::LDR:
11038 case Mips::LEA_ADDiu:
11039 case Mips::LEA_ADDiu64:
11040 case Mips::LH:
11041 case Mips::LH64:
11042 case Mips::LHu:
11043 case Mips::LHu64:
11044 case Mips::LL:
11045 case Mips::LL64:
11046 case Mips::LLD:
11047 case Mips::LW:
11048 case Mips::LW64:
11049 case Mips::LWC1:
11050 case Mips::LWC2:
11051 case Mips::LWC2_R6:
11052 case Mips::LWC3:
11053 case Mips::LWDSP:
11054 case Mips::LWL:
11055 case Mips::LWL64:
11056 case Mips::LWR:
11057 case Mips::LWR64:
11058 case Mips::LWu:
11059 case Mips::SB:
11060 case Mips::SB64:
11061 case Mips::SD:
11062 case Mips::SDC1:
11063 case Mips::SDC2:
11064 case Mips::SDC2_R6:
11065 case Mips::SDC3:
11066 case Mips::SDC164:
11067 case Mips::SDL:
11068 case Mips::SDR:
11069 case Mips::SH:
11070 case Mips::SH64:
11071 case Mips::SW:
11072 case Mips::SW64:
11073 case Mips::SWC1:
11074 case Mips::SWC2:
11075 case Mips::SWC2_R6:
11076 case Mips::SWC3:
11077 case Mips::SWDSP:
11078 case Mips::SWL:
11079 case Mips::SWL64:
11080 case Mips::SWR:
11081 case Mips::SWR64: {
11082 switch (OpNum) {
11083 case 0:
11084 // op: rt
11085 return 16;
11086 case 1:
11087 // op: addr
11088 return 0;
11089 }
11090 break;
11091 }
11092 case Mips::LL64_R6:
11093 case Mips::LLD_R6:
11094 case Mips::LL_R6: {
11095 switch (OpNum) {
11096 case 0:
11097 // op: rt
11098 return 16;
11099 case 1:
11100 // op: addr
11101 return 7;
11102 }
11103 break;
11104 }
11105 case Mips::CFC1:
11106 case Mips::DMFC1:
11107 case Mips::MFC1:
11108 case Mips::MFC1_D64:
11109 case Mips::MFHC1_D32:
11110 case Mips::MFHC1_D64: {
11111 switch (OpNum) {
11112 case 0:
11113 // op: rt
11114 return 16;
11115 case 1:
11116 // op: fs
11117 return 11;
11118 }
11119 break;
11120 }
11121 case Mips::DMFC2_OCTEON:
11122 case Mips::DMTC2_OCTEON:
11123 case Mips::LUi:
11124 case Mips::LUi64:
11125 case Mips::LUi_MM: {
11126 switch (OpNum) {
11127 case 0:
11128 // op: rt
11129 return 16;
11130 case 1:
11131 // op: imm16
11132 return 0;
11133 }
11134 break;
11135 }
11136 case Mips::BC1EQZC_MMR6:
11137 case Mips::BC1NEZC_MMR6:
11138 case Mips::BC2EQZC_MMR6:
11139 case Mips::BC2NEZC_MMR6:
11140 case Mips::BEQZALC:
11141 case Mips::BGEZALC:
11142 case Mips::BGEZALC_MMR6:
11143 case Mips::BGEZC:
11144 case Mips::BGEZC64:
11145 case Mips::BGEZC_MMR6:
11146 case Mips::BGTZALC:
11147 case Mips::BGTZC:
11148 case Mips::BGTZC64:
11149 case Mips::BLEZALC:
11150 case Mips::BLEZC:
11151 case Mips::BLEZC64:
11152 case Mips::BLTZALC:
11153 case Mips::BLTZALC_MMR6:
11154 case Mips::BLTZC:
11155 case Mips::BLTZC64:
11156 case Mips::BLTZC_MMR6:
11157 case Mips::BNEZALC:
11158 case Mips::JIALC:
11159 case Mips::JIALC64:
11160 case Mips::JIALC_MMR6:
11161 case Mips::JIC:
11162 case Mips::JIC64:
11163 case Mips::JIC_MMR6: {
11164 switch (OpNum) {
11165 case 0:
11166 // op: rt
11167 return 16;
11168 case 1:
11169 // op: offset
11170 return 0;
11171 }
11172 break;
11173 }
11174 case Mips::DMFC0:
11175 case Mips::DMFC2:
11176 case Mips::DMFGC0:
11177 case Mips::MFC0:
11178 case Mips::MFC2:
11179 case Mips::MFGC0:
11180 case Mips::MFHGC0: {
11181 switch (OpNum) {
11182 case 0:
11183 // op: rt
11184 return 16;
11185 case 1:
11186 // op: rd
11187 return 11;
11188 case 2:
11189 // op: sel
11190 return 0;
11191 }
11192 break;
11193 }
11194 case Mips::RDHWR:
11195 case Mips::RDHWR64: {
11196 switch (OpNum) {
11197 case 0:
11198 // op: rt
11199 return 16;
11200 case 1:
11201 // op: rd
11202 return 11;
11203 case 2:
11204 // op: sel
11205 return 6;
11206 }
11207 break;
11208 }
11209 case Mips::SLTi:
11210 case Mips::SLTi64:
11211 case Mips::SLTiu:
11212 case Mips::SLTiu64: {
11213 switch (OpNum) {
11214 case 0:
11215 // op: rt
11216 return 16;
11217 case 1:
11218 // op: rs
11219 return 21;
11220 case 2:
11221 // op: imm16
11222 return 0;
11223 }
11224 break;
11225 }
11226 case Mips::CINS:
11227 case Mips::CINS32:
11228 case Mips::CINS64_32:
11229 case Mips::CINS_i32:
11230 case Mips::EXTS:
11231 case Mips::EXTS32: {
11232 switch (OpNum) {
11233 case 0:
11234 // op: rt
11235 return 16;
11236 case 1:
11237 // op: rs
11238 return 21;
11239 case 2:
11240 // op: pos
11241 return 6;
11242 case 3:
11243 // op: lenm1
11244 return 11;
11245 }
11246 break;
11247 }
11248 case Mips::DEXT:
11249 case Mips::DEXT64_32:
11250 case Mips::DEXTM:
11251 case Mips::DEXTU:
11252 case Mips::DINS:
11253 case Mips::DINSM:
11254 case Mips::DINSU:
11255 case Mips::EXT:
11256 case Mips::INS: {
11257 switch (OpNum) {
11258 case 0:
11259 // op: rt
11260 return 16;
11261 case 1:
11262 // op: rs
11263 return 21;
11264 case 2:
11265 // op: pos
11266 return 6;
11267 case 3:
11268 // op: size
11269 return 11;
11270 }
11271 break;
11272 }
11273 case Mips::APPEND:
11274 case Mips::BALIGN:
11275 case Mips::PREPEND: {
11276 switch (OpNum) {
11277 case 0:
11278 // op: rt
11279 return 16;
11280 case 1:
11281 // op: rs
11282 return 21;
11283 case 2:
11284 // op: sa
11285 return 11;
11286 }
11287 break;
11288 }
11289 case Mips::SAA:
11290 case Mips::SAAD: {
11291 switch (OpNum) {
11292 case 0:
11293 // op: rt
11294 return 16;
11295 case 1:
11296 // op: rs
11297 return 21;
11298 }
11299 break;
11300 }
11301 case Mips::INSV: {
11302 switch (OpNum) {
11303 case 0:
11304 // op: rt
11305 return 16;
11306 case 2:
11307 // op: rs
11308 return 21;
11309 }
11310 break;
11311 }
11312 case Mips::DI:
11313 case Mips::DI_MM:
11314 case Mips::DI_MMR6:
11315 case Mips::DMT:
11316 case Mips::DVP:
11317 case Mips::DVPE:
11318 case Mips::EI:
11319 case Mips::EI_MM:
11320 case Mips::EI_MMR6:
11321 case Mips::EMT:
11322 case Mips::EVP:
11323 case Mips::EVPE: {
11324 switch (OpNum) {
11325 case 0:
11326 // op: rt
11327 return 16;
11328 }
11329 break;
11330 }
11331 case Mips::LBE_MM:
11332 case Mips::LB_MM:
11333 case Mips::LBuE_MM:
11334 case Mips::LBu_MM:
11335 case Mips::LDC1_MM_D32:
11336 case Mips::LDC1_MM_D64:
11337 case Mips::LDC2_MMR6:
11338 case Mips::LEA_ADDiu_MM:
11339 case Mips::LHE_MM:
11340 case Mips::LH_MM:
11341 case Mips::LHuE_MM:
11342 case Mips::LHu_MM:
11343 case Mips::LLE_MM:
11344 case Mips::LL_MM:
11345 case Mips::LL_MMR6:
11346 case Mips::LWC1_MM:
11347 case Mips::LWC2_MMR6:
11348 case Mips::LWDSP_MM:
11349 case Mips::LWE_MM:
11350 case Mips::LWLE_MM:
11351 case Mips::LWL_MM:
11352 case Mips::LWM32_MM:
11353 case Mips::LWRE_MM:
11354 case Mips::LWR_MM:
11355 case Mips::LWU_MM:
11356 case Mips::LW_MM:
11357 case Mips::LW_MMR6:
11358 case Mips::SBE_MM:
11359 case Mips::SB_MM:
11360 case Mips::SB_MMR6:
11361 case Mips::SDC1_MM_D32:
11362 case Mips::SDC1_MM_D64:
11363 case Mips::SDC2_MMR6:
11364 case Mips::SHE_MM:
11365 case Mips::SH_MM:
11366 case Mips::SH_MMR6:
11367 case Mips::SWC1_MM:
11368 case Mips::SWC2_MMR6:
11369 case Mips::SWDSP_MM:
11370 case Mips::SWE_MM:
11371 case Mips::SWLE_MM:
11372 case Mips::SWL_MM:
11373 case Mips::SWM32_MM:
11374 case Mips::SWRE_MM:
11375 case Mips::SWR_MM:
11376 case Mips::SW_MM:
11377 case Mips::SW_MMR6: {
11378 switch (OpNum) {
11379 case 0:
11380 // op: rt
11381 return 21;
11382 case 1:
11383 // op: addr
11384 return 0;
11385 }
11386 break;
11387 }
11388 case Mips::CFC1_MM:
11389 case Mips::MFC1_MM:
11390 case Mips::MFC1_MMR6:
11391 case Mips::MFHC1_D32_MM:
11392 case Mips::MFHC1_D64_MM: {
11393 switch (OpNum) {
11394 case 0:
11395 // op: rt
11396 return 21;
11397 case 1:
11398 // op: fs
11399 return 16;
11400 }
11401 break;
11402 }
11403 case Mips::ADDIUPC_MMR6:
11404 case Mips::ALUIPC_MMR6:
11405 case Mips::AUIPC_MMR6:
11406 case Mips::LWPC_MMR6: {
11407 switch (OpNum) {
11408 case 0:
11409 // op: rt
11410 return 21;
11411 case 1:
11412 // op: imm
11413 return 0;
11414 }
11415 break;
11416 }
11417 case Mips::REPL_QB_MM: {
11418 switch (OpNum) {
11419 case 0:
11420 // op: rt
11421 return 21;
11422 case 1:
11423 // op: imm
11424 return 13;
11425 }
11426 break;
11427 }
11428 case Mips::LUI_MMR6: {
11429 switch (OpNum) {
11430 case 0:
11431 // op: rt
11432 return 21;
11433 case 1:
11434 // op: imm16
11435 return 0;
11436 }
11437 break;
11438 }
11439 case Mips::CFC2_MM:
11440 case Mips::MFC2_MMR6:
11441 case Mips::MFHC2_MMR6: {
11442 switch (OpNum) {
11443 case 0:
11444 // op: rt
11445 return 21;
11446 case 1:
11447 // op: impl
11448 return 16;
11449 }
11450 break;
11451 }
11452 case Mips::RDDSP_MM:
11453 case Mips::WRDSP_MM: {
11454 switch (OpNum) {
11455 case 0:
11456 // op: rt
11457 return 21;
11458 case 1:
11459 // op: mask
11460 return 14;
11461 }
11462 break;
11463 }
11464 case Mips::BEQZALC_MMR6:
11465 case Mips::BGTZALC_MMR6:
11466 case Mips::BGTZC_MMR6:
11467 case Mips::BLEZALC_MMR6:
11468 case Mips::BLEZC_MMR6:
11469 case Mips::BNEZALC_MMR6: {
11470 switch (OpNum) {
11471 case 0:
11472 // op: rt
11473 return 21;
11474 case 1:
11475 // op: offset
11476 return 0;
11477 }
11478 break;
11479 }
11480 case Mips::RDHWR_MM:
11481 case Mips::RDPGPR_MMR6: {
11482 switch (OpNum) {
11483 case 0:
11484 // op: rt
11485 return 21;
11486 case 1:
11487 // op: rd
11488 return 16;
11489 }
11490 break;
11491 }
11492 case Mips::BALIGN_MMR2: {
11493 switch (OpNum) {
11494 case 0:
11495 // op: rt
11496 return 21;
11497 case 1:
11498 // op: rs
11499 return 16;
11500 case 2:
11501 // op: bp
11502 return 14;
11503 }
11504 break;
11505 }
11506 case Mips::ADDIU_MMR6:
11507 case Mips::ANDI_MMR6:
11508 case Mips::ORI_MMR6:
11509 case Mips::SLTi_MM:
11510 case Mips::SLTiu_MM:
11511 case Mips::XORI_MMR6: {
11512 switch (OpNum) {
11513 case 0:
11514 // op: rt
11515 return 21;
11516 case 1:
11517 // op: rs
11518 return 16;
11519 case 2:
11520 // op: imm16
11521 return 0;
11522 }
11523 break;
11524 }
11525 case Mips::BNVC_MMR6:
11526 case Mips::BOVC_MMR6: {
11527 switch (OpNum) {
11528 case 0:
11529 // op: rt
11530 return 21;
11531 case 1:
11532 // op: rs
11533 return 16;
11534 case 2:
11535 // op: offset
11536 return 0;
11537 }
11538 break;
11539 }
11540 case Mips::EXT_MM:
11541 case Mips::INS_MM: {
11542 switch (OpNum) {
11543 case 0:
11544 // op: rt
11545 return 21;
11546 case 1:
11547 // op: rs
11548 return 16;
11549 case 2:
11550 // op: pos
11551 return 6;
11552 case 3:
11553 // op: size
11554 return 11;
11555 }
11556 break;
11557 }
11558 case Mips::APPEND_MMR2:
11559 case Mips::PRECR_SRA_PH_W_MMR2:
11560 case Mips::PRECR_SRA_R_PH_W_MMR2:
11561 case Mips::PREPEND_MMR2:
11562 case Mips::SHLL_S_W_MM:
11563 case Mips::SHRA_R_W_MM: {
11564 switch (OpNum) {
11565 case 0:
11566 // op: rt
11567 return 21;
11568 case 1:
11569 // op: rs
11570 return 16;
11571 case 2:
11572 // op: sa
11573 return 11;
11574 }
11575 break;
11576 }
11577 case Mips::SHLL_PH_MM:
11578 case Mips::SHLL_S_PH_MM:
11579 case Mips::SHRA_PH_MM:
11580 case Mips::SHRA_R_PH_MM:
11581 case Mips::SHRL_PH_MMR2: {
11582 switch (OpNum) {
11583 case 0:
11584 // op: rt
11585 return 21;
11586 case 1:
11587 // op: rs
11588 return 16;
11589 case 2:
11590 // op: sa
11591 return 12;
11592 }
11593 break;
11594 }
11595 case Mips::SHLL_QB_MM:
11596 case Mips::SHRA_QB_MMR2:
11597 case Mips::SHRA_R_QB_MMR2:
11598 case Mips::SHRL_QB_MM: {
11599 switch (OpNum) {
11600 case 0:
11601 // op: rt
11602 return 21;
11603 case 1:
11604 // op: rs
11605 return 16;
11606 case 2:
11607 // op: sa
11608 return 13;
11609 }
11610 break;
11611 }
11612 case Mips::MFC0_MMR6:
11613 case Mips::MFGC0_MM:
11614 case Mips::MFHC0_MMR6:
11615 case Mips::MFHGC0_MM:
11616 case Mips::RDHWR_MMR6: {
11617 switch (OpNum) {
11618 case 0:
11619 // op: rt
11620 return 21;
11621 case 1:
11622 // op: rs
11623 return 16;
11624 case 2:
11625 // op: sel
11626 return 11;
11627 }
11628 break;
11629 }
11630 case Mips::EXT_MMR6:
11631 case Mips::INS_MMR6: {
11632 switch (OpNum) {
11633 case 0:
11634 // op: rt
11635 return 21;
11636 case 1:
11637 // op: rs
11638 return 16;
11639 case 3:
11640 // op: size
11641 return 11;
11642 case 2:
11643 // op: pos
11644 return 6;
11645 }
11646 break;
11647 }
11648 case Mips::ABSQ_S_PH_MM:
11649 case Mips::ABSQ_S_QB_MMR2:
11650 case Mips::ABSQ_S_W_MM:
11651 case Mips::BITREV_MM:
11652 case Mips::JALRC_HB_MMR6:
11653 case Mips::JALRC_MMR6:
11654 case Mips::PRECEQU_PH_QBLA_MM:
11655 case Mips::PRECEQU_PH_QBL_MM:
11656 case Mips::PRECEQU_PH_QBRA_MM:
11657 case Mips::PRECEQU_PH_QBR_MM:
11658 case Mips::PRECEQ_W_PHL_MM:
11659 case Mips::PRECEQ_W_PHR_MM:
11660 case Mips::PRECEU_PH_QBLA_MM:
11661 case Mips::PRECEU_PH_QBL_MM:
11662 case Mips::PRECEU_PH_QBRA_MM:
11663 case Mips::PRECEU_PH_QBR_MM:
11664 case Mips::RADDU_W_QB_MM:
11665 case Mips::REPLV_PH_MM:
11666 case Mips::REPLV_QB_MM:
11667 case Mips::WRPGPR_MMR6:
11668 case Mips::WSBH_MMR6: {
11669 switch (OpNum) {
11670 case 0:
11671 // op: rt
11672 return 21;
11673 case 1:
11674 // op: rs
11675 return 16;
11676 }
11677 break;
11678 }
11679 case Mips::LWP_MM:
11680 case Mips::SWP_MM: {
11681 switch (OpNum) {
11682 case 0:
11683 // op: rt
11684 return 21;
11685 case 2:
11686 // op: addr
11687 return 0;
11688 }
11689 break;
11690 }
11691 case Mips::EXTPDP_MM:
11692 case Mips::EXTP_MM:
11693 case Mips::EXTR_RS_W_MM:
11694 case Mips::EXTR_R_W_MM:
11695 case Mips::EXTR_S_H_MM:
11696 case Mips::EXTR_W_MM: {
11697 switch (OpNum) {
11698 case 0:
11699 // op: rt
11700 return 21;
11701 case 2:
11702 // op: imm
11703 return 16;
11704 case 1:
11705 // op: ac
11706 return 14;
11707 }
11708 break;
11709 }
11710 case Mips::EXTPDPV_MM:
11711 case Mips::EXTPV_MM:
11712 case Mips::EXTRV_RS_W_MM:
11713 case Mips::EXTRV_R_W_MM:
11714 case Mips::EXTRV_S_H_MM:
11715 case Mips::EXTRV_W_MM: {
11716 switch (OpNum) {
11717 case 0:
11718 // op: rt
11719 return 21;
11720 case 2:
11721 // op: rs
11722 return 16;
11723 case 1:
11724 // op: ac
11725 return 14;
11726 }
11727 break;
11728 }
11729 case Mips::INSV_MM: {
11730 switch (OpNum) {
11731 case 0:
11732 // op: rt
11733 return 21;
11734 case 2:
11735 // op: rs
11736 return 16;
11737 }
11738 break;
11739 }
11740 case Mips::NOT16_MM: {
11741 switch (OpNum) {
11742 case 0:
11743 // op: rt
11744 return 3;
11745 case 1:
11746 // op: rs
11747 return 0;
11748 }
11749 break;
11750 }
11751 case Mips::LWM16_MM:
11752 case Mips::SWM16_MM: {
11753 switch (OpNum) {
11754 case 0:
11755 // op: rt
11756 return 4;
11757 case 1:
11758 // op: addr
11759 return 0;
11760 }
11761 break;
11762 }
11763 case Mips::LWSP_MM:
11764 case Mips::SWSP_MM:
11765 case Mips::SWSP_MMR6: {
11766 switch (OpNum) {
11767 case 0:
11768 // op: rt
11769 return 5;
11770 case 1:
11771 // op: offset
11772 return 0;
11773 }
11774 break;
11775 }
11776 case Mips::LBU16_MM:
11777 case Mips::LHU16_MM:
11778 case Mips::LW16_MM:
11779 case Mips::SB16_MM:
11780 case Mips::SB16_MMR6:
11781 case Mips::SH16_MM:
11782 case Mips::SH16_MMR6:
11783 case Mips::SW16_MM:
11784 case Mips::SW16_MMR6: {
11785 switch (OpNum) {
11786 case 0:
11787 // op: rt
11788 return 7;
11789 case 1:
11790 // op: addr
11791 return 0;
11792 }
11793 break;
11794 }
11795 case Mips::LWGP_MM: {
11796 switch (OpNum) {
11797 case 0:
11798 // op: rt
11799 return 7;
11800 case 1:
11801 // op: offset
11802 return 0;
11803 }
11804 break;
11805 }
11806 case Mips::NOT16_MMR6: {
11807 switch (OpNum) {
11808 case 0:
11809 // op: rt
11810 return 7;
11811 case 1:
11812 // op: rs
11813 return 4;
11814 }
11815 break;
11816 }
11817 case Mips::LWM16_MMR6:
11818 case Mips::SWM16_MMR6: {
11819 switch (OpNum) {
11820 case 0:
11821 // op: rt
11822 return 8;
11823 case 1:
11824 // op: addr
11825 return 4;
11826 }
11827 break;
11828 }
11829 case Mips::BeqzRxImm16:
11830 case Mips::BnezRxImm16:
11831 case Mips::CmpiRxImm16:
11832 case Mips::LiRxImm16:
11833 case Mips::LwRxPcTcp16:
11834 case Mips::SltiRxImm16:
11835 case Mips::SltiuRxImm16: {
11836 switch (OpNum) {
11837 case 0:
11838 // op: rx
11839 return 8;
11840 case 1:
11841 // op: imm8
11842 return 0;
11843 }
11844 break;
11845 }
11846 case Mips::CmpRxRy16:
11847 case Mips::DivRxRy16:
11848 case Mips::DivuRxRy16:
11849 case Mips::NegRxRy16:
11850 case Mips::NotRxRy16:
11851 case Mips::SltRxRy16:
11852 case Mips::SltuRxRy16: {
11853 switch (OpNum) {
11854 case 0:
11855 // op: rx
11856 return 8;
11857 case 1:
11858 // op: ry
11859 return 5;
11860 }
11861 break;
11862 }
11863 case Mips::AddiuRxRxImm16: {
11864 switch (OpNum) {
11865 case 0:
11866 // op: rx
11867 return 8;
11868 case 2:
11869 // op: imm8
11870 return 0;
11871 }
11872 break;
11873 }
11874 case Mips::JumpLinkReg16:
11875 case Mips::Mfhi16:
11876 case Mips::Mflo16:
11877 case Mips::SebRx16:
11878 case Mips::SehRx16: {
11879 switch (OpNum) {
11880 case 0:
11881 // op: rx
11882 return 8;
11883 }
11884 break;
11885 }
11886 case Mips::MoveR3216: {
11887 switch (OpNum) {
11888 case 0:
11889 // op: ry
11890 return 4;
11891 case 1:
11892 // op: r32
11893 return 0;
11894 }
11895 break;
11896 }
11897 case Mips::SYNC_MM:
11898 case Mips::SYNC_MMR6: {
11899 switch (OpNum) {
11900 case 0:
11901 // op: stype
11902 return 16;
11903 }
11904 break;
11905 }
11906 case Mips::SYNC: {
11907 switch (OpNum) {
11908 case 0:
11909 // op: stype
11910 return 6;
11911 }
11912 break;
11913 }
11914 case Mips::J:
11915 case Mips::JAL:
11916 case Mips::JALS_MM:
11917 case Mips::JALX:
11918 case Mips::JALX_MM:
11919 case Mips::JAL_MM:
11920 case Mips::J_MM: {
11921 switch (OpNum) {
11922 case 0:
11923 // op: target
11924 return 0;
11925 }
11926 break;
11927 }
11928 case Mips::LBU_MMR6:
11929 case Mips::LB_MMR6: {
11930 switch (OpNum) {
11931 case 1:
11932 // op: addr
11933 return 0;
11934 case 0:
11935 // op: rt
11936 return 21;
11937 }
11938 break;
11939 }
11940 case Mips::LD_B:
11941 case Mips::LD_D:
11942 case Mips::LD_H:
11943 case Mips::LD_W:
11944 case Mips::ST_B:
11945 case Mips::ST_D:
11946 case Mips::ST_H:
11947 case Mips::ST_W: {
11948 switch (OpNum) {
11949 case 1:
11950 // op: addr
11951 return 11;
11952 case 0:
11953 // op: wd
11954 return 6;
11955 }
11956 break;
11957 }
11958 case Mips::LBE:
11959 case Mips::LBuE:
11960 case Mips::LHE:
11961 case Mips::LHuE:
11962 case Mips::LLE:
11963 case Mips::LWE:
11964 case Mips::LWLE:
11965 case Mips::LWRE:
11966 case Mips::SBE:
11967 case Mips::SHE:
11968 case Mips::SWE:
11969 case Mips::SWLE:
11970 case Mips::SWRE: {
11971 switch (OpNum) {
11972 case 1:
11973 // op: addr
11974 return 7;
11975 case 0:
11976 // op: rt
11977 return 16;
11978 }
11979 break;
11980 }
11981 case Mips::CLASS_D:
11982 case Mips::CLASS_S:
11983 case Mips::RINT_D:
11984 case Mips::RINT_S: {
11985 switch (OpNum) {
11986 case 1:
11987 // op: fs
11988 return 11;
11989 case 0:
11990 // op: fd
11991 return 6;
11992 }
11993 break;
11994 }
11995 case Mips::C_EQ_D32:
11996 case Mips::C_EQ_D64:
11997 case Mips::C_EQ_S:
11998 case Mips::C_F_D32:
11999 case Mips::C_F_D64:
12000 case Mips::C_F_S:
12001 case Mips::C_LE_D32:
12002 case Mips::C_LE_D64:
12003 case Mips::C_LE_S:
12004 case Mips::C_LT_D32:
12005 case Mips::C_LT_D64:
12006 case Mips::C_LT_S:
12007 case Mips::C_NGE_D32:
12008 case Mips::C_NGE_D64:
12009 case Mips::C_NGE_S:
12010 case Mips::C_NGLE_D32:
12011 case Mips::C_NGLE_D64:
12012 case Mips::C_NGLE_S:
12013 case Mips::C_NGL_D32:
12014 case Mips::C_NGL_D64:
12015 case Mips::C_NGL_S:
12016 case Mips::C_NGT_D32:
12017 case Mips::C_NGT_D64:
12018 case Mips::C_NGT_S:
12019 case Mips::C_OLE_D32:
12020 case Mips::C_OLE_D64:
12021 case Mips::C_OLE_S:
12022 case Mips::C_OLT_D32:
12023 case Mips::C_OLT_D64:
12024 case Mips::C_OLT_S:
12025 case Mips::C_SEQ_D32:
12026 case Mips::C_SEQ_D64:
12027 case Mips::C_SEQ_S:
12028 case Mips::C_SF_D32:
12029 case Mips::C_SF_D64:
12030 case Mips::C_SF_S:
12031 case Mips::C_UEQ_D32:
12032 case Mips::C_UEQ_D64:
12033 case Mips::C_UEQ_S:
12034 case Mips::C_ULE_D32:
12035 case Mips::C_ULE_D64:
12036 case Mips::C_ULE_S:
12037 case Mips::C_ULT_D32:
12038 case Mips::C_ULT_D64:
12039 case Mips::C_ULT_S:
12040 case Mips::C_UN_D32:
12041 case Mips::C_UN_D64:
12042 case Mips::C_UN_S: {
12043 switch (OpNum) {
12044 case 1:
12045 // op: fs
12046 return 11;
12047 case 2:
12048 // op: ft
12049 return 16;
12050 case 0:
12051 // op: fcc
12052 return 8;
12053 }
12054 break;
12055 }
12056 case Mips::C_EQ_D32_MM:
12057 case Mips::C_EQ_D64_MM:
12058 case Mips::C_EQ_S_MM:
12059 case Mips::C_F_D32_MM:
12060 case Mips::C_F_D64_MM:
12061 case Mips::C_F_S_MM:
12062 case Mips::C_LE_D32_MM:
12063 case Mips::C_LE_D64_MM:
12064 case Mips::C_LE_S_MM:
12065 case Mips::C_LT_D32_MM:
12066 case Mips::C_LT_D64_MM:
12067 case Mips::C_LT_S_MM:
12068 case Mips::C_NGE_D32_MM:
12069 case Mips::C_NGE_D64_MM:
12070 case Mips::C_NGE_S_MM:
12071 case Mips::C_NGLE_D32_MM:
12072 case Mips::C_NGLE_D64_MM:
12073 case Mips::C_NGLE_S_MM:
12074 case Mips::C_NGL_D32_MM:
12075 case Mips::C_NGL_D64_MM:
12076 case Mips::C_NGL_S_MM:
12077 case Mips::C_NGT_D32_MM:
12078 case Mips::C_NGT_D64_MM:
12079 case Mips::C_NGT_S_MM:
12080 case Mips::C_OLE_D32_MM:
12081 case Mips::C_OLE_D64_MM:
12082 case Mips::C_OLE_S_MM:
12083 case Mips::C_OLT_D32_MM:
12084 case Mips::C_OLT_D64_MM:
12085 case Mips::C_OLT_S_MM:
12086 case Mips::C_SEQ_D32_MM:
12087 case Mips::C_SEQ_D64_MM:
12088 case Mips::C_SEQ_S_MM:
12089 case Mips::C_SF_D32_MM:
12090 case Mips::C_SF_D64_MM:
12091 case Mips::C_SF_S_MM:
12092 case Mips::C_UEQ_D32_MM:
12093 case Mips::C_UEQ_D64_MM:
12094 case Mips::C_UEQ_S_MM:
12095 case Mips::C_ULE_D32_MM:
12096 case Mips::C_ULE_D64_MM:
12097 case Mips::C_ULE_S_MM:
12098 case Mips::C_ULT_D32_MM:
12099 case Mips::C_ULT_D64_MM:
12100 case Mips::C_ULT_S_MM:
12101 case Mips::C_UN_D32_MM:
12102 case Mips::C_UN_D64_MM:
12103 case Mips::C_UN_S_MM: {
12104 switch (OpNum) {
12105 case 1:
12106 // op: fs
12107 return 16;
12108 case 2:
12109 // op: ft
12110 return 21;
12111 case 0:
12112 // op: fcc
12113 return 13;
12114 }
12115 break;
12116 }
12117 case Mips::CLASS_D_MMR6:
12118 case Mips::CLASS_S_MMR6:
12119 case Mips::RINT_D_MMR6:
12120 case Mips::RINT_S_MMR6: {
12121 switch (OpNum) {
12122 case 1:
12123 // op: fs
12124 return 21;
12125 case 0:
12126 // op: fd
12127 return 16;
12128 }
12129 break;
12130 }
12131 case Mips::FADD_S_MMR6:
12132 case Mips::FDIV_S_MMR6:
12133 case Mips::FMUL_S_MMR6:
12134 case Mips::FSUB_S_MMR6: {
12135 switch (OpNum) {
12136 case 1:
12137 // op: ft
12138 return 21;
12139 case 2:
12140 // op: fs
12141 return 16;
12142 case 0:
12143 // op: fd
12144 return 11;
12145 }
12146 break;
12147 }
12148 case Mips::AddiuRxImmX16:
12149 case Mips::AddiuRxPcImmX16:
12150 case Mips::BeqzRxImmX16:
12151 case Mips::BnezRxImmX16:
12152 case Mips::CmpiRxImmX16:
12153 case Mips::LiRxImmAlignX16:
12154 case Mips::LiRxImmX16:
12155 case Mips::LwRxPcTcpX16:
12156 case Mips::SltiRxImmX16:
12157 case Mips::SltiuRxImmX16: {
12158 switch (OpNum) {
12159 case 1:
12160 // op: imm16
12161 return 0;
12162 case 0:
12163 // op: rx
12164 return 8;
12165 }
12166 break;
12167 }
12168 case Mips::PREFX_MM: {
12169 switch (OpNum) {
12170 case 1:
12171 // op: index
12172 return 21;
12173 case 0:
12174 // op: base
12175 return 16;
12176 case 2:
12177 // op: hint
12178 return 11;
12179 }
12180 break;
12181 }
12182 case Mips::BNZ_B:
12183 case Mips::BNZ_D:
12184 case Mips::BNZ_H:
12185 case Mips::BNZ_V:
12186 case Mips::BNZ_W:
12187 case Mips::BZ_B:
12188 case Mips::BZ_D:
12189 case Mips::BZ_H:
12190 case Mips::BZ_V:
12191 case Mips::BZ_W: {
12192 switch (OpNum) {
12193 case 1:
12194 // op: offset
12195 return 0;
12196 case 0:
12197 // op: wt
12198 return 16;
12199 }
12200 break;
12201 }
12202 case Mips::ADDIUS5_MM: {
12203 switch (OpNum) {
12204 case 1:
12205 // op: rd
12206 return 5;
12207 case 2:
12208 // op: imm
12209 return 1;
12210 }
12211 break;
12212 }
12213 case Mips::MOVE16_MM:
12214 case Mips::MOVE16_MMR6: {
12215 switch (OpNum) {
12216 case 1:
12217 // op: rs
12218 return 0;
12219 case 0:
12220 // op: rd
12221 return 5;
12222 }
12223 break;
12224 }
12225 case Mips::CTCMSA: {
12226 switch (OpNum) {
12227 case 1:
12228 // op: rs
12229 return 11;
12230 case 0:
12231 // op: cd
12232 return 6;
12233 }
12234 break;
12235 }
12236 case Mips::FILL_B:
12237 case Mips::FILL_D:
12238 case Mips::FILL_H:
12239 case Mips::FILL_W: {
12240 switch (OpNum) {
12241 case 1:
12242 // op: rs
12243 return 11;
12244 case 0:
12245 // op: wd
12246 return 6;
12247 }
12248 break;
12249 }
12250 case Mips::MTHI_DSP_MM:
12251 case Mips::MTHLIP_MM:
12252 case Mips::MTLO_DSP_MM:
12253 case Mips::SHILOV_MM: {
12254 switch (OpNum) {
12255 case 1:
12256 // op: rs
12257 return 16;
12258 case 0:
12259 // op: ac
12260 return 14;
12261 }
12262 break;
12263 }
12264 case Mips::JALRS_MM:
12265 case Mips::JALR_MM: {
12266 switch (OpNum) {
12267 case 1:
12268 // op: rs
12269 return 16;
12270 case 0:
12271 // op: rd
12272 return 21;
12273 }
12274 break;
12275 }
12276 case Mips::AUI_MMR6: {
12277 switch (OpNum) {
12278 case 1:
12279 // op: rs
12280 return 16;
12281 case 0:
12282 // op: rt
12283 return 21;
12284 case 2:
12285 // op: imm
12286 return 0;
12287 }
12288 break;
12289 }
12290 case Mips::ADDi_MM:
12291 case Mips::ADDiu_MM:
12292 case Mips::ANDi_MM:
12293 case Mips::ORi_MM:
12294 case Mips::XORi_MM: {
12295 switch (OpNum) {
12296 case 1:
12297 // op: rs
12298 return 16;
12299 case 0:
12300 // op: rt
12301 return 21;
12302 case 2:
12303 // op: imm16
12304 return 0;
12305 }
12306 break;
12307 }
12308 case Mips::CLO_MMR6: {
12309 switch (OpNum) {
12310 case 1:
12311 // op: rs
12312 return 16;
12313 case 0:
12314 // op: rt
12315 return 21;
12316 }
12317 break;
12318 }
12319 case Mips::MTHI_DSP:
12320 case Mips::MTLO_DSP: {
12321 switch (OpNum) {
12322 case 1:
12323 // op: rs
12324 return 21;
12325 case 0:
12326 // op: ac
12327 return 11;
12328 }
12329 break;
12330 }
12331 case Mips::YIELD: {
12332 switch (OpNum) {
12333 case 1:
12334 // op: rs
12335 return 21;
12336 case 0:
12337 // op: rd
12338 return 11;
12339 }
12340 break;
12341 }
12342 case Mips::CLZ_MMR6: {
12343 switch (OpNum) {
12344 case 1:
12345 // op: rs
12346 return 21;
12347 case 0:
12348 // op: rt
12349 return 11;
12350 }
12351 break;
12352 }
12353 case Mips::AUI:
12354 case Mips::DAUI: {
12355 switch (OpNum) {
12356 case 1:
12357 // op: rs
12358 return 21;
12359 case 0:
12360 // op: rt
12361 return 16;
12362 case 2:
12363 // op: imm
12364 return 0;
12365 }
12366 break;
12367 }
12368 case Mips::SEQi:
12369 case Mips::SNEi: {
12370 switch (OpNum) {
12371 case 1:
12372 // op: rs
12373 return 21;
12374 case 0:
12375 // op: rt
12376 return 16;
12377 case 2:
12378 // op: imm10
12379 return 6;
12380 }
12381 break;
12382 }
12383 case Mips::ADDi:
12384 case Mips::ADDiu:
12385 case Mips::ANDi:
12386 case Mips::ANDi64:
12387 case Mips::DADDi:
12388 case Mips::DADDiu:
12389 case Mips::ORi:
12390 case Mips::ORi64:
12391 case Mips::XORi:
12392 case Mips::XORi64: {
12393 switch (OpNum) {
12394 case 1:
12395 // op: rs
12396 return 21;
12397 case 0:
12398 // op: rt
12399 return 16;
12400 case 2:
12401 // op: imm16
12402 return 0;
12403 }
12404 break;
12405 }
12406 case Mips::PRECR_SRA_PH_W:
12407 case Mips::PRECR_SRA_R_PH_W: {
12408 switch (OpNum) {
12409 case 1:
12410 // op: rs
12411 return 21;
12412 case 0:
12413 // op: rt
12414 return 16;
12415 case 2:
12416 // op: sa
12417 return 11;
12418 }
12419 break;
12420 }
12421 case Mips::DLSA:
12422 case Mips::LSA: {
12423 switch (OpNum) {
12424 case 1:
12425 // op: rs
12426 return 21;
12427 case 2:
12428 // op: rt
12429 return 16;
12430 case 0:
12431 // op: rd
12432 return 11;
12433 case 3:
12434 // op: sa
12435 return 6;
12436 }
12437 break;
12438 }
12439 case Mips::CMPGDU_EQ_QB:
12440 case Mips::CMPGDU_LE_QB:
12441 case Mips::CMPGDU_LT_QB:
12442 case Mips::CMPGU_EQ_QB:
12443 case Mips::CMPGU_LE_QB:
12444 case Mips::CMPGU_LT_QB:
12445 case Mips::PACKRL_PH:
12446 case Mips::PICK_PH:
12447 case Mips::PICK_QB:
12448 case Mips::PRECRQU_S_QB_PH:
12449 case Mips::PRECRQ_PH_W:
12450 case Mips::PRECRQ_QB_PH:
12451 case Mips::PRECRQ_RS_PH_W:
12452 case Mips::PRECR_QB_PH: {
12453 switch (OpNum) {
12454 case 1:
12455 // op: rs
12456 return 21;
12457 case 2:
12458 // op: rt
12459 return 16;
12460 case 0:
12461 // op: rd
12462 return 11;
12463 }
12464 break;
12465 }
12466 case Mips::CRC32B:
12467 case Mips::CRC32CB:
12468 case Mips::CRC32CD:
12469 case Mips::CRC32CH:
12470 case Mips::CRC32CW:
12471 case Mips::CRC32D:
12472 case Mips::CRC32H:
12473 case Mips::CRC32W: {
12474 switch (OpNum) {
12475 case 1:
12476 // op: rs
12477 return 21;
12478 case 2:
12479 // op: rt
12480 return 16;
12481 }
12482 break;
12483 }
12484 case Mips::ADDU16_MMR6:
12485 case Mips::SUBU16_MMR6: {
12486 switch (OpNum) {
12487 case 1:
12488 // op: rs
12489 return 7;
12490 case 2:
12491 // op: rt
12492 return 4;
12493 case 0:
12494 // op: rd
12495 return 1;
12496 }
12497 break;
12498 }
12499 case Mips::CTC1:
12500 case Mips::DMTC1:
12501 case Mips::MTC1:
12502 case Mips::MTC1_D64: {
12503 switch (OpNum) {
12504 case 1:
12505 // op: rt
12506 return 16;
12507 case 0:
12508 // op: fs
12509 return 11;
12510 }
12511 break;
12512 }
12513 case Mips::DMTC0:
12514 case Mips::DMTC2:
12515 case Mips::DMTGC0:
12516 case Mips::MTC0:
12517 case Mips::MTC2:
12518 case Mips::MTGC0:
12519 case Mips::MTHGC0: {
12520 switch (OpNum) {
12521 case 1:
12522 // op: rt
12523 return 16;
12524 case 0:
12525 // op: rd
12526 return 11;
12527 case 2:
12528 // op: sel
12529 return 0;
12530 }
12531 break;
12532 }
12533 case Mips::MFTR:
12534 case Mips::MTTR: {
12535 switch (OpNum) {
12536 case 1:
12537 // op: rt
12538 return 16;
12539 case 0:
12540 // op: rd
12541 return 11;
12542 case 2:
12543 // op: u
12544 return 5;
12545 case 4:
12546 // op: h
12547 return 4;
12548 case 3:
12549 // op: sel
12550 return 0;
12551 }
12552 break;
12553 }
12554 case Mips::SC:
12555 case Mips::SC64:
12556 case Mips::SCD: {
12557 switch (OpNum) {
12558 case 1:
12559 // op: rt
12560 return 16;
12561 case 2:
12562 // op: addr
12563 return 0;
12564 }
12565 break;
12566 }
12567 case Mips::SC64_R6:
12568 case Mips::SCD_R6:
12569 case Mips::SC_R6: {
12570 switch (OpNum) {
12571 case 1:
12572 // op: rt
12573 return 16;
12574 case 2:
12575 // op: addr
12576 return 7;
12577 }
12578 break;
12579 }
12580 case Mips::CTC1_MM:
12581 case Mips::MTC1_D64_MM:
12582 case Mips::MTC1_MM:
12583 case Mips::MTC1_MMR6: {
12584 switch (OpNum) {
12585 case 1:
12586 // op: rt
12587 return 21;
12588 case 0:
12589 // op: fs
12590 return 16;
12591 }
12592 break;
12593 }
12594 case Mips::CTC2_MM:
12595 case Mips::MTC2_MMR6:
12596 case Mips::MTHC2_MMR6: {
12597 switch (OpNum) {
12598 case 1:
12599 // op: rt
12600 return 21;
12601 case 0:
12602 // op: impl
12603 return 16;
12604 }
12605 break;
12606 }
12607 case Mips::BEQC_MMR6:
12608 case Mips::BGEC_MMR6:
12609 case Mips::BGEUC_MMR6:
12610 case Mips::BLTC_MMR6:
12611 case Mips::BLTUC_MMR6:
12612 case Mips::BNEC_MMR6: {
12613 switch (OpNum) {
12614 case 1:
12615 // op: rt
12616 return 21;
12617 case 0:
12618 // op: rs
12619 return 16;
12620 case 2:
12621 // op: offset
12622 return 0;
12623 }
12624 break;
12625 }
12626 case Mips::MTC0_MMR6:
12627 case Mips::MTGC0_MM:
12628 case Mips::MTHC0_MMR6:
12629 case Mips::MTHGC0_MM: {
12630 switch (OpNum) {
12631 case 1:
12632 // op: rt
12633 return 21;
12634 case 0:
12635 // op: rs
12636 return 16;
12637 case 2:
12638 // op: sel
12639 return 11;
12640 }
12641 break;
12642 }
12643 case Mips::CMPU_EQ_QB_MM:
12644 case Mips::CMPU_LE_QB_MM:
12645 case Mips::CMPU_LT_QB_MM:
12646 case Mips::CMP_EQ_PH_MM:
12647 case Mips::CMP_LE_PH_MM:
12648 case Mips::CMP_LT_PH_MM: {
12649 switch (OpNum) {
12650 case 1:
12651 // op: rt
12652 return 21;
12653 case 0:
12654 // op: rs
12655 return 16;
12656 }
12657 break;
12658 }
12659 case Mips::SCE_MM:
12660 case Mips::SC_MM:
12661 case Mips::SC_MMR6: {
12662 switch (OpNum) {
12663 case 1:
12664 // op: rt
12665 return 21;
12666 case 2:
12667 // op: addr
12668 return 0;
12669 }
12670 break;
12671 }
12672 case Mips::AdduRxRyRz16:
12673 case Mips::SubuRxRyRz16: {
12674 switch (OpNum) {
12675 case 1:
12676 // op: rx
12677 return 8;
12678 case 2:
12679 // op: ry
12680 return 5;
12681 case 0:
12682 // op: rz
12683 return 2;
12684 }
12685 break;
12686 }
12687 case Mips::AndRxRxRy16:
12688 case Mips::OrRxRxRy16:
12689 case Mips::SllvRxRy16:
12690 case Mips::SravRxRy16:
12691 case Mips::SrlvRxRy16:
12692 case Mips::XorRxRxRy16: {
12693 switch (OpNum) {
12694 case 1:
12695 // op: rx
12696 return 8;
12697 case 2:
12698 // op: ry
12699 return 5;
12700 }
12701 break;
12702 }
12703 case Mips::LDI_B:
12704 case Mips::LDI_D:
12705 case Mips::LDI_H:
12706 case Mips::LDI_W: {
12707 switch (OpNum) {
12708 case 1:
12709 // op: s10
12710 return 11;
12711 case 0:
12712 // op: wd
12713 return 6;
12714 }
12715 break;
12716 }
12717 case Mips::SHILO_MM: {
12718 switch (OpNum) {
12719 case 1:
12720 // op: shift
12721 return 16;
12722 case 0:
12723 // op: ac
12724 return 14;
12725 }
12726 break;
12727 }
12728 case Mips::BCLRI_B:
12729 case Mips::BCLRI_D:
12730 case Mips::BCLRI_H:
12731 case Mips::BCLRI_W:
12732 case Mips::BNEGI_B:
12733 case Mips::BNEGI_D:
12734 case Mips::BNEGI_H:
12735 case Mips::BNEGI_W:
12736 case Mips::BSETI_B:
12737 case Mips::BSETI_D:
12738 case Mips::BSETI_H:
12739 case Mips::BSETI_W:
12740 case Mips::SAT_S_B:
12741 case Mips::SAT_S_D:
12742 case Mips::SAT_S_H:
12743 case Mips::SAT_S_W:
12744 case Mips::SAT_U_B:
12745 case Mips::SAT_U_D:
12746 case Mips::SAT_U_H:
12747 case Mips::SAT_U_W:
12748 case Mips::SLLI_B:
12749 case Mips::SLLI_D:
12750 case Mips::SLLI_H:
12751 case Mips::SLLI_W:
12752 case Mips::SRAI_B:
12753 case Mips::SRAI_D:
12754 case Mips::SRAI_H:
12755 case Mips::SRAI_W:
12756 case Mips::SRARI_B:
12757 case Mips::SRARI_D:
12758 case Mips::SRARI_H:
12759 case Mips::SRARI_W:
12760 case Mips::SRLI_B:
12761 case Mips::SRLI_D:
12762 case Mips::SRLI_H:
12763 case Mips::SRLI_W:
12764 case Mips::SRLRI_B:
12765 case Mips::SRLRI_D:
12766 case Mips::SRLRI_H:
12767 case Mips::SRLRI_W: {
12768 switch (OpNum) {
12769 case 1:
12770 // op: ws
12771 return 11;
12772 case 0:
12773 // op: wd
12774 return 6;
12775 case 2:
12776 // op: m
12777 return 16;
12778 }
12779 break;
12780 }
12781 case Mips::FCLASS_D:
12782 case Mips::FCLASS_W:
12783 case Mips::FEXUPL_D:
12784 case Mips::FEXUPL_W:
12785 case Mips::FEXUPR_D:
12786 case Mips::FEXUPR_W:
12787 case Mips::FFINT_S_D:
12788 case Mips::FFINT_S_W:
12789 case Mips::FFINT_U_D:
12790 case Mips::FFINT_U_W:
12791 case Mips::FFQL_D:
12792 case Mips::FFQL_W:
12793 case Mips::FFQR_D:
12794 case Mips::FFQR_W:
12795 case Mips::FLOG2_D:
12796 case Mips::FLOG2_W:
12797 case Mips::FRCP_D:
12798 case Mips::FRCP_W:
12799 case Mips::FRINT_D:
12800 case Mips::FRINT_W:
12801 case Mips::FRSQRT_D:
12802 case Mips::FRSQRT_W:
12803 case Mips::FSQRT_D:
12804 case Mips::FSQRT_W:
12805 case Mips::FTINT_S_D:
12806 case Mips::FTINT_S_W:
12807 case Mips::FTINT_U_D:
12808 case Mips::FTINT_U_W:
12809 case Mips::FTRUNC_S_D:
12810 case Mips::FTRUNC_S_W:
12811 case Mips::FTRUNC_U_D:
12812 case Mips::FTRUNC_U_W:
12813 case Mips::MOVE_V:
12814 case Mips::NLOC_B:
12815 case Mips::NLOC_D:
12816 case Mips::NLOC_H:
12817 case Mips::NLOC_W:
12818 case Mips::NLZC_B:
12819 case Mips::NLZC_D:
12820 case Mips::NLZC_H:
12821 case Mips::NLZC_W:
12822 case Mips::PCNT_B:
12823 case Mips::PCNT_D:
12824 case Mips::PCNT_H:
12825 case Mips::PCNT_W: {
12826 switch (OpNum) {
12827 case 1:
12828 // op: ws
12829 return 11;
12830 case 0:
12831 // op: wd
12832 return 6;
12833 }
12834 break;
12835 }
12836 case Mips::SCE: {
12837 switch (OpNum) {
12838 case 2:
12839 // op: addr
12840 return 7;
12841 case 1:
12842 // op: rt
12843 return 16;
12844 }
12845 break;
12846 }
12847 case Mips::MAXA_D:
12848 case Mips::MAXA_S:
12849 case Mips::MAX_D:
12850 case Mips::MAX_S:
12851 case Mips::MINA_D:
12852 case Mips::MINA_S:
12853 case Mips::MIN_D:
12854 case Mips::MIN_S:
12855 case Mips::SELEQZ_D:
12856 case Mips::SELEQZ_S:
12857 case Mips::SELNEZ_D:
12858 case Mips::SELNEZ_S: {
12859 switch (OpNum) {
12860 case 2:
12861 // op: ft
12862 return 16;
12863 case 1:
12864 // op: fs
12865 return 11;
12866 case 0:
12867 // op: fd
12868 return 6;
12869 }
12870 break;
12871 }
12872 case Mips::CMP_AF_D_MMR6:
12873 case Mips::CMP_AF_S_MMR6:
12874 case Mips::CMP_EQ_D_MMR6:
12875 case Mips::CMP_EQ_S_MMR6:
12876 case Mips::CMP_LE_D_MMR6:
12877 case Mips::CMP_LE_S_MMR6:
12878 case Mips::CMP_LT_D_MMR6:
12879 case Mips::CMP_LT_S_MMR6:
12880 case Mips::CMP_SAF_D_MMR6:
12881 case Mips::CMP_SAF_S_MMR6:
12882 case Mips::CMP_SEQ_D_MMR6:
12883 case Mips::CMP_SEQ_S_MMR6:
12884 case Mips::CMP_SLE_D_MMR6:
12885 case Mips::CMP_SLE_S_MMR6:
12886 case Mips::CMP_SLT_D_MMR6:
12887 case Mips::CMP_SLT_S_MMR6:
12888 case Mips::CMP_SUEQ_D_MMR6:
12889 case Mips::CMP_SUEQ_S_MMR6:
12890 case Mips::CMP_SULE_D_MMR6:
12891 case Mips::CMP_SULE_S_MMR6:
12892 case Mips::CMP_SULT_D_MMR6:
12893 case Mips::CMP_SULT_S_MMR6:
12894 case Mips::CMP_SUN_D_MMR6:
12895 case Mips::CMP_SUN_S_MMR6:
12896 case Mips::CMP_UEQ_D_MMR6:
12897 case Mips::CMP_UEQ_S_MMR6:
12898 case Mips::CMP_ULE_D_MMR6:
12899 case Mips::CMP_ULE_S_MMR6:
12900 case Mips::CMP_ULT_D_MMR6:
12901 case Mips::CMP_ULT_S_MMR6:
12902 case Mips::CMP_UN_D_MMR6:
12903 case Mips::CMP_UN_S_MMR6:
12904 case Mips::FADD_D32_MM:
12905 case Mips::FADD_D64_MM:
12906 case Mips::FADD_S_MM:
12907 case Mips::FDIV_D32_MM:
12908 case Mips::FDIV_D64_MM:
12909 case Mips::FDIV_S_MM:
12910 case Mips::FMUL_D32_MM:
12911 case Mips::FMUL_D64_MM:
12912 case Mips::FMUL_S_MM:
12913 case Mips::FSUB_D32_MM:
12914 case Mips::FSUB_D64_MM:
12915 case Mips::FSUB_S_MM:
12916 case Mips::MAXA_D_MMR6:
12917 case Mips::MAXA_S_MMR6:
12918 case Mips::MAX_D_MMR6:
12919 case Mips::MAX_S_MMR6:
12920 case Mips::MINA_D_MMR6:
12921 case Mips::MINA_S_MMR6:
12922 case Mips::MIN_D_MMR6:
12923 case Mips::MIN_S_MMR6:
12924 case Mips::SELEQZ_D_MMR6:
12925 case Mips::SELEQZ_S_MMR6:
12926 case Mips::SELNEZ_D_MMR6:
12927 case Mips::SELNEZ_S_MMR6: {
12928 switch (OpNum) {
12929 case 2:
12930 // op: ft
12931 return 21;
12932 case 1:
12933 // op: fs
12934 return 16;
12935 case 0:
12936 // op: fd
12937 return 11;
12938 }
12939 break;
12940 }
12941 case Mips::ADDVI_B:
12942 case Mips::ADDVI_D:
12943 case Mips::ADDVI_H:
12944 case Mips::ADDVI_W:
12945 case Mips::CEQI_B:
12946 case Mips::CEQI_D:
12947 case Mips::CEQI_H:
12948 case Mips::CEQI_W:
12949 case Mips::CLEI_S_B:
12950 case Mips::CLEI_S_D:
12951 case Mips::CLEI_S_H:
12952 case Mips::CLEI_S_W:
12953 case Mips::CLEI_U_B:
12954 case Mips::CLEI_U_D:
12955 case Mips::CLEI_U_H:
12956 case Mips::CLEI_U_W:
12957 case Mips::CLTI_S_B:
12958 case Mips::CLTI_S_D:
12959 case Mips::CLTI_S_H:
12960 case Mips::CLTI_S_W:
12961 case Mips::CLTI_U_B:
12962 case Mips::CLTI_U_D:
12963 case Mips::CLTI_U_H:
12964 case Mips::CLTI_U_W:
12965 case Mips::MAXI_S_B:
12966 case Mips::MAXI_S_D:
12967 case Mips::MAXI_S_H:
12968 case Mips::MAXI_S_W:
12969 case Mips::MAXI_U_B:
12970 case Mips::MAXI_U_D:
12971 case Mips::MAXI_U_H:
12972 case Mips::MAXI_U_W:
12973 case Mips::MINI_S_B:
12974 case Mips::MINI_S_D:
12975 case Mips::MINI_S_H:
12976 case Mips::MINI_S_W:
12977 case Mips::MINI_U_B:
12978 case Mips::MINI_U_D:
12979 case Mips::MINI_U_H:
12980 case Mips::MINI_U_W:
12981 case Mips::SUBVI_B:
12982 case Mips::SUBVI_D:
12983 case Mips::SUBVI_H:
12984 case Mips::SUBVI_W: {
12985 switch (OpNum) {
12986 case 2:
12987 // op: imm
12988 return 16;
12989 case 1:
12990 // op: ws
12991 return 11;
12992 case 0:
12993 // op: wd
12994 return 6;
12995 }
12996 break;
12997 }
12998 case Mips::AddiuRxRyOffMemX16: {
12999 switch (OpNum) {
13000 case 2:
13001 // op: imm15
13002 return 0;
13003 case 1:
13004 // op: rx
13005 return 8;
13006 case 0:
13007 // op: ry
13008 return 5;
13009 }
13010 break;
13011 }
13012 case Mips::AddiuRxRxImmX16: {
13013 switch (OpNum) {
13014 case 2:
13015 // op: imm16
13016 return 0;
13017 case 0:
13018 // op: rx
13019 return 8;
13020 }
13021 break;
13022 }
13023 case Mips::LbRxRyOffMemX16:
13024 case Mips::LbuRxRyOffMemX16:
13025 case Mips::LhRxRyOffMemX16:
13026 case Mips::LhuRxRyOffMemX16:
13027 case Mips::LwRxRyOffMemX16:
13028 case Mips::LwRxSpImmX16:
13029 case Mips::SbRxRyOffMemX16:
13030 case Mips::ShRxRyOffMemX16:
13031 case Mips::SwRxRyOffMemX16:
13032 case Mips::SwRxSpImmX16: {
13033 switch (OpNum) {
13034 case 2:
13035 // op: imm16
13036 return 0;
13037 case 1:
13038 // op: rx
13039 return 8;
13040 case 0:
13041 // op: ry
13042 return 5;
13043 }
13044 break;
13045 }
13046 case Mips::LBUX_MM:
13047 case Mips::LHX_MM:
13048 case Mips::LWX_MM: {
13049 switch (OpNum) {
13050 case 2:
13051 // op: index
13052 return 21;
13053 case 1:
13054 // op: base
13055 return 16;
13056 case 0:
13057 // op: rd
13058 return 11;
13059 }
13060 break;
13061 }
13062 case Mips::COPY_S_B:
13063 case Mips::COPY_S_D:
13064 case Mips::COPY_S_H:
13065 case Mips::COPY_S_W:
13066 case Mips::COPY_U_B:
13067 case Mips::COPY_U_H:
13068 case Mips::COPY_U_W: {
13069 switch (OpNum) {
13070 case 2:
13071 // op: n
13072 return 16;
13073 case 1:
13074 // op: ws
13075 return 11;
13076 case 0:
13077 // op: rd
13078 return 6;
13079 }
13080 break;
13081 }
13082 case Mips::SPLATI_B:
13083 case Mips::SPLATI_D:
13084 case Mips::SPLATI_H:
13085 case Mips::SPLATI_W: {
13086 switch (OpNum) {
13087 case 2:
13088 // op: n
13089 return 16;
13090 case 1:
13091 // op: ws
13092 return 11;
13093 case 0:
13094 // op: wd
13095 return 6;
13096 }
13097 break;
13098 }
13099 case Mips::INSVE_B:
13100 case Mips::INSVE_D:
13101 case Mips::INSVE_H:
13102 case Mips::INSVE_W: {
13103 switch (OpNum) {
13104 case 2:
13105 // op: n
13106 return 16;
13107 case 3:
13108 // op: ws
13109 return 11;
13110 case 0:
13111 // op: wd
13112 return 6;
13113 }
13114 break;
13115 }
13116 case Mips::MTHC1_D32:
13117 case Mips::MTHC1_D64: {
13118 switch (OpNum) {
13119 case 2:
13120 // op: rt
13121 return 16;
13122 case 0:
13123 // op: fs
13124 return 11;
13125 }
13126 break;
13127 }
13128 case Mips::SPLAT_B:
13129 case Mips::SPLAT_D:
13130 case Mips::SPLAT_H:
13131 case Mips::SPLAT_W: {
13132 switch (OpNum) {
13133 case 2:
13134 // op: rt
13135 return 16;
13136 case 1:
13137 // op: ws
13138 return 11;
13139 case 0:
13140 // op: wd
13141 return 6;
13142 }
13143 break;
13144 }
13145 case Mips::MTHC1_D32_MM:
13146 case Mips::MTHC1_D64_MM: {
13147 switch (OpNum) {
13148 case 2:
13149 // op: rt
13150 return 21;
13151 case 0:
13152 // op: fs
13153 return 16;
13154 }
13155 break;
13156 }
13157 case Mips::DPAQX_SA_W_PH_MMR2:
13158 case Mips::DPAQX_S_W_PH_MMR2:
13159 case Mips::DPAQ_SA_L_W_MM:
13160 case Mips::DPAQ_S_W_PH_MM:
13161 case Mips::DPAU_H_QBL_MM:
13162 case Mips::DPAU_H_QBR_MM:
13163 case Mips::DPAX_W_PH_MMR2:
13164 case Mips::DPA_W_PH_MMR2:
13165 case Mips::DPSQX_SA_W_PH_MMR2:
13166 case Mips::DPSQX_S_W_PH_MMR2:
13167 case Mips::DPSQ_SA_L_W_MM:
13168 case Mips::DPSQ_S_W_PH_MM:
13169 case Mips::DPSU_H_QBL_MM:
13170 case Mips::DPSU_H_QBR_MM:
13171 case Mips::DPSX_W_PH_MMR2:
13172 case Mips::DPS_W_PH_MMR2:
13173 case Mips::MADDU_DSP_MM:
13174 case Mips::MADD_DSP_MM:
13175 case Mips::MAQ_SA_W_PHL_MM:
13176 case Mips::MAQ_SA_W_PHR_MM:
13177 case Mips::MAQ_S_W_PHL_MM:
13178 case Mips::MAQ_S_W_PHR_MM:
13179 case Mips::MSUBU_DSP_MM:
13180 case Mips::MSUB_DSP_MM:
13181 case Mips::MULSAQ_S_W_PH_MM:
13182 case Mips::MULSA_W_PH_MMR2:
13183 case Mips::MULTU_DSP_MM:
13184 case Mips::MULT_DSP_MM: {
13185 switch (OpNum) {
13186 case 2:
13187 // op: rt
13188 return 21;
13189 case 1:
13190 // op: rs
13191 return 16;
13192 case 0:
13193 // op: ac
13194 return 14;
13195 }
13196 break;
13197 }
13198 case Mips::ADD_MM:
13199 case Mips::ADDu_MM:
13200 case Mips::AND_MM:
13201 case Mips::CMPGU_EQ_QB_MM:
13202 case Mips::CMPGU_LE_QB_MM:
13203 case Mips::CMPGU_LT_QB_MM:
13204 case Mips::MOVN_I_MM:
13205 case Mips::MOVZ_I_MM:
13206 case Mips::MUL_MM:
13207 case Mips::NOR_MM:
13208 case Mips::OR_MM:
13209 case Mips::SLT_MM:
13210 case Mips::SLTu_MM:
13211 case Mips::SUB_MM:
13212 case Mips::SUBu_MM:
13213 case Mips::XOR_MM: {
13214 switch (OpNum) {
13215 case 2:
13216 // op: rt
13217 return 21;
13218 case 1:
13219 // op: rs
13220 return 16;
13221 case 0:
13222 // op: rd
13223 return 11;
13224 }
13225 break;
13226 }
13227 case Mips::AND16_MM:
13228 case Mips::OR16_MM:
13229 case Mips::XOR16_MM: {
13230 switch (OpNum) {
13231 case 2:
13232 // op: rt
13233 return 3;
13234 case 1:
13235 // op: rs
13236 return 0;
13237 }
13238 break;
13239 }
13240 case Mips::AND16_MMR6:
13241 case Mips::OR16_MMR6:
13242 case Mips::XOR16_MMR6: {
13243 switch (OpNum) {
13244 case 2:
13245 // op: rt
13246 return 7;
13247 case 1:
13248 // op: rs
13249 return 4;
13250 }
13251 break;
13252 }
13253 case Mips::SllX16:
13254 case Mips::SraX16:
13255 case Mips::SrlX16: {
13256 switch (OpNum) {
13257 case 2:
13258 // op: sa6
13259 return 21;
13260 case 0:
13261 // op: rx
13262 return 8;
13263 case 1:
13264 // op: ry
13265 return 5;
13266 }
13267 break;
13268 }
13269 case Mips::ANDI_B:
13270 case Mips::NORI_B:
13271 case Mips::ORI_B:
13272 case Mips::SHF_B:
13273 case Mips::SHF_H:
13274 case Mips::SHF_W:
13275 case Mips::XORI_B: {
13276 switch (OpNum) {
13277 case 2:
13278 // op: u8
13279 return 16;
13280 case 1:
13281 // op: ws
13282 return 11;
13283 case 0:
13284 // op: wd
13285 return 6;
13286 }
13287 break;
13288 }
13289 case Mips::BINSLI_B:
13290 case Mips::BINSLI_D:
13291 case Mips::BINSLI_H:
13292 case Mips::BINSLI_W:
13293 case Mips::BINSRI_B:
13294 case Mips::BINSRI_D:
13295 case Mips::BINSRI_H:
13296 case Mips::BINSRI_W: {
13297 switch (OpNum) {
13298 case 2:
13299 // op: ws
13300 return 11;
13301 case 0:
13302 // op: wd
13303 return 6;
13304 case 3:
13305 // op: m
13306 return 16;
13307 }
13308 break;
13309 }
13310 case Mips::ADDS_A_B:
13311 case Mips::ADDS_A_D:
13312 case Mips::ADDS_A_H:
13313 case Mips::ADDS_A_W:
13314 case Mips::ADDS_S_B:
13315 case Mips::ADDS_S_D:
13316 case Mips::ADDS_S_H:
13317 case Mips::ADDS_S_W:
13318 case Mips::ADDS_U_B:
13319 case Mips::ADDS_U_D:
13320 case Mips::ADDS_U_H:
13321 case Mips::ADDS_U_W:
13322 case Mips::ADDV_B:
13323 case Mips::ADDV_D:
13324 case Mips::ADDV_H:
13325 case Mips::ADDV_W:
13326 case Mips::ADD_A_B:
13327 case Mips::ADD_A_D:
13328 case Mips::ADD_A_H:
13329 case Mips::ADD_A_W:
13330 case Mips::AND_V:
13331 case Mips::ASUB_S_B:
13332 case Mips::ASUB_S_D:
13333 case Mips::ASUB_S_H:
13334 case Mips::ASUB_S_W:
13335 case Mips::ASUB_U_B:
13336 case Mips::ASUB_U_D:
13337 case Mips::ASUB_U_H:
13338 case Mips::ASUB_U_W:
13339 case Mips::AVER_S_B:
13340 case Mips::AVER_S_D:
13341 case Mips::AVER_S_H:
13342 case Mips::AVER_S_W:
13343 case Mips::AVER_U_B:
13344 case Mips::AVER_U_D:
13345 case Mips::AVER_U_H:
13346 case Mips::AVER_U_W:
13347 case Mips::AVE_S_B:
13348 case Mips::AVE_S_D:
13349 case Mips::AVE_S_H:
13350 case Mips::AVE_S_W:
13351 case Mips::AVE_U_B:
13352 case Mips::AVE_U_D:
13353 case Mips::AVE_U_H:
13354 case Mips::AVE_U_W:
13355 case Mips::BCLR_B:
13356 case Mips::BCLR_D:
13357 case Mips::BCLR_H:
13358 case Mips::BCLR_W:
13359 case Mips::BNEG_B:
13360 case Mips::BNEG_D:
13361 case Mips::BNEG_H:
13362 case Mips::BNEG_W:
13363 case Mips::BSET_B:
13364 case Mips::BSET_D:
13365 case Mips::BSET_H:
13366 case Mips::BSET_W:
13367 case Mips::CEQ_B:
13368 case Mips::CEQ_D:
13369 case Mips::CEQ_H:
13370 case Mips::CEQ_W:
13371 case Mips::CLE_S_B:
13372 case Mips::CLE_S_D:
13373 case Mips::CLE_S_H:
13374 case Mips::CLE_S_W:
13375 case Mips::CLE_U_B:
13376 case Mips::CLE_U_D:
13377 case Mips::CLE_U_H:
13378 case Mips::CLE_U_W:
13379 case Mips::CLT_S_B:
13380 case Mips::CLT_S_D:
13381 case Mips::CLT_S_H:
13382 case Mips::CLT_S_W:
13383 case Mips::CLT_U_B:
13384 case Mips::CLT_U_D:
13385 case Mips::CLT_U_H:
13386 case Mips::CLT_U_W:
13387 case Mips::DIV_S_B:
13388 case Mips::DIV_S_D:
13389 case Mips::DIV_S_H:
13390 case Mips::DIV_S_W:
13391 case Mips::DIV_U_B:
13392 case Mips::DIV_U_D:
13393 case Mips::DIV_U_H:
13394 case Mips::DIV_U_W:
13395 case Mips::DOTP_S_D:
13396 case Mips::DOTP_S_H:
13397 case Mips::DOTP_S_W:
13398 case Mips::DOTP_U_D:
13399 case Mips::DOTP_U_H:
13400 case Mips::DOTP_U_W:
13401 case Mips::FADD_D:
13402 case Mips::FADD_W:
13403 case Mips::FCAF_D:
13404 case Mips::FCAF_W:
13405 case Mips::FCEQ_D:
13406 case Mips::FCEQ_W:
13407 case Mips::FCLE_D:
13408 case Mips::FCLE_W:
13409 case Mips::FCLT_D:
13410 case Mips::FCLT_W:
13411 case Mips::FCNE_D:
13412 case Mips::FCNE_W:
13413 case Mips::FCOR_D:
13414 case Mips::FCOR_W:
13415 case Mips::FCUEQ_D:
13416 case Mips::FCUEQ_W:
13417 case Mips::FCULE_D:
13418 case Mips::FCULE_W:
13419 case Mips::FCULT_D:
13420 case Mips::FCULT_W:
13421 case Mips::FCUNE_D:
13422 case Mips::FCUNE_W:
13423 case Mips::FCUN_D:
13424 case Mips::FCUN_W:
13425 case Mips::FDIV_D:
13426 case Mips::FDIV_W:
13427 case Mips::FEXDO_H:
13428 case Mips::FEXDO_W:
13429 case Mips::FEXP2_D:
13430 case Mips::FEXP2_W:
13431 case Mips::FMAX_A_D:
13432 case Mips::FMAX_A_W:
13433 case Mips::FMAX_D:
13434 case Mips::FMAX_W:
13435 case Mips::FMIN_A_D:
13436 case Mips::FMIN_A_W:
13437 case Mips::FMIN_D:
13438 case Mips::FMIN_W:
13439 case Mips::FMUL_D:
13440 case Mips::FMUL_W:
13441 case Mips::FSAF_D:
13442 case Mips::FSAF_W:
13443 case Mips::FSEQ_D:
13444 case Mips::FSEQ_W:
13445 case Mips::FSLE_D:
13446 case Mips::FSLE_W:
13447 case Mips::FSLT_D:
13448 case Mips::FSLT_W:
13449 case Mips::FSNE_D:
13450 case Mips::FSNE_W:
13451 case Mips::FSOR_D:
13452 case Mips::FSOR_W:
13453 case Mips::FSUB_D:
13454 case Mips::FSUB_W:
13455 case Mips::FSUEQ_D:
13456 case Mips::FSUEQ_W:
13457 case Mips::FSULE_D:
13458 case Mips::FSULE_W:
13459 case Mips::FSULT_D:
13460 case Mips::FSULT_W:
13461 case Mips::FSUNE_D:
13462 case Mips::FSUNE_W:
13463 case Mips::FSUN_D:
13464 case Mips::FSUN_W:
13465 case Mips::FTQ_H:
13466 case Mips::FTQ_W:
13467 case Mips::HADD_S_D:
13468 case Mips::HADD_S_H:
13469 case Mips::HADD_S_W:
13470 case Mips::HADD_U_D:
13471 case Mips::HADD_U_H:
13472 case Mips::HADD_U_W:
13473 case Mips::HSUB_S_D:
13474 case Mips::HSUB_S_H:
13475 case Mips::HSUB_S_W:
13476 case Mips::HSUB_U_D:
13477 case Mips::HSUB_U_H:
13478 case Mips::HSUB_U_W:
13479 case Mips::ILVEV_B:
13480 case Mips::ILVEV_D:
13481 case Mips::ILVEV_H:
13482 case Mips::ILVEV_W:
13483 case Mips::ILVL_B:
13484 case Mips::ILVL_D:
13485 case Mips::ILVL_H:
13486 case Mips::ILVL_W:
13487 case Mips::ILVOD_B:
13488 case Mips::ILVOD_D:
13489 case Mips::ILVOD_H:
13490 case Mips::ILVOD_W:
13491 case Mips::ILVR_B:
13492 case Mips::ILVR_D:
13493 case Mips::ILVR_H:
13494 case Mips::ILVR_W:
13495 case Mips::MAX_A_B:
13496 case Mips::MAX_A_D:
13497 case Mips::MAX_A_H:
13498 case Mips::MAX_A_W:
13499 case Mips::MAX_S_B:
13500 case Mips::MAX_S_D:
13501 case Mips::MAX_S_H:
13502 case Mips::MAX_S_W:
13503 case Mips::MAX_U_B:
13504 case Mips::MAX_U_D:
13505 case Mips::MAX_U_H:
13506 case Mips::MAX_U_W:
13507 case Mips::MIN_A_B:
13508 case Mips::MIN_A_D:
13509 case Mips::MIN_A_H:
13510 case Mips::MIN_A_W:
13511 case Mips::MIN_S_B:
13512 case Mips::MIN_S_D:
13513 case Mips::MIN_S_H:
13514 case Mips::MIN_S_W:
13515 case Mips::MIN_U_B:
13516 case Mips::MIN_U_D:
13517 case Mips::MIN_U_H:
13518 case Mips::MIN_U_W:
13519 case Mips::MOD_S_B:
13520 case Mips::MOD_S_D:
13521 case Mips::MOD_S_H:
13522 case Mips::MOD_S_W:
13523 case Mips::MOD_U_B:
13524 case Mips::MOD_U_D:
13525 case Mips::MOD_U_H:
13526 case Mips::MOD_U_W:
13527 case Mips::MULR_Q_H:
13528 case Mips::MULR_Q_W:
13529 case Mips::MULV_B:
13530 case Mips::MULV_D:
13531 case Mips::MULV_H:
13532 case Mips::MULV_W:
13533 case Mips::MUL_Q_H:
13534 case Mips::MUL_Q_W:
13535 case Mips::NOR_V:
13536 case Mips::OR_V:
13537 case Mips::PCKEV_B:
13538 case Mips::PCKEV_D:
13539 case Mips::PCKEV_H:
13540 case Mips::PCKEV_W:
13541 case Mips::PCKOD_B:
13542 case Mips::PCKOD_D:
13543 case Mips::PCKOD_H:
13544 case Mips::PCKOD_W:
13545 case Mips::SLL_B:
13546 case Mips::SLL_D:
13547 case Mips::SLL_H:
13548 case Mips::SLL_W:
13549 case Mips::SRAR_B:
13550 case Mips::SRAR_D:
13551 case Mips::SRAR_H:
13552 case Mips::SRAR_W:
13553 case Mips::SRA_B:
13554 case Mips::SRA_D:
13555 case Mips::SRA_H:
13556 case Mips::SRA_W:
13557 case Mips::SRLR_B:
13558 case Mips::SRLR_D:
13559 case Mips::SRLR_H:
13560 case Mips::SRLR_W:
13561 case Mips::SRL_B:
13562 case Mips::SRL_D:
13563 case Mips::SRL_H:
13564 case Mips::SRL_W:
13565 case Mips::SUBSUS_U_B:
13566 case Mips::SUBSUS_U_D:
13567 case Mips::SUBSUS_U_H:
13568 case Mips::SUBSUS_U_W:
13569 case Mips::SUBSUU_S_B:
13570 case Mips::SUBSUU_S_D:
13571 case Mips::SUBSUU_S_H:
13572 case Mips::SUBSUU_S_W:
13573 case Mips::SUBS_S_B:
13574 case Mips::SUBS_S_D:
13575 case Mips::SUBS_S_H:
13576 case Mips::SUBS_S_W:
13577 case Mips::SUBS_U_B:
13578 case Mips::SUBS_U_D:
13579 case Mips::SUBS_U_H:
13580 case Mips::SUBS_U_W:
13581 case Mips::SUBV_B:
13582 case Mips::SUBV_D:
13583 case Mips::SUBV_H:
13584 case Mips::SUBV_W:
13585 case Mips::XOR_V: {
13586 switch (OpNum) {
13587 case 2:
13588 // op: wt
13589 return 16;
13590 case 1:
13591 // op: ws
13592 return 11;
13593 case 0:
13594 // op: wd
13595 return 6;
13596 }
13597 break;
13598 }
13599 case Mips::MADDF_D:
13600 case Mips::MADDF_S:
13601 case Mips::MSUBF_D:
13602 case Mips::MSUBF_S:
13603 case Mips::SEL_D:
13604 case Mips::SEL_S: {
13605 switch (OpNum) {
13606 case 3:
13607 // op: ft
13608 return 16;
13609 case 2:
13610 // op: fs
13611 return 11;
13612 case 0:
13613 // op: fd
13614 return 6;
13615 }
13616 break;
13617 }
13618 case Mips::MADD_D32_MM:
13619 case Mips::MADD_S_MM:
13620 case Mips::MSUB_D32_MM:
13621 case Mips::MSUB_S_MM:
13622 case Mips::NMADD_D32_MM:
13623 case Mips::NMADD_S_MM:
13624 case Mips::NMSUB_D32_MM:
13625 case Mips::NMSUB_S_MM: {
13626 switch (OpNum) {
13627 case 3:
13628 // op: ft
13629 return 21;
13630 case 2:
13631 // op: fs
13632 return 16;
13633 case 0:
13634 // op: fd
13635 return 11;
13636 case 1:
13637 // op: fr
13638 return 6;
13639 }
13640 break;
13641 }
13642 case Mips::MADDF_D_MMR6:
13643 case Mips::MADDF_S_MMR6:
13644 case Mips::MSUBF_D_MMR6:
13645 case Mips::MSUBF_S_MMR6:
13646 case Mips::SEL_D_MMR6:
13647 case Mips::SEL_S_MMR6: {
13648 switch (OpNum) {
13649 case 3:
13650 // op: ft
13651 return 21;
13652 case 2:
13653 // op: fs
13654 return 16;
13655 case 0:
13656 // op: fd
13657 return 11;
13658 }
13659 break;
13660 }
13661 case Mips::INSERT_B:
13662 case Mips::INSERT_D:
13663 case Mips::INSERT_H:
13664 case Mips::INSERT_W: {
13665 switch (OpNum) {
13666 case 3:
13667 // op: n
13668 return 16;
13669 case 2:
13670 // op: rs
13671 return 11;
13672 case 0:
13673 // op: wd
13674 return 6;
13675 }
13676 break;
13677 }
13678 case Mips::SLDI_B:
13679 case Mips::SLDI_D:
13680 case Mips::SLDI_H:
13681 case Mips::SLDI_W: {
13682 switch (OpNum) {
13683 case 3:
13684 // op: n
13685 return 16;
13686 case 2:
13687 // op: ws
13688 return 11;
13689 case 0:
13690 // op: wd
13691 return 6;
13692 }
13693 break;
13694 }
13695 case Mips::SLD_B:
13696 case Mips::SLD_D:
13697 case Mips::SLD_H:
13698 case Mips::SLD_W: {
13699 switch (OpNum) {
13700 case 3:
13701 // op: rt
13702 return 16;
13703 case 2:
13704 // op: ws
13705 return 11;
13706 case 0:
13707 // op: wd
13708 return 6;
13709 }
13710 break;
13711 }
13712 case Mips::MOVEP_MMR6: {
13713 switch (OpNum) {
13714 case 3:
13715 // op: rt
13716 return 4;
13717 case 2:
13718 // op: rs
13719 return 0;
13720 }
13721 break;
13722 }
13723 case Mips::MOVEP_MM: {
13724 switch (OpNum) {
13725 case 3:
13726 // op: rt
13727 return 4;
13728 case 2:
13729 // op: rs
13730 return 1;
13731 }
13732 break;
13733 }
13734 case Mips::BMNZI_B:
13735 case Mips::BMZI_B:
13736 case Mips::BSELI_B: {
13737 switch (OpNum) {
13738 case 3:
13739 // op: u8
13740 return 16;
13741 case 2:
13742 // op: ws
13743 return 11;
13744 case 0:
13745 // op: wd
13746 return 6;
13747 }
13748 break;
13749 }
13750 case Mips::BINSL_B:
13751 case Mips::BINSL_D:
13752 case Mips::BINSL_H:
13753 case Mips::BINSL_W:
13754 case Mips::BINSR_B:
13755 case Mips::BINSR_D:
13756 case Mips::BINSR_H:
13757 case Mips::BINSR_W:
13758 case Mips::BMNZ_V:
13759 case Mips::BMZ_V:
13760 case Mips::BSEL_V:
13761 case Mips::DPADD_S_D:
13762 case Mips::DPADD_S_H:
13763 case Mips::DPADD_S_W:
13764 case Mips::DPADD_U_D:
13765 case Mips::DPADD_U_H:
13766 case Mips::DPADD_U_W:
13767 case Mips::DPSUB_S_D:
13768 case Mips::DPSUB_S_H:
13769 case Mips::DPSUB_S_W:
13770 case Mips::DPSUB_U_D:
13771 case Mips::DPSUB_U_H:
13772 case Mips::DPSUB_U_W:
13773 case Mips::FMADD_D:
13774 case Mips::FMADD_W:
13775 case Mips::FMSUB_D:
13776 case Mips::FMSUB_W:
13777 case Mips::MADDR_Q_H:
13778 case Mips::MADDR_Q_W:
13779 case Mips::MADDV_B:
13780 case Mips::MADDV_D:
13781 case Mips::MADDV_H:
13782 case Mips::MADDV_W:
13783 case Mips::MADD_Q_H:
13784 case Mips::MADD_Q_W:
13785 case Mips::MSUBR_Q_H:
13786 case Mips::MSUBR_Q_W:
13787 case Mips::MSUBV_B:
13788 case Mips::MSUBV_D:
13789 case Mips::MSUBV_H:
13790 case Mips::MSUBV_W:
13791 case Mips::MSUB_Q_H:
13792 case Mips::MSUB_Q_W:
13793 case Mips::VSHF_B:
13794 case Mips::VSHF_D:
13795 case Mips::VSHF_H:
13796 case Mips::VSHF_W: {
13797 switch (OpNum) {
13798 case 3:
13799 // op: wt
13800 return 16;
13801 case 2:
13802 // op: ws
13803 return 11;
13804 case 0:
13805 // op: wd
13806 return 6;
13807 }
13808 break;
13809 }
13810 }
13811 std::string msg;
13812 raw_string_ostream Msg(msg);
13813 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
13814 report_fatal_error(Msg.str().c_str());
13815}
13816
13817#endif // GET_OPERAND_BIT_OFFSET
13818
13819