1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass NVPTXMCRegisterClasses[];
17
18namespace NVPTX {
19enum {
20 NoRegister,
21 VRDepot = 1,
22 ENVREG0 = 2,
23 ENVREG1 = 3,
24 ENVREG2 = 4,
25 ENVREG3 = 5,
26 ENVREG4 = 6,
27 ENVREG5 = 7,
28 ENVREG6 = 8,
29 ENVREG7 = 9,
30 ENVREG8 = 10,
31 ENVREG9 = 11,
32 ENVREG10 = 12,
33 ENVREG11 = 13,
34 ENVREG12 = 14,
35 ENVREG13 = 15,
36 ENVREG14 = 16,
37 ENVREG15 = 17,
38 ENVREG16 = 18,
39 ENVREG17 = 19,
40 ENVREG18 = 20,
41 ENVREG19 = 21,
42 ENVREG20 = 22,
43 ENVREG21 = 23,
44 ENVREG22 = 24,
45 ENVREG23 = 25,
46 ENVREG24 = 26,
47 ENVREG25 = 27,
48 ENVREG26 = 28,
49 ENVREG27 = 29,
50 ENVREG28 = 30,
51 ENVREG29 = 31,
52 ENVREG30 = 32,
53 ENVREG31 = 33,
54 F0 = 34,
55 F1 = 35,
56 F2 = 36,
57 F3 = 37,
58 F4 = 38,
59 FL0 = 39,
60 FL1 = 40,
61 FL2 = 41,
62 FL3 = 42,
63 FL4 = 43,
64 H0 = 44,
65 H1 = 45,
66 H2 = 46,
67 H3 = 47,
68 H4 = 48,
69 HH0 = 49,
70 HH1 = 50,
71 HH2 = 51,
72 HH3 = 52,
73 HH4 = 53,
74 P0 = 54,
75 P1 = 55,
76 P2 = 56,
77 P3 = 57,
78 P4 = 58,
79 R0 = 59,
80 R1 = 60,
81 R2 = 61,
82 R3 = 62,
83 R4 = 63,
84 RL0 = 64,
85 RL1 = 65,
86 RL2 = 66,
87 RL3 = 67,
88 RL4 = 68,
89 RQ0 = 69,
90 RQ1 = 70,
91 RQ2 = 71,
92 RQ3 = 72,
93 RQ4 = 73,
94 RS0 = 74,
95 RS1 = 75,
96 RS2 = 76,
97 RS3 = 77,
98 RS4 = 78,
99 VRFrame32 = 79,
100 VRFrame64 = 80,
101 VRFrameLocal32 = 81,
102 VRFrameLocal64 = 82,
103 da0 = 83,
104 da1 = 84,
105 da2 = 85,
106 da3 = 86,
107 da4 = 87,
108 fa0 = 88,
109 fa1 = 89,
110 fa2 = 90,
111 fa3 = 91,
112 fa4 = 92,
113 ia0 = 93,
114 ia1 = 94,
115 ia2 = 95,
116 ia3 = 96,
117 ia4 = 97,
118 la0 = 98,
119 la1 = 99,
120 la2 = 100,
121 la3 = 101,
122 la4 = 102,
123 NUM_TARGET_REGS // 103
124};
125} // end namespace NVPTX
126
127// Register classes
128
129namespace NVPTX {
130enum {
131 Int1RegsRegClassID = 0,
132 Int16RegsRegClassID = 1,
133 SpecialRegsRegClassID = 2,
134 Int32RegsRegClassID = 3,
135 Float32ArgRegsRegClassID = 4,
136 Float32RegsRegClassID = 5,
137 Int32ArgRegsRegClassID = 6,
138 Int32Regs_and_SpecialRegsRegClassID = 7,
139 Int64RegsRegClassID = 8,
140 Float64ArgRegsRegClassID = 9,
141 Float64RegsRegClassID = 10,
142 Int64ArgRegsRegClassID = 11,
143 Int128RegsRegClassID = 12,
144
145};
146} // end namespace NVPTX
147
148// Register pressure sets enum.
149namespace NVPTX {
150enum RegisterPressureSets {
151 Int32Regs_and_SpecialRegs = 0,
152 Int1Regs = 1,
153 Int16Regs = 2,
154 Float32ArgRegs = 3,
155 Float32Regs = 4,
156 Int32ArgRegs = 5,
157 Float64ArgRegs = 6,
158 Float64Regs = 7,
159 Int64ArgRegs = 8,
160 Int128Regs = 9,
161 Int32Regs = 10,
162 Int64Regs = 11,
163 SpecialRegs = 12,
164 SpecialRegs_with_Int32Regs = 13,
165};
166} // end namespace NVPTX
167
168} // end namespace llvm
169
170#endif // GET_REGINFO_ENUM
171
172/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
173|* *|
174|* MC Register Information *|
175|* *|
176|* Automatically generated file, do not edit! *|
177|* *|
178\*===----------------------------------------------------------------------===*/
179
180
181#ifdef GET_REGINFO_MC_DESC
182#undef GET_REGINFO_MC_DESC
183
184namespace llvm {
185
186extern const int16_t NVPTXRegDiffLists[] = {
187 /* 0 */ 0,
188};
189
190extern const LaneBitmask NVPTXLaneMaskLists[] = {
191 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
192};
193
194extern const uint16_t NVPTXSubRegIdxLists[] = {
195 /* 0 */ 0,
196};
197
198
199#ifdef __GNUC__
200#pragma GCC diagnostic push
201#pragma GCC diagnostic ignored "-Woverlength-strings"
202#endif
203extern const char NVPTXRegStrings[] = {
204 /* 0 */ "ENVREG10\0"
205 /* 9 */ "ENVREG20\0"
206 /* 18 */ "ENVREG30\0"
207 /* 27 */ "F0\0"
208 /* 30 */ "ENVREG0\0"
209 /* 38 */ "HH0\0"
210 /* 42 */ "FL0\0"
211 /* 46 */ "RL0\0"
212 /* 50 */ "P0\0"
213 /* 53 */ "RQ0\0"
214 /* 57 */ "R0\0"
215 /* 60 */ "RS0\0"
216 /* 64 */ "da0\0"
217 /* 68 */ "fa0\0"
218 /* 72 */ "ia0\0"
219 /* 76 */ "la0\0"
220 /* 80 */ "ENVREG11\0"
221 /* 89 */ "ENVREG21\0"
222 /* 98 */ "ENVREG31\0"
223 /* 107 */ "F1\0"
224 /* 110 */ "ENVREG1\0"
225 /* 118 */ "HH1\0"
226 /* 122 */ "FL1\0"
227 /* 126 */ "RL1\0"
228 /* 130 */ "P1\0"
229 /* 133 */ "RQ1\0"
230 /* 137 */ "R1\0"
231 /* 140 */ "RS1\0"
232 /* 144 */ "da1\0"
233 /* 148 */ "fa1\0"
234 /* 152 */ "ia1\0"
235 /* 156 */ "la1\0"
236 /* 160 */ "ENVREG12\0"
237 /* 169 */ "ENVREG22\0"
238 /* 178 */ "VRFrame32\0"
239 /* 188 */ "VRFrameLocal32\0"
240 /* 203 */ "F2\0"
241 /* 206 */ "ENVREG2\0"
242 /* 214 */ "HH2\0"
243 /* 218 */ "FL2\0"
244 /* 222 */ "RL2\0"
245 /* 226 */ "P2\0"
246 /* 229 */ "RQ2\0"
247 /* 233 */ "R2\0"
248 /* 236 */ "RS2\0"
249 /* 240 */ "da2\0"
250 /* 244 */ "fa2\0"
251 /* 248 */ "ia2\0"
252 /* 252 */ "la2\0"
253 /* 256 */ "ENVREG13\0"
254 /* 265 */ "ENVREG23\0"
255 /* 274 */ "F3\0"
256 /* 277 */ "ENVREG3\0"
257 /* 285 */ "HH3\0"
258 /* 289 */ "FL3\0"
259 /* 293 */ "RL3\0"
260 /* 297 */ "P3\0"
261 /* 300 */ "RQ3\0"
262 /* 304 */ "R3\0"
263 /* 307 */ "RS3\0"
264 /* 311 */ "da3\0"
265 /* 315 */ "fa3\0"
266 /* 319 */ "ia3\0"
267 /* 323 */ "la3\0"
268 /* 327 */ "ENVREG14\0"
269 /* 336 */ "ENVREG24\0"
270 /* 345 */ "VRFrame64\0"
271 /* 355 */ "VRFrameLocal64\0"
272 /* 370 */ "F4\0"
273 /* 373 */ "ENVREG4\0"
274 /* 381 */ "HH4\0"
275 /* 385 */ "FL4\0"
276 /* 389 */ "RL4\0"
277 /* 393 */ "P4\0"
278 /* 396 */ "RQ4\0"
279 /* 400 */ "R4\0"
280 /* 403 */ "RS4\0"
281 /* 407 */ "da4\0"
282 /* 411 */ "fa4\0"
283 /* 415 */ "ia4\0"
284 /* 419 */ "la4\0"
285 /* 423 */ "ENVREG15\0"
286 /* 432 */ "ENVREG25\0"
287 /* 441 */ "ENVREG5\0"
288 /* 449 */ "ENVREG16\0"
289 /* 458 */ "ENVREG26\0"
290 /* 467 */ "ENVREG6\0"
291 /* 475 */ "ENVREG17\0"
292 /* 484 */ "ENVREG27\0"
293 /* 493 */ "ENVREG7\0"
294 /* 501 */ "ENVREG18\0"
295 /* 510 */ "ENVREG28\0"
296 /* 519 */ "ENVREG8\0"
297 /* 527 */ "ENVREG19\0"
298 /* 536 */ "ENVREG29\0"
299 /* 545 */ "ENVREG9\0"
300 /* 553 */ "VRDepot\0"
301};
302#ifdef __GNUC__
303#pragma GCC diagnostic pop
304#endif
305
306extern const MCRegisterDesc NVPTXRegDesc[] = { // Descriptors
307 { 8, 0, 0, 0, 0, 0, 0 },
308 { 553, 0, 0, 0, 0, 0, 0 },
309 { 30, 0, 0, 0, 1, 0, 0 },
310 { 110, 0, 0, 0, 2, 0, 0 },
311 { 206, 0, 0, 0, 3, 0, 0 },
312 { 277, 0, 0, 0, 4, 0, 0 },
313 { 373, 0, 0, 0, 5, 0, 0 },
314 { 441, 0, 0, 0, 6, 0, 0 },
315 { 467, 0, 0, 0, 7, 0, 0 },
316 { 493, 0, 0, 0, 8, 0, 0 },
317 { 519, 0, 0, 0, 9, 0, 0 },
318 { 545, 0, 0, 0, 10, 0, 0 },
319 { 0, 0, 0, 0, 11, 0, 0 },
320 { 80, 0, 0, 0, 12, 0, 0 },
321 { 160, 0, 0, 0, 13, 0, 0 },
322 { 256, 0, 0, 0, 14, 0, 0 },
323 { 327, 0, 0, 0, 15, 0, 0 },
324 { 423, 0, 0, 0, 16, 0, 0 },
325 { 449, 0, 0, 0, 17, 0, 0 },
326 { 475, 0, 0, 0, 18, 0, 0 },
327 { 501, 0, 0, 0, 19, 0, 0 },
328 { 527, 0, 0, 0, 20, 0, 0 },
329 { 9, 0, 0, 0, 21, 0, 0 },
330 { 89, 0, 0, 0, 22, 0, 0 },
331 { 169, 0, 0, 0, 23, 0, 0 },
332 { 265, 0, 0, 0, 24, 0, 0 },
333 { 336, 0, 0, 0, 25, 0, 0 },
334 { 432, 0, 0, 0, 26, 0, 0 },
335 { 458, 0, 0, 0, 27, 0, 0 },
336 { 484, 0, 0, 0, 28, 0, 0 },
337 { 510, 0, 0, 0, 29, 0, 0 },
338 { 536, 0, 0, 0, 30, 0, 0 },
339 { 18, 0, 0, 0, 31, 0, 0 },
340 { 98, 0, 0, 0, 32, 0, 0 },
341 { 27, 0, 0, 0, 33, 0, 0 },
342 { 107, 0, 0, 0, 34, 0, 0 },
343 { 203, 0, 0, 0, 35, 0, 0 },
344 { 274, 0, 0, 0, 36, 0, 0 },
345 { 370, 0, 0, 0, 37, 0, 0 },
346 { 42, 0, 0, 0, 38, 0, 0 },
347 { 122, 0, 0, 0, 39, 0, 0 },
348 { 218, 0, 0, 0, 40, 0, 0 },
349 { 289, 0, 0, 0, 41, 0, 0 },
350 { 385, 0, 0, 0, 42, 0, 0 },
351 { 39, 0, 0, 0, 43, 0, 0 },
352 { 119, 0, 0, 0, 44, 0, 0 },
353 { 215, 0, 0, 0, 45, 0, 0 },
354 { 286, 0, 0, 0, 46, 0, 0 },
355 { 382, 0, 0, 0, 47, 0, 0 },
356 { 38, 0, 0, 0, 48, 0, 0 },
357 { 118, 0, 0, 0, 49, 0, 0 },
358 { 214, 0, 0, 0, 50, 0, 0 },
359 { 285, 0, 0, 0, 51, 0, 0 },
360 { 381, 0, 0, 0, 52, 0, 0 },
361 { 50, 0, 0, 0, 53, 0, 0 },
362 { 130, 0, 0, 0, 54, 0, 0 },
363 { 226, 0, 0, 0, 55, 0, 0 },
364 { 297, 0, 0, 0, 56, 0, 0 },
365 { 393, 0, 0, 0, 57, 0, 0 },
366 { 57, 0, 0, 0, 58, 0, 0 },
367 { 137, 0, 0, 0, 59, 0, 0 },
368 { 233, 0, 0, 0, 60, 0, 0 },
369 { 304, 0, 0, 0, 61, 0, 0 },
370 { 400, 0, 0, 0, 62, 0, 0 },
371 { 46, 0, 0, 0, 63, 0, 0 },
372 { 126, 0, 0, 0, 64, 0, 0 },
373 { 222, 0, 0, 0, 65, 0, 0 },
374 { 293, 0, 0, 0, 66, 0, 0 },
375 { 389, 0, 0, 0, 67, 0, 0 },
376 { 53, 0, 0, 0, 68, 0, 0 },
377 { 133, 0, 0, 0, 69, 0, 0 },
378 { 229, 0, 0, 0, 70, 0, 0 },
379 { 300, 0, 0, 0, 71, 0, 0 },
380 { 396, 0, 0, 0, 72, 0, 0 },
381 { 60, 0, 0, 0, 73, 0, 0 },
382 { 140, 0, 0, 0, 74, 0, 0 },
383 { 236, 0, 0, 0, 75, 0, 0 },
384 { 307, 0, 0, 0, 76, 0, 0 },
385 { 403, 0, 0, 0, 77, 0, 0 },
386 { 178, 0, 0, 0, 78, 0, 0 },
387 { 345, 0, 0, 0, 79, 0, 0 },
388 { 188, 0, 0, 0, 80, 0, 0 },
389 { 355, 0, 0, 0, 81, 0, 0 },
390 { 64, 0, 0, 0, 82, 0, 0 },
391 { 144, 0, 0, 0, 83, 0, 0 },
392 { 240, 0, 0, 0, 84, 0, 0 },
393 { 311, 0, 0, 0, 85, 0, 0 },
394 { 407, 0, 0, 0, 86, 0, 0 },
395 { 68, 0, 0, 0, 87, 0, 0 },
396 { 148, 0, 0, 0, 88, 0, 0 },
397 { 244, 0, 0, 0, 89, 0, 0 },
398 { 315, 0, 0, 0, 90, 0, 0 },
399 { 411, 0, 0, 0, 91, 0, 0 },
400 { 72, 0, 0, 0, 92, 0, 0 },
401 { 152, 0, 0, 0, 93, 0, 0 },
402 { 248, 0, 0, 0, 94, 0, 0 },
403 { 319, 0, 0, 0, 95, 0, 0 },
404 { 415, 0, 0, 0, 96, 0, 0 },
405 { 76, 0, 0, 0, 97, 0, 0 },
406 { 156, 0, 0, 0, 98, 0, 0 },
407 { 252, 0, 0, 0, 99, 0, 0 },
408 { 323, 0, 0, 0, 100, 0, 0 },
409 { 419, 0, 0, 0, 101, 0, 0 },
410};
411
412extern const MCPhysReg NVPTXRegUnitRoots[][2] = {
413 { NVPTX::VRDepot },
414 { NVPTX::ENVREG0 },
415 { NVPTX::ENVREG1 },
416 { NVPTX::ENVREG2 },
417 { NVPTX::ENVREG3 },
418 { NVPTX::ENVREG4 },
419 { NVPTX::ENVREG5 },
420 { NVPTX::ENVREG6 },
421 { NVPTX::ENVREG7 },
422 { NVPTX::ENVREG8 },
423 { NVPTX::ENVREG9 },
424 { NVPTX::ENVREG10 },
425 { NVPTX::ENVREG11 },
426 { NVPTX::ENVREG12 },
427 { NVPTX::ENVREG13 },
428 { NVPTX::ENVREG14 },
429 { NVPTX::ENVREG15 },
430 { NVPTX::ENVREG16 },
431 { NVPTX::ENVREG17 },
432 { NVPTX::ENVREG18 },
433 { NVPTX::ENVREG19 },
434 { NVPTX::ENVREG20 },
435 { NVPTX::ENVREG21 },
436 { NVPTX::ENVREG22 },
437 { NVPTX::ENVREG23 },
438 { NVPTX::ENVREG24 },
439 { NVPTX::ENVREG25 },
440 { NVPTX::ENVREG26 },
441 { NVPTX::ENVREG27 },
442 { NVPTX::ENVREG28 },
443 { NVPTX::ENVREG29 },
444 { NVPTX::ENVREG30 },
445 { NVPTX::ENVREG31 },
446 { NVPTX::F0 },
447 { NVPTX::F1 },
448 { NVPTX::F2 },
449 { NVPTX::F3 },
450 { NVPTX::F4 },
451 { NVPTX::FL0 },
452 { NVPTX::FL1 },
453 { NVPTX::FL2 },
454 { NVPTX::FL3 },
455 { NVPTX::FL4 },
456 { NVPTX::H0 },
457 { NVPTX::H1 },
458 { NVPTX::H2 },
459 { NVPTX::H3 },
460 { NVPTX::H4 },
461 { NVPTX::HH0 },
462 { NVPTX::HH1 },
463 { NVPTX::HH2 },
464 { NVPTX::HH3 },
465 { NVPTX::HH4 },
466 { NVPTX::P0 },
467 { NVPTX::P1 },
468 { NVPTX::P2 },
469 { NVPTX::P3 },
470 { NVPTX::P4 },
471 { NVPTX::R0 },
472 { NVPTX::R1 },
473 { NVPTX::R2 },
474 { NVPTX::R3 },
475 { NVPTX::R4 },
476 { NVPTX::RL0 },
477 { NVPTX::RL1 },
478 { NVPTX::RL2 },
479 { NVPTX::RL3 },
480 { NVPTX::RL4 },
481 { NVPTX::RQ0 },
482 { NVPTX::RQ1 },
483 { NVPTX::RQ2 },
484 { NVPTX::RQ3 },
485 { NVPTX::RQ4 },
486 { NVPTX::RS0 },
487 { NVPTX::RS1 },
488 { NVPTX::RS2 },
489 { NVPTX::RS3 },
490 { NVPTX::RS4 },
491 { NVPTX::VRFrame32 },
492 { NVPTX::VRFrame64 },
493 { NVPTX::VRFrameLocal32 },
494 { NVPTX::VRFrameLocal64 },
495 { NVPTX::da0 },
496 { NVPTX::da1 },
497 { NVPTX::da2 },
498 { NVPTX::da3 },
499 { NVPTX::da4 },
500 { NVPTX::fa0 },
501 { NVPTX::fa1 },
502 { NVPTX::fa2 },
503 { NVPTX::fa3 },
504 { NVPTX::fa4 },
505 { NVPTX::ia0 },
506 { NVPTX::ia1 },
507 { NVPTX::ia2 },
508 { NVPTX::ia3 },
509 { NVPTX::ia4 },
510 { NVPTX::la0 },
511 { NVPTX::la1 },
512 { NVPTX::la2 },
513 { NVPTX::la3 },
514 { NVPTX::la4 },
515};
516
517namespace { // Register classes...
518 // Int1Regs Register Class...
519 const MCPhysReg Int1Regs[] = {
520 NVPTX::P0, NVPTX::P1, NVPTX::P2, NVPTX::P3, NVPTX::P4,
521 };
522
523 // Int1Regs Bit set.
524 const uint8_t Int1RegsBits[] = {
525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07,
526 };
527
528 // Int16Regs Register Class...
529 const MCPhysReg Int16Regs[] = {
530 NVPTX::RS0, NVPTX::RS1, NVPTX::RS2, NVPTX::RS3, NVPTX::RS4,
531 };
532
533 // Int16Regs Bit set.
534 const uint8_t Int16RegsBits[] = {
535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
536 };
537
538 // SpecialRegs Register Class...
539 const MCPhysReg SpecialRegs[] = {
540 NVPTX::VRFrame32, NVPTX::VRFrameLocal32, NVPTX::VRDepot, NVPTX::ENVREG0, NVPTX::ENVREG1, NVPTX::ENVREG2, NVPTX::ENVREG3, NVPTX::ENVREG4, NVPTX::ENVREG5, NVPTX::ENVREG6, NVPTX::ENVREG7, NVPTX::ENVREG8, NVPTX::ENVREG9, NVPTX::ENVREG10, NVPTX::ENVREG11, NVPTX::ENVREG12, NVPTX::ENVREG13, NVPTX::ENVREG14, NVPTX::ENVREG15, NVPTX::ENVREG16, NVPTX::ENVREG17, NVPTX::ENVREG18, NVPTX::ENVREG19, NVPTX::ENVREG20, NVPTX::ENVREG21, NVPTX::ENVREG22, NVPTX::ENVREG23, NVPTX::ENVREG24, NVPTX::ENVREG25, NVPTX::ENVREG26, NVPTX::ENVREG27, NVPTX::ENVREG28, NVPTX::ENVREG29, NVPTX::ENVREG30, NVPTX::ENVREG31,
541 };
542
543 // SpecialRegs Bit set.
544 const uint8_t SpecialRegsBits[] = {
545 0xfe, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02,
546 };
547
548 // Int32Regs Register Class...
549 const MCPhysReg Int32Regs[] = {
550 NVPTX::R0, NVPTX::R1, NVPTX::R2, NVPTX::R3, NVPTX::R4, NVPTX::VRFrame32, NVPTX::VRFrameLocal32,
551 };
552
553 // Int32Regs Bit set.
554 const uint8_t Int32RegsBits[] = {
555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x80, 0x02,
556 };
557
558 // Float32ArgRegs Register Class...
559 const MCPhysReg Float32ArgRegs[] = {
560 NVPTX::fa0, NVPTX::fa1, NVPTX::fa2, NVPTX::fa3, NVPTX::fa4,
561 };
562
563 // Float32ArgRegs Bit set.
564 const uint8_t Float32ArgRegsBits[] = {
565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f,
566 };
567
568 // Float32Regs Register Class...
569 const MCPhysReg Float32Regs[] = {
570 NVPTX::F0, NVPTX::F1, NVPTX::F2, NVPTX::F3, NVPTX::F4,
571 };
572
573 // Float32Regs Bit set.
574 const uint8_t Float32RegsBits[] = {
575 0x00, 0x00, 0x00, 0x00, 0x7c,
576 };
577
578 // Int32ArgRegs Register Class...
579 const MCPhysReg Int32ArgRegs[] = {
580 NVPTX::ia0, NVPTX::ia1, NVPTX::ia2, NVPTX::ia3, NVPTX::ia4,
581 };
582
583 // Int32ArgRegs Bit set.
584 const uint8_t Int32ArgRegsBits[] = {
585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03,
586 };
587
588 // Int32Regs_and_SpecialRegs Register Class...
589 const MCPhysReg Int32Regs_and_SpecialRegs[] = {
590 NVPTX::VRFrame32, NVPTX::VRFrameLocal32,
591 };
592
593 // Int32Regs_and_SpecialRegs Bit set.
594 const uint8_t Int32Regs_and_SpecialRegsBits[] = {
595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02,
596 };
597
598 // Int64Regs Register Class...
599 const MCPhysReg Int64Regs[] = {
600 NVPTX::RL0, NVPTX::RL1, NVPTX::RL2, NVPTX::RL3, NVPTX::RL4, NVPTX::VRFrame64, NVPTX::VRFrameLocal64,
601 };
602
603 // Int64Regs Bit set.
604 const uint8_t Int64RegsBits[] = {
605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x05,
606 };
607
608 // Float64ArgRegs Register Class...
609 const MCPhysReg Float64ArgRegs[] = {
610 NVPTX::da0, NVPTX::da1, NVPTX::da2, NVPTX::da3, NVPTX::da4,
611 };
612
613 // Float64ArgRegs Bit set.
614 const uint8_t Float64ArgRegsBits[] = {
615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
616 };
617
618 // Float64Regs Register Class...
619 const MCPhysReg Float64Regs[] = {
620 NVPTX::FL0, NVPTX::FL1, NVPTX::FL2, NVPTX::FL3, NVPTX::FL4,
621 };
622
623 // Float64Regs Bit set.
624 const uint8_t Float64RegsBits[] = {
625 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f,
626 };
627
628 // Int64ArgRegs Register Class...
629 const MCPhysReg Int64ArgRegs[] = {
630 NVPTX::la0, NVPTX::la1, NVPTX::la2, NVPTX::la3, NVPTX::la4,
631 };
632
633 // Int64ArgRegs Bit set.
634 const uint8_t Int64ArgRegsBits[] = {
635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
636 };
637
638 // Int128Regs Register Class...
639 const MCPhysReg Int128Regs[] = {
640 NVPTX::RQ0, NVPTX::RQ1, NVPTX::RQ2, NVPTX::RQ3, NVPTX::RQ4,
641 };
642
643 // Int128Regs Bit set.
644 const uint8_t Int128RegsBits[] = {
645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03,
646 };
647
648} // end anonymous namespace
649
650
651#ifdef __GNUC__
652#pragma GCC diagnostic push
653#pragma GCC diagnostic ignored "-Woverlength-strings"
654#endif
655extern const char NVPTXRegClassStrings[] = {
656 /* 0 */ "Int1Regs\0"
657 /* 9 */ "Float32Regs\0"
658 /* 21 */ "Int32Regs\0"
659 /* 31 */ "Float64Regs\0"
660 /* 43 */ "Int64Regs\0"
661 /* 53 */ "Int16Regs\0"
662 /* 63 */ "Int128Regs\0"
663 /* 74 */ "Float32ArgRegs\0"
664 /* 89 */ "Int32ArgRegs\0"
665 /* 102 */ "Float64ArgRegs\0"
666 /* 117 */ "Int64ArgRegs\0"
667 /* 130 */ "Int32Regs_and_SpecialRegs\0"
668};
669#ifdef __GNUC__
670#pragma GCC diagnostic pop
671#endif
672
673extern const MCRegisterClass NVPTXMCRegisterClasses[] = {
674 { Int1Regs, Int1RegsBits, 0, 5, sizeof(Int1RegsBits), NVPTX::Int1RegsRegClassID, 1, 1, true, false },
675 { Int16Regs, Int16RegsBits, 53, 5, sizeof(Int16RegsBits), NVPTX::Int16RegsRegClassID, 16, 1, true, false },
676 { SpecialRegs, SpecialRegsBits, 144, 35, sizeof(SpecialRegsBits), NVPTX::SpecialRegsRegClassID, 32, 1, true, false },
677 { Int32Regs, Int32RegsBits, 21, 7, sizeof(Int32RegsBits), NVPTX::Int32RegsRegClassID, 32, 1, true, false },
678 { Float32ArgRegs, Float32ArgRegsBits, 74, 5, sizeof(Float32ArgRegsBits), NVPTX::Float32ArgRegsRegClassID, 32, 1, true, false },
679 { Float32Regs, Float32RegsBits, 9, 5, sizeof(Float32RegsBits), NVPTX::Float32RegsRegClassID, 32, 1, true, false },
680 { Int32ArgRegs, Int32ArgRegsBits, 89, 5, sizeof(Int32ArgRegsBits), NVPTX::Int32ArgRegsRegClassID, 32, 1, true, false },
681 { Int32Regs_and_SpecialRegs, Int32Regs_and_SpecialRegsBits, 130, 2, sizeof(Int32Regs_and_SpecialRegsBits), NVPTX::Int32Regs_and_SpecialRegsRegClassID, 32, 1, true, false },
682 { Int64Regs, Int64RegsBits, 43, 7, sizeof(Int64RegsBits), NVPTX::Int64RegsRegClassID, 64, 1, true, false },
683 { Float64ArgRegs, Float64ArgRegsBits, 102, 5, sizeof(Float64ArgRegsBits), NVPTX::Float64ArgRegsRegClassID, 64, 1, true, false },
684 { Float64Regs, Float64RegsBits, 31, 5, sizeof(Float64RegsBits), NVPTX::Float64RegsRegClassID, 64, 1, true, false },
685 { Int64ArgRegs, Int64ArgRegsBits, 117, 5, sizeof(Int64ArgRegsBits), NVPTX::Int64ArgRegsRegClassID, 64, 1, true, false },
686 { Int128Regs, Int128RegsBits, 63, 5, sizeof(Int128RegsBits), NVPTX::Int128RegsRegClassID, 128, 1, true, false },
687};
688
689extern const uint16_t NVPTXRegEncodingTable[] = {
690 0,
691 0,
692 0,
693 0,
694 0,
695 0,
696 0,
697 0,
698 0,
699 0,
700 0,
701 0,
702 0,
703 0,
704 0,
705 0,
706 0,
707 0,
708 0,
709 0,
710 0,
711 0,
712 0,
713 0,
714 0,
715 0,
716 0,
717 0,
718 0,
719 0,
720 0,
721 0,
722 0,
723 0,
724 0,
725 0,
726 0,
727 0,
728 0,
729 0,
730 0,
731 0,
732 0,
733 0,
734 0,
735 0,
736 0,
737 0,
738 0,
739 0,
740 0,
741 0,
742 0,
743 0,
744 0,
745 0,
746 0,
747 0,
748 0,
749 0,
750 0,
751 0,
752 0,
753 0,
754 0,
755 0,
756 0,
757 0,
758 0,
759 0,
760 0,
761 0,
762 0,
763 0,
764 0,
765 0,
766 0,
767 0,
768 0,
769 0,
770 0,
771 0,
772 0,
773 0,
774 0,
775 0,
776 0,
777 0,
778 0,
779 0,
780 0,
781 0,
782 0,
783 0,
784 0,
785 0,
786 0,
787 0,
788 0,
789 0,
790 0,
791 0,
792 0,
793};
794static inline void InitNVPTXMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
795 RI->InitMCRegisterInfo(NVPTXRegDesc, 103, RA, PC, NVPTXMCRegisterClasses, 13, NVPTXRegUnitRoots, 102, NVPTXRegDiffLists, NVPTXLaneMaskLists, NVPTXRegStrings, NVPTXRegClassStrings, NVPTXSubRegIdxLists, 1,
796NVPTXRegEncodingTable);
797
798}
799
800} // end namespace llvm
801
802#endif // GET_REGINFO_MC_DESC
803
804/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
805|* *|
806|* Register Information Header Fragment *|
807|* *|
808|* Automatically generated file, do not edit! *|
809|* *|
810\*===----------------------------------------------------------------------===*/
811
812
813#ifdef GET_REGINFO_HEADER
814#undef GET_REGINFO_HEADER
815
816#include "llvm/CodeGen/TargetRegisterInfo.h"
817
818namespace llvm {
819
820class NVPTXFrameLowering;
821
822struct NVPTXGenRegisterInfo : public TargetRegisterInfo {
823 explicit NVPTXGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
824 unsigned PC = 0, unsigned HwMode = 0);
825 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
826 unsigned getRegUnitWeight(unsigned RegUnit) const override;
827 unsigned getNumRegPressureSets() const override;
828 const char *getRegPressureSetName(unsigned Idx) const override;
829 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
830 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
831 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
832 ArrayRef<const char *> getRegMaskNames() const override;
833 ArrayRef<const uint32_t *> getRegMasks() const override;
834 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
835 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
836 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
837 bool isConstantPhysReg(MCRegister PhysReg) const override final;
838 /// Devirtualized TargetFrameLowering.
839 static const NVPTXFrameLowering *getFrameLowering(
840 const MachineFunction &MF);
841};
842
843namespace NVPTX { // Register classes
844 extern const TargetRegisterClass Int1RegsRegClass;
845 extern const TargetRegisterClass Int16RegsRegClass;
846 extern const TargetRegisterClass SpecialRegsRegClass;
847 extern const TargetRegisterClass Int32RegsRegClass;
848 extern const TargetRegisterClass Float32ArgRegsRegClass;
849 extern const TargetRegisterClass Float32RegsRegClass;
850 extern const TargetRegisterClass Int32ArgRegsRegClass;
851 extern const TargetRegisterClass Int32Regs_and_SpecialRegsRegClass;
852 extern const TargetRegisterClass Int64RegsRegClass;
853 extern const TargetRegisterClass Float64ArgRegsRegClass;
854 extern const TargetRegisterClass Float64RegsRegClass;
855 extern const TargetRegisterClass Int64ArgRegsRegClass;
856 extern const TargetRegisterClass Int128RegsRegClass;
857} // end namespace NVPTX
858
859} // end namespace llvm
860
861#endif // GET_REGINFO_HEADER
862
863/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
864|* *|
865|* Target Register and Register Classes Information *|
866|* *|
867|* Automatically generated file, do not edit! *|
868|* *|
869\*===----------------------------------------------------------------------===*/
870
871
872#ifdef GET_REGINFO_TARGET_DESC
873#undef GET_REGINFO_TARGET_DESC
874
875namespace llvm {
876
877extern const MCRegisterClass NVPTXMCRegisterClasses[];
878
879static const MVT::SimpleValueType VTLists[] = {
880 /* 0 */ MVT::i1, MVT::Other,
881 /* 2 */ MVT::i32, MVT::Other,
882 /* 4 */ MVT::i64, MVT::Other,
883 /* 6 */ MVT::i128, MVT::Other,
884 /* 8 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
885 /* 12 */ MVT::f32, MVT::Other,
886 /* 14 */ MVT::f64, MVT::Other,
887 /* 16 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::Other,
888};
889
890static const char *SubRegIndexNameTable[] = { "" };
891
892static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
893 { 65535, 65535 },
894};
895
896
897static const LaneBitmask SubRegIndexLaneMaskTable[] = {
898 LaneBitmask::getAll(),
899 };
900
901
902
903static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
904 // Mode = 0 (Default)
905 { 1, 1, 8, /*VTLists+*/0 }, // Int1Regs
906 { 16, 16, 16, /*VTLists+*/8 }, // Int16Regs
907 { 32, 32, 32, /*VTLists+*/2 }, // SpecialRegs
908 { 32, 32, 32, /*VTLists+*/16 }, // Int32Regs
909 { 32, 32, 32, /*VTLists+*/12 }, // Float32ArgRegs
910 { 32, 32, 32, /*VTLists+*/12 }, // Float32Regs
911 { 32, 32, 32, /*VTLists+*/2 }, // Int32ArgRegs
912 { 32, 32, 32, /*VTLists+*/16 }, // Int32Regs_and_SpecialRegs
913 { 64, 64, 64, /*VTLists+*/4 }, // Int64Regs
914 { 64, 64, 64, /*VTLists+*/14 }, // Float64ArgRegs
915 { 64, 64, 64, /*VTLists+*/14 }, // Float64Regs
916 { 64, 64, 64, /*VTLists+*/4 }, // Int64ArgRegs
917 { 128, 128, 128, /*VTLists+*/6 }, // Int128Regs
918};
919
920static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
921
922static const uint32_t Int1RegsSubClassMask[] = {
923 0x00000001,
924};
925
926static const uint32_t Int16RegsSubClassMask[] = {
927 0x00000002,
928};
929
930static const uint32_t SpecialRegsSubClassMask[] = {
931 0x00000084,
932};
933
934static const uint32_t Int32RegsSubClassMask[] = {
935 0x00000088,
936};
937
938static const uint32_t Float32ArgRegsSubClassMask[] = {
939 0x00000010,
940};
941
942static const uint32_t Float32RegsSubClassMask[] = {
943 0x00000020,
944};
945
946static const uint32_t Int32ArgRegsSubClassMask[] = {
947 0x00000040,
948};
949
950static const uint32_t Int32Regs_and_SpecialRegsSubClassMask[] = {
951 0x00000080,
952};
953
954static const uint32_t Int64RegsSubClassMask[] = {
955 0x00000100,
956};
957
958static const uint32_t Float64ArgRegsSubClassMask[] = {
959 0x00000200,
960};
961
962static const uint32_t Float64RegsSubClassMask[] = {
963 0x00000400,
964};
965
966static const uint32_t Int64ArgRegsSubClassMask[] = {
967 0x00000800,
968};
969
970static const uint32_t Int128RegsSubClassMask[] = {
971 0x00001000,
972};
973
974static const uint16_t SuperRegIdxSeqs[] = {
975 /* 0 */ 0,
976};
977
978static const TargetRegisterClass *const Int32Regs_and_SpecialRegsSuperclasses[] = {
979 &NVPTX::SpecialRegsRegClass,
980 &NVPTX::Int32RegsRegClass,
981 nullptr
982};
983
984
985namespace NVPTX { // Register class instances
986 extern const TargetRegisterClass Int1RegsRegClass = {
987 &NVPTXMCRegisterClasses[Int1RegsRegClassID],
988 Int1RegsSubClassMask,
989 SuperRegIdxSeqs + 0,
990 LaneBitmask(0x0000000000000001),
991 0,
992 false,
993 0x00, /* TSFlags */
994 false, /* HasDisjunctSubRegs */
995 false, /* CoveredBySubRegs */
996 NullRegClasses,
997 nullptr
998 };
999
1000 extern const TargetRegisterClass Int16RegsRegClass = {
1001 &NVPTXMCRegisterClasses[Int16RegsRegClassID],
1002 Int16RegsSubClassMask,
1003 SuperRegIdxSeqs + 0,
1004 LaneBitmask(0x0000000000000001),
1005 0,
1006 false,
1007 0x00, /* TSFlags */
1008 false, /* HasDisjunctSubRegs */
1009 false, /* CoveredBySubRegs */
1010 NullRegClasses,
1011 nullptr
1012 };
1013
1014 extern const TargetRegisterClass SpecialRegsRegClass = {
1015 &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
1016 SpecialRegsSubClassMask,
1017 SuperRegIdxSeqs + 0,
1018 LaneBitmask(0x0000000000000001),
1019 0,
1020 false,
1021 0x00, /* TSFlags */
1022 false, /* HasDisjunctSubRegs */
1023 false, /* CoveredBySubRegs */
1024 NullRegClasses,
1025 nullptr
1026 };
1027
1028 extern const TargetRegisterClass Int32RegsRegClass = {
1029 &NVPTXMCRegisterClasses[Int32RegsRegClassID],
1030 Int32RegsSubClassMask,
1031 SuperRegIdxSeqs + 0,
1032 LaneBitmask(0x0000000000000001),
1033 0,
1034 false,
1035 0x00, /* TSFlags */
1036 false, /* HasDisjunctSubRegs */
1037 false, /* CoveredBySubRegs */
1038 NullRegClasses,
1039 nullptr
1040 };
1041
1042 extern const TargetRegisterClass Float32ArgRegsRegClass = {
1043 &NVPTXMCRegisterClasses[Float32ArgRegsRegClassID],
1044 Float32ArgRegsSubClassMask,
1045 SuperRegIdxSeqs + 0,
1046 LaneBitmask(0x0000000000000001),
1047 0,
1048 false,
1049 0x00, /* TSFlags */
1050 false, /* HasDisjunctSubRegs */
1051 false, /* CoveredBySubRegs */
1052 NullRegClasses,
1053 nullptr
1054 };
1055
1056 extern const TargetRegisterClass Float32RegsRegClass = {
1057 &NVPTXMCRegisterClasses[Float32RegsRegClassID],
1058 Float32RegsSubClassMask,
1059 SuperRegIdxSeqs + 0,
1060 LaneBitmask(0x0000000000000001),
1061 0,
1062 false,
1063 0x00, /* TSFlags */
1064 false, /* HasDisjunctSubRegs */
1065 false, /* CoveredBySubRegs */
1066 NullRegClasses,
1067 nullptr
1068 };
1069
1070 extern const TargetRegisterClass Int32ArgRegsRegClass = {
1071 &NVPTXMCRegisterClasses[Int32ArgRegsRegClassID],
1072 Int32ArgRegsSubClassMask,
1073 SuperRegIdxSeqs + 0,
1074 LaneBitmask(0x0000000000000001),
1075 0,
1076 false,
1077 0x00, /* TSFlags */
1078 false, /* HasDisjunctSubRegs */
1079 false, /* CoveredBySubRegs */
1080 NullRegClasses,
1081 nullptr
1082 };
1083
1084 extern const TargetRegisterClass Int32Regs_and_SpecialRegsRegClass = {
1085 &NVPTXMCRegisterClasses[Int32Regs_and_SpecialRegsRegClassID],
1086 Int32Regs_and_SpecialRegsSubClassMask,
1087 SuperRegIdxSeqs + 0,
1088 LaneBitmask(0x0000000000000001),
1089 0,
1090 false,
1091 0x00, /* TSFlags */
1092 false, /* HasDisjunctSubRegs */
1093 false, /* CoveredBySubRegs */
1094 Int32Regs_and_SpecialRegsSuperclasses,
1095 nullptr
1096 };
1097
1098 extern const TargetRegisterClass Int64RegsRegClass = {
1099 &NVPTXMCRegisterClasses[Int64RegsRegClassID],
1100 Int64RegsSubClassMask,
1101 SuperRegIdxSeqs + 0,
1102 LaneBitmask(0x0000000000000001),
1103 0,
1104 false,
1105 0x00, /* TSFlags */
1106 false, /* HasDisjunctSubRegs */
1107 false, /* CoveredBySubRegs */
1108 NullRegClasses,
1109 nullptr
1110 };
1111
1112 extern const TargetRegisterClass Float64ArgRegsRegClass = {
1113 &NVPTXMCRegisterClasses[Float64ArgRegsRegClassID],
1114 Float64ArgRegsSubClassMask,
1115 SuperRegIdxSeqs + 0,
1116 LaneBitmask(0x0000000000000001),
1117 0,
1118 false,
1119 0x00, /* TSFlags */
1120 false, /* HasDisjunctSubRegs */
1121 false, /* CoveredBySubRegs */
1122 NullRegClasses,
1123 nullptr
1124 };
1125
1126 extern const TargetRegisterClass Float64RegsRegClass = {
1127 &NVPTXMCRegisterClasses[Float64RegsRegClassID],
1128 Float64RegsSubClassMask,
1129 SuperRegIdxSeqs + 0,
1130 LaneBitmask(0x0000000000000001),
1131 0,
1132 false,
1133 0x00, /* TSFlags */
1134 false, /* HasDisjunctSubRegs */
1135 false, /* CoveredBySubRegs */
1136 NullRegClasses,
1137 nullptr
1138 };
1139
1140 extern const TargetRegisterClass Int64ArgRegsRegClass = {
1141 &NVPTXMCRegisterClasses[Int64ArgRegsRegClassID],
1142 Int64ArgRegsSubClassMask,
1143 SuperRegIdxSeqs + 0,
1144 LaneBitmask(0x0000000000000001),
1145 0,
1146 false,
1147 0x00, /* TSFlags */
1148 false, /* HasDisjunctSubRegs */
1149 false, /* CoveredBySubRegs */
1150 NullRegClasses,
1151 nullptr
1152 };
1153
1154 extern const TargetRegisterClass Int128RegsRegClass = {
1155 &NVPTXMCRegisterClasses[Int128RegsRegClassID],
1156 Int128RegsSubClassMask,
1157 SuperRegIdxSeqs + 0,
1158 LaneBitmask(0x0000000000000001),
1159 0,
1160 false,
1161 0x00, /* TSFlags */
1162 false, /* HasDisjunctSubRegs */
1163 false, /* CoveredBySubRegs */
1164 NullRegClasses,
1165 nullptr
1166 };
1167
1168} // end namespace NVPTX
1169
1170namespace {
1171 const TargetRegisterClass *const RegisterClasses[] = {
1172 &NVPTX::Int1RegsRegClass,
1173 &NVPTX::Int16RegsRegClass,
1174 &NVPTX::SpecialRegsRegClass,
1175 &NVPTX::Int32RegsRegClass,
1176 &NVPTX::Float32ArgRegsRegClass,
1177 &NVPTX::Float32RegsRegClass,
1178 &NVPTX::Int32ArgRegsRegClass,
1179 &NVPTX::Int32Regs_and_SpecialRegsRegClass,
1180 &NVPTX::Int64RegsRegClass,
1181 &NVPTX::Float64ArgRegsRegClass,
1182 &NVPTX::Float64RegsRegClass,
1183 &NVPTX::Int64ArgRegsRegClass,
1184 &NVPTX::Int128RegsRegClass,
1185 };
1186} // end anonymous namespace
1187
1188static const uint8_t CostPerUseTable[] = {
11890, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1190
1191
1192static const bool InAllocatableClassTable[] = {
1193false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1194
1195
1196static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
1197CostPerUseTable, 1, InAllocatableClassTable};
1198
1199/// Get the weight in units of pressure for this register class.
1200const RegClassWeight &NVPTXGenRegisterInfo::
1201getRegClassWeight(const TargetRegisterClass *RC) const {
1202 static const RegClassWeight RCWeightTable[] = {
1203 {1, 5}, // Int1Regs
1204 {1, 5}, // Int16Regs
1205 {1, 35}, // SpecialRegs
1206 {1, 7}, // Int32Regs
1207 {1, 5}, // Float32ArgRegs
1208 {1, 5}, // Float32Regs
1209 {1, 5}, // Int32ArgRegs
1210 {1, 2}, // Int32Regs_and_SpecialRegs
1211 {1, 7}, // Int64Regs
1212 {1, 5}, // Float64ArgRegs
1213 {1, 5}, // Float64Regs
1214 {1, 5}, // Int64ArgRegs
1215 {1, 5}, // Int128Regs
1216 };
1217 return RCWeightTable[RC->getID()];
1218}
1219
1220/// Get the weight in units of pressure for this register unit.
1221unsigned NVPTXGenRegisterInfo::
1222getRegUnitWeight(unsigned RegUnit) const {
1223 assert(RegUnit < 102 && "invalid register unit");
1224 // All register units have unit weight.
1225 return 1;
1226}
1227
1228
1229// Get the number of dimensions of register pressure.
1230unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
1231 return 14;
1232}
1233
1234// Get the name of this register unit pressure set.
1235const char *NVPTXGenRegisterInfo::
1236getRegPressureSetName(unsigned Idx) const {
1237 static const char *PressureNameTable[] = {
1238 "Int32Regs_and_SpecialRegs",
1239 "Int1Regs",
1240 "Int16Regs",
1241 "Float32ArgRegs",
1242 "Float32Regs",
1243 "Int32ArgRegs",
1244 "Float64ArgRegs",
1245 "Float64Regs",
1246 "Int64ArgRegs",
1247 "Int128Regs",
1248 "Int32Regs",
1249 "Int64Regs",
1250 "SpecialRegs",
1251 "SpecialRegs_with_Int32Regs",
1252 };
1253 return PressureNameTable[Idx];
1254}
1255
1256// Get the register unit pressure limit for this dimension.
1257// This limit must be adjusted dynamically for reserved registers.
1258unsigned NVPTXGenRegisterInfo::
1259getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1260 static const uint8_t PressureLimitTable[] = {
1261 2, // 0: Int32Regs_and_SpecialRegs
1262 5, // 1: Int1Regs
1263 5, // 2: Int16Regs
1264 5, // 3: Float32ArgRegs
1265 5, // 4: Float32Regs
1266 5, // 5: Int32ArgRegs
1267 5, // 6: Float64ArgRegs
1268 5, // 7: Float64Regs
1269 5, // 8: Int64ArgRegs
1270 5, // 9: Int128Regs
1271 7, // 10: Int32Regs
1272 7, // 11: Int64Regs
1273 35, // 12: SpecialRegs
1274 40, // 13: SpecialRegs_with_Int32Regs
1275 };
1276 return PressureLimitTable[Idx];
1277}
1278
1279/// Table of pressure sets per register class or unit.
1280static const int RCSetsTable[] = {
1281 /* 0 */ 1, -1,
1282 /* 2 */ 2, -1,
1283 /* 4 */ 3, -1,
1284 /* 6 */ 4, -1,
1285 /* 8 */ 5, -1,
1286 /* 10 */ 6, -1,
1287 /* 12 */ 7, -1,
1288 /* 14 */ 8, -1,
1289 /* 16 */ 9, -1,
1290 /* 18 */ 11, -1,
1291 /* 20 */ 10, 13, -1,
1292 /* 23 */ 0, 10, 12, 13, -1,
1293};
1294
1295/// Get the dimensions of register pressure impacted by this register class.
1296/// Returns a -1 terminated array of pressure set IDs
1297const int *NVPTXGenRegisterInfo::
1298getRegClassPressureSets(const TargetRegisterClass *RC) const {
1299 static const uint8_t RCSetStartTable[] = {
1300 0,2,25,20,4,6,8,23,18,10,12,14,16,};
1301 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1302}
1303
1304/// Get the dimensions of register pressure impacted by this register unit.
1305/// Returns a -1 terminated array of pressure set IDs
1306const int *NVPTXGenRegisterInfo::
1307getRegUnitPressureSets(unsigned RegUnit) const {
1308 assert(RegUnit < 102 && "invalid register unit");
1309 static const uint8_t RUSetStartTable[] = {
1310 25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,6,6,6,6,6,12,12,12,12,12,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,20,20,20,20,20,18,18,18,18,18,16,16,16,16,16,2,2,2,2,2,23,18,23,18,10,10,10,10,10,4,4,4,4,4,8,8,8,8,8,14,14,14,14,14,};
1311 return &RCSetsTable[RUSetStartTable[RegUnit]];
1312}
1313
1314extern const MCRegisterDesc NVPTXRegDesc[];
1315extern const int16_t NVPTXRegDiffLists[];
1316extern const LaneBitmask NVPTXLaneMaskLists[];
1317extern const char NVPTXRegStrings[];
1318extern const char NVPTXRegClassStrings[];
1319extern const MCPhysReg NVPTXRegUnitRoots[][2];
1320extern const uint16_t NVPTXSubRegIdxLists[];
1321extern const uint16_t NVPTXRegEncodingTable[];
1322NVPTXGenRegisterInfo::
1323NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1324 unsigned PC, unsigned HwMode)
1325 : TargetRegisterInfo(&NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+13,
1326 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1327 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
1328 InitMCRegisterInfo(NVPTXRegDesc, 103, RA, PC,
1329 NVPTXMCRegisterClasses, 13,
1330 NVPTXRegUnitRoots,
1331 102,
1332 NVPTXRegDiffLists,
1333 NVPTXLaneMaskLists,
1334 NVPTXRegStrings,
1335 NVPTXRegClassStrings,
1336 NVPTXSubRegIdxLists,
1337 1,
1338 NVPTXRegEncodingTable);
1339
1340}
1341
1342
1343
1344ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
1345 return std::nullopt;
1346}
1347
1348bool NVPTXGenRegisterInfo::
1349isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1350 return
1351 false;
1352}
1353
1354bool NVPTXGenRegisterInfo::
1355isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1356 return
1357 false;
1358}
1359
1360bool NVPTXGenRegisterInfo::
1361isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1362 return
1363 false;
1364}
1365
1366bool NVPTXGenRegisterInfo::
1367isConstantPhysReg(MCRegister PhysReg) const {
1368 return
1369 false;
1370}
1371
1372ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
1373 return std::nullopt;
1374}
1375
1376const NVPTXFrameLowering *
1377NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1378 return static_cast<const NVPTXFrameLowering *>(
1379 MF.getSubtarget().getFrameLowering());
1380}
1381
1382} // end namespace llvm
1383
1384#endif // GET_REGINFO_TARGET_DESC
1385
1386