1 | //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the entry points for global functions defined in |
10 | // the LLVM NVPTX back-end. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H |
15 | #define LLVM_LIB_TARGET_NVPTX_NVPTX_H |
16 | |
17 | #include "llvm/IR/PassManager.h" |
18 | #include "llvm/Pass.h" |
19 | #include "llvm/Support/CodeGen.h" |
20 | |
21 | namespace llvm { |
22 | class FunctionPass; |
23 | class MachineFunctionPass; |
24 | class NVPTXTargetMachine; |
25 | class PassRegistry; |
26 | |
27 | namespace NVPTXCC { |
28 | enum CondCodes { |
29 | EQ, |
30 | NE, |
31 | LT, |
32 | LE, |
33 | GT, |
34 | GE |
35 | }; |
36 | } |
37 | |
38 | FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM, |
39 | llvm::CodeGenOptLevel OptLevel); |
40 | ModulePass *createNVPTXAssignValidGlobalNamesPass(); |
41 | ModulePass *createGenericToNVVMLegacyPass(); |
42 | ModulePass *createNVPTXCtorDtorLoweringLegacyPass(); |
43 | FunctionPass *createNVVMIntrRangePass(); |
44 | FunctionPass *createNVVMReflectPass(unsigned int SmVersion); |
45 | MachineFunctionPass *createNVPTXPrologEpilogPass(); |
46 | MachineFunctionPass *createNVPTXReplaceImageHandlesPass(); |
47 | FunctionPass *createNVPTXImageOptimizerPass(); |
48 | FunctionPass *createNVPTXLowerArgsPass(); |
49 | FunctionPass *createNVPTXLowerAllocaPass(); |
50 | FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable, |
51 | bool NoTrapAfterNoreturn); |
52 | MachineFunctionPass *createNVPTXPeephole(); |
53 | MachineFunctionPass *createNVPTXProxyRegErasurePass(); |
54 | |
55 | struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> { |
56 | PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); |
57 | }; |
58 | |
59 | struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> { |
60 | NVVMReflectPass(); |
61 | NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {} |
62 | PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); |
63 | |
64 | private: |
65 | unsigned SmVersion; |
66 | }; |
67 | |
68 | struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> { |
69 | PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); |
70 | }; |
71 | |
72 | namespace NVPTX { |
73 | enum DrvInterface { |
74 | NVCL, |
75 | CUDA |
76 | }; |
77 | |
78 | // A field inside TSFlags needs a shift and a mask. The usage is |
79 | // always as follows : |
80 | // ((TSFlags & fieldMask) >> fieldShift) |
81 | // The enum keeps the mask, the shift, and all valid values of the |
82 | // field in one place. |
83 | enum VecInstType { |
84 | VecInstTypeShift = 0, |
85 | VecInstTypeMask = 0xF, |
86 | |
87 | VecNOP = 0, |
88 | VecLoad = 1, |
89 | VecStore = 2, |
90 | VecBuild = 3, |
91 | VecShuffle = 4, |
92 | = 5, |
93 | VecInsert = 6, |
94 | VecDest = 7, |
95 | VecOther = 15 |
96 | }; |
97 | |
98 | enum SimpleMove { |
99 | SimpleMoveMask = 0x10, |
100 | SimpleMoveShift = 4 |
101 | }; |
102 | enum LoadStore { |
103 | isLoadMask = 0x20, |
104 | isLoadShift = 5, |
105 | isStoreMask = 0x40, |
106 | isStoreShift = 6 |
107 | }; |
108 | |
109 | namespace PTXLdStInstCode { |
110 | enum AddressSpace { |
111 | GENERIC = 0, |
112 | GLOBAL = 1, |
113 | CONSTANT = 2, |
114 | SHARED = 3, |
115 | PARAM = 4, |
116 | LOCAL = 5 |
117 | }; |
118 | enum FromType { |
119 | Unsigned = 0, |
120 | Signed, |
121 | Float, |
122 | Untyped |
123 | }; |
124 | enum VecType { |
125 | Scalar = 1, |
126 | V2 = 2, |
127 | V4 = 4 |
128 | }; |
129 | } |
130 | |
131 | /// PTXCvtMode - Conversion code enumeration |
132 | namespace PTXCvtMode { |
133 | enum CvtMode { |
134 | NONE = 0, |
135 | RNI, |
136 | RZI, |
137 | RMI, |
138 | RPI, |
139 | RN, |
140 | RZ, |
141 | RM, |
142 | RP, |
143 | RNA, |
144 | |
145 | BASE_MASK = 0x0F, |
146 | FTZ_FLAG = 0x10, |
147 | SAT_FLAG = 0x20, |
148 | RELU_FLAG = 0x40 |
149 | }; |
150 | } |
151 | |
152 | /// PTXCmpMode - Comparison mode enumeration |
153 | namespace PTXCmpMode { |
154 | enum CmpMode { |
155 | EQ = 0, |
156 | NE, |
157 | LT, |
158 | LE, |
159 | GT, |
160 | GE, |
161 | LO, |
162 | LS, |
163 | HI, |
164 | HS, |
165 | EQU, |
166 | NEU, |
167 | LTU, |
168 | LEU, |
169 | GTU, |
170 | GEU, |
171 | NUM, |
172 | // NAN is a MACRO |
173 | NotANumber, |
174 | |
175 | BASE_MASK = 0xFF, |
176 | FTZ_FLAG = 0x100 |
177 | }; |
178 | } |
179 | |
180 | namespace PTXPrmtMode { |
181 | enum PrmtMode { |
182 | NONE, |
183 | F4E, |
184 | B4E, |
185 | RC8, |
186 | ECL, |
187 | ECR, |
188 | RC16, |
189 | }; |
190 | } |
191 | } |
192 | void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &); |
193 | } // namespace llvm |
194 | |
195 | // Defines symbolic names for NVPTX registers. This defines a mapping from |
196 | // register name to register number. |
197 | #define GET_REGINFO_ENUM |
198 | #include "NVPTXGenRegisterInfo.inc" |
199 | |
200 | // Defines symbolic names for the NVPTX instructions. |
201 | #define GET_INSTRINFO_ENUM |
202 | #define GET_INSTRINFO_MC_HELPER_DECLS |
203 | #include "NVPTXGenInstrInfo.inc" |
204 | |
205 | #endif |
206 | |