1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | |* *| |
3 | |* Machine Code Emitter *| |
4 | |* *| |
5 | |* Automatically generated file, do not edit! *| |
6 | |* *| |
7 | \*===----------------------------------------------------------------------===*/ |
8 | |
9 | uint64_t PPCMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | SmallVectorImpl<MCFixup> &Fixups, |
11 | const MCSubtargetInfo &STI) const { |
12 | static const uint64_t InstBits[] = { |
13 | UINT64_C(0), |
14 | UINT64_C(0), |
15 | UINT64_C(0), |
16 | UINT64_C(0), |
17 | UINT64_C(0), |
18 | UINT64_C(0), |
19 | UINT64_C(0), |
20 | UINT64_C(0), |
21 | UINT64_C(0), |
22 | UINT64_C(0), |
23 | UINT64_C(0), |
24 | UINT64_C(0), |
25 | UINT64_C(0), |
26 | UINT64_C(0), |
27 | UINT64_C(0), |
28 | UINT64_C(0), |
29 | UINT64_C(0), |
30 | UINT64_C(0), |
31 | UINT64_C(0), |
32 | UINT64_C(0), |
33 | UINT64_C(0), |
34 | UINT64_C(0), |
35 | UINT64_C(0), |
36 | UINT64_C(0), |
37 | UINT64_C(0), |
38 | UINT64_C(0), |
39 | UINT64_C(0), |
40 | UINT64_C(0), |
41 | UINT64_C(0), |
42 | UINT64_C(0), |
43 | UINT64_C(0), |
44 | UINT64_C(0), |
45 | UINT64_C(0), |
46 | UINT64_C(0), |
47 | UINT64_C(0), |
48 | UINT64_C(0), |
49 | UINT64_C(0), |
50 | UINT64_C(0), |
51 | UINT64_C(0), |
52 | UINT64_C(0), |
53 | UINT64_C(0), |
54 | UINT64_C(0), |
55 | UINT64_C(0), |
56 | UINT64_C(0), |
57 | UINT64_C(0), |
58 | UINT64_C(0), |
59 | UINT64_C(0), |
60 | UINT64_C(0), |
61 | UINT64_C(0), |
62 | UINT64_C(0), |
63 | UINT64_C(0), |
64 | UINT64_C(0), |
65 | UINT64_C(0), |
66 | UINT64_C(0), |
67 | UINT64_C(0), |
68 | UINT64_C(0), |
69 | UINT64_C(0), |
70 | UINT64_C(0), |
71 | UINT64_C(0), |
72 | UINT64_C(0), |
73 | UINT64_C(0), |
74 | UINT64_C(0), |
75 | UINT64_C(0), |
76 | UINT64_C(0), |
77 | UINT64_C(0), |
78 | UINT64_C(0), |
79 | UINT64_C(0), |
80 | UINT64_C(0), |
81 | UINT64_C(0), |
82 | UINT64_C(0), |
83 | UINT64_C(0), |
84 | UINT64_C(0), |
85 | UINT64_C(0), |
86 | UINT64_C(0), |
87 | UINT64_C(0), |
88 | UINT64_C(0), |
89 | UINT64_C(0), |
90 | UINT64_C(0), |
91 | UINT64_C(0), |
92 | UINT64_C(0), |
93 | UINT64_C(0), |
94 | UINT64_C(0), |
95 | UINT64_C(0), |
96 | UINT64_C(0), |
97 | UINT64_C(0), |
98 | UINT64_C(0), |
99 | UINT64_C(0), |
100 | UINT64_C(0), |
101 | UINT64_C(0), |
102 | UINT64_C(0), |
103 | UINT64_C(0), |
104 | UINT64_C(0), |
105 | UINT64_C(0), |
106 | UINT64_C(0), |
107 | UINT64_C(0), |
108 | UINT64_C(0), |
109 | UINT64_C(0), |
110 | UINT64_C(0), |
111 | UINT64_C(0), |
112 | UINT64_C(0), |
113 | UINT64_C(0), |
114 | UINT64_C(0), |
115 | UINT64_C(0), |
116 | UINT64_C(0), |
117 | UINT64_C(0), |
118 | UINT64_C(0), |
119 | UINT64_C(0), |
120 | UINT64_C(0), |
121 | UINT64_C(0), |
122 | UINT64_C(0), |
123 | UINT64_C(0), |
124 | UINT64_C(0), |
125 | UINT64_C(0), |
126 | UINT64_C(0), |
127 | UINT64_C(0), |
128 | UINT64_C(0), |
129 | UINT64_C(0), |
130 | UINT64_C(0), |
131 | UINT64_C(0), |
132 | UINT64_C(0), |
133 | UINT64_C(0), |
134 | UINT64_C(0), |
135 | UINT64_C(0), |
136 | UINT64_C(0), |
137 | UINT64_C(0), |
138 | UINT64_C(0), |
139 | UINT64_C(0), |
140 | UINT64_C(0), |
141 | UINT64_C(0), |
142 | UINT64_C(0), |
143 | UINT64_C(0), |
144 | UINT64_C(0), |
145 | UINT64_C(0), |
146 | UINT64_C(0), |
147 | UINT64_C(0), |
148 | UINT64_C(0), |
149 | UINT64_C(0), |
150 | UINT64_C(0), |
151 | UINT64_C(0), |
152 | UINT64_C(0), |
153 | UINT64_C(0), |
154 | UINT64_C(0), |
155 | UINT64_C(0), |
156 | UINT64_C(0), |
157 | UINT64_C(0), |
158 | UINT64_C(0), |
159 | UINT64_C(0), |
160 | UINT64_C(0), |
161 | UINT64_C(0), |
162 | UINT64_C(0), |
163 | UINT64_C(0), |
164 | UINT64_C(0), |
165 | UINT64_C(0), |
166 | UINT64_C(0), |
167 | UINT64_C(0), |
168 | UINT64_C(0), |
169 | UINT64_C(0), |
170 | UINT64_C(0), |
171 | UINT64_C(0), |
172 | UINT64_C(0), |
173 | UINT64_C(0), |
174 | UINT64_C(0), |
175 | UINT64_C(0), |
176 | UINT64_C(0), |
177 | UINT64_C(0), |
178 | UINT64_C(0), |
179 | UINT64_C(0), |
180 | UINT64_C(0), |
181 | UINT64_C(0), |
182 | UINT64_C(0), |
183 | UINT64_C(0), |
184 | UINT64_C(0), |
185 | UINT64_C(0), |
186 | UINT64_C(0), |
187 | UINT64_C(0), |
188 | UINT64_C(0), |
189 | UINT64_C(0), |
190 | UINT64_C(0), |
191 | UINT64_C(0), |
192 | UINT64_C(0), |
193 | UINT64_C(0), |
194 | UINT64_C(0), |
195 | UINT64_C(0), |
196 | UINT64_C(0), |
197 | UINT64_C(0), |
198 | UINT64_C(0), |
199 | UINT64_C(0), |
200 | UINT64_C(0), |
201 | UINT64_C(0), |
202 | UINT64_C(0), |
203 | UINT64_C(0), |
204 | UINT64_C(0), |
205 | UINT64_C(0), |
206 | UINT64_C(0), |
207 | UINT64_C(0), |
208 | UINT64_C(0), |
209 | UINT64_C(0), |
210 | UINT64_C(0), |
211 | UINT64_C(0), |
212 | UINT64_C(0), |
213 | UINT64_C(0), |
214 | UINT64_C(0), |
215 | UINT64_C(0), |
216 | UINT64_C(0), |
217 | UINT64_C(0), |
218 | UINT64_C(0), |
219 | UINT64_C(0), |
220 | UINT64_C(0), |
221 | UINT64_C(0), |
222 | UINT64_C(0), |
223 | UINT64_C(0), |
224 | UINT64_C(0), |
225 | UINT64_C(0), |
226 | UINT64_C(0), |
227 | UINT64_C(0), |
228 | UINT64_C(0), |
229 | UINT64_C(0), |
230 | UINT64_C(0), |
231 | UINT64_C(0), |
232 | UINT64_C(0), |
233 | UINT64_C(0), |
234 | UINT64_C(0), |
235 | UINT64_C(0), |
236 | UINT64_C(0), |
237 | UINT64_C(0), |
238 | UINT64_C(0), |
239 | UINT64_C(0), |
240 | UINT64_C(0), |
241 | UINT64_C(0), |
242 | UINT64_C(0), |
243 | UINT64_C(0), |
244 | UINT64_C(0), |
245 | UINT64_C(0), |
246 | UINT64_C(0), |
247 | UINT64_C(0), |
248 | UINT64_C(0), |
249 | UINT64_C(0), |
250 | UINT64_C(0), |
251 | UINT64_C(0), |
252 | UINT64_C(0), |
253 | UINT64_C(0), |
254 | UINT64_C(0), |
255 | UINT64_C(0), |
256 | UINT64_C(0), |
257 | UINT64_C(0), |
258 | UINT64_C(0), |
259 | UINT64_C(0), |
260 | UINT64_C(0), |
261 | UINT64_C(0), |
262 | UINT64_C(0), |
263 | UINT64_C(0), |
264 | UINT64_C(0), |
265 | UINT64_C(0), |
266 | UINT64_C(0), |
267 | UINT64_C(0), |
268 | UINT64_C(0), |
269 | UINT64_C(0), |
270 | UINT64_C(0), |
271 | UINT64_C(0), |
272 | UINT64_C(0), |
273 | UINT64_C(0), |
274 | UINT64_C(0), |
275 | UINT64_C(0), |
276 | UINT64_C(0), |
277 | UINT64_C(0), |
278 | UINT64_C(0), |
279 | UINT64_C(0), |
280 | UINT64_C(0), |
281 | UINT64_C(0), |
282 | UINT64_C(0), |
283 | UINT64_C(0), |
284 | UINT64_C(0), |
285 | UINT64_C(0), |
286 | UINT64_C(0), |
287 | UINT64_C(0), |
288 | UINT64_C(0), |
289 | UINT64_C(0), |
290 | UINT64_C(0), |
291 | UINT64_C(0), |
292 | UINT64_C(0), |
293 | UINT64_C(0), |
294 | UINT64_C(0), |
295 | UINT64_C(0), |
296 | UINT64_C(0), |
297 | UINT64_C(0), |
298 | UINT64_C(0), |
299 | UINT64_C(0), |
300 | UINT64_C(0), |
301 | UINT64_C(0), |
302 | UINT64_C(0), |
303 | UINT64_C(0), |
304 | UINT64_C(0), |
305 | UINT64_C(0), |
306 | UINT64_C(0), |
307 | UINT64_C(0), |
308 | UINT64_C(0), |
309 | UINT64_C(0), |
310 | UINT64_C(0), |
311 | UINT64_C(0), |
312 | UINT64_C(0), |
313 | UINT64_C(0), |
314 | UINT64_C(0), |
315 | UINT64_C(0), |
316 | UINT64_C(0), |
317 | UINT64_C(0), |
318 | UINT64_C(0), |
319 | UINT64_C(0), |
320 | UINT64_C(0), |
321 | UINT64_C(0), |
322 | UINT64_C(0), |
323 | UINT64_C(0), |
324 | UINT64_C(0), |
325 | UINT64_C(0), |
326 | UINT64_C(0), |
327 | UINT64_C(0), |
328 | UINT64_C(0), |
329 | UINT64_C(0), |
330 | UINT64_C(0), |
331 | UINT64_C(0), |
332 | UINT64_C(0), |
333 | UINT64_C(0), |
334 | UINT64_C(0), |
335 | UINT64_C(0), |
336 | UINT64_C(0), |
337 | UINT64_C(0), |
338 | UINT64_C(0), |
339 | UINT64_C(0), |
340 | UINT64_C(0), |
341 | UINT64_C(0), |
342 | UINT64_C(0), |
343 | UINT64_C(0), |
344 | UINT64_C(0), |
345 | UINT64_C(0), |
346 | UINT64_C(0), |
347 | UINT64_C(0), |
348 | UINT64_C(0), |
349 | UINT64_C(0), |
350 | UINT64_C(0), |
351 | UINT64_C(0), |
352 | UINT64_C(0), |
353 | UINT64_C(0), |
354 | UINT64_C(0), |
355 | UINT64_C(0), |
356 | UINT64_C(0), |
357 | UINT64_C(0), |
358 | UINT64_C(0), |
359 | UINT64_C(0), |
360 | UINT64_C(0), |
361 | UINT64_C(0), |
362 | UINT64_C(0), |
363 | UINT64_C(0), |
364 | UINT64_C(0), |
365 | UINT64_C(0), |
366 | UINT64_C(0), |
367 | UINT64_C(0), |
368 | UINT64_C(0), |
369 | UINT64_C(0), |
370 | UINT64_C(0), |
371 | UINT64_C(0), |
372 | UINT64_C(0), |
373 | UINT64_C(0), |
374 | UINT64_C(0), |
375 | UINT64_C(0), |
376 | UINT64_C(0), |
377 | UINT64_C(0), |
378 | UINT64_C(0), |
379 | UINT64_C(0), |
380 | UINT64_C(0), |
381 | UINT64_C(0), |
382 | UINT64_C(0), |
383 | UINT64_C(0), |
384 | UINT64_C(0), |
385 | UINT64_C(0), |
386 | UINT64_C(0), |
387 | UINT64_C(0), |
388 | UINT64_C(0), |
389 | UINT64_C(0), |
390 | UINT64_C(0), |
391 | UINT64_C(0), |
392 | UINT64_C(0), |
393 | UINT64_C(0), |
394 | UINT64_C(0), |
395 | UINT64_C(0), |
396 | UINT64_C(0), |
397 | UINT64_C(2080375316), // ADD4 |
398 | UINT64_C(2080376340), // ADD4O |
399 | UINT64_C(2080376341), // ADD4O_rec |
400 | UINT64_C(2080375316), // ADD4TLS |
401 | UINT64_C(2080375317), // ADD4_rec |
402 | UINT64_C(2080375316), // ADD8 |
403 | UINT64_C(2080376340), // ADD8O |
404 | UINT64_C(2080376341), // ADD8O_rec |
405 | UINT64_C(2080375316), // ADD8TLS |
406 | UINT64_C(2080375316), // ADD8TLS_ |
407 | UINT64_C(2080375317), // ADD8_rec |
408 | UINT64_C(2080374804), // ADDC |
409 | UINT64_C(2080374804), // ADDC8 |
410 | UINT64_C(2080375828), // ADDC8O |
411 | UINT64_C(2080375829), // ADDC8O_rec |
412 | UINT64_C(2080374805), // ADDC8_rec |
413 | UINT64_C(2080375828), // ADDCO |
414 | UINT64_C(2080375829), // ADDCO_rec |
415 | UINT64_C(2080374805), // ADDC_rec |
416 | UINT64_C(2080375060), // ADDE |
417 | UINT64_C(2080375060), // ADDE8 |
418 | UINT64_C(2080376084), // ADDE8O |
419 | UINT64_C(2080376085), // ADDE8O_rec |
420 | UINT64_C(2080375061), // ADDE8_rec |
421 | UINT64_C(2080376084), // ADDEO |
422 | UINT64_C(2080376085), // ADDEO_rec |
423 | UINT64_C(2080375124), // ADDEX |
424 | UINT64_C(2080375124), // ADDEX8 |
425 | UINT64_C(2080375061), // ADDE_rec |
426 | UINT64_C(2080374932), // ADDG6S |
427 | UINT64_C(2080374932), // ADDG6S8 |
428 | UINT64_C(939524096), // ADDI |
429 | UINT64_C(939524096), // ADDI8 |
430 | UINT64_C(805306368), // ADDIC |
431 | UINT64_C(805306368), // ADDIC8 |
432 | UINT64_C(872415232), // ADDIC_rec |
433 | UINT64_C(1006632960), // ADDIS |
434 | UINT64_C(1006632960), // ADDIS8 |
435 | UINT64_C(0), // ADDISdtprelHA |
436 | UINT64_C(0), // ADDISdtprelHA32 |
437 | UINT64_C(0), // ADDISgotTprelHA |
438 | UINT64_C(0), // ADDIStlsgdHA |
439 | UINT64_C(0), // ADDIStlsldHA |
440 | UINT64_C(0), // ADDIStocHA |
441 | UINT64_C(0), // ADDIStocHA8 |
442 | UINT64_C(0), // ADDIdtprelL |
443 | UINT64_C(0), // ADDIdtprelL32 |
444 | UINT64_C(0), // ADDItlsgdL |
445 | UINT64_C(0), // ADDItlsgdL32 |
446 | UINT64_C(0), // ADDItlsgdLADDR |
447 | UINT64_C(0), // ADDItlsgdLADDR32 |
448 | UINT64_C(0), // ADDItlsldL |
449 | UINT64_C(0), // ADDItlsldL32 |
450 | UINT64_C(0), // ADDItlsldLADDR |
451 | UINT64_C(0), // ADDItlsldLADDR32 |
452 | UINT64_C(0), // ADDItoc |
453 | UINT64_C(0), // ADDItoc8 |
454 | UINT64_C(0), // ADDItocL |
455 | UINT64_C(0), // ADDItocL8 |
456 | UINT64_C(2080375252), // ADDME |
457 | UINT64_C(2080375252), // ADDME8 |
458 | UINT64_C(2080376276), // ADDME8O |
459 | UINT64_C(2080376277), // ADDME8O_rec |
460 | UINT64_C(2080375253), // ADDME8_rec |
461 | UINT64_C(2080376276), // ADDMEO |
462 | UINT64_C(2080376277), // ADDMEO_rec |
463 | UINT64_C(2080375253), // ADDME_rec |
464 | UINT64_C(1275068420), // ADDPCIS |
465 | UINT64_C(2080375188), // ADDZE |
466 | UINT64_C(2080375188), // ADDZE8 |
467 | UINT64_C(2080376212), // ADDZE8O |
468 | UINT64_C(2080376213), // ADDZE8O_rec |
469 | UINT64_C(2080375189), // ADDZE8_rec |
470 | UINT64_C(2080376212), // ADDZEO |
471 | UINT64_C(2080376213), // ADDZEO_rec |
472 | UINT64_C(2080375189), // ADDZE_rec |
473 | UINT64_C(0), // ADJCALLSTACKDOWN |
474 | UINT64_C(0), // ADJCALLSTACKUP |
475 | UINT64_C(2080374840), // AND |
476 | UINT64_C(2080374840), // AND8 |
477 | UINT64_C(2080374841), // AND8_rec |
478 | UINT64_C(2080374904), // ANDC |
479 | UINT64_C(2080374904), // ANDC8 |
480 | UINT64_C(2080374905), // ANDC8_rec |
481 | UINT64_C(2080374905), // ANDC_rec |
482 | UINT64_C(1879048192), // ANDI8_rec |
483 | UINT64_C(1946157056), // ANDIS8_rec |
484 | UINT64_C(1946157056), // ANDIS_rec |
485 | UINT64_C(1879048192), // ANDI_rec |
486 | UINT64_C(0), // ANDI_rec_1_EQ_BIT |
487 | UINT64_C(0), // ANDI_rec_1_EQ_BIT8 |
488 | UINT64_C(0), // ANDI_rec_1_GT_BIT |
489 | UINT64_C(0), // ANDI_rec_1_GT_BIT8 |
490 | UINT64_C(2080374841), // AND_rec |
491 | UINT64_C(0), // ATOMIC_CMP_SWAP_I16 |
492 | UINT64_C(0), // ATOMIC_CMP_SWAP_I32 |
493 | UINT64_C(0), // ATOMIC_CMP_SWAP_I64 |
494 | UINT64_C(0), // ATOMIC_CMP_SWAP_I8 |
495 | UINT64_C(0), // ATOMIC_LOAD_ADD_I16 |
496 | UINT64_C(0), // ATOMIC_LOAD_ADD_I32 |
497 | UINT64_C(0), // ATOMIC_LOAD_ADD_I64 |
498 | UINT64_C(0), // ATOMIC_LOAD_ADD_I8 |
499 | UINT64_C(0), // ATOMIC_LOAD_AND_I16 |
500 | UINT64_C(0), // ATOMIC_LOAD_AND_I32 |
501 | UINT64_C(0), // ATOMIC_LOAD_AND_I64 |
502 | UINT64_C(0), // ATOMIC_LOAD_AND_I8 |
503 | UINT64_C(0), // ATOMIC_LOAD_MAX_I16 |
504 | UINT64_C(0), // ATOMIC_LOAD_MAX_I32 |
505 | UINT64_C(0), // ATOMIC_LOAD_MAX_I64 |
506 | UINT64_C(0), // ATOMIC_LOAD_MAX_I8 |
507 | UINT64_C(0), // ATOMIC_LOAD_MIN_I16 |
508 | UINT64_C(0), // ATOMIC_LOAD_MIN_I32 |
509 | UINT64_C(0), // ATOMIC_LOAD_MIN_I64 |
510 | UINT64_C(0), // ATOMIC_LOAD_MIN_I8 |
511 | UINT64_C(0), // ATOMIC_LOAD_NAND_I16 |
512 | UINT64_C(0), // ATOMIC_LOAD_NAND_I32 |
513 | UINT64_C(0), // ATOMIC_LOAD_NAND_I64 |
514 | UINT64_C(0), // ATOMIC_LOAD_NAND_I8 |
515 | UINT64_C(0), // ATOMIC_LOAD_OR_I16 |
516 | UINT64_C(0), // ATOMIC_LOAD_OR_I32 |
517 | UINT64_C(0), // ATOMIC_LOAD_OR_I64 |
518 | UINT64_C(0), // ATOMIC_LOAD_OR_I8 |
519 | UINT64_C(0), // ATOMIC_LOAD_SUB_I16 |
520 | UINT64_C(0), // ATOMIC_LOAD_SUB_I32 |
521 | UINT64_C(0), // ATOMIC_LOAD_SUB_I64 |
522 | UINT64_C(0), // ATOMIC_LOAD_SUB_I8 |
523 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I16 |
524 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I32 |
525 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I64 |
526 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I8 |
527 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I16 |
528 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I32 |
529 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I64 |
530 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I8 |
531 | UINT64_C(0), // ATOMIC_LOAD_XOR_I16 |
532 | UINT64_C(0), // ATOMIC_LOAD_XOR_I32 |
533 | UINT64_C(0), // ATOMIC_LOAD_XOR_I64 |
534 | UINT64_C(0), // ATOMIC_LOAD_XOR_I8 |
535 | UINT64_C(0), // ATOMIC_SWAP_I16 |
536 | UINT64_C(0), // ATOMIC_SWAP_I32 |
537 | UINT64_C(0), // ATOMIC_SWAP_I64 |
538 | UINT64_C(0), // ATOMIC_SWAP_I8 |
539 | UINT64_C(512), // ATTN |
540 | UINT64_C(1207959552), // B |
541 | UINT64_C(1207959554), // BA |
542 | UINT64_C(1098907648), // BC |
543 | UINT64_C(1073741824), // BCC |
544 | UINT64_C(1073741826), // BCCA |
545 | UINT64_C(1275069472), // BCCCTR |
546 | UINT64_C(1275069472), // BCCCTR8 |
547 | UINT64_C(1275069473), // BCCCTRL |
548 | UINT64_C(1275069473), // BCCCTRL8 |
549 | UINT64_C(1073741825), // BCCL |
550 | UINT64_C(1073741827), // BCCLA |
551 | UINT64_C(1275068448), // BCCLR |
552 | UINT64_C(1275068449), // BCCLRL |
553 | UINT64_C(1300235296), // BCCTR |
554 | UINT64_C(1300235296), // BCCTR8 |
555 | UINT64_C(1283458080), // BCCTR8n |
556 | UINT64_C(1300235297), // BCCTRL |
557 | UINT64_C(1300235297), // BCCTRL8 |
558 | UINT64_C(1283458081), // BCCTRL8n |
559 | UINT64_C(1283458081), // BCCTRLn |
560 | UINT64_C(1283458080), // BCCTRn |
561 | UINT64_C(268436481), // BCDADD_rec |
562 | UINT64_C(268895617), // BCDCFN_rec |
563 | UINT64_C(268567937), // BCDCFSQ_rec |
564 | UINT64_C(268830081), // BCDCFZ_rec |
565 | UINT64_C(268436289), // BCDCPSGN_rec |
566 | UINT64_C(268764545), // BCDCTN_rec |
567 | UINT64_C(268436865), // BCDCTSQ_rec |
568 | UINT64_C(268699009), // BCDCTZ_rec |
569 | UINT64_C(270468481), // BCDSETSGN_rec |
570 | UINT64_C(268436929), // BCDSR_rec |
571 | UINT64_C(268436545), // BCDSUB_rec |
572 | UINT64_C(268436673), // BCDS_rec |
573 | UINT64_C(268436737), // BCDTRUNC_rec |
574 | UINT64_C(268436609), // BCDUS_rec |
575 | UINT64_C(268436801), // BCDUTRUNC_rec |
576 | UINT64_C(1098907649), // BCL |
577 | UINT64_C(1300234272), // BCLR |
578 | UINT64_C(1300234273), // BCLRL |
579 | UINT64_C(1283457057), // BCLRLn |
580 | UINT64_C(1283457056), // BCLRn |
581 | UINT64_C(1117716481), // BCLalways |
582 | UINT64_C(1082130433), // BCLn |
583 | UINT64_C(1317012512), // BCTR |
584 | UINT64_C(1317012512), // BCTR8 |
585 | UINT64_C(1317012513), // BCTRL |
586 | UINT64_C(1317012513), // BCTRL8 |
587 | UINT64_C(5656525675654283264), // BCTRL8_LDinto_toc |
588 | UINT64_C(5656525675654283264), // BCTRL8_LDinto_toc_RM |
589 | UINT64_C(1317012513), // BCTRL8_RM |
590 | UINT64_C(5656525673909452800), // BCTRL_LWZinto_toc |
591 | UINT64_C(5656525673909452800), // BCTRL_LWZinto_toc_RM |
592 | UINT64_C(1317012513), // BCTRL_RM |
593 | UINT64_C(1082130432), // BCn |
594 | UINT64_C(1107296256), // BDNZ |
595 | UINT64_C(1107296256), // BDNZ8 |
596 | UINT64_C(1107296258), // BDNZA |
597 | UINT64_C(1124073474), // BDNZAm |
598 | UINT64_C(1126170626), // BDNZAp |
599 | UINT64_C(1107296257), // BDNZL |
600 | UINT64_C(1107296259), // BDNZLA |
601 | UINT64_C(1124073475), // BDNZLAm |
602 | UINT64_C(1126170627), // BDNZLAp |
603 | UINT64_C(1308622880), // BDNZLR |
604 | UINT64_C(1308622880), // BDNZLR8 |
605 | UINT64_C(1308622881), // BDNZLRL |
606 | UINT64_C(1325400097), // BDNZLRLm |
607 | UINT64_C(1327497249), // BDNZLRLp |
608 | UINT64_C(1325400096), // BDNZLRm |
609 | UINT64_C(1327497248), // BDNZLRp |
610 | UINT64_C(1124073473), // BDNZLm |
611 | UINT64_C(1126170625), // BDNZLp |
612 | UINT64_C(1124073472), // BDNZm |
613 | UINT64_C(1126170624), // BDNZp |
614 | UINT64_C(1111490560), // BDZ |
615 | UINT64_C(1111490560), // BDZ8 |
616 | UINT64_C(1111490562), // BDZA |
617 | UINT64_C(1128267778), // BDZAm |
618 | UINT64_C(1130364930), // BDZAp |
619 | UINT64_C(1111490561), // BDZL |
620 | UINT64_C(1111490563), // BDZLA |
621 | UINT64_C(1128267779), // BDZLAm |
622 | UINT64_C(1130364931), // BDZLAp |
623 | UINT64_C(1312817184), // BDZLR |
624 | UINT64_C(1312817184), // BDZLR8 |
625 | UINT64_C(1312817185), // BDZLRL |
626 | UINT64_C(1329594401), // BDZLRLm |
627 | UINT64_C(1331691553), // BDZLRLp |
628 | UINT64_C(1329594400), // BDZLRm |
629 | UINT64_C(1331691552), // BDZLRp |
630 | UINT64_C(1128267777), // BDZLm |
631 | UINT64_C(1130364929), // BDZLp |
632 | UINT64_C(1128267776), // BDZm |
633 | UINT64_C(1130364928), // BDZp |
634 | UINT64_C(1207959553), // BL |
635 | UINT64_C(1207959553), // BL8 |
636 | UINT64_C(5188146776636391424), // BL8_NOP |
637 | UINT64_C(5188146776636391424), // BL8_NOP_RM |
638 | UINT64_C(5188146776636391424), // BL8_NOP_TLS |
639 | UINT64_C(1207959553), // BL8_NOTOC |
640 | UINT64_C(1207959553), // BL8_NOTOC_RM |
641 | UINT64_C(1207959553), // BL8_NOTOC_TLS |
642 | UINT64_C(1207959553), // BL8_RM |
643 | UINT64_C(1207959553), // BL8_TLS |
644 | UINT64_C(1207959553), // BL8_TLS_ |
645 | UINT64_C(1207959555), // BLA |
646 | UINT64_C(1207959555), // BLA8 |
647 | UINT64_C(5188146785226326016), // BLA8_NOP |
648 | UINT64_C(5188146785226326016), // BLA8_NOP_RM |
649 | UINT64_C(1207959555), // BLA8_RM |
650 | UINT64_C(1207959555), // BLA_RM |
651 | UINT64_C(1317011488), // BLR |
652 | UINT64_C(1317011488), // BLR8 |
653 | UINT64_C(1317011489), // BLRL |
654 | UINT64_C(5188146776636391424), // BL_NOP |
655 | UINT64_C(5188146776636391424), // BL_NOP_RM |
656 | UINT64_C(1207959553), // BL_RM |
657 | UINT64_C(1207959553), // BL_TLS |
658 | UINT64_C(2080375288), // BPERMD |
659 | UINT64_C(2080375158), // BRD |
660 | UINT64_C(2080375222), // BRH |
661 | UINT64_C(2080375222), // BRH8 |
662 | UINT64_C(268435983), // BRINC |
663 | UINT64_C(2080375094), // BRW |
664 | UINT64_C(2080375094), // BRW8 |
665 | UINT64_C(2080375412), // CBCDTD |
666 | UINT64_C(2080375412), // CBCDTD8 |
667 | UINT64_C(2080375348), // CDTBCD |
668 | UINT64_C(2080375348), // CDTBCD8 |
669 | UINT64_C(2080375224), // CFUGED |
670 | UINT64_C(2080375644), // CLRBHRB |
671 | UINT64_C(2080375800), // CMPB |
672 | UINT64_C(2080375800), // CMPB8 |
673 | UINT64_C(2082471936), // CMPD |
674 | UINT64_C(740294656), // CMPDI |
675 | UINT64_C(2080375232), // CMPEQB |
676 | UINT64_C(2082472000), // CMPLD |
677 | UINT64_C(673185792), // CMPLDI |
678 | UINT64_C(2080374848), // CMPLW |
679 | UINT64_C(671088640), // CMPLWI |
680 | UINT64_C(2080375168), // CMPRB |
681 | UINT64_C(2080375168), // CMPRB8 |
682 | UINT64_C(2080374784), // CMPW |
683 | UINT64_C(738197504), // CMPWI |
684 | UINT64_C(2080374900), // CNTLZD |
685 | UINT64_C(2080374902), // CNTLZDM |
686 | UINT64_C(2080374901), // CNTLZD_rec |
687 | UINT64_C(2080374836), // CNTLZW |
688 | UINT64_C(2080374836), // CNTLZW8 |
689 | UINT64_C(2080374837), // CNTLZW8_rec |
690 | UINT64_C(2080374837), // CNTLZW_rec |
691 | UINT64_C(2080375924), // CNTTZD |
692 | UINT64_C(2080375926), // CNTTZDM |
693 | UINT64_C(2080375925), // CNTTZD_rec |
694 | UINT64_C(2080375860), // CNTTZW |
695 | UINT64_C(2080375860), // CNTTZW8 |
696 | UINT64_C(2080375861), // CNTTZW8_rec |
697 | UINT64_C(2080375861), // CNTTZW_rec |
698 | UINT64_C(2080376460), // CP_ABORT |
699 | UINT64_C(2082473484), // CP_COPY |
700 | UINT64_C(2082473484), // CP_COPY8 |
701 | UINT64_C(2080376589), // CP_PASTE8_rec |
702 | UINT64_C(2080376589), // CP_PASTE_rec |
703 | UINT64_C(1288057410), // CR6SET |
704 | UINT64_C(1288057218), // CR6UNSET |
705 | UINT64_C(1275068930), // CRAND |
706 | UINT64_C(1275068674), // CRANDC |
707 | UINT64_C(1275068994), // CREQV |
708 | UINT64_C(1275068866), // CRNAND |
709 | UINT64_C(1275068482), // CRNOR |
710 | UINT64_C(1275068482), // CRNOT |
711 | UINT64_C(1275069314), // CROR |
712 | UINT64_C(1275069250), // CRORC |
713 | UINT64_C(1275068994), // CRSET |
714 | UINT64_C(1275068802), // CRUNSET |
715 | UINT64_C(1275068802), // CRXOR |
716 | UINT64_C(1073741824), // CTRL_DEP |
717 | UINT64_C(3959422980), // DADD |
718 | UINT64_C(4227858436), // DADDQ |
719 | UINT64_C(4227858437), // DADDQ_rec |
720 | UINT64_C(3959422981), // DADD_rec |
721 | UINT64_C(2080376294), // DARN |
722 | UINT64_C(2080376300), // DCBA |
723 | UINT64_C(2080374956), // DCBF |
724 | UINT64_C(2080375038), // DCBFEP |
725 | UINT64_C(2080375724), // DCBI |
726 | UINT64_C(2080374892), // DCBST |
727 | UINT64_C(2080374910), // DCBSTEP |
728 | UINT64_C(2080375340), // DCBT |
729 | UINT64_C(2080375422), // DCBTEP |
730 | UINT64_C(2080375276), // DCBTST |
731 | UINT64_C(2080375294), // DCBTSTEP |
732 | UINT64_C(2080376812), // DCBZ |
733 | UINT64_C(2080376830), // DCBZEP |
734 | UINT64_C(2082473964), // DCBZL |
735 | UINT64_C(2082473982), // DCBZLEP |
736 | UINT64_C(2080375692), // DCCCI |
737 | UINT64_C(3959424580), // DCFFIX |
738 | UINT64_C(4227860036), // DCFFIXQ |
739 | UINT64_C(4227860420), // DCFFIXQQ |
740 | UINT64_C(4227860037), // DCFFIXQ_rec |
741 | UINT64_C(3959424581), // DCFFIX_rec |
742 | UINT64_C(3959423236), // DCMPO |
743 | UINT64_C(4227858692), // DCMPOQ |
744 | UINT64_C(3959424260), // DCMPU |
745 | UINT64_C(4227859716), // DCMPUQ |
746 | UINT64_C(3959423492), // DCTDP |
747 | UINT64_C(3959423493), // DCTDP_rec |
748 | UINT64_C(3959423556), // DCTFIX |
749 | UINT64_C(4227859012), // DCTFIXQ |
750 | UINT64_C(4227925956), // DCTFIXQQ |
751 | UINT64_C(4227859013), // DCTFIXQ_rec |
752 | UINT64_C(3959423557), // DCTFIX_rec |
753 | UINT64_C(4227858948), // DCTQPQ |
754 | UINT64_C(4227858949), // DCTQPQ_rec |
755 | UINT64_C(3959423620), // DDEDPD |
756 | UINT64_C(4227859076), // DDEDPDQ |
757 | UINT64_C(4227859077), // DDEDPDQ_rec |
758 | UINT64_C(3959423621), // DDEDPD_rec |
759 | UINT64_C(3959424068), // DDIV |
760 | UINT64_C(4227859524), // DDIVQ |
761 | UINT64_C(4227859525), // DDIVQ_rec |
762 | UINT64_C(3959424069), // DDIV_rec |
763 | UINT64_C(3959424644), // DENBCD |
764 | UINT64_C(4227860100), // DENBCDQ |
765 | UINT64_C(4227860101), // DENBCDQ_rec |
766 | UINT64_C(3959424645), // DENBCD_rec |
767 | UINT64_C(3959424708), // DIEX |
768 | UINT64_C(4227860164), // DIEXQ |
769 | UINT64_C(4227860165), // DIEXQ_rec |
770 | UINT64_C(3959424709), // DIEX_rec |
771 | UINT64_C(2080375762), // DIVD |
772 | UINT64_C(2080375634), // DIVDE |
773 | UINT64_C(2080376658), // DIVDEO |
774 | UINT64_C(2080376659), // DIVDEO_rec |
775 | UINT64_C(2080375570), // DIVDEU |
776 | UINT64_C(2080376594), // DIVDEUO |
777 | UINT64_C(2080376595), // DIVDEUO_rec |
778 | UINT64_C(2080375571), // DIVDEU_rec |
779 | UINT64_C(2080375635), // DIVDE_rec |
780 | UINT64_C(2080376786), // DIVDO |
781 | UINT64_C(2080376787), // DIVDO_rec |
782 | UINT64_C(2080375698), // DIVDU |
783 | UINT64_C(2080376722), // DIVDUO |
784 | UINT64_C(2080376723), // DIVDUO_rec |
785 | UINT64_C(2080375699), // DIVDU_rec |
786 | UINT64_C(2080375763), // DIVD_rec |
787 | UINT64_C(2080375766), // DIVW |
788 | UINT64_C(2080375638), // DIVWE |
789 | UINT64_C(2080376662), // DIVWEO |
790 | UINT64_C(2080376663), // DIVWEO_rec |
791 | UINT64_C(2080375574), // DIVWEU |
792 | UINT64_C(2080376598), // DIVWEUO |
793 | UINT64_C(2080376599), // DIVWEUO_rec |
794 | UINT64_C(2080375575), // DIVWEU_rec |
795 | UINT64_C(2080375639), // DIVWE_rec |
796 | UINT64_C(2080376790), // DIVWO |
797 | UINT64_C(2080376791), // DIVWO_rec |
798 | UINT64_C(2080375702), // DIVWU |
799 | UINT64_C(2080376726), // DIVWUO |
800 | UINT64_C(2080376727), // DIVWUO_rec |
801 | UINT64_C(2080375703), // DIVWU_rec |
802 | UINT64_C(2080375767), // DIVW_rec |
803 | UINT64_C(2080768354), // DMMR |
804 | UINT64_C(2080506210), // DMSETDMRZ |
805 | UINT64_C(3959423044), // DMUL |
806 | UINT64_C(4227858500), // DMULQ |
807 | UINT64_C(4227858501), // DMULQ_rec |
808 | UINT64_C(3959423045), // DMUL_rec |
809 | UINT64_C(2080833890), // DMXOR |
810 | UINT64_C(4026533776), // DMXXEXTFDMR256 |
811 | UINT64_C(4026533648), // DMXXEXTFDMR512 |
812 | UINT64_C(4026599184), // DMXXEXTFDMR512_HI |
813 | UINT64_C(4026533780), // DMXXINSTFDMR256 |
814 | UINT64_C(4026533712), // DMXXINSTFDMR512 |
815 | UINT64_C(4026599248), // DMXXINSTFDMR512_HI |
816 | UINT64_C(3959422982), // DQUA |
817 | UINT64_C(3959423110), // DQUAI |
818 | UINT64_C(4227858566), // DQUAIQ |
819 | UINT64_C(4227858567), // DQUAIQ_rec |
820 | UINT64_C(3959423111), // DQUAI_rec |
821 | UINT64_C(4227858438), // DQUAQ |
822 | UINT64_C(4227858439), // DQUAQ_rec |
823 | UINT64_C(3959422983), // DQUA_rec |
824 | UINT64_C(4227859972), // DRDPQ |
825 | UINT64_C(4227859973), // DRDPQ_rec |
826 | UINT64_C(3959423430), // DRINTN |
827 | UINT64_C(4227858886), // DRINTNQ |
828 | UINT64_C(4227858887), // DRINTNQ_rec |
829 | UINT64_C(3959423431), // DRINTN_rec |
830 | UINT64_C(3959423174), // DRINTX |
831 | UINT64_C(4227858630), // DRINTXQ |
832 | UINT64_C(4227858631), // DRINTXQ_rec |
833 | UINT64_C(3959423175), // DRINTX_rec |
834 | UINT64_C(3959423046), // DRRND |
835 | UINT64_C(4227858502), // DRRNDQ |
836 | UINT64_C(4227858503), // DRRNDQ_rec |
837 | UINT64_C(3959423047), // DRRND_rec |
838 | UINT64_C(3959424516), // DRSP |
839 | UINT64_C(3959424517), // DRSP_rec |
840 | UINT64_C(3959423108), // DSCLI |
841 | UINT64_C(4227858564), // DSCLIQ |
842 | UINT64_C(4227858565), // DSCLIQ_rec |
843 | UINT64_C(3959423109), // DSCLI_rec |
844 | UINT64_C(3959423172), // DSCRI |
845 | UINT64_C(4227858628), // DSCRIQ |
846 | UINT64_C(4227858629), // DSCRIQ_rec |
847 | UINT64_C(3959423173), // DSCRI_rec |
848 | UINT64_C(2080376428), // DSS |
849 | UINT64_C(2113930860), // DSSALL |
850 | UINT64_C(2080375468), // DST |
851 | UINT64_C(2080375468), // DST64 |
852 | UINT64_C(2080375532), // DSTST |
853 | UINT64_C(2080375532), // DSTST64 |
854 | UINT64_C(2113929964), // DSTSTT |
855 | UINT64_C(2113929964), // DSTSTT64 |
856 | UINT64_C(2113929900), // DSTT |
857 | UINT64_C(2113929900), // DSTT64 |
858 | UINT64_C(3959424004), // DSUB |
859 | UINT64_C(4227859460), // DSUBQ |
860 | UINT64_C(4227859461), // DSUBQ_rec |
861 | UINT64_C(3959424005), // DSUB_rec |
862 | UINT64_C(3959423364), // DTSTDC |
863 | UINT64_C(4227858820), // DTSTDCQ |
864 | UINT64_C(3959423428), // DTSTDG |
865 | UINT64_C(4227858884), // DTSTDGQ |
866 | UINT64_C(3959423300), // DTSTEX |
867 | UINT64_C(4227858756), // DTSTEXQ |
868 | UINT64_C(3959424324), // DTSTSF |
869 | UINT64_C(3959424326), // DTSTSFI |
870 | UINT64_C(4227859782), // DTSTSFIQ |
871 | UINT64_C(4227859780), // DTSTSFQ |
872 | UINT64_C(3959423684), // DXEX |
873 | UINT64_C(4227859140), // DXEXQ |
874 | UINT64_C(4227859141), // DXEXQ_rec |
875 | UINT64_C(3959423685), // DXEX_rec |
876 | UINT64_C(0), // DYNALLOC |
877 | UINT64_C(0), // DYNALLOC8 |
878 | UINT64_C(0), // DYNAREAOFFSET |
879 | UINT64_C(0), // DYNAREAOFFSET8 |
880 | UINT64_C(0), // DecreaseCTR8loop |
881 | UINT64_C(0), // DecreaseCTRloop |
882 | UINT64_C(268436196), // EFDABS |
883 | UINT64_C(268436192), // EFDADD |
884 | UINT64_C(268436207), // EFDCFS |
885 | UINT64_C(268436211), // EFDCFSF |
886 | UINT64_C(268436209), // EFDCFSI |
887 | UINT64_C(268436195), // EFDCFSID |
888 | UINT64_C(268436210), // EFDCFUF |
889 | UINT64_C(268436208), // EFDCFUI |
890 | UINT64_C(268436194), // EFDCFUID |
891 | UINT64_C(268436206), // EFDCMPEQ |
892 | UINT64_C(268436204), // EFDCMPGT |
893 | UINT64_C(268436205), // EFDCMPLT |
894 | UINT64_C(268436215), // EFDCTSF |
895 | UINT64_C(268436213), // EFDCTSI |
896 | UINT64_C(268436203), // EFDCTSIDZ |
897 | UINT64_C(268436218), // EFDCTSIZ |
898 | UINT64_C(268436214), // EFDCTUF |
899 | UINT64_C(268436212), // EFDCTUI |
900 | UINT64_C(268436202), // EFDCTUIDZ |
901 | UINT64_C(268436216), // EFDCTUIZ |
902 | UINT64_C(268436201), // EFDDIV |
903 | UINT64_C(268436200), // EFDMUL |
904 | UINT64_C(268436197), // EFDNABS |
905 | UINT64_C(268436198), // EFDNEG |
906 | UINT64_C(268436193), // EFDSUB |
907 | UINT64_C(268436222), // EFDTSTEQ |
908 | UINT64_C(268436220), // EFDTSTGT |
909 | UINT64_C(268436221), // EFDTSTLT |
910 | UINT64_C(268436164), // EFSABS |
911 | UINT64_C(268436160), // EFSADD |
912 | UINT64_C(268436175), // EFSCFD |
913 | UINT64_C(268436179), // EFSCFSF |
914 | UINT64_C(268436177), // EFSCFSI |
915 | UINT64_C(268436178), // EFSCFUF |
916 | UINT64_C(268436176), // EFSCFUI |
917 | UINT64_C(268436174), // EFSCMPEQ |
918 | UINT64_C(268436172), // EFSCMPGT |
919 | UINT64_C(268436173), // EFSCMPLT |
920 | UINT64_C(268436183), // EFSCTSF |
921 | UINT64_C(268436181), // EFSCTSI |
922 | UINT64_C(268436186), // EFSCTSIZ |
923 | UINT64_C(268436182), // EFSCTUF |
924 | UINT64_C(268436180), // EFSCTUI |
925 | UINT64_C(268436184), // EFSCTUIZ |
926 | UINT64_C(268436169), // EFSDIV |
927 | UINT64_C(268436168), // EFSMUL |
928 | UINT64_C(268436165), // EFSNABS |
929 | UINT64_C(268436166), // EFSNEG |
930 | UINT64_C(268436161), // EFSSUB |
931 | UINT64_C(268436190), // EFSTSTEQ |
932 | UINT64_C(268436188), // EFSTSTGT |
933 | UINT64_C(268436189), // EFSTSTLT |
934 | UINT64_C(0), // EH_SjLj_LongJmp32 |
935 | UINT64_C(0), // EH_SjLj_LongJmp64 |
936 | UINT64_C(0), // EH_SjLj_SetJmp32 |
937 | UINT64_C(0), // EH_SjLj_SetJmp64 |
938 | UINT64_C(0), // EH_SjLj_Setup |
939 | UINT64_C(2080375352), // EQV |
940 | UINT64_C(2080375352), // EQV8 |
941 | UINT64_C(2080375353), // EQV8_rec |
942 | UINT64_C(2080375353), // EQV_rec |
943 | UINT64_C(268435976), // EVABS |
944 | UINT64_C(268435970), // EVADDIW |
945 | UINT64_C(268436681), // EVADDSMIAAW |
946 | UINT64_C(268436673), // EVADDSSIAAW |
947 | UINT64_C(268436680), // EVADDUMIAAW |
948 | UINT64_C(268436672), // EVADDUSIAAW |
949 | UINT64_C(268435968), // EVADDW |
950 | UINT64_C(268435985), // EVAND |
951 | UINT64_C(268435986), // EVANDC |
952 | UINT64_C(268436020), // EVCMPEQ |
953 | UINT64_C(268436017), // EVCMPGTS |
954 | UINT64_C(268436016), // EVCMPGTU |
955 | UINT64_C(268436019), // EVCMPLTS |
956 | UINT64_C(268436018), // EVCMPLTU |
957 | UINT64_C(268435982), // EVCNTLSW |
958 | UINT64_C(268435981), // EVCNTLZW |
959 | UINT64_C(268436678), // EVDIVWS |
960 | UINT64_C(268436679), // EVDIVWU |
961 | UINT64_C(268435993), // EVEQV |
962 | UINT64_C(268435978), // EVEXTSB |
963 | UINT64_C(268435979), // EVEXTSH |
964 | UINT64_C(268436100), // EVFSABS |
965 | UINT64_C(268436096), // EVFSADD |
966 | UINT64_C(268436115), // EVFSCFSF |
967 | UINT64_C(268436113), // EVFSCFSI |
968 | UINT64_C(268436114), // EVFSCFUF |
969 | UINT64_C(268436106), // EVFSCFUI |
970 | UINT64_C(268436110), // EVFSCMPEQ |
971 | UINT64_C(268436108), // EVFSCMPGT |
972 | UINT64_C(268436109), // EVFSCMPLT |
973 | UINT64_C(268436119), // EVFSCTSF |
974 | UINT64_C(268436117), // EVFSCTSI |
975 | UINT64_C(268436122), // EVFSCTSIZ |
976 | UINT64_C(268436118), // EVFSCTUF |
977 | UINT64_C(268436116), // EVFSCTUI |
978 | UINT64_C(268436120), // EVFSCTUIZ |
979 | UINT64_C(268436105), // EVFSDIV |
980 | UINT64_C(268436104), // EVFSMUL |
981 | UINT64_C(268436101), // EVFSNABS |
982 | UINT64_C(268436102), // EVFSNEG |
983 | UINT64_C(268436097), // EVFSSUB |
984 | UINT64_C(268436126), // EVFSTSTEQ |
985 | UINT64_C(268436124), // EVFSTSTGT |
986 | UINT64_C(268436125), // EVFSTSTLT |
987 | UINT64_C(268436225), // EVLDD |
988 | UINT64_C(268436224), // EVLDDX |
989 | UINT64_C(268436229), // EVLDH |
990 | UINT64_C(268436228), // EVLDHX |
991 | UINT64_C(268436227), // EVLDW |
992 | UINT64_C(268436226), // EVLDWX |
993 | UINT64_C(268436233), // EVLHHESPLAT |
994 | UINT64_C(268436232), // EVLHHESPLATX |
995 | UINT64_C(268436239), // EVLHHOSSPLAT |
996 | UINT64_C(268436238), // EVLHHOSSPLATX |
997 | UINT64_C(268436237), // EVLHHOUSPLAT |
998 | UINT64_C(268436236), // EVLHHOUSPLATX |
999 | UINT64_C(268436241), // EVLWHE |
1000 | UINT64_C(268436240), // EVLWHEX |
1001 | UINT64_C(268436247), // EVLWHOS |
1002 | UINT64_C(268436246), // EVLWHOSX |
1003 | UINT64_C(268436245), // EVLWHOU |
1004 | UINT64_C(268436244), // EVLWHOUX |
1005 | UINT64_C(268436253), // EVLWHSPLAT |
1006 | UINT64_C(268436252), // EVLWHSPLATX |
1007 | UINT64_C(268436249), // EVLWWSPLAT |
1008 | UINT64_C(268436248), // EVLWWSPLATX |
1009 | UINT64_C(268436012), // EVMERGEHI |
1010 | UINT64_C(268436014), // EVMERGEHILO |
1011 | UINT64_C(268436013), // EVMERGELO |
1012 | UINT64_C(268436015), // EVMERGELOHI |
1013 | UINT64_C(268436779), // EVMHEGSMFAA |
1014 | UINT64_C(268436907), // EVMHEGSMFAN |
1015 | UINT64_C(268436777), // EVMHEGSMIAA |
1016 | UINT64_C(268436905), // EVMHEGSMIAN |
1017 | UINT64_C(268436776), // EVMHEGUMIAA |
1018 | UINT64_C(268436904), // EVMHEGUMIAN |
1019 | UINT64_C(268436491), // EVMHESMF |
1020 | UINT64_C(268436523), // EVMHESMFA |
1021 | UINT64_C(268436747), // EVMHESMFAAW |
1022 | UINT64_C(268436875), // EVMHESMFANW |
1023 | UINT64_C(268436489), // EVMHESMI |
1024 | UINT64_C(268436521), // EVMHESMIA |
1025 | UINT64_C(268436745), // EVMHESMIAAW |
1026 | UINT64_C(268436873), // EVMHESMIANW |
1027 | UINT64_C(268436483), // EVMHESSF |
1028 | UINT64_C(268436515), // EVMHESSFA |
1029 | UINT64_C(268436739), // EVMHESSFAAW |
1030 | UINT64_C(268436867), // EVMHESSFANW |
1031 | UINT64_C(268436737), // EVMHESSIAAW |
1032 | UINT64_C(268436865), // EVMHESSIANW |
1033 | UINT64_C(268436488), // EVMHEUMI |
1034 | UINT64_C(268436520), // EVMHEUMIA |
1035 | UINT64_C(268436744), // EVMHEUMIAAW |
1036 | UINT64_C(268436872), // EVMHEUMIANW |
1037 | UINT64_C(268436736), // EVMHEUSIAAW |
1038 | UINT64_C(268436864), // EVMHEUSIANW |
1039 | UINT64_C(268436783), // EVMHOGSMFAA |
1040 | UINT64_C(268436911), // EVMHOGSMFAN |
1041 | UINT64_C(268436781), // EVMHOGSMIAA |
1042 | UINT64_C(268436909), // EVMHOGSMIAN |
1043 | UINT64_C(268436780), // EVMHOGUMIAA |
1044 | UINT64_C(268436908), // EVMHOGUMIAN |
1045 | UINT64_C(268436495), // EVMHOSMF |
1046 | UINT64_C(268436527), // EVMHOSMFA |
1047 | UINT64_C(268436751), // EVMHOSMFAAW |
1048 | UINT64_C(268436879), // EVMHOSMFANW |
1049 | UINT64_C(268436493), // EVMHOSMI |
1050 | UINT64_C(268436525), // EVMHOSMIA |
1051 | UINT64_C(268436749), // EVMHOSMIAAW |
1052 | UINT64_C(268436877), // EVMHOSMIANW |
1053 | UINT64_C(268436487), // EVMHOSSF |
1054 | UINT64_C(268436519), // EVMHOSSFA |
1055 | UINT64_C(268436743), // EVMHOSSFAAW |
1056 | UINT64_C(268436871), // EVMHOSSFANW |
1057 | UINT64_C(268436741), // EVMHOSSIAAW |
1058 | UINT64_C(268436869), // EVMHOSSIANW |
1059 | UINT64_C(268436492), // EVMHOUMI |
1060 | UINT64_C(268436524), // EVMHOUMIA |
1061 | UINT64_C(268436748), // EVMHOUMIAAW |
1062 | UINT64_C(268436876), // EVMHOUMIANW |
1063 | UINT64_C(268436740), // EVMHOUSIAAW |
1064 | UINT64_C(268436868), // EVMHOUSIANW |
1065 | UINT64_C(268436676), // EVMRA |
1066 | UINT64_C(268436559), // EVMWHSMF |
1067 | UINT64_C(268436591), // EVMWHSMFA |
1068 | UINT64_C(268436557), // EVMWHSMI |
1069 | UINT64_C(268436589), // EVMWHSMIA |
1070 | UINT64_C(268436551), // EVMWHSSF |
1071 | UINT64_C(268436583), // EVMWHSSFA |
1072 | UINT64_C(268436556), // EVMWHUMI |
1073 | UINT64_C(268436588), // EVMWHUMIA |
1074 | UINT64_C(268436809), // EVMWLSMIAAW |
1075 | UINT64_C(268436937), // EVMWLSMIANW |
1076 | UINT64_C(268436801), // EVMWLSSIAAW |
1077 | UINT64_C(268436929), // EVMWLSSIANW |
1078 | UINT64_C(268436552), // EVMWLUMI |
1079 | UINT64_C(268436584), // EVMWLUMIA |
1080 | UINT64_C(268436808), // EVMWLUMIAAW |
1081 | UINT64_C(268436936), // EVMWLUMIANW |
1082 | UINT64_C(268436800), // EVMWLUSIAAW |
1083 | UINT64_C(268436928), // EVMWLUSIANW |
1084 | UINT64_C(268436571), // EVMWSMF |
1085 | UINT64_C(268436603), // EVMWSMFA |
1086 | UINT64_C(268436827), // EVMWSMFAA |
1087 | UINT64_C(268436955), // EVMWSMFAN |
1088 | UINT64_C(268436569), // EVMWSMI |
1089 | UINT64_C(268436601), // EVMWSMIA |
1090 | UINT64_C(268436825), // EVMWSMIAA |
1091 | UINT64_C(268436953), // EVMWSMIAN |
1092 | UINT64_C(268436563), // EVMWSSF |
1093 | UINT64_C(268436595), // EVMWSSFA |
1094 | UINT64_C(268436819), // EVMWSSFAA |
1095 | UINT64_C(268436947), // EVMWSSFAN |
1096 | UINT64_C(268436568), // EVMWUMI |
1097 | UINT64_C(268436600), // EVMWUMIA |
1098 | UINT64_C(268436824), // EVMWUMIAA |
1099 | UINT64_C(268436952), // EVMWUMIAN |
1100 | UINT64_C(268435998), // EVNAND |
1101 | UINT64_C(268435977), // EVNEG |
1102 | UINT64_C(268435992), // EVNOR |
1103 | UINT64_C(268435991), // EVOR |
1104 | UINT64_C(268435995), // EVORC |
1105 | UINT64_C(268436008), // EVRLW |
1106 | UINT64_C(268436010), // EVRLWI |
1107 | UINT64_C(268435980), // EVRNDW |
1108 | UINT64_C(268436088), // EVSEL |
1109 | UINT64_C(268436004), // EVSLW |
1110 | UINT64_C(268436006), // EVSLWI |
1111 | UINT64_C(268436011), // EVSPLATFI |
1112 | UINT64_C(268436009), // EVSPLATI |
1113 | UINT64_C(268436003), // EVSRWIS |
1114 | UINT64_C(268436002), // EVSRWIU |
1115 | UINT64_C(268436001), // EVSRWS |
1116 | UINT64_C(268436000), // EVSRWU |
1117 | UINT64_C(268436257), // EVSTDD |
1118 | UINT64_C(268436256), // EVSTDDX |
1119 | UINT64_C(268436261), // EVSTDH |
1120 | UINT64_C(268436260), // EVSTDHX |
1121 | UINT64_C(268436259), // EVSTDW |
1122 | UINT64_C(268436258), // EVSTDWX |
1123 | UINT64_C(268436273), // EVSTWHE |
1124 | UINT64_C(268436272), // EVSTWHEX |
1125 | UINT64_C(268436277), // EVSTWHO |
1126 | UINT64_C(268436276), // EVSTWHOX |
1127 | UINT64_C(268436281), // EVSTWWE |
1128 | UINT64_C(268436280), // EVSTWWEX |
1129 | UINT64_C(268436285), // EVSTWWO |
1130 | UINT64_C(268436284), // EVSTWWOX |
1131 | UINT64_C(268436683), // EVSUBFSMIAAW |
1132 | UINT64_C(268436675), // EVSUBFSSIAAW |
1133 | UINT64_C(268436682), // EVSUBFUMIAAW |
1134 | UINT64_C(268436674), // EVSUBFUSIAAW |
1135 | UINT64_C(268435972), // EVSUBFW |
1136 | UINT64_C(268435974), // EVSUBIFW |
1137 | UINT64_C(268435990), // EVXOR |
1138 | UINT64_C(2080376692), // EXTSB |
1139 | UINT64_C(2080376692), // EXTSB8 |
1140 | UINT64_C(2080376692), // EXTSB8_32_64 |
1141 | UINT64_C(2080376693), // EXTSB8_rec |
1142 | UINT64_C(2080376693), // EXTSB_rec |
1143 | UINT64_C(2080376628), // EXTSH |
1144 | UINT64_C(2080376628), // EXTSH8 |
1145 | UINT64_C(2080376628), // EXTSH8_32_64 |
1146 | UINT64_C(2080376629), // EXTSH8_rec |
1147 | UINT64_C(2080376629), // EXTSH_rec |
1148 | UINT64_C(2080376756), // EXTSW |
1149 | UINT64_C(2080376564), // EXTSWSLI |
1150 | UINT64_C(2080376564), // EXTSWSLI_32_64 |
1151 | UINT64_C(2080376565), // EXTSWSLI_32_64_rec |
1152 | UINT64_C(2080376565), // EXTSWSLI_rec |
1153 | UINT64_C(2080376756), // EXTSW_32 |
1154 | UINT64_C(2080376756), // EXTSW_32_64 |
1155 | UINT64_C(2080376757), // EXTSW_32_64_rec |
1156 | UINT64_C(2080376757), // EXTSW_rec |
1157 | UINT64_C(2080376492), // EnforceIEIO |
1158 | UINT64_C(4227858960), // FABSD |
1159 | UINT64_C(4227858961), // FABSD_rec |
1160 | UINT64_C(4227858960), // FABSS |
1161 | UINT64_C(4227858961), // FABSS_rec |
1162 | UINT64_C(4227858474), // FADD |
1163 | UINT64_C(3959423018), // FADDS |
1164 | UINT64_C(3959423019), // FADDS_rec |
1165 | UINT64_C(4227858475), // FADD_rec |
1166 | UINT64_C(0), // FADDrtz |
1167 | UINT64_C(4227860124), // FCFID |
1168 | UINT64_C(3959424668), // FCFIDS |
1169 | UINT64_C(3959424669), // FCFIDS_rec |
1170 | UINT64_C(4227860380), // FCFIDU |
1171 | UINT64_C(3959424924), // FCFIDUS |
1172 | UINT64_C(3959424925), // FCFIDUS_rec |
1173 | UINT64_C(4227860381), // FCFIDU_rec |
1174 | UINT64_C(4227860125), // FCFID_rec |
1175 | UINT64_C(4227858496), // FCMPOD |
1176 | UINT64_C(4227858496), // FCMPOS |
1177 | UINT64_C(4227858432), // FCMPUD |
1178 | UINT64_C(4227858432), // FCMPUS |
1179 | UINT64_C(4227858448), // FCPSGND |
1180 | UINT64_C(4227858449), // FCPSGND_rec |
1181 | UINT64_C(4227858448), // FCPSGNS |
1182 | UINT64_C(4227858449), // FCPSGNS_rec |
1183 | UINT64_C(4227860060), // FCTID |
1184 | UINT64_C(4227860316), // FCTIDU |
1185 | UINT64_C(4227860318), // FCTIDUZ |
1186 | UINT64_C(4227860319), // FCTIDUZ_rec |
1187 | UINT64_C(4227860317), // FCTIDU_rec |
1188 | UINT64_C(4227860062), // FCTIDZ |
1189 | UINT64_C(4227860063), // FCTIDZ_rec |
1190 | UINT64_C(4227860061), // FCTID_rec |
1191 | UINT64_C(4227858460), // FCTIW |
1192 | UINT64_C(4227858716), // FCTIWU |
1193 | UINT64_C(4227858718), // FCTIWUZ |
1194 | UINT64_C(4227858719), // FCTIWUZ_rec |
1195 | UINT64_C(4227858717), // FCTIWU_rec |
1196 | UINT64_C(4227858462), // FCTIWZ |
1197 | UINT64_C(4227858463), // FCTIWZ_rec |
1198 | UINT64_C(4227858461), // FCTIW_rec |
1199 | UINT64_C(4227858468), // FDIV |
1200 | UINT64_C(3959423012), // FDIVS |
1201 | UINT64_C(3959423013), // FDIVS_rec |
1202 | UINT64_C(4227858469), // FDIV_rec |
1203 | UINT64_C(0), // FENCE |
1204 | UINT64_C(4227858490), // FMADD |
1205 | UINT64_C(3959423034), // FMADDS |
1206 | UINT64_C(3959423035), // FMADDS_rec |
1207 | UINT64_C(4227858491), // FMADD_rec |
1208 | UINT64_C(4227858576), // FMR |
1209 | UINT64_C(4227858577), // FMR_rec |
1210 | UINT64_C(4227858488), // FMSUB |
1211 | UINT64_C(3959423032), // FMSUBS |
1212 | UINT64_C(3959423033), // FMSUBS_rec |
1213 | UINT64_C(4227858489), // FMSUB_rec |
1214 | UINT64_C(4227858482), // FMUL |
1215 | UINT64_C(3959423026), // FMULS |
1216 | UINT64_C(3959423027), // FMULS_rec |
1217 | UINT64_C(4227858483), // FMUL_rec |
1218 | UINT64_C(4227858704), // FNABSD |
1219 | UINT64_C(4227858705), // FNABSD_rec |
1220 | UINT64_C(4227858704), // FNABSS |
1221 | UINT64_C(4227858705), // FNABSS_rec |
1222 | UINT64_C(4227858512), // FNEGD |
1223 | UINT64_C(4227858513), // FNEGD_rec |
1224 | UINT64_C(4227858512), // FNEGS |
1225 | UINT64_C(4227858513), // FNEGS_rec |
1226 | UINT64_C(4227858494), // FNMADD |
1227 | UINT64_C(3959423038), // FNMADDS |
1228 | UINT64_C(3959423039), // FNMADDS_rec |
1229 | UINT64_C(4227858495), // FNMADD_rec |
1230 | UINT64_C(4227858492), // FNMSUB |
1231 | UINT64_C(3959423036), // FNMSUBS |
1232 | UINT64_C(3959423037), // FNMSUBS_rec |
1233 | UINT64_C(4227858493), // FNMSUB_rec |
1234 | UINT64_C(4227858480), // FRE |
1235 | UINT64_C(3959423024), // FRES |
1236 | UINT64_C(3959423025), // FRES_rec |
1237 | UINT64_C(4227858481), // FRE_rec |
1238 | UINT64_C(4227859408), // FRIMD |
1239 | UINT64_C(4227859409), // FRIMD_rec |
1240 | UINT64_C(4227859408), // FRIMS |
1241 | UINT64_C(4227859409), // FRIMS_rec |
1242 | UINT64_C(4227859216), // FRIND |
1243 | UINT64_C(4227859217), // FRIND_rec |
1244 | UINT64_C(4227859216), // FRINS |
1245 | UINT64_C(4227859217), // FRINS_rec |
1246 | UINT64_C(4227859344), // FRIPD |
1247 | UINT64_C(4227859345), // FRIPD_rec |
1248 | UINT64_C(4227859344), // FRIPS |
1249 | UINT64_C(4227859345), // FRIPS_rec |
1250 | UINT64_C(4227859280), // FRIZD |
1251 | UINT64_C(4227859281), // FRIZD_rec |
1252 | UINT64_C(4227859280), // FRIZS |
1253 | UINT64_C(4227859281), // FRIZS_rec |
1254 | UINT64_C(4227858456), // FRSP |
1255 | UINT64_C(4227858457), // FRSP_rec |
1256 | UINT64_C(4227858484), // FRSQRTE |
1257 | UINT64_C(3959423028), // FRSQRTES |
1258 | UINT64_C(3959423029), // FRSQRTES_rec |
1259 | UINT64_C(4227858485), // FRSQRTE_rec |
1260 | UINT64_C(4227858478), // FSELD |
1261 | UINT64_C(4227858479), // FSELD_rec |
1262 | UINT64_C(4227858478), // FSELS |
1263 | UINT64_C(4227858479), // FSELS_rec |
1264 | UINT64_C(4227858476), // FSQRT |
1265 | UINT64_C(3959423020), // FSQRTS |
1266 | UINT64_C(3959423021), // FSQRTS_rec |
1267 | UINT64_C(4227858477), // FSQRT_rec |
1268 | UINT64_C(4227858472), // FSUB |
1269 | UINT64_C(3959423016), // FSUBS |
1270 | UINT64_C(3959423017), // FSUBS_rec |
1271 | UINT64_C(4227858473), // FSUB_rec |
1272 | UINT64_C(4227858688), // FTDIV |
1273 | UINT64_C(4227858752), // FTSQRT |
1274 | UINT64_C(0), // GETtlsADDR |
1275 | UINT64_C(0), // GETtlsADDR32 |
1276 | UINT64_C(0), // GETtlsADDR32AIX |
1277 | UINT64_C(0), // GETtlsADDR64AIX |
1278 | UINT64_C(0), // GETtlsADDRPCREL |
1279 | UINT64_C(0), // GETtlsMOD32AIX |
1280 | UINT64_C(0), // GETtlsMOD64AIX |
1281 | UINT64_C(0), // GETtlsTpointer32AIX |
1282 | UINT64_C(0), // GETtlsldADDR |
1283 | UINT64_C(0), // GETtlsldADDR32 |
1284 | UINT64_C(0), // GETtlsldADDRPCREL |
1285 | UINT64_C(2080376292), // HASHCHK |
1286 | UINT64_C(2080376292), // HASHCHK8 |
1287 | UINT64_C(2080376164), // HASHCHKP |
1288 | UINT64_C(2080376164), // HASHCHKP8 |
1289 | UINT64_C(2080376228), // HASHST |
1290 | UINT64_C(2080376228), // HASHST8 |
1291 | UINT64_C(2080376100), // HASHSTP |
1292 | UINT64_C(2080376100), // HASHSTP8 |
1293 | UINT64_C(1275068964), // HRFID |
1294 | UINT64_C(2080376748), // ICBI |
1295 | UINT64_C(2080376766), // ICBIEP |
1296 | UINT64_C(2080375244), // ICBLC |
1297 | UINT64_C(2080375180), // ICBLQ |
1298 | UINT64_C(2080374828), // ICBT |
1299 | UINT64_C(2080375756), // ICBTLS |
1300 | UINT64_C(2080376716), // ICCCI |
1301 | UINT64_C(2080374814), // ISEL |
1302 | UINT64_C(2080374814), // ISEL8 |
1303 | UINT64_C(1275068716), // ISYNC |
1304 | UINT64_C(939524096), // LA |
1305 | UINT64_C(939524096), // LA8 |
1306 | UINT64_C(2080374888), // LBARX |
1307 | UINT64_C(2080374889), // LBARXL |
1308 | UINT64_C(2080374974), // LBEPX |
1309 | UINT64_C(2281701376), // LBZ |
1310 | UINT64_C(2281701376), // LBZ8 |
1311 | UINT64_C(2080376490), // LBZCIX |
1312 | UINT64_C(2348810240), // LBZU |
1313 | UINT64_C(2348810240), // LBZU8 |
1314 | UINT64_C(2080375022), // LBZUX |
1315 | UINT64_C(2080375022), // LBZUX8 |
1316 | UINT64_C(2080374958), // LBZX |
1317 | UINT64_C(2080374958), // LBZX8 |
1318 | UINT64_C(2080374958), // LBZXTLS |
1319 | UINT64_C(2080374958), // LBZXTLS_ |
1320 | UINT64_C(2080374958), // LBZXTLS_32 |
1321 | UINT64_C(3892314112), // LD |
1322 | UINT64_C(2080374952), // LDARX |
1323 | UINT64_C(2080374953), // LDARXL |
1324 | UINT64_C(2080376012), // LDAT |
1325 | UINT64_C(2080375848), // LDBRX |
1326 | UINT64_C(2080376554), // LDCIX |
1327 | UINT64_C(3892314113), // LDU |
1328 | UINT64_C(2080374890), // LDUX |
1329 | UINT64_C(2080374826), // LDX |
1330 | UINT64_C(2080374826), // LDXTLS |
1331 | UINT64_C(2080374826), // LDXTLS_ |
1332 | UINT64_C(0), // LDgotTprelL |
1333 | UINT64_C(0), // LDgotTprelL32 |
1334 | UINT64_C(0), // LDtoc |
1335 | UINT64_C(0), // LDtocBA |
1336 | UINT64_C(0), // LDtocCPT |
1337 | UINT64_C(0), // LDtocJTI |
1338 | UINT64_C(0), // LDtocL |
1339 | UINT64_C(3355443200), // LFD |
1340 | UINT64_C(2080375998), // LFDEPX |
1341 | UINT64_C(3422552064), // LFDU |
1342 | UINT64_C(2080376046), // LFDUX |
1343 | UINT64_C(2080375982), // LFDX |
1344 | UINT64_C(2080375982), // LFDXTLS |
1345 | UINT64_C(2080375982), // LFDXTLS_ |
1346 | UINT64_C(2080376494), // LFIWAX |
1347 | UINT64_C(2080376558), // LFIWZX |
1348 | UINT64_C(3221225472), // LFS |
1349 | UINT64_C(3288334336), // LFSU |
1350 | UINT64_C(2080375918), // LFSUX |
1351 | UINT64_C(2080375854), // LFSX |
1352 | UINT64_C(2080375854), // LFSXTLS |
1353 | UINT64_C(2080375854), // LFSXTLS_ |
1354 | UINT64_C(2818572288), // LHA |
1355 | UINT64_C(2818572288), // LHA8 |
1356 | UINT64_C(2080375016), // LHARX |
1357 | UINT64_C(2080375017), // LHARXL |
1358 | UINT64_C(2885681152), // LHAU |
1359 | UINT64_C(2885681152), // LHAU8 |
1360 | UINT64_C(2080375534), // LHAUX |
1361 | UINT64_C(2080375534), // LHAUX8 |
1362 | UINT64_C(2080375470), // LHAX |
1363 | UINT64_C(2080375470), // LHAX8 |
1364 | UINT64_C(2080375470), // LHAXTLS |
1365 | UINT64_C(2080375470), // LHAXTLS_ |
1366 | UINT64_C(2080375470), // LHAXTLS_32 |
1367 | UINT64_C(2080376364), // LHBRX |
1368 | UINT64_C(2080376364), // LHBRX8 |
1369 | UINT64_C(2080375358), // LHEPX |
1370 | UINT64_C(2684354560), // LHZ |
1371 | UINT64_C(2684354560), // LHZ8 |
1372 | UINT64_C(2080376426), // LHZCIX |
1373 | UINT64_C(2751463424), // LHZU |
1374 | UINT64_C(2751463424), // LHZU8 |
1375 | UINT64_C(2080375406), // LHZUX |
1376 | UINT64_C(2080375406), // LHZUX8 |
1377 | UINT64_C(2080375342), // LHZX |
1378 | UINT64_C(2080375342), // LHZX8 |
1379 | UINT64_C(2080375342), // LHZXTLS |
1380 | UINT64_C(2080375342), // LHZXTLS_ |
1381 | UINT64_C(2080375342), // LHZXTLS_32 |
1382 | UINT64_C(939524096), // LI |
1383 | UINT64_C(939524096), // LI8 |
1384 | UINT64_C(1006632960), // LIS |
1385 | UINT64_C(1006632960), // LIS8 |
1386 | UINT64_C(3087007744), // LMW |
1387 | UINT64_C(3758096384), // LQ |
1388 | UINT64_C(2080375336), // LQARX |
1389 | UINT64_C(2080375337), // LQARXL |
1390 | UINT64_C(0), // LQX_PSEUDO |
1391 | UINT64_C(2080375978), // LSWI |
1392 | UINT64_C(2080374798), // LVEBX |
1393 | UINT64_C(2080374862), // LVEHX |
1394 | UINT64_C(2080374926), // LVEWX |
1395 | UINT64_C(2080374796), // LVSL |
1396 | UINT64_C(2080374860), // LVSR |
1397 | UINT64_C(2080374990), // LVX |
1398 | UINT64_C(2080375502), // LVXL |
1399 | UINT64_C(3892314114), // LWA |
1400 | UINT64_C(2080374824), // LWARX |
1401 | UINT64_C(2080374825), // LWARXL |
1402 | UINT64_C(2080375948), // LWAT |
1403 | UINT64_C(2080375530), // LWAUX |
1404 | UINT64_C(2080375466), // LWAX |
1405 | UINT64_C(2080375466), // LWAXTLS |
1406 | UINT64_C(2080375466), // LWAXTLS_ |
1407 | UINT64_C(2080375466), // LWAXTLS_32 |
1408 | UINT64_C(2080375466), // LWAX_32 |
1409 | UINT64_C(3892314114), // LWA_32 |
1410 | UINT64_C(2080375852), // LWBRX |
1411 | UINT64_C(2080375852), // LWBRX8 |
1412 | UINT64_C(2080374846), // LWEPX |
1413 | UINT64_C(2147483648), // LWZ |
1414 | UINT64_C(2147483648), // LWZ8 |
1415 | UINT64_C(2080376362), // LWZCIX |
1416 | UINT64_C(2214592512), // LWZU |
1417 | UINT64_C(2214592512), // LWZU8 |
1418 | UINT64_C(2080374894), // LWZUX |
1419 | UINT64_C(2080374894), // LWZUX8 |
1420 | UINT64_C(2080374830), // LWZX |
1421 | UINT64_C(2080374830), // LWZX8 |
1422 | UINT64_C(2080374830), // LWZXTLS |
1423 | UINT64_C(2080374830), // LWZXTLS_ |
1424 | UINT64_C(2080374830), // LWZXTLS_32 |
1425 | UINT64_C(0), // LWZtoc |
1426 | UINT64_C(0), // LWZtocL |
1427 | UINT64_C(3825205250), // LXSD |
1428 | UINT64_C(2080375960), // LXSDX |
1429 | UINT64_C(2080376346), // LXSIBZX |
1430 | UINT64_C(2080376410), // LXSIHZX |
1431 | UINT64_C(2080374936), // LXSIWAX |
1432 | UINT64_C(2080374808), // LXSIWZX |
1433 | UINT64_C(3825205251), // LXSSP |
1434 | UINT64_C(2080375832), // LXSSPX |
1435 | UINT64_C(4093640705), // LXV |
1436 | UINT64_C(2080376536), // LXVB16X |
1437 | UINT64_C(2080376472), // LXVD2X |
1438 | UINT64_C(2080375448), // LXVDSX |
1439 | UINT64_C(2080376408), // LXVH8X |
1440 | UINT64_C(4028564176), // LXVKQ |
1441 | UINT64_C(2080375322), // LXVL |
1442 | UINT64_C(2080375386), // LXVLL |
1443 | UINT64_C(402653184), // LXVP |
1444 | UINT64_C(2080375962), // LXVPRL |
1445 | UINT64_C(2080376026), // LXVPRLL |
1446 | UINT64_C(2080375450), // LXVPX |
1447 | UINT64_C(2080374810), // LXVRBX |
1448 | UINT64_C(2080375002), // LXVRDX |
1449 | UINT64_C(2080374874), // LXVRHX |
1450 | UINT64_C(2080375834), // LXVRL |
1451 | UINT64_C(2080375898), // LXVRLL |
1452 | UINT64_C(2080374938), // LXVRWX |
1453 | UINT64_C(2080376344), // LXVW4X |
1454 | UINT64_C(2080375512), // LXVWSX |
1455 | UINT64_C(2080375320), // LXVX |
1456 | UINT64_C(268435504), // MADDHD |
1457 | UINT64_C(268435505), // MADDHDU |
1458 | UINT64_C(268435507), // MADDLD |
1459 | UINT64_C(268435507), // MADDLD8 |
1460 | UINT64_C(2080376492), // MBAR |
1461 | UINT64_C(1275068416), // MCRF |
1462 | UINT64_C(4227858560), // MCRFS |
1463 | UINT64_C(2080375936), // MCRXRX |
1464 | UINT64_C(2080375388), // MFBHRBE |
1465 | UINT64_C(2080374822), // MFCR |
1466 | UINT64_C(2080374822), // MFCR8 |
1467 | UINT64_C(2080965286), // MFCTR |
1468 | UINT64_C(2080965286), // MFCTR8 |
1469 | UINT64_C(2080375430), // MFDCR |
1470 | UINT64_C(4227859598), // MFFS |
1471 | UINT64_C(4229170318), // MFFSCDRN |
1472 | UINT64_C(4229235854), // MFFSCDRNI |
1473 | UINT64_C(4227925134), // MFFSCE |
1474 | UINT64_C(4229301390), // MFFSCRN |
1475 | UINT64_C(4229366926), // MFFSCRNI |
1476 | UINT64_C(4229432462), // MFFSL |
1477 | UINT64_C(4227859599), // MFFS_rec |
1478 | UINT64_C(2080899750), // MFLR |
1479 | UINT64_C(2080899750), // MFLR8 |
1480 | UINT64_C(2080374950), // MFMSR |
1481 | UINT64_C(2081423398), // MFOCRF |
1482 | UINT64_C(2081423398), // MFOCRF8 |
1483 | UINT64_C(2080375452), // MFPMR |
1484 | UINT64_C(2080375462), // MFSPR |
1485 | UINT64_C(2080375462), // MFSPR8 |
1486 | UINT64_C(2080375974), // MFSR |
1487 | UINT64_C(2080376102), // MFSRIN |
1488 | UINT64_C(2080375526), // MFTB |
1489 | UINT64_C(2081178278), // MFTB8 |
1490 | UINT64_C(2080572070), // MFUDSCR |
1491 | UINT64_C(2080374886), // MFVRD |
1492 | UINT64_C(2080391846), // MFVRSAVE |
1493 | UINT64_C(2080391846), // MFVRSAVEv |
1494 | UINT64_C(2080375014), // MFVRWZ |
1495 | UINT64_C(268436996), // MFVSCR |
1496 | UINT64_C(2080374886), // MFVSRD |
1497 | UINT64_C(2080375398), // MFVSRLD |
1498 | UINT64_C(2080375014), // MFVSRWZ |
1499 | UINT64_C(2080376338), // MODSD |
1500 | UINT64_C(2080376342), // MODSW |
1501 | UINT64_C(2080375314), // MODUD |
1502 | UINT64_C(2080375318), // MODUW |
1503 | UINT64_C(2080376556), // MSGSYNC |
1504 | UINT64_C(2080375980), // MSYNC |
1505 | UINT64_C(2080375072), // MTCRF |
1506 | UINT64_C(2080375072), // MTCRF8 |
1507 | UINT64_C(2080965542), // MTCTR |
1508 | UINT64_C(2080965542), // MTCTR8 |
1509 | UINT64_C(2080965542), // MTCTR8loop |
1510 | UINT64_C(2080965542), // MTCTRloop |
1511 | UINT64_C(2080375686), // MTDCR |
1512 | UINT64_C(4227858572), // MTFSB0 |
1513 | UINT64_C(4227858508), // MTFSB1 |
1514 | UINT64_C(4227859854), // MTFSF |
1515 | UINT64_C(4227858700), // MTFSFI |
1516 | UINT64_C(4227858701), // MTFSFI_rec |
1517 | UINT64_C(4227858700), // MTFSFIb |
1518 | UINT64_C(4227859855), // MTFSF_rec |
1519 | UINT64_C(4227859854), // MTFSFb |
1520 | UINT64_C(2080900006), // MTLR |
1521 | UINT64_C(2080900006), // MTLR8 |
1522 | UINT64_C(2080375076), // MTMSR |
1523 | UINT64_C(2080375140), // MTMSRD |
1524 | UINT64_C(2081423648), // MTOCRF |
1525 | UINT64_C(2081423648), // MTOCRF8 |
1526 | UINT64_C(2080375708), // MTPMR |
1527 | UINT64_C(2080375718), // MTSPR |
1528 | UINT64_C(2080375718), // MTSPR8 |
1529 | UINT64_C(2080375204), // MTSR |
1530 | UINT64_C(2080375268), // MTSRIN |
1531 | UINT64_C(2080572326), // MTUDSCR |
1532 | UINT64_C(2080375142), // MTVRD |
1533 | UINT64_C(2080392102), // MTVRSAVE |
1534 | UINT64_C(2080392102), // MTVRSAVEv |
1535 | UINT64_C(2080375206), // MTVRWA |
1536 | UINT64_C(2080375270), // MTVRWZ |
1537 | UINT64_C(268437060), // MTVSCR |
1538 | UINT64_C(269485634), // MTVSRBM |
1539 | UINT64_C(268435476), // MTVSRBMI |
1540 | UINT64_C(2080375142), // MTVSRD |
1541 | UINT64_C(2080375654), // MTVSRDD |
1542 | UINT64_C(269682242), // MTVSRDM |
1543 | UINT64_C(269551170), // MTVSRHM |
1544 | UINT64_C(269747778), // MTVSRQM |
1545 | UINT64_C(2080375206), // MTVSRWA |
1546 | UINT64_C(269616706), // MTVSRWM |
1547 | UINT64_C(2080375590), // MTVSRWS |
1548 | UINT64_C(2080375270), // MTVSRWZ |
1549 | UINT64_C(2080374930), // MULHD |
1550 | UINT64_C(2080374802), // MULHDU |
1551 | UINT64_C(2080374803), // MULHDU_rec |
1552 | UINT64_C(2080374931), // MULHD_rec |
1553 | UINT64_C(2080374934), // MULHW |
1554 | UINT64_C(2080374806), // MULHWU |
1555 | UINT64_C(2080374807), // MULHWU_rec |
1556 | UINT64_C(2080374935), // MULHW_rec |
1557 | UINT64_C(2080375250), // MULLD |
1558 | UINT64_C(2080376274), // MULLDO |
1559 | UINT64_C(2080376275), // MULLDO_rec |
1560 | UINT64_C(2080375251), // MULLD_rec |
1561 | UINT64_C(469762048), // MULLI |
1562 | UINT64_C(469762048), // MULLI8 |
1563 | UINT64_C(2080375254), // MULLW |
1564 | UINT64_C(2080376278), // MULLWO |
1565 | UINT64_C(2080376279), // MULLWO_rec |
1566 | UINT64_C(2080375255), // MULLW_rec |
1567 | UINT64_C(0), // MoveGOTtoLR |
1568 | UINT64_C(0), // MovePCtoLR |
1569 | UINT64_C(0), // MovePCtoLR8 |
1570 | UINT64_C(2080375736), // NAND |
1571 | UINT64_C(2080375736), // NAND8 |
1572 | UINT64_C(2080375737), // NAND8_rec |
1573 | UINT64_C(2080375737), // NAND_rec |
1574 | UINT64_C(1275069284), // NAP |
1575 | UINT64_C(2080374992), // NEG |
1576 | UINT64_C(2080374992), // NEG8 |
1577 | UINT64_C(2080376016), // NEG8O |
1578 | UINT64_C(2080376017), // NEG8O_rec |
1579 | UINT64_C(2080374993), // NEG8_rec |
1580 | UINT64_C(2080376016), // NEGO |
1581 | UINT64_C(2080376017), // NEGO_rec |
1582 | UINT64_C(2080374993), // NEG_rec |
1583 | UINT64_C(1610612736), // NOP |
1584 | UINT64_C(1612775424), // NOP_GT_PWR6 |
1585 | UINT64_C(1614938112), // NOP_GT_PWR7 |
1586 | UINT64_C(2080375032), // NOR |
1587 | UINT64_C(2080375032), // NOR8 |
1588 | UINT64_C(2080375033), // NOR8_rec |
1589 | UINT64_C(2080375033), // NOR_rec |
1590 | UINT64_C(2080375672), // OR |
1591 | UINT64_C(2080375672), // OR8 |
1592 | UINT64_C(2080375673), // OR8_rec |
1593 | UINT64_C(2080375608), // ORC |
1594 | UINT64_C(2080375608), // ORC8 |
1595 | UINT64_C(2080375609), // ORC8_rec |
1596 | UINT64_C(2080375609), // ORC_rec |
1597 | UINT64_C(1610612736), // ORI |
1598 | UINT64_C(1610612736), // ORI8 |
1599 | UINT64_C(1677721600), // ORIS |
1600 | UINT64_C(1677721600), // ORIS8 |
1601 | UINT64_C(2080375673), // OR_rec |
1602 | UINT64_C(432345565167091712), // PADDI |
1603 | UINT64_C(432345565167091712), // PADDI8 |
1604 | UINT64_C(436849164794462208), // PADDI8pc |
1605 | UINT64_C(0), // PADDIdtprel |
1606 | UINT64_C(436849164794462208), // PADDIpc |
1607 | UINT64_C(2080375096), // PDEPD |
1608 | UINT64_C(2080375160), // PEXTD |
1609 | UINT64_C(432345565167091712), // PLA |
1610 | UINT64_C(432345565167091712), // PLA8 |
1611 | UINT64_C(432345565167091712), // PLA8pc |
1612 | UINT64_C(432345565167091712), // PLApc |
1613 | UINT64_C(432345566509268992), // PLBZ |
1614 | UINT64_C(432345566509268992), // PLBZ8 |
1615 | UINT64_C(432345566509268992), // PLBZ8nopc |
1616 | UINT64_C(436849166136639488), // PLBZ8onlypc |
1617 | UINT64_C(436849166136639488), // PLBZ8pc |
1618 | UINT64_C(432345566509268992), // PLBZnopc |
1619 | UINT64_C(436849166136639488), // PLBZonlypc |
1620 | UINT64_C(436849166136639488), // PLBZpc |
1621 | UINT64_C(288230379976916992), // PLD |
1622 | UINT64_C(288230379976916992), // PLDnopc |
1623 | UINT64_C(292733979604287488), // PLDonlypc |
1624 | UINT64_C(292733979604287488), // PLDpc |
1625 | UINT64_C(432345567583010816), // PLFD |
1626 | UINT64_C(432345567583010816), // PLFDnopc |
1627 | UINT64_C(436849167210381312), // PLFDonlypc |
1628 | UINT64_C(436849167210381312), // PLFDpc |
1629 | UINT64_C(432345567448793088), // PLFS |
1630 | UINT64_C(432345567448793088), // PLFSnopc |
1631 | UINT64_C(436849167076163584), // PLFSonlypc |
1632 | UINT64_C(436849167076163584), // PLFSpc |
1633 | UINT64_C(432345567046139904), // PLHA |
1634 | UINT64_C(432345567046139904), // PLHA8 |
1635 | UINT64_C(432345567046139904), // PLHA8nopc |
1636 | UINT64_C(436849166673510400), // PLHA8onlypc |
1637 | UINT64_C(436849166673510400), // PLHA8pc |
1638 | UINT64_C(432345567046139904), // PLHAnopc |
1639 | UINT64_C(436849166673510400), // PLHAonlypc |
1640 | UINT64_C(436849166673510400), // PLHApc |
1641 | UINT64_C(432345566911922176), // PLHZ |
1642 | UINT64_C(432345566911922176), // PLHZ8 |
1643 | UINT64_C(432345566911922176), // PLHZ8nopc |
1644 | UINT64_C(436849166539292672), // PLHZ8onlypc |
1645 | UINT64_C(436849166539292672), // PLHZ8pc |
1646 | UINT64_C(432345566911922176), // PLHZnopc |
1647 | UINT64_C(436849166539292672), // PLHZonlypc |
1648 | UINT64_C(436849166539292672), // PLHZpc |
1649 | UINT64_C(432345565167091712), // PLI |
1650 | UINT64_C(432345565167091712), // PLI8 |
1651 | UINT64_C(288230378903175168), // PLWA |
1652 | UINT64_C(288230378903175168), // PLWA8 |
1653 | UINT64_C(288230378903175168), // PLWA8nopc |
1654 | UINT64_C(292733978530545664), // PLWA8onlypc |
1655 | UINT64_C(292733978530545664), // PLWA8pc |
1656 | UINT64_C(288230378903175168), // PLWAnopc |
1657 | UINT64_C(292733978530545664), // PLWAonlypc |
1658 | UINT64_C(292733978530545664), // PLWApc |
1659 | UINT64_C(432345566375051264), // PLWZ |
1660 | UINT64_C(432345566375051264), // PLWZ8 |
1661 | UINT64_C(432345566375051264), // PLWZ8nopc |
1662 | UINT64_C(436849166002421760), // PLWZ8onlypc |
1663 | UINT64_C(436849166002421760), // PLWZ8pc |
1664 | UINT64_C(432345566375051264), // PLWZnopc |
1665 | UINT64_C(436849166002421760), // PLWZonlypc |
1666 | UINT64_C(436849166002421760), // PLWZpc |
1667 | UINT64_C(288230378970284032), // PLXSD |
1668 | UINT64_C(288230378970284032), // PLXSDnopc |
1669 | UINT64_C(292733978597654528), // PLXSDonlypc |
1670 | UINT64_C(292733978597654528), // PLXSDpc |
1671 | UINT64_C(288230379037392896), // PLXSSP |
1672 | UINT64_C(288230379037392896), // PLXSSPnopc |
1673 | UINT64_C(292733978664763392), // PLXSSPonlypc |
1674 | UINT64_C(292733978664763392), // PLXSSPpc |
1675 | UINT64_C(288230379507154944), // PLXV |
1676 | UINT64_C(288230380044025856), // PLXVP |
1677 | UINT64_C(288230380044025856), // PLXVPnopc |
1678 | UINT64_C(292733979671396352), // PLXVPonlypc |
1679 | UINT64_C(292733979671396352), // PLXVPpc |
1680 | UINT64_C(288230379507154944), // PLXVnopc |
1681 | UINT64_C(292733979134525440), // PLXVonlypc |
1682 | UINT64_C(292733979134525440), // PLXVpc |
1683 | UINT64_C(544935558871253400), // PMXVBF16GER2 |
1684 | UINT64_C(544935558871254928), // PMXVBF16GER2NN |
1685 | UINT64_C(544935558871253904), // PMXVBF16GER2NP |
1686 | UINT64_C(544935558871254416), // PMXVBF16GER2PN |
1687 | UINT64_C(544935558871253392), // PMXVBF16GER2PP |
1688 | UINT64_C(544935558871253400), // PMXVBF16GER2W |
1689 | UINT64_C(544935558871254928), // PMXVBF16GER2WNN |
1690 | UINT64_C(544935558871253904), // PMXVBF16GER2WNP |
1691 | UINT64_C(544935558871254416), // PMXVBF16GER2WPN |
1692 | UINT64_C(544935558871253392), // PMXVBF16GER2WPP |
1693 | UINT64_C(544935558871253144), // PMXVF16GER2 |
1694 | UINT64_C(544935558871254672), // PMXVF16GER2NN |
1695 | UINT64_C(544935558871253648), // PMXVF16GER2NP |
1696 | UINT64_C(544935558871254160), // PMXVF16GER2PN |
1697 | UINT64_C(544935558871253136), // PMXVF16GER2PP |
1698 | UINT64_C(544935558871253144), // PMXVF16GER2W |
1699 | UINT64_C(544935558871254672), // PMXVF16GER2WNN |
1700 | UINT64_C(544935558871253648), // PMXVF16GER2WNP |
1701 | UINT64_C(544935558871254160), // PMXVF16GER2WPN |
1702 | UINT64_C(544935558871253136), // PMXVF16GER2WPP |
1703 | UINT64_C(544935558871253208), // PMXVF32GER |
1704 | UINT64_C(544935558871254736), // PMXVF32GERNN |
1705 | UINT64_C(544935558871253712), // PMXVF32GERNP |
1706 | UINT64_C(544935558871254224), // PMXVF32GERPN |
1707 | UINT64_C(544935558871253200), // PMXVF32GERPP |
1708 | UINT64_C(544935558871253208), // PMXVF32GERW |
1709 | UINT64_C(544935558871254736), // PMXVF32GERWNN |
1710 | UINT64_C(544935558871253712), // PMXVF32GERWNP |
1711 | UINT64_C(544935558871254224), // PMXVF32GERWPN |
1712 | UINT64_C(544935558871253200), // PMXVF32GERWPP |
1713 | UINT64_C(544935558871253464), // PMXVF64GER |
1714 | UINT64_C(544935558871254992), // PMXVF64GERNN |
1715 | UINT64_C(544935558871253968), // PMXVF64GERNP |
1716 | UINT64_C(544935558871254480), // PMXVF64GERPN |
1717 | UINT64_C(544935558871253456), // PMXVF64GERPP |
1718 | UINT64_C(544935558871253464), // PMXVF64GERW |
1719 | UINT64_C(544935558871254992), // PMXVF64GERWNN |
1720 | UINT64_C(544935558871253968), // PMXVF64GERWNP |
1721 | UINT64_C(544935558871254480), // PMXVF64GERWPN |
1722 | UINT64_C(544935558871253456), // PMXVF64GERWPP |
1723 | UINT64_C(544935558871253592), // PMXVI16GER2 |
1724 | UINT64_C(544935558871253848), // PMXVI16GER2PP |
1725 | UINT64_C(544935558871253336), // PMXVI16GER2S |
1726 | UINT64_C(544935558871253328), // PMXVI16GER2SPP |
1727 | UINT64_C(544935558871253336), // PMXVI16GER2SW |
1728 | UINT64_C(544935558871253328), // PMXVI16GER2SWPP |
1729 | UINT64_C(544935558871253592), // PMXVI16GER2W |
1730 | UINT64_C(544935558871253848), // PMXVI16GER2WPP |
1731 | UINT64_C(544935558871253272), // PMXVI4GER8 |
1732 | UINT64_C(544935558871253264), // PMXVI4GER8PP |
1733 | UINT64_C(544935558871253272), // PMXVI4GER8W |
1734 | UINT64_C(544935558871253264), // PMXVI4GER8WPP |
1735 | UINT64_C(544935558871253016), // PMXVI8GER4 |
1736 | UINT64_C(544935558871253008), // PMXVI8GER4PP |
1737 | UINT64_C(544935558871253784), // PMXVI8GER4SPP |
1738 | UINT64_C(544935558871253016), // PMXVI8GER4W |
1739 | UINT64_C(544935558871253008), // PMXVI8GER4WPP |
1740 | UINT64_C(544935558871253784), // PMXVI8GER4WSPP |
1741 | UINT64_C(2080375028), // POPCNTB |
1742 | UINT64_C(2080375028), // POPCNTB8 |
1743 | UINT64_C(2080375796), // POPCNTD |
1744 | UINT64_C(2080375540), // POPCNTW |
1745 | UINT64_C(0), // PPC32GOT |
1746 | UINT64_C(0), // PPC32PICGOT |
1747 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_32 |
1748 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_64 |
1749 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 |
1750 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 |
1751 | UINT64_C(0), // PROBED_ALLOCA_32 |
1752 | UINT64_C(0), // PROBED_ALLOCA_64 |
1753 | UINT64_C(0), // PROBED_STACKALLOC_32 |
1754 | UINT64_C(0), // PROBED_STACKALLOC_64 |
1755 | UINT64_C(432345566777704448), // PSTB |
1756 | UINT64_C(432345566777704448), // PSTB8 |
1757 | UINT64_C(432345566777704448), // PSTB8nopc |
1758 | UINT64_C(436849166405074944), // PSTB8onlypc |
1759 | UINT64_C(436849166405074944), // PSTB8pc |
1760 | UINT64_C(432345566777704448), // PSTBnopc |
1761 | UINT64_C(436849166405074944), // PSTBonlypc |
1762 | UINT64_C(436849166405074944), // PSTBpc |
1763 | UINT64_C(288230380245352448), // PSTD |
1764 | UINT64_C(288230380245352448), // PSTDnopc |
1765 | UINT64_C(292733979872722944), // PSTDonlypc |
1766 | UINT64_C(292733979872722944), // PSTDpc |
1767 | UINT64_C(432345567851446272), // PSTFD |
1768 | UINT64_C(432345567851446272), // PSTFDnopc |
1769 | UINT64_C(436849167478816768), // PSTFDonlypc |
1770 | UINT64_C(436849167478816768), // PSTFDpc |
1771 | UINT64_C(432345567717228544), // PSTFS |
1772 | UINT64_C(432345567717228544), // PSTFSnopc |
1773 | UINT64_C(436849167344599040), // PSTFSonlypc |
1774 | UINT64_C(436849167344599040), // PSTFSpc |
1775 | UINT64_C(432345567180357632), // PSTH |
1776 | UINT64_C(432345567180357632), // PSTH8 |
1777 | UINT64_C(432345567180357632), // PSTH8nopc |
1778 | UINT64_C(436849166807728128), // PSTH8onlypc |
1779 | UINT64_C(436849166807728128), // PSTH8pc |
1780 | UINT64_C(432345567180357632), // PSTHnopc |
1781 | UINT64_C(436849166807728128), // PSTHonlypc |
1782 | UINT64_C(436849166807728128), // PSTHpc |
1783 | UINT64_C(432345566643486720), // PSTW |
1784 | UINT64_C(432345566643486720), // PSTW8 |
1785 | UINT64_C(432345566643486720), // PSTW8nopc |
1786 | UINT64_C(436849166270857216), // PSTW8onlypc |
1787 | UINT64_C(436849166270857216), // PSTW8pc |
1788 | UINT64_C(432345566643486720), // PSTWnopc |
1789 | UINT64_C(436849166270857216), // PSTWonlypc |
1790 | UINT64_C(436849166270857216), // PSTWpc |
1791 | UINT64_C(288230379238719488), // PSTXSD |
1792 | UINT64_C(288230379238719488), // PSTXSDnopc |
1793 | UINT64_C(292733978866089984), // PSTXSDonlypc |
1794 | UINT64_C(292733978866089984), // PSTXSDpc |
1795 | UINT64_C(288230379305828352), // PSTXSSP |
1796 | UINT64_C(288230379305828352), // PSTXSSPnopc |
1797 | UINT64_C(292733978933198848), // PSTXSSPonlypc |
1798 | UINT64_C(292733978933198848), // PSTXSSPpc |
1799 | UINT64_C(288230379775590400), // PSTXV |
1800 | UINT64_C(288230380312461312), // PSTXVP |
1801 | UINT64_C(288230380312461312), // PSTXVPnopc |
1802 | UINT64_C(292733979939831808), // PSTXVPonlypc |
1803 | UINT64_C(292733979939831808), // PSTXVPpc |
1804 | UINT64_C(288230379775590400), // PSTXVnopc |
1805 | UINT64_C(292733979402960896), // PSTXVonlypc |
1806 | UINT64_C(292733979402960896), // PSTXVpc |
1807 | UINT64_C(0), // PseudoEIEIO |
1808 | UINT64_C(0), // RESTORE_ACC |
1809 | UINT64_C(0), // RESTORE_CR |
1810 | UINT64_C(0), // RESTORE_CRBIT |
1811 | UINT64_C(0), // RESTORE_QUADWORD |
1812 | UINT64_C(0), // RESTORE_UACC |
1813 | UINT64_C(0), // RESTORE_WACC |
1814 | UINT64_C(1275068518), // RFCI |
1815 | UINT64_C(1275068494), // RFDI |
1816 | UINT64_C(1275068708), // RFEBB |
1817 | UINT64_C(1275068516), // RFI |
1818 | UINT64_C(1275068452), // RFID |
1819 | UINT64_C(1275068492), // RFMCI |
1820 | UINT64_C(2013265936), // RLDCL |
1821 | UINT64_C(2013265937), // RLDCL_rec |
1822 | UINT64_C(2013265938), // RLDCR |
1823 | UINT64_C(2013265939), // RLDCR_rec |
1824 | UINT64_C(2013265928), // RLDIC |
1825 | UINT64_C(2013265920), // RLDICL |
1826 | UINT64_C(2013265920), // RLDICL_32 |
1827 | UINT64_C(2013265920), // RLDICL_32_64 |
1828 | UINT64_C(2013265921), // RLDICL_32_rec |
1829 | UINT64_C(2013265921), // RLDICL_rec |
1830 | UINT64_C(2013265924), // RLDICR |
1831 | UINT64_C(2013265924), // RLDICR_32 |
1832 | UINT64_C(2013265925), // RLDICR_rec |
1833 | UINT64_C(2013265929), // RLDIC_rec |
1834 | UINT64_C(2013265932), // RLDIMI |
1835 | UINT64_C(2013265933), // RLDIMI_rec |
1836 | UINT64_C(1342177280), // RLWIMI |
1837 | UINT64_C(1342177280), // RLWIMI8 |
1838 | UINT64_C(1342177281), // RLWIMI8_rec |
1839 | UINT64_C(1342177281), // RLWIMI_rec |
1840 | UINT64_C(1409286144), // RLWINM |
1841 | UINT64_C(1409286144), // RLWINM8 |
1842 | UINT64_C(1409286145), // RLWINM8_rec |
1843 | UINT64_C(1409286145), // RLWINM_rec |
1844 | UINT64_C(1543503872), // RLWNM |
1845 | UINT64_C(1543503872), // RLWNM8 |
1846 | UINT64_C(1543503873), // RLWNM8_rec |
1847 | UINT64_C(1543503873), // RLWNM_rec |
1848 | UINT64_C(0), // ReadTB |
1849 | UINT64_C(1140850690), // SC |
1850 | UINT64_C(1140850689), // SCV |
1851 | UINT64_C(0), // SELECT_CC_F16 |
1852 | UINT64_C(0), // SELECT_CC_F4 |
1853 | UINT64_C(0), // SELECT_CC_F8 |
1854 | UINT64_C(0), // SELECT_CC_I4 |
1855 | UINT64_C(0), // SELECT_CC_I8 |
1856 | UINT64_C(0), // SELECT_CC_SPE |
1857 | UINT64_C(0), // SELECT_CC_SPE4 |
1858 | UINT64_C(0), // SELECT_CC_VRRC |
1859 | UINT64_C(0), // SELECT_CC_VSFRC |
1860 | UINT64_C(0), // SELECT_CC_VSRC |
1861 | UINT64_C(0), // SELECT_CC_VSSRC |
1862 | UINT64_C(0), // SELECT_F16 |
1863 | UINT64_C(0), // SELECT_F4 |
1864 | UINT64_C(0), // SELECT_F8 |
1865 | UINT64_C(0), // SELECT_I4 |
1866 | UINT64_C(0), // SELECT_I8 |
1867 | UINT64_C(0), // SELECT_SPE |
1868 | UINT64_C(0), // SELECT_SPE4 |
1869 | UINT64_C(0), // SELECT_VRRC |
1870 | UINT64_C(0), // SELECT_VSFRC |
1871 | UINT64_C(0), // SELECT_VSRC |
1872 | UINT64_C(0), // SELECT_VSSRC |
1873 | UINT64_C(2080375040), // SETB |
1874 | UINT64_C(2080375040), // SETB8 |
1875 | UINT64_C(2080375552), // SETBC |
1876 | UINT64_C(2080375552), // SETBC8 |
1877 | UINT64_C(2080375616), // SETBCR |
1878 | UINT64_C(2080375616), // SETBCR8 |
1879 | UINT64_C(0), // SETFLM |
1880 | UINT64_C(2080375680), // SETNBC |
1881 | UINT64_C(2080375680), // SETNBC8 |
1882 | UINT64_C(2080375744), // SETNBCR |
1883 | UINT64_C(2080375744), // SETNBCR8 |
1884 | UINT64_C(0), // SETRND |
1885 | UINT64_C(0), // SETRNDi |
1886 | UINT64_C(2080376743), // SLBFEE_rec |
1887 | UINT64_C(2080375780), // SLBIA |
1888 | UINT64_C(2080375652), // SLBIE |
1889 | UINT64_C(2080375716), // SLBIEG |
1890 | UINT64_C(2080376614), // SLBMFEE |
1891 | UINT64_C(2080376486), // SLBMFEV |
1892 | UINT64_C(2080375588), // SLBMTE |
1893 | UINT64_C(2080375460), // SLBSYNC |
1894 | UINT64_C(2080374838), // SLD |
1895 | UINT64_C(2080374839), // SLD_rec |
1896 | UINT64_C(2080374832), // SLW |
1897 | UINT64_C(2080374832), // SLW8 |
1898 | UINT64_C(2080374833), // SLW8_rec |
1899 | UINT64_C(2080374833), // SLW_rec |
1900 | UINT64_C(2147483648), // SPELWZ |
1901 | UINT64_C(2080374830), // SPELWZX |
1902 | UINT64_C(2415919104), // SPESTW |
1903 | UINT64_C(2080375086), // SPESTWX |
1904 | UINT64_C(0), // SPILL_ACC |
1905 | UINT64_C(0), // SPILL_CR |
1906 | UINT64_C(0), // SPILL_CRBIT |
1907 | UINT64_C(0), // SPILL_QUADWORD |
1908 | UINT64_C(0), // SPILL_UACC |
1909 | UINT64_C(0), // SPILL_WACC |
1910 | UINT64_C(0), // SPLIT_QUADWORD |
1911 | UINT64_C(2080376372), // SRAD |
1912 | UINT64_C(2080376436), // SRADI |
1913 | UINT64_C(2080376436), // SRADI_32 |
1914 | UINT64_C(2080376437), // SRADI_rec |
1915 | UINT64_C(2080376373), // SRAD_rec |
1916 | UINT64_C(2080376368), // SRAW |
1917 | UINT64_C(2080376432), // SRAWI |
1918 | UINT64_C(2080376433), // SRAWI_rec |
1919 | UINT64_C(2080376369), // SRAW_rec |
1920 | UINT64_C(2080375862), // SRD |
1921 | UINT64_C(2080375863), // SRD_rec |
1922 | UINT64_C(2080375856), // SRW |
1923 | UINT64_C(2080375856), // SRW8 |
1924 | UINT64_C(2080375857), // SRW8_rec |
1925 | UINT64_C(2080375857), // SRW_rec |
1926 | UINT64_C(2550136832), // STB |
1927 | UINT64_C(2550136832), // STB8 |
1928 | UINT64_C(2080376746), // STBCIX |
1929 | UINT64_C(2080376173), // STBCX |
1930 | UINT64_C(2080375230), // STBEPX |
1931 | UINT64_C(2617245696), // STBU |
1932 | UINT64_C(2617245696), // STBU8 |
1933 | UINT64_C(2080375278), // STBUX |
1934 | UINT64_C(2080375278), // STBUX8 |
1935 | UINT64_C(2080375214), // STBX |
1936 | UINT64_C(2080375214), // STBX8 |
1937 | UINT64_C(2080375214), // STBXTLS |
1938 | UINT64_C(2080375214), // STBXTLS_ |
1939 | UINT64_C(2080375214), // STBXTLS_32 |
1940 | UINT64_C(4160749568), // STD |
1941 | UINT64_C(2080376268), // STDAT |
1942 | UINT64_C(2080376104), // STDBRX |
1943 | UINT64_C(2080376810), // STDCIX |
1944 | UINT64_C(2080375213), // STDCX |
1945 | UINT64_C(4160749569), // STDU |
1946 | UINT64_C(2080375146), // STDUX |
1947 | UINT64_C(2080375082), // STDX |
1948 | UINT64_C(2080375082), // STDXTLS |
1949 | UINT64_C(2080375082), // STDXTLS_ |
1950 | UINT64_C(3623878656), // STFD |
1951 | UINT64_C(2080376254), // STFDEPX |
1952 | UINT64_C(3690987520), // STFDU |
1953 | UINT64_C(2080376302), // STFDUX |
1954 | UINT64_C(2080376238), // STFDX |
1955 | UINT64_C(2080376238), // STFDXTLS |
1956 | UINT64_C(2080376238), // STFDXTLS_ |
1957 | UINT64_C(2080376750), // STFIWX |
1958 | UINT64_C(3489660928), // STFS |
1959 | UINT64_C(3556769792), // STFSU |
1960 | UINT64_C(2080376174), // STFSUX |
1961 | UINT64_C(2080376110), // STFSX |
1962 | UINT64_C(2080376110), // STFSXTLS |
1963 | UINT64_C(2080376110), // STFSXTLS_ |
1964 | UINT64_C(2952790016), // STH |
1965 | UINT64_C(2952790016), // STH8 |
1966 | UINT64_C(2080376620), // STHBRX |
1967 | UINT64_C(2080376682), // STHCIX |
1968 | UINT64_C(2080376237), // STHCX |
1969 | UINT64_C(2080375614), // STHEPX |
1970 | UINT64_C(3019898880), // STHU |
1971 | UINT64_C(3019898880), // STHU8 |
1972 | UINT64_C(2080375662), // STHUX |
1973 | UINT64_C(2080375662), // STHUX8 |
1974 | UINT64_C(2080375598), // STHX |
1975 | UINT64_C(2080375598), // STHX8 |
1976 | UINT64_C(2080375598), // STHXTLS |
1977 | UINT64_C(2080375598), // STHXTLS_ |
1978 | UINT64_C(2080375598), // STHXTLS_32 |
1979 | UINT64_C(3154116608), // STMW |
1980 | UINT64_C(1275069156), // STOP |
1981 | UINT64_C(4160749570), // STQ |
1982 | UINT64_C(2080375149), // STQCX |
1983 | UINT64_C(0), // STQX_PSEUDO |
1984 | UINT64_C(2080376234), // STSWI |
1985 | UINT64_C(2080375054), // STVEBX |
1986 | UINT64_C(2080375118), // STVEHX |
1987 | UINT64_C(2080375182), // STVEWX |
1988 | UINT64_C(2080375246), // STVX |
1989 | UINT64_C(2080375758), // STVXL |
1990 | UINT64_C(2415919104), // STW |
1991 | UINT64_C(2415919104), // STW8 |
1992 | UINT64_C(2080376204), // STWAT |
1993 | UINT64_C(2080376108), // STWBRX |
1994 | UINT64_C(2080376618), // STWCIX |
1995 | UINT64_C(2080375085), // STWCX |
1996 | UINT64_C(2080375102), // STWEPX |
1997 | UINT64_C(2483027968), // STWU |
1998 | UINT64_C(2483027968), // STWU8 |
1999 | UINT64_C(2080375150), // STWUX |
2000 | UINT64_C(2080375150), // STWUX8 |
2001 | UINT64_C(2080375086), // STWX |
2002 | UINT64_C(2080375086), // STWX8 |
2003 | UINT64_C(2080375086), // STWXTLS |
2004 | UINT64_C(2080375086), // STWXTLS_ |
2005 | UINT64_C(2080375086), // STWXTLS_32 |
2006 | UINT64_C(4093640706), // STXSD |
2007 | UINT64_C(2080376216), // STXSDX |
2008 | UINT64_C(2080376602), // STXSIBX |
2009 | UINT64_C(2080376602), // STXSIBXv |
2010 | UINT64_C(2080376666), // STXSIHX |
2011 | UINT64_C(2080376666), // STXSIHXv |
2012 | UINT64_C(2080375064), // STXSIWX |
2013 | UINT64_C(4093640707), // STXSSP |
2014 | UINT64_C(2080376088), // STXSSPX |
2015 | UINT64_C(4093640709), // STXV |
2016 | UINT64_C(2080376792), // STXVB16X |
2017 | UINT64_C(2080376728), // STXVD2X |
2018 | UINT64_C(2080376664), // STXVH8X |
2019 | UINT64_C(2080375578), // STXVL |
2020 | UINT64_C(2080375642), // STXVLL |
2021 | UINT64_C(402653185), // STXVP |
2022 | UINT64_C(2080376218), // STXVPRL |
2023 | UINT64_C(2080376282), // STXVPRLL |
2024 | UINT64_C(2080375706), // STXVPX |
2025 | UINT64_C(2080375066), // STXVRBX |
2026 | UINT64_C(2080375258), // STXVRDX |
2027 | UINT64_C(2080375130), // STXVRHX |
2028 | UINT64_C(2080376090), // STXVRL |
2029 | UINT64_C(2080376154), // STXVRLL |
2030 | UINT64_C(2080375194), // STXVRWX |
2031 | UINT64_C(2080376600), // STXVW4X |
2032 | UINT64_C(2080375576), // STXVX |
2033 | UINT64_C(2080374864), // SUBF |
2034 | UINT64_C(2080374864), // SUBF8 |
2035 | UINT64_C(2080375888), // SUBF8O |
2036 | UINT64_C(2080375889), // SUBF8O_rec |
2037 | UINT64_C(2080374865), // SUBF8_rec |
2038 | UINT64_C(2080374800), // SUBFC |
2039 | UINT64_C(2080374800), // SUBFC8 |
2040 | UINT64_C(2080375824), // SUBFC8O |
2041 | UINT64_C(2080375825), // SUBFC8O_rec |
2042 | UINT64_C(2080374801), // SUBFC8_rec |
2043 | UINT64_C(2080375824), // SUBFCO |
2044 | UINT64_C(2080375825), // SUBFCO_rec |
2045 | UINT64_C(2080374801), // SUBFC_rec |
2046 | UINT64_C(2080375056), // SUBFE |
2047 | UINT64_C(2080375056), // SUBFE8 |
2048 | UINT64_C(2080376080), // SUBFE8O |
2049 | UINT64_C(2080376081), // SUBFE8O_rec |
2050 | UINT64_C(2080375057), // SUBFE8_rec |
2051 | UINT64_C(2080376080), // SUBFEO |
2052 | UINT64_C(2080376081), // SUBFEO_rec |
2053 | UINT64_C(2080375057), // SUBFE_rec |
2054 | UINT64_C(536870912), // SUBFIC |
2055 | UINT64_C(536870912), // SUBFIC8 |
2056 | UINT64_C(2080375248), // SUBFME |
2057 | UINT64_C(2080375248), // SUBFME8 |
2058 | UINT64_C(2080376272), // SUBFME8O |
2059 | UINT64_C(2080376273), // SUBFME8O_rec |
2060 | UINT64_C(2080375249), // SUBFME8_rec |
2061 | UINT64_C(2080376272), // SUBFMEO |
2062 | UINT64_C(2080376273), // SUBFMEO_rec |
2063 | UINT64_C(2080375249), // SUBFME_rec |
2064 | UINT64_C(2080375888), // SUBFO |
2065 | UINT64_C(2080375889), // SUBFO_rec |
2066 | UINT64_C(2080374928), // SUBFUS |
2067 | UINT64_C(2080374929), // SUBFUS_rec |
2068 | UINT64_C(2080375184), // SUBFZE |
2069 | UINT64_C(2080375184), // SUBFZE8 |
2070 | UINT64_C(2080376208), // SUBFZE8O |
2071 | UINT64_C(2080376209), // SUBFZE8O_rec |
2072 | UINT64_C(2080375185), // SUBFZE8_rec |
2073 | UINT64_C(2080376208), // SUBFZEO |
2074 | UINT64_C(2080376209), // SUBFZEO_rec |
2075 | UINT64_C(2080375185), // SUBFZE_rec |
2076 | UINT64_C(2080374865), // SUBF_rec |
2077 | UINT64_C(2080375980), // SYNC |
2078 | UINT64_C(2080375980), // SYNCP10 |
2079 | UINT64_C(2080376605), // TABORT |
2080 | UINT64_C(2080376413), // TABORTDC |
2081 | UINT64_C(2080376541), // TABORTDCI |
2082 | UINT64_C(2080376349), // TABORTWC |
2083 | UINT64_C(2080376477), // TABORTWCI |
2084 | UINT64_C(1207959552), // TAILB |
2085 | UINT64_C(1207959552), // TAILB8 |
2086 | UINT64_C(1207959552), // TAILBA |
2087 | UINT64_C(1207959552), // TAILBA8 |
2088 | UINT64_C(1317012512), // TAILBCTR |
2089 | UINT64_C(1317012512), // TAILBCTR8 |
2090 | UINT64_C(2080376093), // TBEGIN |
2091 | UINT64_C(0), // TBEGIN_RET |
2092 | UINT64_C(2080376220), // TCHECK |
2093 | UINT64_C(0), // TCHECK_RET |
2094 | UINT64_C(0), // TCRETURNai |
2095 | UINT64_C(0), // TCRETURNai8 |
2096 | UINT64_C(0), // TCRETURNdi |
2097 | UINT64_C(0), // TCRETURNdi8 |
2098 | UINT64_C(0), // TCRETURNri |
2099 | UINT64_C(0), // TCRETURNri8 |
2100 | UINT64_C(2080374920), // TD |
2101 | UINT64_C(134217728), // TDI |
2102 | UINT64_C(2080376157), // TEND |
2103 | UINT64_C(2080375524), // TLBIA |
2104 | UINT64_C(2080375396), // TLBIE |
2105 | UINT64_C(2080375332), // TLBIEL |
2106 | UINT64_C(2080374820), // TLBILX |
2107 | UINT64_C(2080376356), // TLBIVAX |
2108 | UINT64_C(2080376740), // TLBLD |
2109 | UINT64_C(2080376804), // TLBLI |
2110 | UINT64_C(2080376676), // TLBRE |
2111 | UINT64_C(2080376676), // TLBRE2 |
2112 | UINT64_C(2080376612), // TLBSX |
2113 | UINT64_C(2080376612), // TLBSX2 |
2114 | UINT64_C(2080376613), // TLBSX2D |
2115 | UINT64_C(2080375916), // TLBSYNC |
2116 | UINT64_C(2080376740), // TLBWE |
2117 | UINT64_C(2080376740), // TLBWE2 |
2118 | UINT64_C(0), // TLSGDAIX |
2119 | UINT64_C(0), // TLSGDAIX8 |
2120 | UINT64_C(0), // TLSLDAIX |
2121 | UINT64_C(0), // TLSLDAIX8 |
2122 | UINT64_C(2145386504), // TRAP |
2123 | UINT64_C(2080376797), // TRECHKPT |
2124 | UINT64_C(2080376669), // TRECLAIM |
2125 | UINT64_C(2080376285), // TSR |
2126 | UINT64_C(2080374792), // TW |
2127 | UINT64_C(201326592), // TWI |
2128 | UINT64_C(0), // UNENCODED_NOP |
2129 | UINT64_C(0), // UpdateGBR |
2130 | UINT64_C(268436483), // VABSDUB |
2131 | UINT64_C(268436547), // VABSDUH |
2132 | UINT64_C(268436611), // VABSDUW |
2133 | UINT64_C(268435776), // VADDCUQ |
2134 | UINT64_C(268435840), // VADDCUW |
2135 | UINT64_C(268435517), // VADDECUQ |
2136 | UINT64_C(268435516), // VADDEUQM |
2137 | UINT64_C(268435466), // VADDFP |
2138 | UINT64_C(268436224), // VADDSBS |
2139 | UINT64_C(268436288), // VADDSHS |
2140 | UINT64_C(268436352), // VADDSWS |
2141 | UINT64_C(268435456), // VADDUBM |
2142 | UINT64_C(268435968), // VADDUBS |
2143 | UINT64_C(268435648), // VADDUDM |
2144 | UINT64_C(268435520), // VADDUHM |
2145 | UINT64_C(268436032), // VADDUHS |
2146 | UINT64_C(268435712), // VADDUQM |
2147 | UINT64_C(268435584), // VADDUWM |
2148 | UINT64_C(268436096), // VADDUWS |
2149 | UINT64_C(268436484), // VAND |
2150 | UINT64_C(268436548), // VANDC |
2151 | UINT64_C(268436738), // VAVGSB |
2152 | UINT64_C(268436802), // VAVGSH |
2153 | UINT64_C(268436866), // VAVGSW |
2154 | UINT64_C(268436482), // VAVGUB |
2155 | UINT64_C(268436546), // VAVGUH |
2156 | UINT64_C(268436610), // VAVGUW |
2157 | UINT64_C(268436940), // VBPERMD |
2158 | UINT64_C(268436812), // VBPERMQ |
2159 | UINT64_C(268436298), // VCFSX |
2160 | UINT64_C(268436298), // VCFSX_0 |
2161 | UINT64_C(268436813), // VCFUGED |
2162 | UINT64_C(268436234), // VCFUX |
2163 | UINT64_C(268436234), // VCFUX_0 |
2164 | UINT64_C(268436744), // VCIPHER |
2165 | UINT64_C(268436745), // VCIPHERLAST |
2166 | UINT64_C(268435853), // VCLRLB |
2167 | UINT64_C(268435917), // VCLRRB |
2168 | UINT64_C(268437250), // VCLZB |
2169 | UINT64_C(268437442), // VCLZD |
2170 | UINT64_C(268437380), // VCLZDM |
2171 | UINT64_C(268437314), // VCLZH |
2172 | UINT64_C(268436994), // VCLZLSBB |
2173 | UINT64_C(268437378), // VCLZW |
2174 | UINT64_C(268436422), // VCMPBFP |
2175 | UINT64_C(268437446), // VCMPBFP_rec |
2176 | UINT64_C(268435654), // VCMPEQFP |
2177 | UINT64_C(268436678), // VCMPEQFP_rec |
2178 | UINT64_C(268435462), // VCMPEQUB |
2179 | UINT64_C(268436486), // VCMPEQUB_rec |
2180 | UINT64_C(268435655), // VCMPEQUD |
2181 | UINT64_C(268436679), // VCMPEQUD_rec |
2182 | UINT64_C(268435526), // VCMPEQUH |
2183 | UINT64_C(268436550), // VCMPEQUH_rec |
2184 | UINT64_C(268435911), // VCMPEQUQ |
2185 | UINT64_C(268436935), // VCMPEQUQ_rec |
2186 | UINT64_C(268435590), // VCMPEQUW |
2187 | UINT64_C(268436614), // VCMPEQUW_rec |
2188 | UINT64_C(268435910), // VCMPGEFP |
2189 | UINT64_C(268436934), // VCMPGEFP_rec |
2190 | UINT64_C(268436166), // VCMPGTFP |
2191 | UINT64_C(268437190), // VCMPGTFP_rec |
2192 | UINT64_C(268436230), // VCMPGTSB |
2193 | UINT64_C(268437254), // VCMPGTSB_rec |
2194 | UINT64_C(268436423), // VCMPGTSD |
2195 | UINT64_C(268437447), // VCMPGTSD_rec |
2196 | UINT64_C(268436294), // VCMPGTSH |
2197 | UINT64_C(268437318), // VCMPGTSH_rec |
2198 | UINT64_C(268436359), // VCMPGTSQ |
2199 | UINT64_C(268437383), // VCMPGTSQ_rec |
2200 | UINT64_C(268436358), // VCMPGTSW |
2201 | UINT64_C(268437382), // VCMPGTSW_rec |
2202 | UINT64_C(268435974), // VCMPGTUB |
2203 | UINT64_C(268436998), // VCMPGTUB_rec |
2204 | UINT64_C(268436167), // VCMPGTUD |
2205 | UINT64_C(268437191), // VCMPGTUD_rec |
2206 | UINT64_C(268436038), // VCMPGTUH |
2207 | UINT64_C(268437062), // VCMPGTUH_rec |
2208 | UINT64_C(268436103), // VCMPGTUQ |
2209 | UINT64_C(268437127), // VCMPGTUQ_rec |
2210 | UINT64_C(268436102), // VCMPGTUW |
2211 | UINT64_C(268437126), // VCMPGTUW_rec |
2212 | UINT64_C(268435463), // VCMPNEB |
2213 | UINT64_C(268436487), // VCMPNEB_rec |
2214 | UINT64_C(268435527), // VCMPNEH |
2215 | UINT64_C(268436551), // VCMPNEH_rec |
2216 | UINT64_C(268435591), // VCMPNEW |
2217 | UINT64_C(268436615), // VCMPNEW_rec |
2218 | UINT64_C(268435719), // VCMPNEZB |
2219 | UINT64_C(268436743), // VCMPNEZB_rec |
2220 | UINT64_C(268435783), // VCMPNEZH |
2221 | UINT64_C(268436807), // VCMPNEZH_rec |
2222 | UINT64_C(268435847), // VCMPNEZW |
2223 | UINT64_C(268436871), // VCMPNEZW_rec |
2224 | UINT64_C(268435777), // VCMPSQ |
2225 | UINT64_C(268435713), // VCMPUQ |
2226 | UINT64_C(270009922), // VCNTMBB |
2227 | UINT64_C(270403138), // VCNTMBD |
2228 | UINT64_C(270140994), // VCNTMBH |
2229 | UINT64_C(270272066), // VCNTMBW |
2230 | UINT64_C(268436426), // VCTSXS |
2231 | UINT64_C(268436426), // VCTSXS_0 |
2232 | UINT64_C(268436362), // VCTUXS |
2233 | UINT64_C(268436362), // VCTUXS_0 |
2234 | UINT64_C(270272002), // VCTZB |
2235 | UINT64_C(270468610), // VCTZD |
2236 | UINT64_C(268437444), // VCTZDM |
2237 | UINT64_C(270337538), // VCTZH |
2238 | UINT64_C(268502530), // VCTZLSBB |
2239 | UINT64_C(270403074), // VCTZW |
2240 | UINT64_C(268436427), // VDIVESD |
2241 | UINT64_C(268436235), // VDIVESQ |
2242 | UINT64_C(268436363), // VDIVESW |
2243 | UINT64_C(268436171), // VDIVEUD |
2244 | UINT64_C(268435979), // VDIVEUQ |
2245 | UINT64_C(268436107), // VDIVEUW |
2246 | UINT64_C(268435915), // VDIVSD |
2247 | UINT64_C(268435723), // VDIVSQ |
2248 | UINT64_C(268435851), // VDIVSW |
2249 | UINT64_C(268435659), // VDIVUD |
2250 | UINT64_C(268435467), // VDIVUQ |
2251 | UINT64_C(268435595), // VDIVUW |
2252 | UINT64_C(268437124), // VEQV |
2253 | UINT64_C(268437058), // VEXPANDBM |
2254 | UINT64_C(268633666), // VEXPANDDM |
2255 | UINT64_C(268502594), // VEXPANDHM |
2256 | UINT64_C(268699202), // VEXPANDQM |
2257 | UINT64_C(268568130), // VEXPANDWM |
2258 | UINT64_C(268435850), // VEXPTEFP |
2259 | UINT64_C(268435486), // VEXTDDVLX |
2260 | UINT64_C(268435487), // VEXTDDVRX |
2261 | UINT64_C(268435480), // VEXTDUBVLX |
2262 | UINT64_C(268435481), // VEXTDUBVRX |
2263 | UINT64_C(268435482), // VEXTDUHVLX |
2264 | UINT64_C(268435483), // VEXTDUHVRX |
2265 | UINT64_C(268435484), // VEXTDUWVLX |
2266 | UINT64_C(268435485), // VEXTDUWVRX |
2267 | UINT64_C(268961346), // VEXTRACTBM |
2268 | UINT64_C(268436173), // VEXTRACTD |
2269 | UINT64_C(269157954), // VEXTRACTDM |
2270 | UINT64_C(269026882), // VEXTRACTHM |
2271 | UINT64_C(269223490), // VEXTRACTQM |
2272 | UINT64_C(268435981), // VEXTRACTUB |
2273 | UINT64_C(268436045), // VEXTRACTUH |
2274 | UINT64_C(268436109), // VEXTRACTUW |
2275 | UINT64_C(269092418), // VEXTRACTWM |
2276 | UINT64_C(270009858), // VEXTSB2D |
2277 | UINT64_C(270009858), // VEXTSB2Ds |
2278 | UINT64_C(269485570), // VEXTSB2W |
2279 | UINT64_C(269485570), // VEXTSB2Ws |
2280 | UINT64_C(270206466), // VEXTSD2Q |
2281 | UINT64_C(270075394), // VEXTSH2D |
2282 | UINT64_C(270075394), // VEXTSH2Ds |
2283 | UINT64_C(269551106), // VEXTSH2W |
2284 | UINT64_C(269551106), // VEXTSH2Ws |
2285 | UINT64_C(270140930), // VEXTSW2D |
2286 | UINT64_C(270140930), // VEXTSW2Ds |
2287 | UINT64_C(268437005), // VEXTUBLX |
2288 | UINT64_C(268437261), // VEXTUBRX |
2289 | UINT64_C(268437069), // VEXTUHLX |
2290 | UINT64_C(268437325), // VEXTUHRX |
2291 | UINT64_C(268437133), // VEXTUWLX |
2292 | UINT64_C(268437389), // VEXTUWRX |
2293 | UINT64_C(268436748), // VGBBD |
2294 | UINT64_C(268436684), // VGNB |
2295 | UINT64_C(268435983), // VINSBLX |
2296 | UINT64_C(268436239), // VINSBRX |
2297 | UINT64_C(268435471), // VINSBVLX |
2298 | UINT64_C(268435727), // VINSBVRX |
2299 | UINT64_C(268435919), // VINSD |
2300 | UINT64_C(268436175), // VINSDLX |
2301 | UINT64_C(268436431), // VINSDRX |
2302 | UINT64_C(268436237), // VINSERTB |
2303 | UINT64_C(268436429), // VINSERTD |
2304 | UINT64_C(268436301), // VINSERTH |
2305 | UINT64_C(268436365), // VINSERTW |
2306 | UINT64_C(268436047), // VINSHLX |
2307 | UINT64_C(268436303), // VINSHRX |
2308 | UINT64_C(268435535), // VINSHVLX |
2309 | UINT64_C(268435791), // VINSHVRX |
2310 | UINT64_C(268435663), // VINSW |
2311 | UINT64_C(268436111), // VINSWLX |
2312 | UINT64_C(268436367), // VINSWRX |
2313 | UINT64_C(268435599), // VINSWVLX |
2314 | UINT64_C(268435855), // VINSWVRX |
2315 | UINT64_C(268435914), // VLOGEFP |
2316 | UINT64_C(268435502), // VMADDFP |
2317 | UINT64_C(268436490), // VMAXFP |
2318 | UINT64_C(268435714), // VMAXSB |
2319 | UINT64_C(268435906), // VMAXSD |
2320 | UINT64_C(268435778), // VMAXSH |
2321 | UINT64_C(268435842), // VMAXSW |
2322 | UINT64_C(268435458), // VMAXUB |
2323 | UINT64_C(268435650), // VMAXUD |
2324 | UINT64_C(268435522), // VMAXUH |
2325 | UINT64_C(268435586), // VMAXUW |
2326 | UINT64_C(268435488), // VMHADDSHS |
2327 | UINT64_C(268435489), // VMHRADDSHS |
2328 | UINT64_C(268436554), // VMINFP |
2329 | UINT64_C(268436226), // VMINSB |
2330 | UINT64_C(268436418), // VMINSD |
2331 | UINT64_C(268436290), // VMINSH |
2332 | UINT64_C(268436354), // VMINSW |
2333 | UINT64_C(268435970), // VMINUB |
2334 | UINT64_C(268436162), // VMINUD |
2335 | UINT64_C(268436034), // VMINUH |
2336 | UINT64_C(268436098), // VMINUW |
2337 | UINT64_C(268435490), // VMLADDUHM |
2338 | UINT64_C(268437451), // VMODSD |
2339 | UINT64_C(268437259), // VMODSQ |
2340 | UINT64_C(268437387), // VMODSW |
2341 | UINT64_C(268437195), // VMODUD |
2342 | UINT64_C(268437003), // VMODUQ |
2343 | UINT64_C(268437131), // VMODUW |
2344 | UINT64_C(268437388), // VMRGEW |
2345 | UINT64_C(268435468), // VMRGHB |
2346 | UINT64_C(268435532), // VMRGHH |
2347 | UINT64_C(268435596), // VMRGHW |
2348 | UINT64_C(268435724), // VMRGLB |
2349 | UINT64_C(268435788), // VMRGLH |
2350 | UINT64_C(268435852), // VMRGLW |
2351 | UINT64_C(268437132), // VMRGOW |
2352 | UINT64_C(268435479), // VMSUMCUD |
2353 | UINT64_C(268435493), // VMSUMMBM |
2354 | UINT64_C(268435496), // VMSUMSHM |
2355 | UINT64_C(268435497), // VMSUMSHS |
2356 | UINT64_C(268435492), // VMSUMUBM |
2357 | UINT64_C(268435491), // VMSUMUDM |
2358 | UINT64_C(268435494), // VMSUMUHM |
2359 | UINT64_C(268435495), // VMSUMUHS |
2360 | UINT64_C(268435457), // VMUL10CUQ |
2361 | UINT64_C(268435521), // VMUL10ECUQ |
2362 | UINT64_C(268436033), // VMUL10EUQ |
2363 | UINT64_C(268435969), // VMUL10UQ |
2364 | UINT64_C(268436232), // VMULESB |
2365 | UINT64_C(268436424), // VMULESD |
2366 | UINT64_C(268436296), // VMULESH |
2367 | UINT64_C(268436360), // VMULESW |
2368 | UINT64_C(268435976), // VMULEUB |
2369 | UINT64_C(268436168), // VMULEUD |
2370 | UINT64_C(268436040), // VMULEUH |
2371 | UINT64_C(268436104), // VMULEUW |
2372 | UINT64_C(268436425), // VMULHSD |
2373 | UINT64_C(268436361), // VMULHSW |
2374 | UINT64_C(268436169), // VMULHUD |
2375 | UINT64_C(268436105), // VMULHUW |
2376 | UINT64_C(268435913), // VMULLD |
2377 | UINT64_C(268435720), // VMULOSB |
2378 | UINT64_C(268435912), // VMULOSD |
2379 | UINT64_C(268435784), // VMULOSH |
2380 | UINT64_C(268435848), // VMULOSW |
2381 | UINT64_C(268435464), // VMULOUB |
2382 | UINT64_C(268435656), // VMULOUD |
2383 | UINT64_C(268435528), // VMULOUH |
2384 | UINT64_C(268435592), // VMULOUW |
2385 | UINT64_C(268435593), // VMULUWM |
2386 | UINT64_C(268436868), // VNAND |
2387 | UINT64_C(268436808), // VNCIPHER |
2388 | UINT64_C(268436809), // VNCIPHERLAST |
2389 | UINT64_C(268895746), // VNEGD |
2390 | UINT64_C(268830210), // VNEGW |
2391 | UINT64_C(268435503), // VNMSUBFP |
2392 | UINT64_C(268436740), // VNOR |
2393 | UINT64_C(268436612), // VOR |
2394 | UINT64_C(268436804), // VORC |
2395 | UINT64_C(268436941), // VPDEPD |
2396 | UINT64_C(268435499), // VPERM |
2397 | UINT64_C(268435515), // VPERMR |
2398 | UINT64_C(268435501), // VPERMXOR |
2399 | UINT64_C(268436877), // VPEXTD |
2400 | UINT64_C(268436238), // VPKPX |
2401 | UINT64_C(268436942), // VPKSDSS |
2402 | UINT64_C(268436814), // VPKSDUS |
2403 | UINT64_C(268435854), // VPKSHSS |
2404 | UINT64_C(268435726), // VPKSHUS |
2405 | UINT64_C(268435918), // VPKSWSS |
2406 | UINT64_C(268435790), // VPKSWUS |
2407 | UINT64_C(268436558), // VPKUDUM |
2408 | UINT64_C(268436686), // VPKUDUS |
2409 | UINT64_C(268435470), // VPKUHUM |
2410 | UINT64_C(268435598), // VPKUHUS |
2411 | UINT64_C(268435534), // VPKUWUM |
2412 | UINT64_C(268435662), // VPKUWUS |
2413 | UINT64_C(268436488), // VPMSUMB |
2414 | UINT64_C(268436680), // VPMSUMD |
2415 | UINT64_C(268436552), // VPMSUMH |
2416 | UINT64_C(268436616), // VPMSUMW |
2417 | UINT64_C(268437251), // VPOPCNTB |
2418 | UINT64_C(268437443), // VPOPCNTD |
2419 | UINT64_C(268437315), // VPOPCNTH |
2420 | UINT64_C(268437379), // VPOPCNTW |
2421 | UINT64_C(269026818), // VPRTYBD |
2422 | UINT64_C(269092354), // VPRTYBQ |
2423 | UINT64_C(268961282), // VPRTYBW |
2424 | UINT64_C(268435722), // VREFP |
2425 | UINT64_C(268436170), // VRFIM |
2426 | UINT64_C(268435978), // VRFIN |
2427 | UINT64_C(268436106), // VRFIP |
2428 | UINT64_C(268436042), // VRFIZ |
2429 | UINT64_C(268435460), // VRLB |
2430 | UINT64_C(268435652), // VRLD |
2431 | UINT64_C(268435653), // VRLDMI |
2432 | UINT64_C(268435909), // VRLDNM |
2433 | UINT64_C(268435524), // VRLH |
2434 | UINT64_C(268435461), // VRLQ |
2435 | UINT64_C(268435525), // VRLQMI |
2436 | UINT64_C(268435781), // VRLQNM |
2437 | UINT64_C(268435588), // VRLW |
2438 | UINT64_C(268435589), // VRLWMI |
2439 | UINT64_C(268435845), // VRLWNM |
2440 | UINT64_C(268435786), // VRSQRTEFP |
2441 | UINT64_C(268436936), // VSBOX |
2442 | UINT64_C(268435498), // VSEL |
2443 | UINT64_C(268437186), // VSHASIGMAD |
2444 | UINT64_C(268437122), // VSHASIGMAW |
2445 | UINT64_C(268435908), // VSL |
2446 | UINT64_C(268435716), // VSLB |
2447 | UINT64_C(268436932), // VSLD |
2448 | UINT64_C(268435478), // VSLDBI |
2449 | UINT64_C(268435500), // VSLDOI |
2450 | UINT64_C(268435780), // VSLH |
2451 | UINT64_C(268436492), // VSLO |
2452 | UINT64_C(268435717), // VSLQ |
2453 | UINT64_C(268437316), // VSLV |
2454 | UINT64_C(268435844), // VSLW |
2455 | UINT64_C(268435980), // VSPLTB |
2456 | UINT64_C(268435980), // VSPLTBs |
2457 | UINT64_C(268436044), // VSPLTH |
2458 | UINT64_C(268436044), // VSPLTHs |
2459 | UINT64_C(268436236), // VSPLTISB |
2460 | UINT64_C(268436300), // VSPLTISH |
2461 | UINT64_C(268436364), // VSPLTISW |
2462 | UINT64_C(268436108), // VSPLTW |
2463 | UINT64_C(268436164), // VSR |
2464 | UINT64_C(268436228), // VSRAB |
2465 | UINT64_C(268436420), // VSRAD |
2466 | UINT64_C(268436292), // VSRAH |
2467 | UINT64_C(268436229), // VSRAQ |
2468 | UINT64_C(268436356), // VSRAW |
2469 | UINT64_C(268435972), // VSRB |
2470 | UINT64_C(268437188), // VSRD |
2471 | UINT64_C(268435990), // VSRDBI |
2472 | UINT64_C(268436036), // VSRH |
2473 | UINT64_C(268436556), // VSRO |
2474 | UINT64_C(268435973), // VSRQ |
2475 | UINT64_C(268437252), // VSRV |
2476 | UINT64_C(268436100), // VSRW |
2477 | UINT64_C(268435469), // VSTRIBL |
2478 | UINT64_C(268436493), // VSTRIBL_rec |
2479 | UINT64_C(268501005), // VSTRIBR |
2480 | UINT64_C(268502029), // VSTRIBR_rec |
2481 | UINT64_C(268566541), // VSTRIHL |
2482 | UINT64_C(268567565), // VSTRIHL_rec |
2483 | UINT64_C(268632077), // VSTRIHR |
2484 | UINT64_C(268633101), // VSTRIHR_rec |
2485 | UINT64_C(268436800), // VSUBCUQ |
2486 | UINT64_C(268436864), // VSUBCUW |
2487 | UINT64_C(268435519), // VSUBECUQ |
2488 | UINT64_C(268435518), // VSUBEUQM |
2489 | UINT64_C(268435530), // VSUBFP |
2490 | UINT64_C(268437248), // VSUBSBS |
2491 | UINT64_C(268437312), // VSUBSHS |
2492 | UINT64_C(268437376), // VSUBSWS |
2493 | UINT64_C(268436480), // VSUBUBM |
2494 | UINT64_C(268436992), // VSUBUBS |
2495 | UINT64_C(268436672), // VSUBUDM |
2496 | UINT64_C(268436544), // VSUBUHM |
2497 | UINT64_C(268437056), // VSUBUHS |
2498 | UINT64_C(268436736), // VSUBUQM |
2499 | UINT64_C(268436608), // VSUBUWM |
2500 | UINT64_C(268437120), // VSUBUWS |
2501 | UINT64_C(268437128), // VSUM2SWS |
2502 | UINT64_C(268437256), // VSUM4SBS |
2503 | UINT64_C(268437064), // VSUM4SHS |
2504 | UINT64_C(268437000), // VSUM4UBS |
2505 | UINT64_C(268437384), // VSUMSWS |
2506 | UINT64_C(268436302), // VUPKHPX |
2507 | UINT64_C(268435982), // VUPKHSB |
2508 | UINT64_C(268436046), // VUPKHSH |
2509 | UINT64_C(268437070), // VUPKHSW |
2510 | UINT64_C(268436430), // VUPKLPX |
2511 | UINT64_C(268436110), // VUPKLSB |
2512 | UINT64_C(268436174), // VUPKLSH |
2513 | UINT64_C(268437198), // VUPKLSW |
2514 | UINT64_C(268436676), // VXOR |
2515 | UINT64_C(268436676), // V_SET0 |
2516 | UINT64_C(268436676), // V_SET0B |
2517 | UINT64_C(268436676), // V_SET0H |
2518 | UINT64_C(270467980), // V_SETALLONES |
2519 | UINT64_C(270467980), // V_SETALLONESB |
2520 | UINT64_C(270467980), // V_SETALLONESH |
2521 | UINT64_C(2080374844), // WAIT |
2522 | UINT64_C(2080374844), // WAITP10 |
2523 | UINT64_C(2080375046), // WRTEE |
2524 | UINT64_C(2080375110), // WRTEEI |
2525 | UINT64_C(2080375416), // XOR |
2526 | UINT64_C(2080375416), // XOR8 |
2527 | UINT64_C(2080375417), // XOR8_rec |
2528 | UINT64_C(1744830464), // XORI |
2529 | UINT64_C(1744830464), // XORI8 |
2530 | UINT64_C(1811939328), // XORIS |
2531 | UINT64_C(1811939328), // XORIS8 |
2532 | UINT64_C(2080375417), // XOR_rec |
2533 | UINT64_C(4026533220), // XSABSDP |
2534 | UINT64_C(4227860040), // XSABSQP |
2535 | UINT64_C(4026532096), // XSADDDP |
2536 | UINT64_C(4227858440), // XSADDQP |
2537 | UINT64_C(4227858441), // XSADDQPO |
2538 | UINT64_C(4026531840), // XSADDSP |
2539 | UINT64_C(4026531864), // XSCMPEQDP |
2540 | UINT64_C(4227858568), // XSCMPEQQP |
2541 | UINT64_C(4026532312), // XSCMPEXPDP |
2542 | UINT64_C(4227858760), // XSCMPEXPQP |
2543 | UINT64_C(4026531992), // XSCMPGEDP |
2544 | UINT64_C(4227858824), // XSCMPGEQP |
2545 | UINT64_C(4026531928), // XSCMPGTDP |
2546 | UINT64_C(4227858888), // XSCMPGTQP |
2547 | UINT64_C(4026532184), // XSCMPODP |
2548 | UINT64_C(4227858696), // XSCMPOQP |
2549 | UINT64_C(4026532120), // XSCMPUDP |
2550 | UINT64_C(4227859720), // XSCMPUQP |
2551 | UINT64_C(4026533248), // XSCPSGNDP |
2552 | UINT64_C(4227858632), // XSCPSGNQP |
2553 | UINT64_C(4027647340), // XSCVDPHP |
2554 | UINT64_C(4229301896), // XSCVDPQP |
2555 | UINT64_C(4026532900), // XSCVDPSP |
2556 | UINT64_C(4026532908), // XSCVDPSPN |
2557 | UINT64_C(4026533216), // XSCVDPSXDS |
2558 | UINT64_C(4026533216), // XSCVDPSXDSs |
2559 | UINT64_C(4026532192), // XSCVDPSXWS |
2560 | UINT64_C(4026532192), // XSCVDPSXWSs |
2561 | UINT64_C(4026533152), // XSCVDPUXDS |
2562 | UINT64_C(4026533152), // XSCVDPUXDSs |
2563 | UINT64_C(4026532128), // XSCVDPUXWS |
2564 | UINT64_C(4026532128), // XSCVDPUXWSs |
2565 | UINT64_C(4027581804), // XSCVHPDP |
2566 | UINT64_C(4229170824), // XSCVQPDP |
2567 | UINT64_C(4229170825), // XSCVQPDPO |
2568 | UINT64_C(4229498504), // XSCVQPSDZ |
2569 | UINT64_C(4228384392), // XSCVQPSQZ |
2570 | UINT64_C(4228449928), // XSCVQPSWZ |
2571 | UINT64_C(4228974216), // XSCVQPUDZ |
2572 | UINT64_C(4227860104), // XSCVQPUQZ |
2573 | UINT64_C(4227925640), // XSCVQPUWZ |
2574 | UINT64_C(4228515464), // XSCVSDQP |
2575 | UINT64_C(4026533156), // XSCVSPDP |
2576 | UINT64_C(4026533164), // XSCVSPDPN |
2577 | UINT64_C(4228581000), // XSCVSQQP |
2578 | UINT64_C(4026533344), // XSCVSXDDP |
2579 | UINT64_C(4026533088), // XSCVSXDSP |
2580 | UINT64_C(4227991176), // XSCVUDQP |
2581 | UINT64_C(4228056712), // XSCVUQQP |
2582 | UINT64_C(4026533280), // XSCVUXDDP |
2583 | UINT64_C(4026533024), // XSCVUXDSP |
2584 | UINT64_C(4026532288), // XSDIVDP |
2585 | UINT64_C(4227859528), // XSDIVQP |
2586 | UINT64_C(4227859529), // XSDIVQPO |
2587 | UINT64_C(4026532032), // XSDIVSP |
2588 | UINT64_C(4026533676), // XSIEXPDP |
2589 | UINT64_C(4227860168), // XSIEXPQP |
2590 | UINT64_C(4026532104), // XSMADDADP |
2591 | UINT64_C(4026531848), // XSMADDASP |
2592 | UINT64_C(4026532168), // XSMADDMDP |
2593 | UINT64_C(4026531912), // XSMADDMSP |
2594 | UINT64_C(4227859208), // XSMADDQP |
2595 | UINT64_C(4227859209), // XSMADDQPO |
2596 | UINT64_C(4026532864), // XSMAXCDP |
2597 | UINT64_C(4227859784), // XSMAXCQP |
2598 | UINT64_C(4026533120), // XSMAXDP |
2599 | UINT64_C(4026532992), // XSMAXJDP |
2600 | UINT64_C(4026532928), // XSMINCDP |
2601 | UINT64_C(4227859912), // XSMINCQP |
2602 | UINT64_C(4026533184), // XSMINDP |
2603 | UINT64_C(4026533056), // XSMINJDP |
2604 | UINT64_C(4026532232), // XSMSUBADP |
2605 | UINT64_C(4026531976), // XSMSUBASP |
2606 | UINT64_C(4026532296), // XSMSUBMDP |
2607 | UINT64_C(4026532040), // XSMSUBMSP |
2608 | UINT64_C(4227859272), // XSMSUBQP |
2609 | UINT64_C(4227859273), // XSMSUBQPO |
2610 | UINT64_C(4026532224), // XSMULDP |
2611 | UINT64_C(4227858504), // XSMULQP |
2612 | UINT64_C(4227858505), // XSMULQPO |
2613 | UINT64_C(4026531968), // XSMULSP |
2614 | UINT64_C(4026533284), // XSNABSDP |
2615 | UINT64_C(4026533284), // XSNABSDPs |
2616 | UINT64_C(4228384328), // XSNABSQP |
2617 | UINT64_C(4026533348), // XSNEGDP |
2618 | UINT64_C(4228908616), // XSNEGQP |
2619 | UINT64_C(4026533128), // XSNMADDADP |
2620 | UINT64_C(4026532872), // XSNMADDASP |
2621 | UINT64_C(4026533192), // XSNMADDMDP |
2622 | UINT64_C(4026532936), // XSNMADDMSP |
2623 | UINT64_C(4227859336), // XSNMADDQP |
2624 | UINT64_C(4227859337), // XSNMADDQPO |
2625 | UINT64_C(4026533256), // XSNMSUBADP |
2626 | UINT64_C(4026533000), // XSNMSUBASP |
2627 | UINT64_C(4026533320), // XSNMSUBMDP |
2628 | UINT64_C(4026533064), // XSNMSUBMSP |
2629 | UINT64_C(4227859400), // XSNMSUBQP |
2630 | UINT64_C(4227859401), // XSNMSUBQPO |
2631 | UINT64_C(4026532132), // XSRDPI |
2632 | UINT64_C(4026532268), // XSRDPIC |
2633 | UINT64_C(4026532324), // XSRDPIM |
2634 | UINT64_C(4026532260), // XSRDPIP |
2635 | UINT64_C(4026532196), // XSRDPIZ |
2636 | UINT64_C(4026532200), // XSREDP |
2637 | UINT64_C(4026531944), // XSRESP |
2638 | UINT64_C(4227858442), // XSRQPI |
2639 | UINT64_C(4227858443), // XSRQPIX |
2640 | UINT64_C(4227858506), // XSRQPXP |
2641 | UINT64_C(4026532964), // XSRSP |
2642 | UINT64_C(4026532136), // XSRSQRTEDP |
2643 | UINT64_C(4026531880), // XSRSQRTESP |
2644 | UINT64_C(4026532140), // XSSQRTDP |
2645 | UINT64_C(4229629512), // XSSQRTQP |
2646 | UINT64_C(4229629513), // XSSQRTQPO |
2647 | UINT64_C(4026531884), // XSSQRTSP |
2648 | UINT64_C(4026532160), // XSSUBDP |
2649 | UINT64_C(4227859464), // XSSUBQP |
2650 | UINT64_C(4227859465), // XSSUBQPO |
2651 | UINT64_C(4026531904), // XSSUBSP |
2652 | UINT64_C(4026532328), // XSTDIVDP |
2653 | UINT64_C(4026532264), // XSTSQRTDP |
2654 | UINT64_C(4026533288), // XSTSTDCDP |
2655 | UINT64_C(4227859848), // XSTSTDCQP |
2656 | UINT64_C(4026533032), // XSTSTDCSP |
2657 | UINT64_C(4026533228), // XSXEXPDP |
2658 | UINT64_C(4227991112), // XSXEXPQP |
2659 | UINT64_C(4026598764), // XSXSIGDP |
2660 | UINT64_C(4229039688), // XSXSIGQP |
2661 | UINT64_C(4026533732), // XVABSDP |
2662 | UINT64_C(4026533476), // XVABSSP |
2663 | UINT64_C(4026532608), // XVADDDP |
2664 | UINT64_C(4026532352), // XVADDSP |
2665 | UINT64_C(3959423384), // XVBF16GER2 |
2666 | UINT64_C(3959424912), // XVBF16GER2NN |
2667 | UINT64_C(3959423888), // XVBF16GER2NP |
2668 | UINT64_C(3959424400), // XVBF16GER2PN |
2669 | UINT64_C(3959423376), // XVBF16GER2PP |
2670 | UINT64_C(3959423384), // XVBF16GER2W |
2671 | UINT64_C(3959424912), // XVBF16GER2WNN |
2672 | UINT64_C(3959423888), // XVBF16GER2WNP |
2673 | UINT64_C(3959424400), // XVBF16GER2WPN |
2674 | UINT64_C(3959423376), // XVBF16GER2WPP |
2675 | UINT64_C(4026532632), // XVCMPEQDP |
2676 | UINT64_C(4026533656), // XVCMPEQDP_rec |
2677 | UINT64_C(4026532376), // XVCMPEQSP |
2678 | UINT64_C(4026533400), // XVCMPEQSP_rec |
2679 | UINT64_C(4026532760), // XVCMPGEDP |
2680 | UINT64_C(4026533784), // XVCMPGEDP_rec |
2681 | UINT64_C(4026532504), // XVCMPGESP |
2682 | UINT64_C(4026533528), // XVCMPGESP_rec |
2683 | UINT64_C(4026532696), // XVCMPGTDP |
2684 | UINT64_C(4026533720), // XVCMPGTDP_rec |
2685 | UINT64_C(4026532440), // XVCMPGTSP |
2686 | UINT64_C(4026533464), // XVCMPGTSP_rec |
2687 | UINT64_C(4026533760), // XVCPSGNDP |
2688 | UINT64_C(4026533504), // XVCPSGNSP |
2689 | UINT64_C(4027582316), // XVCVBF16SPN |
2690 | UINT64_C(4026533412), // XVCVDPSP |
2691 | UINT64_C(4026533728), // XVCVDPSXDS |
2692 | UINT64_C(4026532704), // XVCVDPSXWS |
2693 | UINT64_C(4026533664), // XVCVDPUXDS |
2694 | UINT64_C(4026532640), // XVCVDPUXWS |
2695 | UINT64_C(4028106604), // XVCVHPSP |
2696 | UINT64_C(4027647852), // XVCVSPBF16 |
2697 | UINT64_C(4026533668), // XVCVSPDP |
2698 | UINT64_C(4028172140), // XVCVSPHP |
2699 | UINT64_C(4026533472), // XVCVSPSXDS |
2700 | UINT64_C(4026532448), // XVCVSPSXWS |
2701 | UINT64_C(4026533408), // XVCVSPUXDS |
2702 | UINT64_C(4026532384), // XVCVSPUXWS |
2703 | UINT64_C(4026533856), // XVCVSXDDP |
2704 | UINT64_C(4026533600), // XVCVSXDSP |
2705 | UINT64_C(4026532832), // XVCVSXWDP |
2706 | UINT64_C(4026532576), // XVCVSXWSP |
2707 | UINT64_C(4026533792), // XVCVUXDDP |
2708 | UINT64_C(4026533536), // XVCVUXDSP |
2709 | UINT64_C(4026532768), // XVCVUXWDP |
2710 | UINT64_C(4026532512), // XVCVUXWSP |
2711 | UINT64_C(4026532800), // XVDIVDP |
2712 | UINT64_C(4026532544), // XVDIVSP |
2713 | UINT64_C(3959423128), // XVF16GER2 |
2714 | UINT64_C(3959424656), // XVF16GER2NN |
2715 | UINT64_C(3959423632), // XVF16GER2NP |
2716 | UINT64_C(3959424144), // XVF16GER2PN |
2717 | UINT64_C(3959423120), // XVF16GER2PP |
2718 | UINT64_C(3959423128), // XVF16GER2W |
2719 | UINT64_C(3959424656), // XVF16GER2WNN |
2720 | UINT64_C(3959423632), // XVF16GER2WNP |
2721 | UINT64_C(3959424144), // XVF16GER2WPN |
2722 | UINT64_C(3959423120), // XVF16GER2WPP |
2723 | UINT64_C(3959423192), // XVF32GER |
2724 | UINT64_C(3959424720), // XVF32GERNN |
2725 | UINT64_C(3959423696), // XVF32GERNP |
2726 | UINT64_C(3959424208), // XVF32GERPN |
2727 | UINT64_C(3959423184), // XVF32GERPP |
2728 | UINT64_C(3959423192), // XVF32GERW |
2729 | UINT64_C(3959424720), // XVF32GERWNN |
2730 | UINT64_C(3959423696), // XVF32GERWNP |
2731 | UINT64_C(3959424208), // XVF32GERWPN |
2732 | UINT64_C(3959423184), // XVF32GERWPP |
2733 | UINT64_C(3959423448), // XVF64GER |
2734 | UINT64_C(3959424976), // XVF64GERNN |
2735 | UINT64_C(3959423952), // XVF64GERNP |
2736 | UINT64_C(3959424464), // XVF64GERPN |
2737 | UINT64_C(3959423440), // XVF64GERPP |
2738 | UINT64_C(3959423448), // XVF64GERW |
2739 | UINT64_C(3959424976), // XVF64GERWNN |
2740 | UINT64_C(3959423952), // XVF64GERWNP |
2741 | UINT64_C(3959424464), // XVF64GERWPN |
2742 | UINT64_C(3959423440), // XVF64GERWPP |
2743 | UINT64_C(3959423576), // XVI16GER2 |
2744 | UINT64_C(3959423832), // XVI16GER2PP |
2745 | UINT64_C(3959423320), // XVI16GER2S |
2746 | UINT64_C(3959423312), // XVI16GER2SPP |
2747 | UINT64_C(3959423320), // XVI16GER2SW |
2748 | UINT64_C(3959423312), // XVI16GER2SWPP |
2749 | UINT64_C(3959423576), // XVI16GER2W |
2750 | UINT64_C(3959423832), // XVI16GER2WPP |
2751 | UINT64_C(3959423256), // XVI4GER8 |
2752 | UINT64_C(3959423248), // XVI4GER8PP |
2753 | UINT64_C(3959423256), // XVI4GER8W |
2754 | UINT64_C(3959423248), // XVI4GER8WPP |
2755 | UINT64_C(3959423000), // XVI8GER4 |
2756 | UINT64_C(3959422992), // XVI8GER4PP |
2757 | UINT64_C(3959423768), // XVI8GER4SPP |
2758 | UINT64_C(3959423000), // XVI8GER4W |
2759 | UINT64_C(3959422992), // XVI8GER4WPP |
2760 | UINT64_C(3959423768), // XVI8GER4WSPP |
2761 | UINT64_C(4026533824), // XVIEXPDP |
2762 | UINT64_C(4026533568), // XVIEXPSP |
2763 | UINT64_C(4026532616), // XVMADDADP |
2764 | UINT64_C(4026532360), // XVMADDASP |
2765 | UINT64_C(4026532680), // XVMADDMDP |
2766 | UINT64_C(4026532424), // XVMADDMSP |
2767 | UINT64_C(4026533632), // XVMAXDP |
2768 | UINT64_C(4026533376), // XVMAXSP |
2769 | UINT64_C(4026533696), // XVMINDP |
2770 | UINT64_C(4026533440), // XVMINSP |
2771 | UINT64_C(4026532744), // XVMSUBADP |
2772 | UINT64_C(4026532488), // XVMSUBASP |
2773 | UINT64_C(4026532808), // XVMSUBMDP |
2774 | UINT64_C(4026532552), // XVMSUBMSP |
2775 | UINT64_C(4026532736), // XVMULDP |
2776 | UINT64_C(4026532480), // XVMULSP |
2777 | UINT64_C(4026533796), // XVNABSDP |
2778 | UINT64_C(4026533540), // XVNABSSP |
2779 | UINT64_C(4026533860), // XVNEGDP |
2780 | UINT64_C(4026533604), // XVNEGSP |
2781 | UINT64_C(4026533640), // XVNMADDADP |
2782 | UINT64_C(4026533384), // XVNMADDASP |
2783 | UINT64_C(4026533704), // XVNMADDMDP |
2784 | UINT64_C(4026533448), // XVNMADDMSP |
2785 | UINT64_C(4026533768), // XVNMSUBADP |
2786 | UINT64_C(4026533512), // XVNMSUBASP |
2787 | UINT64_C(4026533832), // XVNMSUBMDP |
2788 | UINT64_C(4026533576), // XVNMSUBMSP |
2789 | UINT64_C(4026532644), // XVRDPI |
2790 | UINT64_C(4026532780), // XVRDPIC |
2791 | UINT64_C(4026532836), // XVRDPIM |
2792 | UINT64_C(4026532772), // XVRDPIP |
2793 | UINT64_C(4026532708), // XVRDPIZ |
2794 | UINT64_C(4026532712), // XVREDP |
2795 | UINT64_C(4026532456), // XVRESP |
2796 | UINT64_C(4026532388), // XVRSPI |
2797 | UINT64_C(4026532524), // XVRSPIC |
2798 | UINT64_C(4026532580), // XVRSPIM |
2799 | UINT64_C(4026532516), // XVRSPIP |
2800 | UINT64_C(4026532452), // XVRSPIZ |
2801 | UINT64_C(4026532648), // XVRSQRTEDP |
2802 | UINT64_C(4026532392), // XVRSQRTESP |
2803 | UINT64_C(4026532652), // XVSQRTDP |
2804 | UINT64_C(4026532396), // XVSQRTSP |
2805 | UINT64_C(4026532672), // XVSUBDP |
2806 | UINT64_C(4026532416), // XVSUBSP |
2807 | UINT64_C(4026532840), // XVTDIVDP |
2808 | UINT64_C(4026532584), // XVTDIVSP |
2809 | UINT64_C(4026664812), // XVTLSBB |
2810 | UINT64_C(4026532776), // XVTSQRTDP |
2811 | UINT64_C(4026532520), // XVTSQRTSP |
2812 | UINT64_C(4026533800), // XVTSTDCDP |
2813 | UINT64_C(4026533544), // XVTSTDCSP |
2814 | UINT64_C(4026533740), // XVXEXPDP |
2815 | UINT64_C(4027058028), // XVXEXPSP |
2816 | UINT64_C(4026599276), // XVXSIGDP |
2817 | UINT64_C(4027123564), // XVXSIGSP |
2818 | UINT64_C(360287972404232192), // XXBLENDVB |
2819 | UINT64_C(360287972404232240), // XXBLENDVD |
2820 | UINT64_C(360287972404232208), // XXBLENDVH |
2821 | UINT64_C(360287972404232224), // XXBLENDVW |
2822 | UINT64_C(4028041068), // XXBRD |
2823 | UINT64_C(4026992492), // XXBRH |
2824 | UINT64_C(4028565356), // XXBRQ |
2825 | UINT64_C(4027516780), // XXBRW |
2826 | UINT64_C(360287972471341072), // XXEVAL |
2827 | UINT64_C(4026532500), // XXEXTRACTUW |
2828 | UINT64_C(4026533672), // XXGENPCVBM |
2829 | UINT64_C(4026533738), // XXGENPCVDM |
2830 | UINT64_C(4026533674), // XXGENPCVHM |
2831 | UINT64_C(4026533736), // XXGENPCVWM |
2832 | UINT64_C(4026532564), // XXINSERTW |
2833 | UINT64_C(4026532880), // XXLAND |
2834 | UINT64_C(4026532944), // XXLANDC |
2835 | UINT64_C(4026533328), // XXLEQV |
2836 | UINT64_C(4026533328), // XXLEQVOnes |
2837 | UINT64_C(4026533264), // XXLNAND |
2838 | UINT64_C(4026533136), // XXLNOR |
2839 | UINT64_C(4026533008), // XXLOR |
2840 | UINT64_C(4026533200), // XXLORC |
2841 | UINT64_C(4026533008), // XXLORf |
2842 | UINT64_C(4026533072), // XXLXOR |
2843 | UINT64_C(4026533072), // XXLXORdpz |
2844 | UINT64_C(4026533072), // XXLXORspz |
2845 | UINT64_C(4026533072), // XXLXORz |
2846 | UINT64_C(2080375138), // XXMFACC |
2847 | UINT64_C(2080375138), // XXMFACCW |
2848 | UINT64_C(4026531984), // XXMRGHW |
2849 | UINT64_C(4026532240), // XXMRGLW |
2850 | UINT64_C(2080440674), // XXMTACC |
2851 | UINT64_C(2080440674), // XXMTACCW |
2852 | UINT64_C(4026532048), // XXPERM |
2853 | UINT64_C(4026531920), // XXPERMDI |
2854 | UINT64_C(4026531920), // XXPERMDIs |
2855 | UINT64_C(4026532304), // XXPERMR |
2856 | UINT64_C(360287972471341056), // XXPERMX |
2857 | UINT64_C(4026531888), // XXSEL |
2858 | UINT64_C(2080571746), // XXSETACCZ |
2859 | UINT64_C(2080571746), // XXSETACCZW |
2860 | UINT64_C(4026531856), // XXSLDWI |
2861 | UINT64_C(4026531856), // XXSLDWIs |
2862 | UINT64_C(360287972337123328), // XXSPLTI32DX |
2863 | UINT64_C(4026532560), // XXSPLTIB |
2864 | UINT64_C(360287972337385472), // XXSPLTIDP |
2865 | UINT64_C(360287972337516544), // XXSPLTIW |
2866 | UINT64_C(4026532496), // XXSPLTW |
2867 | UINT64_C(4026532496), // XXSPLTWs |
2868 | UINT64_C(1073741824), // gBC |
2869 | UINT64_C(1073741826), // gBCA |
2870 | UINT64_C(1073741826), // gBCAat |
2871 | UINT64_C(1275069472), // gBCCTR |
2872 | UINT64_C(1275069473), // gBCCTRL |
2873 | UINT64_C(1073741825), // gBCL |
2874 | UINT64_C(1073741827), // gBCLA |
2875 | UINT64_C(1073741827), // gBCLAat |
2876 | UINT64_C(1275068448), // gBCLR |
2877 | UINT64_C(1275068449), // gBCLRL |
2878 | UINT64_C(1073741825), // gBCLat |
2879 | UINT64_C(1073741824), // gBCat |
2880 | UINT64_C(0) |
2881 | }; |
2882 | const unsigned opcode = MI.getOpcode(); |
2883 | uint64_t Value = InstBits[opcode]; |
2884 | uint64_t op = 0; |
2885 | (void)op; // suppress warning |
2886 | switch (opcode) { |
2887 | case PPC::ADDISdtprelHA: |
2888 | case PPC::ADDISdtprelHA32: |
2889 | case PPC::ADDISgotTprelHA: |
2890 | case PPC::ADDIStlsgdHA: |
2891 | case PPC::ADDIStlsldHA: |
2892 | case PPC::ADDIStocHA: |
2893 | case PPC::ADDIStocHA8: |
2894 | case PPC::ADDIdtprelL: |
2895 | case PPC::ADDIdtprelL32: |
2896 | case PPC::ADDItlsgdL: |
2897 | case PPC::ADDItlsgdL32: |
2898 | case PPC::ADDItlsgdLADDR: |
2899 | case PPC::ADDItlsgdLADDR32: |
2900 | case PPC::ADDItlsldL: |
2901 | case PPC::ADDItlsldL32: |
2902 | case PPC::ADDItlsldLADDR: |
2903 | case PPC::ADDItlsldLADDR32: |
2904 | case PPC::ADDItoc: |
2905 | case PPC::ADDItoc8: |
2906 | case PPC::ADDItocL: |
2907 | case PPC::ADDItocL8: |
2908 | case PPC::ADJCALLSTACKDOWN: |
2909 | case PPC::ADJCALLSTACKUP: |
2910 | case PPC::ANDI_rec_1_EQ_BIT: |
2911 | case PPC::ANDI_rec_1_EQ_BIT8: |
2912 | case PPC::ANDI_rec_1_GT_BIT: |
2913 | case PPC::ANDI_rec_1_GT_BIT8: |
2914 | case PPC::ATOMIC_CMP_SWAP_I8: |
2915 | case PPC::ATOMIC_CMP_SWAP_I16: |
2916 | case PPC::ATOMIC_CMP_SWAP_I32: |
2917 | case PPC::ATOMIC_CMP_SWAP_I64: |
2918 | case PPC::ATOMIC_LOAD_ADD_I8: |
2919 | case PPC::ATOMIC_LOAD_ADD_I16: |
2920 | case PPC::ATOMIC_LOAD_ADD_I32: |
2921 | case PPC::ATOMIC_LOAD_ADD_I64: |
2922 | case PPC::ATOMIC_LOAD_AND_I8: |
2923 | case PPC::ATOMIC_LOAD_AND_I16: |
2924 | case PPC::ATOMIC_LOAD_AND_I32: |
2925 | case PPC::ATOMIC_LOAD_AND_I64: |
2926 | case PPC::ATOMIC_LOAD_MAX_I8: |
2927 | case PPC::ATOMIC_LOAD_MAX_I16: |
2928 | case PPC::ATOMIC_LOAD_MAX_I32: |
2929 | case PPC::ATOMIC_LOAD_MAX_I64: |
2930 | case PPC::ATOMIC_LOAD_MIN_I8: |
2931 | case PPC::ATOMIC_LOAD_MIN_I16: |
2932 | case PPC::ATOMIC_LOAD_MIN_I32: |
2933 | case PPC::ATOMIC_LOAD_MIN_I64: |
2934 | case PPC::ATOMIC_LOAD_NAND_I8: |
2935 | case PPC::ATOMIC_LOAD_NAND_I16: |
2936 | case PPC::ATOMIC_LOAD_NAND_I32: |
2937 | case PPC::ATOMIC_LOAD_NAND_I64: |
2938 | case PPC::ATOMIC_LOAD_OR_I8: |
2939 | case PPC::ATOMIC_LOAD_OR_I16: |
2940 | case PPC::ATOMIC_LOAD_OR_I32: |
2941 | case PPC::ATOMIC_LOAD_OR_I64: |
2942 | case PPC::ATOMIC_LOAD_SUB_I8: |
2943 | case PPC::ATOMIC_LOAD_SUB_I16: |
2944 | case PPC::ATOMIC_LOAD_SUB_I32: |
2945 | case PPC::ATOMIC_LOAD_SUB_I64: |
2946 | case PPC::ATOMIC_LOAD_UMAX_I8: |
2947 | case PPC::ATOMIC_LOAD_UMAX_I16: |
2948 | case PPC::ATOMIC_LOAD_UMAX_I32: |
2949 | case PPC::ATOMIC_LOAD_UMAX_I64: |
2950 | case PPC::ATOMIC_LOAD_UMIN_I8: |
2951 | case PPC::ATOMIC_LOAD_UMIN_I16: |
2952 | case PPC::ATOMIC_LOAD_UMIN_I32: |
2953 | case PPC::ATOMIC_LOAD_UMIN_I64: |
2954 | case PPC::ATOMIC_LOAD_XOR_I8: |
2955 | case PPC::ATOMIC_LOAD_XOR_I16: |
2956 | case PPC::ATOMIC_LOAD_XOR_I32: |
2957 | case PPC::ATOMIC_LOAD_XOR_I64: |
2958 | case PPC::ATOMIC_SWAP_I8: |
2959 | case PPC::ATOMIC_SWAP_I16: |
2960 | case PPC::ATOMIC_SWAP_I32: |
2961 | case PPC::ATOMIC_SWAP_I64: |
2962 | case PPC::ATTN: |
2963 | case PPC::BCTR: |
2964 | case PPC::BCTR8: |
2965 | case PPC::BCTRL: |
2966 | case PPC::BCTRL8: |
2967 | case PPC::BCTRL8_RM: |
2968 | case PPC::BCTRL_RM: |
2969 | case PPC::BDNZLR: |
2970 | case PPC::BDNZLR8: |
2971 | case PPC::BDNZLRL: |
2972 | case PPC::BDNZLRLm: |
2973 | case PPC::BDNZLRLp: |
2974 | case PPC::BDNZLRm: |
2975 | case PPC::BDNZLRp: |
2976 | case PPC::BDZLR: |
2977 | case PPC::BDZLR8: |
2978 | case PPC::BDZLRL: |
2979 | case PPC::BDZLRLm: |
2980 | case PPC::BDZLRLp: |
2981 | case PPC::BDZLRm: |
2982 | case PPC::BDZLRp: |
2983 | case PPC::BLR: |
2984 | case PPC::BLR8: |
2985 | case PPC::BLRL: |
2986 | case PPC::CLRBHRB: |
2987 | case PPC::CP_ABORT: |
2988 | case PPC::CR6SET: |
2989 | case PPC::CR6UNSET: |
2990 | case PPC::DSSALL: |
2991 | case PPC::DYNALLOC: |
2992 | case PPC::DYNALLOC8: |
2993 | case PPC::DYNAREAOFFSET: |
2994 | case PPC::DYNAREAOFFSET8: |
2995 | case PPC::DecreaseCTR8loop: |
2996 | case PPC::DecreaseCTRloop: |
2997 | case PPC::EH_SjLj_LongJmp32: |
2998 | case PPC::EH_SjLj_LongJmp64: |
2999 | case PPC::EH_SjLj_SetJmp32: |
3000 | case PPC::EH_SjLj_SetJmp64: |
3001 | case PPC::EH_SjLj_Setup: |
3002 | case PPC::EnforceIEIO: |
3003 | case PPC::FADDrtz: |
3004 | case PPC::FENCE: |
3005 | case PPC::GETtlsADDR: |
3006 | case PPC::GETtlsADDR32: |
3007 | case PPC::GETtlsADDR32AIX: |
3008 | case PPC::GETtlsADDR64AIX: |
3009 | case PPC::GETtlsADDRPCREL: |
3010 | case PPC::GETtlsMOD32AIX: |
3011 | case PPC::GETtlsMOD64AIX: |
3012 | case PPC::GETtlsTpointer32AIX: |
3013 | case PPC::GETtlsldADDR: |
3014 | case PPC::GETtlsldADDR32: |
3015 | case PPC::GETtlsldADDRPCREL: |
3016 | case PPC::HRFID: |
3017 | case PPC::ISYNC: |
3018 | case PPC::LDgotTprelL: |
3019 | case PPC::LDgotTprelL32: |
3020 | case PPC::LDtoc: |
3021 | case PPC::LDtocBA: |
3022 | case PPC::LDtocCPT: |
3023 | case PPC::LDtocJTI: |
3024 | case PPC::LDtocL: |
3025 | case PPC::LQX_PSEUDO: |
3026 | case PPC::LWZtoc: |
3027 | case PPC::LWZtocL: |
3028 | case PPC::MSGSYNC: |
3029 | case PPC::MSYNC: |
3030 | case PPC::MoveGOTtoLR: |
3031 | case PPC::MovePCtoLR: |
3032 | case PPC::MovePCtoLR8: |
3033 | case PPC::NAP: |
3034 | case PPC::NOP: |
3035 | case PPC::NOP_GT_PWR6: |
3036 | case PPC::NOP_GT_PWR7: |
3037 | case PPC::PADDIdtprel: |
3038 | case PPC::PPC32GOT: |
3039 | case PPC::PPC32PICGOT: |
3040 | case PPC::PREPARE_PROBED_ALLOCA_32: |
3041 | case PPC::PREPARE_PROBED_ALLOCA_64: |
3042 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32: |
3043 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64: |
3044 | case PPC::PROBED_ALLOCA_32: |
3045 | case PPC::PROBED_ALLOCA_64: |
3046 | case PPC::PROBED_STACKALLOC_32: |
3047 | case PPC::PROBED_STACKALLOC_64: |
3048 | case PPC::PseudoEIEIO: |
3049 | case PPC::RESTORE_ACC: |
3050 | case PPC::RESTORE_CR: |
3051 | case PPC::RESTORE_CRBIT: |
3052 | case PPC::RESTORE_QUADWORD: |
3053 | case PPC::RESTORE_UACC: |
3054 | case PPC::RESTORE_WACC: |
3055 | case PPC::RFCI: |
3056 | case PPC::RFDI: |
3057 | case PPC::RFI: |
3058 | case PPC::RFID: |
3059 | case PPC::RFMCI: |
3060 | case PPC::ReadTB: |
3061 | case PPC::SELECT_CC_F4: |
3062 | case PPC::SELECT_CC_F8: |
3063 | case PPC::SELECT_CC_F16: |
3064 | case PPC::SELECT_CC_I4: |
3065 | case PPC::SELECT_CC_I8: |
3066 | case PPC::SELECT_CC_SPE: |
3067 | case PPC::SELECT_CC_SPE4: |
3068 | case PPC::SELECT_CC_VRRC: |
3069 | case PPC::SELECT_CC_VSFRC: |
3070 | case PPC::SELECT_CC_VSRC: |
3071 | case PPC::SELECT_CC_VSSRC: |
3072 | case PPC::SELECT_F4: |
3073 | case PPC::SELECT_F8: |
3074 | case PPC::SELECT_F16: |
3075 | case PPC::SELECT_I4: |
3076 | case PPC::SELECT_I8: |
3077 | case PPC::SELECT_SPE: |
3078 | case PPC::SELECT_SPE4: |
3079 | case PPC::SELECT_VRRC: |
3080 | case PPC::SELECT_VSFRC: |
3081 | case PPC::SELECT_VSRC: |
3082 | case PPC::SELECT_VSSRC: |
3083 | case PPC::SETFLM: |
3084 | case PPC::SETRND: |
3085 | case PPC::SETRNDi: |
3086 | case PPC::SLBIA: |
3087 | case PPC::SLBSYNC: |
3088 | case PPC::SPILL_ACC: |
3089 | case PPC::SPILL_CR: |
3090 | case PPC::SPILL_CRBIT: |
3091 | case PPC::SPILL_QUADWORD: |
3092 | case PPC::SPILL_UACC: |
3093 | case PPC::SPILL_WACC: |
3094 | case PPC::SPLIT_QUADWORD: |
3095 | case PPC::STOP: |
3096 | case PPC::STQX_PSEUDO: |
3097 | case PPC::TAILBCTR: |
3098 | case PPC::TAILBCTR8: |
3099 | case PPC::TBEGIN_RET: |
3100 | case PPC::TCHECK_RET: |
3101 | case PPC::TCRETURNai: |
3102 | case PPC::TCRETURNai8: |
3103 | case PPC::TCRETURNdi: |
3104 | case PPC::TCRETURNdi8: |
3105 | case PPC::TCRETURNri: |
3106 | case PPC::TCRETURNri8: |
3107 | case PPC::TLBIA: |
3108 | case PPC::TLBRE: |
3109 | case PPC::TLBSYNC: |
3110 | case PPC::TLBWE: |
3111 | case PPC::TLSGDAIX: |
3112 | case PPC::TLSGDAIX8: |
3113 | case PPC::TLSLDAIX: |
3114 | case PPC::TLSLDAIX8: |
3115 | case PPC::TRAP: |
3116 | case PPC::TRECHKPT: |
3117 | case PPC::UNENCODED_NOP: |
3118 | case PPC::UpdateGBR: { |
3119 | break; |
3120 | } |
3121 | case PPC::TEND: { |
3122 | // op: A |
3123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3124 | op &= UINT64_C(1); |
3125 | op <<= 25; |
3126 | Value |= op; |
3127 | break; |
3128 | } |
3129 | case PPC::DMSETDMRZ: |
3130 | case PPC::XXMTACC: |
3131 | case PPC::XXMTACCW: |
3132 | case PPC::XXSETACCZ: |
3133 | case PPC::XXSETACCZW: { |
3134 | // op: AT |
3135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3136 | op &= UINT64_C(7); |
3137 | op <<= 23; |
3138 | Value |= op; |
3139 | break; |
3140 | } |
3141 | case PPC::DMMR: { |
3142 | // op: AT |
3143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3144 | op &= UINT64_C(7); |
3145 | op <<= 23; |
3146 | Value |= op; |
3147 | // op: AB |
3148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3149 | op &= UINT64_C(7); |
3150 | op <<= 13; |
3151 | Value |= op; |
3152 | break; |
3153 | } |
3154 | case PPC::DMXOR: { |
3155 | // op: AT |
3156 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3157 | op &= UINT64_C(7); |
3158 | op <<= 23; |
3159 | Value |= op; |
3160 | // op: AB |
3161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3162 | op &= UINT64_C(7); |
3163 | op <<= 13; |
3164 | Value |= op; |
3165 | break; |
3166 | } |
3167 | case PPC::XVBF16GER2: |
3168 | case PPC::XVBF16GER2W: |
3169 | case PPC::XVF16GER2: |
3170 | case PPC::XVF16GER2W: |
3171 | case PPC::XVF32GER: |
3172 | case PPC::XVF32GERW: |
3173 | case PPC::XVI4GER8: |
3174 | case PPC::XVI4GER8W: |
3175 | case PPC::XVI8GER4: |
3176 | case PPC::XVI8GER4W: |
3177 | case PPC::XVI16GER2: |
3178 | case PPC::XVI16GER2S: |
3179 | case PPC::XVI16GER2SW: |
3180 | case PPC::XVI16GER2W: { |
3181 | // op: AT |
3182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3183 | op &= UINT64_C(7); |
3184 | op <<= 23; |
3185 | Value |= op; |
3186 | // op: XA |
3187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3188 | Value |= (op & UINT64_C(31)) << 16; |
3189 | Value |= (op & UINT64_C(32)) >> 3; |
3190 | // op: XB |
3191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3192 | Value |= (op & UINT64_C(31)) << 11; |
3193 | Value |= (op & UINT64_C(32)) >> 4; |
3194 | break; |
3195 | } |
3196 | case PPC::PMXVF32GER: |
3197 | case PPC::PMXVF32GERW: { |
3198 | // op: AT |
3199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3200 | op &= UINT64_C(7); |
3201 | op <<= 23; |
3202 | Value |= op; |
3203 | // op: XA |
3204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3205 | Value |= (op & UINT64_C(31)) << 16; |
3206 | Value |= (op & UINT64_C(32)) >> 3; |
3207 | // op: XB |
3208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3209 | Value |= (op & UINT64_C(31)) << 11; |
3210 | Value |= (op & UINT64_C(32)) >> 4; |
3211 | // op: XMSK |
3212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3213 | op &= UINT64_C(15); |
3214 | op <<= 36; |
3215 | Value |= op; |
3216 | // op: YMSK |
3217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3218 | op &= UINT64_C(15); |
3219 | op <<= 32; |
3220 | Value |= op; |
3221 | break; |
3222 | } |
3223 | case PPC::PMXVI8GER4: |
3224 | case PPC::PMXVI8GER4W: { |
3225 | // op: AT |
3226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3227 | op &= UINT64_C(7); |
3228 | op <<= 23; |
3229 | Value |= op; |
3230 | // op: XA |
3231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3232 | Value |= (op & UINT64_C(31)) << 16; |
3233 | Value |= (op & UINT64_C(32)) >> 3; |
3234 | // op: XB |
3235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3236 | Value |= (op & UINT64_C(31)) << 11; |
3237 | Value |= (op & UINT64_C(32)) >> 4; |
3238 | // op: XMSK |
3239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3240 | op &= UINT64_C(15); |
3241 | op <<= 36; |
3242 | Value |= op; |
3243 | // op: YMSK |
3244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3245 | op &= UINT64_C(15); |
3246 | op <<= 32; |
3247 | Value |= op; |
3248 | // op: PMSK |
3249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3250 | op &= UINT64_C(15); |
3251 | op <<= 44; |
3252 | Value |= op; |
3253 | break; |
3254 | } |
3255 | case PPC::PMXVI4GER8: |
3256 | case PPC::PMXVI4GER8W: { |
3257 | // op: AT |
3258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3259 | op &= UINT64_C(7); |
3260 | op <<= 23; |
3261 | Value |= op; |
3262 | // op: XA |
3263 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3264 | Value |= (op & UINT64_C(31)) << 16; |
3265 | Value |= (op & UINT64_C(32)) >> 3; |
3266 | // op: XB |
3267 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3268 | Value |= (op & UINT64_C(31)) << 11; |
3269 | Value |= (op & UINT64_C(32)) >> 4; |
3270 | // op: XMSK |
3271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3272 | op &= UINT64_C(15); |
3273 | op <<= 36; |
3274 | Value |= op; |
3275 | // op: YMSK |
3276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3277 | op &= UINT64_C(15); |
3278 | op <<= 32; |
3279 | Value |= op; |
3280 | // op: PMSK |
3281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3282 | op &= UINT64_C(255); |
3283 | op <<= 40; |
3284 | Value |= op; |
3285 | break; |
3286 | } |
3287 | case PPC::PMXVBF16GER2: |
3288 | case PPC::PMXVBF16GER2W: |
3289 | case PPC::PMXVF16GER2: |
3290 | case PPC::PMXVF16GER2W: |
3291 | case PPC::PMXVI16GER2: |
3292 | case PPC::PMXVI16GER2S: |
3293 | case PPC::PMXVI16GER2SW: |
3294 | case PPC::PMXVI16GER2W: { |
3295 | // op: AT |
3296 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3297 | op &= UINT64_C(7); |
3298 | op <<= 23; |
3299 | Value |= op; |
3300 | // op: XA |
3301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3302 | Value |= (op & UINT64_C(31)) << 16; |
3303 | Value |= (op & UINT64_C(32)) >> 3; |
3304 | // op: XB |
3305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3306 | Value |= (op & UINT64_C(31)) << 11; |
3307 | Value |= (op & UINT64_C(32)) >> 4; |
3308 | // op: XMSK |
3309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3310 | op &= UINT64_C(15); |
3311 | op <<= 36; |
3312 | Value |= op; |
3313 | // op: YMSK |
3314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3315 | op &= UINT64_C(15); |
3316 | op <<= 32; |
3317 | Value |= op; |
3318 | // op: PMSK |
3319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3320 | op &= UINT64_C(3); |
3321 | op <<= 46; |
3322 | Value |= op; |
3323 | break; |
3324 | } |
3325 | case PPC::XVBF16GER2NN: |
3326 | case PPC::XVBF16GER2NP: |
3327 | case PPC::XVBF16GER2PN: |
3328 | case PPC::XVBF16GER2PP: |
3329 | case PPC::XVBF16GER2WNN: |
3330 | case PPC::XVBF16GER2WNP: |
3331 | case PPC::XVBF16GER2WPN: |
3332 | case PPC::XVBF16GER2WPP: |
3333 | case PPC::XVF16GER2NN: |
3334 | case PPC::XVF16GER2NP: |
3335 | case PPC::XVF16GER2PN: |
3336 | case PPC::XVF16GER2PP: |
3337 | case PPC::XVF16GER2WNN: |
3338 | case PPC::XVF16GER2WNP: |
3339 | case PPC::XVF16GER2WPN: |
3340 | case PPC::XVF16GER2WPP: |
3341 | case PPC::XVF32GERNN: |
3342 | case PPC::XVF32GERNP: |
3343 | case PPC::XVF32GERPN: |
3344 | case PPC::XVF32GERPP: |
3345 | case PPC::XVF32GERWNN: |
3346 | case PPC::XVF32GERWNP: |
3347 | case PPC::XVF32GERWPN: |
3348 | case PPC::XVF32GERWPP: |
3349 | case PPC::XVI4GER8PP: |
3350 | case PPC::XVI4GER8WPP: |
3351 | case PPC::XVI8GER4PP: |
3352 | case PPC::XVI8GER4SPP: |
3353 | case PPC::XVI8GER4WPP: |
3354 | case PPC::XVI8GER4WSPP: |
3355 | case PPC::XVI16GER2PP: |
3356 | case PPC::XVI16GER2SPP: |
3357 | case PPC::XVI16GER2SWPP: |
3358 | case PPC::XVI16GER2WPP: { |
3359 | // op: AT |
3360 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3361 | op &= UINT64_C(7); |
3362 | op <<= 23; |
3363 | Value |= op; |
3364 | // op: XA |
3365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3366 | Value |= (op & UINT64_C(31)) << 16; |
3367 | Value |= (op & UINT64_C(32)) >> 3; |
3368 | // op: XB |
3369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3370 | Value |= (op & UINT64_C(31)) << 11; |
3371 | Value |= (op & UINT64_C(32)) >> 4; |
3372 | break; |
3373 | } |
3374 | case PPC::PMXVF32GERNN: |
3375 | case PPC::PMXVF32GERNP: |
3376 | case PPC::PMXVF32GERPN: |
3377 | case PPC::PMXVF32GERPP: |
3378 | case PPC::PMXVF32GERWNN: |
3379 | case PPC::PMXVF32GERWNP: |
3380 | case PPC::PMXVF32GERWPN: |
3381 | case PPC::PMXVF32GERWPP: { |
3382 | // op: AT |
3383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3384 | op &= UINT64_C(7); |
3385 | op <<= 23; |
3386 | Value |= op; |
3387 | // op: XA |
3388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3389 | Value |= (op & UINT64_C(31)) << 16; |
3390 | Value |= (op & UINT64_C(32)) >> 3; |
3391 | // op: XB |
3392 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3393 | Value |= (op & UINT64_C(31)) << 11; |
3394 | Value |= (op & UINT64_C(32)) >> 4; |
3395 | // op: XMSK |
3396 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3397 | op &= UINT64_C(15); |
3398 | op <<= 36; |
3399 | Value |= op; |
3400 | // op: YMSK |
3401 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3402 | op &= UINT64_C(15); |
3403 | op <<= 32; |
3404 | Value |= op; |
3405 | break; |
3406 | } |
3407 | case PPC::PMXVI8GER4PP: |
3408 | case PPC::PMXVI8GER4SPP: |
3409 | case PPC::PMXVI8GER4WPP: |
3410 | case PPC::PMXVI8GER4WSPP: { |
3411 | // op: AT |
3412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3413 | op &= UINT64_C(7); |
3414 | op <<= 23; |
3415 | Value |= op; |
3416 | // op: XA |
3417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3418 | Value |= (op & UINT64_C(31)) << 16; |
3419 | Value |= (op & UINT64_C(32)) >> 3; |
3420 | // op: XB |
3421 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3422 | Value |= (op & UINT64_C(31)) << 11; |
3423 | Value |= (op & UINT64_C(32)) >> 4; |
3424 | // op: XMSK |
3425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3426 | op &= UINT64_C(15); |
3427 | op <<= 36; |
3428 | Value |= op; |
3429 | // op: YMSK |
3430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3431 | op &= UINT64_C(15); |
3432 | op <<= 32; |
3433 | Value |= op; |
3434 | // op: PMSK |
3435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
3436 | op &= UINT64_C(15); |
3437 | op <<= 44; |
3438 | Value |= op; |
3439 | break; |
3440 | } |
3441 | case PPC::PMXVI4GER8PP: |
3442 | case PPC::PMXVI4GER8WPP: { |
3443 | // op: AT |
3444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3445 | op &= UINT64_C(7); |
3446 | op <<= 23; |
3447 | Value |= op; |
3448 | // op: XA |
3449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3450 | Value |= (op & UINT64_C(31)) << 16; |
3451 | Value |= (op & UINT64_C(32)) >> 3; |
3452 | // op: XB |
3453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3454 | Value |= (op & UINT64_C(31)) << 11; |
3455 | Value |= (op & UINT64_C(32)) >> 4; |
3456 | // op: XMSK |
3457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3458 | op &= UINT64_C(15); |
3459 | op <<= 36; |
3460 | Value |= op; |
3461 | // op: YMSK |
3462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3463 | op &= UINT64_C(15); |
3464 | op <<= 32; |
3465 | Value |= op; |
3466 | // op: PMSK |
3467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
3468 | op &= UINT64_C(255); |
3469 | op <<= 40; |
3470 | Value |= op; |
3471 | break; |
3472 | } |
3473 | case PPC::PMXVBF16GER2NN: |
3474 | case PPC::PMXVBF16GER2NP: |
3475 | case PPC::PMXVBF16GER2PN: |
3476 | case PPC::PMXVBF16GER2PP: |
3477 | case PPC::PMXVBF16GER2WNN: |
3478 | case PPC::PMXVBF16GER2WNP: |
3479 | case PPC::PMXVBF16GER2WPN: |
3480 | case PPC::PMXVBF16GER2WPP: |
3481 | case PPC::PMXVF16GER2NN: |
3482 | case PPC::PMXVF16GER2NP: |
3483 | case PPC::PMXVF16GER2PN: |
3484 | case PPC::PMXVF16GER2PP: |
3485 | case PPC::PMXVF16GER2WNN: |
3486 | case PPC::PMXVF16GER2WNP: |
3487 | case PPC::PMXVF16GER2WPN: |
3488 | case PPC::PMXVF16GER2WPP: |
3489 | case PPC::PMXVI16GER2PP: |
3490 | case PPC::PMXVI16GER2SPP: |
3491 | case PPC::PMXVI16GER2SWPP: |
3492 | case PPC::PMXVI16GER2WPP: { |
3493 | // op: AT |
3494 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3495 | op &= UINT64_C(7); |
3496 | op <<= 23; |
3497 | Value |= op; |
3498 | // op: XA |
3499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3500 | Value |= (op & UINT64_C(31)) << 16; |
3501 | Value |= (op & UINT64_C(32)) >> 3; |
3502 | // op: XB |
3503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3504 | Value |= (op & UINT64_C(31)) << 11; |
3505 | Value |= (op & UINT64_C(32)) >> 4; |
3506 | // op: XMSK |
3507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3508 | op &= UINT64_C(15); |
3509 | op <<= 36; |
3510 | Value |= op; |
3511 | // op: YMSK |
3512 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3513 | op &= UINT64_C(15); |
3514 | op <<= 32; |
3515 | Value |= op; |
3516 | // op: PMSK |
3517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
3518 | op &= UINT64_C(3); |
3519 | op <<= 46; |
3520 | Value |= op; |
3521 | break; |
3522 | } |
3523 | case PPC::XVF64GER: |
3524 | case PPC::XVF64GERW: { |
3525 | // op: AT |
3526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3527 | op &= UINT64_C(7); |
3528 | op <<= 23; |
3529 | Value |= op; |
3530 | // op: XA |
3531 | op = getVSRpEvenEncoding(MI, OpNo: 1, Fixups, STI); |
3532 | Value |= (op & UINT64_C(31)) << 16; |
3533 | Value |= (op & UINT64_C(32)) >> 3; |
3534 | // op: XB |
3535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3536 | Value |= (op & UINT64_C(31)) << 11; |
3537 | Value |= (op & UINT64_C(32)) >> 4; |
3538 | break; |
3539 | } |
3540 | case PPC::PMXVF64GER: |
3541 | case PPC::PMXVF64GERW: { |
3542 | // op: AT |
3543 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3544 | op &= UINT64_C(7); |
3545 | op <<= 23; |
3546 | Value |= op; |
3547 | // op: XA |
3548 | op = getVSRpEvenEncoding(MI, OpNo: 1, Fixups, STI); |
3549 | Value |= (op & UINT64_C(31)) << 16; |
3550 | Value |= (op & UINT64_C(32)) >> 3; |
3551 | // op: XB |
3552 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3553 | Value |= (op & UINT64_C(31)) << 11; |
3554 | Value |= (op & UINT64_C(32)) >> 4; |
3555 | // op: XMSK |
3556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3557 | op &= UINT64_C(15); |
3558 | op <<= 36; |
3559 | Value |= op; |
3560 | // op: YMSK |
3561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3562 | op &= UINT64_C(3); |
3563 | op <<= 34; |
3564 | Value |= op; |
3565 | break; |
3566 | } |
3567 | case PPC::XVF64GERNN: |
3568 | case PPC::XVF64GERNP: |
3569 | case PPC::XVF64GERPN: |
3570 | case PPC::XVF64GERPP: |
3571 | case PPC::XVF64GERWNN: |
3572 | case PPC::XVF64GERWNP: |
3573 | case PPC::XVF64GERWPN: |
3574 | case PPC::XVF64GERWPP: { |
3575 | // op: AT |
3576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3577 | op &= UINT64_C(7); |
3578 | op <<= 23; |
3579 | Value |= op; |
3580 | // op: XA |
3581 | op = getVSRpEvenEncoding(MI, OpNo: 2, Fixups, STI); |
3582 | Value |= (op & UINT64_C(31)) << 16; |
3583 | Value |= (op & UINT64_C(32)) >> 3; |
3584 | // op: XB |
3585 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3586 | Value |= (op & UINT64_C(31)) << 11; |
3587 | Value |= (op & UINT64_C(32)) >> 4; |
3588 | break; |
3589 | } |
3590 | case PPC::PMXVF64GERNN: |
3591 | case PPC::PMXVF64GERNP: |
3592 | case PPC::PMXVF64GERPN: |
3593 | case PPC::PMXVF64GERPP: |
3594 | case PPC::PMXVF64GERWNN: |
3595 | case PPC::PMXVF64GERWNP: |
3596 | case PPC::PMXVF64GERWPN: |
3597 | case PPC::PMXVF64GERWPP: { |
3598 | // op: AT |
3599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3600 | op &= UINT64_C(7); |
3601 | op <<= 23; |
3602 | Value |= op; |
3603 | // op: XA |
3604 | op = getVSRpEvenEncoding(MI, OpNo: 2, Fixups, STI); |
3605 | Value |= (op & UINT64_C(31)) << 16; |
3606 | Value |= (op & UINT64_C(32)) >> 3; |
3607 | // op: XB |
3608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3609 | Value |= (op & UINT64_C(31)) << 11; |
3610 | Value |= (op & UINT64_C(32)) >> 4; |
3611 | // op: XMSK |
3612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
3613 | op &= UINT64_C(15); |
3614 | op <<= 36; |
3615 | Value |= op; |
3616 | // op: YMSK |
3617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
3618 | op &= UINT64_C(3); |
3619 | op <<= 34; |
3620 | Value |= op; |
3621 | break; |
3622 | } |
3623 | case PPC::DMXXINSTFDMR512: |
3624 | case PPC::DMXXINSTFDMR512_HI: { |
3625 | // op: AT |
3626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3627 | op &= UINT64_C(7); |
3628 | op <<= 23; |
3629 | Value |= op; |
3630 | // op: XAp |
3631 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3632 | Value |= (op & UINT64_C(15)) << 17; |
3633 | Value |= (op & UINT64_C(16)) >> 2; |
3634 | // op: XBp |
3635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3636 | Value |= (op & UINT64_C(15)) << 12; |
3637 | Value |= (op & UINT64_C(16)) >> 3; |
3638 | break; |
3639 | } |
3640 | case PPC::DMXXINSTFDMR256: { |
3641 | // op: AT |
3642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3643 | op &= UINT64_C(7); |
3644 | op <<= 23; |
3645 | Value |= op; |
3646 | // op: XBp |
3647 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3648 | Value |= (op & UINT64_C(15)) << 12; |
3649 | Value |= (op & UINT64_C(16)) >> 3; |
3650 | // op: P |
3651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3652 | Value |= (op & UINT64_C(1)) << 16; |
3653 | Value |= (op & UINT64_C(2)) << 10; |
3654 | break; |
3655 | } |
3656 | case PPC::XXMFACC: |
3657 | case PPC::XXMFACCW: { |
3658 | // op: AT |
3659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3660 | op &= UINT64_C(7); |
3661 | op <<= 23; |
3662 | Value |= op; |
3663 | break; |
3664 | } |
3665 | case PPC::DMXXEXTFDMR256: { |
3666 | // op: AT |
3667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3668 | op &= UINT64_C(7); |
3669 | op <<= 23; |
3670 | Value |= op; |
3671 | // op: XBp |
3672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3673 | Value |= (op & UINT64_C(15)) << 12; |
3674 | Value |= (op & UINT64_C(16)) >> 3; |
3675 | // op: P |
3676 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3677 | Value |= (op & UINT64_C(1)) << 16; |
3678 | Value |= (op & UINT64_C(2)) << 10; |
3679 | break; |
3680 | } |
3681 | case PPC::DMXXEXTFDMR512: |
3682 | case PPC::DMXXEXTFDMR512_HI: { |
3683 | // op: AT |
3684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3685 | op &= UINT64_C(7); |
3686 | op <<= 23; |
3687 | Value |= op; |
3688 | // op: XAp |
3689 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3690 | Value |= (op & UINT64_C(15)) << 17; |
3691 | Value |= (op & UINT64_C(16)) >> 2; |
3692 | // op: XBp |
3693 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3694 | Value |= (op & UINT64_C(15)) << 12; |
3695 | Value |= (op & UINT64_C(16)) >> 3; |
3696 | break; |
3697 | } |
3698 | case PPC::BDNZA: |
3699 | case PPC::BDNZAm: |
3700 | case PPC::BDNZAp: |
3701 | case PPC::BDNZLA: |
3702 | case PPC::BDNZLAm: |
3703 | case PPC::BDNZLAp: |
3704 | case PPC::BDZA: |
3705 | case PPC::BDZAm: |
3706 | case PPC::BDZAp: |
3707 | case PPC::BDZLA: |
3708 | case PPC::BDZLAm: |
3709 | case PPC::BDZLAp: { |
3710 | // op: BD |
3711 | op = getAbsCondBrEncoding(MI, OpNo: 0, Fixups, STI); |
3712 | op &= UINT64_C(16383); |
3713 | op <<= 2; |
3714 | Value |= op; |
3715 | break; |
3716 | } |
3717 | case PPC::BCLalways: |
3718 | case PPC::BDNZ: |
3719 | case PPC::BDNZ8: |
3720 | case PPC::BDNZL: |
3721 | case PPC::BDNZLm: |
3722 | case PPC::BDNZLp: |
3723 | case PPC::BDNZm: |
3724 | case PPC::BDNZp: |
3725 | case PPC::BDZ: |
3726 | case PPC::BDZ8: |
3727 | case PPC::BDZL: |
3728 | case PPC::BDZLm: |
3729 | case PPC::BDZLp: |
3730 | case PPC::BDZm: |
3731 | case PPC::BDZp: { |
3732 | // op: BD |
3733 | op = getCondBrEncoding(MI, OpNo: 0, Fixups, STI); |
3734 | op &= UINT64_C(16383); |
3735 | op <<= 2; |
3736 | Value |= op; |
3737 | break; |
3738 | } |
3739 | case PPC::MCRXRX: |
3740 | case PPC::TCHECK: { |
3741 | // op: BF |
3742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3743 | op &= UINT64_C(7); |
3744 | op <<= 23; |
3745 | Value |= op; |
3746 | break; |
3747 | } |
3748 | case PPC::MCRF: |
3749 | case PPC::MCRFS: { |
3750 | // op: BF |
3751 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3752 | op &= UINT64_C(7); |
3753 | op <<= 23; |
3754 | Value |= op; |
3755 | // op: BFA |
3756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3757 | op &= UINT64_C(7); |
3758 | op <<= 18; |
3759 | Value |= op; |
3760 | break; |
3761 | } |
3762 | case PPC::XSTSTDCQP: { |
3763 | // op: BF |
3764 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3765 | op &= UINT64_C(7); |
3766 | op <<= 23; |
3767 | Value |= op; |
3768 | // op: DCMX |
3769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3770 | op &= UINT64_C(127); |
3771 | op <<= 16; |
3772 | Value |= op; |
3773 | // op: VB |
3774 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3775 | op &= UINT64_C(31); |
3776 | op <<= 11; |
3777 | Value |= op; |
3778 | break; |
3779 | } |
3780 | case PPC::XSTSTDCDP: |
3781 | case PPC::XSTSTDCSP: { |
3782 | // op: BF |
3783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3784 | op &= UINT64_C(7); |
3785 | op <<= 23; |
3786 | Value |= op; |
3787 | // op: DCMX |
3788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3789 | op &= UINT64_C(127); |
3790 | op <<= 16; |
3791 | Value |= op; |
3792 | // op: XB |
3793 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3794 | Value |= (op & UINT64_C(31)) << 11; |
3795 | Value |= (op & UINT64_C(32)) >> 4; |
3796 | break; |
3797 | } |
3798 | case PPC::DTSTDC: |
3799 | case PPC::DTSTDCQ: |
3800 | case PPC::DTSTDG: |
3801 | case PPC::DTSTDGQ: { |
3802 | // op: BF |
3803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3804 | op &= UINT64_C(7); |
3805 | op <<= 23; |
3806 | Value |= op; |
3807 | // op: FRA |
3808 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3809 | op &= UINT64_C(31); |
3810 | op <<= 16; |
3811 | Value |= op; |
3812 | // op: DCM |
3813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3814 | op &= UINT64_C(63); |
3815 | op <<= 10; |
3816 | Value |= op; |
3817 | break; |
3818 | } |
3819 | case PPC::CMPRB: |
3820 | case PPC::CMPRB8: { |
3821 | // op: BF |
3822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3823 | op &= UINT64_C(7); |
3824 | op <<= 23; |
3825 | Value |= op; |
3826 | // op: L |
3827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3828 | op &= UINT64_C(1); |
3829 | op <<= 21; |
3830 | Value |= op; |
3831 | // op: RA |
3832 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3833 | op &= UINT64_C(31); |
3834 | op <<= 16; |
3835 | Value |= op; |
3836 | // op: RB |
3837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
3838 | op &= UINT64_C(31); |
3839 | op <<= 11; |
3840 | Value |= op; |
3841 | break; |
3842 | } |
3843 | case PPC::CMPDI: |
3844 | case PPC::CMPLDI: |
3845 | case PPC::CMPLWI: |
3846 | case PPC::CMPWI: { |
3847 | // op: BF |
3848 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3849 | op &= UINT64_C(7); |
3850 | op <<= 23; |
3851 | Value |= op; |
3852 | // op: RA |
3853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3854 | op &= UINT64_C(31); |
3855 | op <<= 16; |
3856 | Value |= op; |
3857 | // op: D |
3858 | op = getImm16Encoding(MI, OpNo: 2, Fixups, STI); |
3859 | op &= UINT64_C(65535); |
3860 | Value |= op; |
3861 | break; |
3862 | } |
3863 | case PPC::CMPD: |
3864 | case PPC::CMPEQB: |
3865 | case PPC::CMPLD: |
3866 | case PPC::CMPLW: |
3867 | case PPC::CMPW: |
3868 | case PPC::DCMPO: |
3869 | case PPC::DCMPOQ: |
3870 | case PPC::DCMPU: |
3871 | case PPC::DCMPUQ: |
3872 | case PPC::DTSTEX: |
3873 | case PPC::DTSTEXQ: |
3874 | case PPC::DTSTSF: |
3875 | case PPC::DTSTSFQ: |
3876 | case PPC::FCMPOD: |
3877 | case PPC::FCMPOS: |
3878 | case PPC::FCMPUD: |
3879 | case PPC::FCMPUS: |
3880 | case PPC::FTDIV: |
3881 | case PPC::XSCMPEXPQP: |
3882 | case PPC::XSCMPOQP: |
3883 | case PPC::XSCMPUQP: { |
3884 | // op: BF |
3885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3886 | op &= UINT64_C(7); |
3887 | op <<= 23; |
3888 | Value |= op; |
3889 | // op: RA |
3890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3891 | op &= UINT64_C(31); |
3892 | op <<= 16; |
3893 | Value |= op; |
3894 | // op: RB |
3895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3896 | op &= UINT64_C(31); |
3897 | op <<= 11; |
3898 | Value |= op; |
3899 | break; |
3900 | } |
3901 | case PPC::FTSQRT: { |
3902 | // op: BF |
3903 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3904 | op &= UINT64_C(7); |
3905 | op <<= 23; |
3906 | Value |= op; |
3907 | // op: RB |
3908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3909 | op &= UINT64_C(31); |
3910 | op <<= 11; |
3911 | Value |= op; |
3912 | break; |
3913 | } |
3914 | case PPC::MTFSFIb: { |
3915 | // op: BF |
3916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3917 | op &= UINT64_C(7); |
3918 | op <<= 23; |
3919 | Value |= op; |
3920 | // op: U |
3921 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3922 | op &= UINT64_C(15); |
3923 | op <<= 12; |
3924 | Value |= op; |
3925 | break; |
3926 | } |
3927 | case PPC::DTSTSFI: |
3928 | case PPC::DTSTSFIQ: { |
3929 | // op: BF |
3930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3931 | op &= UINT64_C(7); |
3932 | op <<= 23; |
3933 | Value |= op; |
3934 | // op: UIM |
3935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3936 | op &= UINT64_C(63); |
3937 | op <<= 16; |
3938 | Value |= op; |
3939 | // op: FRB |
3940 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3941 | op &= UINT64_C(31); |
3942 | op <<= 11; |
3943 | Value |= op; |
3944 | break; |
3945 | } |
3946 | case PPC::VCMPSQ: |
3947 | case PPC::VCMPUQ: { |
3948 | // op: BF |
3949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3950 | op &= UINT64_C(7); |
3951 | op <<= 23; |
3952 | Value |= op; |
3953 | // op: VA |
3954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3955 | op &= UINT64_C(31); |
3956 | op <<= 16; |
3957 | Value |= op; |
3958 | // op: VB |
3959 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3960 | op &= UINT64_C(31); |
3961 | op <<= 11; |
3962 | Value |= op; |
3963 | break; |
3964 | } |
3965 | case PPC::MTFSFI: |
3966 | case PPC::MTFSFI_rec: { |
3967 | // op: BF |
3968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3969 | op &= UINT64_C(7); |
3970 | op <<= 23; |
3971 | Value |= op; |
3972 | // op: W |
3973 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
3974 | op &= UINT64_C(1); |
3975 | op <<= 16; |
3976 | Value |= op; |
3977 | // op: U |
3978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3979 | op &= UINT64_C(15); |
3980 | op <<= 12; |
3981 | Value |= op; |
3982 | break; |
3983 | } |
3984 | case PPC::XVTLSBB: { |
3985 | // op: BF |
3986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
3987 | op &= UINT64_C(7); |
3988 | op <<= 23; |
3989 | Value |= op; |
3990 | // op: XB |
3991 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
3992 | Value |= (op & UINT64_C(31)) << 11; |
3993 | Value |= (op & UINT64_C(32)) >> 4; |
3994 | break; |
3995 | } |
3996 | case PPC::BCCTR: |
3997 | case PPC::BCCTR8: |
3998 | case PPC::BCCTR8n: |
3999 | case PPC::BCCTRL: |
4000 | case PPC::BCCTRL8: |
4001 | case PPC::BCCTRL8n: |
4002 | case PPC::BCCTRLn: |
4003 | case PPC::BCCTRn: |
4004 | case PPC::BCLR: |
4005 | case PPC::BCLRL: |
4006 | case PPC::BCLRLn: |
4007 | case PPC::BCLRn: { |
4008 | // op: BI |
4009 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4010 | op &= UINT64_C(31); |
4011 | op <<= 16; |
4012 | Value |= op; |
4013 | break; |
4014 | } |
4015 | case PPC::BC: |
4016 | case PPC::BCL: |
4017 | case PPC::BCLn: |
4018 | case PPC::BCn: { |
4019 | // op: BI |
4020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4021 | op &= UINT64_C(31); |
4022 | op <<= 16; |
4023 | Value |= op; |
4024 | // op: BD |
4025 | op = getCondBrEncoding(MI, OpNo: 1, Fixups, STI); |
4026 | op &= UINT64_C(16383); |
4027 | op <<= 2; |
4028 | Value |= op; |
4029 | break; |
4030 | } |
4031 | case PPC::BCCCTR: |
4032 | case PPC::BCCCTR8: |
4033 | case PPC::BCCCTRL: |
4034 | case PPC::BCCCTRL8: |
4035 | case PPC::BCCLR: |
4036 | case PPC::BCCLRL: { |
4037 | // op: BIBO |
4038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4039 | Value |= (op & UINT64_C(31)) << 21; |
4040 | Value |= (op & UINT64_C(96)) << 11; |
4041 | // op: CR |
4042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4043 | op &= UINT64_C(7); |
4044 | op <<= 18; |
4045 | Value |= op; |
4046 | break; |
4047 | } |
4048 | case PPC::BCCA: |
4049 | case PPC::BCCLA: { |
4050 | // op: BIBO |
4051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4052 | Value |= (op & UINT64_C(31)) << 21; |
4053 | Value |= (op & UINT64_C(96)) << 11; |
4054 | // op: CR |
4055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4056 | op &= UINT64_C(7); |
4057 | op <<= 18; |
4058 | Value |= op; |
4059 | // op: BD |
4060 | op = getAbsCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
4061 | op &= UINT64_C(16383); |
4062 | op <<= 2; |
4063 | Value |= op; |
4064 | break; |
4065 | } |
4066 | case PPC::BCC: |
4067 | case PPC::BCCL: |
4068 | case PPC::CTRL_DEP: { |
4069 | // op: BIBO |
4070 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4071 | Value |= (op & UINT64_C(31)) << 21; |
4072 | Value |= (op & UINT64_C(96)) << 11; |
4073 | // op: CR |
4074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4075 | op &= UINT64_C(7); |
4076 | op <<= 18; |
4077 | Value |= op; |
4078 | // op: BD |
4079 | op = getCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
4080 | op &= UINT64_C(16383); |
4081 | op <<= 2; |
4082 | Value |= op; |
4083 | break; |
4084 | } |
4085 | case PPC::gBCAat: |
4086 | case PPC::gBCLAat: { |
4087 | // op: BO |
4088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4089 | op &= UINT64_C(28); |
4090 | op <<= 21; |
4091 | Value |= op; |
4092 | // op: at |
4093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4094 | op &= UINT64_C(3); |
4095 | op <<= 21; |
4096 | Value |= op; |
4097 | // op: BI |
4098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4099 | op &= UINT64_C(31); |
4100 | op <<= 16; |
4101 | Value |= op; |
4102 | // op: BD |
4103 | op = getAbsCondBrEncoding(MI, OpNo: 3, Fixups, STI); |
4104 | op &= UINT64_C(16383); |
4105 | op <<= 2; |
4106 | Value |= op; |
4107 | break; |
4108 | } |
4109 | case PPC::gBCLat: |
4110 | case PPC::gBCat: { |
4111 | // op: BO |
4112 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4113 | op &= UINT64_C(28); |
4114 | op <<= 21; |
4115 | Value |= op; |
4116 | // op: at |
4117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4118 | op &= UINT64_C(3); |
4119 | op <<= 21; |
4120 | Value |= op; |
4121 | // op: BI |
4122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4123 | op &= UINT64_C(31); |
4124 | op <<= 16; |
4125 | Value |= op; |
4126 | // op: BD |
4127 | op = getCondBrEncoding(MI, OpNo: 3, Fixups, STI); |
4128 | op &= UINT64_C(16383); |
4129 | op <<= 2; |
4130 | Value |= op; |
4131 | break; |
4132 | } |
4133 | case PPC::gBCA: |
4134 | case PPC::gBCLA: { |
4135 | // op: BO |
4136 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4137 | op &= UINT64_C(31); |
4138 | op <<= 21; |
4139 | Value |= op; |
4140 | // op: BI |
4141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4142 | op &= UINT64_C(31); |
4143 | op <<= 16; |
4144 | Value |= op; |
4145 | // op: BD |
4146 | op = getAbsCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
4147 | op &= UINT64_C(16383); |
4148 | op <<= 2; |
4149 | Value |= op; |
4150 | break; |
4151 | } |
4152 | case PPC::gBC: |
4153 | case PPC::gBCL: { |
4154 | // op: BO |
4155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4156 | op &= UINT64_C(31); |
4157 | op <<= 21; |
4158 | Value |= op; |
4159 | // op: BI |
4160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4161 | op &= UINT64_C(31); |
4162 | op <<= 16; |
4163 | Value |= op; |
4164 | // op: BD |
4165 | op = getCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
4166 | op &= UINT64_C(16383); |
4167 | op <<= 2; |
4168 | Value |= op; |
4169 | break; |
4170 | } |
4171 | case PPC::gBCCTR: |
4172 | case PPC::gBCCTRL: |
4173 | case PPC::gBCLR: |
4174 | case PPC::gBCLRL: { |
4175 | // op: BO |
4176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4177 | op &= UINT64_C(31); |
4178 | op <<= 21; |
4179 | Value |= op; |
4180 | // op: BI |
4181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4182 | op &= UINT64_C(31); |
4183 | op <<= 16; |
4184 | Value |= op; |
4185 | // op: BH |
4186 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4187 | op &= UINT64_C(3); |
4188 | op <<= 11; |
4189 | Value |= op; |
4190 | break; |
4191 | } |
4192 | case PPC::XSCMPEXPDP: |
4193 | case PPC::XSCMPODP: |
4194 | case PPC::XSCMPUDP: |
4195 | case PPC::XSTDIVDP: |
4196 | case PPC::XVTDIVDP: |
4197 | case PPC::XVTDIVSP: { |
4198 | // op: CR |
4199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4200 | op &= UINT64_C(7); |
4201 | op <<= 23; |
4202 | Value |= op; |
4203 | // op: XA |
4204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4205 | Value |= (op & UINT64_C(31)) << 16; |
4206 | Value |= (op & UINT64_C(32)) >> 3; |
4207 | // op: XB |
4208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4209 | Value |= (op & UINT64_C(31)) << 11; |
4210 | Value |= (op & UINT64_C(32)) >> 4; |
4211 | break; |
4212 | } |
4213 | case PPC::XSTSQRTDP: |
4214 | case PPC::XVTSQRTDP: |
4215 | case PPC::XVTSQRTSP: { |
4216 | // op: CR |
4217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4218 | op &= UINT64_C(7); |
4219 | op <<= 23; |
4220 | Value |= op; |
4221 | // op: XB |
4222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4223 | Value |= (op & UINT64_C(31)) << 11; |
4224 | Value |= (op & UINT64_C(32)) >> 4; |
4225 | break; |
4226 | } |
4227 | case PPC::CRSET: |
4228 | case PPC::CRUNSET: { |
4229 | // op: CRD |
4230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4231 | Value |= (op & UINT64_C(31)) << 21; |
4232 | Value |= (op & UINT64_C(31)) << 16; |
4233 | Value |= (op & UINT64_C(31)) << 11; |
4234 | break; |
4235 | } |
4236 | case PPC::CRNOT: { |
4237 | // op: CRD |
4238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4239 | op &= UINT64_C(31); |
4240 | op <<= 21; |
4241 | Value |= op; |
4242 | // op: CRA |
4243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4244 | Value |= (op & UINT64_C(31)) << 16; |
4245 | Value |= (op & UINT64_C(31)) << 11; |
4246 | break; |
4247 | } |
4248 | case PPC::CRAND: |
4249 | case PPC::CRANDC: |
4250 | case PPC::CREQV: |
4251 | case PPC::CRNAND: |
4252 | case PPC::CRNOR: |
4253 | case PPC::CROR: |
4254 | case PPC::CRORC: |
4255 | case PPC::CRXOR: { |
4256 | // op: CRD |
4257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4258 | op &= UINT64_C(31); |
4259 | op <<= 21; |
4260 | Value |= op; |
4261 | // op: CRA |
4262 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4263 | op &= UINT64_C(31); |
4264 | op <<= 16; |
4265 | Value |= op; |
4266 | // op: CRB |
4267 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4268 | op &= UINT64_C(31); |
4269 | op <<= 11; |
4270 | Value |= op; |
4271 | break; |
4272 | } |
4273 | case PPC::ICBLC: |
4274 | case PPC::ICBLQ: |
4275 | case PPC::ICBT: |
4276 | case PPC::ICBTLS: { |
4277 | // op: CT |
4278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4279 | op &= UINT64_C(15); |
4280 | op <<= 21; |
4281 | Value |= op; |
4282 | // op: RA |
4283 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4284 | op &= UINT64_C(31); |
4285 | op <<= 16; |
4286 | Value |= op; |
4287 | // op: RB |
4288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4289 | op &= UINT64_C(31); |
4290 | op <<= 11; |
4291 | Value |= op; |
4292 | break; |
4293 | } |
4294 | case PPC::WRTEEI: { |
4295 | // op: E |
4296 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4297 | op &= UINT64_C(1); |
4298 | op <<= 15; |
4299 | Value |= op; |
4300 | break; |
4301 | } |
4302 | case PPC::MTFSFb: { |
4303 | // op: FM |
4304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4305 | op &= UINT64_C(255); |
4306 | op <<= 17; |
4307 | Value |= op; |
4308 | // op: RT |
4309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4310 | op &= UINT64_C(31); |
4311 | op <<= 11; |
4312 | Value |= op; |
4313 | break; |
4314 | } |
4315 | case PPC::MTFSB0: |
4316 | case PPC::MTFSB1: { |
4317 | // op: FM |
4318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4319 | op &= UINT64_C(31); |
4320 | op <<= 21; |
4321 | Value |= op; |
4322 | break; |
4323 | } |
4324 | case PPC::FADD: |
4325 | case PPC::FADDS: |
4326 | case PPC::FADDS_rec: |
4327 | case PPC::FADD_rec: |
4328 | case PPC::FDIV: |
4329 | case PPC::FDIVS: |
4330 | case PPC::FDIVS_rec: |
4331 | case PPC::FDIV_rec: |
4332 | case PPC::FSUB: |
4333 | case PPC::FSUBS: |
4334 | case PPC::FSUBS_rec: |
4335 | case PPC::FSUB_rec: |
4336 | case PPC::XSIEXPQP: { |
4337 | // op: FRT |
4338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4339 | op &= UINT64_C(31); |
4340 | op <<= 21; |
4341 | Value |= op; |
4342 | // op: FRA |
4343 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4344 | op &= UINT64_C(31); |
4345 | op <<= 16; |
4346 | Value |= op; |
4347 | // op: FRB |
4348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4349 | op &= UINT64_C(31); |
4350 | op <<= 11; |
4351 | Value |= op; |
4352 | break; |
4353 | } |
4354 | case PPC::DQUA: |
4355 | case PPC::DQUAQ: |
4356 | case PPC::DQUAQ_rec: |
4357 | case PPC::DQUA_rec: |
4358 | case PPC::DRRND: |
4359 | case PPC::DRRNDQ: |
4360 | case PPC::DRRNDQ_rec: |
4361 | case PPC::DRRND_rec: { |
4362 | // op: FRT |
4363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4364 | op &= UINT64_C(31); |
4365 | op <<= 21; |
4366 | Value |= op; |
4367 | // op: FRA |
4368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4369 | op &= UINT64_C(31); |
4370 | op <<= 16; |
4371 | Value |= op; |
4372 | // op: FRB |
4373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4374 | op &= UINT64_C(31); |
4375 | op <<= 11; |
4376 | Value |= op; |
4377 | // op: RMC |
4378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4379 | op &= UINT64_C(3); |
4380 | op <<= 9; |
4381 | Value |= op; |
4382 | break; |
4383 | } |
4384 | case PPC::FMUL: |
4385 | case PPC::FMULS: |
4386 | case PPC::FMULS_rec: |
4387 | case PPC::FMUL_rec: { |
4388 | // op: FRT |
4389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4390 | op &= UINT64_C(31); |
4391 | op <<= 21; |
4392 | Value |= op; |
4393 | // op: FRA |
4394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4395 | op &= UINT64_C(31); |
4396 | op <<= 16; |
4397 | Value |= op; |
4398 | // op: FRC |
4399 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4400 | op &= UINT64_C(31); |
4401 | op <<= 6; |
4402 | Value |= op; |
4403 | break; |
4404 | } |
4405 | case PPC::FMADD: |
4406 | case PPC::FMADDS: |
4407 | case PPC::FMADDS_rec: |
4408 | case PPC::FMADD_rec: |
4409 | case PPC::FMSUB: |
4410 | case PPC::FMSUBS: |
4411 | case PPC::FMSUBS_rec: |
4412 | case PPC::FMSUB_rec: |
4413 | case PPC::FNMADD: |
4414 | case PPC::FNMADDS: |
4415 | case PPC::FNMADDS_rec: |
4416 | case PPC::FNMADD_rec: |
4417 | case PPC::FNMSUB: |
4418 | case PPC::FNMSUBS: |
4419 | case PPC::FNMSUBS_rec: |
4420 | case PPC::FNMSUB_rec: |
4421 | case PPC::FSELD: |
4422 | case PPC::FSELD_rec: |
4423 | case PPC::FSELS: |
4424 | case PPC::FSELS_rec: { |
4425 | // op: FRT |
4426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4427 | op &= UINT64_C(31); |
4428 | op <<= 21; |
4429 | Value |= op; |
4430 | // op: FRA |
4431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4432 | op &= UINT64_C(31); |
4433 | op <<= 16; |
4434 | Value |= op; |
4435 | // op: FRC |
4436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4437 | op &= UINT64_C(31); |
4438 | op <<= 6; |
4439 | Value |= op; |
4440 | // op: FRB |
4441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4442 | op &= UINT64_C(31); |
4443 | op <<= 11; |
4444 | Value |= op; |
4445 | break; |
4446 | } |
4447 | case PPC::DSCLI: |
4448 | case PPC::DSCLIQ: |
4449 | case PPC::DSCLIQ_rec: |
4450 | case PPC::DSCLI_rec: |
4451 | case PPC::DSCRI: |
4452 | case PPC::DSCRIQ: |
4453 | case PPC::DSCRIQ_rec: |
4454 | case PPC::DSCRI_rec: { |
4455 | // op: FRT |
4456 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4457 | op &= UINT64_C(31); |
4458 | op <<= 21; |
4459 | Value |= op; |
4460 | // op: FRA |
4461 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4462 | op &= UINT64_C(31); |
4463 | op <<= 16; |
4464 | Value |= op; |
4465 | // op: SH |
4466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4467 | op &= UINT64_C(63); |
4468 | op <<= 10; |
4469 | Value |= op; |
4470 | break; |
4471 | } |
4472 | case PPC::DQUAI: |
4473 | case PPC::DQUAIQ: |
4474 | case PPC::DQUAIQ_rec: |
4475 | case PPC::DQUAI_rec: { |
4476 | // op: FRT |
4477 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4478 | op &= UINT64_C(31); |
4479 | op <<= 21; |
4480 | Value |= op; |
4481 | // op: FRB |
4482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4483 | op &= UINT64_C(31); |
4484 | op <<= 11; |
4485 | Value |= op; |
4486 | // op: RMC |
4487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4488 | op &= UINT64_C(3); |
4489 | op <<= 9; |
4490 | Value |= op; |
4491 | // op: TE |
4492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4493 | op &= UINT64_C(31); |
4494 | op <<= 16; |
4495 | Value |= op; |
4496 | break; |
4497 | } |
4498 | case PPC::DRINTN: |
4499 | case PPC::DRINTNQ: |
4500 | case PPC::DRINTNQ_rec: |
4501 | case PPC::DRINTN_rec: |
4502 | case PPC::DRINTX: |
4503 | case PPC::DRINTXQ: |
4504 | case PPC::DRINTXQ_rec: |
4505 | case PPC::DRINTX_rec: { |
4506 | // op: FRT |
4507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4508 | op &= UINT64_C(31); |
4509 | op <<= 21; |
4510 | Value |= op; |
4511 | // op: R |
4512 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4513 | op &= UINT64_C(1); |
4514 | op <<= 16; |
4515 | Value |= op; |
4516 | // op: FRB |
4517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4518 | op &= UINT64_C(31); |
4519 | op <<= 11; |
4520 | Value |= op; |
4521 | // op: RMC |
4522 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4523 | op &= UINT64_C(3); |
4524 | op <<= 9; |
4525 | Value |= op; |
4526 | break; |
4527 | } |
4528 | case PPC::MTCRF: |
4529 | case PPC::MTCRF8: { |
4530 | // op: FXM |
4531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4532 | op &= UINT64_C(255); |
4533 | op <<= 12; |
4534 | Value |= op; |
4535 | // op: RST |
4536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4537 | op &= UINT64_C(31); |
4538 | op <<= 21; |
4539 | Value |= op; |
4540 | break; |
4541 | } |
4542 | case PPC::TSR: { |
4543 | // op: L |
4544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4545 | op &= UINT64_C(1); |
4546 | op <<= 21; |
4547 | Value |= op; |
4548 | break; |
4549 | } |
4550 | case PPC::SYNC: |
4551 | case PPC::WAIT: { |
4552 | // op: L |
4553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4554 | op &= UINT64_C(3); |
4555 | op <<= 21; |
4556 | Value |= op; |
4557 | break; |
4558 | } |
4559 | case PPC::WAITP10: { |
4560 | // op: L |
4561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4562 | op &= UINT64_C(3); |
4563 | op <<= 21; |
4564 | Value |= op; |
4565 | // op: PL |
4566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4567 | op &= UINT64_C(3); |
4568 | op <<= 16; |
4569 | Value |= op; |
4570 | break; |
4571 | } |
4572 | case PPC::SYNCP10: { |
4573 | // op: L |
4574 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4575 | op &= UINT64_C(7); |
4576 | op <<= 21; |
4577 | Value |= op; |
4578 | // op: SC |
4579 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4580 | op &= UINT64_C(3); |
4581 | op <<= 16; |
4582 | Value |= op; |
4583 | break; |
4584 | } |
4585 | case PPC::CP_PASTE8_rec: |
4586 | case PPC::CP_PASTE_rec: { |
4587 | // op: L |
4588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4589 | op &= UINT64_C(1); |
4590 | op <<= 21; |
4591 | Value |= op; |
4592 | // op: RA |
4593 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4594 | op &= UINT64_C(31); |
4595 | op <<= 16; |
4596 | Value |= op; |
4597 | // op: RB |
4598 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4599 | op &= UINT64_C(31); |
4600 | op <<= 11; |
4601 | Value |= op; |
4602 | break; |
4603 | } |
4604 | case PPC::MTFSF: |
4605 | case PPC::MTFSF_rec: { |
4606 | // op: L |
4607 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4608 | op &= UINT64_C(1); |
4609 | op <<= 25; |
4610 | Value |= op; |
4611 | // op: FLM |
4612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4613 | op &= UINT64_C(255); |
4614 | op <<= 17; |
4615 | Value |= op; |
4616 | // op: W |
4617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4618 | op &= UINT64_C(1); |
4619 | op <<= 16; |
4620 | Value |= op; |
4621 | // op: FRB |
4622 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4623 | op &= UINT64_C(31); |
4624 | op <<= 11; |
4625 | Value |= op; |
4626 | break; |
4627 | } |
4628 | case PPC::SC: |
4629 | case PPC::SCV: { |
4630 | // op: LEV |
4631 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4632 | op &= UINT64_C(127); |
4633 | op <<= 5; |
4634 | Value |= op; |
4635 | break; |
4636 | } |
4637 | case PPC::BA: |
4638 | case PPC::BLA: |
4639 | case PPC::BLA8: |
4640 | case PPC::BLA8_RM: |
4641 | case PPC::BLA_RM: |
4642 | case PPC::TAILBA: |
4643 | case PPC::TAILBA8: { |
4644 | // op: LI |
4645 | op = getAbsDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
4646 | op &= UINT64_C(16777215); |
4647 | op <<= 2; |
4648 | Value |= op; |
4649 | break; |
4650 | } |
4651 | case PPC::BLA8_NOP: |
4652 | case PPC::BLA8_NOP_RM: { |
4653 | // op: LI |
4654 | op = getAbsDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
4655 | op &= UINT64_C(16777215); |
4656 | op <<= 34; |
4657 | Value |= op; |
4658 | break; |
4659 | } |
4660 | case PPC::B: |
4661 | case PPC::BL: |
4662 | case PPC::BL8: |
4663 | case PPC::BL8_NOTOC: |
4664 | case PPC::BL8_NOTOC_RM: |
4665 | case PPC::BL8_RM: |
4666 | case PPC::BL_RM: |
4667 | case PPC::TAILB: |
4668 | case PPC::TAILB8: { |
4669 | // op: LI |
4670 | op = getDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
4671 | op &= UINT64_C(16777215); |
4672 | op <<= 2; |
4673 | Value |= op; |
4674 | break; |
4675 | } |
4676 | case PPC::BL8_NOP: |
4677 | case PPC::BL8_NOP_RM: |
4678 | case PPC::BL_NOP: |
4679 | case PPC::BL_NOP_RM: { |
4680 | // op: LI |
4681 | op = getDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
4682 | op &= UINT64_C(16777215); |
4683 | op <<= 34; |
4684 | Value |= op; |
4685 | break; |
4686 | } |
4687 | case PPC::BL8_NOTOC_TLS: |
4688 | case PPC::BL8_TLS: |
4689 | case PPC::BL8_TLS_: |
4690 | case PPC::BL_TLS: { |
4691 | // op: LI |
4692 | op = getTLSCallEncoding(MI, OpNo: 0, Fixups, STI); |
4693 | op &= UINT64_C(16777215); |
4694 | op <<= 2; |
4695 | Value |= op; |
4696 | break; |
4697 | } |
4698 | case PPC::BL8_NOP_TLS: { |
4699 | // op: LI |
4700 | op = getTLSCallEncoding(MI, OpNo: 0, Fixups, STI); |
4701 | op &= UINT64_C(16777215); |
4702 | op <<= 34; |
4703 | Value |= op; |
4704 | break; |
4705 | } |
4706 | case PPC::MBAR: { |
4707 | // op: MO |
4708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4709 | op &= UINT64_C(31); |
4710 | op <<= 21; |
4711 | Value |= op; |
4712 | break; |
4713 | } |
4714 | case PPC::TBEGIN: { |
4715 | // op: R |
4716 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4717 | op &= UINT64_C(1); |
4718 | op <<= 21; |
4719 | Value |= op; |
4720 | break; |
4721 | } |
4722 | case PPC::TABORT: |
4723 | case PPC::TRECLAIM: { |
4724 | // op: RA |
4725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4726 | op &= UINT64_C(31); |
4727 | op <<= 16; |
4728 | Value |= op; |
4729 | break; |
4730 | } |
4731 | case PPC::CP_COPY: |
4732 | case PPC::CP_COPY8: |
4733 | case PPC::DCBA: |
4734 | case PPC::DCBFEP: |
4735 | case PPC::DCBI: |
4736 | case PPC::DCBST: |
4737 | case PPC::DCBSTEP: |
4738 | case PPC::DCBZ: |
4739 | case PPC::DCBZEP: |
4740 | case PPC::DCBZL: |
4741 | case PPC::DCBZLEP: |
4742 | case PPC::DCCCI: |
4743 | case PPC::ICBI: |
4744 | case PPC::ICBIEP: |
4745 | case PPC::ICCCI: |
4746 | case PPC::TLBIVAX: |
4747 | case PPC::TLBSX: { |
4748 | // op: RA |
4749 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4750 | op &= UINT64_C(31); |
4751 | op <<= 16; |
4752 | Value |= op; |
4753 | // op: RB |
4754 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4755 | op &= UINT64_C(31); |
4756 | op <<= 11; |
4757 | Value |= op; |
4758 | break; |
4759 | } |
4760 | case PPC::RLWNM: |
4761 | case PPC::RLWNM8: |
4762 | case PPC::RLWNM8_rec: |
4763 | case PPC::RLWNM_rec: { |
4764 | // op: RA |
4765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4766 | op &= UINT64_C(31); |
4767 | op <<= 16; |
4768 | Value |= op; |
4769 | // op: RS |
4770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4771 | op &= UINT64_C(31); |
4772 | op <<= 21; |
4773 | Value |= op; |
4774 | // op: RB |
4775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4776 | op &= UINT64_C(31); |
4777 | op <<= 11; |
4778 | Value |= op; |
4779 | // op: MB |
4780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4781 | op &= UINT64_C(31); |
4782 | op <<= 6; |
4783 | Value |= op; |
4784 | // op: ME |
4785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
4786 | op &= UINT64_C(31); |
4787 | op <<= 1; |
4788 | Value |= op; |
4789 | break; |
4790 | } |
4791 | case PPC::RLDCL: |
4792 | case PPC::RLDCL_rec: |
4793 | case PPC::RLDCR: |
4794 | case PPC::RLDCR_rec: { |
4795 | // op: RA |
4796 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4797 | op &= UINT64_C(31); |
4798 | op <<= 16; |
4799 | Value |= op; |
4800 | // op: RS |
4801 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4802 | op &= UINT64_C(31); |
4803 | op <<= 21; |
4804 | Value |= op; |
4805 | // op: RB |
4806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4807 | op &= UINT64_C(31); |
4808 | op <<= 11; |
4809 | Value |= op; |
4810 | // op: MBE |
4811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4812 | Value |= (op & UINT64_C(31)) << 6; |
4813 | Value |= (op & UINT64_C(32)); |
4814 | break; |
4815 | } |
4816 | case PPC::EXTSWSLI: |
4817 | case PPC::EXTSWSLI_32_64: |
4818 | case PPC::EXTSWSLI_32_64_rec: |
4819 | case PPC::EXTSWSLI_rec: |
4820 | case PPC::SRADI: |
4821 | case PPC::SRADI_32: |
4822 | case PPC::SRADI_rec: { |
4823 | // op: RA |
4824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4825 | op &= UINT64_C(31); |
4826 | op <<= 16; |
4827 | Value |= op; |
4828 | // op: RS |
4829 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4830 | op &= UINT64_C(31); |
4831 | op <<= 21; |
4832 | Value |= op; |
4833 | // op: SH |
4834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4835 | Value |= (op & UINT64_C(31)) << 11; |
4836 | Value |= (op & UINT64_C(32)) >> 4; |
4837 | break; |
4838 | } |
4839 | case PPC::RLDIC: |
4840 | case PPC::RLDICL: |
4841 | case PPC::RLDICL_32: |
4842 | case PPC::RLDICL_32_64: |
4843 | case PPC::RLDICL_32_rec: |
4844 | case PPC::RLDICL_rec: |
4845 | case PPC::RLDICR: |
4846 | case PPC::RLDICR_32: |
4847 | case PPC::RLDICR_rec: |
4848 | case PPC::RLDIC_rec: { |
4849 | // op: RA |
4850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4851 | op &= UINT64_C(31); |
4852 | op <<= 16; |
4853 | Value |= op; |
4854 | // op: RS |
4855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4856 | op &= UINT64_C(31); |
4857 | op <<= 21; |
4858 | Value |= op; |
4859 | // op: SH |
4860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4861 | Value |= (op & UINT64_C(31)) << 11; |
4862 | Value |= (op & UINT64_C(32)) >> 4; |
4863 | // op: MBE |
4864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4865 | Value |= (op & UINT64_C(31)) << 6; |
4866 | Value |= (op & UINT64_C(32)); |
4867 | break; |
4868 | } |
4869 | case PPC::RLWINM: |
4870 | case PPC::RLWINM8: |
4871 | case PPC::RLWINM8_rec: |
4872 | case PPC::RLWINM_rec: { |
4873 | // op: RA |
4874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4875 | op &= UINT64_C(31); |
4876 | op <<= 16; |
4877 | Value |= op; |
4878 | // op: RS |
4879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
4880 | op &= UINT64_C(31); |
4881 | op <<= 21; |
4882 | Value |= op; |
4883 | // op: SH |
4884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4885 | op &= UINT64_C(31); |
4886 | op <<= 11; |
4887 | Value |= op; |
4888 | // op: MB |
4889 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4890 | op &= UINT64_C(31); |
4891 | op <<= 6; |
4892 | Value |= op; |
4893 | // op: ME |
4894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
4895 | op &= UINT64_C(31); |
4896 | op <<= 1; |
4897 | Value |= op; |
4898 | break; |
4899 | } |
4900 | case PPC::RLDIMI: |
4901 | case PPC::RLDIMI_rec: { |
4902 | // op: RA |
4903 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4904 | op &= UINT64_C(31); |
4905 | op <<= 16; |
4906 | Value |= op; |
4907 | // op: RS |
4908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4909 | op &= UINT64_C(31); |
4910 | op <<= 21; |
4911 | Value |= op; |
4912 | // op: SH |
4913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4914 | Value |= (op & UINT64_C(31)) << 11; |
4915 | Value |= (op & UINT64_C(32)) >> 4; |
4916 | // op: MBE |
4917 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
4918 | Value |= (op & UINT64_C(31)) << 6; |
4919 | Value |= (op & UINT64_C(32)); |
4920 | break; |
4921 | } |
4922 | case PPC::RLWIMI: |
4923 | case PPC::RLWIMI8: |
4924 | case PPC::RLWIMI8_rec: |
4925 | case PPC::RLWIMI_rec: { |
4926 | // op: RA |
4927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4928 | op &= UINT64_C(31); |
4929 | op <<= 16; |
4930 | Value |= op; |
4931 | // op: RS |
4932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
4933 | op &= UINT64_C(31); |
4934 | op <<= 21; |
4935 | Value |= op; |
4936 | // op: SH |
4937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
4938 | op &= UINT64_C(31); |
4939 | op <<= 11; |
4940 | Value |= op; |
4941 | // op: MB |
4942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
4943 | op &= UINT64_C(31); |
4944 | op <<= 6; |
4945 | Value |= op; |
4946 | // op: ME |
4947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
4948 | op &= UINT64_C(31); |
4949 | op <<= 1; |
4950 | Value |= op; |
4951 | break; |
4952 | } |
4953 | case PPC::BRD: |
4954 | case PPC::BRH: |
4955 | case PPC::BRH8: |
4956 | case PPC::BRW: |
4957 | case PPC::BRW8: |
4958 | case PPC::CBCDTD: |
4959 | case PPC::CBCDTD8: |
4960 | case PPC::CDTBCD: |
4961 | case PPC::CDTBCD8: |
4962 | case PPC::CNTLZD: |
4963 | case PPC::CNTLZD_rec: |
4964 | case PPC::CNTLZW: |
4965 | case PPC::CNTLZW8: |
4966 | case PPC::CNTLZW8_rec: |
4967 | case PPC::CNTLZW_rec: |
4968 | case PPC::CNTTZD: |
4969 | case PPC::CNTTZD_rec: |
4970 | case PPC::CNTTZW: |
4971 | case PPC::CNTTZW8: |
4972 | case PPC::CNTTZW8_rec: |
4973 | case PPC::CNTTZW_rec: |
4974 | case PPC::EXTSB: |
4975 | case PPC::EXTSB8: |
4976 | case PPC::EXTSB8_32_64: |
4977 | case PPC::EXTSB8_rec: |
4978 | case PPC::EXTSB_rec: |
4979 | case PPC::EXTSH: |
4980 | case PPC::EXTSH8: |
4981 | case PPC::EXTSH8_32_64: |
4982 | case PPC::EXTSH8_rec: |
4983 | case PPC::EXTSH_rec: |
4984 | case PPC::EXTSW: |
4985 | case PPC::EXTSW_32: |
4986 | case PPC::EXTSW_32_64: |
4987 | case PPC::EXTSW_32_64_rec: |
4988 | case PPC::EXTSW_rec: |
4989 | case PPC::POPCNTB: |
4990 | case PPC::POPCNTB8: |
4991 | case PPC::POPCNTD: |
4992 | case PPC::POPCNTW: { |
4993 | // op: RA |
4994 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
4995 | op &= UINT64_C(31); |
4996 | op <<= 16; |
4997 | Value |= op; |
4998 | // op: RST |
4999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5000 | op &= UINT64_C(31); |
5001 | op <<= 21; |
5002 | Value |= op; |
5003 | break; |
5004 | } |
5005 | case PPC::ANDI8_rec: |
5006 | case PPC::ANDIS8_rec: |
5007 | case PPC::ANDIS_rec: |
5008 | case PPC::ANDI_rec: |
5009 | case PPC::ORI: |
5010 | case PPC::ORI8: |
5011 | case PPC::ORIS: |
5012 | case PPC::ORIS8: |
5013 | case PPC::XORI: |
5014 | case PPC::XORI8: |
5015 | case PPC::XORIS: |
5016 | case PPC::XORIS8: { |
5017 | // op: RA |
5018 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5019 | op &= UINT64_C(31); |
5020 | op <<= 16; |
5021 | Value |= op; |
5022 | // op: RST |
5023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5024 | op &= UINT64_C(31); |
5025 | op <<= 21; |
5026 | Value |= op; |
5027 | // op: D |
5028 | op = getImm16Encoding(MI, OpNo: 2, Fixups, STI); |
5029 | op &= UINT64_C(65535); |
5030 | Value |= op; |
5031 | break; |
5032 | } |
5033 | case PPC::AND: |
5034 | case PPC::AND8: |
5035 | case PPC::AND8_rec: |
5036 | case PPC::ANDC: |
5037 | case PPC::ANDC8: |
5038 | case PPC::ANDC8_rec: |
5039 | case PPC::ANDC_rec: |
5040 | case PPC::AND_rec: |
5041 | case PPC::BPERMD: |
5042 | case PPC::CFUGED: |
5043 | case PPC::CMPB: |
5044 | case PPC::CMPB8: |
5045 | case PPC::CNTLZDM: |
5046 | case PPC::CNTTZDM: |
5047 | case PPC::EQV: |
5048 | case PPC::EQV8: |
5049 | case PPC::EQV8_rec: |
5050 | case PPC::EQV_rec: |
5051 | case PPC::NAND: |
5052 | case PPC::NAND8: |
5053 | case PPC::NAND8_rec: |
5054 | case PPC::NAND_rec: |
5055 | case PPC::NOR: |
5056 | case PPC::NOR8: |
5057 | case PPC::NOR8_rec: |
5058 | case PPC::NOR_rec: |
5059 | case PPC::OR: |
5060 | case PPC::OR8: |
5061 | case PPC::OR8_rec: |
5062 | case PPC::ORC: |
5063 | case PPC::ORC8: |
5064 | case PPC::ORC8_rec: |
5065 | case PPC::ORC_rec: |
5066 | case PPC::OR_rec: |
5067 | case PPC::PDEPD: |
5068 | case PPC::PEXTD: |
5069 | case PPC::SLD: |
5070 | case PPC::SLD_rec: |
5071 | case PPC::SLW: |
5072 | case PPC::SLW8: |
5073 | case PPC::SLW8_rec: |
5074 | case PPC::SLW_rec: |
5075 | case PPC::SRAD: |
5076 | case PPC::SRAD_rec: |
5077 | case PPC::SRAW: |
5078 | case PPC::SRAWI: |
5079 | case PPC::SRAWI_rec: |
5080 | case PPC::SRAW_rec: |
5081 | case PPC::SRD: |
5082 | case PPC::SRD_rec: |
5083 | case PPC::SRW: |
5084 | case PPC::SRW8: |
5085 | case PPC::SRW8_rec: |
5086 | case PPC::SRW_rec: |
5087 | case PPC::XOR: |
5088 | case PPC::XOR8: |
5089 | case PPC::XOR8_rec: |
5090 | case PPC::XOR_rec: { |
5091 | // op: RA |
5092 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5093 | op &= UINT64_C(31); |
5094 | op <<= 16; |
5095 | Value |= op; |
5096 | // op: RST |
5097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5098 | op &= UINT64_C(31); |
5099 | op <<= 21; |
5100 | Value |= op; |
5101 | // op: RB |
5102 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5103 | op &= UINT64_C(31); |
5104 | op <<= 11; |
5105 | Value |= op; |
5106 | break; |
5107 | } |
5108 | case PPC::BCTRL_LWZinto_toc: |
5109 | case PPC::BCTRL_LWZinto_toc_RM: { |
5110 | // op: RA |
5111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5112 | op &= UINT64_C(31); |
5113 | op <<= 16; |
5114 | Value |= op; |
5115 | // op: D |
5116 | op = getDispRIEncoding(MI, OpNo: 0, Fixups, STI); |
5117 | op &= UINT64_C(65535); |
5118 | Value |= op; |
5119 | break; |
5120 | } |
5121 | case PPC::BCTRL8_LDinto_toc: |
5122 | case PPC::BCTRL8_LDinto_toc_RM: { |
5123 | // op: RA |
5124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5125 | op &= UINT64_C(31); |
5126 | op <<= 16; |
5127 | Value |= op; |
5128 | // op: D |
5129 | op = getDispRIXEncoding(MI, OpNo: 0, Fixups, STI); |
5130 | op &= UINT64_C(16383); |
5131 | op <<= 2; |
5132 | Value |= op; |
5133 | break; |
5134 | } |
5135 | case PPC::TLBILX: { |
5136 | // op: RA |
5137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5138 | op &= UINT64_C(31); |
5139 | op <<= 16; |
5140 | Value |= op; |
5141 | // op: RB |
5142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5143 | op &= UINT64_C(31); |
5144 | op <<= 11; |
5145 | Value |= op; |
5146 | // op: T |
5147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5148 | op &= UINT64_C(31); |
5149 | op <<= 21; |
5150 | Value |= op; |
5151 | break; |
5152 | } |
5153 | case PPC::HASHCHK: |
5154 | case PPC::HASHCHK8: |
5155 | case PPC::HASHCHKP: |
5156 | case PPC::HASHCHKP8: |
5157 | case PPC::HASHST: |
5158 | case PPC::HASHST8: |
5159 | case PPC::HASHSTP: |
5160 | case PPC::HASHSTP8: { |
5161 | // op: RA |
5162 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5163 | op &= UINT64_C(31); |
5164 | op <<= 16; |
5165 | Value |= op; |
5166 | // op: D |
5167 | op = getDispRIHashEncoding(MI, OpNo: 1, Fixups, STI); |
5168 | Value |= (op & UINT64_C(31)) << 21; |
5169 | Value |= (op & UINT64_C(32)) >> 5; |
5170 | // op: RB |
5171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5172 | op &= UINT64_C(31); |
5173 | op <<= 11; |
5174 | Value |= op; |
5175 | break; |
5176 | } |
5177 | case PPC::SLBIE: |
5178 | case PPC::TLBIEL: |
5179 | case PPC::TLBLD: |
5180 | case PPC::TLBLI: { |
5181 | // op: RB |
5182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5183 | op &= UINT64_C(31); |
5184 | op <<= 11; |
5185 | Value |= op; |
5186 | break; |
5187 | } |
5188 | case PPC::VCNTMBB: |
5189 | case PPC::VCNTMBD: |
5190 | case PPC::VCNTMBH: |
5191 | case PPC::VCNTMBW: { |
5192 | // op: RD |
5193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5194 | op &= UINT64_C(31); |
5195 | op <<= 21; |
5196 | Value |= op; |
5197 | // op: VB |
5198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5199 | op &= UINT64_C(31); |
5200 | op <<= 11; |
5201 | Value |= op; |
5202 | // op: MP |
5203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5204 | op &= UINT64_C(1); |
5205 | op <<= 16; |
5206 | Value |= op; |
5207 | break; |
5208 | } |
5209 | case PPC::VGNB: { |
5210 | // op: RD |
5211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5212 | op &= UINT64_C(31); |
5213 | op <<= 21; |
5214 | Value |= op; |
5215 | // op: VB |
5216 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5217 | op &= UINT64_C(31); |
5218 | op <<= 11; |
5219 | Value |= op; |
5220 | // op: N |
5221 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5222 | op &= UINT64_C(7); |
5223 | op <<= 16; |
5224 | Value |= op; |
5225 | break; |
5226 | } |
5227 | case PPC::WRTEE: { |
5228 | // op: RS |
5229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5230 | op &= UINT64_C(31); |
5231 | op <<= 21; |
5232 | Value |= op; |
5233 | break; |
5234 | } |
5235 | case PPC::MTMSR: |
5236 | case PPC::MTMSRD: { |
5237 | // op: RS |
5238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5239 | op &= UINT64_C(31); |
5240 | op <<= 21; |
5241 | Value |= op; |
5242 | // op: L |
5243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5244 | op &= UINT64_C(1); |
5245 | op <<= 16; |
5246 | Value |= op; |
5247 | break; |
5248 | } |
5249 | case PPC::MFSRIN: |
5250 | case PPC::MTSRIN: { |
5251 | // op: RS |
5252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5253 | op &= UINT64_C(31); |
5254 | op <<= 21; |
5255 | Value |= op; |
5256 | // op: RB |
5257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5258 | op &= UINT64_C(31); |
5259 | op <<= 11; |
5260 | Value |= op; |
5261 | break; |
5262 | } |
5263 | case PPC::MFSR: |
5264 | case PPC::MTSR: { |
5265 | // op: RS |
5266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5267 | op &= UINT64_C(31); |
5268 | op <<= 21; |
5269 | Value |= op; |
5270 | // op: SR |
5271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5272 | op &= UINT64_C(15); |
5273 | op <<= 16; |
5274 | Value |= op; |
5275 | break; |
5276 | } |
5277 | case PPC::MFCTR: |
5278 | case PPC::MFCTR8: |
5279 | case PPC::MFFS: |
5280 | case PPC::MFFSCE: |
5281 | case PPC::MFFSL: |
5282 | case PPC::MFFS_rec: |
5283 | case PPC::MFLR: |
5284 | case PPC::MFLR8: |
5285 | case PPC::MFMSR: |
5286 | case PPC::MFTB8: |
5287 | case PPC::MFUDSCR: |
5288 | case PPC::MFVRSAVE: |
5289 | case PPC::MFVRSAVEv: |
5290 | case PPC::MTCTR: |
5291 | case PPC::MTCTR8: |
5292 | case PPC::MTCTR8loop: |
5293 | case PPC::MTCTRloop: |
5294 | case PPC::MTLR: |
5295 | case PPC::MTLR8: |
5296 | case PPC::MTUDSCR: |
5297 | case PPC::MTVRSAVE: { |
5298 | // op: RST |
5299 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5300 | op &= UINT64_C(31); |
5301 | op <<= 21; |
5302 | Value |= op; |
5303 | break; |
5304 | } |
5305 | case PPC::SETBC: |
5306 | case PPC::SETBC8: |
5307 | case PPC::SETBCR: |
5308 | case PPC::SETBCR8: |
5309 | case PPC::SETNBC: |
5310 | case PPC::SETNBC8: |
5311 | case PPC::SETNBCR: |
5312 | case PPC::SETNBCR8: { |
5313 | // op: RST |
5314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5315 | op &= UINT64_C(31); |
5316 | op <<= 21; |
5317 | Value |= op; |
5318 | // op: BI |
5319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5320 | op &= UINT64_C(31); |
5321 | op <<= 16; |
5322 | Value |= op; |
5323 | break; |
5324 | } |
5325 | case PPC::LI: |
5326 | case PPC::LI8: |
5327 | case PPC::LIS: |
5328 | case PPC::LIS8: { |
5329 | // op: RST |
5330 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5331 | op &= UINT64_C(31); |
5332 | op <<= 21; |
5333 | Value |= op; |
5334 | // op: D |
5335 | op = getImm16Encoding(MI, OpNo: 1, Fixups, STI); |
5336 | op &= UINT64_C(65535); |
5337 | Value |= op; |
5338 | break; |
5339 | } |
5340 | case PPC::PLBZ8onlypc: |
5341 | case PPC::PLBZonlypc: |
5342 | case PPC::PLDonlypc: |
5343 | case PPC::PLFDonlypc: |
5344 | case PPC::PLFSonlypc: |
5345 | case PPC::PLHA8onlypc: |
5346 | case PPC::PLHAonlypc: |
5347 | case PPC::PLHZ8onlypc: |
5348 | case PPC::PLHZonlypc: |
5349 | case PPC::PLWA8onlypc: |
5350 | case PPC::PLWAonlypc: |
5351 | case PPC::PLWZ8onlypc: |
5352 | case PPC::PLWZonlypc: |
5353 | case PPC::PLXSDonlypc: |
5354 | case PPC::PLXSSPonlypc: |
5355 | case PPC::PSTB8onlypc: |
5356 | case PPC::PSTBonlypc: |
5357 | case PPC::PSTDonlypc: |
5358 | case PPC::PSTFDonlypc: |
5359 | case PPC::PSTFSonlypc: |
5360 | case PPC::PSTH8onlypc: |
5361 | case PPC::PSTHonlypc: |
5362 | case PPC::PSTW8onlypc: |
5363 | case PPC::PSTWonlypc: |
5364 | case PPC::PSTXSDonlypc: |
5365 | case PPC::PSTXSSPonlypc: { |
5366 | // op: RST |
5367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5368 | op &= UINT64_C(31); |
5369 | op <<= 21; |
5370 | Value |= op; |
5371 | // op: D |
5372 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
5373 | Value |= (op & UINT64_C(17179803648)) << 16; |
5374 | Value |= (op & UINT64_C(65535)); |
5375 | break; |
5376 | } |
5377 | case PPC::MFFSCDRNI: { |
5378 | // op: RST |
5379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5380 | op &= UINT64_C(31); |
5381 | op <<= 21; |
5382 | Value |= op; |
5383 | // op: DRM |
5384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5385 | op &= UINT64_C(7); |
5386 | op <<= 11; |
5387 | Value |= op; |
5388 | break; |
5389 | } |
5390 | case PPC::MFFSCDRN: |
5391 | case PPC::MFFSCRN: { |
5392 | // op: RST |
5393 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5394 | op &= UINT64_C(31); |
5395 | op <<= 21; |
5396 | Value |= op; |
5397 | // op: FRB |
5398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5399 | op &= UINT64_C(31); |
5400 | op <<= 11; |
5401 | Value |= op; |
5402 | break; |
5403 | } |
5404 | case PPC::MFOCRF: |
5405 | case PPC::MFOCRF8: { |
5406 | // op: RST |
5407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5408 | op &= UINT64_C(31); |
5409 | op <<= 21; |
5410 | Value |= op; |
5411 | // op: FXM |
5412 | op = get_crbitm_encoding(MI, OpNo: 1, Fixups, STI); |
5413 | op &= UINT64_C(255); |
5414 | op <<= 12; |
5415 | Value |= op; |
5416 | break; |
5417 | } |
5418 | case PPC::ADDI: |
5419 | case PPC::ADDI8: |
5420 | case PPC::ADDIC: |
5421 | case PPC::ADDIC8: |
5422 | case PPC::ADDIC_rec: |
5423 | case PPC::ADDIS: |
5424 | case PPC::ADDIS8: |
5425 | case PPC::LA: |
5426 | case PPC::LA8: |
5427 | case PPC::MULLI: |
5428 | case PPC::MULLI8: |
5429 | case PPC::SUBFIC: |
5430 | case PPC::SUBFIC8: |
5431 | case PPC::TDI: |
5432 | case PPC::TWI: { |
5433 | // op: RST |
5434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5435 | op &= UINT64_C(31); |
5436 | op <<= 21; |
5437 | Value |= op; |
5438 | // op: RA |
5439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5440 | op &= UINT64_C(31); |
5441 | op <<= 16; |
5442 | Value |= op; |
5443 | // op: D |
5444 | op = getImm16Encoding(MI, OpNo: 2, Fixups, STI); |
5445 | op &= UINT64_C(65535); |
5446 | Value |= op; |
5447 | break; |
5448 | } |
5449 | case PPC::DADD: |
5450 | case PPC::DADDQ: |
5451 | case PPC::DADDQ_rec: |
5452 | case PPC::DADD_rec: |
5453 | case PPC::DDIV: |
5454 | case PPC::DDIVQ: |
5455 | case PPC::DDIVQ_rec: |
5456 | case PPC::DDIV_rec: |
5457 | case PPC::DIEX: |
5458 | case PPC::DIEXQ: |
5459 | case PPC::DIEXQ_rec: |
5460 | case PPC::DIEX_rec: |
5461 | case PPC::DMUL: |
5462 | case PPC::DMULQ: |
5463 | case PPC::DMULQ_rec: |
5464 | case PPC::DMUL_rec: |
5465 | case PPC::DSUB: |
5466 | case PPC::DSUBQ: |
5467 | case PPC::DSUBQ_rec: |
5468 | case PPC::DSUB_rec: |
5469 | case PPC::FCPSGND: |
5470 | case PPC::FCPSGND_rec: |
5471 | case PPC::FCPSGNS: |
5472 | case PPC::FCPSGNS_rec: |
5473 | case PPC::LBARX: |
5474 | case PPC::LBARXL: |
5475 | case PPC::LBEPX: |
5476 | case PPC::LBZCIX: |
5477 | case PPC::LBZX: |
5478 | case PPC::LBZX8: |
5479 | case PPC::LDARX: |
5480 | case PPC::LDARXL: |
5481 | case PPC::LDAT: |
5482 | case PPC::LDBRX: |
5483 | case PPC::LDCIX: |
5484 | case PPC::LDX: |
5485 | case PPC::LFDEPX: |
5486 | case PPC::LFDX: |
5487 | case PPC::LFIWAX: |
5488 | case PPC::LFIWZX: |
5489 | case PPC::LFSX: |
5490 | case PPC::LHARX: |
5491 | case PPC::LHARXL: |
5492 | case PPC::LHAX: |
5493 | case PPC::LHAX8: |
5494 | case PPC::LHBRX: |
5495 | case PPC::LHBRX8: |
5496 | case PPC::LHEPX: |
5497 | case PPC::LHZCIX: |
5498 | case PPC::LHZX: |
5499 | case PPC::LHZX8: |
5500 | case PPC::LQARX: |
5501 | case PPC::LQARXL: |
5502 | case PPC::LSWI: |
5503 | case PPC::LVEBX: |
5504 | case PPC::LVEHX: |
5505 | case PPC::LVEWX: |
5506 | case PPC::LVSL: |
5507 | case PPC::LVSR: |
5508 | case PPC::LVX: |
5509 | case PPC::LVXL: |
5510 | case PPC::LWARX: |
5511 | case PPC::LWARXL: |
5512 | case PPC::LWAT: |
5513 | case PPC::LWAX: |
5514 | case PPC::LWAX_32: |
5515 | case PPC::LWBRX: |
5516 | case PPC::LWBRX8: |
5517 | case PPC::LWEPX: |
5518 | case PPC::LWZCIX: |
5519 | case PPC::LWZX: |
5520 | case PPC::LWZX8: |
5521 | case PPC::MODSD: |
5522 | case PPC::MODSW: |
5523 | case PPC::MODUD: |
5524 | case PPC::MODUW: |
5525 | case PPC::SPELWZX: |
5526 | case PPC::SPESTWX: |
5527 | case PPC::STBCIX: |
5528 | case PPC::STBCX: |
5529 | case PPC::STBEPX: |
5530 | case PPC::STBX: |
5531 | case PPC::STBX8: |
5532 | case PPC::STDAT: |
5533 | case PPC::STDBRX: |
5534 | case PPC::STDCIX: |
5535 | case PPC::STDCX: |
5536 | case PPC::STDX: |
5537 | case PPC::STFDEPX: |
5538 | case PPC::STFDX: |
5539 | case PPC::STFIWX: |
5540 | case PPC::STFSX: |
5541 | case PPC::STHBRX: |
5542 | case PPC::STHCIX: |
5543 | case PPC::STHCX: |
5544 | case PPC::STHEPX: |
5545 | case PPC::STHX: |
5546 | case PPC::STHX8: |
5547 | case PPC::STQCX: |
5548 | case PPC::STSWI: |
5549 | case PPC::STVEBX: |
5550 | case PPC::STVEHX: |
5551 | case PPC::STVEWX: |
5552 | case PPC::STVX: |
5553 | case PPC::STVXL: |
5554 | case PPC::STWAT: |
5555 | case PPC::STWBRX: |
5556 | case PPC::STWCIX: |
5557 | case PPC::STWCX: |
5558 | case PPC::STWEPX: |
5559 | case PPC::STWX: |
5560 | case PPC::STWX8: |
5561 | case PPC::TABORTDC: |
5562 | case PPC::TABORTDCI: |
5563 | case PPC::TABORTWC: |
5564 | case PPC::TABORTWCI: |
5565 | case PPC::TD: |
5566 | case PPC::TLBSX2: |
5567 | case PPC::TLBSX2D: |
5568 | case PPC::TW: |
5569 | case PPC::XSADDQP: |
5570 | case PPC::XSADDQPO: |
5571 | case PPC::XSCMPEQQP: |
5572 | case PPC::XSCMPGEQP: |
5573 | case PPC::XSCMPGTQP: |
5574 | case PPC::XSCPSGNQP: |
5575 | case PPC::XSDIVQP: |
5576 | case PPC::XSDIVQPO: |
5577 | case PPC::XSMAXCQP: |
5578 | case PPC::XSMINCQP: |
5579 | case PPC::XSMULQP: |
5580 | case PPC::XSMULQPO: |
5581 | case PPC::XSSUBQP: |
5582 | case PPC::XSSUBQPO: { |
5583 | // op: RST |
5584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5585 | op &= UINT64_C(31); |
5586 | op <<= 21; |
5587 | Value |= op; |
5588 | // op: RA |
5589 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5590 | op &= UINT64_C(31); |
5591 | op <<= 16; |
5592 | Value |= op; |
5593 | // op: RB |
5594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5595 | op &= UINT64_C(31); |
5596 | op <<= 11; |
5597 | Value |= op; |
5598 | break; |
5599 | } |
5600 | case PPC::LBZXTLS: |
5601 | case PPC::LBZXTLS_: |
5602 | case PPC::LBZXTLS_32: |
5603 | case PPC::LDXTLS: |
5604 | case PPC::LDXTLS_: |
5605 | case PPC::LFDXTLS: |
5606 | case PPC::LFDXTLS_: |
5607 | case PPC::LFSXTLS: |
5608 | case PPC::LFSXTLS_: |
5609 | case PPC::LHAXTLS: |
5610 | case PPC::LHAXTLS_: |
5611 | case PPC::LHAXTLS_32: |
5612 | case PPC::LHZXTLS: |
5613 | case PPC::LHZXTLS_: |
5614 | case PPC::LHZXTLS_32: |
5615 | case PPC::LWAXTLS: |
5616 | case PPC::LWAXTLS_: |
5617 | case PPC::LWAXTLS_32: |
5618 | case PPC::LWZXTLS: |
5619 | case PPC::LWZXTLS_: |
5620 | case PPC::LWZXTLS_32: |
5621 | case PPC::STBXTLS: |
5622 | case PPC::STBXTLS_: |
5623 | case PPC::STBXTLS_32: |
5624 | case PPC::STDXTLS: |
5625 | case PPC::STDXTLS_: |
5626 | case PPC::STFDXTLS: |
5627 | case PPC::STFDXTLS_: |
5628 | case PPC::STFSXTLS: |
5629 | case PPC::STFSXTLS_: |
5630 | case PPC::STHXTLS: |
5631 | case PPC::STHXTLS_: |
5632 | case PPC::STHXTLS_32: |
5633 | case PPC::STWXTLS: |
5634 | case PPC::STWXTLS_: |
5635 | case PPC::STWXTLS_32: { |
5636 | // op: RST |
5637 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5638 | op &= UINT64_C(31); |
5639 | op <<= 21; |
5640 | Value |= op; |
5641 | // op: RA |
5642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5643 | op &= UINT64_C(31); |
5644 | op <<= 16; |
5645 | Value |= op; |
5646 | // op: RB |
5647 | op = getTLSRegEncoding(MI, OpNo: 2, Fixups, STI); |
5648 | op &= UINT64_C(31); |
5649 | op <<= 11; |
5650 | Value |= op; |
5651 | break; |
5652 | } |
5653 | case PPC::TLBRE2: |
5654 | case PPC::TLBWE2: { |
5655 | // op: RST |
5656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5657 | op &= UINT64_C(31); |
5658 | op <<= 21; |
5659 | Value |= op; |
5660 | // op: RA |
5661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
5662 | op &= UINT64_C(31); |
5663 | op <<= 16; |
5664 | Value |= op; |
5665 | // op: WS |
5666 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5667 | op &= UINT64_C(1); |
5668 | op <<= 11; |
5669 | Value |= op; |
5670 | break; |
5671 | } |
5672 | case PPC::PLBZ: |
5673 | case PPC::PLBZ8: |
5674 | case PPC::PLBZ8nopc: |
5675 | case PPC::PLBZnopc: |
5676 | case PPC::PLD: |
5677 | case PPC::PLDnopc: |
5678 | case PPC::PLFD: |
5679 | case PPC::PLFDnopc: |
5680 | case PPC::PLFS: |
5681 | case PPC::PLFSnopc: |
5682 | case PPC::PLHA: |
5683 | case PPC::PLHA8: |
5684 | case PPC::PLHA8nopc: |
5685 | case PPC::PLHAnopc: |
5686 | case PPC::PLHZ: |
5687 | case PPC::PLHZ8: |
5688 | case PPC::PLHZ8nopc: |
5689 | case PPC::PLHZnopc: |
5690 | case PPC::PLWA: |
5691 | case PPC::PLWA8: |
5692 | case PPC::PLWA8nopc: |
5693 | case PPC::PLWAnopc: |
5694 | case PPC::PLWZ: |
5695 | case PPC::PLWZ8: |
5696 | case PPC::PLWZ8nopc: |
5697 | case PPC::PLWZnopc: |
5698 | case PPC::PLXSD: |
5699 | case PPC::PLXSDnopc: |
5700 | case PPC::PLXSSP: |
5701 | case PPC::PLXSSPnopc: |
5702 | case PPC::PSTB: |
5703 | case PPC::PSTB8: |
5704 | case PPC::PSTB8nopc: |
5705 | case PPC::PSTBnopc: |
5706 | case PPC::PSTD: |
5707 | case PPC::PSTDnopc: |
5708 | case PPC::PSTFD: |
5709 | case PPC::PSTFDnopc: |
5710 | case PPC::PSTFS: |
5711 | case PPC::PSTFSnopc: |
5712 | case PPC::PSTH: |
5713 | case PPC::PSTH8: |
5714 | case PPC::PSTH8nopc: |
5715 | case PPC::PSTHnopc: |
5716 | case PPC::PSTW: |
5717 | case PPC::PSTW8: |
5718 | case PPC::PSTW8nopc: |
5719 | case PPC::PSTWnopc: |
5720 | case PPC::PSTXSD: |
5721 | case PPC::PSTXSDnopc: |
5722 | case PPC::PSTXSSP: |
5723 | case PPC::PSTXSSPnopc: { |
5724 | // op: RST |
5725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5726 | op &= UINT64_C(31); |
5727 | op <<= 21; |
5728 | Value |= op; |
5729 | // op: RA |
5730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5731 | op &= UINT64_C(31); |
5732 | op <<= 16; |
5733 | Value |= op; |
5734 | // op: D |
5735 | op = getDispRI34Encoding(MI, OpNo: 1, Fixups, STI); |
5736 | Value |= (op & UINT64_C(17179803648)) << 16; |
5737 | Value |= (op & UINT64_C(65535)); |
5738 | break; |
5739 | } |
5740 | case PPC::PLBZ8pc: |
5741 | case PPC::PLBZpc: |
5742 | case PPC::PLDpc: |
5743 | case PPC::PLFDpc: |
5744 | case PPC::PLFSpc: |
5745 | case PPC::PLHA8pc: |
5746 | case PPC::PLHApc: |
5747 | case PPC::PLHZ8pc: |
5748 | case PPC::PLHZpc: |
5749 | case PPC::PLWA8pc: |
5750 | case PPC::PLWApc: |
5751 | case PPC::PLWZ8pc: |
5752 | case PPC::PLWZpc: |
5753 | case PPC::PLXSDpc: |
5754 | case PPC::PLXSSPpc: |
5755 | case PPC::PSTB8pc: |
5756 | case PPC::PSTBpc: |
5757 | case PPC::PSTDpc: |
5758 | case PPC::PSTFDpc: |
5759 | case PPC::PSTFSpc: |
5760 | case PPC::PSTH8pc: |
5761 | case PPC::PSTHpc: |
5762 | case PPC::PSTW8pc: |
5763 | case PPC::PSTWpc: |
5764 | case PPC::PSTXSDpc: |
5765 | case PPC::PSTXSSPpc: { |
5766 | // op: RST |
5767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5768 | op &= UINT64_C(31); |
5769 | op <<= 21; |
5770 | Value |= op; |
5771 | // op: RA |
5772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5773 | op &= UINT64_C(31); |
5774 | op <<= 16; |
5775 | Value |= op; |
5776 | // op: D |
5777 | op = getDispRI34PCRelEncoding(MI, OpNo: 1, Fixups, STI); |
5778 | Value |= (op & UINT64_C(17179803648)) << 16; |
5779 | Value |= (op & UINT64_C(65535)); |
5780 | break; |
5781 | } |
5782 | case PPC::LBZ: |
5783 | case PPC::LBZ8: |
5784 | case PPC::LFD: |
5785 | case PPC::LFS: |
5786 | case PPC::LHA: |
5787 | case PPC::LHA8: |
5788 | case PPC::LHZ: |
5789 | case PPC::LHZ8: |
5790 | case PPC::LMW: |
5791 | case PPC::LWZ: |
5792 | case PPC::LWZ8: |
5793 | case PPC::SPELWZ: |
5794 | case PPC::SPESTW: |
5795 | case PPC::STB: |
5796 | case PPC::STB8: |
5797 | case PPC::STFD: |
5798 | case PPC::STFS: |
5799 | case PPC::STH: |
5800 | case PPC::STH8: |
5801 | case PPC::STMW: |
5802 | case PPC::STW: |
5803 | case PPC::STW8: { |
5804 | // op: RST |
5805 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5806 | op &= UINT64_C(31); |
5807 | op <<= 21; |
5808 | Value |= op; |
5809 | // op: RA |
5810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5811 | op &= UINT64_C(31); |
5812 | op <<= 16; |
5813 | Value |= op; |
5814 | // op: D |
5815 | op = getDispRIEncoding(MI, OpNo: 1, Fixups, STI); |
5816 | op &= UINT64_C(65535); |
5817 | Value |= op; |
5818 | break; |
5819 | } |
5820 | case PPC::LD: |
5821 | case PPC::LWA: |
5822 | case PPC::LWA_32: |
5823 | case PPC::LXSD: |
5824 | case PPC::LXSSP: |
5825 | case PPC::STD: |
5826 | case PPC::STQ: |
5827 | case PPC::STXSD: |
5828 | case PPC::STXSSP: { |
5829 | // op: RST |
5830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5831 | op &= UINT64_C(31); |
5832 | op <<= 21; |
5833 | Value |= op; |
5834 | // op: RA |
5835 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5836 | op &= UINT64_C(31); |
5837 | op <<= 16; |
5838 | Value |= op; |
5839 | // op: D |
5840 | op = getDispRIXEncoding(MI, OpNo: 1, Fixups, STI); |
5841 | op &= UINT64_C(16383); |
5842 | op <<= 2; |
5843 | Value |= op; |
5844 | break; |
5845 | } |
5846 | case PPC::LBZUX: |
5847 | case PPC::LBZUX8: |
5848 | case PPC::LDUX: |
5849 | case PPC::LFDUX: |
5850 | case PPC::LFSUX: |
5851 | case PPC::LHAUX: |
5852 | case PPC::LHAUX8: |
5853 | case PPC::LHZUX: |
5854 | case PPC::LHZUX8: |
5855 | case PPC::LWAUX: |
5856 | case PPC::LWZUX: |
5857 | case PPC::LWZUX8: |
5858 | case PPC::XSMADDQP: |
5859 | case PPC::XSMADDQPO: |
5860 | case PPC::XSMSUBQP: |
5861 | case PPC::XSMSUBQPO: |
5862 | case PPC::XSNMADDQP: |
5863 | case PPC::XSNMADDQPO: |
5864 | case PPC::XSNMSUBQP: |
5865 | case PPC::XSNMSUBQPO: { |
5866 | // op: RST |
5867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5868 | op &= UINT64_C(31); |
5869 | op <<= 21; |
5870 | Value |= op; |
5871 | // op: RA |
5872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
5873 | op &= UINT64_C(31); |
5874 | op <<= 16; |
5875 | Value |= op; |
5876 | // op: RB |
5877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
5878 | op &= UINT64_C(31); |
5879 | op <<= 11; |
5880 | Value |= op; |
5881 | break; |
5882 | } |
5883 | case PPC::LBZU: |
5884 | case PPC::LBZU8: |
5885 | case PPC::LFDU: |
5886 | case PPC::LFSU: |
5887 | case PPC::LHAU: |
5888 | case PPC::LHAU8: |
5889 | case PPC::LHZU: |
5890 | case PPC::LHZU8: |
5891 | case PPC::LWZU: |
5892 | case PPC::LWZU8: { |
5893 | // op: RST |
5894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5895 | op &= UINT64_C(31); |
5896 | op <<= 21; |
5897 | Value |= op; |
5898 | // op: RA |
5899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
5900 | op &= UINT64_C(31); |
5901 | op <<= 16; |
5902 | Value |= op; |
5903 | // op: D |
5904 | op = getDispRIEncoding(MI, OpNo: 2, Fixups, STI); |
5905 | op &= UINT64_C(65535); |
5906 | Value |= op; |
5907 | break; |
5908 | } |
5909 | case PPC::LDU: { |
5910 | // op: RST |
5911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
5912 | op &= UINT64_C(31); |
5913 | op <<= 21; |
5914 | Value |= op; |
5915 | // op: RA |
5916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
5917 | op &= UINT64_C(31); |
5918 | op <<= 16; |
5919 | Value |= op; |
5920 | // op: D |
5921 | op = getDispRIXEncoding(MI, OpNo: 2, Fixups, STI); |
5922 | op &= UINT64_C(16383); |
5923 | op <<= 2; |
5924 | Value |= op; |
5925 | break; |
5926 | } |
5927 | case PPC::DCFFIX: |
5928 | case PPC::DCFFIXQ: |
5929 | case PPC::DCFFIXQQ: |
5930 | case PPC::DCFFIXQ_rec: |
5931 | case PPC::DCFFIX_rec: |
5932 | case PPC::DCTDP: |
5933 | case PPC::DCTDP_rec: |
5934 | case PPC::DCTFIX: |
5935 | case PPC::DCTFIXQ: |
5936 | case PPC::DCTFIXQQ: |
5937 | case PPC::DCTFIXQ_rec: |
5938 | case PPC::DCTFIX_rec: |
5939 | case PPC::DCTQPQ: |
5940 | case PPC::DCTQPQ_rec: |
5941 | case PPC::DRDPQ: |
5942 | case PPC::DRDPQ_rec: |
5943 | case PPC::DRSP: |
5944 | case PPC::DRSP_rec: |
5945 | case PPC::DXEX: |
5946 | case PPC::DXEXQ: |
5947 | case PPC::DXEXQ_rec: |
5948 | case PPC::DXEX_rec: |
5949 | case PPC::FABSD: |
5950 | case PPC::FABSD_rec: |
5951 | case PPC::FABSS: |
5952 | case PPC::FABSS_rec: |
5953 | case PPC::FCFID: |
5954 | case PPC::FCFIDS: |
5955 | case PPC::FCFIDS_rec: |
5956 | case PPC::FCFIDU: |
5957 | case PPC::FCFIDUS: |
5958 | case PPC::FCFIDUS_rec: |
5959 | case PPC::FCFIDU_rec: |
5960 | case PPC::FCFID_rec: |
5961 | case PPC::FCTID: |
5962 | case PPC::FCTIDU: |
5963 | case PPC::FCTIDUZ: |
5964 | case PPC::FCTIDUZ_rec: |
5965 | case PPC::FCTIDU_rec: |
5966 | case PPC::FCTIDZ: |
5967 | case PPC::FCTIDZ_rec: |
5968 | case PPC::FCTID_rec: |
5969 | case PPC::FCTIW: |
5970 | case PPC::FCTIWU: |
5971 | case PPC::FCTIWUZ: |
5972 | case PPC::FCTIWUZ_rec: |
5973 | case PPC::FCTIWU_rec: |
5974 | case PPC::FCTIWZ: |
5975 | case PPC::FCTIWZ_rec: |
5976 | case PPC::FCTIW_rec: |
5977 | case PPC::FMR: |
5978 | case PPC::FMR_rec: |
5979 | case PPC::FNABSD: |
5980 | case PPC::FNABSD_rec: |
5981 | case PPC::FNABSS: |
5982 | case PPC::FNABSS_rec: |
5983 | case PPC::FNEGD: |
5984 | case PPC::FNEGD_rec: |
5985 | case PPC::FNEGS: |
5986 | case PPC::FNEGS_rec: |
5987 | case PPC::FRE: |
5988 | case PPC::FRES: |
5989 | case PPC::FRES_rec: |
5990 | case PPC::FRE_rec: |
5991 | case PPC::FRIMD: |
5992 | case PPC::FRIMD_rec: |
5993 | case PPC::FRIMS: |
5994 | case PPC::FRIMS_rec: |
5995 | case PPC::FRIND: |
5996 | case PPC::FRIND_rec: |
5997 | case PPC::FRINS: |
5998 | case PPC::FRINS_rec: |
5999 | case PPC::FRIPD: |
6000 | case PPC::FRIPD_rec: |
6001 | case PPC::FRIPS: |
6002 | case PPC::FRIPS_rec: |
6003 | case PPC::FRIZD: |
6004 | case PPC::FRIZD_rec: |
6005 | case PPC::FRIZS: |
6006 | case PPC::FRIZS_rec: |
6007 | case PPC::FRSP: |
6008 | case PPC::FRSP_rec: |
6009 | case PPC::FRSQRTE: |
6010 | case PPC::FRSQRTES: |
6011 | case PPC::FRSQRTES_rec: |
6012 | case PPC::FRSQRTE_rec: |
6013 | case PPC::FSQRT: |
6014 | case PPC::FSQRTS: |
6015 | case PPC::FSQRTS_rec: |
6016 | case PPC::FSQRT_rec: |
6017 | case PPC::SLBFEE_rec: |
6018 | case PPC::SLBIEG: |
6019 | case PPC::SLBMFEE: |
6020 | case PPC::SLBMTE: |
6021 | case PPC::TLBIE: |
6022 | case PPC::XSABSQP: |
6023 | case PPC::XSCVDPQP: |
6024 | case PPC::XSCVQPDP: |
6025 | case PPC::XSCVQPDPO: |
6026 | case PPC::XSCVQPSDZ: |
6027 | case PPC::XSCVQPSQZ: |
6028 | case PPC::XSCVQPSWZ: |
6029 | case PPC::XSCVQPUDZ: |
6030 | case PPC::XSCVQPUQZ: |
6031 | case PPC::XSCVQPUWZ: |
6032 | case PPC::XSCVSDQP: |
6033 | case PPC::XSCVSQQP: |
6034 | case PPC::XSCVUDQP: |
6035 | case PPC::XSCVUQQP: |
6036 | case PPC::XSNABSQP: |
6037 | case PPC::XSNEGQP: |
6038 | case PPC::XSSQRTQP: |
6039 | case PPC::XSSQRTQPO: |
6040 | case PPC::XSXEXPQP: |
6041 | case PPC::XSXSIGQP: { |
6042 | // op: RST |
6043 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6044 | op &= UINT64_C(31); |
6045 | op <<= 21; |
6046 | Value |= op; |
6047 | // op: RB |
6048 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6049 | op &= UINT64_C(31); |
6050 | op <<= 11; |
6051 | Value |= op; |
6052 | break; |
6053 | } |
6054 | case PPC::MFFSCRNI: { |
6055 | // op: RST |
6056 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6057 | op &= UINT64_C(31); |
6058 | op <<= 21; |
6059 | Value |= op; |
6060 | // op: RM |
6061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6062 | op &= UINT64_C(3); |
6063 | op <<= 11; |
6064 | Value |= op; |
6065 | break; |
6066 | } |
6067 | case PPC::MFDCR: |
6068 | case PPC::MFPMR: |
6069 | case PPC::MFSPR: |
6070 | case PPC::MFSPR8: |
6071 | case PPC::MFTB: |
6072 | case PPC::MTDCR: { |
6073 | // op: RST |
6074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6075 | op &= UINT64_C(31); |
6076 | op <<= 21; |
6077 | Value |= op; |
6078 | // op: SPR |
6079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6080 | Value |= (op & UINT64_C(31)) << 16; |
6081 | Value |= (op & UINT64_C(992)) << 6; |
6082 | break; |
6083 | } |
6084 | case PPC::MTVRSAVEv: { |
6085 | // op: RST |
6086 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6087 | op &= UINT64_C(31); |
6088 | op <<= 21; |
6089 | Value |= op; |
6090 | break; |
6091 | } |
6092 | case PPC::MTOCRF: |
6093 | case PPC::MTOCRF8: { |
6094 | // op: RST |
6095 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6096 | op &= UINT64_C(31); |
6097 | op <<= 21; |
6098 | Value |= op; |
6099 | // op: FXM |
6100 | op = get_crbitm_encoding(MI, OpNo: 0, Fixups, STI); |
6101 | op &= UINT64_C(255); |
6102 | op <<= 12; |
6103 | Value |= op; |
6104 | break; |
6105 | } |
6106 | case PPC::STBUX: |
6107 | case PPC::STBUX8: |
6108 | case PPC::STDUX: |
6109 | case PPC::STFDUX: |
6110 | case PPC::STFSUX: |
6111 | case PPC::STHUX: |
6112 | case PPC::STHUX8: |
6113 | case PPC::STWUX: |
6114 | case PPC::STWUX8: { |
6115 | // op: RST |
6116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6117 | op &= UINT64_C(31); |
6118 | op <<= 21; |
6119 | Value |= op; |
6120 | // op: RA |
6121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6122 | op &= UINT64_C(31); |
6123 | op <<= 16; |
6124 | Value |= op; |
6125 | // op: RB |
6126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6127 | op &= UINT64_C(31); |
6128 | op <<= 11; |
6129 | Value |= op; |
6130 | break; |
6131 | } |
6132 | case PPC::STBU: |
6133 | case PPC::STBU8: |
6134 | case PPC::STFDU: |
6135 | case PPC::STFSU: |
6136 | case PPC::STHU: |
6137 | case PPC::STHU8: |
6138 | case PPC::STWU: |
6139 | case PPC::STWU8: { |
6140 | // op: RST |
6141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6142 | op &= UINT64_C(31); |
6143 | op <<= 21; |
6144 | Value |= op; |
6145 | // op: RA |
6146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6147 | op &= UINT64_C(31); |
6148 | op <<= 16; |
6149 | Value |= op; |
6150 | // op: D |
6151 | op = getDispRIEncoding(MI, OpNo: 2, Fixups, STI); |
6152 | op &= UINT64_C(65535); |
6153 | Value |= op; |
6154 | break; |
6155 | } |
6156 | case PPC::STDU: { |
6157 | // op: RST |
6158 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6159 | op &= UINT64_C(31); |
6160 | op <<= 21; |
6161 | Value |= op; |
6162 | // op: RA |
6163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6164 | op &= UINT64_C(31); |
6165 | op <<= 16; |
6166 | Value |= op; |
6167 | // op: D |
6168 | op = getDispRIXEncoding(MI, OpNo: 2, Fixups, STI); |
6169 | op &= UINT64_C(16383); |
6170 | op <<= 2; |
6171 | Value |= op; |
6172 | break; |
6173 | } |
6174 | case PPC::MTPMR: |
6175 | case PPC::MTSPR: |
6176 | case PPC::MTSPR8: { |
6177 | // op: RST |
6178 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6179 | op &= UINT64_C(31); |
6180 | op <<= 21; |
6181 | Value |= op; |
6182 | // op: SPR |
6183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6184 | Value |= (op & UINT64_C(31)) << 16; |
6185 | Value |= (op & UINT64_C(992)) << 6; |
6186 | break; |
6187 | } |
6188 | case PPC::MFCR: |
6189 | case PPC::MFCR8: { |
6190 | // op: RT |
6191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6192 | op &= UINT64_C(31); |
6193 | op <<= 21; |
6194 | Value |= op; |
6195 | break; |
6196 | } |
6197 | case PPC::SETB: |
6198 | case PPC::SETB8: { |
6199 | // op: RT |
6200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6201 | op &= UINT64_C(31); |
6202 | op <<= 21; |
6203 | Value |= op; |
6204 | // op: BFA |
6205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6206 | op &= UINT64_C(7); |
6207 | op <<= 18; |
6208 | Value |= op; |
6209 | break; |
6210 | } |
6211 | case PPC::MTVSRBMI: { |
6212 | // op: RT |
6213 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6214 | op &= UINT64_C(31); |
6215 | op <<= 21; |
6216 | Value |= op; |
6217 | // op: D |
6218 | op = getImm16Encoding(MI, OpNo: 1, Fixups, STI); |
6219 | Value |= (op & UINT64_C(62)) << 15; |
6220 | Value |= (op & UINT64_C(65472)); |
6221 | Value |= (op & UINT64_C(1)); |
6222 | break; |
6223 | } |
6224 | case PPC::ADDPCIS: { |
6225 | // op: RT |
6226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6227 | op &= UINT64_C(31); |
6228 | op <<= 21; |
6229 | Value |= op; |
6230 | // op: D |
6231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6232 | Value |= (op & UINT64_C(62)) << 15; |
6233 | Value |= (op & UINT64_C(65472)); |
6234 | Value |= (op & UINT64_C(1)); |
6235 | break; |
6236 | } |
6237 | case PPC::DARN: { |
6238 | // op: RT |
6239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6240 | op &= UINT64_C(31); |
6241 | op <<= 21; |
6242 | Value |= op; |
6243 | // op: L |
6244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6245 | op &= UINT64_C(3); |
6246 | op <<= 16; |
6247 | Value |= op; |
6248 | break; |
6249 | } |
6250 | case PPC::ADDME: |
6251 | case PPC::ADDME8: |
6252 | case PPC::ADDME8O: |
6253 | case PPC::ADDME8O_rec: |
6254 | case PPC::ADDME8_rec: |
6255 | case PPC::ADDMEO: |
6256 | case PPC::ADDMEO_rec: |
6257 | case PPC::ADDME_rec: |
6258 | case PPC::ADDZE: |
6259 | case PPC::ADDZE8: |
6260 | case PPC::ADDZE8O: |
6261 | case PPC::ADDZE8O_rec: |
6262 | case PPC::ADDZE8_rec: |
6263 | case PPC::ADDZEO: |
6264 | case PPC::ADDZEO_rec: |
6265 | case PPC::ADDZE_rec: |
6266 | case PPC::EFDABS: |
6267 | case PPC::EFDNABS: |
6268 | case PPC::EFDNEG: |
6269 | case PPC::EFSABS: |
6270 | case PPC::EFSNABS: |
6271 | case PPC::EFSNEG: |
6272 | case PPC::EVABS: |
6273 | case PPC::EVADDSMIAAW: |
6274 | case PPC::EVADDSSIAAW: |
6275 | case PPC::EVADDUMIAAW: |
6276 | case PPC::EVADDUSIAAW: |
6277 | case PPC::EVCNTLSW: |
6278 | case PPC::EVCNTLZW: |
6279 | case PPC::EVEXTSB: |
6280 | case PPC::EVEXTSH: |
6281 | case PPC::EVFSABS: |
6282 | case PPC::EVFSNABS: |
6283 | case PPC::EVFSNEG: |
6284 | case PPC::EVMRA: |
6285 | case PPC::EVNEG: |
6286 | case PPC::EVRNDW: |
6287 | case PPC::EVSPLATFI: |
6288 | case PPC::EVSPLATI: |
6289 | case PPC::EVSUBFSMIAAW: |
6290 | case PPC::EVSUBFSSIAAW: |
6291 | case PPC::EVSUBFUMIAAW: |
6292 | case PPC::EVSUBFUSIAAW: |
6293 | case PPC::NEG: |
6294 | case PPC::NEG8: |
6295 | case PPC::NEG8O: |
6296 | case PPC::NEG8O_rec: |
6297 | case PPC::NEG8_rec: |
6298 | case PPC::NEGO: |
6299 | case PPC::NEGO_rec: |
6300 | case PPC::NEG_rec: |
6301 | case PPC::SUBFME: |
6302 | case PPC::SUBFME8: |
6303 | case PPC::SUBFME8O: |
6304 | case PPC::SUBFME8O_rec: |
6305 | case PPC::SUBFME8_rec: |
6306 | case PPC::SUBFMEO: |
6307 | case PPC::SUBFMEO_rec: |
6308 | case PPC::SUBFME_rec: |
6309 | case PPC::SUBFZE: |
6310 | case PPC::SUBFZE8: |
6311 | case PPC::SUBFZE8O: |
6312 | case PPC::SUBFZE8O_rec: |
6313 | case PPC::SUBFZE8_rec: |
6314 | case PPC::SUBFZEO: |
6315 | case PPC::SUBFZEO_rec: |
6316 | case PPC::SUBFZE_rec: { |
6317 | // op: RT |
6318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6319 | op &= UINT64_C(31); |
6320 | op <<= 21; |
6321 | Value |= op; |
6322 | // op: RA |
6323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6324 | op &= UINT64_C(31); |
6325 | op <<= 16; |
6326 | Value |= op; |
6327 | break; |
6328 | } |
6329 | case PPC::ADD4: |
6330 | case PPC::ADD4O: |
6331 | case PPC::ADD4O_rec: |
6332 | case PPC::ADD4_rec: |
6333 | case PPC::ADD8: |
6334 | case PPC::ADD8O: |
6335 | case PPC::ADD8O_rec: |
6336 | case PPC::ADD8_rec: |
6337 | case PPC::ADDC: |
6338 | case PPC::ADDC8: |
6339 | case PPC::ADDC8O: |
6340 | case PPC::ADDC8O_rec: |
6341 | case PPC::ADDC8_rec: |
6342 | case PPC::ADDCO: |
6343 | case PPC::ADDCO_rec: |
6344 | case PPC::ADDC_rec: |
6345 | case PPC::ADDE: |
6346 | case PPC::ADDE8: |
6347 | case PPC::ADDE8O: |
6348 | case PPC::ADDE8O_rec: |
6349 | case PPC::ADDE8_rec: |
6350 | case PPC::ADDEO: |
6351 | case PPC::ADDEO_rec: |
6352 | case PPC::ADDE_rec: |
6353 | case PPC::ADDG6S: |
6354 | case PPC::ADDG6S8: |
6355 | case PPC::BRINC: |
6356 | case PPC::DIVD: |
6357 | case PPC::DIVDE: |
6358 | case PPC::DIVDEO: |
6359 | case PPC::DIVDEO_rec: |
6360 | case PPC::DIVDEU: |
6361 | case PPC::DIVDEUO: |
6362 | case PPC::DIVDEUO_rec: |
6363 | case PPC::DIVDEU_rec: |
6364 | case PPC::DIVDE_rec: |
6365 | case PPC::DIVDO: |
6366 | case PPC::DIVDO_rec: |
6367 | case PPC::DIVDU: |
6368 | case PPC::DIVDUO: |
6369 | case PPC::DIVDUO_rec: |
6370 | case PPC::DIVDU_rec: |
6371 | case PPC::DIVD_rec: |
6372 | case PPC::DIVW: |
6373 | case PPC::DIVWE: |
6374 | case PPC::DIVWEO: |
6375 | case PPC::DIVWEO_rec: |
6376 | case PPC::DIVWEU: |
6377 | case PPC::DIVWEUO: |
6378 | case PPC::DIVWEUO_rec: |
6379 | case PPC::DIVWEU_rec: |
6380 | case PPC::DIVWE_rec: |
6381 | case PPC::DIVWO: |
6382 | case PPC::DIVWO_rec: |
6383 | case PPC::DIVWU: |
6384 | case PPC::DIVWUO: |
6385 | case PPC::DIVWUO_rec: |
6386 | case PPC::DIVWU_rec: |
6387 | case PPC::DIVW_rec: |
6388 | case PPC::EFDADD: |
6389 | case PPC::EFDDIV: |
6390 | case PPC::EFDMUL: |
6391 | case PPC::EFDSUB: |
6392 | case PPC::EFSADD: |
6393 | case PPC::EFSDIV: |
6394 | case PPC::EFSMUL: |
6395 | case PPC::EFSSUB: |
6396 | case PPC::EVADDIW: |
6397 | case PPC::EVADDW: |
6398 | case PPC::EVAND: |
6399 | case PPC::EVANDC: |
6400 | case PPC::EVDIVWS: |
6401 | case PPC::EVDIVWU: |
6402 | case PPC::EVEQV: |
6403 | case PPC::EVFSADD: |
6404 | case PPC::EVFSDIV: |
6405 | case PPC::EVFSMUL: |
6406 | case PPC::EVFSSUB: |
6407 | case PPC::EVLDDX: |
6408 | case PPC::EVLDHX: |
6409 | case PPC::EVLDWX: |
6410 | case PPC::EVLHHESPLATX: |
6411 | case PPC::EVLHHOSSPLATX: |
6412 | case PPC::EVLHHOUSPLATX: |
6413 | case PPC::EVLWHEX: |
6414 | case PPC::EVLWHOSX: |
6415 | case PPC::EVLWHOUX: |
6416 | case PPC::EVLWHSPLATX: |
6417 | case PPC::EVLWWSPLATX: |
6418 | case PPC::EVMERGEHI: |
6419 | case PPC::EVMERGEHILO: |
6420 | case PPC::EVMERGELO: |
6421 | case PPC::EVMERGELOHI: |
6422 | case PPC::EVMHEGSMFAA: |
6423 | case PPC::EVMHEGSMFAN: |
6424 | case PPC::EVMHEGSMIAA: |
6425 | case PPC::EVMHEGSMIAN: |
6426 | case PPC::EVMHEGUMIAA: |
6427 | case PPC::EVMHEGUMIAN: |
6428 | case PPC::EVMHESMF: |
6429 | case PPC::EVMHESMFA: |
6430 | case PPC::EVMHESMFAAW: |
6431 | case PPC::EVMHESMFANW: |
6432 | case PPC::EVMHESMI: |
6433 | case PPC::EVMHESMIA: |
6434 | case PPC::EVMHESMIAAW: |
6435 | case PPC::EVMHESMIANW: |
6436 | case PPC::EVMHESSF: |
6437 | case PPC::EVMHESSFA: |
6438 | case PPC::EVMHESSFAAW: |
6439 | case PPC::EVMHESSFANW: |
6440 | case PPC::EVMHESSIAAW: |
6441 | case PPC::EVMHESSIANW: |
6442 | case PPC::EVMHEUMI: |
6443 | case PPC::EVMHEUMIA: |
6444 | case PPC::EVMHEUMIAAW: |
6445 | case PPC::EVMHEUMIANW: |
6446 | case PPC::EVMHEUSIAAW: |
6447 | case PPC::EVMHEUSIANW: |
6448 | case PPC::EVMHOGSMFAA: |
6449 | case PPC::EVMHOGSMFAN: |
6450 | case PPC::EVMHOGSMIAA: |
6451 | case PPC::EVMHOGSMIAN: |
6452 | case PPC::EVMHOGUMIAA: |
6453 | case PPC::EVMHOGUMIAN: |
6454 | case PPC::EVMHOSMF: |
6455 | case PPC::EVMHOSMFA: |
6456 | case PPC::EVMHOSMFAAW: |
6457 | case PPC::EVMHOSMFANW: |
6458 | case PPC::EVMHOSMI: |
6459 | case PPC::EVMHOSMIA: |
6460 | case PPC::EVMHOSMIAAW: |
6461 | case PPC::EVMHOSMIANW: |
6462 | case PPC::EVMHOSSF: |
6463 | case PPC::EVMHOSSFA: |
6464 | case PPC::EVMHOSSFAAW: |
6465 | case PPC::EVMHOSSFANW: |
6466 | case PPC::EVMHOSSIAAW: |
6467 | case PPC::EVMHOSSIANW: |
6468 | case PPC::EVMHOUMI: |
6469 | case PPC::EVMHOUMIA: |
6470 | case PPC::EVMHOUMIAAW: |
6471 | case PPC::EVMHOUMIANW: |
6472 | case PPC::EVMHOUSIAAW: |
6473 | case PPC::EVMHOUSIANW: |
6474 | case PPC::EVMWHSMF: |
6475 | case PPC::EVMWHSMFA: |
6476 | case PPC::EVMWHSMI: |
6477 | case PPC::EVMWHSMIA: |
6478 | case PPC::EVMWHSSF: |
6479 | case PPC::EVMWHSSFA: |
6480 | case PPC::EVMWHUMI: |
6481 | case PPC::EVMWHUMIA: |
6482 | case PPC::EVMWLSMIAAW: |
6483 | case PPC::EVMWLSMIANW: |
6484 | case PPC::EVMWLSSIAAW: |
6485 | case PPC::EVMWLSSIANW: |
6486 | case PPC::EVMWLUMI: |
6487 | case PPC::EVMWLUMIA: |
6488 | case PPC::EVMWLUMIAAW: |
6489 | case PPC::EVMWLUMIANW: |
6490 | case PPC::EVMWLUSIAAW: |
6491 | case PPC::EVMWLUSIANW: |
6492 | case PPC::EVMWSMF: |
6493 | case PPC::EVMWSMFA: |
6494 | case PPC::EVMWSMFAA: |
6495 | case PPC::EVMWSMFAN: |
6496 | case PPC::EVMWSMI: |
6497 | case PPC::EVMWSMIA: |
6498 | case PPC::EVMWSMIAA: |
6499 | case PPC::EVMWSMIAN: |
6500 | case PPC::EVMWSSF: |
6501 | case PPC::EVMWSSFA: |
6502 | case PPC::EVMWSSFAA: |
6503 | case PPC::EVMWSSFAN: |
6504 | case PPC::EVMWUMI: |
6505 | case PPC::EVMWUMIA: |
6506 | case PPC::EVMWUMIAA: |
6507 | case PPC::EVMWUMIAN: |
6508 | case PPC::EVNAND: |
6509 | case PPC::EVNOR: |
6510 | case PPC::EVOR: |
6511 | case PPC::EVORC: |
6512 | case PPC::EVRLW: |
6513 | case PPC::EVRLWI: |
6514 | case PPC::EVSLW: |
6515 | case PPC::EVSLWI: |
6516 | case PPC::EVSRWIS: |
6517 | case PPC::EVSRWIU: |
6518 | case PPC::EVSRWS: |
6519 | case PPC::EVSRWU: |
6520 | case PPC::EVSTDDX: |
6521 | case PPC::EVSTDHX: |
6522 | case PPC::EVSTDWX: |
6523 | case PPC::EVSTWHEX: |
6524 | case PPC::EVSTWHOX: |
6525 | case PPC::EVSTWWEX: |
6526 | case PPC::EVSTWWOX: |
6527 | case PPC::EVSUBFW: |
6528 | case PPC::EVSUBIFW: |
6529 | case PPC::EVXOR: |
6530 | case PPC::MULHD: |
6531 | case PPC::MULHDU: |
6532 | case PPC::MULHDU_rec: |
6533 | case PPC::MULHD_rec: |
6534 | case PPC::MULHW: |
6535 | case PPC::MULHWU: |
6536 | case PPC::MULHWU_rec: |
6537 | case PPC::MULHW_rec: |
6538 | case PPC::MULLD: |
6539 | case PPC::MULLDO: |
6540 | case PPC::MULLDO_rec: |
6541 | case PPC::MULLD_rec: |
6542 | case PPC::MULLW: |
6543 | case PPC::MULLWO: |
6544 | case PPC::MULLWO_rec: |
6545 | case PPC::MULLW_rec: |
6546 | case PPC::SUBF: |
6547 | case PPC::SUBF8: |
6548 | case PPC::SUBF8O: |
6549 | case PPC::SUBF8O_rec: |
6550 | case PPC::SUBF8_rec: |
6551 | case PPC::SUBFC: |
6552 | case PPC::SUBFC8: |
6553 | case PPC::SUBFC8O: |
6554 | case PPC::SUBFC8O_rec: |
6555 | case PPC::SUBFC8_rec: |
6556 | case PPC::SUBFCO: |
6557 | case PPC::SUBFCO_rec: |
6558 | case PPC::SUBFC_rec: |
6559 | case PPC::SUBFE: |
6560 | case PPC::SUBFE8: |
6561 | case PPC::SUBFE8O: |
6562 | case PPC::SUBFE8O_rec: |
6563 | case PPC::SUBFE8_rec: |
6564 | case PPC::SUBFEO: |
6565 | case PPC::SUBFEO_rec: |
6566 | case PPC::SUBFE_rec: |
6567 | case PPC::SUBFO: |
6568 | case PPC::SUBFO_rec: |
6569 | case PPC::SUBF_rec: { |
6570 | // op: RT |
6571 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6572 | op &= UINT64_C(31); |
6573 | op <<= 21; |
6574 | Value |= op; |
6575 | // op: RA |
6576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6577 | op &= UINT64_C(31); |
6578 | op <<= 16; |
6579 | Value |= op; |
6580 | // op: RB |
6581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6582 | op &= UINT64_C(31); |
6583 | op <<= 11; |
6584 | Value |= op; |
6585 | break; |
6586 | } |
6587 | case PPC::ISEL: |
6588 | case PPC::ISEL8: { |
6589 | // op: RT |
6590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6591 | op &= UINT64_C(31); |
6592 | op <<= 21; |
6593 | Value |= op; |
6594 | // op: RA |
6595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6596 | op &= UINT64_C(31); |
6597 | op <<= 16; |
6598 | Value |= op; |
6599 | // op: RB |
6600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6601 | op &= UINT64_C(31); |
6602 | op <<= 11; |
6603 | Value |= op; |
6604 | // op: COND |
6605 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6606 | op &= UINT64_C(31); |
6607 | op <<= 6; |
6608 | Value |= op; |
6609 | break; |
6610 | } |
6611 | case PPC::ADDEX: |
6612 | case PPC::ADDEX8: { |
6613 | // op: RT |
6614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6615 | op &= UINT64_C(31); |
6616 | op <<= 21; |
6617 | Value |= op; |
6618 | // op: RA |
6619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6620 | op &= UINT64_C(31); |
6621 | op <<= 16; |
6622 | Value |= op; |
6623 | // op: RB |
6624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6625 | op &= UINT64_C(31); |
6626 | op <<= 11; |
6627 | Value |= op; |
6628 | // op: CY |
6629 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6630 | op &= UINT64_C(3); |
6631 | op <<= 9; |
6632 | Value |= op; |
6633 | break; |
6634 | } |
6635 | case PPC::SUBFUS: |
6636 | case PPC::SUBFUS_rec: { |
6637 | // op: RT |
6638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6639 | op &= UINT64_C(31); |
6640 | op <<= 21; |
6641 | Value |= op; |
6642 | // op: RA |
6643 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6644 | op &= UINT64_C(31); |
6645 | op <<= 16; |
6646 | Value |= op; |
6647 | // op: RB |
6648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6649 | op &= UINT64_C(31); |
6650 | op <<= 11; |
6651 | Value |= op; |
6652 | // op: L |
6653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6654 | op &= UINT64_C(1); |
6655 | op <<= 10; |
6656 | Value |= op; |
6657 | break; |
6658 | } |
6659 | case PPC::MADDHD: |
6660 | case PPC::MADDHDU: |
6661 | case PPC::MADDLD: |
6662 | case PPC::MADDLD8: |
6663 | case PPC::VADDECUQ: |
6664 | case PPC::VADDEUQM: |
6665 | case PPC::VEXTDDVLX: |
6666 | case PPC::VEXTDDVRX: |
6667 | case PPC::VEXTDUBVLX: |
6668 | case PPC::VEXTDUBVRX: |
6669 | case PPC::VEXTDUHVLX: |
6670 | case PPC::VEXTDUHVRX: |
6671 | case PPC::VEXTDUWVLX: |
6672 | case PPC::VEXTDUWVRX: |
6673 | case PPC::VMHADDSHS: |
6674 | case PPC::VMHRADDSHS: |
6675 | case PPC::VMLADDUHM: |
6676 | case PPC::VMSUMCUD: |
6677 | case PPC::VMSUMMBM: |
6678 | case PPC::VMSUMSHM: |
6679 | case PPC::VMSUMSHS: |
6680 | case PPC::VMSUMUBM: |
6681 | case PPC::VMSUMUDM: |
6682 | case PPC::VMSUMUHM: |
6683 | case PPC::VMSUMUHS: |
6684 | case PPC::VPERM: |
6685 | case PPC::VPERMR: |
6686 | case PPC::VSEL: |
6687 | case PPC::VSUBECUQ: |
6688 | case PPC::VSUBEUQM: { |
6689 | // op: RT |
6690 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6691 | op &= UINT64_C(31); |
6692 | op <<= 21; |
6693 | Value |= op; |
6694 | // op: RA |
6695 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6696 | op &= UINT64_C(31); |
6697 | op <<= 16; |
6698 | Value |= op; |
6699 | // op: RB |
6700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6701 | op &= UINT64_C(31); |
6702 | op <<= 11; |
6703 | Value |= op; |
6704 | // op: RC |
6705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6706 | op &= UINT64_C(31); |
6707 | op <<= 6; |
6708 | Value |= op; |
6709 | break; |
6710 | } |
6711 | case PPC::VSLDOI: { |
6712 | // op: RT |
6713 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6714 | op &= UINT64_C(31); |
6715 | op <<= 21; |
6716 | Value |= op; |
6717 | // op: RA |
6718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6719 | op &= UINT64_C(31); |
6720 | op <<= 16; |
6721 | Value |= op; |
6722 | // op: RB |
6723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6724 | op &= UINT64_C(31); |
6725 | op <<= 11; |
6726 | Value |= op; |
6727 | // op: SH |
6728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6729 | op &= UINT64_C(15); |
6730 | op <<= 6; |
6731 | Value |= op; |
6732 | break; |
6733 | } |
6734 | case PPC::ADD4TLS: |
6735 | case PPC::ADD8TLS: |
6736 | case PPC::ADD8TLS_: { |
6737 | // op: RT |
6738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6739 | op &= UINT64_C(31); |
6740 | op <<= 21; |
6741 | Value |= op; |
6742 | // op: RA |
6743 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6744 | op &= UINT64_C(31); |
6745 | op <<= 16; |
6746 | Value |= op; |
6747 | // op: RB |
6748 | op = getTLSRegEncoding(MI, OpNo: 2, Fixups, STI); |
6749 | op &= UINT64_C(31); |
6750 | op <<= 11; |
6751 | Value |= op; |
6752 | break; |
6753 | } |
6754 | case PPC::VMADDFP: |
6755 | case PPC::VNMSUBFP: { |
6756 | // op: RT |
6757 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6758 | op &= UINT64_C(31); |
6759 | op <<= 21; |
6760 | Value |= op; |
6761 | // op: RA |
6762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6763 | op &= UINT64_C(31); |
6764 | op <<= 16; |
6765 | Value |= op; |
6766 | // op: RC |
6767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6768 | op &= UINT64_C(31); |
6769 | op <<= 6; |
6770 | Value |= op; |
6771 | // op: RB |
6772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6773 | op &= UINT64_C(31); |
6774 | op <<= 11; |
6775 | Value |= op; |
6776 | break; |
6777 | } |
6778 | case PPC::VPERMXOR: { |
6779 | // op: RT |
6780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6781 | op &= UINT64_C(31); |
6782 | op <<= 21; |
6783 | Value |= op; |
6784 | // op: RA |
6785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6786 | op &= UINT64_C(31); |
6787 | op <<= 16; |
6788 | Value |= op; |
6789 | // op: RC |
6790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
6791 | op &= UINT64_C(31); |
6792 | op <<= 6; |
6793 | Value |= op; |
6794 | // op: RB |
6795 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6796 | op &= UINT64_C(31); |
6797 | op <<= 11; |
6798 | Value |= op; |
6799 | break; |
6800 | } |
6801 | case PPC::PADDI: |
6802 | case PPC::PADDI8: { |
6803 | // op: RT |
6804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6805 | op &= UINT64_C(31); |
6806 | op <<= 21; |
6807 | Value |= op; |
6808 | // op: RA |
6809 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6810 | op &= UINT64_C(31); |
6811 | op <<= 16; |
6812 | Value |= op; |
6813 | // op: SI |
6814 | op = getImm34EncodingNoPCRel(MI, OpNo: 2, Fixups, STI); |
6815 | Value |= (op & UINT64_C(17179803648)) << 16; |
6816 | Value |= (op & UINT64_C(65535)); |
6817 | break; |
6818 | } |
6819 | case PPC::PADDI8pc: |
6820 | case PPC::PADDIpc: { |
6821 | // op: RT |
6822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6823 | op &= UINT64_C(31); |
6824 | op <<= 21; |
6825 | Value |= op; |
6826 | // op: RA |
6827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6828 | op &= UINT64_C(31); |
6829 | op <<= 16; |
6830 | Value |= op; |
6831 | // op: SI |
6832 | op = getImm34EncodingPCRel(MI, OpNo: 2, Fixups, STI); |
6833 | Value |= (op & UINT64_C(17179803648)) << 16; |
6834 | Value |= (op & UINT64_C(65535)); |
6835 | break; |
6836 | } |
6837 | case PPC::EVLHHESPLAT: |
6838 | case PPC::EVLHHOSSPLAT: |
6839 | case PPC::EVLHHOUSPLAT: { |
6840 | // op: RT |
6841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6842 | op &= UINT64_C(31); |
6843 | op <<= 21; |
6844 | Value |= op; |
6845 | // op: RA |
6846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6847 | op &= UINT64_C(31); |
6848 | op <<= 16; |
6849 | Value |= op; |
6850 | // op: D |
6851 | op = getDispSPE2Encoding(MI, OpNo: 1, Fixups, STI); |
6852 | op &= UINT64_C(31); |
6853 | op <<= 11; |
6854 | Value |= op; |
6855 | break; |
6856 | } |
6857 | case PPC::EVLWHE: |
6858 | case PPC::EVLWHOS: |
6859 | case PPC::EVLWHOU: |
6860 | case PPC::EVLWHSPLAT: |
6861 | case PPC::EVLWWSPLAT: |
6862 | case PPC::EVSTWHE: |
6863 | case PPC::EVSTWHO: |
6864 | case PPC::EVSTWWE: |
6865 | case PPC::EVSTWWO: { |
6866 | // op: RT |
6867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6868 | op &= UINT64_C(31); |
6869 | op <<= 21; |
6870 | Value |= op; |
6871 | // op: RA |
6872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6873 | op &= UINT64_C(31); |
6874 | op <<= 16; |
6875 | Value |= op; |
6876 | // op: D |
6877 | op = getDispSPE4Encoding(MI, OpNo: 1, Fixups, STI); |
6878 | op &= UINT64_C(31); |
6879 | op <<= 11; |
6880 | Value |= op; |
6881 | break; |
6882 | } |
6883 | case PPC::EVLDD: |
6884 | case PPC::EVLDH: |
6885 | case PPC::EVLDW: |
6886 | case PPC::EVSTDD: |
6887 | case PPC::EVSTDH: |
6888 | case PPC::EVSTDW: { |
6889 | // op: RT |
6890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6891 | op &= UINT64_C(31); |
6892 | op <<= 21; |
6893 | Value |= op; |
6894 | // op: RA |
6895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
6896 | op &= UINT64_C(31); |
6897 | op <<= 16; |
6898 | Value |= op; |
6899 | // op: D |
6900 | op = getDispSPE8Encoding(MI, OpNo: 1, Fixups, STI); |
6901 | op &= UINT64_C(31); |
6902 | op <<= 11; |
6903 | Value |= op; |
6904 | break; |
6905 | } |
6906 | case PPC::EFDCFS: |
6907 | case PPC::EFDCFSF: |
6908 | case PPC::EFDCFSI: |
6909 | case PPC::EFDCFSID: |
6910 | case PPC::EFDCFUF: |
6911 | case PPC::EFDCFUI: |
6912 | case PPC::EFDCFUID: |
6913 | case PPC::EFDCTSF: |
6914 | case PPC::EFDCTSI: |
6915 | case PPC::EFDCTSIDZ: |
6916 | case PPC::EFDCTSIZ: |
6917 | case PPC::EFDCTUF: |
6918 | case PPC::EFDCTUI: |
6919 | case PPC::EFDCTUIDZ: |
6920 | case PPC::EFDCTUIZ: |
6921 | case PPC::EFSCFD: |
6922 | case PPC::EFSCFSF: |
6923 | case PPC::EFSCFSI: |
6924 | case PPC::EFSCFUF: |
6925 | case PPC::EFSCFUI: |
6926 | case PPC::EFSCTSF: |
6927 | case PPC::EFSCTSI: |
6928 | case PPC::EFSCTSIZ: |
6929 | case PPC::EFSCTUF: |
6930 | case PPC::EFSCTUI: |
6931 | case PPC::EFSCTUIZ: |
6932 | case PPC::EVFSCFSF: |
6933 | case PPC::EVFSCFSI: |
6934 | case PPC::EVFSCFUF: |
6935 | case PPC::EVFSCFUI: |
6936 | case PPC::EVFSCTSF: |
6937 | case PPC::EVFSCTSI: |
6938 | case PPC::EVFSCTSIZ: |
6939 | case PPC::EVFSCTUF: |
6940 | case PPC::EVFSCTUI: |
6941 | case PPC::EVFSCTUIZ: |
6942 | case PPC::SLBMFEV: { |
6943 | // op: RT |
6944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6945 | op &= UINT64_C(31); |
6946 | op <<= 21; |
6947 | Value |= op; |
6948 | // op: RB |
6949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
6950 | op &= UINT64_C(31); |
6951 | op <<= 11; |
6952 | Value |= op; |
6953 | break; |
6954 | } |
6955 | case PPC::PLI: |
6956 | case PPC::PLI8: { |
6957 | // op: RT |
6958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6959 | op &= UINT64_C(31); |
6960 | op <<= 21; |
6961 | Value |= op; |
6962 | // op: SI |
6963 | op = getImm34EncodingNoPCRel(MI, OpNo: 1, Fixups, STI); |
6964 | Value |= (op & UINT64_C(17179803648)) << 16; |
6965 | Value |= (op & UINT64_C(65535)); |
6966 | break; |
6967 | } |
6968 | case PPC::PLA: |
6969 | case PPC::PLA8: { |
6970 | // op: RT |
6971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6972 | op &= UINT64_C(31); |
6973 | op <<= 21; |
6974 | Value |= op; |
6975 | // op: SI |
6976 | op = getImm34EncodingNoPCRel(MI, OpNo: 2, Fixups, STI); |
6977 | Value |= (op & UINT64_C(17179803648)) << 16; |
6978 | Value |= (op & UINT64_C(65535)); |
6979 | break; |
6980 | } |
6981 | case PPC::PLA8pc: |
6982 | case PPC::PLApc: { |
6983 | // op: RT |
6984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6985 | op &= UINT64_C(31); |
6986 | op <<= 21; |
6987 | Value |= op; |
6988 | // op: SI |
6989 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
6990 | Value |= (op & UINT64_C(17179803648)) << 16; |
6991 | Value |= (op & UINT64_C(65535)); |
6992 | break; |
6993 | } |
6994 | case PPC::XSXEXPDP: |
6995 | case PPC::XSXSIGDP: { |
6996 | // op: RT |
6997 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
6998 | op &= UINT64_C(31); |
6999 | op <<= 21; |
7000 | Value |= op; |
7001 | // op: XB |
7002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7003 | Value |= (op & UINT64_C(31)) << 11; |
7004 | Value |= (op & UINT64_C(32)) >> 4; |
7005 | break; |
7006 | } |
7007 | case PPC::MFBHRBE: { |
7008 | // op: RT |
7009 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7010 | op &= UINT64_C(31); |
7011 | op <<= 21; |
7012 | Value |= op; |
7013 | // op: imm |
7014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7015 | op &= UINT64_C(1023); |
7016 | op <<= 11; |
7017 | Value |= op; |
7018 | break; |
7019 | } |
7020 | case PPC::LQ: { |
7021 | // op: RTp |
7022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7023 | op &= UINT64_C(31); |
7024 | op <<= 21; |
7025 | Value |= op; |
7026 | // op: RA |
7027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7028 | op &= UINT64_C(31); |
7029 | op <<= 16; |
7030 | Value |= op; |
7031 | // op: DQ |
7032 | op = getDispRIX16Encoding(MI, OpNo: 1, Fixups, STI); |
7033 | op &= UINT64_C(4095); |
7034 | op <<= 4; |
7035 | Value |= op; |
7036 | break; |
7037 | } |
7038 | case PPC::RFEBB: { |
7039 | // op: S |
7040 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7041 | op &= UINT64_C(1); |
7042 | op <<= 11; |
7043 | Value |= op; |
7044 | break; |
7045 | } |
7046 | case PPC::DENBCD: |
7047 | case PPC::DENBCDQ: |
7048 | case PPC::DENBCDQ_rec: |
7049 | case PPC::DENBCD_rec: { |
7050 | // op: S |
7051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7052 | op &= UINT64_C(1); |
7053 | op <<= 20; |
7054 | Value |= op; |
7055 | // op: FRT |
7056 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7057 | op &= UINT64_C(31); |
7058 | op <<= 21; |
7059 | Value |= op; |
7060 | // op: FRB |
7061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7062 | op &= UINT64_C(31); |
7063 | op <<= 11; |
7064 | Value |= op; |
7065 | break; |
7066 | } |
7067 | case PPC::DDEDPD: |
7068 | case PPC::DDEDPDQ: |
7069 | case PPC::DDEDPDQ_rec: |
7070 | case PPC::DDEDPD_rec: { |
7071 | // op: SP |
7072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7073 | op &= UINT64_C(3); |
7074 | op <<= 19; |
7075 | Value |= op; |
7076 | // op: FRT |
7077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7078 | op &= UINT64_C(31); |
7079 | op <<= 21; |
7080 | Value |= op; |
7081 | // op: FRB |
7082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7083 | op &= UINT64_C(31); |
7084 | op <<= 11; |
7085 | Value |= op; |
7086 | break; |
7087 | } |
7088 | case PPC::DSS: { |
7089 | // op: STRM |
7090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7091 | op &= UINT64_C(3); |
7092 | op <<= 21; |
7093 | Value |= op; |
7094 | break; |
7095 | } |
7096 | case PPC::DST: |
7097 | case PPC::DST64: |
7098 | case PPC::DSTST: |
7099 | case PPC::DSTST64: |
7100 | case PPC::DSTSTT: |
7101 | case PPC::DSTSTT64: |
7102 | case PPC::DSTT: |
7103 | case PPC::DSTT64: { |
7104 | // op: STRM |
7105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7106 | op &= UINT64_C(3); |
7107 | op <<= 21; |
7108 | Value |= op; |
7109 | // op: RA |
7110 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7111 | op &= UINT64_C(31); |
7112 | op <<= 16; |
7113 | Value |= op; |
7114 | // op: RB |
7115 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7116 | op &= UINT64_C(31); |
7117 | op <<= 11; |
7118 | Value |= op; |
7119 | break; |
7120 | } |
7121 | case PPC::DCBF: |
7122 | case PPC::DCBT: |
7123 | case PPC::DCBTST: { |
7124 | // op: TH |
7125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7126 | op &= UINT64_C(31); |
7127 | op <<= 21; |
7128 | Value |= op; |
7129 | // op: RA |
7130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7131 | op &= UINT64_C(31); |
7132 | op <<= 16; |
7133 | Value |= op; |
7134 | // op: RB |
7135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7136 | op &= UINT64_C(31); |
7137 | op <<= 11; |
7138 | Value |= op; |
7139 | break; |
7140 | } |
7141 | case PPC::DCBTEP: |
7142 | case PPC::DCBTSTEP: { |
7143 | // op: TH |
7144 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7145 | op &= UINT64_C(31); |
7146 | op <<= 21; |
7147 | Value |= op; |
7148 | // op: RA |
7149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7150 | op &= UINT64_C(31); |
7151 | op <<= 16; |
7152 | Value |= op; |
7153 | // op: RB |
7154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7155 | op &= UINT64_C(31); |
7156 | op <<= 11; |
7157 | Value |= op; |
7158 | break; |
7159 | } |
7160 | case PPC::MTVSCR: { |
7161 | // op: VB |
7162 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7163 | op &= UINT64_C(31); |
7164 | op <<= 11; |
7165 | Value |= op; |
7166 | break; |
7167 | } |
7168 | case PPC::V_SET0: |
7169 | case PPC::V_SET0B: |
7170 | case PPC::V_SET0H: { |
7171 | // op: VD |
7172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7173 | Value |= (op & UINT64_C(31)) << 21; |
7174 | Value |= (op & UINT64_C(31)) << 16; |
7175 | Value |= (op & UINT64_C(31)) << 11; |
7176 | break; |
7177 | } |
7178 | case PPC::MFVSCR: |
7179 | case PPC::V_SETALLONES: |
7180 | case PPC::V_SETALLONESB: |
7181 | case PPC::V_SETALLONESH: { |
7182 | // op: VD |
7183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7184 | op &= UINT64_C(31); |
7185 | op <<= 21; |
7186 | Value |= op; |
7187 | break; |
7188 | } |
7189 | case PPC::VSPLTISB: |
7190 | case PPC::VSPLTISH: |
7191 | case PPC::VSPLTISW: { |
7192 | // op: VD |
7193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7194 | op &= UINT64_C(31); |
7195 | op <<= 21; |
7196 | Value |= op; |
7197 | // op: IMM |
7198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7199 | op &= UINT64_C(31); |
7200 | op <<= 16; |
7201 | Value |= op; |
7202 | break; |
7203 | } |
7204 | case PPC::VMUL10CUQ: |
7205 | case PPC::VMUL10UQ: |
7206 | case PPC::VSBOX: { |
7207 | // op: VD |
7208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7209 | op &= UINT64_C(31); |
7210 | op <<= 21; |
7211 | Value |= op; |
7212 | // op: VA |
7213 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7214 | op &= UINT64_C(31); |
7215 | op <<= 16; |
7216 | Value |= op; |
7217 | break; |
7218 | } |
7219 | case PPC::VSHASIGMAD: |
7220 | case PPC::VSHASIGMAW: { |
7221 | // op: VD |
7222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7223 | op &= UINT64_C(31); |
7224 | op <<= 21; |
7225 | Value |= op; |
7226 | // op: VA |
7227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7228 | op &= UINT64_C(31); |
7229 | op <<= 16; |
7230 | Value |= op; |
7231 | // op: ST |
7232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7233 | op &= UINT64_C(1); |
7234 | op <<= 15; |
7235 | Value |= op; |
7236 | // op: SIX |
7237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
7238 | op &= UINT64_C(15); |
7239 | op <<= 11; |
7240 | Value |= op; |
7241 | break; |
7242 | } |
7243 | case PPC::BCDCPSGN_rec: |
7244 | case PPC::BCDUS_rec: |
7245 | case PPC::BCDUTRUNC_rec: |
7246 | case PPC::VABSDUB: |
7247 | case PPC::VABSDUH: |
7248 | case PPC::VABSDUW: |
7249 | case PPC::VADDCUQ: |
7250 | case PPC::VADDCUW: |
7251 | case PPC::VADDFP: |
7252 | case PPC::VADDSBS: |
7253 | case PPC::VADDSHS: |
7254 | case PPC::VADDSWS: |
7255 | case PPC::VADDUBM: |
7256 | case PPC::VADDUBS: |
7257 | case PPC::VADDUDM: |
7258 | case PPC::VADDUHM: |
7259 | case PPC::VADDUHS: |
7260 | case PPC::VADDUQM: |
7261 | case PPC::VADDUWM: |
7262 | case PPC::VADDUWS: |
7263 | case PPC::VAND: |
7264 | case PPC::VANDC: |
7265 | case PPC::VAVGSB: |
7266 | case PPC::VAVGSH: |
7267 | case PPC::VAVGSW: |
7268 | case PPC::VAVGUB: |
7269 | case PPC::VAVGUH: |
7270 | case PPC::VAVGUW: |
7271 | case PPC::VBPERMD: |
7272 | case PPC::VBPERMQ: |
7273 | case PPC::VCFSX: |
7274 | case PPC::VCFUGED: |
7275 | case PPC::VCFUX: |
7276 | case PPC::VCIPHER: |
7277 | case PPC::VCIPHERLAST: |
7278 | case PPC::VCLRLB: |
7279 | case PPC::VCLRRB: |
7280 | case PPC::VCLZDM: |
7281 | case PPC::VCMPBFP: |
7282 | case PPC::VCMPBFP_rec: |
7283 | case PPC::VCMPEQFP: |
7284 | case PPC::VCMPEQFP_rec: |
7285 | case PPC::VCMPEQUB: |
7286 | case PPC::VCMPEQUB_rec: |
7287 | case PPC::VCMPEQUD: |
7288 | case PPC::VCMPEQUD_rec: |
7289 | case PPC::VCMPEQUH: |
7290 | case PPC::VCMPEQUH_rec: |
7291 | case PPC::VCMPEQUQ: |
7292 | case PPC::VCMPEQUQ_rec: |
7293 | case PPC::VCMPEQUW: |
7294 | case PPC::VCMPEQUW_rec: |
7295 | case PPC::VCMPGEFP: |
7296 | case PPC::VCMPGEFP_rec: |
7297 | case PPC::VCMPGTFP: |
7298 | case PPC::VCMPGTFP_rec: |
7299 | case PPC::VCMPGTSB: |
7300 | case PPC::VCMPGTSB_rec: |
7301 | case PPC::VCMPGTSD: |
7302 | case PPC::VCMPGTSD_rec: |
7303 | case PPC::VCMPGTSH: |
7304 | case PPC::VCMPGTSH_rec: |
7305 | case PPC::VCMPGTSQ: |
7306 | case PPC::VCMPGTSQ_rec: |
7307 | case PPC::VCMPGTSW: |
7308 | case PPC::VCMPGTSW_rec: |
7309 | case PPC::VCMPGTUB: |
7310 | case PPC::VCMPGTUB_rec: |
7311 | case PPC::VCMPGTUD: |
7312 | case PPC::VCMPGTUD_rec: |
7313 | case PPC::VCMPGTUH: |
7314 | case PPC::VCMPGTUH_rec: |
7315 | case PPC::VCMPGTUQ: |
7316 | case PPC::VCMPGTUQ_rec: |
7317 | case PPC::VCMPGTUW: |
7318 | case PPC::VCMPGTUW_rec: |
7319 | case PPC::VCMPNEB: |
7320 | case PPC::VCMPNEB_rec: |
7321 | case PPC::VCMPNEH: |
7322 | case PPC::VCMPNEH_rec: |
7323 | case PPC::VCMPNEW: |
7324 | case PPC::VCMPNEW_rec: |
7325 | case PPC::VCMPNEZB: |
7326 | case PPC::VCMPNEZB_rec: |
7327 | case PPC::VCMPNEZH: |
7328 | case PPC::VCMPNEZH_rec: |
7329 | case PPC::VCMPNEZW: |
7330 | case PPC::VCMPNEZW_rec: |
7331 | case PPC::VCTSXS: |
7332 | case PPC::VCTUXS: |
7333 | case PPC::VCTZDM: |
7334 | case PPC::VDIVESD: |
7335 | case PPC::VDIVESQ: |
7336 | case PPC::VDIVESW: |
7337 | case PPC::VDIVEUD: |
7338 | case PPC::VDIVEUQ: |
7339 | case PPC::VDIVEUW: |
7340 | case PPC::VDIVSD: |
7341 | case PPC::VDIVSQ: |
7342 | case PPC::VDIVSW: |
7343 | case PPC::VDIVUD: |
7344 | case PPC::VDIVUQ: |
7345 | case PPC::VDIVUW: |
7346 | case PPC::VEQV: |
7347 | case PPC::VEXTRACTD: |
7348 | case PPC::VEXTRACTUB: |
7349 | case PPC::VEXTRACTUH: |
7350 | case PPC::VEXTRACTUW: |
7351 | case PPC::VEXTUBLX: |
7352 | case PPC::VEXTUBRX: |
7353 | case PPC::VEXTUHLX: |
7354 | case PPC::VEXTUHRX: |
7355 | case PPC::VEXTUWLX: |
7356 | case PPC::VEXTUWRX: |
7357 | case PPC::VINSERTD: |
7358 | case PPC::VINSERTW: |
7359 | case PPC::VMAXFP: |
7360 | case PPC::VMAXSB: |
7361 | case PPC::VMAXSD: |
7362 | case PPC::VMAXSH: |
7363 | case PPC::VMAXSW: |
7364 | case PPC::VMAXUB: |
7365 | case PPC::VMAXUD: |
7366 | case PPC::VMAXUH: |
7367 | case PPC::VMAXUW: |
7368 | case PPC::VMINFP: |
7369 | case PPC::VMINSB: |
7370 | case PPC::VMINSD: |
7371 | case PPC::VMINSH: |
7372 | case PPC::VMINSW: |
7373 | case PPC::VMINUB: |
7374 | case PPC::VMINUD: |
7375 | case PPC::VMINUH: |
7376 | case PPC::VMINUW: |
7377 | case PPC::VMODSD: |
7378 | case PPC::VMODSQ: |
7379 | case PPC::VMODSW: |
7380 | case PPC::VMODUD: |
7381 | case PPC::VMODUQ: |
7382 | case PPC::VMODUW: |
7383 | case PPC::VMRGEW: |
7384 | case PPC::VMRGHB: |
7385 | case PPC::VMRGHH: |
7386 | case PPC::VMRGHW: |
7387 | case PPC::VMRGLB: |
7388 | case PPC::VMRGLH: |
7389 | case PPC::VMRGLW: |
7390 | case PPC::VMRGOW: |
7391 | case PPC::VMUL10ECUQ: |
7392 | case PPC::VMUL10EUQ: |
7393 | case PPC::VMULESB: |
7394 | case PPC::VMULESD: |
7395 | case PPC::VMULESH: |
7396 | case PPC::VMULESW: |
7397 | case PPC::VMULEUB: |
7398 | case PPC::VMULEUD: |
7399 | case PPC::VMULEUH: |
7400 | case PPC::VMULEUW: |
7401 | case PPC::VMULHSD: |
7402 | case PPC::VMULHSW: |
7403 | case PPC::VMULHUD: |
7404 | case PPC::VMULHUW: |
7405 | case PPC::VMULLD: |
7406 | case PPC::VMULOSB: |
7407 | case PPC::VMULOSD: |
7408 | case PPC::VMULOSH: |
7409 | case PPC::VMULOSW: |
7410 | case PPC::VMULOUB: |
7411 | case PPC::VMULOUD: |
7412 | case PPC::VMULOUH: |
7413 | case PPC::VMULOUW: |
7414 | case PPC::VMULUWM: |
7415 | case PPC::VNAND: |
7416 | case PPC::VNCIPHER: |
7417 | case PPC::VNCIPHERLAST: |
7418 | case PPC::VNOR: |
7419 | case PPC::VOR: |
7420 | case PPC::VORC: |
7421 | case PPC::VPDEPD: |
7422 | case PPC::VPEXTD: |
7423 | case PPC::VPKPX: |
7424 | case PPC::VPKSDSS: |
7425 | case PPC::VPKSDUS: |
7426 | case PPC::VPKSHSS: |
7427 | case PPC::VPKSHUS: |
7428 | case PPC::VPKSWSS: |
7429 | case PPC::VPKSWUS: |
7430 | case PPC::VPKUDUM: |
7431 | case PPC::VPKUDUS: |
7432 | case PPC::VPKUHUM: |
7433 | case PPC::VPKUHUS: |
7434 | case PPC::VPKUWUM: |
7435 | case PPC::VPKUWUS: |
7436 | case PPC::VPMSUMB: |
7437 | case PPC::VPMSUMD: |
7438 | case PPC::VPMSUMH: |
7439 | case PPC::VPMSUMW: |
7440 | case PPC::VRLB: |
7441 | case PPC::VRLD: |
7442 | case PPC::VRLDMI: |
7443 | case PPC::VRLDNM: |
7444 | case PPC::VRLH: |
7445 | case PPC::VRLQ: |
7446 | case PPC::VRLQMI: |
7447 | case PPC::VRLQNM: |
7448 | case PPC::VRLW: |
7449 | case PPC::VRLWMI: |
7450 | case PPC::VRLWNM: |
7451 | case PPC::VSL: |
7452 | case PPC::VSLB: |
7453 | case PPC::VSLD: |
7454 | case PPC::VSLH: |
7455 | case PPC::VSLO: |
7456 | case PPC::VSLQ: |
7457 | case PPC::VSLV: |
7458 | case PPC::VSLW: |
7459 | case PPC::VSPLTB: |
7460 | case PPC::VSPLTBs: |
7461 | case PPC::VSPLTH: |
7462 | case PPC::VSPLTHs: |
7463 | case PPC::VSPLTW: |
7464 | case PPC::VSR: |
7465 | case PPC::VSRAB: |
7466 | case PPC::VSRAD: |
7467 | case PPC::VSRAH: |
7468 | case PPC::VSRAQ: |
7469 | case PPC::VSRAW: |
7470 | case PPC::VSRB: |
7471 | case PPC::VSRD: |
7472 | case PPC::VSRH: |
7473 | case PPC::VSRO: |
7474 | case PPC::VSRQ: |
7475 | case PPC::VSRV: |
7476 | case PPC::VSRW: |
7477 | case PPC::VSUBCUQ: |
7478 | case PPC::VSUBCUW: |
7479 | case PPC::VSUBFP: |
7480 | case PPC::VSUBSBS: |
7481 | case PPC::VSUBSHS: |
7482 | case PPC::VSUBSWS: |
7483 | case PPC::VSUBUBM: |
7484 | case PPC::VSUBUBS: |
7485 | case PPC::VSUBUDM: |
7486 | case PPC::VSUBUHM: |
7487 | case PPC::VSUBUHS: |
7488 | case PPC::VSUBUQM: |
7489 | case PPC::VSUBUWM: |
7490 | case PPC::VSUBUWS: |
7491 | case PPC::VSUM2SWS: |
7492 | case PPC::VSUM4SBS: |
7493 | case PPC::VSUM4SHS: |
7494 | case PPC::VSUM4UBS: |
7495 | case PPC::VSUMSWS: |
7496 | case PPC::VXOR: { |
7497 | // op: VD |
7498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7499 | op &= UINT64_C(31); |
7500 | op <<= 21; |
7501 | Value |= op; |
7502 | // op: VA |
7503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7504 | op &= UINT64_C(31); |
7505 | op <<= 16; |
7506 | Value |= op; |
7507 | // op: VB |
7508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7509 | op &= UINT64_C(31); |
7510 | op <<= 11; |
7511 | Value |= op; |
7512 | break; |
7513 | } |
7514 | case PPC::BCDADD_rec: |
7515 | case PPC::BCDSR_rec: |
7516 | case PPC::BCDSUB_rec: |
7517 | case PPC::BCDS_rec: |
7518 | case PPC::BCDTRUNC_rec: { |
7519 | // op: VD |
7520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7521 | op &= UINT64_C(31); |
7522 | op <<= 21; |
7523 | Value |= op; |
7524 | // op: VA |
7525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7526 | op &= UINT64_C(31); |
7527 | op <<= 16; |
7528 | Value |= op; |
7529 | // op: VB |
7530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7531 | op &= UINT64_C(31); |
7532 | op <<= 11; |
7533 | Value |= op; |
7534 | // op: PS |
7535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
7536 | op &= UINT64_C(1); |
7537 | op <<= 9; |
7538 | Value |= op; |
7539 | break; |
7540 | } |
7541 | case PPC::VINSBLX: |
7542 | case PPC::VINSBRX: |
7543 | case PPC::VINSBVLX: |
7544 | case PPC::VINSBVRX: |
7545 | case PPC::VINSD: |
7546 | case PPC::VINSDLX: |
7547 | case PPC::VINSDRX: |
7548 | case PPC::VINSERTB: |
7549 | case PPC::VINSERTH: |
7550 | case PPC::VINSHLX: |
7551 | case PPC::VINSHRX: |
7552 | case PPC::VINSHVLX: |
7553 | case PPC::VINSHVRX: |
7554 | case PPC::VINSW: |
7555 | case PPC::VINSWLX: |
7556 | case PPC::VINSWRX: |
7557 | case PPC::VINSWVLX: |
7558 | case PPC::VINSWVRX: { |
7559 | // op: VD |
7560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7561 | op &= UINT64_C(31); |
7562 | op <<= 21; |
7563 | Value |= op; |
7564 | // op: VA |
7565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7566 | op &= UINT64_C(31); |
7567 | op <<= 16; |
7568 | Value |= op; |
7569 | // op: VB |
7570 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
7571 | op &= UINT64_C(31); |
7572 | op <<= 11; |
7573 | Value |= op; |
7574 | break; |
7575 | } |
7576 | case PPC::BCDCTN_rec: |
7577 | case PPC::BCDCTSQ_rec: |
7578 | case PPC::MTVSRBM: |
7579 | case PPC::MTVSRDM: |
7580 | case PPC::MTVSRHM: |
7581 | case PPC::MTVSRQM: |
7582 | case PPC::MTVSRWM: |
7583 | case PPC::VCFSX_0: |
7584 | case PPC::VCFUX_0: |
7585 | case PPC::VCLZB: |
7586 | case PPC::VCLZD: |
7587 | case PPC::VCLZH: |
7588 | case PPC::VCLZLSBB: |
7589 | case PPC::VCLZW: |
7590 | case PPC::VCTSXS_0: |
7591 | case PPC::VCTUXS_0: |
7592 | case PPC::VCTZB: |
7593 | case PPC::VCTZD: |
7594 | case PPC::VCTZH: |
7595 | case PPC::VCTZLSBB: |
7596 | case PPC::VCTZW: |
7597 | case PPC::VEXPANDBM: |
7598 | case PPC::VEXPANDDM: |
7599 | case PPC::VEXPANDHM: |
7600 | case PPC::VEXPANDQM: |
7601 | case PPC::VEXPANDWM: |
7602 | case PPC::VEXPTEFP: |
7603 | case PPC::VEXTRACTBM: |
7604 | case PPC::VEXTRACTDM: |
7605 | case PPC::VEXTRACTHM: |
7606 | case PPC::VEXTRACTQM: |
7607 | case PPC::VEXTRACTWM: |
7608 | case PPC::VEXTSB2D: |
7609 | case PPC::VEXTSB2Ds: |
7610 | case PPC::VEXTSB2W: |
7611 | case PPC::VEXTSB2Ws: |
7612 | case PPC::VEXTSD2Q: |
7613 | case PPC::VEXTSH2D: |
7614 | case PPC::VEXTSH2Ds: |
7615 | case PPC::VEXTSH2W: |
7616 | case PPC::VEXTSH2Ws: |
7617 | case PPC::VEXTSW2D: |
7618 | case PPC::VEXTSW2Ds: |
7619 | case PPC::VGBBD: |
7620 | case PPC::VLOGEFP: |
7621 | case PPC::VNEGD: |
7622 | case PPC::VNEGW: |
7623 | case PPC::VPOPCNTB: |
7624 | case PPC::VPOPCNTD: |
7625 | case PPC::VPOPCNTH: |
7626 | case PPC::VPOPCNTW: |
7627 | case PPC::VPRTYBD: |
7628 | case PPC::VPRTYBQ: |
7629 | case PPC::VPRTYBW: |
7630 | case PPC::VREFP: |
7631 | case PPC::VRFIM: |
7632 | case PPC::VRFIN: |
7633 | case PPC::VRFIP: |
7634 | case PPC::VRFIZ: |
7635 | case PPC::VRSQRTEFP: |
7636 | case PPC::VUPKHPX: |
7637 | case PPC::VUPKHSB: |
7638 | case PPC::VUPKHSH: |
7639 | case PPC::VUPKHSW: |
7640 | case PPC::VUPKLPX: |
7641 | case PPC::VUPKLSB: |
7642 | case PPC::VUPKLSH: |
7643 | case PPC::VUPKLSW: { |
7644 | // op: VD |
7645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7646 | op &= UINT64_C(31); |
7647 | op <<= 21; |
7648 | Value |= op; |
7649 | // op: VB |
7650 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7651 | op &= UINT64_C(31); |
7652 | op <<= 11; |
7653 | Value |= op; |
7654 | break; |
7655 | } |
7656 | case PPC::BCDCFN_rec: |
7657 | case PPC::BCDCFSQ_rec: |
7658 | case PPC::BCDCFZ_rec: |
7659 | case PPC::BCDCTZ_rec: |
7660 | case PPC::BCDSETSGN_rec: { |
7661 | // op: VD |
7662 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7663 | op &= UINT64_C(31); |
7664 | op <<= 21; |
7665 | Value |= op; |
7666 | // op: VB |
7667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7668 | op &= UINT64_C(31); |
7669 | op <<= 11; |
7670 | Value |= op; |
7671 | // op: PS |
7672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7673 | op &= UINT64_C(1); |
7674 | op <<= 9; |
7675 | Value |= op; |
7676 | break; |
7677 | } |
7678 | case PPC::XSRQPI: |
7679 | case PPC::XSRQPIX: |
7680 | case PPC::XSRQPXP: { |
7681 | // op: VRT |
7682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7683 | op &= UINT64_C(31); |
7684 | op <<= 21; |
7685 | Value |= op; |
7686 | // op: R |
7687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7688 | op &= UINT64_C(1); |
7689 | op <<= 16; |
7690 | Value |= op; |
7691 | // op: VRB |
7692 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7693 | op &= UINT64_C(31); |
7694 | op <<= 11; |
7695 | Value |= op; |
7696 | // op: idx |
7697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
7698 | op &= UINT64_C(3); |
7699 | op <<= 9; |
7700 | Value |= op; |
7701 | break; |
7702 | } |
7703 | case PPC::VSLDBI: |
7704 | case PPC::VSRDBI: { |
7705 | // op: VRT |
7706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7707 | op &= UINT64_C(31); |
7708 | op <<= 21; |
7709 | Value |= op; |
7710 | // op: VRA |
7711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7712 | op &= UINT64_C(31); |
7713 | op <<= 16; |
7714 | Value |= op; |
7715 | // op: VRB |
7716 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7717 | op &= UINT64_C(31); |
7718 | op <<= 11; |
7719 | Value |= op; |
7720 | // op: SD |
7721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
7722 | op &= UINT64_C(7); |
7723 | op <<= 6; |
7724 | Value |= op; |
7725 | break; |
7726 | } |
7727 | case PPC::VSTRIBL: |
7728 | case PPC::VSTRIBL_rec: |
7729 | case PPC::VSTRIBR: |
7730 | case PPC::VSTRIBR_rec: |
7731 | case PPC::VSTRIHL: |
7732 | case PPC::VSTRIHL_rec: |
7733 | case PPC::VSTRIHR: |
7734 | case PPC::VSTRIHR_rec: { |
7735 | // op: VT |
7736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7737 | op &= UINT64_C(31); |
7738 | op <<= 21; |
7739 | Value |= op; |
7740 | // op: VB |
7741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7742 | op &= UINT64_C(31); |
7743 | op <<= 11; |
7744 | Value |= op; |
7745 | break; |
7746 | } |
7747 | case PPC::PLXVonlypc: |
7748 | case PPC::PSTXVonlypc: { |
7749 | // op: XST |
7750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7751 | op &= UINT64_C(63); |
7752 | op <<= 21; |
7753 | Value |= op; |
7754 | // op: D |
7755 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
7756 | Value |= (op & UINT64_C(17179803648)) << 16; |
7757 | Value |= (op & UINT64_C(65535)); |
7758 | break; |
7759 | } |
7760 | case PPC::PLXV: |
7761 | case PPC::PLXVnopc: |
7762 | case PPC::PSTXV: |
7763 | case PPC::PSTXVnopc: { |
7764 | // op: XST |
7765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7766 | op &= UINT64_C(63); |
7767 | op <<= 21; |
7768 | Value |= op; |
7769 | // op: RA |
7770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7771 | op &= UINT64_C(31); |
7772 | op <<= 16; |
7773 | Value |= op; |
7774 | // op: D |
7775 | op = getDispRI34Encoding(MI, OpNo: 1, Fixups, STI); |
7776 | Value |= (op & UINT64_C(17179803648)) << 16; |
7777 | Value |= (op & UINT64_C(65535)); |
7778 | break; |
7779 | } |
7780 | case PPC::PLXVpc: |
7781 | case PPC::PSTXVpc: { |
7782 | // op: XST |
7783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7784 | op &= UINT64_C(63); |
7785 | op <<= 21; |
7786 | Value |= op; |
7787 | // op: RA |
7788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7789 | op &= UINT64_C(31); |
7790 | op <<= 16; |
7791 | Value |= op; |
7792 | // op: D |
7793 | op = getDispRI34PCRelEncoding(MI, OpNo: 1, Fixups, STI); |
7794 | Value |= (op & UINT64_C(17179803648)) << 16; |
7795 | Value |= (op & UINT64_C(65535)); |
7796 | break; |
7797 | } |
7798 | case PPC::XXLEQVOnes: |
7799 | case PPC::XXLXORdpz: |
7800 | case PPC::XXLXORspz: |
7801 | case PPC::XXLXORz: { |
7802 | // op: XT |
7803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7804 | Value |= (op & UINT64_C(31)) << 21; |
7805 | Value |= (op & UINT64_C(31)) << 16; |
7806 | Value |= (op & UINT64_C(31)) << 11; |
7807 | Value |= (op & UINT64_C(32)) >> 3; |
7808 | Value |= (op & UINT64_C(32)) >> 4; |
7809 | Value |= (op & UINT64_C(32)) >> 5; |
7810 | break; |
7811 | } |
7812 | case PPC::XXSPLTIDP: |
7813 | case PPC::XXSPLTIW: { |
7814 | // op: XT |
7815 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7816 | Value |= (op & UINT64_C(31)) << 21; |
7817 | Value |= (op & UINT64_C(32)) << 11; |
7818 | // op: IMM32 |
7819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7820 | Value |= (op & UINT64_C(4294901760)) << 16; |
7821 | Value |= (op & UINT64_C(65535)); |
7822 | break; |
7823 | } |
7824 | case PPC::XXSPLTI32DX: { |
7825 | // op: XT |
7826 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7827 | Value |= (op & UINT64_C(31)) << 21; |
7828 | Value |= (op & UINT64_C(32)) << 11; |
7829 | // op: IX |
7830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7831 | op &= UINT64_C(1); |
7832 | op <<= 17; |
7833 | Value |= op; |
7834 | // op: IMM32 |
7835 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
7836 | Value |= (op & UINT64_C(4294901760)) << 16; |
7837 | Value |= (op & UINT64_C(65535)); |
7838 | break; |
7839 | } |
7840 | case PPC::LXV: |
7841 | case PPC::STXV: { |
7842 | // op: XT |
7843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7844 | Value |= (op & UINT64_C(31)) << 21; |
7845 | Value |= (op & UINT64_C(32)) >> 2; |
7846 | // op: RA |
7847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7848 | op &= UINT64_C(31); |
7849 | op <<= 16; |
7850 | Value |= op; |
7851 | // op: DQ |
7852 | op = getDispRIX16Encoding(MI, OpNo: 1, Fixups, STI); |
7853 | op &= UINT64_C(4095); |
7854 | op <<= 4; |
7855 | Value |= op; |
7856 | break; |
7857 | } |
7858 | case PPC::XVTSTDCDP: |
7859 | case PPC::XVTSTDCSP: { |
7860 | // op: XT |
7861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7862 | Value |= (op & UINT64_C(31)) << 21; |
7863 | Value |= (op & UINT64_C(32)) >> 5; |
7864 | // op: DCMX |
7865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7866 | Value |= (op & UINT64_C(31)) << 16; |
7867 | Value |= (op & UINT64_C(64)); |
7868 | Value |= (op & UINT64_C(32)) >> 3; |
7869 | // op: XB |
7870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7871 | Value |= (op & UINT64_C(31)) << 11; |
7872 | Value |= (op & UINT64_C(32)) >> 4; |
7873 | break; |
7874 | } |
7875 | case PPC::XXSPLTIB: { |
7876 | // op: XT |
7877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7878 | Value |= (op & UINT64_C(31)) << 21; |
7879 | Value |= (op & UINT64_C(32)) >> 5; |
7880 | // op: IMM8 |
7881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7882 | op &= UINT64_C(255); |
7883 | op <<= 11; |
7884 | Value |= op; |
7885 | break; |
7886 | } |
7887 | case PPC::MTVRD: |
7888 | case PPC::MTVRWA: |
7889 | case PPC::MTVRWZ: |
7890 | case PPC::MTVSRD: |
7891 | case PPC::MTVSRWA: |
7892 | case PPC::MTVSRWS: |
7893 | case PPC::MTVSRWZ: { |
7894 | // op: XT |
7895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7896 | Value |= (op & UINT64_C(31)) << 21; |
7897 | Value |= (op & UINT64_C(32)) >> 5; |
7898 | // op: RA |
7899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7900 | op &= UINT64_C(31); |
7901 | op <<= 16; |
7902 | Value |= op; |
7903 | break; |
7904 | } |
7905 | case PPC::LXSDX: |
7906 | case PPC::LXSIBZX: |
7907 | case PPC::LXSIHZX: |
7908 | case PPC::LXSIWAX: |
7909 | case PPC::LXSIWZX: |
7910 | case PPC::LXSSPX: |
7911 | case PPC::LXVB16X: |
7912 | case PPC::LXVD2X: |
7913 | case PPC::LXVDSX: |
7914 | case PPC::LXVH8X: |
7915 | case PPC::LXVL: |
7916 | case PPC::LXVLL: |
7917 | case PPC::LXVRBX: |
7918 | case PPC::LXVRDX: |
7919 | case PPC::LXVRHX: |
7920 | case PPC::LXVRL: |
7921 | case PPC::LXVRLL: |
7922 | case PPC::LXVRWX: |
7923 | case PPC::LXVW4X: |
7924 | case PPC::LXVWSX: |
7925 | case PPC::LXVX: |
7926 | case PPC::MTVSRDD: |
7927 | case PPC::STXSDX: |
7928 | case PPC::STXSIBX: |
7929 | case PPC::STXSIBXv: |
7930 | case PPC::STXSIHX: |
7931 | case PPC::STXSIHXv: |
7932 | case PPC::STXSIWX: |
7933 | case PPC::STXSSPX: |
7934 | case PPC::STXVB16X: |
7935 | case PPC::STXVD2X: |
7936 | case PPC::STXVH8X: |
7937 | case PPC::STXVL: |
7938 | case PPC::STXVLL: |
7939 | case PPC::STXVRBX: |
7940 | case PPC::STXVRDX: |
7941 | case PPC::STXVRHX: |
7942 | case PPC::STXVRL: |
7943 | case PPC::STXVRLL: |
7944 | case PPC::STXVRWX: |
7945 | case PPC::STXVW4X: |
7946 | case PPC::STXVX: |
7947 | case PPC::XSIEXPDP: { |
7948 | // op: XT |
7949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7950 | Value |= (op & UINT64_C(31)) << 21; |
7951 | Value |= (op & UINT64_C(32)) >> 5; |
7952 | // op: RA |
7953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7954 | op &= UINT64_C(31); |
7955 | op <<= 16; |
7956 | Value |= op; |
7957 | // op: RB |
7958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7959 | op &= UINT64_C(31); |
7960 | op <<= 11; |
7961 | Value |= op; |
7962 | break; |
7963 | } |
7964 | case PPC::LXVKQ: { |
7965 | // op: XT |
7966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7967 | Value |= (op & UINT64_C(31)) << 21; |
7968 | Value |= (op & UINT64_C(32)) >> 5; |
7969 | // op: UIM |
7970 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7971 | op &= UINT64_C(31); |
7972 | op <<= 11; |
7973 | Value |= op; |
7974 | break; |
7975 | } |
7976 | case PPC::XXGENPCVBM: |
7977 | case PPC::XXGENPCVDM: |
7978 | case PPC::XXGENPCVHM: |
7979 | case PPC::XXGENPCVWM: { |
7980 | // op: XT |
7981 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
7982 | Value |= (op & UINT64_C(31)) << 21; |
7983 | Value |= (op & UINT64_C(32)) >> 5; |
7984 | // op: VRB |
7985 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
7986 | op &= UINT64_C(31); |
7987 | op <<= 11; |
7988 | Value |= op; |
7989 | // op: IMM |
7990 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
7991 | op &= UINT64_C(31); |
7992 | op <<= 16; |
7993 | Value |= op; |
7994 | break; |
7995 | } |
7996 | case PPC::XXPERMDIs: |
7997 | case PPC::XXSLDWIs: { |
7998 | // op: XT |
7999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8000 | Value |= (op & UINT64_C(31)) << 21; |
8001 | Value |= (op & UINT64_C(32)) >> 5; |
8002 | // op: XA |
8003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8004 | Value |= (op & UINT64_C(31)) << 16; |
8005 | Value |= (op & UINT64_C(31)) << 11; |
8006 | Value |= (op & UINT64_C(32)) >> 3; |
8007 | Value |= (op & UINT64_C(32)) >> 4; |
8008 | // op: D |
8009 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8010 | op &= UINT64_C(3); |
8011 | op <<= 8; |
8012 | Value |= op; |
8013 | break; |
8014 | } |
8015 | case PPC::XSADDDP: |
8016 | case PPC::XSADDSP: |
8017 | case PPC::XSCMPEQDP: |
8018 | case PPC::XSCMPGEDP: |
8019 | case PPC::XSCMPGTDP: |
8020 | case PPC::XSCPSGNDP: |
8021 | case PPC::XSDIVDP: |
8022 | case PPC::XSDIVSP: |
8023 | case PPC::XSMAXCDP: |
8024 | case PPC::XSMAXDP: |
8025 | case PPC::XSMAXJDP: |
8026 | case PPC::XSMINCDP: |
8027 | case PPC::XSMINDP: |
8028 | case PPC::XSMINJDP: |
8029 | case PPC::XSMULDP: |
8030 | case PPC::XSMULSP: |
8031 | case PPC::XSSUBDP: |
8032 | case PPC::XSSUBSP: |
8033 | case PPC::XVADDDP: |
8034 | case PPC::XVADDSP: |
8035 | case PPC::XVCMPEQDP: |
8036 | case PPC::XVCMPEQDP_rec: |
8037 | case PPC::XVCMPEQSP: |
8038 | case PPC::XVCMPEQSP_rec: |
8039 | case PPC::XVCMPGEDP: |
8040 | case PPC::XVCMPGEDP_rec: |
8041 | case PPC::XVCMPGESP: |
8042 | case PPC::XVCMPGESP_rec: |
8043 | case PPC::XVCMPGTDP: |
8044 | case PPC::XVCMPGTDP_rec: |
8045 | case PPC::XVCMPGTSP: |
8046 | case PPC::XVCMPGTSP_rec: |
8047 | case PPC::XVCPSGNDP: |
8048 | case PPC::XVCPSGNSP: |
8049 | case PPC::XVDIVDP: |
8050 | case PPC::XVDIVSP: |
8051 | case PPC::XVIEXPDP: |
8052 | case PPC::XVIEXPSP: |
8053 | case PPC::XVMAXDP: |
8054 | case PPC::XVMAXSP: |
8055 | case PPC::XVMINDP: |
8056 | case PPC::XVMINSP: |
8057 | case PPC::XVMULDP: |
8058 | case PPC::XVMULSP: |
8059 | case PPC::XVSUBDP: |
8060 | case PPC::XVSUBSP: |
8061 | case PPC::XXLAND: |
8062 | case PPC::XXLANDC: |
8063 | case PPC::XXLEQV: |
8064 | case PPC::XXLNAND: |
8065 | case PPC::XXLNOR: |
8066 | case PPC::XXLOR: |
8067 | case PPC::XXLORC: |
8068 | case PPC::XXLORf: |
8069 | case PPC::XXLXOR: |
8070 | case PPC::XXMRGHW: |
8071 | case PPC::XXMRGLW: { |
8072 | // op: XT |
8073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8074 | Value |= (op & UINT64_C(31)) << 21; |
8075 | Value |= (op & UINT64_C(32)) >> 5; |
8076 | // op: XA |
8077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8078 | Value |= (op & UINT64_C(31)) << 16; |
8079 | Value |= (op & UINT64_C(32)) >> 3; |
8080 | // op: XB |
8081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8082 | Value |= (op & UINT64_C(31)) << 11; |
8083 | Value |= (op & UINT64_C(32)) >> 4; |
8084 | break; |
8085 | } |
8086 | case PPC::XXPERMDI: |
8087 | case PPC::XXSLDWI: { |
8088 | // op: XT |
8089 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8090 | Value |= (op & UINT64_C(31)) << 21; |
8091 | Value |= (op & UINT64_C(32)) >> 5; |
8092 | // op: XA |
8093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8094 | Value |= (op & UINT64_C(31)) << 16; |
8095 | Value |= (op & UINT64_C(32)) >> 3; |
8096 | // op: XB |
8097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8098 | Value |= (op & UINT64_C(31)) << 11; |
8099 | Value |= (op & UINT64_C(32)) >> 4; |
8100 | // op: D |
8101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8102 | op &= UINT64_C(3); |
8103 | op <<= 8; |
8104 | Value |= op; |
8105 | break; |
8106 | } |
8107 | case PPC::XXBLENDVB: |
8108 | case PPC::XXBLENDVD: |
8109 | case PPC::XXBLENDVH: |
8110 | case PPC::XXBLENDVW: |
8111 | case PPC::XXSEL: { |
8112 | // op: XT |
8113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8114 | Value |= (op & UINT64_C(31)) << 21; |
8115 | Value |= (op & UINT64_C(32)) >> 5; |
8116 | // op: XA |
8117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8118 | Value |= (op & UINT64_C(31)) << 16; |
8119 | Value |= (op & UINT64_C(32)) >> 3; |
8120 | // op: XB |
8121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8122 | Value |= (op & UINT64_C(31)) << 11; |
8123 | Value |= (op & UINT64_C(32)) >> 4; |
8124 | // op: XC |
8125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8126 | Value |= (op & UINT64_C(31)) << 6; |
8127 | Value |= (op & UINT64_C(32)) >> 2; |
8128 | break; |
8129 | } |
8130 | case PPC::XXEVAL: { |
8131 | // op: XT |
8132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8133 | Value |= (op & UINT64_C(31)) << 21; |
8134 | Value |= (op & UINT64_C(32)) >> 5; |
8135 | // op: XA |
8136 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8137 | Value |= (op & UINT64_C(31)) << 16; |
8138 | Value |= (op & UINT64_C(32)) >> 3; |
8139 | // op: XB |
8140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8141 | Value |= (op & UINT64_C(31)) << 11; |
8142 | Value |= (op & UINT64_C(32)) >> 4; |
8143 | // op: XC |
8144 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8145 | Value |= (op & UINT64_C(31)) << 6; |
8146 | Value |= (op & UINT64_C(32)) >> 2; |
8147 | // op: IMM |
8148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
8149 | op &= UINT64_C(255); |
8150 | op <<= 32; |
8151 | Value |= op; |
8152 | break; |
8153 | } |
8154 | case PPC::XXPERMX: { |
8155 | // op: XT |
8156 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8157 | Value |= (op & UINT64_C(31)) << 21; |
8158 | Value |= (op & UINT64_C(32)) >> 5; |
8159 | // op: XA |
8160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8161 | Value |= (op & UINT64_C(31)) << 16; |
8162 | Value |= (op & UINT64_C(32)) >> 3; |
8163 | // op: XB |
8164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8165 | Value |= (op & UINT64_C(31)) << 11; |
8166 | Value |= (op & UINT64_C(32)) >> 4; |
8167 | // op: XC |
8168 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8169 | Value |= (op & UINT64_C(31)) << 6; |
8170 | Value |= (op & UINT64_C(32)) >> 2; |
8171 | // op: IMM |
8172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
8173 | op &= UINT64_C(7); |
8174 | op <<= 32; |
8175 | Value |= op; |
8176 | break; |
8177 | } |
8178 | case PPC::XXPERM: |
8179 | case PPC::XXPERMR: { |
8180 | // op: XT |
8181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8182 | Value |= (op & UINT64_C(31)) << 21; |
8183 | Value |= (op & UINT64_C(32)) >> 5; |
8184 | // op: XA |
8185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8186 | Value |= (op & UINT64_C(31)) << 16; |
8187 | Value |= (op & UINT64_C(32)) >> 3; |
8188 | // op: XB |
8189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8190 | Value |= (op & UINT64_C(31)) << 11; |
8191 | Value |= (op & UINT64_C(32)) >> 4; |
8192 | break; |
8193 | } |
8194 | case PPC::XSMADDADP: |
8195 | case PPC::XSMADDASP: |
8196 | case PPC::XSMADDMDP: |
8197 | case PPC::XSMADDMSP: |
8198 | case PPC::XSMSUBADP: |
8199 | case PPC::XSMSUBASP: |
8200 | case PPC::XSMSUBMDP: |
8201 | case PPC::XSMSUBMSP: |
8202 | case PPC::XSNMADDADP: |
8203 | case PPC::XSNMADDASP: |
8204 | case PPC::XSNMADDMDP: |
8205 | case PPC::XSNMADDMSP: |
8206 | case PPC::XSNMSUBADP: |
8207 | case PPC::XSNMSUBASP: |
8208 | case PPC::XSNMSUBMDP: |
8209 | case PPC::XSNMSUBMSP: |
8210 | case PPC::XVMADDADP: |
8211 | case PPC::XVMADDASP: |
8212 | case PPC::XVMADDMDP: |
8213 | case PPC::XVMADDMSP: |
8214 | case PPC::XVMSUBADP: |
8215 | case PPC::XVMSUBASP: |
8216 | case PPC::XVMSUBMDP: |
8217 | case PPC::XVMSUBMSP: |
8218 | case PPC::XVNMADDADP: |
8219 | case PPC::XVNMADDASP: |
8220 | case PPC::XVNMADDMDP: |
8221 | case PPC::XVNMADDMSP: |
8222 | case PPC::XVNMSUBADP: |
8223 | case PPC::XVNMSUBASP: |
8224 | case PPC::XVNMSUBMDP: |
8225 | case PPC::XVNMSUBMSP: { |
8226 | // op: XT |
8227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8228 | Value |= (op & UINT64_C(31)) << 21; |
8229 | Value |= (op & UINT64_C(32)) >> 5; |
8230 | // op: XA |
8231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8232 | Value |= (op & UINT64_C(31)) << 16; |
8233 | Value |= (op & UINT64_C(32)) >> 3; |
8234 | // op: XB |
8235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8236 | Value |= (op & UINT64_C(31)) << 11; |
8237 | Value |= (op & UINT64_C(32)) >> 4; |
8238 | break; |
8239 | } |
8240 | case PPC::XSABSDP: |
8241 | case PPC::XSCVDPHP: |
8242 | case PPC::XSCVDPSP: |
8243 | case PPC::XSCVDPSPN: |
8244 | case PPC::XSCVDPSXDS: |
8245 | case PPC::XSCVDPSXDSs: |
8246 | case PPC::XSCVDPSXWS: |
8247 | case PPC::XSCVDPSXWSs: |
8248 | case PPC::XSCVDPUXDS: |
8249 | case PPC::XSCVDPUXDSs: |
8250 | case PPC::XSCVDPUXWS: |
8251 | case PPC::XSCVDPUXWSs: |
8252 | case PPC::XSCVHPDP: |
8253 | case PPC::XSCVSPDP: |
8254 | case PPC::XSCVSPDPN: |
8255 | case PPC::XSCVSXDDP: |
8256 | case PPC::XSCVSXDSP: |
8257 | case PPC::XSCVUXDDP: |
8258 | case PPC::XSCVUXDSP: |
8259 | case PPC::XSNABSDP: |
8260 | case PPC::XSNABSDPs: |
8261 | case PPC::XSNEGDP: |
8262 | case PPC::XSRDPI: |
8263 | case PPC::XSRDPIC: |
8264 | case PPC::XSRDPIM: |
8265 | case PPC::XSRDPIP: |
8266 | case PPC::XSRDPIZ: |
8267 | case PPC::XSREDP: |
8268 | case PPC::XSRESP: |
8269 | case PPC::XSRSP: |
8270 | case PPC::XSRSQRTEDP: |
8271 | case PPC::XSRSQRTESP: |
8272 | case PPC::XSSQRTDP: |
8273 | case PPC::XSSQRTSP: |
8274 | case PPC::XVABSDP: |
8275 | case PPC::XVABSSP: |
8276 | case PPC::XVCVBF16SPN: |
8277 | case PPC::XVCVDPSP: |
8278 | case PPC::XVCVDPSXDS: |
8279 | case PPC::XVCVDPSXWS: |
8280 | case PPC::XVCVDPUXDS: |
8281 | case PPC::XVCVDPUXWS: |
8282 | case PPC::XVCVHPSP: |
8283 | case PPC::XVCVSPBF16: |
8284 | case PPC::XVCVSPDP: |
8285 | case PPC::XVCVSPHP: |
8286 | case PPC::XVCVSPSXDS: |
8287 | case PPC::XVCVSPSXWS: |
8288 | case PPC::XVCVSPUXDS: |
8289 | case PPC::XVCVSPUXWS: |
8290 | case PPC::XVCVSXDDP: |
8291 | case PPC::XVCVSXDSP: |
8292 | case PPC::XVCVSXWDP: |
8293 | case PPC::XVCVSXWSP: |
8294 | case PPC::XVCVUXDDP: |
8295 | case PPC::XVCVUXDSP: |
8296 | case PPC::XVCVUXWDP: |
8297 | case PPC::XVCVUXWSP: |
8298 | case PPC::XVNABSDP: |
8299 | case PPC::XVNABSSP: |
8300 | case PPC::XVNEGDP: |
8301 | case PPC::XVNEGSP: |
8302 | case PPC::XVRDPI: |
8303 | case PPC::XVRDPIC: |
8304 | case PPC::XVRDPIM: |
8305 | case PPC::XVRDPIP: |
8306 | case PPC::XVRDPIZ: |
8307 | case PPC::XVREDP: |
8308 | case PPC::XVRESP: |
8309 | case PPC::XVRSPI: |
8310 | case PPC::XVRSPIC: |
8311 | case PPC::XVRSPIM: |
8312 | case PPC::XVRSPIP: |
8313 | case PPC::XVRSPIZ: |
8314 | case PPC::XVRSQRTEDP: |
8315 | case PPC::XVRSQRTESP: |
8316 | case PPC::XVSQRTDP: |
8317 | case PPC::XVSQRTSP: |
8318 | case PPC::XVXEXPDP: |
8319 | case PPC::XVXEXPSP: |
8320 | case PPC::XVXSIGDP: |
8321 | case PPC::XVXSIGSP: |
8322 | case PPC::XXBRD: |
8323 | case PPC::XXBRH: |
8324 | case PPC::XXBRQ: |
8325 | case PPC::XXBRW: { |
8326 | // op: XT |
8327 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8328 | Value |= (op & UINT64_C(31)) << 21; |
8329 | Value |= (op & UINT64_C(32)) >> 5; |
8330 | // op: XB |
8331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8332 | Value |= (op & UINT64_C(31)) << 11; |
8333 | Value |= (op & UINT64_C(32)) >> 4; |
8334 | break; |
8335 | } |
8336 | case PPC::XXSPLTW: |
8337 | case PPC::XXSPLTWs: { |
8338 | // op: XT |
8339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8340 | Value |= (op & UINT64_C(31)) << 21; |
8341 | Value |= (op & UINT64_C(32)) >> 5; |
8342 | // op: XB |
8343 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8344 | Value |= (op & UINT64_C(31)) << 11; |
8345 | Value |= (op & UINT64_C(32)) >> 4; |
8346 | // op: D |
8347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8348 | op &= UINT64_C(3); |
8349 | op <<= 16; |
8350 | Value |= op; |
8351 | break; |
8352 | } |
8353 | case PPC::XXEXTRACTUW: { |
8354 | // op: XT |
8355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8356 | Value |= (op & UINT64_C(31)) << 21; |
8357 | Value |= (op & UINT64_C(32)) >> 5; |
8358 | // op: XB |
8359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8360 | Value |= (op & UINT64_C(31)) << 11; |
8361 | Value |= (op & UINT64_C(32)) >> 4; |
8362 | // op: UIM5 |
8363 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8364 | op &= UINT64_C(31); |
8365 | op <<= 16; |
8366 | Value |= op; |
8367 | break; |
8368 | } |
8369 | case PPC::XXINSERTW: { |
8370 | // op: XT |
8371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8372 | Value |= (op & UINT64_C(31)) << 21; |
8373 | Value |= (op & UINT64_C(32)) >> 5; |
8374 | // op: XB |
8375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8376 | Value |= (op & UINT64_C(31)) << 11; |
8377 | Value |= (op & UINT64_C(32)) >> 4; |
8378 | // op: UIM5 |
8379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8380 | op &= UINT64_C(31); |
8381 | op <<= 16; |
8382 | Value |= op; |
8383 | break; |
8384 | } |
8385 | case PPC::MFVRD: |
8386 | case PPC::MFVRWZ: |
8387 | case PPC::MFVSRD: |
8388 | case PPC::MFVSRLD: |
8389 | case PPC::MFVSRWZ: { |
8390 | // op: XT |
8391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8392 | Value |= (op & UINT64_C(31)) << 21; |
8393 | Value |= (op & UINT64_C(32)) >> 5; |
8394 | // op: RA |
8395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8396 | op &= UINT64_C(31); |
8397 | op <<= 16; |
8398 | Value |= op; |
8399 | break; |
8400 | } |
8401 | case PPC::PLXVPonlypc: |
8402 | case PPC::PSTXVPonlypc: { |
8403 | // op: XTp |
8404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8405 | Value |= (op & UINT64_C(15)) << 22; |
8406 | Value |= (op & UINT64_C(16)) << 17; |
8407 | // op: D |
8408 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
8409 | Value |= (op & UINT64_C(17179803648)) << 16; |
8410 | Value |= (op & UINT64_C(65535)); |
8411 | break; |
8412 | } |
8413 | case PPC::LXVPRL: |
8414 | case PPC::LXVPRLL: |
8415 | case PPC::LXVPX: |
8416 | case PPC::STXVPRL: |
8417 | case PPC::STXVPRLL: |
8418 | case PPC::STXVPX: { |
8419 | // op: XTp |
8420 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8421 | Value |= (op & UINT64_C(15)) << 22; |
8422 | Value |= (op & UINT64_C(16)) << 17; |
8423 | // op: RA |
8424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8425 | op &= UINT64_C(31); |
8426 | op <<= 16; |
8427 | Value |= op; |
8428 | // op: RB |
8429 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8430 | op &= UINT64_C(31); |
8431 | op <<= 11; |
8432 | Value |= op; |
8433 | break; |
8434 | } |
8435 | case PPC::PLXVP: |
8436 | case PPC::PLXVPnopc: |
8437 | case PPC::PSTXVP: |
8438 | case PPC::PSTXVPnopc: { |
8439 | // op: XTp |
8440 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8441 | Value |= (op & UINT64_C(15)) << 22; |
8442 | Value |= (op & UINT64_C(16)) << 17; |
8443 | // op: RA |
8444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8445 | op &= UINT64_C(31); |
8446 | op <<= 16; |
8447 | Value |= op; |
8448 | // op: D |
8449 | op = getDispRI34Encoding(MI, OpNo: 1, Fixups, STI); |
8450 | Value |= (op & UINT64_C(17179803648)) << 16; |
8451 | Value |= (op & UINT64_C(65535)); |
8452 | break; |
8453 | } |
8454 | case PPC::PLXVPpc: |
8455 | case PPC::PSTXVPpc: { |
8456 | // op: XTp |
8457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8458 | Value |= (op & UINT64_C(15)) << 22; |
8459 | Value |= (op & UINT64_C(16)) << 17; |
8460 | // op: RA |
8461 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8462 | op &= UINT64_C(31); |
8463 | op <<= 16; |
8464 | Value |= op; |
8465 | // op: D |
8466 | op = getDispRI34PCRelEncoding(MI, OpNo: 1, Fixups, STI); |
8467 | Value |= (op & UINT64_C(17179803648)) << 16; |
8468 | Value |= (op & UINT64_C(65535)); |
8469 | break; |
8470 | } |
8471 | case PPC::LXVP: |
8472 | case PPC::STXVP: { |
8473 | // op: XTp |
8474 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8475 | Value |= (op & UINT64_C(15)) << 22; |
8476 | Value |= (op & UINT64_C(16)) << 17; |
8477 | // op: RA |
8478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8479 | op &= UINT64_C(31); |
8480 | op <<= 16; |
8481 | Value |= op; |
8482 | // op: DQ |
8483 | op = getDispRIX16Encoding(MI, OpNo: 1, Fixups, STI); |
8484 | op &= UINT64_C(4095); |
8485 | op <<= 4; |
8486 | Value |= op; |
8487 | break; |
8488 | } |
8489 | case PPC::EFDCMPEQ: |
8490 | case PPC::EFDCMPGT: |
8491 | case PPC::EFDCMPLT: |
8492 | case PPC::EFDTSTEQ: |
8493 | case PPC::EFDTSTGT: |
8494 | case PPC::EFDTSTLT: |
8495 | case PPC::EFSCMPEQ: |
8496 | case PPC::EFSCMPGT: |
8497 | case PPC::EFSCMPLT: |
8498 | case PPC::EFSTSTEQ: |
8499 | case PPC::EFSTSTGT: |
8500 | case PPC::EFSTSTLT: |
8501 | case PPC::EVCMPEQ: |
8502 | case PPC::EVCMPGTS: |
8503 | case PPC::EVCMPGTU: |
8504 | case PPC::EVCMPLTS: |
8505 | case PPC::EVCMPLTU: |
8506 | case PPC::EVFSCMPEQ: |
8507 | case PPC::EVFSCMPGT: |
8508 | case PPC::EVFSCMPLT: |
8509 | case PPC::EVFSTSTEQ: |
8510 | case PPC::EVFSTSTGT: |
8511 | case PPC::EVFSTSTLT: { |
8512 | // op: crD |
8513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8514 | op &= UINT64_C(7); |
8515 | op <<= 23; |
8516 | Value |= op; |
8517 | // op: RA |
8518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8519 | op &= UINT64_C(31); |
8520 | op <<= 16; |
8521 | Value |= op; |
8522 | // op: RB |
8523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8524 | op &= UINT64_C(31); |
8525 | op <<= 11; |
8526 | Value |= op; |
8527 | break; |
8528 | } |
8529 | case PPC::EVSEL: { |
8530 | // op: crD |
8531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
8532 | op &= UINT64_C(7); |
8533 | Value |= op; |
8534 | // op: RA |
8535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
8536 | op &= UINT64_C(31); |
8537 | op <<= 16; |
8538 | Value |= op; |
8539 | // op: RB |
8540 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
8541 | op &= UINT64_C(31); |
8542 | op <<= 11; |
8543 | Value |= op; |
8544 | // op: RT |
8545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
8546 | op &= UINT64_C(31); |
8547 | op <<= 21; |
8548 | Value |= op; |
8549 | break; |
8550 | } |
8551 | default: |
8552 | std::string msg; |
8553 | raw_string_ostream Msg(msg); |
8554 | Msg << "Not supported instr: " << MI; |
8555 | report_fatal_error(reason: Msg.str().c_str()); |
8556 | } |
8557 | return Value; |
8558 | } |
8559 | |
8560 | #ifdef GET_OPERAND_BIT_OFFSET |
8561 | #undef GET_OPERAND_BIT_OFFSET |
8562 | |
8563 | uint32_t PPCMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
8564 | unsigned OpNum, |
8565 | const MCSubtargetInfo &STI) const { |
8566 | switch (MI.getOpcode()) { |
8567 | case PPC::ADDISdtprelHA: |
8568 | case PPC::ADDISdtprelHA32: |
8569 | case PPC::ADDISgotTprelHA: |
8570 | case PPC::ADDIStlsgdHA: |
8571 | case PPC::ADDIStlsldHA: |
8572 | case PPC::ADDIStocHA: |
8573 | case PPC::ADDIStocHA8: |
8574 | case PPC::ADDIdtprelL: |
8575 | case PPC::ADDIdtprelL32: |
8576 | case PPC::ADDItlsgdL: |
8577 | case PPC::ADDItlsgdL32: |
8578 | case PPC::ADDItlsgdLADDR: |
8579 | case PPC::ADDItlsgdLADDR32: |
8580 | case PPC::ADDItlsldL: |
8581 | case PPC::ADDItlsldL32: |
8582 | case PPC::ADDItlsldLADDR: |
8583 | case PPC::ADDItlsldLADDR32: |
8584 | case PPC::ADDItoc: |
8585 | case PPC::ADDItoc8: |
8586 | case PPC::ADDItocL: |
8587 | case PPC::ADDItocL8: |
8588 | case PPC::ADJCALLSTACKDOWN: |
8589 | case PPC::ADJCALLSTACKUP: |
8590 | case PPC::ANDI_rec_1_EQ_BIT: |
8591 | case PPC::ANDI_rec_1_EQ_BIT8: |
8592 | case PPC::ANDI_rec_1_GT_BIT: |
8593 | case PPC::ANDI_rec_1_GT_BIT8: |
8594 | case PPC::ATOMIC_CMP_SWAP_I8: |
8595 | case PPC::ATOMIC_CMP_SWAP_I16: |
8596 | case PPC::ATOMIC_CMP_SWAP_I32: |
8597 | case PPC::ATOMIC_CMP_SWAP_I64: |
8598 | case PPC::ATOMIC_LOAD_ADD_I8: |
8599 | case PPC::ATOMIC_LOAD_ADD_I16: |
8600 | case PPC::ATOMIC_LOAD_ADD_I32: |
8601 | case PPC::ATOMIC_LOAD_ADD_I64: |
8602 | case PPC::ATOMIC_LOAD_AND_I8: |
8603 | case PPC::ATOMIC_LOAD_AND_I16: |
8604 | case PPC::ATOMIC_LOAD_AND_I32: |
8605 | case PPC::ATOMIC_LOAD_AND_I64: |
8606 | case PPC::ATOMIC_LOAD_MAX_I8: |
8607 | case PPC::ATOMIC_LOAD_MAX_I16: |
8608 | case PPC::ATOMIC_LOAD_MAX_I32: |
8609 | case PPC::ATOMIC_LOAD_MAX_I64: |
8610 | case PPC::ATOMIC_LOAD_MIN_I8: |
8611 | case PPC::ATOMIC_LOAD_MIN_I16: |
8612 | case PPC::ATOMIC_LOAD_MIN_I32: |
8613 | case PPC::ATOMIC_LOAD_MIN_I64: |
8614 | case PPC::ATOMIC_LOAD_NAND_I8: |
8615 | case PPC::ATOMIC_LOAD_NAND_I16: |
8616 | case PPC::ATOMIC_LOAD_NAND_I32: |
8617 | case PPC::ATOMIC_LOAD_NAND_I64: |
8618 | case PPC::ATOMIC_LOAD_OR_I8: |
8619 | case PPC::ATOMIC_LOAD_OR_I16: |
8620 | case PPC::ATOMIC_LOAD_OR_I32: |
8621 | case PPC::ATOMIC_LOAD_OR_I64: |
8622 | case PPC::ATOMIC_LOAD_SUB_I8: |
8623 | case PPC::ATOMIC_LOAD_SUB_I16: |
8624 | case PPC::ATOMIC_LOAD_SUB_I32: |
8625 | case PPC::ATOMIC_LOAD_SUB_I64: |
8626 | case PPC::ATOMIC_LOAD_UMAX_I8: |
8627 | case PPC::ATOMIC_LOAD_UMAX_I16: |
8628 | case PPC::ATOMIC_LOAD_UMAX_I32: |
8629 | case PPC::ATOMIC_LOAD_UMAX_I64: |
8630 | case PPC::ATOMIC_LOAD_UMIN_I8: |
8631 | case PPC::ATOMIC_LOAD_UMIN_I16: |
8632 | case PPC::ATOMIC_LOAD_UMIN_I32: |
8633 | case PPC::ATOMIC_LOAD_UMIN_I64: |
8634 | case PPC::ATOMIC_LOAD_XOR_I8: |
8635 | case PPC::ATOMIC_LOAD_XOR_I16: |
8636 | case PPC::ATOMIC_LOAD_XOR_I32: |
8637 | case PPC::ATOMIC_LOAD_XOR_I64: |
8638 | case PPC::ATOMIC_SWAP_I8: |
8639 | case PPC::ATOMIC_SWAP_I16: |
8640 | case PPC::ATOMIC_SWAP_I32: |
8641 | case PPC::ATOMIC_SWAP_I64: |
8642 | case PPC::ATTN: |
8643 | case PPC::BCTR: |
8644 | case PPC::BCTR8: |
8645 | case PPC::BCTRL: |
8646 | case PPC::BCTRL8: |
8647 | case PPC::BCTRL8_RM: |
8648 | case PPC::BCTRL_RM: |
8649 | case PPC::BDNZLR: |
8650 | case PPC::BDNZLR8: |
8651 | case PPC::BDNZLRL: |
8652 | case PPC::BDNZLRLm: |
8653 | case PPC::BDNZLRLp: |
8654 | case PPC::BDNZLRm: |
8655 | case PPC::BDNZLRp: |
8656 | case PPC::BDZLR: |
8657 | case PPC::BDZLR8: |
8658 | case PPC::BDZLRL: |
8659 | case PPC::BDZLRLm: |
8660 | case PPC::BDZLRLp: |
8661 | case PPC::BDZLRm: |
8662 | case PPC::BDZLRp: |
8663 | case PPC::BLR: |
8664 | case PPC::BLR8: |
8665 | case PPC::BLRL: |
8666 | case PPC::CLRBHRB: |
8667 | case PPC::CP_ABORT: |
8668 | case PPC::CR6SET: |
8669 | case PPC::CR6UNSET: |
8670 | case PPC::DSSALL: |
8671 | case PPC::DYNALLOC: |
8672 | case PPC::DYNALLOC8: |
8673 | case PPC::DYNAREAOFFSET: |
8674 | case PPC::DYNAREAOFFSET8: |
8675 | case PPC::DecreaseCTR8loop: |
8676 | case PPC::DecreaseCTRloop: |
8677 | case PPC::EH_SjLj_LongJmp32: |
8678 | case PPC::EH_SjLj_LongJmp64: |
8679 | case PPC::EH_SjLj_SetJmp32: |
8680 | case PPC::EH_SjLj_SetJmp64: |
8681 | case PPC::EH_SjLj_Setup: |
8682 | case PPC::EnforceIEIO: |
8683 | case PPC::FADDrtz: |
8684 | case PPC::FENCE: |
8685 | case PPC::GETtlsADDR: |
8686 | case PPC::GETtlsADDR32: |
8687 | case PPC::GETtlsADDR32AIX: |
8688 | case PPC::GETtlsADDR64AIX: |
8689 | case PPC::GETtlsADDRPCREL: |
8690 | case PPC::GETtlsMOD32AIX: |
8691 | case PPC::GETtlsMOD64AIX: |
8692 | case PPC::GETtlsTpointer32AIX: |
8693 | case PPC::GETtlsldADDR: |
8694 | case PPC::GETtlsldADDR32: |
8695 | case PPC::GETtlsldADDRPCREL: |
8696 | case PPC::HRFID: |
8697 | case PPC::ISYNC: |
8698 | case PPC::LDgotTprelL: |
8699 | case PPC::LDgotTprelL32: |
8700 | case PPC::LDtoc: |
8701 | case PPC::LDtocBA: |
8702 | case PPC::LDtocCPT: |
8703 | case PPC::LDtocJTI: |
8704 | case PPC::LDtocL: |
8705 | case PPC::LQX_PSEUDO: |
8706 | case PPC::LWZtoc: |
8707 | case PPC::LWZtocL: |
8708 | case PPC::MSGSYNC: |
8709 | case PPC::MSYNC: |
8710 | case PPC::MoveGOTtoLR: |
8711 | case PPC::MovePCtoLR: |
8712 | case PPC::MovePCtoLR8: |
8713 | case PPC::NAP: |
8714 | case PPC::NOP: |
8715 | case PPC::NOP_GT_PWR6: |
8716 | case PPC::NOP_GT_PWR7: |
8717 | case PPC::PADDIdtprel: |
8718 | case PPC::PPC32GOT: |
8719 | case PPC::PPC32PICGOT: |
8720 | case PPC::PREPARE_PROBED_ALLOCA_32: |
8721 | case PPC::PREPARE_PROBED_ALLOCA_64: |
8722 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32: |
8723 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64: |
8724 | case PPC::PROBED_ALLOCA_32: |
8725 | case PPC::PROBED_ALLOCA_64: |
8726 | case PPC::PROBED_STACKALLOC_32: |
8727 | case PPC::PROBED_STACKALLOC_64: |
8728 | case PPC::PseudoEIEIO: |
8729 | case PPC::RESTORE_ACC: |
8730 | case PPC::RESTORE_CR: |
8731 | case PPC::RESTORE_CRBIT: |
8732 | case PPC::RESTORE_QUADWORD: |
8733 | case PPC::RESTORE_UACC: |
8734 | case PPC::RESTORE_WACC: |
8735 | case PPC::RFCI: |
8736 | case PPC::RFDI: |
8737 | case PPC::RFI: |
8738 | case PPC::RFID: |
8739 | case PPC::RFMCI: |
8740 | case PPC::ReadTB: |
8741 | case PPC::SELECT_CC_F4: |
8742 | case PPC::SELECT_CC_F8: |
8743 | case PPC::SELECT_CC_F16: |
8744 | case PPC::SELECT_CC_I4: |
8745 | case PPC::SELECT_CC_I8: |
8746 | case PPC::SELECT_CC_SPE: |
8747 | case PPC::SELECT_CC_SPE4: |
8748 | case PPC::SELECT_CC_VRRC: |
8749 | case PPC::SELECT_CC_VSFRC: |
8750 | case PPC::SELECT_CC_VSRC: |
8751 | case PPC::SELECT_CC_VSSRC: |
8752 | case PPC::SELECT_F4: |
8753 | case PPC::SELECT_F8: |
8754 | case PPC::SELECT_F16: |
8755 | case PPC::SELECT_I4: |
8756 | case PPC::SELECT_I8: |
8757 | case PPC::SELECT_SPE: |
8758 | case PPC::SELECT_SPE4: |
8759 | case PPC::SELECT_VRRC: |
8760 | case PPC::SELECT_VSFRC: |
8761 | case PPC::SELECT_VSRC: |
8762 | case PPC::SELECT_VSSRC: |
8763 | case PPC::SETFLM: |
8764 | case PPC::SETRND: |
8765 | case PPC::SETRNDi: |
8766 | case PPC::SLBIA: |
8767 | case PPC::SLBSYNC: |
8768 | case PPC::SPILL_ACC: |
8769 | case PPC::SPILL_CR: |
8770 | case PPC::SPILL_CRBIT: |
8771 | case PPC::SPILL_QUADWORD: |
8772 | case PPC::SPILL_UACC: |
8773 | case PPC::SPILL_WACC: |
8774 | case PPC::SPLIT_QUADWORD: |
8775 | case PPC::STOP: |
8776 | case PPC::STQX_PSEUDO: |
8777 | case PPC::TAILBCTR: |
8778 | case PPC::TAILBCTR8: |
8779 | case PPC::TBEGIN_RET: |
8780 | case PPC::TCHECK_RET: |
8781 | case PPC::TCRETURNai: |
8782 | case PPC::TCRETURNai8: |
8783 | case PPC::TCRETURNdi: |
8784 | case PPC::TCRETURNdi8: |
8785 | case PPC::TCRETURNri: |
8786 | case PPC::TCRETURNri8: |
8787 | case PPC::TLBIA: |
8788 | case PPC::TLBRE: |
8789 | case PPC::TLBSYNC: |
8790 | case PPC::TLBWE: |
8791 | case PPC::TLSGDAIX: |
8792 | case PPC::TLSGDAIX8: |
8793 | case PPC::TLSLDAIX: |
8794 | case PPC::TLSLDAIX8: |
8795 | case PPC::TRAP: |
8796 | case PPC::TRECHKPT: |
8797 | case PPC::UNENCODED_NOP: |
8798 | case PPC::UpdateGBR: { |
8799 | break; |
8800 | } |
8801 | case PPC::TEND: { |
8802 | switch (OpNum) { |
8803 | case 0: |
8804 | // op: A |
8805 | return 25; |
8806 | } |
8807 | break; |
8808 | } |
8809 | case PPC::DMMR: { |
8810 | switch (OpNum) { |
8811 | case 0: |
8812 | // op: AT |
8813 | return 23; |
8814 | case 1: |
8815 | // op: AB |
8816 | return 13; |
8817 | } |
8818 | break; |
8819 | } |
8820 | case PPC::PMXVI4GER8: |
8821 | case PPC::PMXVI4GER8W: { |
8822 | switch (OpNum) { |
8823 | case 0: |
8824 | // op: AT |
8825 | return 23; |
8826 | case 1: |
8827 | // op: XA |
8828 | return 2; |
8829 | case 2: |
8830 | // op: XB |
8831 | return 1; |
8832 | case 3: |
8833 | // op: XMSK |
8834 | return 36; |
8835 | case 4: |
8836 | // op: YMSK |
8837 | return 32; |
8838 | case 5: |
8839 | // op: PMSK |
8840 | return 40; |
8841 | } |
8842 | break; |
8843 | } |
8844 | case PPC::PMXVI8GER4: |
8845 | case PPC::PMXVI8GER4W: { |
8846 | switch (OpNum) { |
8847 | case 0: |
8848 | // op: AT |
8849 | return 23; |
8850 | case 1: |
8851 | // op: XA |
8852 | return 2; |
8853 | case 2: |
8854 | // op: XB |
8855 | return 1; |
8856 | case 3: |
8857 | // op: XMSK |
8858 | return 36; |
8859 | case 4: |
8860 | // op: YMSK |
8861 | return 32; |
8862 | case 5: |
8863 | // op: PMSK |
8864 | return 44; |
8865 | } |
8866 | break; |
8867 | } |
8868 | case PPC::PMXVBF16GER2: |
8869 | case PPC::PMXVBF16GER2W: |
8870 | case PPC::PMXVF16GER2: |
8871 | case PPC::PMXVF16GER2W: |
8872 | case PPC::PMXVI16GER2: |
8873 | case PPC::PMXVI16GER2S: |
8874 | case PPC::PMXVI16GER2SW: |
8875 | case PPC::PMXVI16GER2W: { |
8876 | switch (OpNum) { |
8877 | case 0: |
8878 | // op: AT |
8879 | return 23; |
8880 | case 1: |
8881 | // op: XA |
8882 | return 2; |
8883 | case 2: |
8884 | // op: XB |
8885 | return 1; |
8886 | case 3: |
8887 | // op: XMSK |
8888 | return 36; |
8889 | case 4: |
8890 | // op: YMSK |
8891 | return 32; |
8892 | case 5: |
8893 | // op: PMSK |
8894 | return 46; |
8895 | } |
8896 | break; |
8897 | } |
8898 | case PPC::PMXVF32GER: |
8899 | case PPC::PMXVF32GERW: { |
8900 | switch (OpNum) { |
8901 | case 0: |
8902 | // op: AT |
8903 | return 23; |
8904 | case 1: |
8905 | // op: XA |
8906 | return 2; |
8907 | case 2: |
8908 | // op: XB |
8909 | return 1; |
8910 | case 3: |
8911 | // op: XMSK |
8912 | return 36; |
8913 | case 4: |
8914 | // op: YMSK |
8915 | return 32; |
8916 | } |
8917 | break; |
8918 | } |
8919 | case PPC::PMXVF64GER: |
8920 | case PPC::PMXVF64GERW: { |
8921 | switch (OpNum) { |
8922 | case 0: |
8923 | // op: AT |
8924 | return 23; |
8925 | case 1: |
8926 | // op: XA |
8927 | return 2; |
8928 | case 2: |
8929 | // op: XB |
8930 | return 1; |
8931 | case 3: |
8932 | // op: XMSK |
8933 | return 36; |
8934 | case 4: |
8935 | // op: YMSK |
8936 | return 34; |
8937 | } |
8938 | break; |
8939 | } |
8940 | case PPC::XVBF16GER2: |
8941 | case PPC::XVBF16GER2W: |
8942 | case PPC::XVF16GER2: |
8943 | case PPC::XVF16GER2W: |
8944 | case PPC::XVF32GER: |
8945 | case PPC::XVF32GERW: |
8946 | case PPC::XVF64GER: |
8947 | case PPC::XVF64GERW: |
8948 | case PPC::XVI4GER8: |
8949 | case PPC::XVI4GER8W: |
8950 | case PPC::XVI8GER4: |
8951 | case PPC::XVI8GER4W: |
8952 | case PPC::XVI16GER2: |
8953 | case PPC::XVI16GER2S: |
8954 | case PPC::XVI16GER2SW: |
8955 | case PPC::XVI16GER2W: { |
8956 | switch (OpNum) { |
8957 | case 0: |
8958 | // op: AT |
8959 | return 23; |
8960 | case 1: |
8961 | // op: XA |
8962 | return 2; |
8963 | case 2: |
8964 | // op: XB |
8965 | return 1; |
8966 | } |
8967 | break; |
8968 | } |
8969 | case PPC::DMXXINSTFDMR512: |
8970 | case PPC::DMXXINSTFDMR512_HI: { |
8971 | switch (OpNum) { |
8972 | case 0: |
8973 | // op: AT |
8974 | return 23; |
8975 | case 1: |
8976 | // op: XAp |
8977 | return 2; |
8978 | case 2: |
8979 | // op: XBp |
8980 | return 1; |
8981 | } |
8982 | break; |
8983 | } |
8984 | case PPC::DMXXINSTFDMR256: { |
8985 | switch (OpNum) { |
8986 | case 0: |
8987 | // op: AT |
8988 | return 23; |
8989 | case 1: |
8990 | // op: XBp |
8991 | return 1; |
8992 | case 2: |
8993 | // op: P |
8994 | return 11; |
8995 | } |
8996 | break; |
8997 | } |
8998 | case PPC::DMXOR: { |
8999 | switch (OpNum) { |
9000 | case 0: |
9001 | // op: AT |
9002 | return 23; |
9003 | case 2: |
9004 | // op: AB |
9005 | return 13; |
9006 | } |
9007 | break; |
9008 | } |
9009 | case PPC::PMXVI4GER8PP: |
9010 | case PPC::PMXVI4GER8WPP: { |
9011 | switch (OpNum) { |
9012 | case 0: |
9013 | // op: AT |
9014 | return 23; |
9015 | case 2: |
9016 | // op: XA |
9017 | return 2; |
9018 | case 3: |
9019 | // op: XB |
9020 | return 1; |
9021 | case 4: |
9022 | // op: XMSK |
9023 | return 36; |
9024 | case 5: |
9025 | // op: YMSK |
9026 | return 32; |
9027 | case 6: |
9028 | // op: PMSK |
9029 | return 40; |
9030 | } |
9031 | break; |
9032 | } |
9033 | case PPC::PMXVI8GER4PP: |
9034 | case PPC::PMXVI8GER4SPP: |
9035 | case PPC::PMXVI8GER4WPP: |
9036 | case PPC::PMXVI8GER4WSPP: { |
9037 | switch (OpNum) { |
9038 | case 0: |
9039 | // op: AT |
9040 | return 23; |
9041 | case 2: |
9042 | // op: XA |
9043 | return 2; |
9044 | case 3: |
9045 | // op: XB |
9046 | return 1; |
9047 | case 4: |
9048 | // op: XMSK |
9049 | return 36; |
9050 | case 5: |
9051 | // op: YMSK |
9052 | return 32; |
9053 | case 6: |
9054 | // op: PMSK |
9055 | return 44; |
9056 | } |
9057 | break; |
9058 | } |
9059 | case PPC::PMXVBF16GER2NN: |
9060 | case PPC::PMXVBF16GER2NP: |
9061 | case PPC::PMXVBF16GER2PN: |
9062 | case PPC::PMXVBF16GER2PP: |
9063 | case PPC::PMXVBF16GER2WNN: |
9064 | case PPC::PMXVBF16GER2WNP: |
9065 | case PPC::PMXVBF16GER2WPN: |
9066 | case PPC::PMXVBF16GER2WPP: |
9067 | case PPC::PMXVF16GER2NN: |
9068 | case PPC::PMXVF16GER2NP: |
9069 | case PPC::PMXVF16GER2PN: |
9070 | case PPC::PMXVF16GER2PP: |
9071 | case PPC::PMXVF16GER2WNN: |
9072 | case PPC::PMXVF16GER2WNP: |
9073 | case PPC::PMXVF16GER2WPN: |
9074 | case PPC::PMXVF16GER2WPP: |
9075 | case PPC::PMXVI16GER2PP: |
9076 | case PPC::PMXVI16GER2SPP: |
9077 | case PPC::PMXVI16GER2SWPP: |
9078 | case PPC::PMXVI16GER2WPP: { |
9079 | switch (OpNum) { |
9080 | case 0: |
9081 | // op: AT |
9082 | return 23; |
9083 | case 2: |
9084 | // op: XA |
9085 | return 2; |
9086 | case 3: |
9087 | // op: XB |
9088 | return 1; |
9089 | case 4: |
9090 | // op: XMSK |
9091 | return 36; |
9092 | case 5: |
9093 | // op: YMSK |
9094 | return 32; |
9095 | case 6: |
9096 | // op: PMSK |
9097 | return 46; |
9098 | } |
9099 | break; |
9100 | } |
9101 | case PPC::PMXVF32GERNN: |
9102 | case PPC::PMXVF32GERNP: |
9103 | case PPC::PMXVF32GERPN: |
9104 | case PPC::PMXVF32GERPP: |
9105 | case PPC::PMXVF32GERWNN: |
9106 | case PPC::PMXVF32GERWNP: |
9107 | case PPC::PMXVF32GERWPN: |
9108 | case PPC::PMXVF32GERWPP: { |
9109 | switch (OpNum) { |
9110 | case 0: |
9111 | // op: AT |
9112 | return 23; |
9113 | case 2: |
9114 | // op: XA |
9115 | return 2; |
9116 | case 3: |
9117 | // op: XB |
9118 | return 1; |
9119 | case 4: |
9120 | // op: XMSK |
9121 | return 36; |
9122 | case 5: |
9123 | // op: YMSK |
9124 | return 32; |
9125 | } |
9126 | break; |
9127 | } |
9128 | case PPC::PMXVF64GERNN: |
9129 | case PPC::PMXVF64GERNP: |
9130 | case PPC::PMXVF64GERPN: |
9131 | case PPC::PMXVF64GERPP: |
9132 | case PPC::PMXVF64GERWNN: |
9133 | case PPC::PMXVF64GERWNP: |
9134 | case PPC::PMXVF64GERWPN: |
9135 | case PPC::PMXVF64GERWPP: { |
9136 | switch (OpNum) { |
9137 | case 0: |
9138 | // op: AT |
9139 | return 23; |
9140 | case 2: |
9141 | // op: XA |
9142 | return 2; |
9143 | case 3: |
9144 | // op: XB |
9145 | return 1; |
9146 | case 4: |
9147 | // op: XMSK |
9148 | return 36; |
9149 | case 5: |
9150 | // op: YMSK |
9151 | return 34; |
9152 | } |
9153 | break; |
9154 | } |
9155 | case PPC::XVBF16GER2NN: |
9156 | case PPC::XVBF16GER2NP: |
9157 | case PPC::XVBF16GER2PN: |
9158 | case PPC::XVBF16GER2PP: |
9159 | case PPC::XVBF16GER2WNN: |
9160 | case PPC::XVBF16GER2WNP: |
9161 | case PPC::XVBF16GER2WPN: |
9162 | case PPC::XVBF16GER2WPP: |
9163 | case PPC::XVF16GER2NN: |
9164 | case PPC::XVF16GER2NP: |
9165 | case PPC::XVF16GER2PN: |
9166 | case PPC::XVF16GER2PP: |
9167 | case PPC::XVF16GER2WNN: |
9168 | case PPC::XVF16GER2WNP: |
9169 | case PPC::XVF16GER2WPN: |
9170 | case PPC::XVF16GER2WPP: |
9171 | case PPC::XVF32GERNN: |
9172 | case PPC::XVF32GERNP: |
9173 | case PPC::XVF32GERPN: |
9174 | case PPC::XVF32GERPP: |
9175 | case PPC::XVF32GERWNN: |
9176 | case PPC::XVF32GERWNP: |
9177 | case PPC::XVF32GERWPN: |
9178 | case PPC::XVF32GERWPP: |
9179 | case PPC::XVF64GERNN: |
9180 | case PPC::XVF64GERNP: |
9181 | case PPC::XVF64GERPN: |
9182 | case PPC::XVF64GERPP: |
9183 | case PPC::XVF64GERWNN: |
9184 | case PPC::XVF64GERWNP: |
9185 | case PPC::XVF64GERWPN: |
9186 | case PPC::XVF64GERWPP: |
9187 | case PPC::XVI4GER8PP: |
9188 | case PPC::XVI4GER8WPP: |
9189 | case PPC::XVI8GER4PP: |
9190 | case PPC::XVI8GER4SPP: |
9191 | case PPC::XVI8GER4WPP: |
9192 | case PPC::XVI8GER4WSPP: |
9193 | case PPC::XVI16GER2PP: |
9194 | case PPC::XVI16GER2SPP: |
9195 | case PPC::XVI16GER2SWPP: |
9196 | case PPC::XVI16GER2WPP: { |
9197 | switch (OpNum) { |
9198 | case 0: |
9199 | // op: AT |
9200 | return 23; |
9201 | case 2: |
9202 | // op: XA |
9203 | return 2; |
9204 | case 3: |
9205 | // op: XB |
9206 | return 1; |
9207 | } |
9208 | break; |
9209 | } |
9210 | case PPC::DMSETDMRZ: |
9211 | case PPC::XXMTACC: |
9212 | case PPC::XXMTACCW: |
9213 | case PPC::XXSETACCZ: |
9214 | case PPC::XXSETACCZW: { |
9215 | switch (OpNum) { |
9216 | case 0: |
9217 | // op: AT |
9218 | return 23; |
9219 | } |
9220 | break; |
9221 | } |
9222 | case PPC::BCLalways: |
9223 | case PPC::BDNZ: |
9224 | case PPC::BDNZ8: |
9225 | case PPC::BDNZA: |
9226 | case PPC::BDNZAm: |
9227 | case PPC::BDNZAp: |
9228 | case PPC::BDNZL: |
9229 | case PPC::BDNZLA: |
9230 | case PPC::BDNZLAm: |
9231 | case PPC::BDNZLAp: |
9232 | case PPC::BDNZLm: |
9233 | case PPC::BDNZLp: |
9234 | case PPC::BDNZm: |
9235 | case PPC::BDNZp: |
9236 | case PPC::BDZ: |
9237 | case PPC::BDZ8: |
9238 | case PPC::BDZA: |
9239 | case PPC::BDZAm: |
9240 | case PPC::BDZAp: |
9241 | case PPC::BDZL: |
9242 | case PPC::BDZLA: |
9243 | case PPC::BDZLAm: |
9244 | case PPC::BDZLAp: |
9245 | case PPC::BDZLm: |
9246 | case PPC::BDZLp: |
9247 | case PPC::BDZm: |
9248 | case PPC::BDZp: { |
9249 | switch (OpNum) { |
9250 | case 0: |
9251 | // op: BD |
9252 | return 2; |
9253 | } |
9254 | break; |
9255 | } |
9256 | case PPC::MCRF: |
9257 | case PPC::MCRFS: { |
9258 | switch (OpNum) { |
9259 | case 0: |
9260 | // op: BF |
9261 | return 23; |
9262 | case 1: |
9263 | // op: BFA |
9264 | return 18; |
9265 | } |
9266 | break; |
9267 | } |
9268 | case PPC::XSTSTDCQP: { |
9269 | switch (OpNum) { |
9270 | case 0: |
9271 | // op: BF |
9272 | return 23; |
9273 | case 1: |
9274 | // op: DCMX |
9275 | return 16; |
9276 | case 2: |
9277 | // op: VB |
9278 | return 11; |
9279 | } |
9280 | break; |
9281 | } |
9282 | case PPC::XSTSTDCDP: |
9283 | case PPC::XSTSTDCSP: { |
9284 | switch (OpNum) { |
9285 | case 0: |
9286 | // op: BF |
9287 | return 23; |
9288 | case 1: |
9289 | // op: DCMX |
9290 | return 16; |
9291 | case 2: |
9292 | // op: XB |
9293 | return 1; |
9294 | } |
9295 | break; |
9296 | } |
9297 | case PPC::DTSTDC: |
9298 | case PPC::DTSTDCQ: |
9299 | case PPC::DTSTDG: |
9300 | case PPC::DTSTDGQ: { |
9301 | switch (OpNum) { |
9302 | case 0: |
9303 | // op: BF |
9304 | return 23; |
9305 | case 1: |
9306 | // op: FRA |
9307 | return 16; |
9308 | case 2: |
9309 | // op: DCM |
9310 | return 10; |
9311 | } |
9312 | break; |
9313 | } |
9314 | case PPC::CMPRB: |
9315 | case PPC::CMPRB8: { |
9316 | switch (OpNum) { |
9317 | case 0: |
9318 | // op: BF |
9319 | return 23; |
9320 | case 1: |
9321 | // op: L |
9322 | return 21; |
9323 | case 2: |
9324 | // op: RA |
9325 | return 16; |
9326 | case 3: |
9327 | // op: RB |
9328 | return 11; |
9329 | } |
9330 | break; |
9331 | } |
9332 | case PPC::CMPDI: |
9333 | case PPC::CMPLDI: |
9334 | case PPC::CMPLWI: |
9335 | case PPC::CMPWI: { |
9336 | switch (OpNum) { |
9337 | case 0: |
9338 | // op: BF |
9339 | return 23; |
9340 | case 1: |
9341 | // op: RA |
9342 | return 16; |
9343 | case 2: |
9344 | // op: D |
9345 | return 0; |
9346 | } |
9347 | break; |
9348 | } |
9349 | case PPC::CMPD: |
9350 | case PPC::CMPEQB: |
9351 | case PPC::CMPLD: |
9352 | case PPC::CMPLW: |
9353 | case PPC::CMPW: |
9354 | case PPC::DCMPO: |
9355 | case PPC::DCMPOQ: |
9356 | case PPC::DCMPU: |
9357 | case PPC::DCMPUQ: |
9358 | case PPC::DTSTEX: |
9359 | case PPC::DTSTEXQ: |
9360 | case PPC::DTSTSF: |
9361 | case PPC::DTSTSFQ: |
9362 | case PPC::FCMPOD: |
9363 | case PPC::FCMPOS: |
9364 | case PPC::FCMPUD: |
9365 | case PPC::FCMPUS: |
9366 | case PPC::FTDIV: |
9367 | case PPC::XSCMPEXPQP: |
9368 | case PPC::XSCMPOQP: |
9369 | case PPC::XSCMPUQP: { |
9370 | switch (OpNum) { |
9371 | case 0: |
9372 | // op: BF |
9373 | return 23; |
9374 | case 1: |
9375 | // op: RA |
9376 | return 16; |
9377 | case 2: |
9378 | // op: RB |
9379 | return 11; |
9380 | } |
9381 | break; |
9382 | } |
9383 | case PPC::FTSQRT: { |
9384 | switch (OpNum) { |
9385 | case 0: |
9386 | // op: BF |
9387 | return 23; |
9388 | case 1: |
9389 | // op: RB |
9390 | return 11; |
9391 | } |
9392 | break; |
9393 | } |
9394 | case PPC::MTFSFIb: { |
9395 | switch (OpNum) { |
9396 | case 0: |
9397 | // op: BF |
9398 | return 23; |
9399 | case 1: |
9400 | // op: U |
9401 | return 12; |
9402 | } |
9403 | break; |
9404 | } |
9405 | case PPC::DTSTSFI: |
9406 | case PPC::DTSTSFIQ: { |
9407 | switch (OpNum) { |
9408 | case 0: |
9409 | // op: BF |
9410 | return 23; |
9411 | case 1: |
9412 | // op: UIM |
9413 | return 16; |
9414 | case 2: |
9415 | // op: FRB |
9416 | return 11; |
9417 | } |
9418 | break; |
9419 | } |
9420 | case PPC::VCMPSQ: |
9421 | case PPC::VCMPUQ: { |
9422 | switch (OpNum) { |
9423 | case 0: |
9424 | // op: BF |
9425 | return 23; |
9426 | case 1: |
9427 | // op: VA |
9428 | return 16; |
9429 | case 2: |
9430 | // op: VB |
9431 | return 11; |
9432 | } |
9433 | break; |
9434 | } |
9435 | case PPC::XVTLSBB: { |
9436 | switch (OpNum) { |
9437 | case 0: |
9438 | // op: BF |
9439 | return 23; |
9440 | case 1: |
9441 | // op: XB |
9442 | return 1; |
9443 | } |
9444 | break; |
9445 | } |
9446 | case PPC::MTFSFI: |
9447 | case PPC::MTFSFI_rec: { |
9448 | switch (OpNum) { |
9449 | case 0: |
9450 | // op: BF |
9451 | return 23; |
9452 | case 2: |
9453 | // op: W |
9454 | return 16; |
9455 | case 1: |
9456 | // op: U |
9457 | return 12; |
9458 | } |
9459 | break; |
9460 | } |
9461 | case PPC::MCRXRX: |
9462 | case PPC::TCHECK: { |
9463 | switch (OpNum) { |
9464 | case 0: |
9465 | // op: BF |
9466 | return 23; |
9467 | } |
9468 | break; |
9469 | } |
9470 | case PPC::BC: |
9471 | case PPC::BCL: |
9472 | case PPC::BCLn: |
9473 | case PPC::BCn: { |
9474 | switch (OpNum) { |
9475 | case 0: |
9476 | // op: BI |
9477 | return 16; |
9478 | case 1: |
9479 | // op: BD |
9480 | return 2; |
9481 | } |
9482 | break; |
9483 | } |
9484 | case PPC::BCCTR: |
9485 | case PPC::BCCTR8: |
9486 | case PPC::BCCTR8n: |
9487 | case PPC::BCCTRL: |
9488 | case PPC::BCCTRL8: |
9489 | case PPC::BCCTRL8n: |
9490 | case PPC::BCCTRLn: |
9491 | case PPC::BCCTRn: |
9492 | case PPC::BCLR: |
9493 | case PPC::BCLRL: |
9494 | case PPC::BCLRLn: |
9495 | case PPC::BCLRn: { |
9496 | switch (OpNum) { |
9497 | case 0: |
9498 | // op: BI |
9499 | return 16; |
9500 | } |
9501 | break; |
9502 | } |
9503 | case PPC::BCC: |
9504 | case PPC::BCCA: |
9505 | case PPC::BCCL: |
9506 | case PPC::BCCLA: |
9507 | case PPC::CTRL_DEP: { |
9508 | switch (OpNum) { |
9509 | case 0: |
9510 | // op: BIBO |
9511 | return 16; |
9512 | case 1: |
9513 | // op: CR |
9514 | return 18; |
9515 | case 2: |
9516 | // op: BD |
9517 | return 2; |
9518 | } |
9519 | break; |
9520 | } |
9521 | case PPC::BCCCTR: |
9522 | case PPC::BCCCTR8: |
9523 | case PPC::BCCCTRL: |
9524 | case PPC::BCCCTRL8: |
9525 | case PPC::BCCLR: |
9526 | case PPC::BCCLRL: { |
9527 | switch (OpNum) { |
9528 | case 0: |
9529 | // op: BIBO |
9530 | return 16; |
9531 | case 1: |
9532 | // op: CR |
9533 | return 18; |
9534 | } |
9535 | break; |
9536 | } |
9537 | case PPC::gBC: |
9538 | case PPC::gBCA: |
9539 | case PPC::gBCL: |
9540 | case PPC::gBCLA: { |
9541 | switch (OpNum) { |
9542 | case 0: |
9543 | // op: BO |
9544 | return 21; |
9545 | case 1: |
9546 | // op: BI |
9547 | return 16; |
9548 | case 2: |
9549 | // op: BD |
9550 | return 2; |
9551 | } |
9552 | break; |
9553 | } |
9554 | case PPC::gBCCTR: |
9555 | case PPC::gBCCTRL: |
9556 | case PPC::gBCLR: |
9557 | case PPC::gBCLRL: { |
9558 | switch (OpNum) { |
9559 | case 0: |
9560 | // op: BO |
9561 | return 21; |
9562 | case 1: |
9563 | // op: BI |
9564 | return 16; |
9565 | case 2: |
9566 | // op: BH |
9567 | return 11; |
9568 | } |
9569 | break; |
9570 | } |
9571 | case PPC::gBCAat: |
9572 | case PPC::gBCLAat: |
9573 | case PPC::gBCLat: |
9574 | case PPC::gBCat: { |
9575 | switch (OpNum) { |
9576 | case 0: |
9577 | // op: BO |
9578 | return 23; |
9579 | case 1: |
9580 | // op: at |
9581 | return 21; |
9582 | case 2: |
9583 | // op: BI |
9584 | return 16; |
9585 | case 3: |
9586 | // op: BD |
9587 | return 2; |
9588 | } |
9589 | break; |
9590 | } |
9591 | case PPC::XSCMPEXPDP: |
9592 | case PPC::XSCMPODP: |
9593 | case PPC::XSCMPUDP: |
9594 | case PPC::XSTDIVDP: |
9595 | case PPC::XVTDIVDP: |
9596 | case PPC::XVTDIVSP: { |
9597 | switch (OpNum) { |
9598 | case 0: |
9599 | // op: CR |
9600 | return 23; |
9601 | case 1: |
9602 | // op: XA |
9603 | return 2; |
9604 | case 2: |
9605 | // op: XB |
9606 | return 1; |
9607 | } |
9608 | break; |
9609 | } |
9610 | case PPC::XSTSQRTDP: |
9611 | case PPC::XVTSQRTDP: |
9612 | case PPC::XVTSQRTSP: { |
9613 | switch (OpNum) { |
9614 | case 0: |
9615 | // op: CR |
9616 | return 23; |
9617 | case 1: |
9618 | // op: XB |
9619 | return 1; |
9620 | } |
9621 | break; |
9622 | } |
9623 | case PPC::CRSET: |
9624 | case PPC::CRUNSET: { |
9625 | switch (OpNum) { |
9626 | case 0: |
9627 | // op: CRD |
9628 | return 11; |
9629 | } |
9630 | break; |
9631 | } |
9632 | case PPC::CRNOT: { |
9633 | switch (OpNum) { |
9634 | case 0: |
9635 | // op: CRD |
9636 | return 21; |
9637 | case 1: |
9638 | // op: CRA |
9639 | return 11; |
9640 | } |
9641 | break; |
9642 | } |
9643 | case PPC::CRAND: |
9644 | case PPC::CRANDC: |
9645 | case PPC::CREQV: |
9646 | case PPC::CRNAND: |
9647 | case PPC::CRNOR: |
9648 | case PPC::CROR: |
9649 | case PPC::CRORC: |
9650 | case PPC::CRXOR: { |
9651 | switch (OpNum) { |
9652 | case 0: |
9653 | // op: CRD |
9654 | return 21; |
9655 | case 1: |
9656 | // op: CRA |
9657 | return 16; |
9658 | case 2: |
9659 | // op: CRB |
9660 | return 11; |
9661 | } |
9662 | break; |
9663 | } |
9664 | case PPC::ICBLC: |
9665 | case PPC::ICBLQ: |
9666 | case PPC::ICBT: |
9667 | case PPC::ICBTLS: { |
9668 | switch (OpNum) { |
9669 | case 0: |
9670 | // op: CT |
9671 | return 21; |
9672 | case 1: |
9673 | // op: RA |
9674 | return 16; |
9675 | case 2: |
9676 | // op: RB |
9677 | return 11; |
9678 | } |
9679 | break; |
9680 | } |
9681 | case PPC::WRTEEI: { |
9682 | switch (OpNum) { |
9683 | case 0: |
9684 | // op: E |
9685 | return 15; |
9686 | } |
9687 | break; |
9688 | } |
9689 | case PPC::MTFSFb: { |
9690 | switch (OpNum) { |
9691 | case 0: |
9692 | // op: FM |
9693 | return 17; |
9694 | case 1: |
9695 | // op: RT |
9696 | return 11; |
9697 | } |
9698 | break; |
9699 | } |
9700 | case PPC::MTFSB0: |
9701 | case PPC::MTFSB1: { |
9702 | switch (OpNum) { |
9703 | case 0: |
9704 | // op: FM |
9705 | return 21; |
9706 | } |
9707 | break; |
9708 | } |
9709 | case PPC::DQUA: |
9710 | case PPC::DQUAQ: |
9711 | case PPC::DQUAQ_rec: |
9712 | case PPC::DQUA_rec: |
9713 | case PPC::DRRND: |
9714 | case PPC::DRRNDQ: |
9715 | case PPC::DRRNDQ_rec: |
9716 | case PPC::DRRND_rec: { |
9717 | switch (OpNum) { |
9718 | case 0: |
9719 | // op: FRT |
9720 | return 21; |
9721 | case 1: |
9722 | // op: FRA |
9723 | return 16; |
9724 | case 2: |
9725 | // op: FRB |
9726 | return 11; |
9727 | case 3: |
9728 | // op: RMC |
9729 | return 9; |
9730 | } |
9731 | break; |
9732 | } |
9733 | case PPC::FADD: |
9734 | case PPC::FADDS: |
9735 | case PPC::FADDS_rec: |
9736 | case PPC::FADD_rec: |
9737 | case PPC::FDIV: |
9738 | case PPC::FDIVS: |
9739 | case PPC::FDIVS_rec: |
9740 | case PPC::FDIV_rec: |
9741 | case PPC::FSUB: |
9742 | case PPC::FSUBS: |
9743 | case PPC::FSUBS_rec: |
9744 | case PPC::FSUB_rec: |
9745 | case PPC::XSIEXPQP: { |
9746 | switch (OpNum) { |
9747 | case 0: |
9748 | // op: FRT |
9749 | return 21; |
9750 | case 1: |
9751 | // op: FRA |
9752 | return 16; |
9753 | case 2: |
9754 | // op: FRB |
9755 | return 11; |
9756 | } |
9757 | break; |
9758 | } |
9759 | case PPC::FMADD: |
9760 | case PPC::FMADDS: |
9761 | case PPC::FMADDS_rec: |
9762 | case PPC::FMADD_rec: |
9763 | case PPC::FMSUB: |
9764 | case PPC::FMSUBS: |
9765 | case PPC::FMSUBS_rec: |
9766 | case PPC::FMSUB_rec: |
9767 | case PPC::FNMADD: |
9768 | case PPC::FNMADDS: |
9769 | case PPC::FNMADDS_rec: |
9770 | case PPC::FNMADD_rec: |
9771 | case PPC::FNMSUB: |
9772 | case PPC::FNMSUBS: |
9773 | case PPC::FNMSUBS_rec: |
9774 | case PPC::FNMSUB_rec: |
9775 | case PPC::FSELD: |
9776 | case PPC::FSELD_rec: |
9777 | case PPC::FSELS: |
9778 | case PPC::FSELS_rec: { |
9779 | switch (OpNum) { |
9780 | case 0: |
9781 | // op: FRT |
9782 | return 21; |
9783 | case 1: |
9784 | // op: FRA |
9785 | return 16; |
9786 | case 2: |
9787 | // op: FRC |
9788 | return 6; |
9789 | case 3: |
9790 | // op: FRB |
9791 | return 11; |
9792 | } |
9793 | break; |
9794 | } |
9795 | case PPC::FMUL: |
9796 | case PPC::FMULS: |
9797 | case PPC::FMULS_rec: |
9798 | case PPC::FMUL_rec: { |
9799 | switch (OpNum) { |
9800 | case 0: |
9801 | // op: FRT |
9802 | return 21; |
9803 | case 1: |
9804 | // op: FRA |
9805 | return 16; |
9806 | case 2: |
9807 | // op: FRC |
9808 | return 6; |
9809 | } |
9810 | break; |
9811 | } |
9812 | case PPC::DSCLI: |
9813 | case PPC::DSCLIQ: |
9814 | case PPC::DSCLIQ_rec: |
9815 | case PPC::DSCLI_rec: |
9816 | case PPC::DSCRI: |
9817 | case PPC::DSCRIQ: |
9818 | case PPC::DSCRIQ_rec: |
9819 | case PPC::DSCRI_rec: { |
9820 | switch (OpNum) { |
9821 | case 0: |
9822 | // op: FRT |
9823 | return 21; |
9824 | case 1: |
9825 | // op: FRA |
9826 | return 16; |
9827 | case 2: |
9828 | // op: SH |
9829 | return 10; |
9830 | } |
9831 | break; |
9832 | } |
9833 | case PPC::DRINTN: |
9834 | case PPC::DRINTNQ: |
9835 | case PPC::DRINTNQ_rec: |
9836 | case PPC::DRINTN_rec: |
9837 | case PPC::DRINTX: |
9838 | case PPC::DRINTXQ: |
9839 | case PPC::DRINTXQ_rec: |
9840 | case PPC::DRINTX_rec: { |
9841 | switch (OpNum) { |
9842 | case 0: |
9843 | // op: FRT |
9844 | return 21; |
9845 | case 1: |
9846 | // op: R |
9847 | return 16; |
9848 | case 2: |
9849 | // op: FRB |
9850 | return 11; |
9851 | case 3: |
9852 | // op: RMC |
9853 | return 9; |
9854 | } |
9855 | break; |
9856 | } |
9857 | case PPC::DQUAI: |
9858 | case PPC::DQUAIQ: |
9859 | case PPC::DQUAIQ_rec: |
9860 | case PPC::DQUAI_rec: { |
9861 | switch (OpNum) { |
9862 | case 0: |
9863 | // op: FRT |
9864 | return 21; |
9865 | case 2: |
9866 | // op: FRB |
9867 | return 11; |
9868 | case 3: |
9869 | // op: RMC |
9870 | return 9; |
9871 | case 1: |
9872 | // op: TE |
9873 | return 16; |
9874 | } |
9875 | break; |
9876 | } |
9877 | case PPC::MTCRF: |
9878 | case PPC::MTCRF8: { |
9879 | switch (OpNum) { |
9880 | case 0: |
9881 | // op: FXM |
9882 | return 12; |
9883 | case 1: |
9884 | // op: RST |
9885 | return 21; |
9886 | } |
9887 | break; |
9888 | } |
9889 | case PPC::WAITP10: { |
9890 | switch (OpNum) { |
9891 | case 0: |
9892 | // op: L |
9893 | return 21; |
9894 | case 1: |
9895 | // op: PL |
9896 | return 16; |
9897 | } |
9898 | break; |
9899 | } |
9900 | case PPC::SYNCP10: { |
9901 | switch (OpNum) { |
9902 | case 0: |
9903 | // op: L |
9904 | return 21; |
9905 | case 1: |
9906 | // op: SC |
9907 | return 16; |
9908 | } |
9909 | break; |
9910 | } |
9911 | case PPC::SYNC: |
9912 | case PPC::TSR: |
9913 | case PPC::WAIT: { |
9914 | switch (OpNum) { |
9915 | case 0: |
9916 | // op: L |
9917 | return 21; |
9918 | } |
9919 | break; |
9920 | } |
9921 | case PPC::SC: |
9922 | case PPC::SCV: { |
9923 | switch (OpNum) { |
9924 | case 0: |
9925 | // op: LEV |
9926 | return 5; |
9927 | } |
9928 | break; |
9929 | } |
9930 | case PPC::B: |
9931 | case PPC::BA: |
9932 | case PPC::BL: |
9933 | case PPC::BL8: |
9934 | case PPC::BL8_NOTOC: |
9935 | case PPC::BL8_NOTOC_RM: |
9936 | case PPC::BL8_NOTOC_TLS: |
9937 | case PPC::BL8_RM: |
9938 | case PPC::BL8_TLS: |
9939 | case PPC::BL8_TLS_: |
9940 | case PPC::BLA: |
9941 | case PPC::BLA8: |
9942 | case PPC::BLA8_RM: |
9943 | case PPC::BLA_RM: |
9944 | case PPC::BL_RM: |
9945 | case PPC::BL_TLS: |
9946 | case PPC::TAILB: |
9947 | case PPC::TAILB8: |
9948 | case PPC::TAILBA: |
9949 | case PPC::TAILBA8: { |
9950 | switch (OpNum) { |
9951 | case 0: |
9952 | // op: LI |
9953 | return 2; |
9954 | } |
9955 | break; |
9956 | } |
9957 | case PPC::BL8_NOP: |
9958 | case PPC::BL8_NOP_RM: |
9959 | case PPC::BL8_NOP_TLS: |
9960 | case PPC::BLA8_NOP: |
9961 | case PPC::BLA8_NOP_RM: |
9962 | case PPC::BL_NOP: |
9963 | case PPC::BL_NOP_RM: { |
9964 | switch (OpNum) { |
9965 | case 0: |
9966 | // op: LI |
9967 | return 34; |
9968 | } |
9969 | break; |
9970 | } |
9971 | case PPC::MBAR: { |
9972 | switch (OpNum) { |
9973 | case 0: |
9974 | // op: MO |
9975 | return 21; |
9976 | } |
9977 | break; |
9978 | } |
9979 | case PPC::TBEGIN: { |
9980 | switch (OpNum) { |
9981 | case 0: |
9982 | // op: R |
9983 | return 21; |
9984 | } |
9985 | break; |
9986 | } |
9987 | case PPC::CP_COPY: |
9988 | case PPC::CP_COPY8: |
9989 | case PPC::DCBA: |
9990 | case PPC::DCBFEP: |
9991 | case PPC::DCBI: |
9992 | case PPC::DCBST: |
9993 | case PPC::DCBSTEP: |
9994 | case PPC::DCBZ: |
9995 | case PPC::DCBZEP: |
9996 | case PPC::DCBZL: |
9997 | case PPC::DCBZLEP: |
9998 | case PPC::DCCCI: |
9999 | case PPC::ICBI: |
10000 | case PPC::ICBIEP: |
10001 | case PPC::ICCCI: |
10002 | case PPC::TLBIVAX: |
10003 | case PPC::TLBSX: { |
10004 | switch (OpNum) { |
10005 | case 0: |
10006 | // op: RA |
10007 | return 16; |
10008 | case 1: |
10009 | // op: RB |
10010 | return 11; |
10011 | } |
10012 | break; |
10013 | } |
10014 | case PPC::RLWNM: |
10015 | case PPC::RLWNM8: |
10016 | case PPC::RLWNM8_rec: |
10017 | case PPC::RLWNM_rec: { |
10018 | switch (OpNum) { |
10019 | case 0: |
10020 | // op: RA |
10021 | return 16; |
10022 | case 1: |
10023 | // op: RS |
10024 | return 21; |
10025 | case 2: |
10026 | // op: RB |
10027 | return 11; |
10028 | case 3: |
10029 | // op: MB |
10030 | return 6; |
10031 | case 4: |
10032 | // op: ME |
10033 | return 1; |
10034 | } |
10035 | break; |
10036 | } |
10037 | case PPC::RLDCL: |
10038 | case PPC::RLDCL_rec: |
10039 | case PPC::RLDCR: |
10040 | case PPC::RLDCR_rec: { |
10041 | switch (OpNum) { |
10042 | case 0: |
10043 | // op: RA |
10044 | return 16; |
10045 | case 1: |
10046 | // op: RS |
10047 | return 21; |
10048 | case 2: |
10049 | // op: RB |
10050 | return 11; |
10051 | case 3: |
10052 | // op: MBE |
10053 | return 5; |
10054 | } |
10055 | break; |
10056 | } |
10057 | case PPC::RLWINM: |
10058 | case PPC::RLWINM8: |
10059 | case PPC::RLWINM8_rec: |
10060 | case PPC::RLWINM_rec: { |
10061 | switch (OpNum) { |
10062 | case 0: |
10063 | // op: RA |
10064 | return 16; |
10065 | case 1: |
10066 | // op: RS |
10067 | return 21; |
10068 | case 2: |
10069 | // op: SH |
10070 | return 11; |
10071 | case 3: |
10072 | // op: MB |
10073 | return 6; |
10074 | case 4: |
10075 | // op: ME |
10076 | return 1; |
10077 | } |
10078 | break; |
10079 | } |
10080 | case PPC::RLDIC: |
10081 | case PPC::RLDICL: |
10082 | case PPC::RLDICL_32: |
10083 | case PPC::RLDICL_32_64: |
10084 | case PPC::RLDICL_32_rec: |
10085 | case PPC::RLDICL_rec: |
10086 | case PPC::RLDICR: |
10087 | case PPC::RLDICR_32: |
10088 | case PPC::RLDICR_rec: |
10089 | case PPC::RLDIC_rec: { |
10090 | switch (OpNum) { |
10091 | case 0: |
10092 | // op: RA |
10093 | return 16; |
10094 | case 1: |
10095 | // op: RS |
10096 | return 21; |
10097 | case 2: |
10098 | // op: SH |
10099 | return 1; |
10100 | case 3: |
10101 | // op: MBE |
10102 | return 5; |
10103 | } |
10104 | break; |
10105 | } |
10106 | case PPC::EXTSWSLI: |
10107 | case PPC::EXTSWSLI_32_64: |
10108 | case PPC::EXTSWSLI_32_64_rec: |
10109 | case PPC::EXTSWSLI_rec: |
10110 | case PPC::SRADI: |
10111 | case PPC::SRADI_32: |
10112 | case PPC::SRADI_rec: { |
10113 | switch (OpNum) { |
10114 | case 0: |
10115 | // op: RA |
10116 | return 16; |
10117 | case 1: |
10118 | // op: RS |
10119 | return 21; |
10120 | case 2: |
10121 | // op: SH |
10122 | return 1; |
10123 | } |
10124 | break; |
10125 | } |
10126 | case PPC::ANDI8_rec: |
10127 | case PPC::ANDIS8_rec: |
10128 | case PPC::ANDIS_rec: |
10129 | case PPC::ANDI_rec: |
10130 | case PPC::ORI: |
10131 | case PPC::ORI8: |
10132 | case PPC::ORIS: |
10133 | case PPC::ORIS8: |
10134 | case PPC::XORI: |
10135 | case PPC::XORI8: |
10136 | case PPC::XORIS: |
10137 | case PPC::XORIS8: { |
10138 | switch (OpNum) { |
10139 | case 0: |
10140 | // op: RA |
10141 | return 16; |
10142 | case 1: |
10143 | // op: RST |
10144 | return 21; |
10145 | case 2: |
10146 | // op: D |
10147 | return 0; |
10148 | } |
10149 | break; |
10150 | } |
10151 | case PPC::AND: |
10152 | case PPC::AND8: |
10153 | case PPC::AND8_rec: |
10154 | case PPC::ANDC: |
10155 | case PPC::ANDC8: |
10156 | case PPC::ANDC8_rec: |
10157 | case PPC::ANDC_rec: |
10158 | case PPC::AND_rec: |
10159 | case PPC::BPERMD: |
10160 | case PPC::CFUGED: |
10161 | case PPC::CMPB: |
10162 | case PPC::CMPB8: |
10163 | case PPC::CNTLZDM: |
10164 | case PPC::CNTTZDM: |
10165 | case PPC::EQV: |
10166 | case PPC::EQV8: |
10167 | case PPC::EQV8_rec: |
10168 | case PPC::EQV_rec: |
10169 | case PPC::NAND: |
10170 | case PPC::NAND8: |
10171 | case PPC::NAND8_rec: |
10172 | case PPC::NAND_rec: |
10173 | case PPC::NOR: |
10174 | case PPC::NOR8: |
10175 | case PPC::NOR8_rec: |
10176 | case PPC::NOR_rec: |
10177 | case PPC::OR: |
10178 | case PPC::OR8: |
10179 | case PPC::OR8_rec: |
10180 | case PPC::ORC: |
10181 | case PPC::ORC8: |
10182 | case PPC::ORC8_rec: |
10183 | case PPC::ORC_rec: |
10184 | case PPC::OR_rec: |
10185 | case PPC::PDEPD: |
10186 | case PPC::PEXTD: |
10187 | case PPC::SLD: |
10188 | case PPC::SLD_rec: |
10189 | case PPC::SLW: |
10190 | case PPC::SLW8: |
10191 | case PPC::SLW8_rec: |
10192 | case PPC::SLW_rec: |
10193 | case PPC::SRAD: |
10194 | case PPC::SRAD_rec: |
10195 | case PPC::SRAW: |
10196 | case PPC::SRAWI: |
10197 | case PPC::SRAWI_rec: |
10198 | case PPC::SRAW_rec: |
10199 | case PPC::SRD: |
10200 | case PPC::SRD_rec: |
10201 | case PPC::SRW: |
10202 | case PPC::SRW8: |
10203 | case PPC::SRW8_rec: |
10204 | case PPC::SRW_rec: |
10205 | case PPC::XOR: |
10206 | case PPC::XOR8: |
10207 | case PPC::XOR8_rec: |
10208 | case PPC::XOR_rec: { |
10209 | switch (OpNum) { |
10210 | case 0: |
10211 | // op: RA |
10212 | return 16; |
10213 | case 1: |
10214 | // op: RST |
10215 | return 21; |
10216 | case 2: |
10217 | // op: RB |
10218 | return 11; |
10219 | } |
10220 | break; |
10221 | } |
10222 | case PPC::BRD: |
10223 | case PPC::BRH: |
10224 | case PPC::BRH8: |
10225 | case PPC::BRW: |
10226 | case PPC::BRW8: |
10227 | case PPC::CBCDTD: |
10228 | case PPC::CBCDTD8: |
10229 | case PPC::CDTBCD: |
10230 | case PPC::CDTBCD8: |
10231 | case PPC::CNTLZD: |
10232 | case PPC::CNTLZD_rec: |
10233 | case PPC::CNTLZW: |
10234 | case PPC::CNTLZW8: |
10235 | case PPC::CNTLZW8_rec: |
10236 | case PPC::CNTLZW_rec: |
10237 | case PPC::CNTTZD: |
10238 | case PPC::CNTTZD_rec: |
10239 | case PPC::CNTTZW: |
10240 | case PPC::CNTTZW8: |
10241 | case PPC::CNTTZW8_rec: |
10242 | case PPC::CNTTZW_rec: |
10243 | case PPC::EXTSB: |
10244 | case PPC::EXTSB8: |
10245 | case PPC::EXTSB8_32_64: |
10246 | case PPC::EXTSB8_rec: |
10247 | case PPC::EXTSB_rec: |
10248 | case PPC::EXTSH: |
10249 | case PPC::EXTSH8: |
10250 | case PPC::EXTSH8_32_64: |
10251 | case PPC::EXTSH8_rec: |
10252 | case PPC::EXTSH_rec: |
10253 | case PPC::EXTSW: |
10254 | case PPC::EXTSW_32: |
10255 | case PPC::EXTSW_32_64: |
10256 | case PPC::EXTSW_32_64_rec: |
10257 | case PPC::EXTSW_rec: |
10258 | case PPC::POPCNTB: |
10259 | case PPC::POPCNTB8: |
10260 | case PPC::POPCNTD: |
10261 | case PPC::POPCNTW: { |
10262 | switch (OpNum) { |
10263 | case 0: |
10264 | // op: RA |
10265 | return 16; |
10266 | case 1: |
10267 | // op: RST |
10268 | return 21; |
10269 | } |
10270 | break; |
10271 | } |
10272 | case PPC::RLWIMI: |
10273 | case PPC::RLWIMI8: |
10274 | case PPC::RLWIMI8_rec: |
10275 | case PPC::RLWIMI_rec: { |
10276 | switch (OpNum) { |
10277 | case 0: |
10278 | // op: RA |
10279 | return 16; |
10280 | case 2: |
10281 | // op: RS |
10282 | return 21; |
10283 | case 3: |
10284 | // op: SH |
10285 | return 11; |
10286 | case 4: |
10287 | // op: MB |
10288 | return 6; |
10289 | case 5: |
10290 | // op: ME |
10291 | return 1; |
10292 | } |
10293 | break; |
10294 | } |
10295 | case PPC::RLDIMI: |
10296 | case PPC::RLDIMI_rec: { |
10297 | switch (OpNum) { |
10298 | case 0: |
10299 | // op: RA |
10300 | return 16; |
10301 | case 2: |
10302 | // op: RS |
10303 | return 21; |
10304 | case 3: |
10305 | // op: SH |
10306 | return 1; |
10307 | case 4: |
10308 | // op: MBE |
10309 | return 5; |
10310 | } |
10311 | break; |
10312 | } |
10313 | case PPC::TABORT: |
10314 | case PPC::TRECLAIM: { |
10315 | switch (OpNum) { |
10316 | case 0: |
10317 | // op: RA |
10318 | return 16; |
10319 | } |
10320 | break; |
10321 | } |
10322 | case PPC::SLBIE: |
10323 | case PPC::TLBIEL: |
10324 | case PPC::TLBLD: |
10325 | case PPC::TLBLI: { |
10326 | switch (OpNum) { |
10327 | case 0: |
10328 | // op: RB |
10329 | return 11; |
10330 | } |
10331 | break; |
10332 | } |
10333 | case PPC::VCNTMBB: |
10334 | case PPC::VCNTMBD: |
10335 | case PPC::VCNTMBH: |
10336 | case PPC::VCNTMBW: { |
10337 | switch (OpNum) { |
10338 | case 0: |
10339 | // op: RD |
10340 | return 21; |
10341 | case 1: |
10342 | // op: VB |
10343 | return 11; |
10344 | case 2: |
10345 | // op: MP |
10346 | return 16; |
10347 | } |
10348 | break; |
10349 | } |
10350 | case PPC::VGNB: { |
10351 | switch (OpNum) { |
10352 | case 0: |
10353 | // op: RD |
10354 | return 21; |
10355 | case 1: |
10356 | // op: VB |
10357 | return 11; |
10358 | case 2: |
10359 | // op: N |
10360 | return 16; |
10361 | } |
10362 | break; |
10363 | } |
10364 | case PPC::MTMSR: |
10365 | case PPC::MTMSRD: { |
10366 | switch (OpNum) { |
10367 | case 0: |
10368 | // op: RS |
10369 | return 21; |
10370 | case 1: |
10371 | // op: L |
10372 | return 16; |
10373 | } |
10374 | break; |
10375 | } |
10376 | case PPC::MFSRIN: |
10377 | case PPC::MTSRIN: { |
10378 | switch (OpNum) { |
10379 | case 0: |
10380 | // op: RS |
10381 | return 21; |
10382 | case 1: |
10383 | // op: RB |
10384 | return 11; |
10385 | } |
10386 | break; |
10387 | } |
10388 | case PPC::MFSR: |
10389 | case PPC::MTSR: { |
10390 | switch (OpNum) { |
10391 | case 0: |
10392 | // op: RS |
10393 | return 21; |
10394 | case 1: |
10395 | // op: SR |
10396 | return 16; |
10397 | } |
10398 | break; |
10399 | } |
10400 | case PPC::WRTEE: { |
10401 | switch (OpNum) { |
10402 | case 0: |
10403 | // op: RS |
10404 | return 21; |
10405 | } |
10406 | break; |
10407 | } |
10408 | case PPC::SETBC: |
10409 | case PPC::SETBC8: |
10410 | case PPC::SETBCR: |
10411 | case PPC::SETBCR8: |
10412 | case PPC::SETNBC: |
10413 | case PPC::SETNBC8: |
10414 | case PPC::SETNBCR: |
10415 | case PPC::SETNBCR8: { |
10416 | switch (OpNum) { |
10417 | case 0: |
10418 | // op: RST |
10419 | return 21; |
10420 | case 1: |
10421 | // op: BI |
10422 | return 16; |
10423 | } |
10424 | break; |
10425 | } |
10426 | case PPC::LI: |
10427 | case PPC::LI8: |
10428 | case PPC::LIS: |
10429 | case PPC::LIS8: |
10430 | case PPC::PLBZ8onlypc: |
10431 | case PPC::PLBZonlypc: |
10432 | case PPC::PLDonlypc: |
10433 | case PPC::PLFDonlypc: |
10434 | case PPC::PLFSonlypc: |
10435 | case PPC::PLHA8onlypc: |
10436 | case PPC::PLHAonlypc: |
10437 | case PPC::PLHZ8onlypc: |
10438 | case PPC::PLHZonlypc: |
10439 | case PPC::PLWA8onlypc: |
10440 | case PPC::PLWAonlypc: |
10441 | case PPC::PLWZ8onlypc: |
10442 | case PPC::PLWZonlypc: |
10443 | case PPC::PLXSDonlypc: |
10444 | case PPC::PLXSSPonlypc: |
10445 | case PPC::PSTB8onlypc: |
10446 | case PPC::PSTBonlypc: |
10447 | case PPC::PSTDonlypc: |
10448 | case PPC::PSTFDonlypc: |
10449 | case PPC::PSTFSonlypc: |
10450 | case PPC::PSTH8onlypc: |
10451 | case PPC::PSTHonlypc: |
10452 | case PPC::PSTW8onlypc: |
10453 | case PPC::PSTWonlypc: |
10454 | case PPC::PSTXSDonlypc: |
10455 | case PPC::PSTXSSPonlypc: { |
10456 | switch (OpNum) { |
10457 | case 0: |
10458 | // op: RST |
10459 | return 21; |
10460 | case 1: |
10461 | // op: D |
10462 | return 0; |
10463 | } |
10464 | break; |
10465 | } |
10466 | case PPC::MFFSCDRNI: { |
10467 | switch (OpNum) { |
10468 | case 0: |
10469 | // op: RST |
10470 | return 21; |
10471 | case 1: |
10472 | // op: DRM |
10473 | return 11; |
10474 | } |
10475 | break; |
10476 | } |
10477 | case PPC::MFFSCDRN: |
10478 | case PPC::MFFSCRN: { |
10479 | switch (OpNum) { |
10480 | case 0: |
10481 | // op: RST |
10482 | return 21; |
10483 | case 1: |
10484 | // op: FRB |
10485 | return 11; |
10486 | } |
10487 | break; |
10488 | } |
10489 | case PPC::MFOCRF: |
10490 | case PPC::MFOCRF8: { |
10491 | switch (OpNum) { |
10492 | case 0: |
10493 | // op: RST |
10494 | return 21; |
10495 | case 1: |
10496 | // op: FXM |
10497 | return 12; |
10498 | } |
10499 | break; |
10500 | } |
10501 | case PPC::ADDI: |
10502 | case PPC::ADDI8: |
10503 | case PPC::ADDIC: |
10504 | case PPC::ADDIC8: |
10505 | case PPC::ADDIC_rec: |
10506 | case PPC::ADDIS: |
10507 | case PPC::ADDIS8: |
10508 | case PPC::LA: |
10509 | case PPC::LA8: |
10510 | case PPC::MULLI: |
10511 | case PPC::MULLI8: |
10512 | case PPC::SUBFIC: |
10513 | case PPC::SUBFIC8: |
10514 | case PPC::TDI: |
10515 | case PPC::TWI: { |
10516 | switch (OpNum) { |
10517 | case 0: |
10518 | // op: RST |
10519 | return 21; |
10520 | case 1: |
10521 | // op: RA |
10522 | return 16; |
10523 | case 2: |
10524 | // op: D |
10525 | return 0; |
10526 | } |
10527 | break; |
10528 | } |
10529 | case PPC::DADD: |
10530 | case PPC::DADDQ: |
10531 | case PPC::DADDQ_rec: |
10532 | case PPC::DADD_rec: |
10533 | case PPC::DDIV: |
10534 | case PPC::DDIVQ: |
10535 | case PPC::DDIVQ_rec: |
10536 | case PPC::DDIV_rec: |
10537 | case PPC::DIEX: |
10538 | case PPC::DIEXQ: |
10539 | case PPC::DIEXQ_rec: |
10540 | case PPC::DIEX_rec: |
10541 | case PPC::DMUL: |
10542 | case PPC::DMULQ: |
10543 | case PPC::DMULQ_rec: |
10544 | case PPC::DMUL_rec: |
10545 | case PPC::DSUB: |
10546 | case PPC::DSUBQ: |
10547 | case PPC::DSUBQ_rec: |
10548 | case PPC::DSUB_rec: |
10549 | case PPC::FCPSGND: |
10550 | case PPC::FCPSGND_rec: |
10551 | case PPC::FCPSGNS: |
10552 | case PPC::FCPSGNS_rec: |
10553 | case PPC::LBARX: |
10554 | case PPC::LBARXL: |
10555 | case PPC::LBEPX: |
10556 | case PPC::LBZCIX: |
10557 | case PPC::LBZX: |
10558 | case PPC::LBZX8: |
10559 | case PPC::LBZXTLS: |
10560 | case PPC::LBZXTLS_: |
10561 | case PPC::LBZXTLS_32: |
10562 | case PPC::LDARX: |
10563 | case PPC::LDARXL: |
10564 | case PPC::LDAT: |
10565 | case PPC::LDBRX: |
10566 | case PPC::LDCIX: |
10567 | case PPC::LDX: |
10568 | case PPC::LDXTLS: |
10569 | case PPC::LDXTLS_: |
10570 | case PPC::LFDEPX: |
10571 | case PPC::LFDX: |
10572 | case PPC::LFDXTLS: |
10573 | case PPC::LFDXTLS_: |
10574 | case PPC::LFIWAX: |
10575 | case PPC::LFIWZX: |
10576 | case PPC::LFSX: |
10577 | case PPC::LFSXTLS: |
10578 | case PPC::LFSXTLS_: |
10579 | case PPC::LHARX: |
10580 | case PPC::LHARXL: |
10581 | case PPC::LHAX: |
10582 | case PPC::LHAX8: |
10583 | case PPC::LHAXTLS: |
10584 | case PPC::LHAXTLS_: |
10585 | case PPC::LHAXTLS_32: |
10586 | case PPC::LHBRX: |
10587 | case PPC::LHBRX8: |
10588 | case PPC::LHEPX: |
10589 | case PPC::LHZCIX: |
10590 | case PPC::LHZX: |
10591 | case PPC::LHZX8: |
10592 | case PPC::LHZXTLS: |
10593 | case PPC::LHZXTLS_: |
10594 | case PPC::LHZXTLS_32: |
10595 | case PPC::LQARX: |
10596 | case PPC::LQARXL: |
10597 | case PPC::LSWI: |
10598 | case PPC::LVEBX: |
10599 | case PPC::LVEHX: |
10600 | case PPC::LVEWX: |
10601 | case PPC::LVSL: |
10602 | case PPC::LVSR: |
10603 | case PPC::LVX: |
10604 | case PPC::LVXL: |
10605 | case PPC::LWARX: |
10606 | case PPC::LWARXL: |
10607 | case PPC::LWAT: |
10608 | case PPC::LWAX: |
10609 | case PPC::LWAXTLS: |
10610 | case PPC::LWAXTLS_: |
10611 | case PPC::LWAXTLS_32: |
10612 | case PPC::LWAX_32: |
10613 | case PPC::LWBRX: |
10614 | case PPC::LWBRX8: |
10615 | case PPC::LWEPX: |
10616 | case PPC::LWZCIX: |
10617 | case PPC::LWZX: |
10618 | case PPC::LWZX8: |
10619 | case PPC::LWZXTLS: |
10620 | case PPC::LWZXTLS_: |
10621 | case PPC::LWZXTLS_32: |
10622 | case PPC::MODSD: |
10623 | case PPC::MODSW: |
10624 | case PPC::MODUD: |
10625 | case PPC::MODUW: |
10626 | case PPC::SPELWZX: |
10627 | case PPC::SPESTWX: |
10628 | case PPC::STBCIX: |
10629 | case PPC::STBCX: |
10630 | case PPC::STBEPX: |
10631 | case PPC::STBX: |
10632 | case PPC::STBX8: |
10633 | case PPC::STBXTLS: |
10634 | case PPC::STBXTLS_: |
10635 | case PPC::STBXTLS_32: |
10636 | case PPC::STDAT: |
10637 | case PPC::STDBRX: |
10638 | case PPC::STDCIX: |
10639 | case PPC::STDCX: |
10640 | case PPC::STDX: |
10641 | case PPC::STDXTLS: |
10642 | case PPC::STDXTLS_: |
10643 | case PPC::STFDEPX: |
10644 | case PPC::STFDX: |
10645 | case PPC::STFDXTLS: |
10646 | case PPC::STFDXTLS_: |
10647 | case PPC::STFIWX: |
10648 | case PPC::STFSX: |
10649 | case PPC::STFSXTLS: |
10650 | case PPC::STFSXTLS_: |
10651 | case PPC::STHBRX: |
10652 | case PPC::STHCIX: |
10653 | case PPC::STHCX: |
10654 | case PPC::STHEPX: |
10655 | case PPC::STHX: |
10656 | case PPC::STHX8: |
10657 | case PPC::STHXTLS: |
10658 | case PPC::STHXTLS_: |
10659 | case PPC::STHXTLS_32: |
10660 | case PPC::STQCX: |
10661 | case PPC::STSWI: |
10662 | case PPC::STVEBX: |
10663 | case PPC::STVEHX: |
10664 | case PPC::STVEWX: |
10665 | case PPC::STVX: |
10666 | case PPC::STVXL: |
10667 | case PPC::STWAT: |
10668 | case PPC::STWBRX: |
10669 | case PPC::STWCIX: |
10670 | case PPC::STWCX: |
10671 | case PPC::STWEPX: |
10672 | case PPC::STWX: |
10673 | case PPC::STWX8: |
10674 | case PPC::STWXTLS: |
10675 | case PPC::STWXTLS_: |
10676 | case PPC::STWXTLS_32: |
10677 | case PPC::TABORTDC: |
10678 | case PPC::TABORTDCI: |
10679 | case PPC::TABORTWC: |
10680 | case PPC::TABORTWCI: |
10681 | case PPC::TD: |
10682 | case PPC::TLBSX2: |
10683 | case PPC::TLBSX2D: |
10684 | case PPC::TW: |
10685 | case PPC::XSADDQP: |
10686 | case PPC::XSADDQPO: |
10687 | case PPC::XSCMPEQQP: |
10688 | case PPC::XSCMPGEQP: |
10689 | case PPC::XSCMPGTQP: |
10690 | case PPC::XSCPSGNQP: |
10691 | case PPC::XSDIVQP: |
10692 | case PPC::XSDIVQPO: |
10693 | case PPC::XSMAXCQP: |
10694 | case PPC::XSMINCQP: |
10695 | case PPC::XSMULQP: |
10696 | case PPC::XSMULQPO: |
10697 | case PPC::XSSUBQP: |
10698 | case PPC::XSSUBQPO: { |
10699 | switch (OpNum) { |
10700 | case 0: |
10701 | // op: RST |
10702 | return 21; |
10703 | case 1: |
10704 | // op: RA |
10705 | return 16; |
10706 | case 2: |
10707 | // op: RB |
10708 | return 11; |
10709 | } |
10710 | break; |
10711 | } |
10712 | case PPC::TLBRE2: |
10713 | case PPC::TLBWE2: { |
10714 | switch (OpNum) { |
10715 | case 0: |
10716 | // op: RST |
10717 | return 21; |
10718 | case 1: |
10719 | // op: RA |
10720 | return 16; |
10721 | case 2: |
10722 | // op: WS |
10723 | return 11; |
10724 | } |
10725 | break; |
10726 | } |
10727 | case PPC::DCFFIX: |
10728 | case PPC::DCFFIXQ: |
10729 | case PPC::DCFFIXQQ: |
10730 | case PPC::DCFFIXQ_rec: |
10731 | case PPC::DCFFIX_rec: |
10732 | case PPC::DCTDP: |
10733 | case PPC::DCTDP_rec: |
10734 | case PPC::DCTFIX: |
10735 | case PPC::DCTFIXQ: |
10736 | case PPC::DCTFIXQQ: |
10737 | case PPC::DCTFIXQ_rec: |
10738 | case PPC::DCTFIX_rec: |
10739 | case PPC::DCTQPQ: |
10740 | case PPC::DCTQPQ_rec: |
10741 | case PPC::DRDPQ: |
10742 | case PPC::DRDPQ_rec: |
10743 | case PPC::DRSP: |
10744 | case PPC::DRSP_rec: |
10745 | case PPC::DXEX: |
10746 | case PPC::DXEXQ: |
10747 | case PPC::DXEXQ_rec: |
10748 | case PPC::DXEX_rec: |
10749 | case PPC::FABSD: |
10750 | case PPC::FABSD_rec: |
10751 | case PPC::FABSS: |
10752 | case PPC::FABSS_rec: |
10753 | case PPC::FCFID: |
10754 | case PPC::FCFIDS: |
10755 | case PPC::FCFIDS_rec: |
10756 | case PPC::FCFIDU: |
10757 | case PPC::FCFIDUS: |
10758 | case PPC::FCFIDUS_rec: |
10759 | case PPC::FCFIDU_rec: |
10760 | case PPC::FCFID_rec: |
10761 | case PPC::FCTID: |
10762 | case PPC::FCTIDU: |
10763 | case PPC::FCTIDUZ: |
10764 | case PPC::FCTIDUZ_rec: |
10765 | case PPC::FCTIDU_rec: |
10766 | case PPC::FCTIDZ: |
10767 | case PPC::FCTIDZ_rec: |
10768 | case PPC::FCTID_rec: |
10769 | case PPC::FCTIW: |
10770 | case PPC::FCTIWU: |
10771 | case PPC::FCTIWUZ: |
10772 | case PPC::FCTIWUZ_rec: |
10773 | case PPC::FCTIWU_rec: |
10774 | case PPC::FCTIWZ: |
10775 | case PPC::FCTIWZ_rec: |
10776 | case PPC::FCTIW_rec: |
10777 | case PPC::FMR: |
10778 | case PPC::FMR_rec: |
10779 | case PPC::FNABSD: |
10780 | case PPC::FNABSD_rec: |
10781 | case PPC::FNABSS: |
10782 | case PPC::FNABSS_rec: |
10783 | case PPC::FNEGD: |
10784 | case PPC::FNEGD_rec: |
10785 | case PPC::FNEGS: |
10786 | case PPC::FNEGS_rec: |
10787 | case PPC::FRE: |
10788 | case PPC::FRES: |
10789 | case PPC::FRES_rec: |
10790 | case PPC::FRE_rec: |
10791 | case PPC::FRIMD: |
10792 | case PPC::FRIMD_rec: |
10793 | case PPC::FRIMS: |
10794 | case PPC::FRIMS_rec: |
10795 | case PPC::FRIND: |
10796 | case PPC::FRIND_rec: |
10797 | case PPC::FRINS: |
10798 | case PPC::FRINS_rec: |
10799 | case PPC::FRIPD: |
10800 | case PPC::FRIPD_rec: |
10801 | case PPC::FRIPS: |
10802 | case PPC::FRIPS_rec: |
10803 | case PPC::FRIZD: |
10804 | case PPC::FRIZD_rec: |
10805 | case PPC::FRIZS: |
10806 | case PPC::FRIZS_rec: |
10807 | case PPC::FRSP: |
10808 | case PPC::FRSP_rec: |
10809 | case PPC::FRSQRTE: |
10810 | case PPC::FRSQRTES: |
10811 | case PPC::FRSQRTES_rec: |
10812 | case PPC::FRSQRTE_rec: |
10813 | case PPC::FSQRT: |
10814 | case PPC::FSQRTS: |
10815 | case PPC::FSQRTS_rec: |
10816 | case PPC::FSQRT_rec: |
10817 | case PPC::SLBFEE_rec: |
10818 | case PPC::SLBIEG: |
10819 | case PPC::SLBMFEE: |
10820 | case PPC::SLBMTE: |
10821 | case PPC::TLBIE: |
10822 | case PPC::XSABSQP: |
10823 | case PPC::XSCVDPQP: |
10824 | case PPC::XSCVQPDP: |
10825 | case PPC::XSCVQPDPO: |
10826 | case PPC::XSCVQPSDZ: |
10827 | case PPC::XSCVQPSQZ: |
10828 | case PPC::XSCVQPSWZ: |
10829 | case PPC::XSCVQPUDZ: |
10830 | case PPC::XSCVQPUQZ: |
10831 | case PPC::XSCVQPUWZ: |
10832 | case PPC::XSCVSDQP: |
10833 | case PPC::XSCVSQQP: |
10834 | case PPC::XSCVUDQP: |
10835 | case PPC::XSCVUQQP: |
10836 | case PPC::XSNABSQP: |
10837 | case PPC::XSNEGQP: |
10838 | case PPC::XSSQRTQP: |
10839 | case PPC::XSSQRTQPO: |
10840 | case PPC::XSXEXPQP: |
10841 | case PPC::XSXSIGQP: { |
10842 | switch (OpNum) { |
10843 | case 0: |
10844 | // op: RST |
10845 | return 21; |
10846 | case 1: |
10847 | // op: RB |
10848 | return 11; |
10849 | } |
10850 | break; |
10851 | } |
10852 | case PPC::MFFSCRNI: { |
10853 | switch (OpNum) { |
10854 | case 0: |
10855 | // op: RST |
10856 | return 21; |
10857 | case 1: |
10858 | // op: RM |
10859 | return 11; |
10860 | } |
10861 | break; |
10862 | } |
10863 | case PPC::MFDCR: |
10864 | case PPC::MFPMR: |
10865 | case PPC::MFSPR: |
10866 | case PPC::MFSPR8: |
10867 | case PPC::MFTB: |
10868 | case PPC::MTDCR: { |
10869 | switch (OpNum) { |
10870 | case 0: |
10871 | // op: RST |
10872 | return 21; |
10873 | case 1: |
10874 | // op: SPR |
10875 | return 11; |
10876 | } |
10877 | break; |
10878 | } |
10879 | case PPC::LBZ: |
10880 | case PPC::LBZ8: |
10881 | case PPC::LFD: |
10882 | case PPC::LFS: |
10883 | case PPC::LHA: |
10884 | case PPC::LHA8: |
10885 | case PPC::LHZ: |
10886 | case PPC::LHZ8: |
10887 | case PPC::LMW: |
10888 | case PPC::LWZ: |
10889 | case PPC::LWZ8: |
10890 | case PPC::PLBZ: |
10891 | case PPC::PLBZ8: |
10892 | case PPC::PLBZ8nopc: |
10893 | case PPC::PLBZ8pc: |
10894 | case PPC::PLBZnopc: |
10895 | case PPC::PLBZpc: |
10896 | case PPC::PLD: |
10897 | case PPC::PLDnopc: |
10898 | case PPC::PLDpc: |
10899 | case PPC::PLFD: |
10900 | case PPC::PLFDnopc: |
10901 | case PPC::PLFDpc: |
10902 | case PPC::PLFS: |
10903 | case PPC::PLFSnopc: |
10904 | case PPC::PLFSpc: |
10905 | case PPC::PLHA: |
10906 | case PPC::PLHA8: |
10907 | case PPC::PLHA8nopc: |
10908 | case PPC::PLHA8pc: |
10909 | case PPC::PLHAnopc: |
10910 | case PPC::PLHApc: |
10911 | case PPC::PLHZ: |
10912 | case PPC::PLHZ8: |
10913 | case PPC::PLHZ8nopc: |
10914 | case PPC::PLHZ8pc: |
10915 | case PPC::PLHZnopc: |
10916 | case PPC::PLHZpc: |
10917 | case PPC::PLWA: |
10918 | case PPC::PLWA8: |
10919 | case PPC::PLWA8nopc: |
10920 | case PPC::PLWA8pc: |
10921 | case PPC::PLWAnopc: |
10922 | case PPC::PLWApc: |
10923 | case PPC::PLWZ: |
10924 | case PPC::PLWZ8: |
10925 | case PPC::PLWZ8nopc: |
10926 | case PPC::PLWZ8pc: |
10927 | case PPC::PLWZnopc: |
10928 | case PPC::PLWZpc: |
10929 | case PPC::PLXSD: |
10930 | case PPC::PLXSDnopc: |
10931 | case PPC::PLXSDpc: |
10932 | case PPC::PLXSSP: |
10933 | case PPC::PLXSSPnopc: |
10934 | case PPC::PLXSSPpc: |
10935 | case PPC::PSTB: |
10936 | case PPC::PSTB8: |
10937 | case PPC::PSTB8nopc: |
10938 | case PPC::PSTB8pc: |
10939 | case PPC::PSTBnopc: |
10940 | case PPC::PSTBpc: |
10941 | case PPC::PSTD: |
10942 | case PPC::PSTDnopc: |
10943 | case PPC::PSTDpc: |
10944 | case PPC::PSTFD: |
10945 | case PPC::PSTFDnopc: |
10946 | case PPC::PSTFDpc: |
10947 | case PPC::PSTFS: |
10948 | case PPC::PSTFSnopc: |
10949 | case PPC::PSTFSpc: |
10950 | case PPC::PSTH: |
10951 | case PPC::PSTH8: |
10952 | case PPC::PSTH8nopc: |
10953 | case PPC::PSTH8pc: |
10954 | case PPC::PSTHnopc: |
10955 | case PPC::PSTHpc: |
10956 | case PPC::PSTW: |
10957 | case PPC::PSTW8: |
10958 | case PPC::PSTW8nopc: |
10959 | case PPC::PSTW8pc: |
10960 | case PPC::PSTWnopc: |
10961 | case PPC::PSTWpc: |
10962 | case PPC::PSTXSD: |
10963 | case PPC::PSTXSDnopc: |
10964 | case PPC::PSTXSDpc: |
10965 | case PPC::PSTXSSP: |
10966 | case PPC::PSTXSSPnopc: |
10967 | case PPC::PSTXSSPpc: |
10968 | case PPC::SPELWZ: |
10969 | case PPC::SPESTW: |
10970 | case PPC::STB: |
10971 | case PPC::STB8: |
10972 | case PPC::STFD: |
10973 | case PPC::STFS: |
10974 | case PPC::STH: |
10975 | case PPC::STH8: |
10976 | case PPC::STMW: |
10977 | case PPC::STW: |
10978 | case PPC::STW8: { |
10979 | switch (OpNum) { |
10980 | case 0: |
10981 | // op: RST |
10982 | return 21; |
10983 | case 2: |
10984 | // op: RA |
10985 | return 16; |
10986 | case 1: |
10987 | // op: D |
10988 | return 0; |
10989 | } |
10990 | break; |
10991 | } |
10992 | case PPC::LD: |
10993 | case PPC::LWA: |
10994 | case PPC::LWA_32: |
10995 | case PPC::LXSD: |
10996 | case PPC::LXSSP: |
10997 | case PPC::STD: |
10998 | case PPC::STQ: |
10999 | case PPC::STXSD: |
11000 | case PPC::STXSSP: { |
11001 | switch (OpNum) { |
11002 | case 0: |
11003 | // op: RST |
11004 | return 21; |
11005 | case 2: |
11006 | // op: RA |
11007 | return 16; |
11008 | case 1: |
11009 | // op: D |
11010 | return 2; |
11011 | } |
11012 | break; |
11013 | } |
11014 | case PPC::LBZUX: |
11015 | case PPC::LBZUX8: |
11016 | case PPC::LDUX: |
11017 | case PPC::LFDUX: |
11018 | case PPC::LFSUX: |
11019 | case PPC::LHAUX: |
11020 | case PPC::LHAUX8: |
11021 | case PPC::LHZUX: |
11022 | case PPC::LHZUX8: |
11023 | case PPC::LWAUX: |
11024 | case PPC::LWZUX: |
11025 | case PPC::LWZUX8: |
11026 | case PPC::XSMADDQP: |
11027 | case PPC::XSMADDQPO: |
11028 | case PPC::XSMSUBQP: |
11029 | case PPC::XSMSUBQPO: |
11030 | case PPC::XSNMADDQP: |
11031 | case PPC::XSNMADDQPO: |
11032 | case PPC::XSNMSUBQP: |
11033 | case PPC::XSNMSUBQPO: { |
11034 | switch (OpNum) { |
11035 | case 0: |
11036 | // op: RST |
11037 | return 21; |
11038 | case 2: |
11039 | // op: RA |
11040 | return 16; |
11041 | case 3: |
11042 | // op: RB |
11043 | return 11; |
11044 | } |
11045 | break; |
11046 | } |
11047 | case PPC::LBZU: |
11048 | case PPC::LBZU8: |
11049 | case PPC::LFDU: |
11050 | case PPC::LFSU: |
11051 | case PPC::LHAU: |
11052 | case PPC::LHAU8: |
11053 | case PPC::LHZU: |
11054 | case PPC::LHZU8: |
11055 | case PPC::LWZU: |
11056 | case PPC::LWZU8: { |
11057 | switch (OpNum) { |
11058 | case 0: |
11059 | // op: RST |
11060 | return 21; |
11061 | case 3: |
11062 | // op: RA |
11063 | return 16; |
11064 | case 2: |
11065 | // op: D |
11066 | return 0; |
11067 | } |
11068 | break; |
11069 | } |
11070 | case PPC::LDU: { |
11071 | switch (OpNum) { |
11072 | case 0: |
11073 | // op: RST |
11074 | return 21; |
11075 | case 3: |
11076 | // op: RA |
11077 | return 16; |
11078 | case 2: |
11079 | // op: D |
11080 | return 2; |
11081 | } |
11082 | break; |
11083 | } |
11084 | case PPC::MFCTR: |
11085 | case PPC::MFCTR8: |
11086 | case PPC::MFFS: |
11087 | case PPC::MFFSCE: |
11088 | case PPC::MFFSL: |
11089 | case PPC::MFFS_rec: |
11090 | case PPC::MFLR: |
11091 | case PPC::MFLR8: |
11092 | case PPC::MFMSR: |
11093 | case PPC::MFTB8: |
11094 | case PPC::MFUDSCR: |
11095 | case PPC::MFVRSAVE: |
11096 | case PPC::MFVRSAVEv: |
11097 | case PPC::MTCTR: |
11098 | case PPC::MTCTR8: |
11099 | case PPC::MTCTR8loop: |
11100 | case PPC::MTCTRloop: |
11101 | case PPC::MTLR: |
11102 | case PPC::MTLR8: |
11103 | case PPC::MTUDSCR: |
11104 | case PPC::MTVRSAVE: { |
11105 | switch (OpNum) { |
11106 | case 0: |
11107 | // op: RST |
11108 | return 21; |
11109 | } |
11110 | break; |
11111 | } |
11112 | case PPC::SETB: |
11113 | case PPC::SETB8: { |
11114 | switch (OpNum) { |
11115 | case 0: |
11116 | // op: RT |
11117 | return 21; |
11118 | case 1: |
11119 | // op: BFA |
11120 | return 18; |
11121 | } |
11122 | break; |
11123 | } |
11124 | case PPC::ADDPCIS: |
11125 | case PPC::MTVSRBMI: { |
11126 | switch (OpNum) { |
11127 | case 0: |
11128 | // op: RT |
11129 | return 21; |
11130 | case 1: |
11131 | // op: D |
11132 | return 0; |
11133 | } |
11134 | break; |
11135 | } |
11136 | case PPC::DARN: { |
11137 | switch (OpNum) { |
11138 | case 0: |
11139 | // op: RT |
11140 | return 21; |
11141 | case 1: |
11142 | // op: L |
11143 | return 16; |
11144 | } |
11145 | break; |
11146 | } |
11147 | case PPC::ISEL: |
11148 | case PPC::ISEL8: { |
11149 | switch (OpNum) { |
11150 | case 0: |
11151 | // op: RT |
11152 | return 21; |
11153 | case 1: |
11154 | // op: RA |
11155 | return 16; |
11156 | case 2: |
11157 | // op: RB |
11158 | return 11; |
11159 | case 3: |
11160 | // op: COND |
11161 | return 6; |
11162 | } |
11163 | break; |
11164 | } |
11165 | case PPC::ADDEX: |
11166 | case PPC::ADDEX8: { |
11167 | switch (OpNum) { |
11168 | case 0: |
11169 | // op: RT |
11170 | return 21; |
11171 | case 1: |
11172 | // op: RA |
11173 | return 16; |
11174 | case 2: |
11175 | // op: RB |
11176 | return 11; |
11177 | case 3: |
11178 | // op: CY |
11179 | return 9; |
11180 | } |
11181 | break; |
11182 | } |
11183 | case PPC::SUBFUS: |
11184 | case PPC::SUBFUS_rec: { |
11185 | switch (OpNum) { |
11186 | case 0: |
11187 | // op: RT |
11188 | return 21; |
11189 | case 1: |
11190 | // op: RA |
11191 | return 16; |
11192 | case 2: |
11193 | // op: RB |
11194 | return 11; |
11195 | case 3: |
11196 | // op: L |
11197 | return 10; |
11198 | } |
11199 | break; |
11200 | } |
11201 | case PPC::MADDHD: |
11202 | case PPC::MADDHDU: |
11203 | case PPC::MADDLD: |
11204 | case PPC::MADDLD8: |
11205 | case PPC::VADDECUQ: |
11206 | case PPC::VADDEUQM: |
11207 | case PPC::VEXTDDVLX: |
11208 | case PPC::VEXTDDVRX: |
11209 | case PPC::VEXTDUBVLX: |
11210 | case PPC::VEXTDUBVRX: |
11211 | case PPC::VEXTDUHVLX: |
11212 | case PPC::VEXTDUHVRX: |
11213 | case PPC::VEXTDUWVLX: |
11214 | case PPC::VEXTDUWVRX: |
11215 | case PPC::VMHADDSHS: |
11216 | case PPC::VMHRADDSHS: |
11217 | case PPC::VMLADDUHM: |
11218 | case PPC::VMSUMCUD: |
11219 | case PPC::VMSUMMBM: |
11220 | case PPC::VMSUMSHM: |
11221 | case PPC::VMSUMSHS: |
11222 | case PPC::VMSUMUBM: |
11223 | case PPC::VMSUMUDM: |
11224 | case PPC::VMSUMUHM: |
11225 | case PPC::VMSUMUHS: |
11226 | case PPC::VPERM: |
11227 | case PPC::VPERMR: |
11228 | case PPC::VSEL: |
11229 | case PPC::VSUBECUQ: |
11230 | case PPC::VSUBEUQM: { |
11231 | switch (OpNum) { |
11232 | case 0: |
11233 | // op: RT |
11234 | return 21; |
11235 | case 1: |
11236 | // op: RA |
11237 | return 16; |
11238 | case 2: |
11239 | // op: RB |
11240 | return 11; |
11241 | case 3: |
11242 | // op: RC |
11243 | return 6; |
11244 | } |
11245 | break; |
11246 | } |
11247 | case PPC::VSLDOI: { |
11248 | switch (OpNum) { |
11249 | case 0: |
11250 | // op: RT |
11251 | return 21; |
11252 | case 1: |
11253 | // op: RA |
11254 | return 16; |
11255 | case 2: |
11256 | // op: RB |
11257 | return 11; |
11258 | case 3: |
11259 | // op: SH |
11260 | return 6; |
11261 | } |
11262 | break; |
11263 | } |
11264 | case PPC::ADD4: |
11265 | case PPC::ADD4O: |
11266 | case PPC::ADD4O_rec: |
11267 | case PPC::ADD4TLS: |
11268 | case PPC::ADD4_rec: |
11269 | case PPC::ADD8: |
11270 | case PPC::ADD8O: |
11271 | case PPC::ADD8O_rec: |
11272 | case PPC::ADD8TLS: |
11273 | case PPC::ADD8TLS_: |
11274 | case PPC::ADD8_rec: |
11275 | case PPC::ADDC: |
11276 | case PPC::ADDC8: |
11277 | case PPC::ADDC8O: |
11278 | case PPC::ADDC8O_rec: |
11279 | case PPC::ADDC8_rec: |
11280 | case PPC::ADDCO: |
11281 | case PPC::ADDCO_rec: |
11282 | case PPC::ADDC_rec: |
11283 | case PPC::ADDE: |
11284 | case PPC::ADDE8: |
11285 | case PPC::ADDE8O: |
11286 | case PPC::ADDE8O_rec: |
11287 | case PPC::ADDE8_rec: |
11288 | case PPC::ADDEO: |
11289 | case PPC::ADDEO_rec: |
11290 | case PPC::ADDE_rec: |
11291 | case PPC::ADDG6S: |
11292 | case PPC::ADDG6S8: |
11293 | case PPC::BRINC: |
11294 | case PPC::DIVD: |
11295 | case PPC::DIVDE: |
11296 | case PPC::DIVDEO: |
11297 | case PPC::DIVDEO_rec: |
11298 | case PPC::DIVDEU: |
11299 | case PPC::DIVDEUO: |
11300 | case PPC::DIVDEUO_rec: |
11301 | case PPC::DIVDEU_rec: |
11302 | case PPC::DIVDE_rec: |
11303 | case PPC::DIVDO: |
11304 | case PPC::DIVDO_rec: |
11305 | case PPC::DIVDU: |
11306 | case PPC::DIVDUO: |
11307 | case PPC::DIVDUO_rec: |
11308 | case PPC::DIVDU_rec: |
11309 | case PPC::DIVD_rec: |
11310 | case PPC::DIVW: |
11311 | case PPC::DIVWE: |
11312 | case PPC::DIVWEO: |
11313 | case PPC::DIVWEO_rec: |
11314 | case PPC::DIVWEU: |
11315 | case PPC::DIVWEUO: |
11316 | case PPC::DIVWEUO_rec: |
11317 | case PPC::DIVWEU_rec: |
11318 | case PPC::DIVWE_rec: |
11319 | case PPC::DIVWO: |
11320 | case PPC::DIVWO_rec: |
11321 | case PPC::DIVWU: |
11322 | case PPC::DIVWUO: |
11323 | case PPC::DIVWUO_rec: |
11324 | case PPC::DIVWU_rec: |
11325 | case PPC::DIVW_rec: |
11326 | case PPC::EFDADD: |
11327 | case PPC::EFDDIV: |
11328 | case PPC::EFDMUL: |
11329 | case PPC::EFDSUB: |
11330 | case PPC::EFSADD: |
11331 | case PPC::EFSDIV: |
11332 | case PPC::EFSMUL: |
11333 | case PPC::EFSSUB: |
11334 | case PPC::EVADDIW: |
11335 | case PPC::EVADDW: |
11336 | case PPC::EVAND: |
11337 | case PPC::EVANDC: |
11338 | case PPC::EVDIVWS: |
11339 | case PPC::EVDIVWU: |
11340 | case PPC::EVEQV: |
11341 | case PPC::EVFSADD: |
11342 | case PPC::EVFSDIV: |
11343 | case PPC::EVFSMUL: |
11344 | case PPC::EVFSSUB: |
11345 | case PPC::EVLDDX: |
11346 | case PPC::EVLDHX: |
11347 | case PPC::EVLDWX: |
11348 | case PPC::EVLHHESPLATX: |
11349 | case PPC::EVLHHOSSPLATX: |
11350 | case PPC::EVLHHOUSPLATX: |
11351 | case PPC::EVLWHEX: |
11352 | case PPC::EVLWHOSX: |
11353 | case PPC::EVLWHOUX: |
11354 | case PPC::EVLWHSPLATX: |
11355 | case PPC::EVLWWSPLATX: |
11356 | case PPC::EVMERGEHI: |
11357 | case PPC::EVMERGEHILO: |
11358 | case PPC::EVMERGELO: |
11359 | case PPC::EVMERGELOHI: |
11360 | case PPC::EVMHEGSMFAA: |
11361 | case PPC::EVMHEGSMFAN: |
11362 | case PPC::EVMHEGSMIAA: |
11363 | case PPC::EVMHEGSMIAN: |
11364 | case PPC::EVMHEGUMIAA: |
11365 | case PPC::EVMHEGUMIAN: |
11366 | case PPC::EVMHESMF: |
11367 | case PPC::EVMHESMFA: |
11368 | case PPC::EVMHESMFAAW: |
11369 | case PPC::EVMHESMFANW: |
11370 | case PPC::EVMHESMI: |
11371 | case PPC::EVMHESMIA: |
11372 | case PPC::EVMHESMIAAW: |
11373 | case PPC::EVMHESMIANW: |
11374 | case PPC::EVMHESSF: |
11375 | case PPC::EVMHESSFA: |
11376 | case PPC::EVMHESSFAAW: |
11377 | case PPC::EVMHESSFANW: |
11378 | case PPC::EVMHESSIAAW: |
11379 | case PPC::EVMHESSIANW: |
11380 | case PPC::EVMHEUMI: |
11381 | case PPC::EVMHEUMIA: |
11382 | case PPC::EVMHEUMIAAW: |
11383 | case PPC::EVMHEUMIANW: |
11384 | case PPC::EVMHEUSIAAW: |
11385 | case PPC::EVMHEUSIANW: |
11386 | case PPC::EVMHOGSMFAA: |
11387 | case PPC::EVMHOGSMFAN: |
11388 | case PPC::EVMHOGSMIAA: |
11389 | case PPC::EVMHOGSMIAN: |
11390 | case PPC::EVMHOGUMIAA: |
11391 | case PPC::EVMHOGUMIAN: |
11392 | case PPC::EVMHOSMF: |
11393 | case PPC::EVMHOSMFA: |
11394 | case PPC::EVMHOSMFAAW: |
11395 | case PPC::EVMHOSMFANW: |
11396 | case PPC::EVMHOSMI: |
11397 | case PPC::EVMHOSMIA: |
11398 | case PPC::EVMHOSMIAAW: |
11399 | case PPC::EVMHOSMIANW: |
11400 | case PPC::EVMHOSSF: |
11401 | case PPC::EVMHOSSFA: |
11402 | case PPC::EVMHOSSFAAW: |
11403 | case PPC::EVMHOSSFANW: |
11404 | case PPC::EVMHOSSIAAW: |
11405 | case PPC::EVMHOSSIANW: |
11406 | case PPC::EVMHOUMI: |
11407 | case PPC::EVMHOUMIA: |
11408 | case PPC::EVMHOUMIAAW: |
11409 | case PPC::EVMHOUMIANW: |
11410 | case PPC::EVMHOUSIAAW: |
11411 | case PPC::EVMHOUSIANW: |
11412 | case PPC::EVMWHSMF: |
11413 | case PPC::EVMWHSMFA: |
11414 | case PPC::EVMWHSMI: |
11415 | case PPC::EVMWHSMIA: |
11416 | case PPC::EVMWHSSF: |
11417 | case PPC::EVMWHSSFA: |
11418 | case PPC::EVMWHUMI: |
11419 | case PPC::EVMWHUMIA: |
11420 | case PPC::EVMWLSMIAAW: |
11421 | case PPC::EVMWLSMIANW: |
11422 | case PPC::EVMWLSSIAAW: |
11423 | case PPC::EVMWLSSIANW: |
11424 | case PPC::EVMWLUMI: |
11425 | case PPC::EVMWLUMIA: |
11426 | case PPC::EVMWLUMIAAW: |
11427 | case PPC::EVMWLUMIANW: |
11428 | case PPC::EVMWLUSIAAW: |
11429 | case PPC::EVMWLUSIANW: |
11430 | case PPC::EVMWSMF: |
11431 | case PPC::EVMWSMFA: |
11432 | case PPC::EVMWSMFAA: |
11433 | case PPC::EVMWSMFAN: |
11434 | case PPC::EVMWSMI: |
11435 | case PPC::EVMWSMIA: |
11436 | case PPC::EVMWSMIAA: |
11437 | case PPC::EVMWSMIAN: |
11438 | case PPC::EVMWSSF: |
11439 | case PPC::EVMWSSFA: |
11440 | case PPC::EVMWSSFAA: |
11441 | case PPC::EVMWSSFAN: |
11442 | case PPC::EVMWUMI: |
11443 | case PPC::EVMWUMIA: |
11444 | case PPC::EVMWUMIAA: |
11445 | case PPC::EVMWUMIAN: |
11446 | case PPC::EVNAND: |
11447 | case PPC::EVNOR: |
11448 | case PPC::EVOR: |
11449 | case PPC::EVORC: |
11450 | case PPC::EVRLW: |
11451 | case PPC::EVRLWI: |
11452 | case PPC::EVSLW: |
11453 | case PPC::EVSLWI: |
11454 | case PPC::EVSRWIS: |
11455 | case PPC::EVSRWIU: |
11456 | case PPC::EVSRWS: |
11457 | case PPC::EVSRWU: |
11458 | case PPC::EVSTDDX: |
11459 | case PPC::EVSTDHX: |
11460 | case PPC::EVSTDWX: |
11461 | case PPC::EVSTWHEX: |
11462 | case PPC::EVSTWHOX: |
11463 | case PPC::EVSTWWEX: |
11464 | case PPC::EVSTWWOX: |
11465 | case PPC::EVSUBFW: |
11466 | case PPC::EVSUBIFW: |
11467 | case PPC::EVXOR: |
11468 | case PPC::MULHD: |
11469 | case PPC::MULHDU: |
11470 | case PPC::MULHDU_rec: |
11471 | case PPC::MULHD_rec: |
11472 | case PPC::MULHW: |
11473 | case PPC::MULHWU: |
11474 | case PPC::MULHWU_rec: |
11475 | case PPC::MULHW_rec: |
11476 | case PPC::MULLD: |
11477 | case PPC::MULLDO: |
11478 | case PPC::MULLDO_rec: |
11479 | case PPC::MULLD_rec: |
11480 | case PPC::MULLW: |
11481 | case PPC::MULLWO: |
11482 | case PPC::MULLWO_rec: |
11483 | case PPC::MULLW_rec: |
11484 | case PPC::SUBF: |
11485 | case PPC::SUBF8: |
11486 | case PPC::SUBF8O: |
11487 | case PPC::SUBF8O_rec: |
11488 | case PPC::SUBF8_rec: |
11489 | case PPC::SUBFC: |
11490 | case PPC::SUBFC8: |
11491 | case PPC::SUBFC8O: |
11492 | case PPC::SUBFC8O_rec: |
11493 | case PPC::SUBFC8_rec: |
11494 | case PPC::SUBFCO: |
11495 | case PPC::SUBFCO_rec: |
11496 | case PPC::SUBFC_rec: |
11497 | case PPC::SUBFE: |
11498 | case PPC::SUBFE8: |
11499 | case PPC::SUBFE8O: |
11500 | case PPC::SUBFE8O_rec: |
11501 | case PPC::SUBFE8_rec: |
11502 | case PPC::SUBFEO: |
11503 | case PPC::SUBFEO_rec: |
11504 | case PPC::SUBFE_rec: |
11505 | case PPC::SUBFO: |
11506 | case PPC::SUBFO_rec: |
11507 | case PPC::SUBF_rec: { |
11508 | switch (OpNum) { |
11509 | case 0: |
11510 | // op: RT |
11511 | return 21; |
11512 | case 1: |
11513 | // op: RA |
11514 | return 16; |
11515 | case 2: |
11516 | // op: RB |
11517 | return 11; |
11518 | } |
11519 | break; |
11520 | } |
11521 | case PPC::VMADDFP: |
11522 | case PPC::VNMSUBFP: { |
11523 | switch (OpNum) { |
11524 | case 0: |
11525 | // op: RT |
11526 | return 21; |
11527 | case 1: |
11528 | // op: RA |
11529 | return 16; |
11530 | case 2: |
11531 | // op: RC |
11532 | return 6; |
11533 | case 3: |
11534 | // op: RB |
11535 | return 11; |
11536 | } |
11537 | break; |
11538 | } |
11539 | case PPC::PADDI: |
11540 | case PPC::PADDI8: |
11541 | case PPC::PADDI8pc: |
11542 | case PPC::PADDIpc: { |
11543 | switch (OpNum) { |
11544 | case 0: |
11545 | // op: RT |
11546 | return 21; |
11547 | case 1: |
11548 | // op: RA |
11549 | return 16; |
11550 | case 2: |
11551 | // op: SI |
11552 | return 0; |
11553 | } |
11554 | break; |
11555 | } |
11556 | case PPC::VPERMXOR: { |
11557 | switch (OpNum) { |
11558 | case 0: |
11559 | // op: RT |
11560 | return 21; |
11561 | case 1: |
11562 | // op: RA |
11563 | return 16; |
11564 | case 3: |
11565 | // op: RC |
11566 | return 6; |
11567 | case 2: |
11568 | // op: RB |
11569 | return 11; |
11570 | } |
11571 | break; |
11572 | } |
11573 | case PPC::ADDME: |
11574 | case PPC::ADDME8: |
11575 | case PPC::ADDME8O: |
11576 | case PPC::ADDME8O_rec: |
11577 | case PPC::ADDME8_rec: |
11578 | case PPC::ADDMEO: |
11579 | case PPC::ADDMEO_rec: |
11580 | case PPC::ADDME_rec: |
11581 | case PPC::ADDZE: |
11582 | case PPC::ADDZE8: |
11583 | case PPC::ADDZE8O: |
11584 | case PPC::ADDZE8O_rec: |
11585 | case PPC::ADDZE8_rec: |
11586 | case PPC::ADDZEO: |
11587 | case PPC::ADDZEO_rec: |
11588 | case PPC::ADDZE_rec: |
11589 | case PPC::EFDABS: |
11590 | case PPC::EFDNABS: |
11591 | case PPC::EFDNEG: |
11592 | case PPC::EFSABS: |
11593 | case PPC::EFSNABS: |
11594 | case PPC::EFSNEG: |
11595 | case PPC::EVABS: |
11596 | case PPC::EVADDSMIAAW: |
11597 | case PPC::EVADDSSIAAW: |
11598 | case PPC::EVADDUMIAAW: |
11599 | case PPC::EVADDUSIAAW: |
11600 | case PPC::EVCNTLSW: |
11601 | case PPC::EVCNTLZW: |
11602 | case PPC::EVEXTSB: |
11603 | case PPC::EVEXTSH: |
11604 | case PPC::EVFSABS: |
11605 | case PPC::EVFSNABS: |
11606 | case PPC::EVFSNEG: |
11607 | case PPC::EVMRA: |
11608 | case PPC::EVNEG: |
11609 | case PPC::EVRNDW: |
11610 | case PPC::EVSPLATFI: |
11611 | case PPC::EVSPLATI: |
11612 | case PPC::EVSUBFSMIAAW: |
11613 | case PPC::EVSUBFSSIAAW: |
11614 | case PPC::EVSUBFUMIAAW: |
11615 | case PPC::EVSUBFUSIAAW: |
11616 | case PPC::NEG: |
11617 | case PPC::NEG8: |
11618 | case PPC::NEG8O: |
11619 | case PPC::NEG8O_rec: |
11620 | case PPC::NEG8_rec: |
11621 | case PPC::NEGO: |
11622 | case PPC::NEGO_rec: |
11623 | case PPC::NEG_rec: |
11624 | case PPC::SUBFME: |
11625 | case PPC::SUBFME8: |
11626 | case PPC::SUBFME8O: |
11627 | case PPC::SUBFME8O_rec: |
11628 | case PPC::SUBFME8_rec: |
11629 | case PPC::SUBFMEO: |
11630 | case PPC::SUBFMEO_rec: |
11631 | case PPC::SUBFME_rec: |
11632 | case PPC::SUBFZE: |
11633 | case PPC::SUBFZE8: |
11634 | case PPC::SUBFZE8O: |
11635 | case PPC::SUBFZE8O_rec: |
11636 | case PPC::SUBFZE8_rec: |
11637 | case PPC::SUBFZEO: |
11638 | case PPC::SUBFZEO_rec: |
11639 | case PPC::SUBFZE_rec: { |
11640 | switch (OpNum) { |
11641 | case 0: |
11642 | // op: RT |
11643 | return 21; |
11644 | case 1: |
11645 | // op: RA |
11646 | return 16; |
11647 | } |
11648 | break; |
11649 | } |
11650 | case PPC::EFDCFS: |
11651 | case PPC::EFDCFSF: |
11652 | case PPC::EFDCFSI: |
11653 | case PPC::EFDCFSID: |
11654 | case PPC::EFDCFUF: |
11655 | case PPC::EFDCFUI: |
11656 | case PPC::EFDCFUID: |
11657 | case PPC::EFDCTSF: |
11658 | case PPC::EFDCTSI: |
11659 | case PPC::EFDCTSIDZ: |
11660 | case PPC::EFDCTSIZ: |
11661 | case PPC::EFDCTUF: |
11662 | case PPC::EFDCTUI: |
11663 | case PPC::EFDCTUIDZ: |
11664 | case PPC::EFDCTUIZ: |
11665 | case PPC::EFSCFD: |
11666 | case PPC::EFSCFSF: |
11667 | case PPC::EFSCFSI: |
11668 | case PPC::EFSCFUF: |
11669 | case PPC::EFSCFUI: |
11670 | case PPC::EFSCTSF: |
11671 | case PPC::EFSCTSI: |
11672 | case PPC::EFSCTSIZ: |
11673 | case PPC::EFSCTUF: |
11674 | case PPC::EFSCTUI: |
11675 | case PPC::EFSCTUIZ: |
11676 | case PPC::EVFSCFSF: |
11677 | case PPC::EVFSCFSI: |
11678 | case PPC::EVFSCFUF: |
11679 | case PPC::EVFSCFUI: |
11680 | case PPC::EVFSCTSF: |
11681 | case PPC::EVFSCTSI: |
11682 | case PPC::EVFSCTSIZ: |
11683 | case PPC::EVFSCTUF: |
11684 | case PPC::EVFSCTUI: |
11685 | case PPC::EVFSCTUIZ: |
11686 | case PPC::SLBMFEV: { |
11687 | switch (OpNum) { |
11688 | case 0: |
11689 | // op: RT |
11690 | return 21; |
11691 | case 1: |
11692 | // op: RB |
11693 | return 11; |
11694 | } |
11695 | break; |
11696 | } |
11697 | case PPC::PLA8pc: |
11698 | case PPC::PLApc: |
11699 | case PPC::PLI: |
11700 | case PPC::PLI8: { |
11701 | switch (OpNum) { |
11702 | case 0: |
11703 | // op: RT |
11704 | return 21; |
11705 | case 1: |
11706 | // op: SI |
11707 | return 0; |
11708 | } |
11709 | break; |
11710 | } |
11711 | case PPC::XSXEXPDP: |
11712 | case PPC::XSXSIGDP: { |
11713 | switch (OpNum) { |
11714 | case 0: |
11715 | // op: RT |
11716 | return 21; |
11717 | case 1: |
11718 | // op: XB |
11719 | return 1; |
11720 | } |
11721 | break; |
11722 | } |
11723 | case PPC::MFBHRBE: { |
11724 | switch (OpNum) { |
11725 | case 0: |
11726 | // op: RT |
11727 | return 21; |
11728 | case 1: |
11729 | // op: imm |
11730 | return 11; |
11731 | } |
11732 | break; |
11733 | } |
11734 | case PPC::EVLDD: |
11735 | case PPC::EVLDH: |
11736 | case PPC::EVLDW: |
11737 | case PPC::EVLHHESPLAT: |
11738 | case PPC::EVLHHOSSPLAT: |
11739 | case PPC::EVLHHOUSPLAT: |
11740 | case PPC::EVLWHE: |
11741 | case PPC::EVLWHOS: |
11742 | case PPC::EVLWHOU: |
11743 | case PPC::EVLWHSPLAT: |
11744 | case PPC::EVLWWSPLAT: |
11745 | case PPC::EVSTDD: |
11746 | case PPC::EVSTDH: |
11747 | case PPC::EVSTDW: |
11748 | case PPC::EVSTWHE: |
11749 | case PPC::EVSTWHO: |
11750 | case PPC::EVSTWWE: |
11751 | case PPC::EVSTWWO: { |
11752 | switch (OpNum) { |
11753 | case 0: |
11754 | // op: RT |
11755 | return 21; |
11756 | case 2: |
11757 | // op: RA |
11758 | return 16; |
11759 | case 1: |
11760 | // op: D |
11761 | return 11; |
11762 | } |
11763 | break; |
11764 | } |
11765 | case PPC::PLA: |
11766 | case PPC::PLA8: { |
11767 | switch (OpNum) { |
11768 | case 0: |
11769 | // op: RT |
11770 | return 21; |
11771 | case 2: |
11772 | // op: SI |
11773 | return 0; |
11774 | } |
11775 | break; |
11776 | } |
11777 | case PPC::MFCR: |
11778 | case PPC::MFCR8: { |
11779 | switch (OpNum) { |
11780 | case 0: |
11781 | // op: RT |
11782 | return 21; |
11783 | } |
11784 | break; |
11785 | } |
11786 | case PPC::LQ: { |
11787 | switch (OpNum) { |
11788 | case 0: |
11789 | // op: RTp |
11790 | return 21; |
11791 | case 2: |
11792 | // op: RA |
11793 | return 16; |
11794 | case 1: |
11795 | // op: DQ |
11796 | return 4; |
11797 | } |
11798 | break; |
11799 | } |
11800 | case PPC::RFEBB: { |
11801 | switch (OpNum) { |
11802 | case 0: |
11803 | // op: S |
11804 | return 11; |
11805 | } |
11806 | break; |
11807 | } |
11808 | case PPC::DST: |
11809 | case PPC::DST64: |
11810 | case PPC::DSTST: |
11811 | case PPC::DSTST64: |
11812 | case PPC::DSTSTT: |
11813 | case PPC::DSTSTT64: |
11814 | case PPC::DSTT: |
11815 | case PPC::DSTT64: { |
11816 | switch (OpNum) { |
11817 | case 0: |
11818 | // op: STRM |
11819 | return 21; |
11820 | case 1: |
11821 | // op: RA |
11822 | return 16; |
11823 | case 2: |
11824 | // op: RB |
11825 | return 11; |
11826 | } |
11827 | break; |
11828 | } |
11829 | case PPC::DSS: { |
11830 | switch (OpNum) { |
11831 | case 0: |
11832 | // op: STRM |
11833 | return 21; |
11834 | } |
11835 | break; |
11836 | } |
11837 | case PPC::DCBF: |
11838 | case PPC::DCBT: |
11839 | case PPC::DCBTST: { |
11840 | switch (OpNum) { |
11841 | case 0: |
11842 | // op: TH |
11843 | return 21; |
11844 | case 1: |
11845 | // op: RA |
11846 | return 16; |
11847 | case 2: |
11848 | // op: RB |
11849 | return 11; |
11850 | } |
11851 | break; |
11852 | } |
11853 | case PPC::MTVSCR: { |
11854 | switch (OpNum) { |
11855 | case 0: |
11856 | // op: VB |
11857 | return 11; |
11858 | } |
11859 | break; |
11860 | } |
11861 | case PPC::V_SET0: |
11862 | case PPC::V_SET0B: |
11863 | case PPC::V_SET0H: { |
11864 | switch (OpNum) { |
11865 | case 0: |
11866 | // op: VD |
11867 | return 11; |
11868 | } |
11869 | break; |
11870 | } |
11871 | case PPC::VSPLTISB: |
11872 | case PPC::VSPLTISH: |
11873 | case PPC::VSPLTISW: { |
11874 | switch (OpNum) { |
11875 | case 0: |
11876 | // op: VD |
11877 | return 21; |
11878 | case 1: |
11879 | // op: IMM |
11880 | return 16; |
11881 | } |
11882 | break; |
11883 | } |
11884 | case PPC::VSHASIGMAD: |
11885 | case PPC::VSHASIGMAW: { |
11886 | switch (OpNum) { |
11887 | case 0: |
11888 | // op: VD |
11889 | return 21; |
11890 | case 1: |
11891 | // op: VA |
11892 | return 16; |
11893 | case 2: |
11894 | // op: ST |
11895 | return 15; |
11896 | case 3: |
11897 | // op: SIX |
11898 | return 11; |
11899 | } |
11900 | break; |
11901 | } |
11902 | case PPC::BCDADD_rec: |
11903 | case PPC::BCDSR_rec: |
11904 | case PPC::BCDSUB_rec: |
11905 | case PPC::BCDS_rec: |
11906 | case PPC::BCDTRUNC_rec: { |
11907 | switch (OpNum) { |
11908 | case 0: |
11909 | // op: VD |
11910 | return 21; |
11911 | case 1: |
11912 | // op: VA |
11913 | return 16; |
11914 | case 2: |
11915 | // op: VB |
11916 | return 11; |
11917 | case 3: |
11918 | // op: PS |
11919 | return 9; |
11920 | } |
11921 | break; |
11922 | } |
11923 | case PPC::BCDCPSGN_rec: |
11924 | case PPC::BCDUS_rec: |
11925 | case PPC::BCDUTRUNC_rec: |
11926 | case PPC::VABSDUB: |
11927 | case PPC::VABSDUH: |
11928 | case PPC::VABSDUW: |
11929 | case PPC::VADDCUQ: |
11930 | case PPC::VADDCUW: |
11931 | case PPC::VADDFP: |
11932 | case PPC::VADDSBS: |
11933 | case PPC::VADDSHS: |
11934 | case PPC::VADDSWS: |
11935 | case PPC::VADDUBM: |
11936 | case PPC::VADDUBS: |
11937 | case PPC::VADDUDM: |
11938 | case PPC::VADDUHM: |
11939 | case PPC::VADDUHS: |
11940 | case PPC::VADDUQM: |
11941 | case PPC::VADDUWM: |
11942 | case PPC::VADDUWS: |
11943 | case PPC::VAND: |
11944 | case PPC::VANDC: |
11945 | case PPC::VAVGSB: |
11946 | case PPC::VAVGSH: |
11947 | case PPC::VAVGSW: |
11948 | case PPC::VAVGUB: |
11949 | case PPC::VAVGUH: |
11950 | case PPC::VAVGUW: |
11951 | case PPC::VBPERMD: |
11952 | case PPC::VBPERMQ: |
11953 | case PPC::VCFSX: |
11954 | case PPC::VCFUGED: |
11955 | case PPC::VCFUX: |
11956 | case PPC::VCIPHER: |
11957 | case PPC::VCIPHERLAST: |
11958 | case PPC::VCLRLB: |
11959 | case PPC::VCLRRB: |
11960 | case PPC::VCLZDM: |
11961 | case PPC::VCMPBFP: |
11962 | case PPC::VCMPBFP_rec: |
11963 | case PPC::VCMPEQFP: |
11964 | case PPC::VCMPEQFP_rec: |
11965 | case PPC::VCMPEQUB: |
11966 | case PPC::VCMPEQUB_rec: |
11967 | case PPC::VCMPEQUD: |
11968 | case PPC::VCMPEQUD_rec: |
11969 | case PPC::VCMPEQUH: |
11970 | case PPC::VCMPEQUH_rec: |
11971 | case PPC::VCMPEQUQ: |
11972 | case PPC::VCMPEQUQ_rec: |
11973 | case PPC::VCMPEQUW: |
11974 | case PPC::VCMPEQUW_rec: |
11975 | case PPC::VCMPGEFP: |
11976 | case PPC::VCMPGEFP_rec: |
11977 | case PPC::VCMPGTFP: |
11978 | case PPC::VCMPGTFP_rec: |
11979 | case PPC::VCMPGTSB: |
11980 | case PPC::VCMPGTSB_rec: |
11981 | case PPC::VCMPGTSD: |
11982 | case PPC::VCMPGTSD_rec: |
11983 | case PPC::VCMPGTSH: |
11984 | case PPC::VCMPGTSH_rec: |
11985 | case PPC::VCMPGTSQ: |
11986 | case PPC::VCMPGTSQ_rec: |
11987 | case PPC::VCMPGTSW: |
11988 | case PPC::VCMPGTSW_rec: |
11989 | case PPC::VCMPGTUB: |
11990 | case PPC::VCMPGTUB_rec: |
11991 | case PPC::VCMPGTUD: |
11992 | case PPC::VCMPGTUD_rec: |
11993 | case PPC::VCMPGTUH: |
11994 | case PPC::VCMPGTUH_rec: |
11995 | case PPC::VCMPGTUQ: |
11996 | case PPC::VCMPGTUQ_rec: |
11997 | case PPC::VCMPGTUW: |
11998 | case PPC::VCMPGTUW_rec: |
11999 | case PPC::VCMPNEB: |
12000 | case PPC::VCMPNEB_rec: |
12001 | case PPC::VCMPNEH: |
12002 | case PPC::VCMPNEH_rec: |
12003 | case PPC::VCMPNEW: |
12004 | case PPC::VCMPNEW_rec: |
12005 | case PPC::VCMPNEZB: |
12006 | case PPC::VCMPNEZB_rec: |
12007 | case PPC::VCMPNEZH: |
12008 | case PPC::VCMPNEZH_rec: |
12009 | case PPC::VCMPNEZW: |
12010 | case PPC::VCMPNEZW_rec: |
12011 | case PPC::VCTSXS: |
12012 | case PPC::VCTUXS: |
12013 | case PPC::VCTZDM: |
12014 | case PPC::VDIVESD: |
12015 | case PPC::VDIVESQ: |
12016 | case PPC::VDIVESW: |
12017 | case PPC::VDIVEUD: |
12018 | case PPC::VDIVEUQ: |
12019 | case PPC::VDIVEUW: |
12020 | case PPC::VDIVSD: |
12021 | case PPC::VDIVSQ: |
12022 | case PPC::VDIVSW: |
12023 | case PPC::VDIVUD: |
12024 | case PPC::VDIVUQ: |
12025 | case PPC::VDIVUW: |
12026 | case PPC::VEQV: |
12027 | case PPC::VEXTRACTD: |
12028 | case PPC::VEXTRACTUB: |
12029 | case PPC::VEXTRACTUH: |
12030 | case PPC::VEXTRACTUW: |
12031 | case PPC::VEXTUBLX: |
12032 | case PPC::VEXTUBRX: |
12033 | case PPC::VEXTUHLX: |
12034 | case PPC::VEXTUHRX: |
12035 | case PPC::VEXTUWLX: |
12036 | case PPC::VEXTUWRX: |
12037 | case PPC::VINSERTD: |
12038 | case PPC::VINSERTW: |
12039 | case PPC::VMAXFP: |
12040 | case PPC::VMAXSB: |
12041 | case PPC::VMAXSD: |
12042 | case PPC::VMAXSH: |
12043 | case PPC::VMAXSW: |
12044 | case PPC::VMAXUB: |
12045 | case PPC::VMAXUD: |
12046 | case PPC::VMAXUH: |
12047 | case PPC::VMAXUW: |
12048 | case PPC::VMINFP: |
12049 | case PPC::VMINSB: |
12050 | case PPC::VMINSD: |
12051 | case PPC::VMINSH: |
12052 | case PPC::VMINSW: |
12053 | case PPC::VMINUB: |
12054 | case PPC::VMINUD: |
12055 | case PPC::VMINUH: |
12056 | case PPC::VMINUW: |
12057 | case PPC::VMODSD: |
12058 | case PPC::VMODSQ: |
12059 | case PPC::VMODSW: |
12060 | case PPC::VMODUD: |
12061 | case PPC::VMODUQ: |
12062 | case PPC::VMODUW: |
12063 | case PPC::VMRGEW: |
12064 | case PPC::VMRGHB: |
12065 | case PPC::VMRGHH: |
12066 | case PPC::VMRGHW: |
12067 | case PPC::VMRGLB: |
12068 | case PPC::VMRGLH: |
12069 | case PPC::VMRGLW: |
12070 | case PPC::VMRGOW: |
12071 | case PPC::VMUL10ECUQ: |
12072 | case PPC::VMUL10EUQ: |
12073 | case PPC::VMULESB: |
12074 | case PPC::VMULESD: |
12075 | case PPC::VMULESH: |
12076 | case PPC::VMULESW: |
12077 | case PPC::VMULEUB: |
12078 | case PPC::VMULEUD: |
12079 | case PPC::VMULEUH: |
12080 | case PPC::VMULEUW: |
12081 | case PPC::VMULHSD: |
12082 | case PPC::VMULHSW: |
12083 | case PPC::VMULHUD: |
12084 | case PPC::VMULHUW: |
12085 | case PPC::VMULLD: |
12086 | case PPC::VMULOSB: |
12087 | case PPC::VMULOSD: |
12088 | case PPC::VMULOSH: |
12089 | case PPC::VMULOSW: |
12090 | case PPC::VMULOUB: |
12091 | case PPC::VMULOUD: |
12092 | case PPC::VMULOUH: |
12093 | case PPC::VMULOUW: |
12094 | case PPC::VMULUWM: |
12095 | case PPC::VNAND: |
12096 | case PPC::VNCIPHER: |
12097 | case PPC::VNCIPHERLAST: |
12098 | case PPC::VNOR: |
12099 | case PPC::VOR: |
12100 | case PPC::VORC: |
12101 | case PPC::VPDEPD: |
12102 | case PPC::VPEXTD: |
12103 | case PPC::VPKPX: |
12104 | case PPC::VPKSDSS: |
12105 | case PPC::VPKSDUS: |
12106 | case PPC::VPKSHSS: |
12107 | case PPC::VPKSHUS: |
12108 | case PPC::VPKSWSS: |
12109 | case PPC::VPKSWUS: |
12110 | case PPC::VPKUDUM: |
12111 | case PPC::VPKUDUS: |
12112 | case PPC::VPKUHUM: |
12113 | case PPC::VPKUHUS: |
12114 | case PPC::VPKUWUM: |
12115 | case PPC::VPKUWUS: |
12116 | case PPC::VPMSUMB: |
12117 | case PPC::VPMSUMD: |
12118 | case PPC::VPMSUMH: |
12119 | case PPC::VPMSUMW: |
12120 | case PPC::VRLB: |
12121 | case PPC::VRLD: |
12122 | case PPC::VRLDMI: |
12123 | case PPC::VRLDNM: |
12124 | case PPC::VRLH: |
12125 | case PPC::VRLQ: |
12126 | case PPC::VRLQMI: |
12127 | case PPC::VRLQNM: |
12128 | case PPC::VRLW: |
12129 | case PPC::VRLWMI: |
12130 | case PPC::VRLWNM: |
12131 | case PPC::VSL: |
12132 | case PPC::VSLB: |
12133 | case PPC::VSLD: |
12134 | case PPC::VSLH: |
12135 | case PPC::VSLO: |
12136 | case PPC::VSLQ: |
12137 | case PPC::VSLV: |
12138 | case PPC::VSLW: |
12139 | case PPC::VSPLTB: |
12140 | case PPC::VSPLTBs: |
12141 | case PPC::VSPLTH: |
12142 | case PPC::VSPLTHs: |
12143 | case PPC::VSPLTW: |
12144 | case PPC::VSR: |
12145 | case PPC::VSRAB: |
12146 | case PPC::VSRAD: |
12147 | case PPC::VSRAH: |
12148 | case PPC::VSRAQ: |
12149 | case PPC::VSRAW: |
12150 | case PPC::VSRB: |
12151 | case PPC::VSRD: |
12152 | case PPC::VSRH: |
12153 | case PPC::VSRO: |
12154 | case PPC::VSRQ: |
12155 | case PPC::VSRV: |
12156 | case PPC::VSRW: |
12157 | case PPC::VSUBCUQ: |
12158 | case PPC::VSUBCUW: |
12159 | case PPC::VSUBFP: |
12160 | case PPC::VSUBSBS: |
12161 | case PPC::VSUBSHS: |
12162 | case PPC::VSUBSWS: |
12163 | case PPC::VSUBUBM: |
12164 | case PPC::VSUBUBS: |
12165 | case PPC::VSUBUDM: |
12166 | case PPC::VSUBUHM: |
12167 | case PPC::VSUBUHS: |
12168 | case PPC::VSUBUQM: |
12169 | case PPC::VSUBUWM: |
12170 | case PPC::VSUBUWS: |
12171 | case PPC::VSUM2SWS: |
12172 | case PPC::VSUM4SBS: |
12173 | case PPC::VSUM4SHS: |
12174 | case PPC::VSUM4UBS: |
12175 | case PPC::VSUMSWS: |
12176 | case PPC::VXOR: { |
12177 | switch (OpNum) { |
12178 | case 0: |
12179 | // op: VD |
12180 | return 21; |
12181 | case 1: |
12182 | // op: VA |
12183 | return 16; |
12184 | case 2: |
12185 | // op: VB |
12186 | return 11; |
12187 | } |
12188 | break; |
12189 | } |
12190 | case PPC::VMUL10CUQ: |
12191 | case PPC::VMUL10UQ: |
12192 | case PPC::VSBOX: { |
12193 | switch (OpNum) { |
12194 | case 0: |
12195 | // op: VD |
12196 | return 21; |
12197 | case 1: |
12198 | // op: VA |
12199 | return 16; |
12200 | } |
12201 | break; |
12202 | } |
12203 | case PPC::BCDCFN_rec: |
12204 | case PPC::BCDCFSQ_rec: |
12205 | case PPC::BCDCFZ_rec: |
12206 | case PPC::BCDCTZ_rec: |
12207 | case PPC::BCDSETSGN_rec: { |
12208 | switch (OpNum) { |
12209 | case 0: |
12210 | // op: VD |
12211 | return 21; |
12212 | case 1: |
12213 | // op: VB |
12214 | return 11; |
12215 | case 2: |
12216 | // op: PS |
12217 | return 9; |
12218 | } |
12219 | break; |
12220 | } |
12221 | case PPC::BCDCTN_rec: |
12222 | case PPC::BCDCTSQ_rec: |
12223 | case PPC::MTVSRBM: |
12224 | case PPC::MTVSRDM: |
12225 | case PPC::MTVSRHM: |
12226 | case PPC::MTVSRQM: |
12227 | case PPC::MTVSRWM: |
12228 | case PPC::VCFSX_0: |
12229 | case PPC::VCFUX_0: |
12230 | case PPC::VCLZB: |
12231 | case PPC::VCLZD: |
12232 | case PPC::VCLZH: |
12233 | case PPC::VCLZLSBB: |
12234 | case PPC::VCLZW: |
12235 | case PPC::VCTSXS_0: |
12236 | case PPC::VCTUXS_0: |
12237 | case PPC::VCTZB: |
12238 | case PPC::VCTZD: |
12239 | case PPC::VCTZH: |
12240 | case PPC::VCTZLSBB: |
12241 | case PPC::VCTZW: |
12242 | case PPC::VEXPANDBM: |
12243 | case PPC::VEXPANDDM: |
12244 | case PPC::VEXPANDHM: |
12245 | case PPC::VEXPANDQM: |
12246 | case PPC::VEXPANDWM: |
12247 | case PPC::VEXPTEFP: |
12248 | case PPC::VEXTRACTBM: |
12249 | case PPC::VEXTRACTDM: |
12250 | case PPC::VEXTRACTHM: |
12251 | case PPC::VEXTRACTQM: |
12252 | case PPC::VEXTRACTWM: |
12253 | case PPC::VEXTSB2D: |
12254 | case PPC::VEXTSB2Ds: |
12255 | case PPC::VEXTSB2W: |
12256 | case PPC::VEXTSB2Ws: |
12257 | case PPC::VEXTSD2Q: |
12258 | case PPC::VEXTSH2D: |
12259 | case PPC::VEXTSH2Ds: |
12260 | case PPC::VEXTSH2W: |
12261 | case PPC::VEXTSH2Ws: |
12262 | case PPC::VEXTSW2D: |
12263 | case PPC::VEXTSW2Ds: |
12264 | case PPC::VGBBD: |
12265 | case PPC::VLOGEFP: |
12266 | case PPC::VNEGD: |
12267 | case PPC::VNEGW: |
12268 | case PPC::VPOPCNTB: |
12269 | case PPC::VPOPCNTD: |
12270 | case PPC::VPOPCNTH: |
12271 | case PPC::VPOPCNTW: |
12272 | case PPC::VPRTYBD: |
12273 | case PPC::VPRTYBQ: |
12274 | case PPC::VPRTYBW: |
12275 | case PPC::VREFP: |
12276 | case PPC::VRFIM: |
12277 | case PPC::VRFIN: |
12278 | case PPC::VRFIP: |
12279 | case PPC::VRFIZ: |
12280 | case PPC::VRSQRTEFP: |
12281 | case PPC::VUPKHPX: |
12282 | case PPC::VUPKHSB: |
12283 | case PPC::VUPKHSH: |
12284 | case PPC::VUPKHSW: |
12285 | case PPC::VUPKLPX: |
12286 | case PPC::VUPKLSB: |
12287 | case PPC::VUPKLSH: |
12288 | case PPC::VUPKLSW: { |
12289 | switch (OpNum) { |
12290 | case 0: |
12291 | // op: VD |
12292 | return 21; |
12293 | case 1: |
12294 | // op: VB |
12295 | return 11; |
12296 | } |
12297 | break; |
12298 | } |
12299 | case PPC::VINSBLX: |
12300 | case PPC::VINSBRX: |
12301 | case PPC::VINSBVLX: |
12302 | case PPC::VINSBVRX: |
12303 | case PPC::VINSD: |
12304 | case PPC::VINSDLX: |
12305 | case PPC::VINSDRX: |
12306 | case PPC::VINSERTB: |
12307 | case PPC::VINSERTH: |
12308 | case PPC::VINSHLX: |
12309 | case PPC::VINSHRX: |
12310 | case PPC::VINSHVLX: |
12311 | case PPC::VINSHVRX: |
12312 | case PPC::VINSW: |
12313 | case PPC::VINSWLX: |
12314 | case PPC::VINSWRX: |
12315 | case PPC::VINSWVLX: |
12316 | case PPC::VINSWVRX: { |
12317 | switch (OpNum) { |
12318 | case 0: |
12319 | // op: VD |
12320 | return 21; |
12321 | case 2: |
12322 | // op: VA |
12323 | return 16; |
12324 | case 3: |
12325 | // op: VB |
12326 | return 11; |
12327 | } |
12328 | break; |
12329 | } |
12330 | case PPC::MFVSCR: |
12331 | case PPC::V_SETALLONES: |
12332 | case PPC::V_SETALLONESB: |
12333 | case PPC::V_SETALLONESH: { |
12334 | switch (OpNum) { |
12335 | case 0: |
12336 | // op: VD |
12337 | return 21; |
12338 | } |
12339 | break; |
12340 | } |
12341 | case PPC::XSRQPI: |
12342 | case PPC::XSRQPIX: |
12343 | case PPC::XSRQPXP: { |
12344 | switch (OpNum) { |
12345 | case 0: |
12346 | // op: VRT |
12347 | return 21; |
12348 | case 1: |
12349 | // op: R |
12350 | return 16; |
12351 | case 2: |
12352 | // op: VRB |
12353 | return 11; |
12354 | case 3: |
12355 | // op: idx |
12356 | return 9; |
12357 | } |
12358 | break; |
12359 | } |
12360 | case PPC::VSLDBI: |
12361 | case PPC::VSRDBI: { |
12362 | switch (OpNum) { |
12363 | case 0: |
12364 | // op: VRT |
12365 | return 21; |
12366 | case 1: |
12367 | // op: VRA |
12368 | return 16; |
12369 | case 2: |
12370 | // op: VRB |
12371 | return 11; |
12372 | case 3: |
12373 | // op: SD |
12374 | return 6; |
12375 | } |
12376 | break; |
12377 | } |
12378 | case PPC::VSTRIBL: |
12379 | case PPC::VSTRIBL_rec: |
12380 | case PPC::VSTRIBR: |
12381 | case PPC::VSTRIBR_rec: |
12382 | case PPC::VSTRIHL: |
12383 | case PPC::VSTRIHL_rec: |
12384 | case PPC::VSTRIHR: |
12385 | case PPC::VSTRIHR_rec: { |
12386 | switch (OpNum) { |
12387 | case 0: |
12388 | // op: VT |
12389 | return 21; |
12390 | case 1: |
12391 | // op: VB |
12392 | return 11; |
12393 | } |
12394 | break; |
12395 | } |
12396 | case PPC::PLXVonlypc: |
12397 | case PPC::PSTXVonlypc: { |
12398 | switch (OpNum) { |
12399 | case 0: |
12400 | // op: XST |
12401 | return 21; |
12402 | case 1: |
12403 | // op: D |
12404 | return 0; |
12405 | } |
12406 | break; |
12407 | } |
12408 | case PPC::PLXV: |
12409 | case PPC::PLXVnopc: |
12410 | case PPC::PLXVpc: |
12411 | case PPC::PSTXV: |
12412 | case PPC::PSTXVnopc: |
12413 | case PPC::PSTXVpc: { |
12414 | switch (OpNum) { |
12415 | case 0: |
12416 | // op: XST |
12417 | return 21; |
12418 | case 2: |
12419 | // op: RA |
12420 | return 16; |
12421 | case 1: |
12422 | // op: D |
12423 | return 0; |
12424 | } |
12425 | break; |
12426 | } |
12427 | case PPC::XVTSTDCDP: |
12428 | case PPC::XVTSTDCSP: { |
12429 | switch (OpNum) { |
12430 | case 0: |
12431 | // op: XT |
12432 | return 0; |
12433 | case 1: |
12434 | // op: DCMX |
12435 | return 2; |
12436 | case 2: |
12437 | // op: XB |
12438 | return 1; |
12439 | } |
12440 | break; |
12441 | } |
12442 | case PPC::XXSPLTIB: { |
12443 | switch (OpNum) { |
12444 | case 0: |
12445 | // op: XT |
12446 | return 0; |
12447 | case 1: |
12448 | // op: IMM8 |
12449 | return 11; |
12450 | } |
12451 | break; |
12452 | } |
12453 | case PPC::LXSDX: |
12454 | case PPC::LXSIBZX: |
12455 | case PPC::LXSIHZX: |
12456 | case PPC::LXSIWAX: |
12457 | case PPC::LXSIWZX: |
12458 | case PPC::LXSSPX: |
12459 | case PPC::LXVB16X: |
12460 | case PPC::LXVD2X: |
12461 | case PPC::LXVDSX: |
12462 | case PPC::LXVH8X: |
12463 | case PPC::LXVL: |
12464 | case PPC::LXVLL: |
12465 | case PPC::LXVRBX: |
12466 | case PPC::LXVRDX: |
12467 | case PPC::LXVRHX: |
12468 | case PPC::LXVRL: |
12469 | case PPC::LXVRLL: |
12470 | case PPC::LXVRWX: |
12471 | case PPC::LXVW4X: |
12472 | case PPC::LXVWSX: |
12473 | case PPC::LXVX: |
12474 | case PPC::MTVSRDD: |
12475 | case PPC::STXSDX: |
12476 | case PPC::STXSIBX: |
12477 | case PPC::STXSIBXv: |
12478 | case PPC::STXSIHX: |
12479 | case PPC::STXSIHXv: |
12480 | case PPC::STXSIWX: |
12481 | case PPC::STXSSPX: |
12482 | case PPC::STXVB16X: |
12483 | case PPC::STXVD2X: |
12484 | case PPC::STXVH8X: |
12485 | case PPC::STXVL: |
12486 | case PPC::STXVLL: |
12487 | case PPC::STXVRBX: |
12488 | case PPC::STXVRDX: |
12489 | case PPC::STXVRHX: |
12490 | case PPC::STXVRL: |
12491 | case PPC::STXVRLL: |
12492 | case PPC::STXVRWX: |
12493 | case PPC::STXVW4X: |
12494 | case PPC::STXVX: |
12495 | case PPC::XSIEXPDP: { |
12496 | switch (OpNum) { |
12497 | case 0: |
12498 | // op: XT |
12499 | return 0; |
12500 | case 1: |
12501 | // op: RA |
12502 | return 16; |
12503 | case 2: |
12504 | // op: RB |
12505 | return 11; |
12506 | } |
12507 | break; |
12508 | } |
12509 | case PPC::MTVRD: |
12510 | case PPC::MTVRWA: |
12511 | case PPC::MTVRWZ: |
12512 | case PPC::MTVSRD: |
12513 | case PPC::MTVSRWA: |
12514 | case PPC::MTVSRWS: |
12515 | case PPC::MTVSRWZ: { |
12516 | switch (OpNum) { |
12517 | case 0: |
12518 | // op: XT |
12519 | return 0; |
12520 | case 1: |
12521 | // op: RA |
12522 | return 16; |
12523 | } |
12524 | break; |
12525 | } |
12526 | case PPC::LXVKQ: { |
12527 | switch (OpNum) { |
12528 | case 0: |
12529 | // op: XT |
12530 | return 0; |
12531 | case 1: |
12532 | // op: UIM |
12533 | return 11; |
12534 | } |
12535 | break; |
12536 | } |
12537 | case PPC::XXGENPCVBM: |
12538 | case PPC::XXGENPCVDM: |
12539 | case PPC::XXGENPCVHM: |
12540 | case PPC::XXGENPCVWM: { |
12541 | switch (OpNum) { |
12542 | case 0: |
12543 | // op: XT |
12544 | return 0; |
12545 | case 1: |
12546 | // op: VRB |
12547 | return 11; |
12548 | case 2: |
12549 | // op: IMM |
12550 | return 16; |
12551 | } |
12552 | break; |
12553 | } |
12554 | case PPC::XXPERMDIs: |
12555 | case PPC::XXSLDWIs: { |
12556 | switch (OpNum) { |
12557 | case 0: |
12558 | // op: XT |
12559 | return 0; |
12560 | case 1: |
12561 | // op: XA |
12562 | return 1; |
12563 | case 2: |
12564 | // op: D |
12565 | return 8; |
12566 | } |
12567 | break; |
12568 | } |
12569 | case PPC::XXPERMDI: |
12570 | case PPC::XXSLDWI: { |
12571 | switch (OpNum) { |
12572 | case 0: |
12573 | // op: XT |
12574 | return 0; |
12575 | case 1: |
12576 | // op: XA |
12577 | return 2; |
12578 | case 2: |
12579 | // op: XB |
12580 | return 1; |
12581 | case 3: |
12582 | // op: D |
12583 | return 8; |
12584 | } |
12585 | break; |
12586 | } |
12587 | case PPC::XXEVAL: |
12588 | case PPC::XXPERMX: { |
12589 | switch (OpNum) { |
12590 | case 0: |
12591 | // op: XT |
12592 | return 0; |
12593 | case 1: |
12594 | // op: XA |
12595 | return 2; |
12596 | case 2: |
12597 | // op: XB |
12598 | return 1; |
12599 | case 3: |
12600 | // op: XC |
12601 | return 3; |
12602 | case 4: |
12603 | // op: IMM |
12604 | return 32; |
12605 | } |
12606 | break; |
12607 | } |
12608 | case PPC::XXBLENDVB: |
12609 | case PPC::XXBLENDVD: |
12610 | case PPC::XXBLENDVH: |
12611 | case PPC::XXBLENDVW: |
12612 | case PPC::XXSEL: { |
12613 | switch (OpNum) { |
12614 | case 0: |
12615 | // op: XT |
12616 | return 0; |
12617 | case 1: |
12618 | // op: XA |
12619 | return 2; |
12620 | case 2: |
12621 | // op: XB |
12622 | return 1; |
12623 | case 3: |
12624 | // op: XC |
12625 | return 3; |
12626 | } |
12627 | break; |
12628 | } |
12629 | case PPC::XSADDDP: |
12630 | case PPC::XSADDSP: |
12631 | case PPC::XSCMPEQDP: |
12632 | case PPC::XSCMPGEDP: |
12633 | case PPC::XSCMPGTDP: |
12634 | case PPC::XSCPSGNDP: |
12635 | case PPC::XSDIVDP: |
12636 | case PPC::XSDIVSP: |
12637 | case PPC::XSMAXCDP: |
12638 | case PPC::XSMAXDP: |
12639 | case PPC::XSMAXJDP: |
12640 | case PPC::XSMINCDP: |
12641 | case PPC::XSMINDP: |
12642 | case PPC::XSMINJDP: |
12643 | case PPC::XSMULDP: |
12644 | case PPC::XSMULSP: |
12645 | case PPC::XSSUBDP: |
12646 | case PPC::XSSUBSP: |
12647 | case PPC::XVADDDP: |
12648 | case PPC::XVADDSP: |
12649 | case PPC::XVCMPEQDP: |
12650 | case PPC::XVCMPEQDP_rec: |
12651 | case PPC::XVCMPEQSP: |
12652 | case PPC::XVCMPEQSP_rec: |
12653 | case PPC::XVCMPGEDP: |
12654 | case PPC::XVCMPGEDP_rec: |
12655 | case PPC::XVCMPGESP: |
12656 | case PPC::XVCMPGESP_rec: |
12657 | case PPC::XVCMPGTDP: |
12658 | case PPC::XVCMPGTDP_rec: |
12659 | case PPC::XVCMPGTSP: |
12660 | case PPC::XVCMPGTSP_rec: |
12661 | case PPC::XVCPSGNDP: |
12662 | case PPC::XVCPSGNSP: |
12663 | case PPC::XVDIVDP: |
12664 | case PPC::XVDIVSP: |
12665 | case PPC::XVIEXPDP: |
12666 | case PPC::XVIEXPSP: |
12667 | case PPC::XVMAXDP: |
12668 | case PPC::XVMAXSP: |
12669 | case PPC::XVMINDP: |
12670 | case PPC::XVMINSP: |
12671 | case PPC::XVMULDP: |
12672 | case PPC::XVMULSP: |
12673 | case PPC::XVSUBDP: |
12674 | case PPC::XVSUBSP: |
12675 | case PPC::XXLAND: |
12676 | case PPC::XXLANDC: |
12677 | case PPC::XXLEQV: |
12678 | case PPC::XXLNAND: |
12679 | case PPC::XXLNOR: |
12680 | case PPC::XXLOR: |
12681 | case PPC::XXLORC: |
12682 | case PPC::XXLORf: |
12683 | case PPC::XXLXOR: |
12684 | case PPC::XXMRGHW: |
12685 | case PPC::XXMRGLW: { |
12686 | switch (OpNum) { |
12687 | case 0: |
12688 | // op: XT |
12689 | return 0; |
12690 | case 1: |
12691 | // op: XA |
12692 | return 2; |
12693 | case 2: |
12694 | // op: XB |
12695 | return 1; |
12696 | } |
12697 | break; |
12698 | } |
12699 | case PPC::XXPERM: |
12700 | case PPC::XXPERMR: { |
12701 | switch (OpNum) { |
12702 | case 0: |
12703 | // op: XT |
12704 | return 0; |
12705 | case 1: |
12706 | // op: XA |
12707 | return 2; |
12708 | case 3: |
12709 | // op: XB |
12710 | return 1; |
12711 | } |
12712 | break; |
12713 | } |
12714 | case PPC::XXSPLTW: |
12715 | case PPC::XXSPLTWs: { |
12716 | switch (OpNum) { |
12717 | case 0: |
12718 | // op: XT |
12719 | return 0; |
12720 | case 1: |
12721 | // op: XB |
12722 | return 1; |
12723 | case 2: |
12724 | // op: D |
12725 | return 16; |
12726 | } |
12727 | break; |
12728 | } |
12729 | case PPC::XXEXTRACTUW: { |
12730 | switch (OpNum) { |
12731 | case 0: |
12732 | // op: XT |
12733 | return 0; |
12734 | case 1: |
12735 | // op: XB |
12736 | return 1; |
12737 | case 2: |
12738 | // op: UIM5 |
12739 | return 16; |
12740 | } |
12741 | break; |
12742 | } |
12743 | case PPC::XSABSDP: |
12744 | case PPC::XSCVDPHP: |
12745 | case PPC::XSCVDPSP: |
12746 | case PPC::XSCVDPSPN: |
12747 | case PPC::XSCVDPSXDS: |
12748 | case PPC::XSCVDPSXDSs: |
12749 | case PPC::XSCVDPSXWS: |
12750 | case PPC::XSCVDPSXWSs: |
12751 | case PPC::XSCVDPUXDS: |
12752 | case PPC::XSCVDPUXDSs: |
12753 | case PPC::XSCVDPUXWS: |
12754 | case PPC::XSCVDPUXWSs: |
12755 | case PPC::XSCVHPDP: |
12756 | case PPC::XSCVSPDP: |
12757 | case PPC::XSCVSPDPN: |
12758 | case PPC::XSCVSXDDP: |
12759 | case PPC::XSCVSXDSP: |
12760 | case PPC::XSCVUXDDP: |
12761 | case PPC::XSCVUXDSP: |
12762 | case PPC::XSNABSDP: |
12763 | case PPC::XSNABSDPs: |
12764 | case PPC::XSNEGDP: |
12765 | case PPC::XSRDPI: |
12766 | case PPC::XSRDPIC: |
12767 | case PPC::XSRDPIM: |
12768 | case PPC::XSRDPIP: |
12769 | case PPC::XSRDPIZ: |
12770 | case PPC::XSREDP: |
12771 | case PPC::XSRESP: |
12772 | case PPC::XSRSP: |
12773 | case PPC::XSRSQRTEDP: |
12774 | case PPC::XSRSQRTESP: |
12775 | case PPC::XSSQRTDP: |
12776 | case PPC::XSSQRTSP: |
12777 | case PPC::XVABSDP: |
12778 | case PPC::XVABSSP: |
12779 | case PPC::XVCVBF16SPN: |
12780 | case PPC::XVCVDPSP: |
12781 | case PPC::XVCVDPSXDS: |
12782 | case PPC::XVCVDPSXWS: |
12783 | case PPC::XVCVDPUXDS: |
12784 | case PPC::XVCVDPUXWS: |
12785 | case PPC::XVCVHPSP: |
12786 | case PPC::XVCVSPBF16: |
12787 | case PPC::XVCVSPDP: |
12788 | case PPC::XVCVSPHP: |
12789 | case PPC::XVCVSPSXDS: |
12790 | case PPC::XVCVSPSXWS: |
12791 | case PPC::XVCVSPUXDS: |
12792 | case PPC::XVCVSPUXWS: |
12793 | case PPC::XVCVSXDDP: |
12794 | case PPC::XVCVSXDSP: |
12795 | case PPC::XVCVSXWDP: |
12796 | case PPC::XVCVSXWSP: |
12797 | case PPC::XVCVUXDDP: |
12798 | case PPC::XVCVUXDSP: |
12799 | case PPC::XVCVUXWDP: |
12800 | case PPC::XVCVUXWSP: |
12801 | case PPC::XVNABSDP: |
12802 | case PPC::XVNABSSP: |
12803 | case PPC::XVNEGDP: |
12804 | case PPC::XVNEGSP: |
12805 | case PPC::XVRDPI: |
12806 | case PPC::XVRDPIC: |
12807 | case PPC::XVRDPIM: |
12808 | case PPC::XVRDPIP: |
12809 | case PPC::XVRDPIZ: |
12810 | case PPC::XVREDP: |
12811 | case PPC::XVRESP: |
12812 | case PPC::XVRSPI: |
12813 | case PPC::XVRSPIC: |
12814 | case PPC::XVRSPIM: |
12815 | case PPC::XVRSPIP: |
12816 | case PPC::XVRSPIZ: |
12817 | case PPC::XVRSQRTEDP: |
12818 | case PPC::XVRSQRTESP: |
12819 | case PPC::XVSQRTDP: |
12820 | case PPC::XVSQRTSP: |
12821 | case PPC::XVXEXPDP: |
12822 | case PPC::XVXEXPSP: |
12823 | case PPC::XVXSIGDP: |
12824 | case PPC::XVXSIGSP: |
12825 | case PPC::XXBRD: |
12826 | case PPC::XXBRH: |
12827 | case PPC::XXBRQ: |
12828 | case PPC::XXBRW: { |
12829 | switch (OpNum) { |
12830 | case 0: |
12831 | // op: XT |
12832 | return 0; |
12833 | case 1: |
12834 | // op: XB |
12835 | return 1; |
12836 | } |
12837 | break; |
12838 | } |
12839 | case PPC::XSMADDADP: |
12840 | case PPC::XSMADDASP: |
12841 | case PPC::XSMADDMDP: |
12842 | case PPC::XSMADDMSP: |
12843 | case PPC::XSMSUBADP: |
12844 | case PPC::XSMSUBASP: |
12845 | case PPC::XSMSUBMDP: |
12846 | case PPC::XSMSUBMSP: |
12847 | case PPC::XSNMADDADP: |
12848 | case PPC::XSNMADDASP: |
12849 | case PPC::XSNMADDMDP: |
12850 | case PPC::XSNMADDMSP: |
12851 | case PPC::XSNMSUBADP: |
12852 | case PPC::XSNMSUBASP: |
12853 | case PPC::XSNMSUBMDP: |
12854 | case PPC::XSNMSUBMSP: |
12855 | case PPC::XVMADDADP: |
12856 | case PPC::XVMADDASP: |
12857 | case PPC::XVMADDMDP: |
12858 | case PPC::XVMADDMSP: |
12859 | case PPC::XVMSUBADP: |
12860 | case PPC::XVMSUBASP: |
12861 | case PPC::XVMSUBMDP: |
12862 | case PPC::XVMSUBMSP: |
12863 | case PPC::XVNMADDADP: |
12864 | case PPC::XVNMADDASP: |
12865 | case PPC::XVNMADDMDP: |
12866 | case PPC::XVNMADDMSP: |
12867 | case PPC::XVNMSUBADP: |
12868 | case PPC::XVNMSUBASP: |
12869 | case PPC::XVNMSUBMDP: |
12870 | case PPC::XVNMSUBMSP: { |
12871 | switch (OpNum) { |
12872 | case 0: |
12873 | // op: XT |
12874 | return 0; |
12875 | case 2: |
12876 | // op: XA |
12877 | return 2; |
12878 | case 3: |
12879 | // op: XB |
12880 | return 1; |
12881 | } |
12882 | break; |
12883 | } |
12884 | case PPC::XXINSERTW: { |
12885 | switch (OpNum) { |
12886 | case 0: |
12887 | // op: XT |
12888 | return 0; |
12889 | case 2: |
12890 | // op: XB |
12891 | return 1; |
12892 | case 3: |
12893 | // op: UIM5 |
12894 | return 16; |
12895 | } |
12896 | break; |
12897 | } |
12898 | case PPC::XXLEQVOnes: |
12899 | case PPC::XXLXORdpz: |
12900 | case PPC::XXLXORspz: |
12901 | case PPC::XXLXORz: { |
12902 | switch (OpNum) { |
12903 | case 0: |
12904 | // op: XT |
12905 | return 0; |
12906 | } |
12907 | break; |
12908 | } |
12909 | case PPC::XXSPLTIDP: |
12910 | case PPC::XXSPLTIW: { |
12911 | switch (OpNum) { |
12912 | case 0: |
12913 | // op: XT |
12914 | return 16; |
12915 | case 1: |
12916 | // op: IMM32 |
12917 | return 0; |
12918 | } |
12919 | break; |
12920 | } |
12921 | case PPC::XXSPLTI32DX: { |
12922 | switch (OpNum) { |
12923 | case 0: |
12924 | // op: XT |
12925 | return 16; |
12926 | case 2: |
12927 | // op: IX |
12928 | return 17; |
12929 | case 3: |
12930 | // op: IMM32 |
12931 | return 0; |
12932 | } |
12933 | break; |
12934 | } |
12935 | case PPC::LXV: |
12936 | case PPC::STXV: { |
12937 | switch (OpNum) { |
12938 | case 0: |
12939 | // op: XT |
12940 | return 3; |
12941 | case 2: |
12942 | // op: RA |
12943 | return 16; |
12944 | case 1: |
12945 | // op: DQ |
12946 | return 4; |
12947 | } |
12948 | break; |
12949 | } |
12950 | case PPC::PLXVPonlypc: |
12951 | case PPC::PSTXVPonlypc: { |
12952 | switch (OpNum) { |
12953 | case 0: |
12954 | // op: XTp |
12955 | return 21; |
12956 | case 1: |
12957 | // op: D |
12958 | return 0; |
12959 | } |
12960 | break; |
12961 | } |
12962 | case PPC::LXVPRL: |
12963 | case PPC::LXVPRLL: |
12964 | case PPC::LXVPX: |
12965 | case PPC::STXVPRL: |
12966 | case PPC::STXVPRLL: |
12967 | case PPC::STXVPX: { |
12968 | switch (OpNum) { |
12969 | case 0: |
12970 | // op: XTp |
12971 | return 21; |
12972 | case 1: |
12973 | // op: RA |
12974 | return 16; |
12975 | case 2: |
12976 | // op: RB |
12977 | return 11; |
12978 | } |
12979 | break; |
12980 | } |
12981 | case PPC::PLXVP: |
12982 | case PPC::PLXVPnopc: |
12983 | case PPC::PLXVPpc: |
12984 | case PPC::PSTXVP: |
12985 | case PPC::PSTXVPnopc: |
12986 | case PPC::PSTXVPpc: { |
12987 | switch (OpNum) { |
12988 | case 0: |
12989 | // op: XTp |
12990 | return 21; |
12991 | case 2: |
12992 | // op: RA |
12993 | return 16; |
12994 | case 1: |
12995 | // op: D |
12996 | return 0; |
12997 | } |
12998 | break; |
12999 | } |
13000 | case PPC::LXVP: |
13001 | case PPC::STXVP: { |
13002 | switch (OpNum) { |
13003 | case 0: |
13004 | // op: XTp |
13005 | return 21; |
13006 | case 2: |
13007 | // op: RA |
13008 | return 16; |
13009 | case 1: |
13010 | // op: DQ |
13011 | return 4; |
13012 | } |
13013 | break; |
13014 | } |
13015 | case PPC::EFDCMPEQ: |
13016 | case PPC::EFDCMPGT: |
13017 | case PPC::EFDCMPLT: |
13018 | case PPC::EFDTSTEQ: |
13019 | case PPC::EFDTSTGT: |
13020 | case PPC::EFDTSTLT: |
13021 | case PPC::EFSCMPEQ: |
13022 | case PPC::EFSCMPGT: |
13023 | case PPC::EFSCMPLT: |
13024 | case PPC::EFSTSTEQ: |
13025 | case PPC::EFSTSTGT: |
13026 | case PPC::EFSTSTLT: |
13027 | case PPC::EVCMPEQ: |
13028 | case PPC::EVCMPGTS: |
13029 | case PPC::EVCMPGTU: |
13030 | case PPC::EVCMPLTS: |
13031 | case PPC::EVCMPLTU: |
13032 | case PPC::EVFSCMPEQ: |
13033 | case PPC::EVFSCMPGT: |
13034 | case PPC::EVFSCMPLT: |
13035 | case PPC::EVFSTSTEQ: |
13036 | case PPC::EVFSTSTGT: |
13037 | case PPC::EVFSTSTLT: { |
13038 | switch (OpNum) { |
13039 | case 0: |
13040 | // op: crD |
13041 | return 23; |
13042 | case 1: |
13043 | // op: RA |
13044 | return 16; |
13045 | case 2: |
13046 | // op: RB |
13047 | return 11; |
13048 | } |
13049 | break; |
13050 | } |
13051 | case PPC::DMXXEXTFDMR256: { |
13052 | switch (OpNum) { |
13053 | case 1: |
13054 | // op: AT |
13055 | return 23; |
13056 | case 0: |
13057 | // op: XBp |
13058 | return 1; |
13059 | case 2: |
13060 | // op: P |
13061 | return 11; |
13062 | } |
13063 | break; |
13064 | } |
13065 | case PPC::XXMFACC: |
13066 | case PPC::XXMFACCW: { |
13067 | switch (OpNum) { |
13068 | case 1: |
13069 | // op: AT |
13070 | return 23; |
13071 | } |
13072 | break; |
13073 | } |
13074 | case PPC::BCTRL_LWZinto_toc: |
13075 | case PPC::BCTRL_LWZinto_toc_RM: { |
13076 | switch (OpNum) { |
13077 | case 1: |
13078 | // op: RA |
13079 | return 16; |
13080 | case 0: |
13081 | // op: D |
13082 | return 0; |
13083 | } |
13084 | break; |
13085 | } |
13086 | case PPC::BCTRL8_LDinto_toc: |
13087 | case PPC::BCTRL8_LDinto_toc_RM: { |
13088 | switch (OpNum) { |
13089 | case 1: |
13090 | // op: RA |
13091 | return 16; |
13092 | case 0: |
13093 | // op: D |
13094 | return 2; |
13095 | } |
13096 | break; |
13097 | } |
13098 | case PPC::TLBILX: { |
13099 | switch (OpNum) { |
13100 | case 1: |
13101 | // op: RA |
13102 | return 16; |
13103 | case 2: |
13104 | // op: RB |
13105 | return 11; |
13106 | case 0: |
13107 | // op: T |
13108 | return 21; |
13109 | } |
13110 | break; |
13111 | } |
13112 | case PPC::MTOCRF: |
13113 | case PPC::MTOCRF8: { |
13114 | switch (OpNum) { |
13115 | case 1: |
13116 | // op: RST |
13117 | return 21; |
13118 | case 0: |
13119 | // op: FXM |
13120 | return 12; |
13121 | } |
13122 | break; |
13123 | } |
13124 | case PPC::MTPMR: |
13125 | case PPC::MTSPR: |
13126 | case PPC::MTSPR8: { |
13127 | switch (OpNum) { |
13128 | case 1: |
13129 | // op: RST |
13130 | return 21; |
13131 | case 0: |
13132 | // op: SPR |
13133 | return 11; |
13134 | } |
13135 | break; |
13136 | } |
13137 | case PPC::STBUX: |
13138 | case PPC::STBUX8: |
13139 | case PPC::STDUX: |
13140 | case PPC::STFDUX: |
13141 | case PPC::STFSUX: |
13142 | case PPC::STHUX: |
13143 | case PPC::STHUX8: |
13144 | case PPC::STWUX: |
13145 | case PPC::STWUX8: { |
13146 | switch (OpNum) { |
13147 | case 1: |
13148 | // op: RST |
13149 | return 21; |
13150 | case 2: |
13151 | // op: RA |
13152 | return 16; |
13153 | case 3: |
13154 | // op: RB |
13155 | return 11; |
13156 | } |
13157 | break; |
13158 | } |
13159 | case PPC::STBU: |
13160 | case PPC::STBU8: |
13161 | case PPC::STFDU: |
13162 | case PPC::STFSU: |
13163 | case PPC::STHU: |
13164 | case PPC::STHU8: |
13165 | case PPC::STWU: |
13166 | case PPC::STWU8: { |
13167 | switch (OpNum) { |
13168 | case 1: |
13169 | // op: RST |
13170 | return 21; |
13171 | case 3: |
13172 | // op: RA |
13173 | return 16; |
13174 | case 2: |
13175 | // op: D |
13176 | return 0; |
13177 | } |
13178 | break; |
13179 | } |
13180 | case PPC::STDU: { |
13181 | switch (OpNum) { |
13182 | case 1: |
13183 | // op: RST |
13184 | return 21; |
13185 | case 3: |
13186 | // op: RA |
13187 | return 16; |
13188 | case 2: |
13189 | // op: D |
13190 | return 2; |
13191 | } |
13192 | break; |
13193 | } |
13194 | case PPC::MTVRSAVEv: { |
13195 | switch (OpNum) { |
13196 | case 1: |
13197 | // op: RST |
13198 | return 21; |
13199 | } |
13200 | break; |
13201 | } |
13202 | case PPC::DENBCD: |
13203 | case PPC::DENBCDQ: |
13204 | case PPC::DENBCDQ_rec: |
13205 | case PPC::DENBCD_rec: { |
13206 | switch (OpNum) { |
13207 | case 1: |
13208 | // op: S |
13209 | return 20; |
13210 | case 0: |
13211 | // op: FRT |
13212 | return 21; |
13213 | case 2: |
13214 | // op: FRB |
13215 | return 11; |
13216 | } |
13217 | break; |
13218 | } |
13219 | case PPC::DDEDPD: |
13220 | case PPC::DDEDPDQ: |
13221 | case PPC::DDEDPDQ_rec: |
13222 | case PPC::DDEDPD_rec: { |
13223 | switch (OpNum) { |
13224 | case 1: |
13225 | // op: SP |
13226 | return 19; |
13227 | case 0: |
13228 | // op: FRT |
13229 | return 21; |
13230 | case 2: |
13231 | // op: FRB |
13232 | return 11; |
13233 | } |
13234 | break; |
13235 | } |
13236 | case PPC::MFVRD: |
13237 | case PPC::MFVRWZ: |
13238 | case PPC::MFVSRD: |
13239 | case PPC::MFVSRLD: |
13240 | case PPC::MFVSRWZ: { |
13241 | switch (OpNum) { |
13242 | case 1: |
13243 | // op: XT |
13244 | return 0; |
13245 | case 0: |
13246 | // op: RA |
13247 | return 16; |
13248 | } |
13249 | break; |
13250 | } |
13251 | case PPC::DMXXEXTFDMR512: |
13252 | case PPC::DMXXEXTFDMR512_HI: { |
13253 | switch (OpNum) { |
13254 | case 2: |
13255 | // op: AT |
13256 | return 23; |
13257 | case 0: |
13258 | // op: XAp |
13259 | return 2; |
13260 | case 1: |
13261 | // op: XBp |
13262 | return 1; |
13263 | } |
13264 | break; |
13265 | } |
13266 | case PPC::CP_PASTE8_rec: |
13267 | case PPC::CP_PASTE_rec: { |
13268 | switch (OpNum) { |
13269 | case 2: |
13270 | // op: L |
13271 | return 21; |
13272 | case 0: |
13273 | // op: RA |
13274 | return 16; |
13275 | case 1: |
13276 | // op: RB |
13277 | return 11; |
13278 | } |
13279 | break; |
13280 | } |
13281 | case PPC::MTFSF: |
13282 | case PPC::MTFSF_rec: { |
13283 | switch (OpNum) { |
13284 | case 2: |
13285 | // op: L |
13286 | return 25; |
13287 | case 0: |
13288 | // op: FLM |
13289 | return 17; |
13290 | case 3: |
13291 | // op: W |
13292 | return 16; |
13293 | case 1: |
13294 | // op: FRB |
13295 | return 11; |
13296 | } |
13297 | break; |
13298 | } |
13299 | case PPC::HASHCHK: |
13300 | case PPC::HASHCHK8: |
13301 | case PPC::HASHCHKP: |
13302 | case PPC::HASHCHKP8: |
13303 | case PPC::HASHST: |
13304 | case PPC::HASHST8: |
13305 | case PPC::HASHSTP: |
13306 | case PPC::HASHSTP8: { |
13307 | switch (OpNum) { |
13308 | case 2: |
13309 | // op: RA |
13310 | return 16; |
13311 | case 1: |
13312 | // op: D |
13313 | return 0; |
13314 | case 0: |
13315 | // op: RB |
13316 | return 11; |
13317 | } |
13318 | break; |
13319 | } |
13320 | case PPC::DCBTEP: |
13321 | case PPC::DCBTSTEP: { |
13322 | switch (OpNum) { |
13323 | case 2: |
13324 | // op: TH |
13325 | return 21; |
13326 | case 0: |
13327 | // op: RA |
13328 | return 16; |
13329 | case 1: |
13330 | // op: RB |
13331 | return 11; |
13332 | } |
13333 | break; |
13334 | } |
13335 | case PPC::EVSEL: { |
13336 | switch (OpNum) { |
13337 | case 3: |
13338 | // op: crD |
13339 | return 0; |
13340 | case 1: |
13341 | // op: RA |
13342 | return 16; |
13343 | case 2: |
13344 | // op: RB |
13345 | return 11; |
13346 | case 0: |
13347 | // op: RT |
13348 | return 21; |
13349 | } |
13350 | break; |
13351 | } |
13352 | } |
13353 | std::string msg; |
13354 | raw_string_ostream Msg(msg); |
13355 | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]" ; |
13356 | report_fatal_error(Msg.str().c_str()); |
13357 | } |
13358 | |
13359 | #endif // GET_OPERAND_BIT_OFFSET |
13360 | |
13361 | |