1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass PPCMCRegisterClasses[];
17
18namespace PPC {
19enum {
20 NoRegister,
21 BP = 1,
22 CARRY = 2,
23 CTR = 3,
24 FP = 4,
25 LR = 5,
26 RM = 6,
27 SPEFSCR = 7,
28 VRSAVE = 8,
29 XER = 9,
30 ZERO = 10,
31 ACC0 = 11,
32 ACC1 = 12,
33 ACC2 = 13,
34 ACC3 = 14,
35 ACC4 = 15,
36 ACC5 = 16,
37 ACC6 = 17,
38 ACC7 = 18,
39 BP8 = 19,
40 CR0 = 20,
41 CR1 = 21,
42 CR2 = 22,
43 CR3 = 23,
44 CR4 = 24,
45 CR5 = 25,
46 CR6 = 26,
47 CR7 = 27,
48 CTR8 = 28,
49 DMR0 = 29,
50 DMR1 = 30,
51 DMR2 = 31,
52 DMR3 = 32,
53 DMR4 = 33,
54 DMR5 = 34,
55 DMR6 = 35,
56 DMR7 = 36,
57 DMRROW0 = 37,
58 DMRROW1 = 38,
59 DMRROW2 = 39,
60 DMRROW3 = 40,
61 DMRROW4 = 41,
62 DMRROW5 = 42,
63 DMRROW6 = 43,
64 DMRROW7 = 44,
65 DMRROW8 = 45,
66 DMRROW9 = 46,
67 DMRROW10 = 47,
68 DMRROW11 = 48,
69 DMRROW12 = 49,
70 DMRROW13 = 50,
71 DMRROW14 = 51,
72 DMRROW15 = 52,
73 DMRROW16 = 53,
74 DMRROW17 = 54,
75 DMRROW18 = 55,
76 DMRROW19 = 56,
77 DMRROW20 = 57,
78 DMRROW21 = 58,
79 DMRROW22 = 59,
80 DMRROW23 = 60,
81 DMRROW24 = 61,
82 DMRROW25 = 62,
83 DMRROW26 = 63,
84 DMRROW27 = 64,
85 DMRROW28 = 65,
86 DMRROW29 = 66,
87 DMRROW30 = 67,
88 DMRROW31 = 68,
89 DMRROW32 = 69,
90 DMRROW33 = 70,
91 DMRROW34 = 71,
92 DMRROW35 = 72,
93 DMRROW36 = 73,
94 DMRROW37 = 74,
95 DMRROW38 = 75,
96 DMRROW39 = 76,
97 DMRROW40 = 77,
98 DMRROW41 = 78,
99 DMRROW42 = 79,
100 DMRROW43 = 80,
101 DMRROW44 = 81,
102 DMRROW45 = 82,
103 DMRROW46 = 83,
104 DMRROW47 = 84,
105 DMRROW48 = 85,
106 DMRROW49 = 86,
107 DMRROW50 = 87,
108 DMRROW51 = 88,
109 DMRROW52 = 89,
110 DMRROW53 = 90,
111 DMRROW54 = 91,
112 DMRROW55 = 92,
113 DMRROW56 = 93,
114 DMRROW57 = 94,
115 DMRROW58 = 95,
116 DMRROW59 = 96,
117 DMRROW60 = 97,
118 DMRROW61 = 98,
119 DMRROW62 = 99,
120 DMRROW63 = 100,
121 DMRROWp0 = 101,
122 DMRROWp1 = 102,
123 DMRROWp2 = 103,
124 DMRROWp3 = 104,
125 DMRROWp4 = 105,
126 DMRROWp5 = 106,
127 DMRROWp6 = 107,
128 DMRROWp7 = 108,
129 DMRROWp8 = 109,
130 DMRROWp9 = 110,
131 DMRROWp10 = 111,
132 DMRROWp11 = 112,
133 DMRROWp12 = 113,
134 DMRROWp13 = 114,
135 DMRROWp14 = 115,
136 DMRROWp15 = 116,
137 DMRROWp16 = 117,
138 DMRROWp17 = 118,
139 DMRROWp18 = 119,
140 DMRROWp19 = 120,
141 DMRROWp20 = 121,
142 DMRROWp21 = 122,
143 DMRROWp22 = 123,
144 DMRROWp23 = 124,
145 DMRROWp24 = 125,
146 DMRROWp25 = 126,
147 DMRROWp26 = 127,
148 DMRROWp27 = 128,
149 DMRROWp28 = 129,
150 DMRROWp29 = 130,
151 DMRROWp30 = 131,
152 DMRROWp31 = 132,
153 DMRp0 = 133,
154 DMRp1 = 134,
155 DMRp2 = 135,
156 DMRp3 = 136,
157 F0 = 137,
158 F1 = 138,
159 F2 = 139,
160 F3 = 140,
161 F4 = 141,
162 F5 = 142,
163 F6 = 143,
164 F7 = 144,
165 F8 = 145,
166 F9 = 146,
167 F10 = 147,
168 F11 = 148,
169 F12 = 149,
170 F13 = 150,
171 F14 = 151,
172 F15 = 152,
173 F16 = 153,
174 F17 = 154,
175 F18 = 155,
176 F19 = 156,
177 F20 = 157,
178 F21 = 158,
179 F22 = 159,
180 F23 = 160,
181 F24 = 161,
182 F25 = 162,
183 F26 = 163,
184 F27 = 164,
185 F28 = 165,
186 F29 = 166,
187 F30 = 167,
188 F31 = 168,
189 FH0 = 169,
190 FH1 = 170,
191 FH2 = 171,
192 FH3 = 172,
193 FH4 = 173,
194 FH5 = 174,
195 FH6 = 175,
196 FH7 = 176,
197 FH8 = 177,
198 FH9 = 178,
199 FH10 = 179,
200 FH11 = 180,
201 FH12 = 181,
202 FH13 = 182,
203 FH14 = 183,
204 FH15 = 184,
205 FH16 = 185,
206 FH17 = 186,
207 FH18 = 187,
208 FH19 = 188,
209 FH20 = 189,
210 FH21 = 190,
211 FH22 = 191,
212 FH23 = 192,
213 FH24 = 193,
214 FH25 = 194,
215 FH26 = 195,
216 FH27 = 196,
217 FH28 = 197,
218 FH29 = 198,
219 FH30 = 199,
220 FH31 = 200,
221 FP8 = 201,
222 Fpair0 = 202,
223 Fpair2 = 203,
224 Fpair4 = 204,
225 Fpair6 = 205,
226 Fpair8 = 206,
227 Fpair10 = 207,
228 Fpair12 = 208,
229 Fpair14 = 209,
230 Fpair16 = 210,
231 Fpair18 = 211,
232 Fpair20 = 212,
233 Fpair22 = 213,
234 Fpair24 = 214,
235 Fpair26 = 215,
236 Fpair28 = 216,
237 Fpair30 = 217,
238 H0 = 218,
239 H1 = 219,
240 H2 = 220,
241 H3 = 221,
242 H4 = 222,
243 H5 = 223,
244 H6 = 224,
245 H7 = 225,
246 H8 = 226,
247 H9 = 227,
248 H10 = 228,
249 H11 = 229,
250 H12 = 230,
251 H13 = 231,
252 H14 = 232,
253 H15 = 233,
254 H16 = 234,
255 H17 = 235,
256 H18 = 236,
257 H19 = 237,
258 H20 = 238,
259 H21 = 239,
260 H22 = 240,
261 H23 = 241,
262 H24 = 242,
263 H25 = 243,
264 H26 = 244,
265 H27 = 245,
266 H28 = 246,
267 H29 = 247,
268 H30 = 248,
269 H31 = 249,
270 LR8 = 250,
271 R0 = 251,
272 R1 = 252,
273 R2 = 253,
274 R3 = 254,
275 R4 = 255,
276 R5 = 256,
277 R6 = 257,
278 R7 = 258,
279 R8 = 259,
280 R9 = 260,
281 R10 = 261,
282 R11 = 262,
283 R12 = 263,
284 R13 = 264,
285 R14 = 265,
286 R15 = 266,
287 R16 = 267,
288 R17 = 268,
289 R18 = 269,
290 R19 = 270,
291 R20 = 271,
292 R21 = 272,
293 R22 = 273,
294 R23 = 274,
295 R24 = 275,
296 R25 = 276,
297 R26 = 277,
298 R27 = 278,
299 R28 = 279,
300 R29 = 280,
301 R30 = 281,
302 R31 = 282,
303 S0 = 283,
304 S1 = 284,
305 S2 = 285,
306 S3 = 286,
307 S4 = 287,
308 S5 = 288,
309 S6 = 289,
310 S7 = 290,
311 S8 = 291,
312 S9 = 292,
313 S10 = 293,
314 S11 = 294,
315 S12 = 295,
316 S13 = 296,
317 S14 = 297,
318 S15 = 298,
319 S16 = 299,
320 S17 = 300,
321 S18 = 301,
322 S19 = 302,
323 S20 = 303,
324 S21 = 304,
325 S22 = 305,
326 S23 = 306,
327 S24 = 307,
328 S25 = 308,
329 S26 = 309,
330 S27 = 310,
331 S28 = 311,
332 S29 = 312,
333 S30 = 313,
334 S31 = 314,
335 UACC0 = 315,
336 UACC1 = 316,
337 UACC2 = 317,
338 UACC3 = 318,
339 UACC4 = 319,
340 UACC5 = 320,
341 UACC6 = 321,
342 UACC7 = 322,
343 V0 = 323,
344 V1 = 324,
345 V2 = 325,
346 V3 = 326,
347 V4 = 327,
348 V5 = 328,
349 V6 = 329,
350 V7 = 330,
351 V8 = 331,
352 V9 = 332,
353 V10 = 333,
354 V11 = 334,
355 V12 = 335,
356 V13 = 336,
357 V14 = 337,
358 V15 = 338,
359 V16 = 339,
360 V17 = 340,
361 V18 = 341,
362 V19 = 342,
363 V20 = 343,
364 V21 = 344,
365 V22 = 345,
366 V23 = 346,
367 V24 = 347,
368 V25 = 348,
369 V26 = 349,
370 V27 = 350,
371 V28 = 351,
372 V29 = 352,
373 V30 = 353,
374 V31 = 354,
375 VF0 = 355,
376 VF1 = 356,
377 VF2 = 357,
378 VF3 = 358,
379 VF4 = 359,
380 VF5 = 360,
381 VF6 = 361,
382 VF7 = 362,
383 VF8 = 363,
384 VF9 = 364,
385 VF10 = 365,
386 VF11 = 366,
387 VF12 = 367,
388 VF13 = 368,
389 VF14 = 369,
390 VF15 = 370,
391 VF16 = 371,
392 VF17 = 372,
393 VF18 = 373,
394 VF19 = 374,
395 VF20 = 375,
396 VF21 = 376,
397 VF22 = 377,
398 VF23 = 378,
399 VF24 = 379,
400 VF25 = 380,
401 VF26 = 381,
402 VF27 = 382,
403 VF28 = 383,
404 VF29 = 384,
405 VF30 = 385,
406 VF31 = 386,
407 VFH0 = 387,
408 VFH1 = 388,
409 VFH2 = 389,
410 VFH3 = 390,
411 VFH4 = 391,
412 VFH5 = 392,
413 VFH6 = 393,
414 VFH7 = 394,
415 VFH8 = 395,
416 VFH9 = 396,
417 VFH10 = 397,
418 VFH11 = 398,
419 VFH12 = 399,
420 VFH13 = 400,
421 VFH14 = 401,
422 VFH15 = 402,
423 VFH16 = 403,
424 VFH17 = 404,
425 VFH18 = 405,
426 VFH19 = 406,
427 VFH20 = 407,
428 VFH21 = 408,
429 VFH22 = 409,
430 VFH23 = 410,
431 VFH24 = 411,
432 VFH25 = 412,
433 VFH26 = 413,
434 VFH27 = 414,
435 VFH28 = 415,
436 VFH29 = 416,
437 VFH30 = 417,
438 VFH31 = 418,
439 VSL0 = 419,
440 VSL1 = 420,
441 VSL2 = 421,
442 VSL3 = 422,
443 VSL4 = 423,
444 VSL5 = 424,
445 VSL6 = 425,
446 VSL7 = 426,
447 VSL8 = 427,
448 VSL9 = 428,
449 VSL10 = 429,
450 VSL11 = 430,
451 VSL12 = 431,
452 VSL13 = 432,
453 VSL14 = 433,
454 VSL15 = 434,
455 VSL16 = 435,
456 VSL17 = 436,
457 VSL18 = 437,
458 VSL19 = 438,
459 VSL20 = 439,
460 VSL21 = 440,
461 VSL22 = 441,
462 VSL23 = 442,
463 VSL24 = 443,
464 VSL25 = 444,
465 VSL26 = 445,
466 VSL27 = 446,
467 VSL28 = 447,
468 VSL29 = 448,
469 VSL30 = 449,
470 VSL31 = 450,
471 VSRp0 = 451,
472 VSRp1 = 452,
473 VSRp2 = 453,
474 VSRp3 = 454,
475 VSRp4 = 455,
476 VSRp5 = 456,
477 VSRp6 = 457,
478 VSRp7 = 458,
479 VSRp8 = 459,
480 VSRp9 = 460,
481 VSRp10 = 461,
482 VSRp11 = 462,
483 VSRp12 = 463,
484 VSRp13 = 464,
485 VSRp14 = 465,
486 VSRp15 = 466,
487 VSRp16 = 467,
488 VSRp17 = 468,
489 VSRp18 = 469,
490 VSRp19 = 470,
491 VSRp20 = 471,
492 VSRp21 = 472,
493 VSRp22 = 473,
494 VSRp23 = 474,
495 VSRp24 = 475,
496 VSRp25 = 476,
497 VSRp26 = 477,
498 VSRp27 = 478,
499 VSRp28 = 479,
500 VSRp29 = 480,
501 VSRp30 = 481,
502 VSRp31 = 482,
503 VSX32 = 483,
504 VSX33 = 484,
505 VSX34 = 485,
506 VSX35 = 486,
507 VSX36 = 487,
508 VSX37 = 488,
509 VSX38 = 489,
510 VSX39 = 490,
511 VSX40 = 491,
512 VSX41 = 492,
513 VSX42 = 493,
514 VSX43 = 494,
515 VSX44 = 495,
516 VSX45 = 496,
517 VSX46 = 497,
518 VSX47 = 498,
519 VSX48 = 499,
520 VSX49 = 500,
521 VSX50 = 501,
522 VSX51 = 502,
523 VSX52 = 503,
524 VSX53 = 504,
525 VSX54 = 505,
526 VSX55 = 506,
527 VSX56 = 507,
528 VSX57 = 508,
529 VSX58 = 509,
530 VSX59 = 510,
531 VSX60 = 511,
532 VSX61 = 512,
533 VSX62 = 513,
534 VSX63 = 514,
535 WACC0 = 515,
536 WACC1 = 516,
537 WACC2 = 517,
538 WACC3 = 518,
539 WACC4 = 519,
540 WACC5 = 520,
541 WACC6 = 521,
542 WACC7 = 522,
543 WACC_HI0 = 523,
544 WACC_HI1 = 524,
545 WACC_HI2 = 525,
546 WACC_HI3 = 526,
547 WACC_HI4 = 527,
548 WACC_HI5 = 528,
549 WACC_HI6 = 529,
550 WACC_HI7 = 530,
551 X0 = 531,
552 X1 = 532,
553 X2 = 533,
554 X3 = 534,
555 X4 = 535,
556 X5 = 536,
557 X6 = 537,
558 X7 = 538,
559 X8 = 539,
560 X9 = 540,
561 X10 = 541,
562 X11 = 542,
563 X12 = 543,
564 X13 = 544,
565 X14 = 545,
566 X15 = 546,
567 X16 = 547,
568 X17 = 548,
569 X18 = 549,
570 X19 = 550,
571 X20 = 551,
572 X21 = 552,
573 X22 = 553,
574 X23 = 554,
575 X24 = 555,
576 X25 = 556,
577 X26 = 557,
578 X27 = 558,
579 X28 = 559,
580 X29 = 560,
581 X30 = 561,
582 X31 = 562,
583 ZERO8 = 563,
584 CR0EQ = 564,
585 CR1EQ = 565,
586 CR2EQ = 566,
587 CR3EQ = 567,
588 CR4EQ = 568,
589 CR5EQ = 569,
590 CR6EQ = 570,
591 CR7EQ = 571,
592 CR0GT = 572,
593 CR1GT = 573,
594 CR2GT = 574,
595 CR3GT = 575,
596 CR4GT = 576,
597 CR5GT = 577,
598 CR6GT = 578,
599 CR7GT = 579,
600 CR0LT = 580,
601 CR1LT = 581,
602 CR2LT = 582,
603 CR3LT = 583,
604 CR4LT = 584,
605 CR5LT = 585,
606 CR6LT = 586,
607 CR7LT = 587,
608 CR0UN = 588,
609 CR1UN = 589,
610 CR2UN = 590,
611 CR3UN = 591,
612 CR4UN = 592,
613 CR5UN = 593,
614 CR6UN = 594,
615 CR7UN = 595,
616 G8p0 = 596,
617 G8p1 = 597,
618 G8p2 = 598,
619 G8p3 = 599,
620 G8p4 = 600,
621 G8p5 = 601,
622 G8p6 = 602,
623 G8p7 = 603,
624 G8p8 = 604,
625 G8p9 = 605,
626 G8p10 = 606,
627 G8p11 = 607,
628 G8p12 = 608,
629 G8p13 = 609,
630 G8p14 = 610,
631 G8p15 = 611,
632 NUM_TARGET_REGS // 612
633};
634} // end namespace PPC
635
636// Register classes
637
638namespace PPC {
639enum {
640 VSSRCRegClassID = 0,
641 GPRCRegClassID = 1,
642 GPRC_NOR0RegClassID = 2,
643 GPRC_and_GPRC_NOR0RegClassID = 3,
644 CRBITRCRegClassID = 4,
645 F4RCRegClassID = 5,
646 GPRC32RegClassID = 6,
647 CRRCRegClassID = 7,
648 CARRYRCRegClassID = 8,
649 CTRRCRegClassID = 9,
650 LRRCRegClassID = 10,
651 VRSAVERCRegClassID = 11,
652 SPILLTOVSRRCRegClassID = 12,
653 VSFRCRegClassID = 13,
654 G8RCRegClassID = 14,
655 G8RC_NOX0RegClassID = 15,
656 SPILLTOVSRRC_and_VSFRCRegClassID = 16,
657 G8RC_and_G8RC_NOX0RegClassID = 17,
658 F8RCRegClassID = 18,
659 FHRCRegClassID = 19,
660 SPERCRegClassID = 20,
661 VFHRCRegClassID = 21,
662 VFRCRegClassID = 22,
663 SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 23,
664 SPILLTOVSRRC_and_VFRCRegClassID = 24,
665 SPILLTOVSRRC_and_F4RCRegClassID = 25,
666 CTRRC8RegClassID = 26,
667 LR8RCRegClassID = 27,
668 DMRROWRCRegClassID = 28,
669 VSRCRegClassID = 29,
670 VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 30,
671 VRRCRegClassID = 31,
672 VSLRCRegClassID = 32,
673 VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 33,
674 FpRCRegClassID = 34,
675 G8pRCRegClassID = 35,
676 G8pRC_with_sub_32_in_GPRC_NOR0RegClassID = 36,
677 VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 37,
678 FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID = 38,
679 DMRROWpRCRegClassID = 39,
680 VSRpRCRegClassID = 40,
681 VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 41,
682 VSRpRC_with_sub_64_in_F4RCRegClassID = 42,
683 VSRpRC_with_sub_64_in_VFRCRegClassID = 43,
684 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID = 44,
685 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID = 45,
686 ACCRCRegClassID = 46,
687 UACCRCRegClassID = 47,
688 WACCRCRegClassID = 48,
689 WACC_HIRCRegClassID = 49,
690 ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 50,
691 UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 51,
692 ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 52,
693 UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 53,
694 DMRRCRegClassID = 54,
695 DMRpRCRegClassID = 55,
696
697};
698} // end namespace PPC
699
700
701// Subregister indices
702
703namespace PPC {
704enum : uint16_t {
705 NoSubRegister,
706 sub_32, // 1
707 sub_32_hi_phony, // 2
708 sub_64, // 3
709 sub_64_hi_phony, // 4
710 sub_dmr0, // 5
711 sub_dmr1, // 6
712 sub_dmrrow0, // 7
713 sub_dmrrow1, // 8
714 sub_dmrrowp0, // 9
715 sub_dmrrowp1, // 10
716 sub_eq, // 11
717 sub_fp0, // 12
718 sub_fp1, // 13
719 sub_gp8_x0, // 14
720 sub_gp8_x1, // 15
721 sub_gt, // 16
722 sub_lt, // 17
723 sub_pair0, // 18
724 sub_pair1, // 19
725 sub_un, // 20
726 sub_vsx0, // 21
727 sub_vsx1, // 22
728 sub_wacc_hi, // 23
729 sub_wacc_lo, // 24
730 sub_vsx1_then_sub_64, // 25
731 sub_vsx1_then_sub_64_hi_phony, // 26
732 sub_pair1_then_sub_64, // 27
733 sub_pair1_then_sub_64_hi_phony, // 28
734 sub_pair1_then_sub_vsx0, // 29
735 sub_pair1_then_sub_vsx1, // 30
736 sub_pair1_then_sub_vsx1_then_sub_64, // 31
737 sub_pair1_then_sub_vsx1_then_sub_64_hi_phony, // 32
738 sub_dmrrowp1_then_sub_dmrrow0, // 33
739 sub_dmrrowp1_then_sub_dmrrow1, // 34
740 sub_wacc_hi_then_sub_dmrrow0, // 35
741 sub_wacc_hi_then_sub_dmrrow1, // 36
742 sub_wacc_hi_then_sub_dmrrowp0, // 37
743 sub_wacc_hi_then_sub_dmrrowp1, // 38
744 sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 39
745 sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 40
746 sub_dmr1_then_sub_dmrrow0, // 41
747 sub_dmr1_then_sub_dmrrow1, // 42
748 sub_dmr1_then_sub_dmrrowp0, // 43
749 sub_dmr1_then_sub_dmrrowp1, // 44
750 sub_dmr1_then_sub_wacc_hi, // 45
751 sub_dmr1_then_sub_wacc_lo, // 46
752 sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, // 47
753 sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, // 48
754 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, // 49
755 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, // 50
756 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, // 51
757 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, // 52
758 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 53
759 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 54
760 sub_gp8_x1_then_sub_32, // 55
761 NUM_TARGET_SUBREGS
762};
763} // end namespace PPC
764
765// Register pressure sets enum.
766namespace PPC {
767enum RegisterPressureSets {
768 CARRYRC = 0,
769 VRSAVERC = 1,
770 SPILLTOVSRRC_and_F4RC = 2,
771 SPILLTOVSRRC_and_VFRC = 3,
772 CRBITRC = 4,
773 F4RC = 5,
774 VFRC = 6,
775 WACCRC = 7,
776 WACC_HIRC = 8,
777 GPRC = 9,
778 SPILLTOVSRRC_and_VSFRC = 10,
779 SPILLTOVSRRC_and_VSFRC_with_VFRC = 11,
780 F4RC_with_SPILLTOVSRRC_and_VSFRC = 12,
781 VSSRC = 13,
782 DMRROWRC = 14,
783 SPILLTOVSRRC = 15,
784 SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC = 16,
785 SPILLTOVSRRC_with_VFRC = 17,
786 F4RC_with_SPILLTOVSRRC = 18,
787 VSSRC_with_SPILLTOVSRRC = 19,
788};
789} // end namespace PPC
790
791} // end namespace llvm
792
793#endif // GET_REGINFO_ENUM
794
795/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
796|* *|
797|* MC Register Information *|
798|* *|
799|* Automatically generated file, do not edit! *|
800|* *|
801\*===----------------------------------------------------------------------===*/
802
803
804#ifdef GET_REGINFO_MC_DESC
805#undef GET_REGINFO_MC_DESC
806
807namespace llvm {
808
809extern const int16_t PPCRegDiffLists[] = {
810 /* 0 */ -568, 0,
811 /* 2 */ -560, 0,
812 /* 4 */ -553, 0,
813 /* 6 */ -552, 0,
814 /* 8 */ -544, 0,
815 /* 10 */ -65, -280, 281, -280, 0,
816 /* 15 */ -64, -280, 281, -280, 0,
817 /* 20 */ -63, -280, 281, -280, 0,
818 /* 25 */ -62, -280, 281, -280, 0,
819 /* 30 */ -61, -280, 281, -280, 0,
820 /* 35 */ -60, -280, 281, -280, 0,
821 /* 40 */ -59, -280, 281, -280, 0,
822 /* 45 */ -58, -280, 281, -280, 0,
823 /* 50 */ -57, -280, 281, -280, 0,
824 /* 55 */ -56, -280, 281, -280, 0,
825 /* 60 */ -55, -280, 281, -280, 0,
826 /* 65 */ -54, -280, 281, -280, 0,
827 /* 70 */ -53, -280, 281, -280, 0,
828 /* 75 */ -52, -280, 281, -280, 0,
829 /* 80 */ -51, -280, 281, -280, 0,
830 /* 85 */ -50, -280, 281, -280, 0,
831 /* 90 */ -197, 0,
832 /* 92 */ -32, -33, 0,
833 /* 95 */ -18, 0,
834 /* 97 */ -65, 1, 0,
835 /* 100 */ -64, 1, 0,
836 /* 103 */ -414, -64, 1, 64, -63, 1, 0,
837 /* 110 */ -62, 1, 0,
838 /* 113 */ 486, -414, -64, 1, 64, -63, 1, 483, -420, -62, 1, 62, -61, 1, 0,
839 /* 128 */ -60, 1, 0,
840 /* 131 */ -411, -60, 1, 60, -59, 1, 0,
841 /* 138 */ -58, 1, 0,
842 /* 141 */ -104, 486, -414, -64, 1, 64, -63, 1, 483, -420, -62, 1, 62, -61, 1, -14, 486, -411, -60, 1, 60, -59, 1, 476, -417, -58, 1, 58, -57, 1, 0,
843 /* 172 */ -56, 1, 0,
844 /* 175 */ -408, -56, 1, 56, -55, 1, 0,
845 /* 182 */ -54, 1, 0,
846 /* 185 */ 486, -408, -56, 1, 56, -55, 1, 469, -414, -54, 1, 54, -53, 1, 0,
847 /* 200 */ -52, 1, 0,
848 /* 203 */ -405, -52, 1, 52, -51, 1, 0,
849 /* 210 */ -50, 1, 0,
850 /* 213 */ -103, 486, -408, -56, 1, 56, -55, 1, 469, -414, -54, 1, 54, -53, 1, -28, 486, -405, -52, 1, 52, -51, 1, 462, -411, -50, 1, 50, -49, 1, 0,
851 /* 244 */ -48, 1, 0,
852 /* 247 */ -402, -48, 1, 48, -47, 1, 0,
853 /* 254 */ -46, 1, 0,
854 /* 257 */ 486, -402, -48, 1, 48, -47, 1, 455, -408, -46, 1, 46, -45, 1, 0,
855 /* 272 */ -44, 1, 0,
856 /* 275 */ -399, -44, 1, 44, -43, 1, 0,
857 /* 282 */ -42, 1, 0,
858 /* 285 */ -102, 486, -402, -48, 1, 48, -47, 1, 455, -408, -46, 1, 46, -45, 1, -42, 486, -399, -44, 1, 44, -43, 1, 448, -405, -42, 1, 42, -41, 1, 0,
859 /* 316 */ -40, 1, 0,
860 /* 319 */ -396, -40, 1, 40, -39, 1, 0,
861 /* 326 */ -38, 1, 0,
862 /* 329 */ 486, -396, -40, 1, 40, -39, 1, 441, -402, -38, 1, 38, -37, 1, 0,
863 /* 344 */ -36, 1, 0,
864 /* 347 */ -393, -36, 1, 36, -35, 1, 0,
865 /* 354 */ -34, 1, 0,
866 /* 357 */ -101, 486, -396, -40, 1, 40, -39, 1, 441, -402, -38, 1, 38, -37, 1, -56, 486, -393, -36, 1, 36, -35, 1, 434, -399, -34, 1, 34, -33, 1, 0,
867 /* 388 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
868 /* 404 */ 2, 0,
869 /* 406 */ 18, 0,
870 /* 408 */ 560, -8, -8, 24, 0,
871 /* 413 */ -32, -282, 32, 251, -282, 32, 0,
872 /* 420 */ 136, -32, -282, 32, 251, -282, 32, 282, -31, -282, 32, 251, -282, 32, 0,
873 /* 435 */ 440, -32, -282, 32, 251, -282, 32, 282, -31, -282, 32, 251, -282, 32, 0,
874 /* 450 */ -30, -282, 32, 251, -282, 32, 0,
875 /* 457 */ 137, -30, -282, 32, 251, -282, 32, 280, -29, -282, 32, 251, -282, 32, 0,
876 /* 472 */ 441, -30, -282, 32, 251, -282, 32, 280, -29, -282, 32, 251, -282, 32, 0,
877 /* 487 */ -28, -282, 32, 251, -282, 32, 0,
878 /* 494 */ 138, -28, -282, 32, 251, -282, 32, 278, -27, -282, 32, 251, -282, 32, 0,
879 /* 509 */ 442, -28, -282, 32, 251, -282, 32, 278, -27, -282, 32, 251, -282, 32, 0,
880 /* 524 */ -26, -282, 32, 251, -282, 32, 0,
881 /* 531 */ 139, -26, -282, 32, 251, -282, 32, 276, -25, -282, 32, 251, -282, 32, 0,
882 /* 546 */ 443, -26, -282, 32, 251, -282, 32, 276, -25, -282, 32, 251, -282, 32, 0,
883 /* 561 */ -24, -282, 32, 251, -282, 32, 0,
884 /* 568 */ 140, -24, -282, 32, 251, -282, 32, 274, -23, -282, 32, 251, -282, 32, 0,
885 /* 583 */ 444, -24, -282, 32, 251, -282, 32, 274, -23, -282, 32, 251, -282, 32, 0,
886 /* 598 */ -22, -282, 32, 251, -282, 32, 0,
887 /* 605 */ 141, -22, -282, 32, 251, -282, 32, 272, -21, -282, 32, 251, -282, 32, 0,
888 /* 620 */ 445, -22, -282, 32, 251, -282, 32, 272, -21, -282, 32, 251, -282, 32, 0,
889 /* 635 */ -20, -282, 32, 251, -282, 32, 0,
890 /* 642 */ 142, -20, -282, 32, 251, -282, 32, 270, -19, -282, 32, 251, -282, 32, 0,
891 /* 657 */ 446, -20, -282, 32, 251, -282, 32, 270, -19, -282, 32, 251, -282, 32, 0,
892 /* 672 */ -18, -282, 32, 251, -282, 32, 0,
893 /* 679 */ 143, -18, -282, 32, 251, -282, 32, 268, -17, -282, 32, 251, -282, 32, 0,
894 /* 694 */ 447, -18, -282, 32, 251, -282, 32, 268, -17, -282, 32, 251, -282, 32, 0,
895 /* 709 */ -144, 32, 32, -63, 32, 32, 0,
896 /* 716 */ -143, 32, 32, -63, 32, 32, 0,
897 /* 723 */ -142, 32, 32, -63, 32, 32, 0,
898 /* 730 */ -141, 32, 32, -63, 32, 32, 0,
899 /* 737 */ -140, 32, 32, -63, 32, 32, 0,
900 /* 744 */ -139, 32, 32, -63, 32, 32, 0,
901 /* 751 */ -138, 32, 32, -63, 32, 32, 0,
902 /* 758 */ -137, 32, 32, -63, 32, 32, 0,
903 /* 765 */ -136, 32, 32, -63, 32, 32, 0,
904 /* 772 */ -135, 32, 32, -63, 32, 32, 0,
905 /* 779 */ -134, 32, 32, -63, 32, 32, 0,
906 /* 786 */ -133, 32, 32, -63, 32, 32, 0,
907 /* 793 */ -132, 32, 32, -63, 32, 32, 0,
908 /* 800 */ -131, 32, 32, -63, 32, 32, 0,
909 /* 807 */ -130, 32, 32, -63, 32, 32, 0,
910 /* 814 */ -129, 32, 32, -63, 32, 32, 0,
911 /* 821 */ 32, 248, 49, 0,
912 /* 825 */ 32, 248, 50, 0,
913 /* 829 */ 32, 248, 51, 0,
914 /* 833 */ 32, 248, 52, 0,
915 /* 837 */ 32, 248, 53, 0,
916 /* 841 */ 32, 248, 54, 0,
917 /* 845 */ 32, 248, 55, 0,
918 /* 849 */ 32, 248, 56, 0,
919 /* 853 */ 32, 248, 57, 0,
920 /* 857 */ 32, 248, 58, 0,
921 /* 861 */ 32, 248, 59, 0,
922 /* 865 */ 32, 248, 60, 0,
923 /* 869 */ 32, 248, 61, 0,
924 /* 873 */ 32, 248, 62, 0,
925 /* 877 */ 32, 248, 63, 0,
926 /* 881 */ 32, 248, 64, 0,
927 /* 885 */ 32, 248, 65, 0,
928 /* 889 */ 32, 398, -494, 100, 0,
929 /* 894 */ 33, 398, -494, 100, 0,
930 /* 899 */ 33, 399, -494, 100, 0,
931 /* 904 */ 34, 399, -494, 100, 0,
932 /* 909 */ 34, 392, -486, 100, 0,
933 /* 914 */ 35, 392, -486, 100, 0,
934 /* 919 */ 35, 393, -486, 100, 0,
935 /* 924 */ 36, 393, -486, 100, 0,
936 /* 929 */ 36, 401, -494, 101, 0,
937 /* 934 */ 37, 401, -494, 101, 0,
938 /* 939 */ 37, 402, -494, 101, 0,
939 /* 944 */ 38, 402, -494, 101, 0,
940 /* 949 */ 40, 404, -494, 101, 0,
941 /* 954 */ 41, 404, -494, 101, 0,
942 /* 959 */ 41, 405, -494, 101, 0,
943 /* 964 */ 42, 405, -494, 101, 0,
944 /* 969 */ 38, 395, -486, 101, 0,
945 /* 974 */ 39, 395, -486, 101, 0,
946 /* 979 */ 39, 396, -486, 101, 0,
947 /* 984 */ 40, 396, -486, 101, 0,
948 /* 989 */ 42, 398, -486, 101, 0,
949 /* 994 */ 43, 398, -486, 101, 0,
950 /* 999 */ 43, 399, -486, 101, 0,
951 /* 1004 */ 44, 399, -486, 101, 0,
952 /* 1009 */ 44, 407, -494, 102, 0,
953 /* 1014 */ 45, 407, -494, 102, 0,
954 /* 1019 */ 45, 408, -494, 102, 0,
955 /* 1024 */ 46, 408, -494, 102, 0,
956 /* 1029 */ 48, 410, -494, 102, 0,
957 /* 1034 */ 49, 410, -494, 102, 0,
958 /* 1039 */ 49, 411, -494, 102, 0,
959 /* 1044 */ 50, 411, -494, 102, 0,
960 /* 1049 */ 46, 401, -486, 102, 0,
961 /* 1054 */ 47, 401, -486, 102, 0,
962 /* 1059 */ 47, 402, -486, 102, 0,
963 /* 1064 */ 48, 402, -486, 102, 0,
964 /* 1069 */ 50, 404, -486, 102, 0,
965 /* 1074 */ 51, 404, -486, 102, 0,
966 /* 1079 */ 51, 405, -486, 102, 0,
967 /* 1084 */ 52, 405, -486, 102, 0,
968 /* 1089 */ 52, 413, -494, 103, 0,
969 /* 1094 */ 53, 413, -494, 103, 0,
970 /* 1099 */ 53, 414, -494, 103, 0,
971 /* 1104 */ 54, 414, -494, 103, 0,
972 /* 1109 */ 56, 416, -494, 103, 0,
973 /* 1114 */ 57, 416, -494, 103, 0,
974 /* 1119 */ 57, 417, -494, 103, 0,
975 /* 1124 */ 58, 417, -494, 103, 0,
976 /* 1129 */ 54, 407, -486, 103, 0,
977 /* 1134 */ 55, 407, -486, 103, 0,
978 /* 1139 */ 55, 408, -486, 103, 0,
979 /* 1144 */ 56, 408, -486, 103, 0,
980 /* 1149 */ 58, 410, -486, 103, 0,
981 /* 1154 */ 59, 410, -486, 103, 0,
982 /* 1159 */ 59, 411, -486, 103, 0,
983 /* 1164 */ 60, 411, -486, 103, 0,
984 /* 1169 */ 60, 419, -494, 104, 0,
985 /* 1174 */ 61, 419, -494, 104, 0,
986 /* 1179 */ 61, 420, -494, 104, 0,
987 /* 1184 */ 62, 420, -494, 104, 0,
988 /* 1189 */ 62, 413, -486, 104, 0,
989 /* 1194 */ 63, 413, -486, 104, 0,
990 /* 1199 */ 63, 414, -486, 104, 0,
991 /* 1204 */ 64, 414, -486, 104, 0,
992 /* 1209 */ 282, 16, -448, 199, 105, 0,
993 /* 1215 */ 282, 17, -448, 199, 105, 0,
994 /* 1221 */ 282, 17, -447, 198, 106, 0,
995 /* 1227 */ 282, 18, -447, 198, 106, 0,
996 /* 1233 */ 282, 19, -447, 198, 106, 0,
997 /* 1239 */ 282, 19, -446, 197, 107, 0,
998 /* 1245 */ 282, 20, -446, 197, 107, 0,
999 /* 1251 */ 282, 21, -446, 197, 107, 0,
1000 /* 1257 */ 282, 21, -445, 196, 108, 0,
1001 /* 1263 */ 282, 22, -445, 196, 108, 0,
1002 /* 1269 */ 282, 23, -445, 196, 108, 0,
1003 /* 1275 */ 282, 23, -444, 195, 109, 0,
1004 /* 1281 */ 282, 24, -444, 195, 109, 0,
1005 /* 1287 */ 282, 25, -444, 195, 109, 0,
1006 /* 1293 */ 282, 25, -443, 194, 110, 0,
1007 /* 1299 */ 282, 26, -443, 194, 110, 0,
1008 /* 1305 */ 282, 27, -443, 194, 110, 0,
1009 /* 1311 */ 282, 27, -442, 193, 111, 0,
1010 /* 1317 */ 282, 28, -442, 193, 111, 0,
1011 /* 1323 */ 282, 29, -442, 193, 111, 0,
1012 /* 1329 */ 282, 29, -441, 192, 112, 0,
1013 /* 1335 */ 282, 30, -441, 192, 112, 0,
1014 /* 1341 */ 282, 31, -441, 192, 112, 0,
1015 /* 1347 */ 282, 31, -440, 191, 113, 0,
1016 /* 1353 */ 282, 32, -440, 191, 113, 0,
1017 /* 1359 */ -64, 128, 0,
1018 /* 1362 */ -32, 128, 0,
1019 /* 1365 */ -64, 129, 0,
1020 /* 1368 */ -32, 129, 0,
1021 /* 1371 */ -64, 130, 0,
1022 /* 1374 */ -32, 130, 0,
1023 /* 1377 */ -64, 131, 0,
1024 /* 1380 */ -32, 131, 0,
1025 /* 1383 */ -64, 132, 0,
1026 /* 1386 */ -32, 132, 0,
1027 /* 1389 */ -64, 133, 0,
1028 /* 1392 */ -32, 133, 0,
1029 /* 1395 */ -64, 134, 0,
1030 /* 1398 */ -32, 134, 0,
1031 /* 1401 */ -64, 135, 0,
1032 /* 1404 */ -32, 135, 0,
1033 /* 1407 */ -64, 136, 0,
1034 /* 1410 */ -32, 136, 0,
1035 /* 1413 */ -64, 137, 0,
1036 /* 1416 */ -32, 137, 0,
1037 /* 1419 */ -64, 138, 0,
1038 /* 1422 */ -32, 138, 0,
1039 /* 1425 */ -64, 139, 0,
1040 /* 1428 */ -32, 139, 0,
1041 /* 1431 */ -64, 140, 0,
1042 /* 1434 */ -32, 140, 0,
1043 /* 1437 */ -64, 141, 0,
1044 /* 1440 */ -32, 141, 0,
1045 /* 1443 */ -64, 142, 0,
1046 /* 1446 */ -32, 142, 0,
1047 /* 1449 */ -64, 143, 0,
1048 /* 1452 */ -32, 143, 0,
1049 /* 1455 */ -64, 144, 0,
1050 /* 1458 */ -32, 144, 0,
1051 /* 1461 */ 197, 0,
1052 /* 1463 */ 250, 16, -448, 304, 0,
1053 /* 1468 */ 250, 17, -448, 304, 0,
1054 /* 1473 */ 250, 17, -447, 304, 0,
1055 /* 1478 */ 250, 18, -447, 304, 0,
1056 /* 1483 */ 250, 19, -447, 304, 0,
1057 /* 1488 */ 250, 19, -446, 304, 0,
1058 /* 1493 */ 250, 20, -446, 304, 0,
1059 /* 1498 */ 250, 21, -446, 304, 0,
1060 /* 1503 */ 250, 21, -445, 304, 0,
1061 /* 1508 */ 250, 22, -445, 304, 0,
1062 /* 1513 */ 250, 23, -445, 304, 0,
1063 /* 1518 */ 250, 23, -444, 304, 0,
1064 /* 1523 */ 250, 24, -444, 304, 0,
1065 /* 1528 */ 250, 25, -444, 304, 0,
1066 /* 1533 */ 250, 25, -443, 304, 0,
1067 /* 1538 */ 250, 26, -443, 304, 0,
1068 /* 1543 */ 250, 27, -443, 304, 0,
1069 /* 1548 */ 250, 27, -442, 304, 0,
1070 /* 1553 */ 250, 28, -442, 304, 0,
1071 /* 1558 */ 250, 29, -442, 304, 0,
1072 /* 1563 */ 250, 29, -441, 304, 0,
1073 /* 1568 */ 250, 30, -441, 304, 0,
1074 /* 1573 */ 250, 31, -441, 304, 0,
1075 /* 1578 */ 250, 31, -440, 304, 0,
1076 /* 1583 */ 250, 32, -440, 304, 0,
1077 /* 1588 */ 553, 0,
1078};
1079
1080extern const LaneBitmask PPCLaneMaskLists[] = {
1081 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
1082 /* 3 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
1083 /* 6 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
1084 /* 9 */ LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask::getAll(),
1085 /* 12 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000800), LaneBitmask::getAll(),
1086 /* 17 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask::getAll(),
1087 /* 22 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask::getAll(),
1088 /* 31 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask::getAll(),
1089 /* 36 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask::getAll(),
1090 /* 45 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000080000000), LaneBitmask::getAll(),
1091 /* 62 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000100000000), LaneBitmask::getAll(),
1092 /* 65 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
1093};
1094
1095extern const uint16_t PPCSubRegIdxLists[] = {
1096 /* 0 */ 1, 0,
1097 /* 2 */ 1, 2, 0,
1098 /* 5 */ 3, 4, 0,
1099 /* 8 */ 7, 8, 0,
1100 /* 11 */ 12, 13, 0,
1101 /* 14 */ 17, 16, 11, 20, 0,
1102 /* 19 */ 21, 3, 4, 22, 25, 26, 0,
1103 /* 26 */ 18, 21, 3, 4, 22, 25, 26, 19, 29, 27, 28, 30, 31, 32, 0,
1104 /* 41 */ 9, 7, 8, 10, 33, 34, 0,
1105 /* 48 */ 24, 9, 7, 8, 10, 33, 34, 23, 37, 35, 36, 38, 39, 40, 0,
1106 /* 63 */ 5, 24, 9, 7, 8, 10, 33, 34, 23, 37, 35, 36, 38, 39, 40, 6, 46, 43, 41, 42, 44, 47, 48, 45, 51, 49, 50, 52, 53, 54, 0,
1107 /* 94 */ 14, 1, 15, 55, 0,
1108};
1109
1110
1111#ifdef __GNUC__
1112#pragma GCC diagnostic push
1113#pragma GCC diagnostic ignored "-Woverlength-strings"
1114#endif
1115extern const char PPCRegStrings[] = {
1116 /* 0 */ "VF10\0"
1117 /* 5 */ "VFH10\0"
1118 /* 11 */ "VSL10\0"
1119 /* 17 */ "R10\0"
1120 /* 21 */ "S10\0"
1121 /* 25 */ "V10\0"
1122 /* 29 */ "DMRROW10\0"
1123 /* 38 */ "X10\0"
1124 /* 42 */ "G8p10\0"
1125 /* 48 */ "VSRp10\0"
1126 /* 55 */ "DMRROWp10\0"
1127 /* 65 */ "Fpair10\0"
1128 /* 73 */ "VF20\0"
1129 /* 78 */ "VFH20\0"
1130 /* 84 */ "VSL20\0"
1131 /* 90 */ "R20\0"
1132 /* 94 */ "S20\0"
1133 /* 98 */ "V20\0"
1134 /* 102 */ "DMRROW20\0"
1135 /* 111 */ "X20\0"
1136 /* 115 */ "VSRp20\0"
1137 /* 122 */ "DMRROWp20\0"
1138 /* 132 */ "Fpair20\0"
1139 /* 140 */ "VF30\0"
1140 /* 145 */ "VFH30\0"
1141 /* 151 */ "VSL30\0"
1142 /* 157 */ "R30\0"
1143 /* 161 */ "S30\0"
1144 /* 165 */ "V30\0"
1145 /* 169 */ "DMRROW30\0"
1146 /* 178 */ "X30\0"
1147 /* 182 */ "VSRp30\0"
1148 /* 189 */ "DMRROWp30\0"
1149 /* 199 */ "Fpair30\0"
1150 /* 207 */ "DMRROW40\0"
1151 /* 216 */ "VSX40\0"
1152 /* 222 */ "DMRROW50\0"
1153 /* 231 */ "VSX50\0"
1154 /* 237 */ "DMRROW60\0"
1155 /* 246 */ "VSX60\0"
1156 /* 252 */ "UACC0\0"
1157 /* 258 */ "WACC0\0"
1158 /* 264 */ "VF0\0"
1159 /* 268 */ "VFH0\0"
1160 /* 273 */ "WACC_HI0\0"
1161 /* 282 */ "VSL0\0"
1162 /* 287 */ "CR0\0"
1163 /* 291 */ "DMR0\0"
1164 /* 296 */ "S0\0"
1165 /* 299 */ "V0\0"
1166 /* 302 */ "DMRROW0\0"
1167 /* 310 */ "X0\0"
1168 /* 313 */ "G8p0\0"
1169 /* 318 */ "DMRp0\0"
1170 /* 324 */ "VSRp0\0"
1171 /* 330 */ "DMRROWp0\0"
1172 /* 339 */ "Fpair0\0"
1173 /* 346 */ "VF11\0"
1174 /* 351 */ "VFH11\0"
1175 /* 357 */ "VSL11\0"
1176 /* 363 */ "R11\0"
1177 /* 367 */ "S11\0"
1178 /* 371 */ "V11\0"
1179 /* 375 */ "DMRROW11\0"
1180 /* 384 */ "X11\0"
1181 /* 388 */ "G8p11\0"
1182 /* 394 */ "VSRp11\0"
1183 /* 401 */ "DMRROWp11\0"
1184 /* 411 */ "VF21\0"
1185 /* 416 */ "VFH21\0"
1186 /* 422 */ "VSL21\0"
1187 /* 428 */ "R21\0"
1188 /* 432 */ "S21\0"
1189 /* 436 */ "V21\0"
1190 /* 440 */ "DMRROW21\0"
1191 /* 449 */ "X21\0"
1192 /* 453 */ "VSRp21\0"
1193 /* 460 */ "DMRROWp21\0"
1194 /* 470 */ "VF31\0"
1195 /* 475 */ "VFH31\0"
1196 /* 481 */ "VSL31\0"
1197 /* 487 */ "R31\0"
1198 /* 491 */ "S31\0"
1199 /* 495 */ "V31\0"
1200 /* 499 */ "DMRROW31\0"
1201 /* 508 */ "X31\0"
1202 /* 512 */ "VSRp31\0"
1203 /* 519 */ "DMRROWp31\0"
1204 /* 529 */ "DMRROW41\0"
1205 /* 538 */ "VSX41\0"
1206 /* 544 */ "DMRROW51\0"
1207 /* 553 */ "VSX51\0"
1208 /* 559 */ "DMRROW61\0"
1209 /* 568 */ "VSX61\0"
1210 /* 574 */ "UACC1\0"
1211 /* 580 */ "WACC1\0"
1212 /* 586 */ "VF1\0"
1213 /* 590 */ "VFH1\0"
1214 /* 595 */ "WACC_HI1\0"
1215 /* 604 */ "VSL1\0"
1216 /* 609 */ "CR1\0"
1217 /* 613 */ "DMR1\0"
1218 /* 618 */ "S1\0"
1219 /* 621 */ "V1\0"
1220 /* 624 */ "DMRROW1\0"
1221 /* 632 */ "X1\0"
1222 /* 635 */ "G8p1\0"
1223 /* 640 */ "DMRp1\0"
1224 /* 646 */ "VSRp1\0"
1225 /* 652 */ "DMRROWp1\0"
1226 /* 661 */ "VF12\0"
1227 /* 666 */ "VFH12\0"
1228 /* 672 */ "VSL12\0"
1229 /* 678 */ "R12\0"
1230 /* 682 */ "S12\0"
1231 /* 686 */ "V12\0"
1232 /* 690 */ "DMRROW12\0"
1233 /* 699 */ "X12\0"
1234 /* 703 */ "G8p12\0"
1235 /* 709 */ "VSRp12\0"
1236 /* 716 */ "DMRROWp12\0"
1237 /* 726 */ "Fpair12\0"
1238 /* 734 */ "VF22\0"
1239 /* 739 */ "VFH22\0"
1240 /* 745 */ "VSL22\0"
1241 /* 751 */ "R22\0"
1242 /* 755 */ "S22\0"
1243 /* 759 */ "V22\0"
1244 /* 763 */ "DMRROW22\0"
1245 /* 772 */ "X22\0"
1246 /* 776 */ "VSRp22\0"
1247 /* 783 */ "DMRROWp22\0"
1248 /* 793 */ "Fpair22\0"
1249 /* 801 */ "DMRROW32\0"
1250 /* 810 */ "VSX32\0"
1251 /* 816 */ "DMRROW42\0"
1252 /* 825 */ "VSX42\0"
1253 /* 831 */ "DMRROW52\0"
1254 /* 840 */ "VSX52\0"
1255 /* 846 */ "DMRROW62\0"
1256 /* 855 */ "VSX62\0"
1257 /* 861 */ "UACC2\0"
1258 /* 867 */ "WACC2\0"
1259 /* 873 */ "VF2\0"
1260 /* 877 */ "VFH2\0"
1261 /* 882 */ "WACC_HI2\0"
1262 /* 891 */ "VSL2\0"
1263 /* 896 */ "CR2\0"
1264 /* 900 */ "DMR2\0"
1265 /* 905 */ "S2\0"
1266 /* 908 */ "V2\0"
1267 /* 911 */ "DMRROW2\0"
1268 /* 919 */ "X2\0"
1269 /* 922 */ "G8p2\0"
1270 /* 927 */ "DMRp2\0"
1271 /* 933 */ "VSRp2\0"
1272 /* 939 */ "DMRROWp2\0"
1273 /* 948 */ "Fpair2\0"
1274 /* 955 */ "VF13\0"
1275 /* 960 */ "VFH13\0"
1276 /* 966 */ "VSL13\0"
1277 /* 972 */ "R13\0"
1278 /* 976 */ "S13\0"
1279 /* 980 */ "V13\0"
1280 /* 984 */ "DMRROW13\0"
1281 /* 993 */ "X13\0"
1282 /* 997 */ "G8p13\0"
1283 /* 1003 */ "VSRp13\0"
1284 /* 1010 */ "DMRROWp13\0"
1285 /* 1020 */ "VF23\0"
1286 /* 1025 */ "VFH23\0"
1287 /* 1031 */ "VSL23\0"
1288 /* 1037 */ "R23\0"
1289 /* 1041 */ "S23\0"
1290 /* 1045 */ "V23\0"
1291 /* 1049 */ "DMRROW23\0"
1292 /* 1058 */ "X23\0"
1293 /* 1062 */ "VSRp23\0"
1294 /* 1069 */ "DMRROWp23\0"
1295 /* 1079 */ "DMRROW33\0"
1296 /* 1088 */ "VSX33\0"
1297 /* 1094 */ "DMRROW43\0"
1298 /* 1103 */ "VSX43\0"
1299 /* 1109 */ "DMRROW53\0"
1300 /* 1118 */ "VSX53\0"
1301 /* 1124 */ "DMRROW63\0"
1302 /* 1133 */ "VSX63\0"
1303 /* 1139 */ "UACC3\0"
1304 /* 1145 */ "WACC3\0"
1305 /* 1151 */ "VF3\0"
1306 /* 1155 */ "VFH3\0"
1307 /* 1160 */ "WACC_HI3\0"
1308 /* 1169 */ "VSL3\0"
1309 /* 1174 */ "CR3\0"
1310 /* 1178 */ "DMR3\0"
1311 /* 1183 */ "S3\0"
1312 /* 1186 */ "V3\0"
1313 /* 1189 */ "DMRROW3\0"
1314 /* 1197 */ "X3\0"
1315 /* 1200 */ "G8p3\0"
1316 /* 1205 */ "DMRp3\0"
1317 /* 1211 */ "VSRp3\0"
1318 /* 1217 */ "DMRROWp3\0"
1319 /* 1226 */ "VF14\0"
1320 /* 1231 */ "VFH14\0"
1321 /* 1237 */ "VSL14\0"
1322 /* 1243 */ "R14\0"
1323 /* 1247 */ "S14\0"
1324 /* 1251 */ "V14\0"
1325 /* 1255 */ "DMRROW14\0"
1326 /* 1264 */ "X14\0"
1327 /* 1268 */ "G8p14\0"
1328 /* 1274 */ "VSRp14\0"
1329 /* 1281 */ "DMRROWp14\0"
1330 /* 1291 */ "Fpair14\0"
1331 /* 1299 */ "VF24\0"
1332 /* 1304 */ "VFH24\0"
1333 /* 1310 */ "VSL24\0"
1334 /* 1316 */ "R24\0"
1335 /* 1320 */ "S24\0"
1336 /* 1324 */ "V24\0"
1337 /* 1328 */ "DMRROW24\0"
1338 /* 1337 */ "X24\0"
1339 /* 1341 */ "VSRp24\0"
1340 /* 1348 */ "DMRROWp24\0"
1341 /* 1358 */ "Fpair24\0"
1342 /* 1366 */ "DMRROW34\0"
1343 /* 1375 */ "VSX34\0"
1344 /* 1381 */ "DMRROW44\0"
1345 /* 1390 */ "VSX44\0"
1346 /* 1396 */ "DMRROW54\0"
1347 /* 1405 */ "VSX54\0"
1348 /* 1411 */ "UACC4\0"
1349 /* 1417 */ "WACC4\0"
1350 /* 1423 */ "VF4\0"
1351 /* 1427 */ "VFH4\0"
1352 /* 1432 */ "WACC_HI4\0"
1353 /* 1441 */ "VSL4\0"
1354 /* 1446 */ "CR4\0"
1355 /* 1450 */ "DMR4\0"
1356 /* 1455 */ "S4\0"
1357 /* 1458 */ "V4\0"
1358 /* 1461 */ "DMRROW4\0"
1359 /* 1469 */ "X4\0"
1360 /* 1472 */ "G8p4\0"
1361 /* 1477 */ "VSRp4\0"
1362 /* 1483 */ "DMRROWp4\0"
1363 /* 1492 */ "Fpair4\0"
1364 /* 1499 */ "VF15\0"
1365 /* 1504 */ "VFH15\0"
1366 /* 1510 */ "VSL15\0"
1367 /* 1516 */ "R15\0"
1368 /* 1520 */ "S15\0"
1369 /* 1524 */ "V15\0"
1370 /* 1528 */ "DMRROW15\0"
1371 /* 1537 */ "X15\0"
1372 /* 1541 */ "G8p15\0"
1373 /* 1547 */ "VSRp15\0"
1374 /* 1554 */ "DMRROWp15\0"
1375 /* 1564 */ "VF25\0"
1376 /* 1569 */ "VFH25\0"
1377 /* 1575 */ "VSL25\0"
1378 /* 1581 */ "R25\0"
1379 /* 1585 */ "S25\0"
1380 /* 1589 */ "V25\0"
1381 /* 1593 */ "DMRROW25\0"
1382 /* 1602 */ "X25\0"
1383 /* 1606 */ "VSRp25\0"
1384 /* 1613 */ "DMRROWp25\0"
1385 /* 1623 */ "DMRROW35\0"
1386 /* 1632 */ "VSX35\0"
1387 /* 1638 */ "DMRROW45\0"
1388 /* 1647 */ "VSX45\0"
1389 /* 1653 */ "DMRROW55\0"
1390 /* 1662 */ "VSX55\0"
1391 /* 1668 */ "UACC5\0"
1392 /* 1674 */ "WACC5\0"
1393 /* 1680 */ "VF5\0"
1394 /* 1684 */ "VFH5\0"
1395 /* 1689 */ "WACC_HI5\0"
1396 /* 1698 */ "VSL5\0"
1397 /* 1703 */ "CR5\0"
1398 /* 1707 */ "DMR5\0"
1399 /* 1712 */ "S5\0"
1400 /* 1715 */ "V5\0"
1401 /* 1718 */ "DMRROW5\0"
1402 /* 1726 */ "X5\0"
1403 /* 1729 */ "G8p5\0"
1404 /* 1734 */ "VSRp5\0"
1405 /* 1740 */ "DMRROWp5\0"
1406 /* 1749 */ "VF16\0"
1407 /* 1754 */ "VFH16\0"
1408 /* 1760 */ "VSL16\0"
1409 /* 1766 */ "R16\0"
1410 /* 1770 */ "S16\0"
1411 /* 1774 */ "V16\0"
1412 /* 1778 */ "DMRROW16\0"
1413 /* 1787 */ "X16\0"
1414 /* 1791 */ "VSRp16\0"
1415 /* 1798 */ "DMRROWp16\0"
1416 /* 1808 */ "Fpair16\0"
1417 /* 1816 */ "VF26\0"
1418 /* 1821 */ "VFH26\0"
1419 /* 1827 */ "VSL26\0"
1420 /* 1833 */ "R26\0"
1421 /* 1837 */ "S26\0"
1422 /* 1841 */ "V26\0"
1423 /* 1845 */ "DMRROW26\0"
1424 /* 1854 */ "X26\0"
1425 /* 1858 */ "VSRp26\0"
1426 /* 1865 */ "DMRROWp26\0"
1427 /* 1875 */ "Fpair26\0"
1428 /* 1883 */ "DMRROW36\0"
1429 /* 1892 */ "VSX36\0"
1430 /* 1898 */ "DMRROW46\0"
1431 /* 1907 */ "VSX46\0"
1432 /* 1913 */ "DMRROW56\0"
1433 /* 1922 */ "VSX56\0"
1434 /* 1928 */ "UACC6\0"
1435 /* 1934 */ "WACC6\0"
1436 /* 1940 */ "VF6\0"
1437 /* 1944 */ "VFH6\0"
1438 /* 1949 */ "WACC_HI6\0"
1439 /* 1958 */ "VSL6\0"
1440 /* 1963 */ "CR6\0"
1441 /* 1967 */ "DMR6\0"
1442 /* 1972 */ "S6\0"
1443 /* 1975 */ "V6\0"
1444 /* 1978 */ "DMRROW6\0"
1445 /* 1986 */ "X6\0"
1446 /* 1989 */ "G8p6\0"
1447 /* 1994 */ "VSRp6\0"
1448 /* 2000 */ "DMRROWp6\0"
1449 /* 2009 */ "Fpair6\0"
1450 /* 2016 */ "VF17\0"
1451 /* 2021 */ "VFH17\0"
1452 /* 2027 */ "VSL17\0"
1453 /* 2033 */ "R17\0"
1454 /* 2037 */ "S17\0"
1455 /* 2041 */ "V17\0"
1456 /* 2045 */ "DMRROW17\0"
1457 /* 2054 */ "X17\0"
1458 /* 2058 */ "VSRp17\0"
1459 /* 2065 */ "DMRROWp17\0"
1460 /* 2075 */ "VF27\0"
1461 /* 2080 */ "VFH27\0"
1462 /* 2086 */ "VSL27\0"
1463 /* 2092 */ "R27\0"
1464 /* 2096 */ "S27\0"
1465 /* 2100 */ "V27\0"
1466 /* 2104 */ "DMRROW27\0"
1467 /* 2113 */ "X27\0"
1468 /* 2117 */ "VSRp27\0"
1469 /* 2124 */ "DMRROWp27\0"
1470 /* 2134 */ "DMRROW37\0"
1471 /* 2143 */ "VSX37\0"
1472 /* 2149 */ "DMRROW47\0"
1473 /* 2158 */ "VSX47\0"
1474 /* 2164 */ "DMRROW57\0"
1475 /* 2173 */ "VSX57\0"
1476 /* 2179 */ "UACC7\0"
1477 /* 2185 */ "WACC7\0"
1478 /* 2191 */ "VF7\0"
1479 /* 2195 */ "VFH7\0"
1480 /* 2200 */ "WACC_HI7\0"
1481 /* 2209 */ "VSL7\0"
1482 /* 2214 */ "CR7\0"
1483 /* 2218 */ "DMR7\0"
1484 /* 2223 */ "S7\0"
1485 /* 2226 */ "V7\0"
1486 /* 2229 */ "DMRROW7\0"
1487 /* 2237 */ "X7\0"
1488 /* 2240 */ "G8p7\0"
1489 /* 2245 */ "VSRp7\0"
1490 /* 2251 */ "DMRROWp7\0"
1491 /* 2260 */ "VF18\0"
1492 /* 2265 */ "VFH18\0"
1493 /* 2271 */ "VSL18\0"
1494 /* 2277 */ "R18\0"
1495 /* 2281 */ "S18\0"
1496 /* 2285 */ "V18\0"
1497 /* 2289 */ "DMRROW18\0"
1498 /* 2298 */ "X18\0"
1499 /* 2302 */ "VSRp18\0"
1500 /* 2309 */ "DMRROWp18\0"
1501 /* 2319 */ "Fpair18\0"
1502 /* 2327 */ "VF28\0"
1503 /* 2332 */ "VFH28\0"
1504 /* 2338 */ "VSL28\0"
1505 /* 2344 */ "R28\0"
1506 /* 2348 */ "S28\0"
1507 /* 2352 */ "V28\0"
1508 /* 2356 */ "DMRROW28\0"
1509 /* 2365 */ "X28\0"
1510 /* 2369 */ "VSRp28\0"
1511 /* 2376 */ "DMRROWp28\0"
1512 /* 2386 */ "Fpair28\0"
1513 /* 2394 */ "DMRROW38\0"
1514 /* 2403 */ "VSX38\0"
1515 /* 2409 */ "DMRROW48\0"
1516 /* 2418 */ "VSX48\0"
1517 /* 2424 */ "DMRROW58\0"
1518 /* 2433 */ "VSX58\0"
1519 /* 2439 */ "VF8\0"
1520 /* 2443 */ "VFH8\0"
1521 /* 2448 */ "VSL8\0"
1522 /* 2453 */ "ZERO8\0"
1523 /* 2459 */ "BP8\0"
1524 /* 2463 */ "FP8\0"
1525 /* 2467 */ "LR8\0"
1526 /* 2471 */ "CTR8\0"
1527 /* 2476 */ "S8\0"
1528 /* 2479 */ "V8\0"
1529 /* 2482 */ "DMRROW8\0"
1530 /* 2490 */ "X8\0"
1531 /* 2493 */ "G8p8\0"
1532 /* 2498 */ "VSRp8\0"
1533 /* 2504 */ "DMRROWp8\0"
1534 /* 2513 */ "Fpair8\0"
1535 /* 2520 */ "VF19\0"
1536 /* 2525 */ "VFH19\0"
1537 /* 2531 */ "VSL19\0"
1538 /* 2537 */ "R19\0"
1539 /* 2541 */ "S19\0"
1540 /* 2545 */ "V19\0"
1541 /* 2549 */ "DMRROW19\0"
1542 /* 2558 */ "X19\0"
1543 /* 2562 */ "VSRp19\0"
1544 /* 2569 */ "DMRROWp19\0"
1545 /* 2579 */ "VF29\0"
1546 /* 2584 */ "VFH29\0"
1547 /* 2590 */ "VSL29\0"
1548 /* 2596 */ "R29\0"
1549 /* 2600 */ "S29\0"
1550 /* 2604 */ "V29\0"
1551 /* 2608 */ "DMRROW29\0"
1552 /* 2617 */ "X29\0"
1553 /* 2621 */ "VSRp29\0"
1554 /* 2628 */ "DMRROWp29\0"
1555 /* 2638 */ "DMRROW39\0"
1556 /* 2647 */ "VSX39\0"
1557 /* 2653 */ "DMRROW49\0"
1558 /* 2662 */ "VSX49\0"
1559 /* 2668 */ "DMRROW59\0"
1560 /* 2677 */ "VSX59\0"
1561 /* 2683 */ "VF9\0"
1562 /* 2687 */ "VFH9\0"
1563 /* 2692 */ "VSL9\0"
1564 /* 2697 */ "R9\0"
1565 /* 2700 */ "S9\0"
1566 /* 2703 */ "V9\0"
1567 /* 2706 */ "DMRROW9\0"
1568 /* 2714 */ "X9\0"
1569 /* 2717 */ "G8p9\0"
1570 /* 2722 */ "VSRp9\0"
1571 /* 2728 */ "DMRROWp9\0"
1572 /* 2737 */ "VRSAVE\0"
1573 /* 2744 */ "RM\0"
1574 /* 2747 */ "CR0UN\0"
1575 /* 2753 */ "CR1UN\0"
1576 /* 2759 */ "CR2UN\0"
1577 /* 2765 */ "CR3UN\0"
1578 /* 2771 */ "CR4UN\0"
1579 /* 2777 */ "CR5UN\0"
1580 /* 2783 */ "CR6UN\0"
1581 /* 2789 */ "CR7UN\0"
1582 /* 2795 */ "ZERO\0"
1583 /* 2800 */ "BP\0"
1584 /* 2803 */ "FP\0"
1585 /* 2806 */ "CR0EQ\0"
1586 /* 2812 */ "CR1EQ\0"
1587 /* 2818 */ "CR2EQ\0"
1588 /* 2824 */ "CR3EQ\0"
1589 /* 2830 */ "CR4EQ\0"
1590 /* 2836 */ "CR5EQ\0"
1591 /* 2842 */ "CR6EQ\0"
1592 /* 2848 */ "CR7EQ\0"
1593 /* 2854 */ "SPEFSCR\0"
1594 /* 2862 */ "XER\0"
1595 /* 2866 */ "LR\0"
1596 /* 2869 */ "CTR\0"
1597 /* 2873 */ "CR0GT\0"
1598 /* 2879 */ "CR1GT\0"
1599 /* 2885 */ "CR2GT\0"
1600 /* 2891 */ "CR3GT\0"
1601 /* 2897 */ "CR4GT\0"
1602 /* 2903 */ "CR5GT\0"
1603 /* 2909 */ "CR6GT\0"
1604 /* 2915 */ "CR7GT\0"
1605 /* 2921 */ "CR0LT\0"
1606 /* 2927 */ "CR1LT\0"
1607 /* 2933 */ "CR2LT\0"
1608 /* 2939 */ "CR3LT\0"
1609 /* 2945 */ "CR4LT\0"
1610 /* 2951 */ "CR5LT\0"
1611 /* 2957 */ "CR6LT\0"
1612 /* 2963 */ "CR7LT\0"
1613 /* 2969 */ "CARRY\0"
1614};
1615#ifdef __GNUC__
1616#pragma GCC diagnostic pop
1617#endif
1618
1619extern const MCRegisterDesc PPCRegDesc[] = { // Descriptors
1620 { 4, 0, 0, 0, 0, 0, 0 },
1621 { 2800, 1, 406, 1, 4096, 65, 0 },
1622 { 2969, 1, 1, 1, 4097, 65, 0 },
1623 { 2869, 1, 1, 1, 4098, 65, 0 },
1624 { 2803, 1, 1461, 1, 4099, 65, 0 },
1625 { 2866, 1, 1, 1, 4100, 65, 0 },
1626 { 2744, 1, 1, 1, 4101, 65, 0 },
1627 { 2854, 1, 1, 1, 4102, 65, 0 },
1628 { 2737, 1, 1, 1, 4103, 65, 0 },
1629 { 2862, 1, 1, 1, 4097, 65, 0 },
1630 { 2795, 1, 1588, 1, 4104, 65, 1 },
1631 { 253, 435, 1, 26, 1622025, 22, 0 },
1632 { 575, 472, 1, 26, 1622033, 22, 0 },
1633 { 862, 509, 1, 26, 1622041, 22, 0 },
1634 { 1140, 546, 1, 26, 1622049, 22, 0 },
1635 { 1412, 583, 1, 26, 1622057, 22, 0 },
1636 { 1669, 620, 1, 26, 1622065, 22, 0 },
1637 { 1929, 657, 1, 26, 1622073, 22, 0 },
1638 { 2180, 694, 1, 26, 1622081, 22, 0 },
1639 { 2459, 95, 1, 0, 4096, 1, 0 },
1640 { 287, 408, 1, 14, 1638473, 12, 0 },
1641 { 609, 408, 1, 14, 1638477, 12, 0 },
1642 { 896, 408, 1, 14, 1638481, 12, 0 },
1643 { 1174, 408, 1, 14, 1638485, 12, 0 },
1644 { 1446, 408, 1, 14, 1638489, 12, 0 },
1645 { 1703, 408, 1, 14, 1638493, 12, 0 },
1646 { 1963, 408, 1, 14, 1638497, 12, 0 },
1647 { 2214, 408, 1, 14, 1638501, 12, 0 },
1648 { 2471, 1, 1, 1, 4098, 65, 0 },
1649 { 291, 113, 1172, 48, 1622121, 36, 0 },
1650 { 613, 157, 1092, 48, 1622129, 36, 0 },
1651 { 900, 185, 1092, 48, 1622137, 36, 0 },
1652 { 1178, 229, 1012, 48, 1622145, 36, 0 },
1653 { 1450, 257, 1012, 48, 1622153, 36, 0 },
1654 { 1707, 301, 932, 48, 1622161, 36, 0 },
1655 { 1967, 329, 932, 48, 1622169, 36, 0 },
1656 { 2218, 373, 892, 48, 1622177, 36, 0 },
1657 { 302, 1, 1204, 1, 4201, 65, 0 },
1658 { 624, 1, 1199, 1, 4202, 65, 0 },
1659 { 911, 1, 1194, 1, 4203, 65, 0 },
1660 { 1189, 1, 1189, 1, 4204, 65, 0 },
1661 { 1461, 1, 1184, 1, 4205, 65, 0 },
1662 { 1718, 1, 1179, 1, 4206, 65, 0 },
1663 { 1978, 1, 1174, 1, 4207, 65, 0 },
1664 { 2229, 1, 1169, 1, 4208, 65, 0 },
1665 { 2482, 1, 1164, 1, 4209, 65, 0 },
1666 { 2706, 1, 1159, 1, 4210, 65, 0 },
1667 { 29, 1, 1154, 1, 4211, 65, 0 },
1668 { 375, 1, 1149, 1, 4212, 65, 0 },
1669 { 690, 1, 1124, 1, 4213, 65, 0 },
1670 { 984, 1, 1119, 1, 4214, 65, 0 },
1671 { 1255, 1, 1114, 1, 4215, 65, 0 },
1672 { 1528, 1, 1109, 1, 4216, 65, 0 },
1673 { 1778, 1, 1144, 1, 4217, 65, 0 },
1674 { 2045, 1, 1139, 1, 4218, 65, 0 },
1675 { 2289, 1, 1134, 1, 4219, 65, 0 },
1676 { 2549, 1, 1129, 1, 4220, 65, 0 },
1677 { 102, 1, 1104, 1, 4221, 65, 0 },
1678 { 440, 1, 1099, 1, 4222, 65, 0 },
1679 { 763, 1, 1094, 1, 4223, 65, 0 },
1680 { 1049, 1, 1089, 1, 4224, 65, 0 },
1681 { 1328, 1, 1084, 1, 4225, 65, 0 },
1682 { 1593, 1, 1079, 1, 4226, 65, 0 },
1683 { 1845, 1, 1074, 1, 4227, 65, 0 },
1684 { 2104, 1, 1069, 1, 4228, 65, 0 },
1685 { 2356, 1, 1044, 1, 4229, 65, 0 },
1686 { 2608, 1, 1039, 1, 4230, 65, 0 },
1687 { 169, 1, 1034, 1, 4231, 65, 0 },
1688 { 499, 1, 1029, 1, 4232, 65, 0 },
1689 { 801, 1, 1064, 1, 4233, 65, 0 },
1690 { 1079, 1, 1059, 1, 4234, 65, 0 },
1691 { 1366, 1, 1054, 1, 4235, 65, 0 },
1692 { 1623, 1, 1049, 1, 4236, 65, 0 },
1693 { 1883, 1, 1024, 1, 4237, 65, 0 },
1694 { 2134, 1, 1019, 1, 4238, 65, 0 },
1695 { 2394, 1, 1014, 1, 4239, 65, 0 },
1696 { 2638, 1, 1009, 1, 4240, 65, 0 },
1697 { 207, 1, 1004, 1, 4241, 65, 0 },
1698 { 529, 1, 999, 1, 4242, 65, 0 },
1699 { 816, 1, 994, 1, 4243, 65, 0 },
1700 { 1094, 1, 989, 1, 4244, 65, 0 },
1701 { 1381, 1, 964, 1, 4245, 65, 0 },
1702 { 1638, 1, 959, 1, 4246, 65, 0 },
1703 { 1898, 1, 954, 1, 4247, 65, 0 },
1704 { 2149, 1, 949, 1, 4248, 65, 0 },
1705 { 2409, 1, 984, 1, 4249, 65, 0 },
1706 { 2653, 1, 979, 1, 4250, 65, 0 },
1707 { 222, 1, 974, 1, 4251, 65, 0 },
1708 { 544, 1, 969, 1, 4252, 65, 0 },
1709 { 831, 1, 944, 1, 4253, 65, 0 },
1710 { 1109, 1, 939, 1, 4254, 65, 0 },
1711 { 1396, 1, 934, 1, 4255, 65, 0 },
1712 { 1653, 1, 929, 1, 4256, 65, 0 },
1713 { 1913, 1, 924, 1, 4257, 65, 0 },
1714 { 2164, 1, 919, 1, 4258, 65, 0 },
1715 { 2424, 1, 914, 1, 4259, 65, 0 },
1716 { 2668, 1, 909, 1, 4260, 65, 0 },
1717 { 237, 1, 904, 1, 4261, 65, 0 },
1718 { 559, 1, 899, 1, 4262, 65, 0 },
1719 { 846, 1, 894, 1, 4263, 65, 0 },
1720 { 1124, 1, 889, 1, 4264, 65, 0 },
1721 { 330, 100, 1200, 8, 401513, 6, 0 },
1722 { 652, 107, 1190, 8, 401515, 6, 0 },
1723 { 939, 110, 1180, 8, 401517, 6, 0 },
1724 { 1217, 125, 1170, 8, 401519, 6, 0 },
1725 { 1483, 128, 1160, 8, 401521, 6, 0 },
1726 { 1740, 135, 1150, 8, 401523, 6, 0 },
1727 { 2000, 138, 1120, 8, 401525, 6, 0 },
1728 { 2251, 169, 1110, 8, 401527, 6, 0 },
1729 { 2504, 172, 1140, 8, 401529, 6, 0 },
1730 { 2728, 179, 1130, 8, 401531, 6, 0 },
1731 { 55, 182, 1100, 8, 401533, 6, 0 },
1732 { 401, 197, 1090, 8, 401535, 6, 0 },
1733 { 716, 200, 1080, 8, 401537, 6, 0 },
1734 { 1010, 207, 1070, 8, 401539, 6, 0 },
1735 { 1281, 210, 1040, 8, 401541, 6, 0 },
1736 { 1554, 241, 1030, 8, 401543, 6, 0 },
1737 { 1798, 244, 1060, 8, 401545, 6, 0 },
1738 { 2065, 251, 1050, 8, 401547, 6, 0 },
1739 { 2309, 254, 1020, 8, 401549, 6, 0 },
1740 { 2569, 269, 1010, 8, 401551, 6, 0 },
1741 { 122, 272, 1000, 8, 401553, 6, 0 },
1742 { 460, 279, 990, 8, 401555, 6, 0 },
1743 { 783, 282, 960, 8, 401557, 6, 0 },
1744 { 1069, 313, 950, 8, 401559, 6, 0 },
1745 { 1348, 316, 980, 8, 401561, 6, 0 },
1746 { 1613, 323, 970, 8, 401563, 6, 0 },
1747 { 1865, 326, 940, 8, 401565, 6, 0 },
1748 { 2124, 341, 930, 8, 401567, 6, 0 },
1749 { 2376, 344, 920, 8, 401569, 6, 0 },
1750 { 2628, 351, 910, 8, 401571, 6, 0 },
1751 { 189, 354, 900, 8, 401573, 6, 0 },
1752 { 519, 385, 890, 8, 401575, 6, 0 },
1753 { 318, 141, 1, 63, 1589353, 45, 0 },
1754 { 640, 213, 1, 63, 1589369, 45, 0 },
1755 { 927, 285, 1, 63, 1589385, 45, 0 },
1756 { 1205, 357, 1, 63, 1589401, 45, 0 },
1757 { 265, 1, 1353, 1, 4105, 65, 0 },
1758 { 587, 1, 1347, 1, 4107, 65, 0 },
1759 { 874, 1, 1341, 1, 4109, 65, 0 },
1760 { 1152, 1, 1335, 1, 4111, 65, 0 },
1761 { 1424, 1, 1335, 1, 4113, 65, 0 },
1762 { 1681, 1, 1329, 1, 4115, 65, 0 },
1763 { 1941, 1, 1323, 1, 4117, 65, 0 },
1764 { 2192, 1, 1317, 1, 4119, 65, 0 },
1765 { 2440, 1, 1317, 1, 4121, 65, 0 },
1766 { 2684, 1, 1311, 1, 4123, 65, 0 },
1767 { 1, 1, 1305, 1, 4125, 65, 0 },
1768 { 347, 1, 1299, 1, 4127, 65, 0 },
1769 { 662, 1, 1299, 1, 4129, 65, 0 },
1770 { 956, 1, 1293, 1, 4131, 65, 0 },
1771 { 1227, 1, 1287, 1, 4133, 65, 0 },
1772 { 1500, 1, 1281, 1, 4135, 65, 0 },
1773 { 1750, 1, 1281, 1, 4137, 65, 0 },
1774 { 2017, 1, 1275, 1, 4139, 65, 0 },
1775 { 2261, 1, 1269, 1, 4141, 65, 0 },
1776 { 2521, 1, 1263, 1, 4143, 65, 0 },
1777 { 74, 1, 1263, 1, 4145, 65, 0 },
1778 { 412, 1, 1257, 1, 4147, 65, 0 },
1779 { 735, 1, 1251, 1, 4149, 65, 0 },
1780 { 1021, 1, 1245, 1, 4151, 65, 0 },
1781 { 1300, 1, 1245, 1, 4153, 65, 0 },
1782 { 1565, 1, 1239, 1, 4155, 65, 0 },
1783 { 1817, 1, 1233, 1, 4157, 65, 0 },
1784 { 2076, 1, 1227, 1, 4159, 65, 0 },
1785 { 2328, 1, 1227, 1, 4161, 65, 0 },
1786 { 2580, 1, 1221, 1, 4163, 65, 0 },
1787 { 141, 1, 1215, 1, 4165, 65, 0 },
1788 { 471, 1, 1209, 1, 4167, 65, 0 },
1789 { 269, 1, 1583, 1, 4106, 65, 0 },
1790 { 591, 1, 1578, 1, 4108, 65, 0 },
1791 { 878, 1, 1573, 1, 4110, 65, 0 },
1792 { 1156, 1, 1568, 1, 4112, 65, 0 },
1793 { 1428, 1, 1568, 1, 4114, 65, 0 },
1794 { 1685, 1, 1563, 1, 4116, 65, 0 },
1795 { 1945, 1, 1558, 1, 4118, 65, 0 },
1796 { 2196, 1, 1553, 1, 4120, 65, 0 },
1797 { 2444, 1, 1553, 1, 4122, 65, 0 },
1798 { 2688, 1, 1548, 1, 4124, 65, 0 },
1799 { 6, 1, 1543, 1, 4126, 65, 0 },
1800 { 352, 1, 1538, 1, 4128, 65, 0 },
1801 { 667, 1, 1538, 1, 4130, 65, 0 },
1802 { 961, 1, 1533, 1, 4132, 65, 0 },
1803 { 1232, 1, 1528, 1, 4134, 65, 0 },
1804 { 1505, 1, 1523, 1, 4136, 65, 0 },
1805 { 1755, 1, 1523, 1, 4138, 65, 0 },
1806 { 2022, 1, 1518, 1, 4140, 65, 0 },
1807 { 2266, 1, 1513, 1, 4142, 65, 0 },
1808 { 2526, 1, 1508, 1, 4144, 65, 0 },
1809 { 79, 1, 1508, 1, 4146, 65, 0 },
1810 { 417, 1, 1503, 1, 4148, 65, 0 },
1811 { 740, 1, 1498, 1, 4150, 65, 0 },
1812 { 1026, 1, 1493, 1, 4152, 65, 0 },
1813 { 1305, 1, 1493, 1, 4154, 65, 0 },
1814 { 1570, 1, 1488, 1, 4156, 65, 0 },
1815 { 1822, 1, 1483, 1, 4158, 65, 0 },
1816 { 2081, 1, 1478, 1, 4160, 65, 0 },
1817 { 2333, 1, 1478, 1, 4162, 65, 0 },
1818 { 2585, 1, 1473, 1, 4164, 65, 0 },
1819 { 146, 1, 1468, 1, 4166, 65, 0 },
1820 { 476, 1, 1463, 1, 4168, 65, 0 },
1821 { 2463, 90, 1, 0, 4099, 1, 0 },
1822 { 339, 97, 1, 11, 1654793, 9, 0 },
1823 { 948, 100, 1, 11, 1654797, 9, 0 },
1824 { 1492, 107, 1, 11, 1654801, 9, 0 },
1825 { 2009, 110, 1, 11, 1654805, 9, 0 },
1826 { 2513, 125, 1, 11, 1654809, 9, 0 },
1827 { 65, 128, 1, 11, 1654813, 9, 0 },
1828 { 726, 135, 1, 11, 1654817, 9, 0 },
1829 { 1291, 138, 1, 11, 1654821, 9, 0 },
1830 { 1808, 169, 1, 11, 1654825, 9, 0 },
1831 { 2319, 172, 1, 11, 1654829, 9, 0 },
1832 { 132, 179, 1, 11, 1654833, 9, 0 },
1833 { 793, 182, 1, 11, 1654837, 9, 0 },
1834 { 1358, 197, 1, 11, 1654841, 9, 0 },
1835 { 1875, 200, 1, 11, 1654845, 9, 0 },
1836 { 2386, 207, 1, 11, 1654849, 9, 0 },
1837 { 199, 210, 1, 11, 1654853, 9, 0 },
1838 { 270, 1, 887, 1, 4265, 65, 0 },
1839 { 592, 1, 887, 1, 4266, 65, 0 },
1840 { 879, 1, 887, 1, 4267, 65, 0 },
1841 { 1157, 1, 887, 1, 4268, 65, 0 },
1842 { 1429, 1, 887, 1, 4269, 65, 0 },
1843 { 1686, 1, 887, 1, 4270, 65, 0 },
1844 { 1946, 1, 887, 1, 4271, 65, 0 },
1845 { 2197, 1, 887, 1, 4272, 65, 0 },
1846 { 2445, 1, 887, 1, 4273, 65, 0 },
1847 { 2689, 1, 887, 1, 4274, 65, 0 },
1848 { 7, 1, 887, 1, 4275, 65, 0 },
1849 { 353, 1, 887, 1, 4276, 65, 0 },
1850 { 668, 1, 887, 1, 4277, 65, 0 },
1851 { 962, 1, 887, 1, 4278, 65, 0 },
1852 { 1233, 1, 887, 1, 4279, 65, 0 },
1853 { 1506, 1, 887, 1, 4280, 65, 0 },
1854 { 1756, 1, 887, 1, 4281, 65, 0 },
1855 { 2023, 1, 887, 1, 4282, 65, 0 },
1856 { 2267, 1, 887, 1, 4283, 65, 0 },
1857 { 2527, 1, 887, 1, 4284, 65, 0 },
1858 { 80, 1, 887, 1, 4285, 65, 0 },
1859 { 418, 1, 887, 1, 4286, 65, 0 },
1860 { 741, 1, 887, 1, 4287, 65, 0 },
1861 { 1027, 1, 887, 1, 4288, 65, 0 },
1862 { 1306, 1, 887, 1, 4289, 65, 0 },
1863 { 1571, 1, 887, 1, 4290, 65, 0 },
1864 { 1823, 1, 887, 1, 4291, 65, 0 },
1865 { 2082, 1, 887, 1, 4292, 65, 0 },
1866 { 2334, 1, 887, 1, 4293, 65, 0 },
1867 { 2586, 1, 887, 1, 4294, 65, 0 },
1868 { 147, 1, 887, 1, 4295, 65, 0 },
1869 { 477, 1, 887, 1, 4296, 65, 0 },
1870 { 2467, 1, 1, 1, 4100, 65, 0 },
1871 { 288, 1, 885, 1, 4297, 65, 0 },
1872 { 610, 1, 881, 1, 4298, 65, 0 },
1873 { 897, 1, 881, 1, 4299, 65, 0 },
1874 { 1175, 1, 877, 1, 4300, 65, 0 },
1875 { 1447, 1, 877, 1, 4301, 65, 0 },
1876 { 1704, 1, 873, 1, 4302, 65, 0 },
1877 { 1964, 1, 873, 1, 4303, 65, 0 },
1878 { 2215, 1, 869, 1, 4304, 65, 0 },
1879 { 2468, 1, 869, 1, 4305, 65, 0 },
1880 { 2697, 1, 865, 1, 4306, 65, 0 },
1881 { 17, 1, 865, 1, 4307, 65, 0 },
1882 { 363, 1, 861, 1, 4308, 65, 0 },
1883 { 678, 1, 861, 1, 4309, 65, 0 },
1884 { 972, 1, 857, 1, 4310, 65, 0 },
1885 { 1243, 1, 857, 1, 4311, 65, 0 },
1886 { 1516, 1, 853, 1, 4312, 65, 0 },
1887 { 1766, 1, 853, 1, 4313, 65, 0 },
1888 { 2033, 1, 849, 1, 4314, 65, 0 },
1889 { 2277, 1, 849, 1, 4315, 65, 0 },
1890 { 2537, 1, 845, 1, 4316, 65, 0 },
1891 { 90, 1, 845, 1, 4317, 65, 0 },
1892 { 428, 1, 841, 1, 4318, 65, 0 },
1893 { 751, 1, 841, 1, 4319, 65, 0 },
1894 { 1037, 1, 837, 1, 4320, 65, 0 },
1895 { 1316, 1, 837, 1, 4321, 65, 0 },
1896 { 1581, 1, 833, 1, 4322, 65, 0 },
1897 { 1833, 1, 833, 1, 4323, 65, 0 },
1898 { 2092, 1, 829, 1, 4324, 65, 0 },
1899 { 2344, 1, 829, 1, 4325, 65, 0 },
1900 { 2596, 1, 825, 1, 4326, 65, 0 },
1901 { 157, 1, 825, 1, 4327, 65, 0 },
1902 { 487, 1, 821, 1, 4328, 65, 0 },
1903 { 296, 92, 1, 2, 1712297, 0, 0 },
1904 { 618, 92, 1, 2, 1712298, 0, 0 },
1905 { 905, 92, 1, 2, 1712299, 0, 0 },
1906 { 1183, 92, 1, 2, 1712300, 0, 0 },
1907 { 1455, 92, 1, 2, 1712301, 0, 0 },
1908 { 1712, 92, 1, 2, 1712302, 0, 0 },
1909 { 1972, 92, 1, 2, 1712303, 0, 0 },
1910 { 2223, 92, 1, 2, 1712304, 0, 0 },
1911 { 2476, 92, 1, 2, 1712305, 0, 0 },
1912 { 2700, 92, 1, 2, 1712306, 0, 0 },
1913 { 21, 92, 1, 2, 1712307, 0, 0 },
1914 { 367, 92, 1, 2, 1712308, 0, 0 },
1915 { 682, 92, 1, 2, 1712309, 0, 0 },
1916 { 976, 92, 1, 2, 1712310, 0, 0 },
1917 { 1247, 92, 1, 2, 1712311, 0, 0 },
1918 { 1520, 92, 1, 2, 1712312, 0, 0 },
1919 { 1770, 92, 1, 2, 1712313, 0, 0 },
1920 { 2037, 92, 1, 2, 1712314, 0, 0 },
1921 { 2281, 92, 1, 2, 1712315, 0, 0 },
1922 { 2541, 92, 1, 2, 1712316, 0, 0 },
1923 { 94, 92, 1, 2, 1712317, 0, 0 },
1924 { 432, 92, 1, 2, 1712318, 0, 0 },
1925 { 755, 92, 1, 2, 1712319, 0, 0 },
1926 { 1041, 92, 1, 2, 1712320, 0, 0 },
1927 { 1320, 92, 1, 2, 1712321, 0, 0 },
1928 { 1585, 92, 1, 2, 1712322, 0, 0 },
1929 { 1837, 92, 1, 2, 1712323, 0, 0 },
1930 { 2096, 92, 1, 2, 1712324, 0, 0 },
1931 { 2348, 92, 1, 2, 1712325, 0, 0 },
1932 { 2600, 92, 1, 2, 1712326, 0, 0 },
1933 { 161, 92, 1, 2, 1712327, 0, 0 },
1934 { 491, 92, 1, 2, 1712328, 0, 0 },
1935 { 252, 420, 1, 26, 1622025, 22, 0 },
1936 { 574, 457, 1, 26, 1622033, 22, 0 },
1937 { 861, 494, 1, 26, 1622041, 22, 0 },
1938 { 1139, 531, 1, 26, 1622049, 22, 0 },
1939 { 1411, 568, 1, 26, 1622057, 22, 0 },
1940 { 1668, 605, 1, 26, 1622065, 22, 0 },
1941 { 1928, 642, 1, 26, 1622073, 22, 0 },
1942 { 2179, 679, 1, 26, 1622081, 22, 0 },
1943 { 299, 713, 1456, 5, 401641, 3, 0 },
1944 { 621, 713, 1450, 5, 401643, 3, 0 },
1945 { 908, 713, 1450, 5, 401645, 3, 0 },
1946 { 1186, 713, 1444, 5, 401647, 3, 0 },
1947 { 1458, 713, 1444, 5, 401649, 3, 0 },
1948 { 1715, 713, 1438, 5, 401651, 3, 0 },
1949 { 1975, 713, 1438, 5, 401653, 3, 0 },
1950 { 2226, 713, 1432, 5, 401655, 3, 0 },
1951 { 2479, 713, 1432, 5, 401657, 3, 0 },
1952 { 2703, 713, 1426, 5, 401659, 3, 0 },
1953 { 25, 713, 1426, 5, 401661, 3, 0 },
1954 { 371, 713, 1420, 5, 401663, 3, 0 },
1955 { 686, 713, 1420, 5, 401665, 3, 0 },
1956 { 980, 713, 1414, 5, 401667, 3, 0 },
1957 { 1251, 713, 1414, 5, 401669, 3, 0 },
1958 { 1524, 713, 1408, 5, 401671, 3, 0 },
1959 { 1774, 713, 1408, 5, 401673, 3, 0 },
1960 { 2041, 713, 1402, 5, 401675, 3, 0 },
1961 { 2285, 713, 1402, 5, 401677, 3, 0 },
1962 { 2545, 713, 1396, 5, 401679, 3, 0 },
1963 { 98, 713, 1396, 5, 401681, 3, 0 },
1964 { 436, 713, 1390, 5, 401683, 3, 0 },
1965 { 759, 713, 1390, 5, 401685, 3, 0 },
1966 { 1045, 713, 1384, 5, 401687, 3, 0 },
1967 { 1324, 713, 1384, 5, 401689, 3, 0 },
1968 { 1589, 713, 1378, 5, 401691, 3, 0 },
1969 { 1841, 713, 1378, 5, 401693, 3, 0 },
1970 { 2100, 713, 1372, 5, 401695, 3, 0 },
1971 { 2352, 713, 1372, 5, 401697, 3, 0 },
1972 { 2604, 713, 1366, 5, 401699, 3, 0 },
1973 { 165, 713, 1366, 5, 401701, 3, 0 },
1974 { 495, 713, 1360, 5, 401703, 3, 0 },
1975 { 264, 1, 1458, 1, 4329, 65, 0 },
1976 { 586, 1, 1452, 1, 4331, 65, 0 },
1977 { 873, 1, 1452, 1, 4333, 65, 0 },
1978 { 1151, 1, 1446, 1, 4335, 65, 0 },
1979 { 1423, 1, 1446, 1, 4337, 65, 0 },
1980 { 1680, 1, 1440, 1, 4339, 65, 0 },
1981 { 1940, 1, 1440, 1, 4341, 65, 0 },
1982 { 2191, 1, 1434, 1, 4343, 65, 0 },
1983 { 2439, 1, 1434, 1, 4345, 65, 0 },
1984 { 2683, 1, 1428, 1, 4347, 65, 0 },
1985 { 0, 1, 1428, 1, 4349, 65, 0 },
1986 { 346, 1, 1422, 1, 4351, 65, 0 },
1987 { 661, 1, 1422, 1, 4353, 65, 0 },
1988 { 955, 1, 1416, 1, 4355, 65, 0 },
1989 { 1226, 1, 1416, 1, 4357, 65, 0 },
1990 { 1499, 1, 1410, 1, 4359, 65, 0 },
1991 { 1749, 1, 1410, 1, 4361, 65, 0 },
1992 { 2016, 1, 1404, 1, 4363, 65, 0 },
1993 { 2260, 1, 1404, 1, 4365, 65, 0 },
1994 { 2520, 1, 1398, 1, 4367, 65, 0 },
1995 { 73, 1, 1398, 1, 4369, 65, 0 },
1996 { 411, 1, 1392, 1, 4371, 65, 0 },
1997 { 734, 1, 1392, 1, 4373, 65, 0 },
1998 { 1020, 1, 1386, 1, 4375, 65, 0 },
1999 { 1299, 1, 1386, 1, 4377, 65, 0 },
2000 { 1564, 1, 1380, 1, 4379, 65, 0 },
2001 { 1816, 1, 1380, 1, 4381, 65, 0 },
2002 { 2075, 1, 1374, 1, 4383, 65, 0 },
2003 { 2327, 1, 1374, 1, 4385, 65, 0 },
2004 { 2579, 1, 1368, 1, 4387, 65, 0 },
2005 { 140, 1, 1368, 1, 4389, 65, 0 },
2006 { 470, 1, 1362, 1, 4391, 65, 0 },
2007 { 268, 1, 1455, 1, 4330, 65, 0 },
2008 { 590, 1, 1449, 1, 4332, 65, 0 },
2009 { 877, 1, 1449, 1, 4334, 65, 0 },
2010 { 1155, 1, 1443, 1, 4336, 65, 0 },
2011 { 1427, 1, 1443, 1, 4338, 65, 0 },
2012 { 1684, 1, 1437, 1, 4340, 65, 0 },
2013 { 1944, 1, 1437, 1, 4342, 65, 0 },
2014 { 2195, 1, 1431, 1, 4344, 65, 0 },
2015 { 2443, 1, 1431, 1, 4346, 65, 0 },
2016 { 2687, 1, 1425, 1, 4348, 65, 0 },
2017 { 5, 1, 1425, 1, 4350, 65, 0 },
2018 { 351, 1, 1419, 1, 4352, 65, 0 },
2019 { 666, 1, 1419, 1, 4354, 65, 0 },
2020 { 960, 1, 1413, 1, 4356, 65, 0 },
2021 { 1231, 1, 1413, 1, 4358, 65, 0 },
2022 { 1504, 1, 1407, 1, 4360, 65, 0 },
2023 { 1754, 1, 1407, 1, 4362, 65, 0 },
2024 { 2021, 1, 1401, 1, 4364, 65, 0 },
2025 { 2265, 1, 1401, 1, 4366, 65, 0 },
2026 { 2525, 1, 1395, 1, 4368, 65, 0 },
2027 { 78, 1, 1395, 1, 4370, 65, 0 },
2028 { 416, 1, 1389, 1, 4372, 65, 0 },
2029 { 739, 1, 1389, 1, 4374, 65, 0 },
2030 { 1025, 1, 1383, 1, 4376, 65, 0 },
2031 { 1304, 1, 1383, 1, 4378, 65, 0 },
2032 { 1569, 1, 1377, 1, 4380, 65, 0 },
2033 { 1821, 1, 1377, 1, 4382, 65, 0 },
2034 { 2080, 1, 1371, 1, 4384, 65, 0 },
2035 { 2332, 1, 1371, 1, 4386, 65, 0 },
2036 { 2584, 1, 1365, 1, 4388, 65, 0 },
2037 { 145, 1, 1365, 1, 4390, 65, 0 },
2038 { 475, 1, 1359, 1, 4392, 65, 0 },
2039 { 282, 417, 1584, 5, 401417, 3, 0 },
2040 { 604, 417, 1579, 5, 401419, 3, 0 },
2041 { 891, 417, 1574, 5, 401421, 3, 0 },
2042 { 1169, 417, 1569, 5, 401423, 3, 0 },
2043 { 1441, 417, 1569, 5, 401425, 3, 0 },
2044 { 1698, 417, 1564, 5, 401427, 3, 0 },
2045 { 1958, 417, 1559, 5, 401429, 3, 0 },
2046 { 2209, 417, 1554, 5, 401431, 3, 0 },
2047 { 2448, 417, 1554, 5, 401433, 3, 0 },
2048 { 2692, 417, 1549, 5, 401435, 3, 0 },
2049 { 11, 417, 1544, 5, 401437, 3, 0 },
2050 { 357, 417, 1539, 5, 401439, 3, 0 },
2051 { 672, 417, 1539, 5, 401441, 3, 0 },
2052 { 966, 417, 1534, 5, 401443, 3, 0 },
2053 { 1237, 417, 1529, 5, 401445, 3, 0 },
2054 { 1510, 417, 1524, 5, 401447, 3, 0 },
2055 { 1760, 417, 1524, 5, 401449, 3, 0 },
2056 { 2027, 417, 1519, 5, 401451, 3, 0 },
2057 { 2271, 417, 1514, 5, 401453, 3, 0 },
2058 { 2531, 417, 1509, 5, 401455, 3, 0 },
2059 { 84, 417, 1509, 5, 401457, 3, 0 },
2060 { 422, 417, 1504, 5, 401459, 3, 0 },
2061 { 745, 417, 1499, 5, 401461, 3, 0 },
2062 { 1031, 417, 1494, 5, 401463, 3, 0 },
2063 { 1310, 417, 1494, 5, 401465, 3, 0 },
2064 { 1575, 417, 1489, 5, 401467, 3, 0 },
2065 { 1827, 417, 1484, 5, 401469, 3, 0 },
2066 { 2086, 417, 1479, 5, 401471, 3, 0 },
2067 { 2338, 417, 1479, 5, 401473, 3, 0 },
2068 { 2590, 417, 1474, 5, 401475, 3, 0 },
2069 { 151, 417, 1469, 5, 401477, 3, 0 },
2070 { 481, 417, 1464, 5, 401479, 3, 0 },
2071 { 324, 413, 1580, 19, 1638409, 17, 0 },
2072 { 646, 428, 1565, 19, 1638413, 17, 0 },
2073 { 933, 450, 1565, 19, 1638417, 17, 0 },
2074 { 1211, 465, 1550, 19, 1638421, 17, 0 },
2075 { 1477, 487, 1550, 19, 1638425, 17, 0 },
2076 { 1734, 502, 1535, 19, 1638429, 17, 0 },
2077 { 1994, 524, 1535, 19, 1638433, 17, 0 },
2078 { 2245, 539, 1520, 19, 1638437, 17, 0 },
2079 { 2498, 561, 1520, 19, 1638441, 17, 0 },
2080 { 2722, 576, 1505, 19, 1638445, 17, 0 },
2081 { 48, 598, 1505, 19, 1638449, 17, 0 },
2082 { 394, 613, 1490, 19, 1638453, 17, 0 },
2083 { 709, 635, 1490, 19, 1638457, 17, 0 },
2084 { 1003, 650, 1475, 19, 1638461, 17, 0 },
2085 { 1274, 672, 1475, 19, 1638465, 17, 0 },
2086 { 1547, 687, 1465, 19, 1638469, 17, 0 },
2087 { 1791, 709, 1, 19, 1638633, 17, 0 },
2088 { 2058, 716, 1, 19, 1638637, 17, 0 },
2089 { 2302, 723, 1, 19, 1638641, 17, 0 },
2090 { 2562, 730, 1, 19, 1638645, 17, 0 },
2091 { 115, 737, 1, 19, 1638649, 17, 0 },
2092 { 453, 744, 1, 19, 1638653, 17, 0 },
2093 { 776, 751, 1, 19, 1638657, 17, 0 },
2094 { 1062, 758, 1, 19, 1638661, 17, 0 },
2095 { 1341, 765, 1, 19, 1638665, 17, 0 },
2096 { 1606, 772, 1, 19, 1638669, 17, 0 },
2097 { 1858, 779, 1, 19, 1638673, 17, 0 },
2098 { 2117, 786, 1, 19, 1638677, 17, 0 },
2099 { 2369, 793, 1, 19, 1638681, 17, 0 },
2100 { 2621, 800, 1, 19, 1638685, 17, 0 },
2101 { 182, 807, 1, 19, 1638689, 17, 0 },
2102 { 512, 814, 1, 19, 1638693, 17, 0 },
2103 { 810, 1, 1, 1, 4393, 65, 0 },
2104 { 1088, 1, 1, 1, 4394, 65, 0 },
2105 { 1375, 1, 1, 1, 4395, 65, 0 },
2106 { 1632, 1, 1, 1, 4396, 65, 0 },
2107 { 1892, 1, 1, 1, 4397, 65, 0 },
2108 { 2143, 1, 1, 1, 4398, 65, 0 },
2109 { 2403, 1, 1, 1, 4399, 65, 0 },
2110 { 2647, 1, 1, 1, 4400, 65, 0 },
2111 { 216, 1, 1, 1, 4401, 65, 0 },
2112 { 538, 1, 1, 1, 4402, 65, 0 },
2113 { 825, 1, 1, 1, 4403, 65, 0 },
2114 { 1103, 1, 1, 1, 4404, 65, 0 },
2115 { 1390, 1, 1, 1, 4405, 65, 0 },
2116 { 1647, 1, 1, 1, 4406, 65, 0 },
2117 { 1907, 1, 1, 1, 4407, 65, 0 },
2118 { 2158, 1, 1, 1, 4408, 65, 0 },
2119 { 2418, 1, 1, 1, 4409, 65, 0 },
2120 { 2662, 1, 1, 1, 4410, 65, 0 },
2121 { 231, 1, 1, 1, 4411, 65, 0 },
2122 { 553, 1, 1, 1, 4412, 65, 0 },
2123 { 840, 1, 1, 1, 4413, 65, 0 },
2124 { 1118, 1, 1, 1, 4414, 65, 0 },
2125 { 1405, 1, 1, 1, 4415, 65, 0 },
2126 { 1662, 1, 1, 1, 4416, 65, 0 },
2127 { 1922, 1, 1, 1, 4417, 65, 0 },
2128 { 2173, 1, 1, 1, 4418, 65, 0 },
2129 { 2433, 1, 1, 1, 4419, 65, 0 },
2130 { 2677, 1, 1, 1, 4420, 65, 0 },
2131 { 246, 1, 1, 1, 4421, 65, 0 },
2132 { 568, 1, 1, 1, 4422, 65, 0 },
2133 { 855, 1, 1, 1, 4423, 65, 0 },
2134 { 1133, 1, 1, 1, 4424, 65, 0 },
2135 { 258, 103, 1191, 41, 1638505, 31, 0 },
2136 { 580, 131, 1131, 41, 1638513, 31, 0 },
2137 { 867, 175, 1131, 41, 1638521, 31, 0 },
2138 { 1145, 203, 1051, 41, 1638529, 31, 0 },
2139 { 1417, 247, 1051, 41, 1638537, 31, 0 },
2140 { 1674, 275, 971, 41, 1638545, 31, 0 },
2141 { 1934, 319, 971, 41, 1638553, 31, 0 },
2142 { 2185, 347, 911, 41, 1638561, 31, 0 },
2143 { 273, 121, 1171, 41, 1638509, 31, 0 },
2144 { 595, 165, 1091, 41, 1638517, 31, 0 },
2145 { 882, 193, 1091, 41, 1638525, 31, 0 },
2146 { 1160, 237, 1011, 41, 1638533, 31, 0 },
2147 { 1432, 265, 1011, 41, 1638541, 31, 0 },
2148 { 1689, 309, 931, 41, 1638549, 31, 0 },
2149 { 1949, 337, 931, 41, 1638557, 31, 0 },
2150 { 2200, 381, 891, 41, 1638565, 31, 0 },
2151 { 310, 13, 887, 0, 4297, 1, 0 },
2152 { 632, 13, 883, 0, 4298, 1, 0 },
2153 { 919, 13, 883, 0, 4299, 1, 0 },
2154 { 1197, 13, 879, 0, 4300, 1, 0 },
2155 { 1469, 13, 879, 0, 4301, 1, 0 },
2156 { 1726, 13, 875, 0, 4302, 1, 0 },
2157 { 1986, 13, 875, 0, 4303, 1, 0 },
2158 { 2237, 13, 871, 0, 4304, 1, 0 },
2159 { 2490, 13, 871, 0, 4305, 1, 0 },
2160 { 2714, 13, 867, 0, 4306, 1, 0 },
2161 { 38, 13, 867, 0, 4307, 1, 0 },
2162 { 384, 13, 863, 0, 4308, 1, 0 },
2163 { 699, 13, 863, 0, 4309, 1, 0 },
2164 { 993, 13, 859, 0, 4310, 1, 0 },
2165 { 1264, 13, 859, 0, 4311, 1, 0 },
2166 { 1537, 13, 855, 0, 4312, 1, 0 },
2167 { 1787, 13, 855, 0, 4313, 1, 0 },
2168 { 2054, 13, 851, 0, 4314, 1, 0 },
2169 { 2298, 13, 851, 0, 4315, 1, 0 },
2170 { 2558, 13, 847, 0, 4316, 1, 0 },
2171 { 111, 13, 847, 0, 4317, 1, 0 },
2172 { 449, 13, 843, 0, 4318, 1, 0 },
2173 { 772, 13, 843, 0, 4319, 1, 0 },
2174 { 1058, 13, 839, 0, 4320, 1, 0 },
2175 { 1337, 13, 839, 0, 4321, 1, 0 },
2176 { 1602, 13, 835, 0, 4322, 1, 0 },
2177 { 1854, 13, 835, 0, 4323, 1, 0 },
2178 { 2113, 13, 831, 0, 4324, 1, 0 },
2179 { 2365, 13, 831, 0, 4325, 1, 0 },
2180 { 2617, 13, 827, 0, 4326, 1, 0 },
2181 { 178, 13, 827, 0, 4327, 1, 0 },
2182 { 508, 13, 823, 0, 4328, 1, 0 },
2183 { 2453, 4, 1, 0, 4104, 1, 1 },
2184 { 2806, 1, 8, 1, 4171, 65, 0 },
2185 { 2812, 1, 8, 1, 4175, 65, 0 },
2186 { 2818, 1, 8, 1, 4179, 65, 0 },
2187 { 2824, 1, 8, 1, 4183, 65, 0 },
2188 { 2830, 1, 8, 1, 4187, 65, 0 },
2189 { 2836, 1, 8, 1, 4191, 65, 0 },
2190 { 2842, 1, 8, 1, 4195, 65, 0 },
2191 { 2848, 1, 8, 1, 4199, 65, 0 },
2192 { 2873, 1, 6, 1, 4170, 65, 0 },
2193 { 2879, 1, 6, 1, 4174, 65, 0 },
2194 { 2885, 1, 6, 1, 4178, 65, 0 },
2195 { 2891, 1, 6, 1, 4182, 65, 0 },
2196 { 2897, 1, 6, 1, 4186, 65, 0 },
2197 { 2903, 1, 6, 1, 4190, 65, 0 },
2198 { 2909, 1, 6, 1, 4194, 65, 0 },
2199 { 2915, 1, 6, 1, 4198, 65, 0 },
2200 { 2921, 1, 2, 1, 4169, 65, 0 },
2201 { 2927, 1, 2, 1, 4173, 65, 0 },
2202 { 2933, 1, 2, 1, 4177, 65, 0 },
2203 { 2939, 1, 2, 1, 4181, 65, 0 },
2204 { 2945, 1, 2, 1, 4185, 65, 0 },
2205 { 2951, 1, 2, 1, 4189, 65, 0 },
2206 { 2957, 1, 2, 1, 4193, 65, 0 },
2207 { 2963, 1, 2, 1, 4197, 65, 0 },
2208 { 2747, 1, 0, 1, 4172, 65, 0 },
2209 { 2753, 1, 0, 1, 4176, 65, 0 },
2210 { 2759, 1, 0, 1, 4180, 65, 0 },
2211 { 2765, 1, 0, 1, 4184, 65, 0 },
2212 { 2771, 1, 0, 1, 4188, 65, 0 },
2213 { 2777, 1, 0, 1, 4192, 65, 0 },
2214 { 2783, 1, 0, 1, 4196, 65, 0 },
2215 { 2789, 1, 0, 1, 4200, 65, 0 },
2216 { 313, 10, 1, 94, 401609, 62, 0 },
2217 { 635, 15, 1, 94, 401611, 62, 0 },
2218 { 922, 20, 1, 94, 401613, 62, 0 },
2219 { 1200, 25, 1, 94, 401615, 62, 0 },
2220 { 1472, 30, 1, 94, 401617, 62, 0 },
2221 { 1729, 35, 1, 94, 401619, 62, 0 },
2222 { 1989, 40, 1, 94, 401621, 62, 0 },
2223 { 2240, 45, 1, 94, 401623, 62, 0 },
2224 { 2493, 50, 1, 94, 401625, 62, 0 },
2225 { 2717, 55, 1, 94, 401627, 62, 0 },
2226 { 42, 60, 1, 94, 401629, 62, 0 },
2227 { 388, 65, 1, 94, 401631, 62, 0 },
2228 { 703, 70, 1, 94, 401633, 62, 0 },
2229 { 997, 75, 1, 94, 401635, 62, 0 },
2230 { 1268, 80, 1, 94, 401637, 62, 0 },
2231 { 1541, 85, 1, 94, 401639, 62, 0 },
2232};
2233
2234extern const MCPhysReg PPCRegUnitRoots[][2] = {
2235 { PPC::BP },
2236 { PPC::CARRY, PPC::XER },
2237 { PPC::CTR, PPC::CTR8 },
2238 { PPC::FP },
2239 { PPC::LR, PPC::LR8 },
2240 { PPC::RM },
2241 { PPC::SPEFSCR },
2242 { PPC::VRSAVE },
2243 { PPC::ZERO },
2244 { PPC::F0 },
2245 { PPC::FH0 },
2246 { PPC::F1 },
2247 { PPC::FH1 },
2248 { PPC::F2 },
2249 { PPC::FH2 },
2250 { PPC::F3 },
2251 { PPC::FH3 },
2252 { PPC::F4 },
2253 { PPC::FH4 },
2254 { PPC::F5 },
2255 { PPC::FH5 },
2256 { PPC::F6 },
2257 { PPC::FH6 },
2258 { PPC::F7 },
2259 { PPC::FH7 },
2260 { PPC::F8 },
2261 { PPC::FH8 },
2262 { PPC::F9 },
2263 { PPC::FH9 },
2264 { PPC::F10 },
2265 { PPC::FH10 },
2266 { PPC::F11 },
2267 { PPC::FH11 },
2268 { PPC::F12 },
2269 { PPC::FH12 },
2270 { PPC::F13 },
2271 { PPC::FH13 },
2272 { PPC::F14 },
2273 { PPC::FH14 },
2274 { PPC::F15 },
2275 { PPC::FH15 },
2276 { PPC::F16 },
2277 { PPC::FH16 },
2278 { PPC::F17 },
2279 { PPC::FH17 },
2280 { PPC::F18 },
2281 { PPC::FH18 },
2282 { PPC::F19 },
2283 { PPC::FH19 },
2284 { PPC::F20 },
2285 { PPC::FH20 },
2286 { PPC::F21 },
2287 { PPC::FH21 },
2288 { PPC::F22 },
2289 { PPC::FH22 },
2290 { PPC::F23 },
2291 { PPC::FH23 },
2292 { PPC::F24 },
2293 { PPC::FH24 },
2294 { PPC::F25 },
2295 { PPC::FH25 },
2296 { PPC::F26 },
2297 { PPC::FH26 },
2298 { PPC::F27 },
2299 { PPC::FH27 },
2300 { PPC::F28 },
2301 { PPC::FH28 },
2302 { PPC::F29 },
2303 { PPC::FH29 },
2304 { PPC::F30 },
2305 { PPC::FH30 },
2306 { PPC::F31 },
2307 { PPC::FH31 },
2308 { PPC::CR0LT },
2309 { PPC::CR0GT },
2310 { PPC::CR0EQ },
2311 { PPC::CR0UN },
2312 { PPC::CR1LT },
2313 { PPC::CR1GT },
2314 { PPC::CR1EQ },
2315 { PPC::CR1UN },
2316 { PPC::CR2LT },
2317 { PPC::CR2GT },
2318 { PPC::CR2EQ },
2319 { PPC::CR2UN },
2320 { PPC::CR3LT },
2321 { PPC::CR3GT },
2322 { PPC::CR3EQ },
2323 { PPC::CR3UN },
2324 { PPC::CR4LT },
2325 { PPC::CR4GT },
2326 { PPC::CR4EQ },
2327 { PPC::CR4UN },
2328 { PPC::CR5LT },
2329 { PPC::CR5GT },
2330 { PPC::CR5EQ },
2331 { PPC::CR5UN },
2332 { PPC::CR6LT },
2333 { PPC::CR6GT },
2334 { PPC::CR6EQ },
2335 { PPC::CR6UN },
2336 { PPC::CR7LT },
2337 { PPC::CR7GT },
2338 { PPC::CR7EQ },
2339 { PPC::CR7UN },
2340 { PPC::DMRROW0 },
2341 { PPC::DMRROW1 },
2342 { PPC::DMRROW2 },
2343 { PPC::DMRROW3 },
2344 { PPC::DMRROW4 },
2345 { PPC::DMRROW5 },
2346 { PPC::DMRROW6 },
2347 { PPC::DMRROW7 },
2348 { PPC::DMRROW8 },
2349 { PPC::DMRROW9 },
2350 { PPC::DMRROW10 },
2351 { PPC::DMRROW11 },
2352 { PPC::DMRROW12 },
2353 { PPC::DMRROW13 },
2354 { PPC::DMRROW14 },
2355 { PPC::DMRROW15 },
2356 { PPC::DMRROW16 },
2357 { PPC::DMRROW17 },
2358 { PPC::DMRROW18 },
2359 { PPC::DMRROW19 },
2360 { PPC::DMRROW20 },
2361 { PPC::DMRROW21 },
2362 { PPC::DMRROW22 },
2363 { PPC::DMRROW23 },
2364 { PPC::DMRROW24 },
2365 { PPC::DMRROW25 },
2366 { PPC::DMRROW26 },
2367 { PPC::DMRROW27 },
2368 { PPC::DMRROW28 },
2369 { PPC::DMRROW29 },
2370 { PPC::DMRROW30 },
2371 { PPC::DMRROW31 },
2372 { PPC::DMRROW32 },
2373 { PPC::DMRROW33 },
2374 { PPC::DMRROW34 },
2375 { PPC::DMRROW35 },
2376 { PPC::DMRROW36 },
2377 { PPC::DMRROW37 },
2378 { PPC::DMRROW38 },
2379 { PPC::DMRROW39 },
2380 { PPC::DMRROW40 },
2381 { PPC::DMRROW41 },
2382 { PPC::DMRROW42 },
2383 { PPC::DMRROW43 },
2384 { PPC::DMRROW44 },
2385 { PPC::DMRROW45 },
2386 { PPC::DMRROW46 },
2387 { PPC::DMRROW47 },
2388 { PPC::DMRROW48 },
2389 { PPC::DMRROW49 },
2390 { PPC::DMRROW50 },
2391 { PPC::DMRROW51 },
2392 { PPC::DMRROW52 },
2393 { PPC::DMRROW53 },
2394 { PPC::DMRROW54 },
2395 { PPC::DMRROW55 },
2396 { PPC::DMRROW56 },
2397 { PPC::DMRROW57 },
2398 { PPC::DMRROW58 },
2399 { PPC::DMRROW59 },
2400 { PPC::DMRROW60 },
2401 { PPC::DMRROW61 },
2402 { PPC::DMRROW62 },
2403 { PPC::DMRROW63 },
2404 { PPC::H0 },
2405 { PPC::H1 },
2406 { PPC::H2 },
2407 { PPC::H3 },
2408 { PPC::H4 },
2409 { PPC::H5 },
2410 { PPC::H6 },
2411 { PPC::H7 },
2412 { PPC::H8 },
2413 { PPC::H9 },
2414 { PPC::H10 },
2415 { PPC::H11 },
2416 { PPC::H12 },
2417 { PPC::H13 },
2418 { PPC::H14 },
2419 { PPC::H15 },
2420 { PPC::H16 },
2421 { PPC::H17 },
2422 { PPC::H18 },
2423 { PPC::H19 },
2424 { PPC::H20 },
2425 { PPC::H21 },
2426 { PPC::H22 },
2427 { PPC::H23 },
2428 { PPC::H24 },
2429 { PPC::H25 },
2430 { PPC::H26 },
2431 { PPC::H27 },
2432 { PPC::H28 },
2433 { PPC::H29 },
2434 { PPC::H30 },
2435 { PPC::H31 },
2436 { PPC::R0 },
2437 { PPC::R1 },
2438 { PPC::R2 },
2439 { PPC::R3 },
2440 { PPC::R4 },
2441 { PPC::R5 },
2442 { PPC::R6 },
2443 { PPC::R7 },
2444 { PPC::R8 },
2445 { PPC::R9 },
2446 { PPC::R10 },
2447 { PPC::R11 },
2448 { PPC::R12 },
2449 { PPC::R13 },
2450 { PPC::R14 },
2451 { PPC::R15 },
2452 { PPC::R16 },
2453 { PPC::R17 },
2454 { PPC::R18 },
2455 { PPC::R19 },
2456 { PPC::R20 },
2457 { PPC::R21 },
2458 { PPC::R22 },
2459 { PPC::R23 },
2460 { PPC::R24 },
2461 { PPC::R25 },
2462 { PPC::R26 },
2463 { PPC::R27 },
2464 { PPC::R28 },
2465 { PPC::R29 },
2466 { PPC::R30 },
2467 { PPC::R31 },
2468 { PPC::VF0 },
2469 { PPC::VFH0 },
2470 { PPC::VF1 },
2471 { PPC::VFH1 },
2472 { PPC::VF2 },
2473 { PPC::VFH2 },
2474 { PPC::VF3 },
2475 { PPC::VFH3 },
2476 { PPC::VF4 },
2477 { PPC::VFH4 },
2478 { PPC::VF5 },
2479 { PPC::VFH5 },
2480 { PPC::VF6 },
2481 { PPC::VFH6 },
2482 { PPC::VF7 },
2483 { PPC::VFH7 },
2484 { PPC::VF8 },
2485 { PPC::VFH8 },
2486 { PPC::VF9 },
2487 { PPC::VFH9 },
2488 { PPC::VF10 },
2489 { PPC::VFH10 },
2490 { PPC::VF11 },
2491 { PPC::VFH11 },
2492 { PPC::VF12 },
2493 { PPC::VFH12 },
2494 { PPC::VF13 },
2495 { PPC::VFH13 },
2496 { PPC::VF14 },
2497 { PPC::VFH14 },
2498 { PPC::VF15 },
2499 { PPC::VFH15 },
2500 { PPC::VF16 },
2501 { PPC::VFH16 },
2502 { PPC::VF17 },
2503 { PPC::VFH17 },
2504 { PPC::VF18 },
2505 { PPC::VFH18 },
2506 { PPC::VF19 },
2507 { PPC::VFH19 },
2508 { PPC::VF20 },
2509 { PPC::VFH20 },
2510 { PPC::VF21 },
2511 { PPC::VFH21 },
2512 { PPC::VF22 },
2513 { PPC::VFH22 },
2514 { PPC::VF23 },
2515 { PPC::VFH23 },
2516 { PPC::VF24 },
2517 { PPC::VFH24 },
2518 { PPC::VF25 },
2519 { PPC::VFH25 },
2520 { PPC::VF26 },
2521 { PPC::VFH26 },
2522 { PPC::VF27 },
2523 { PPC::VFH27 },
2524 { PPC::VF28 },
2525 { PPC::VFH28 },
2526 { PPC::VF29 },
2527 { PPC::VFH29 },
2528 { PPC::VF30 },
2529 { PPC::VFH30 },
2530 { PPC::VF31 },
2531 { PPC::VFH31 },
2532 { PPC::VSX32 },
2533 { PPC::VSX33 },
2534 { PPC::VSX34 },
2535 { PPC::VSX35 },
2536 { PPC::VSX36 },
2537 { PPC::VSX37 },
2538 { PPC::VSX38 },
2539 { PPC::VSX39 },
2540 { PPC::VSX40 },
2541 { PPC::VSX41 },
2542 { PPC::VSX42 },
2543 { PPC::VSX43 },
2544 { PPC::VSX44 },
2545 { PPC::VSX45 },
2546 { PPC::VSX46 },
2547 { PPC::VSX47 },
2548 { PPC::VSX48 },
2549 { PPC::VSX49 },
2550 { PPC::VSX50 },
2551 { PPC::VSX51 },
2552 { PPC::VSX52 },
2553 { PPC::VSX53 },
2554 { PPC::VSX54 },
2555 { PPC::VSX55 },
2556 { PPC::VSX56 },
2557 { PPC::VSX57 },
2558 { PPC::VSX58 },
2559 { PPC::VSX59 },
2560 { PPC::VSX60 },
2561 { PPC::VSX61 },
2562 { PPC::VSX62 },
2563 { PPC::VSX63 },
2564};
2565
2566namespace { // Register classes...
2567 // VSSRC Register Class...
2568 const MCPhysReg VSSRC[] = {
2569 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2570 };
2571
2572 // VSSRC Bit set.
2573 const uint8_t VSSRCBits[] = {
2574 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2575 };
2576
2577 // GPRC Register Class...
2578 const MCPhysReg GPRC[] = {
2579 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP,
2580 };
2581
2582 // GPRC Bit set.
2583 const uint8_t GPRCBits[] = {
2584 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2585 };
2586
2587 // GPRC_NOR0 Register Class...
2588 const MCPhysReg GPRC_NOR0[] = {
2589 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO,
2590 };
2591
2592 // GPRC_NOR0 Bit set.
2593 const uint8_t GPRC_NOR0Bits[] = {
2594 0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2595 };
2596
2597 // GPRC_and_GPRC_NOR0 Register Class...
2598 const MCPhysReg GPRC_and_GPRC_NOR0[] = {
2599 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP,
2600 };
2601
2602 // GPRC_and_GPRC_NOR0 Bit set.
2603 const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
2604 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2605 };
2606
2607 // CRBITRC Register Class...
2608 const MCPhysReg CRBITRC[] = {
2609 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
2610 };
2611
2612 // CRBITRC Bit set.
2613 const uint8_t CRBITRCBits[] = {
2614 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2615 };
2616
2617 // F4RC Register Class...
2618 const MCPhysReg F4RC[] = {
2619 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
2620 };
2621
2622 // F4RC Bit set.
2623 const uint8_t F4RCBits[] = {
2624 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2625 };
2626
2627 // GPRC32 Register Class...
2628 const MCPhysReg GPRC32[] = {
2629 PPC::H2, PPC::H3, PPC::H4, PPC::H5, PPC::H6, PPC::H7, PPC::H8, PPC::H9, PPC::H10, PPC::H11, PPC::H12, PPC::H30, PPC::H29, PPC::H28, PPC::H27, PPC::H26, PPC::H25, PPC::H24, PPC::H23, PPC::H22, PPC::H21, PPC::H20, PPC::H19, PPC::H18, PPC::H17, PPC::H16, PPC::H15, PPC::H14, PPC::H13, PPC::H31, PPC::H0, PPC::H1,
2630 };
2631
2632 // GPRC32 Bit set.
2633 const uint8_t GPRC32Bits[] = {
2634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
2635 };
2636
2637 // CRRC Register Class...
2638 const MCPhysReg CRRC[] = {
2639 PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4,
2640 };
2641
2642 // CRRC Bit set.
2643 const uint8_t CRRCBits[] = {
2644 0x00, 0x00, 0xf0, 0x0f,
2645 };
2646
2647 // CARRYRC Register Class...
2648 const MCPhysReg CARRYRC[] = {
2649 PPC::CARRY, PPC::XER,
2650 };
2651
2652 // CARRYRC Bit set.
2653 const uint8_t CARRYRCBits[] = {
2654 0x04, 0x02,
2655 };
2656
2657 // CTRRC Register Class...
2658 const MCPhysReg CTRRC[] = {
2659 PPC::CTR,
2660 };
2661
2662 // CTRRC Bit set.
2663 const uint8_t CTRRCBits[] = {
2664 0x08,
2665 };
2666
2667 // LRRC Register Class...
2668 const MCPhysReg LRRC[] = {
2669 PPC::LR,
2670 };
2671
2672 // LRRC Bit set.
2673 const uint8_t LRRCBits[] = {
2674 0x20,
2675 };
2676
2677 // VRSAVERC Register Class...
2678 const MCPhysReg VRSAVERC[] = {
2679 PPC::VRSAVE,
2680 };
2681
2682 // VRSAVERC Bit set.
2683 const uint8_t VRSAVERCBits[] = {
2684 0x00, 0x01,
2685 };
2686
2687 // SPILLTOVSRRC Register Class...
2688 const MCPhysReg SPILLTOVSRRC[] = {
2689 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2690 };
2691
2692 // SPILLTOVSRRC Bit set.
2693 const uint8_t SPILLTOVSRRCBits[] = {
2694 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2695 };
2696
2697 // VSFRC Register Class...
2698 const MCPhysReg VSFRC[] = {
2699 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2700 };
2701
2702 // VSFRC Bit set.
2703 const uint8_t VSFRCBits[] = {
2704 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2705 };
2706
2707 // G8RC Register Class...
2708 const MCPhysReg G8RC[] = {
2709 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8,
2710 };
2711
2712 // G8RC Bit set.
2713 const uint8_t G8RCBits[] = {
2714 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2715 };
2716
2717 // G8RC_NOX0 Register Class...
2718 const MCPhysReg G8RC_NOX0[] = {
2719 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8,
2720 };
2721
2722 // G8RC_NOX0 Bit set.
2723 const uint8_t G8RC_NOX0Bits[] = {
2724 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2725 };
2726
2727 // SPILLTOVSRRC_and_VSFRC Register Class...
2728 const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
2729 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2730 };
2731
2732 // SPILLTOVSRRC_and_VSFRC Bit set.
2733 const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = {
2734 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2735 };
2736
2737 // G8RC_and_G8RC_NOX0 Register Class...
2738 const MCPhysReg G8RC_and_G8RC_NOX0[] = {
2739 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8,
2740 };
2741
2742 // G8RC_and_G8RC_NOX0 Bit set.
2743 const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
2744 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2745 };
2746
2747 // F8RC Register Class...
2748 const MCPhysReg F8RC[] = {
2749 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
2750 };
2751
2752 // F8RC Bit set.
2753 const uint8_t F8RCBits[] = {
2754 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2755 };
2756
2757 // FHRC Register Class...
2758 const MCPhysReg FHRC[] = {
2759 PPC::FH0, PPC::FH1, PPC::FH2, PPC::FH3, PPC::FH4, PPC::FH5, PPC::FH6, PPC::FH7, PPC::FH8, PPC::FH9, PPC::FH10, PPC::FH11, PPC::FH12, PPC::FH13, PPC::FH14, PPC::FH15, PPC::FH16, PPC::FH17, PPC::FH18, PPC::FH19, PPC::FH20, PPC::FH21, PPC::FH22, PPC::FH23, PPC::FH24, PPC::FH25, PPC::FH26, PPC::FH27, PPC::FH28, PPC::FH29, PPC::FH30, PPC::FH31,
2760 };
2761
2762 // FHRC Bit set.
2763 const uint8_t FHRCBits[] = {
2764 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2765 };
2766
2767 // SPERC Register Class...
2768 const MCPhysReg SPERC[] = {
2769 PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S0, PPC::S1,
2770 };
2771
2772 // SPERC Bit set.
2773 const uint8_t SPERCBits[] = {
2774 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2775 };
2776
2777 // VFHRC Register Class...
2778 const MCPhysReg VFHRC[] = {
2779 PPC::VFH0, PPC::VFH1, PPC::VFH2, PPC::VFH3, PPC::VFH4, PPC::VFH5, PPC::VFH6, PPC::VFH7, PPC::VFH8, PPC::VFH9, PPC::VFH10, PPC::VFH11, PPC::VFH12, PPC::VFH13, PPC::VFH14, PPC::VFH15, PPC::VFH16, PPC::VFH17, PPC::VFH18, PPC::VFH19, PPC::VFH20, PPC::VFH21, PPC::VFH22, PPC::VFH23, PPC::VFH24, PPC::VFH25, PPC::VFH26, PPC::VFH27, PPC::VFH28, PPC::VFH29, PPC::VFH30, PPC::VFH31,
2780 };
2781
2782 // VFHRC Bit set.
2783 const uint8_t VFHRCBits[] = {
2784 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2785 };
2786
2787 // VFRC Register Class...
2788 const MCPhysReg VFRC[] = {
2789 PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2790 };
2791
2792 // VFRC Bit set.
2793 const uint8_t VFRCBits[] = {
2794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2795 };
2796
2797 // SPERC_with_sub_32_in_GPRC_NOR0 Register Class...
2798 const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
2799 PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S1,
2800 };
2801
2802 // SPERC_with_sub_32_in_GPRC_NOR0 Bit set.
2803 const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = {
2804 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2805 };
2806
2807 // SPILLTOVSRRC_and_VFRC Register Class...
2808 const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
2809 PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2810 };
2811
2812 // SPILLTOVSRRC_and_VFRC Bit set.
2813 const uint8_t SPILLTOVSRRC_and_VFRCBits[] = {
2814 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2815 };
2816
2817 // SPILLTOVSRRC_and_F4RC Register Class...
2818 const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
2819 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13,
2820 };
2821
2822 // SPILLTOVSRRC_and_F4RC Bit set.
2823 const uint8_t SPILLTOVSRRC_and_F4RCBits[] = {
2824 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f,
2825 };
2826
2827 // CTRRC8 Register Class...
2828 const MCPhysReg CTRRC8[] = {
2829 PPC::CTR8,
2830 };
2831
2832 // CTRRC8 Bit set.
2833 const uint8_t CTRRC8Bits[] = {
2834 0x00, 0x00, 0x00, 0x10,
2835 };
2836
2837 // LR8RC Register Class...
2838 const MCPhysReg LR8RC[] = {
2839 PPC::LR8,
2840 };
2841
2842 // LR8RC Bit set.
2843 const uint8_t LR8RCBits[] = {
2844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2845 };
2846
2847 // DMRROWRC Register Class...
2848 const MCPhysReg DMRROWRC[] = {
2849 PPC::DMRROW0, PPC::DMRROW1, PPC::DMRROW2, PPC::DMRROW3, PPC::DMRROW4, PPC::DMRROW5, PPC::DMRROW6, PPC::DMRROW7, PPC::DMRROW8, PPC::DMRROW9, PPC::DMRROW10, PPC::DMRROW11, PPC::DMRROW12, PPC::DMRROW13, PPC::DMRROW14, PPC::DMRROW15, PPC::DMRROW16, PPC::DMRROW17, PPC::DMRROW18, PPC::DMRROW19, PPC::DMRROW20, PPC::DMRROW21, PPC::DMRROW22, PPC::DMRROW23, PPC::DMRROW24, PPC::DMRROW25, PPC::DMRROW26, PPC::DMRROW27, PPC::DMRROW28, PPC::DMRROW29, PPC::DMRROW30, PPC::DMRROW31, PPC::DMRROW32, PPC::DMRROW33, PPC::DMRROW34, PPC::DMRROW35, PPC::DMRROW36, PPC::DMRROW37, PPC::DMRROW38, PPC::DMRROW39, PPC::DMRROW40, PPC::DMRROW41, PPC::DMRROW42, PPC::DMRROW43, PPC::DMRROW44, PPC::DMRROW45, PPC::DMRROW46, PPC::DMRROW47, PPC::DMRROW48, PPC::DMRROW49, PPC::DMRROW50, PPC::DMRROW51, PPC::DMRROW52, PPC::DMRROW53, PPC::DMRROW54, PPC::DMRROW55, PPC::DMRROW56, PPC::DMRROW57, PPC::DMRROW58, PPC::DMRROW59, PPC::DMRROW60, PPC::DMRROW61, PPC::DMRROW62, PPC::DMRROW63,
2850 };
2851
2852 // DMRROWRC Bit set.
2853 const uint8_t DMRROWRCBits[] = {
2854 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f,
2855 };
2856
2857 // VSRC Register Class...
2858 const MCPhysReg VSRC[] = {
2859 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2860 };
2861
2862 // VSRC Bit set.
2863 const uint8_t VSRCBits[] = {
2864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2865 };
2866
2867 // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2868 const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
2869 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2870 };
2871
2872 // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2873 const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2874 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2875 };
2876
2877 // VRRC Register Class...
2878 const MCPhysReg VRRC[] = {
2879 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2880 };
2881
2882 // VRRC Bit set.
2883 const uint8_t VRRCBits[] = {
2884 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2885 };
2886
2887 // VSLRC Register Class...
2888 const MCPhysReg VSLRC[] = {
2889 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14,
2890 };
2891
2892 // VSLRC Bit set.
2893 const uint8_t VSLRCBits[] = {
2894 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2895 };
2896
2897 // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2898 const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
2899 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2900 };
2901
2902 // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2903 const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2904 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2905 };
2906
2907 // FpRC Register Class...
2908 const MCPhysReg FpRC[] = {
2909 PPC::Fpair0, PPC::Fpair2, PPC::Fpair4, PPC::Fpair6, PPC::Fpair8, PPC::Fpair10, PPC::Fpair12, PPC::Fpair14, PPC::Fpair16, PPC::Fpair18, PPC::Fpair20, PPC::Fpair22, PPC::Fpair24, PPC::Fpair26, PPC::Fpair28, PPC::Fpair30,
2910 };
2911
2912 // FpRC Bit set.
2913 const uint8_t FpRCBits[] = {
2914 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
2915 };
2916
2917 // G8pRC Register Class...
2918 const MCPhysReg G8pRC[] = {
2919 PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0,
2920 };
2921
2922 // G8pRC Bit set.
2923 const uint8_t G8pRCBits[] = {
2924 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2925 };
2926
2927 // G8pRC_with_sub_32_in_GPRC_NOR0 Register Class...
2928 const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = {
2929 PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6,
2930 };
2931
2932 // G8pRC_with_sub_32_in_GPRC_NOR0 Bit set.
2933 const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = {
2934 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2935 };
2936
2937 // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2938 const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
2939 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13,
2940 };
2941
2942 // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2943 const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2944 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2945 };
2946
2947 // FpRC_with_sub_fp0_in_SPILLTOVSRRC Register Class...
2948 const MCPhysReg FpRC_with_sub_fp0_in_SPILLTOVSRRC[] = {
2949 PPC::Fpair0, PPC::Fpair2, PPC::Fpair4, PPC::Fpair6, PPC::Fpair8, PPC::Fpair10, PPC::Fpair12,
2950 };
2951
2952 // FpRC_with_sub_fp0_in_SPILLTOVSRRC Bit set.
2953 const uint8_t FpRC_with_sub_fp0_in_SPILLTOVSRRCBits[] = {
2954 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
2955 };
2956
2957 // DMRROWpRC Register Class...
2958 const MCPhysReg DMRROWpRC[] = {
2959 PPC::DMRROWp0, PPC::DMRROWp1, PPC::DMRROWp2, PPC::DMRROWp3, PPC::DMRROWp4, PPC::DMRROWp5, PPC::DMRROWp6, PPC::DMRROWp7, PPC::DMRROWp8, PPC::DMRROWp9, PPC::DMRROWp10, PPC::DMRROWp11, PPC::DMRROWp12, PPC::DMRROWp13, PPC::DMRROWp14, PPC::DMRROWp15, PPC::DMRROWp16, PPC::DMRROWp17, PPC::DMRROWp18, PPC::DMRROWp19, PPC::DMRROWp20, PPC::DMRROWp21, PPC::DMRROWp22, PPC::DMRROWp23, PPC::DMRROWp24, PPC::DMRROWp25, PPC::DMRROWp26, PPC::DMRROWp27, PPC::DMRROWp28, PPC::DMRROWp29, PPC::DMRROWp30, PPC::DMRROWp31,
2960 };
2961
2962 // DMRROWpRC Bit set.
2963 const uint8_t DMRROWpRCBits[] = {
2964 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2965 };
2966
2967 // VSRpRC Register Class...
2968 const MCPhysReg VSRpRC[] = {
2969 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
2970 };
2971
2972 // VSRpRC Bit set.
2973 const uint8_t VSRpRCBits[] = {
2974 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2975 };
2976
2977 // VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2978 const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = {
2979 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
2980 };
2981
2982 // VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2983 const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xf8, 0x1f,
2985 };
2986
2987 // VSRpRC_with_sub_64_in_F4RC Register Class...
2988 const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = {
2989 PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
2990 };
2991
2992 // VSRpRC_with_sub_64_in_F4RC Bit set.
2993 const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = {
2994 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
2995 };
2996
2997 // VSRpRC_with_sub_64_in_VFRC Register Class...
2998 const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = {
2999 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26,
3000 };
3001
3002 // VSRpRC_with_sub_64_in_VFRC Bit set.
3003 const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = {
3004 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3005 };
3006
3007 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class...
3008 const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = {
3009 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25,
3010 };
3011
3012 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set.
3013 const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = {
3014 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f,
3015 };
3016
3017 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class...
3018 const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = {
3019 PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
3020 };
3021
3022 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set.
3023 const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = {
3024 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
3025 };
3026
3027 // ACCRC Register Class...
3028 const MCPhysReg ACCRC[] = {
3029 PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3, PPC::ACC4, PPC::ACC5, PPC::ACC6, PPC::ACC7,
3030 };
3031
3032 // ACCRC Bit set.
3033 const uint8_t ACCRCBits[] = {
3034 0x00, 0xf8, 0x07,
3035 };
3036
3037 // UACCRC Register Class...
3038 const MCPhysReg UACCRC[] = {
3039 PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3, PPC::UACC4, PPC::UACC5, PPC::UACC6, PPC::UACC7,
3040 };
3041
3042 // UACCRC Bit set.
3043 const uint8_t UACCRCBits[] = {
3044 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3045 };
3046
3047 // WACCRC Register Class...
3048 const MCPhysReg WACCRC[] = {
3049 PPC::WACC0, PPC::WACC1, PPC::WACC2, PPC::WACC3, PPC::WACC4, PPC::WACC5, PPC::WACC6, PPC::WACC7,
3050 };
3051
3052 // WACCRC Bit set.
3053 const uint8_t WACCRCBits[] = {
3054 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3055 };
3056
3057 // WACC_HIRC Register Class...
3058 const MCPhysReg WACC_HIRC[] = {
3059 PPC::WACC_HI0, PPC::WACC_HI1, PPC::WACC_HI2, PPC::WACC_HI3, PPC::WACC_HI4, PPC::WACC_HI5, PPC::WACC_HI6, PPC::WACC_HI7,
3060 };
3061
3062 // WACC_HIRC Bit set.
3063 const uint8_t WACC_HIRCBits[] = {
3064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3065 };
3066
3067 // ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
3068 const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
3069 PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3,
3070 };
3071
3072 // ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
3073 const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
3074 0x00, 0x78,
3075 };
3076
3077 // UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
3078 const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
3079 PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3,
3080 };
3081
3082 // UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
3083 const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
3084 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
3085 };
3086
3087 // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
3088 const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
3089 PPC::ACC0, PPC::ACC1, PPC::ACC2,
3090 };
3091
3092 // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
3093 const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
3094 0x00, 0x38,
3095 };
3096
3097 // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
3098 const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
3099 PPC::UACC0, PPC::UACC1, PPC::UACC2,
3100 };
3101
3102 // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
3103 const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
3104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
3105 };
3106
3107 // DMRRC Register Class...
3108 const MCPhysReg DMRRC[] = {
3109 PPC::DMR0, PPC::DMR1, PPC::DMR2, PPC::DMR3, PPC::DMR4, PPC::DMR5, PPC::DMR6, PPC::DMR7,
3110 };
3111
3112 // DMRRC Bit set.
3113 const uint8_t DMRRCBits[] = {
3114 0x00, 0x00, 0x00, 0xe0, 0x1f,
3115 };
3116
3117 // DMRpRC Register Class...
3118 const MCPhysReg DMRpRC[] = {
3119 PPC::DMRp0, PPC::DMRp1, PPC::DMRp2, PPC::DMRp3,
3120 };
3121
3122 // DMRpRC Bit set.
3123 const uint8_t DMRpRCBits[] = {
3124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
3125 };
3126
3127} // end anonymous namespace
3128
3129
3130#ifdef __GNUC__
3131#pragma GCC diagnostic push
3132#pragma GCC diagnostic ignored "-Woverlength-strings"
3133#endif
3134extern const char PPCRegClassStrings[] = {
3135 /* 0 */ "GPRC_and_GPRC_NOR0\0"
3136 /* 19 */ "SPERC_with_sub_32_in_GPRC_NOR0\0"
3137 /* 50 */ "G8pRC_with_sub_32_in_GPRC_NOR0\0"
3138 /* 81 */ "G8RC_and_G8RC_NOX0\0"
3139 /* 100 */ "GPRC32\0"
3140 /* 107 */ "CTRRC8\0"
3141 /* 114 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC\0"
3142 /* 158 */ "VSRpRC_with_sub_64_in_F4RC\0"
3143 /* 185 */ "F8RC\0"
3144 /* 190 */ "G8RC\0"
3145 /* 195 */ "LR8RC\0"
3146 /* 201 */ "UACCRC\0"
3147 /* 208 */ "WACCRC\0"
3148 /* 215 */ "SPERC\0"
3149 /* 221 */ "VRSAVERC\0"
3150 /* 230 */ "SPILLTOVSRRC_and_VSFRC\0"
3151 /* 253 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC\0"
3152 /* 297 */ "VSRpRC_with_sub_64_in_VFRC\0"
3153 /* 324 */ "VFHRC\0"
3154 /* 330 */ "WACC_HIRC\0"
3155 /* 340 */ "VSLRC\0"
3156 /* 346 */ "GPRC\0"
3157 /* 351 */ "CRRC\0"
3158 /* 356 */ "LRRC\0"
3159 /* 361 */ "DMRRC\0"
3160 /* 367 */ "FpRC_with_sub_fp0_in_SPILLTOVSRRC\0"
3161 /* 401 */ "UACCRC_with_sub_64_in_SPILLTOVSRRC\0"
3162 /* 436 */ "VSLRC_with_sub_64_in_SPILLTOVSRRC\0"
3163 /* 470 */ "VRRC_with_sub_64_in_SPILLTOVSRRC\0"
3164 /* 503 */ "VSRC_with_sub_64_in_SPILLTOVSRRC\0"
3165 /* 536 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC\0"
3166 /* 571 */ "UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC\0"
3167 /* 621 */ "CTRRC\0"
3168 /* 627 */ "VRRC\0"
3169 /* 632 */ "VSSRC\0"
3170 /* 638 */ "VSRC\0"
3171 /* 643 */ "CRBITRC\0"
3172 /* 651 */ "DMRROWRC\0"
3173 /* 660 */ "CARRYRC\0"
3174 /* 668 */ "G8pRC\0"
3175 /* 674 */ "FpRC\0"
3176 /* 679 */ "DMRpRC\0"
3177 /* 686 */ "VSRpRC\0"
3178 /* 693 */ "DMRROWpRC\0"
3179};
3180#ifdef __GNUC__
3181#pragma GCC diagnostic pop
3182#endif
3183
3184extern const MCRegisterClass PPCMCRegisterClasses[] = {
3185 { VSSRC, VSSRCBits, 632, 64, sizeof(VSSRCBits), PPC::VSSRCRegClassID, 32, 1, true, false },
3186 { GPRC, GPRCBits, 346, 34, sizeof(GPRCBits), PPC::GPRCRegClassID, 32, 1, true, false },
3187 { GPRC_NOR0, GPRC_NOR0Bits, 9, 34, sizeof(GPRC_NOR0Bits), PPC::GPRC_NOR0RegClassID, 32, 1, true, false },
3188 { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 0, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC::GPRC_and_GPRC_NOR0RegClassID, 32, 1, true, false },
3189 { CRBITRC, CRBITRCBits, 643, 32, sizeof(CRBITRCBits), PPC::CRBITRCRegClassID, 32, 1, true, false },
3190 { F4RC, F4RCBits, 153, 32, sizeof(F4RCBits), PPC::F4RCRegClassID, 32, 1, true, false },
3191 { GPRC32, GPRC32Bits, 100, 32, sizeof(GPRC32Bits), PPC::GPRC32RegClassID, 32, 1, false, false },
3192 { CRRC, CRRCBits, 351, 8, sizeof(CRRCBits), PPC::CRRCRegClassID, 32, 1, true, false },
3193 { CARRYRC, CARRYRCBits, 660, 2, sizeof(CARRYRCBits), PPC::CARRYRCRegClassID, 32, -1, true, false },
3194 { CTRRC, CTRRCBits, 621, 1, sizeof(CTRRCBits), PPC::CTRRCRegClassID, 32, 1, false, false },
3195 { LRRC, LRRCBits, 356, 1, sizeof(LRRCBits), PPC::LRRCRegClassID, 32, 1, false, false },
3196 { VRSAVERC, VRSAVERCBits, 221, 1, sizeof(VRSAVERCBits), PPC::VRSAVERCRegClassID, 32, 1, true, false },
3197 { SPILLTOVSRRC, SPILLTOVSRRCBits, 388, 68, sizeof(SPILLTOVSRRCBits), PPC::SPILLTOVSRRCRegClassID, 64, 1, true, false },
3198 { VSFRC, VSFRCBits, 247, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 64, 1, true, false },
3199 { G8RC, G8RCBits, 190, 34, sizeof(G8RCBits), PPC::G8RCRegClassID, 64, 1, true, false },
3200 { G8RC_NOX0, G8RC_NOX0Bits, 90, 34, sizeof(G8RC_NOX0Bits), PPC::G8RC_NOX0RegClassID, 64, 1, true, false },
3201 { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, 230, 34, sizeof(SPILLTOVSRRC_and_VSFRCBits), PPC::SPILLTOVSRRC_and_VSFRCRegClassID, 64, 1, true, false },
3202 { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 81, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC::G8RC_and_G8RC_NOX0RegClassID, 64, 1, true, false },
3203 { F8RC, F8RCBits, 185, 32, sizeof(F8RCBits), PPC::F8RCRegClassID, 64, 1, true, false },
3204 { FHRC, FHRCBits, 325, 32, sizeof(FHRCBits), PPC::FHRCRegClassID, 64, -1, false, false },
3205 { SPERC, SPERCBits, 215, 32, sizeof(SPERCBits), PPC::SPERCRegClassID, 64, 1, true, false },
3206 { VFHRC, VFHRCBits, 324, 32, sizeof(VFHRCBits), PPC::VFHRCRegClassID, 64, -1, false, false },
3207 { VFRC, VFRCBits, 292, 32, sizeof(VFRCBits), PPC::VFRCRegClassID, 64, 1, true, false },
3208 { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, 19, 31, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits), PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClassID, 64, 1, true, false },
3209 { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, 275, 20, sizeof(SPILLTOVSRRC_and_VFRCBits), PPC::SPILLTOVSRRC_and_VFRCRegClassID, 64, 1, true, false },
3210 { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, 136, 14, sizeof(SPILLTOVSRRC_and_F4RCBits), PPC::SPILLTOVSRRC_and_F4RCRegClassID, 64, 1, true, false },
3211 { CTRRC8, CTRRC8Bits, 107, 1, sizeof(CTRRC8Bits), PPC::CTRRC8RegClassID, 64, 1, false, false },
3212 { LR8RC, LR8RCBits, 195, 1, sizeof(LR8RCBits), PPC::LR8RCRegClassID, 64, 1, false, false },
3213 { DMRROWRC, DMRROWRCBits, 651, 64, sizeof(DMRROWRCBits), PPC::DMRROWRCRegClassID, 128, 1, true, false },
3214 { VSRC, VSRCBits, 638, 64, sizeof(VSRCBits), PPC::VSRCRegClassID, 128, 1, true, false },
3215 { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, 503, 34, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3216 { VRRC, VRRCBits, 627, 32, sizeof(VRRCBits), PPC::VRRCRegClassID, 128, 1, true, false },
3217 { VSLRC, VSLRCBits, 340, 32, sizeof(VSLRCBits), PPC::VSLRCRegClassID, 128, 1, true, false },
3218 { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, 470, 20, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3219 { FpRC, FpRCBits, 674, 16, sizeof(FpRCBits), PPC::FpRCRegClassID, 128, 1, true, false },
3220 { G8pRC, G8pRCBits, 668, 16, sizeof(G8pRCBits), PPC::G8pRCRegClassID, 128, 1, true, false },
3221 { G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, 50, 15, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits), PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID, 128, 1, true, false },
3222 { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, 436, 14, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3223 { FpRC_with_sub_fp0_in_SPILLTOVSRRC, FpRC_with_sub_fp0_in_SPILLTOVSRRCBits, 367, 7, sizeof(FpRC_with_sub_fp0_in_SPILLTOVSRRCBits), PPC::FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3224 { DMRROWpRC, DMRROWpRCBits, 693, 32, sizeof(DMRROWpRCBits), PPC::DMRROWpRCRegClassID, 256, 1, true, false },
3225 { VSRpRC, VSRpRCBits, 686, 32, sizeof(VSRpRCBits), PPC::VSRpRCRegClassID, 256, 1, true, false },
3226 { VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, 536, 17, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 256, 1, true, false },
3227 { VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, 158, 16, sizeof(VSRpRC_with_sub_64_in_F4RCBits), PPC::VSRpRC_with_sub_64_in_F4RCRegClassID, 256, 1, true, false },
3228 { VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, 297, 16, sizeof(VSRpRC_with_sub_64_in_VFRCBits), PPC::VSRpRC_with_sub_64_in_VFRCRegClassID, 256, 1, true, false },
3229 { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, 253, 10, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID, 256, 1, true, false },
3230 { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, 114, 7, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID, 256, 1, true, false },
3231 { ACCRC, ACCRCBits, 202, 8, sizeof(ACCRCBits), PPC::ACCRCRegClassID, 512, 1, true, false },
3232 { UACCRC, UACCRCBits, 201, 8, sizeof(UACCRCBits), PPC::UACCRCRegClassID, 512, 1, true, false },
3233 { WACCRC, WACCRCBits, 208, 8, sizeof(WACCRCBits), PPC::WACCRCRegClassID, 512, 1, true, false },
3234 { WACC_HIRC, WACC_HIRCBits, 330, 8, sizeof(WACC_HIRCBits), PPC::WACC_HIRCRegClassID, 512, 1, true, false },
3235 { ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, 402, 4, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3236 { UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, 401, 4, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3237 { ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 572, 3, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3238 { UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 571, 3, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3239 { DMRRC, DMRRCBits, 361, 8, sizeof(DMRRCBits), PPC::DMRRCRegClassID, 1024, 1, true, false },
3240 { DMRpRC, DMRpRCBits, 679, 4, sizeof(DMRpRCBits), PPC::DMRpRCRegClassID, 2048, 1, true, false },
3241};
3242
3243// PPC Dwarf<->LLVM register mappings.
3244extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = {
3245 { 0U, PPC::X0 },
3246 { 1U, PPC::X1 },
3247 { 2U, PPC::X2 },
3248 { 3U, PPC::X3 },
3249 { 4U, PPC::X4 },
3250 { 5U, PPC::X5 },
3251 { 6U, PPC::X6 },
3252 { 7U, PPC::X7 },
3253 { 8U, PPC::X8 },
3254 { 9U, PPC::X9 },
3255 { 10U, PPC::X10 },
3256 { 11U, PPC::X11 },
3257 { 12U, PPC::X12 },
3258 { 13U, PPC::X13 },
3259 { 14U, PPC::X14 },
3260 { 15U, PPC::X15 },
3261 { 16U, PPC::X16 },
3262 { 17U, PPC::X17 },
3263 { 18U, PPC::X18 },
3264 { 19U, PPC::X19 },
3265 { 20U, PPC::X20 },
3266 { 21U, PPC::X21 },
3267 { 22U, PPC::X22 },
3268 { 23U, PPC::X23 },
3269 { 24U, PPC::X24 },
3270 { 25U, PPC::X25 },
3271 { 26U, PPC::X26 },
3272 { 27U, PPC::X27 },
3273 { 28U, PPC::X28 },
3274 { 29U, PPC::X29 },
3275 { 30U, PPC::X30 },
3276 { 31U, PPC::X31 },
3277 { 32U, PPC::F0 },
3278 { 33U, PPC::F1 },
3279 { 34U, PPC::F2 },
3280 { 35U, PPC::F3 },
3281 { 36U, PPC::F4 },
3282 { 37U, PPC::F5 },
3283 { 38U, PPC::F6 },
3284 { 39U, PPC::F7 },
3285 { 40U, PPC::F8 },
3286 { 41U, PPC::F9 },
3287 { 42U, PPC::F10 },
3288 { 43U, PPC::F11 },
3289 { 44U, PPC::F12 },
3290 { 45U, PPC::F13 },
3291 { 46U, PPC::F14 },
3292 { 47U, PPC::F15 },
3293 { 48U, PPC::F16 },
3294 { 49U, PPC::F17 },
3295 { 50U, PPC::F18 },
3296 { 51U, PPC::F19 },
3297 { 52U, PPC::F20 },
3298 { 53U, PPC::F21 },
3299 { 54U, PPC::F22 },
3300 { 55U, PPC::F23 },
3301 { 56U, PPC::F24 },
3302 { 57U, PPC::F25 },
3303 { 58U, PPC::F26 },
3304 { 59U, PPC::F27 },
3305 { 60U, PPC::F28 },
3306 { 61U, PPC::F29 },
3307 { 62U, PPC::F30 },
3308 { 63U, PPC::F31 },
3309 { 65U, PPC::LR8 },
3310 { 66U, PPC::CTR8 },
3311 { 68U, PPC::CR0 },
3312 { 69U, PPC::CR1 },
3313 { 70U, PPC::CR2 },
3314 { 71U, PPC::CR3 },
3315 { 72U, PPC::CR4 },
3316 { 73U, PPC::CR5 },
3317 { 74U, PPC::CR6 },
3318 { 75U, PPC::CR7 },
3319 { 76U, PPC::XER },
3320 { 77U, PPC::VF0 },
3321 { 78U, PPC::VF1 },
3322 { 79U, PPC::VF2 },
3323 { 80U, PPC::VF3 },
3324 { 81U, PPC::VF4 },
3325 { 82U, PPC::VF5 },
3326 { 83U, PPC::VF6 },
3327 { 84U, PPC::VF7 },
3328 { 85U, PPC::VF8 },
3329 { 86U, PPC::VF9 },
3330 { 87U, PPC::VF10 },
3331 { 88U, PPC::VF11 },
3332 { 89U, PPC::VF12 },
3333 { 90U, PPC::VF13 },
3334 { 91U, PPC::VF14 },
3335 { 92U, PPC::VF15 },
3336 { 93U, PPC::VF16 },
3337 { 94U, PPC::VF17 },
3338 { 95U, PPC::VF18 },
3339 { 96U, PPC::VF19 },
3340 { 97U, PPC::VF20 },
3341 { 98U, PPC::VF21 },
3342 { 99U, PPC::VF22 },
3343 { 100U, PPC::VF23 },
3344 { 101U, PPC::VF24 },
3345 { 102U, PPC::VF25 },
3346 { 103U, PPC::VF26 },
3347 { 104U, PPC::VF27 },
3348 { 105U, PPC::VF28 },
3349 { 106U, PPC::VF29 },
3350 { 107U, PPC::VF30 },
3351 { 108U, PPC::VF31 },
3352 { 109U, PPC::VRSAVE },
3353 { 612U, PPC::SPEFSCR },
3354 { 1200U, PPC::S0 },
3355 { 1201U, PPC::S1 },
3356 { 1202U, PPC::S2 },
3357 { 1203U, PPC::S3 },
3358 { 1204U, PPC::S4 },
3359 { 1205U, PPC::S5 },
3360 { 1206U, PPC::S6 },
3361 { 1207U, PPC::S7 },
3362 { 1208U, PPC::S8 },
3363 { 1209U, PPC::S9 },
3364 { 1210U, PPC::S10 },
3365 { 1211U, PPC::S11 },
3366 { 1212U, PPC::S12 },
3367 { 1213U, PPC::S13 },
3368 { 1214U, PPC::S14 },
3369 { 1215U, PPC::S15 },
3370 { 1216U, PPC::S16 },
3371 { 1217U, PPC::S17 },
3372 { 1218U, PPC::S18 },
3373 { 1219U, PPC::S19 },
3374 { 1220U, PPC::S20 },
3375 { 1221U, PPC::S21 },
3376 { 1222U, PPC::S22 },
3377 { 1223U, PPC::S23 },
3378 { 1224U, PPC::S24 },
3379 { 1225U, PPC::S25 },
3380 { 1226U, PPC::S26 },
3381 { 1227U, PPC::S27 },
3382 { 1228U, PPC::S28 },
3383 { 1229U, PPC::S29 },
3384 { 1230U, PPC::S30 },
3385 { 1231U, PPC::S31 },
3386};
3387extern const unsigned PPCDwarfFlavour0Dwarf2LSize = std::size(PPCDwarfFlavour0Dwarf2L);
3388
3389extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
3390 { 0U, PPC::R0 },
3391 { 1U, PPC::R1 },
3392 { 2U, PPC::R2 },
3393 { 3U, PPC::R3 },
3394 { 4U, PPC::R4 },
3395 { 5U, PPC::R5 },
3396 { 6U, PPC::R6 },
3397 { 7U, PPC::R7 },
3398 { 8U, PPC::R8 },
3399 { 9U, PPC::R9 },
3400 { 10U, PPC::R10 },
3401 { 11U, PPC::R11 },
3402 { 12U, PPC::R12 },
3403 { 13U, PPC::R13 },
3404 { 14U, PPC::R14 },
3405 { 15U, PPC::R15 },
3406 { 16U, PPC::R16 },
3407 { 17U, PPC::R17 },
3408 { 18U, PPC::R18 },
3409 { 19U, PPC::R19 },
3410 { 20U, PPC::R20 },
3411 { 21U, PPC::R21 },
3412 { 22U, PPC::R22 },
3413 { 23U, PPC::R23 },
3414 { 24U, PPC::R24 },
3415 { 25U, PPC::R25 },
3416 { 26U, PPC::R26 },
3417 { 27U, PPC::R27 },
3418 { 28U, PPC::R28 },
3419 { 29U, PPC::R29 },
3420 { 30U, PPC::R30 },
3421 { 31U, PPC::R31 },
3422 { 32U, PPC::F0 },
3423 { 33U, PPC::F1 },
3424 { 34U, PPC::F2 },
3425 { 35U, PPC::F3 },
3426 { 36U, PPC::F4 },
3427 { 37U, PPC::F5 },
3428 { 38U, PPC::F6 },
3429 { 39U, PPC::F7 },
3430 { 40U, PPC::F8 },
3431 { 41U, PPC::F9 },
3432 { 42U, PPC::F10 },
3433 { 43U, PPC::F11 },
3434 { 44U, PPC::F12 },
3435 { 45U, PPC::F13 },
3436 { 46U, PPC::F14 },
3437 { 47U, PPC::F15 },
3438 { 48U, PPC::F16 },
3439 { 49U, PPC::F17 },
3440 { 50U, PPC::F18 },
3441 { 51U, PPC::F19 },
3442 { 52U, PPC::F20 },
3443 { 53U, PPC::F21 },
3444 { 54U, PPC::F22 },
3445 { 55U, PPC::F23 },
3446 { 56U, PPC::F24 },
3447 { 57U, PPC::F25 },
3448 { 58U, PPC::F26 },
3449 { 59U, PPC::F27 },
3450 { 60U, PPC::F28 },
3451 { 61U, PPC::F29 },
3452 { 62U, PPC::F30 },
3453 { 63U, PPC::F31 },
3454 { 65U, PPC::LR },
3455 { 66U, PPC::CTR },
3456 { 68U, PPC::CR0 },
3457 { 69U, PPC::CR1 },
3458 { 70U, PPC::CR2 },
3459 { 71U, PPC::CR3 },
3460 { 72U, PPC::CR4 },
3461 { 73U, PPC::CR5 },
3462 { 74U, PPC::CR6 },
3463 { 75U, PPC::CR7 },
3464 { 77U, PPC::VF0 },
3465 { 78U, PPC::VF1 },
3466 { 79U, PPC::VF2 },
3467 { 80U, PPC::VF3 },
3468 { 81U, PPC::VF4 },
3469 { 82U, PPC::VF5 },
3470 { 83U, PPC::VF6 },
3471 { 84U, PPC::VF7 },
3472 { 85U, PPC::VF8 },
3473 { 86U, PPC::VF9 },
3474 { 87U, PPC::VF10 },
3475 { 88U, PPC::VF11 },
3476 { 89U, PPC::VF12 },
3477 { 90U, PPC::VF13 },
3478 { 91U, PPC::VF14 },
3479 { 92U, PPC::VF15 },
3480 { 93U, PPC::VF16 },
3481 { 94U, PPC::VF17 },
3482 { 95U, PPC::VF18 },
3483 { 96U, PPC::VF19 },
3484 { 97U, PPC::VF20 },
3485 { 98U, PPC::VF21 },
3486 { 99U, PPC::VF22 },
3487 { 100U, PPC::VF23 },
3488 { 101U, PPC::VF24 },
3489 { 102U, PPC::VF25 },
3490 { 103U, PPC::VF26 },
3491 { 104U, PPC::VF27 },
3492 { 105U, PPC::VF28 },
3493 { 106U, PPC::VF29 },
3494 { 107U, PPC::VF30 },
3495 { 108U, PPC::VF31 },
3496 { 112U, PPC::SPEFSCR },
3497 { 1200U, PPC::S0 },
3498 { 1201U, PPC::S1 },
3499 { 1202U, PPC::S2 },
3500 { 1203U, PPC::S3 },
3501 { 1204U, PPC::S4 },
3502 { 1205U, PPC::S5 },
3503 { 1206U, PPC::S6 },
3504 { 1207U, PPC::S7 },
3505 { 1208U, PPC::S8 },
3506 { 1209U, PPC::S9 },
3507 { 1210U, PPC::S10 },
3508 { 1211U, PPC::S11 },
3509 { 1212U, PPC::S12 },
3510 { 1213U, PPC::S13 },
3511 { 1214U, PPC::S14 },
3512 { 1215U, PPC::S15 },
3513 { 1216U, PPC::S16 },
3514 { 1217U, PPC::S17 },
3515 { 1218U, PPC::S18 },
3516 { 1219U, PPC::S19 },
3517 { 1220U, PPC::S20 },
3518 { 1221U, PPC::S21 },
3519 { 1222U, PPC::S22 },
3520 { 1223U, PPC::S23 },
3521 { 1224U, PPC::S24 },
3522 { 1225U, PPC::S25 },
3523 { 1226U, PPC::S26 },
3524 { 1227U, PPC::S27 },
3525 { 1228U, PPC::S28 },
3526 { 1229U, PPC::S29 },
3527 { 1230U, PPC::S30 },
3528 { 1231U, PPC::S31 },
3529};
3530extern const unsigned PPCDwarfFlavour1Dwarf2LSize = std::size(PPCDwarfFlavour1Dwarf2L);
3531
3532extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = {
3533 { 0U, PPC::X0 },
3534 { 1U, PPC::X1 },
3535 { 2U, PPC::X2 },
3536 { 3U, PPC::X3 },
3537 { 4U, PPC::X4 },
3538 { 5U, PPC::X5 },
3539 { 6U, PPC::X6 },
3540 { 7U, PPC::X7 },
3541 { 8U, PPC::X8 },
3542 { 9U, PPC::X9 },
3543 { 10U, PPC::X10 },
3544 { 11U, PPC::X11 },
3545 { 12U, PPC::X12 },
3546 { 13U, PPC::X13 },
3547 { 14U, PPC::X14 },
3548 { 15U, PPC::X15 },
3549 { 16U, PPC::X16 },
3550 { 17U, PPC::X17 },
3551 { 18U, PPC::X18 },
3552 { 19U, PPC::X19 },
3553 { 20U, PPC::X20 },
3554 { 21U, PPC::X21 },
3555 { 22U, PPC::X22 },
3556 { 23U, PPC::X23 },
3557 { 24U, PPC::X24 },
3558 { 25U, PPC::X25 },
3559 { 26U, PPC::X26 },
3560 { 27U, PPC::X27 },
3561 { 28U, PPC::X28 },
3562 { 29U, PPC::X29 },
3563 { 30U, PPC::X30 },
3564 { 31U, PPC::X31 },
3565 { 32U, PPC::F0 },
3566 { 33U, PPC::F1 },
3567 { 34U, PPC::F2 },
3568 { 35U, PPC::F3 },
3569 { 36U, PPC::F4 },
3570 { 37U, PPC::F5 },
3571 { 38U, PPC::F6 },
3572 { 39U, PPC::F7 },
3573 { 40U, PPC::F8 },
3574 { 41U, PPC::F9 },
3575 { 42U, PPC::F10 },
3576 { 43U, PPC::F11 },
3577 { 44U, PPC::F12 },
3578 { 45U, PPC::F13 },
3579 { 46U, PPC::F14 },
3580 { 47U, PPC::F15 },
3581 { 48U, PPC::F16 },
3582 { 49U, PPC::F17 },
3583 { 50U, PPC::F18 },
3584 { 51U, PPC::F19 },
3585 { 52U, PPC::F20 },
3586 { 53U, PPC::F21 },
3587 { 54U, PPC::F22 },
3588 { 55U, PPC::F23 },
3589 { 56U, PPC::F24 },
3590 { 57U, PPC::F25 },
3591 { 58U, PPC::F26 },
3592 { 59U, PPC::F27 },
3593 { 60U, PPC::F28 },
3594 { 61U, PPC::F29 },
3595 { 62U, PPC::F30 },
3596 { 63U, PPC::F31 },
3597 { 65U, PPC::LR8 },
3598 { 66U, PPC::CTR8 },
3599 { 68U, PPC::CR0 },
3600 { 69U, PPC::CR1 },
3601 { 70U, PPC::CR2 },
3602 { 71U, PPC::CR3 },
3603 { 72U, PPC::CR4 },
3604 { 73U, PPC::CR5 },
3605 { 74U, PPC::CR6 },
3606 { 75U, PPC::CR7 },
3607 { 76U, PPC::XER },
3608 { 77U, PPC::VF0 },
3609 { 78U, PPC::VF1 },
3610 { 79U, PPC::VF2 },
3611 { 80U, PPC::VF3 },
3612 { 81U, PPC::VF4 },
3613 { 82U, PPC::VF5 },
3614 { 83U, PPC::VF6 },
3615 { 84U, PPC::VF7 },
3616 { 85U, PPC::VF8 },
3617 { 86U, PPC::VF9 },
3618 { 87U, PPC::VF10 },
3619 { 88U, PPC::VF11 },
3620 { 89U, PPC::VF12 },
3621 { 90U, PPC::VF13 },
3622 { 91U, PPC::VF14 },
3623 { 92U, PPC::VF15 },
3624 { 93U, PPC::VF16 },
3625 { 94U, PPC::VF17 },
3626 { 95U, PPC::VF18 },
3627 { 96U, PPC::VF19 },
3628 { 97U, PPC::VF20 },
3629 { 98U, PPC::VF21 },
3630 { 99U, PPC::VF22 },
3631 { 100U, PPC::VF23 },
3632 { 101U, PPC::VF24 },
3633 { 102U, PPC::VF25 },
3634 { 103U, PPC::VF26 },
3635 { 104U, PPC::VF27 },
3636 { 105U, PPC::VF28 },
3637 { 106U, PPC::VF29 },
3638 { 107U, PPC::VF30 },
3639 { 108U, PPC::VF31 },
3640 { 109U, PPC::VRSAVE },
3641 { 612U, PPC::SPEFSCR },
3642 { 1200U, PPC::S0 },
3643 { 1201U, PPC::S1 },
3644 { 1202U, PPC::S2 },
3645 { 1203U, PPC::S3 },
3646 { 1204U, PPC::S4 },
3647 { 1205U, PPC::S5 },
3648 { 1206U, PPC::S6 },
3649 { 1207U, PPC::S7 },
3650 { 1208U, PPC::S8 },
3651 { 1209U, PPC::S9 },
3652 { 1210U, PPC::S10 },
3653 { 1211U, PPC::S11 },
3654 { 1212U, PPC::S12 },
3655 { 1213U, PPC::S13 },
3656 { 1214U, PPC::S14 },
3657 { 1215U, PPC::S15 },
3658 { 1216U, PPC::S16 },
3659 { 1217U, PPC::S17 },
3660 { 1218U, PPC::S18 },
3661 { 1219U, PPC::S19 },
3662 { 1220U, PPC::S20 },
3663 { 1221U, PPC::S21 },
3664 { 1222U, PPC::S22 },
3665 { 1223U, PPC::S23 },
3666 { 1224U, PPC::S24 },
3667 { 1225U, PPC::S25 },
3668 { 1226U, PPC::S26 },
3669 { 1227U, PPC::S27 },
3670 { 1228U, PPC::S28 },
3671 { 1229U, PPC::S29 },
3672 { 1230U, PPC::S30 },
3673 { 1231U, PPC::S31 },
3674};
3675extern const unsigned PPCEHFlavour0Dwarf2LSize = std::size(PPCEHFlavour0Dwarf2L);
3676
3677extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = {
3678 { 0U, PPC::R0 },
3679 { 1U, PPC::R1 },
3680 { 2U, PPC::R2 },
3681 { 3U, PPC::R3 },
3682 { 4U, PPC::R4 },
3683 { 5U, PPC::R5 },
3684 { 6U, PPC::R6 },
3685 { 7U, PPC::R7 },
3686 { 8U, PPC::R8 },
3687 { 9U, PPC::R9 },
3688 { 10U, PPC::R10 },
3689 { 11U, PPC::R11 },
3690 { 12U, PPC::R12 },
3691 { 13U, PPC::R13 },
3692 { 14U, PPC::R14 },
3693 { 15U, PPC::R15 },
3694 { 16U, PPC::R16 },
3695 { 17U, PPC::R17 },
3696 { 18U, PPC::R18 },
3697 { 19U, PPC::R19 },
3698 { 20U, PPC::R20 },
3699 { 21U, PPC::R21 },
3700 { 22U, PPC::R22 },
3701 { 23U, PPC::R23 },
3702 { 24U, PPC::R24 },
3703 { 25U, PPC::R25 },
3704 { 26U, PPC::R26 },
3705 { 27U, PPC::R27 },
3706 { 28U, PPC::R28 },
3707 { 29U, PPC::R29 },
3708 { 30U, PPC::R30 },
3709 { 31U, PPC::R31 },
3710 { 32U, PPC::F0 },
3711 { 33U, PPC::F1 },
3712 { 34U, PPC::F2 },
3713 { 35U, PPC::F3 },
3714 { 36U, PPC::F4 },
3715 { 37U, PPC::F5 },
3716 { 38U, PPC::F6 },
3717 { 39U, PPC::F7 },
3718 { 40U, PPC::F8 },
3719 { 41U, PPC::F9 },
3720 { 42U, PPC::F10 },
3721 { 43U, PPC::F11 },
3722 { 44U, PPC::F12 },
3723 { 45U, PPC::F13 },
3724 { 46U, PPC::F14 },
3725 { 47U, PPC::F15 },
3726 { 48U, PPC::F16 },
3727 { 49U, PPC::F17 },
3728 { 50U, PPC::F18 },
3729 { 51U, PPC::F19 },
3730 { 52U, PPC::F20 },
3731 { 53U, PPC::F21 },
3732 { 54U, PPC::F22 },
3733 { 55U, PPC::F23 },
3734 { 56U, PPC::F24 },
3735 { 57U, PPC::F25 },
3736 { 58U, PPC::F26 },
3737 { 59U, PPC::F27 },
3738 { 60U, PPC::F28 },
3739 { 61U, PPC::F29 },
3740 { 62U, PPC::F30 },
3741 { 63U, PPC::F31 },
3742 { 65U, PPC::LR },
3743 { 66U, PPC::CTR },
3744 { 68U, PPC::CR0 },
3745 { 69U, PPC::CR1 },
3746 { 70U, PPC::CR2 },
3747 { 71U, PPC::CR3 },
3748 { 72U, PPC::CR4 },
3749 { 73U, PPC::CR5 },
3750 { 74U, PPC::CR6 },
3751 { 75U, PPC::CR7 },
3752 { 77U, PPC::VF0 },
3753 { 78U, PPC::VF1 },
3754 { 79U, PPC::VF2 },
3755 { 80U, PPC::VF3 },
3756 { 81U, PPC::VF4 },
3757 { 82U, PPC::VF5 },
3758 { 83U, PPC::VF6 },
3759 { 84U, PPC::VF7 },
3760 { 85U, PPC::VF8 },
3761 { 86U, PPC::VF9 },
3762 { 87U, PPC::VF10 },
3763 { 88U, PPC::VF11 },
3764 { 89U, PPC::VF12 },
3765 { 90U, PPC::VF13 },
3766 { 91U, PPC::VF14 },
3767 { 92U, PPC::VF15 },
3768 { 93U, PPC::VF16 },
3769 { 94U, PPC::VF17 },
3770 { 95U, PPC::VF18 },
3771 { 96U, PPC::VF19 },
3772 { 97U, PPC::VF20 },
3773 { 98U, PPC::VF21 },
3774 { 99U, PPC::VF22 },
3775 { 100U, PPC::VF23 },
3776 { 101U, PPC::VF24 },
3777 { 102U, PPC::VF25 },
3778 { 103U, PPC::VF26 },
3779 { 104U, PPC::VF27 },
3780 { 105U, PPC::VF28 },
3781 { 106U, PPC::VF29 },
3782 { 107U, PPC::VF30 },
3783 { 108U, PPC::VF31 },
3784 { 112U, PPC::SPEFSCR },
3785 { 1200U, PPC::S0 },
3786 { 1201U, PPC::S1 },
3787 { 1202U, PPC::S2 },
3788 { 1203U, PPC::S3 },
3789 { 1204U, PPC::S4 },
3790 { 1205U, PPC::S5 },
3791 { 1206U, PPC::S6 },
3792 { 1207U, PPC::S7 },
3793 { 1208U, PPC::S8 },
3794 { 1209U, PPC::S9 },
3795 { 1210U, PPC::S10 },
3796 { 1211U, PPC::S11 },
3797 { 1212U, PPC::S12 },
3798 { 1213U, PPC::S13 },
3799 { 1214U, PPC::S14 },
3800 { 1215U, PPC::S15 },
3801 { 1216U, PPC::S16 },
3802 { 1217U, PPC::S17 },
3803 { 1218U, PPC::S18 },
3804 { 1219U, PPC::S19 },
3805 { 1220U, PPC::S20 },
3806 { 1221U, PPC::S21 },
3807 { 1222U, PPC::S22 },
3808 { 1223U, PPC::S23 },
3809 { 1224U, PPC::S24 },
3810 { 1225U, PPC::S25 },
3811 { 1226U, PPC::S26 },
3812 { 1227U, PPC::S27 },
3813 { 1228U, PPC::S28 },
3814 { 1229U, PPC::S29 },
3815 { 1230U, PPC::S30 },
3816 { 1231U, PPC::S31 },
3817};
3818extern const unsigned PPCEHFlavour1Dwarf2LSize = std::size(PPCEHFlavour1Dwarf2L);
3819
3820extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = {
3821 { PPC::CARRY, 76U },
3822 { PPC::CTR, -2U },
3823 { PPC::LR, -2U },
3824 { PPC::SPEFSCR, 612U },
3825 { PPC::VRSAVE, 109U },
3826 { PPC::XER, 76U },
3827 { PPC::ZERO, -2U },
3828 { PPC::CR0, 68U },
3829 { PPC::CR1, 69U },
3830 { PPC::CR2, 70U },
3831 { PPC::CR3, 71U },
3832 { PPC::CR4, 72U },
3833 { PPC::CR5, 73U },
3834 { PPC::CR6, 74U },
3835 { PPC::CR7, 75U },
3836 { PPC::CTR8, 66U },
3837 { PPC::F0, 32U },
3838 { PPC::F1, 33U },
3839 { PPC::F2, 34U },
3840 { PPC::F3, 35U },
3841 { PPC::F4, 36U },
3842 { PPC::F5, 37U },
3843 { PPC::F6, 38U },
3844 { PPC::F7, 39U },
3845 { PPC::F8, 40U },
3846 { PPC::F9, 41U },
3847 { PPC::F10, 42U },
3848 { PPC::F11, 43U },
3849 { PPC::F12, 44U },
3850 { PPC::F13, 45U },
3851 { PPC::F14, 46U },
3852 { PPC::F15, 47U },
3853 { PPC::F16, 48U },
3854 { PPC::F17, 49U },
3855 { PPC::F18, 50U },
3856 { PPC::F19, 51U },
3857 { PPC::F20, 52U },
3858 { PPC::F21, 53U },
3859 { PPC::F22, 54U },
3860 { PPC::F23, 55U },
3861 { PPC::F24, 56U },
3862 { PPC::F25, 57U },
3863 { PPC::F26, 58U },
3864 { PPC::F27, 59U },
3865 { PPC::F28, 60U },
3866 { PPC::F29, 61U },
3867 { PPC::F30, 62U },
3868 { PPC::F31, 63U },
3869 { PPC::LR8, 65U },
3870 { PPC::R0, -2U },
3871 { PPC::R1, -2U },
3872 { PPC::R2, -2U },
3873 { PPC::R3, -2U },
3874 { PPC::R4, -2U },
3875 { PPC::R5, -2U },
3876 { PPC::R6, -2U },
3877 { PPC::R7, -2U },
3878 { PPC::R8, -2U },
3879 { PPC::R9, -2U },
3880 { PPC::R10, -2U },
3881 { PPC::R11, -2U },
3882 { PPC::R12, -2U },
3883 { PPC::R13, -2U },
3884 { PPC::R14, -2U },
3885 { PPC::R15, -2U },
3886 { PPC::R16, -2U },
3887 { PPC::R17, -2U },
3888 { PPC::R18, -2U },
3889 { PPC::R19, -2U },
3890 { PPC::R20, -2U },
3891 { PPC::R21, -2U },
3892 { PPC::R22, -2U },
3893 { PPC::R23, -2U },
3894 { PPC::R24, -2U },
3895 { PPC::R25, -2U },
3896 { PPC::R26, -2U },
3897 { PPC::R27, -2U },
3898 { PPC::R28, -2U },
3899 { PPC::R29, -2U },
3900 { PPC::R30, -2U },
3901 { PPC::R31, -2U },
3902 { PPC::S0, 1200U },
3903 { PPC::S1, 1201U },
3904 { PPC::S2, 1202U },
3905 { PPC::S3, 1203U },
3906 { PPC::S4, 1204U },
3907 { PPC::S5, 1205U },
3908 { PPC::S6, 1206U },
3909 { PPC::S7, 1207U },
3910 { PPC::S8, 1208U },
3911 { PPC::S9, 1209U },
3912 { PPC::S10, 1210U },
3913 { PPC::S11, 1211U },
3914 { PPC::S12, 1212U },
3915 { PPC::S13, 1213U },
3916 { PPC::S14, 1214U },
3917 { PPC::S15, 1215U },
3918 { PPC::S16, 1216U },
3919 { PPC::S17, 1217U },
3920 { PPC::S18, 1218U },
3921 { PPC::S19, 1219U },
3922 { PPC::S20, 1220U },
3923 { PPC::S21, 1221U },
3924 { PPC::S22, 1222U },
3925 { PPC::S23, 1223U },
3926 { PPC::S24, 1224U },
3927 { PPC::S25, 1225U },
3928 { PPC::S26, 1226U },
3929 { PPC::S27, 1227U },
3930 { PPC::S28, 1228U },
3931 { PPC::S29, 1229U },
3932 { PPC::S30, 1230U },
3933 { PPC::S31, 1231U },
3934 { PPC::V0, 77U },
3935 { PPC::V1, 78U },
3936 { PPC::V2, 79U },
3937 { PPC::V3, 80U },
3938 { PPC::V4, 81U },
3939 { PPC::V5, 82U },
3940 { PPC::V6, 83U },
3941 { PPC::V7, 84U },
3942 { PPC::V8, 85U },
3943 { PPC::V9, 86U },
3944 { PPC::V10, 87U },
3945 { PPC::V11, 88U },
3946 { PPC::V12, 89U },
3947 { PPC::V13, 90U },
3948 { PPC::V14, 91U },
3949 { PPC::V15, 92U },
3950 { PPC::V16, 93U },
3951 { PPC::V17, 94U },
3952 { PPC::V18, 95U },
3953 { PPC::V19, 96U },
3954 { PPC::V20, 97U },
3955 { PPC::V21, 98U },
3956 { PPC::V22, 99U },
3957 { PPC::V23, 100U },
3958 { PPC::V24, 101U },
3959 { PPC::V25, 102U },
3960 { PPC::V26, 103U },
3961 { PPC::V27, 104U },
3962 { PPC::V28, 105U },
3963 { PPC::V29, 106U },
3964 { PPC::V30, 107U },
3965 { PPC::V31, 108U },
3966 { PPC::VF0, 77U },
3967 { PPC::VF1, 78U },
3968 { PPC::VF2, 79U },
3969 { PPC::VF3, 80U },
3970 { PPC::VF4, 81U },
3971 { PPC::VF5, 82U },
3972 { PPC::VF6, 83U },
3973 { PPC::VF7, 84U },
3974 { PPC::VF8, 85U },
3975 { PPC::VF9, 86U },
3976 { PPC::VF10, 87U },
3977 { PPC::VF11, 88U },
3978 { PPC::VF12, 89U },
3979 { PPC::VF13, 90U },
3980 { PPC::VF14, 91U },
3981 { PPC::VF15, 92U },
3982 { PPC::VF16, 93U },
3983 { PPC::VF17, 94U },
3984 { PPC::VF18, 95U },
3985 { PPC::VF19, 96U },
3986 { PPC::VF20, 97U },
3987 { PPC::VF21, 98U },
3988 { PPC::VF22, 99U },
3989 { PPC::VF23, 100U },
3990 { PPC::VF24, 101U },
3991 { PPC::VF25, 102U },
3992 { PPC::VF26, 103U },
3993 { PPC::VF27, 104U },
3994 { PPC::VF28, 105U },
3995 { PPC::VF29, 106U },
3996 { PPC::VF30, 107U },
3997 { PPC::VF31, 108U },
3998 { PPC::VSL0, 32U },
3999 { PPC::VSL1, 33U },
4000 { PPC::VSL2, 34U },
4001 { PPC::VSL3, 35U },
4002 { PPC::VSL4, 36U },
4003 { PPC::VSL5, 37U },
4004 { PPC::VSL6, 38U },
4005 { PPC::VSL7, 39U },
4006 { PPC::VSL8, 40U },
4007 { PPC::VSL9, 41U },
4008 { PPC::VSL10, 42U },
4009 { PPC::VSL11, 43U },
4010 { PPC::VSL12, 44U },
4011 { PPC::VSL13, 45U },
4012 { PPC::VSL14, 46U },
4013 { PPC::VSL15, 47U },
4014 { PPC::VSL16, 48U },
4015 { PPC::VSL17, 49U },
4016 { PPC::VSL18, 50U },
4017 { PPC::VSL19, 51U },
4018 { PPC::VSL20, 52U },
4019 { PPC::VSL21, 53U },
4020 { PPC::VSL22, 54U },
4021 { PPC::VSL23, 55U },
4022 { PPC::VSL24, 56U },
4023 { PPC::VSL25, 57U },
4024 { PPC::VSL26, 58U },
4025 { PPC::VSL27, 59U },
4026 { PPC::VSL28, 60U },
4027 { PPC::VSL29, 61U },
4028 { PPC::VSL30, 62U },
4029 { PPC::VSL31, 63U },
4030 { PPC::VSRp16, 77U },
4031 { PPC::VSRp17, 79U },
4032 { PPC::VSRp18, 81U },
4033 { PPC::VSRp19, 83U },
4034 { PPC::VSRp20, 85U },
4035 { PPC::VSRp21, 87U },
4036 { PPC::VSRp22, 89U },
4037 { PPC::VSRp23, 91U },
4038 { PPC::VSRp24, 93U },
4039 { PPC::VSRp25, 95U },
4040 { PPC::VSRp26, 97U },
4041 { PPC::VSRp27, 99U },
4042 { PPC::VSRp28, 101U },
4043 { PPC::VSRp29, 103U },
4044 { PPC::VSRp30, 105U },
4045 { PPC::VSRp31, 107U },
4046 { PPC::X0, 0U },
4047 { PPC::X1, 1U },
4048 { PPC::X2, 2U },
4049 { PPC::X3, 3U },
4050 { PPC::X4, 4U },
4051 { PPC::X5, 5U },
4052 { PPC::X6, 6U },
4053 { PPC::X7, 7U },
4054 { PPC::X8, 8U },
4055 { PPC::X9, 9U },
4056 { PPC::X10, 10U },
4057 { PPC::X11, 11U },
4058 { PPC::X12, 12U },
4059 { PPC::X13, 13U },
4060 { PPC::X14, 14U },
4061 { PPC::X15, 15U },
4062 { PPC::X16, 16U },
4063 { PPC::X17, 17U },
4064 { PPC::X18, 18U },
4065 { PPC::X19, 19U },
4066 { PPC::X20, 20U },
4067 { PPC::X21, 21U },
4068 { PPC::X22, 22U },
4069 { PPC::X23, 23U },
4070 { PPC::X24, 24U },
4071 { PPC::X25, 25U },
4072 { PPC::X26, 26U },
4073 { PPC::X27, 27U },
4074 { PPC::X28, 28U },
4075 { PPC::X29, 29U },
4076 { PPC::X30, 30U },
4077 { PPC::X31, 31U },
4078 { PPC::ZERO8, 0U },
4079};
4080extern const unsigned PPCDwarfFlavour0L2DwarfSize = std::size(PPCDwarfFlavour0L2Dwarf);
4081
4082extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = {
4083 { PPC::CTR, 66U },
4084 { PPC::LR, 65U },
4085 { PPC::SPEFSCR, 112U },
4086 { PPC::ZERO, 0U },
4087 { PPC::CR0, 68U },
4088 { PPC::CR1, 69U },
4089 { PPC::CR2, 70U },
4090 { PPC::CR3, 71U },
4091 { PPC::CR4, 72U },
4092 { PPC::CR5, 73U },
4093 { PPC::CR6, 74U },
4094 { PPC::CR7, 75U },
4095 { PPC::CTR8, -2U },
4096 { PPC::F0, 32U },
4097 { PPC::F1, 33U },
4098 { PPC::F2, 34U },
4099 { PPC::F3, 35U },
4100 { PPC::F4, 36U },
4101 { PPC::F5, 37U },
4102 { PPC::F6, 38U },
4103 { PPC::F7, 39U },
4104 { PPC::F8, 40U },
4105 { PPC::F9, 41U },
4106 { PPC::F10, 42U },
4107 { PPC::F11, 43U },
4108 { PPC::F12, 44U },
4109 { PPC::F13, 45U },
4110 { PPC::F14, 46U },
4111 { PPC::F15, 47U },
4112 { PPC::F16, 48U },
4113 { PPC::F17, 49U },
4114 { PPC::F18, 50U },
4115 { PPC::F19, 51U },
4116 { PPC::F20, 52U },
4117 { PPC::F21, 53U },
4118 { PPC::F22, 54U },
4119 { PPC::F23, 55U },
4120 { PPC::F24, 56U },
4121 { PPC::F25, 57U },
4122 { PPC::F26, 58U },
4123 { PPC::F27, 59U },
4124 { PPC::F28, 60U },
4125 { PPC::F29, 61U },
4126 { PPC::F30, 62U },
4127 { PPC::F31, 63U },
4128 { PPC::LR8, -2U },
4129 { PPC::R0, 0U },
4130 { PPC::R1, 1U },
4131 { PPC::R2, 2U },
4132 { PPC::R3, 3U },
4133 { PPC::R4, 4U },
4134 { PPC::R5, 5U },
4135 { PPC::R6, 6U },
4136 { PPC::R7, 7U },
4137 { PPC::R8, 8U },
4138 { PPC::R9, 9U },
4139 { PPC::R10, 10U },
4140 { PPC::R11, 11U },
4141 { PPC::R12, 12U },
4142 { PPC::R13, 13U },
4143 { PPC::R14, 14U },
4144 { PPC::R15, 15U },
4145 { PPC::R16, 16U },
4146 { PPC::R17, 17U },
4147 { PPC::R18, 18U },
4148 { PPC::R19, 19U },
4149 { PPC::R20, 20U },
4150 { PPC::R21, 21U },
4151 { PPC::R22, 22U },
4152 { PPC::R23, 23U },
4153 { PPC::R24, 24U },
4154 { PPC::R25, 25U },
4155 { PPC::R26, 26U },
4156 { PPC::R27, 27U },
4157 { PPC::R28, 28U },
4158 { PPC::R29, 29U },
4159 { PPC::R30, 30U },
4160 { PPC::R31, 31U },
4161 { PPC::S0, 1200U },
4162 { PPC::S1, 1201U },
4163 { PPC::S2, 1202U },
4164 { PPC::S3, 1203U },
4165 { PPC::S4, 1204U },
4166 { PPC::S5, 1205U },
4167 { PPC::S6, 1206U },
4168 { PPC::S7, 1207U },
4169 { PPC::S8, 1208U },
4170 { PPC::S9, 1209U },
4171 { PPC::S10, 1210U },
4172 { PPC::S11, 1211U },
4173 { PPC::S12, 1212U },
4174 { PPC::S13, 1213U },
4175 { PPC::S14, 1214U },
4176 { PPC::S15, 1215U },
4177 { PPC::S16, 1216U },
4178 { PPC::S17, 1217U },
4179 { PPC::S18, 1218U },
4180 { PPC::S19, 1219U },
4181 { PPC::S20, 1220U },
4182 { PPC::S21, 1221U },
4183 { PPC::S22, 1222U },
4184 { PPC::S23, 1223U },
4185 { PPC::S24, 1224U },
4186 { PPC::S25, 1225U },
4187 { PPC::S26, 1226U },
4188 { PPC::S27, 1227U },
4189 { PPC::S28, 1228U },
4190 { PPC::S29, 1229U },
4191 { PPC::S30, 1230U },
4192 { PPC::S31, 1231U },
4193 { PPC::V0, 77U },
4194 { PPC::V1, 78U },
4195 { PPC::V2, 79U },
4196 { PPC::V3, 80U },
4197 { PPC::V4, 81U },
4198 { PPC::V5, 82U },
4199 { PPC::V6, 83U },
4200 { PPC::V7, 84U },
4201 { PPC::V8, 85U },
4202 { PPC::V9, 86U },
4203 { PPC::V10, 87U },
4204 { PPC::V11, 88U },
4205 { PPC::V12, 89U },
4206 { PPC::V13, 90U },
4207 { PPC::V14, 91U },
4208 { PPC::V15, 92U },
4209 { PPC::V16, 93U },
4210 { PPC::V17, 94U },
4211 { PPC::V18, 95U },
4212 { PPC::V19, 96U },
4213 { PPC::V20, 97U },
4214 { PPC::V21, 98U },
4215 { PPC::V22, 99U },
4216 { PPC::V23, 100U },
4217 { PPC::V24, 101U },
4218 { PPC::V25, 102U },
4219 { PPC::V26, 103U },
4220 { PPC::V27, 104U },
4221 { PPC::V28, 105U },
4222 { PPC::V29, 106U },
4223 { PPC::V30, 107U },
4224 { PPC::V31, 108U },
4225 { PPC::VF0, 77U },
4226 { PPC::VF1, 78U },
4227 { PPC::VF2, 79U },
4228 { PPC::VF3, 80U },
4229 { PPC::VF4, 81U },
4230 { PPC::VF5, 82U },
4231 { PPC::VF6, 83U },
4232 { PPC::VF7, 84U },
4233 { PPC::VF8, 85U },
4234 { PPC::VF9, 86U },
4235 { PPC::VF10, 87U },
4236 { PPC::VF11, 88U },
4237 { PPC::VF12, 89U },
4238 { PPC::VF13, 90U },
4239 { PPC::VF14, 91U },
4240 { PPC::VF15, 92U },
4241 { PPC::VF16, 93U },
4242 { PPC::VF17, 94U },
4243 { PPC::VF18, 95U },
4244 { PPC::VF19, 96U },
4245 { PPC::VF20, 97U },
4246 { PPC::VF21, 98U },
4247 { PPC::VF22, 99U },
4248 { PPC::VF23, 100U },
4249 { PPC::VF24, 101U },
4250 { PPC::VF25, 102U },
4251 { PPC::VF26, 103U },
4252 { PPC::VF27, 104U },
4253 { PPC::VF28, 105U },
4254 { PPC::VF29, 106U },
4255 { PPC::VF30, 107U },
4256 { PPC::VF31, 108U },
4257 { PPC::VSL0, 32U },
4258 { PPC::VSL1, 33U },
4259 { PPC::VSL2, 34U },
4260 { PPC::VSL3, 35U },
4261 { PPC::VSL4, 36U },
4262 { PPC::VSL5, 37U },
4263 { PPC::VSL6, 38U },
4264 { PPC::VSL7, 39U },
4265 { PPC::VSL8, 40U },
4266 { PPC::VSL9, 41U },
4267 { PPC::VSL10, 42U },
4268 { PPC::VSL11, 43U },
4269 { PPC::VSL12, 44U },
4270 { PPC::VSL13, 45U },
4271 { PPC::VSL14, 46U },
4272 { PPC::VSL15, 47U },
4273 { PPC::VSL16, 48U },
4274 { PPC::VSL17, 49U },
4275 { PPC::VSL18, 50U },
4276 { PPC::VSL19, 51U },
4277 { PPC::VSL20, 52U },
4278 { PPC::VSL21, 53U },
4279 { PPC::VSL22, 54U },
4280 { PPC::VSL23, 55U },
4281 { PPC::VSL24, 56U },
4282 { PPC::VSL25, 57U },
4283 { PPC::VSL26, 58U },
4284 { PPC::VSL27, 59U },
4285 { PPC::VSL28, 60U },
4286 { PPC::VSL29, 61U },
4287 { PPC::VSL30, 62U },
4288 { PPC::VSL31, 63U },
4289 { PPC::VSRp16, 77U },
4290 { PPC::VSRp17, 79U },
4291 { PPC::VSRp18, 81U },
4292 { PPC::VSRp19, 83U },
4293 { PPC::VSRp20, 85U },
4294 { PPC::VSRp21, 87U },
4295 { PPC::VSRp22, 89U },
4296 { PPC::VSRp23, 91U },
4297 { PPC::VSRp24, 93U },
4298 { PPC::VSRp25, 95U },
4299 { PPC::VSRp26, 97U },
4300 { PPC::VSRp27, 99U },
4301 { PPC::VSRp28, 101U },
4302 { PPC::VSRp29, 103U },
4303 { PPC::VSRp30, 105U },
4304 { PPC::VSRp31, 107U },
4305 { PPC::X0, -2U },
4306 { PPC::X1, -2U },
4307 { PPC::X2, -2U },
4308 { PPC::X3, -2U },
4309 { PPC::X4, -2U },
4310 { PPC::X5, -2U },
4311 { PPC::X6, -2U },
4312 { PPC::X7, -2U },
4313 { PPC::X8, -2U },
4314 { PPC::X9, -2U },
4315 { PPC::X10, -2U },
4316 { PPC::X11, -2U },
4317 { PPC::X12, -2U },
4318 { PPC::X13, -2U },
4319 { PPC::X14, -2U },
4320 { PPC::X15, -2U },
4321 { PPC::X16, -2U },
4322 { PPC::X17, -2U },
4323 { PPC::X18, -2U },
4324 { PPC::X19, -2U },
4325 { PPC::X20, -2U },
4326 { PPC::X21, -2U },
4327 { PPC::X22, -2U },
4328 { PPC::X23, -2U },
4329 { PPC::X24, -2U },
4330 { PPC::X25, -2U },
4331 { PPC::X26, -2U },
4332 { PPC::X27, -2U },
4333 { PPC::X28, -2U },
4334 { PPC::X29, -2U },
4335 { PPC::X30, -2U },
4336 { PPC::X31, -2U },
4337 { PPC::ZERO8, -2U },
4338};
4339extern const unsigned PPCDwarfFlavour1L2DwarfSize = std::size(PPCDwarfFlavour1L2Dwarf);
4340
4341extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = {
4342 { PPC::CARRY, 76U },
4343 { PPC::CTR, -2U },
4344 { PPC::LR, -2U },
4345 { PPC::SPEFSCR, 612U },
4346 { PPC::VRSAVE, 109U },
4347 { PPC::XER, 76U },
4348 { PPC::ZERO, -2U },
4349 { PPC::CR0, 68U },
4350 { PPC::CR1, 69U },
4351 { PPC::CR2, 70U },
4352 { PPC::CR3, 71U },
4353 { PPC::CR4, 72U },
4354 { PPC::CR5, 73U },
4355 { PPC::CR6, 74U },
4356 { PPC::CR7, 75U },
4357 { PPC::CTR8, 66U },
4358 { PPC::F0, 32U },
4359 { PPC::F1, 33U },
4360 { PPC::F2, 34U },
4361 { PPC::F3, 35U },
4362 { PPC::F4, 36U },
4363 { PPC::F5, 37U },
4364 { PPC::F6, 38U },
4365 { PPC::F7, 39U },
4366 { PPC::F8, 40U },
4367 { PPC::F9, 41U },
4368 { PPC::F10, 42U },
4369 { PPC::F11, 43U },
4370 { PPC::F12, 44U },
4371 { PPC::F13, 45U },
4372 { PPC::F14, 46U },
4373 { PPC::F15, 47U },
4374 { PPC::F16, 48U },
4375 { PPC::F17, 49U },
4376 { PPC::F18, 50U },
4377 { PPC::F19, 51U },
4378 { PPC::F20, 52U },
4379 { PPC::F21, 53U },
4380 { PPC::F22, 54U },
4381 { PPC::F23, 55U },
4382 { PPC::F24, 56U },
4383 { PPC::F25, 57U },
4384 { PPC::F26, 58U },
4385 { PPC::F27, 59U },
4386 { PPC::F28, 60U },
4387 { PPC::F29, 61U },
4388 { PPC::F30, 62U },
4389 { PPC::F31, 63U },
4390 { PPC::LR8, 65U },
4391 { PPC::R0, -2U },
4392 { PPC::R1, -2U },
4393 { PPC::R2, -2U },
4394 { PPC::R3, -2U },
4395 { PPC::R4, -2U },
4396 { PPC::R5, -2U },
4397 { PPC::R6, -2U },
4398 { PPC::R7, -2U },
4399 { PPC::R8, -2U },
4400 { PPC::R9, -2U },
4401 { PPC::R10, -2U },
4402 { PPC::R11, -2U },
4403 { PPC::R12, -2U },
4404 { PPC::R13, -2U },
4405 { PPC::R14, -2U },
4406 { PPC::R15, -2U },
4407 { PPC::R16, -2U },
4408 { PPC::R17, -2U },
4409 { PPC::R18, -2U },
4410 { PPC::R19, -2U },
4411 { PPC::R20, -2U },
4412 { PPC::R21, -2U },
4413 { PPC::R22, -2U },
4414 { PPC::R23, -2U },
4415 { PPC::R24, -2U },
4416 { PPC::R25, -2U },
4417 { PPC::R26, -2U },
4418 { PPC::R27, -2U },
4419 { PPC::R28, -2U },
4420 { PPC::R29, -2U },
4421 { PPC::R30, -2U },
4422 { PPC::R31, -2U },
4423 { PPC::S0, 1200U },
4424 { PPC::S1, 1201U },
4425 { PPC::S2, 1202U },
4426 { PPC::S3, 1203U },
4427 { PPC::S4, 1204U },
4428 { PPC::S5, 1205U },
4429 { PPC::S6, 1206U },
4430 { PPC::S7, 1207U },
4431 { PPC::S8, 1208U },
4432 { PPC::S9, 1209U },
4433 { PPC::S10, 1210U },
4434 { PPC::S11, 1211U },
4435 { PPC::S12, 1212U },
4436 { PPC::S13, 1213U },
4437 { PPC::S14, 1214U },
4438 { PPC::S15, 1215U },
4439 { PPC::S16, 1216U },
4440 { PPC::S17, 1217U },
4441 { PPC::S18, 1218U },
4442 { PPC::S19, 1219U },
4443 { PPC::S20, 1220U },
4444 { PPC::S21, 1221U },
4445 { PPC::S22, 1222U },
4446 { PPC::S23, 1223U },
4447 { PPC::S24, 1224U },
4448 { PPC::S25, 1225U },
4449 { PPC::S26, 1226U },
4450 { PPC::S27, 1227U },
4451 { PPC::S28, 1228U },
4452 { PPC::S29, 1229U },
4453 { PPC::S30, 1230U },
4454 { PPC::S31, 1231U },
4455 { PPC::V0, 77U },
4456 { PPC::V1, 78U },
4457 { PPC::V2, 79U },
4458 { PPC::V3, 80U },
4459 { PPC::V4, 81U },
4460 { PPC::V5, 82U },
4461 { PPC::V6, 83U },
4462 { PPC::V7, 84U },
4463 { PPC::V8, 85U },
4464 { PPC::V9, 86U },
4465 { PPC::V10, 87U },
4466 { PPC::V11, 88U },
4467 { PPC::V12, 89U },
4468 { PPC::V13, 90U },
4469 { PPC::V14, 91U },
4470 { PPC::V15, 92U },
4471 { PPC::V16, 93U },
4472 { PPC::V17, 94U },
4473 { PPC::V18, 95U },
4474 { PPC::V19, 96U },
4475 { PPC::V20, 97U },
4476 { PPC::V21, 98U },
4477 { PPC::V22, 99U },
4478 { PPC::V23, 100U },
4479 { PPC::V24, 101U },
4480 { PPC::V25, 102U },
4481 { PPC::V26, 103U },
4482 { PPC::V27, 104U },
4483 { PPC::V28, 105U },
4484 { PPC::V29, 106U },
4485 { PPC::V30, 107U },
4486 { PPC::V31, 108U },
4487 { PPC::VF0, 77U },
4488 { PPC::VF1, 78U },
4489 { PPC::VF2, 79U },
4490 { PPC::VF3, 80U },
4491 { PPC::VF4, 81U },
4492 { PPC::VF5, 82U },
4493 { PPC::VF6, 83U },
4494 { PPC::VF7, 84U },
4495 { PPC::VF8, 85U },
4496 { PPC::VF9, 86U },
4497 { PPC::VF10, 87U },
4498 { PPC::VF11, 88U },
4499 { PPC::VF12, 89U },
4500 { PPC::VF13, 90U },
4501 { PPC::VF14, 91U },
4502 { PPC::VF15, 92U },
4503 { PPC::VF16, 93U },
4504 { PPC::VF17, 94U },
4505 { PPC::VF18, 95U },
4506 { PPC::VF19, 96U },
4507 { PPC::VF20, 97U },
4508 { PPC::VF21, 98U },
4509 { PPC::VF22, 99U },
4510 { PPC::VF23, 100U },
4511 { PPC::VF24, 101U },
4512 { PPC::VF25, 102U },
4513 { PPC::VF26, 103U },
4514 { PPC::VF27, 104U },
4515 { PPC::VF28, 105U },
4516 { PPC::VF29, 106U },
4517 { PPC::VF30, 107U },
4518 { PPC::VF31, 108U },
4519 { PPC::VSL0, 32U },
4520 { PPC::VSL1, 33U },
4521 { PPC::VSL2, 34U },
4522 { PPC::VSL3, 35U },
4523 { PPC::VSL4, 36U },
4524 { PPC::VSL5, 37U },
4525 { PPC::VSL6, 38U },
4526 { PPC::VSL7, 39U },
4527 { PPC::VSL8, 40U },
4528 { PPC::VSL9, 41U },
4529 { PPC::VSL10, 42U },
4530 { PPC::VSL11, 43U },
4531 { PPC::VSL12, 44U },
4532 { PPC::VSL13, 45U },
4533 { PPC::VSL14, 46U },
4534 { PPC::VSL15, 47U },
4535 { PPC::VSL16, 48U },
4536 { PPC::VSL17, 49U },
4537 { PPC::VSL18, 50U },
4538 { PPC::VSL19, 51U },
4539 { PPC::VSL20, 52U },
4540 { PPC::VSL21, 53U },
4541 { PPC::VSL22, 54U },
4542 { PPC::VSL23, 55U },
4543 { PPC::VSL24, 56U },
4544 { PPC::VSL25, 57U },
4545 { PPC::VSL26, 58U },
4546 { PPC::VSL27, 59U },
4547 { PPC::VSL28, 60U },
4548 { PPC::VSL29, 61U },
4549 { PPC::VSL30, 62U },
4550 { PPC::VSL31, 63U },
4551 { PPC::VSRp16, 77U },
4552 { PPC::VSRp17, 79U },
4553 { PPC::VSRp18, 81U },
4554 { PPC::VSRp19, 83U },
4555 { PPC::VSRp20, 85U },
4556 { PPC::VSRp21, 87U },
4557 { PPC::VSRp22, 89U },
4558 { PPC::VSRp23, 91U },
4559 { PPC::VSRp24, 93U },
4560 { PPC::VSRp25, 95U },
4561 { PPC::VSRp26, 97U },
4562 { PPC::VSRp27, 99U },
4563 { PPC::VSRp28, 101U },
4564 { PPC::VSRp29, 103U },
4565 { PPC::VSRp30, 105U },
4566 { PPC::VSRp31, 107U },
4567 { PPC::X0, 0U },
4568 { PPC::X1, 1U },
4569 { PPC::X2, 2U },
4570 { PPC::X3, 3U },
4571 { PPC::X4, 4U },
4572 { PPC::X5, 5U },
4573 { PPC::X6, 6U },
4574 { PPC::X7, 7U },
4575 { PPC::X8, 8U },
4576 { PPC::X9, 9U },
4577 { PPC::X10, 10U },
4578 { PPC::X11, 11U },
4579 { PPC::X12, 12U },
4580 { PPC::X13, 13U },
4581 { PPC::X14, 14U },
4582 { PPC::X15, 15U },
4583 { PPC::X16, 16U },
4584 { PPC::X17, 17U },
4585 { PPC::X18, 18U },
4586 { PPC::X19, 19U },
4587 { PPC::X20, 20U },
4588 { PPC::X21, 21U },
4589 { PPC::X22, 22U },
4590 { PPC::X23, 23U },
4591 { PPC::X24, 24U },
4592 { PPC::X25, 25U },
4593 { PPC::X26, 26U },
4594 { PPC::X27, 27U },
4595 { PPC::X28, 28U },
4596 { PPC::X29, 29U },
4597 { PPC::X30, 30U },
4598 { PPC::X31, 31U },
4599 { PPC::ZERO8, 0U },
4600};
4601extern const unsigned PPCEHFlavour0L2DwarfSize = std::size(PPCEHFlavour0L2Dwarf);
4602
4603extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = {
4604 { PPC::CTR, 66U },
4605 { PPC::LR, 65U },
4606 { PPC::SPEFSCR, 112U },
4607 { PPC::ZERO, 0U },
4608 { PPC::CR0, 68U },
4609 { PPC::CR1, 69U },
4610 { PPC::CR2, 70U },
4611 { PPC::CR3, 71U },
4612 { PPC::CR4, 72U },
4613 { PPC::CR5, 73U },
4614 { PPC::CR6, 74U },
4615 { PPC::CR7, 75U },
4616 { PPC::CTR8, -2U },
4617 { PPC::F0, 32U },
4618 { PPC::F1, 33U },
4619 { PPC::F2, 34U },
4620 { PPC::F3, 35U },
4621 { PPC::F4, 36U },
4622 { PPC::F5, 37U },
4623 { PPC::F6, 38U },
4624 { PPC::F7, 39U },
4625 { PPC::F8, 40U },
4626 { PPC::F9, 41U },
4627 { PPC::F10, 42U },
4628 { PPC::F11, 43U },
4629 { PPC::F12, 44U },
4630 { PPC::F13, 45U },
4631 { PPC::F14, 46U },
4632 { PPC::F15, 47U },
4633 { PPC::F16, 48U },
4634 { PPC::F17, 49U },
4635 { PPC::F18, 50U },
4636 { PPC::F19, 51U },
4637 { PPC::F20, 52U },
4638 { PPC::F21, 53U },
4639 { PPC::F22, 54U },
4640 { PPC::F23, 55U },
4641 { PPC::F24, 56U },
4642 { PPC::F25, 57U },
4643 { PPC::F26, 58U },
4644 { PPC::F27, 59U },
4645 { PPC::F28, 60U },
4646 { PPC::F29, 61U },
4647 { PPC::F30, 62U },
4648 { PPC::F31, 63U },
4649 { PPC::LR8, -2U },
4650 { PPC::R0, 0U },
4651 { PPC::R1, 1U },
4652 { PPC::R2, 2U },
4653 { PPC::R3, 3U },
4654 { PPC::R4, 4U },
4655 { PPC::R5, 5U },
4656 { PPC::R6, 6U },
4657 { PPC::R7, 7U },
4658 { PPC::R8, 8U },
4659 { PPC::R9, 9U },
4660 { PPC::R10, 10U },
4661 { PPC::R11, 11U },
4662 { PPC::R12, 12U },
4663 { PPC::R13, 13U },
4664 { PPC::R14, 14U },
4665 { PPC::R15, 15U },
4666 { PPC::R16, 16U },
4667 { PPC::R17, 17U },
4668 { PPC::R18, 18U },
4669 { PPC::R19, 19U },
4670 { PPC::R20, 20U },
4671 { PPC::R21, 21U },
4672 { PPC::R22, 22U },
4673 { PPC::R23, 23U },
4674 { PPC::R24, 24U },
4675 { PPC::R25, 25U },
4676 { PPC::R26, 26U },
4677 { PPC::R27, 27U },
4678 { PPC::R28, 28U },
4679 { PPC::R29, 29U },
4680 { PPC::R30, 30U },
4681 { PPC::R31, 31U },
4682 { PPC::S0, 1200U },
4683 { PPC::S1, 1201U },
4684 { PPC::S2, 1202U },
4685 { PPC::S3, 1203U },
4686 { PPC::S4, 1204U },
4687 { PPC::S5, 1205U },
4688 { PPC::S6, 1206U },
4689 { PPC::S7, 1207U },
4690 { PPC::S8, 1208U },
4691 { PPC::S9, 1209U },
4692 { PPC::S10, 1210U },
4693 { PPC::S11, 1211U },
4694 { PPC::S12, 1212U },
4695 { PPC::S13, 1213U },
4696 { PPC::S14, 1214U },
4697 { PPC::S15, 1215U },
4698 { PPC::S16, 1216U },
4699 { PPC::S17, 1217U },
4700 { PPC::S18, 1218U },
4701 { PPC::S19, 1219U },
4702 { PPC::S20, 1220U },
4703 { PPC::S21, 1221U },
4704 { PPC::S22, 1222U },
4705 { PPC::S23, 1223U },
4706 { PPC::S24, 1224U },
4707 { PPC::S25, 1225U },
4708 { PPC::S26, 1226U },
4709 { PPC::S27, 1227U },
4710 { PPC::S28, 1228U },
4711 { PPC::S29, 1229U },
4712 { PPC::S30, 1230U },
4713 { PPC::S31, 1231U },
4714 { PPC::V0, 77U },
4715 { PPC::V1, 78U },
4716 { PPC::V2, 79U },
4717 { PPC::V3, 80U },
4718 { PPC::V4, 81U },
4719 { PPC::V5, 82U },
4720 { PPC::V6, 83U },
4721 { PPC::V7, 84U },
4722 { PPC::V8, 85U },
4723 { PPC::V9, 86U },
4724 { PPC::V10, 87U },
4725 { PPC::V11, 88U },
4726 { PPC::V12, 89U },
4727 { PPC::V13, 90U },
4728 { PPC::V14, 91U },
4729 { PPC::V15, 92U },
4730 { PPC::V16, 93U },
4731 { PPC::V17, 94U },
4732 { PPC::V18, 95U },
4733 { PPC::V19, 96U },
4734 { PPC::V20, 97U },
4735 { PPC::V21, 98U },
4736 { PPC::V22, 99U },
4737 { PPC::V23, 100U },
4738 { PPC::V24, 101U },
4739 { PPC::V25, 102U },
4740 { PPC::V26, 103U },
4741 { PPC::V27, 104U },
4742 { PPC::V28, 105U },
4743 { PPC::V29, 106U },
4744 { PPC::V30, 107U },
4745 { PPC::V31, 108U },
4746 { PPC::VF0, 77U },
4747 { PPC::VF1, 78U },
4748 { PPC::VF2, 79U },
4749 { PPC::VF3, 80U },
4750 { PPC::VF4, 81U },
4751 { PPC::VF5, 82U },
4752 { PPC::VF6, 83U },
4753 { PPC::VF7, 84U },
4754 { PPC::VF8, 85U },
4755 { PPC::VF9, 86U },
4756 { PPC::VF10, 87U },
4757 { PPC::VF11, 88U },
4758 { PPC::VF12, 89U },
4759 { PPC::VF13, 90U },
4760 { PPC::VF14, 91U },
4761 { PPC::VF15, 92U },
4762 { PPC::VF16, 93U },
4763 { PPC::VF17, 94U },
4764 { PPC::VF18, 95U },
4765 { PPC::VF19, 96U },
4766 { PPC::VF20, 97U },
4767 { PPC::VF21, 98U },
4768 { PPC::VF22, 99U },
4769 { PPC::VF23, 100U },
4770 { PPC::VF24, 101U },
4771 { PPC::VF25, 102U },
4772 { PPC::VF26, 103U },
4773 { PPC::VF27, 104U },
4774 { PPC::VF28, 105U },
4775 { PPC::VF29, 106U },
4776 { PPC::VF30, 107U },
4777 { PPC::VF31, 108U },
4778 { PPC::VSL0, 32U },
4779 { PPC::VSL1, 33U },
4780 { PPC::VSL2, 34U },
4781 { PPC::VSL3, 35U },
4782 { PPC::VSL4, 36U },
4783 { PPC::VSL5, 37U },
4784 { PPC::VSL6, 38U },
4785 { PPC::VSL7, 39U },
4786 { PPC::VSL8, 40U },
4787 { PPC::VSL9, 41U },
4788 { PPC::VSL10, 42U },
4789 { PPC::VSL11, 43U },
4790 { PPC::VSL12, 44U },
4791 { PPC::VSL13, 45U },
4792 { PPC::VSL14, 46U },
4793 { PPC::VSL15, 47U },
4794 { PPC::VSL16, 48U },
4795 { PPC::VSL17, 49U },
4796 { PPC::VSL18, 50U },
4797 { PPC::VSL19, 51U },
4798 { PPC::VSL20, 52U },
4799 { PPC::VSL21, 53U },
4800 { PPC::VSL22, 54U },
4801 { PPC::VSL23, 55U },
4802 { PPC::VSL24, 56U },
4803 { PPC::VSL25, 57U },
4804 { PPC::VSL26, 58U },
4805 { PPC::VSL27, 59U },
4806 { PPC::VSL28, 60U },
4807 { PPC::VSL29, 61U },
4808 { PPC::VSL30, 62U },
4809 { PPC::VSL31, 63U },
4810 { PPC::VSRp16, 77U },
4811 { PPC::VSRp17, 79U },
4812 { PPC::VSRp18, 81U },
4813 { PPC::VSRp19, 83U },
4814 { PPC::VSRp20, 85U },
4815 { PPC::VSRp21, 87U },
4816 { PPC::VSRp22, 89U },
4817 { PPC::VSRp23, 91U },
4818 { PPC::VSRp24, 93U },
4819 { PPC::VSRp25, 95U },
4820 { PPC::VSRp26, 97U },
4821 { PPC::VSRp27, 99U },
4822 { PPC::VSRp28, 101U },
4823 { PPC::VSRp29, 103U },
4824 { PPC::VSRp30, 105U },
4825 { PPC::VSRp31, 107U },
4826 { PPC::X0, -2U },
4827 { PPC::X1, -2U },
4828 { PPC::X2, -2U },
4829 { PPC::X3, -2U },
4830 { PPC::X4, -2U },
4831 { PPC::X5, -2U },
4832 { PPC::X6, -2U },
4833 { PPC::X7, -2U },
4834 { PPC::X8, -2U },
4835 { PPC::X9, -2U },
4836 { PPC::X10, -2U },
4837 { PPC::X11, -2U },
4838 { PPC::X12, -2U },
4839 { PPC::X13, -2U },
4840 { PPC::X14, -2U },
4841 { PPC::X15, -2U },
4842 { PPC::X16, -2U },
4843 { PPC::X17, -2U },
4844 { PPC::X18, -2U },
4845 { PPC::X19, -2U },
4846 { PPC::X20, -2U },
4847 { PPC::X21, -2U },
4848 { PPC::X22, -2U },
4849 { PPC::X23, -2U },
4850 { PPC::X24, -2U },
4851 { PPC::X25, -2U },
4852 { PPC::X26, -2U },
4853 { PPC::X27, -2U },
4854 { PPC::X28, -2U },
4855 { PPC::X29, -2U },
4856 { PPC::X30, -2U },
4857 { PPC::X31, -2U },
4858 { PPC::ZERO8, -2U },
4859};
4860extern const unsigned PPCEHFlavour1L2DwarfSize = std::size(PPCEHFlavour1L2Dwarf);
4861
4862extern const uint16_t PPCRegEncodingTable[] = {
4863 0,
4864 0,
4865 1,
4866 9,
4867 0,
4868 8,
4869 0,
4870 512,
4871 256,
4872 1,
4873 0,
4874 0,
4875 1,
4876 2,
4877 3,
4878 4,
4879 5,
4880 6,
4881 7,
4882 0,
4883 0,
4884 1,
4885 2,
4886 3,
4887 4,
4888 5,
4889 6,
4890 7,
4891 9,
4892 0,
4893 1,
4894 2,
4895 3,
4896 4,
4897 5,
4898 6,
4899 7,
4900 0,
4901 1,
4902 2,
4903 3,
4904 4,
4905 5,
4906 6,
4907 7,
4908 8,
4909 9,
4910 10,
4911 11,
4912 12,
4913 13,
4914 14,
4915 15,
4916 16,
4917 17,
4918 18,
4919 19,
4920 20,
4921 21,
4922 22,
4923 23,
4924 24,
4925 25,
4926 26,
4927 27,
4928 28,
4929 29,
4930 30,
4931 31,
4932 32,
4933 33,
4934 34,
4935 35,
4936 36,
4937 37,
4938 38,
4939 39,
4940 40,
4941 41,
4942 42,
4943 43,
4944 44,
4945 45,
4946 46,
4947 47,
4948 48,
4949 49,
4950 50,
4951 51,
4952 52,
4953 53,
4954 54,
4955 55,
4956 56,
4957 57,
4958 58,
4959 59,
4960 60,
4961 61,
4962 62,
4963 63,
4964 0,
4965 1,
4966 2,
4967 3,
4968 4,
4969 5,
4970 6,
4971 7,
4972 8,
4973 9,
4974 10,
4975 11,
4976 12,
4977 13,
4978 14,
4979 15,
4980 16,
4981 17,
4982 18,
4983 19,
4984 20,
4985 21,
4986 22,
4987 23,
4988 24,
4989 25,
4990 26,
4991 27,
4992 28,
4993 29,
4994 30,
4995 31,
4996 0,
4997 1,
4998 2,
4999 3,
5000 0,
5001 1,
5002 2,
5003 3,
5004 4,
5005 5,
5006 6,
5007 7,
5008 8,
5009 9,
5010 10,
5011 11,
5012 12,
5013 13,
5014 14,
5015 15,
5016 16,
5017 17,
5018 18,
5019 19,
5020 20,
5021 21,
5022 22,
5023 23,
5024 24,
5025 25,
5026 26,
5027 27,
5028 28,
5029 29,
5030 30,
5031 31,
5032 31,
5033 31,
5034 31,
5035 31,
5036 31,
5037 31,
5038 31,
5039 31,
5040 31,
5041 31,
5042 31,
5043 31,
5044 31,
5045 31,
5046 31,
5047 31,
5048 31,
5049 31,
5050 31,
5051 31,
5052 31,
5053 31,
5054 31,
5055 31,
5056 31,
5057 31,
5058 31,
5059 31,
5060 31,
5061 31,
5062 31,
5063 31,
5064 0,
5065 0,
5066 2,
5067 4,
5068 6,
5069 8,
5070 10,
5071 12,
5072 14,
5073 16,
5074 18,
5075 20,
5076 22,
5077 24,
5078 26,
5079 28,
5080 30,
5081 31,
5082 31,
5083 31,
5084 31,
5085 31,
5086 31,
5087 31,
5088 31,
5089 31,
5090 31,
5091 31,
5092 31,
5093 31,
5094 31,
5095 31,
5096 31,
5097 31,
5098 31,
5099 31,
5100 31,
5101 31,
5102 31,
5103 31,
5104 31,
5105 31,
5106 31,
5107 31,
5108 31,
5109 31,
5110 31,
5111 31,
5112 31,
5113 8,
5114 0,
5115 1,
5116 2,
5117 3,
5118 4,
5119 5,
5120 6,
5121 7,
5122 8,
5123 9,
5124 10,
5125 11,
5126 12,
5127 13,
5128 14,
5129 15,
5130 16,
5131 17,
5132 18,
5133 19,
5134 20,
5135 21,
5136 22,
5137 23,
5138 24,
5139 25,
5140 26,
5141 27,
5142 28,
5143 29,
5144 30,
5145 31,
5146 0,
5147 1,
5148 2,
5149 3,
5150 4,
5151 5,
5152 6,
5153 7,
5154 8,
5155 9,
5156 10,
5157 11,
5158 12,
5159 13,
5160 14,
5161 15,
5162 16,
5163 17,
5164 18,
5165 19,
5166 20,
5167 21,
5168 22,
5169 23,
5170 24,
5171 25,
5172 26,
5173 27,
5174 28,
5175 29,
5176 30,
5177 31,
5178 0,
5179 1,
5180 2,
5181 3,
5182 4,
5183 5,
5184 6,
5185 7,
5186 0,
5187 1,
5188 2,
5189 3,
5190 4,
5191 5,
5192 6,
5193 7,
5194 8,
5195 9,
5196 10,
5197 11,
5198 12,
5199 13,
5200 14,
5201 15,
5202 16,
5203 17,
5204 18,
5205 19,
5206 20,
5207 21,
5208 22,
5209 23,
5210 24,
5211 25,
5212 26,
5213 27,
5214 28,
5215 29,
5216 30,
5217 31,
5218 32,
5219 33,
5220 34,
5221 35,
5222 36,
5223 37,
5224 38,
5225 39,
5226 40,
5227 41,
5228 42,
5229 43,
5230 44,
5231 45,
5232 46,
5233 47,
5234 48,
5235 49,
5236 50,
5237 51,
5238 52,
5239 53,
5240 54,
5241 55,
5242 56,
5243 57,
5244 58,
5245 59,
5246 60,
5247 61,
5248 62,
5249 63,
5250 63,
5251 63,
5252 63,
5253 63,
5254 63,
5255 63,
5256 63,
5257 63,
5258 63,
5259 63,
5260 63,
5261 63,
5262 63,
5263 63,
5264 63,
5265 63,
5266 63,
5267 63,
5268 63,
5269 63,
5270 63,
5271 63,
5272 63,
5273 63,
5274 63,
5275 63,
5276 63,
5277 63,
5278 63,
5279 63,
5280 63,
5281 63,
5282 0,
5283 1,
5284 2,
5285 3,
5286 4,
5287 5,
5288 6,
5289 7,
5290 8,
5291 9,
5292 10,
5293 11,
5294 12,
5295 13,
5296 14,
5297 15,
5298 16,
5299 17,
5300 18,
5301 19,
5302 20,
5303 21,
5304 22,
5305 23,
5306 24,
5307 25,
5308 26,
5309 27,
5310 28,
5311 29,
5312 30,
5313 31,
5314 0,
5315 1,
5316 2,
5317 3,
5318 4,
5319 5,
5320 6,
5321 7,
5322 8,
5323 9,
5324 10,
5325 11,
5326 12,
5327 13,
5328 14,
5329 15,
5330 16,
5331 17,
5332 18,
5333 19,
5334 20,
5335 21,
5336 22,
5337 23,
5338 24,
5339 25,
5340 26,
5341 27,
5342 28,
5343 29,
5344 30,
5345 31,
5346 32,
5347 33,
5348 34,
5349 35,
5350 36,
5351 37,
5352 38,
5353 39,
5354 40,
5355 41,
5356 42,
5357 43,
5358 44,
5359 45,
5360 46,
5361 47,
5362 48,
5363 49,
5364 50,
5365 51,
5366 52,
5367 53,
5368 54,
5369 55,
5370 56,
5371 57,
5372 58,
5373 59,
5374 60,
5375 61,
5376 62,
5377 63,
5378 0,
5379 1,
5380 2,
5381 3,
5382 4,
5383 5,
5384 6,
5385 7,
5386 0,
5387 1,
5388 2,
5389 3,
5390 4,
5391 5,
5392 6,
5393 7,
5394 0,
5395 1,
5396 2,
5397 3,
5398 4,
5399 5,
5400 6,
5401 7,
5402 8,
5403 9,
5404 10,
5405 11,
5406 12,
5407 13,
5408 14,
5409 15,
5410 16,
5411 17,
5412 18,
5413 19,
5414 20,
5415 21,
5416 22,
5417 23,
5418 24,
5419 25,
5420 26,
5421 27,
5422 28,
5423 29,
5424 30,
5425 31,
5426 0,
5427 2,
5428 6,
5429 10,
5430 14,
5431 18,
5432 22,
5433 26,
5434 30,
5435 1,
5436 5,
5437 9,
5438 13,
5439 17,
5440 21,
5441 25,
5442 29,
5443 0,
5444 4,
5445 8,
5446 12,
5447 16,
5448 20,
5449 24,
5450 28,
5451 3,
5452 7,
5453 11,
5454 15,
5455 19,
5456 23,
5457 27,
5458 31,
5459 0,
5460 2,
5461 4,
5462 6,
5463 8,
5464 10,
5465 12,
5466 14,
5467 16,
5468 18,
5469 20,
5470 22,
5471 24,
5472 26,
5473 28,
5474 30,
5475};
5476static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
5477 RI->InitMCRegisterInfo(PPCRegDesc, 612, RA, PC, PPCMCRegisterClasses, 56, PPCRegUnitRoots, 329, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 56,
5478PPCRegEncodingTable);
5479
5480 switch (DwarfFlavour) {
5481 default:
5482 llvm_unreachable("Unknown DWARF flavour");
5483 case 0:
5484 RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
5485 break;
5486 case 1:
5487 RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
5488 break;
5489 }
5490 switch (EHFlavour) {
5491 default:
5492 llvm_unreachable("Unknown DWARF flavour");
5493 case 0:
5494 RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
5495 break;
5496 case 1:
5497 RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
5498 break;
5499 }
5500 switch (DwarfFlavour) {
5501 default:
5502 llvm_unreachable("Unknown DWARF flavour");
5503 case 0:
5504 RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
5505 break;
5506 case 1:
5507 RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
5508 break;
5509 }
5510 switch (EHFlavour) {
5511 default:
5512 llvm_unreachable("Unknown DWARF flavour");
5513 case 0:
5514 RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
5515 break;
5516 case 1:
5517 RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
5518 break;
5519 }
5520}
5521
5522} // end namespace llvm
5523
5524#endif // GET_REGINFO_MC_DESC
5525
5526/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5527|* *|
5528|* Register Information Header Fragment *|
5529|* *|
5530|* Automatically generated file, do not edit! *|
5531|* *|
5532\*===----------------------------------------------------------------------===*/
5533
5534
5535#ifdef GET_REGINFO_HEADER
5536#undef GET_REGINFO_HEADER
5537
5538#include "llvm/CodeGen/TargetRegisterInfo.h"
5539
5540namespace llvm {
5541
5542class PPCFrameLowering;
5543
5544struct PPCGenRegisterInfo : public TargetRegisterInfo {
5545 explicit PPCGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5546 unsigned PC = 0, unsigned HwMode = 0);
5547 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5548 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5549 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5550 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
5551 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
5552 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5553 unsigned getRegUnitWeight(unsigned RegUnit) const override;
5554 unsigned getNumRegPressureSets() const override;
5555 const char *getRegPressureSetName(unsigned Idx) const override;
5556 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5557 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5558 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5559 ArrayRef<const char *> getRegMaskNames() const override;
5560 ArrayRef<const uint32_t *> getRegMasks() const override;
5561 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
5562 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
5563 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
5564 bool isConstantPhysReg(MCRegister PhysReg) const override final;
5565 /// Devirtualized TargetFrameLowering.
5566 static const PPCFrameLowering *getFrameLowering(
5567 const MachineFunction &MF);
5568};
5569
5570namespace PPC { // Register classes
5571 extern const TargetRegisterClass VSSRCRegClass;
5572 extern const TargetRegisterClass GPRCRegClass;
5573 extern const TargetRegisterClass GPRC_NOR0RegClass;
5574 extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass;
5575 extern const TargetRegisterClass CRBITRCRegClass;
5576 extern const TargetRegisterClass F4RCRegClass;
5577 extern const TargetRegisterClass GPRC32RegClass;
5578 extern const TargetRegisterClass CRRCRegClass;
5579 extern const TargetRegisterClass CARRYRCRegClass;
5580 extern const TargetRegisterClass CTRRCRegClass;
5581 extern const TargetRegisterClass LRRCRegClass;
5582 extern const TargetRegisterClass VRSAVERCRegClass;
5583 extern const TargetRegisterClass SPILLTOVSRRCRegClass;
5584 extern const TargetRegisterClass VSFRCRegClass;
5585 extern const TargetRegisterClass G8RCRegClass;
5586 extern const TargetRegisterClass G8RC_NOX0RegClass;
5587 extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass;
5588 extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass;
5589 extern const TargetRegisterClass F8RCRegClass;
5590 extern const TargetRegisterClass FHRCRegClass;
5591 extern const TargetRegisterClass SPERCRegClass;
5592 extern const TargetRegisterClass VFHRCRegClass;
5593 extern const TargetRegisterClass VFRCRegClass;
5594 extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass;
5595 extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass;
5596 extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass;
5597 extern const TargetRegisterClass CTRRC8RegClass;
5598 extern const TargetRegisterClass LR8RCRegClass;
5599 extern const TargetRegisterClass DMRROWRCRegClass;
5600 extern const TargetRegisterClass VSRCRegClass;
5601 extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5602 extern const TargetRegisterClass VRRCRegClass;
5603 extern const TargetRegisterClass VSLRCRegClass;
5604 extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5605 extern const TargetRegisterClass FpRCRegClass;
5606 extern const TargetRegisterClass G8pRCRegClass;
5607 extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass;
5608 extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5609 extern const TargetRegisterClass FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass;
5610 extern const TargetRegisterClass DMRROWpRCRegClass;
5611 extern const TargetRegisterClass VSRpRCRegClass;
5612 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5613 extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass;
5614 extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass;
5615 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass;
5616 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass;
5617 extern const TargetRegisterClass ACCRCRegClass;
5618 extern const TargetRegisterClass UACCRCRegClass;
5619 extern const TargetRegisterClass WACCRCRegClass;
5620 extern const TargetRegisterClass WACC_HIRCRegClass;
5621 extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5622 extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5623 extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
5624 extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
5625 extern const TargetRegisterClass DMRRCRegClass;
5626 extern const TargetRegisterClass DMRpRCRegClass;
5627} // end namespace PPC
5628
5629} // end namespace llvm
5630
5631#endif // GET_REGINFO_HEADER
5632
5633/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5634|* *|
5635|* Target Register and Register Classes Information *|
5636|* *|
5637|* Automatically generated file, do not edit! *|
5638|* *|
5639\*===----------------------------------------------------------------------===*/
5640
5641
5642#ifdef GET_REGINFO_TARGET_DESC
5643#undef GET_REGINFO_TARGET_DESC
5644
5645namespace llvm {
5646
5647extern const MCRegisterClass PPCMCRegisterClasses[];
5648
5649static const MVT::SimpleValueType VTLists[] = {
5650 /* 0 */ MVT::i1, MVT::Other,
5651 /* 2 */ MVT::i32, MVT::Other,
5652 /* 4 */ MVT::i64, MVT::Other,
5653 /* 6 */ MVT::i128, MVT::Other,
5654 /* 8 */ MVT::i32, MVT::f32, MVT::Other,
5655 /* 11 */ MVT::i64, MVT::f64, MVT::Other,
5656 /* 14 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
5657 /* 23 */ MVT::ppcf128, MVT::Other,
5658 /* 25 */ MVT::v128i1, MVT::Other,
5659 /* 27 */ MVT::v256i1, MVT::Other,
5660 /* 29 */ MVT::v512i1, MVT::Other,
5661 /* 31 */ MVT::v1024i1, MVT::Other,
5662 /* 33 */ MVT::v2048i1, MVT::Other,
5663 /* 35 */ MVT::v4i32, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::Other,
5664};
5665
5666static const char *SubRegIndexNameTable[] = { "sub_32", "sub_32_hi_phony", "sub_64", "sub_64_hi_phony", "sub_dmr0", "sub_dmr1", "sub_dmrrow0", "sub_dmrrow1", "sub_dmrrowp0", "sub_dmrrowp1", "sub_eq", "sub_fp0", "sub_fp1", "sub_gp8_x0", "sub_gp8_x1", "sub_gt", "sub_lt", "sub_pair0", "sub_pair1", "sub_un", "sub_vsx0", "sub_vsx1", "sub_wacc_hi", "sub_wacc_lo", "sub_vsx1_then_sub_64", "sub_vsx1_then_sub_64_hi_phony", "sub_pair1_then_sub_64", "sub_pair1_then_sub_64_hi_phony", "sub_pair1_then_sub_vsx0", "sub_pair1_then_sub_vsx1", "sub_pair1_then_sub_vsx1_then_sub_64", "sub_pair1_then_sub_vsx1_then_sub_64_hi_phony", "sub_dmrrowp1_then_sub_dmrrow0", "sub_dmrrowp1_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrowp0", "sub_wacc_hi_then_sub_dmrrowp1", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrowp0", "sub_dmr1_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi", "sub_dmr1_then_sub_wacc_lo", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_gp8_x1_then_sub_32", "" };
5667
5668static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
5669 { 65535, 65535 },
5670 { 0, 32 }, // sub_32
5671 { 32, 32 }, // sub_32_hi_phony
5672 { 0, 64 }, // sub_64
5673 { 64, 64 }, // sub_64_hi_phony
5674 { 0, 1024 }, // sub_dmr0
5675 { 1024, 1024 }, // sub_dmr1
5676 { 0, 128 }, // sub_dmrrow0
5677 { 128, 128 }, // sub_dmrrow1
5678 { 0, 256 }, // sub_dmrrowp0
5679 { 256, 256 }, // sub_dmrrowp1
5680 { 2, 1 }, // sub_eq
5681 { 0, 64 }, // sub_fp0
5682 { 64, 64 }, // sub_fp1
5683 { 0, 64 }, // sub_gp8_x0
5684 { 64, 64 }, // sub_gp8_x1
5685 { 1, 1 }, // sub_gt
5686 { 0, 1 }, // sub_lt
5687 { 0, 256 }, // sub_pair0
5688 { 256, 256 }, // sub_pair1
5689 { 3, 1 }, // sub_un
5690 { 0, 128 }, // sub_vsx0
5691 { 128, 128 }, // sub_vsx1
5692 { 512, 512 }, // sub_wacc_hi
5693 { 0, 512 }, // sub_wacc_lo
5694 { 128, 64 }, // sub_vsx1_then_sub_64
5695 { 192, 64 }, // sub_vsx1_then_sub_64_hi_phony
5696 { 256, 64 }, // sub_pair1_then_sub_64
5697 { 320, 64 }, // sub_pair1_then_sub_64_hi_phony
5698 { 256, 128 }, // sub_pair1_then_sub_vsx0
5699 { 384, 128 }, // sub_pair1_then_sub_vsx1
5700 { 384, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64
5701 { 448, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
5702 { 256, 128 }, // sub_dmrrowp1_then_sub_dmrrow0
5703 { 384, 128 }, // sub_dmrrowp1_then_sub_dmrrow1
5704 { 512, 128 }, // sub_wacc_hi_then_sub_dmrrow0
5705 { 640, 128 }, // sub_wacc_hi_then_sub_dmrrow1
5706 { 512, 256 }, // sub_wacc_hi_then_sub_dmrrowp0
5707 { 768, 256 }, // sub_wacc_hi_then_sub_dmrrowp1
5708 { 768, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5709 { 896, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5710 { 1024, 128 }, // sub_dmr1_then_sub_dmrrow0
5711 { 1152, 128 }, // sub_dmr1_then_sub_dmrrow1
5712 { 1024, 256 }, // sub_dmr1_then_sub_dmrrowp0
5713 { 1280, 256 }, // sub_dmr1_then_sub_dmrrowp1
5714 { 1536, 512 }, // sub_dmr1_then_sub_wacc_hi
5715 { 1024, 512 }, // sub_dmr1_then_sub_wacc_lo
5716 { 1280, 128 }, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
5717 { 1408, 128 }, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
5718 { 1536, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
5719 { 1664, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
5720 { 1536, 256 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
5721 { 1792, 256 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
5722 { 1792, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5723 { 1920, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5724 { 64, 32 }, // sub_gp8_x1_then_sub_32
5725};
5726
5727
5728static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5729 LaneBitmask::getAll(),
5730 LaneBitmask(0x0000000000000001), // sub_32
5731 LaneBitmask(0x0000000000000002), // sub_32_hi_phony
5732 LaneBitmask(0x0000000000000004), // sub_64
5733 LaneBitmask(0x0000000000000008), // sub_64_hi_phony
5734 LaneBitmask(0x0000000000FC0030), // sub_dmr0
5735 LaneBitmask(0x00000000FF000000), // sub_dmr1
5736 LaneBitmask(0x0000000000000010), // sub_dmrrow0
5737 LaneBitmask(0x0000000000000020), // sub_dmrrow1
5738 LaneBitmask(0x0000000000000030), // sub_dmrrowp0
5739 LaneBitmask(0x00000000000C0000), // sub_dmrrowp1
5740 LaneBitmask(0x0000000000000040), // sub_eq
5741 LaneBitmask(0x0000000000000080), // sub_fp0
5742 LaneBitmask(0x0000000000000100), // sub_fp1
5743 LaneBitmask(0x0000000000000001), // sub_gp8_x0
5744 LaneBitmask(0x0000000100000000), // sub_gp8_x1
5745 LaneBitmask(0x0000000000000200), // sub_gt
5746 LaneBitmask(0x0000000000000400), // sub_lt
5747 LaneBitmask(0x000000000000300C), // sub_pair0
5748 LaneBitmask(0x000000000003C000), // sub_pair1
5749 LaneBitmask(0x0000000000000800), // sub_un
5750 LaneBitmask(0x000000000000000C), // sub_vsx0
5751 LaneBitmask(0x0000000000003000), // sub_vsx1
5752 LaneBitmask(0x0000000000F00000), // sub_wacc_hi
5753 LaneBitmask(0x00000000000C0030), // sub_wacc_lo
5754 LaneBitmask(0x0000000000001000), // sub_vsx1_then_sub_64
5755 LaneBitmask(0x0000000000002000), // sub_vsx1_then_sub_64_hi_phony
5756 LaneBitmask(0x0000000000004000), // sub_pair1_then_sub_64
5757 LaneBitmask(0x0000000000008000), // sub_pair1_then_sub_64_hi_phony
5758 LaneBitmask(0x000000000000C000), // sub_pair1_then_sub_vsx0
5759 LaneBitmask(0x0000000000030000), // sub_pair1_then_sub_vsx1
5760 LaneBitmask(0x0000000000010000), // sub_pair1_then_sub_vsx1_then_sub_64
5761 LaneBitmask(0x0000000000020000), // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
5762 LaneBitmask(0x0000000000040000), // sub_dmrrowp1_then_sub_dmrrow0
5763 LaneBitmask(0x0000000000080000), // sub_dmrrowp1_then_sub_dmrrow1
5764 LaneBitmask(0x0000000000100000), // sub_wacc_hi_then_sub_dmrrow0
5765 LaneBitmask(0x0000000000200000), // sub_wacc_hi_then_sub_dmrrow1
5766 LaneBitmask(0x0000000000300000), // sub_wacc_hi_then_sub_dmrrowp0
5767 LaneBitmask(0x0000000000C00000), // sub_wacc_hi_then_sub_dmrrowp1
5768 LaneBitmask(0x0000000000400000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5769 LaneBitmask(0x0000000000800000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5770 LaneBitmask(0x0000000001000000), // sub_dmr1_then_sub_dmrrow0
5771 LaneBitmask(0x0000000002000000), // sub_dmr1_then_sub_dmrrow1
5772 LaneBitmask(0x0000000003000000), // sub_dmr1_then_sub_dmrrowp0
5773 LaneBitmask(0x000000000C000000), // sub_dmr1_then_sub_dmrrowp1
5774 LaneBitmask(0x00000000F0000000), // sub_dmr1_then_sub_wacc_hi
5775 LaneBitmask(0x000000000F000000), // sub_dmr1_then_sub_wacc_lo
5776 LaneBitmask(0x0000000004000000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
5777 LaneBitmask(0x0000000008000000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
5778 LaneBitmask(0x0000000010000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
5779 LaneBitmask(0x0000000020000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
5780 LaneBitmask(0x0000000030000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
5781 LaneBitmask(0x00000000C0000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
5782 LaneBitmask(0x0000000040000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5783 LaneBitmask(0x0000000080000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5784 LaneBitmask(0x0000000100000000), // sub_gp8_x1_then_sub_32
5785 };
5786
5787
5788
5789static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5790 // Mode = 0 (Default)
5791 { 32, 32, 32, /*VTLists+*/9 }, // VSSRC
5792 { 32, 32, 32, /*VTLists+*/8 }, // GPRC
5793 { 32, 32, 32, /*VTLists+*/8 }, // GPRC_NOR0
5794 { 32, 32, 32, /*VTLists+*/8 }, // GPRC_and_GPRC_NOR0
5795 { 32, 32, 32, /*VTLists+*/0 }, // CRBITRC
5796 { 32, 32, 32, /*VTLists+*/9 }, // F4RC
5797 { 32, 32, 32, /*VTLists+*/8 }, // GPRC32
5798 { 32, 32, 32, /*VTLists+*/2 }, // CRRC
5799 { 32, 32, 32, /*VTLists+*/2 }, // CARRYRC
5800 { 32, 32, 32, /*VTLists+*/2 }, // CTRRC
5801 { 32, 32, 32, /*VTLists+*/2 }, // LRRC
5802 { 32, 32, 32, /*VTLists+*/2 }, // VRSAVERC
5803 { 64, 64, 64, /*VTLists+*/11 }, // SPILLTOVSRRC
5804 { 64, 64, 64, /*VTLists+*/12 }, // VSFRC
5805 { 64, 64, 64, /*VTLists+*/4 }, // G8RC
5806 { 64, 64, 64, /*VTLists+*/4 }, // G8RC_NOX0
5807 { 64, 64, 64, /*VTLists+*/12 }, // SPILLTOVSRRC_and_VSFRC
5808 { 64, 64, 64, /*VTLists+*/4 }, // G8RC_and_G8RC_NOX0
5809 { 64, 64, 64, /*VTLists+*/12 }, // F8RC
5810 { 64, 64, 64, /*VTLists+*/12 }, // FHRC
5811 { 64, 64, 64, /*VTLists+*/12 }, // SPERC
5812 { 64, 64, 64, /*VTLists+*/12 }, // VFHRC
5813 { 64, 64, 64, /*VTLists+*/12 }, // VFRC
5814 { 64, 64, 64, /*VTLists+*/12 }, // SPERC_with_sub_32_in_GPRC_NOR0
5815 { 64, 64, 64, /*VTLists+*/12 }, // SPILLTOVSRRC_and_VFRC
5816 { 64, 64, 64, /*VTLists+*/12 }, // SPILLTOVSRRC_and_F4RC
5817 { 64, 64, 64, /*VTLists+*/4 }, // CTRRC8
5818 { 64, 64, 64, /*VTLists+*/4 }, // LR8RC
5819 { 128, 128, 128, /*VTLists+*/25 }, // DMRROWRC
5820 { 128, 128, 128, /*VTLists+*/35 }, // VSRC
5821 { 128, 128, 128, /*VTLists+*/35 }, // VSRC_with_sub_64_in_SPILLTOVSRRC
5822 { 128, 128, 128, /*VTLists+*/14 }, // VRRC
5823 { 128, 128, 128, /*VTLists+*/35 }, // VSLRC
5824 { 128, 128, 128, /*VTLists+*/14 }, // VRRC_with_sub_64_in_SPILLTOVSRRC
5825 { 128, 128, 128, /*VTLists+*/23 }, // FpRC
5826 { 128, 128, 128, /*VTLists+*/6 }, // G8pRC
5827 { 128, 128, 128, /*VTLists+*/6 }, // G8pRC_with_sub_32_in_GPRC_NOR0
5828 { 128, 128, 128, /*VTLists+*/35 }, // VSLRC_with_sub_64_in_SPILLTOVSRRC
5829 { 128, 128, 128, /*VTLists+*/23 }, // FpRC_with_sub_fp0_in_SPILLTOVSRRC
5830 { 256, 256, 128, /*VTLists+*/27 }, // DMRROWpRC
5831 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC
5832 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC
5833 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_F4RC
5834 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_VFRC
5835 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
5836 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
5837 { 512, 512, 128, /*VTLists+*/29 }, // ACCRC
5838 { 512, 512, 128, /*VTLists+*/29 }, // UACCRC
5839 { 512, 512, 128, /*VTLists+*/29 }, // WACCRC
5840 { 512, 512, 128, /*VTLists+*/29 }, // WACC_HIRC
5841 { 512, 512, 128, /*VTLists+*/29 }, // ACCRC_with_sub_64_in_SPILLTOVSRRC
5842 { 512, 512, 128, /*VTLists+*/29 }, // UACCRC_with_sub_64_in_SPILLTOVSRRC
5843 { 512, 512, 128, /*VTLists+*/29 }, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
5844 { 512, 512, 128, /*VTLists+*/29 }, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
5845 { 1024, 1024, 128, /*VTLists+*/31 }, // DMRRC
5846 { 2048, 2048, 128, /*VTLists+*/33 }, // DMRpRC
5847};
5848
5849static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
5850
5851static const uint32_t VSSRCSubClassMask[] = {
5852 0x03452021, 0x00000000,
5853 0xe0000000, 0x003cff23, // sub_64
5854 0x00000000, 0x00000044, // sub_fp0
5855 0x00000000, 0x00000044, // sub_fp1
5856 0x00000000, 0x003cff00, // sub_vsx1_then_sub_64
5857 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5858 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5859};
5860
5861static const uint32_t GPRCSubClassMask[] = {
5862 0x0000000a, 0x00000000,
5863 0x00924000, 0x00000018, // sub_32
5864 0x00000000, 0x00000018, // sub_gp8_x1_then_sub_32
5865};
5866
5867static const uint32_t GPRC_NOR0SubClassMask[] = {
5868 0x0000000c, 0x00000000,
5869 0x00828000, 0x00000010, // sub_32
5870 0x00000000, 0x00000018, // sub_gp8_x1_then_sub_32
5871};
5872
5873static const uint32_t GPRC_and_GPRC_NOR0SubClassMask[] = {
5874 0x00000008, 0x00000000,
5875 0x00820000, 0x00000010, // sub_32
5876 0x00000000, 0x00000018, // sub_gp8_x1_then_sub_32
5877};
5878
5879static const uint32_t CRBITRCSubClassMask[] = {
5880 0x00000010, 0x00000000,
5881 0x00000080, 0x00000000, // sub_eq
5882 0x00000080, 0x00000000, // sub_gt
5883 0x00000080, 0x00000000, // sub_lt
5884 0x00000080, 0x00000000, // sub_un
5885};
5886
5887static const uint32_t F4RCSubClassMask[] = {
5888 0x02040020, 0x00000000,
5889 0x00000000, 0x003ce421, // sub_64
5890 0x00000000, 0x00000044, // sub_fp0
5891 0x00000000, 0x00000044, // sub_fp1
5892 0x00000000, 0x003ce400, // sub_vsx1_then_sub_64
5893 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5894 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5895};
5896
5897static const uint32_t GPRC32SubClassMask[] = {
5898 0x00000040, 0x00000000,
5899};
5900
5901static const uint32_t CRRCSubClassMask[] = {
5902 0x00000080, 0x00000000,
5903};
5904
5905static const uint32_t CARRYRCSubClassMask[] = {
5906 0x00000100, 0x00000000,
5907};
5908
5909static const uint32_t CTRRCSubClassMask[] = {
5910 0x00000200, 0x00000000,
5911};
5912
5913static const uint32_t LRRCSubClassMask[] = {
5914 0x00000400, 0x00000000,
5915};
5916
5917static const uint32_t VRSAVERCSubClassMask[] = {
5918 0x00000800, 0x00000000,
5919};
5920
5921static const uint32_t SPILLTOVSRRCSubClassMask[] = {
5922 0x03035000, 0x00000000,
5923 0x40000000, 0x003c3222, // sub_64
5924 0x00000000, 0x00000040, // sub_fp0
5925 0x00000000, 0x00000040, // sub_fp1
5926 0x00000000, 0x00000018, // sub_gp8_x0
5927 0x00000000, 0x00000018, // sub_gp8_x1
5928 0x00000000, 0x003c3200, // sub_vsx1_then_sub_64
5929 0x00000000, 0x00300000, // sub_pair1_then_sub_64
5930 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1_then_sub_64
5931};
5932
5933static const uint32_t VSFRCSubClassMask[] = {
5934 0x03452000, 0x00000000,
5935 0xe0000000, 0x003cff23, // sub_64
5936 0x00000000, 0x00000044, // sub_fp0
5937 0x00000000, 0x00000044, // sub_fp1
5938 0x00000000, 0x003cff00, // sub_vsx1_then_sub_64
5939 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5940 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5941};
5942
5943static const uint32_t G8RCSubClassMask[] = {
5944 0x00024000, 0x00000000,
5945 0x00000000, 0x00000018, // sub_gp8_x0
5946 0x00000000, 0x00000018, // sub_gp8_x1
5947};
5948
5949static const uint32_t G8RC_NOX0SubClassMask[] = {
5950 0x00028000, 0x00000000,
5951 0x00000000, 0x00000010, // sub_gp8_x0
5952 0x00000000, 0x00000018, // sub_gp8_x1
5953};
5954
5955static const uint32_t SPILLTOVSRRC_and_VSFRCSubClassMask[] = {
5956 0x03010000, 0x00000000,
5957 0x40000000, 0x003c3222, // sub_64
5958 0x00000000, 0x00000040, // sub_fp0
5959 0x00000000, 0x00000040, // sub_fp1
5960 0x00000000, 0x003c3200, // sub_vsx1_then_sub_64
5961 0x00000000, 0x00300000, // sub_pair1_then_sub_64
5962 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1_then_sub_64
5963};
5964
5965static const uint32_t G8RC_and_G8RC_NOX0SubClassMask[] = {
5966 0x00020000, 0x00000000,
5967 0x00000000, 0x00000010, // sub_gp8_x0
5968 0x00000000, 0x00000018, // sub_gp8_x1
5969};
5970
5971static const uint32_t F8RCSubClassMask[] = {
5972 0x02040000, 0x00000000,
5973 0x00000000, 0x003ce421, // sub_64
5974 0x00000000, 0x00000044, // sub_fp0
5975 0x00000000, 0x00000044, // sub_fp1
5976 0x00000000, 0x003ce400, // sub_vsx1_then_sub_64
5977 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5978 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5979};
5980
5981static const uint32_t FHRCSubClassMask[] = {
5982 0x00080000, 0x00000000,
5983};
5984
5985static const uint32_t SPERCSubClassMask[] = {
5986 0x00900000, 0x00000000,
5987};
5988
5989static const uint32_t VFHRCSubClassMask[] = {
5990 0x00200000, 0x00000000,
5991};
5992
5993static const uint32_t VFRCSubClassMask[] = {
5994 0x01400000, 0x00000000,
5995 0x80000000, 0x00001802, // sub_64
5996 0x00000000, 0x00001800, // sub_vsx1_then_sub_64
5997};
5998
5999static const uint32_t SPERC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
6000 0x00800000, 0x00000000,
6001};
6002
6003static const uint32_t SPILLTOVSRRC_and_VFRCSubClassMask[] = {
6004 0x01000000, 0x00000000,
6005 0x00000000, 0x00001002, // sub_64
6006 0x00000000, 0x00001000, // sub_vsx1_then_sub_64
6007};
6008
6009static const uint32_t SPILLTOVSRRC_and_F4RCSubClassMask[] = {
6010 0x02000000, 0x00000000,
6011 0x00000000, 0x003c2020, // sub_64
6012 0x00000000, 0x00000040, // sub_fp0
6013 0x00000000, 0x00000040, // sub_fp1
6014 0x00000000, 0x003c2000, // sub_vsx1_then_sub_64
6015 0x00000000, 0x00300000, // sub_pair1_then_sub_64
6016 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1_then_sub_64
6017};
6018
6019static const uint32_t CTRRC8SubClassMask[] = {
6020 0x04000000, 0x00000000,
6021};
6022
6023static const uint32_t LR8RCSubClassMask[] = {
6024 0x08000000, 0x00000000,
6025};
6026
6027static const uint32_t DMRROWRCSubClassMask[] = {
6028 0x10000000, 0x00000000,
6029 0x00000000, 0x00c30080, // sub_dmrrow0
6030 0x00000000, 0x00c30080, // sub_dmrrow1
6031 0x00000000, 0x00c30000, // sub_dmrrowp1_then_sub_dmrrow0
6032 0x00000000, 0x00c30000, // sub_dmrrowp1_then_sub_dmrrow1
6033 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrow0
6034 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrow1
6035 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6036 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6037 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrow0
6038 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrow1
6039 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6040 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6041 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6042 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6043 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6044 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6045};
6046
6047static const uint32_t VSRCSubClassMask[] = {
6048 0xe0000000, 0x00000023,
6049 0x00000000, 0x003cff00, // sub_vsx0
6050 0x00000000, 0x003cff00, // sub_vsx1
6051 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx0
6052 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1
6053};
6054
6055static const uint32_t VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6056 0x40000000, 0x00000022,
6057 0x00000000, 0x003c3200, // sub_vsx0
6058 0x00000000, 0x003c3200, // sub_vsx1
6059 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx0
6060 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1
6061};
6062
6063static const uint32_t VRRCSubClassMask[] = {
6064 0x80000000, 0x00000002,
6065 0x00000000, 0x00001800, // sub_vsx0
6066 0x00000000, 0x00001800, // sub_vsx1
6067};
6068
6069static const uint32_t VSLRCSubClassMask[] = {
6070 0x00000000, 0x00000021,
6071 0x00000000, 0x003ce400, // sub_vsx0
6072 0x00000000, 0x003ce400, // sub_vsx1
6073 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx0
6074 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1
6075};
6076
6077static const uint32_t VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6078 0x00000000, 0x00000002,
6079 0x00000000, 0x00001000, // sub_vsx0
6080 0x00000000, 0x00001000, // sub_vsx1
6081};
6082
6083static const uint32_t FpRCSubClassMask[] = {
6084 0x00000000, 0x00000044,
6085};
6086
6087static const uint32_t G8pRCSubClassMask[] = {
6088 0x00000000, 0x00000018,
6089};
6090
6091static const uint32_t G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
6092 0x00000000, 0x00000010,
6093};
6094
6095static const uint32_t VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6096 0x00000000, 0x00000020,
6097 0x00000000, 0x003c2000, // sub_vsx0
6098 0x00000000, 0x003c2000, // sub_vsx1
6099 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx0
6100 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1
6101};
6102
6103static const uint32_t FpRC_with_sub_fp0_in_SPILLTOVSRRCSubClassMask[] = {
6104 0x00000000, 0x00000040,
6105};
6106
6107static const uint32_t DMRROWpRCSubClassMask[] = {
6108 0x00000000, 0x00000080,
6109 0x00000000, 0x00c30000, // sub_dmrrowp0
6110 0x00000000, 0x00c30000, // sub_dmrrowp1
6111 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp0
6112 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp1
6113 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp0
6114 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp1
6115 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6116 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6117};
6118
6119static const uint32_t VSRpRCSubClassMask[] = {
6120 0x00000000, 0x00003f00,
6121 0x00000000, 0x003cc000, // sub_pair0
6122 0x00000000, 0x003cc000, // sub_pair1
6123};
6124
6125static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6126 0x00000000, 0x00003200,
6127 0x00000000, 0x003c0000, // sub_pair0
6128 0x00000000, 0x00300000, // sub_pair1
6129};
6130
6131static const uint32_t VSRpRC_with_sub_64_in_F4RCSubClassMask[] = {
6132 0x00000000, 0x00002400,
6133 0x00000000, 0x003cc000, // sub_pair0
6134 0x00000000, 0x003cc000, // sub_pair1
6135};
6136
6137static const uint32_t VSRpRC_with_sub_64_in_VFRCSubClassMask[] = {
6138 0x00000000, 0x00001800,
6139};
6140
6141static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask[] = {
6142 0x00000000, 0x00001000,
6143};
6144
6145static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask[] = {
6146 0x00000000, 0x00002000,
6147 0x00000000, 0x003c0000, // sub_pair0
6148 0x00000000, 0x00300000, // sub_pair1
6149};
6150
6151static const uint32_t ACCRCSubClassMask[] = {
6152 0x00000000, 0x00144000,
6153};
6154
6155static const uint32_t UACCRCSubClassMask[] = {
6156 0x00000000, 0x00288000,
6157};
6158
6159static const uint32_t WACCRCSubClassMask[] = {
6160 0x00000000, 0x00010000,
6161 0x00000000, 0x00c00000, // sub_wacc_lo
6162 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_lo
6163};
6164
6165static const uint32_t WACC_HIRCSubClassMask[] = {
6166 0x00000000, 0x00020000,
6167 0x00000000, 0x00c00000, // sub_wacc_hi
6168 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi
6169};
6170
6171static const uint32_t ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6172 0x00000000, 0x00140000,
6173};
6174
6175static const uint32_t UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6176 0x00000000, 0x00280000,
6177};
6178
6179static const uint32_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6180 0x00000000, 0x00100000,
6181};
6182
6183static const uint32_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6184 0x00000000, 0x00200000,
6185};
6186
6187static const uint32_t DMRRCSubClassMask[] = {
6188 0x00000000, 0x00400000,
6189 0x00000000, 0x00800000, // sub_dmr0
6190 0x00000000, 0x00800000, // sub_dmr1
6191};
6192
6193static const uint32_t DMRpRCSubClassMask[] = {
6194 0x00000000, 0x00800000,
6195};
6196
6197static const uint16_t SuperRegIdxSeqs[] = {
6198 /* 0 */ 5, 6, 0,
6199 /* 3 */ 14, 15, 0,
6200 /* 6 */ 18, 19, 0,
6201 /* 9 */ 11, 16, 17, 20, 0,
6202 /* 14 */ 21, 22, 0,
6203 /* 17 */ 3, 25, 0,
6204 /* 20 */ 21, 22, 29, 30, 0,
6205 /* 25 */ 3, 12, 13, 25, 27, 31, 0,
6206 /* 32 */ 3, 12, 13, 14, 15, 25, 27, 31, 0,
6207 /* 41 */ 23, 45, 0,
6208 /* 44 */ 24, 46, 0,
6209 /* 47 */ 9, 10, 37, 38, 43, 44, 51, 52, 0,
6210 /* 56 */ 7, 8, 33, 34, 35, 36, 39, 40, 41, 42, 47, 48, 49, 50, 53, 54, 0,
6211 /* 73 */ 1, 55, 0,
6212};
6213
6214static const TargetRegisterClass *const GPRC_and_GPRC_NOR0Superclasses[] = {
6215 &PPC::GPRCRegClass,
6216 &PPC::GPRC_NOR0RegClass,
6217 nullptr
6218};
6219
6220static const TargetRegisterClass *const F4RCSuperclasses[] = {
6221 &PPC::VSSRCRegClass,
6222 nullptr
6223};
6224
6225static const TargetRegisterClass *const VSFRCSuperclasses[] = {
6226 &PPC::VSSRCRegClass,
6227 nullptr
6228};
6229
6230static const TargetRegisterClass *const G8RCSuperclasses[] = {
6231 &PPC::SPILLTOVSRRCRegClass,
6232 nullptr
6233};
6234
6235static const TargetRegisterClass *const SPILLTOVSRRC_and_VSFRCSuperclasses[] = {
6236 &PPC::VSSRCRegClass,
6237 &PPC::SPILLTOVSRRCRegClass,
6238 &PPC::VSFRCRegClass,
6239 nullptr
6240};
6241
6242static const TargetRegisterClass *const G8RC_and_G8RC_NOX0Superclasses[] = {
6243 &PPC::SPILLTOVSRRCRegClass,
6244 &PPC::G8RCRegClass,
6245 &PPC::G8RC_NOX0RegClass,
6246 nullptr
6247};
6248
6249static const TargetRegisterClass *const F8RCSuperclasses[] = {
6250 &PPC::VSSRCRegClass,
6251 &PPC::F4RCRegClass,
6252 &PPC::VSFRCRegClass,
6253 nullptr
6254};
6255
6256static const TargetRegisterClass *const VFRCSuperclasses[] = {
6257 &PPC::VSSRCRegClass,
6258 &PPC::VSFRCRegClass,
6259 nullptr
6260};
6261
6262static const TargetRegisterClass *const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
6263 &PPC::SPERCRegClass,
6264 nullptr
6265};
6266
6267static const TargetRegisterClass *const SPILLTOVSRRC_and_VFRCSuperclasses[] = {
6268 &PPC::VSSRCRegClass,
6269 &PPC::SPILLTOVSRRCRegClass,
6270 &PPC::VSFRCRegClass,
6271 &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
6272 &PPC::VFRCRegClass,
6273 nullptr
6274};
6275
6276static const TargetRegisterClass *const SPILLTOVSRRC_and_F4RCSuperclasses[] = {
6277 &PPC::VSSRCRegClass,
6278 &PPC::F4RCRegClass,
6279 &PPC::SPILLTOVSRRCRegClass,
6280 &PPC::VSFRCRegClass,
6281 &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
6282 &PPC::F8RCRegClass,
6283 nullptr
6284};
6285
6286static const TargetRegisterClass *const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6287 &PPC::VSRCRegClass,
6288 nullptr
6289};
6290
6291static const TargetRegisterClass *const VRRCSuperclasses[] = {
6292 &PPC::VSRCRegClass,
6293 nullptr
6294};
6295
6296static const TargetRegisterClass *const VSLRCSuperclasses[] = {
6297 &PPC::VSRCRegClass,
6298 nullptr
6299};
6300
6301static const TargetRegisterClass *const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6302 &PPC::VSRCRegClass,
6303 &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6304 &PPC::VRRCRegClass,
6305 nullptr
6306};
6307
6308static const TargetRegisterClass *const G8pRC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
6309 &PPC::G8pRCRegClass,
6310 nullptr
6311};
6312
6313static const TargetRegisterClass *const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6314 &PPC::VSRCRegClass,
6315 &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6316 &PPC::VSLRCRegClass,
6317 nullptr
6318};
6319
6320static const TargetRegisterClass *const FpRC_with_sub_fp0_in_SPILLTOVSRRCSuperclasses[] = {
6321 &PPC::FpRCRegClass,
6322 nullptr
6323};
6324
6325static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6326 &PPC::VSRpRCRegClass,
6327 nullptr
6328};
6329
6330static const TargetRegisterClass *const VSRpRC_with_sub_64_in_F4RCSuperclasses[] = {
6331 &PPC::VSRpRCRegClass,
6332 nullptr
6333};
6334
6335static const TargetRegisterClass *const VSRpRC_with_sub_64_in_VFRCSuperclasses[] = {
6336 &PPC::VSRpRCRegClass,
6337 nullptr
6338};
6339
6340static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses[] = {
6341 &PPC::VSRpRCRegClass,
6342 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6343 &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
6344 nullptr
6345};
6346
6347static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses[] = {
6348 &PPC::VSRpRCRegClass,
6349 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6350 &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
6351 nullptr
6352};
6353
6354static const TargetRegisterClass *const ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6355 &PPC::ACCRCRegClass,
6356 nullptr
6357};
6358
6359static const TargetRegisterClass *const UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6360 &PPC::UACCRCRegClass,
6361 nullptr
6362};
6363
6364static const TargetRegisterClass *const ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6365 &PPC::ACCRCRegClass,
6366 &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6367 nullptr
6368};
6369
6370static const TargetRegisterClass *const UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6371 &PPC::UACCRCRegClass,
6372 &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6373 nullptr
6374};
6375
6376
6377static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) {
6378 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6379 }
6380
6381static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
6382 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
6383 static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
6384 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
6385 const ArrayRef<MCPhysReg> Order[] = {
6386 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6387 ArrayRef(AltOrder1),
6388 ArrayRef(AltOrder2)
6389 };
6390 const unsigned Select = GPRCAltOrderSelect(MF);
6391 assert(Select < 3);
6392 return Order[Select];
6393}
6394
6395static inline unsigned GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
6396 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6397 }
6398
6399static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
6400 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 };
6401 static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO };
6402 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
6403 const ArrayRef<MCPhysReg> Order[] = {
6404 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6405 ArrayRef(AltOrder1),
6406 ArrayRef(AltOrder2)
6407 };
6408 const unsigned Select = GPRC_NOR0AltOrderSelect(MF);
6409 assert(Select < 3);
6410 return Order[Select];
6411}
6412
6413static inline unsigned GPRC_and_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
6414 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6415 }
6416
6417static ArrayRef<MCPhysReg> GPRC_and_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
6418 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
6419 static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP };
6420 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
6421 const ArrayRef<MCPhysReg> Order[] = {
6422 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6423 ArrayRef(AltOrder1),
6424 ArrayRef(AltOrder2)
6425 };
6426 const unsigned Select = GPRC_and_GPRC_NOR0AltOrderSelect(MF);
6427 assert(Select < 3);
6428 return Order[Select];
6429}
6430
6431static inline unsigned CRBITRCAltOrderSelect(const MachineFunction &MF) {
6432 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
6433 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
6434 }
6435
6436static ArrayRef<MCPhysReg> CRBITRCGetRawAllocationOrder(const MachineFunction &MF) {
6437 static const MCPhysReg AltOrder1[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN };
6438 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRBITRCRegClassID];
6439 const ArrayRef<MCPhysReg> Order[] = {
6440 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6441 ArrayRef(AltOrder1)
6442 };
6443 const unsigned Select = CRBITRCAltOrderSelect(MF);
6444 assert(Select < 2);
6445 return Order[Select];
6446}
6447
6448static inline unsigned CRRCAltOrderSelect(const MachineFunction &MF) {
6449 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
6450 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
6451 }
6452
6453static ArrayRef<MCPhysReg> CRRCGetRawAllocationOrder(const MachineFunction &MF) {
6454 static const MCPhysReg AltOrder1[] = { PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 };
6455 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRRCRegClassID];
6456 const ArrayRef<MCPhysReg> Order[] = {
6457 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6458 ArrayRef(AltOrder1)
6459 };
6460 const unsigned Select = CRRCAltOrderSelect(MF);
6461 assert(Select < 2);
6462 return Order[Select];
6463}
6464
6465static inline unsigned G8RCAltOrderSelect(const MachineFunction &MF) {
6466 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6467 }
6468
6469static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF) {
6470 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
6471 static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8 };
6472 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
6473 const ArrayRef<MCPhysReg> Order[] = {
6474 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6475 ArrayRef(AltOrder1),
6476 ArrayRef(AltOrder2)
6477 };
6478 const unsigned Select = G8RCAltOrderSelect(MF);
6479 assert(Select < 3);
6480 return Order[Select];
6481}
6482
6483static inline unsigned G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
6484 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6485 }
6486
6487static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
6488 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 };
6489 static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8 };
6490 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
6491 const ArrayRef<MCPhysReg> Order[] = {
6492 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6493 ArrayRef(AltOrder1),
6494 ArrayRef(AltOrder2)
6495 };
6496 const unsigned Select = G8RC_NOX0AltOrderSelect(MF);
6497 assert(Select < 3);
6498 return Order[Select];
6499}
6500
6501static inline unsigned G8RC_and_G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
6502 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6503 }
6504
6505static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
6506 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
6507 static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8 };
6508 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID];
6509 const ArrayRef<MCPhysReg> Order[] = {
6510 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6511 ArrayRef(AltOrder1),
6512 ArrayRef(AltOrder2)
6513 };
6514 const unsigned Select = G8RC_and_G8RC_NOX0AltOrderSelect(MF);
6515 assert(Select < 3);
6516 return Order[Select];
6517}
6518
6519static inline unsigned G8pRCAltOrderSelect(const MachineFunction &MF) {
6520 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
6521 }
6522
6523static ArrayRef<MCPhysReg> G8pRCGetRawAllocationOrder(const MachineFunction &MF) {
6524 static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0, PPC::G8p1 };
6525 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRCRegClassID];
6526 const ArrayRef<MCPhysReg> Order[] = {
6527 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6528 ArrayRef(AltOrder1)
6529 };
6530 const unsigned Select = G8pRCAltOrderSelect(MF);
6531 assert(Select < 2);
6532 return Order[Select];
6533}
6534
6535static inline unsigned G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
6536 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
6537 }
6538
6539static ArrayRef<MCPhysReg> G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
6540 static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p1 };
6541 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID];
6542 const ArrayRef<MCPhysReg> Order[] = {
6543 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6544 ArrayRef(AltOrder1)
6545 };
6546 const unsigned Select = G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(MF);
6547 assert(Select < 2);
6548 return Order[Select];
6549}
6550
6551namespace PPC { // Register class instances
6552 extern const TargetRegisterClass VSSRCRegClass = {
6553 &PPCMCRegisterClasses[VSSRCRegClassID],
6554 VSSRCSubClassMask,
6555 SuperRegIdxSeqs + 25,
6556 LaneBitmask(0x0000000000000001),
6557 0,
6558 false,
6559 0x00, /* TSFlags */
6560 false, /* HasDisjunctSubRegs */
6561 false, /* CoveredBySubRegs */
6562 NullRegClasses,
6563 nullptr
6564 };
6565
6566 extern const TargetRegisterClass GPRCRegClass = {
6567 &PPCMCRegisterClasses[GPRCRegClassID],
6568 GPRCSubClassMask,
6569 SuperRegIdxSeqs + 73,
6570 LaneBitmask(0x0000000000000001),
6571 0,
6572 false,
6573 0x00, /* TSFlags */
6574 false, /* HasDisjunctSubRegs */
6575 false, /* CoveredBySubRegs */
6576 NullRegClasses,
6577 GPRCGetRawAllocationOrder
6578 };
6579
6580 extern const TargetRegisterClass GPRC_NOR0RegClass = {
6581 &PPCMCRegisterClasses[GPRC_NOR0RegClassID],
6582 GPRC_NOR0SubClassMask,
6583 SuperRegIdxSeqs + 73,
6584 LaneBitmask(0x0000000000000001),
6585 0,
6586 false,
6587 0x00, /* TSFlags */
6588 false, /* HasDisjunctSubRegs */
6589 false, /* CoveredBySubRegs */
6590 NullRegClasses,
6591 GPRC_NOR0GetRawAllocationOrder
6592 };
6593
6594 extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = {
6595 &PPCMCRegisterClasses[GPRC_and_GPRC_NOR0RegClassID],
6596 GPRC_and_GPRC_NOR0SubClassMask,
6597 SuperRegIdxSeqs + 73,
6598 LaneBitmask(0x0000000000000001),
6599 0,
6600 false,
6601 0x00, /* TSFlags */
6602 false, /* HasDisjunctSubRegs */
6603 false, /* CoveredBySubRegs */
6604 GPRC_and_GPRC_NOR0Superclasses,
6605 GPRC_and_GPRC_NOR0GetRawAllocationOrder
6606 };
6607
6608 extern const TargetRegisterClass CRBITRCRegClass = {
6609 &PPCMCRegisterClasses[CRBITRCRegClassID],
6610 CRBITRCSubClassMask,
6611 SuperRegIdxSeqs + 9,
6612 LaneBitmask(0x0000000000000001),
6613 0,
6614 false,
6615 0x00, /* TSFlags */
6616 false, /* HasDisjunctSubRegs */
6617 false, /* CoveredBySubRegs */
6618 NullRegClasses,
6619 CRBITRCGetRawAllocationOrder
6620 };
6621
6622 extern const TargetRegisterClass F4RCRegClass = {
6623 &PPCMCRegisterClasses[F4RCRegClassID],
6624 F4RCSubClassMask,
6625 SuperRegIdxSeqs + 25,
6626 LaneBitmask(0x0000000000000001),
6627 0,
6628 false,
6629 0x00, /* TSFlags */
6630 false, /* HasDisjunctSubRegs */
6631 false, /* CoveredBySubRegs */
6632 F4RCSuperclasses,
6633 nullptr
6634 };
6635
6636 extern const TargetRegisterClass GPRC32RegClass = {
6637 &PPCMCRegisterClasses[GPRC32RegClassID],
6638 GPRC32SubClassMask,
6639 SuperRegIdxSeqs + 2,
6640 LaneBitmask(0x0000000000000001),
6641 0,
6642 false,
6643 0x00, /* TSFlags */
6644 false, /* HasDisjunctSubRegs */
6645 false, /* CoveredBySubRegs */
6646 NullRegClasses,
6647 nullptr
6648 };
6649
6650 extern const TargetRegisterClass CRRCRegClass = {
6651 &PPCMCRegisterClasses[CRRCRegClassID],
6652 CRRCSubClassMask,
6653 SuperRegIdxSeqs + 2,
6654 LaneBitmask(0x0000000000000E40),
6655 0,
6656 false,
6657 0x00, /* TSFlags */
6658 true, /* HasDisjunctSubRegs */
6659 false, /* CoveredBySubRegs */
6660 NullRegClasses,
6661 CRRCGetRawAllocationOrder
6662 };
6663
6664 extern const TargetRegisterClass CARRYRCRegClass = {
6665 &PPCMCRegisterClasses[CARRYRCRegClassID],
6666 CARRYRCSubClassMask,
6667 SuperRegIdxSeqs + 2,
6668 LaneBitmask(0x0000000000000001),
6669 0,
6670 false,
6671 0x00, /* TSFlags */
6672 false, /* HasDisjunctSubRegs */
6673 false, /* CoveredBySubRegs */
6674 NullRegClasses,
6675 nullptr
6676 };
6677
6678 extern const TargetRegisterClass CTRRCRegClass = {
6679 &PPCMCRegisterClasses[CTRRCRegClassID],
6680 CTRRCSubClassMask,
6681 SuperRegIdxSeqs + 2,
6682 LaneBitmask(0x0000000000000001),
6683 0,
6684 false,
6685 0x00, /* TSFlags */
6686 false, /* HasDisjunctSubRegs */
6687 false, /* CoveredBySubRegs */
6688 NullRegClasses,
6689 nullptr
6690 };
6691
6692 extern const TargetRegisterClass LRRCRegClass = {
6693 &PPCMCRegisterClasses[LRRCRegClassID],
6694 LRRCSubClassMask,
6695 SuperRegIdxSeqs + 2,
6696 LaneBitmask(0x0000000000000001),
6697 0,
6698 false,
6699 0x00, /* TSFlags */
6700 false, /* HasDisjunctSubRegs */
6701 false, /* CoveredBySubRegs */
6702 NullRegClasses,
6703 nullptr
6704 };
6705
6706 extern const TargetRegisterClass VRSAVERCRegClass = {
6707 &PPCMCRegisterClasses[VRSAVERCRegClassID],
6708 VRSAVERCSubClassMask,
6709 SuperRegIdxSeqs + 2,
6710 LaneBitmask(0x0000000000000001),
6711 0,
6712 false,
6713 0x00, /* TSFlags */
6714 false, /* HasDisjunctSubRegs */
6715 false, /* CoveredBySubRegs */
6716 NullRegClasses,
6717 nullptr
6718 };
6719
6720 extern const TargetRegisterClass SPILLTOVSRRCRegClass = {
6721 &PPCMCRegisterClasses[SPILLTOVSRRCRegClassID],
6722 SPILLTOVSRRCSubClassMask,
6723 SuperRegIdxSeqs + 32,
6724 LaneBitmask(0x0000000000000001),
6725 0,
6726 false,
6727 0x00, /* TSFlags */
6728 false, /* HasDisjunctSubRegs */
6729 false, /* CoveredBySubRegs */
6730 NullRegClasses,
6731 nullptr
6732 };
6733
6734 extern const TargetRegisterClass VSFRCRegClass = {
6735 &PPCMCRegisterClasses[VSFRCRegClassID],
6736 VSFRCSubClassMask,
6737 SuperRegIdxSeqs + 25,
6738 LaneBitmask(0x0000000000000001),
6739 0,
6740 false,
6741 0x00, /* TSFlags */
6742 false, /* HasDisjunctSubRegs */
6743 false, /* CoveredBySubRegs */
6744 VSFRCSuperclasses,
6745 nullptr
6746 };
6747
6748 extern const TargetRegisterClass G8RCRegClass = {
6749 &PPCMCRegisterClasses[G8RCRegClassID],
6750 G8RCSubClassMask,
6751 SuperRegIdxSeqs + 3,
6752 LaneBitmask(0x0000000000000001),
6753 0,
6754 false,
6755 0x00, /* TSFlags */
6756 false, /* HasDisjunctSubRegs */
6757 false, /* CoveredBySubRegs */
6758 G8RCSuperclasses,
6759 G8RCGetRawAllocationOrder
6760 };
6761
6762 extern const TargetRegisterClass G8RC_NOX0RegClass = {
6763 &PPCMCRegisterClasses[G8RC_NOX0RegClassID],
6764 G8RC_NOX0SubClassMask,
6765 SuperRegIdxSeqs + 3,
6766 LaneBitmask(0x0000000000000001),
6767 0,
6768 false,
6769 0x00, /* TSFlags */
6770 false, /* HasDisjunctSubRegs */
6771 false, /* CoveredBySubRegs */
6772 NullRegClasses,
6773 G8RC_NOX0GetRawAllocationOrder
6774 };
6775
6776 extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = {
6777 &PPCMCRegisterClasses[SPILLTOVSRRC_and_VSFRCRegClassID],
6778 SPILLTOVSRRC_and_VSFRCSubClassMask,
6779 SuperRegIdxSeqs + 25,
6780 LaneBitmask(0x0000000000000001),
6781 0,
6782 false,
6783 0x00, /* TSFlags */
6784 false, /* HasDisjunctSubRegs */
6785 false, /* CoveredBySubRegs */
6786 SPILLTOVSRRC_and_VSFRCSuperclasses,
6787 nullptr
6788 };
6789
6790 extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = {
6791 &PPCMCRegisterClasses[G8RC_and_G8RC_NOX0RegClassID],
6792 G8RC_and_G8RC_NOX0SubClassMask,
6793 SuperRegIdxSeqs + 3,
6794 LaneBitmask(0x0000000000000001),
6795 0,
6796 false,
6797 0x00, /* TSFlags */
6798 false, /* HasDisjunctSubRegs */
6799 false, /* CoveredBySubRegs */
6800 G8RC_and_G8RC_NOX0Superclasses,
6801 G8RC_and_G8RC_NOX0GetRawAllocationOrder
6802 };
6803
6804 extern const TargetRegisterClass F8RCRegClass = {
6805 &PPCMCRegisterClasses[F8RCRegClassID],
6806 F8RCSubClassMask,
6807 SuperRegIdxSeqs + 25,
6808 LaneBitmask(0x0000000000000001),
6809 0,
6810 false,
6811 0x00, /* TSFlags */
6812 false, /* HasDisjunctSubRegs */
6813 false, /* CoveredBySubRegs */
6814 F8RCSuperclasses,
6815 nullptr
6816 };
6817
6818 extern const TargetRegisterClass FHRCRegClass = {
6819 &PPCMCRegisterClasses[FHRCRegClassID],
6820 FHRCSubClassMask,
6821 SuperRegIdxSeqs + 2,
6822 LaneBitmask(0x0000000000000001),
6823 0,
6824 false,
6825 0x00, /* TSFlags */
6826 false, /* HasDisjunctSubRegs */
6827 false, /* CoveredBySubRegs */
6828 NullRegClasses,
6829 nullptr
6830 };
6831
6832 extern const TargetRegisterClass SPERCRegClass = {
6833 &PPCMCRegisterClasses[SPERCRegClassID],
6834 SPERCSubClassMask,
6835 SuperRegIdxSeqs + 2,
6836 LaneBitmask(0x0000000000000001),
6837 0,
6838 false,
6839 0x00, /* TSFlags */
6840 true, /* HasDisjunctSubRegs */
6841 true, /* CoveredBySubRegs */
6842 NullRegClasses,
6843 nullptr
6844 };
6845
6846 extern const TargetRegisterClass VFHRCRegClass = {
6847 &PPCMCRegisterClasses[VFHRCRegClassID],
6848 VFHRCSubClassMask,
6849 SuperRegIdxSeqs + 2,
6850 LaneBitmask(0x0000000000000001),
6851 0,
6852 false,
6853 0x00, /* TSFlags */
6854 false, /* HasDisjunctSubRegs */
6855 false, /* CoveredBySubRegs */
6856 NullRegClasses,
6857 nullptr
6858 };
6859
6860 extern const TargetRegisterClass VFRCRegClass = {
6861 &PPCMCRegisterClasses[VFRCRegClassID],
6862 VFRCSubClassMask,
6863 SuperRegIdxSeqs + 17,
6864 LaneBitmask(0x0000000000000001),
6865 0,
6866 false,
6867 0x00, /* TSFlags */
6868 false, /* HasDisjunctSubRegs */
6869 false, /* CoveredBySubRegs */
6870 VFRCSuperclasses,
6871 nullptr
6872 };
6873
6874 extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = {
6875 &PPCMCRegisterClasses[SPERC_with_sub_32_in_GPRC_NOR0RegClassID],
6876 SPERC_with_sub_32_in_GPRC_NOR0SubClassMask,
6877 SuperRegIdxSeqs + 2,
6878 LaneBitmask(0x0000000000000001),
6879 0,
6880 false,
6881 0x00, /* TSFlags */
6882 true, /* HasDisjunctSubRegs */
6883 true, /* CoveredBySubRegs */
6884 SPERC_with_sub_32_in_GPRC_NOR0Superclasses,
6885 nullptr
6886 };
6887
6888 extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = {
6889 &PPCMCRegisterClasses[SPILLTOVSRRC_and_VFRCRegClassID],
6890 SPILLTOVSRRC_and_VFRCSubClassMask,
6891 SuperRegIdxSeqs + 17,
6892 LaneBitmask(0x0000000000000001),
6893 0,
6894 false,
6895 0x00, /* TSFlags */
6896 false, /* HasDisjunctSubRegs */
6897 false, /* CoveredBySubRegs */
6898 SPILLTOVSRRC_and_VFRCSuperclasses,
6899 nullptr
6900 };
6901
6902 extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = {
6903 &PPCMCRegisterClasses[SPILLTOVSRRC_and_F4RCRegClassID],
6904 SPILLTOVSRRC_and_F4RCSubClassMask,
6905 SuperRegIdxSeqs + 25,
6906 LaneBitmask(0x0000000000000001),
6907 0,
6908 false,
6909 0x00, /* TSFlags */
6910 false, /* HasDisjunctSubRegs */
6911 false, /* CoveredBySubRegs */
6912 SPILLTOVSRRC_and_F4RCSuperclasses,
6913 nullptr
6914 };
6915
6916 extern const TargetRegisterClass CTRRC8RegClass = {
6917 &PPCMCRegisterClasses[CTRRC8RegClassID],
6918 CTRRC8SubClassMask,
6919 SuperRegIdxSeqs + 2,
6920 LaneBitmask(0x0000000000000001),
6921 0,
6922 false,
6923 0x00, /* TSFlags */
6924 false, /* HasDisjunctSubRegs */
6925 false, /* CoveredBySubRegs */
6926 NullRegClasses,
6927 nullptr
6928 };
6929
6930 extern const TargetRegisterClass LR8RCRegClass = {
6931 &PPCMCRegisterClasses[LR8RCRegClassID],
6932 LR8RCSubClassMask,
6933 SuperRegIdxSeqs + 2,
6934 LaneBitmask(0x0000000000000001),
6935 0,
6936 false,
6937 0x00, /* TSFlags */
6938 false, /* HasDisjunctSubRegs */
6939 false, /* CoveredBySubRegs */
6940 NullRegClasses,
6941 nullptr
6942 };
6943
6944 extern const TargetRegisterClass DMRROWRCRegClass = {
6945 &PPCMCRegisterClasses[DMRROWRCRegClassID],
6946 DMRROWRCSubClassMask,
6947 SuperRegIdxSeqs + 56,
6948 LaneBitmask(0x0000000000000001),
6949 0,
6950 false,
6951 0x00, /* TSFlags */
6952 false, /* HasDisjunctSubRegs */
6953 false, /* CoveredBySubRegs */
6954 NullRegClasses,
6955 nullptr
6956 };
6957
6958 extern const TargetRegisterClass VSRCRegClass = {
6959 &PPCMCRegisterClasses[VSRCRegClassID],
6960 VSRCSubClassMask,
6961 SuperRegIdxSeqs + 20,
6962 LaneBitmask(0x0000000000000004),
6963 0,
6964 false,
6965 0x00, /* TSFlags */
6966 true, /* HasDisjunctSubRegs */
6967 true, /* CoveredBySubRegs */
6968 NullRegClasses,
6969 nullptr
6970 };
6971
6972 extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6973 &PPCMCRegisterClasses[VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6974 VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6975 SuperRegIdxSeqs + 20,
6976 LaneBitmask(0x0000000000000004),
6977 0,
6978 false,
6979 0x00, /* TSFlags */
6980 true, /* HasDisjunctSubRegs */
6981 true, /* CoveredBySubRegs */
6982 VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6983 nullptr
6984 };
6985
6986 extern const TargetRegisterClass VRRCRegClass = {
6987 &PPCMCRegisterClasses[VRRCRegClassID],
6988 VRRCSubClassMask,
6989 SuperRegIdxSeqs + 14,
6990 LaneBitmask(0x0000000000000004),
6991 0,
6992 false,
6993 0x00, /* TSFlags */
6994 true, /* HasDisjunctSubRegs */
6995 true, /* CoveredBySubRegs */
6996 VRRCSuperclasses,
6997 nullptr
6998 };
6999
7000 extern const TargetRegisterClass VSLRCRegClass = {
7001 &PPCMCRegisterClasses[VSLRCRegClassID],
7002 VSLRCSubClassMask,
7003 SuperRegIdxSeqs + 20,
7004 LaneBitmask(0x0000000000000004),
7005 0,
7006 false,
7007 0x00, /* TSFlags */
7008 true, /* HasDisjunctSubRegs */
7009 true, /* CoveredBySubRegs */
7010 VSLRCSuperclasses,
7011 nullptr
7012 };
7013
7014 extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7015 &PPCMCRegisterClasses[VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7016 VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7017 SuperRegIdxSeqs + 14,
7018 LaneBitmask(0x0000000000000004),
7019 0,
7020 false,
7021 0x00, /* TSFlags */
7022 true, /* HasDisjunctSubRegs */
7023 true, /* CoveredBySubRegs */
7024 VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
7025 nullptr
7026 };
7027
7028 extern const TargetRegisterClass FpRCRegClass = {
7029 &PPCMCRegisterClasses[FpRCRegClassID],
7030 FpRCSubClassMask,
7031 SuperRegIdxSeqs + 2,
7032 LaneBitmask(0x0000000000000180),
7033 0,
7034 false,
7035 0x00, /* TSFlags */
7036 true, /* HasDisjunctSubRegs */
7037 false, /* CoveredBySubRegs */
7038 NullRegClasses,
7039 nullptr
7040 };
7041
7042 extern const TargetRegisterClass G8pRCRegClass = {
7043 &PPCMCRegisterClasses[G8pRCRegClassID],
7044 G8pRCSubClassMask,
7045 SuperRegIdxSeqs + 2,
7046 LaneBitmask(0x0000000100000001),
7047 0,
7048 false,
7049 0x00, /* TSFlags */
7050 true, /* HasDisjunctSubRegs */
7051 false, /* CoveredBySubRegs */
7052 NullRegClasses,
7053 G8pRCGetRawAllocationOrder
7054 };
7055
7056 extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass = {
7057 &PPCMCRegisterClasses[G8pRC_with_sub_32_in_GPRC_NOR0RegClassID],
7058 G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask,
7059 SuperRegIdxSeqs + 2,
7060 LaneBitmask(0x0000000100000001),
7061 0,
7062 false,
7063 0x00, /* TSFlags */
7064 true, /* HasDisjunctSubRegs */
7065 false, /* CoveredBySubRegs */
7066 G8pRC_with_sub_32_in_GPRC_NOR0Superclasses,
7067 G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder
7068 };
7069
7070 extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7071 &PPCMCRegisterClasses[VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7072 VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7073 SuperRegIdxSeqs + 20,
7074 LaneBitmask(0x0000000000000004),
7075 0,
7076 false,
7077 0x00, /* TSFlags */
7078 true, /* HasDisjunctSubRegs */
7079 true, /* CoveredBySubRegs */
7080 VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
7081 nullptr
7082 };
7083
7084 extern const TargetRegisterClass FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass = {
7085 &PPCMCRegisterClasses[FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID],
7086 FpRC_with_sub_fp0_in_SPILLTOVSRRCSubClassMask,
7087 SuperRegIdxSeqs + 2,
7088 LaneBitmask(0x0000000000000180),
7089 0,
7090 false,
7091 0x00, /* TSFlags */
7092 true, /* HasDisjunctSubRegs */
7093 false, /* CoveredBySubRegs */
7094 FpRC_with_sub_fp0_in_SPILLTOVSRRCSuperclasses,
7095 nullptr
7096 };
7097
7098 extern const TargetRegisterClass DMRROWpRCRegClass = {
7099 &PPCMCRegisterClasses[DMRROWpRCRegClassID],
7100 DMRROWpRCSubClassMask,
7101 SuperRegIdxSeqs + 47,
7102 LaneBitmask(0x0000000000000030),
7103 0,
7104 false,
7105 0x00, /* TSFlags */
7106 true, /* HasDisjunctSubRegs */
7107 false, /* CoveredBySubRegs */
7108 NullRegClasses,
7109 nullptr
7110 };
7111
7112 extern const TargetRegisterClass VSRpRCRegClass = {
7113 &PPCMCRegisterClasses[VSRpRCRegClassID],
7114 VSRpRCSubClassMask,
7115 SuperRegIdxSeqs + 6,
7116 LaneBitmask(0x000000000000300C),
7117 2,
7118 false,
7119 0x00, /* TSFlags */
7120 true, /* HasDisjunctSubRegs */
7121 false, /* CoveredBySubRegs */
7122 NullRegClasses,
7123 nullptr
7124 };
7125
7126 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7127 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7128 VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7129 SuperRegIdxSeqs + 6,
7130 LaneBitmask(0x000000000000300C),
7131 2,
7132 false,
7133 0x00, /* TSFlags */
7134 true, /* HasDisjunctSubRegs */
7135 false, /* CoveredBySubRegs */
7136 VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
7137 nullptr
7138 };
7139
7140 extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass = {
7141 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_F4RCRegClassID],
7142 VSRpRC_with_sub_64_in_F4RCSubClassMask,
7143 SuperRegIdxSeqs + 6,
7144 LaneBitmask(0x000000000000300C),
7145 2,
7146 false,
7147 0x00, /* TSFlags */
7148 true, /* HasDisjunctSubRegs */
7149 false, /* CoveredBySubRegs */
7150 VSRpRC_with_sub_64_in_F4RCSuperclasses,
7151 nullptr
7152 };
7153
7154 extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass = {
7155 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_VFRCRegClassID],
7156 VSRpRC_with_sub_64_in_VFRCSubClassMask,
7157 SuperRegIdxSeqs + 2,
7158 LaneBitmask(0x000000000000300C),
7159 2,
7160 false,
7161 0x00, /* TSFlags */
7162 true, /* HasDisjunctSubRegs */
7163 false, /* CoveredBySubRegs */
7164 VSRpRC_with_sub_64_in_VFRCSuperclasses,
7165 nullptr
7166 };
7167
7168 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass = {
7169 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID],
7170 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask,
7171 SuperRegIdxSeqs + 2,
7172 LaneBitmask(0x000000000000300C),
7173 2,
7174 false,
7175 0x00, /* TSFlags */
7176 true, /* HasDisjunctSubRegs */
7177 false, /* CoveredBySubRegs */
7178 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses,
7179 nullptr
7180 };
7181
7182 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass = {
7183 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID],
7184 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask,
7185 SuperRegIdxSeqs + 6,
7186 LaneBitmask(0x000000000000300C),
7187 2,
7188 false,
7189 0x00, /* TSFlags */
7190 true, /* HasDisjunctSubRegs */
7191 false, /* CoveredBySubRegs */
7192 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses,
7193 nullptr
7194 };
7195
7196 extern const TargetRegisterClass ACCRCRegClass = {
7197 &PPCMCRegisterClasses[ACCRCRegClassID],
7198 ACCRCSubClassMask,
7199 SuperRegIdxSeqs + 2,
7200 LaneBitmask(0x000000000003F00C),
7201 31,
7202 true,
7203 0x00, /* TSFlags */
7204 true, /* HasDisjunctSubRegs */
7205 false, /* CoveredBySubRegs */
7206 NullRegClasses,
7207 nullptr
7208 };
7209
7210 extern const TargetRegisterClass UACCRCRegClass = {
7211 &PPCMCRegisterClasses[UACCRCRegClassID],
7212 UACCRCSubClassMask,
7213 SuperRegIdxSeqs + 2,
7214 LaneBitmask(0x000000000003F00C),
7215 4,
7216 true,
7217 0x00, /* TSFlags */
7218 true, /* HasDisjunctSubRegs */
7219 false, /* CoveredBySubRegs */
7220 NullRegClasses,
7221 nullptr
7222 };
7223
7224 extern const TargetRegisterClass WACCRCRegClass = {
7225 &PPCMCRegisterClasses[WACCRCRegClassID],
7226 WACCRCSubClassMask,
7227 SuperRegIdxSeqs + 44,
7228 LaneBitmask(0x00000000000C0030),
7229 0,
7230 false,
7231 0x00, /* TSFlags */
7232 true, /* HasDisjunctSubRegs */
7233 false, /* CoveredBySubRegs */
7234 NullRegClasses,
7235 nullptr
7236 };
7237
7238 extern const TargetRegisterClass WACC_HIRCRegClass = {
7239 &PPCMCRegisterClasses[WACC_HIRCRegClassID],
7240 WACC_HIRCSubClassMask,
7241 SuperRegIdxSeqs + 41,
7242 LaneBitmask(0x00000000000C0030),
7243 0,
7244 false,
7245 0x00, /* TSFlags */
7246 true, /* HasDisjunctSubRegs */
7247 false, /* CoveredBySubRegs */
7248 NullRegClasses,
7249 nullptr
7250 };
7251
7252 extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7253 &PPCMCRegisterClasses[ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7254 ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7255 SuperRegIdxSeqs + 2,
7256 LaneBitmask(0x000000000003F00C),
7257 31,
7258 true,
7259 0x00, /* TSFlags */
7260 true, /* HasDisjunctSubRegs */
7261 false, /* CoveredBySubRegs */
7262 ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
7263 nullptr
7264 };
7265
7266 extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7267 &PPCMCRegisterClasses[UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7268 UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7269 SuperRegIdxSeqs + 2,
7270 LaneBitmask(0x000000000003F00C),
7271 4,
7272 true,
7273 0x00, /* TSFlags */
7274 true, /* HasDisjunctSubRegs */
7275 false, /* CoveredBySubRegs */
7276 UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
7277 nullptr
7278 };
7279
7280 extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
7281 &PPCMCRegisterClasses[ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
7282 ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
7283 SuperRegIdxSeqs + 2,
7284 LaneBitmask(0x000000000003F00C),
7285 31,
7286 true,
7287 0x00, /* TSFlags */
7288 true, /* HasDisjunctSubRegs */
7289 false, /* CoveredBySubRegs */
7290 ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
7291 nullptr
7292 };
7293
7294 extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
7295 &PPCMCRegisterClasses[UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
7296 UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
7297 SuperRegIdxSeqs + 2,
7298 LaneBitmask(0x000000000003F00C),
7299 4,
7300 true,
7301 0x00, /* TSFlags */
7302 true, /* HasDisjunctSubRegs */
7303 false, /* CoveredBySubRegs */
7304 UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
7305 nullptr
7306 };
7307
7308 extern const TargetRegisterClass DMRRCRegClass = {
7309 &PPCMCRegisterClasses[DMRRCRegClassID],
7310 DMRRCSubClassMask,
7311 SuperRegIdxSeqs + 0,
7312 LaneBitmask(0x0000000000FC0030),
7313 0,
7314 false,
7315 0x00, /* TSFlags */
7316 true, /* HasDisjunctSubRegs */
7317 false, /* CoveredBySubRegs */
7318 NullRegClasses,
7319 nullptr
7320 };
7321
7322 extern const TargetRegisterClass DMRpRCRegClass = {
7323 &PPCMCRegisterClasses[DMRpRCRegClassID],
7324 DMRpRCSubClassMask,
7325 SuperRegIdxSeqs + 2,
7326 LaneBitmask(0x00000000FFFC0030),
7327 0,
7328 false,
7329 0x00, /* TSFlags */
7330 true, /* HasDisjunctSubRegs */
7331 false, /* CoveredBySubRegs */
7332 NullRegClasses,
7333 nullptr
7334 };
7335
7336} // end namespace PPC
7337
7338namespace {
7339 const TargetRegisterClass *const RegisterClasses[] = {
7340 &PPC::VSSRCRegClass,
7341 &PPC::GPRCRegClass,
7342 &PPC::GPRC_NOR0RegClass,
7343 &PPC::GPRC_and_GPRC_NOR0RegClass,
7344 &PPC::CRBITRCRegClass,
7345 &PPC::F4RCRegClass,
7346 &PPC::GPRC32RegClass,
7347 &PPC::CRRCRegClass,
7348 &PPC::CARRYRCRegClass,
7349 &PPC::CTRRCRegClass,
7350 &PPC::LRRCRegClass,
7351 &PPC::VRSAVERCRegClass,
7352 &PPC::SPILLTOVSRRCRegClass,
7353 &PPC::VSFRCRegClass,
7354 &PPC::G8RCRegClass,
7355 &PPC::G8RC_NOX0RegClass,
7356 &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
7357 &PPC::G8RC_and_G8RC_NOX0RegClass,
7358 &PPC::F8RCRegClass,
7359 &PPC::FHRCRegClass,
7360 &PPC::SPERCRegClass,
7361 &PPC::VFHRCRegClass,
7362 &PPC::VFRCRegClass,
7363 &PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClass,
7364 &PPC::SPILLTOVSRRC_and_VFRCRegClass,
7365 &PPC::SPILLTOVSRRC_and_F4RCRegClass,
7366 &PPC::CTRRC8RegClass,
7367 &PPC::LR8RCRegClass,
7368 &PPC::DMRROWRCRegClass,
7369 &PPC::VSRCRegClass,
7370 &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7371 &PPC::VRRCRegClass,
7372 &PPC::VSLRCRegClass,
7373 &PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7374 &PPC::FpRCRegClass,
7375 &PPC::G8pRCRegClass,
7376 &PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClass,
7377 &PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7378 &PPC::FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass,
7379 &PPC::DMRROWpRCRegClass,
7380 &PPC::VSRpRCRegClass,
7381 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7382 &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
7383 &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
7384 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass,
7385 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass,
7386 &PPC::ACCRCRegClass,
7387 &PPC::UACCRCRegClass,
7388 &PPC::WACCRCRegClass,
7389 &PPC::WACC_HIRCRegClass,
7390 &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7391 &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7392 &PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
7393 &PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
7394 &PPC::DMRRCRegClass,
7395 &PPC::DMRpRCRegClass,
7396 };
7397} // end anonymous namespace
7398
7399static const uint8_t CostPerUseTable[] = {
74000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
7401
7402
7403static const bool InAllocatableClassTable[] = {
7404false, true, true, false, true, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
7405
7406
7407static const TargetRegisterInfoDesc PPCRegInfoDesc = { // Extra Descriptors
7408CostPerUseTable, 1, InAllocatableClassTable};
7409
7410unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
7411 static const uint8_t RowMap[55] = {
7412 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 2, 3, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 1, 5, 6, 1, 0, 0, 0, 0, 6, 7, 0, 0, 0,
7413 };
7414 static const uint8_t Rows[8][55] = {
7415 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7416 { PPC::sub_gp8_x1_then_sub_32, 0, PPC::sub_pair1_then_sub_64, PPC::sub_pair1_then_sub_64_hi_phony, 0, 0, PPC::sub_dmr1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_pair1_then_sub_vsx0, PPC::sub_pair1_then_sub_vsx1, PPC::sub_dmr1_then_sub_wacc_hi, PPC::sub_dmr1_then_sub_wacc_lo, PPC::sub_pair1_then_sub_vsx1_then_sub_64, PPC::sub_pair1_then_sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7417 { 0, 0, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7418 { 0, 0, PPC::sub_pair1_then_sub_vsx1_then_sub_64, PPC::sub_pair1_then_sub_vsx1_then_sub_64_hi_phony, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7419 { 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7420 { 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7421 { 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7422 { 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7423 };
7424
7425 --IdxA; assert(IdxA < 55); (void) IdxA;
7426 --IdxB; assert(IdxB < 55);
7427 return Rows[RowMap[IdxA]][IdxB];
7428}
7429
7430 struct MaskRolOp {
7431 LaneBitmask Mask;
7432 uint8_t RotateLeft;
7433 };
7434 static const MaskRolOp LaneMaskComposeSequences[] = {
7435 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
7436 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
7437 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
7438 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
7439 { LaneBitmask(0x0000000000000030), 20 }, { LaneBitmask(0x0000000000FC0000), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
7440 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 11
7441 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 13
7442 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 15
7443 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 17
7444 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 19
7445 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 21
7446 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 32 }, { LaneBitmask::getNone(), 0 }, // Sequence 23
7447 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 25
7448 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 27
7449 { LaneBitmask(0x000000000000000C), 12 }, { LaneBitmask(0x0000000000003000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 29
7450 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 32
7451 { LaneBitmask(0x0000000000000030), 16 }, { LaneBitmask(0x00000000000C0000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 34
7452 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 37
7453 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 39
7454 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 41
7455 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 43
7456 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }, // Sequence 45
7457 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 47
7458 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 }, // Sequence 49
7459 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 20 }, { LaneBitmask::getNone(), 0 }, // Sequence 51
7460 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 21 }, { LaneBitmask::getNone(), 0 }, // Sequence 53
7461 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 22 }, { LaneBitmask::getNone(), 0 }, // Sequence 55
7462 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 23 }, { LaneBitmask::getNone(), 0 }, // Sequence 57
7463 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 24 }, { LaneBitmask::getNone(), 0 }, // Sequence 59
7464 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 25 }, { LaneBitmask::getNone(), 0 }, // Sequence 61
7465 { LaneBitmask(0x0000000000000030), 24 }, { LaneBitmask(0x00000000000C0000), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 63
7466 { LaneBitmask(0x0000000000000030), 20 }, { LaneBitmask(0x00000000000C0000), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 66
7467 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 26 }, { LaneBitmask::getNone(), 0 }, // Sequence 69
7468 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 27 }, { LaneBitmask::getNone(), 0 }, // Sequence 71
7469 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 28 }, { LaneBitmask::getNone(), 0 }, // Sequence 73
7470 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 29 }, { LaneBitmask::getNone(), 0 }, // Sequence 75
7471 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 30 }, { LaneBitmask::getNone(), 0 }, // Sequence 77
7472 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 31 }, { LaneBitmask::getNone(), 0 } // Sequence 79
7473 };
7474 static const uint8_t CompositeSequences[] = {
7475 0, // to sub_32
7476 2, // to sub_32_hi_phony
7477 4, // to sub_64
7478 6, // to sub_64_hi_phony
7479 0, // to sub_dmr0
7480 8, // to sub_dmr1
7481 11, // to sub_dmrrow0
7482 13, // to sub_dmrrow1
7483 0, // to sub_dmrrowp0
7484 15, // to sub_dmrrowp1
7485 17, // to sub_eq
7486 19, // to sub_fp0
7487 21, // to sub_fp1
7488 0, // to sub_gp8_x0
7489 23, // to sub_gp8_x1
7490 25, // to sub_gt
7491 27, // to sub_lt
7492 0, // to sub_pair0
7493 29, // to sub_pair1
7494 32, // to sub_un
7495 0, // to sub_vsx0
7496 27, // to sub_vsx1
7497 34, // to sub_wacc_hi
7498 0, // to sub_wacc_lo
7499 37, // to sub_vsx1_then_sub_64
7500 39, // to sub_vsx1_then_sub_64_hi_phony
7501 15, // to sub_pair1_then_sub_64
7502 41, // to sub_pair1_then_sub_64_hi_phony
7503 37, // to sub_pair1_then_sub_vsx0
7504 15, // to sub_pair1_then_sub_vsx1
7505 43, // to sub_pair1_then_sub_vsx1_then_sub_64
7506 45, // to sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7507 47, // to sub_dmrrowp1_then_sub_dmrrow0
7508 49, // to sub_dmrrowp1_then_sub_dmrrow1
7509 51, // to sub_wacc_hi_then_sub_dmrrow0
7510 53, // to sub_wacc_hi_then_sub_dmrrow1
7511 43, // to sub_wacc_hi_then_sub_dmrrowp0
7512 47, // to sub_wacc_hi_then_sub_dmrrowp1
7513 55, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7514 57, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7515 59, // to sub_dmr1_then_sub_dmrrow0
7516 61, // to sub_dmr1_then_sub_dmrrow1
7517 51, // to sub_dmr1_then_sub_dmrrowp0
7518 55, // to sub_dmr1_then_sub_dmrrowp1
7519 63, // to sub_dmr1_then_sub_wacc_hi
7520 66, // to sub_dmr1_then_sub_wacc_lo
7521 69, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7522 71, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7523 73, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7524 75, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7525 59, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7526 69, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7527 77, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7528 79, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7529 23 // to sub_gp8_x1_then_sub_32
7530 };
7531
7532LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
7533 --IdxA; assert(IdxA < 55 && "Subregister index out of bounds");
7534 LaneBitmask Result;
7535 for (const MaskRolOp *Ops =
7536 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
7537 Ops->Mask.any(); ++Ops) {
7538 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
7539 if (unsigned S = Ops->RotateLeft)
7540 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
7541 else
7542 Result |= LaneBitmask(M);
7543 }
7544 return Result;
7545}
7546
7547LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
7548 LaneMask &= getSubRegIndexLaneMask(IdxA);
7549 --IdxA; assert(IdxA < 55 && "Subregister index out of bounds");
7550 LaneBitmask Result;
7551 for (const MaskRolOp *Ops =
7552 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
7553 Ops->Mask.any(); ++Ops) {
7554 LaneBitmask::Type M = LaneMask.getAsInteger();
7555 if (unsigned S = Ops->RotateLeft)
7556 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
7557 else
7558 Result |= LaneBitmask(M);
7559 }
7560 return Result;
7561}
7562
7563const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
7564 static const uint8_t Table[56][55] = {
7565 { // VSSRC
7566 0, // sub_32
7567 0, // sub_32_hi_phony
7568 0, // sub_64
7569 0, // sub_64_hi_phony
7570 0, // sub_dmr0
7571 0, // sub_dmr1
7572 0, // sub_dmrrow0
7573 0, // sub_dmrrow1
7574 0, // sub_dmrrowp0
7575 0, // sub_dmrrowp1
7576 0, // sub_eq
7577 0, // sub_fp0
7578 0, // sub_fp1
7579 0, // sub_gp8_x0
7580 0, // sub_gp8_x1
7581 0, // sub_gt
7582 0, // sub_lt
7583 0, // sub_pair0
7584 0, // sub_pair1
7585 0, // sub_un
7586 0, // sub_vsx0
7587 0, // sub_vsx1
7588 0, // sub_wacc_hi
7589 0, // sub_wacc_lo
7590 0, // sub_vsx1_then_sub_64
7591 0, // sub_vsx1_then_sub_64_hi_phony
7592 0, // sub_pair1_then_sub_64
7593 0, // sub_pair1_then_sub_64_hi_phony
7594 0, // sub_pair1_then_sub_vsx0
7595 0, // sub_pair1_then_sub_vsx1
7596 0, // sub_pair1_then_sub_vsx1_then_sub_64
7597 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7598 0, // sub_dmrrowp1_then_sub_dmrrow0
7599 0, // sub_dmrrowp1_then_sub_dmrrow1
7600 0, // sub_wacc_hi_then_sub_dmrrow0
7601 0, // sub_wacc_hi_then_sub_dmrrow1
7602 0, // sub_wacc_hi_then_sub_dmrrowp0
7603 0, // sub_wacc_hi_then_sub_dmrrowp1
7604 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7605 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7606 0, // sub_dmr1_then_sub_dmrrow0
7607 0, // sub_dmr1_then_sub_dmrrow1
7608 0, // sub_dmr1_then_sub_dmrrowp0
7609 0, // sub_dmr1_then_sub_dmrrowp1
7610 0, // sub_dmr1_then_sub_wacc_hi
7611 0, // sub_dmr1_then_sub_wacc_lo
7612 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7613 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7614 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7615 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7616 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7617 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7618 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7619 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7620 0, // sub_gp8_x1_then_sub_32
7621 },
7622 { // GPRC
7623 0, // sub_32
7624 0, // sub_32_hi_phony
7625 0, // sub_64
7626 0, // sub_64_hi_phony
7627 0, // sub_dmr0
7628 0, // sub_dmr1
7629 0, // sub_dmrrow0
7630 0, // sub_dmrrow1
7631 0, // sub_dmrrowp0
7632 0, // sub_dmrrowp1
7633 0, // sub_eq
7634 0, // sub_fp0
7635 0, // sub_fp1
7636 0, // sub_gp8_x0
7637 0, // sub_gp8_x1
7638 0, // sub_gt
7639 0, // sub_lt
7640 0, // sub_pair0
7641 0, // sub_pair1
7642 0, // sub_un
7643 0, // sub_vsx0
7644 0, // sub_vsx1
7645 0, // sub_wacc_hi
7646 0, // sub_wacc_lo
7647 0, // sub_vsx1_then_sub_64
7648 0, // sub_vsx1_then_sub_64_hi_phony
7649 0, // sub_pair1_then_sub_64
7650 0, // sub_pair1_then_sub_64_hi_phony
7651 0, // sub_pair1_then_sub_vsx0
7652 0, // sub_pair1_then_sub_vsx1
7653 0, // sub_pair1_then_sub_vsx1_then_sub_64
7654 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7655 0, // sub_dmrrowp1_then_sub_dmrrow0
7656 0, // sub_dmrrowp1_then_sub_dmrrow1
7657 0, // sub_wacc_hi_then_sub_dmrrow0
7658 0, // sub_wacc_hi_then_sub_dmrrow1
7659 0, // sub_wacc_hi_then_sub_dmrrowp0
7660 0, // sub_wacc_hi_then_sub_dmrrowp1
7661 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7662 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7663 0, // sub_dmr1_then_sub_dmrrow0
7664 0, // sub_dmr1_then_sub_dmrrow1
7665 0, // sub_dmr1_then_sub_dmrrowp0
7666 0, // sub_dmr1_then_sub_dmrrowp1
7667 0, // sub_dmr1_then_sub_wacc_hi
7668 0, // sub_dmr1_then_sub_wacc_lo
7669 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7670 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7671 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7672 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7673 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7674 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7675 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7676 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7677 0, // sub_gp8_x1_then_sub_32
7678 },
7679 { // GPRC_NOR0
7680 0, // sub_32
7681 0, // sub_32_hi_phony
7682 0, // sub_64
7683 0, // sub_64_hi_phony
7684 0, // sub_dmr0
7685 0, // sub_dmr1
7686 0, // sub_dmrrow0
7687 0, // sub_dmrrow1
7688 0, // sub_dmrrowp0
7689 0, // sub_dmrrowp1
7690 0, // sub_eq
7691 0, // sub_fp0
7692 0, // sub_fp1
7693 0, // sub_gp8_x0
7694 0, // sub_gp8_x1
7695 0, // sub_gt
7696 0, // sub_lt
7697 0, // sub_pair0
7698 0, // sub_pair1
7699 0, // sub_un
7700 0, // sub_vsx0
7701 0, // sub_vsx1
7702 0, // sub_wacc_hi
7703 0, // sub_wacc_lo
7704 0, // sub_vsx1_then_sub_64
7705 0, // sub_vsx1_then_sub_64_hi_phony
7706 0, // sub_pair1_then_sub_64
7707 0, // sub_pair1_then_sub_64_hi_phony
7708 0, // sub_pair1_then_sub_vsx0
7709 0, // sub_pair1_then_sub_vsx1
7710 0, // sub_pair1_then_sub_vsx1_then_sub_64
7711 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7712 0, // sub_dmrrowp1_then_sub_dmrrow0
7713 0, // sub_dmrrowp1_then_sub_dmrrow1
7714 0, // sub_wacc_hi_then_sub_dmrrow0
7715 0, // sub_wacc_hi_then_sub_dmrrow1
7716 0, // sub_wacc_hi_then_sub_dmrrowp0
7717 0, // sub_wacc_hi_then_sub_dmrrowp1
7718 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7719 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7720 0, // sub_dmr1_then_sub_dmrrow0
7721 0, // sub_dmr1_then_sub_dmrrow1
7722 0, // sub_dmr1_then_sub_dmrrowp0
7723 0, // sub_dmr1_then_sub_dmrrowp1
7724 0, // sub_dmr1_then_sub_wacc_hi
7725 0, // sub_dmr1_then_sub_wacc_lo
7726 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7727 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7728 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7729 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7730 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7731 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7732 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7733 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7734 0, // sub_gp8_x1_then_sub_32
7735 },
7736 { // GPRC_and_GPRC_NOR0
7737 0, // sub_32
7738 0, // sub_32_hi_phony
7739 0, // sub_64
7740 0, // sub_64_hi_phony
7741 0, // sub_dmr0
7742 0, // sub_dmr1
7743 0, // sub_dmrrow0
7744 0, // sub_dmrrow1
7745 0, // sub_dmrrowp0
7746 0, // sub_dmrrowp1
7747 0, // sub_eq
7748 0, // sub_fp0
7749 0, // sub_fp1
7750 0, // sub_gp8_x0
7751 0, // sub_gp8_x1
7752 0, // sub_gt
7753 0, // sub_lt
7754 0, // sub_pair0
7755 0, // sub_pair1
7756 0, // sub_un
7757 0, // sub_vsx0
7758 0, // sub_vsx1
7759 0, // sub_wacc_hi
7760 0, // sub_wacc_lo
7761 0, // sub_vsx1_then_sub_64
7762 0, // sub_vsx1_then_sub_64_hi_phony
7763 0, // sub_pair1_then_sub_64
7764 0, // sub_pair1_then_sub_64_hi_phony
7765 0, // sub_pair1_then_sub_vsx0
7766 0, // sub_pair1_then_sub_vsx1
7767 0, // sub_pair1_then_sub_vsx1_then_sub_64
7768 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7769 0, // sub_dmrrowp1_then_sub_dmrrow0
7770 0, // sub_dmrrowp1_then_sub_dmrrow1
7771 0, // sub_wacc_hi_then_sub_dmrrow0
7772 0, // sub_wacc_hi_then_sub_dmrrow1
7773 0, // sub_wacc_hi_then_sub_dmrrowp0
7774 0, // sub_wacc_hi_then_sub_dmrrowp1
7775 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7776 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7777 0, // sub_dmr1_then_sub_dmrrow0
7778 0, // sub_dmr1_then_sub_dmrrow1
7779 0, // sub_dmr1_then_sub_dmrrowp0
7780 0, // sub_dmr1_then_sub_dmrrowp1
7781 0, // sub_dmr1_then_sub_wacc_hi
7782 0, // sub_dmr1_then_sub_wacc_lo
7783 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7784 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7785 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7786 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7787 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7788 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7789 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7790 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7791 0, // sub_gp8_x1_then_sub_32
7792 },
7793 { // CRBITRC
7794 0, // sub_32
7795 0, // sub_32_hi_phony
7796 0, // sub_64
7797 0, // sub_64_hi_phony
7798 0, // sub_dmr0
7799 0, // sub_dmr1
7800 0, // sub_dmrrow0
7801 0, // sub_dmrrow1
7802 0, // sub_dmrrowp0
7803 0, // sub_dmrrowp1
7804 0, // sub_eq
7805 0, // sub_fp0
7806 0, // sub_fp1
7807 0, // sub_gp8_x0
7808 0, // sub_gp8_x1
7809 0, // sub_gt
7810 0, // sub_lt
7811 0, // sub_pair0
7812 0, // sub_pair1
7813 0, // sub_un
7814 0, // sub_vsx0
7815 0, // sub_vsx1
7816 0, // sub_wacc_hi
7817 0, // sub_wacc_lo
7818 0, // sub_vsx1_then_sub_64
7819 0, // sub_vsx1_then_sub_64_hi_phony
7820 0, // sub_pair1_then_sub_64
7821 0, // sub_pair1_then_sub_64_hi_phony
7822 0, // sub_pair1_then_sub_vsx0
7823 0, // sub_pair1_then_sub_vsx1
7824 0, // sub_pair1_then_sub_vsx1_then_sub_64
7825 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7826 0, // sub_dmrrowp1_then_sub_dmrrow0
7827 0, // sub_dmrrowp1_then_sub_dmrrow1
7828 0, // sub_wacc_hi_then_sub_dmrrow0
7829 0, // sub_wacc_hi_then_sub_dmrrow1
7830 0, // sub_wacc_hi_then_sub_dmrrowp0
7831 0, // sub_wacc_hi_then_sub_dmrrowp1
7832 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7833 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7834 0, // sub_dmr1_then_sub_dmrrow0
7835 0, // sub_dmr1_then_sub_dmrrow1
7836 0, // sub_dmr1_then_sub_dmrrowp0
7837 0, // sub_dmr1_then_sub_dmrrowp1
7838 0, // sub_dmr1_then_sub_wacc_hi
7839 0, // sub_dmr1_then_sub_wacc_lo
7840 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7841 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7842 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7843 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7844 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7845 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7846 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7847 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7848 0, // sub_gp8_x1_then_sub_32
7849 },
7850 { // F4RC
7851 0, // sub_32
7852 0, // sub_32_hi_phony
7853 0, // sub_64
7854 0, // sub_64_hi_phony
7855 0, // sub_dmr0
7856 0, // sub_dmr1
7857 0, // sub_dmrrow0
7858 0, // sub_dmrrow1
7859 0, // sub_dmrrowp0
7860 0, // sub_dmrrowp1
7861 0, // sub_eq
7862 0, // sub_fp0
7863 0, // sub_fp1
7864 0, // sub_gp8_x0
7865 0, // sub_gp8_x1
7866 0, // sub_gt
7867 0, // sub_lt
7868 0, // sub_pair0
7869 0, // sub_pair1
7870 0, // sub_un
7871 0, // sub_vsx0
7872 0, // sub_vsx1
7873 0, // sub_wacc_hi
7874 0, // sub_wacc_lo
7875 0, // sub_vsx1_then_sub_64
7876 0, // sub_vsx1_then_sub_64_hi_phony
7877 0, // sub_pair1_then_sub_64
7878 0, // sub_pair1_then_sub_64_hi_phony
7879 0, // sub_pair1_then_sub_vsx0
7880 0, // sub_pair1_then_sub_vsx1
7881 0, // sub_pair1_then_sub_vsx1_then_sub_64
7882 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7883 0, // sub_dmrrowp1_then_sub_dmrrow0
7884 0, // sub_dmrrowp1_then_sub_dmrrow1
7885 0, // sub_wacc_hi_then_sub_dmrrow0
7886 0, // sub_wacc_hi_then_sub_dmrrow1
7887 0, // sub_wacc_hi_then_sub_dmrrowp0
7888 0, // sub_wacc_hi_then_sub_dmrrowp1
7889 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7890 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7891 0, // sub_dmr1_then_sub_dmrrow0
7892 0, // sub_dmr1_then_sub_dmrrow1
7893 0, // sub_dmr1_then_sub_dmrrowp0
7894 0, // sub_dmr1_then_sub_dmrrowp1
7895 0, // sub_dmr1_then_sub_wacc_hi
7896 0, // sub_dmr1_then_sub_wacc_lo
7897 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7898 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7899 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7900 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7901 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7902 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7903 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7904 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7905 0, // sub_gp8_x1_then_sub_32
7906 },
7907 { // GPRC32
7908 0, // sub_32
7909 0, // sub_32_hi_phony
7910 0, // sub_64
7911 0, // sub_64_hi_phony
7912 0, // sub_dmr0
7913 0, // sub_dmr1
7914 0, // sub_dmrrow0
7915 0, // sub_dmrrow1
7916 0, // sub_dmrrowp0
7917 0, // sub_dmrrowp1
7918 0, // sub_eq
7919 0, // sub_fp0
7920 0, // sub_fp1
7921 0, // sub_gp8_x0
7922 0, // sub_gp8_x1
7923 0, // sub_gt
7924 0, // sub_lt
7925 0, // sub_pair0
7926 0, // sub_pair1
7927 0, // sub_un
7928 0, // sub_vsx0
7929 0, // sub_vsx1
7930 0, // sub_wacc_hi
7931 0, // sub_wacc_lo
7932 0, // sub_vsx1_then_sub_64
7933 0, // sub_vsx1_then_sub_64_hi_phony
7934 0, // sub_pair1_then_sub_64
7935 0, // sub_pair1_then_sub_64_hi_phony
7936 0, // sub_pair1_then_sub_vsx0
7937 0, // sub_pair1_then_sub_vsx1
7938 0, // sub_pair1_then_sub_vsx1_then_sub_64
7939 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7940 0, // sub_dmrrowp1_then_sub_dmrrow0
7941 0, // sub_dmrrowp1_then_sub_dmrrow1
7942 0, // sub_wacc_hi_then_sub_dmrrow0
7943 0, // sub_wacc_hi_then_sub_dmrrow1
7944 0, // sub_wacc_hi_then_sub_dmrrowp0
7945 0, // sub_wacc_hi_then_sub_dmrrowp1
7946 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7947 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7948 0, // sub_dmr1_then_sub_dmrrow0
7949 0, // sub_dmr1_then_sub_dmrrow1
7950 0, // sub_dmr1_then_sub_dmrrowp0
7951 0, // sub_dmr1_then_sub_dmrrowp1
7952 0, // sub_dmr1_then_sub_wacc_hi
7953 0, // sub_dmr1_then_sub_wacc_lo
7954 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7955 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7956 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7957 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7958 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7959 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7960 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7961 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7962 0, // sub_gp8_x1_then_sub_32
7963 },
7964 { // CRRC
7965 0, // sub_32
7966 0, // sub_32_hi_phony
7967 0, // sub_64
7968 0, // sub_64_hi_phony
7969 0, // sub_dmr0
7970 0, // sub_dmr1
7971 0, // sub_dmrrow0
7972 0, // sub_dmrrow1
7973 0, // sub_dmrrowp0
7974 0, // sub_dmrrowp1
7975 8, // sub_eq -> CRRC
7976 0, // sub_fp0
7977 0, // sub_fp1
7978 0, // sub_gp8_x0
7979 0, // sub_gp8_x1
7980 8, // sub_gt -> CRRC
7981 8, // sub_lt -> CRRC
7982 0, // sub_pair0
7983 0, // sub_pair1
7984 8, // sub_un -> CRRC
7985 0, // sub_vsx0
7986 0, // sub_vsx1
7987 0, // sub_wacc_hi
7988 0, // sub_wacc_lo
7989 0, // sub_vsx1_then_sub_64
7990 0, // sub_vsx1_then_sub_64_hi_phony
7991 0, // sub_pair1_then_sub_64
7992 0, // sub_pair1_then_sub_64_hi_phony
7993 0, // sub_pair1_then_sub_vsx0
7994 0, // sub_pair1_then_sub_vsx1
7995 0, // sub_pair1_then_sub_vsx1_then_sub_64
7996 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7997 0, // sub_dmrrowp1_then_sub_dmrrow0
7998 0, // sub_dmrrowp1_then_sub_dmrrow1
7999 0, // sub_wacc_hi_then_sub_dmrrow0
8000 0, // sub_wacc_hi_then_sub_dmrrow1
8001 0, // sub_wacc_hi_then_sub_dmrrowp0
8002 0, // sub_wacc_hi_then_sub_dmrrowp1
8003 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8004 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8005 0, // sub_dmr1_then_sub_dmrrow0
8006 0, // sub_dmr1_then_sub_dmrrow1
8007 0, // sub_dmr1_then_sub_dmrrowp0
8008 0, // sub_dmr1_then_sub_dmrrowp1
8009 0, // sub_dmr1_then_sub_wacc_hi
8010 0, // sub_dmr1_then_sub_wacc_lo
8011 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8012 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8013 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8014 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8015 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8016 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8017 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8018 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8019 0, // sub_gp8_x1_then_sub_32
8020 },
8021 { // CARRYRC
8022 0, // sub_32
8023 0, // sub_32_hi_phony
8024 0, // sub_64
8025 0, // sub_64_hi_phony
8026 0, // sub_dmr0
8027 0, // sub_dmr1
8028 0, // sub_dmrrow0
8029 0, // sub_dmrrow1
8030 0, // sub_dmrrowp0
8031 0, // sub_dmrrowp1
8032 0, // sub_eq
8033 0, // sub_fp0
8034 0, // sub_fp1
8035 0, // sub_gp8_x0
8036 0, // sub_gp8_x1
8037 0, // sub_gt
8038 0, // sub_lt
8039 0, // sub_pair0
8040 0, // sub_pair1
8041 0, // sub_un
8042 0, // sub_vsx0
8043 0, // sub_vsx1
8044 0, // sub_wacc_hi
8045 0, // sub_wacc_lo
8046 0, // sub_vsx1_then_sub_64
8047 0, // sub_vsx1_then_sub_64_hi_phony
8048 0, // sub_pair1_then_sub_64
8049 0, // sub_pair1_then_sub_64_hi_phony
8050 0, // sub_pair1_then_sub_vsx0
8051 0, // sub_pair1_then_sub_vsx1
8052 0, // sub_pair1_then_sub_vsx1_then_sub_64
8053 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8054 0, // sub_dmrrowp1_then_sub_dmrrow0
8055 0, // sub_dmrrowp1_then_sub_dmrrow1
8056 0, // sub_wacc_hi_then_sub_dmrrow0
8057 0, // sub_wacc_hi_then_sub_dmrrow1
8058 0, // sub_wacc_hi_then_sub_dmrrowp0
8059 0, // sub_wacc_hi_then_sub_dmrrowp1
8060 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8061 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8062 0, // sub_dmr1_then_sub_dmrrow0
8063 0, // sub_dmr1_then_sub_dmrrow1
8064 0, // sub_dmr1_then_sub_dmrrowp0
8065 0, // sub_dmr1_then_sub_dmrrowp1
8066 0, // sub_dmr1_then_sub_wacc_hi
8067 0, // sub_dmr1_then_sub_wacc_lo
8068 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8069 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8070 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8071 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8072 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8073 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8074 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8075 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8076 0, // sub_gp8_x1_then_sub_32
8077 },
8078 { // CTRRC
8079 0, // sub_32
8080 0, // sub_32_hi_phony
8081 0, // sub_64
8082 0, // sub_64_hi_phony
8083 0, // sub_dmr0
8084 0, // sub_dmr1
8085 0, // sub_dmrrow0
8086 0, // sub_dmrrow1
8087 0, // sub_dmrrowp0
8088 0, // sub_dmrrowp1
8089 0, // sub_eq
8090 0, // sub_fp0
8091 0, // sub_fp1
8092 0, // sub_gp8_x0
8093 0, // sub_gp8_x1
8094 0, // sub_gt
8095 0, // sub_lt
8096 0, // sub_pair0
8097 0, // sub_pair1
8098 0, // sub_un
8099 0, // sub_vsx0
8100 0, // sub_vsx1
8101 0, // sub_wacc_hi
8102 0, // sub_wacc_lo
8103 0, // sub_vsx1_then_sub_64
8104 0, // sub_vsx1_then_sub_64_hi_phony
8105 0, // sub_pair1_then_sub_64
8106 0, // sub_pair1_then_sub_64_hi_phony
8107 0, // sub_pair1_then_sub_vsx0
8108 0, // sub_pair1_then_sub_vsx1
8109 0, // sub_pair1_then_sub_vsx1_then_sub_64
8110 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8111 0, // sub_dmrrowp1_then_sub_dmrrow0
8112 0, // sub_dmrrowp1_then_sub_dmrrow1
8113 0, // sub_wacc_hi_then_sub_dmrrow0
8114 0, // sub_wacc_hi_then_sub_dmrrow1
8115 0, // sub_wacc_hi_then_sub_dmrrowp0
8116 0, // sub_wacc_hi_then_sub_dmrrowp1
8117 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8118 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8119 0, // sub_dmr1_then_sub_dmrrow0
8120 0, // sub_dmr1_then_sub_dmrrow1
8121 0, // sub_dmr1_then_sub_dmrrowp0
8122 0, // sub_dmr1_then_sub_dmrrowp1
8123 0, // sub_dmr1_then_sub_wacc_hi
8124 0, // sub_dmr1_then_sub_wacc_lo
8125 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8126 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8127 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8128 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8129 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8130 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8131 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8132 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8133 0, // sub_gp8_x1_then_sub_32
8134 },
8135 { // LRRC
8136 0, // sub_32
8137 0, // sub_32_hi_phony
8138 0, // sub_64
8139 0, // sub_64_hi_phony
8140 0, // sub_dmr0
8141 0, // sub_dmr1
8142 0, // sub_dmrrow0
8143 0, // sub_dmrrow1
8144 0, // sub_dmrrowp0
8145 0, // sub_dmrrowp1
8146 0, // sub_eq
8147 0, // sub_fp0
8148 0, // sub_fp1
8149 0, // sub_gp8_x0
8150 0, // sub_gp8_x1
8151 0, // sub_gt
8152 0, // sub_lt
8153 0, // sub_pair0
8154 0, // sub_pair1
8155 0, // sub_un
8156 0, // sub_vsx0
8157 0, // sub_vsx1
8158 0, // sub_wacc_hi
8159 0, // sub_wacc_lo
8160 0, // sub_vsx1_then_sub_64
8161 0, // sub_vsx1_then_sub_64_hi_phony
8162 0, // sub_pair1_then_sub_64
8163 0, // sub_pair1_then_sub_64_hi_phony
8164 0, // sub_pair1_then_sub_vsx0
8165 0, // sub_pair1_then_sub_vsx1
8166 0, // sub_pair1_then_sub_vsx1_then_sub_64
8167 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8168 0, // sub_dmrrowp1_then_sub_dmrrow0
8169 0, // sub_dmrrowp1_then_sub_dmrrow1
8170 0, // sub_wacc_hi_then_sub_dmrrow0
8171 0, // sub_wacc_hi_then_sub_dmrrow1
8172 0, // sub_wacc_hi_then_sub_dmrrowp0
8173 0, // sub_wacc_hi_then_sub_dmrrowp1
8174 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8175 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8176 0, // sub_dmr1_then_sub_dmrrow0
8177 0, // sub_dmr1_then_sub_dmrrow1
8178 0, // sub_dmr1_then_sub_dmrrowp0
8179 0, // sub_dmr1_then_sub_dmrrowp1
8180 0, // sub_dmr1_then_sub_wacc_hi
8181 0, // sub_dmr1_then_sub_wacc_lo
8182 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8183 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8184 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8185 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8186 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8187 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8188 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8189 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8190 0, // sub_gp8_x1_then_sub_32
8191 },
8192 { // VRSAVERC
8193 0, // sub_32
8194 0, // sub_32_hi_phony
8195 0, // sub_64
8196 0, // sub_64_hi_phony
8197 0, // sub_dmr0
8198 0, // sub_dmr1
8199 0, // sub_dmrrow0
8200 0, // sub_dmrrow1
8201 0, // sub_dmrrowp0
8202 0, // sub_dmrrowp1
8203 0, // sub_eq
8204 0, // sub_fp0
8205 0, // sub_fp1
8206 0, // sub_gp8_x0
8207 0, // sub_gp8_x1
8208 0, // sub_gt
8209 0, // sub_lt
8210 0, // sub_pair0
8211 0, // sub_pair1
8212 0, // sub_un
8213 0, // sub_vsx0
8214 0, // sub_vsx1
8215 0, // sub_wacc_hi
8216 0, // sub_wacc_lo
8217 0, // sub_vsx1_then_sub_64
8218 0, // sub_vsx1_then_sub_64_hi_phony
8219 0, // sub_pair1_then_sub_64
8220 0, // sub_pair1_then_sub_64_hi_phony
8221 0, // sub_pair1_then_sub_vsx0
8222 0, // sub_pair1_then_sub_vsx1
8223 0, // sub_pair1_then_sub_vsx1_then_sub_64
8224 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8225 0, // sub_dmrrowp1_then_sub_dmrrow0
8226 0, // sub_dmrrowp1_then_sub_dmrrow1
8227 0, // sub_wacc_hi_then_sub_dmrrow0
8228 0, // sub_wacc_hi_then_sub_dmrrow1
8229 0, // sub_wacc_hi_then_sub_dmrrowp0
8230 0, // sub_wacc_hi_then_sub_dmrrowp1
8231 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8232 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8233 0, // sub_dmr1_then_sub_dmrrow0
8234 0, // sub_dmr1_then_sub_dmrrow1
8235 0, // sub_dmr1_then_sub_dmrrowp0
8236 0, // sub_dmr1_then_sub_dmrrowp1
8237 0, // sub_dmr1_then_sub_wacc_hi
8238 0, // sub_dmr1_then_sub_wacc_lo
8239 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8240 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8241 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8242 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8243 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8244 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8245 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8246 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8247 0, // sub_gp8_x1_then_sub_32
8248 },
8249 { // SPILLTOVSRRC
8250 15, // sub_32 -> G8RC
8251 0, // sub_32_hi_phony
8252 0, // sub_64
8253 0, // sub_64_hi_phony
8254 0, // sub_dmr0
8255 0, // sub_dmr1
8256 0, // sub_dmrrow0
8257 0, // sub_dmrrow1
8258 0, // sub_dmrrowp0
8259 0, // sub_dmrrowp1
8260 0, // sub_eq
8261 0, // sub_fp0
8262 0, // sub_fp1
8263 0, // sub_gp8_x0
8264 0, // sub_gp8_x1
8265 0, // sub_gt
8266 0, // sub_lt
8267 0, // sub_pair0
8268 0, // sub_pair1
8269 0, // sub_un
8270 0, // sub_vsx0
8271 0, // sub_vsx1
8272 0, // sub_wacc_hi
8273 0, // sub_wacc_lo
8274 0, // sub_vsx1_then_sub_64
8275 0, // sub_vsx1_then_sub_64_hi_phony
8276 0, // sub_pair1_then_sub_64
8277 0, // sub_pair1_then_sub_64_hi_phony
8278 0, // sub_pair1_then_sub_vsx0
8279 0, // sub_pair1_then_sub_vsx1
8280 0, // sub_pair1_then_sub_vsx1_then_sub_64
8281 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8282 0, // sub_dmrrowp1_then_sub_dmrrow0
8283 0, // sub_dmrrowp1_then_sub_dmrrow1
8284 0, // sub_wacc_hi_then_sub_dmrrow0
8285 0, // sub_wacc_hi_then_sub_dmrrow1
8286 0, // sub_wacc_hi_then_sub_dmrrowp0
8287 0, // sub_wacc_hi_then_sub_dmrrowp1
8288 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8289 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8290 0, // sub_dmr1_then_sub_dmrrow0
8291 0, // sub_dmr1_then_sub_dmrrow1
8292 0, // sub_dmr1_then_sub_dmrrowp0
8293 0, // sub_dmr1_then_sub_dmrrowp1
8294 0, // sub_dmr1_then_sub_wacc_hi
8295 0, // sub_dmr1_then_sub_wacc_lo
8296 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8297 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8298 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8299 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8300 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8301 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8302 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8303 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8304 0, // sub_gp8_x1_then_sub_32
8305 },
8306 { // VSFRC
8307 0, // sub_32
8308 0, // sub_32_hi_phony
8309 0, // sub_64
8310 0, // sub_64_hi_phony
8311 0, // sub_dmr0
8312 0, // sub_dmr1
8313 0, // sub_dmrrow0
8314 0, // sub_dmrrow1
8315 0, // sub_dmrrowp0
8316 0, // sub_dmrrowp1
8317 0, // sub_eq
8318 0, // sub_fp0
8319 0, // sub_fp1
8320 0, // sub_gp8_x0
8321 0, // sub_gp8_x1
8322 0, // sub_gt
8323 0, // sub_lt
8324 0, // sub_pair0
8325 0, // sub_pair1
8326 0, // sub_un
8327 0, // sub_vsx0
8328 0, // sub_vsx1
8329 0, // sub_wacc_hi
8330 0, // sub_wacc_lo
8331 0, // sub_vsx1_then_sub_64
8332 0, // sub_vsx1_then_sub_64_hi_phony
8333 0, // sub_pair1_then_sub_64
8334 0, // sub_pair1_then_sub_64_hi_phony
8335 0, // sub_pair1_then_sub_vsx0
8336 0, // sub_pair1_then_sub_vsx1
8337 0, // sub_pair1_then_sub_vsx1_then_sub_64
8338 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8339 0, // sub_dmrrowp1_then_sub_dmrrow0
8340 0, // sub_dmrrowp1_then_sub_dmrrow1
8341 0, // sub_wacc_hi_then_sub_dmrrow0
8342 0, // sub_wacc_hi_then_sub_dmrrow1
8343 0, // sub_wacc_hi_then_sub_dmrrowp0
8344 0, // sub_wacc_hi_then_sub_dmrrowp1
8345 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8346 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8347 0, // sub_dmr1_then_sub_dmrrow0
8348 0, // sub_dmr1_then_sub_dmrrow1
8349 0, // sub_dmr1_then_sub_dmrrowp0
8350 0, // sub_dmr1_then_sub_dmrrowp1
8351 0, // sub_dmr1_then_sub_wacc_hi
8352 0, // sub_dmr1_then_sub_wacc_lo
8353 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8354 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8355 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8356 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8357 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8358 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8359 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8360 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8361 0, // sub_gp8_x1_then_sub_32
8362 },
8363 { // G8RC
8364 15, // sub_32 -> G8RC
8365 0, // sub_32_hi_phony
8366 0, // sub_64
8367 0, // sub_64_hi_phony
8368 0, // sub_dmr0
8369 0, // sub_dmr1
8370 0, // sub_dmrrow0
8371 0, // sub_dmrrow1
8372 0, // sub_dmrrowp0
8373 0, // sub_dmrrowp1
8374 0, // sub_eq
8375 0, // sub_fp0
8376 0, // sub_fp1
8377 0, // sub_gp8_x0
8378 0, // sub_gp8_x1
8379 0, // sub_gt
8380 0, // sub_lt
8381 0, // sub_pair0
8382 0, // sub_pair1
8383 0, // sub_un
8384 0, // sub_vsx0
8385 0, // sub_vsx1
8386 0, // sub_wacc_hi
8387 0, // sub_wacc_lo
8388 0, // sub_vsx1_then_sub_64
8389 0, // sub_vsx1_then_sub_64_hi_phony
8390 0, // sub_pair1_then_sub_64
8391 0, // sub_pair1_then_sub_64_hi_phony
8392 0, // sub_pair1_then_sub_vsx0
8393 0, // sub_pair1_then_sub_vsx1
8394 0, // sub_pair1_then_sub_vsx1_then_sub_64
8395 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8396 0, // sub_dmrrowp1_then_sub_dmrrow0
8397 0, // sub_dmrrowp1_then_sub_dmrrow1
8398 0, // sub_wacc_hi_then_sub_dmrrow0
8399 0, // sub_wacc_hi_then_sub_dmrrow1
8400 0, // sub_wacc_hi_then_sub_dmrrowp0
8401 0, // sub_wacc_hi_then_sub_dmrrowp1
8402 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8403 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8404 0, // sub_dmr1_then_sub_dmrrow0
8405 0, // sub_dmr1_then_sub_dmrrow1
8406 0, // sub_dmr1_then_sub_dmrrowp0
8407 0, // sub_dmr1_then_sub_dmrrowp1
8408 0, // sub_dmr1_then_sub_wacc_hi
8409 0, // sub_dmr1_then_sub_wacc_lo
8410 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8411 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8412 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8413 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8414 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8415 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8416 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8417 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8418 0, // sub_gp8_x1_then_sub_32
8419 },
8420 { // G8RC_NOX0
8421 16, // sub_32 -> G8RC_NOX0
8422 0, // sub_32_hi_phony
8423 0, // sub_64
8424 0, // sub_64_hi_phony
8425 0, // sub_dmr0
8426 0, // sub_dmr1
8427 0, // sub_dmrrow0
8428 0, // sub_dmrrow1
8429 0, // sub_dmrrowp0
8430 0, // sub_dmrrowp1
8431 0, // sub_eq
8432 0, // sub_fp0
8433 0, // sub_fp1
8434 0, // sub_gp8_x0
8435 0, // sub_gp8_x1
8436 0, // sub_gt
8437 0, // sub_lt
8438 0, // sub_pair0
8439 0, // sub_pair1
8440 0, // sub_un
8441 0, // sub_vsx0
8442 0, // sub_vsx1
8443 0, // sub_wacc_hi
8444 0, // sub_wacc_lo
8445 0, // sub_vsx1_then_sub_64
8446 0, // sub_vsx1_then_sub_64_hi_phony
8447 0, // sub_pair1_then_sub_64
8448 0, // sub_pair1_then_sub_64_hi_phony
8449 0, // sub_pair1_then_sub_vsx0
8450 0, // sub_pair1_then_sub_vsx1
8451 0, // sub_pair1_then_sub_vsx1_then_sub_64
8452 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8453 0, // sub_dmrrowp1_then_sub_dmrrow0
8454 0, // sub_dmrrowp1_then_sub_dmrrow1
8455 0, // sub_wacc_hi_then_sub_dmrrow0
8456 0, // sub_wacc_hi_then_sub_dmrrow1
8457 0, // sub_wacc_hi_then_sub_dmrrowp0
8458 0, // sub_wacc_hi_then_sub_dmrrowp1
8459 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8460 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8461 0, // sub_dmr1_then_sub_dmrrow0
8462 0, // sub_dmr1_then_sub_dmrrow1
8463 0, // sub_dmr1_then_sub_dmrrowp0
8464 0, // sub_dmr1_then_sub_dmrrowp1
8465 0, // sub_dmr1_then_sub_wacc_hi
8466 0, // sub_dmr1_then_sub_wacc_lo
8467 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8468 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8469 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8470 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8471 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8472 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8473 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8474 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8475 0, // sub_gp8_x1_then_sub_32
8476 },
8477 { // SPILLTOVSRRC_and_VSFRC
8478 0, // sub_32
8479 0, // sub_32_hi_phony
8480 0, // sub_64
8481 0, // sub_64_hi_phony
8482 0, // sub_dmr0
8483 0, // sub_dmr1
8484 0, // sub_dmrrow0
8485 0, // sub_dmrrow1
8486 0, // sub_dmrrowp0
8487 0, // sub_dmrrowp1
8488 0, // sub_eq
8489 0, // sub_fp0
8490 0, // sub_fp1
8491 0, // sub_gp8_x0
8492 0, // sub_gp8_x1
8493 0, // sub_gt
8494 0, // sub_lt
8495 0, // sub_pair0
8496 0, // sub_pair1
8497 0, // sub_un
8498 0, // sub_vsx0
8499 0, // sub_vsx1
8500 0, // sub_wacc_hi
8501 0, // sub_wacc_lo
8502 0, // sub_vsx1_then_sub_64
8503 0, // sub_vsx1_then_sub_64_hi_phony
8504 0, // sub_pair1_then_sub_64
8505 0, // sub_pair1_then_sub_64_hi_phony
8506 0, // sub_pair1_then_sub_vsx0
8507 0, // sub_pair1_then_sub_vsx1
8508 0, // sub_pair1_then_sub_vsx1_then_sub_64
8509 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8510 0, // sub_dmrrowp1_then_sub_dmrrow0
8511 0, // sub_dmrrowp1_then_sub_dmrrow1
8512 0, // sub_wacc_hi_then_sub_dmrrow0
8513 0, // sub_wacc_hi_then_sub_dmrrow1
8514 0, // sub_wacc_hi_then_sub_dmrrowp0
8515 0, // sub_wacc_hi_then_sub_dmrrowp1
8516 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8517 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8518 0, // sub_dmr1_then_sub_dmrrow0
8519 0, // sub_dmr1_then_sub_dmrrow1
8520 0, // sub_dmr1_then_sub_dmrrowp0
8521 0, // sub_dmr1_then_sub_dmrrowp1
8522 0, // sub_dmr1_then_sub_wacc_hi
8523 0, // sub_dmr1_then_sub_wacc_lo
8524 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8525 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8526 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8527 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8528 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8529 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8530 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8531 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8532 0, // sub_gp8_x1_then_sub_32
8533 },
8534 { // G8RC_and_G8RC_NOX0
8535 18, // sub_32 -> G8RC_and_G8RC_NOX0
8536 0, // sub_32_hi_phony
8537 0, // sub_64
8538 0, // sub_64_hi_phony
8539 0, // sub_dmr0
8540 0, // sub_dmr1
8541 0, // sub_dmrrow0
8542 0, // sub_dmrrow1
8543 0, // sub_dmrrowp0
8544 0, // sub_dmrrowp1
8545 0, // sub_eq
8546 0, // sub_fp0
8547 0, // sub_fp1
8548 0, // sub_gp8_x0
8549 0, // sub_gp8_x1
8550 0, // sub_gt
8551 0, // sub_lt
8552 0, // sub_pair0
8553 0, // sub_pair1
8554 0, // sub_un
8555 0, // sub_vsx0
8556 0, // sub_vsx1
8557 0, // sub_wacc_hi
8558 0, // sub_wacc_lo
8559 0, // sub_vsx1_then_sub_64
8560 0, // sub_vsx1_then_sub_64_hi_phony
8561 0, // sub_pair1_then_sub_64
8562 0, // sub_pair1_then_sub_64_hi_phony
8563 0, // sub_pair1_then_sub_vsx0
8564 0, // sub_pair1_then_sub_vsx1
8565 0, // sub_pair1_then_sub_vsx1_then_sub_64
8566 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8567 0, // sub_dmrrowp1_then_sub_dmrrow0
8568 0, // sub_dmrrowp1_then_sub_dmrrow1
8569 0, // sub_wacc_hi_then_sub_dmrrow0
8570 0, // sub_wacc_hi_then_sub_dmrrow1
8571 0, // sub_wacc_hi_then_sub_dmrrowp0
8572 0, // sub_wacc_hi_then_sub_dmrrowp1
8573 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8574 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8575 0, // sub_dmr1_then_sub_dmrrow0
8576 0, // sub_dmr1_then_sub_dmrrow1
8577 0, // sub_dmr1_then_sub_dmrrowp0
8578 0, // sub_dmr1_then_sub_dmrrowp1
8579 0, // sub_dmr1_then_sub_wacc_hi
8580 0, // sub_dmr1_then_sub_wacc_lo
8581 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8582 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8583 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8584 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8585 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8586 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8587 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8588 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8589 0, // sub_gp8_x1_then_sub_32
8590 },
8591 { // F8RC
8592 0, // sub_32
8593 0, // sub_32_hi_phony
8594 0, // sub_64
8595 0, // sub_64_hi_phony
8596 0, // sub_dmr0
8597 0, // sub_dmr1
8598 0, // sub_dmrrow0
8599 0, // sub_dmrrow1
8600 0, // sub_dmrrowp0
8601 0, // sub_dmrrowp1
8602 0, // sub_eq
8603 0, // sub_fp0
8604 0, // sub_fp1
8605 0, // sub_gp8_x0
8606 0, // sub_gp8_x1
8607 0, // sub_gt
8608 0, // sub_lt
8609 0, // sub_pair0
8610 0, // sub_pair1
8611 0, // sub_un
8612 0, // sub_vsx0
8613 0, // sub_vsx1
8614 0, // sub_wacc_hi
8615 0, // sub_wacc_lo
8616 0, // sub_vsx1_then_sub_64
8617 0, // sub_vsx1_then_sub_64_hi_phony
8618 0, // sub_pair1_then_sub_64
8619 0, // sub_pair1_then_sub_64_hi_phony
8620 0, // sub_pair1_then_sub_vsx0
8621 0, // sub_pair1_then_sub_vsx1
8622 0, // sub_pair1_then_sub_vsx1_then_sub_64
8623 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8624 0, // sub_dmrrowp1_then_sub_dmrrow0
8625 0, // sub_dmrrowp1_then_sub_dmrrow1
8626 0, // sub_wacc_hi_then_sub_dmrrow0
8627 0, // sub_wacc_hi_then_sub_dmrrow1
8628 0, // sub_wacc_hi_then_sub_dmrrowp0
8629 0, // sub_wacc_hi_then_sub_dmrrowp1
8630 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8631 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8632 0, // sub_dmr1_then_sub_dmrrow0
8633 0, // sub_dmr1_then_sub_dmrrow1
8634 0, // sub_dmr1_then_sub_dmrrowp0
8635 0, // sub_dmr1_then_sub_dmrrowp1
8636 0, // sub_dmr1_then_sub_wacc_hi
8637 0, // sub_dmr1_then_sub_wacc_lo
8638 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8639 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8640 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8641 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8642 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8643 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8644 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8645 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8646 0, // sub_gp8_x1_then_sub_32
8647 },
8648 { // FHRC
8649 0, // sub_32
8650 0, // sub_32_hi_phony
8651 0, // sub_64
8652 0, // sub_64_hi_phony
8653 0, // sub_dmr0
8654 0, // sub_dmr1
8655 0, // sub_dmrrow0
8656 0, // sub_dmrrow1
8657 0, // sub_dmrrowp0
8658 0, // sub_dmrrowp1
8659 0, // sub_eq
8660 0, // sub_fp0
8661 0, // sub_fp1
8662 0, // sub_gp8_x0
8663 0, // sub_gp8_x1
8664 0, // sub_gt
8665 0, // sub_lt
8666 0, // sub_pair0
8667 0, // sub_pair1
8668 0, // sub_un
8669 0, // sub_vsx0
8670 0, // sub_vsx1
8671 0, // sub_wacc_hi
8672 0, // sub_wacc_lo
8673 0, // sub_vsx1_then_sub_64
8674 0, // sub_vsx1_then_sub_64_hi_phony
8675 0, // sub_pair1_then_sub_64
8676 0, // sub_pair1_then_sub_64_hi_phony
8677 0, // sub_pair1_then_sub_vsx0
8678 0, // sub_pair1_then_sub_vsx1
8679 0, // sub_pair1_then_sub_vsx1_then_sub_64
8680 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8681 0, // sub_dmrrowp1_then_sub_dmrrow0
8682 0, // sub_dmrrowp1_then_sub_dmrrow1
8683 0, // sub_wacc_hi_then_sub_dmrrow0
8684 0, // sub_wacc_hi_then_sub_dmrrow1
8685 0, // sub_wacc_hi_then_sub_dmrrowp0
8686 0, // sub_wacc_hi_then_sub_dmrrowp1
8687 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8688 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8689 0, // sub_dmr1_then_sub_dmrrow0
8690 0, // sub_dmr1_then_sub_dmrrow1
8691 0, // sub_dmr1_then_sub_dmrrowp0
8692 0, // sub_dmr1_then_sub_dmrrowp1
8693 0, // sub_dmr1_then_sub_wacc_hi
8694 0, // sub_dmr1_then_sub_wacc_lo
8695 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8696 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8697 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8698 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8699 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8700 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8701 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8702 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8703 0, // sub_gp8_x1_then_sub_32
8704 },
8705 { // SPERC
8706 21, // sub_32 -> SPERC
8707 0, // sub_32_hi_phony
8708 0, // sub_64
8709 0, // sub_64_hi_phony
8710 0, // sub_dmr0
8711 0, // sub_dmr1
8712 0, // sub_dmrrow0
8713 0, // sub_dmrrow1
8714 0, // sub_dmrrowp0
8715 0, // sub_dmrrowp1
8716 0, // sub_eq
8717 0, // sub_fp0
8718 0, // sub_fp1
8719 0, // sub_gp8_x0
8720 0, // sub_gp8_x1
8721 0, // sub_gt
8722 0, // sub_lt
8723 0, // sub_pair0
8724 0, // sub_pair1
8725 0, // sub_un
8726 0, // sub_vsx0
8727 0, // sub_vsx1
8728 0, // sub_wacc_hi
8729 0, // sub_wacc_lo
8730 0, // sub_vsx1_then_sub_64
8731 0, // sub_vsx1_then_sub_64_hi_phony
8732 0, // sub_pair1_then_sub_64
8733 0, // sub_pair1_then_sub_64_hi_phony
8734 0, // sub_pair1_then_sub_vsx0
8735 0, // sub_pair1_then_sub_vsx1
8736 0, // sub_pair1_then_sub_vsx1_then_sub_64
8737 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8738 0, // sub_dmrrowp1_then_sub_dmrrow0
8739 0, // sub_dmrrowp1_then_sub_dmrrow1
8740 0, // sub_wacc_hi_then_sub_dmrrow0
8741 0, // sub_wacc_hi_then_sub_dmrrow1
8742 0, // sub_wacc_hi_then_sub_dmrrowp0
8743 0, // sub_wacc_hi_then_sub_dmrrowp1
8744 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8745 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8746 0, // sub_dmr1_then_sub_dmrrow0
8747 0, // sub_dmr1_then_sub_dmrrow1
8748 0, // sub_dmr1_then_sub_dmrrowp0
8749 0, // sub_dmr1_then_sub_dmrrowp1
8750 0, // sub_dmr1_then_sub_wacc_hi
8751 0, // sub_dmr1_then_sub_wacc_lo
8752 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8753 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8754 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8755 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8756 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8757 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8758 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8759 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8760 0, // sub_gp8_x1_then_sub_32
8761 },
8762 { // VFHRC
8763 0, // sub_32
8764 0, // sub_32_hi_phony
8765 0, // sub_64
8766 0, // sub_64_hi_phony
8767 0, // sub_dmr0
8768 0, // sub_dmr1
8769 0, // sub_dmrrow0
8770 0, // sub_dmrrow1
8771 0, // sub_dmrrowp0
8772 0, // sub_dmrrowp1
8773 0, // sub_eq
8774 0, // sub_fp0
8775 0, // sub_fp1
8776 0, // sub_gp8_x0
8777 0, // sub_gp8_x1
8778 0, // sub_gt
8779 0, // sub_lt
8780 0, // sub_pair0
8781 0, // sub_pair1
8782 0, // sub_un
8783 0, // sub_vsx0
8784 0, // sub_vsx1
8785 0, // sub_wacc_hi
8786 0, // sub_wacc_lo
8787 0, // sub_vsx1_then_sub_64
8788 0, // sub_vsx1_then_sub_64_hi_phony
8789 0, // sub_pair1_then_sub_64
8790 0, // sub_pair1_then_sub_64_hi_phony
8791 0, // sub_pair1_then_sub_vsx0
8792 0, // sub_pair1_then_sub_vsx1
8793 0, // sub_pair1_then_sub_vsx1_then_sub_64
8794 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8795 0, // sub_dmrrowp1_then_sub_dmrrow0
8796 0, // sub_dmrrowp1_then_sub_dmrrow1
8797 0, // sub_wacc_hi_then_sub_dmrrow0
8798 0, // sub_wacc_hi_then_sub_dmrrow1
8799 0, // sub_wacc_hi_then_sub_dmrrowp0
8800 0, // sub_wacc_hi_then_sub_dmrrowp1
8801 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8802 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8803 0, // sub_dmr1_then_sub_dmrrow0
8804 0, // sub_dmr1_then_sub_dmrrow1
8805 0, // sub_dmr1_then_sub_dmrrowp0
8806 0, // sub_dmr1_then_sub_dmrrowp1
8807 0, // sub_dmr1_then_sub_wacc_hi
8808 0, // sub_dmr1_then_sub_wacc_lo
8809 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8810 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8811 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8812 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8813 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8814 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8815 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8816 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8817 0, // sub_gp8_x1_then_sub_32
8818 },
8819 { // VFRC
8820 0, // sub_32
8821 0, // sub_32_hi_phony
8822 0, // sub_64
8823 0, // sub_64_hi_phony
8824 0, // sub_dmr0
8825 0, // sub_dmr1
8826 0, // sub_dmrrow0
8827 0, // sub_dmrrow1
8828 0, // sub_dmrrowp0
8829 0, // sub_dmrrowp1
8830 0, // sub_eq
8831 0, // sub_fp0
8832 0, // sub_fp1
8833 0, // sub_gp8_x0
8834 0, // sub_gp8_x1
8835 0, // sub_gt
8836 0, // sub_lt
8837 0, // sub_pair0
8838 0, // sub_pair1
8839 0, // sub_un
8840 0, // sub_vsx0
8841 0, // sub_vsx1
8842 0, // sub_wacc_hi
8843 0, // sub_wacc_lo
8844 0, // sub_vsx1_then_sub_64
8845 0, // sub_vsx1_then_sub_64_hi_phony
8846 0, // sub_pair1_then_sub_64
8847 0, // sub_pair1_then_sub_64_hi_phony
8848 0, // sub_pair1_then_sub_vsx0
8849 0, // sub_pair1_then_sub_vsx1
8850 0, // sub_pair1_then_sub_vsx1_then_sub_64
8851 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8852 0, // sub_dmrrowp1_then_sub_dmrrow0
8853 0, // sub_dmrrowp1_then_sub_dmrrow1
8854 0, // sub_wacc_hi_then_sub_dmrrow0
8855 0, // sub_wacc_hi_then_sub_dmrrow1
8856 0, // sub_wacc_hi_then_sub_dmrrowp0
8857 0, // sub_wacc_hi_then_sub_dmrrowp1
8858 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8859 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8860 0, // sub_dmr1_then_sub_dmrrow0
8861 0, // sub_dmr1_then_sub_dmrrow1
8862 0, // sub_dmr1_then_sub_dmrrowp0
8863 0, // sub_dmr1_then_sub_dmrrowp1
8864 0, // sub_dmr1_then_sub_wacc_hi
8865 0, // sub_dmr1_then_sub_wacc_lo
8866 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8867 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8868 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8869 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8870 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8871 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8872 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8873 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8874 0, // sub_gp8_x1_then_sub_32
8875 },
8876 { // SPERC_with_sub_32_in_GPRC_NOR0
8877 24, // sub_32 -> SPERC_with_sub_32_in_GPRC_NOR0
8878 0, // sub_32_hi_phony
8879 0, // sub_64
8880 0, // sub_64_hi_phony
8881 0, // sub_dmr0
8882 0, // sub_dmr1
8883 0, // sub_dmrrow0
8884 0, // sub_dmrrow1
8885 0, // sub_dmrrowp0
8886 0, // sub_dmrrowp1
8887 0, // sub_eq
8888 0, // sub_fp0
8889 0, // sub_fp1
8890 0, // sub_gp8_x0
8891 0, // sub_gp8_x1
8892 0, // sub_gt
8893 0, // sub_lt
8894 0, // sub_pair0
8895 0, // sub_pair1
8896 0, // sub_un
8897 0, // sub_vsx0
8898 0, // sub_vsx1
8899 0, // sub_wacc_hi
8900 0, // sub_wacc_lo
8901 0, // sub_vsx1_then_sub_64
8902 0, // sub_vsx1_then_sub_64_hi_phony
8903 0, // sub_pair1_then_sub_64
8904 0, // sub_pair1_then_sub_64_hi_phony
8905 0, // sub_pair1_then_sub_vsx0
8906 0, // sub_pair1_then_sub_vsx1
8907 0, // sub_pair1_then_sub_vsx1_then_sub_64
8908 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8909 0, // sub_dmrrowp1_then_sub_dmrrow0
8910 0, // sub_dmrrowp1_then_sub_dmrrow1
8911 0, // sub_wacc_hi_then_sub_dmrrow0
8912 0, // sub_wacc_hi_then_sub_dmrrow1
8913 0, // sub_wacc_hi_then_sub_dmrrowp0
8914 0, // sub_wacc_hi_then_sub_dmrrowp1
8915 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8916 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8917 0, // sub_dmr1_then_sub_dmrrow0
8918 0, // sub_dmr1_then_sub_dmrrow1
8919 0, // sub_dmr1_then_sub_dmrrowp0
8920 0, // sub_dmr1_then_sub_dmrrowp1
8921 0, // sub_dmr1_then_sub_wacc_hi
8922 0, // sub_dmr1_then_sub_wacc_lo
8923 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8924 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8925 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8926 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8927 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8928 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8929 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8930 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8931 0, // sub_gp8_x1_then_sub_32
8932 },
8933 { // SPILLTOVSRRC_and_VFRC
8934 0, // sub_32
8935 0, // sub_32_hi_phony
8936 0, // sub_64
8937 0, // sub_64_hi_phony
8938 0, // sub_dmr0
8939 0, // sub_dmr1
8940 0, // sub_dmrrow0
8941 0, // sub_dmrrow1
8942 0, // sub_dmrrowp0
8943 0, // sub_dmrrowp1
8944 0, // sub_eq
8945 0, // sub_fp0
8946 0, // sub_fp1
8947 0, // sub_gp8_x0
8948 0, // sub_gp8_x1
8949 0, // sub_gt
8950 0, // sub_lt
8951 0, // sub_pair0
8952 0, // sub_pair1
8953 0, // sub_un
8954 0, // sub_vsx0
8955 0, // sub_vsx1
8956 0, // sub_wacc_hi
8957 0, // sub_wacc_lo
8958 0, // sub_vsx1_then_sub_64
8959 0, // sub_vsx1_then_sub_64_hi_phony
8960 0, // sub_pair1_then_sub_64
8961 0, // sub_pair1_then_sub_64_hi_phony
8962 0, // sub_pair1_then_sub_vsx0
8963 0, // sub_pair1_then_sub_vsx1
8964 0, // sub_pair1_then_sub_vsx1_then_sub_64
8965 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8966 0, // sub_dmrrowp1_then_sub_dmrrow0
8967 0, // sub_dmrrowp1_then_sub_dmrrow1
8968 0, // sub_wacc_hi_then_sub_dmrrow0
8969 0, // sub_wacc_hi_then_sub_dmrrow1
8970 0, // sub_wacc_hi_then_sub_dmrrowp0
8971 0, // sub_wacc_hi_then_sub_dmrrowp1
8972 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8973 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8974 0, // sub_dmr1_then_sub_dmrrow0
8975 0, // sub_dmr1_then_sub_dmrrow1
8976 0, // sub_dmr1_then_sub_dmrrowp0
8977 0, // sub_dmr1_then_sub_dmrrowp1
8978 0, // sub_dmr1_then_sub_wacc_hi
8979 0, // sub_dmr1_then_sub_wacc_lo
8980 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8981 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8982 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8983 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8984 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8985 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8986 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8987 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8988 0, // sub_gp8_x1_then_sub_32
8989 },
8990 { // SPILLTOVSRRC_and_F4RC
8991 0, // sub_32
8992 0, // sub_32_hi_phony
8993 0, // sub_64
8994 0, // sub_64_hi_phony
8995 0, // sub_dmr0
8996 0, // sub_dmr1
8997 0, // sub_dmrrow0
8998 0, // sub_dmrrow1
8999 0, // sub_dmrrowp0
9000 0, // sub_dmrrowp1
9001 0, // sub_eq
9002 0, // sub_fp0
9003 0, // sub_fp1
9004 0, // sub_gp8_x0
9005 0, // sub_gp8_x1
9006 0, // sub_gt
9007 0, // sub_lt
9008 0, // sub_pair0
9009 0, // sub_pair1
9010 0, // sub_un
9011 0, // sub_vsx0
9012 0, // sub_vsx1
9013 0, // sub_wacc_hi
9014 0, // sub_wacc_lo
9015 0, // sub_vsx1_then_sub_64
9016 0, // sub_vsx1_then_sub_64_hi_phony
9017 0, // sub_pair1_then_sub_64
9018 0, // sub_pair1_then_sub_64_hi_phony
9019 0, // sub_pair1_then_sub_vsx0
9020 0, // sub_pair1_then_sub_vsx1
9021 0, // sub_pair1_then_sub_vsx1_then_sub_64
9022 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9023 0, // sub_dmrrowp1_then_sub_dmrrow0
9024 0, // sub_dmrrowp1_then_sub_dmrrow1
9025 0, // sub_wacc_hi_then_sub_dmrrow0
9026 0, // sub_wacc_hi_then_sub_dmrrow1
9027 0, // sub_wacc_hi_then_sub_dmrrowp0
9028 0, // sub_wacc_hi_then_sub_dmrrowp1
9029 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9030 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9031 0, // sub_dmr1_then_sub_dmrrow0
9032 0, // sub_dmr1_then_sub_dmrrow1
9033 0, // sub_dmr1_then_sub_dmrrowp0
9034 0, // sub_dmr1_then_sub_dmrrowp1
9035 0, // sub_dmr1_then_sub_wacc_hi
9036 0, // sub_dmr1_then_sub_wacc_lo
9037 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9038 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9039 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9040 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9041 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9042 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9043 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9044 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9045 0, // sub_gp8_x1_then_sub_32
9046 },
9047 { // CTRRC8
9048 0, // sub_32
9049 0, // sub_32_hi_phony
9050 0, // sub_64
9051 0, // sub_64_hi_phony
9052 0, // sub_dmr0
9053 0, // sub_dmr1
9054 0, // sub_dmrrow0
9055 0, // sub_dmrrow1
9056 0, // sub_dmrrowp0
9057 0, // sub_dmrrowp1
9058 0, // sub_eq
9059 0, // sub_fp0
9060 0, // sub_fp1
9061 0, // sub_gp8_x0
9062 0, // sub_gp8_x1
9063 0, // sub_gt
9064 0, // sub_lt
9065 0, // sub_pair0
9066 0, // sub_pair1
9067 0, // sub_un
9068 0, // sub_vsx0
9069 0, // sub_vsx1
9070 0, // sub_wacc_hi
9071 0, // sub_wacc_lo
9072 0, // sub_vsx1_then_sub_64
9073 0, // sub_vsx1_then_sub_64_hi_phony
9074 0, // sub_pair1_then_sub_64
9075 0, // sub_pair1_then_sub_64_hi_phony
9076 0, // sub_pair1_then_sub_vsx0
9077 0, // sub_pair1_then_sub_vsx1
9078 0, // sub_pair1_then_sub_vsx1_then_sub_64
9079 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9080 0, // sub_dmrrowp1_then_sub_dmrrow0
9081 0, // sub_dmrrowp1_then_sub_dmrrow1
9082 0, // sub_wacc_hi_then_sub_dmrrow0
9083 0, // sub_wacc_hi_then_sub_dmrrow1
9084 0, // sub_wacc_hi_then_sub_dmrrowp0
9085 0, // sub_wacc_hi_then_sub_dmrrowp1
9086 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9087 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9088 0, // sub_dmr1_then_sub_dmrrow0
9089 0, // sub_dmr1_then_sub_dmrrow1
9090 0, // sub_dmr1_then_sub_dmrrowp0
9091 0, // sub_dmr1_then_sub_dmrrowp1
9092 0, // sub_dmr1_then_sub_wacc_hi
9093 0, // sub_dmr1_then_sub_wacc_lo
9094 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9095 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9096 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9097 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9098 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9099 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9100 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9101 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9102 0, // sub_gp8_x1_then_sub_32
9103 },
9104 { // LR8RC
9105 0, // sub_32
9106 0, // sub_32_hi_phony
9107 0, // sub_64
9108 0, // sub_64_hi_phony
9109 0, // sub_dmr0
9110 0, // sub_dmr1
9111 0, // sub_dmrrow0
9112 0, // sub_dmrrow1
9113 0, // sub_dmrrowp0
9114 0, // sub_dmrrowp1
9115 0, // sub_eq
9116 0, // sub_fp0
9117 0, // sub_fp1
9118 0, // sub_gp8_x0
9119 0, // sub_gp8_x1
9120 0, // sub_gt
9121 0, // sub_lt
9122 0, // sub_pair0
9123 0, // sub_pair1
9124 0, // sub_un
9125 0, // sub_vsx0
9126 0, // sub_vsx1
9127 0, // sub_wacc_hi
9128 0, // sub_wacc_lo
9129 0, // sub_vsx1_then_sub_64
9130 0, // sub_vsx1_then_sub_64_hi_phony
9131 0, // sub_pair1_then_sub_64
9132 0, // sub_pair1_then_sub_64_hi_phony
9133 0, // sub_pair1_then_sub_vsx0
9134 0, // sub_pair1_then_sub_vsx1
9135 0, // sub_pair1_then_sub_vsx1_then_sub_64
9136 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9137 0, // sub_dmrrowp1_then_sub_dmrrow0
9138 0, // sub_dmrrowp1_then_sub_dmrrow1
9139 0, // sub_wacc_hi_then_sub_dmrrow0
9140 0, // sub_wacc_hi_then_sub_dmrrow1
9141 0, // sub_wacc_hi_then_sub_dmrrowp0
9142 0, // sub_wacc_hi_then_sub_dmrrowp1
9143 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9144 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9145 0, // sub_dmr1_then_sub_dmrrow0
9146 0, // sub_dmr1_then_sub_dmrrow1
9147 0, // sub_dmr1_then_sub_dmrrowp0
9148 0, // sub_dmr1_then_sub_dmrrowp1
9149 0, // sub_dmr1_then_sub_wacc_hi
9150 0, // sub_dmr1_then_sub_wacc_lo
9151 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9152 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9153 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9154 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9155 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9156 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9157 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9158 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9159 0, // sub_gp8_x1_then_sub_32
9160 },
9161 { // DMRROWRC
9162 0, // sub_32
9163 0, // sub_32_hi_phony
9164 0, // sub_64
9165 0, // sub_64_hi_phony
9166 0, // sub_dmr0
9167 0, // sub_dmr1
9168 0, // sub_dmrrow0
9169 0, // sub_dmrrow1
9170 0, // sub_dmrrowp0
9171 0, // sub_dmrrowp1
9172 0, // sub_eq
9173 0, // sub_fp0
9174 0, // sub_fp1
9175 0, // sub_gp8_x0
9176 0, // sub_gp8_x1
9177 0, // sub_gt
9178 0, // sub_lt
9179 0, // sub_pair0
9180 0, // sub_pair1
9181 0, // sub_un
9182 0, // sub_vsx0
9183 0, // sub_vsx1
9184 0, // sub_wacc_hi
9185 0, // sub_wacc_lo
9186 0, // sub_vsx1_then_sub_64
9187 0, // sub_vsx1_then_sub_64_hi_phony
9188 0, // sub_pair1_then_sub_64
9189 0, // sub_pair1_then_sub_64_hi_phony
9190 0, // sub_pair1_then_sub_vsx0
9191 0, // sub_pair1_then_sub_vsx1
9192 0, // sub_pair1_then_sub_vsx1_then_sub_64
9193 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9194 0, // sub_dmrrowp1_then_sub_dmrrow0
9195 0, // sub_dmrrowp1_then_sub_dmrrow1
9196 0, // sub_wacc_hi_then_sub_dmrrow0
9197 0, // sub_wacc_hi_then_sub_dmrrow1
9198 0, // sub_wacc_hi_then_sub_dmrrowp0
9199 0, // sub_wacc_hi_then_sub_dmrrowp1
9200 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9201 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9202 0, // sub_dmr1_then_sub_dmrrow0
9203 0, // sub_dmr1_then_sub_dmrrow1
9204 0, // sub_dmr1_then_sub_dmrrowp0
9205 0, // sub_dmr1_then_sub_dmrrowp1
9206 0, // sub_dmr1_then_sub_wacc_hi
9207 0, // sub_dmr1_then_sub_wacc_lo
9208 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9209 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9210 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9211 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9212 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9213 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9214 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9215 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9216 0, // sub_gp8_x1_then_sub_32
9217 },
9218 { // VSRC
9219 0, // sub_32
9220 0, // sub_32_hi_phony
9221 30, // sub_64 -> VSRC
9222 0, // sub_64_hi_phony
9223 0, // sub_dmr0
9224 0, // sub_dmr1
9225 0, // sub_dmrrow0
9226 0, // sub_dmrrow1
9227 0, // sub_dmrrowp0
9228 0, // sub_dmrrowp1
9229 0, // sub_eq
9230 0, // sub_fp0
9231 0, // sub_fp1
9232 0, // sub_gp8_x0
9233 0, // sub_gp8_x1
9234 0, // sub_gt
9235 0, // sub_lt
9236 0, // sub_pair0
9237 0, // sub_pair1
9238 0, // sub_un
9239 0, // sub_vsx0
9240 0, // sub_vsx1
9241 0, // sub_wacc_hi
9242 0, // sub_wacc_lo
9243 0, // sub_vsx1_then_sub_64
9244 0, // sub_vsx1_then_sub_64_hi_phony
9245 0, // sub_pair1_then_sub_64
9246 0, // sub_pair1_then_sub_64_hi_phony
9247 0, // sub_pair1_then_sub_vsx0
9248 0, // sub_pair1_then_sub_vsx1
9249 0, // sub_pair1_then_sub_vsx1_then_sub_64
9250 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9251 0, // sub_dmrrowp1_then_sub_dmrrow0
9252 0, // sub_dmrrowp1_then_sub_dmrrow1
9253 0, // sub_wacc_hi_then_sub_dmrrow0
9254 0, // sub_wacc_hi_then_sub_dmrrow1
9255 0, // sub_wacc_hi_then_sub_dmrrowp0
9256 0, // sub_wacc_hi_then_sub_dmrrowp1
9257 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9258 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9259 0, // sub_dmr1_then_sub_dmrrow0
9260 0, // sub_dmr1_then_sub_dmrrow1
9261 0, // sub_dmr1_then_sub_dmrrowp0
9262 0, // sub_dmr1_then_sub_dmrrowp1
9263 0, // sub_dmr1_then_sub_wacc_hi
9264 0, // sub_dmr1_then_sub_wacc_lo
9265 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9266 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9267 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9268 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9269 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9270 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9271 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9272 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9273 0, // sub_gp8_x1_then_sub_32
9274 },
9275 { // VSRC_with_sub_64_in_SPILLTOVSRRC
9276 0, // sub_32
9277 0, // sub_32_hi_phony
9278 31, // sub_64 -> VSRC_with_sub_64_in_SPILLTOVSRRC
9279 0, // sub_64_hi_phony
9280 0, // sub_dmr0
9281 0, // sub_dmr1
9282 0, // sub_dmrrow0
9283 0, // sub_dmrrow1
9284 0, // sub_dmrrowp0
9285 0, // sub_dmrrowp1
9286 0, // sub_eq
9287 0, // sub_fp0
9288 0, // sub_fp1
9289 0, // sub_gp8_x0
9290 0, // sub_gp8_x1
9291 0, // sub_gt
9292 0, // sub_lt
9293 0, // sub_pair0
9294 0, // sub_pair1
9295 0, // sub_un
9296 0, // sub_vsx0
9297 0, // sub_vsx1
9298 0, // sub_wacc_hi
9299 0, // sub_wacc_lo
9300 0, // sub_vsx1_then_sub_64
9301 0, // sub_vsx1_then_sub_64_hi_phony
9302 0, // sub_pair1_then_sub_64
9303 0, // sub_pair1_then_sub_64_hi_phony
9304 0, // sub_pair1_then_sub_vsx0
9305 0, // sub_pair1_then_sub_vsx1
9306 0, // sub_pair1_then_sub_vsx1_then_sub_64
9307 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9308 0, // sub_dmrrowp1_then_sub_dmrrow0
9309 0, // sub_dmrrowp1_then_sub_dmrrow1
9310 0, // sub_wacc_hi_then_sub_dmrrow0
9311 0, // sub_wacc_hi_then_sub_dmrrow1
9312 0, // sub_wacc_hi_then_sub_dmrrowp0
9313 0, // sub_wacc_hi_then_sub_dmrrowp1
9314 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9315 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9316 0, // sub_dmr1_then_sub_dmrrow0
9317 0, // sub_dmr1_then_sub_dmrrow1
9318 0, // sub_dmr1_then_sub_dmrrowp0
9319 0, // sub_dmr1_then_sub_dmrrowp1
9320 0, // sub_dmr1_then_sub_wacc_hi
9321 0, // sub_dmr1_then_sub_wacc_lo
9322 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9323 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9324 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9325 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9326 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9327 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9328 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9329 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9330 0, // sub_gp8_x1_then_sub_32
9331 },
9332 { // VRRC
9333 0, // sub_32
9334 0, // sub_32_hi_phony
9335 32, // sub_64 -> VRRC
9336 0, // sub_64_hi_phony
9337 0, // sub_dmr0
9338 0, // sub_dmr1
9339 0, // sub_dmrrow0
9340 0, // sub_dmrrow1
9341 0, // sub_dmrrowp0
9342 0, // sub_dmrrowp1
9343 0, // sub_eq
9344 0, // sub_fp0
9345 0, // sub_fp1
9346 0, // sub_gp8_x0
9347 0, // sub_gp8_x1
9348 0, // sub_gt
9349 0, // sub_lt
9350 0, // sub_pair0
9351 0, // sub_pair1
9352 0, // sub_un
9353 0, // sub_vsx0
9354 0, // sub_vsx1
9355 0, // sub_wacc_hi
9356 0, // sub_wacc_lo
9357 0, // sub_vsx1_then_sub_64
9358 0, // sub_vsx1_then_sub_64_hi_phony
9359 0, // sub_pair1_then_sub_64
9360 0, // sub_pair1_then_sub_64_hi_phony
9361 0, // sub_pair1_then_sub_vsx0
9362 0, // sub_pair1_then_sub_vsx1
9363 0, // sub_pair1_then_sub_vsx1_then_sub_64
9364 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9365 0, // sub_dmrrowp1_then_sub_dmrrow0
9366 0, // sub_dmrrowp1_then_sub_dmrrow1
9367 0, // sub_wacc_hi_then_sub_dmrrow0
9368 0, // sub_wacc_hi_then_sub_dmrrow1
9369 0, // sub_wacc_hi_then_sub_dmrrowp0
9370 0, // sub_wacc_hi_then_sub_dmrrowp1
9371 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9372 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9373 0, // sub_dmr1_then_sub_dmrrow0
9374 0, // sub_dmr1_then_sub_dmrrow1
9375 0, // sub_dmr1_then_sub_dmrrowp0
9376 0, // sub_dmr1_then_sub_dmrrowp1
9377 0, // sub_dmr1_then_sub_wacc_hi
9378 0, // sub_dmr1_then_sub_wacc_lo
9379 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9380 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9381 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9382 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9383 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9384 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9385 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9386 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9387 0, // sub_gp8_x1_then_sub_32
9388 },
9389 { // VSLRC
9390 0, // sub_32
9391 0, // sub_32_hi_phony
9392 33, // sub_64 -> VSLRC
9393 0, // sub_64_hi_phony
9394 0, // sub_dmr0
9395 0, // sub_dmr1
9396 0, // sub_dmrrow0
9397 0, // sub_dmrrow1
9398 0, // sub_dmrrowp0
9399 0, // sub_dmrrowp1
9400 0, // sub_eq
9401 0, // sub_fp0
9402 0, // sub_fp1
9403 0, // sub_gp8_x0
9404 0, // sub_gp8_x1
9405 0, // sub_gt
9406 0, // sub_lt
9407 0, // sub_pair0
9408 0, // sub_pair1
9409 0, // sub_un
9410 0, // sub_vsx0
9411 0, // sub_vsx1
9412 0, // sub_wacc_hi
9413 0, // sub_wacc_lo
9414 0, // sub_vsx1_then_sub_64
9415 0, // sub_vsx1_then_sub_64_hi_phony
9416 0, // sub_pair1_then_sub_64
9417 0, // sub_pair1_then_sub_64_hi_phony
9418 0, // sub_pair1_then_sub_vsx0
9419 0, // sub_pair1_then_sub_vsx1
9420 0, // sub_pair1_then_sub_vsx1_then_sub_64
9421 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9422 0, // sub_dmrrowp1_then_sub_dmrrow0
9423 0, // sub_dmrrowp1_then_sub_dmrrow1
9424 0, // sub_wacc_hi_then_sub_dmrrow0
9425 0, // sub_wacc_hi_then_sub_dmrrow1
9426 0, // sub_wacc_hi_then_sub_dmrrowp0
9427 0, // sub_wacc_hi_then_sub_dmrrowp1
9428 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9429 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9430 0, // sub_dmr1_then_sub_dmrrow0
9431 0, // sub_dmr1_then_sub_dmrrow1
9432 0, // sub_dmr1_then_sub_dmrrowp0
9433 0, // sub_dmr1_then_sub_dmrrowp1
9434 0, // sub_dmr1_then_sub_wacc_hi
9435 0, // sub_dmr1_then_sub_wacc_lo
9436 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9437 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9438 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9439 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9440 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9441 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9442 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9443 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9444 0, // sub_gp8_x1_then_sub_32
9445 },
9446 { // VRRC_with_sub_64_in_SPILLTOVSRRC
9447 0, // sub_32
9448 0, // sub_32_hi_phony
9449 34, // sub_64 -> VRRC_with_sub_64_in_SPILLTOVSRRC
9450 0, // sub_64_hi_phony
9451 0, // sub_dmr0
9452 0, // sub_dmr1
9453 0, // sub_dmrrow0
9454 0, // sub_dmrrow1
9455 0, // sub_dmrrowp0
9456 0, // sub_dmrrowp1
9457 0, // sub_eq
9458 0, // sub_fp0
9459 0, // sub_fp1
9460 0, // sub_gp8_x0
9461 0, // sub_gp8_x1
9462 0, // sub_gt
9463 0, // sub_lt
9464 0, // sub_pair0
9465 0, // sub_pair1
9466 0, // sub_un
9467 0, // sub_vsx0
9468 0, // sub_vsx1
9469 0, // sub_wacc_hi
9470 0, // sub_wacc_lo
9471 0, // sub_vsx1_then_sub_64
9472 0, // sub_vsx1_then_sub_64_hi_phony
9473 0, // sub_pair1_then_sub_64
9474 0, // sub_pair1_then_sub_64_hi_phony
9475 0, // sub_pair1_then_sub_vsx0
9476 0, // sub_pair1_then_sub_vsx1
9477 0, // sub_pair1_then_sub_vsx1_then_sub_64
9478 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9479 0, // sub_dmrrowp1_then_sub_dmrrow0
9480 0, // sub_dmrrowp1_then_sub_dmrrow1
9481 0, // sub_wacc_hi_then_sub_dmrrow0
9482 0, // sub_wacc_hi_then_sub_dmrrow1
9483 0, // sub_wacc_hi_then_sub_dmrrowp0
9484 0, // sub_wacc_hi_then_sub_dmrrowp1
9485 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9486 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9487 0, // sub_dmr1_then_sub_dmrrow0
9488 0, // sub_dmr1_then_sub_dmrrow1
9489 0, // sub_dmr1_then_sub_dmrrowp0
9490 0, // sub_dmr1_then_sub_dmrrowp1
9491 0, // sub_dmr1_then_sub_wacc_hi
9492 0, // sub_dmr1_then_sub_wacc_lo
9493 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9494 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9495 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9496 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9497 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9498 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9499 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9500 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9501 0, // sub_gp8_x1_then_sub_32
9502 },
9503 { // FpRC
9504 0, // sub_32
9505 0, // sub_32_hi_phony
9506 0, // sub_64
9507 0, // sub_64_hi_phony
9508 0, // sub_dmr0
9509 0, // sub_dmr1
9510 0, // sub_dmrrow0
9511 0, // sub_dmrrow1
9512 0, // sub_dmrrowp0
9513 0, // sub_dmrrowp1
9514 0, // sub_eq
9515 35, // sub_fp0 -> FpRC
9516 35, // sub_fp1 -> FpRC
9517 0, // sub_gp8_x0
9518 0, // sub_gp8_x1
9519 0, // sub_gt
9520 0, // sub_lt
9521 0, // sub_pair0
9522 0, // sub_pair1
9523 0, // sub_un
9524 0, // sub_vsx0
9525 0, // sub_vsx1
9526 0, // sub_wacc_hi
9527 0, // sub_wacc_lo
9528 0, // sub_vsx1_then_sub_64
9529 0, // sub_vsx1_then_sub_64_hi_phony
9530 0, // sub_pair1_then_sub_64
9531 0, // sub_pair1_then_sub_64_hi_phony
9532 0, // sub_pair1_then_sub_vsx0
9533 0, // sub_pair1_then_sub_vsx1
9534 0, // sub_pair1_then_sub_vsx1_then_sub_64
9535 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9536 0, // sub_dmrrowp1_then_sub_dmrrow0
9537 0, // sub_dmrrowp1_then_sub_dmrrow1
9538 0, // sub_wacc_hi_then_sub_dmrrow0
9539 0, // sub_wacc_hi_then_sub_dmrrow1
9540 0, // sub_wacc_hi_then_sub_dmrrowp0
9541 0, // sub_wacc_hi_then_sub_dmrrowp1
9542 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9543 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9544 0, // sub_dmr1_then_sub_dmrrow0
9545 0, // sub_dmr1_then_sub_dmrrow1
9546 0, // sub_dmr1_then_sub_dmrrowp0
9547 0, // sub_dmr1_then_sub_dmrrowp1
9548 0, // sub_dmr1_then_sub_wacc_hi
9549 0, // sub_dmr1_then_sub_wacc_lo
9550 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9551 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9552 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9553 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9554 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9555 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9556 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9557 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9558 0, // sub_gp8_x1_then_sub_32
9559 },
9560 { // G8pRC
9561 36, // sub_32 -> G8pRC
9562 0, // sub_32_hi_phony
9563 0, // sub_64
9564 0, // sub_64_hi_phony
9565 0, // sub_dmr0
9566 0, // sub_dmr1
9567 0, // sub_dmrrow0
9568 0, // sub_dmrrow1
9569 0, // sub_dmrrowp0
9570 0, // sub_dmrrowp1
9571 0, // sub_eq
9572 0, // sub_fp0
9573 0, // sub_fp1
9574 36, // sub_gp8_x0 -> G8pRC
9575 36, // sub_gp8_x1 -> G8pRC
9576 0, // sub_gt
9577 0, // sub_lt
9578 0, // sub_pair0
9579 0, // sub_pair1
9580 0, // sub_un
9581 0, // sub_vsx0
9582 0, // sub_vsx1
9583 0, // sub_wacc_hi
9584 0, // sub_wacc_lo
9585 0, // sub_vsx1_then_sub_64
9586 0, // sub_vsx1_then_sub_64_hi_phony
9587 0, // sub_pair1_then_sub_64
9588 0, // sub_pair1_then_sub_64_hi_phony
9589 0, // sub_pair1_then_sub_vsx0
9590 0, // sub_pair1_then_sub_vsx1
9591 0, // sub_pair1_then_sub_vsx1_then_sub_64
9592 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9593 0, // sub_dmrrowp1_then_sub_dmrrow0
9594 0, // sub_dmrrowp1_then_sub_dmrrow1
9595 0, // sub_wacc_hi_then_sub_dmrrow0
9596 0, // sub_wacc_hi_then_sub_dmrrow1
9597 0, // sub_wacc_hi_then_sub_dmrrowp0
9598 0, // sub_wacc_hi_then_sub_dmrrowp1
9599 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9600 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9601 0, // sub_dmr1_then_sub_dmrrow0
9602 0, // sub_dmr1_then_sub_dmrrow1
9603 0, // sub_dmr1_then_sub_dmrrowp0
9604 0, // sub_dmr1_then_sub_dmrrowp1
9605 0, // sub_dmr1_then_sub_wacc_hi
9606 0, // sub_dmr1_then_sub_wacc_lo
9607 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9608 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9609 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9610 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9611 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9612 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9613 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9614 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9615 36, // sub_gp8_x1_then_sub_32 -> G8pRC
9616 },
9617 { // G8pRC_with_sub_32_in_GPRC_NOR0
9618 37, // sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
9619 0, // sub_32_hi_phony
9620 0, // sub_64
9621 0, // sub_64_hi_phony
9622 0, // sub_dmr0
9623 0, // sub_dmr1
9624 0, // sub_dmrrow0
9625 0, // sub_dmrrow1
9626 0, // sub_dmrrowp0
9627 0, // sub_dmrrowp1
9628 0, // sub_eq
9629 0, // sub_fp0
9630 0, // sub_fp1
9631 37, // sub_gp8_x0 -> G8pRC_with_sub_32_in_GPRC_NOR0
9632 37, // sub_gp8_x1 -> G8pRC_with_sub_32_in_GPRC_NOR0
9633 0, // sub_gt
9634 0, // sub_lt
9635 0, // sub_pair0
9636 0, // sub_pair1
9637 0, // sub_un
9638 0, // sub_vsx0
9639 0, // sub_vsx1
9640 0, // sub_wacc_hi
9641 0, // sub_wacc_lo
9642 0, // sub_vsx1_then_sub_64
9643 0, // sub_vsx1_then_sub_64_hi_phony
9644 0, // sub_pair1_then_sub_64
9645 0, // sub_pair1_then_sub_64_hi_phony
9646 0, // sub_pair1_then_sub_vsx0
9647 0, // sub_pair1_then_sub_vsx1
9648 0, // sub_pair1_then_sub_vsx1_then_sub_64
9649 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9650 0, // sub_dmrrowp1_then_sub_dmrrow0
9651 0, // sub_dmrrowp1_then_sub_dmrrow1
9652 0, // sub_wacc_hi_then_sub_dmrrow0
9653 0, // sub_wacc_hi_then_sub_dmrrow1
9654 0, // sub_wacc_hi_then_sub_dmrrowp0
9655 0, // sub_wacc_hi_then_sub_dmrrowp1
9656 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9657 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9658 0, // sub_dmr1_then_sub_dmrrow0
9659 0, // sub_dmr1_then_sub_dmrrow1
9660 0, // sub_dmr1_then_sub_dmrrowp0
9661 0, // sub_dmr1_then_sub_dmrrowp1
9662 0, // sub_dmr1_then_sub_wacc_hi
9663 0, // sub_dmr1_then_sub_wacc_lo
9664 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9665 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9666 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9667 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9668 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9669 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9670 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9671 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9672 37, // sub_gp8_x1_then_sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
9673 },
9674 { // VSLRC_with_sub_64_in_SPILLTOVSRRC
9675 0, // sub_32
9676 0, // sub_32_hi_phony
9677 38, // sub_64 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
9678 0, // sub_64_hi_phony
9679 0, // sub_dmr0
9680 0, // sub_dmr1
9681 0, // sub_dmrrow0
9682 0, // sub_dmrrow1
9683 0, // sub_dmrrowp0
9684 0, // sub_dmrrowp1
9685 0, // sub_eq
9686 0, // sub_fp0
9687 0, // sub_fp1
9688 0, // sub_gp8_x0
9689 0, // sub_gp8_x1
9690 0, // sub_gt
9691 0, // sub_lt
9692 0, // sub_pair0
9693 0, // sub_pair1
9694 0, // sub_un
9695 0, // sub_vsx0
9696 0, // sub_vsx1
9697 0, // sub_wacc_hi
9698 0, // sub_wacc_lo
9699 0, // sub_vsx1_then_sub_64
9700 0, // sub_vsx1_then_sub_64_hi_phony
9701 0, // sub_pair1_then_sub_64
9702 0, // sub_pair1_then_sub_64_hi_phony
9703 0, // sub_pair1_then_sub_vsx0
9704 0, // sub_pair1_then_sub_vsx1
9705 0, // sub_pair1_then_sub_vsx1_then_sub_64
9706 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9707 0, // sub_dmrrowp1_then_sub_dmrrow0
9708 0, // sub_dmrrowp1_then_sub_dmrrow1
9709 0, // sub_wacc_hi_then_sub_dmrrow0
9710 0, // sub_wacc_hi_then_sub_dmrrow1
9711 0, // sub_wacc_hi_then_sub_dmrrowp0
9712 0, // sub_wacc_hi_then_sub_dmrrowp1
9713 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9714 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9715 0, // sub_dmr1_then_sub_dmrrow0
9716 0, // sub_dmr1_then_sub_dmrrow1
9717 0, // sub_dmr1_then_sub_dmrrowp0
9718 0, // sub_dmr1_then_sub_dmrrowp1
9719 0, // sub_dmr1_then_sub_wacc_hi
9720 0, // sub_dmr1_then_sub_wacc_lo
9721 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9722 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9723 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9724 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9725 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9726 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9727 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9728 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9729 0, // sub_gp8_x1_then_sub_32
9730 },
9731 { // FpRC_with_sub_fp0_in_SPILLTOVSRRC
9732 0, // sub_32
9733 0, // sub_32_hi_phony
9734 0, // sub_64
9735 0, // sub_64_hi_phony
9736 0, // sub_dmr0
9737 0, // sub_dmr1
9738 0, // sub_dmrrow0
9739 0, // sub_dmrrow1
9740 0, // sub_dmrrowp0
9741 0, // sub_dmrrowp1
9742 0, // sub_eq
9743 39, // sub_fp0 -> FpRC_with_sub_fp0_in_SPILLTOVSRRC
9744 39, // sub_fp1 -> FpRC_with_sub_fp0_in_SPILLTOVSRRC
9745 0, // sub_gp8_x0
9746 0, // sub_gp8_x1
9747 0, // sub_gt
9748 0, // sub_lt
9749 0, // sub_pair0
9750 0, // sub_pair1
9751 0, // sub_un
9752 0, // sub_vsx0
9753 0, // sub_vsx1
9754 0, // sub_wacc_hi
9755 0, // sub_wacc_lo
9756 0, // sub_vsx1_then_sub_64
9757 0, // sub_vsx1_then_sub_64_hi_phony
9758 0, // sub_pair1_then_sub_64
9759 0, // sub_pair1_then_sub_64_hi_phony
9760 0, // sub_pair1_then_sub_vsx0
9761 0, // sub_pair1_then_sub_vsx1
9762 0, // sub_pair1_then_sub_vsx1_then_sub_64
9763 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9764 0, // sub_dmrrowp1_then_sub_dmrrow0
9765 0, // sub_dmrrowp1_then_sub_dmrrow1
9766 0, // sub_wacc_hi_then_sub_dmrrow0
9767 0, // sub_wacc_hi_then_sub_dmrrow1
9768 0, // sub_wacc_hi_then_sub_dmrrowp0
9769 0, // sub_wacc_hi_then_sub_dmrrowp1
9770 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9771 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9772 0, // sub_dmr1_then_sub_dmrrow0
9773 0, // sub_dmr1_then_sub_dmrrow1
9774 0, // sub_dmr1_then_sub_dmrrowp0
9775 0, // sub_dmr1_then_sub_dmrrowp1
9776 0, // sub_dmr1_then_sub_wacc_hi
9777 0, // sub_dmr1_then_sub_wacc_lo
9778 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9779 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9780 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9781 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9782 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9783 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9784 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9785 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9786 0, // sub_gp8_x1_then_sub_32
9787 },
9788 { // DMRROWpRC
9789 0, // sub_32
9790 0, // sub_32_hi_phony
9791 0, // sub_64
9792 0, // sub_64_hi_phony
9793 0, // sub_dmr0
9794 0, // sub_dmr1
9795 40, // sub_dmrrow0 -> DMRROWpRC
9796 40, // sub_dmrrow1 -> DMRROWpRC
9797 0, // sub_dmrrowp0
9798 0, // sub_dmrrowp1
9799 0, // sub_eq
9800 0, // sub_fp0
9801 0, // sub_fp1
9802 0, // sub_gp8_x0
9803 0, // sub_gp8_x1
9804 0, // sub_gt
9805 0, // sub_lt
9806 0, // sub_pair0
9807 0, // sub_pair1
9808 0, // sub_un
9809 0, // sub_vsx0
9810 0, // sub_vsx1
9811 0, // sub_wacc_hi
9812 0, // sub_wacc_lo
9813 0, // sub_vsx1_then_sub_64
9814 0, // sub_vsx1_then_sub_64_hi_phony
9815 0, // sub_pair1_then_sub_64
9816 0, // sub_pair1_then_sub_64_hi_phony
9817 0, // sub_pair1_then_sub_vsx0
9818 0, // sub_pair1_then_sub_vsx1
9819 0, // sub_pair1_then_sub_vsx1_then_sub_64
9820 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9821 0, // sub_dmrrowp1_then_sub_dmrrow0
9822 0, // sub_dmrrowp1_then_sub_dmrrow1
9823 0, // sub_wacc_hi_then_sub_dmrrow0
9824 0, // sub_wacc_hi_then_sub_dmrrow1
9825 0, // sub_wacc_hi_then_sub_dmrrowp0
9826 0, // sub_wacc_hi_then_sub_dmrrowp1
9827 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9828 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9829 0, // sub_dmr1_then_sub_dmrrow0
9830 0, // sub_dmr1_then_sub_dmrrow1
9831 0, // sub_dmr1_then_sub_dmrrowp0
9832 0, // sub_dmr1_then_sub_dmrrowp1
9833 0, // sub_dmr1_then_sub_wacc_hi
9834 0, // sub_dmr1_then_sub_wacc_lo
9835 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9836 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9837 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9838 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9839 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9840 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9841 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9842 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9843 0, // sub_gp8_x1_then_sub_32
9844 },
9845 { // VSRpRC
9846 0, // sub_32
9847 0, // sub_32_hi_phony
9848 41, // sub_64 -> VSRpRC
9849 0, // sub_64_hi_phony
9850 0, // sub_dmr0
9851 0, // sub_dmr1
9852 0, // sub_dmrrow0
9853 0, // sub_dmrrow1
9854 0, // sub_dmrrowp0
9855 0, // sub_dmrrowp1
9856 0, // sub_eq
9857 0, // sub_fp0
9858 0, // sub_fp1
9859 0, // sub_gp8_x0
9860 0, // sub_gp8_x1
9861 0, // sub_gt
9862 0, // sub_lt
9863 0, // sub_pair0
9864 0, // sub_pair1
9865 0, // sub_un
9866 41, // sub_vsx0 -> VSRpRC
9867 41, // sub_vsx1 -> VSRpRC
9868 0, // sub_wacc_hi
9869 0, // sub_wacc_lo
9870 41, // sub_vsx1_then_sub_64 -> VSRpRC
9871 0, // sub_vsx1_then_sub_64_hi_phony
9872 0, // sub_pair1_then_sub_64
9873 0, // sub_pair1_then_sub_64_hi_phony
9874 0, // sub_pair1_then_sub_vsx0
9875 0, // sub_pair1_then_sub_vsx1
9876 0, // sub_pair1_then_sub_vsx1_then_sub_64
9877 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9878 0, // sub_dmrrowp1_then_sub_dmrrow0
9879 0, // sub_dmrrowp1_then_sub_dmrrow1
9880 0, // sub_wacc_hi_then_sub_dmrrow0
9881 0, // sub_wacc_hi_then_sub_dmrrow1
9882 0, // sub_wacc_hi_then_sub_dmrrowp0
9883 0, // sub_wacc_hi_then_sub_dmrrowp1
9884 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9885 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9886 0, // sub_dmr1_then_sub_dmrrow0
9887 0, // sub_dmr1_then_sub_dmrrow1
9888 0, // sub_dmr1_then_sub_dmrrowp0
9889 0, // sub_dmr1_then_sub_dmrrowp1
9890 0, // sub_dmr1_then_sub_wacc_hi
9891 0, // sub_dmr1_then_sub_wacc_lo
9892 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9893 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9894 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9895 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9896 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9897 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9898 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9899 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9900 0, // sub_gp8_x1_then_sub_32
9901 },
9902 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC
9903 0, // sub_32
9904 0, // sub_32_hi_phony
9905 42, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9906 0, // sub_64_hi_phony
9907 0, // sub_dmr0
9908 0, // sub_dmr1
9909 0, // sub_dmrrow0
9910 0, // sub_dmrrow1
9911 0, // sub_dmrrowp0
9912 0, // sub_dmrrowp1
9913 0, // sub_eq
9914 0, // sub_fp0
9915 0, // sub_fp1
9916 0, // sub_gp8_x0
9917 0, // sub_gp8_x1
9918 0, // sub_gt
9919 0, // sub_lt
9920 0, // sub_pair0
9921 0, // sub_pair1
9922 0, // sub_un
9923 42, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9924 42, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9925 0, // sub_wacc_hi
9926 0, // sub_wacc_lo
9927 42, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9928 0, // sub_vsx1_then_sub_64_hi_phony
9929 0, // sub_pair1_then_sub_64
9930 0, // sub_pair1_then_sub_64_hi_phony
9931 0, // sub_pair1_then_sub_vsx0
9932 0, // sub_pair1_then_sub_vsx1
9933 0, // sub_pair1_then_sub_vsx1_then_sub_64
9934 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9935 0, // sub_dmrrowp1_then_sub_dmrrow0
9936 0, // sub_dmrrowp1_then_sub_dmrrow1
9937 0, // sub_wacc_hi_then_sub_dmrrow0
9938 0, // sub_wacc_hi_then_sub_dmrrow1
9939 0, // sub_wacc_hi_then_sub_dmrrowp0
9940 0, // sub_wacc_hi_then_sub_dmrrowp1
9941 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9942 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9943 0, // sub_dmr1_then_sub_dmrrow0
9944 0, // sub_dmr1_then_sub_dmrrow1
9945 0, // sub_dmr1_then_sub_dmrrowp0
9946 0, // sub_dmr1_then_sub_dmrrowp1
9947 0, // sub_dmr1_then_sub_wacc_hi
9948 0, // sub_dmr1_then_sub_wacc_lo
9949 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9950 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9951 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9952 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9953 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9954 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9955 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9956 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9957 0, // sub_gp8_x1_then_sub_32
9958 },
9959 { // VSRpRC_with_sub_64_in_F4RC
9960 0, // sub_32
9961 0, // sub_32_hi_phony
9962 43, // sub_64 -> VSRpRC_with_sub_64_in_F4RC
9963 0, // sub_64_hi_phony
9964 0, // sub_dmr0
9965 0, // sub_dmr1
9966 0, // sub_dmrrow0
9967 0, // sub_dmrrow1
9968 0, // sub_dmrrowp0
9969 0, // sub_dmrrowp1
9970 0, // sub_eq
9971 0, // sub_fp0
9972 0, // sub_fp1
9973 0, // sub_gp8_x0
9974 0, // sub_gp8_x1
9975 0, // sub_gt
9976 0, // sub_lt
9977 0, // sub_pair0
9978 0, // sub_pair1
9979 0, // sub_un
9980 43, // sub_vsx0 -> VSRpRC_with_sub_64_in_F4RC
9981 43, // sub_vsx1 -> VSRpRC_with_sub_64_in_F4RC
9982 0, // sub_wacc_hi
9983 0, // sub_wacc_lo
9984 43, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_F4RC
9985 0, // sub_vsx1_then_sub_64_hi_phony
9986 0, // sub_pair1_then_sub_64
9987 0, // sub_pair1_then_sub_64_hi_phony
9988 0, // sub_pair1_then_sub_vsx0
9989 0, // sub_pair1_then_sub_vsx1
9990 0, // sub_pair1_then_sub_vsx1_then_sub_64
9991 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9992 0, // sub_dmrrowp1_then_sub_dmrrow0
9993 0, // sub_dmrrowp1_then_sub_dmrrow1
9994 0, // sub_wacc_hi_then_sub_dmrrow0
9995 0, // sub_wacc_hi_then_sub_dmrrow1
9996 0, // sub_wacc_hi_then_sub_dmrrowp0
9997 0, // sub_wacc_hi_then_sub_dmrrowp1
9998 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9999 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10000 0, // sub_dmr1_then_sub_dmrrow0
10001 0, // sub_dmr1_then_sub_dmrrow1
10002 0, // sub_dmr1_then_sub_dmrrowp0
10003 0, // sub_dmr1_then_sub_dmrrowp1
10004 0, // sub_dmr1_then_sub_wacc_hi
10005 0, // sub_dmr1_then_sub_wacc_lo
10006 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10007 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10008 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10009 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10010 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10011 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10012 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10013 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10014 0, // sub_gp8_x1_then_sub_32
10015 },
10016 { // VSRpRC_with_sub_64_in_VFRC
10017 0, // sub_32
10018 0, // sub_32_hi_phony
10019 44, // sub_64 -> VSRpRC_with_sub_64_in_VFRC
10020 0, // sub_64_hi_phony
10021 0, // sub_dmr0
10022 0, // sub_dmr1
10023 0, // sub_dmrrow0
10024 0, // sub_dmrrow1
10025 0, // sub_dmrrowp0
10026 0, // sub_dmrrowp1
10027 0, // sub_eq
10028 0, // sub_fp0
10029 0, // sub_fp1
10030 0, // sub_gp8_x0
10031 0, // sub_gp8_x1
10032 0, // sub_gt
10033 0, // sub_lt
10034 0, // sub_pair0
10035 0, // sub_pair1
10036 0, // sub_un
10037 44, // sub_vsx0 -> VSRpRC_with_sub_64_in_VFRC
10038 44, // sub_vsx1 -> VSRpRC_with_sub_64_in_VFRC
10039 0, // sub_wacc_hi
10040 0, // sub_wacc_lo
10041 44, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_VFRC
10042 0, // sub_vsx1_then_sub_64_hi_phony
10043 0, // sub_pair1_then_sub_64
10044 0, // sub_pair1_then_sub_64_hi_phony
10045 0, // sub_pair1_then_sub_vsx0
10046 0, // sub_pair1_then_sub_vsx1
10047 0, // sub_pair1_then_sub_vsx1_then_sub_64
10048 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10049 0, // sub_dmrrowp1_then_sub_dmrrow0
10050 0, // sub_dmrrowp1_then_sub_dmrrow1
10051 0, // sub_wacc_hi_then_sub_dmrrow0
10052 0, // sub_wacc_hi_then_sub_dmrrow1
10053 0, // sub_wacc_hi_then_sub_dmrrowp0
10054 0, // sub_wacc_hi_then_sub_dmrrowp1
10055 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10056 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10057 0, // sub_dmr1_then_sub_dmrrow0
10058 0, // sub_dmr1_then_sub_dmrrow1
10059 0, // sub_dmr1_then_sub_dmrrowp0
10060 0, // sub_dmr1_then_sub_dmrrowp1
10061 0, // sub_dmr1_then_sub_wacc_hi
10062 0, // sub_dmr1_then_sub_wacc_lo
10063 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10064 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10065 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10066 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10067 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10068 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10069 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10070 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10071 0, // sub_gp8_x1_then_sub_32
10072 },
10073 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10074 0, // sub_32
10075 0, // sub_32_hi_phony
10076 45, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10077 0, // sub_64_hi_phony
10078 0, // sub_dmr0
10079 0, // sub_dmr1
10080 0, // sub_dmrrow0
10081 0, // sub_dmrrow1
10082 0, // sub_dmrrowp0
10083 0, // sub_dmrrowp1
10084 0, // sub_eq
10085 0, // sub_fp0
10086 0, // sub_fp1
10087 0, // sub_gp8_x0
10088 0, // sub_gp8_x1
10089 0, // sub_gt
10090 0, // sub_lt
10091 0, // sub_pair0
10092 0, // sub_pair1
10093 0, // sub_un
10094 45, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10095 45, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10096 0, // sub_wacc_hi
10097 0, // sub_wacc_lo
10098 45, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10099 0, // sub_vsx1_then_sub_64_hi_phony
10100 0, // sub_pair1_then_sub_64
10101 0, // sub_pair1_then_sub_64_hi_phony
10102 0, // sub_pair1_then_sub_vsx0
10103 0, // sub_pair1_then_sub_vsx1
10104 0, // sub_pair1_then_sub_vsx1_then_sub_64
10105 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10106 0, // sub_dmrrowp1_then_sub_dmrrow0
10107 0, // sub_dmrrowp1_then_sub_dmrrow1
10108 0, // sub_wacc_hi_then_sub_dmrrow0
10109 0, // sub_wacc_hi_then_sub_dmrrow1
10110 0, // sub_wacc_hi_then_sub_dmrrowp0
10111 0, // sub_wacc_hi_then_sub_dmrrowp1
10112 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10113 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10114 0, // sub_dmr1_then_sub_dmrrow0
10115 0, // sub_dmr1_then_sub_dmrrow1
10116 0, // sub_dmr1_then_sub_dmrrowp0
10117 0, // sub_dmr1_then_sub_dmrrowp1
10118 0, // sub_dmr1_then_sub_wacc_hi
10119 0, // sub_dmr1_then_sub_wacc_lo
10120 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10121 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10122 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10123 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10124 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10125 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10126 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10127 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10128 0, // sub_gp8_x1_then_sub_32
10129 },
10130 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10131 0, // sub_32
10132 0, // sub_32_hi_phony
10133 46, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10134 0, // sub_64_hi_phony
10135 0, // sub_dmr0
10136 0, // sub_dmr1
10137 0, // sub_dmrrow0
10138 0, // sub_dmrrow1
10139 0, // sub_dmrrowp0
10140 0, // sub_dmrrowp1
10141 0, // sub_eq
10142 0, // sub_fp0
10143 0, // sub_fp1
10144 0, // sub_gp8_x0
10145 0, // sub_gp8_x1
10146 0, // sub_gt
10147 0, // sub_lt
10148 0, // sub_pair0
10149 0, // sub_pair1
10150 0, // sub_un
10151 46, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10152 46, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10153 0, // sub_wacc_hi
10154 0, // sub_wacc_lo
10155 46, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10156 0, // sub_vsx1_then_sub_64_hi_phony
10157 0, // sub_pair1_then_sub_64
10158 0, // sub_pair1_then_sub_64_hi_phony
10159 0, // sub_pair1_then_sub_vsx0
10160 0, // sub_pair1_then_sub_vsx1
10161 0, // sub_pair1_then_sub_vsx1_then_sub_64
10162 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10163 0, // sub_dmrrowp1_then_sub_dmrrow0
10164 0, // sub_dmrrowp1_then_sub_dmrrow1
10165 0, // sub_wacc_hi_then_sub_dmrrow0
10166 0, // sub_wacc_hi_then_sub_dmrrow1
10167 0, // sub_wacc_hi_then_sub_dmrrowp0
10168 0, // sub_wacc_hi_then_sub_dmrrowp1
10169 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10170 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10171 0, // sub_dmr1_then_sub_dmrrow0
10172 0, // sub_dmr1_then_sub_dmrrow1
10173 0, // sub_dmr1_then_sub_dmrrowp0
10174 0, // sub_dmr1_then_sub_dmrrowp1
10175 0, // sub_dmr1_then_sub_wacc_hi
10176 0, // sub_dmr1_then_sub_wacc_lo
10177 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10178 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10179 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10180 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10181 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10182 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10183 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10184 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10185 0, // sub_gp8_x1_then_sub_32
10186 },
10187 { // ACCRC
10188 0, // sub_32
10189 0, // sub_32_hi_phony
10190 47, // sub_64 -> ACCRC
10191 0, // sub_64_hi_phony
10192 0, // sub_dmr0
10193 0, // sub_dmr1
10194 0, // sub_dmrrow0
10195 0, // sub_dmrrow1
10196 0, // sub_dmrrowp0
10197 0, // sub_dmrrowp1
10198 0, // sub_eq
10199 0, // sub_fp0
10200 0, // sub_fp1
10201 0, // sub_gp8_x0
10202 0, // sub_gp8_x1
10203 0, // sub_gt
10204 0, // sub_lt
10205 47, // sub_pair0 -> ACCRC
10206 47, // sub_pair1 -> ACCRC
10207 0, // sub_un
10208 47, // sub_vsx0 -> ACCRC
10209 47, // sub_vsx1 -> ACCRC
10210 0, // sub_wacc_hi
10211 0, // sub_wacc_lo
10212 47, // sub_vsx1_then_sub_64 -> ACCRC
10213 0, // sub_vsx1_then_sub_64_hi_phony
10214 47, // sub_pair1_then_sub_64 -> ACCRC
10215 0, // sub_pair1_then_sub_64_hi_phony
10216 47, // sub_pair1_then_sub_vsx0 -> ACCRC
10217 47, // sub_pair1_then_sub_vsx1 -> ACCRC
10218 47, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC
10219 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10220 0, // sub_dmrrowp1_then_sub_dmrrow0
10221 0, // sub_dmrrowp1_then_sub_dmrrow1
10222 0, // sub_wacc_hi_then_sub_dmrrow0
10223 0, // sub_wacc_hi_then_sub_dmrrow1
10224 0, // sub_wacc_hi_then_sub_dmrrowp0
10225 0, // sub_wacc_hi_then_sub_dmrrowp1
10226 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10227 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10228 0, // sub_dmr1_then_sub_dmrrow0
10229 0, // sub_dmr1_then_sub_dmrrow1
10230 0, // sub_dmr1_then_sub_dmrrowp0
10231 0, // sub_dmr1_then_sub_dmrrowp1
10232 0, // sub_dmr1_then_sub_wacc_hi
10233 0, // sub_dmr1_then_sub_wacc_lo
10234 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10235 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10236 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10237 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10238 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10239 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10240 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10241 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10242 0, // sub_gp8_x1_then_sub_32
10243 },
10244 { // UACCRC
10245 0, // sub_32
10246 0, // sub_32_hi_phony
10247 48, // sub_64 -> UACCRC
10248 0, // sub_64_hi_phony
10249 0, // sub_dmr0
10250 0, // sub_dmr1
10251 0, // sub_dmrrow0
10252 0, // sub_dmrrow1
10253 0, // sub_dmrrowp0
10254 0, // sub_dmrrowp1
10255 0, // sub_eq
10256 0, // sub_fp0
10257 0, // sub_fp1
10258 0, // sub_gp8_x0
10259 0, // sub_gp8_x1
10260 0, // sub_gt
10261 0, // sub_lt
10262 48, // sub_pair0 -> UACCRC
10263 48, // sub_pair1 -> UACCRC
10264 0, // sub_un
10265 48, // sub_vsx0 -> UACCRC
10266 48, // sub_vsx1 -> UACCRC
10267 0, // sub_wacc_hi
10268 0, // sub_wacc_lo
10269 48, // sub_vsx1_then_sub_64 -> UACCRC
10270 0, // sub_vsx1_then_sub_64_hi_phony
10271 48, // sub_pair1_then_sub_64 -> UACCRC
10272 0, // sub_pair1_then_sub_64_hi_phony
10273 48, // sub_pair1_then_sub_vsx0 -> UACCRC
10274 48, // sub_pair1_then_sub_vsx1 -> UACCRC
10275 48, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC
10276 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10277 0, // sub_dmrrowp1_then_sub_dmrrow0
10278 0, // sub_dmrrowp1_then_sub_dmrrow1
10279 0, // sub_wacc_hi_then_sub_dmrrow0
10280 0, // sub_wacc_hi_then_sub_dmrrow1
10281 0, // sub_wacc_hi_then_sub_dmrrowp0
10282 0, // sub_wacc_hi_then_sub_dmrrowp1
10283 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10284 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10285 0, // sub_dmr1_then_sub_dmrrow0
10286 0, // sub_dmr1_then_sub_dmrrow1
10287 0, // sub_dmr1_then_sub_dmrrowp0
10288 0, // sub_dmr1_then_sub_dmrrowp1
10289 0, // sub_dmr1_then_sub_wacc_hi
10290 0, // sub_dmr1_then_sub_wacc_lo
10291 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10292 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10293 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10294 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10295 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10296 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10297 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10298 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10299 0, // sub_gp8_x1_then_sub_32
10300 },
10301 { // WACCRC
10302 0, // sub_32
10303 0, // sub_32_hi_phony
10304 0, // sub_64
10305 0, // sub_64_hi_phony
10306 0, // sub_dmr0
10307 0, // sub_dmr1
10308 49, // sub_dmrrow0 -> WACCRC
10309 49, // sub_dmrrow1 -> WACCRC
10310 49, // sub_dmrrowp0 -> WACCRC
10311 49, // sub_dmrrowp1 -> WACCRC
10312 0, // sub_eq
10313 0, // sub_fp0
10314 0, // sub_fp1
10315 0, // sub_gp8_x0
10316 0, // sub_gp8_x1
10317 0, // sub_gt
10318 0, // sub_lt
10319 0, // sub_pair0
10320 0, // sub_pair1
10321 0, // sub_un
10322 0, // sub_vsx0
10323 0, // sub_vsx1
10324 0, // sub_wacc_hi
10325 0, // sub_wacc_lo
10326 0, // sub_vsx1_then_sub_64
10327 0, // sub_vsx1_then_sub_64_hi_phony
10328 0, // sub_pair1_then_sub_64
10329 0, // sub_pair1_then_sub_64_hi_phony
10330 0, // sub_pair1_then_sub_vsx0
10331 0, // sub_pair1_then_sub_vsx1
10332 0, // sub_pair1_then_sub_vsx1_then_sub_64
10333 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10334 49, // sub_dmrrowp1_then_sub_dmrrow0 -> WACCRC
10335 49, // sub_dmrrowp1_then_sub_dmrrow1 -> WACCRC
10336 0, // sub_wacc_hi_then_sub_dmrrow0
10337 0, // sub_wacc_hi_then_sub_dmrrow1
10338 0, // sub_wacc_hi_then_sub_dmrrowp0
10339 0, // sub_wacc_hi_then_sub_dmrrowp1
10340 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10341 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10342 0, // sub_dmr1_then_sub_dmrrow0
10343 0, // sub_dmr1_then_sub_dmrrow1
10344 0, // sub_dmr1_then_sub_dmrrowp0
10345 0, // sub_dmr1_then_sub_dmrrowp1
10346 0, // sub_dmr1_then_sub_wacc_hi
10347 0, // sub_dmr1_then_sub_wacc_lo
10348 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10349 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10350 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10351 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10352 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10353 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10354 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10355 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10356 0, // sub_gp8_x1_then_sub_32
10357 },
10358 { // WACC_HIRC
10359 0, // sub_32
10360 0, // sub_32_hi_phony
10361 0, // sub_64
10362 0, // sub_64_hi_phony
10363 0, // sub_dmr0
10364 0, // sub_dmr1
10365 50, // sub_dmrrow0 -> WACC_HIRC
10366 50, // sub_dmrrow1 -> WACC_HIRC
10367 50, // sub_dmrrowp0 -> WACC_HIRC
10368 50, // sub_dmrrowp1 -> WACC_HIRC
10369 0, // sub_eq
10370 0, // sub_fp0
10371 0, // sub_fp1
10372 0, // sub_gp8_x0
10373 0, // sub_gp8_x1
10374 0, // sub_gt
10375 0, // sub_lt
10376 0, // sub_pair0
10377 0, // sub_pair1
10378 0, // sub_un
10379 0, // sub_vsx0
10380 0, // sub_vsx1
10381 0, // sub_wacc_hi
10382 0, // sub_wacc_lo
10383 0, // sub_vsx1_then_sub_64
10384 0, // sub_vsx1_then_sub_64_hi_phony
10385 0, // sub_pair1_then_sub_64
10386 0, // sub_pair1_then_sub_64_hi_phony
10387 0, // sub_pair1_then_sub_vsx0
10388 0, // sub_pair1_then_sub_vsx1
10389 0, // sub_pair1_then_sub_vsx1_then_sub_64
10390 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10391 50, // sub_dmrrowp1_then_sub_dmrrow0 -> WACC_HIRC
10392 50, // sub_dmrrowp1_then_sub_dmrrow1 -> WACC_HIRC
10393 0, // sub_wacc_hi_then_sub_dmrrow0
10394 0, // sub_wacc_hi_then_sub_dmrrow1
10395 0, // sub_wacc_hi_then_sub_dmrrowp0
10396 0, // sub_wacc_hi_then_sub_dmrrowp1
10397 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10398 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10399 0, // sub_dmr1_then_sub_dmrrow0
10400 0, // sub_dmr1_then_sub_dmrrow1
10401 0, // sub_dmr1_then_sub_dmrrowp0
10402 0, // sub_dmr1_then_sub_dmrrowp1
10403 0, // sub_dmr1_then_sub_wacc_hi
10404 0, // sub_dmr1_then_sub_wacc_lo
10405 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10406 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10407 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10408 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10409 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10410 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10411 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10412 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10413 0, // sub_gp8_x1_then_sub_32
10414 },
10415 { // ACCRC_with_sub_64_in_SPILLTOVSRRC
10416 0, // sub_32
10417 0, // sub_32_hi_phony
10418 51, // sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10419 0, // sub_64_hi_phony
10420 0, // sub_dmr0
10421 0, // sub_dmr1
10422 0, // sub_dmrrow0
10423 0, // sub_dmrrow1
10424 0, // sub_dmrrowp0
10425 0, // sub_dmrrowp1
10426 0, // sub_eq
10427 0, // sub_fp0
10428 0, // sub_fp1
10429 0, // sub_gp8_x0
10430 0, // sub_gp8_x1
10431 0, // sub_gt
10432 0, // sub_lt
10433 51, // sub_pair0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10434 51, // sub_pair1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10435 0, // sub_un
10436 51, // sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10437 51, // sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10438 0, // sub_wacc_hi
10439 0, // sub_wacc_lo
10440 51, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10441 0, // sub_vsx1_then_sub_64_hi_phony
10442 51, // sub_pair1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10443 0, // sub_pair1_then_sub_64_hi_phony
10444 51, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10445 51, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10446 51, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10447 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10448 0, // sub_dmrrowp1_then_sub_dmrrow0
10449 0, // sub_dmrrowp1_then_sub_dmrrow1
10450 0, // sub_wacc_hi_then_sub_dmrrow0
10451 0, // sub_wacc_hi_then_sub_dmrrow1
10452 0, // sub_wacc_hi_then_sub_dmrrowp0
10453 0, // sub_wacc_hi_then_sub_dmrrowp1
10454 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10455 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10456 0, // sub_dmr1_then_sub_dmrrow0
10457 0, // sub_dmr1_then_sub_dmrrow1
10458 0, // sub_dmr1_then_sub_dmrrowp0
10459 0, // sub_dmr1_then_sub_dmrrowp1
10460 0, // sub_dmr1_then_sub_wacc_hi
10461 0, // sub_dmr1_then_sub_wacc_lo
10462 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10463 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10464 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10465 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10466 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10467 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10468 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10469 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10470 0, // sub_gp8_x1_then_sub_32
10471 },
10472 { // UACCRC_with_sub_64_in_SPILLTOVSRRC
10473 0, // sub_32
10474 0, // sub_32_hi_phony
10475 52, // sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10476 0, // sub_64_hi_phony
10477 0, // sub_dmr0
10478 0, // sub_dmr1
10479 0, // sub_dmrrow0
10480 0, // sub_dmrrow1
10481 0, // sub_dmrrowp0
10482 0, // sub_dmrrowp1
10483 0, // sub_eq
10484 0, // sub_fp0
10485 0, // sub_fp1
10486 0, // sub_gp8_x0
10487 0, // sub_gp8_x1
10488 0, // sub_gt
10489 0, // sub_lt
10490 52, // sub_pair0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10491 52, // sub_pair1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10492 0, // sub_un
10493 52, // sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10494 52, // sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10495 0, // sub_wacc_hi
10496 0, // sub_wacc_lo
10497 52, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10498 0, // sub_vsx1_then_sub_64_hi_phony
10499 52, // sub_pair1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10500 0, // sub_pair1_then_sub_64_hi_phony
10501 52, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10502 52, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10503 52, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10504 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10505 0, // sub_dmrrowp1_then_sub_dmrrow0
10506 0, // sub_dmrrowp1_then_sub_dmrrow1
10507 0, // sub_wacc_hi_then_sub_dmrrow0
10508 0, // sub_wacc_hi_then_sub_dmrrow1
10509 0, // sub_wacc_hi_then_sub_dmrrowp0
10510 0, // sub_wacc_hi_then_sub_dmrrowp1
10511 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10512 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10513 0, // sub_dmr1_then_sub_dmrrow0
10514 0, // sub_dmr1_then_sub_dmrrow1
10515 0, // sub_dmr1_then_sub_dmrrowp0
10516 0, // sub_dmr1_then_sub_dmrrowp1
10517 0, // sub_dmr1_then_sub_wacc_hi
10518 0, // sub_dmr1_then_sub_wacc_lo
10519 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10520 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10521 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10522 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10523 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10524 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10525 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10526 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10527 0, // sub_gp8_x1_then_sub_32
10528 },
10529 { // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10530 0, // sub_32
10531 0, // sub_32_hi_phony
10532 53, // sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10533 0, // sub_64_hi_phony
10534 0, // sub_dmr0
10535 0, // sub_dmr1
10536 0, // sub_dmrrow0
10537 0, // sub_dmrrow1
10538 0, // sub_dmrrowp0
10539 0, // sub_dmrrowp1
10540 0, // sub_eq
10541 0, // sub_fp0
10542 0, // sub_fp1
10543 0, // sub_gp8_x0
10544 0, // sub_gp8_x1
10545 0, // sub_gt
10546 0, // sub_lt
10547 53, // sub_pair0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10548 53, // sub_pair1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10549 0, // sub_un
10550 53, // sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10551 53, // sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10552 0, // sub_wacc_hi
10553 0, // sub_wacc_lo
10554 53, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10555 0, // sub_vsx1_then_sub_64_hi_phony
10556 53, // sub_pair1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10557 0, // sub_pair1_then_sub_64_hi_phony
10558 53, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10559 53, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10560 53, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10561 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10562 0, // sub_dmrrowp1_then_sub_dmrrow0
10563 0, // sub_dmrrowp1_then_sub_dmrrow1
10564 0, // sub_wacc_hi_then_sub_dmrrow0
10565 0, // sub_wacc_hi_then_sub_dmrrow1
10566 0, // sub_wacc_hi_then_sub_dmrrowp0
10567 0, // sub_wacc_hi_then_sub_dmrrowp1
10568 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10569 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10570 0, // sub_dmr1_then_sub_dmrrow0
10571 0, // sub_dmr1_then_sub_dmrrow1
10572 0, // sub_dmr1_then_sub_dmrrowp0
10573 0, // sub_dmr1_then_sub_dmrrowp1
10574 0, // sub_dmr1_then_sub_wacc_hi
10575 0, // sub_dmr1_then_sub_wacc_lo
10576 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10577 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10578 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10579 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10580 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10581 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10582 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10583 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10584 0, // sub_gp8_x1_then_sub_32
10585 },
10586 { // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10587 0, // sub_32
10588 0, // sub_32_hi_phony
10589 54, // sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10590 0, // sub_64_hi_phony
10591 0, // sub_dmr0
10592 0, // sub_dmr1
10593 0, // sub_dmrrow0
10594 0, // sub_dmrrow1
10595 0, // sub_dmrrowp0
10596 0, // sub_dmrrowp1
10597 0, // sub_eq
10598 0, // sub_fp0
10599 0, // sub_fp1
10600 0, // sub_gp8_x0
10601 0, // sub_gp8_x1
10602 0, // sub_gt
10603 0, // sub_lt
10604 54, // sub_pair0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10605 54, // sub_pair1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10606 0, // sub_un
10607 54, // sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10608 54, // sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10609 0, // sub_wacc_hi
10610 0, // sub_wacc_lo
10611 54, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10612 0, // sub_vsx1_then_sub_64_hi_phony
10613 54, // sub_pair1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10614 0, // sub_pair1_then_sub_64_hi_phony
10615 54, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10616 54, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10617 54, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10618 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10619 0, // sub_dmrrowp1_then_sub_dmrrow0
10620 0, // sub_dmrrowp1_then_sub_dmrrow1
10621 0, // sub_wacc_hi_then_sub_dmrrow0
10622 0, // sub_wacc_hi_then_sub_dmrrow1
10623 0, // sub_wacc_hi_then_sub_dmrrowp0
10624 0, // sub_wacc_hi_then_sub_dmrrowp1
10625 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10626 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10627 0, // sub_dmr1_then_sub_dmrrow0
10628 0, // sub_dmr1_then_sub_dmrrow1
10629 0, // sub_dmr1_then_sub_dmrrowp0
10630 0, // sub_dmr1_then_sub_dmrrowp1
10631 0, // sub_dmr1_then_sub_wacc_hi
10632 0, // sub_dmr1_then_sub_wacc_lo
10633 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10634 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10635 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10636 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10637 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10638 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10639 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10640 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10641 0, // sub_gp8_x1_then_sub_32
10642 },
10643 { // DMRRC
10644 0, // sub_32
10645 0, // sub_32_hi_phony
10646 0, // sub_64
10647 0, // sub_64_hi_phony
10648 0, // sub_dmr0
10649 0, // sub_dmr1
10650 55, // sub_dmrrow0 -> DMRRC
10651 55, // sub_dmrrow1 -> DMRRC
10652 55, // sub_dmrrowp0 -> DMRRC
10653 55, // sub_dmrrowp1 -> DMRRC
10654 0, // sub_eq
10655 0, // sub_fp0
10656 0, // sub_fp1
10657 0, // sub_gp8_x0
10658 0, // sub_gp8_x1
10659 0, // sub_gt
10660 0, // sub_lt
10661 0, // sub_pair0
10662 0, // sub_pair1
10663 0, // sub_un
10664 0, // sub_vsx0
10665 0, // sub_vsx1
10666 55, // sub_wacc_hi -> DMRRC
10667 55, // sub_wacc_lo -> DMRRC
10668 0, // sub_vsx1_then_sub_64
10669 0, // sub_vsx1_then_sub_64_hi_phony
10670 0, // sub_pair1_then_sub_64
10671 0, // sub_pair1_then_sub_64_hi_phony
10672 0, // sub_pair1_then_sub_vsx0
10673 0, // sub_pair1_then_sub_vsx1
10674 0, // sub_pair1_then_sub_vsx1_then_sub_64
10675 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10676 55, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
10677 55, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
10678 55, // sub_wacc_hi_then_sub_dmrrow0 -> DMRRC
10679 55, // sub_wacc_hi_then_sub_dmrrow1 -> DMRRC
10680 55, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRRC
10681 55, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRRC
10682 55, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
10683 55, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
10684 0, // sub_dmr1_then_sub_dmrrow0
10685 0, // sub_dmr1_then_sub_dmrrow1
10686 0, // sub_dmr1_then_sub_dmrrowp0
10687 0, // sub_dmr1_then_sub_dmrrowp1
10688 0, // sub_dmr1_then_sub_wacc_hi
10689 0, // sub_dmr1_then_sub_wacc_lo
10690 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10691 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10692 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10693 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10694 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10695 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10696 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10697 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10698 0, // sub_gp8_x1_then_sub_32
10699 },
10700 { // DMRpRC
10701 0, // sub_32
10702 0, // sub_32_hi_phony
10703 0, // sub_64
10704 0, // sub_64_hi_phony
10705 56, // sub_dmr0 -> DMRpRC
10706 56, // sub_dmr1 -> DMRpRC
10707 56, // sub_dmrrow0 -> DMRpRC
10708 56, // sub_dmrrow1 -> DMRpRC
10709 56, // sub_dmrrowp0 -> DMRpRC
10710 56, // sub_dmrrowp1 -> DMRpRC
10711 0, // sub_eq
10712 0, // sub_fp0
10713 0, // sub_fp1
10714 0, // sub_gp8_x0
10715 0, // sub_gp8_x1
10716 0, // sub_gt
10717 0, // sub_lt
10718 0, // sub_pair0
10719 0, // sub_pair1
10720 0, // sub_un
10721 0, // sub_vsx0
10722 0, // sub_vsx1
10723 56, // sub_wacc_hi -> DMRpRC
10724 56, // sub_wacc_lo -> DMRpRC
10725 0, // sub_vsx1_then_sub_64
10726 0, // sub_vsx1_then_sub_64_hi_phony
10727 0, // sub_pair1_then_sub_64
10728 0, // sub_pair1_then_sub_64_hi_phony
10729 0, // sub_pair1_then_sub_vsx0
10730 0, // sub_pair1_then_sub_vsx1
10731 0, // sub_pair1_then_sub_vsx1_then_sub_64
10732 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10733 56, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10734 56, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10735 56, // sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
10736 56, // sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
10737 56, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
10738 56, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
10739 56, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10740 56, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10741 56, // sub_dmr1_then_sub_dmrrow0 -> DMRpRC
10742 56, // sub_dmr1_then_sub_dmrrow1 -> DMRpRC
10743 56, // sub_dmr1_then_sub_dmrrowp0 -> DMRpRC
10744 56, // sub_dmr1_then_sub_dmrrowp1 -> DMRpRC
10745 56, // sub_dmr1_then_sub_wacc_hi -> DMRpRC
10746 56, // sub_dmr1_then_sub_wacc_lo -> DMRpRC
10747 56, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10748 56, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10749 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
10750 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
10751 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
10752 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
10753 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10754 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10755 0, // sub_gp8_x1_then_sub_32
10756 },
10757 };
10758 assert(RC && "Missing regclass");
10759 if (!Idx) return RC;
10760 --Idx;
10761 assert(Idx < 55 && "Bad subreg");
10762 unsigned TV = Table[RC->getID()][Idx];
10763 return TV ? getRegClass(TV - 1) : nullptr;
10764}
10765
10766const TargetRegisterClass *PPCGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
10767 static const uint8_t Table[56][55] = {
10768 { // VSSRC
10769 0, // VSSRC:sub_32
10770 0, // VSSRC:sub_32_hi_phony
10771 0, // VSSRC:sub_64
10772 0, // VSSRC:sub_64_hi_phony
10773 0, // VSSRC:sub_dmr0
10774 0, // VSSRC:sub_dmr1
10775 0, // VSSRC:sub_dmrrow0
10776 0, // VSSRC:sub_dmrrow1
10777 0, // VSSRC:sub_dmrrowp0
10778 0, // VSSRC:sub_dmrrowp1
10779 0, // VSSRC:sub_eq
10780 0, // VSSRC:sub_fp0
10781 0, // VSSRC:sub_fp1
10782 0, // VSSRC:sub_gp8_x0
10783 0, // VSSRC:sub_gp8_x1
10784 0, // VSSRC:sub_gt
10785 0, // VSSRC:sub_lt
10786 0, // VSSRC:sub_pair0
10787 0, // VSSRC:sub_pair1
10788 0, // VSSRC:sub_un
10789 0, // VSSRC:sub_vsx0
10790 0, // VSSRC:sub_vsx1
10791 0, // VSSRC:sub_wacc_hi
10792 0, // VSSRC:sub_wacc_lo
10793 0, // VSSRC:sub_vsx1_then_sub_64
10794 0, // VSSRC:sub_vsx1_then_sub_64_hi_phony
10795 0, // VSSRC:sub_pair1_then_sub_64
10796 0, // VSSRC:sub_pair1_then_sub_64_hi_phony
10797 0, // VSSRC:sub_pair1_then_sub_vsx0
10798 0, // VSSRC:sub_pair1_then_sub_vsx1
10799 0, // VSSRC:sub_pair1_then_sub_vsx1_then_sub_64
10800 0, // VSSRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10801 0, // VSSRC:sub_dmrrowp1_then_sub_dmrrow0
10802 0, // VSSRC:sub_dmrrowp1_then_sub_dmrrow1
10803 0, // VSSRC:sub_wacc_hi_then_sub_dmrrow0
10804 0, // VSSRC:sub_wacc_hi_then_sub_dmrrow1
10805 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp0
10806 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1
10807 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10808 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10809 0, // VSSRC:sub_dmr1_then_sub_dmrrow0
10810 0, // VSSRC:sub_dmr1_then_sub_dmrrow1
10811 0, // VSSRC:sub_dmr1_then_sub_dmrrowp0
10812 0, // VSSRC:sub_dmr1_then_sub_dmrrowp1
10813 0, // VSSRC:sub_dmr1_then_sub_wacc_hi
10814 0, // VSSRC:sub_dmr1_then_sub_wacc_lo
10815 0, // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10816 0, // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10817 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10818 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10819 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10820 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10821 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10822 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10823 0, // VSSRC:sub_gp8_x1_then_sub_32
10824 },
10825 { // GPRC
10826 0, // GPRC:sub_32
10827 0, // GPRC:sub_32_hi_phony
10828 0, // GPRC:sub_64
10829 0, // GPRC:sub_64_hi_phony
10830 0, // GPRC:sub_dmr0
10831 0, // GPRC:sub_dmr1
10832 0, // GPRC:sub_dmrrow0
10833 0, // GPRC:sub_dmrrow1
10834 0, // GPRC:sub_dmrrowp0
10835 0, // GPRC:sub_dmrrowp1
10836 0, // GPRC:sub_eq
10837 0, // GPRC:sub_fp0
10838 0, // GPRC:sub_fp1
10839 0, // GPRC:sub_gp8_x0
10840 0, // GPRC:sub_gp8_x1
10841 0, // GPRC:sub_gt
10842 0, // GPRC:sub_lt
10843 0, // GPRC:sub_pair0
10844 0, // GPRC:sub_pair1
10845 0, // GPRC:sub_un
10846 0, // GPRC:sub_vsx0
10847 0, // GPRC:sub_vsx1
10848 0, // GPRC:sub_wacc_hi
10849 0, // GPRC:sub_wacc_lo
10850 0, // GPRC:sub_vsx1_then_sub_64
10851 0, // GPRC:sub_vsx1_then_sub_64_hi_phony
10852 0, // GPRC:sub_pair1_then_sub_64
10853 0, // GPRC:sub_pair1_then_sub_64_hi_phony
10854 0, // GPRC:sub_pair1_then_sub_vsx0
10855 0, // GPRC:sub_pair1_then_sub_vsx1
10856 0, // GPRC:sub_pair1_then_sub_vsx1_then_sub_64
10857 0, // GPRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10858 0, // GPRC:sub_dmrrowp1_then_sub_dmrrow0
10859 0, // GPRC:sub_dmrrowp1_then_sub_dmrrow1
10860 0, // GPRC:sub_wacc_hi_then_sub_dmrrow0
10861 0, // GPRC:sub_wacc_hi_then_sub_dmrrow1
10862 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp0
10863 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1
10864 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10865 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10866 0, // GPRC:sub_dmr1_then_sub_dmrrow0
10867 0, // GPRC:sub_dmr1_then_sub_dmrrow1
10868 0, // GPRC:sub_dmr1_then_sub_dmrrowp0
10869 0, // GPRC:sub_dmr1_then_sub_dmrrowp1
10870 0, // GPRC:sub_dmr1_then_sub_wacc_hi
10871 0, // GPRC:sub_dmr1_then_sub_wacc_lo
10872 0, // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10873 0, // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10874 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10875 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10876 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10877 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10878 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10879 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10880 0, // GPRC:sub_gp8_x1_then_sub_32
10881 },
10882 { // GPRC_NOR0
10883 0, // GPRC_NOR0:sub_32
10884 0, // GPRC_NOR0:sub_32_hi_phony
10885 0, // GPRC_NOR0:sub_64
10886 0, // GPRC_NOR0:sub_64_hi_phony
10887 0, // GPRC_NOR0:sub_dmr0
10888 0, // GPRC_NOR0:sub_dmr1
10889 0, // GPRC_NOR0:sub_dmrrow0
10890 0, // GPRC_NOR0:sub_dmrrow1
10891 0, // GPRC_NOR0:sub_dmrrowp0
10892 0, // GPRC_NOR0:sub_dmrrowp1
10893 0, // GPRC_NOR0:sub_eq
10894 0, // GPRC_NOR0:sub_fp0
10895 0, // GPRC_NOR0:sub_fp1
10896 0, // GPRC_NOR0:sub_gp8_x0
10897 0, // GPRC_NOR0:sub_gp8_x1
10898 0, // GPRC_NOR0:sub_gt
10899 0, // GPRC_NOR0:sub_lt
10900 0, // GPRC_NOR0:sub_pair0
10901 0, // GPRC_NOR0:sub_pair1
10902 0, // GPRC_NOR0:sub_un
10903 0, // GPRC_NOR0:sub_vsx0
10904 0, // GPRC_NOR0:sub_vsx1
10905 0, // GPRC_NOR0:sub_wacc_hi
10906 0, // GPRC_NOR0:sub_wacc_lo
10907 0, // GPRC_NOR0:sub_vsx1_then_sub_64
10908 0, // GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
10909 0, // GPRC_NOR0:sub_pair1_then_sub_64
10910 0, // GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
10911 0, // GPRC_NOR0:sub_pair1_then_sub_vsx0
10912 0, // GPRC_NOR0:sub_pair1_then_sub_vsx1
10913 0, // GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
10914 0, // GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10915 0, // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
10916 0, // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
10917 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
10918 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
10919 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
10920 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
10921 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10922 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10923 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
10924 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
10925 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
10926 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
10927 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
10928 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
10929 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10930 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10931 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10932 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10933 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10934 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10935 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10936 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10937 0, // GPRC_NOR0:sub_gp8_x1_then_sub_32
10938 },
10939 { // GPRC_and_GPRC_NOR0
10940 0, // GPRC_and_GPRC_NOR0:sub_32
10941 0, // GPRC_and_GPRC_NOR0:sub_32_hi_phony
10942 0, // GPRC_and_GPRC_NOR0:sub_64
10943 0, // GPRC_and_GPRC_NOR0:sub_64_hi_phony
10944 0, // GPRC_and_GPRC_NOR0:sub_dmr0
10945 0, // GPRC_and_GPRC_NOR0:sub_dmr1
10946 0, // GPRC_and_GPRC_NOR0:sub_dmrrow0
10947 0, // GPRC_and_GPRC_NOR0:sub_dmrrow1
10948 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp0
10949 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1
10950 0, // GPRC_and_GPRC_NOR0:sub_eq
10951 0, // GPRC_and_GPRC_NOR0:sub_fp0
10952 0, // GPRC_and_GPRC_NOR0:sub_fp1
10953 0, // GPRC_and_GPRC_NOR0:sub_gp8_x0
10954 0, // GPRC_and_GPRC_NOR0:sub_gp8_x1
10955 0, // GPRC_and_GPRC_NOR0:sub_gt
10956 0, // GPRC_and_GPRC_NOR0:sub_lt
10957 0, // GPRC_and_GPRC_NOR0:sub_pair0
10958 0, // GPRC_and_GPRC_NOR0:sub_pair1
10959 0, // GPRC_and_GPRC_NOR0:sub_un
10960 0, // GPRC_and_GPRC_NOR0:sub_vsx0
10961 0, // GPRC_and_GPRC_NOR0:sub_vsx1
10962 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi
10963 0, // GPRC_and_GPRC_NOR0:sub_wacc_lo
10964 0, // GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64
10965 0, // GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
10966 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64
10967 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
10968 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx0
10969 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1
10970 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
10971 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10972 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
10973 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
10974 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
10975 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
10976 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
10977 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
10978 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10979 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10980 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
10981 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
10982 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
10983 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
10984 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
10985 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
10986 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10987 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10988 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10989 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10990 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10991 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10992 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10993 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10994 0, // GPRC_and_GPRC_NOR0:sub_gp8_x1_then_sub_32
10995 },
10996 { // CRBITRC
10997 0, // CRBITRC:sub_32
10998 0, // CRBITRC:sub_32_hi_phony
10999 0, // CRBITRC:sub_64
11000 0, // CRBITRC:sub_64_hi_phony
11001 0, // CRBITRC:sub_dmr0
11002 0, // CRBITRC:sub_dmr1
11003 0, // CRBITRC:sub_dmrrow0
11004 0, // CRBITRC:sub_dmrrow1
11005 0, // CRBITRC:sub_dmrrowp0
11006 0, // CRBITRC:sub_dmrrowp1
11007 0, // CRBITRC:sub_eq
11008 0, // CRBITRC:sub_fp0
11009 0, // CRBITRC:sub_fp1
11010 0, // CRBITRC:sub_gp8_x0
11011 0, // CRBITRC:sub_gp8_x1
11012 0, // CRBITRC:sub_gt
11013 0, // CRBITRC:sub_lt
11014 0, // CRBITRC:sub_pair0
11015 0, // CRBITRC:sub_pair1
11016 0, // CRBITRC:sub_un
11017 0, // CRBITRC:sub_vsx0
11018 0, // CRBITRC:sub_vsx1
11019 0, // CRBITRC:sub_wacc_hi
11020 0, // CRBITRC:sub_wacc_lo
11021 0, // CRBITRC:sub_vsx1_then_sub_64
11022 0, // CRBITRC:sub_vsx1_then_sub_64_hi_phony
11023 0, // CRBITRC:sub_pair1_then_sub_64
11024 0, // CRBITRC:sub_pair1_then_sub_64_hi_phony
11025 0, // CRBITRC:sub_pair1_then_sub_vsx0
11026 0, // CRBITRC:sub_pair1_then_sub_vsx1
11027 0, // CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64
11028 0, // CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11029 0, // CRBITRC:sub_dmrrowp1_then_sub_dmrrow0
11030 0, // CRBITRC:sub_dmrrowp1_then_sub_dmrrow1
11031 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrow0
11032 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrow1
11033 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp0
11034 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1
11035 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11036 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11037 0, // CRBITRC:sub_dmr1_then_sub_dmrrow0
11038 0, // CRBITRC:sub_dmr1_then_sub_dmrrow1
11039 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp0
11040 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1
11041 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi
11042 0, // CRBITRC:sub_dmr1_then_sub_wacc_lo
11043 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11044 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11045 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11046 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11047 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11048 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11049 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11050 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11051 0, // CRBITRC:sub_gp8_x1_then_sub_32
11052 },
11053 { // F4RC
11054 0, // F4RC:sub_32
11055 0, // F4RC:sub_32_hi_phony
11056 0, // F4RC:sub_64
11057 0, // F4RC:sub_64_hi_phony
11058 0, // F4RC:sub_dmr0
11059 0, // F4RC:sub_dmr1
11060 0, // F4RC:sub_dmrrow0
11061 0, // F4RC:sub_dmrrow1
11062 0, // F4RC:sub_dmrrowp0
11063 0, // F4RC:sub_dmrrowp1
11064 0, // F4RC:sub_eq
11065 0, // F4RC:sub_fp0
11066 0, // F4RC:sub_fp1
11067 0, // F4RC:sub_gp8_x0
11068 0, // F4RC:sub_gp8_x1
11069 0, // F4RC:sub_gt
11070 0, // F4RC:sub_lt
11071 0, // F4RC:sub_pair0
11072 0, // F4RC:sub_pair1
11073 0, // F4RC:sub_un
11074 0, // F4RC:sub_vsx0
11075 0, // F4RC:sub_vsx1
11076 0, // F4RC:sub_wacc_hi
11077 0, // F4RC:sub_wacc_lo
11078 0, // F4RC:sub_vsx1_then_sub_64
11079 0, // F4RC:sub_vsx1_then_sub_64_hi_phony
11080 0, // F4RC:sub_pair1_then_sub_64
11081 0, // F4RC:sub_pair1_then_sub_64_hi_phony
11082 0, // F4RC:sub_pair1_then_sub_vsx0
11083 0, // F4RC:sub_pair1_then_sub_vsx1
11084 0, // F4RC:sub_pair1_then_sub_vsx1_then_sub_64
11085 0, // F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11086 0, // F4RC:sub_dmrrowp1_then_sub_dmrrow0
11087 0, // F4RC:sub_dmrrowp1_then_sub_dmrrow1
11088 0, // F4RC:sub_wacc_hi_then_sub_dmrrow0
11089 0, // F4RC:sub_wacc_hi_then_sub_dmrrow1
11090 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp0
11091 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1
11092 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11093 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11094 0, // F4RC:sub_dmr1_then_sub_dmrrow0
11095 0, // F4RC:sub_dmr1_then_sub_dmrrow1
11096 0, // F4RC:sub_dmr1_then_sub_dmrrowp0
11097 0, // F4RC:sub_dmr1_then_sub_dmrrowp1
11098 0, // F4RC:sub_dmr1_then_sub_wacc_hi
11099 0, // F4RC:sub_dmr1_then_sub_wacc_lo
11100 0, // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11101 0, // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11102 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11103 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11104 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11105 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11106 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11107 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11108 0, // F4RC:sub_gp8_x1_then_sub_32
11109 },
11110 { // GPRC32
11111 0, // GPRC32:sub_32
11112 0, // GPRC32:sub_32_hi_phony
11113 0, // GPRC32:sub_64
11114 0, // GPRC32:sub_64_hi_phony
11115 0, // GPRC32:sub_dmr0
11116 0, // GPRC32:sub_dmr1
11117 0, // GPRC32:sub_dmrrow0
11118 0, // GPRC32:sub_dmrrow1
11119 0, // GPRC32:sub_dmrrowp0
11120 0, // GPRC32:sub_dmrrowp1
11121 0, // GPRC32:sub_eq
11122 0, // GPRC32:sub_fp0
11123 0, // GPRC32:sub_fp1
11124 0, // GPRC32:sub_gp8_x0
11125 0, // GPRC32:sub_gp8_x1
11126 0, // GPRC32:sub_gt
11127 0, // GPRC32:sub_lt
11128 0, // GPRC32:sub_pair0
11129 0, // GPRC32:sub_pair1
11130 0, // GPRC32:sub_un
11131 0, // GPRC32:sub_vsx0
11132 0, // GPRC32:sub_vsx1
11133 0, // GPRC32:sub_wacc_hi
11134 0, // GPRC32:sub_wacc_lo
11135 0, // GPRC32:sub_vsx1_then_sub_64
11136 0, // GPRC32:sub_vsx1_then_sub_64_hi_phony
11137 0, // GPRC32:sub_pair1_then_sub_64
11138 0, // GPRC32:sub_pair1_then_sub_64_hi_phony
11139 0, // GPRC32:sub_pair1_then_sub_vsx0
11140 0, // GPRC32:sub_pair1_then_sub_vsx1
11141 0, // GPRC32:sub_pair1_then_sub_vsx1_then_sub_64
11142 0, // GPRC32:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11143 0, // GPRC32:sub_dmrrowp1_then_sub_dmrrow0
11144 0, // GPRC32:sub_dmrrowp1_then_sub_dmrrow1
11145 0, // GPRC32:sub_wacc_hi_then_sub_dmrrow0
11146 0, // GPRC32:sub_wacc_hi_then_sub_dmrrow1
11147 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp0
11148 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp1
11149 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11150 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11151 0, // GPRC32:sub_dmr1_then_sub_dmrrow0
11152 0, // GPRC32:sub_dmr1_then_sub_dmrrow1
11153 0, // GPRC32:sub_dmr1_then_sub_dmrrowp0
11154 0, // GPRC32:sub_dmr1_then_sub_dmrrowp1
11155 0, // GPRC32:sub_dmr1_then_sub_wacc_hi
11156 0, // GPRC32:sub_dmr1_then_sub_wacc_lo
11157 0, // GPRC32:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11158 0, // GPRC32:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11159 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11160 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11161 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11162 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11163 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11164 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11165 0, // GPRC32:sub_gp8_x1_then_sub_32
11166 },
11167 { // CRRC
11168 0, // CRRC:sub_32
11169 0, // CRRC:sub_32_hi_phony
11170 0, // CRRC:sub_64
11171 0, // CRRC:sub_64_hi_phony
11172 0, // CRRC:sub_dmr0
11173 0, // CRRC:sub_dmr1
11174 0, // CRRC:sub_dmrrow0
11175 0, // CRRC:sub_dmrrow1
11176 0, // CRRC:sub_dmrrowp0
11177 0, // CRRC:sub_dmrrowp1
11178 5, // CRRC:sub_eq -> CRBITRC
11179 0, // CRRC:sub_fp0
11180 0, // CRRC:sub_fp1
11181 0, // CRRC:sub_gp8_x0
11182 0, // CRRC:sub_gp8_x1
11183 5, // CRRC:sub_gt -> CRBITRC
11184 5, // CRRC:sub_lt -> CRBITRC
11185 0, // CRRC:sub_pair0
11186 0, // CRRC:sub_pair1
11187 5, // CRRC:sub_un -> CRBITRC
11188 0, // CRRC:sub_vsx0
11189 0, // CRRC:sub_vsx1
11190 0, // CRRC:sub_wacc_hi
11191 0, // CRRC:sub_wacc_lo
11192 0, // CRRC:sub_vsx1_then_sub_64
11193 0, // CRRC:sub_vsx1_then_sub_64_hi_phony
11194 0, // CRRC:sub_pair1_then_sub_64
11195 0, // CRRC:sub_pair1_then_sub_64_hi_phony
11196 0, // CRRC:sub_pair1_then_sub_vsx0
11197 0, // CRRC:sub_pair1_then_sub_vsx1
11198 0, // CRRC:sub_pair1_then_sub_vsx1_then_sub_64
11199 0, // CRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11200 0, // CRRC:sub_dmrrowp1_then_sub_dmrrow0
11201 0, // CRRC:sub_dmrrowp1_then_sub_dmrrow1
11202 0, // CRRC:sub_wacc_hi_then_sub_dmrrow0
11203 0, // CRRC:sub_wacc_hi_then_sub_dmrrow1
11204 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp0
11205 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1
11206 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11207 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11208 0, // CRRC:sub_dmr1_then_sub_dmrrow0
11209 0, // CRRC:sub_dmr1_then_sub_dmrrow1
11210 0, // CRRC:sub_dmr1_then_sub_dmrrowp0
11211 0, // CRRC:sub_dmr1_then_sub_dmrrowp1
11212 0, // CRRC:sub_dmr1_then_sub_wacc_hi
11213 0, // CRRC:sub_dmr1_then_sub_wacc_lo
11214 0, // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11215 0, // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11216 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11217 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11218 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11219 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11220 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11221 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11222 0, // CRRC:sub_gp8_x1_then_sub_32
11223 },
11224 { // CARRYRC
11225 0, // CARRYRC:sub_32
11226 0, // CARRYRC:sub_32_hi_phony
11227 0, // CARRYRC:sub_64
11228 0, // CARRYRC:sub_64_hi_phony
11229 0, // CARRYRC:sub_dmr0
11230 0, // CARRYRC:sub_dmr1
11231 0, // CARRYRC:sub_dmrrow0
11232 0, // CARRYRC:sub_dmrrow1
11233 0, // CARRYRC:sub_dmrrowp0
11234 0, // CARRYRC:sub_dmrrowp1
11235 0, // CARRYRC:sub_eq
11236 0, // CARRYRC:sub_fp0
11237 0, // CARRYRC:sub_fp1
11238 0, // CARRYRC:sub_gp8_x0
11239 0, // CARRYRC:sub_gp8_x1
11240 0, // CARRYRC:sub_gt
11241 0, // CARRYRC:sub_lt
11242 0, // CARRYRC:sub_pair0
11243 0, // CARRYRC:sub_pair1
11244 0, // CARRYRC:sub_un
11245 0, // CARRYRC:sub_vsx0
11246 0, // CARRYRC:sub_vsx1
11247 0, // CARRYRC:sub_wacc_hi
11248 0, // CARRYRC:sub_wacc_lo
11249 0, // CARRYRC:sub_vsx1_then_sub_64
11250 0, // CARRYRC:sub_vsx1_then_sub_64_hi_phony
11251 0, // CARRYRC:sub_pair1_then_sub_64
11252 0, // CARRYRC:sub_pair1_then_sub_64_hi_phony
11253 0, // CARRYRC:sub_pair1_then_sub_vsx0
11254 0, // CARRYRC:sub_pair1_then_sub_vsx1
11255 0, // CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64
11256 0, // CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11257 0, // CARRYRC:sub_dmrrowp1_then_sub_dmrrow0
11258 0, // CARRYRC:sub_dmrrowp1_then_sub_dmrrow1
11259 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrow0
11260 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrow1
11261 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp0
11262 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1
11263 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11264 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11265 0, // CARRYRC:sub_dmr1_then_sub_dmrrow0
11266 0, // CARRYRC:sub_dmr1_then_sub_dmrrow1
11267 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp0
11268 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1
11269 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi
11270 0, // CARRYRC:sub_dmr1_then_sub_wacc_lo
11271 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11272 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11273 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11274 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11275 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11276 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11277 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11278 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11279 0, // CARRYRC:sub_gp8_x1_then_sub_32
11280 },
11281 { // CTRRC
11282 0, // CTRRC:sub_32
11283 0, // CTRRC:sub_32_hi_phony
11284 0, // CTRRC:sub_64
11285 0, // CTRRC:sub_64_hi_phony
11286 0, // CTRRC:sub_dmr0
11287 0, // CTRRC:sub_dmr1
11288 0, // CTRRC:sub_dmrrow0
11289 0, // CTRRC:sub_dmrrow1
11290 0, // CTRRC:sub_dmrrowp0
11291 0, // CTRRC:sub_dmrrowp1
11292 0, // CTRRC:sub_eq
11293 0, // CTRRC:sub_fp0
11294 0, // CTRRC:sub_fp1
11295 0, // CTRRC:sub_gp8_x0
11296 0, // CTRRC:sub_gp8_x1
11297 0, // CTRRC:sub_gt
11298 0, // CTRRC:sub_lt
11299 0, // CTRRC:sub_pair0
11300 0, // CTRRC:sub_pair1
11301 0, // CTRRC:sub_un
11302 0, // CTRRC:sub_vsx0
11303 0, // CTRRC:sub_vsx1
11304 0, // CTRRC:sub_wacc_hi
11305 0, // CTRRC:sub_wacc_lo
11306 0, // CTRRC:sub_vsx1_then_sub_64
11307 0, // CTRRC:sub_vsx1_then_sub_64_hi_phony
11308 0, // CTRRC:sub_pair1_then_sub_64
11309 0, // CTRRC:sub_pair1_then_sub_64_hi_phony
11310 0, // CTRRC:sub_pair1_then_sub_vsx0
11311 0, // CTRRC:sub_pair1_then_sub_vsx1
11312 0, // CTRRC:sub_pair1_then_sub_vsx1_then_sub_64
11313 0, // CTRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11314 0, // CTRRC:sub_dmrrowp1_then_sub_dmrrow0
11315 0, // CTRRC:sub_dmrrowp1_then_sub_dmrrow1
11316 0, // CTRRC:sub_wacc_hi_then_sub_dmrrow0
11317 0, // CTRRC:sub_wacc_hi_then_sub_dmrrow1
11318 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp0
11319 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1
11320 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11321 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11322 0, // CTRRC:sub_dmr1_then_sub_dmrrow0
11323 0, // CTRRC:sub_dmr1_then_sub_dmrrow1
11324 0, // CTRRC:sub_dmr1_then_sub_dmrrowp0
11325 0, // CTRRC:sub_dmr1_then_sub_dmrrowp1
11326 0, // CTRRC:sub_dmr1_then_sub_wacc_hi
11327 0, // CTRRC:sub_dmr1_then_sub_wacc_lo
11328 0, // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11329 0, // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11330 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11331 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11332 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11333 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11334 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11335 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11336 0, // CTRRC:sub_gp8_x1_then_sub_32
11337 },
11338 { // LRRC
11339 0, // LRRC:sub_32
11340 0, // LRRC:sub_32_hi_phony
11341 0, // LRRC:sub_64
11342 0, // LRRC:sub_64_hi_phony
11343 0, // LRRC:sub_dmr0
11344 0, // LRRC:sub_dmr1
11345 0, // LRRC:sub_dmrrow0
11346 0, // LRRC:sub_dmrrow1
11347 0, // LRRC:sub_dmrrowp0
11348 0, // LRRC:sub_dmrrowp1
11349 0, // LRRC:sub_eq
11350 0, // LRRC:sub_fp0
11351 0, // LRRC:sub_fp1
11352 0, // LRRC:sub_gp8_x0
11353 0, // LRRC:sub_gp8_x1
11354 0, // LRRC:sub_gt
11355 0, // LRRC:sub_lt
11356 0, // LRRC:sub_pair0
11357 0, // LRRC:sub_pair1
11358 0, // LRRC:sub_un
11359 0, // LRRC:sub_vsx0
11360 0, // LRRC:sub_vsx1
11361 0, // LRRC:sub_wacc_hi
11362 0, // LRRC:sub_wacc_lo
11363 0, // LRRC:sub_vsx1_then_sub_64
11364 0, // LRRC:sub_vsx1_then_sub_64_hi_phony
11365 0, // LRRC:sub_pair1_then_sub_64
11366 0, // LRRC:sub_pair1_then_sub_64_hi_phony
11367 0, // LRRC:sub_pair1_then_sub_vsx0
11368 0, // LRRC:sub_pair1_then_sub_vsx1
11369 0, // LRRC:sub_pair1_then_sub_vsx1_then_sub_64
11370 0, // LRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11371 0, // LRRC:sub_dmrrowp1_then_sub_dmrrow0
11372 0, // LRRC:sub_dmrrowp1_then_sub_dmrrow1
11373 0, // LRRC:sub_wacc_hi_then_sub_dmrrow0
11374 0, // LRRC:sub_wacc_hi_then_sub_dmrrow1
11375 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp0
11376 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1
11377 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11378 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11379 0, // LRRC:sub_dmr1_then_sub_dmrrow0
11380 0, // LRRC:sub_dmr1_then_sub_dmrrow1
11381 0, // LRRC:sub_dmr1_then_sub_dmrrowp0
11382 0, // LRRC:sub_dmr1_then_sub_dmrrowp1
11383 0, // LRRC:sub_dmr1_then_sub_wacc_hi
11384 0, // LRRC:sub_dmr1_then_sub_wacc_lo
11385 0, // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11386 0, // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11387 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11388 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11389 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11390 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11391 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11392 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11393 0, // LRRC:sub_gp8_x1_then_sub_32
11394 },
11395 { // VRSAVERC
11396 0, // VRSAVERC:sub_32
11397 0, // VRSAVERC:sub_32_hi_phony
11398 0, // VRSAVERC:sub_64
11399 0, // VRSAVERC:sub_64_hi_phony
11400 0, // VRSAVERC:sub_dmr0
11401 0, // VRSAVERC:sub_dmr1
11402 0, // VRSAVERC:sub_dmrrow0
11403 0, // VRSAVERC:sub_dmrrow1
11404 0, // VRSAVERC:sub_dmrrowp0
11405 0, // VRSAVERC:sub_dmrrowp1
11406 0, // VRSAVERC:sub_eq
11407 0, // VRSAVERC:sub_fp0
11408 0, // VRSAVERC:sub_fp1
11409 0, // VRSAVERC:sub_gp8_x0
11410 0, // VRSAVERC:sub_gp8_x1
11411 0, // VRSAVERC:sub_gt
11412 0, // VRSAVERC:sub_lt
11413 0, // VRSAVERC:sub_pair0
11414 0, // VRSAVERC:sub_pair1
11415 0, // VRSAVERC:sub_un
11416 0, // VRSAVERC:sub_vsx0
11417 0, // VRSAVERC:sub_vsx1
11418 0, // VRSAVERC:sub_wacc_hi
11419 0, // VRSAVERC:sub_wacc_lo
11420 0, // VRSAVERC:sub_vsx1_then_sub_64
11421 0, // VRSAVERC:sub_vsx1_then_sub_64_hi_phony
11422 0, // VRSAVERC:sub_pair1_then_sub_64
11423 0, // VRSAVERC:sub_pair1_then_sub_64_hi_phony
11424 0, // VRSAVERC:sub_pair1_then_sub_vsx0
11425 0, // VRSAVERC:sub_pair1_then_sub_vsx1
11426 0, // VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64
11427 0, // VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11428 0, // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow0
11429 0, // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow1
11430 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrow0
11431 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrow1
11432 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp0
11433 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1
11434 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11435 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11436 0, // VRSAVERC:sub_dmr1_then_sub_dmrrow0
11437 0, // VRSAVERC:sub_dmr1_then_sub_dmrrow1
11438 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp0
11439 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1
11440 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi
11441 0, // VRSAVERC:sub_dmr1_then_sub_wacc_lo
11442 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11443 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11444 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11445 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11446 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11447 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11448 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11449 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11450 0, // VRSAVERC:sub_gp8_x1_then_sub_32
11451 },
11452 { // SPILLTOVSRRC
11453 2, // SPILLTOVSRRC:sub_32 -> GPRC
11454 0, // SPILLTOVSRRC:sub_32_hi_phony
11455 0, // SPILLTOVSRRC:sub_64
11456 0, // SPILLTOVSRRC:sub_64_hi_phony
11457 0, // SPILLTOVSRRC:sub_dmr0
11458 0, // SPILLTOVSRRC:sub_dmr1
11459 0, // SPILLTOVSRRC:sub_dmrrow0
11460 0, // SPILLTOVSRRC:sub_dmrrow1
11461 0, // SPILLTOVSRRC:sub_dmrrowp0
11462 0, // SPILLTOVSRRC:sub_dmrrowp1
11463 0, // SPILLTOVSRRC:sub_eq
11464 0, // SPILLTOVSRRC:sub_fp0
11465 0, // SPILLTOVSRRC:sub_fp1
11466 0, // SPILLTOVSRRC:sub_gp8_x0
11467 0, // SPILLTOVSRRC:sub_gp8_x1
11468 0, // SPILLTOVSRRC:sub_gt
11469 0, // SPILLTOVSRRC:sub_lt
11470 0, // SPILLTOVSRRC:sub_pair0
11471 0, // SPILLTOVSRRC:sub_pair1
11472 0, // SPILLTOVSRRC:sub_un
11473 0, // SPILLTOVSRRC:sub_vsx0
11474 0, // SPILLTOVSRRC:sub_vsx1
11475 0, // SPILLTOVSRRC:sub_wacc_hi
11476 0, // SPILLTOVSRRC:sub_wacc_lo
11477 0, // SPILLTOVSRRC:sub_vsx1_then_sub_64
11478 0, // SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
11479 0, // SPILLTOVSRRC:sub_pair1_then_sub_64
11480 0, // SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
11481 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx0
11482 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1
11483 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
11484 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11485 0, // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11486 0, // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11487 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11488 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11489 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11490 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11491 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11492 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11493 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11494 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11495 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11496 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11497 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11498 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11499 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11500 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11501 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11502 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11503 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11504 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11505 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11506 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11507 0, // SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11508 },
11509 { // VSFRC
11510 0, // VSFRC:sub_32
11511 0, // VSFRC:sub_32_hi_phony
11512 0, // VSFRC:sub_64
11513 0, // VSFRC:sub_64_hi_phony
11514 0, // VSFRC:sub_dmr0
11515 0, // VSFRC:sub_dmr1
11516 0, // VSFRC:sub_dmrrow0
11517 0, // VSFRC:sub_dmrrow1
11518 0, // VSFRC:sub_dmrrowp0
11519 0, // VSFRC:sub_dmrrowp1
11520 0, // VSFRC:sub_eq
11521 0, // VSFRC:sub_fp0
11522 0, // VSFRC:sub_fp1
11523 0, // VSFRC:sub_gp8_x0
11524 0, // VSFRC:sub_gp8_x1
11525 0, // VSFRC:sub_gt
11526 0, // VSFRC:sub_lt
11527 0, // VSFRC:sub_pair0
11528 0, // VSFRC:sub_pair1
11529 0, // VSFRC:sub_un
11530 0, // VSFRC:sub_vsx0
11531 0, // VSFRC:sub_vsx1
11532 0, // VSFRC:sub_wacc_hi
11533 0, // VSFRC:sub_wacc_lo
11534 0, // VSFRC:sub_vsx1_then_sub_64
11535 0, // VSFRC:sub_vsx1_then_sub_64_hi_phony
11536 0, // VSFRC:sub_pair1_then_sub_64
11537 0, // VSFRC:sub_pair1_then_sub_64_hi_phony
11538 0, // VSFRC:sub_pair1_then_sub_vsx0
11539 0, // VSFRC:sub_pair1_then_sub_vsx1
11540 0, // VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
11541 0, // VSFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11542 0, // VSFRC:sub_dmrrowp1_then_sub_dmrrow0
11543 0, // VSFRC:sub_dmrrowp1_then_sub_dmrrow1
11544 0, // VSFRC:sub_wacc_hi_then_sub_dmrrow0
11545 0, // VSFRC:sub_wacc_hi_then_sub_dmrrow1
11546 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp0
11547 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1
11548 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11549 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11550 0, // VSFRC:sub_dmr1_then_sub_dmrrow0
11551 0, // VSFRC:sub_dmr1_then_sub_dmrrow1
11552 0, // VSFRC:sub_dmr1_then_sub_dmrrowp0
11553 0, // VSFRC:sub_dmr1_then_sub_dmrrowp1
11554 0, // VSFRC:sub_dmr1_then_sub_wacc_hi
11555 0, // VSFRC:sub_dmr1_then_sub_wacc_lo
11556 0, // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11557 0, // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11558 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11559 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11560 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11561 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11562 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11563 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11564 0, // VSFRC:sub_gp8_x1_then_sub_32
11565 },
11566 { // G8RC
11567 2, // G8RC:sub_32 -> GPRC
11568 0, // G8RC:sub_32_hi_phony
11569 0, // G8RC:sub_64
11570 0, // G8RC:sub_64_hi_phony
11571 0, // G8RC:sub_dmr0
11572 0, // G8RC:sub_dmr1
11573 0, // G8RC:sub_dmrrow0
11574 0, // G8RC:sub_dmrrow1
11575 0, // G8RC:sub_dmrrowp0
11576 0, // G8RC:sub_dmrrowp1
11577 0, // G8RC:sub_eq
11578 0, // G8RC:sub_fp0
11579 0, // G8RC:sub_fp1
11580 0, // G8RC:sub_gp8_x0
11581 0, // G8RC:sub_gp8_x1
11582 0, // G8RC:sub_gt
11583 0, // G8RC:sub_lt
11584 0, // G8RC:sub_pair0
11585 0, // G8RC:sub_pair1
11586 0, // G8RC:sub_un
11587 0, // G8RC:sub_vsx0
11588 0, // G8RC:sub_vsx1
11589 0, // G8RC:sub_wacc_hi
11590 0, // G8RC:sub_wacc_lo
11591 0, // G8RC:sub_vsx1_then_sub_64
11592 0, // G8RC:sub_vsx1_then_sub_64_hi_phony
11593 0, // G8RC:sub_pair1_then_sub_64
11594 0, // G8RC:sub_pair1_then_sub_64_hi_phony
11595 0, // G8RC:sub_pair1_then_sub_vsx0
11596 0, // G8RC:sub_pair1_then_sub_vsx1
11597 0, // G8RC:sub_pair1_then_sub_vsx1_then_sub_64
11598 0, // G8RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11599 0, // G8RC:sub_dmrrowp1_then_sub_dmrrow0
11600 0, // G8RC:sub_dmrrowp1_then_sub_dmrrow1
11601 0, // G8RC:sub_wacc_hi_then_sub_dmrrow0
11602 0, // G8RC:sub_wacc_hi_then_sub_dmrrow1
11603 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp0
11604 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1
11605 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11606 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11607 0, // G8RC:sub_dmr1_then_sub_dmrrow0
11608 0, // G8RC:sub_dmr1_then_sub_dmrrow1
11609 0, // G8RC:sub_dmr1_then_sub_dmrrowp0
11610 0, // G8RC:sub_dmr1_then_sub_dmrrowp1
11611 0, // G8RC:sub_dmr1_then_sub_wacc_hi
11612 0, // G8RC:sub_dmr1_then_sub_wacc_lo
11613 0, // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11614 0, // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11615 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11616 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11617 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11618 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11619 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11620 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11621 0, // G8RC:sub_gp8_x1_then_sub_32
11622 },
11623 { // G8RC_NOX0
11624 3, // G8RC_NOX0:sub_32 -> GPRC_NOR0
11625 0, // G8RC_NOX0:sub_32_hi_phony
11626 0, // G8RC_NOX0:sub_64
11627 0, // G8RC_NOX0:sub_64_hi_phony
11628 0, // G8RC_NOX0:sub_dmr0
11629 0, // G8RC_NOX0:sub_dmr1
11630 0, // G8RC_NOX0:sub_dmrrow0
11631 0, // G8RC_NOX0:sub_dmrrow1
11632 0, // G8RC_NOX0:sub_dmrrowp0
11633 0, // G8RC_NOX0:sub_dmrrowp1
11634 0, // G8RC_NOX0:sub_eq
11635 0, // G8RC_NOX0:sub_fp0
11636 0, // G8RC_NOX0:sub_fp1
11637 0, // G8RC_NOX0:sub_gp8_x0
11638 0, // G8RC_NOX0:sub_gp8_x1
11639 0, // G8RC_NOX0:sub_gt
11640 0, // G8RC_NOX0:sub_lt
11641 0, // G8RC_NOX0:sub_pair0
11642 0, // G8RC_NOX0:sub_pair1
11643 0, // G8RC_NOX0:sub_un
11644 0, // G8RC_NOX0:sub_vsx0
11645 0, // G8RC_NOX0:sub_vsx1
11646 0, // G8RC_NOX0:sub_wacc_hi
11647 0, // G8RC_NOX0:sub_wacc_lo
11648 0, // G8RC_NOX0:sub_vsx1_then_sub_64
11649 0, // G8RC_NOX0:sub_vsx1_then_sub_64_hi_phony
11650 0, // G8RC_NOX0:sub_pair1_then_sub_64
11651 0, // G8RC_NOX0:sub_pair1_then_sub_64_hi_phony
11652 0, // G8RC_NOX0:sub_pair1_then_sub_vsx0
11653 0, // G8RC_NOX0:sub_pair1_then_sub_vsx1
11654 0, // G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
11655 0, // G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11656 0, // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
11657 0, // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
11658 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
11659 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
11660 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
11661 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
11662 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11663 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11664 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
11665 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
11666 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
11667 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
11668 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
11669 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
11670 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11671 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11672 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11673 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11674 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11675 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11676 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11677 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11678 0, // G8RC_NOX0:sub_gp8_x1_then_sub_32
11679 },
11680 { // SPILLTOVSRRC_and_VSFRC
11681 0, // SPILLTOVSRRC_and_VSFRC:sub_32
11682 0, // SPILLTOVSRRC_and_VSFRC:sub_32_hi_phony
11683 0, // SPILLTOVSRRC_and_VSFRC:sub_64
11684 0, // SPILLTOVSRRC_and_VSFRC:sub_64_hi_phony
11685 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr0
11686 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1
11687 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrow0
11688 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrow1
11689 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp0
11690 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1
11691 0, // SPILLTOVSRRC_and_VSFRC:sub_eq
11692 0, // SPILLTOVSRRC_and_VSFRC:sub_fp0
11693 0, // SPILLTOVSRRC_and_VSFRC:sub_fp1
11694 0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x0
11695 0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1
11696 0, // SPILLTOVSRRC_and_VSFRC:sub_gt
11697 0, // SPILLTOVSRRC_and_VSFRC:sub_lt
11698 0, // SPILLTOVSRRC_and_VSFRC:sub_pair0
11699 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1
11700 0, // SPILLTOVSRRC_and_VSFRC:sub_un
11701 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx0
11702 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1
11703 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi
11704 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_lo
11705 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64
11706 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64_hi_phony
11707 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64
11708 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64_hi_phony
11709 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx0
11710 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1
11711 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
11712 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11713 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow0
11714 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow1
11715 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow0
11716 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow1
11717 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp0
11718 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1
11719 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11720 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11721 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow0
11722 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow1
11723 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp0
11724 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1
11725 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi
11726 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_lo
11727 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11728 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11729 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11730 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11731 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11732 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11733 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11734 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11735 0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1_then_sub_32
11736 },
11737 { // G8RC_and_G8RC_NOX0
11738 4, // G8RC_and_G8RC_NOX0:sub_32 -> GPRC_and_GPRC_NOR0
11739 0, // G8RC_and_G8RC_NOX0:sub_32_hi_phony
11740 0, // G8RC_and_G8RC_NOX0:sub_64
11741 0, // G8RC_and_G8RC_NOX0:sub_64_hi_phony
11742 0, // G8RC_and_G8RC_NOX0:sub_dmr0
11743 0, // G8RC_and_G8RC_NOX0:sub_dmr1
11744 0, // G8RC_and_G8RC_NOX0:sub_dmrrow0
11745 0, // G8RC_and_G8RC_NOX0:sub_dmrrow1
11746 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp0
11747 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1
11748 0, // G8RC_and_G8RC_NOX0:sub_eq
11749 0, // G8RC_and_G8RC_NOX0:sub_fp0
11750 0, // G8RC_and_G8RC_NOX0:sub_fp1
11751 0, // G8RC_and_G8RC_NOX0:sub_gp8_x0
11752 0, // G8RC_and_G8RC_NOX0:sub_gp8_x1
11753 0, // G8RC_and_G8RC_NOX0:sub_gt
11754 0, // G8RC_and_G8RC_NOX0:sub_lt
11755 0, // G8RC_and_G8RC_NOX0:sub_pair0
11756 0, // G8RC_and_G8RC_NOX0:sub_pair1
11757 0, // G8RC_and_G8RC_NOX0:sub_un
11758 0, // G8RC_and_G8RC_NOX0:sub_vsx0
11759 0, // G8RC_and_G8RC_NOX0:sub_vsx1
11760 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi
11761 0, // G8RC_and_G8RC_NOX0:sub_wacc_lo
11762 0, // G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64
11763 0, // G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64_hi_phony
11764 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64
11765 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64_hi_phony
11766 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx0
11767 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1
11768 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
11769 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11770 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
11771 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
11772 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
11773 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
11774 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
11775 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
11776 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11777 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11778 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
11779 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
11780 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
11781 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
11782 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
11783 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
11784 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11785 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11786 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11787 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11788 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11789 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11790 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11791 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11792 0, // G8RC_and_G8RC_NOX0:sub_gp8_x1_then_sub_32
11793 },
11794 { // F8RC
11795 0, // F8RC:sub_32
11796 0, // F8RC:sub_32_hi_phony
11797 0, // F8RC:sub_64
11798 0, // F8RC:sub_64_hi_phony
11799 0, // F8RC:sub_dmr0
11800 0, // F8RC:sub_dmr1
11801 0, // F8RC:sub_dmrrow0
11802 0, // F8RC:sub_dmrrow1
11803 0, // F8RC:sub_dmrrowp0
11804 0, // F8RC:sub_dmrrowp1
11805 0, // F8RC:sub_eq
11806 0, // F8RC:sub_fp0
11807 0, // F8RC:sub_fp1
11808 0, // F8RC:sub_gp8_x0
11809 0, // F8RC:sub_gp8_x1
11810 0, // F8RC:sub_gt
11811 0, // F8RC:sub_lt
11812 0, // F8RC:sub_pair0
11813 0, // F8RC:sub_pair1
11814 0, // F8RC:sub_un
11815 0, // F8RC:sub_vsx0
11816 0, // F8RC:sub_vsx1
11817 0, // F8RC:sub_wacc_hi
11818 0, // F8RC:sub_wacc_lo
11819 0, // F8RC:sub_vsx1_then_sub_64
11820 0, // F8RC:sub_vsx1_then_sub_64_hi_phony
11821 0, // F8RC:sub_pair1_then_sub_64
11822 0, // F8RC:sub_pair1_then_sub_64_hi_phony
11823 0, // F8RC:sub_pair1_then_sub_vsx0
11824 0, // F8RC:sub_pair1_then_sub_vsx1
11825 0, // F8RC:sub_pair1_then_sub_vsx1_then_sub_64
11826 0, // F8RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11827 0, // F8RC:sub_dmrrowp1_then_sub_dmrrow0
11828 0, // F8RC:sub_dmrrowp1_then_sub_dmrrow1
11829 0, // F8RC:sub_wacc_hi_then_sub_dmrrow0
11830 0, // F8RC:sub_wacc_hi_then_sub_dmrrow1
11831 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp0
11832 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1
11833 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11834 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11835 0, // F8RC:sub_dmr1_then_sub_dmrrow0
11836 0, // F8RC:sub_dmr1_then_sub_dmrrow1
11837 0, // F8RC:sub_dmr1_then_sub_dmrrowp0
11838 0, // F8RC:sub_dmr1_then_sub_dmrrowp1
11839 0, // F8RC:sub_dmr1_then_sub_wacc_hi
11840 0, // F8RC:sub_dmr1_then_sub_wacc_lo
11841 0, // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11842 0, // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11843 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11844 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11845 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11846 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11847 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11848 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11849 0, // F8RC:sub_gp8_x1_then_sub_32
11850 },
11851 { // FHRC
11852 0, // FHRC:sub_32
11853 0, // FHRC:sub_32_hi_phony
11854 0, // FHRC:sub_64
11855 0, // FHRC:sub_64_hi_phony
11856 0, // FHRC:sub_dmr0
11857 0, // FHRC:sub_dmr1
11858 0, // FHRC:sub_dmrrow0
11859 0, // FHRC:sub_dmrrow1
11860 0, // FHRC:sub_dmrrowp0
11861 0, // FHRC:sub_dmrrowp1
11862 0, // FHRC:sub_eq
11863 0, // FHRC:sub_fp0
11864 0, // FHRC:sub_fp1
11865 0, // FHRC:sub_gp8_x0
11866 0, // FHRC:sub_gp8_x1
11867 0, // FHRC:sub_gt
11868 0, // FHRC:sub_lt
11869 0, // FHRC:sub_pair0
11870 0, // FHRC:sub_pair1
11871 0, // FHRC:sub_un
11872 0, // FHRC:sub_vsx0
11873 0, // FHRC:sub_vsx1
11874 0, // FHRC:sub_wacc_hi
11875 0, // FHRC:sub_wacc_lo
11876 0, // FHRC:sub_vsx1_then_sub_64
11877 0, // FHRC:sub_vsx1_then_sub_64_hi_phony
11878 0, // FHRC:sub_pair1_then_sub_64
11879 0, // FHRC:sub_pair1_then_sub_64_hi_phony
11880 0, // FHRC:sub_pair1_then_sub_vsx0
11881 0, // FHRC:sub_pair1_then_sub_vsx1
11882 0, // FHRC:sub_pair1_then_sub_vsx1_then_sub_64
11883 0, // FHRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11884 0, // FHRC:sub_dmrrowp1_then_sub_dmrrow0
11885 0, // FHRC:sub_dmrrowp1_then_sub_dmrrow1
11886 0, // FHRC:sub_wacc_hi_then_sub_dmrrow0
11887 0, // FHRC:sub_wacc_hi_then_sub_dmrrow1
11888 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp0
11889 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp1
11890 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11891 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11892 0, // FHRC:sub_dmr1_then_sub_dmrrow0
11893 0, // FHRC:sub_dmr1_then_sub_dmrrow1
11894 0, // FHRC:sub_dmr1_then_sub_dmrrowp0
11895 0, // FHRC:sub_dmr1_then_sub_dmrrowp1
11896 0, // FHRC:sub_dmr1_then_sub_wacc_hi
11897 0, // FHRC:sub_dmr1_then_sub_wacc_lo
11898 0, // FHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11899 0, // FHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11900 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11901 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11902 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11903 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11904 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11905 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11906 0, // FHRC:sub_gp8_x1_then_sub_32
11907 },
11908 { // SPERC
11909 2, // SPERC:sub_32 -> GPRC
11910 0, // SPERC:sub_32_hi_phony
11911 0, // SPERC:sub_64
11912 0, // SPERC:sub_64_hi_phony
11913 0, // SPERC:sub_dmr0
11914 0, // SPERC:sub_dmr1
11915 0, // SPERC:sub_dmrrow0
11916 0, // SPERC:sub_dmrrow1
11917 0, // SPERC:sub_dmrrowp0
11918 0, // SPERC:sub_dmrrowp1
11919 0, // SPERC:sub_eq
11920 0, // SPERC:sub_fp0
11921 0, // SPERC:sub_fp1
11922 0, // SPERC:sub_gp8_x0
11923 0, // SPERC:sub_gp8_x1
11924 0, // SPERC:sub_gt
11925 0, // SPERC:sub_lt
11926 0, // SPERC:sub_pair0
11927 0, // SPERC:sub_pair1
11928 0, // SPERC:sub_un
11929 0, // SPERC:sub_vsx0
11930 0, // SPERC:sub_vsx1
11931 0, // SPERC:sub_wacc_hi
11932 0, // SPERC:sub_wacc_lo
11933 0, // SPERC:sub_vsx1_then_sub_64
11934 0, // SPERC:sub_vsx1_then_sub_64_hi_phony
11935 0, // SPERC:sub_pair1_then_sub_64
11936 0, // SPERC:sub_pair1_then_sub_64_hi_phony
11937 0, // SPERC:sub_pair1_then_sub_vsx0
11938 0, // SPERC:sub_pair1_then_sub_vsx1
11939 0, // SPERC:sub_pair1_then_sub_vsx1_then_sub_64
11940 0, // SPERC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11941 0, // SPERC:sub_dmrrowp1_then_sub_dmrrow0
11942 0, // SPERC:sub_dmrrowp1_then_sub_dmrrow1
11943 0, // SPERC:sub_wacc_hi_then_sub_dmrrow0
11944 0, // SPERC:sub_wacc_hi_then_sub_dmrrow1
11945 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp0
11946 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1
11947 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11948 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11949 0, // SPERC:sub_dmr1_then_sub_dmrrow0
11950 0, // SPERC:sub_dmr1_then_sub_dmrrow1
11951 0, // SPERC:sub_dmr1_then_sub_dmrrowp0
11952 0, // SPERC:sub_dmr1_then_sub_dmrrowp1
11953 0, // SPERC:sub_dmr1_then_sub_wacc_hi
11954 0, // SPERC:sub_dmr1_then_sub_wacc_lo
11955 0, // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11956 0, // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11957 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11958 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11959 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11960 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11961 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11962 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11963 0, // SPERC:sub_gp8_x1_then_sub_32
11964 },
11965 { // VFHRC
11966 0, // VFHRC:sub_32
11967 0, // VFHRC:sub_32_hi_phony
11968 0, // VFHRC:sub_64
11969 0, // VFHRC:sub_64_hi_phony
11970 0, // VFHRC:sub_dmr0
11971 0, // VFHRC:sub_dmr1
11972 0, // VFHRC:sub_dmrrow0
11973 0, // VFHRC:sub_dmrrow1
11974 0, // VFHRC:sub_dmrrowp0
11975 0, // VFHRC:sub_dmrrowp1
11976 0, // VFHRC:sub_eq
11977 0, // VFHRC:sub_fp0
11978 0, // VFHRC:sub_fp1
11979 0, // VFHRC:sub_gp8_x0
11980 0, // VFHRC:sub_gp8_x1
11981 0, // VFHRC:sub_gt
11982 0, // VFHRC:sub_lt
11983 0, // VFHRC:sub_pair0
11984 0, // VFHRC:sub_pair1
11985 0, // VFHRC:sub_un
11986 0, // VFHRC:sub_vsx0
11987 0, // VFHRC:sub_vsx1
11988 0, // VFHRC:sub_wacc_hi
11989 0, // VFHRC:sub_wacc_lo
11990 0, // VFHRC:sub_vsx1_then_sub_64
11991 0, // VFHRC:sub_vsx1_then_sub_64_hi_phony
11992 0, // VFHRC:sub_pair1_then_sub_64
11993 0, // VFHRC:sub_pair1_then_sub_64_hi_phony
11994 0, // VFHRC:sub_pair1_then_sub_vsx0
11995 0, // VFHRC:sub_pair1_then_sub_vsx1
11996 0, // VFHRC:sub_pair1_then_sub_vsx1_then_sub_64
11997 0, // VFHRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11998 0, // VFHRC:sub_dmrrowp1_then_sub_dmrrow0
11999 0, // VFHRC:sub_dmrrowp1_then_sub_dmrrow1
12000 0, // VFHRC:sub_wacc_hi_then_sub_dmrrow0
12001 0, // VFHRC:sub_wacc_hi_then_sub_dmrrow1
12002 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp0
12003 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp1
12004 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12005 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12006 0, // VFHRC:sub_dmr1_then_sub_dmrrow0
12007 0, // VFHRC:sub_dmr1_then_sub_dmrrow1
12008 0, // VFHRC:sub_dmr1_then_sub_dmrrowp0
12009 0, // VFHRC:sub_dmr1_then_sub_dmrrowp1
12010 0, // VFHRC:sub_dmr1_then_sub_wacc_hi
12011 0, // VFHRC:sub_dmr1_then_sub_wacc_lo
12012 0, // VFHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12013 0, // VFHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12014 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12015 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12016 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12017 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12018 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12019 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12020 0, // VFHRC:sub_gp8_x1_then_sub_32
12021 },
12022 { // VFRC
12023 0, // VFRC:sub_32
12024 0, // VFRC:sub_32_hi_phony
12025 0, // VFRC:sub_64
12026 0, // VFRC:sub_64_hi_phony
12027 0, // VFRC:sub_dmr0
12028 0, // VFRC:sub_dmr1
12029 0, // VFRC:sub_dmrrow0
12030 0, // VFRC:sub_dmrrow1
12031 0, // VFRC:sub_dmrrowp0
12032 0, // VFRC:sub_dmrrowp1
12033 0, // VFRC:sub_eq
12034 0, // VFRC:sub_fp0
12035 0, // VFRC:sub_fp1
12036 0, // VFRC:sub_gp8_x0
12037 0, // VFRC:sub_gp8_x1
12038 0, // VFRC:sub_gt
12039 0, // VFRC:sub_lt
12040 0, // VFRC:sub_pair0
12041 0, // VFRC:sub_pair1
12042 0, // VFRC:sub_un
12043 0, // VFRC:sub_vsx0
12044 0, // VFRC:sub_vsx1
12045 0, // VFRC:sub_wacc_hi
12046 0, // VFRC:sub_wacc_lo
12047 0, // VFRC:sub_vsx1_then_sub_64
12048 0, // VFRC:sub_vsx1_then_sub_64_hi_phony
12049 0, // VFRC:sub_pair1_then_sub_64
12050 0, // VFRC:sub_pair1_then_sub_64_hi_phony
12051 0, // VFRC:sub_pair1_then_sub_vsx0
12052 0, // VFRC:sub_pair1_then_sub_vsx1
12053 0, // VFRC:sub_pair1_then_sub_vsx1_then_sub_64
12054 0, // VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12055 0, // VFRC:sub_dmrrowp1_then_sub_dmrrow0
12056 0, // VFRC:sub_dmrrowp1_then_sub_dmrrow1
12057 0, // VFRC:sub_wacc_hi_then_sub_dmrrow0
12058 0, // VFRC:sub_wacc_hi_then_sub_dmrrow1
12059 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp0
12060 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1
12061 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12062 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12063 0, // VFRC:sub_dmr1_then_sub_dmrrow0
12064 0, // VFRC:sub_dmr1_then_sub_dmrrow1
12065 0, // VFRC:sub_dmr1_then_sub_dmrrowp0
12066 0, // VFRC:sub_dmr1_then_sub_dmrrowp1
12067 0, // VFRC:sub_dmr1_then_sub_wacc_hi
12068 0, // VFRC:sub_dmr1_then_sub_wacc_lo
12069 0, // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12070 0, // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12071 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12072 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12073 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12074 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12075 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12076 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12077 0, // VFRC:sub_gp8_x1_then_sub_32
12078 },
12079 { // SPERC_with_sub_32_in_GPRC_NOR0
12080 4, // SPERC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
12081 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_32_hi_phony
12082 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_64
12083 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_64_hi_phony
12084 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr0
12085 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1
12086 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
12087 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
12088 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
12089 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
12090 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_eq
12091 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_fp0
12092 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_fp1
12093 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0
12094 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1
12095 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gt
12096 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_lt
12097 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair0
12098 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1
12099 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_un
12100 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx0
12101 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1
12102 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
12103 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
12104 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
12105 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
12106 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
12107 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
12108 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
12109 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
12110 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
12111 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12112 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
12113 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
12114 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
12115 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
12116 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
12117 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
12118 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12119 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12120 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
12121 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
12122 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
12123 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
12124 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
12125 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
12126 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12127 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12128 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12129 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12130 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12131 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12132 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12133 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12134 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32
12135 },
12136 { // SPILLTOVSRRC_and_VFRC
12137 0, // SPILLTOVSRRC_and_VFRC:sub_32
12138 0, // SPILLTOVSRRC_and_VFRC:sub_32_hi_phony
12139 0, // SPILLTOVSRRC_and_VFRC:sub_64
12140 0, // SPILLTOVSRRC_and_VFRC:sub_64_hi_phony
12141 0, // SPILLTOVSRRC_and_VFRC:sub_dmr0
12142 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1
12143 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrow0
12144 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrow1
12145 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
12146 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
12147 0, // SPILLTOVSRRC_and_VFRC:sub_eq
12148 0, // SPILLTOVSRRC_and_VFRC:sub_fp0
12149 0, // SPILLTOVSRRC_and_VFRC:sub_fp1
12150 0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x0
12151 0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x1
12152 0, // SPILLTOVSRRC_and_VFRC:sub_gt
12153 0, // SPILLTOVSRRC_and_VFRC:sub_lt
12154 0, // SPILLTOVSRRC_and_VFRC:sub_pair0
12155 0, // SPILLTOVSRRC_and_VFRC:sub_pair1
12156 0, // SPILLTOVSRRC_and_VFRC:sub_un
12157 0, // SPILLTOVSRRC_and_VFRC:sub_vsx0
12158 0, // SPILLTOVSRRC_and_VFRC:sub_vsx1
12159 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi
12160 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_lo
12161 0, // SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64
12162 0, // SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64_hi_phony
12163 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
12164 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64_hi_phony
12165 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
12166 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
12167 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
12168 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12169 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
12170 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
12171 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
12172 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
12173 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
12174 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
12175 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12176 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12177 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
12178 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
12179 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
12180 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
12181 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
12182 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
12183 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12184 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12185 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12186 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12187 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12188 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12189 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12190 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12191 0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
12192 },
12193 { // SPILLTOVSRRC_and_F4RC
12194 0, // SPILLTOVSRRC_and_F4RC:sub_32
12195 0, // SPILLTOVSRRC_and_F4RC:sub_32_hi_phony
12196 0, // SPILLTOVSRRC_and_F4RC:sub_64
12197 0, // SPILLTOVSRRC_and_F4RC:sub_64_hi_phony
12198 0, // SPILLTOVSRRC_and_F4RC:sub_dmr0
12199 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1
12200 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrow0
12201 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrow1
12202 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
12203 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
12204 0, // SPILLTOVSRRC_and_F4RC:sub_eq
12205 0, // SPILLTOVSRRC_and_F4RC:sub_fp0
12206 0, // SPILLTOVSRRC_and_F4RC:sub_fp1
12207 0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x0
12208 0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x1
12209 0, // SPILLTOVSRRC_and_F4RC:sub_gt
12210 0, // SPILLTOVSRRC_and_F4RC:sub_lt
12211 0, // SPILLTOVSRRC_and_F4RC:sub_pair0
12212 0, // SPILLTOVSRRC_and_F4RC:sub_pair1
12213 0, // SPILLTOVSRRC_and_F4RC:sub_un
12214 0, // SPILLTOVSRRC_and_F4RC:sub_vsx0
12215 0, // SPILLTOVSRRC_and_F4RC:sub_vsx1
12216 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi
12217 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_lo
12218 0, // SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64
12219 0, // SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64_hi_phony
12220 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
12221 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64_hi_phony
12222 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
12223 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
12224 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
12225 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12226 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
12227 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
12228 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
12229 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
12230 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
12231 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
12232 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12233 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12234 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
12235 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
12236 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
12237 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
12238 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
12239 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
12240 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12241 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12242 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12243 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12244 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12245 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12246 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12247 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12248 0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
12249 },
12250 { // CTRRC8
12251 0, // CTRRC8:sub_32
12252 0, // CTRRC8:sub_32_hi_phony
12253 0, // CTRRC8:sub_64
12254 0, // CTRRC8:sub_64_hi_phony
12255 0, // CTRRC8:sub_dmr0
12256 0, // CTRRC8:sub_dmr1
12257 0, // CTRRC8:sub_dmrrow0
12258 0, // CTRRC8:sub_dmrrow1
12259 0, // CTRRC8:sub_dmrrowp0
12260 0, // CTRRC8:sub_dmrrowp1
12261 0, // CTRRC8:sub_eq
12262 0, // CTRRC8:sub_fp0
12263 0, // CTRRC8:sub_fp1
12264 0, // CTRRC8:sub_gp8_x0
12265 0, // CTRRC8:sub_gp8_x1
12266 0, // CTRRC8:sub_gt
12267 0, // CTRRC8:sub_lt
12268 0, // CTRRC8:sub_pair0
12269 0, // CTRRC8:sub_pair1
12270 0, // CTRRC8:sub_un
12271 0, // CTRRC8:sub_vsx0
12272 0, // CTRRC8:sub_vsx1
12273 0, // CTRRC8:sub_wacc_hi
12274 0, // CTRRC8:sub_wacc_lo
12275 0, // CTRRC8:sub_vsx1_then_sub_64
12276 0, // CTRRC8:sub_vsx1_then_sub_64_hi_phony
12277 0, // CTRRC8:sub_pair1_then_sub_64
12278 0, // CTRRC8:sub_pair1_then_sub_64_hi_phony
12279 0, // CTRRC8:sub_pair1_then_sub_vsx0
12280 0, // CTRRC8:sub_pair1_then_sub_vsx1
12281 0, // CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64
12282 0, // CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12283 0, // CTRRC8:sub_dmrrowp1_then_sub_dmrrow0
12284 0, // CTRRC8:sub_dmrrowp1_then_sub_dmrrow1
12285 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrow0
12286 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrow1
12287 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp0
12288 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1
12289 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12290 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12291 0, // CTRRC8:sub_dmr1_then_sub_dmrrow0
12292 0, // CTRRC8:sub_dmr1_then_sub_dmrrow1
12293 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp0
12294 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1
12295 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi
12296 0, // CTRRC8:sub_dmr1_then_sub_wacc_lo
12297 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12298 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12299 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12300 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12301 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12302 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12303 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12304 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12305 0, // CTRRC8:sub_gp8_x1_then_sub_32
12306 },
12307 { // LR8RC
12308 0, // LR8RC:sub_32
12309 0, // LR8RC:sub_32_hi_phony
12310 0, // LR8RC:sub_64
12311 0, // LR8RC:sub_64_hi_phony
12312 0, // LR8RC:sub_dmr0
12313 0, // LR8RC:sub_dmr1
12314 0, // LR8RC:sub_dmrrow0
12315 0, // LR8RC:sub_dmrrow1
12316 0, // LR8RC:sub_dmrrowp0
12317 0, // LR8RC:sub_dmrrowp1
12318 0, // LR8RC:sub_eq
12319 0, // LR8RC:sub_fp0
12320 0, // LR8RC:sub_fp1
12321 0, // LR8RC:sub_gp8_x0
12322 0, // LR8RC:sub_gp8_x1
12323 0, // LR8RC:sub_gt
12324 0, // LR8RC:sub_lt
12325 0, // LR8RC:sub_pair0
12326 0, // LR8RC:sub_pair1
12327 0, // LR8RC:sub_un
12328 0, // LR8RC:sub_vsx0
12329 0, // LR8RC:sub_vsx1
12330 0, // LR8RC:sub_wacc_hi
12331 0, // LR8RC:sub_wacc_lo
12332 0, // LR8RC:sub_vsx1_then_sub_64
12333 0, // LR8RC:sub_vsx1_then_sub_64_hi_phony
12334 0, // LR8RC:sub_pair1_then_sub_64
12335 0, // LR8RC:sub_pair1_then_sub_64_hi_phony
12336 0, // LR8RC:sub_pair1_then_sub_vsx0
12337 0, // LR8RC:sub_pair1_then_sub_vsx1
12338 0, // LR8RC:sub_pair1_then_sub_vsx1_then_sub_64
12339 0, // LR8RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12340 0, // LR8RC:sub_dmrrowp1_then_sub_dmrrow0
12341 0, // LR8RC:sub_dmrrowp1_then_sub_dmrrow1
12342 0, // LR8RC:sub_wacc_hi_then_sub_dmrrow0
12343 0, // LR8RC:sub_wacc_hi_then_sub_dmrrow1
12344 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp0
12345 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1
12346 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12347 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12348 0, // LR8RC:sub_dmr1_then_sub_dmrrow0
12349 0, // LR8RC:sub_dmr1_then_sub_dmrrow1
12350 0, // LR8RC:sub_dmr1_then_sub_dmrrowp0
12351 0, // LR8RC:sub_dmr1_then_sub_dmrrowp1
12352 0, // LR8RC:sub_dmr1_then_sub_wacc_hi
12353 0, // LR8RC:sub_dmr1_then_sub_wacc_lo
12354 0, // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12355 0, // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12356 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12357 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12358 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12359 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12360 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12361 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12362 0, // LR8RC:sub_gp8_x1_then_sub_32
12363 },
12364 { // DMRROWRC
12365 0, // DMRROWRC:sub_32
12366 0, // DMRROWRC:sub_32_hi_phony
12367 0, // DMRROWRC:sub_64
12368 0, // DMRROWRC:sub_64_hi_phony
12369 0, // DMRROWRC:sub_dmr0
12370 0, // DMRROWRC:sub_dmr1
12371 0, // DMRROWRC:sub_dmrrow0
12372 0, // DMRROWRC:sub_dmrrow1
12373 0, // DMRROWRC:sub_dmrrowp0
12374 0, // DMRROWRC:sub_dmrrowp1
12375 0, // DMRROWRC:sub_eq
12376 0, // DMRROWRC:sub_fp0
12377 0, // DMRROWRC:sub_fp1
12378 0, // DMRROWRC:sub_gp8_x0
12379 0, // DMRROWRC:sub_gp8_x1
12380 0, // DMRROWRC:sub_gt
12381 0, // DMRROWRC:sub_lt
12382 0, // DMRROWRC:sub_pair0
12383 0, // DMRROWRC:sub_pair1
12384 0, // DMRROWRC:sub_un
12385 0, // DMRROWRC:sub_vsx0
12386 0, // DMRROWRC:sub_vsx1
12387 0, // DMRROWRC:sub_wacc_hi
12388 0, // DMRROWRC:sub_wacc_lo
12389 0, // DMRROWRC:sub_vsx1_then_sub_64
12390 0, // DMRROWRC:sub_vsx1_then_sub_64_hi_phony
12391 0, // DMRROWRC:sub_pair1_then_sub_64
12392 0, // DMRROWRC:sub_pair1_then_sub_64_hi_phony
12393 0, // DMRROWRC:sub_pair1_then_sub_vsx0
12394 0, // DMRROWRC:sub_pair1_then_sub_vsx1
12395 0, // DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64
12396 0, // DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12397 0, // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow0
12398 0, // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow1
12399 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrow0
12400 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrow1
12401 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp0
12402 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1
12403 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12404 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12405 0, // DMRROWRC:sub_dmr1_then_sub_dmrrow0
12406 0, // DMRROWRC:sub_dmr1_then_sub_dmrrow1
12407 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp0
12408 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1
12409 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi
12410 0, // DMRROWRC:sub_dmr1_then_sub_wacc_lo
12411 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12412 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12413 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12414 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12415 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12416 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12417 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12418 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12419 0, // DMRROWRC:sub_gp8_x1_then_sub_32
12420 },
12421 { // VSRC
12422 0, // VSRC:sub_32
12423 0, // VSRC:sub_32_hi_phony
12424 1, // VSRC:sub_64 -> VSSRC
12425 0, // VSRC:sub_64_hi_phony
12426 0, // VSRC:sub_dmr0
12427 0, // VSRC:sub_dmr1
12428 0, // VSRC:sub_dmrrow0
12429 0, // VSRC:sub_dmrrow1
12430 0, // VSRC:sub_dmrrowp0
12431 0, // VSRC:sub_dmrrowp1
12432 0, // VSRC:sub_eq
12433 0, // VSRC:sub_fp0
12434 0, // VSRC:sub_fp1
12435 0, // VSRC:sub_gp8_x0
12436 0, // VSRC:sub_gp8_x1
12437 0, // VSRC:sub_gt
12438 0, // VSRC:sub_lt
12439 0, // VSRC:sub_pair0
12440 0, // VSRC:sub_pair1
12441 0, // VSRC:sub_un
12442 0, // VSRC:sub_vsx0
12443 0, // VSRC:sub_vsx1
12444 0, // VSRC:sub_wacc_hi
12445 0, // VSRC:sub_wacc_lo
12446 0, // VSRC:sub_vsx1_then_sub_64
12447 0, // VSRC:sub_vsx1_then_sub_64_hi_phony
12448 0, // VSRC:sub_pair1_then_sub_64
12449 0, // VSRC:sub_pair1_then_sub_64_hi_phony
12450 0, // VSRC:sub_pair1_then_sub_vsx0
12451 0, // VSRC:sub_pair1_then_sub_vsx1
12452 0, // VSRC:sub_pair1_then_sub_vsx1_then_sub_64
12453 0, // VSRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12454 0, // VSRC:sub_dmrrowp1_then_sub_dmrrow0
12455 0, // VSRC:sub_dmrrowp1_then_sub_dmrrow1
12456 0, // VSRC:sub_wacc_hi_then_sub_dmrrow0
12457 0, // VSRC:sub_wacc_hi_then_sub_dmrrow1
12458 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp0
12459 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1
12460 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12461 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12462 0, // VSRC:sub_dmr1_then_sub_dmrrow0
12463 0, // VSRC:sub_dmr1_then_sub_dmrrow1
12464 0, // VSRC:sub_dmr1_then_sub_dmrrowp0
12465 0, // VSRC:sub_dmr1_then_sub_dmrrowp1
12466 0, // VSRC:sub_dmr1_then_sub_wacc_hi
12467 0, // VSRC:sub_dmr1_then_sub_wacc_lo
12468 0, // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12469 0, // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12470 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12471 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12472 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12473 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12474 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12475 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12476 0, // VSRC:sub_gp8_x1_then_sub_32
12477 },
12478 { // VSRC_with_sub_64_in_SPILLTOVSRRC
12479 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32
12480 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
12481 17, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
12482 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
12483 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
12484 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
12485 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
12486 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
12487 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
12488 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
12489 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
12490 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
12491 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
12492 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
12493 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
12494 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
12495 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
12496 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
12497 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
12498 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_un
12499 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
12500 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
12501 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
12502 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
12503 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12504 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12505 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12506 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12507 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12508 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12509 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12510 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12511 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12512 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12513 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12514 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12515 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12516 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12517 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12518 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12519 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12520 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12521 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12522 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12523 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12524 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12525 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12526 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12527 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12528 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12529 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12530 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12531 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12532 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12533 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12534 },
12535 { // VRRC
12536 0, // VRRC:sub_32
12537 0, // VRRC:sub_32_hi_phony
12538 23, // VRRC:sub_64 -> VFRC
12539 0, // VRRC:sub_64_hi_phony
12540 0, // VRRC:sub_dmr0
12541 0, // VRRC:sub_dmr1
12542 0, // VRRC:sub_dmrrow0
12543 0, // VRRC:sub_dmrrow1
12544 0, // VRRC:sub_dmrrowp0
12545 0, // VRRC:sub_dmrrowp1
12546 0, // VRRC:sub_eq
12547 0, // VRRC:sub_fp0
12548 0, // VRRC:sub_fp1
12549 0, // VRRC:sub_gp8_x0
12550 0, // VRRC:sub_gp8_x1
12551 0, // VRRC:sub_gt
12552 0, // VRRC:sub_lt
12553 0, // VRRC:sub_pair0
12554 0, // VRRC:sub_pair1
12555 0, // VRRC:sub_un
12556 0, // VRRC:sub_vsx0
12557 0, // VRRC:sub_vsx1
12558 0, // VRRC:sub_wacc_hi
12559 0, // VRRC:sub_wacc_lo
12560 0, // VRRC:sub_vsx1_then_sub_64
12561 0, // VRRC:sub_vsx1_then_sub_64_hi_phony
12562 0, // VRRC:sub_pair1_then_sub_64
12563 0, // VRRC:sub_pair1_then_sub_64_hi_phony
12564 0, // VRRC:sub_pair1_then_sub_vsx0
12565 0, // VRRC:sub_pair1_then_sub_vsx1
12566 0, // VRRC:sub_pair1_then_sub_vsx1_then_sub_64
12567 0, // VRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12568 0, // VRRC:sub_dmrrowp1_then_sub_dmrrow0
12569 0, // VRRC:sub_dmrrowp1_then_sub_dmrrow1
12570 0, // VRRC:sub_wacc_hi_then_sub_dmrrow0
12571 0, // VRRC:sub_wacc_hi_then_sub_dmrrow1
12572 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp0
12573 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1
12574 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12575 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12576 0, // VRRC:sub_dmr1_then_sub_dmrrow0
12577 0, // VRRC:sub_dmr1_then_sub_dmrrow1
12578 0, // VRRC:sub_dmr1_then_sub_dmrrowp0
12579 0, // VRRC:sub_dmr1_then_sub_dmrrowp1
12580 0, // VRRC:sub_dmr1_then_sub_wacc_hi
12581 0, // VRRC:sub_dmr1_then_sub_wacc_lo
12582 0, // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12583 0, // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12584 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12585 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12586 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12587 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12588 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12589 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12590 0, // VRRC:sub_gp8_x1_then_sub_32
12591 },
12592 { // VSLRC
12593 0, // VSLRC:sub_32
12594 0, // VSLRC:sub_32_hi_phony
12595 6, // VSLRC:sub_64 -> F4RC
12596 0, // VSLRC:sub_64_hi_phony
12597 0, // VSLRC:sub_dmr0
12598 0, // VSLRC:sub_dmr1
12599 0, // VSLRC:sub_dmrrow0
12600 0, // VSLRC:sub_dmrrow1
12601 0, // VSLRC:sub_dmrrowp0
12602 0, // VSLRC:sub_dmrrowp1
12603 0, // VSLRC:sub_eq
12604 0, // VSLRC:sub_fp0
12605 0, // VSLRC:sub_fp1
12606 0, // VSLRC:sub_gp8_x0
12607 0, // VSLRC:sub_gp8_x1
12608 0, // VSLRC:sub_gt
12609 0, // VSLRC:sub_lt
12610 0, // VSLRC:sub_pair0
12611 0, // VSLRC:sub_pair1
12612 0, // VSLRC:sub_un
12613 0, // VSLRC:sub_vsx0
12614 0, // VSLRC:sub_vsx1
12615 0, // VSLRC:sub_wacc_hi
12616 0, // VSLRC:sub_wacc_lo
12617 0, // VSLRC:sub_vsx1_then_sub_64
12618 0, // VSLRC:sub_vsx1_then_sub_64_hi_phony
12619 0, // VSLRC:sub_pair1_then_sub_64
12620 0, // VSLRC:sub_pair1_then_sub_64_hi_phony
12621 0, // VSLRC:sub_pair1_then_sub_vsx0
12622 0, // VSLRC:sub_pair1_then_sub_vsx1
12623 0, // VSLRC:sub_pair1_then_sub_vsx1_then_sub_64
12624 0, // VSLRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12625 0, // VSLRC:sub_dmrrowp1_then_sub_dmrrow0
12626 0, // VSLRC:sub_dmrrowp1_then_sub_dmrrow1
12627 0, // VSLRC:sub_wacc_hi_then_sub_dmrrow0
12628 0, // VSLRC:sub_wacc_hi_then_sub_dmrrow1
12629 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp0
12630 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1
12631 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12632 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12633 0, // VSLRC:sub_dmr1_then_sub_dmrrow0
12634 0, // VSLRC:sub_dmr1_then_sub_dmrrow1
12635 0, // VSLRC:sub_dmr1_then_sub_dmrrowp0
12636 0, // VSLRC:sub_dmr1_then_sub_dmrrowp1
12637 0, // VSLRC:sub_dmr1_then_sub_wacc_hi
12638 0, // VSLRC:sub_dmr1_then_sub_wacc_lo
12639 0, // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12640 0, // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12641 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12642 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12643 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12644 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12645 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12646 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12647 0, // VSLRC:sub_gp8_x1_then_sub_32
12648 },
12649 { // VRRC_with_sub_64_in_SPILLTOVSRRC
12650 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32
12651 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
12652 25, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VFRC
12653 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
12654 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
12655 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
12656 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
12657 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
12658 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
12659 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
12660 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
12661 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
12662 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
12663 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
12664 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
12665 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
12666 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
12667 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
12668 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
12669 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_un
12670 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
12671 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
12672 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
12673 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
12674 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12675 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12676 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12677 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12678 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12679 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12680 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12681 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12682 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12683 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12684 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12685 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12686 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12687 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12688 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12689 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12690 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12691 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12692 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12693 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12694 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12695 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12696 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12697 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12698 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12699 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12700 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12701 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12702 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12703 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12704 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12705 },
12706 { // FpRC
12707 0, // FpRC:sub_32
12708 0, // FpRC:sub_32_hi_phony
12709 0, // FpRC:sub_64
12710 0, // FpRC:sub_64_hi_phony
12711 0, // FpRC:sub_dmr0
12712 0, // FpRC:sub_dmr1
12713 0, // FpRC:sub_dmrrow0
12714 0, // FpRC:sub_dmrrow1
12715 0, // FpRC:sub_dmrrowp0
12716 0, // FpRC:sub_dmrrowp1
12717 0, // FpRC:sub_eq
12718 19, // FpRC:sub_fp0 -> F8RC
12719 19, // FpRC:sub_fp1 -> F8RC
12720 0, // FpRC:sub_gp8_x0
12721 0, // FpRC:sub_gp8_x1
12722 0, // FpRC:sub_gt
12723 0, // FpRC:sub_lt
12724 0, // FpRC:sub_pair0
12725 0, // FpRC:sub_pair1
12726 0, // FpRC:sub_un
12727 0, // FpRC:sub_vsx0
12728 0, // FpRC:sub_vsx1
12729 0, // FpRC:sub_wacc_hi
12730 0, // FpRC:sub_wacc_lo
12731 0, // FpRC:sub_vsx1_then_sub_64
12732 0, // FpRC:sub_vsx1_then_sub_64_hi_phony
12733 0, // FpRC:sub_pair1_then_sub_64
12734 0, // FpRC:sub_pair1_then_sub_64_hi_phony
12735 0, // FpRC:sub_pair1_then_sub_vsx0
12736 0, // FpRC:sub_pair1_then_sub_vsx1
12737 0, // FpRC:sub_pair1_then_sub_vsx1_then_sub_64
12738 0, // FpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12739 0, // FpRC:sub_dmrrowp1_then_sub_dmrrow0
12740 0, // FpRC:sub_dmrrowp1_then_sub_dmrrow1
12741 0, // FpRC:sub_wacc_hi_then_sub_dmrrow0
12742 0, // FpRC:sub_wacc_hi_then_sub_dmrrow1
12743 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp0
12744 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp1
12745 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12746 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12747 0, // FpRC:sub_dmr1_then_sub_dmrrow0
12748 0, // FpRC:sub_dmr1_then_sub_dmrrow1
12749 0, // FpRC:sub_dmr1_then_sub_dmrrowp0
12750 0, // FpRC:sub_dmr1_then_sub_dmrrowp1
12751 0, // FpRC:sub_dmr1_then_sub_wacc_hi
12752 0, // FpRC:sub_dmr1_then_sub_wacc_lo
12753 0, // FpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12754 0, // FpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12755 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12756 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12757 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12758 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12759 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12760 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12761 0, // FpRC:sub_gp8_x1_then_sub_32
12762 },
12763 { // G8pRC
12764 2, // G8pRC:sub_32 -> GPRC
12765 0, // G8pRC:sub_32_hi_phony
12766 0, // G8pRC:sub_64
12767 0, // G8pRC:sub_64_hi_phony
12768 0, // G8pRC:sub_dmr0
12769 0, // G8pRC:sub_dmr1
12770 0, // G8pRC:sub_dmrrow0
12771 0, // G8pRC:sub_dmrrow1
12772 0, // G8pRC:sub_dmrrowp0
12773 0, // G8pRC:sub_dmrrowp1
12774 0, // G8pRC:sub_eq
12775 0, // G8pRC:sub_fp0
12776 0, // G8pRC:sub_fp1
12777 15, // G8pRC:sub_gp8_x0 -> G8RC
12778 18, // G8pRC:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
12779 0, // G8pRC:sub_gt
12780 0, // G8pRC:sub_lt
12781 0, // G8pRC:sub_pair0
12782 0, // G8pRC:sub_pair1
12783 0, // G8pRC:sub_un
12784 0, // G8pRC:sub_vsx0
12785 0, // G8pRC:sub_vsx1
12786 0, // G8pRC:sub_wacc_hi
12787 0, // G8pRC:sub_wacc_lo
12788 0, // G8pRC:sub_vsx1_then_sub_64
12789 0, // G8pRC:sub_vsx1_then_sub_64_hi_phony
12790 0, // G8pRC:sub_pair1_then_sub_64
12791 0, // G8pRC:sub_pair1_then_sub_64_hi_phony
12792 0, // G8pRC:sub_pair1_then_sub_vsx0
12793 0, // G8pRC:sub_pair1_then_sub_vsx1
12794 0, // G8pRC:sub_pair1_then_sub_vsx1_then_sub_64
12795 0, // G8pRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12796 0, // G8pRC:sub_dmrrowp1_then_sub_dmrrow0
12797 0, // G8pRC:sub_dmrrowp1_then_sub_dmrrow1
12798 0, // G8pRC:sub_wacc_hi_then_sub_dmrrow0
12799 0, // G8pRC:sub_wacc_hi_then_sub_dmrrow1
12800 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp0
12801 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1
12802 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12803 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12804 0, // G8pRC:sub_dmr1_then_sub_dmrrow0
12805 0, // G8pRC:sub_dmr1_then_sub_dmrrow1
12806 0, // G8pRC:sub_dmr1_then_sub_dmrrowp0
12807 0, // G8pRC:sub_dmr1_then_sub_dmrrowp1
12808 0, // G8pRC:sub_dmr1_then_sub_wacc_hi
12809 0, // G8pRC:sub_dmr1_then_sub_wacc_lo
12810 0, // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12811 0, // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12812 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12813 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12814 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12815 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12816 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12817 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12818 4, // G8pRC:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
12819 },
12820 { // G8pRC_with_sub_32_in_GPRC_NOR0
12821 4, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
12822 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32_hi_phony
12823 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_64
12824 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_64_hi_phony
12825 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr0
12826 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1
12827 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
12828 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
12829 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
12830 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
12831 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_eq
12832 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_fp0
12833 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_fp1
12834 18, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0 -> G8RC_and_G8RC_NOX0
12835 18, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
12836 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gt
12837 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_lt
12838 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair0
12839 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1
12840 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_un
12841 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx0
12842 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1
12843 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
12844 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
12845 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
12846 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
12847 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
12848 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
12849 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
12850 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
12851 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
12852 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12853 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
12854 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
12855 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
12856 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
12857 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
12858 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
12859 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12860 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12861 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
12862 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
12863 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
12864 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
12865 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
12866 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
12867 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12868 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12869 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12870 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12871 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12872 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12873 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12874 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12875 4, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
12876 },
12877 { // VSLRC_with_sub_64_in_SPILLTOVSRRC
12878 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32
12879 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
12880 26, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
12881 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
12882 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
12883 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
12884 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
12885 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
12886 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
12887 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
12888 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
12889 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
12890 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
12891 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
12892 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
12893 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
12894 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
12895 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
12896 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
12897 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_un
12898 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
12899 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
12900 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
12901 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
12902 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12903 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12904 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12905 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12906 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12907 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12908 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12909 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12910 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12911 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12912 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12913 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12914 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12915 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12916 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12917 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12918 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12919 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12920 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12921 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12922 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12923 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12924 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12925 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12926 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12927 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12928 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12929 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12930 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12931 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12932 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12933 },
12934 { // FpRC_with_sub_fp0_in_SPILLTOVSRRC
12935 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_32
12936 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_32_hi_phony
12937 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_64
12938 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_64_hi_phony
12939 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr0
12940 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1
12941 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrow0
12942 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrow1
12943 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp0
12944 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1
12945 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_eq
12946 26, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_fp0 -> SPILLTOVSRRC_and_F4RC
12947 26, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_fp1 -> SPILLTOVSRRC_and_F4RC
12948 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x0
12949 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x1
12950 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gt
12951 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_lt
12952 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair0
12953 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1
12954 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_un
12955 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx0
12956 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1
12957 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi
12958 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_lo
12959 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12960 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12961 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12962 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12963 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12964 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12965 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12966 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12967 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12968 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12969 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12970 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12971 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12972 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12973 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12974 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12975 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12976 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12977 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12978 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12979 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12980 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12981 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12982 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12983 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12984 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12985 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12986 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12987 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12988 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12989 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12990 },
12991 { // DMRROWpRC
12992 0, // DMRROWpRC:sub_32
12993 0, // DMRROWpRC:sub_32_hi_phony
12994 0, // DMRROWpRC:sub_64
12995 0, // DMRROWpRC:sub_64_hi_phony
12996 0, // DMRROWpRC:sub_dmr0
12997 0, // DMRROWpRC:sub_dmr1
12998 29, // DMRROWpRC:sub_dmrrow0 -> DMRROWRC
12999 29, // DMRROWpRC:sub_dmrrow1 -> DMRROWRC
13000 0, // DMRROWpRC:sub_dmrrowp0
13001 0, // DMRROWpRC:sub_dmrrowp1
13002 0, // DMRROWpRC:sub_eq
13003 0, // DMRROWpRC:sub_fp0
13004 0, // DMRROWpRC:sub_fp1
13005 0, // DMRROWpRC:sub_gp8_x0
13006 0, // DMRROWpRC:sub_gp8_x1
13007 0, // DMRROWpRC:sub_gt
13008 0, // DMRROWpRC:sub_lt
13009 0, // DMRROWpRC:sub_pair0
13010 0, // DMRROWpRC:sub_pair1
13011 0, // DMRROWpRC:sub_un
13012 0, // DMRROWpRC:sub_vsx0
13013 0, // DMRROWpRC:sub_vsx1
13014 0, // DMRROWpRC:sub_wacc_hi
13015 0, // DMRROWpRC:sub_wacc_lo
13016 0, // DMRROWpRC:sub_vsx1_then_sub_64
13017 0, // DMRROWpRC:sub_vsx1_then_sub_64_hi_phony
13018 0, // DMRROWpRC:sub_pair1_then_sub_64
13019 0, // DMRROWpRC:sub_pair1_then_sub_64_hi_phony
13020 0, // DMRROWpRC:sub_pair1_then_sub_vsx0
13021 0, // DMRROWpRC:sub_pair1_then_sub_vsx1
13022 0, // DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64
13023 0, // DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13024 0, // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow0
13025 0, // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow1
13026 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow0
13027 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow1
13028 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp0
13029 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1
13030 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13031 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13032 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrow0
13033 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrow1
13034 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp0
13035 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1
13036 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi
13037 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_lo
13038 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13039 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13040 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13041 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13042 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13043 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13044 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13045 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13046 0, // DMRROWpRC:sub_gp8_x1_then_sub_32
13047 },
13048 { // VSRpRC
13049 0, // VSRpRC:sub_32
13050 0, // VSRpRC:sub_32_hi_phony
13051 14, // VSRpRC:sub_64 -> VSFRC
13052 0, // VSRpRC:sub_64_hi_phony
13053 0, // VSRpRC:sub_dmr0
13054 0, // VSRpRC:sub_dmr1
13055 0, // VSRpRC:sub_dmrrow0
13056 0, // VSRpRC:sub_dmrrow1
13057 0, // VSRpRC:sub_dmrrowp0
13058 0, // VSRpRC:sub_dmrrowp1
13059 0, // VSRpRC:sub_eq
13060 0, // VSRpRC:sub_fp0
13061 0, // VSRpRC:sub_fp1
13062 0, // VSRpRC:sub_gp8_x0
13063 0, // VSRpRC:sub_gp8_x1
13064 0, // VSRpRC:sub_gt
13065 0, // VSRpRC:sub_lt
13066 0, // VSRpRC:sub_pair0
13067 0, // VSRpRC:sub_pair1
13068 0, // VSRpRC:sub_un
13069 30, // VSRpRC:sub_vsx0 -> VSRC
13070 30, // VSRpRC:sub_vsx1 -> VSRC
13071 0, // VSRpRC:sub_wacc_hi
13072 0, // VSRpRC:sub_wacc_lo
13073 14, // VSRpRC:sub_vsx1_then_sub_64 -> VSFRC
13074 0, // VSRpRC:sub_vsx1_then_sub_64_hi_phony
13075 0, // VSRpRC:sub_pair1_then_sub_64
13076 0, // VSRpRC:sub_pair1_then_sub_64_hi_phony
13077 0, // VSRpRC:sub_pair1_then_sub_vsx0
13078 0, // VSRpRC:sub_pair1_then_sub_vsx1
13079 0, // VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64
13080 0, // VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13081 0, // VSRpRC:sub_dmrrowp1_then_sub_dmrrow0
13082 0, // VSRpRC:sub_dmrrowp1_then_sub_dmrrow1
13083 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrow0
13084 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrow1
13085 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp0
13086 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1
13087 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13088 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13089 0, // VSRpRC:sub_dmr1_then_sub_dmrrow0
13090 0, // VSRpRC:sub_dmr1_then_sub_dmrrow1
13091 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp0
13092 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1
13093 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi
13094 0, // VSRpRC:sub_dmr1_then_sub_wacc_lo
13095 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13096 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13097 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13098 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13099 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13100 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13101 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13102 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13103 0, // VSRpRC:sub_gp8_x1_then_sub_32
13104 },
13105 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC
13106 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32
13107 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13108 17, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
13109 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13110 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
13111 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
13112 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13113 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13114 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13115 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13116 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
13117 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
13118 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
13119 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13120 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13121 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
13122 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
13123 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
13124 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
13125 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_un
13126 31, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSRC_with_sub_64_in_SPILLTOVSRRC
13127 31, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSRC_with_sub_64_in_SPILLTOVSRRC
13128 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13129 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13130 17, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VSFRC
13131 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13132 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
13133 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13134 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
13135 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
13136 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
13137 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13138 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13139 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13140 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13141 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13142 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13143 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13144 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13145 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13146 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13147 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13148 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13149 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13150 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13151 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13152 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13153 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13154 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13155 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13156 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13157 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13158 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13159 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13160 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13161 },
13162 { // VSRpRC_with_sub_64_in_F4RC
13163 0, // VSRpRC_with_sub_64_in_F4RC:sub_32
13164 0, // VSRpRC_with_sub_64_in_F4RC:sub_32_hi_phony
13165 19, // VSRpRC_with_sub_64_in_F4RC:sub_64 -> F8RC
13166 0, // VSRpRC_with_sub_64_in_F4RC:sub_64_hi_phony
13167 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr0
13168 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1
13169 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow0
13170 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow1
13171 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp0
13172 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1
13173 0, // VSRpRC_with_sub_64_in_F4RC:sub_eq
13174 0, // VSRpRC_with_sub_64_in_F4RC:sub_fp0
13175 0, // VSRpRC_with_sub_64_in_F4RC:sub_fp1
13176 0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x0
13177 0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1
13178 0, // VSRpRC_with_sub_64_in_F4RC:sub_gt
13179 0, // VSRpRC_with_sub_64_in_F4RC:sub_lt
13180 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair0
13181 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1
13182 0, // VSRpRC_with_sub_64_in_F4RC:sub_un
13183 33, // VSRpRC_with_sub_64_in_F4RC:sub_vsx0 -> VSLRC
13184 33, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1 -> VSLRC
13185 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi
13186 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_lo
13187 19, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64 -> F8RC
13188 0, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64_hi_phony
13189 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64
13190 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64_hi_phony
13191 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx0
13192 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1
13193 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
13194 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13195 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow0
13196 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow1
13197 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow0
13198 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow1
13199 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp0
13200 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1
13201 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13202 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13203 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow0
13204 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow1
13205 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp0
13206 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1
13207 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi
13208 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_lo
13209 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13210 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13211 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13212 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13213 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13214 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13215 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13216 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13217 0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1_then_sub_32
13218 },
13219 { // VSRpRC_with_sub_64_in_VFRC
13220 0, // VSRpRC_with_sub_64_in_VFRC:sub_32
13221 0, // VSRpRC_with_sub_64_in_VFRC:sub_32_hi_phony
13222 23, // VSRpRC_with_sub_64_in_VFRC:sub_64 -> VFRC
13223 0, // VSRpRC_with_sub_64_in_VFRC:sub_64_hi_phony
13224 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr0
13225 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1
13226 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow0
13227 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow1
13228 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp0
13229 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1
13230 0, // VSRpRC_with_sub_64_in_VFRC:sub_eq
13231 0, // VSRpRC_with_sub_64_in_VFRC:sub_fp0
13232 0, // VSRpRC_with_sub_64_in_VFRC:sub_fp1
13233 0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x0
13234 0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1
13235 0, // VSRpRC_with_sub_64_in_VFRC:sub_gt
13236 0, // VSRpRC_with_sub_64_in_VFRC:sub_lt
13237 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair0
13238 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1
13239 0, // VSRpRC_with_sub_64_in_VFRC:sub_un
13240 32, // VSRpRC_with_sub_64_in_VFRC:sub_vsx0 -> VRRC
13241 32, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1 -> VRRC
13242 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi
13243 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_lo
13244 23, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64 -> VFRC
13245 0, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64_hi_phony
13246 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64
13247 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64_hi_phony
13248 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx0
13249 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1
13250 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
13251 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13252 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow0
13253 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow1
13254 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow0
13255 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow1
13256 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp0
13257 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1
13258 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13259 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13260 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow0
13261 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow1
13262 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp0
13263 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1
13264 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi
13265 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_lo
13266 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13267 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13268 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13269 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13270 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13271 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13272 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13273 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13274 0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1_then_sub_32
13275 },
13276 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
13277 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32
13278 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32_hi_phony
13279 25, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64 -> SPILLTOVSRRC_and_VFRC
13280 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64_hi_phony
13281 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr0
13282 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1
13283 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow0
13284 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow1
13285 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
13286 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
13287 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_eq
13288 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_fp0
13289 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_fp1
13290 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x0
13291 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1
13292 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gt
13293 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_lt
13294 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair0
13295 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1
13296 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_un
13297 34, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx0 -> VRRC_with_sub_64_in_SPILLTOVSRRC
13298 34, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1 -> VRRC_with_sub_64_in_SPILLTOVSRRC
13299 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi
13300 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_lo
13301 25, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VFRC
13302 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64_hi_phony
13303 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
13304 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64_hi_phony
13305 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
13306 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
13307 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
13308 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13309 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
13310 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
13311 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
13312 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
13313 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
13314 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
13315 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13316 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13317 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
13318 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
13319 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
13320 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
13321 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
13322 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
13323 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13324 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13325 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13326 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13327 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13328 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13329 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13330 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13331 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
13332 },
13333 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13334 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32
13335 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32_hi_phony
13336 26, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64 -> SPILLTOVSRRC_and_F4RC
13337 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64_hi_phony
13338 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr0
13339 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1
13340 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow0
13341 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow1
13342 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
13343 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
13344 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_eq
13345 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_fp0
13346 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_fp1
13347 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x0
13348 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1
13349 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gt
13350 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_lt
13351 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair0
13352 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1
13353 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_un
13354 38, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13355 38, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13356 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi
13357 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_lo
13358 26, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13359 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64_hi_phony
13360 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
13361 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64_hi_phony
13362 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
13363 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
13364 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
13365 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13366 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
13367 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
13368 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
13369 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
13370 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
13371 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
13372 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13373 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13374 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
13375 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
13376 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
13377 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
13378 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
13379 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
13380 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13381 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13382 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13383 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13384 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13385 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13386 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13387 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13388 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
13389 },
13390 { // ACCRC
13391 0, // ACCRC:sub_32
13392 0, // ACCRC:sub_32_hi_phony
13393 19, // ACCRC:sub_64 -> F8RC
13394 0, // ACCRC:sub_64_hi_phony
13395 0, // ACCRC:sub_dmr0
13396 0, // ACCRC:sub_dmr1
13397 0, // ACCRC:sub_dmrrow0
13398 0, // ACCRC:sub_dmrrow1
13399 0, // ACCRC:sub_dmrrowp0
13400 0, // ACCRC:sub_dmrrowp1
13401 0, // ACCRC:sub_eq
13402 0, // ACCRC:sub_fp0
13403 0, // ACCRC:sub_fp1
13404 0, // ACCRC:sub_gp8_x0
13405 0, // ACCRC:sub_gp8_x1
13406 0, // ACCRC:sub_gt
13407 0, // ACCRC:sub_lt
13408 43, // ACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
13409 43, // ACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13410 0, // ACCRC:sub_un
13411 33, // ACCRC:sub_vsx0 -> VSLRC
13412 33, // ACCRC:sub_vsx1 -> VSLRC
13413 0, // ACCRC:sub_wacc_hi
13414 0, // ACCRC:sub_wacc_lo
13415 19, // ACCRC:sub_vsx1_then_sub_64 -> F8RC
13416 0, // ACCRC:sub_vsx1_then_sub_64_hi_phony
13417 19, // ACCRC:sub_pair1_then_sub_64 -> F8RC
13418 0, // ACCRC:sub_pair1_then_sub_64_hi_phony
13419 33, // ACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
13420 33, // ACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
13421 19, // ACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13422 0, // ACCRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13423 0, // ACCRC:sub_dmrrowp1_then_sub_dmrrow0
13424 0, // ACCRC:sub_dmrrowp1_then_sub_dmrrow1
13425 0, // ACCRC:sub_wacc_hi_then_sub_dmrrow0
13426 0, // ACCRC:sub_wacc_hi_then_sub_dmrrow1
13427 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp0
13428 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1
13429 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13430 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13431 0, // ACCRC:sub_dmr1_then_sub_dmrrow0
13432 0, // ACCRC:sub_dmr1_then_sub_dmrrow1
13433 0, // ACCRC:sub_dmr1_then_sub_dmrrowp0
13434 0, // ACCRC:sub_dmr1_then_sub_dmrrowp1
13435 0, // ACCRC:sub_dmr1_then_sub_wacc_hi
13436 0, // ACCRC:sub_dmr1_then_sub_wacc_lo
13437 0, // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13438 0, // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13439 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13440 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13441 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13442 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13443 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13444 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13445 0, // ACCRC:sub_gp8_x1_then_sub_32
13446 },
13447 { // UACCRC
13448 0, // UACCRC:sub_32
13449 0, // UACCRC:sub_32_hi_phony
13450 19, // UACCRC:sub_64 -> F8RC
13451 0, // UACCRC:sub_64_hi_phony
13452 0, // UACCRC:sub_dmr0
13453 0, // UACCRC:sub_dmr1
13454 0, // UACCRC:sub_dmrrow0
13455 0, // UACCRC:sub_dmrrow1
13456 0, // UACCRC:sub_dmrrowp0
13457 0, // UACCRC:sub_dmrrowp1
13458 0, // UACCRC:sub_eq
13459 0, // UACCRC:sub_fp0
13460 0, // UACCRC:sub_fp1
13461 0, // UACCRC:sub_gp8_x0
13462 0, // UACCRC:sub_gp8_x1
13463 0, // UACCRC:sub_gt
13464 0, // UACCRC:sub_lt
13465 43, // UACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
13466 43, // UACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13467 0, // UACCRC:sub_un
13468 33, // UACCRC:sub_vsx0 -> VSLRC
13469 33, // UACCRC:sub_vsx1 -> VSLRC
13470 0, // UACCRC:sub_wacc_hi
13471 0, // UACCRC:sub_wacc_lo
13472 19, // UACCRC:sub_vsx1_then_sub_64 -> F8RC
13473 0, // UACCRC:sub_vsx1_then_sub_64_hi_phony
13474 19, // UACCRC:sub_pair1_then_sub_64 -> F8RC
13475 0, // UACCRC:sub_pair1_then_sub_64_hi_phony
13476 33, // UACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
13477 33, // UACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
13478 19, // UACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13479 0, // UACCRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13480 0, // UACCRC:sub_dmrrowp1_then_sub_dmrrow0
13481 0, // UACCRC:sub_dmrrowp1_then_sub_dmrrow1
13482 0, // UACCRC:sub_wacc_hi_then_sub_dmrrow0
13483 0, // UACCRC:sub_wacc_hi_then_sub_dmrrow1
13484 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp0
13485 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1
13486 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13487 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13488 0, // UACCRC:sub_dmr1_then_sub_dmrrow0
13489 0, // UACCRC:sub_dmr1_then_sub_dmrrow1
13490 0, // UACCRC:sub_dmr1_then_sub_dmrrowp0
13491 0, // UACCRC:sub_dmr1_then_sub_dmrrowp1
13492 0, // UACCRC:sub_dmr1_then_sub_wacc_hi
13493 0, // UACCRC:sub_dmr1_then_sub_wacc_lo
13494 0, // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13495 0, // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13496 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13497 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13498 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13499 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13500 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13501 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13502 0, // UACCRC:sub_gp8_x1_then_sub_32
13503 },
13504 { // WACCRC
13505 0, // WACCRC:sub_32
13506 0, // WACCRC:sub_32_hi_phony
13507 0, // WACCRC:sub_64
13508 0, // WACCRC:sub_64_hi_phony
13509 0, // WACCRC:sub_dmr0
13510 0, // WACCRC:sub_dmr1
13511 29, // WACCRC:sub_dmrrow0 -> DMRROWRC
13512 29, // WACCRC:sub_dmrrow1 -> DMRROWRC
13513 40, // WACCRC:sub_dmrrowp0 -> DMRROWpRC
13514 40, // WACCRC:sub_dmrrowp1 -> DMRROWpRC
13515 0, // WACCRC:sub_eq
13516 0, // WACCRC:sub_fp0
13517 0, // WACCRC:sub_fp1
13518 0, // WACCRC:sub_gp8_x0
13519 0, // WACCRC:sub_gp8_x1
13520 0, // WACCRC:sub_gt
13521 0, // WACCRC:sub_lt
13522 0, // WACCRC:sub_pair0
13523 0, // WACCRC:sub_pair1
13524 0, // WACCRC:sub_un
13525 0, // WACCRC:sub_vsx0
13526 0, // WACCRC:sub_vsx1
13527 0, // WACCRC:sub_wacc_hi
13528 0, // WACCRC:sub_wacc_lo
13529 0, // WACCRC:sub_vsx1_then_sub_64
13530 0, // WACCRC:sub_vsx1_then_sub_64_hi_phony
13531 0, // WACCRC:sub_pair1_then_sub_64
13532 0, // WACCRC:sub_pair1_then_sub_64_hi_phony
13533 0, // WACCRC:sub_pair1_then_sub_vsx0
13534 0, // WACCRC:sub_pair1_then_sub_vsx1
13535 0, // WACCRC:sub_pair1_then_sub_vsx1_then_sub_64
13536 0, // WACCRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13537 29, // WACCRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13538 29, // WACCRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13539 0, // WACCRC:sub_wacc_hi_then_sub_dmrrow0
13540 0, // WACCRC:sub_wacc_hi_then_sub_dmrrow1
13541 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp0
13542 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1
13543 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13544 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13545 0, // WACCRC:sub_dmr1_then_sub_dmrrow0
13546 0, // WACCRC:sub_dmr1_then_sub_dmrrow1
13547 0, // WACCRC:sub_dmr1_then_sub_dmrrowp0
13548 0, // WACCRC:sub_dmr1_then_sub_dmrrowp1
13549 0, // WACCRC:sub_dmr1_then_sub_wacc_hi
13550 0, // WACCRC:sub_dmr1_then_sub_wacc_lo
13551 0, // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13552 0, // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13553 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13554 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13555 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13556 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13557 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13558 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13559 0, // WACCRC:sub_gp8_x1_then_sub_32
13560 },
13561 { // WACC_HIRC
13562 0, // WACC_HIRC:sub_32
13563 0, // WACC_HIRC:sub_32_hi_phony
13564 0, // WACC_HIRC:sub_64
13565 0, // WACC_HIRC:sub_64_hi_phony
13566 0, // WACC_HIRC:sub_dmr0
13567 0, // WACC_HIRC:sub_dmr1
13568 29, // WACC_HIRC:sub_dmrrow0 -> DMRROWRC
13569 29, // WACC_HIRC:sub_dmrrow1 -> DMRROWRC
13570 40, // WACC_HIRC:sub_dmrrowp0 -> DMRROWpRC
13571 40, // WACC_HIRC:sub_dmrrowp1 -> DMRROWpRC
13572 0, // WACC_HIRC:sub_eq
13573 0, // WACC_HIRC:sub_fp0
13574 0, // WACC_HIRC:sub_fp1
13575 0, // WACC_HIRC:sub_gp8_x0
13576 0, // WACC_HIRC:sub_gp8_x1
13577 0, // WACC_HIRC:sub_gt
13578 0, // WACC_HIRC:sub_lt
13579 0, // WACC_HIRC:sub_pair0
13580 0, // WACC_HIRC:sub_pair1
13581 0, // WACC_HIRC:sub_un
13582 0, // WACC_HIRC:sub_vsx0
13583 0, // WACC_HIRC:sub_vsx1
13584 0, // WACC_HIRC:sub_wacc_hi
13585 0, // WACC_HIRC:sub_wacc_lo
13586 0, // WACC_HIRC:sub_vsx1_then_sub_64
13587 0, // WACC_HIRC:sub_vsx1_then_sub_64_hi_phony
13588 0, // WACC_HIRC:sub_pair1_then_sub_64
13589 0, // WACC_HIRC:sub_pair1_then_sub_64_hi_phony
13590 0, // WACC_HIRC:sub_pair1_then_sub_vsx0
13591 0, // WACC_HIRC:sub_pair1_then_sub_vsx1
13592 0, // WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64
13593 0, // WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13594 29, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13595 29, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13596 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow0
13597 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow1
13598 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp0
13599 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1
13600 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13601 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13602 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrow0
13603 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrow1
13604 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp0
13605 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1
13606 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi
13607 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_lo
13608 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13609 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13610 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13611 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13612 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13613 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13614 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13615 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13616 0, // WACC_HIRC:sub_gp8_x1_then_sub_32
13617 },
13618 { // ACCRC_with_sub_64_in_SPILLTOVSRRC
13619 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
13620 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13621 26, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13622 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13623 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
13624 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
13625 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13626 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13627 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13628 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13629 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
13630 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
13631 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
13632 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13633 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13634 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
13635 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
13636 46, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13637 43, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13638 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
13639 38, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13640 38, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13641 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13642 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13643 26, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13644 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13645 19, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
13646 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13647 33, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
13648 33, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
13649 19, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13650 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13651 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13652 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13653 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13654 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13655 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13656 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13657 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13658 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13659 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13660 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13661 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13662 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13663 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13664 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13665 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13666 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13667 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13668 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13669 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13670 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13671 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13672 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13673 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13674 },
13675 { // UACCRC_with_sub_64_in_SPILLTOVSRRC
13676 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
13677 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13678 26, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13679 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13680 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
13681 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
13682 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13683 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13684 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13685 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13686 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
13687 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
13688 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
13689 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13690 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13691 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
13692 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
13693 46, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13694 43, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13695 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
13696 38, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13697 38, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13698 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13699 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13700 26, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13701 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13702 19, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
13703 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13704 33, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
13705 33, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
13706 19, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13707 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13708 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13709 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13710 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13711 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13712 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13713 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13714 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13715 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13716 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13717 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13718 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13719 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13720 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13721 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13722 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13723 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13724 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13725 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13726 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13727 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13728 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13729 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13730 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13731 },
13732 { // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
13733 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
13734 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13735 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13736 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13737 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
13738 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
13739 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13740 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13741 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13742 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13743 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
13744 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp0
13745 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp1
13746 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13747 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13748 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
13749 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
13750 46, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13751 46, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13752 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
13753 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13754 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13755 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13756 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13757 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13758 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13759 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13760 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13761 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13762 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13763 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13764 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13765 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13766 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13767 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13768 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13769 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13770 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13771 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13772 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13773 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13774 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13775 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13776 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13777 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13778 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13779 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13780 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13781 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13782 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13783 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13784 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13785 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13786 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13787 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13788 },
13789 { // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
13790 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
13791 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13792 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13793 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13794 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
13795 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
13796 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13797 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13798 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13799 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13800 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
13801 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp0
13802 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp1
13803 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13804 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13805 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
13806 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
13807 46, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13808 46, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13809 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
13810 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13811 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13812 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13813 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13814 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13815 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13816 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13817 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13818 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13819 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13820 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13821 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13822 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13823 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13824 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13825 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13826 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13827 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13828 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13829 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13830 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13831 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13832 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13833 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13834 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13835 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13836 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13837 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13838 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13839 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13840 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13841 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13842 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13843 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13844 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13845 },
13846 { // DMRRC
13847 0, // DMRRC:sub_32
13848 0, // DMRRC:sub_32_hi_phony
13849 0, // DMRRC:sub_64
13850 0, // DMRRC:sub_64_hi_phony
13851 0, // DMRRC:sub_dmr0
13852 0, // DMRRC:sub_dmr1
13853 29, // DMRRC:sub_dmrrow0 -> DMRROWRC
13854 29, // DMRRC:sub_dmrrow1 -> DMRROWRC
13855 40, // DMRRC:sub_dmrrowp0 -> DMRROWpRC
13856 40, // DMRRC:sub_dmrrowp1 -> DMRROWpRC
13857 0, // DMRRC:sub_eq
13858 0, // DMRRC:sub_fp0
13859 0, // DMRRC:sub_fp1
13860 0, // DMRRC:sub_gp8_x0
13861 0, // DMRRC:sub_gp8_x1
13862 0, // DMRRC:sub_gt
13863 0, // DMRRC:sub_lt
13864 0, // DMRRC:sub_pair0
13865 0, // DMRRC:sub_pair1
13866 0, // DMRRC:sub_un
13867 0, // DMRRC:sub_vsx0
13868 0, // DMRRC:sub_vsx1
13869 50, // DMRRC:sub_wacc_hi -> WACC_HIRC
13870 49, // DMRRC:sub_wacc_lo -> WACCRC
13871 0, // DMRRC:sub_vsx1_then_sub_64
13872 0, // DMRRC:sub_vsx1_then_sub_64_hi_phony
13873 0, // DMRRC:sub_pair1_then_sub_64
13874 0, // DMRRC:sub_pair1_then_sub_64_hi_phony
13875 0, // DMRRC:sub_pair1_then_sub_vsx0
13876 0, // DMRRC:sub_pair1_then_sub_vsx1
13877 0, // DMRRC:sub_pair1_then_sub_vsx1_then_sub_64
13878 0, // DMRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13879 29, // DMRRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13880 29, // DMRRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13881 29, // DMRRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
13882 29, // DMRRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
13883 40, // DMRRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
13884 40, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
13885 29, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13886 29, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13887 0, // DMRRC:sub_dmr1_then_sub_dmrrow0
13888 0, // DMRRC:sub_dmr1_then_sub_dmrrow1
13889 0, // DMRRC:sub_dmr1_then_sub_dmrrowp0
13890 0, // DMRRC:sub_dmr1_then_sub_dmrrowp1
13891 0, // DMRRC:sub_dmr1_then_sub_wacc_hi
13892 0, // DMRRC:sub_dmr1_then_sub_wacc_lo
13893 0, // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13894 0, // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13895 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13896 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13897 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13898 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13899 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13900 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13901 0, // DMRRC:sub_gp8_x1_then_sub_32
13902 },
13903 { // DMRpRC
13904 0, // DMRpRC:sub_32
13905 0, // DMRpRC:sub_32_hi_phony
13906 0, // DMRpRC:sub_64
13907 0, // DMRpRC:sub_64_hi_phony
13908 55, // DMRpRC:sub_dmr0 -> DMRRC
13909 55, // DMRpRC:sub_dmr1 -> DMRRC
13910 29, // DMRpRC:sub_dmrrow0 -> DMRROWRC
13911 29, // DMRpRC:sub_dmrrow1 -> DMRROWRC
13912 40, // DMRpRC:sub_dmrrowp0 -> DMRROWpRC
13913 40, // DMRpRC:sub_dmrrowp1 -> DMRROWpRC
13914 0, // DMRpRC:sub_eq
13915 0, // DMRpRC:sub_fp0
13916 0, // DMRpRC:sub_fp1
13917 0, // DMRpRC:sub_gp8_x0
13918 0, // DMRpRC:sub_gp8_x1
13919 0, // DMRpRC:sub_gt
13920 0, // DMRpRC:sub_lt
13921 0, // DMRpRC:sub_pair0
13922 0, // DMRpRC:sub_pair1
13923 0, // DMRpRC:sub_un
13924 0, // DMRpRC:sub_vsx0
13925 0, // DMRpRC:sub_vsx1
13926 50, // DMRpRC:sub_wacc_hi -> WACC_HIRC
13927 49, // DMRpRC:sub_wacc_lo -> WACCRC
13928 0, // DMRpRC:sub_vsx1_then_sub_64
13929 0, // DMRpRC:sub_vsx1_then_sub_64_hi_phony
13930 0, // DMRpRC:sub_pair1_then_sub_64
13931 0, // DMRpRC:sub_pair1_then_sub_64_hi_phony
13932 0, // DMRpRC:sub_pair1_then_sub_vsx0
13933 0, // DMRpRC:sub_pair1_then_sub_vsx1
13934 0, // DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64
13935 0, // DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13936 29, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13937 29, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13938 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
13939 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
13940 40, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
13941 40, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
13942 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13943 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13944 29, // DMRpRC:sub_dmr1_then_sub_dmrrow0 -> DMRROWRC
13945 29, // DMRpRC:sub_dmr1_then_sub_dmrrow1 -> DMRROWRC
13946 40, // DMRpRC:sub_dmr1_then_sub_dmrrowp0 -> DMRROWpRC
13947 40, // DMRpRC:sub_dmr1_then_sub_dmrrowp1 -> DMRROWpRC
13948 50, // DMRpRC:sub_dmr1_then_sub_wacc_hi -> WACC_HIRC
13949 49, // DMRpRC:sub_dmr1_then_sub_wacc_lo -> WACCRC
13950 29, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13951 29, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13952 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
13953 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
13954 40, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
13955 40, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
13956 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13957 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13958 0, // DMRpRC:sub_gp8_x1_then_sub_32
13959 },
13960 };
13961 assert(RC && "Missing regclass");
13962 if (!Idx) return RC;
13963 --Idx;
13964 assert(Idx < 55 && "Bad subreg");
13965 unsigned TV = Table[RC->getID()][Idx];
13966 return TV ? getRegClass(TV - 1) : nullptr;
13967}
13968
13969/// Get the weight in units of pressure for this register class.
13970const RegClassWeight &PPCGenRegisterInfo::
13971getRegClassWeight(const TargetRegisterClass *RC) const {
13972 static const RegClassWeight RCWeightTable[] = {
13973 {1, 64}, // VSSRC
13974 {1, 34}, // GPRC
13975 {1, 34}, // GPRC_NOR0
13976 {1, 33}, // GPRC_and_GPRC_NOR0
13977 {1, 32}, // CRBITRC
13978 {1, 32}, // F4RC
13979 {0, 0}, // GPRC32
13980 {4, 32}, // CRRC
13981 {1, 1}, // CARRYRC
13982 {0, 0}, // CTRRC
13983 {0, 0}, // LRRC
13984 {1, 1}, // VRSAVERC
13985 {1, 68}, // SPILLTOVSRRC
13986 {1, 64}, // VSFRC
13987 {1, 34}, // G8RC
13988 {1, 34}, // G8RC_NOX0
13989 {1, 34}, // SPILLTOVSRRC_and_VSFRC
13990 {1, 33}, // G8RC_and_G8RC_NOX0
13991 {1, 32}, // F8RC
13992 {0, 0}, // FHRC
13993 {1, 32}, // SPERC
13994 {0, 0}, // VFHRC
13995 {1, 32}, // VFRC
13996 {1, 31}, // SPERC_with_sub_32_in_GPRC_NOR0
13997 {1, 20}, // SPILLTOVSRRC_and_VFRC
13998 {1, 14}, // SPILLTOVSRRC_and_F4RC
13999 {0, 0}, // CTRRC8
14000 {0, 0}, // LR8RC
14001 {1, 64}, // DMRROWRC
14002 {1, 64}, // VSRC
14003 {1, 34}, // VSRC_with_sub_64_in_SPILLTOVSRRC
14004 {1, 32}, // VRRC
14005 {1, 32}, // VSLRC
14006 {1, 20}, // VRRC_with_sub_64_in_SPILLTOVSRRC
14007 {2, 32}, // FpRC
14008 {2, 32}, // G8pRC
14009 {2, 30}, // G8pRC_with_sub_32_in_GPRC_NOR0
14010 {1, 14}, // VSLRC_with_sub_64_in_SPILLTOVSRRC
14011 {2, 14}, // FpRC_with_sub_fp0_in_SPILLTOVSRRC
14012 {2, 64}, // DMRROWpRC
14013 {2, 64}, // VSRpRC
14014 {2, 34}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC
14015 {2, 32}, // VSRpRC_with_sub_64_in_F4RC
14016 {2, 32}, // VSRpRC_with_sub_64_in_VFRC
14017 {2, 20}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
14018 {2, 14}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
14019 {4, 32}, // ACCRC
14020 {4, 32}, // UACCRC
14021 {4, 32}, // WACCRC
14022 {4, 32}, // WACC_HIRC
14023 {4, 16}, // ACCRC_with_sub_64_in_SPILLTOVSRRC
14024 {4, 16}, // UACCRC_with_sub_64_in_SPILLTOVSRRC
14025 {4, 12}, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
14026 {4, 12}, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
14027 {8, 64}, // DMRRC
14028 {16, 64}, // DMRpRC
14029 };
14030 return RCWeightTable[RC->getID()];
14031}
14032
14033/// Get the weight in units of pressure for this register unit.
14034unsigned PPCGenRegisterInfo::
14035getRegUnitWeight(unsigned RegUnit) const {
14036 assert(RegUnit < 329 && "invalid register unit");
14037 // All register units have unit weight.
14038 return 1;
14039}
14040
14041
14042// Get the number of dimensions of register pressure.
14043unsigned PPCGenRegisterInfo::getNumRegPressureSets() const {
14044 return 20;
14045}
14046
14047// Get the name of this register unit pressure set.
14048const char *PPCGenRegisterInfo::
14049getRegPressureSetName(unsigned Idx) const {
14050 static const char *PressureNameTable[] = {
14051 "CARRYRC",
14052 "VRSAVERC",
14053 "SPILLTOVSRRC_and_F4RC",
14054 "SPILLTOVSRRC_and_VFRC",
14055 "CRBITRC",
14056 "F4RC",
14057 "VFRC",
14058 "WACCRC",
14059 "WACC_HIRC",
14060 "GPRC",
14061 "SPILLTOVSRRC_and_VSFRC",
14062 "SPILLTOVSRRC_and_VSFRC_with_VFRC",
14063 "F4RC_with_SPILLTOVSRRC_and_VSFRC",
14064 "VSSRC",
14065 "DMRROWRC",
14066 "SPILLTOVSRRC",
14067 "SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC",
14068 "SPILLTOVSRRC_with_VFRC",
14069 "F4RC_with_SPILLTOVSRRC",
14070 "VSSRC_with_SPILLTOVSRRC",
14071 };
14072 return PressureNameTable[Idx];
14073}
14074
14075// Get the register unit pressure limit for this dimension.
14076// This limit must be adjusted dynamically for reserved registers.
14077unsigned PPCGenRegisterInfo::
14078getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
14079 static const uint8_t PressureLimitTable[] = {
14080 1, // 0: CARRYRC
14081 1, // 1: VRSAVERC
14082 16, // 2: SPILLTOVSRRC_and_F4RC
14083 20, // 3: SPILLTOVSRRC_and_VFRC
14084 32, // 4: CRBITRC
14085 32, // 5: F4RC
14086 32, // 6: VFRC
14087 32, // 7: WACCRC
14088 32, // 8: WACC_HIRC
14089 35, // 9: GPRC
14090 36, // 10: SPILLTOVSRRC_and_VSFRC
14091 46, // 11: SPILLTOVSRRC_and_VSFRC_with_VFRC
14092 52, // 12: F4RC_with_SPILLTOVSRRC_and_VSFRC
14093 64, // 13: VSSRC
14094 64, // 14: DMRROWRC
14095 69, // 15: SPILLTOVSRRC
14096 70, // 16: SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC
14097 80, // 17: SPILLTOVSRRC_with_VFRC
14098 86, // 18: F4RC_with_SPILLTOVSRRC
14099 98, // 19: VSSRC_with_SPILLTOVSRRC
14100 };
14101 return PressureLimitTable[Idx];
14102}
14103
14104/// Table of pressure sets per register class or unit.
14105static const int RCSetsTable[] = {
14106 /* 0 */ 0, -1,
14107 /* 2 */ 1, -1,
14108 /* 4 */ 4, -1,
14109 /* 6 */ 7, 14, -1,
14110 /* 9 */ 8, 14, -1,
14111 /* 12 */ 9, 15, -1,
14112 /* 15 */ 13, 19, -1,
14113 /* 18 */ 6, 11, 13, 17, 19, -1,
14114 /* 24 */ 5, 12, 13, 18, 19, -1,
14115 /* 30 */ 2, 5, 10, 12, 13, 16, 18, 19, -1,
14116 /* 39 */ 9, 15, 16, 17, 18, 19, -1,
14117 /* 46 */ 2, 5, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
14118 /* 58 */ 3, 6, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
14119};
14120
14121/// Get the dimensions of register pressure impacted by this register class.
14122/// Returns a -1 terminated array of pressure set IDs
14123const int *PPCGenRegisterInfo::
14124getRegClassPressureSets(const TargetRegisterClass *RC) const {
14125 static const uint8_t RCSetStartTable[] = {
14126 15,39,12,39,4,24,1,4,0,1,1,2,40,15,39,12,48,39,24,1,39,1,18,39,58,46,1,1,7,15,48,18,24,58,24,39,39,46,46,7,15,48,24,18,58,46,24,24,6,9,30,30,46,46,7,7,};
14127 return &RCSetsTable[RCSetStartTable[RC->getID()]];
14128}
14129
14130/// Get the dimensions of register pressure impacted by this register unit.
14131/// Returns a -1 terminated array of pressure set IDs
14132const int *PPCGenRegisterInfo::
14133getRegUnitPressureSets(unsigned RegUnit) const {
14134 assert(RegUnit < 329 && "invalid register unit");
14135 static const uint8_t RUSetStartTable[] = {
14136 39,0,1,39,1,1,1,2,12,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,46,1,30,1,30,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,24,1,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,58,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
14137 return &RCSetsTable[RUSetStartTable[RegUnit]];
14138}
14139
14140extern const MCRegisterDesc PPCRegDesc[];
14141extern const int16_t PPCRegDiffLists[];
14142extern const LaneBitmask PPCLaneMaskLists[];
14143extern const char PPCRegStrings[];
14144extern const char PPCRegClassStrings[];
14145extern const MCPhysReg PPCRegUnitRoots[][2];
14146extern const uint16_t PPCSubRegIdxLists[];
14147extern const uint16_t PPCRegEncodingTable[];
14148// PPC Dwarf<->LLVM register mappings.
14149extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[];
14150extern const unsigned PPCDwarfFlavour0Dwarf2LSize;
14151
14152extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[];
14153extern const unsigned PPCDwarfFlavour1Dwarf2LSize;
14154
14155extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[];
14156extern const unsigned PPCEHFlavour0Dwarf2LSize;
14157
14158extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[];
14159extern const unsigned PPCEHFlavour1Dwarf2LSize;
14160
14161extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[];
14162extern const unsigned PPCDwarfFlavour0L2DwarfSize;
14163
14164extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[];
14165extern const unsigned PPCDwarfFlavour1L2DwarfSize;
14166
14167extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[];
14168extern const unsigned PPCEHFlavour0L2DwarfSize;
14169
14170extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[];
14171extern const unsigned PPCEHFlavour1L2DwarfSize;
14172
14173PPCGenRegisterInfo::
14174PPCGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
14175 unsigned PC, unsigned HwMode)
14176 : TargetRegisterInfo(&PPCRegInfoDesc, RegisterClasses, RegisterClasses+56,
14177 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
14178 LaneBitmask(0xFFFFFFFE00000002), RegClassInfos, VTLists, HwMode) {
14179 InitMCRegisterInfo(PPCRegDesc, 612, RA, PC,
14180 PPCMCRegisterClasses, 56,
14181 PPCRegUnitRoots,
14182 329,
14183 PPCRegDiffLists,
14184 PPCLaneMaskLists,
14185 PPCRegStrings,
14186 PPCRegClassStrings,
14187 PPCSubRegIdxLists,
14188 56,
14189 PPCRegEncodingTable);
14190
14191 switch (DwarfFlavour) {
14192 default:
14193 llvm_unreachable("Unknown DWARF flavour");
14194 case 0:
14195 mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
14196 break;
14197 case 1:
14198 mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
14199 break;
14200 }
14201 switch (EHFlavour) {
14202 default:
14203 llvm_unreachable("Unknown DWARF flavour");
14204 case 0:
14205 mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
14206 break;
14207 case 1:
14208 mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
14209 break;
14210 }
14211 switch (DwarfFlavour) {
14212 default:
14213 llvm_unreachable("Unknown DWARF flavour");
14214 case 0:
14215 mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
14216 break;
14217 case 1:
14218 mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
14219 break;
14220 }
14221 switch (EHFlavour) {
14222 default:
14223 llvm_unreachable("Unknown DWARF flavour");
14224 case 0:
14225 mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
14226 break;
14227 case 1:
14228 mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
14229 break;
14230 }
14231}
14232
14233static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
14234static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14235static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 0 };
14236static const uint32_t CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0x007ffff8, 0x007ffff8, 0x007ffff8, 0x00000000, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14237static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 0 };
14238static const uint32_t CSR_64_AllRegs_AIX_Dflt_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x1fffffff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0x007fffff, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14239static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14240static const uint32_t CSR_64_AllRegs_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14241static const MCPhysReg CSR_64_AllRegs_VSRP_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14242static const uint32_t CSR_64_AllRegs_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14243static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 };
14244static const uint32_t CSR_64_AllRegs_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14245static const MCPhysReg CSR_AIX32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
14246static const uint32_t CSR_AIX32_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07ffff00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14247static const MCPhysReg CSR_AIX32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14248static const uint32_t CSR_AIX32_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07ffff00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14249static const MCPhysReg CSR_AIX32_VSRP_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14250static const uint32_t CSR_AIX32_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07ffff00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14251static const MCPhysReg CSR_AIX64_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
14252static const uint32_t CSR_AIX64_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14253static const MCPhysReg CSR_AIX64_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14254static const uint32_t CSR_AIX64_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14255static const MCPhysReg CSR_ALL_VSRP_SaveList[] = { PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14256static const uint32_t CSR_ALL_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14257static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14258static const uint32_t CSR_Altivec_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14259static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
14260static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14261static const MCPhysReg CSR_PPC64_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
14262static const uint32_t CSR_PPC64_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14263static const MCPhysReg CSR_PPC64_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14264static const uint32_t CSR_PPC64_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14265static const MCPhysReg CSR_PPC64_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
14266static const uint32_t CSR_PPC64_R2_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14267static const MCPhysReg CSR_PPC64_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
14268static const uint32_t CSR_PPC64_R2_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14269static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
14270static const uint32_t CSR_SPE_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffff00, 0x03fffe00, 0x03fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14271static const MCPhysReg CSR_SPE_NO_S30_31_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
14272static const uint32_t CSR_SPE_NO_S30_31_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ffff00, 0x01fffe00, 0x01fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14273static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
14274static const uint32_t CSR_SVR32_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14275static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14276static const uint32_t CSR_SVR32_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14277static const MCPhysReg CSR_SVR32_ColdCC_Common_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
14278static const uint32_t CSR_SVR32_ColdCC_Common_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14279static const MCPhysReg CSR_SVR32_ColdCC_SPE_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
14280static const uint32_t CSR_SVR32_ColdCC_SPE_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0x83ffff1f, 0x87fffe3f, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14281static const MCPhysReg CSR_SVR32_ColdCC_VSRP_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14282static const uint32_t CSR_SVR32_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0xffffffff, 0xffefffff, 0x00000007, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14283static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
14284static const uint32_t CSR_SVR64_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
14285static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14286static const uint32_t CSR_SVR64_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
14287static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 };
14288static const uint32_t CSR_SVR64_ColdCC_R2_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0xa0000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
14289static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
14290static const uint32_t CSR_SVR64_ColdCC_R2_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0xa0000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
14291static const MCPhysReg CSR_SVR64_ColdCC_R2_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
14292static const uint32_t CSR_SVR64_ColdCC_R2_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0xa0000000, 0x07fffe3f, 0x00000000, 0xffffff98, 0xffffff9f, 0xffffff9f, 0xffffffff, 0xffefffff, 0x00000007, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
14293static const MCPhysReg CSR_SVR64_ColdCC_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14294static const uint32_t CSR_SVR64_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffff98, 0xffffff9f, 0xffffff9f, 0xffffffff, 0xffefffff, 0x00000007, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
14295static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
14296static const uint32_t CSR_SVR432_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14297static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14298static const uint32_t CSR_SVR432_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14299static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
14300static const uint32_t CSR_SVR432_COMM_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14301static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
14302static const uint32_t CSR_SVR432_SPE_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffff00, 0x07fffe00, 0x03fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14303static const MCPhysReg CSR_SVR432_SPE_NO_S30_31_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
14304static const uint32_t CSR_SVR432_SPE_NO_S30_31_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ffff00, 0x07fffe00, 0x01fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14305static const MCPhysReg CSR_SVR432_VSRP_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14306static const uint32_t CSR_SVR432_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14307static const MCPhysReg CSR_SVR464_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
14308static const uint32_t CSR_SVR464_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14309static const MCPhysReg CSR_SVR464_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14310static const uint32_t CSR_SVR464_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14311static const MCPhysReg CSR_VSRP_SaveList[] = { PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14312static const uint32_t CSR_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14313
14314
14315ArrayRef<const uint32_t *> PPCGenRegisterInfo::getRegMasks() const {
14316 static const uint32_t *const Masks[] = {
14317 CSR_64_AllRegs_RegMask,
14318 CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask,
14319 CSR_64_AllRegs_AIX_Dflt_VSX_RegMask,
14320 CSR_64_AllRegs_Altivec_RegMask,
14321 CSR_64_AllRegs_VSRP_RegMask,
14322 CSR_64_AllRegs_VSX_RegMask,
14323 CSR_AIX32_RegMask,
14324 CSR_AIX32_Altivec_RegMask,
14325 CSR_AIX32_VSRP_RegMask,
14326 CSR_AIX64_R2_VSRP_RegMask,
14327 CSR_AIX64_VSRP_RegMask,
14328 CSR_ALL_VSRP_RegMask,
14329 CSR_Altivec_RegMask,
14330 CSR_NoRegs_RegMask,
14331 CSR_PPC64_RegMask,
14332 CSR_PPC64_Altivec_RegMask,
14333 CSR_PPC64_R2_RegMask,
14334 CSR_PPC64_R2_Altivec_RegMask,
14335 CSR_SPE_RegMask,
14336 CSR_SPE_NO_S30_31_RegMask,
14337 CSR_SVR32_ColdCC_RegMask,
14338 CSR_SVR32_ColdCC_Altivec_RegMask,
14339 CSR_SVR32_ColdCC_Common_RegMask,
14340 CSR_SVR32_ColdCC_SPE_RegMask,
14341 CSR_SVR32_ColdCC_VSRP_RegMask,
14342 CSR_SVR64_ColdCC_RegMask,
14343 CSR_SVR64_ColdCC_Altivec_RegMask,
14344 CSR_SVR64_ColdCC_R2_RegMask,
14345 CSR_SVR64_ColdCC_R2_Altivec_RegMask,
14346 CSR_SVR64_ColdCC_R2_VSRP_RegMask,
14347 CSR_SVR64_ColdCC_VSRP_RegMask,
14348 CSR_SVR432_RegMask,
14349 CSR_SVR432_Altivec_RegMask,
14350 CSR_SVR432_COMM_RegMask,
14351 CSR_SVR432_SPE_RegMask,
14352 CSR_SVR432_SPE_NO_S30_31_RegMask,
14353 CSR_SVR432_VSRP_RegMask,
14354 CSR_SVR464_R2_VSRP_RegMask,
14355 CSR_SVR464_VSRP_RegMask,
14356 CSR_VSRP_RegMask,
14357 };
14358 return ArrayRef(Masks);
14359}
14360
14361bool PPCGenRegisterInfo::
14362isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14363 return
14364 false;
14365}
14366
14367bool PPCGenRegisterInfo::
14368isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14369 return
14370 false;
14371}
14372
14373bool PPCGenRegisterInfo::
14374isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14375 return
14376 false;
14377}
14378
14379bool PPCGenRegisterInfo::
14380isConstantPhysReg(MCRegister PhysReg) const {
14381 return
14382 PhysReg == PPC::ZERO ||
14383 PhysReg == PPC::ZERO8 ||
14384 false;
14385}
14386
14387ArrayRef<const char *> PPCGenRegisterInfo::getRegMaskNames() const {
14388 static const char *Names[] = {
14389 "CSR_64_AllRegs",
14390 "CSR_64_AllRegs_AIX_Dflt_Altivec",
14391 "CSR_64_AllRegs_AIX_Dflt_VSX",
14392 "CSR_64_AllRegs_Altivec",
14393 "CSR_64_AllRegs_VSRP",
14394 "CSR_64_AllRegs_VSX",
14395 "CSR_AIX32",
14396 "CSR_AIX32_Altivec",
14397 "CSR_AIX32_VSRP",
14398 "CSR_AIX64_R2_VSRP",
14399 "CSR_AIX64_VSRP",
14400 "CSR_ALL_VSRP",
14401 "CSR_Altivec",
14402 "CSR_NoRegs",
14403 "CSR_PPC64",
14404 "CSR_PPC64_Altivec",
14405 "CSR_PPC64_R2",
14406 "CSR_PPC64_R2_Altivec",
14407 "CSR_SPE",
14408 "CSR_SPE_NO_S30_31",
14409 "CSR_SVR32_ColdCC",
14410 "CSR_SVR32_ColdCC_Altivec",
14411 "CSR_SVR32_ColdCC_Common",
14412 "CSR_SVR32_ColdCC_SPE",
14413 "CSR_SVR32_ColdCC_VSRP",
14414 "CSR_SVR64_ColdCC",
14415 "CSR_SVR64_ColdCC_Altivec",
14416 "CSR_SVR64_ColdCC_R2",
14417 "CSR_SVR64_ColdCC_R2_Altivec",
14418 "CSR_SVR64_ColdCC_R2_VSRP",
14419 "CSR_SVR64_ColdCC_VSRP",
14420 "CSR_SVR432",
14421 "CSR_SVR432_Altivec",
14422 "CSR_SVR432_COMM",
14423 "CSR_SVR432_SPE",
14424 "CSR_SVR432_SPE_NO_S30_31",
14425 "CSR_SVR432_VSRP",
14426 "CSR_SVR464_R2_VSRP",
14427 "CSR_SVR464_VSRP",
14428 "CSR_VSRP",
14429 };
14430 return ArrayRef(Names);
14431}
14432
14433const PPCFrameLowering *
14434PPCGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
14435 return static_cast<const PPCFrameLowering *>(
14436 MF.getSubtarget().getFrameLowering());
14437}
14438
14439} // end namespace llvm
14440
14441#endif // GET_REGINFO_TARGET_DESC
14442
14443