1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Compress instruction Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: RISCV.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GEN_COMPRESS_INSTR
12#undef GEN_COMPRESS_INSTR
13
14static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp,
15 const MCSubtargetInfo &STI,
16 unsigned PredicateIndex) {
17 switch (PredicateIndex) {
18 default:
19 llvm_unreachable("Unknown MCOperandPredicate kind");
20 break;
21 case 1: {
22 // uimm10_lsb00nonzero
23
24 int64_t Imm;
25 if (!MCOp.evaluateAsConstantImm(Imm))
26 return false;
27 return isShiftedUInt<8, 2>(x: Imm) && (Imm != 0);
28
29 }
30 case 2: {
31 // simm6nonzero
32
33 int64_t Imm;
34 if (MCOp.evaluateAsConstantImm(Imm))
35 return (Imm != 0) && isInt<6>(x: Imm);
36 return MCOp.isBareSymbolRef();
37
38 }
39 case 3: {
40 // simm6
41
42 int64_t Imm;
43 if (MCOp.evaluateAsConstantImm(Imm))
44 return isInt<6>(x: Imm);
45 return MCOp.isBareSymbolRef();
46
47 }
48 case 4: {
49 // simm10_lsb0000nonzero
50
51 int64_t Imm;
52 if (!MCOp.evaluateAsConstantImm(Imm))
53 return false;
54 return isShiftedInt<6, 4>(x: Imm) && (Imm != 0);
55
56 }
57 case 5: {
58 // simm9_lsb0
59
60 int64_t Imm;
61 if (MCOp.evaluateAsConstantImm(Imm))
62 return isShiftedInt<8, 1>(x: Imm);
63 return MCOp.isBareSymbolRef();
64
65
66 }
67 case 6: {
68 // uimm8_lsb000
69
70 int64_t Imm;
71 if (!MCOp.evaluateAsConstantImm(Imm))
72 return false;
73 return isShiftedUInt<5, 3>(x: Imm);
74
75 }
76 case 7: {
77 // uimm9_lsb000
78
79 int64_t Imm;
80 if (!MCOp.evaluateAsConstantImm(Imm))
81 return false;
82 return isShiftedUInt<6, 3>(x: Imm);
83
84 }
85 case 8: {
86 // uimm7_lsb00
87
88 int64_t Imm;
89 if (!MCOp.evaluateAsConstantImm(Imm))
90 return false;
91 return isShiftedUInt<5, 2>(x: Imm);
92
93 }
94 case 9: {
95 // uimm8_lsb00
96
97 int64_t Imm;
98 if (!MCOp.evaluateAsConstantImm(Imm))
99 return false;
100 return isShiftedUInt<6, 2>(x: Imm);
101
102 }
103 case 10: {
104 // simm12_lsb0
105
106 int64_t Imm;
107 if (MCOp.evaluateAsConstantImm(Imm))
108 return isShiftedInt<11, 1>(x: Imm);
109 return MCOp.isBareSymbolRef();
110
111 }
112 case 11: {
113 // uimm2
114
115 int64_t Imm;
116 if (!MCOp.evaluateAsConstantImm(Imm))
117 return false;
118 return isUInt<2>(x: Imm);
119
120 }
121 case 12: {
122 // uimm5_with_predicate
123
124 int64_t Imm;
125 if (!MCOp.evaluateAsConstantImm(Imm))
126 return false;
127 return isUInt<5>(x: Imm);
128
129 }
130 case 13: {
131 // uimm4_with_predicate
132
133 int64_t Imm;
134 if (!MCOp.evaluateAsConstantImm(Imm))
135 return false;
136 return isUInt<4>(x: Imm);
137
138 }
139 case 14: {
140 // uimm2_lsb0
141
142 int64_t Imm;
143 if (!MCOp.evaluateAsConstantImm(Imm))
144 return false;
145 return isShiftedUInt<1, 1>(x: Imm);
146
147 }
148 case 15: {
149 // uimm6_lsb0
150
151 int64_t Imm;
152 if (!MCOp.evaluateAsConstantImm(Imm))
153 return false;
154 return isShiftedUInt<5, 1>(x: Imm);
155
156 }
157 case 16: {
158 // uimm5_lsb0
159
160 int64_t Imm;
161 if (!MCOp.evaluateAsConstantImm(Imm))
162 return false;
163 return isShiftedUInt<4, 1>(x: Imm);
164
165 }
166 case 17: {
167 // c_lui_imm
168
169 int64_t Imm;
170 if (MCOp.evaluateAsConstantImm(Imm))
171 return (Imm != 0) && (isUInt<5>(x: Imm) ||
172 (Imm >= 0xfffe0 && Imm <= 0xfffff));
173 return MCOp.isBareSymbolRef();
174
175 }
176 case 18: {
177 // uimmlog2xlennonzero
178
179 int64_t Imm;
180 if (!MCOp.evaluateAsConstantImm(Imm))
181 return false;
182 if (STI.getTargetTriple().isArch64Bit())
183 return isUInt<6>(x: Imm) && (Imm != 0);
184 return isUInt<5>(x: Imm) && (Imm != 0);
185
186 }
187 }
188}
189
190static bool compressInst(MCInst &OutInst,
191 const MCInst &MI,
192 const MCSubtargetInfo &STI) {
193 switch (MI.getOpcode()) {
194 default: return false;
195 case RISCV::ADD: {
196 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
197 (MI.getOperand(i: 1).isReg()) &&
198 (MI.getOperand(i: 1).getReg() == RISCV::X0) &&
199 (MI.getOperand(i: 0).isReg()) &&
200 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
201 (MI.getOperand(i: 2).isReg()) &&
202 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
203 // c.mv $rs1, $rs2
204 OutInst.setOpcode(RISCV::C_MV);
205 // Operand: rs1
206 OutInst.addOperand(Op: MI.getOperand(i: 0));
207 // Operand: rs2
208 OutInst.addOperand(Op: MI.getOperand(i: 2));
209 OutInst.setLoc(MI.getLoc());
210 return true;
211 } // if
212 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
213 (MI.getOperand(i: 2).isReg()) &&
214 (MI.getOperand(i: 2).getReg() == RISCV::X0) &&
215 (MI.getOperand(i: 0).isReg()) &&
216 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
217 (MI.getOperand(i: 1).isReg()) &&
218 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
219 // c.mv $rs1, $rs2
220 OutInst.setOpcode(RISCV::C_MV);
221 // Operand: rs1
222 OutInst.addOperand(Op: MI.getOperand(i: 0));
223 // Operand: rs2
224 OutInst.addOperand(Op: MI.getOperand(i: 1));
225 OutInst.setLoc(MI.getLoc());
226 return true;
227 } // if
228 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
229 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
230 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
231 (MI.getOperand(i: 1).isReg()) &&
232 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
233 (MI.getOperand(i: 2).isReg()) &&
234 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
235 // c.add $rs1, $rs2
236 OutInst.setOpcode(RISCV::C_ADD);
237 // Operand: rs1_wb
238 OutInst.addOperand(Op: MI.getOperand(i: 1));
239 // Operand: rs1
240 OutInst.addOperand(Op: MI.getOperand(i: 1));
241 // Operand: rs2
242 OutInst.addOperand(Op: MI.getOperand(i: 2));
243 OutInst.setLoc(MI.getLoc());
244 return true;
245 } // if
246 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
247 (MI.getOperand(i: 2).isReg()) && (MI.getOperand(i: 0).isReg()) &&
248 (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) &&
249 (MI.getOperand(i: 2).isReg()) &&
250 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 2).getReg())) &&
251 (MI.getOperand(i: 1).isReg()) &&
252 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
253 // c.add $rs1, $rs2
254 OutInst.setOpcode(RISCV::C_ADD);
255 // Operand: rs1_wb
256 OutInst.addOperand(Op: MI.getOperand(i: 2));
257 // Operand: rs1
258 OutInst.addOperand(Op: MI.getOperand(i: 2));
259 // Operand: rs2
260 OutInst.addOperand(Op: MI.getOperand(i: 1));
261 OutInst.setLoc(MI.getLoc());
262 return true;
263 } // if
264 break;
265 } // case ADD
266 case RISCV::ADDI: {
267 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
268 (MI.getOperand(i: 0).isReg()) &&
269 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
270 (MI.getOperand(i: 1).isReg()) &&
271 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
272 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
273 // c.addi4spn $rd, $rs1, $imm
274 OutInst.setOpcode(RISCV::C_ADDI4SPN);
275 // Operand: rd
276 OutInst.addOperand(Op: MI.getOperand(i: 0));
277 // Operand: rs1
278 OutInst.addOperand(Op: MI.getOperand(i: 1));
279 // Operand: imm
280 OutInst.addOperand(Op: MI.getOperand(i: 2));
281 OutInst.setLoc(MI.getLoc());
282 return true;
283 } // if
284 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
285 (MI.getOperand(i: 0).isReg()) &&
286 (MI.getOperand(i: 0).getReg() == RISCV::X0) &&
287 (MI.getOperand(i: 1).isReg()) &&
288 (MI.getOperand(i: 1).getReg() == RISCV::X0) &&
289 (MI.getOperand(i: 2).isImm()) &&
290 (MI.getOperand(i: 2).getImm() == 0)) {
291 // c.nop
292 OutInst.setOpcode(RISCV::C_NOP);
293 OutInst.setLoc(MI.getLoc());
294 return true;
295 } // if
296 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
297 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
298 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
299 (MI.getOperand(i: 1).isReg()) &&
300 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
301 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 2)) {
302 // c.addi $rd, $imm
303 OutInst.setOpcode(RISCV::C_ADDI);
304 // Operand: rd_wb
305 OutInst.addOperand(Op: MI.getOperand(i: 1));
306 // Operand: rd
307 OutInst.addOperand(Op: MI.getOperand(i: 1));
308 // Operand: imm
309 OutInst.addOperand(Op: MI.getOperand(i: 2));
310 OutInst.setLoc(MI.getLoc());
311 return true;
312 } // if
313 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
314 (MI.getOperand(i: 1).isReg()) &&
315 (MI.getOperand(i: 1).getReg() == RISCV::X0) &&
316 (MI.getOperand(i: 0).isReg()) &&
317 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
318 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3)) {
319 // c.li $rd, $imm
320 OutInst.setOpcode(RISCV::C_LI);
321 // Operand: rd
322 OutInst.addOperand(Op: MI.getOperand(i: 0));
323 // Operand: imm
324 OutInst.addOperand(Op: MI.getOperand(i: 2));
325 OutInst.setLoc(MI.getLoc());
326 return true;
327 } // if
328 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
329 (MI.getOperand(i: 0).isReg()) &&
330 (MI.getOperand(i: 0).getReg() == RISCV::X2) &&
331 (MI.getOperand(i: 1).isReg()) &&
332 (MI.getOperand(i: 1).getReg() == RISCV::X2) &&
333 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 4)) {
334 // c.addi16sp $rd, $imm
335 OutInst.setOpcode(RISCV::C_ADDI16SP);
336 // Operand: rd_wb
337 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
338 // Operand: rd
339 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
340 // Operand: imm
341 OutInst.addOperand(Op: MI.getOperand(i: 2));
342 OutInst.setLoc(MI.getLoc());
343 return true;
344 } // if
345 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
346 (MI.getOperand(i: 2).isImm()) &&
347 (MI.getOperand(i: 2).getImm() == 0) &&
348 (MI.getOperand(i: 0).isReg()) &&
349 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
350 (MI.getOperand(i: 1).isReg()) &&
351 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
352 // c.mv $rs1, $rs2
353 OutInst.setOpcode(RISCV::C_MV);
354 // Operand: rs1
355 OutInst.addOperand(Op: MI.getOperand(i: 0));
356 // Operand: rs2
357 OutInst.addOperand(Op: MI.getOperand(i: 1));
358 OutInst.setLoc(MI.getLoc());
359 return true;
360 } // if
361 break;
362 } // case ADDI
363 case RISCV::ADDIW: {
364 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
365 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
366 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
367 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
368 (MI.getOperand(i: 1).isReg()) &&
369 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
370 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3)) {
371 // c.addiw $rd, $imm
372 OutInst.setOpcode(RISCV::C_ADDIW);
373 // Operand: rd_wb
374 OutInst.addOperand(Op: MI.getOperand(i: 1));
375 // Operand: rd
376 OutInst.addOperand(Op: MI.getOperand(i: 1));
377 // Operand: imm
378 OutInst.addOperand(Op: MI.getOperand(i: 2));
379 OutInst.setLoc(MI.getLoc());
380 return true;
381 } // if
382 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
383 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
384 (MI.getOperand(i: 1).isReg()) &&
385 (MI.getOperand(i: 1).getReg() == RISCV::X0) &&
386 (MI.getOperand(i: 0).isReg()) &&
387 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
388 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3)) {
389 // c.li $rd, $imm
390 OutInst.setOpcode(RISCV::C_LI);
391 // Operand: rd
392 OutInst.addOperand(Op: MI.getOperand(i: 0));
393 // Operand: imm
394 OutInst.addOperand(Op: MI.getOperand(i: 2));
395 OutInst.setLoc(MI.getLoc());
396 return true;
397 } // if
398 break;
399 } // case ADDIW
400 case RISCV::ADDW: {
401 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
402 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
403 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
404 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
405 (MI.getOperand(i: 1).isReg()) &&
406 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
407 (MI.getOperand(i: 2).isReg()) &&
408 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
409 // c.addw $rd, $rs2
410 OutInst.setOpcode(RISCV::C_ADDW);
411 // Operand: rd_wb
412 OutInst.addOperand(Op: MI.getOperand(i: 1));
413 // Operand: rd
414 OutInst.addOperand(Op: MI.getOperand(i: 1));
415 // Operand: rs2
416 OutInst.addOperand(Op: MI.getOperand(i: 2));
417 OutInst.setLoc(MI.getLoc());
418 return true;
419 } // if
420 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
421 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
422 (MI.getOperand(i: 2).isReg()) && (MI.getOperand(i: 0).isReg()) &&
423 (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) &&
424 (MI.getOperand(i: 2).isReg()) &&
425 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg())) &&
426 (MI.getOperand(i: 1).isReg()) &&
427 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
428 // c.addw $rd, $rs2
429 OutInst.setOpcode(RISCV::C_ADDW);
430 // Operand: rd_wb
431 OutInst.addOperand(Op: MI.getOperand(i: 2));
432 // Operand: rd
433 OutInst.addOperand(Op: MI.getOperand(i: 2));
434 // Operand: rs2
435 OutInst.addOperand(Op: MI.getOperand(i: 1));
436 OutInst.setLoc(MI.getLoc());
437 return true;
438 } // if
439 break;
440 } // case ADDW
441 case RISCV::ADD_UW: {
442 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
443 STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
444 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
445 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
446 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
447 (MI.getOperand(i: 2).isReg()) &&
448 (MI.getOperand(i: 2).getReg() == RISCV::X0) &&
449 (MI.getOperand(i: 1).isReg()) &&
450 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
451 // c.zext.w $rd
452 OutInst.setOpcode(RISCV::C_ZEXT_W);
453 // Operand: rd_wb
454 OutInst.addOperand(Op: MI.getOperand(i: 1));
455 // Operand: rd
456 OutInst.addOperand(Op: MI.getOperand(i: 1));
457 OutInst.setLoc(MI.getLoc());
458 return true;
459 } // if
460 break;
461 } // case ADD_UW
462 case RISCV::AND: {
463 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
464 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
465 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
466 (MI.getOperand(i: 1).isReg()) &&
467 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
468 (MI.getOperand(i: 2).isReg()) &&
469 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
470 // c.and $rd, $rs2
471 OutInst.setOpcode(RISCV::C_AND);
472 // Operand: rd_wb
473 OutInst.addOperand(Op: MI.getOperand(i: 1));
474 // Operand: rd
475 OutInst.addOperand(Op: MI.getOperand(i: 1));
476 // Operand: rs2
477 OutInst.addOperand(Op: MI.getOperand(i: 2));
478 OutInst.setLoc(MI.getLoc());
479 return true;
480 } // if
481 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
482 (MI.getOperand(i: 2).isReg()) && (MI.getOperand(i: 0).isReg()) &&
483 (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) &&
484 (MI.getOperand(i: 2).isReg()) &&
485 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg())) &&
486 (MI.getOperand(i: 1).isReg()) &&
487 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
488 // c.and $rd, $rs2
489 OutInst.setOpcode(RISCV::C_AND);
490 // Operand: rd_wb
491 OutInst.addOperand(Op: MI.getOperand(i: 2));
492 // Operand: rd
493 OutInst.addOperand(Op: MI.getOperand(i: 2));
494 // Operand: rs2
495 OutInst.addOperand(Op: MI.getOperand(i: 1));
496 OutInst.setLoc(MI.getLoc());
497 return true;
498 } // if
499 break;
500 } // case AND
501 case RISCV::ANDI: {
502 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
503 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
504 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
505 (MI.getOperand(i: 1).isReg()) &&
506 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
507 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 3)) {
508 // c.andi $rs1, $imm
509 OutInst.setOpcode(RISCV::C_ANDI);
510 // Operand: rs1_wb
511 OutInst.addOperand(Op: MI.getOperand(i: 1));
512 // Operand: rs1
513 OutInst.addOperand(Op: MI.getOperand(i: 1));
514 // Operand: imm
515 OutInst.addOperand(Op: MI.getOperand(i: 2));
516 OutInst.setLoc(MI.getLoc());
517 return true;
518 } // if
519 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
520 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
521 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
522 (MI.getOperand(i: 2).isImm()) &&
523 (MI.getOperand(i: 2).getImm() == 255) &&
524 (MI.getOperand(i: 1).isReg()) &&
525 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
526 // c.zext.b $rd
527 OutInst.setOpcode(RISCV::C_ZEXT_B);
528 // Operand: rd_wb
529 OutInst.addOperand(Op: MI.getOperand(i: 1));
530 // Operand: rd
531 OutInst.addOperand(Op: MI.getOperand(i: 1));
532 OutInst.setLoc(MI.getLoc());
533 return true;
534 } // if
535 break;
536 } // case ANDI
537 case RISCV::BEQ: {
538 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
539 (MI.getOperand(i: 1).isReg()) &&
540 (MI.getOperand(i: 1).getReg() == RISCV::X0) &&
541 (MI.getOperand(i: 0).isReg()) &&
542 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
543 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
544 // c.beqz $rs1, $imm
545 OutInst.setOpcode(RISCV::C_BEQZ);
546 // Operand: rs1
547 OutInst.addOperand(Op: MI.getOperand(i: 0));
548 // Operand: imm
549 OutInst.addOperand(Op: MI.getOperand(i: 2));
550 OutInst.setLoc(MI.getLoc());
551 return true;
552 } // if
553 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
554 (MI.getOperand(i: 0).isReg()) &&
555 (MI.getOperand(i: 0).getReg() == RISCV::X0) &&
556 (MI.getOperand(i: 1).isReg()) &&
557 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
558 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
559 // c.beqz $rs1, $imm
560 OutInst.setOpcode(RISCV::C_BEQZ);
561 // Operand: rs1
562 OutInst.addOperand(Op: MI.getOperand(i: 1));
563 // Operand: imm
564 OutInst.addOperand(Op: MI.getOperand(i: 2));
565 OutInst.setLoc(MI.getLoc());
566 return true;
567 } // if
568 break;
569 } // case BEQ
570 case RISCV::BNE: {
571 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
572 (MI.getOperand(i: 1).isReg()) &&
573 (MI.getOperand(i: 1).getReg() == RISCV::X0) &&
574 (MI.getOperand(i: 0).isReg()) &&
575 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
576 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
577 // c.bnez $rs1, $imm
578 OutInst.setOpcode(RISCV::C_BNEZ);
579 // Operand: rs1
580 OutInst.addOperand(Op: MI.getOperand(i: 0));
581 // Operand: imm
582 OutInst.addOperand(Op: MI.getOperand(i: 2));
583 OutInst.setLoc(MI.getLoc());
584 return true;
585 } // if
586 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
587 (MI.getOperand(i: 0).isReg()) &&
588 (MI.getOperand(i: 0).getReg() == RISCV::X0) &&
589 (MI.getOperand(i: 1).isReg()) &&
590 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
591 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
592 // c.bnez $rs1, $imm
593 OutInst.setOpcode(RISCV::C_BNEZ);
594 // Operand: rs1
595 OutInst.addOperand(Op: MI.getOperand(i: 1));
596 // Operand: imm
597 OutInst.addOperand(Op: MI.getOperand(i: 2));
598 OutInst.setLoc(MI.getLoc());
599 return true;
600 } // if
601 break;
602 } // case BNE
603 case RISCV::EBREAK: {
604 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
605 // c.ebreak
606 OutInst.setOpcode(RISCV::C_EBREAK);
607 OutInst.setLoc(MI.getLoc());
608 return true;
609 } // if
610 break;
611 } // case EBREAK
612 case RISCV::FLD: {
613 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
614 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
615 (MI.getOperand(i: 0).isReg()) &&
616 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
617 (MI.getOperand(i: 1).isReg()) &&
618 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
619 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6)) {
620 // c.fld $rd, ${imm}(${rs1})
621 OutInst.setOpcode(RISCV::C_FLD);
622 // Operand: rd
623 OutInst.addOperand(Op: MI.getOperand(i: 0));
624 // Operand: rs1
625 OutInst.addOperand(Op: MI.getOperand(i: 1));
626 // Operand: imm
627 OutInst.addOperand(Op: MI.getOperand(i: 2));
628 OutInst.setLoc(MI.getLoc());
629 return true;
630 } // if
631 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
632 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
633 (MI.getOperand(i: 0).isReg()) &&
634 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
635 (MI.getOperand(i: 1).isReg()) &&
636 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
637 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7)) {
638 // c.fldsp $rd, ${imm}(${rs1})
639 OutInst.setOpcode(RISCV::C_FLDSP);
640 // Operand: rd
641 OutInst.addOperand(Op: MI.getOperand(i: 0));
642 // Operand: rs1
643 OutInst.addOperand(Op: MI.getOperand(i: 1));
644 // Operand: imm
645 OutInst.addOperand(Op: MI.getOperand(i: 2));
646 OutInst.setLoc(MI.getLoc());
647 return true;
648 } // if
649 break;
650 } // case FLD
651 case RISCV::FLW: {
652 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
653 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
654 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
655 (MI.getOperand(i: 0).isReg()) &&
656 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
657 (MI.getOperand(i: 1).isReg()) &&
658 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
659 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8)) {
660 // c.flw $rd, ${imm}(${rs1})
661 OutInst.setOpcode(RISCV::C_FLW);
662 // Operand: rd
663 OutInst.addOperand(Op: MI.getOperand(i: 0));
664 // Operand: rs1
665 OutInst.addOperand(Op: MI.getOperand(i: 1));
666 // Operand: imm
667 OutInst.addOperand(Op: MI.getOperand(i: 2));
668 OutInst.setLoc(MI.getLoc());
669 return true;
670 } // if
671 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
672 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
673 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
674 (MI.getOperand(i: 0).isReg()) &&
675 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
676 (MI.getOperand(i: 1).isReg()) &&
677 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
678 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9)) {
679 // c.flwsp $rd, ${imm}(${rs1})
680 OutInst.setOpcode(RISCV::C_FLWSP);
681 // Operand: rd
682 OutInst.addOperand(Op: MI.getOperand(i: 0));
683 // Operand: rs1
684 OutInst.addOperand(Op: MI.getOperand(i: 1));
685 // Operand: imm
686 OutInst.addOperand(Op: MI.getOperand(i: 2));
687 OutInst.setLoc(MI.getLoc());
688 return true;
689 } // if
690 break;
691 } // case FLW
692 case RISCV::FSD: {
693 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
694 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
695 (MI.getOperand(i: 0).isReg()) &&
696 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
697 (MI.getOperand(i: 1).isReg()) &&
698 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
699 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6)) {
700 // c.fsd $rs2, ${imm}(${rs1})
701 OutInst.setOpcode(RISCV::C_FSD);
702 // Operand: rs2
703 OutInst.addOperand(Op: MI.getOperand(i: 0));
704 // Operand: rs1
705 OutInst.addOperand(Op: MI.getOperand(i: 1));
706 // Operand: imm
707 OutInst.addOperand(Op: MI.getOperand(i: 2));
708 OutInst.setLoc(MI.getLoc());
709 return true;
710 } // if
711 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
712 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
713 (MI.getOperand(i: 0).isReg()) &&
714 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
715 (MI.getOperand(i: 1).isReg()) &&
716 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
717 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7)) {
718 // c.fsdsp $rs2, ${imm}(${rs1})
719 OutInst.setOpcode(RISCV::C_FSDSP);
720 // Operand: rs2
721 OutInst.addOperand(Op: MI.getOperand(i: 0));
722 // Operand: rs1
723 OutInst.addOperand(Op: MI.getOperand(i: 1));
724 // Operand: imm
725 OutInst.addOperand(Op: MI.getOperand(i: 2));
726 OutInst.setLoc(MI.getLoc());
727 return true;
728 } // if
729 break;
730 } // case FSD
731 case RISCV::FSW: {
732 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
733 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
734 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
735 (MI.getOperand(i: 0).isReg()) &&
736 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
737 (MI.getOperand(i: 1).isReg()) &&
738 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
739 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8)) {
740 // c.fsw $rs2, ${imm}(${rs1})
741 OutInst.setOpcode(RISCV::C_FSW);
742 // Operand: rs2
743 OutInst.addOperand(Op: MI.getOperand(i: 0));
744 // Operand: rs1
745 OutInst.addOperand(Op: MI.getOperand(i: 1));
746 // Operand: imm
747 OutInst.addOperand(Op: MI.getOperand(i: 2));
748 OutInst.setLoc(MI.getLoc());
749 return true;
750 } // if
751 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
752 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
753 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
754 (MI.getOperand(i: 0).isReg()) &&
755 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
756 (MI.getOperand(i: 1).isReg()) &&
757 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
758 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9)) {
759 // c.fswsp $rs2, ${imm}(${rs1})
760 OutInst.setOpcode(RISCV::C_FSWSP);
761 // Operand: rs2
762 OutInst.addOperand(Op: MI.getOperand(i: 0));
763 // Operand: rs1
764 OutInst.addOperand(Op: MI.getOperand(i: 1));
765 // Operand: imm
766 OutInst.addOperand(Op: MI.getOperand(i: 2));
767 OutInst.setLoc(MI.getLoc());
768 return true;
769 } // if
770 break;
771 } // case FSW
772 case RISCV::JAL: {
773 if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
774 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
775 (MI.getOperand(i: 0).isReg()) &&
776 (MI.getOperand(i: 0).getReg() == RISCV::X1) &&
777 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 10)) {
778 // c.jal $offset
779 OutInst.setOpcode(RISCV::C_JAL);
780 // Operand: offset
781 OutInst.addOperand(Op: MI.getOperand(i: 1));
782 OutInst.setLoc(MI.getLoc());
783 return true;
784 } // if
785 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
786 (MI.getOperand(i: 0).isReg()) &&
787 (MI.getOperand(i: 0).getReg() == RISCV::X0) &&
788 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 10)) {
789 // c.j $offset
790 OutInst.setOpcode(RISCV::C_J);
791 // Operand: offset
792 OutInst.addOperand(Op: MI.getOperand(i: 1));
793 OutInst.setLoc(MI.getLoc());
794 return true;
795 } // if
796 break;
797 } // case JAL
798 case RISCV::JALR: {
799 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
800 (MI.getOperand(i: 0).isReg()) &&
801 (MI.getOperand(i: 0).getReg() == RISCV::X0) &&
802 (MI.getOperand(i: 2).isImm()) &&
803 (MI.getOperand(i: 2).getImm() == 0) &&
804 (MI.getOperand(i: 1).isReg()) &&
805 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
806 // c.jr $rs1
807 OutInst.setOpcode(RISCV::C_JR);
808 // Operand: rs1
809 OutInst.addOperand(Op: MI.getOperand(i: 1));
810 OutInst.setLoc(MI.getLoc());
811 return true;
812 } // if
813 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
814 (MI.getOperand(i: 0).isReg()) &&
815 (MI.getOperand(i: 0).getReg() == RISCV::X1) &&
816 (MI.getOperand(i: 2).isImm()) &&
817 (MI.getOperand(i: 2).getImm() == 0) &&
818 (MI.getOperand(i: 1).isReg()) &&
819 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
820 // c.jalr $rs1
821 OutInst.setOpcode(RISCV::C_JALR);
822 // Operand: rs1
823 OutInst.addOperand(Op: MI.getOperand(i: 1));
824 OutInst.setLoc(MI.getLoc());
825 return true;
826 } // if
827 break;
828 } // case JALR
829 case RISCV::LBU: {
830 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
831 (MI.getOperand(i: 0).isReg()) &&
832 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
833 (MI.getOperand(i: 1).isReg()) &&
834 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
835 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11)) {
836 // c.lbu $rd, ${imm}(${rs1})
837 OutInst.setOpcode(RISCV::C_LBU);
838 // Operand: rd
839 OutInst.addOperand(Op: MI.getOperand(i: 0));
840 // Operand: rs1
841 OutInst.addOperand(Op: MI.getOperand(i: 1));
842 // Operand: imm
843 OutInst.addOperand(Op: MI.getOperand(i: 2));
844 OutInst.setLoc(MI.getLoc());
845 return true;
846 } // if
847 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
848 (MI.getOperand(i: 0).isReg()) &&
849 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
850 (MI.getOperand(i: 1).isReg()) &&
851 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
852 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12)) {
853 // qk.c.lbu $rd, ${imm}(${rs1})
854 OutInst.setOpcode(RISCV::QK_C_LBU);
855 // Operand: rd
856 OutInst.addOperand(Op: MI.getOperand(i: 0));
857 // Operand: rs1
858 OutInst.addOperand(Op: MI.getOperand(i: 1));
859 // Operand: imm
860 OutInst.addOperand(Op: MI.getOperand(i: 2));
861 OutInst.setLoc(MI.getLoc());
862 return true;
863 } // if
864 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
865 (MI.getOperand(i: 0).isReg()) &&
866 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
867 (MI.getOperand(i: 1).isReg()) &&
868 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
869 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13)) {
870 // qk.c.lbusp $rd_rs2, ${imm}(${rs1})
871 OutInst.setOpcode(RISCV::QK_C_LBUSP);
872 // Operand: rd_rs2
873 OutInst.addOperand(Op: MI.getOperand(i: 0));
874 // Operand: rs1
875 OutInst.addOperand(Op: MI.getOperand(i: 1));
876 // Operand: imm
877 OutInst.addOperand(Op: MI.getOperand(i: 2));
878 OutInst.setLoc(MI.getLoc());
879 return true;
880 } // if
881 break;
882 } // case LBU
883 case RISCV::LD: {
884 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
885 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
886 (MI.getOperand(i: 0).isReg()) &&
887 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
888 (MI.getOperand(i: 1).isReg()) &&
889 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
890 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6)) {
891 // c.ld $rd, ${imm}(${rs1})
892 OutInst.setOpcode(RISCV::C_LD);
893 // Operand: rd
894 OutInst.addOperand(Op: MI.getOperand(i: 0));
895 // Operand: rs1
896 OutInst.addOperand(Op: MI.getOperand(i: 1));
897 // Operand: imm
898 OutInst.addOperand(Op: MI.getOperand(i: 2));
899 OutInst.setLoc(MI.getLoc());
900 return true;
901 } // if
902 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
903 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
904 (MI.getOperand(i: 0).isReg()) &&
905 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
906 (MI.getOperand(i: 1).isReg()) &&
907 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
908 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7)) {
909 // c.ldsp $rd, ${imm}(${rs1})
910 OutInst.setOpcode(RISCV::C_LDSP);
911 // Operand: rd
912 OutInst.addOperand(Op: MI.getOperand(i: 0));
913 // Operand: rs1
914 OutInst.addOperand(Op: MI.getOperand(i: 1));
915 // Operand: imm
916 OutInst.addOperand(Op: MI.getOperand(i: 2));
917 OutInst.setLoc(MI.getLoc());
918 return true;
919 } // if
920 break;
921 } // case LD
922 case RISCV::LH: {
923 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
924 (MI.getOperand(i: 0).isReg()) &&
925 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
926 (MI.getOperand(i: 1).isReg()) &&
927 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
928 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14)) {
929 // c.lh $rd, ${imm}(${rs1})
930 OutInst.setOpcode(RISCV::C_LH);
931 // Operand: rd
932 OutInst.addOperand(Op: MI.getOperand(i: 0));
933 // Operand: rs1
934 OutInst.addOperand(Op: MI.getOperand(i: 1));
935 // Operand: imm
936 OutInst.addOperand(Op: MI.getOperand(i: 2));
937 OutInst.setLoc(MI.getLoc());
938 return true;
939 } // if
940 break;
941 } // case LH
942 case RISCV::LHU: {
943 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
944 (MI.getOperand(i: 0).isReg()) &&
945 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
946 (MI.getOperand(i: 1).isReg()) &&
947 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
948 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14)) {
949 // c.lhu $rd, ${imm}(${rs1})
950 OutInst.setOpcode(RISCV::C_LHU);
951 // Operand: rd
952 OutInst.addOperand(Op: MI.getOperand(i: 0));
953 // Operand: rs1
954 OutInst.addOperand(Op: MI.getOperand(i: 1));
955 // Operand: imm
956 OutInst.addOperand(Op: MI.getOperand(i: 2));
957 OutInst.setLoc(MI.getLoc());
958 return true;
959 } // if
960 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
961 (MI.getOperand(i: 0).isReg()) &&
962 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
963 (MI.getOperand(i: 1).isReg()) &&
964 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
965 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 15)) {
966 // qk.c.lhu $rd, ${imm}(${rs1})
967 OutInst.setOpcode(RISCV::QK_C_LHU);
968 // Operand: rd
969 OutInst.addOperand(Op: MI.getOperand(i: 0));
970 // Operand: rs1
971 OutInst.addOperand(Op: MI.getOperand(i: 1));
972 // Operand: imm
973 OutInst.addOperand(Op: MI.getOperand(i: 2));
974 OutInst.setLoc(MI.getLoc());
975 return true;
976 } // if
977 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
978 (MI.getOperand(i: 0).isReg()) &&
979 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
980 (MI.getOperand(i: 1).isReg()) &&
981 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
982 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16)) {
983 // qk.c.lhusp $rd_rs2, ${imm}(${rs1})
984 OutInst.setOpcode(RISCV::QK_C_LHUSP);
985 // Operand: rd_rs2
986 OutInst.addOperand(Op: MI.getOperand(i: 0));
987 // Operand: rs1
988 OutInst.addOperand(Op: MI.getOperand(i: 1));
989 // Operand: imm
990 OutInst.addOperand(Op: MI.getOperand(i: 2));
991 OutInst.setLoc(MI.getLoc());
992 return true;
993 } // if
994 break;
995 } // case LHU
996 case RISCV::LUI: {
997 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
998 (MI.getOperand(i: 0).isReg()) &&
999 (RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1000 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 17)) {
1001 // c.lui $rd, $imm
1002 OutInst.setOpcode(RISCV::C_LUI);
1003 // Operand: rd
1004 OutInst.addOperand(Op: MI.getOperand(i: 0));
1005 // Operand: imm
1006 OutInst.addOperand(Op: MI.getOperand(i: 1));
1007 OutInst.setLoc(MI.getLoc());
1008 return true;
1009 } // if
1010 break;
1011 } // case LUI
1012 case RISCV::LW: {
1013 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1014 (MI.getOperand(i: 0).isReg()) &&
1015 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1016 (MI.getOperand(i: 1).isReg()) &&
1017 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1018 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8)) {
1019 // c.lw $rd, ${imm}(${rs1})
1020 OutInst.setOpcode(RISCV::C_LW);
1021 // Operand: rd
1022 OutInst.addOperand(Op: MI.getOperand(i: 0));
1023 // Operand: rs1
1024 OutInst.addOperand(Op: MI.getOperand(i: 1));
1025 // Operand: imm
1026 OutInst.addOperand(Op: MI.getOperand(i: 2));
1027 OutInst.setLoc(MI.getLoc());
1028 return true;
1029 } // if
1030 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1031 (MI.getOperand(i: 0).isReg()) &&
1032 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1033 (MI.getOperand(i: 1).isReg()) &&
1034 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1035 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9)) {
1036 // c.lwsp $rd, ${imm}(${rs1})
1037 OutInst.setOpcode(RISCV::C_LWSP);
1038 // Operand: rd
1039 OutInst.addOperand(Op: MI.getOperand(i: 0));
1040 // Operand: rs1
1041 OutInst.addOperand(Op: MI.getOperand(i: 1));
1042 // Operand: imm
1043 OutInst.addOperand(Op: MI.getOperand(i: 2));
1044 OutInst.setLoc(MI.getLoc());
1045 return true;
1046 } // if
1047 break;
1048 } // case LW
1049 case RISCV::MUL: {
1050 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1051 STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1052 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1053 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1054 (MI.getOperand(i: 1).isReg()) &&
1055 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1056 (MI.getOperand(i: 2).isReg()) &&
1057 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1058 // c.mul $rd, $rs2
1059 OutInst.setOpcode(RISCV::C_MUL);
1060 // Operand: rd_wb
1061 OutInst.addOperand(Op: MI.getOperand(i: 1));
1062 // Operand: rd
1063 OutInst.addOperand(Op: MI.getOperand(i: 1));
1064 // Operand: rs2
1065 OutInst.addOperand(Op: MI.getOperand(i: 2));
1066 OutInst.setLoc(MI.getLoc());
1067 return true;
1068 } // if
1069 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1070 STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1071 (MI.getOperand(i: 2).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1072 (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) &&
1073 (MI.getOperand(i: 2).isReg()) &&
1074 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg())) &&
1075 (MI.getOperand(i: 1).isReg()) &&
1076 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1077 // c.mul $rd, $rs2
1078 OutInst.setOpcode(RISCV::C_MUL);
1079 // Operand: rd_wb
1080 OutInst.addOperand(Op: MI.getOperand(i: 2));
1081 // Operand: rd
1082 OutInst.addOperand(Op: MI.getOperand(i: 2));
1083 // Operand: rs2
1084 OutInst.addOperand(Op: MI.getOperand(i: 1));
1085 OutInst.setLoc(MI.getLoc());
1086 return true;
1087 } // if
1088 break;
1089 } // case MUL
1090 case RISCV::OR: {
1091 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1092 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1093 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1094 (MI.getOperand(i: 1).isReg()) &&
1095 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1096 (MI.getOperand(i: 2).isReg()) &&
1097 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1098 // c.or $rd, $rs2
1099 OutInst.setOpcode(RISCV::C_OR);
1100 // Operand: rd_wb
1101 OutInst.addOperand(Op: MI.getOperand(i: 1));
1102 // Operand: rd
1103 OutInst.addOperand(Op: MI.getOperand(i: 1));
1104 // Operand: rs2
1105 OutInst.addOperand(Op: MI.getOperand(i: 2));
1106 OutInst.setLoc(MI.getLoc());
1107 return true;
1108 } // if
1109 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1110 (MI.getOperand(i: 2).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1111 (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) &&
1112 (MI.getOperand(i: 2).isReg()) &&
1113 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg())) &&
1114 (MI.getOperand(i: 1).isReg()) &&
1115 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1116 // c.or $rd, $rs2
1117 OutInst.setOpcode(RISCV::C_OR);
1118 // Operand: rd_wb
1119 OutInst.addOperand(Op: MI.getOperand(i: 2));
1120 // Operand: rd
1121 OutInst.addOperand(Op: MI.getOperand(i: 2));
1122 // Operand: rs2
1123 OutInst.addOperand(Op: MI.getOperand(i: 1));
1124 OutInst.setLoc(MI.getLoc());
1125 return true;
1126 } // if
1127 break;
1128 } // case OR
1129 case RISCV::SB: {
1130 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1131 (MI.getOperand(i: 0).isReg()) &&
1132 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1133 (MI.getOperand(i: 1).isReg()) &&
1134 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1135 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 11)) {
1136 // c.sb $rs2, ${imm}(${rs1})
1137 OutInst.setOpcode(RISCV::C_SB);
1138 // Operand: rs2
1139 OutInst.addOperand(Op: MI.getOperand(i: 0));
1140 // Operand: rs1
1141 OutInst.addOperand(Op: MI.getOperand(i: 1));
1142 // Operand: imm
1143 OutInst.addOperand(Op: MI.getOperand(i: 2));
1144 OutInst.setLoc(MI.getLoc());
1145 return true;
1146 } // if
1147 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1148 (MI.getOperand(i: 0).isReg()) &&
1149 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1150 (MI.getOperand(i: 1).isReg()) &&
1151 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1152 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 12)) {
1153 // qk.c.sb $rs2, ${imm}(${rs1})
1154 OutInst.setOpcode(RISCV::QK_C_SB);
1155 // Operand: rs2
1156 OutInst.addOperand(Op: MI.getOperand(i: 0));
1157 // Operand: rs1
1158 OutInst.addOperand(Op: MI.getOperand(i: 1));
1159 // Operand: imm
1160 OutInst.addOperand(Op: MI.getOperand(i: 2));
1161 OutInst.setLoc(MI.getLoc());
1162 return true;
1163 } // if
1164 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1165 (MI.getOperand(i: 0).isReg()) &&
1166 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1167 (MI.getOperand(i: 1).isReg()) &&
1168 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1169 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 13)) {
1170 // qk.c.sbsp $rd_rs2, ${imm}(${rs1})
1171 OutInst.setOpcode(RISCV::QK_C_SBSP);
1172 // Operand: rd_rs2
1173 OutInst.addOperand(Op: MI.getOperand(i: 0));
1174 // Operand: rs1
1175 OutInst.addOperand(Op: MI.getOperand(i: 1));
1176 // Operand: imm
1177 OutInst.addOperand(Op: MI.getOperand(i: 2));
1178 OutInst.setLoc(MI.getLoc());
1179 return true;
1180 } // if
1181 break;
1182 } // case SB
1183 case RISCV::SD: {
1184 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1185 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1186 (MI.getOperand(i: 0).isReg()) &&
1187 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1188 (MI.getOperand(i: 1).isReg()) &&
1189 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1190 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 6)) {
1191 // c.sd $rs2, ${imm}(${rs1})
1192 OutInst.setOpcode(RISCV::C_SD);
1193 // Operand: rs2
1194 OutInst.addOperand(Op: MI.getOperand(i: 0));
1195 // Operand: rs1
1196 OutInst.addOperand(Op: MI.getOperand(i: 1));
1197 // Operand: imm
1198 OutInst.addOperand(Op: MI.getOperand(i: 2));
1199 OutInst.setLoc(MI.getLoc());
1200 return true;
1201 } // if
1202 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1203 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1204 (MI.getOperand(i: 0).isReg()) &&
1205 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1206 (MI.getOperand(i: 1).isReg()) &&
1207 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1208 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 7)) {
1209 // c.sdsp $rs2, ${imm}(${rs1})
1210 OutInst.setOpcode(RISCV::C_SDSP);
1211 // Operand: rs2
1212 OutInst.addOperand(Op: MI.getOperand(i: 0));
1213 // Operand: rs1
1214 OutInst.addOperand(Op: MI.getOperand(i: 1));
1215 // Operand: imm
1216 OutInst.addOperand(Op: MI.getOperand(i: 2));
1217 OutInst.setLoc(MI.getLoc());
1218 return true;
1219 } // if
1220 break;
1221 } // case SD
1222 case RISCV::SEXT_B: {
1223 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1224 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1225 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1226 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1227 (MI.getOperand(i: 1).isReg()) &&
1228 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1229 // c.sext.b $rd
1230 OutInst.setOpcode(RISCV::C_SEXT_B);
1231 // Operand: rd_wb
1232 OutInst.addOperand(Op: MI.getOperand(i: 1));
1233 // Operand: rd
1234 OutInst.addOperand(Op: MI.getOperand(i: 1));
1235 OutInst.setLoc(MI.getLoc());
1236 return true;
1237 } // if
1238 break;
1239 } // case SEXT_B
1240 case RISCV::SEXT_H: {
1241 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1242 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1243 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1244 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1245 (MI.getOperand(i: 1).isReg()) &&
1246 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1247 // c.sext.h $rd
1248 OutInst.setOpcode(RISCV::C_SEXT_H);
1249 // Operand: rd_wb
1250 OutInst.addOperand(Op: MI.getOperand(i: 1));
1251 // Operand: rd
1252 OutInst.addOperand(Op: MI.getOperand(i: 1));
1253 OutInst.setLoc(MI.getLoc());
1254 return true;
1255 } // if
1256 break;
1257 } // case SEXT_H
1258 case RISCV::SH: {
1259 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1260 (MI.getOperand(i: 0).isReg()) &&
1261 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1262 (MI.getOperand(i: 1).isReg()) &&
1263 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1264 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 14)) {
1265 // c.sh $rs2, ${imm}(${rs1})
1266 OutInst.setOpcode(RISCV::C_SH);
1267 // Operand: rs2
1268 OutInst.addOperand(Op: MI.getOperand(i: 0));
1269 // Operand: rs1
1270 OutInst.addOperand(Op: MI.getOperand(i: 1));
1271 // Operand: imm
1272 OutInst.addOperand(Op: MI.getOperand(i: 2));
1273 OutInst.setLoc(MI.getLoc());
1274 return true;
1275 } // if
1276 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1277 (MI.getOperand(i: 0).isReg()) &&
1278 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1279 (MI.getOperand(i: 1).isReg()) &&
1280 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1281 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 15)) {
1282 // qk.c.sh $rs2, ${imm}(${rs1})
1283 OutInst.setOpcode(RISCV::QK_C_SH);
1284 // Operand: rs2
1285 OutInst.addOperand(Op: MI.getOperand(i: 0));
1286 // Operand: rs1
1287 OutInst.addOperand(Op: MI.getOperand(i: 1));
1288 // Operand: imm
1289 OutInst.addOperand(Op: MI.getOperand(i: 2));
1290 OutInst.setLoc(MI.getLoc());
1291 return true;
1292 } // if
1293 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1294 (MI.getOperand(i: 0).isReg()) &&
1295 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1296 (MI.getOperand(i: 1).isReg()) &&
1297 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1298 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 16)) {
1299 // qk.c.shsp $rd_rs2, ${imm}(${rs1})
1300 OutInst.setOpcode(RISCV::QK_C_SHSP);
1301 // Operand: rd_rs2
1302 OutInst.addOperand(Op: MI.getOperand(i: 0));
1303 // Operand: rs1
1304 OutInst.addOperand(Op: MI.getOperand(i: 1));
1305 // Operand: imm
1306 OutInst.addOperand(Op: MI.getOperand(i: 2));
1307 OutInst.setLoc(MI.getLoc());
1308 return true;
1309 } // if
1310 break;
1311 } // case SH
1312 case RISCV::SLLI: {
1313 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1314 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1315 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1316 (MI.getOperand(i: 1).isReg()) &&
1317 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1318 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 18)) {
1319 // c.slli $rd, $imm
1320 OutInst.setOpcode(RISCV::C_SLLI);
1321 // Operand: rd_wb
1322 OutInst.addOperand(Op: MI.getOperand(i: 1));
1323 // Operand: rd
1324 OutInst.addOperand(Op: MI.getOperand(i: 1));
1325 // Operand: imm
1326 OutInst.addOperand(Op: MI.getOperand(i: 2));
1327 OutInst.setLoc(MI.getLoc());
1328 return true;
1329 } // if
1330 break;
1331 } // case SLLI
1332 case RISCV::SRAI: {
1333 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1334 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1335 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1336 (MI.getOperand(i: 1).isReg()) &&
1337 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1338 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 18)) {
1339 // c.srai $rs1, $imm
1340 OutInst.setOpcode(RISCV::C_SRAI);
1341 // Operand: rs1_wb
1342 OutInst.addOperand(Op: MI.getOperand(i: 1));
1343 // Operand: rs1
1344 OutInst.addOperand(Op: MI.getOperand(i: 1));
1345 // Operand: imm
1346 OutInst.addOperand(Op: MI.getOperand(i: 2));
1347 OutInst.setLoc(MI.getLoc());
1348 return true;
1349 } // if
1350 break;
1351 } // case SRAI
1352 case RISCV::SRLI: {
1353 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1354 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1355 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1356 (MI.getOperand(i: 1).isReg()) &&
1357 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1358 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 18)) {
1359 // c.srli $rs1, $imm
1360 OutInst.setOpcode(RISCV::C_SRLI);
1361 // Operand: rs1_wb
1362 OutInst.addOperand(Op: MI.getOperand(i: 1));
1363 // Operand: rs1
1364 OutInst.addOperand(Op: MI.getOperand(i: 1));
1365 // Operand: imm
1366 OutInst.addOperand(Op: MI.getOperand(i: 2));
1367 OutInst.setLoc(MI.getLoc());
1368 return true;
1369 } // if
1370 break;
1371 } // case SRLI
1372 case RISCV::SSPOPCHK: {
1373 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
1374 STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
1375 (MI.getOperand(i: 0).isReg()) &&
1376 (MI.getOperand(i: 0).getReg() == RISCV::X5)) {
1377 // c.sspopchk $rs1
1378 OutInst.setOpcode(RISCV::C_SSPOPCHK);
1379 // Operand: rs1
1380 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
1381 OutInst.setLoc(MI.getLoc());
1382 return true;
1383 } // if
1384 break;
1385 } // case SSPOPCHK
1386 case RISCV::SSPUSH: {
1387 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
1388 STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
1389 (MI.getOperand(i: 0).isReg()) &&
1390 (MI.getOperand(i: 0).getReg() == RISCV::X1)) {
1391 // c.sspush $rs1
1392 OutInst.setOpcode(RISCV::C_SSPUSH);
1393 // Operand: rs1
1394 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
1395 OutInst.setLoc(MI.getLoc());
1396 return true;
1397 } // if
1398 break;
1399 } // case SSPUSH
1400 case RISCV::SUB: {
1401 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1402 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1403 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1404 (MI.getOperand(i: 1).isReg()) &&
1405 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1406 (MI.getOperand(i: 2).isReg()) &&
1407 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1408 // c.sub $rd, $rs2
1409 OutInst.setOpcode(RISCV::C_SUB);
1410 // Operand: rd_wb
1411 OutInst.addOperand(Op: MI.getOperand(i: 1));
1412 // Operand: rd
1413 OutInst.addOperand(Op: MI.getOperand(i: 1));
1414 // Operand: rs2
1415 OutInst.addOperand(Op: MI.getOperand(i: 2));
1416 OutInst.setLoc(MI.getLoc());
1417 return true;
1418 } // if
1419 break;
1420 } // case SUB
1421 case RISCV::SUBW: {
1422 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1423 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1424 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1425 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1426 (MI.getOperand(i: 1).isReg()) &&
1427 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1428 (MI.getOperand(i: 2).isReg()) &&
1429 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1430 // c.subw $rd, $rs2
1431 OutInst.setOpcode(RISCV::C_SUBW);
1432 // Operand: rd_wb
1433 OutInst.addOperand(Op: MI.getOperand(i: 1));
1434 // Operand: rd
1435 OutInst.addOperand(Op: MI.getOperand(i: 1));
1436 // Operand: rs2
1437 OutInst.addOperand(Op: MI.getOperand(i: 2));
1438 OutInst.setLoc(MI.getLoc());
1439 return true;
1440 } // if
1441 break;
1442 } // case SUBW
1443 case RISCV::SW: {
1444 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1445 (MI.getOperand(i: 0).isReg()) &&
1446 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1447 (MI.getOperand(i: 1).isReg()) &&
1448 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1449 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 8)) {
1450 // c.sw $rs2, ${imm}(${rs1})
1451 OutInst.setOpcode(RISCV::C_SW);
1452 // Operand: rs2
1453 OutInst.addOperand(Op: MI.getOperand(i: 0));
1454 // Operand: rs1
1455 OutInst.addOperand(Op: MI.getOperand(i: 1));
1456 // Operand: imm
1457 OutInst.addOperand(Op: MI.getOperand(i: 2));
1458 OutInst.setLoc(MI.getLoc());
1459 return true;
1460 } // if
1461 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1462 (MI.getOperand(i: 0).isReg()) &&
1463 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1464 (MI.getOperand(i: 1).isReg()) &&
1465 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1466 RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 9)) {
1467 // c.swsp $rs2, ${imm}(${rs1})
1468 OutInst.setOpcode(RISCV::C_SWSP);
1469 // Operand: rs2
1470 OutInst.addOperand(Op: MI.getOperand(i: 0));
1471 // Operand: rs1
1472 OutInst.addOperand(Op: MI.getOperand(i: 1));
1473 // Operand: imm
1474 OutInst.addOperand(Op: MI.getOperand(i: 2));
1475 OutInst.setLoc(MI.getLoc());
1476 return true;
1477 } // if
1478 break;
1479 } // case SW
1480 case RISCV::UNIMP: {
1481 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
1482 // c.unimp
1483 OutInst.setOpcode(RISCV::C_UNIMP);
1484 OutInst.setLoc(MI.getLoc());
1485 return true;
1486 } // if
1487 break;
1488 } // case UNIMP
1489 case RISCV::XOR: {
1490 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1491 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1492 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1493 (MI.getOperand(i: 1).isReg()) &&
1494 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1495 (MI.getOperand(i: 2).isReg()) &&
1496 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1497 // c.xor $rd, $rs2
1498 OutInst.setOpcode(RISCV::C_XOR);
1499 // Operand: rd_wb
1500 OutInst.addOperand(Op: MI.getOperand(i: 1));
1501 // Operand: rd
1502 OutInst.addOperand(Op: MI.getOperand(i: 1));
1503 // Operand: rs2
1504 OutInst.addOperand(Op: MI.getOperand(i: 2));
1505 OutInst.setLoc(MI.getLoc());
1506 return true;
1507 } // if
1508 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1509 (MI.getOperand(i: 2).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1510 (MI.getOperand(i: 2).getReg() == MI.getOperand(i: 0).getReg()) &&
1511 (MI.getOperand(i: 2).isReg()) &&
1512 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 2).getReg())) &&
1513 (MI.getOperand(i: 1).isReg()) &&
1514 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1515 // c.xor $rd, $rs2
1516 OutInst.setOpcode(RISCV::C_XOR);
1517 // Operand: rd_wb
1518 OutInst.addOperand(Op: MI.getOperand(i: 2));
1519 // Operand: rd
1520 OutInst.addOperand(Op: MI.getOperand(i: 2));
1521 // Operand: rs2
1522 OutInst.addOperand(Op: MI.getOperand(i: 1));
1523 OutInst.setLoc(MI.getLoc());
1524 return true;
1525 } // if
1526 break;
1527 } // case XOR
1528 case RISCV::XORI: {
1529 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1530 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1531 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1532 (MI.getOperand(i: 2).isImm()) &&
1533 (MI.getOperand(i: 2).getImm() == -1) &&
1534 (MI.getOperand(i: 1).isReg()) &&
1535 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1536 // c.not $rd
1537 OutInst.setOpcode(RISCV::C_NOT);
1538 // Operand: rd_wb
1539 OutInst.addOperand(Op: MI.getOperand(i: 1));
1540 // Operand: rd
1541 OutInst.addOperand(Op: MI.getOperand(i: 1));
1542 OutInst.setLoc(MI.getLoc());
1543 return true;
1544 } // if
1545 break;
1546 } // case XORI
1547 case RISCV::ZEXT_H_RV32: {
1548 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1549 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1550 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1551 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1552 (MI.getOperand(i: 1).isReg()) &&
1553 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1554 // c.zext.h $rd
1555 OutInst.setOpcode(RISCV::C_ZEXT_H);
1556 // Operand: rd_wb
1557 OutInst.addOperand(Op: MI.getOperand(i: 1));
1558 // Operand: rd
1559 OutInst.addOperand(Op: MI.getOperand(i: 1));
1560 OutInst.setLoc(MI.getLoc());
1561 return true;
1562 } // if
1563 break;
1564 } // case ZEXT_H_RV32
1565 case RISCV::ZEXT_H_RV64: {
1566 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1567 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1568 (MI.getOperand(i: 1).isReg()) && (MI.getOperand(i: 0).isReg()) &&
1569 (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 0).getReg()) &&
1570 (MI.getOperand(i: 1).isReg()) &&
1571 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: 1).getReg()))) {
1572 // c.zext.h $rd
1573 OutInst.setOpcode(RISCV::C_ZEXT_H);
1574 // Operand: rd_wb
1575 OutInst.addOperand(Op: MI.getOperand(i: 1));
1576 // Operand: rd
1577 OutInst.addOperand(Op: MI.getOperand(i: 1));
1578 OutInst.setLoc(MI.getLoc());
1579 return true;
1580 } // if
1581
1582 } // case ZEXT_H_RV64
1583 } // switch
1584 return false;
1585}
1586
1587#endif //GEN_COMPRESS_INSTR
1588
1589#ifdef GEN_UNCOMPRESS_INSTR
1590#undef GEN_UNCOMPRESS_INSTR
1591
1592static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp,
1593 const MCSubtargetInfo &STI,
1594 unsigned PredicateIndex) {
1595 switch (PredicateIndex) {
1596 default:
1597 llvm_unreachable("Unknown MCOperandPredicate kind");
1598 break;
1599 case 1: {
1600 // simm12
1601
1602 int64_t Imm;
1603 if (MCOp.evaluateAsConstantImm(Imm))
1604 return isInt<12>(x: Imm);
1605 return MCOp.isBareSymbolRef();
1606
1607 }
1608 case 2: {
1609 // simm13_lsb0
1610
1611 int64_t Imm;
1612 if (MCOp.evaluateAsConstantImm(Imm))
1613 return isShiftedInt<12, 1>(x: Imm);
1614 return MCOp.isBareSymbolRef();
1615
1616 }
1617 case 3: {
1618 // simm21_lsb0_jal
1619
1620 int64_t Imm;
1621 if (MCOp.evaluateAsConstantImm(Imm))
1622 return isShiftedInt<20, 1>(x: Imm);
1623 return MCOp.isBareSymbolRef();
1624
1625 }
1626 case 4: {
1627 // uimm20_lui
1628
1629 int64_t Imm;
1630 if (MCOp.evaluateAsConstantImm(Imm))
1631 return isUInt<20>(x: Imm);
1632 return MCOp.isBareSymbolRef();
1633
1634 }
1635 case 5: {
1636 // uimmlog2xlen
1637
1638 int64_t Imm;
1639 if (!MCOp.evaluateAsConstantImm(Imm))
1640 return false;
1641 if (STI.getTargetTriple().isArch64Bit())
1642 return isUInt<6>(x: Imm);
1643 return isUInt<5>(x: Imm);
1644
1645 }
1646 }
1647}
1648
1649static bool uncompressInst(MCInst &OutInst,
1650 const MCInst &MI,
1651 const MCSubtargetInfo &STI) {
1652 switch (MI.getOpcode()) {
1653 default: return false;
1654 case RISCV::C_ADD: {
1655 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1656 (MI.getOperand(i: 0).isReg()) &&
1657 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1658 (MI.getOperand(i: 0).isReg()) &&
1659 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1660 (MI.getOperand(i: 2).isReg()) &&
1661 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1662 // add $rd, $rs1, $rs2
1663 OutInst.setOpcode(RISCV::ADD);
1664 // Operand: rd
1665 OutInst.addOperand(Op: MI.getOperand(i: 0));
1666 // Operand: rs1
1667 OutInst.addOperand(Op: MI.getOperand(i: 0));
1668 // Operand: rs2
1669 OutInst.addOperand(Op: MI.getOperand(i: 2));
1670 OutInst.setLoc(MI.getLoc());
1671 return true;
1672 } // if
1673 break;
1674 } // case C_ADD
1675 case RISCV::C_ADDI: {
1676 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1677 (MI.getOperand(i: 0).isReg()) &&
1678 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1679 (MI.getOperand(i: 0).isReg()) &&
1680 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1681 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1682 // addi $rd, $rs1, $imm12
1683 OutInst.setOpcode(RISCV::ADDI);
1684 // Operand: rd
1685 OutInst.addOperand(Op: MI.getOperand(i: 0));
1686 // Operand: rs1
1687 OutInst.addOperand(Op: MI.getOperand(i: 0));
1688 // Operand: imm12
1689 OutInst.addOperand(Op: MI.getOperand(i: 2));
1690 OutInst.setLoc(MI.getLoc());
1691 return true;
1692 } // if
1693 break;
1694 } // case C_ADDI
1695 case RISCV::C_ADDI16SP: {
1696 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1697 (MI.getOperand(i: 0).isReg()) &&
1698 (MI.getOperand(i: 0).getReg() == RISCV::X2) &&
1699 (MI.getOperand(i: 1).isReg()) &&
1700 (MI.getOperand(i: 1).getReg() == RISCV::X2) &&
1701 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1702 // addi $rd, $rs1, $imm12
1703 OutInst.setOpcode(RISCV::ADDI);
1704 // Operand: rd
1705 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1706 // Operand: rs1
1707 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1708 // Operand: imm12
1709 OutInst.addOperand(Op: MI.getOperand(i: 2));
1710 OutInst.setLoc(MI.getLoc());
1711 return true;
1712 } // if
1713 break;
1714 } // case C_ADDI16SP
1715 case RISCV::C_ADDI4SPN: {
1716 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1717 (MI.getOperand(i: 0).isReg()) &&
1718 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1719 (MI.getOperand(i: 1).isReg()) &&
1720 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1721 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1722 // addi $rd, $rs1, $imm12
1723 OutInst.setOpcode(RISCV::ADDI);
1724 // Operand: rd
1725 OutInst.addOperand(Op: MI.getOperand(i: 0));
1726 // Operand: rs1
1727 OutInst.addOperand(Op: MI.getOperand(i: 1));
1728 // Operand: imm12
1729 OutInst.addOperand(Op: MI.getOperand(i: 2));
1730 OutInst.setLoc(MI.getLoc());
1731 return true;
1732 } // if
1733 break;
1734 } // case C_ADDI4SPN
1735 case RISCV::C_ADDIW: {
1736 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1737 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1738 (MI.getOperand(i: 0).isReg()) &&
1739 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1740 (MI.getOperand(i: 0).isReg()) &&
1741 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1742 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1743 // addiw $rd, $rs1, $imm12
1744 OutInst.setOpcode(RISCV::ADDIW);
1745 // Operand: rd
1746 OutInst.addOperand(Op: MI.getOperand(i: 0));
1747 // Operand: rs1
1748 OutInst.addOperand(Op: MI.getOperand(i: 0));
1749 // Operand: imm12
1750 OutInst.addOperand(Op: MI.getOperand(i: 2));
1751 OutInst.setLoc(MI.getLoc());
1752 return true;
1753 } // if
1754 break;
1755 } // case C_ADDIW
1756 case RISCV::C_ADDW: {
1757 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1758 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1759 (MI.getOperand(i: 0).isReg()) &&
1760 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1761 (MI.getOperand(i: 0).isReg()) &&
1762 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1763 (MI.getOperand(i: 2).isReg()) &&
1764 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1765 // addw $rd, $rs1, $rs2
1766 OutInst.setOpcode(RISCV::ADDW);
1767 // Operand: rd
1768 OutInst.addOperand(Op: MI.getOperand(i: 0));
1769 // Operand: rs1
1770 OutInst.addOperand(Op: MI.getOperand(i: 0));
1771 // Operand: rs2
1772 OutInst.addOperand(Op: MI.getOperand(i: 2));
1773 OutInst.setLoc(MI.getLoc());
1774 return true;
1775 } // if
1776 break;
1777 } // case C_ADDW
1778 case RISCV::C_AND: {
1779 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1780 (MI.getOperand(i: 0).isReg()) &&
1781 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1782 (MI.getOperand(i: 0).isReg()) &&
1783 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1784 (MI.getOperand(i: 2).isReg()) &&
1785 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
1786 // and $rd, $rs1, $rs2
1787 OutInst.setOpcode(RISCV::AND);
1788 // Operand: rd
1789 OutInst.addOperand(Op: MI.getOperand(i: 0));
1790 // Operand: rs1
1791 OutInst.addOperand(Op: MI.getOperand(i: 0));
1792 // Operand: rs2
1793 OutInst.addOperand(Op: MI.getOperand(i: 2));
1794 OutInst.setLoc(MI.getLoc());
1795 return true;
1796 } // if
1797 break;
1798 } // case C_AND
1799 case RISCV::C_ANDI: {
1800 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1801 (MI.getOperand(i: 0).isReg()) &&
1802 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1803 (MI.getOperand(i: 0).isReg()) &&
1804 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1805 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1806 // andi $rd, $rs1, $imm12
1807 OutInst.setOpcode(RISCV::ANDI);
1808 // Operand: rd
1809 OutInst.addOperand(Op: MI.getOperand(i: 0));
1810 // Operand: rs1
1811 OutInst.addOperand(Op: MI.getOperand(i: 0));
1812 // Operand: imm12
1813 OutInst.addOperand(Op: MI.getOperand(i: 2));
1814 OutInst.setLoc(MI.getLoc());
1815 return true;
1816 } // if
1817 break;
1818 } // case C_ANDI
1819 case RISCV::C_BEQZ: {
1820 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1821 (MI.getOperand(i: 0).isReg()) &&
1822 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1823 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 2)) {
1824 // beq $rs1, $rs2, $imm12
1825 OutInst.setOpcode(RISCV::BEQ);
1826 // Operand: rs1
1827 OutInst.addOperand(Op: MI.getOperand(i: 0));
1828 // Operand: rs2
1829 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
1830 // Operand: imm12
1831 OutInst.addOperand(Op: MI.getOperand(i: 1));
1832 OutInst.setLoc(MI.getLoc());
1833 return true;
1834 } // if
1835 break;
1836 } // case C_BEQZ
1837 case RISCV::C_BNEZ: {
1838 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1839 (MI.getOperand(i: 0).isReg()) &&
1840 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1841 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 2)) {
1842 // bne $rs1, $rs2, $imm12
1843 OutInst.setOpcode(RISCV::BNE);
1844 // Operand: rs1
1845 OutInst.addOperand(Op: MI.getOperand(i: 0));
1846 // Operand: rs2
1847 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
1848 // Operand: imm12
1849 OutInst.addOperand(Op: MI.getOperand(i: 1));
1850 OutInst.setLoc(MI.getLoc());
1851 return true;
1852 } // if
1853 break;
1854 } // case C_BNEZ
1855 case RISCV::C_EBREAK: {
1856 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
1857 // ebreak
1858 OutInst.setOpcode(RISCV::EBREAK);
1859 OutInst.setLoc(MI.getLoc());
1860 return true;
1861 } // if
1862 break;
1863 } // case C_EBREAK
1864 case RISCV::C_FLD: {
1865 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1866 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1867 (MI.getOperand(i: 0).isReg()) &&
1868 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1869 (MI.getOperand(i: 1).isReg()) &&
1870 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1871 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1872 // fld $rd, ${imm12}(${rs1})
1873 OutInst.setOpcode(RISCV::FLD);
1874 // Operand: rd
1875 OutInst.addOperand(Op: MI.getOperand(i: 0));
1876 // Operand: rs1
1877 OutInst.addOperand(Op: MI.getOperand(i: 1));
1878 // Operand: imm12
1879 OutInst.addOperand(Op: MI.getOperand(i: 2));
1880 OutInst.setLoc(MI.getLoc());
1881 return true;
1882 } // if
1883 break;
1884 } // case C_FLD
1885 case RISCV::C_FLDSP: {
1886 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1887 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1888 (MI.getOperand(i: 0).isReg()) &&
1889 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1890 (MI.getOperand(i: 1).isReg()) &&
1891 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1892 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1893 // fld $rd, ${imm12}(${rs1})
1894 OutInst.setOpcode(RISCV::FLD);
1895 // Operand: rd
1896 OutInst.addOperand(Op: MI.getOperand(i: 0));
1897 // Operand: rs1
1898 OutInst.addOperand(Op: MI.getOperand(i: 1));
1899 // Operand: imm12
1900 OutInst.addOperand(Op: MI.getOperand(i: 2));
1901 OutInst.setLoc(MI.getLoc());
1902 return true;
1903 } // if
1904 break;
1905 } // case C_FLDSP
1906 case RISCV::C_FLW: {
1907 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1908 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1909 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1910 (MI.getOperand(i: 0).isReg()) &&
1911 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1912 (MI.getOperand(i: 1).isReg()) &&
1913 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1914 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1915 // flw $rd, ${imm12}(${rs1})
1916 OutInst.setOpcode(RISCV::FLW);
1917 // Operand: rd
1918 OutInst.addOperand(Op: MI.getOperand(i: 0));
1919 // Operand: rs1
1920 OutInst.addOperand(Op: MI.getOperand(i: 1));
1921 // Operand: imm12
1922 OutInst.addOperand(Op: MI.getOperand(i: 2));
1923 OutInst.setLoc(MI.getLoc());
1924 return true;
1925 } // if
1926 break;
1927 } // case C_FLW
1928 case RISCV::C_FLWSP: {
1929 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1930 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1931 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1932 (MI.getOperand(i: 0).isReg()) &&
1933 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1934 (MI.getOperand(i: 1).isReg()) &&
1935 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1936 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1937 // flw $rd, ${imm12}(${rs1})
1938 OutInst.setOpcode(RISCV::FLW);
1939 // Operand: rd
1940 OutInst.addOperand(Op: MI.getOperand(i: 0));
1941 // Operand: rs1
1942 OutInst.addOperand(Op: MI.getOperand(i: 1));
1943 // Operand: imm12
1944 OutInst.addOperand(Op: MI.getOperand(i: 2));
1945 OutInst.setLoc(MI.getLoc());
1946 return true;
1947 } // if
1948 break;
1949 } // case C_FLWSP
1950 case RISCV::C_FSD: {
1951 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1952 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1953 (MI.getOperand(i: 0).isReg()) &&
1954 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1955 (MI.getOperand(i: 1).isReg()) &&
1956 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1957 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1958 // fsd $rs2, ${imm12}(${rs1})
1959 OutInst.setOpcode(RISCV::FSD);
1960 // Operand: rs2
1961 OutInst.addOperand(Op: MI.getOperand(i: 0));
1962 // Operand: rs1
1963 OutInst.addOperand(Op: MI.getOperand(i: 1));
1964 // Operand: imm12
1965 OutInst.addOperand(Op: MI.getOperand(i: 2));
1966 OutInst.setLoc(MI.getLoc());
1967 return true;
1968 } // if
1969 break;
1970 } // case C_FSD
1971 case RISCV::C_FSDSP: {
1972 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1973 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1974 (MI.getOperand(i: 0).isReg()) &&
1975 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1976 (MI.getOperand(i: 1).isReg()) &&
1977 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
1978 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
1979 // fsd $rs2, ${imm12}(${rs1})
1980 OutInst.setOpcode(RISCV::FSD);
1981 // Operand: rs2
1982 OutInst.addOperand(Op: MI.getOperand(i: 0));
1983 // Operand: rs1
1984 OutInst.addOperand(Op: MI.getOperand(i: 1));
1985 // Operand: imm12
1986 OutInst.addOperand(Op: MI.getOperand(i: 2));
1987 OutInst.setLoc(MI.getLoc());
1988 return true;
1989 } // if
1990 break;
1991 } // case C_FSDSP
1992 case RISCV::C_FSW: {
1993 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1994 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1995 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1996 (MI.getOperand(i: 0).isReg()) &&
1997 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
1998 (MI.getOperand(i: 1).isReg()) &&
1999 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2000 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2001 // fsw $rs2, ${imm12}(${rs1})
2002 OutInst.setOpcode(RISCV::FSW);
2003 // Operand: rs2
2004 OutInst.addOperand(Op: MI.getOperand(i: 0));
2005 // Operand: rs1
2006 OutInst.addOperand(Op: MI.getOperand(i: 1));
2007 // Operand: imm12
2008 OutInst.addOperand(Op: MI.getOperand(i: 2));
2009 OutInst.setLoc(MI.getLoc());
2010 return true;
2011 } // if
2012 break;
2013 } // case C_FSW
2014 case RISCV::C_FSWSP: {
2015 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
2016 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
2017 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
2018 (MI.getOperand(i: 0).isReg()) &&
2019 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2020 (MI.getOperand(i: 1).isReg()) &&
2021 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2022 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2023 // fsw $rs2, ${imm12}(${rs1})
2024 OutInst.setOpcode(RISCV::FSW);
2025 // Operand: rs2
2026 OutInst.addOperand(Op: MI.getOperand(i: 0));
2027 // Operand: rs1
2028 OutInst.addOperand(Op: MI.getOperand(i: 1));
2029 // Operand: imm12
2030 OutInst.addOperand(Op: MI.getOperand(i: 2));
2031 OutInst.setLoc(MI.getLoc());
2032 return true;
2033 } // if
2034 break;
2035 } // case C_FSWSP
2036 case RISCV::C_J: {
2037 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2038 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 3)) {
2039 // jal $rd, $imm20
2040 OutInst.setOpcode(RISCV::JAL);
2041 // Operand: rd
2042 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2043 // Operand: imm20
2044 OutInst.addOperand(Op: MI.getOperand(i: 0));
2045 OutInst.setLoc(MI.getLoc());
2046 return true;
2047 } // if
2048 break;
2049 } // case C_J
2050 case RISCV::C_JAL: {
2051 if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2052 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2053 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 0), STI, PredicateIndex: 3)) {
2054 // jal $rd, $imm20
2055 OutInst.setOpcode(RISCV::JAL);
2056 // Operand: rd
2057 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
2058 // Operand: imm20
2059 OutInst.addOperand(Op: MI.getOperand(i: 0));
2060 OutInst.setLoc(MI.getLoc());
2061 return true;
2062 } // if
2063 break;
2064 } // case C_JAL
2065 case RISCV::C_JALR: {
2066 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2067 (MI.getOperand(i: 0).isReg()) &&
2068 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2069 RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 1)) {
2070 // jalr $rd, ${imm12}(${rs1})
2071 OutInst.setOpcode(RISCV::JALR);
2072 // Operand: rd
2073 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
2074 // Operand: rs1
2075 OutInst.addOperand(Op: MI.getOperand(i: 0));
2076 // Operand: imm12
2077 OutInst.addOperand(Op: MCOperand::createImm(Val: 0));
2078 OutInst.setLoc(MI.getLoc());
2079 return true;
2080 } // if
2081 break;
2082 } // case C_JALR
2083 case RISCV::C_JR: {
2084 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2085 (MI.getOperand(i: 0).isReg()) &&
2086 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2087 RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 1)) {
2088 // jalr $rd, ${imm12}(${rs1})
2089 OutInst.setOpcode(RISCV::JALR);
2090 // Operand: rd
2091 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2092 // Operand: rs1
2093 OutInst.addOperand(Op: MI.getOperand(i: 0));
2094 // Operand: imm12
2095 OutInst.addOperand(Op: MCOperand::createImm(Val: 0));
2096 OutInst.setLoc(MI.getLoc());
2097 return true;
2098 } // if
2099 break;
2100 } // case C_JR
2101 case RISCV::C_LBU: {
2102 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2103 (MI.getOperand(i: 0).isReg()) &&
2104 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2105 (MI.getOperand(i: 1).isReg()) &&
2106 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2107 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2108 // lbu $rd, ${imm12}(${rs1})
2109 OutInst.setOpcode(RISCV::LBU);
2110 // Operand: rd
2111 OutInst.addOperand(Op: MI.getOperand(i: 0));
2112 // Operand: rs1
2113 OutInst.addOperand(Op: MI.getOperand(i: 1));
2114 // Operand: imm12
2115 OutInst.addOperand(Op: MI.getOperand(i: 2));
2116 OutInst.setLoc(MI.getLoc());
2117 return true;
2118 } // if
2119 break;
2120 } // case C_LBU
2121 case RISCV::C_LD: {
2122 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2123 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2124 (MI.getOperand(i: 0).isReg()) &&
2125 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2126 (MI.getOperand(i: 1).isReg()) &&
2127 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2128 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2129 // ld $rd, ${imm12}(${rs1})
2130 OutInst.setOpcode(RISCV::LD);
2131 // Operand: rd
2132 OutInst.addOperand(Op: MI.getOperand(i: 0));
2133 // Operand: rs1
2134 OutInst.addOperand(Op: MI.getOperand(i: 1));
2135 // Operand: imm12
2136 OutInst.addOperand(Op: MI.getOperand(i: 2));
2137 OutInst.setLoc(MI.getLoc());
2138 return true;
2139 } // if
2140 break;
2141 } // case C_LD
2142 case RISCV::C_LDSP: {
2143 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2144 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2145 (MI.getOperand(i: 0).isReg()) &&
2146 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2147 (MI.getOperand(i: 1).isReg()) &&
2148 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2149 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2150 // ld $rd, ${imm12}(${rs1})
2151 OutInst.setOpcode(RISCV::LD);
2152 // Operand: rd
2153 OutInst.addOperand(Op: MI.getOperand(i: 0));
2154 // Operand: rs1
2155 OutInst.addOperand(Op: MI.getOperand(i: 1));
2156 // Operand: imm12
2157 OutInst.addOperand(Op: MI.getOperand(i: 2));
2158 OutInst.setLoc(MI.getLoc());
2159 return true;
2160 } // if
2161 break;
2162 } // case C_LDSP
2163 case RISCV::C_LH: {
2164 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2165 (MI.getOperand(i: 0).isReg()) &&
2166 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2167 (MI.getOperand(i: 1).isReg()) &&
2168 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2169 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2170 // lh $rd, ${imm12}(${rs1})
2171 OutInst.setOpcode(RISCV::LH);
2172 // Operand: rd
2173 OutInst.addOperand(Op: MI.getOperand(i: 0));
2174 // Operand: rs1
2175 OutInst.addOperand(Op: MI.getOperand(i: 1));
2176 // Operand: imm12
2177 OutInst.addOperand(Op: MI.getOperand(i: 2));
2178 OutInst.setLoc(MI.getLoc());
2179 return true;
2180 } // if
2181 break;
2182 } // case C_LH
2183 case RISCV::C_LHU: {
2184 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2185 (MI.getOperand(i: 0).isReg()) &&
2186 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2187 (MI.getOperand(i: 1).isReg()) &&
2188 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2189 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2190 // lhu $rd, ${imm12}(${rs1})
2191 OutInst.setOpcode(RISCV::LHU);
2192 // Operand: rd
2193 OutInst.addOperand(Op: MI.getOperand(i: 0));
2194 // Operand: rs1
2195 OutInst.addOperand(Op: MI.getOperand(i: 1));
2196 // Operand: imm12
2197 OutInst.addOperand(Op: MI.getOperand(i: 2));
2198 OutInst.setLoc(MI.getLoc());
2199 return true;
2200 } // if
2201 break;
2202 } // case C_LHU
2203 case RISCV::C_LI: {
2204 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2205 (MI.getOperand(i: 0).isReg()) &&
2206 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2207 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 1)) {
2208 // addi $rd, $rs1, $imm12
2209 OutInst.setOpcode(RISCV::ADDI);
2210 // Operand: rd
2211 OutInst.addOperand(Op: MI.getOperand(i: 0));
2212 // Operand: rs1
2213 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2214 // Operand: imm12
2215 OutInst.addOperand(Op: MI.getOperand(i: 1));
2216 OutInst.setLoc(MI.getLoc());
2217 return true;
2218 } // if
2219 break;
2220 } // case C_LI
2221 case RISCV::C_LUI: {
2222 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2223 (MI.getOperand(i: 0).isReg()) &&
2224 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2225 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 1), STI, PredicateIndex: 4)) {
2226 // lui $rd, $imm20
2227 OutInst.setOpcode(RISCV::LUI);
2228 // Operand: rd
2229 OutInst.addOperand(Op: MI.getOperand(i: 0));
2230 // Operand: imm20
2231 OutInst.addOperand(Op: MI.getOperand(i: 1));
2232 OutInst.setLoc(MI.getLoc());
2233 return true;
2234 } // if
2235 break;
2236 } // case C_LUI
2237 case RISCV::C_LW: {
2238 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2239 (MI.getOperand(i: 0).isReg()) &&
2240 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2241 (MI.getOperand(i: 1).isReg()) &&
2242 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2243 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2244 // lw $rd, ${imm12}(${rs1})
2245 OutInst.setOpcode(RISCV::LW);
2246 // Operand: rd
2247 OutInst.addOperand(Op: MI.getOperand(i: 0));
2248 // Operand: rs1
2249 OutInst.addOperand(Op: MI.getOperand(i: 1));
2250 // Operand: imm12
2251 OutInst.addOperand(Op: MI.getOperand(i: 2));
2252 OutInst.setLoc(MI.getLoc());
2253 return true;
2254 } // if
2255 break;
2256 } // case C_LW
2257 case RISCV::C_LWSP: {
2258 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2259 (MI.getOperand(i: 0).isReg()) &&
2260 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2261 (MI.getOperand(i: 1).isReg()) &&
2262 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2263 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2264 // lw $rd, ${imm12}(${rs1})
2265 OutInst.setOpcode(RISCV::LW);
2266 // Operand: rd
2267 OutInst.addOperand(Op: MI.getOperand(i: 0));
2268 // Operand: rs1
2269 OutInst.addOperand(Op: MI.getOperand(i: 1));
2270 // Operand: imm12
2271 OutInst.addOperand(Op: MI.getOperand(i: 2));
2272 OutInst.setLoc(MI.getLoc());
2273 return true;
2274 } // if
2275 break;
2276 } // case C_LWSP
2277 case RISCV::C_MUL: {
2278 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2279 STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
2280 (MI.getOperand(i: 0).isReg()) &&
2281 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2282 (MI.getOperand(i: 0).isReg()) &&
2283 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2284 (MI.getOperand(i: 2).isReg()) &&
2285 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
2286 // mul $rd, $rs1, $rs2
2287 OutInst.setOpcode(RISCV::MUL);
2288 // Operand: rd
2289 OutInst.addOperand(Op: MI.getOperand(i: 0));
2290 // Operand: rs1
2291 OutInst.addOperand(Op: MI.getOperand(i: 0));
2292 // Operand: rs2
2293 OutInst.addOperand(Op: MI.getOperand(i: 2));
2294 OutInst.setLoc(MI.getLoc());
2295 return true;
2296 } // if
2297 break;
2298 } // case C_MUL
2299 case RISCV::C_MV: {
2300 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2301 (MI.getOperand(i: 0).isReg()) &&
2302 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2303 (MI.getOperand(i: 1).isReg()) &&
2304 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2305 RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 1)) {
2306 // addi $rd, $rs1, $imm12
2307 OutInst.setOpcode(RISCV::ADDI);
2308 // Operand: rd
2309 OutInst.addOperand(Op: MI.getOperand(i: 0));
2310 // Operand: rs1
2311 OutInst.addOperand(Op: MI.getOperand(i: 1));
2312 // Operand: imm12
2313 OutInst.addOperand(Op: MCOperand::createImm(Val: 0));
2314 OutInst.setLoc(MI.getLoc());
2315 return true;
2316 } // if
2317 break;
2318 } // case C_MV
2319 case RISCV::C_NOP: {
2320 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2321 RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 0), STI, PredicateIndex: 1)) {
2322 // addi $rd, $rs1, $imm12
2323 OutInst.setOpcode(RISCV::ADDI);
2324 // Operand: rd
2325 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2326 // Operand: rs1
2327 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2328 // Operand: imm12
2329 OutInst.addOperand(Op: MCOperand::createImm(Val: 0));
2330 OutInst.setLoc(MI.getLoc());
2331 return true;
2332 } // if
2333 break;
2334 } // case C_NOP
2335 case RISCV::C_NOT: {
2336 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2337 (MI.getOperand(i: 0).isReg()) &&
2338 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2339 (MI.getOperand(i: 0).isReg()) &&
2340 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2341 RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: -1), STI, PredicateIndex: 1)) {
2342 // xori $rd, $rs1, $imm12
2343 OutInst.setOpcode(RISCV::XORI);
2344 // Operand: rd
2345 OutInst.addOperand(Op: MI.getOperand(i: 0));
2346 // Operand: rs1
2347 OutInst.addOperand(Op: MI.getOperand(i: 0));
2348 // Operand: imm12
2349 OutInst.addOperand(Op: MCOperand::createImm(Val: -1));
2350 OutInst.setLoc(MI.getLoc());
2351 return true;
2352 } // if
2353 break;
2354 } // case C_NOT
2355 case RISCV::C_OR: {
2356 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2357 (MI.getOperand(i: 0).isReg()) &&
2358 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2359 (MI.getOperand(i: 0).isReg()) &&
2360 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2361 (MI.getOperand(i: 2).isReg()) &&
2362 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
2363 // or $rd, $rs1, $rs2
2364 OutInst.setOpcode(RISCV::OR);
2365 // Operand: rd
2366 OutInst.addOperand(Op: MI.getOperand(i: 0));
2367 // Operand: rs1
2368 OutInst.addOperand(Op: MI.getOperand(i: 0));
2369 // Operand: rs2
2370 OutInst.addOperand(Op: MI.getOperand(i: 2));
2371 OutInst.setLoc(MI.getLoc());
2372 return true;
2373 } // if
2374 break;
2375 } // case C_OR
2376 case RISCV::C_SB: {
2377 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2378 (MI.getOperand(i: 0).isReg()) &&
2379 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2380 (MI.getOperand(i: 1).isReg()) &&
2381 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2382 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2383 // sb $rs2, ${imm12}(${rs1})
2384 OutInst.setOpcode(RISCV::SB);
2385 // Operand: rs2
2386 OutInst.addOperand(Op: MI.getOperand(i: 0));
2387 // Operand: rs1
2388 OutInst.addOperand(Op: MI.getOperand(i: 1));
2389 // Operand: imm12
2390 OutInst.addOperand(Op: MI.getOperand(i: 2));
2391 OutInst.setLoc(MI.getLoc());
2392 return true;
2393 } // if
2394 break;
2395 } // case C_SB
2396 case RISCV::C_SD: {
2397 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2398 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2399 (MI.getOperand(i: 0).isReg()) &&
2400 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2401 (MI.getOperand(i: 1).isReg()) &&
2402 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2403 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2404 // sd $rs2, ${imm12}(${rs1})
2405 OutInst.setOpcode(RISCV::SD);
2406 // Operand: rs2
2407 OutInst.addOperand(Op: MI.getOperand(i: 0));
2408 // Operand: rs1
2409 OutInst.addOperand(Op: MI.getOperand(i: 1));
2410 // Operand: imm12
2411 OutInst.addOperand(Op: MI.getOperand(i: 2));
2412 OutInst.setLoc(MI.getLoc());
2413 return true;
2414 } // if
2415 break;
2416 } // case C_SD
2417 case RISCV::C_SDSP: {
2418 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2419 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2420 (MI.getOperand(i: 0).isReg()) &&
2421 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2422 (MI.getOperand(i: 1).isReg()) &&
2423 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2424 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2425 // sd $rs2, ${imm12}(${rs1})
2426 OutInst.setOpcode(RISCV::SD);
2427 // Operand: rs2
2428 OutInst.addOperand(Op: MI.getOperand(i: 0));
2429 // Operand: rs1
2430 OutInst.addOperand(Op: MI.getOperand(i: 1));
2431 // Operand: imm12
2432 OutInst.addOperand(Op: MI.getOperand(i: 2));
2433 OutInst.setLoc(MI.getLoc());
2434 return true;
2435 } // if
2436 break;
2437 } // case C_SDSP
2438 case RISCV::C_SEXT_B: {
2439 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2440 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2441 (MI.getOperand(i: 0).isReg()) &&
2442 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2443 (MI.getOperand(i: 0).isReg()) &&
2444 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg()))) {
2445 // sext.b $rd, $rs1
2446 OutInst.setOpcode(RISCV::SEXT_B);
2447 // Operand: rd
2448 OutInst.addOperand(Op: MI.getOperand(i: 0));
2449 // Operand: rs1
2450 OutInst.addOperand(Op: MI.getOperand(i: 0));
2451 OutInst.setLoc(MI.getLoc());
2452 return true;
2453 } // if
2454 break;
2455 } // case C_SEXT_B
2456 case RISCV::C_SEXT_H: {
2457 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2458 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2459 (MI.getOperand(i: 0).isReg()) &&
2460 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2461 (MI.getOperand(i: 0).isReg()) &&
2462 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg()))) {
2463 // sext.h $rd, $rs1
2464 OutInst.setOpcode(RISCV::SEXT_H);
2465 // Operand: rd
2466 OutInst.addOperand(Op: MI.getOperand(i: 0));
2467 // Operand: rs1
2468 OutInst.addOperand(Op: MI.getOperand(i: 0));
2469 OutInst.setLoc(MI.getLoc());
2470 return true;
2471 } // if
2472 break;
2473 } // case C_SEXT_H
2474 case RISCV::C_SH: {
2475 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2476 (MI.getOperand(i: 0).isReg()) &&
2477 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2478 (MI.getOperand(i: 1).isReg()) &&
2479 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2480 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2481 // sh $rs2, ${imm12}(${rs1})
2482 OutInst.setOpcode(RISCV::SH);
2483 // Operand: rs2
2484 OutInst.addOperand(Op: MI.getOperand(i: 0));
2485 // Operand: rs1
2486 OutInst.addOperand(Op: MI.getOperand(i: 1));
2487 // Operand: imm12
2488 OutInst.addOperand(Op: MI.getOperand(i: 2));
2489 OutInst.setLoc(MI.getLoc());
2490 return true;
2491 } // if
2492 break;
2493 } // case C_SH
2494 case RISCV::C_SLLI: {
2495 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2496 (MI.getOperand(i: 0).isReg()) &&
2497 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2498 (MI.getOperand(i: 0).isReg()) &&
2499 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2500 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
2501 // slli $rd, $rs1, $shamt
2502 OutInst.setOpcode(RISCV::SLLI);
2503 // Operand: rd
2504 OutInst.addOperand(Op: MI.getOperand(i: 0));
2505 // Operand: rs1
2506 OutInst.addOperand(Op: MI.getOperand(i: 0));
2507 // Operand: shamt
2508 OutInst.addOperand(Op: MI.getOperand(i: 2));
2509 OutInst.setLoc(MI.getLoc());
2510 return true;
2511 } // if
2512 break;
2513 } // case C_SLLI
2514 case RISCV::C_SRAI: {
2515 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2516 (MI.getOperand(i: 0).isReg()) &&
2517 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2518 (MI.getOperand(i: 0).isReg()) &&
2519 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2520 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
2521 // srai $rd, $rs1, $shamt
2522 OutInst.setOpcode(RISCV::SRAI);
2523 // Operand: rd
2524 OutInst.addOperand(Op: MI.getOperand(i: 0));
2525 // Operand: rs1
2526 OutInst.addOperand(Op: MI.getOperand(i: 0));
2527 // Operand: shamt
2528 OutInst.addOperand(Op: MI.getOperand(i: 2));
2529 OutInst.setLoc(MI.getLoc());
2530 return true;
2531 } // if
2532 break;
2533 } // case C_SRAI
2534 case RISCV::C_SRLI: {
2535 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2536 (MI.getOperand(i: 0).isReg()) &&
2537 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2538 (MI.getOperand(i: 0).isReg()) &&
2539 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2540 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 5)) {
2541 // srli $rd, $rs1, $shamt
2542 OutInst.setOpcode(RISCV::SRLI);
2543 // Operand: rd
2544 OutInst.addOperand(Op: MI.getOperand(i: 0));
2545 // Operand: rs1
2546 OutInst.addOperand(Op: MI.getOperand(i: 0));
2547 // Operand: shamt
2548 OutInst.addOperand(Op: MI.getOperand(i: 2));
2549 OutInst.setLoc(MI.getLoc());
2550 return true;
2551 } // if
2552 break;
2553 } // case C_SRLI
2554 case RISCV::C_SSPOPCHK: {
2555 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2556 STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
2557 (MI.getOperand(i: 0).isReg()) &&
2558 (MI.getOperand(i: 0).getReg() == RISCV::X5)) {
2559 // sspopchk $rs1
2560 OutInst.setOpcode(RISCV::SSPOPCHK);
2561 // Operand: rs1
2562 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
2563 OutInst.setLoc(MI.getLoc());
2564 return true;
2565 } // if
2566 break;
2567 } // case C_SSPOPCHK
2568 case RISCV::C_SSPUSH: {
2569 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2570 STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
2571 (MI.getOperand(i: 0).isReg()) &&
2572 (MI.getOperand(i: 0).getReg() == RISCV::X1)) {
2573 // sspush $rs2
2574 OutInst.setOpcode(RISCV::SSPUSH);
2575 // Operand: rs2
2576 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
2577 OutInst.setLoc(MI.getLoc());
2578 return true;
2579 } // if
2580 break;
2581 } // case C_SSPUSH
2582 case RISCV::C_SUB: {
2583 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2584 (MI.getOperand(i: 0).isReg()) &&
2585 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2586 (MI.getOperand(i: 0).isReg()) &&
2587 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2588 (MI.getOperand(i: 2).isReg()) &&
2589 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
2590 // sub $rd, $rs1, $rs2
2591 OutInst.setOpcode(RISCV::SUB);
2592 // Operand: rd
2593 OutInst.addOperand(Op: MI.getOperand(i: 0));
2594 // Operand: rs1
2595 OutInst.addOperand(Op: MI.getOperand(i: 0));
2596 // Operand: rs2
2597 OutInst.addOperand(Op: MI.getOperand(i: 2));
2598 OutInst.setLoc(MI.getLoc());
2599 return true;
2600 } // if
2601 break;
2602 } // case C_SUB
2603 case RISCV::C_SUBW: {
2604 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2605 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2606 (MI.getOperand(i: 0).isReg()) &&
2607 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2608 (MI.getOperand(i: 0).isReg()) &&
2609 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2610 (MI.getOperand(i: 2).isReg()) &&
2611 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
2612 // subw $rd, $rs1, $rs2
2613 OutInst.setOpcode(RISCV::SUBW);
2614 // Operand: rd
2615 OutInst.addOperand(Op: MI.getOperand(i: 0));
2616 // Operand: rs1
2617 OutInst.addOperand(Op: MI.getOperand(i: 0));
2618 // Operand: rs2
2619 OutInst.addOperand(Op: MI.getOperand(i: 2));
2620 OutInst.setLoc(MI.getLoc());
2621 return true;
2622 } // if
2623 break;
2624 } // case C_SUBW
2625 case RISCV::C_SW: {
2626 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2627 (MI.getOperand(i: 0).isReg()) &&
2628 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2629 (MI.getOperand(i: 1).isReg()) &&
2630 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2631 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2632 // sw $rs2, ${imm12}(${rs1})
2633 OutInst.setOpcode(RISCV::SW);
2634 // Operand: rs2
2635 OutInst.addOperand(Op: MI.getOperand(i: 0));
2636 // Operand: rs1
2637 OutInst.addOperand(Op: MI.getOperand(i: 1));
2638 // Operand: imm12
2639 OutInst.addOperand(Op: MI.getOperand(i: 2));
2640 OutInst.setLoc(MI.getLoc());
2641 return true;
2642 } // if
2643 break;
2644 } // case C_SW
2645 case RISCV::C_SWSP: {
2646 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2647 (MI.getOperand(i: 0).isReg()) &&
2648 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2649 (MI.getOperand(i: 1).isReg()) &&
2650 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2651 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2652 // sw $rs2, ${imm12}(${rs1})
2653 OutInst.setOpcode(RISCV::SW);
2654 // Operand: rs2
2655 OutInst.addOperand(Op: MI.getOperand(i: 0));
2656 // Operand: rs1
2657 OutInst.addOperand(Op: MI.getOperand(i: 1));
2658 // Operand: imm12
2659 OutInst.addOperand(Op: MI.getOperand(i: 2));
2660 OutInst.setLoc(MI.getLoc());
2661 return true;
2662 } // if
2663 break;
2664 } // case C_SWSP
2665 case RISCV::C_UNIMP: {
2666 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
2667 // unimp
2668 OutInst.setOpcode(RISCV::UNIMP);
2669 OutInst.setLoc(MI.getLoc());
2670 return true;
2671 } // if
2672 break;
2673 } // case C_UNIMP
2674 case RISCV::C_XOR: {
2675 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2676 (MI.getOperand(i: 0).isReg()) &&
2677 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2678 (MI.getOperand(i: 0).isReg()) &&
2679 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2680 (MI.getOperand(i: 2).isReg()) &&
2681 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 2).getReg()))) {
2682 // xor $rd, $rs1, $rs2
2683 OutInst.setOpcode(RISCV::XOR);
2684 // Operand: rd
2685 OutInst.addOperand(Op: MI.getOperand(i: 0));
2686 // Operand: rs1
2687 OutInst.addOperand(Op: MI.getOperand(i: 0));
2688 // Operand: rs2
2689 OutInst.addOperand(Op: MI.getOperand(i: 2));
2690 OutInst.setLoc(MI.getLoc());
2691 return true;
2692 } // if
2693 break;
2694 } // case C_XOR
2695 case RISCV::C_ZEXT_B: {
2696 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2697 (MI.getOperand(i: 0).isReg()) &&
2698 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2699 (MI.getOperand(i: 0).isReg()) &&
2700 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2701 RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: 255), STI, PredicateIndex: 1)) {
2702 // andi $rd, $rs1, $imm12
2703 OutInst.setOpcode(RISCV::ANDI);
2704 // Operand: rd
2705 OutInst.addOperand(Op: MI.getOperand(i: 0));
2706 // Operand: rs1
2707 OutInst.addOperand(Op: MI.getOperand(i: 0));
2708 // Operand: imm12
2709 OutInst.addOperand(Op: MCOperand::createImm(Val: 255));
2710 OutInst.setLoc(MI.getLoc());
2711 return true;
2712 } // if
2713 break;
2714 } // case C_ZEXT_B
2715 case RISCV::C_ZEXT_H: {
2716 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2717 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2718 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
2719 (MI.getOperand(i: 0).isReg()) &&
2720 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2721 (MI.getOperand(i: 0).isReg()) &&
2722 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg()))) {
2723 // zext.h $rd, $rs1
2724 OutInst.setOpcode(RISCV::ZEXT_H_RV32);
2725 // Operand: rd
2726 OutInst.addOperand(Op: MI.getOperand(i: 0));
2727 // Operand: rs1
2728 OutInst.addOperand(Op: MI.getOperand(i: 0));
2729 OutInst.setLoc(MI.getLoc());
2730 return true;
2731 } // if
2732 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2733 STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2734 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2735 (MI.getOperand(i: 0).isReg()) &&
2736 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2737 (MI.getOperand(i: 0).isReg()) &&
2738 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg()))) {
2739 // zext.h $rd, $rs1
2740 OutInst.setOpcode(RISCV::ZEXT_H_RV64);
2741 // Operand: rd
2742 OutInst.addOperand(Op: MI.getOperand(i: 0));
2743 // Operand: rs1
2744 OutInst.addOperand(Op: MI.getOperand(i: 0));
2745 OutInst.setLoc(MI.getLoc());
2746 return true;
2747 } // if
2748 break;
2749 } // case C_ZEXT_H
2750 case RISCV::C_ZEXT_W: {
2751 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2752 STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2753 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2754 (MI.getOperand(i: 0).isReg()) &&
2755 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2756 (MI.getOperand(i: 0).isReg()) &&
2757 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg()))) {
2758 // add.uw $rd, $rs1, $rs2
2759 OutInst.setOpcode(RISCV::ADD_UW);
2760 // Operand: rd
2761 OutInst.addOperand(Op: MI.getOperand(i: 0));
2762 // Operand: rs1
2763 OutInst.addOperand(Op: MI.getOperand(i: 0));
2764 // Operand: rs2
2765 OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2766 OutInst.setLoc(MI.getLoc());
2767 return true;
2768 } // if
2769 break;
2770 } // case C_ZEXT_W
2771 case RISCV::QK_C_LBU: {
2772 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2773 (MI.getOperand(i: 0).isReg()) &&
2774 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2775 (MI.getOperand(i: 1).isReg()) &&
2776 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2777 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2778 // lbu $rd, ${imm12}(${rs1})
2779 OutInst.setOpcode(RISCV::LBU);
2780 // Operand: rd
2781 OutInst.addOperand(Op: MI.getOperand(i: 0));
2782 // Operand: rs1
2783 OutInst.addOperand(Op: MI.getOperand(i: 1));
2784 // Operand: imm12
2785 OutInst.addOperand(Op: MI.getOperand(i: 2));
2786 OutInst.setLoc(MI.getLoc());
2787 return true;
2788 } // if
2789 break;
2790 } // case QK_C_LBU
2791 case RISCV::QK_C_LBUSP: {
2792 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2793 (MI.getOperand(i: 0).isReg()) &&
2794 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2795 (MI.getOperand(i: 1).isReg()) &&
2796 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2797 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2798 // lbu $rd, ${imm12}(${rs1})
2799 OutInst.setOpcode(RISCV::LBU);
2800 // Operand: rd
2801 OutInst.addOperand(Op: MI.getOperand(i: 0));
2802 // Operand: rs1
2803 OutInst.addOperand(Op: MI.getOperand(i: 1));
2804 // Operand: imm12
2805 OutInst.addOperand(Op: MI.getOperand(i: 2));
2806 OutInst.setLoc(MI.getLoc());
2807 return true;
2808 } // if
2809 break;
2810 } // case QK_C_LBUSP
2811 case RISCV::QK_C_LHU: {
2812 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2813 (MI.getOperand(i: 0).isReg()) &&
2814 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2815 (MI.getOperand(i: 1).isReg()) &&
2816 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2817 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2818 // lhu $rd, ${imm12}(${rs1})
2819 OutInst.setOpcode(RISCV::LHU);
2820 // Operand: rd
2821 OutInst.addOperand(Op: MI.getOperand(i: 0));
2822 // Operand: rs1
2823 OutInst.addOperand(Op: MI.getOperand(i: 1));
2824 // Operand: imm12
2825 OutInst.addOperand(Op: MI.getOperand(i: 2));
2826 OutInst.setLoc(MI.getLoc());
2827 return true;
2828 } // if
2829 break;
2830 } // case QK_C_LHU
2831 case RISCV::QK_C_LHUSP: {
2832 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2833 (MI.getOperand(i: 0).isReg()) &&
2834 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2835 (MI.getOperand(i: 1).isReg()) &&
2836 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2837 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2838 // lhu $rd, ${imm12}(${rs1})
2839 OutInst.setOpcode(RISCV::LHU);
2840 // Operand: rd
2841 OutInst.addOperand(Op: MI.getOperand(i: 0));
2842 // Operand: rs1
2843 OutInst.addOperand(Op: MI.getOperand(i: 1));
2844 // Operand: imm12
2845 OutInst.addOperand(Op: MI.getOperand(i: 2));
2846 OutInst.setLoc(MI.getLoc());
2847 return true;
2848 } // if
2849 break;
2850 } // case QK_C_LHUSP
2851 case RISCV::QK_C_SB: {
2852 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2853 (MI.getOperand(i: 0).isReg()) &&
2854 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2855 (MI.getOperand(i: 1).isReg()) &&
2856 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2857 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2858 // sb $rs2, ${imm12}(${rs1})
2859 OutInst.setOpcode(RISCV::SB);
2860 // Operand: rs2
2861 OutInst.addOperand(Op: MI.getOperand(i: 0));
2862 // Operand: rs1
2863 OutInst.addOperand(Op: MI.getOperand(i: 1));
2864 // Operand: imm12
2865 OutInst.addOperand(Op: MI.getOperand(i: 2));
2866 OutInst.setLoc(MI.getLoc());
2867 return true;
2868 } // if
2869 break;
2870 } // case QK_C_SB
2871 case RISCV::QK_C_SBSP: {
2872 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2873 (MI.getOperand(i: 0).isReg()) &&
2874 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2875 (MI.getOperand(i: 1).isReg()) &&
2876 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2877 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2878 // sb $rs2, ${imm12}(${rs1})
2879 OutInst.setOpcode(RISCV::SB);
2880 // Operand: rs2
2881 OutInst.addOperand(Op: MI.getOperand(i: 0));
2882 // Operand: rs1
2883 OutInst.addOperand(Op: MI.getOperand(i: 1));
2884 // Operand: imm12
2885 OutInst.addOperand(Op: MI.getOperand(i: 2));
2886 OutInst.setLoc(MI.getLoc());
2887 return true;
2888 } // if
2889 break;
2890 } // case QK_C_SBSP
2891 case RISCV::QK_C_SH: {
2892 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2893 (MI.getOperand(i: 0).isReg()) &&
2894 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2895 (MI.getOperand(i: 1).isReg()) &&
2896 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2897 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2898 // sh $rs2, ${imm12}(${rs1})
2899 OutInst.setOpcode(RISCV::SH);
2900 // Operand: rs2
2901 OutInst.addOperand(Op: MI.getOperand(i: 0));
2902 // Operand: rs1
2903 OutInst.addOperand(Op: MI.getOperand(i: 1));
2904 // Operand: imm12
2905 OutInst.addOperand(Op: MI.getOperand(i: 2));
2906 OutInst.setLoc(MI.getLoc());
2907 return true;
2908 } // if
2909 break;
2910 } // case QK_C_SH
2911 case RISCV::QK_C_SHSP: {
2912 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2913 (MI.getOperand(i: 0).isReg()) &&
2914 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 0).getReg())) &&
2915 (MI.getOperand(i: 1).isReg()) &&
2916 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: 1).getReg())) &&
2917 RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: 2), STI, PredicateIndex: 1)) {
2918 // sh $rs2, ${imm12}(${rs1})
2919 OutInst.setOpcode(RISCV::SH);
2920 // Operand: rs2
2921 OutInst.addOperand(Op: MI.getOperand(i: 0));
2922 // Operand: rs1
2923 OutInst.addOperand(Op: MI.getOperand(i: 1));
2924 // Operand: imm12
2925 OutInst.addOperand(Op: MI.getOperand(i: 2));
2926 OutInst.setLoc(MI.getLoc());
2927 return true;
2928 } // if
2929
2930 } // case QK_C_SHSP
2931 } // switch
2932 return false;
2933}
2934
2935#endif //GEN_UNCOMPRESS_INSTR
2936
2937
2938#ifdef GEN_CHECK_COMPRESS_INSTR
2939#undef GEN_CHECK_COMPRESS_INSTR
2940
2941static bool RISCVValidateMachineOperand(const MachineOperand &MO,
2942 const RISCVSubtarget *Subtarget,
2943 unsigned PredicateIndex) {
2944 int64_t Imm = MO.getImm();
2945 switch (PredicateIndex) {
2946 default:
2947 llvm_unreachable("Unknown ImmLeaf Predicate kind");
2948 break;
2949 case 1: {
2950 // simm6nonzero
2951 return (Imm != 0) && isInt<6>(Imm);
2952 }
2953 case 2: {
2954 // simm10_lsb0000nonzero
2955 return (Imm != 0) && isShiftedInt<6, 4>(Imm);
2956 }
2957 case 3: {
2958 // uimm10_lsb00nonzero
2959 return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
2960 }
2961 case 4: {
2962 // simm6
2963 return isInt<6>(Imm);
2964 }
2965 case 5: {
2966 // simm9_lsb0
2967 return isShiftedInt<8, 1>(Imm);
2968 }
2969 case 6: {
2970 // uimm8_lsb000
2971 return isShiftedUInt<5, 3>(Imm);
2972 }
2973 case 7: {
2974 // uimm9_lsb000
2975 return isShiftedUInt<6, 3>(Imm);
2976 }
2977 case 8: {
2978 // uimm7_lsb00
2979 return isShiftedUInt<5, 2>(Imm);
2980 }
2981 case 9: {
2982 // uimm8_lsb00
2983 return isShiftedUInt<6, 2>(Imm);
2984 }
2985 case 10: {
2986 // simm12_lsb0
2987 return isShiftedInt<11, 1>(Imm);
2988 }
2989 case 11: {
2990 // uimm2
2991 return isUInt<2>(Imm);
2992 }
2993 case 12: {
2994 // uimm5_with_predicate
2995 return isUInt<5>(Imm);
2996 }
2997 case 13: {
2998 // uimm4_with_predicate
2999 return isUInt<4>(Imm);
3000 }
3001 case 14: {
3002 // uimm2_lsb0
3003 return isShiftedUInt<1, 1>(Imm);
3004 }
3005 case 15: {
3006 // uimm6_lsb0
3007 return isShiftedUInt<5, 1>(Imm);
3008 }
3009 case 16: {
3010 // uimm5_lsb0
3011 return isShiftedUInt<4, 1>(Imm);
3012 }
3013 case 17: {
3014 // c_lui_imm
3015 return (Imm != 0) &&
3016 (isUInt<5>(Imm) ||
3017 (Imm >= 0xfffe0 && Imm <= 0xfffff));
3018 }
3019 case 18: {
3020 // uimmlog2xlennonzero
3021
3022 if (Subtarget->is64Bit())
3023 return isUInt<6>(Imm) && (Imm != 0);
3024 return isUInt<5>(Imm) && (Imm != 0);
3025
3026 }
3027 }
3028}
3029
3030static bool isCompressibleInst(const MachineInstr &MI,
3031 const RISCVSubtarget &STI) {
3032 switch (MI.getOpcode()) {
3033 default: return false;
3034 case RISCV::ADD: {
3035 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3036 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3037 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3038 (MI.getOperand(1).isReg()) &&
3039 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
3040 (MI.getOperand(2).isReg()) &&
3041 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) {
3042 // c.add $rs1, $rs2
3043 // Operand: rs1_wb
3044 // Operand: rs1
3045 // Operand: rs2
3046 return true;
3047 } // if
3048 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3049 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3050 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
3051 (MI.getOperand(2).isReg()) &&
3052 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg())) &&
3053 (MI.getOperand(1).isReg()) &&
3054 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3055 // c.add $rs1, $rs2
3056 // Operand: rs1_wb
3057 // Operand: rs1
3058 // Operand: rs2
3059 return true;
3060 } // if
3061 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3062 (MI.getOperand(1).isReg()) &&
3063 (MI.getOperand(1).getReg() == RISCV::X0) &&
3064 (MI.getOperand(0).isReg()) &&
3065 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3066 (MI.getOperand(2).isReg()) &&
3067 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) {
3068 // c.mv $rs1, $rs2
3069 // Operand: rs1
3070 // Operand: rs2
3071 return true;
3072 } // if
3073 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3074 (MI.getOperand(2).isReg()) &&
3075 (MI.getOperand(2).getReg() == RISCV::X0) &&
3076 (MI.getOperand(0).isReg()) &&
3077 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3078 (MI.getOperand(1).isReg()) &&
3079 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3080 // c.mv $rs1, $rs2
3081 // Operand: rs1
3082 // Operand: rs2
3083 return true;
3084 } // if
3085 break;
3086 } // case ADD
3087 case RISCV::ADDI: {
3088 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3089 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3090 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3091 (MI.getOperand(1).isReg()) &&
3092 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
3093 MI.getOperand(2).isImm() &&
3094 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 1)) {
3095 // c.addi $rd, $imm
3096 // Operand: rd_wb
3097 // Operand: rd
3098 // Operand: imm
3099 return true;
3100 } // if
3101 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3102 (MI.getOperand(0).isReg()) &&
3103 (MI.getOperand(0).getReg() == RISCV::X2) &&
3104 (MI.getOperand(1).isReg()) &&
3105 (MI.getOperand(1).getReg() == RISCV::X2) &&
3106 MI.getOperand(2).isImm() &&
3107 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2)) {
3108 // c.addi16sp $rd, $imm
3109 // Operand: rd_wb
3110 // Operand: rd
3111 // Operand: imm
3112 return true;
3113 } // if
3114 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3115 (MI.getOperand(0).isReg()) &&
3116 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3117 (MI.getOperand(1).isReg()) &&
3118 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3119 MI.getOperand(2).isImm() &&
3120 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 3)) {
3121 // c.addi4spn $rd, $rs1, $imm
3122 // Operand: rd
3123 // Operand: rs1
3124 // Operand: imm
3125 return true;
3126 } // if
3127 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3128 (MI.getOperand(1).isReg()) &&
3129 (MI.getOperand(1).getReg() == RISCV::X0) &&
3130 (MI.getOperand(0).isReg()) &&
3131 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3132 MI.getOperand(2).isImm() &&
3133 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
3134 // c.li $rd, $imm
3135 // Operand: rd
3136 // Operand: imm
3137 return true;
3138 } // if
3139 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3140 (MI.getOperand(2).isImm()) &&
3141 (MI.getOperand(2).getImm() == 0) &&
3142 (MI.getOperand(0).isReg()) &&
3143 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3144 (MI.getOperand(1).isReg()) &&
3145 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3146 // c.mv $rs1, $rs2
3147 // Operand: rs1
3148 // Operand: rs2
3149 return true;
3150 } // if
3151 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3152 (MI.getOperand(0).isReg()) &&
3153 (MI.getOperand(0).getReg() == RISCV::X0) &&
3154 (MI.getOperand(1).isReg()) &&
3155 (MI.getOperand(1).getReg() == RISCV::X0) &&
3156 (MI.getOperand(2).isImm()) &&
3157 (MI.getOperand(2).getImm() == 0)) {
3158 // c.nop
3159 return true;
3160 } // if
3161 break;
3162 } // case ADDI
3163 case RISCV::ADDIW: {
3164 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3165 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3166 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3167 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3168 (MI.getOperand(1).isReg()) &&
3169 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
3170 MI.getOperand(2).isImm() &&
3171 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
3172 // c.addiw $rd, $imm
3173 // Operand: rd_wb
3174 // Operand: rd
3175 // Operand: imm
3176 return true;
3177 } // if
3178 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3179 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3180 (MI.getOperand(1).isReg()) &&
3181 (MI.getOperand(1).getReg() == RISCV::X0) &&
3182 (MI.getOperand(0).isReg()) &&
3183 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3184 MI.getOperand(2).isImm() &&
3185 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
3186 // c.li $rd, $imm
3187 // Operand: rd
3188 // Operand: imm
3189 return true;
3190 } // if
3191 break;
3192 } // case ADDIW
3193 case RISCV::ADDW: {
3194 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3195 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3196 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3197 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3198 (MI.getOperand(1).isReg()) &&
3199 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3200 (MI.getOperand(2).isReg()) &&
3201 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3202 // c.addw $rd, $rs2
3203 // Operand: rd_wb
3204 // Operand: rd
3205 // Operand: rs2
3206 return true;
3207 } // if
3208 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3209 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3210 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3211 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
3212 (MI.getOperand(2).isReg()) &&
3213 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3214 (MI.getOperand(1).isReg()) &&
3215 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3216 // c.addw $rd, $rs2
3217 // Operand: rd_wb
3218 // Operand: rd
3219 // Operand: rs2
3220 return true;
3221 } // if
3222 break;
3223 } // case ADDW
3224 case RISCV::ADD_UW: {
3225 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3226 STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
3227 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3228 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3229 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3230 (MI.getOperand(2).isReg()) &&
3231 (MI.getOperand(2).getReg() == RISCV::X0) &&
3232 (MI.getOperand(1).isReg()) &&
3233 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3234 // c.zext.w $rd
3235 // Operand: rd_wb
3236 // Operand: rd
3237 return true;
3238 } // if
3239 break;
3240 } // case ADD_UW
3241 case RISCV::AND: {
3242 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3243 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3244 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3245 (MI.getOperand(1).isReg()) &&
3246 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3247 (MI.getOperand(2).isReg()) &&
3248 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3249 // c.and $rd, $rs2
3250 // Operand: rd_wb
3251 // Operand: rd
3252 // Operand: rs2
3253 return true;
3254 } // if
3255 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3256 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3257 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
3258 (MI.getOperand(2).isReg()) &&
3259 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3260 (MI.getOperand(1).isReg()) &&
3261 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3262 // c.and $rd, $rs2
3263 // Operand: rd_wb
3264 // Operand: rd
3265 // Operand: rs2
3266 return true;
3267 } // if
3268 break;
3269 } // case AND
3270 case RISCV::ANDI: {
3271 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3272 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3273 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3274 (MI.getOperand(1).isReg()) &&
3275 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3276 MI.getOperand(2).isImm() &&
3277 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
3278 // c.andi $rs1, $imm
3279 // Operand: rs1_wb
3280 // Operand: rs1
3281 // Operand: imm
3282 return true;
3283 } // if
3284 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3285 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3286 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3287 (MI.getOperand(2).isImm()) &&
3288 (MI.getOperand(2).getImm() == 255) &&
3289 (MI.getOperand(1).isReg()) &&
3290 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3291 // c.zext.b $rd
3292 // Operand: rd_wb
3293 // Operand: rd
3294 return true;
3295 } // if
3296 break;
3297 } // case ANDI
3298 case RISCV::BEQ: {
3299 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3300 (MI.getOperand(1).isReg()) &&
3301 (MI.getOperand(1).getReg() == RISCV::X0) &&
3302 (MI.getOperand(0).isReg()) &&
3303 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3304 MI.getOperand(2).isImm() &&
3305 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
3306 // c.beqz $rs1, $imm
3307 // Operand: rs1
3308 // Operand: imm
3309 return true;
3310 } // if
3311 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3312 (MI.getOperand(0).isReg()) &&
3313 (MI.getOperand(0).getReg() == RISCV::X0) &&
3314 (MI.getOperand(1).isReg()) &&
3315 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3316 MI.getOperand(2).isImm() &&
3317 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
3318 // c.beqz $rs1, $imm
3319 // Operand: rs1
3320 // Operand: imm
3321 return true;
3322 } // if
3323 break;
3324 } // case BEQ
3325 case RISCV::BNE: {
3326 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3327 (MI.getOperand(1).isReg()) &&
3328 (MI.getOperand(1).getReg() == RISCV::X0) &&
3329 (MI.getOperand(0).isReg()) &&
3330 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3331 MI.getOperand(2).isImm() &&
3332 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
3333 // c.bnez $rs1, $imm
3334 // Operand: rs1
3335 // Operand: imm
3336 return true;
3337 } // if
3338 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3339 (MI.getOperand(0).isReg()) &&
3340 (MI.getOperand(0).getReg() == RISCV::X0) &&
3341 (MI.getOperand(1).isReg()) &&
3342 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3343 MI.getOperand(2).isImm() &&
3344 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
3345 // c.bnez $rs1, $imm
3346 // Operand: rs1
3347 // Operand: imm
3348 return true;
3349 } // if
3350 break;
3351 } // case BNE
3352 case RISCV::EBREAK: {
3353 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
3354 // c.ebreak
3355 return true;
3356 } // if
3357 break;
3358 } // case EBREAK
3359 case RISCV::FLD: {
3360 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3361 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3362 (MI.getOperand(0).isReg()) &&
3363 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) &&
3364 (MI.getOperand(1).isReg()) &&
3365 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3366 MI.getOperand(2).isImm() &&
3367 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3368 // c.fld $rd, ${imm}(${rs1})
3369 // Operand: rd
3370 // Operand: rs1
3371 // Operand: imm
3372 return true;
3373 } // if
3374 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3375 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3376 (MI.getOperand(0).isReg()) &&
3377 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
3378 (MI.getOperand(1).isReg()) &&
3379 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3380 MI.getOperand(2).isImm() &&
3381 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3382 // c.fldsp $rd, ${imm}(${rs1})
3383 // Operand: rd
3384 // Operand: rs1
3385 // Operand: imm
3386 return true;
3387 } // if
3388 break;
3389 } // case FLD
3390 case RISCV::FLW: {
3391 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3392 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3393 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3394 (MI.getOperand(0).isReg()) &&
3395 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) &&
3396 (MI.getOperand(1).isReg()) &&
3397 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3398 MI.getOperand(2).isImm() &&
3399 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3400 // c.flw $rd, ${imm}(${rs1})
3401 // Operand: rd
3402 // Operand: rs1
3403 // Operand: imm
3404 return true;
3405 } // if
3406 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3407 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3408 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3409 (MI.getOperand(0).isReg()) &&
3410 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
3411 (MI.getOperand(1).isReg()) &&
3412 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3413 MI.getOperand(2).isImm() &&
3414 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3415 // c.flwsp $rd, ${imm}(${rs1})
3416 // Operand: rd
3417 // Operand: rs1
3418 // Operand: imm
3419 return true;
3420 } // if
3421 break;
3422 } // case FLW
3423 case RISCV::FSD: {
3424 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3425 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3426 (MI.getOperand(0).isReg()) &&
3427 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) &&
3428 (MI.getOperand(1).isReg()) &&
3429 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3430 MI.getOperand(2).isImm() &&
3431 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3432 // c.fsd $rs2, ${imm}(${rs1})
3433 // Operand: rs2
3434 // Operand: rs1
3435 // Operand: imm
3436 return true;
3437 } // if
3438 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3439 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3440 (MI.getOperand(0).isReg()) &&
3441 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
3442 (MI.getOperand(1).isReg()) &&
3443 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3444 MI.getOperand(2).isImm() &&
3445 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3446 // c.fsdsp $rs2, ${imm}(${rs1})
3447 // Operand: rs2
3448 // Operand: rs1
3449 // Operand: imm
3450 return true;
3451 } // if
3452 break;
3453 } // case FSD
3454 case RISCV::FSW: {
3455 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3456 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3457 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3458 (MI.getOperand(0).isReg()) &&
3459 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) &&
3460 (MI.getOperand(1).isReg()) &&
3461 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3462 MI.getOperand(2).isImm() &&
3463 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3464 // c.fsw $rs2, ${imm}(${rs1})
3465 // Operand: rs2
3466 // Operand: rs1
3467 // Operand: imm
3468 return true;
3469 } // if
3470 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3471 !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3472 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3473 (MI.getOperand(0).isReg()) &&
3474 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
3475 (MI.getOperand(1).isReg()) &&
3476 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3477 MI.getOperand(2).isImm() &&
3478 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3479 // c.fswsp $rs2, ${imm}(${rs1})
3480 // Operand: rs2
3481 // Operand: rs1
3482 // Operand: imm
3483 return true;
3484 } // if
3485 break;
3486 } // case FSW
3487 case RISCV::JAL: {
3488 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3489 (MI.getOperand(0).isReg()) &&
3490 (MI.getOperand(0).getReg() == RISCV::X0) &&
3491 MI.getOperand(1).isImm() &&
3492 RISCVValidateMachineOperand(MI.getOperand(1), &STI, 10)) {
3493 // c.j $offset
3494 // Operand: offset
3495 return true;
3496 } // if
3497 if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3498 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3499 (MI.getOperand(0).isReg()) &&
3500 (MI.getOperand(0).getReg() == RISCV::X1) &&
3501 MI.getOperand(1).isImm() &&
3502 RISCVValidateMachineOperand(MI.getOperand(1), &STI, 10)) {
3503 // c.jal $offset
3504 // Operand: offset
3505 return true;
3506 } // if
3507 break;
3508 } // case JAL
3509 case RISCV::JALR: {
3510 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3511 (MI.getOperand(0).isReg()) &&
3512 (MI.getOperand(0).getReg() == RISCV::X1) &&
3513 (MI.getOperand(2).isImm()) &&
3514 (MI.getOperand(2).getImm() == 0) &&
3515 (MI.getOperand(1).isReg()) &&
3516 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3517 // c.jalr $rs1
3518 // Operand: rs1
3519 return true;
3520 } // if
3521 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3522 (MI.getOperand(0).isReg()) &&
3523 (MI.getOperand(0).getReg() == RISCV::X0) &&
3524 (MI.getOperand(2).isImm()) &&
3525 (MI.getOperand(2).getImm() == 0) &&
3526 (MI.getOperand(1).isReg()) &&
3527 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3528 // c.jr $rs1
3529 // Operand: rs1
3530 return true;
3531 } // if
3532 break;
3533 } // case JALR
3534 case RISCV::LBU: {
3535 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3536 (MI.getOperand(0).isReg()) &&
3537 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3538 (MI.getOperand(1).isReg()) &&
3539 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3540 MI.getOperand(2).isImm() &&
3541 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11)) {
3542 // c.lbu $rd, ${imm}(${rs1})
3543 // Operand: rd
3544 // Operand: rs1
3545 // Operand: imm
3546 return true;
3547 } // if
3548 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3549 (MI.getOperand(0).isReg()) &&
3550 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3551 (MI.getOperand(1).isReg()) &&
3552 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3553 MI.getOperand(2).isImm() &&
3554 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) {
3555 // qk.c.lbu $rd, ${imm}(${rs1})
3556 // Operand: rd
3557 // Operand: rs1
3558 // Operand: imm
3559 return true;
3560 } // if
3561 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3562 (MI.getOperand(0).isReg()) &&
3563 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3564 (MI.getOperand(1).isReg()) &&
3565 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3566 MI.getOperand(2).isImm() &&
3567 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13)) {
3568 // qk.c.lbusp $rd_rs2, ${imm}(${rs1})
3569 // Operand: rd_rs2
3570 // Operand: rs1
3571 // Operand: imm
3572 return true;
3573 } // if
3574 break;
3575 } // case LBU
3576 case RISCV::LD: {
3577 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3578 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3579 (MI.getOperand(0).isReg()) &&
3580 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3581 (MI.getOperand(1).isReg()) &&
3582 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3583 MI.getOperand(2).isImm() &&
3584 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3585 // c.ld $rd, ${imm}(${rs1})
3586 // Operand: rd
3587 // Operand: rs1
3588 // Operand: imm
3589 return true;
3590 } // if
3591 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3592 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3593 (MI.getOperand(0).isReg()) &&
3594 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3595 (MI.getOperand(1).isReg()) &&
3596 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3597 MI.getOperand(2).isImm() &&
3598 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3599 // c.ldsp $rd, ${imm}(${rs1})
3600 // Operand: rd
3601 // Operand: rs1
3602 // Operand: imm
3603 return true;
3604 } // if
3605 break;
3606 } // case LD
3607 case RISCV::LH: {
3608 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3609 (MI.getOperand(0).isReg()) &&
3610 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3611 (MI.getOperand(1).isReg()) &&
3612 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3613 MI.getOperand(2).isImm() &&
3614 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14)) {
3615 // c.lh $rd, ${imm}(${rs1})
3616 // Operand: rd
3617 // Operand: rs1
3618 // Operand: imm
3619 return true;
3620 } // if
3621 break;
3622 } // case LH
3623 case RISCV::LHU: {
3624 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3625 (MI.getOperand(0).isReg()) &&
3626 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3627 (MI.getOperand(1).isReg()) &&
3628 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3629 MI.getOperand(2).isImm() &&
3630 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14)) {
3631 // c.lhu $rd, ${imm}(${rs1})
3632 // Operand: rd
3633 // Operand: rs1
3634 // Operand: imm
3635 return true;
3636 } // if
3637 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3638 (MI.getOperand(0).isReg()) &&
3639 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3640 (MI.getOperand(1).isReg()) &&
3641 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3642 MI.getOperand(2).isImm() &&
3643 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 15)) {
3644 // qk.c.lhu $rd, ${imm}(${rs1})
3645 // Operand: rd
3646 // Operand: rs1
3647 // Operand: imm
3648 return true;
3649 } // if
3650 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3651 (MI.getOperand(0).isReg()) &&
3652 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3653 (MI.getOperand(1).isReg()) &&
3654 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3655 MI.getOperand(2).isImm() &&
3656 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 16)) {
3657 // qk.c.lhusp $rd_rs2, ${imm}(${rs1})
3658 // Operand: rd_rs2
3659 // Operand: rs1
3660 // Operand: imm
3661 return true;
3662 } // if
3663 break;
3664 } // case LHU
3665 case RISCV::LUI: {
3666 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3667 (MI.getOperand(0).isReg()) &&
3668 (RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(0).getReg())) &&
3669 MI.getOperand(1).isImm() &&
3670 RISCVValidateMachineOperand(MI.getOperand(1), &STI, 17)) {
3671 // c.lui $rd, $imm
3672 // Operand: rd
3673 // Operand: imm
3674 return true;
3675 } // if
3676 break;
3677 } // case LUI
3678 case RISCV::LW: {
3679 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3680 (MI.getOperand(0).isReg()) &&
3681 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3682 (MI.getOperand(1).isReg()) &&
3683 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3684 MI.getOperand(2).isImm() &&
3685 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3686 // c.lw $rd, ${imm}(${rs1})
3687 // Operand: rd
3688 // Operand: rs1
3689 // Operand: imm
3690 return true;
3691 } // if
3692 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3693 (MI.getOperand(0).isReg()) &&
3694 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3695 (MI.getOperand(1).isReg()) &&
3696 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3697 MI.getOperand(2).isImm() &&
3698 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3699 // c.lwsp $rd, ${imm}(${rs1})
3700 // Operand: rd
3701 // Operand: rs1
3702 // Operand: imm
3703 return true;
3704 } // if
3705 break;
3706 } // case LW
3707 case RISCV::MUL: {
3708 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3709 STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
3710 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3711 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3712 (MI.getOperand(1).isReg()) &&
3713 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3714 (MI.getOperand(2).isReg()) &&
3715 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3716 // c.mul $rd, $rs2
3717 // Operand: rd_wb
3718 // Operand: rd
3719 // Operand: rs2
3720 return true;
3721 } // if
3722 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3723 STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
3724 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3725 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
3726 (MI.getOperand(2).isReg()) &&
3727 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3728 (MI.getOperand(1).isReg()) &&
3729 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3730 // c.mul $rd, $rs2
3731 // Operand: rd_wb
3732 // Operand: rd
3733 // Operand: rs2
3734 return true;
3735 } // if
3736 break;
3737 } // case MUL
3738 case RISCV::OR: {
3739 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3740 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3741 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3742 (MI.getOperand(1).isReg()) &&
3743 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3744 (MI.getOperand(2).isReg()) &&
3745 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3746 // c.or $rd, $rs2
3747 // Operand: rd_wb
3748 // Operand: rd
3749 // Operand: rs2
3750 return true;
3751 } // if
3752 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3753 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3754 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
3755 (MI.getOperand(2).isReg()) &&
3756 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3757 (MI.getOperand(1).isReg()) &&
3758 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3759 // c.or $rd, $rs2
3760 // Operand: rd_wb
3761 // Operand: rd
3762 // Operand: rs2
3763 return true;
3764 } // if
3765 break;
3766 } // case OR
3767 case RISCV::SB: {
3768 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3769 (MI.getOperand(0).isReg()) &&
3770 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3771 (MI.getOperand(1).isReg()) &&
3772 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3773 MI.getOperand(2).isImm() &&
3774 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11)) {
3775 // c.sb $rs2, ${imm}(${rs1})
3776 // Operand: rs2
3777 // Operand: rs1
3778 // Operand: imm
3779 return true;
3780 } // if
3781 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3782 (MI.getOperand(0).isReg()) &&
3783 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3784 (MI.getOperand(1).isReg()) &&
3785 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3786 MI.getOperand(2).isImm() &&
3787 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) {
3788 // qk.c.sb $rs2, ${imm}(${rs1})
3789 // Operand: rs2
3790 // Operand: rs1
3791 // Operand: imm
3792 return true;
3793 } // if
3794 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3795 (MI.getOperand(0).isReg()) &&
3796 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3797 (MI.getOperand(1).isReg()) &&
3798 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3799 MI.getOperand(2).isImm() &&
3800 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 13)) {
3801 // qk.c.sbsp $rd_rs2, ${imm}(${rs1})
3802 // Operand: rd_rs2
3803 // Operand: rs1
3804 // Operand: imm
3805 return true;
3806 } // if
3807 break;
3808 } // case SB
3809 case RISCV::SD: {
3810 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3811 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3812 (MI.getOperand(0).isReg()) &&
3813 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3814 (MI.getOperand(1).isReg()) &&
3815 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3816 MI.getOperand(2).isImm() &&
3817 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3818 // c.sd $rs2, ${imm}(${rs1})
3819 // Operand: rs2
3820 // Operand: rs1
3821 // Operand: imm
3822 return true;
3823 } // if
3824 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3825 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3826 (MI.getOperand(0).isReg()) &&
3827 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
3828 (MI.getOperand(1).isReg()) &&
3829 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3830 MI.getOperand(2).isImm() &&
3831 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3832 // c.sdsp $rs2, ${imm}(${rs1})
3833 // Operand: rs2
3834 // Operand: rs1
3835 // Operand: imm
3836 return true;
3837 } // if
3838 break;
3839 } // case SD
3840 case RISCV::SEXT_B: {
3841 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3842 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3843 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3844 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3845 (MI.getOperand(1).isReg()) &&
3846 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3847 // c.sext.b $rd
3848 // Operand: rd_wb
3849 // Operand: rd
3850 return true;
3851 } // if
3852 break;
3853 } // case SEXT_B
3854 case RISCV::SEXT_H: {
3855 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3856 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3857 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3858 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3859 (MI.getOperand(1).isReg()) &&
3860 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3861 // c.sext.h $rd
3862 // Operand: rd_wb
3863 // Operand: rd
3864 return true;
3865 } // if
3866 break;
3867 } // case SEXT_H
3868 case RISCV::SH: {
3869 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3870 (MI.getOperand(0).isReg()) &&
3871 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3872 (MI.getOperand(1).isReg()) &&
3873 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3874 MI.getOperand(2).isImm() &&
3875 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14)) {
3876 // c.sh $rs2, ${imm}(${rs1})
3877 // Operand: rs2
3878 // Operand: rs1
3879 // Operand: imm
3880 return true;
3881 } // if
3882 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3883 (MI.getOperand(0).isReg()) &&
3884 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3885 (MI.getOperand(1).isReg()) &&
3886 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3887 MI.getOperand(2).isImm() &&
3888 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 15)) {
3889 // qk.c.sh $rs2, ${imm}(${rs1})
3890 // Operand: rs2
3891 // Operand: rs1
3892 // Operand: imm
3893 return true;
3894 } // if
3895 if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
3896 (MI.getOperand(0).isReg()) &&
3897 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3898 (MI.getOperand(1).isReg()) &&
3899 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3900 MI.getOperand(2).isImm() &&
3901 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 16)) {
3902 // qk.c.shsp $rd_rs2, ${imm}(${rs1})
3903 // Operand: rd_rs2
3904 // Operand: rs1
3905 // Operand: imm
3906 return true;
3907 } // if
3908 break;
3909 } // case SH
3910 case RISCV::SLLI: {
3911 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3912 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3913 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3914 (MI.getOperand(1).isReg()) &&
3915 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
3916 MI.getOperand(2).isImm() &&
3917 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 18)) {
3918 // c.slli $rd, $imm
3919 // Operand: rd_wb
3920 // Operand: rd
3921 // Operand: imm
3922 return true;
3923 } // if
3924 break;
3925 } // case SLLI
3926 case RISCV::SRAI: {
3927 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3928 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3929 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3930 (MI.getOperand(1).isReg()) &&
3931 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3932 MI.getOperand(2).isImm() &&
3933 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 18)) {
3934 // c.srai $rs1, $imm
3935 // Operand: rs1_wb
3936 // Operand: rs1
3937 // Operand: imm
3938 return true;
3939 } // if
3940 break;
3941 } // case SRAI
3942 case RISCV::SRLI: {
3943 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3944 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3945 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3946 (MI.getOperand(1).isReg()) &&
3947 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3948 MI.getOperand(2).isImm() &&
3949 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 18)) {
3950 // c.srli $rs1, $imm
3951 // Operand: rs1_wb
3952 // Operand: rs1
3953 // Operand: imm
3954 return true;
3955 } // if
3956 break;
3957 } // case SRLI
3958 case RISCV::SSPOPCHK: {
3959 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
3960 STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
3961 (MI.getOperand(0).isReg()) &&
3962 (MI.getOperand(0).getReg() == RISCV::X5)) {
3963 // c.sspopchk $rs1
3964 // Operand: rs1
3965 return true;
3966 } // if
3967 break;
3968 } // case SSPOPCHK
3969 case RISCV::SSPUSH: {
3970 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
3971 STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
3972 (MI.getOperand(0).isReg()) &&
3973 (MI.getOperand(0).getReg() == RISCV::X1)) {
3974 // c.sspush $rs1
3975 // Operand: rs1
3976 return true;
3977 } // if
3978 break;
3979 } // case SSPUSH
3980 case RISCV::SUB: {
3981 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3982 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3983 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
3984 (MI.getOperand(1).isReg()) &&
3985 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3986 (MI.getOperand(2).isReg()) &&
3987 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3988 // c.sub $rd, $rs2
3989 // Operand: rd_wb
3990 // Operand: rd
3991 // Operand: rs2
3992 return true;
3993 } // if
3994 break;
3995 } // case SUB
3996 case RISCV::SUBW: {
3997 if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3998 (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3999 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
4000 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
4001 (MI.getOperand(1).isReg()) &&
4002 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
4003 (MI.getOperand(2).isReg()) &&
4004 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
4005 // c.subw $rd, $rs2
4006 // Operand: rd_wb
4007 // Operand: rd
4008 // Operand: rs2
4009 return true;
4010 } // if
4011 break;
4012 } // case SUBW
4013 case RISCV::SW: {
4014 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4015 (MI.getOperand(0).isReg()) &&
4016 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
4017 (MI.getOperand(1).isReg()) &&
4018 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
4019 MI.getOperand(2).isImm() &&
4020 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
4021 // c.sw $rs2, ${imm}(${rs1})
4022 // Operand: rs2
4023 // Operand: rs1
4024 // Operand: imm
4025 return true;
4026 } // if
4027 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4028 (MI.getOperand(0).isReg()) &&
4029 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
4030 (MI.getOperand(1).isReg()) &&
4031 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
4032 MI.getOperand(2).isImm() &&
4033 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
4034 // c.swsp $rs2, ${imm}(${rs1})
4035 // Operand: rs2
4036 // Operand: rs1
4037 // Operand: imm
4038 return true;
4039 } // if
4040 break;
4041 } // case SW
4042 case RISCV::UNIMP: {
4043 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
4044 // c.unimp
4045 return true;
4046 } // if
4047 break;
4048 } // case UNIMP
4049 case RISCV::XOR: {
4050 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4051 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
4052 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
4053 (MI.getOperand(1).isReg()) &&
4054 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
4055 (MI.getOperand(2).isReg()) &&
4056 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
4057 // c.xor $rd, $rs2
4058 // Operand: rd_wb
4059 // Operand: rd
4060 // Operand: rs2
4061 return true;
4062 } // if
4063 if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4064 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
4065 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
4066 (MI.getOperand(2).isReg()) &&
4067 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
4068 (MI.getOperand(1).isReg()) &&
4069 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
4070 // c.xor $rd, $rs2
4071 // Operand: rd_wb
4072 // Operand: rd
4073 // Operand: rs2
4074 return true;
4075 } // if
4076 break;
4077 } // case XOR
4078 case RISCV::XORI: {
4079 if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4080 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
4081 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
4082 (MI.getOperand(2).isImm()) &&
4083 (MI.getOperand(2).getImm() == -1) &&
4084 (MI.getOperand(1).isReg()) &&
4085 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
4086 // c.not $rd
4087 // Operand: rd_wb
4088 // Operand: rd
4089 return true;
4090 } // if
4091 break;
4092 } // case XORI
4093 case RISCV::ZEXT_H_RV32: {
4094 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4095 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4096 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
4097 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
4098 (MI.getOperand(1).isReg()) &&
4099 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
4100 // c.zext.h $rd
4101 // Operand: rd_wb
4102 // Operand: rd
4103 return true;
4104 } // if
4105 break;
4106 } // case ZEXT_H_RV32
4107 case RISCV::ZEXT_H_RV64: {
4108 if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
4109 STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4110 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
4111 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
4112 (MI.getOperand(1).isReg()) &&
4113 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
4114 // c.zext.h $rd
4115 // Operand: rd_wb
4116 // Operand: rd
4117 return true;
4118 } // if
4119
4120 } // case ZEXT_H_RV64
4121 } // switch
4122 return false;
4123}
4124
4125#endif //GEN_CHECK_COMPRESS_INSTR
4126
4127