1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(2155880448), // ADDCCri
326 UINT64_C(2155872256), // ADDCCrr
327 UINT64_C(2151686144), // ADDCri
328 UINT64_C(2151677952), // ADDCrr
329 UINT64_C(2160074752), // ADDEri
330 UINT64_C(2160066560), // ADDErr
331 UINT64_C(2175795744), // ADDXC
332 UINT64_C(2175795808), // ADDXCCC
333 UINT64_C(2147491840), // ADDri
334 UINT64_C(2147483648), // ADDrr
335 UINT64_C(2175795968), // ALIGNADDR
336 UINT64_C(2175796032), // ALIGNADDRL
337 UINT64_C(2156404736), // ANDCCri
338 UINT64_C(2156396544), // ANDCCrr
339 UINT64_C(2158501888), // ANDNCCri
340 UINT64_C(2158493696), // ANDNCCrr
341 UINT64_C(2150113280), // ANDNri
342 UINT64_C(2150105088), // ANDNrr
343 UINT64_C(2148016128), // ANDri
344 UINT64_C(2148007936), // ANDrr
345 UINT64_C(2175795776), // ARRAY16
346 UINT64_C(2175795840), // ARRAY32
347 UINT64_C(2175795712), // ARRAY8
348 UINT64_C(276824064), // BA
349 UINT64_C(8388608), // BCOND
350 UINT64_C(545259520), // BCONDA
351 UINT64_C(2176851968), // BINDri
352 UINT64_C(2176843776), // BINDrr
353 UINT64_C(2175796000), // BMASK
354 UINT64_C(21495808), // BPFCC
355 UINT64_C(558366720), // BPFCCA
356 UINT64_C(557842432), // BPFCCANT
357 UINT64_C(20971520), // BPFCCNT
358 UINT64_C(4718592), // BPICC
359 UINT64_C(541589504), // BPICCA
360 UINT64_C(541065216), // BPICCANT
361 UINT64_C(4194304), // BPICCNT
362 UINT64_C(13107200), // BPR
363 UINT64_C(549978112), // BPRA
364 UINT64_C(549453824), // BPRANT
365 UINT64_C(12582912), // BPRNT
366 UINT64_C(6815744), // BPXCC
367 UINT64_C(543686656), // BPXCCA
368 UINT64_C(543162368), // BPXCCANT
369 UINT64_C(6291456), // BPXCCNT
370 UINT64_C(2175796096), // BSHUFFLE
371 UINT64_C(1073741824), // CALL
372 UINT64_C(2680168448), // CALLri
373 UINT64_C(2680160256), // CALLrr
374 UINT64_C(3252690944), // CASAri
375 UINT64_C(3252682752), // CASArr
376 UINT64_C(3253739520), // CASXAri
377 UINT64_C(3253731328), // CASXArr
378 UINT64_C(29360128), // CBCOND
379 UINT64_C(566231040), // CBCONDA
380 UINT64_C(2175796128), // CMASK16
381 UINT64_C(2175796192), // CMASK32
382 UINT64_C(2175796064), // CMASK8
383 UINT64_C(2179989504), // DONE
384 UINT64_C(2175795328), // EDGE16
385 UINT64_C(2175795392), // EDGE16L
386 UINT64_C(2175795424), // EDGE16LN
387 UINT64_C(2175795360), // EDGE16N
388 UINT64_C(2175795456), // EDGE32
389 UINT64_C(2175795520), // EDGE32L
390 UINT64_C(2175795552), // EDGE32LN
391 UINT64_C(2175795488), // EDGE32N
392 UINT64_C(2175795200), // EDGE8
393 UINT64_C(2175795264), // EDGE8L
394 UINT64_C(2175795296), // EDGE8LN
395 UINT64_C(2175795232), // EDGE8N
396 UINT64_C(2174746944), // FABSD
397 UINT64_C(2174746976), // FABSQ
398 UINT64_C(2174746912), // FABSS
399 UINT64_C(2174748736), // FADDD
400 UINT64_C(2174748768), // FADDQ
401 UINT64_C(2174748704), // FADDS
402 UINT64_C(2175797504), // FALIGNADATA
403 UINT64_C(2175798784), // FAND
404 UINT64_C(2175798528), // FANDNOT1
405 UINT64_C(2175798560), // FANDNOT1S
406 UINT64_C(2175798400), // FANDNOT2
407 UINT64_C(2175798432), // FANDNOT2S
408 UINT64_C(2175798816), // FANDS
409 UINT64_C(25165824), // FBCOND
410 UINT64_C(562036736), // FBCONDA
411 UINT64_C(558366720), // FBCONDA_V9
412 UINT64_C(21495808), // FBCOND_V9
413 UINT64_C(2175797376), // FCHKSM16
414 UINT64_C(2175273536), // FCMPD
415 UINT64_C(2175273536), // FCMPD_V9
416 UINT64_C(2175796544), // FCMPEQ16
417 UINT64_C(2175796672), // FCMPEQ32
418 UINT64_C(2175796480), // FCMPGT16
419 UINT64_C(2175796608), // FCMPGT32
420 UINT64_C(2175796224), // FCMPLE16
421 UINT64_C(2175796352), // FCMPLE32
422 UINT64_C(2175796288), // FCMPNE16
423 UINT64_C(2175796416), // FCMPNE32
424 UINT64_C(2175273568), // FCMPQ
425 UINT64_C(2175273568), // FCMPQ_V9
426 UINT64_C(2175273504), // FCMPS
427 UINT64_C(2175273504), // FCMPS_V9
428 UINT64_C(2174749120), // FDIVD
429 UINT64_C(2174749152), // FDIVQ
430 UINT64_C(2174749088), // FDIVS
431 UINT64_C(2174750144), // FDMULQ
432 UINT64_C(2174753344), // FDTOI
433 UINT64_C(2174753216), // FDTOQ
434 UINT64_C(2174752960), // FDTOS
435 UINT64_C(2174750784), // FDTOX
436 UINT64_C(2175797664), // FEXPAND
437 UINT64_C(2174749760), // FHADDD
438 UINT64_C(2174749728), // FHADDS
439 UINT64_C(2174749888), // FHSUBD
440 UINT64_C(2174749856), // FHSUBS
441 UINT64_C(2174753024), // FITOD
442 UINT64_C(2174753152), // FITOQ
443 UINT64_C(2174752896), // FITOS
444 UINT64_C(2175806016), // FLCMPD
445 UINT64_C(2175805984), // FLCMPS
446 UINT64_C(2178416640), // FLUSH
447 UINT64_C(2170028032), // FLUSHW
448 UINT64_C(2178424832), // FLUSHri
449 UINT64_C(2178416640), // FLUSHrr
450 UINT64_C(2175797248), // FMEAN16
451 UINT64_C(2174746688), // FMOVD
452 UINT64_C(2175270976), // FMOVD_FCC
453 UINT64_C(2175279168), // FMOVD_ICC
454 UINT64_C(2175283264), // FMOVD_XCC
455 UINT64_C(2174746720), // FMOVQ
456 UINT64_C(2175271008), // FMOVQ_FCC
457 UINT64_C(2175279200), // FMOVQ_ICC
458 UINT64_C(2175283296), // FMOVQ_XCC
459 UINT64_C(2175271104), // FMOVRD
460 UINT64_C(2175271136), // FMOVRQ
461 UINT64_C(2175271072), // FMOVRS
462 UINT64_C(2174746656), // FMOVS
463 UINT64_C(2175270944), // FMOVS_FCC
464 UINT64_C(2175279136), // FMOVS_ICC
465 UINT64_C(2175283232), // FMOVS_XCC
466 UINT64_C(2175796928), // FMUL8SUX16
467 UINT64_C(2175796960), // FMUL8ULX16
468 UINT64_C(2175796768), // FMUL8X16
469 UINT64_C(2175796896), // FMUL8X16AL
470 UINT64_C(2175796832), // FMUL8X16AU
471 UINT64_C(2174748992), // FMULD
472 UINT64_C(2175796992), // FMULD8SUX16
473 UINT64_C(2175797024), // FMULD8ULX16
474 UINT64_C(2174749024), // FMULQ
475 UINT64_C(2174748960), // FMULS
476 UINT64_C(2174749248), // FNADDD
477 UINT64_C(2174749216), // FNADDS
478 UINT64_C(2175798720), // FNAND
479 UINT64_C(2175798752), // FNANDS
480 UINT64_C(2174746816), // FNEGD
481 UINT64_C(2174746848), // FNEGQ
482 UINT64_C(2174746784), // FNEGS
483 UINT64_C(2174750272), // FNHADDD
484 UINT64_C(2174750240), // FNHADDS
485 UINT64_C(2174749504), // FNMULD
486 UINT64_C(2174749472), // FNMULS
487 UINT64_C(2175798336), // FNOR
488 UINT64_C(2175798368), // FNORS
489 UINT64_C(2175798592), // FNOT1
490 UINT64_C(2175798624), // FNOT1S
491 UINT64_C(2175798464), // FNOT2
492 UINT64_C(2175798496), // FNOT2S
493 UINT64_C(2174750496), // FNSMULD
494 UINT64_C(2175799232), // FONE
495 UINT64_C(2175799264), // FONES
496 UINT64_C(2175799168), // FOR
497 UINT64_C(2175799104), // FORNOT1
498 UINT64_C(2175799136), // FORNOT1S
499 UINT64_C(2175798976), // FORNOT2
500 UINT64_C(2175799008), // FORNOT2S
501 UINT64_C(2175799200), // FORS
502 UINT64_C(2175797088), // FPACK16
503 UINT64_C(2175797056), // FPACK32
504 UINT64_C(2175797152), // FPACKFIX
505 UINT64_C(2175797760), // FPADD16
506 UINT64_C(2175797792), // FPADD16S
507 UINT64_C(2175797824), // FPADD32
508 UINT64_C(2175797856), // FPADD32S
509 UINT64_C(2175797312), // FPADD64
510 UINT64_C(2175797600), // FPMERGE
511 UINT64_C(2175797888), // FPSUB16
512 UINT64_C(2175797920), // FPSUB16S
513 UINT64_C(2175797952), // FPSUB32
514 UINT64_C(2175797984), // FPSUB32S
515 UINT64_C(2174753120), // FQTOD
516 UINT64_C(2174753376), // FQTOI
517 UINT64_C(2174752992), // FQTOS
518 UINT64_C(2174750816), // FQTOX
519 UINT64_C(2175796512), // FSLAS16
520 UINT64_C(2175796640), // FSLAS32
521 UINT64_C(2175796256), // FSLL16
522 UINT64_C(2175796384), // FSLL32
523 UINT64_C(2174749984), // FSMULD
524 UINT64_C(2174747968), // FSQRTD
525 UINT64_C(2174748000), // FSQRTQ
526 UINT64_C(2174747936), // FSQRTS
527 UINT64_C(2175796576), // FSRA16
528 UINT64_C(2175796704), // FSRA32
529 UINT64_C(2175798912), // FSRC1
530 UINT64_C(2175798944), // FSRC1S
531 UINT64_C(2175799040), // FSRC2
532 UINT64_C(2175799072), // FSRC2S
533 UINT64_C(2175796320), // FSRL16
534 UINT64_C(2175796448), // FSRL32
535 UINT64_C(2174753056), // FSTOD
536 UINT64_C(2174753312), // FSTOI
537 UINT64_C(2174753184), // FSTOQ
538 UINT64_C(2174750752), // FSTOX
539 UINT64_C(2174748864), // FSUBD
540 UINT64_C(2174748896), // FSUBQ
541 UINT64_C(2174748832), // FSUBS
542 UINT64_C(2175798848), // FXNOR
543 UINT64_C(2175798880), // FXNORS
544 UINT64_C(2175798656), // FXOR
545 UINT64_C(2175798688), // FXORS
546 UINT64_C(2174750976), // FXTOD
547 UINT64_C(2174751104), // FXTOQ
548 UINT64_C(2174750848), // FXTOS
549 UINT64_C(2175798272), // FZERO
550 UINT64_C(2175798304), // FZEROS
551 UINT64_C(3226992640), // GDOP_LDXrr
552 UINT64_C(3221225472), // GDOP_LDrr
553 UINT64_C(2176851968), // JMPLri
554 UINT64_C(2176843776), // JMPLrr
555 UINT64_C(3229622272), // LDAri
556 UINT64_C(3229614080), // LDArr
557 UINT64_C(3246923776), // LDCSRri
558 UINT64_C(3246915584), // LDCSRrr
559 UINT64_C(3246399488), // LDCri
560 UINT64_C(3246391296), // LDCrr
561 UINT64_C(3231195136), // LDDAri
562 UINT64_C(3231186944), // LDDArr
563 UINT64_C(3247972352), // LDDCri
564 UINT64_C(3247964160), // LDDCrr
565 UINT64_C(3247972352), // LDDFAri
566 UINT64_C(3247964160), // LDDFArr
567 UINT64_C(3239583744), // LDDFri
568 UINT64_C(3239575552), // LDDFrr
569 UINT64_C(3222806528), // LDDri
570 UINT64_C(3222798336), // LDDrr
571 UINT64_C(3246399488), // LDFAri
572 UINT64_C(3246391296), // LDFArr
573 UINT64_C(3238535168), // LDFSRri
574 UINT64_C(3238526976), // LDFSRrr
575 UINT64_C(3238010880), // LDFri
576 UINT64_C(3238002688), // LDFrr
577 UINT64_C(3247448064), // LDQFAri
578 UINT64_C(3247439872), // LDQFArr
579 UINT64_C(3239059456), // LDQFri
580 UINT64_C(3239051264), // LDQFrr
581 UINT64_C(3234340864), // LDSBAri
582 UINT64_C(3234332672), // LDSBArr
583 UINT64_C(3225952256), // LDSBri
584 UINT64_C(3225944064), // LDSBrr
585 UINT64_C(3234865152), // LDSHAri
586 UINT64_C(3234856960), // LDSHArr
587 UINT64_C(3226476544), // LDSHri
588 UINT64_C(3226468352), // LDSHrr
589 UINT64_C(3236438016), // LDSTUBAri
590 UINT64_C(3236429824), // LDSTUBArr
591 UINT64_C(3228049408), // LDSTUBri
592 UINT64_C(3228041216), // LDSTUBrr
593 UINT64_C(3233816576), // LDSWAri
594 UINT64_C(3233808384), // LDSWArr
595 UINT64_C(3225427968), // LDSWri
596 UINT64_C(3225419776), // LDSWrr
597 UINT64_C(3230146560), // LDUBAri
598 UINT64_C(3230138368), // LDUBArr
599 UINT64_C(3221757952), // LDUBri
600 UINT64_C(3221749760), // LDUBrr
601 UINT64_C(3230670848), // LDUHAri
602 UINT64_C(3230662656), // LDUHArr
603 UINT64_C(3222282240), // LDUHri
604 UINT64_C(3222274048), // LDUHrr
605 UINT64_C(3235389440), // LDXAri
606 UINT64_C(3235381248), // LDXArr
607 UINT64_C(3272089600), // LDXFSRri
608 UINT64_C(3272081408), // LDXFSRrr
609 UINT64_C(3227000832), // LDXri
610 UINT64_C(3226992640), // LDXrr
611 UINT64_C(3221233664), // LDri
612 UINT64_C(3221225472), // LDrr
613 UINT64_C(2175795936), // LZCNT
614 UINT64_C(2168709120), // MEMBARi
615 UINT64_C(2175803904), // MOVDTOX
616 UINT64_C(2170560512), // MOVFCCri
617 UINT64_C(2170552320), // MOVFCCrr
618 UINT64_C(2170822656), // MOVICCri
619 UINT64_C(2170814464), // MOVICCrr
620 UINT64_C(2172133376), // MOVRri
621 UINT64_C(2172125184), // MOVRrr
622 UINT64_C(2175804000), // MOVSTOSW
623 UINT64_C(2175803936), // MOVSTOUW
624 UINT64_C(2175804192), // MOVWTOS
625 UINT64_C(2170826752), // MOVXCCri
626 UINT64_C(2170818560), // MOVXCCrr
627 UINT64_C(2175804160), // MOVXTOD
628 UINT64_C(2166366208), // MULSCCri
629 UINT64_C(2166358016), // MULSCCrr
630 UINT64_C(2152210432), // MULXri
631 UINT64_C(2152202240), // MULXrr
632 UINT64_C(16777216), // NOP
633 UINT64_C(2156929024), // ORCCri
634 UINT64_C(2156920832), // ORCCrr
635 UINT64_C(2159026176), // ORNCCri
636 UINT64_C(2159017984), // ORNCCrr
637 UINT64_C(2150637568), // ORNri
638 UINT64_C(2150629376), // ORNrr
639 UINT64_C(2148540416), // ORri
640 UINT64_C(2148532224), // ORrr
641 UINT64_C(2175797184), // PDIST
642 UINT64_C(2175797216), // PDISTN
643 UINT64_C(2171600896), // POPCrr
644 UINT64_C(3253215232), // PREFETCHAi
645 UINT64_C(3253207040), // PREFETCHAr
646 UINT64_C(3244826624), // PREFETCHi
647 UINT64_C(3244818432), // PREFETCHr
648 UINT64_C(2206736384), // PWRPSRri
649 UINT64_C(2206728192), // PWRPSRrr
650 UINT64_C(2168455168), // RDASR
651 UINT64_C(2169749504), // RDFQ
652 UINT64_C(2169503744), // RDPR
653 UINT64_C(2168979456), // RDPSR
654 UINT64_C(2170028032), // RDTBR
655 UINT64_C(2169503744), // RDWIM
656 UINT64_C(2206728192), // RESTORED
657 UINT64_C(2179473408), // RESTOREri
658 UINT64_C(2179465216), // RESTORErr
659 UINT64_C(2177359872), // RET
660 UINT64_C(2177097728), // RETL
661 UINT64_C(2213543936), // RETRY
662 UINT64_C(2177376256), // RETTri
663 UINT64_C(2177368064), // RETTrr
664 UINT64_C(2173173760), // SAVED
665 UINT64_C(2178949120), // SAVEri
666 UINT64_C(2178940928), // SAVErr
667 UINT64_C(2163744768), // SDIVCCri
668 UINT64_C(2163736576), // SDIVCCrr
669 UINT64_C(2171084800), // SDIVXri
670 UINT64_C(2171076608), // SDIVXrr
671 UINT64_C(2155356160), // SDIVri
672 UINT64_C(2155347968), // SDIVrr
673 UINT64_C(16777216), // SETHIi
674 UINT64_C(2175799296), // SHUTDOWN
675 UINT64_C(2175799328), // SIAM
676 UINT64_C(2675974144), // SIR
677 UINT64_C(2166894592), // SLLXri
678 UINT64_C(2166886400), // SLLXrr
679 UINT64_C(2166890496), // SLLri
680 UINT64_C(2166882304), // SLLrr
681 UINT64_C(2180521984), // SMACri
682 UINT64_C(2180513792), // SMACrr
683 UINT64_C(2161647616), // SMULCCri
684 UINT64_C(2161639424), // SMULCCrr
685 UINT64_C(2153259008), // SMULri
686 UINT64_C(2153250816), // SMULrr
687 UINT64_C(2167943168), // SRAXri
688 UINT64_C(2167934976), // SRAXrr
689 UINT64_C(2167939072), // SRAri
690 UINT64_C(2167930880), // SRArr
691 UINT64_C(2167418880), // SRLXri
692 UINT64_C(2167410688), // SRLXrr
693 UINT64_C(2167414784), // SRLri
694 UINT64_C(2167406592), // SRLrr
695 UINT64_C(3231719424), // STAri
696 UINT64_C(3231711232), // STArr
697 UINT64_C(2168700928), // STBAR
698 UINT64_C(3232243712), // STBAri
699 UINT64_C(3232235520), // STBArr
700 UINT64_C(3223855104), // STBri
701 UINT64_C(3223846912), // STBrr
702 UINT64_C(3249020928), // STCSRri
703 UINT64_C(3249012736), // STCSRrr
704 UINT64_C(3248496640), // STCri
705 UINT64_C(3248488448), // STCrr
706 UINT64_C(3233292288), // STDAri
707 UINT64_C(3233284096), // STDArr
708 UINT64_C(3249545216), // STDCQri
709 UINT64_C(3249537024), // STDCQrr
710 UINT64_C(3250069504), // STDCri
711 UINT64_C(3250061312), // STDCrr
712 UINT64_C(3250069504), // STDFAri
713 UINT64_C(3250061312), // STDFArr
714 UINT64_C(3241156608), // STDFQri
715 UINT64_C(3241148416), // STDFQrr
716 UINT64_C(3241680896), // STDFri
717 UINT64_C(3241672704), // STDFrr
718 UINT64_C(3224903680), // STDri
719 UINT64_C(3224895488), // STDrr
720 UINT64_C(3248496640), // STFAri
721 UINT64_C(3248488448), // STFArr
722 UINT64_C(3240632320), // STFSRri
723 UINT64_C(3240624128), // STFSRrr
724 UINT64_C(3240108032), // STFri
725 UINT64_C(3240099840), // STFrr
726 UINT64_C(3232768000), // STHAri
727 UINT64_C(3232759808), // STHArr
728 UINT64_C(3224379392), // STHri
729 UINT64_C(3224371200), // STHrr
730 UINT64_C(3249545216), // STQFAri
731 UINT64_C(3249537024), // STQFArr
732 UINT64_C(3241156608), // STQFri
733 UINT64_C(3241148416), // STQFrr
734 UINT64_C(3236962304), // STXAri
735 UINT64_C(3236954112), // STXArr
736 UINT64_C(3274186752), // STXFSRri
737 UINT64_C(3274178560), // STXFSRrr
738 UINT64_C(3228573696), // STXri
739 UINT64_C(3228565504), // STXrr
740 UINT64_C(3223330816), // STri
741 UINT64_C(3223322624), // STrr
742 UINT64_C(2157977600), // SUBCCri
743 UINT64_C(2157969408), // SUBCCrr
744 UINT64_C(2153783296), // SUBCri
745 UINT64_C(2153775104), // SUBCrr
746 UINT64_C(2162171904), // SUBEri
747 UINT64_C(2162163712), // SUBErr
748 UINT64_C(2149588992), // SUBri
749 UINT64_C(2149580800), // SUBrr
750 UINT64_C(3237486592), // SWAPAri
751 UINT64_C(3237478400), // SWAPArr
752 UINT64_C(3229097984), // SWAPri
753 UINT64_C(3229089792), // SWAPrr
754 UINT64_C(2446336001), // TA1
755 UINT64_C(2446336003), // TA3
756 UINT64_C(2446336005), // TA5
757 UINT64_C(2165317632), // TADDCCTVri
758 UINT64_C(2165309440), // TADDCCTVrr
759 UINT64_C(2164269056), // TADDCCri
760 UINT64_C(2164260864), // TADDCCrr
761 UINT64_C(1073741824), // TAIL_CALL
762 UINT64_C(2176851968), // TAIL_CALLri
763 UINT64_C(2177900544), // TICCri
764 UINT64_C(2177892352), // TICCrr
765 UINT64_C(2147483648), // TLS_ADDrr
766 UINT64_C(1073741824), // TLS_CALL
767 UINT64_C(3226992640), // TLS_LDXrr
768 UINT64_C(3221225472), // TLS_LDrr
769 UINT64_C(2177900544), // TRAPri
770 UINT64_C(2177892352), // TRAPrr
771 UINT64_C(2165841920), // TSUBCCTVri
772 UINT64_C(2165833728), // TSUBCCTVrr
773 UINT64_C(2164793344), // TSUBCCri
774 UINT64_C(2164785152), // TSUBCCrr
775 UINT64_C(2177904640), // TXCCri
776 UINT64_C(2177896448), // TXCCrr
777 UINT64_C(2163220480), // UDIVCCri
778 UINT64_C(2163212288), // UDIVCCrr
779 UINT64_C(2154307584), // UDIVXri
780 UINT64_C(2154299392), // UDIVXrr
781 UINT64_C(2154831872), // UDIVri
782 UINT64_C(2154823680), // UDIVrr
783 UINT64_C(2179997696), // UMACri
784 UINT64_C(2179989504), // UMACrr
785 UINT64_C(2161123328), // UMULCCri
786 UINT64_C(2161115136), // UMULCCrr
787 UINT64_C(2175795904), // UMULXHI
788 UINT64_C(2152734720), // UMULri
789 UINT64_C(2152726528), // UMULrr
790 UINT64_C(0), // UNIMP
791 UINT64_C(2175273536), // V9FCMPD
792 UINT64_C(2175273664), // V9FCMPED
793 UINT64_C(2175273696), // V9FCMPEQ
794 UINT64_C(2175273632), // V9FCMPES
795 UINT64_C(2175273568), // V9FCMPQ
796 UINT64_C(2175273504), // V9FCMPS
797 UINT64_C(2175270976), // V9FMOVD_FCC
798 UINT64_C(2175271008), // V9FMOVQ_FCC
799 UINT64_C(2175270944), // V9FMOVS_FCC
800 UINT64_C(2170560512), // V9MOVFCCri
801 UINT64_C(2170552320), // V9MOVFCCrr
802 UINT64_C(2172657664), // WRASRri
803 UINT64_C(2172649472), // WRASRrr
804 UINT64_C(2173706240), // WRPRri
805 UINT64_C(2173698048), // WRPRrr
806 UINT64_C(2173181952), // WRPSRri
807 UINT64_C(2173173760), // WRPSRrr
808 UINT64_C(2174230528), // WRTBRri
809 UINT64_C(2174222336), // WRTBRrr
810 UINT64_C(2173706240), // WRWIMri
811 UINT64_C(2173698048), // WRWIMrr
812 UINT64_C(2175804064), // XMULX
813 UINT64_C(2175804128), // XMULXHI
814 UINT64_C(2159550464), // XNORCCri
815 UINT64_C(2159542272), // XNORCCrr
816 UINT64_C(2151161856), // XNORri
817 UINT64_C(2151153664), // XNORrr
818 UINT64_C(2157453312), // XORCCri
819 UINT64_C(2157445120), // XORCCrr
820 UINT64_C(2149064704), // XORri
821 UINT64_C(2149056512), // XORrr
822 UINT64_C(0)
823 };
824 const unsigned opcode = MI.getOpcode();
825 uint64_t Value = InstBits[opcode];
826 uint64_t op = 0;
827 (void)op; // suppress warning
828 switch (opcode) {
829 case SP::DONE:
830 case SP::FLUSH:
831 case SP::FLUSHW:
832 case SP::NOP:
833 case SP::RESTORED:
834 case SP::RETRY:
835 case SP::SAVED:
836 case SP::SHUTDOWN:
837 case SP::SIAM:
838 case SP::STBAR:
839 case SP::TA1:
840 case SP::TA3:
841 case SP::TA5: {
842 break;
843 }
844 case SP::BPFCC:
845 case SP::BPFCCA:
846 case SP::BPFCCANT:
847 case SP::BPFCCNT: {
848 // op: cc
849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
850 op &= UINT64_C(3);
851 op <<= 20;
852 Value |= op;
853 // op: cond
854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
855 op &= UINT64_C(15);
856 op <<= 25;
857 Value |= op;
858 // op: imm19
859 op = getBranchPredTargetOpValue(MI, OpNo: 0, Fixups, STI);
860 op &= UINT64_C(524287);
861 Value |= op;
862 break;
863 }
864 case SP::BPICC:
865 case SP::BPICCA:
866 case SP::BPICCANT:
867 case SP::BPICCNT:
868 case SP::BPXCC:
869 case SP::BPXCCA:
870 case SP::BPXCCANT:
871 case SP::BPXCCNT:
872 case SP::FBCONDA_V9:
873 case SP::FBCOND_V9: {
874 // op: cond
875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
876 op &= UINT64_C(15);
877 op <<= 25;
878 Value |= op;
879 // op: imm19
880 op = getBranchPredTargetOpValue(MI, OpNo: 0, Fixups, STI);
881 op &= UINT64_C(524287);
882 Value |= op;
883 break;
884 }
885 case SP::CALL:
886 case SP::TAIL_CALL:
887 case SP::TLS_CALL: {
888 // op: disp
889 op = getCallTargetOpValue(MI, OpNo: 0, Fixups, STI);
890 op &= UINT64_C(1073741823);
891 Value |= op;
892 break;
893 }
894 case SP::BPR:
895 case SP::BPRA:
896 case SP::BPRANT:
897 case SP::BPRNT: {
898 // op: imm16
899 op = getBranchOnRegTargetOpValue(MI, OpNo: 0, Fixups, STI);
900 Value |= (op & UINT64_C(49152)) << 6;
901 Value |= (op & UINT64_C(16383));
902 // op: rs1
903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
904 op &= UINT64_C(31);
905 op <<= 14;
906 Value |= op;
907 // op: rcond
908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
909 op &= UINT64_C(7);
910 op <<= 25;
911 Value |= op;
912 break;
913 }
914 case SP::BA: {
915 // op: imm22
916 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
917 op &= UINT64_C(4194303);
918 Value |= op;
919 break;
920 }
921 case SP::BCOND:
922 case SP::BCONDA:
923 case SP::CBCOND:
924 case SP::CBCONDA:
925 case SP::FBCOND:
926 case SP::FBCONDA: {
927 // op: imm22
928 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
929 op &= UINT64_C(4194303);
930 Value |= op;
931 // op: cond
932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
933 op &= UINT64_C(15);
934 op <<= 25;
935 Value |= op;
936 break;
937 }
938 case SP::UNIMP: {
939 // op: imm22
940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
941 op &= UINT64_C(4194303);
942 Value |= op;
943 break;
944 }
945 case SP::SETHIi: {
946 // op: imm22
947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
948 op &= UINT64_C(4194303);
949 Value |= op;
950 // op: rd
951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
952 op &= UINT64_C(31);
953 op <<= 25;
954 Value |= op;
955 break;
956 }
957 case SP::FONE:
958 case SP::FONES:
959 case SP::FZERO:
960 case SP::FZEROS:
961 case SP::RDFQ:
962 case SP::RDPSR:
963 case SP::RDTBR:
964 case SP::RDWIM: {
965 // op: rd
966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
967 op &= UINT64_C(31);
968 op <<= 25;
969 Value |= op;
970 break;
971 }
972 case SP::V9MOVFCCrr: {
973 // op: rd
974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
975 op &= UINT64_C(31);
976 op <<= 25;
977 Value |= op;
978 // op: cc
979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
980 op &= UINT64_C(3);
981 op <<= 11;
982 Value |= op;
983 // op: cond
984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
985 op &= UINT64_C(15);
986 op <<= 14;
987 Value |= op;
988 // op: rs2
989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
990 op &= UINT64_C(31);
991 Value |= op;
992 break;
993 }
994 case SP::V9MOVFCCri: {
995 // op: rd
996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
997 op &= UINT64_C(31);
998 op <<= 25;
999 Value |= op;
1000 // op: cc
1001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1002 op &= UINT64_C(3);
1003 op <<= 11;
1004 Value |= op;
1005 // op: cond
1006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1007 op &= UINT64_C(15);
1008 op <<= 14;
1009 Value |= op;
1010 // op: simm11
1011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1012 op &= UINT64_C(2047);
1013 Value |= op;
1014 break;
1015 }
1016 case SP::FMOVD_FCC:
1017 case SP::FMOVD_ICC:
1018 case SP::FMOVD_XCC:
1019 case SP::FMOVQ_FCC:
1020 case SP::FMOVQ_ICC:
1021 case SP::FMOVQ_XCC:
1022 case SP::FMOVS_FCC:
1023 case SP::FMOVS_ICC:
1024 case SP::FMOVS_XCC:
1025 case SP::MOVFCCrr:
1026 case SP::MOVICCrr:
1027 case SP::MOVXCCrr: {
1028 // op: rd
1029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1030 op &= UINT64_C(31);
1031 op <<= 25;
1032 Value |= op;
1033 // op: cond
1034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1035 op &= UINT64_C(15);
1036 op <<= 14;
1037 Value |= op;
1038 // op: rs2
1039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1040 op &= UINT64_C(31);
1041 Value |= op;
1042 break;
1043 }
1044 case SP::MOVFCCri:
1045 case SP::MOVICCri:
1046 case SP::MOVXCCri: {
1047 // op: rd
1048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1049 op &= UINT64_C(31);
1050 op <<= 25;
1051 Value |= op;
1052 // op: cond
1053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1054 op &= UINT64_C(15);
1055 op <<= 14;
1056 Value |= op;
1057 // op: simm11
1058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1059 op &= UINT64_C(2047);
1060 Value |= op;
1061 break;
1062 }
1063 case SP::V9FMOVD_FCC:
1064 case SP::V9FMOVQ_FCC:
1065 case SP::V9FMOVS_FCC: {
1066 // op: rd
1067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1068 op &= UINT64_C(31);
1069 op <<= 25;
1070 Value |= op;
1071 // op: cond
1072 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1073 op &= UINT64_C(15);
1074 op <<= 14;
1075 Value |= op;
1076 // op: opf_cc
1077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1078 op &= UINT64_C(3);
1079 op <<= 11;
1080 Value |= op;
1081 // op: rs2
1082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1083 op &= UINT64_C(31);
1084 Value |= op;
1085 break;
1086 }
1087 case SP::FNOT1:
1088 case SP::FNOT1S:
1089 case SP::FSRC1:
1090 case SP::FSRC1S:
1091 case SP::RDASR:
1092 case SP::RDPR: {
1093 // op: rd
1094 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1095 op &= UINT64_C(31);
1096 op <<= 25;
1097 Value |= op;
1098 // op: rs1
1099 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1100 op &= UINT64_C(31);
1101 op <<= 14;
1102 Value |= op;
1103 break;
1104 }
1105 case SP::LDArr:
1106 case SP::LDDArr:
1107 case SP::LDDFArr:
1108 case SP::LDFArr:
1109 case SP::LDQFArr:
1110 case SP::LDSBArr:
1111 case SP::LDSHArr:
1112 case SP::LDSTUBArr:
1113 case SP::LDSWArr:
1114 case SP::LDUBArr:
1115 case SP::LDUHArr:
1116 case SP::LDXArr:
1117 case SP::SWAPArr: {
1118 // op: rd
1119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1120 op &= UINT64_C(31);
1121 op <<= 25;
1122 Value |= op;
1123 // op: rs1
1124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1125 op &= UINT64_C(31);
1126 op <<= 14;
1127 Value |= op;
1128 // op: asi
1129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1130 op &= UINT64_C(255);
1131 op <<= 5;
1132 Value |= op;
1133 // op: rs2
1134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1135 op &= UINT64_C(31);
1136 Value |= op;
1137 break;
1138 }
1139 case SP::CASArr:
1140 case SP::CASXArr: {
1141 // op: rd
1142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1143 op &= UINT64_C(31);
1144 op <<= 25;
1145 Value |= op;
1146 // op: rs1
1147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1148 op &= UINT64_C(31);
1149 op <<= 14;
1150 Value |= op;
1151 // op: asi
1152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1153 op &= UINT64_C(255);
1154 op <<= 5;
1155 Value |= op;
1156 // op: rs2
1157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1158 op &= UINT64_C(31);
1159 Value |= op;
1160 break;
1161 }
1162 case SP::ADDCCrr:
1163 case SP::ADDCrr:
1164 case SP::ADDErr:
1165 case SP::ADDXC:
1166 case SP::ADDXCCC:
1167 case SP::ADDrr:
1168 case SP::ALIGNADDR:
1169 case SP::ALIGNADDRL:
1170 case SP::ANDCCrr:
1171 case SP::ANDNCCrr:
1172 case SP::ANDNrr:
1173 case SP::ANDrr:
1174 case SP::ARRAY8:
1175 case SP::ARRAY16:
1176 case SP::ARRAY32:
1177 case SP::BMASK:
1178 case SP::BSHUFFLE:
1179 case SP::CASAri:
1180 case SP::CASXAri:
1181 case SP::EDGE8:
1182 case SP::EDGE8L:
1183 case SP::EDGE8LN:
1184 case SP::EDGE8N:
1185 case SP::EDGE16:
1186 case SP::EDGE16L:
1187 case SP::EDGE16LN:
1188 case SP::EDGE16N:
1189 case SP::EDGE32:
1190 case SP::EDGE32L:
1191 case SP::EDGE32LN:
1192 case SP::EDGE32N:
1193 case SP::FADDD:
1194 case SP::FADDQ:
1195 case SP::FADDS:
1196 case SP::FALIGNADATA:
1197 case SP::FAND:
1198 case SP::FANDNOT1:
1199 case SP::FANDNOT1S:
1200 case SP::FANDNOT2:
1201 case SP::FANDNOT2S:
1202 case SP::FANDS:
1203 case SP::FCHKSM16:
1204 case SP::FCMPEQ16:
1205 case SP::FCMPEQ32:
1206 case SP::FCMPGT16:
1207 case SP::FCMPGT32:
1208 case SP::FCMPLE16:
1209 case SP::FCMPLE32:
1210 case SP::FCMPNE16:
1211 case SP::FCMPNE32:
1212 case SP::FDIVD:
1213 case SP::FDIVQ:
1214 case SP::FDIVS:
1215 case SP::FDMULQ:
1216 case SP::FHADDD:
1217 case SP::FHADDS:
1218 case SP::FHSUBD:
1219 case SP::FHSUBS:
1220 case SP::FLCMPD:
1221 case SP::FLCMPS:
1222 case SP::FMEAN16:
1223 case SP::FMUL8SUX16:
1224 case SP::FMUL8ULX16:
1225 case SP::FMUL8X16:
1226 case SP::FMUL8X16AL:
1227 case SP::FMUL8X16AU:
1228 case SP::FMULD:
1229 case SP::FMULD8SUX16:
1230 case SP::FMULD8ULX16:
1231 case SP::FMULQ:
1232 case SP::FMULS:
1233 case SP::FNADDD:
1234 case SP::FNADDS:
1235 case SP::FNAND:
1236 case SP::FNANDS:
1237 case SP::FNHADDD:
1238 case SP::FNHADDS:
1239 case SP::FNMULD:
1240 case SP::FNMULS:
1241 case SP::FNOR:
1242 case SP::FNORS:
1243 case SP::FNSMULD:
1244 case SP::FOR:
1245 case SP::FORNOT1:
1246 case SP::FORNOT1S:
1247 case SP::FORNOT2:
1248 case SP::FORNOT2S:
1249 case SP::FORS:
1250 case SP::FPACK32:
1251 case SP::FPADD16:
1252 case SP::FPADD16S:
1253 case SP::FPADD32:
1254 case SP::FPADD32S:
1255 case SP::FPADD64:
1256 case SP::FPMERGE:
1257 case SP::FPSUB16:
1258 case SP::FPSUB16S:
1259 case SP::FPSUB32:
1260 case SP::FPSUB32S:
1261 case SP::FSLAS16:
1262 case SP::FSLAS32:
1263 case SP::FSLL16:
1264 case SP::FSLL32:
1265 case SP::FSMULD:
1266 case SP::FSRA16:
1267 case SP::FSRA32:
1268 case SP::FSRL16:
1269 case SP::FSRL32:
1270 case SP::FSUBD:
1271 case SP::FSUBQ:
1272 case SP::FSUBS:
1273 case SP::FXNOR:
1274 case SP::FXNORS:
1275 case SP::FXOR:
1276 case SP::FXORS:
1277 case SP::GDOP_LDXrr:
1278 case SP::GDOP_LDrr:
1279 case SP::JMPLrr:
1280 case SP::LDCrr:
1281 case SP::LDDCrr:
1282 case SP::LDDFrr:
1283 case SP::LDDrr:
1284 case SP::LDFrr:
1285 case SP::LDQFrr:
1286 case SP::LDSBrr:
1287 case SP::LDSHrr:
1288 case SP::LDSTUBrr:
1289 case SP::LDSWrr:
1290 case SP::LDUBrr:
1291 case SP::LDUHrr:
1292 case SP::LDXrr:
1293 case SP::LDrr:
1294 case SP::MULSCCrr:
1295 case SP::MULXrr:
1296 case SP::ORCCrr:
1297 case SP::ORNCCrr:
1298 case SP::ORNrr:
1299 case SP::ORrr:
1300 case SP::PDIST:
1301 case SP::PDISTN:
1302 case SP::RESTORErr:
1303 case SP::SAVErr:
1304 case SP::SDIVCCrr:
1305 case SP::SDIVXrr:
1306 case SP::SDIVrr:
1307 case SP::SLLXrr:
1308 case SP::SLLrr:
1309 case SP::SMACrr:
1310 case SP::SMULCCrr:
1311 case SP::SMULrr:
1312 case SP::SRAXrr:
1313 case SP::SRArr:
1314 case SP::SRLXrr:
1315 case SP::SRLrr:
1316 case SP::SUBCCrr:
1317 case SP::SUBCrr:
1318 case SP::SUBErr:
1319 case SP::SUBrr:
1320 case SP::SWAPrr:
1321 case SP::TADDCCTVrr:
1322 case SP::TADDCCrr:
1323 case SP::TLS_ADDrr:
1324 case SP::TLS_LDXrr:
1325 case SP::TLS_LDrr:
1326 case SP::TSUBCCTVrr:
1327 case SP::TSUBCCrr:
1328 case SP::UDIVCCrr:
1329 case SP::UDIVXrr:
1330 case SP::UDIVrr:
1331 case SP::UMACrr:
1332 case SP::UMULCCrr:
1333 case SP::UMULXHI:
1334 case SP::UMULrr:
1335 case SP::V9FCMPD:
1336 case SP::V9FCMPED:
1337 case SP::V9FCMPEQ:
1338 case SP::V9FCMPES:
1339 case SP::V9FCMPQ:
1340 case SP::V9FCMPS:
1341 case SP::WRASRrr:
1342 case SP::WRPRrr:
1343 case SP::XMULX:
1344 case SP::XMULXHI:
1345 case SP::XNORCCrr:
1346 case SP::XNORrr:
1347 case SP::XORCCrr:
1348 case SP::XORrr: {
1349 // op: rd
1350 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1351 op &= UINT64_C(31);
1352 op <<= 25;
1353 Value |= op;
1354 // op: rs1
1355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1356 op &= UINT64_C(31);
1357 op <<= 14;
1358 Value |= op;
1359 // op: rs2
1360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1361 op &= UINT64_C(31);
1362 Value |= op;
1363 break;
1364 }
1365 case SP::FMOVRD:
1366 case SP::FMOVRQ:
1367 case SP::FMOVRS:
1368 case SP::MOVRrr: {
1369 // op: rd
1370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1371 op &= UINT64_C(31);
1372 op <<= 25;
1373 Value |= op;
1374 // op: rs1
1375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1376 op &= UINT64_C(31);
1377 op <<= 14;
1378 Value |= op;
1379 // op: rs2
1380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1381 op &= UINT64_C(31);
1382 Value |= op;
1383 // op: rcond
1384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1385 op &= UINT64_C(7);
1386 op <<= 10;
1387 Value |= op;
1388 break;
1389 }
1390 case SP::SLLXri:
1391 case SP::SLLri:
1392 case SP::SRAXri:
1393 case SP::SRAri:
1394 case SP::SRLXri:
1395 case SP::SRLri: {
1396 // op: rd
1397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1398 op &= UINT64_C(31);
1399 op <<= 25;
1400 Value |= op;
1401 // op: rs1
1402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1403 op &= UINT64_C(31);
1404 op <<= 14;
1405 Value |= op;
1406 // op: shcnt
1407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1408 op &= UINT64_C(63);
1409 Value |= op;
1410 break;
1411 }
1412 case SP::MOVRri: {
1413 // op: rd
1414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1415 op &= UINT64_C(31);
1416 op <<= 25;
1417 Value |= op;
1418 // op: rs1
1419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1420 op &= UINT64_C(31);
1421 op <<= 14;
1422 Value |= op;
1423 // op: simm10
1424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1425 op &= UINT64_C(1023);
1426 Value |= op;
1427 // op: rcond
1428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1429 op &= UINT64_C(7);
1430 op <<= 10;
1431 Value |= op;
1432 break;
1433 }
1434 case SP::JMPLri:
1435 case SP::LDAri:
1436 case SP::LDCri:
1437 case SP::LDDAri:
1438 case SP::LDDCri:
1439 case SP::LDDFAri:
1440 case SP::LDDFri:
1441 case SP::LDDri:
1442 case SP::LDFAri:
1443 case SP::LDFri:
1444 case SP::LDQFAri:
1445 case SP::LDQFri:
1446 case SP::LDSBAri:
1447 case SP::LDSBri:
1448 case SP::LDSHAri:
1449 case SP::LDSHri:
1450 case SP::LDSTUBAri:
1451 case SP::LDSTUBri:
1452 case SP::LDSWAri:
1453 case SP::LDSWri:
1454 case SP::LDUBAri:
1455 case SP::LDUBri:
1456 case SP::LDUHAri:
1457 case SP::LDUHri:
1458 case SP::LDXAri:
1459 case SP::LDXri:
1460 case SP::LDri:
1461 case SP::MULXri:
1462 case SP::SDIVXri:
1463 case SP::SWAPAri:
1464 case SP::SWAPri:
1465 case SP::UDIVXri: {
1466 // op: rd
1467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1468 op &= UINT64_C(31);
1469 op <<= 25;
1470 Value |= op;
1471 // op: rs1
1472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1473 op &= UINT64_C(31);
1474 op <<= 14;
1475 Value |= op;
1476 // op: simm13
1477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1478 op &= UINT64_C(8191);
1479 Value |= op;
1480 break;
1481 }
1482 case SP::ADDCCri:
1483 case SP::ADDCri:
1484 case SP::ADDEri:
1485 case SP::ADDri:
1486 case SP::ANDCCri:
1487 case SP::ANDNCCri:
1488 case SP::ANDNri:
1489 case SP::ANDri:
1490 case SP::MULSCCri:
1491 case SP::ORCCri:
1492 case SP::ORNCCri:
1493 case SP::ORNri:
1494 case SP::ORri:
1495 case SP::RESTOREri:
1496 case SP::SAVEri:
1497 case SP::SDIVCCri:
1498 case SP::SDIVri:
1499 case SP::SMACri:
1500 case SP::SMULCCri:
1501 case SP::SMULri:
1502 case SP::SUBCCri:
1503 case SP::SUBCri:
1504 case SP::SUBEri:
1505 case SP::SUBri:
1506 case SP::TADDCCTVri:
1507 case SP::TADDCCri:
1508 case SP::TSUBCCTVri:
1509 case SP::TSUBCCri:
1510 case SP::UDIVCCri:
1511 case SP::UDIVri:
1512 case SP::UMACri:
1513 case SP::UMULCCri:
1514 case SP::UMULri:
1515 case SP::WRASRri:
1516 case SP::WRPRri:
1517 case SP::XNORCCri:
1518 case SP::XNORri:
1519 case SP::XORCCri:
1520 case SP::XORri: {
1521 // op: rd
1522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1523 op &= UINT64_C(31);
1524 op <<= 25;
1525 Value |= op;
1526 // op: rs1
1527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1528 op &= UINT64_C(31);
1529 op <<= 14;
1530 Value |= op;
1531 // op: simm13
1532 op = getSImm13OpValue(MI, OpNo: 2, Fixups, STI);
1533 op &= UINT64_C(8191);
1534 Value |= op;
1535 break;
1536 }
1537 case SP::FABSD:
1538 case SP::FABSQ:
1539 case SP::FABSS:
1540 case SP::FDTOI:
1541 case SP::FDTOQ:
1542 case SP::FDTOS:
1543 case SP::FDTOX:
1544 case SP::FEXPAND:
1545 case SP::FITOD:
1546 case SP::FITOQ:
1547 case SP::FITOS:
1548 case SP::FMOVD:
1549 case SP::FMOVQ:
1550 case SP::FMOVS:
1551 case SP::FNEGD:
1552 case SP::FNEGQ:
1553 case SP::FNEGS:
1554 case SP::FNOT2:
1555 case SP::FNOT2S:
1556 case SP::FPACK16:
1557 case SP::FPACKFIX:
1558 case SP::FQTOD:
1559 case SP::FQTOI:
1560 case SP::FQTOS:
1561 case SP::FQTOX:
1562 case SP::FSQRTD:
1563 case SP::FSQRTQ:
1564 case SP::FSQRTS:
1565 case SP::FSRC2:
1566 case SP::FSRC2S:
1567 case SP::FSTOD:
1568 case SP::FSTOI:
1569 case SP::FSTOQ:
1570 case SP::FSTOX:
1571 case SP::FXTOD:
1572 case SP::FXTOQ:
1573 case SP::FXTOS:
1574 case SP::LZCNT:
1575 case SP::MOVDTOX:
1576 case SP::MOVSTOSW:
1577 case SP::MOVSTOUW:
1578 case SP::MOVWTOS:
1579 case SP::MOVXTOD:
1580 case SP::POPCrr: {
1581 // op: rd
1582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1583 op &= UINT64_C(31);
1584 op <<= 25;
1585 Value |= op;
1586 // op: rs2
1587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1588 op &= UINT64_C(31);
1589 Value |= op;
1590 break;
1591 }
1592 case SP::STArr:
1593 case SP::STBArr:
1594 case SP::STDArr:
1595 case SP::STDFArr:
1596 case SP::STFArr:
1597 case SP::STHArr:
1598 case SP::STQFArr:
1599 case SP::STXArr: {
1600 // op: rd
1601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1602 op &= UINT64_C(31);
1603 op <<= 25;
1604 Value |= op;
1605 // op: rs1
1606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1607 op &= UINT64_C(31);
1608 op <<= 14;
1609 Value |= op;
1610 // op: asi
1611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1612 op &= UINT64_C(255);
1613 op <<= 5;
1614 Value |= op;
1615 // op: rs2
1616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1617 op &= UINT64_C(31);
1618 Value |= op;
1619 break;
1620 }
1621 case SP::PREFETCHr:
1622 case SP::STBrr:
1623 case SP::STCrr:
1624 case SP::STDCrr:
1625 case SP::STDFrr:
1626 case SP::STDrr:
1627 case SP::STFrr:
1628 case SP::STHrr:
1629 case SP::STQFrr:
1630 case SP::STXrr:
1631 case SP::STrr: {
1632 // op: rd
1633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1634 op &= UINT64_C(31);
1635 op <<= 25;
1636 Value |= op;
1637 // op: rs1
1638 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1639 op &= UINT64_C(31);
1640 op <<= 14;
1641 Value |= op;
1642 // op: rs2
1643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1644 op &= UINT64_C(31);
1645 Value |= op;
1646 break;
1647 }
1648 case SP::PREFETCHAi:
1649 case SP::PREFETCHi:
1650 case SP::STAri:
1651 case SP::STBAri:
1652 case SP::STBri:
1653 case SP::STCri:
1654 case SP::STDAri:
1655 case SP::STDCri:
1656 case SP::STDFAri:
1657 case SP::STDFri:
1658 case SP::STDri:
1659 case SP::STFAri:
1660 case SP::STFri:
1661 case SP::STHAri:
1662 case SP::STHri:
1663 case SP::STQFAri:
1664 case SP::STQFri:
1665 case SP::STXAri:
1666 case SP::STXri:
1667 case SP::STri: {
1668 // op: rd
1669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1670 op &= UINT64_C(31);
1671 op <<= 25;
1672 Value |= op;
1673 // op: rs1
1674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1675 op &= UINT64_C(31);
1676 op <<= 14;
1677 Value |= op;
1678 // op: simm13
1679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1680 op &= UINT64_C(8191);
1681 Value |= op;
1682 break;
1683 }
1684 case SP::PREFETCHAr: {
1685 // op: rd
1686 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1687 op &= UINT64_C(31);
1688 op <<= 25;
1689 Value |= op;
1690 // op: rs1
1691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1692 op &= UINT64_C(31);
1693 op <<= 14;
1694 Value |= op;
1695 // op: asi
1696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1697 op &= UINT64_C(255);
1698 op <<= 5;
1699 Value |= op;
1700 // op: rs2
1701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1702 op &= UINT64_C(31);
1703 Value |= op;
1704 break;
1705 }
1706 case SP::TICCri:
1707 case SP::TRAPri:
1708 case SP::TXCCri: {
1709 // op: rs1
1710 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1711 op &= UINT64_C(31);
1712 op <<= 14;
1713 Value |= op;
1714 // op: cond
1715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1716 op &= UINT64_C(15);
1717 op <<= 25;
1718 Value |= op;
1719 // op: imm
1720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1721 op &= UINT64_C(255);
1722 Value |= op;
1723 break;
1724 }
1725 case SP::TICCrr:
1726 case SP::TRAPrr:
1727 case SP::TXCCrr: {
1728 // op: rs1
1729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1730 op &= UINT64_C(31);
1731 op <<= 14;
1732 Value |= op;
1733 // op: cond
1734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1735 op &= UINT64_C(15);
1736 op <<= 25;
1737 Value |= op;
1738 // op: rs2
1739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1740 op &= UINT64_C(31);
1741 Value |= op;
1742 break;
1743 }
1744 case SP::BINDrr:
1745 case SP::CALLrr:
1746 case SP::FCMPD:
1747 case SP::FCMPD_V9:
1748 case SP::FCMPQ:
1749 case SP::FCMPQ_V9:
1750 case SP::FCMPS:
1751 case SP::FCMPS_V9:
1752 case SP::FLUSHrr:
1753 case SP::LDCSRrr:
1754 case SP::LDFSRrr:
1755 case SP::LDXFSRrr:
1756 case SP::PWRPSRrr:
1757 case SP::RETTrr:
1758 case SP::STCSRrr:
1759 case SP::STDCQrr:
1760 case SP::STDFQrr:
1761 case SP::STFSRrr:
1762 case SP::STXFSRrr:
1763 case SP::WRPSRrr:
1764 case SP::WRTBRrr:
1765 case SP::WRWIMrr: {
1766 // op: rs1
1767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1768 op &= UINT64_C(31);
1769 op <<= 14;
1770 Value |= op;
1771 // op: rs2
1772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1773 op &= UINT64_C(31);
1774 Value |= op;
1775 break;
1776 }
1777 case SP::BINDri:
1778 case SP::CALLri:
1779 case SP::FLUSHri:
1780 case SP::LDCSRri:
1781 case SP::LDFSRri:
1782 case SP::LDXFSRri:
1783 case SP::RETTri:
1784 case SP::STCSRri:
1785 case SP::STDCQri:
1786 case SP::STDFQri:
1787 case SP::STFSRri:
1788 case SP::STXFSRri:
1789 case SP::TAIL_CALLri: {
1790 // op: rs1
1791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1792 op &= UINT64_C(31);
1793 op <<= 14;
1794 Value |= op;
1795 // op: simm13
1796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1797 op &= UINT64_C(8191);
1798 Value |= op;
1799 break;
1800 }
1801 case SP::PWRPSRri:
1802 case SP::WRPSRri:
1803 case SP::WRTBRri:
1804 case SP::WRWIMri: {
1805 // op: rs1
1806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1807 op &= UINT64_C(31);
1808 op <<= 14;
1809 Value |= op;
1810 // op: simm13
1811 op = getSImm13OpValue(MI, OpNo: 1, Fixups, STI);
1812 op &= UINT64_C(8191);
1813 Value |= op;
1814 break;
1815 }
1816 case SP::CMASK8:
1817 case SP::CMASK16:
1818 case SP::CMASK32: {
1819 // op: rs2
1820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1821 op &= UINT64_C(31);
1822 Value |= op;
1823 break;
1824 }
1825 case SP::MEMBARi:
1826 case SP::RET:
1827 case SP::RETL: {
1828 // op: simm13
1829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1830 op &= UINT64_C(8191);
1831 Value |= op;
1832 break;
1833 }
1834 case SP::SIR: {
1835 // op: simm13
1836 op = getSImm13OpValue(MI, OpNo: 0, Fixups, STI);
1837 op &= UINT64_C(8191);
1838 Value |= op;
1839 break;
1840 }
1841 default:
1842 std::string msg;
1843 raw_string_ostream Msg(msg);
1844 Msg << "Not supported instr: " << MI;
1845 report_fatal_error(reason: Msg.str().c_str());
1846 }
1847 return Value;
1848}
1849
1850#ifdef GET_OPERAND_BIT_OFFSET
1851#undef GET_OPERAND_BIT_OFFSET
1852
1853uint32_t SparcMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
1854 unsigned OpNum,
1855 const MCSubtargetInfo &STI) const {
1856 switch (MI.getOpcode()) {
1857 case SP::DONE:
1858 case SP::FLUSH:
1859 case SP::FLUSHW:
1860 case SP::NOP:
1861 case SP::RESTORED:
1862 case SP::RETRY:
1863 case SP::SAVED:
1864 case SP::SHUTDOWN:
1865 case SP::SIAM:
1866 case SP::STBAR:
1867 case SP::TA1:
1868 case SP::TA3:
1869 case SP::TA5: {
1870 break;
1871 }
1872 case SP::CALL:
1873 case SP::TAIL_CALL:
1874 case SP::TLS_CALL: {
1875 switch (OpNum) {
1876 case 0:
1877 // op: disp
1878 return 0;
1879 }
1880 break;
1881 }
1882 case SP::BPR:
1883 case SP::BPRA:
1884 case SP::BPRANT:
1885 case SP::BPRNT: {
1886 switch (OpNum) {
1887 case 0:
1888 // op: imm16
1889 return 0;
1890 case 2:
1891 // op: rs1
1892 return 14;
1893 case 1:
1894 // op: rcond
1895 return 25;
1896 }
1897 break;
1898 }
1899 case SP::BCOND:
1900 case SP::BCONDA:
1901 case SP::CBCOND:
1902 case SP::CBCONDA:
1903 case SP::FBCOND:
1904 case SP::FBCONDA: {
1905 switch (OpNum) {
1906 case 0:
1907 // op: imm22
1908 return 0;
1909 case 1:
1910 // op: cond
1911 return 25;
1912 }
1913 break;
1914 }
1915 case SP::BA:
1916 case SP::UNIMP: {
1917 switch (OpNum) {
1918 case 0:
1919 // op: imm22
1920 return 0;
1921 }
1922 break;
1923 }
1924 case SP::V9MOVFCCrr: {
1925 switch (OpNum) {
1926 case 0:
1927 // op: rd
1928 return 25;
1929 case 1:
1930 // op: cc
1931 return 11;
1932 case 4:
1933 // op: cond
1934 return 14;
1935 case 2:
1936 // op: rs2
1937 return 0;
1938 }
1939 break;
1940 }
1941 case SP::V9MOVFCCri: {
1942 switch (OpNum) {
1943 case 0:
1944 // op: rd
1945 return 25;
1946 case 1:
1947 // op: cc
1948 return 11;
1949 case 4:
1950 // op: cond
1951 return 14;
1952 case 2:
1953 // op: simm11
1954 return 0;
1955 }
1956 break;
1957 }
1958 case SP::FMOVRD:
1959 case SP::FMOVRQ:
1960 case SP::FMOVRS:
1961 case SP::MOVRrr: {
1962 switch (OpNum) {
1963 case 0:
1964 // op: rd
1965 return 25;
1966 case 1:
1967 // op: rs1
1968 return 14;
1969 case 2:
1970 // op: rs2
1971 return 0;
1972 case 4:
1973 // op: rcond
1974 return 10;
1975 }
1976 break;
1977 }
1978 case SP::ADDCCrr:
1979 case SP::ADDCrr:
1980 case SP::ADDErr:
1981 case SP::ADDXC:
1982 case SP::ADDXCCC:
1983 case SP::ADDrr:
1984 case SP::ALIGNADDR:
1985 case SP::ALIGNADDRL:
1986 case SP::ANDCCrr:
1987 case SP::ANDNCCrr:
1988 case SP::ANDNrr:
1989 case SP::ANDrr:
1990 case SP::ARRAY8:
1991 case SP::ARRAY16:
1992 case SP::ARRAY32:
1993 case SP::BMASK:
1994 case SP::BSHUFFLE:
1995 case SP::CASAri:
1996 case SP::CASXAri:
1997 case SP::EDGE8:
1998 case SP::EDGE8L:
1999 case SP::EDGE8LN:
2000 case SP::EDGE8N:
2001 case SP::EDGE16:
2002 case SP::EDGE16L:
2003 case SP::EDGE16LN:
2004 case SP::EDGE16N:
2005 case SP::EDGE32:
2006 case SP::EDGE32L:
2007 case SP::EDGE32LN:
2008 case SP::EDGE32N:
2009 case SP::FADDD:
2010 case SP::FADDQ:
2011 case SP::FADDS:
2012 case SP::FALIGNADATA:
2013 case SP::FAND:
2014 case SP::FANDNOT1:
2015 case SP::FANDNOT1S:
2016 case SP::FANDNOT2:
2017 case SP::FANDNOT2S:
2018 case SP::FANDS:
2019 case SP::FCHKSM16:
2020 case SP::FCMPEQ16:
2021 case SP::FCMPEQ32:
2022 case SP::FCMPGT16:
2023 case SP::FCMPGT32:
2024 case SP::FCMPLE16:
2025 case SP::FCMPLE32:
2026 case SP::FCMPNE16:
2027 case SP::FCMPNE32:
2028 case SP::FDIVD:
2029 case SP::FDIVQ:
2030 case SP::FDIVS:
2031 case SP::FDMULQ:
2032 case SP::FHADDD:
2033 case SP::FHADDS:
2034 case SP::FHSUBD:
2035 case SP::FHSUBS:
2036 case SP::FLCMPD:
2037 case SP::FLCMPS:
2038 case SP::FMEAN16:
2039 case SP::FMUL8SUX16:
2040 case SP::FMUL8ULX16:
2041 case SP::FMUL8X16:
2042 case SP::FMUL8X16AL:
2043 case SP::FMUL8X16AU:
2044 case SP::FMULD:
2045 case SP::FMULD8SUX16:
2046 case SP::FMULD8ULX16:
2047 case SP::FMULQ:
2048 case SP::FMULS:
2049 case SP::FNADDD:
2050 case SP::FNADDS:
2051 case SP::FNAND:
2052 case SP::FNANDS:
2053 case SP::FNHADDD:
2054 case SP::FNHADDS:
2055 case SP::FNMULD:
2056 case SP::FNMULS:
2057 case SP::FNOR:
2058 case SP::FNORS:
2059 case SP::FNSMULD:
2060 case SP::FOR:
2061 case SP::FORNOT1:
2062 case SP::FORNOT1S:
2063 case SP::FORNOT2:
2064 case SP::FORNOT2S:
2065 case SP::FORS:
2066 case SP::FPACK32:
2067 case SP::FPADD16:
2068 case SP::FPADD16S:
2069 case SP::FPADD32:
2070 case SP::FPADD32S:
2071 case SP::FPADD64:
2072 case SP::FPMERGE:
2073 case SP::FPSUB16:
2074 case SP::FPSUB16S:
2075 case SP::FPSUB32:
2076 case SP::FPSUB32S:
2077 case SP::FSLAS16:
2078 case SP::FSLAS32:
2079 case SP::FSLL16:
2080 case SP::FSLL32:
2081 case SP::FSMULD:
2082 case SP::FSRA16:
2083 case SP::FSRA32:
2084 case SP::FSRL16:
2085 case SP::FSRL32:
2086 case SP::FSUBD:
2087 case SP::FSUBQ:
2088 case SP::FSUBS:
2089 case SP::FXNOR:
2090 case SP::FXNORS:
2091 case SP::FXOR:
2092 case SP::FXORS:
2093 case SP::GDOP_LDXrr:
2094 case SP::GDOP_LDrr:
2095 case SP::JMPLrr:
2096 case SP::LDCrr:
2097 case SP::LDDCrr:
2098 case SP::LDDFrr:
2099 case SP::LDDrr:
2100 case SP::LDFrr:
2101 case SP::LDQFrr:
2102 case SP::LDSBrr:
2103 case SP::LDSHrr:
2104 case SP::LDSTUBrr:
2105 case SP::LDSWrr:
2106 case SP::LDUBrr:
2107 case SP::LDUHrr:
2108 case SP::LDXrr:
2109 case SP::LDrr:
2110 case SP::MULSCCrr:
2111 case SP::MULXrr:
2112 case SP::ORCCrr:
2113 case SP::ORNCCrr:
2114 case SP::ORNrr:
2115 case SP::ORrr:
2116 case SP::PDIST:
2117 case SP::PDISTN:
2118 case SP::RESTORErr:
2119 case SP::SAVErr:
2120 case SP::SDIVCCrr:
2121 case SP::SDIVXrr:
2122 case SP::SDIVrr:
2123 case SP::SLLXrr:
2124 case SP::SLLrr:
2125 case SP::SMACrr:
2126 case SP::SMULCCrr:
2127 case SP::SMULrr:
2128 case SP::SRAXrr:
2129 case SP::SRArr:
2130 case SP::SRLXrr:
2131 case SP::SRLrr:
2132 case SP::SUBCCrr:
2133 case SP::SUBCrr:
2134 case SP::SUBErr:
2135 case SP::SUBrr:
2136 case SP::SWAPrr:
2137 case SP::TADDCCTVrr:
2138 case SP::TADDCCrr:
2139 case SP::TLS_ADDrr:
2140 case SP::TLS_LDXrr:
2141 case SP::TLS_LDrr:
2142 case SP::TSUBCCTVrr:
2143 case SP::TSUBCCrr:
2144 case SP::UDIVCCrr:
2145 case SP::UDIVXrr:
2146 case SP::UDIVrr:
2147 case SP::UMACrr:
2148 case SP::UMULCCrr:
2149 case SP::UMULXHI:
2150 case SP::UMULrr:
2151 case SP::V9FCMPD:
2152 case SP::V9FCMPED:
2153 case SP::V9FCMPEQ:
2154 case SP::V9FCMPES:
2155 case SP::V9FCMPQ:
2156 case SP::V9FCMPS:
2157 case SP::WRASRrr:
2158 case SP::WRPRrr:
2159 case SP::XMULX:
2160 case SP::XMULXHI:
2161 case SP::XNORCCrr:
2162 case SP::XNORrr:
2163 case SP::XORCCrr:
2164 case SP::XORrr: {
2165 switch (OpNum) {
2166 case 0:
2167 // op: rd
2168 return 25;
2169 case 1:
2170 // op: rs1
2171 return 14;
2172 case 2:
2173 // op: rs2
2174 return 0;
2175 }
2176 break;
2177 }
2178 case SP::SLLXri:
2179 case SP::SLLri:
2180 case SP::SRAXri:
2181 case SP::SRAri:
2182 case SP::SRLXri:
2183 case SP::SRLri: {
2184 switch (OpNum) {
2185 case 0:
2186 // op: rd
2187 return 25;
2188 case 1:
2189 // op: rs1
2190 return 14;
2191 case 2:
2192 // op: shcnt
2193 return 0;
2194 }
2195 break;
2196 }
2197 case SP::MOVRri: {
2198 switch (OpNum) {
2199 case 0:
2200 // op: rd
2201 return 25;
2202 case 1:
2203 // op: rs1
2204 return 14;
2205 case 2:
2206 // op: simm10
2207 return 0;
2208 case 4:
2209 // op: rcond
2210 return 10;
2211 }
2212 break;
2213 }
2214 case SP::ADDCCri:
2215 case SP::ADDCri:
2216 case SP::ADDEri:
2217 case SP::ADDri:
2218 case SP::ANDCCri:
2219 case SP::ANDNCCri:
2220 case SP::ANDNri:
2221 case SP::ANDri:
2222 case SP::JMPLri:
2223 case SP::LDAri:
2224 case SP::LDCri:
2225 case SP::LDDAri:
2226 case SP::LDDCri:
2227 case SP::LDDFAri:
2228 case SP::LDDFri:
2229 case SP::LDDri:
2230 case SP::LDFAri:
2231 case SP::LDFri:
2232 case SP::LDQFAri:
2233 case SP::LDQFri:
2234 case SP::LDSBAri:
2235 case SP::LDSBri:
2236 case SP::LDSHAri:
2237 case SP::LDSHri:
2238 case SP::LDSTUBAri:
2239 case SP::LDSTUBri:
2240 case SP::LDSWAri:
2241 case SP::LDSWri:
2242 case SP::LDUBAri:
2243 case SP::LDUBri:
2244 case SP::LDUHAri:
2245 case SP::LDUHri:
2246 case SP::LDXAri:
2247 case SP::LDXri:
2248 case SP::LDri:
2249 case SP::MULSCCri:
2250 case SP::MULXri:
2251 case SP::ORCCri:
2252 case SP::ORNCCri:
2253 case SP::ORNri:
2254 case SP::ORri:
2255 case SP::RESTOREri:
2256 case SP::SAVEri:
2257 case SP::SDIVCCri:
2258 case SP::SDIVXri:
2259 case SP::SDIVri:
2260 case SP::SMACri:
2261 case SP::SMULCCri:
2262 case SP::SMULri:
2263 case SP::SUBCCri:
2264 case SP::SUBCri:
2265 case SP::SUBEri:
2266 case SP::SUBri:
2267 case SP::SWAPAri:
2268 case SP::SWAPri:
2269 case SP::TADDCCTVri:
2270 case SP::TADDCCri:
2271 case SP::TSUBCCTVri:
2272 case SP::TSUBCCri:
2273 case SP::UDIVCCri:
2274 case SP::UDIVXri:
2275 case SP::UDIVri:
2276 case SP::UMACri:
2277 case SP::UMULCCri:
2278 case SP::UMULri:
2279 case SP::WRASRri:
2280 case SP::WRPRri:
2281 case SP::XNORCCri:
2282 case SP::XNORri:
2283 case SP::XORCCri:
2284 case SP::XORri: {
2285 switch (OpNum) {
2286 case 0:
2287 // op: rd
2288 return 25;
2289 case 1:
2290 // op: rs1
2291 return 14;
2292 case 2:
2293 // op: simm13
2294 return 0;
2295 }
2296 break;
2297 }
2298 case SP::LDArr:
2299 case SP::LDDArr:
2300 case SP::LDDFArr:
2301 case SP::LDFArr:
2302 case SP::LDQFArr:
2303 case SP::LDSBArr:
2304 case SP::LDSHArr:
2305 case SP::LDSTUBArr:
2306 case SP::LDSWArr:
2307 case SP::LDUBArr:
2308 case SP::LDUHArr:
2309 case SP::LDXArr:
2310 case SP::SWAPArr: {
2311 switch (OpNum) {
2312 case 0:
2313 // op: rd
2314 return 25;
2315 case 1:
2316 // op: rs1
2317 return 14;
2318 case 3:
2319 // op: asi
2320 return 5;
2321 case 2:
2322 // op: rs2
2323 return 0;
2324 }
2325 break;
2326 }
2327 case SP::CASArr:
2328 case SP::CASXArr: {
2329 switch (OpNum) {
2330 case 0:
2331 // op: rd
2332 return 25;
2333 case 1:
2334 // op: rs1
2335 return 14;
2336 case 4:
2337 // op: asi
2338 return 5;
2339 case 2:
2340 // op: rs2
2341 return 0;
2342 }
2343 break;
2344 }
2345 case SP::FNOT1:
2346 case SP::FNOT1S:
2347 case SP::FSRC1:
2348 case SP::FSRC1S:
2349 case SP::RDASR:
2350 case SP::RDPR: {
2351 switch (OpNum) {
2352 case 0:
2353 // op: rd
2354 return 25;
2355 case 1:
2356 // op: rs1
2357 return 14;
2358 }
2359 break;
2360 }
2361 case SP::FABSD:
2362 case SP::FABSQ:
2363 case SP::FABSS:
2364 case SP::FDTOI:
2365 case SP::FDTOQ:
2366 case SP::FDTOS:
2367 case SP::FDTOX:
2368 case SP::FEXPAND:
2369 case SP::FITOD:
2370 case SP::FITOQ:
2371 case SP::FITOS:
2372 case SP::FMOVD:
2373 case SP::FMOVQ:
2374 case SP::FMOVS:
2375 case SP::FNEGD:
2376 case SP::FNEGQ:
2377 case SP::FNEGS:
2378 case SP::FNOT2:
2379 case SP::FNOT2S:
2380 case SP::FPACK16:
2381 case SP::FPACKFIX:
2382 case SP::FQTOD:
2383 case SP::FQTOI:
2384 case SP::FQTOS:
2385 case SP::FQTOX:
2386 case SP::FSQRTD:
2387 case SP::FSQRTQ:
2388 case SP::FSQRTS:
2389 case SP::FSRC2:
2390 case SP::FSRC2S:
2391 case SP::FSTOD:
2392 case SP::FSTOI:
2393 case SP::FSTOQ:
2394 case SP::FSTOX:
2395 case SP::FXTOD:
2396 case SP::FXTOQ:
2397 case SP::FXTOS:
2398 case SP::LZCNT:
2399 case SP::MOVDTOX:
2400 case SP::MOVSTOSW:
2401 case SP::MOVSTOUW:
2402 case SP::MOVWTOS:
2403 case SP::MOVXTOD:
2404 case SP::POPCrr: {
2405 switch (OpNum) {
2406 case 0:
2407 // op: rd
2408 return 25;
2409 case 1:
2410 // op: rs2
2411 return 0;
2412 }
2413 break;
2414 }
2415 case SP::FMOVD_FCC:
2416 case SP::FMOVD_ICC:
2417 case SP::FMOVD_XCC:
2418 case SP::FMOVQ_FCC:
2419 case SP::FMOVQ_ICC:
2420 case SP::FMOVQ_XCC:
2421 case SP::FMOVS_FCC:
2422 case SP::FMOVS_ICC:
2423 case SP::FMOVS_XCC:
2424 case SP::MOVFCCrr:
2425 case SP::MOVICCrr:
2426 case SP::MOVXCCrr: {
2427 switch (OpNum) {
2428 case 0:
2429 // op: rd
2430 return 25;
2431 case 3:
2432 // op: cond
2433 return 14;
2434 case 1:
2435 // op: rs2
2436 return 0;
2437 }
2438 break;
2439 }
2440 case SP::MOVFCCri:
2441 case SP::MOVICCri:
2442 case SP::MOVXCCri: {
2443 switch (OpNum) {
2444 case 0:
2445 // op: rd
2446 return 25;
2447 case 3:
2448 // op: cond
2449 return 14;
2450 case 1:
2451 // op: simm11
2452 return 0;
2453 }
2454 break;
2455 }
2456 case SP::V9FMOVD_FCC:
2457 case SP::V9FMOVQ_FCC:
2458 case SP::V9FMOVS_FCC: {
2459 switch (OpNum) {
2460 case 0:
2461 // op: rd
2462 return 25;
2463 case 4:
2464 // op: cond
2465 return 14;
2466 case 1:
2467 // op: opf_cc
2468 return 11;
2469 case 2:
2470 // op: rs2
2471 return 0;
2472 }
2473 break;
2474 }
2475 case SP::FONE:
2476 case SP::FONES:
2477 case SP::FZERO:
2478 case SP::FZEROS:
2479 case SP::RDFQ:
2480 case SP::RDPSR:
2481 case SP::RDTBR:
2482 case SP::RDWIM: {
2483 switch (OpNum) {
2484 case 0:
2485 // op: rd
2486 return 25;
2487 }
2488 break;
2489 }
2490 case SP::BINDrr:
2491 case SP::CALLrr:
2492 case SP::FCMPD:
2493 case SP::FCMPD_V9:
2494 case SP::FCMPQ:
2495 case SP::FCMPQ_V9:
2496 case SP::FCMPS:
2497 case SP::FCMPS_V9:
2498 case SP::FLUSHrr:
2499 case SP::LDCSRrr:
2500 case SP::LDFSRrr:
2501 case SP::LDXFSRrr:
2502 case SP::PWRPSRrr:
2503 case SP::RETTrr:
2504 case SP::STCSRrr:
2505 case SP::STDCQrr:
2506 case SP::STDFQrr:
2507 case SP::STFSRrr:
2508 case SP::STXFSRrr:
2509 case SP::WRPSRrr:
2510 case SP::WRTBRrr:
2511 case SP::WRWIMrr: {
2512 switch (OpNum) {
2513 case 0:
2514 // op: rs1
2515 return 14;
2516 case 1:
2517 // op: rs2
2518 return 0;
2519 }
2520 break;
2521 }
2522 case SP::BINDri:
2523 case SP::CALLri:
2524 case SP::FLUSHri:
2525 case SP::LDCSRri:
2526 case SP::LDFSRri:
2527 case SP::LDXFSRri:
2528 case SP::PWRPSRri:
2529 case SP::RETTri:
2530 case SP::STCSRri:
2531 case SP::STDCQri:
2532 case SP::STDFQri:
2533 case SP::STFSRri:
2534 case SP::STXFSRri:
2535 case SP::TAIL_CALLri:
2536 case SP::WRPSRri:
2537 case SP::WRTBRri:
2538 case SP::WRWIMri: {
2539 switch (OpNum) {
2540 case 0:
2541 // op: rs1
2542 return 14;
2543 case 1:
2544 // op: simm13
2545 return 0;
2546 }
2547 break;
2548 }
2549 case SP::TICCri:
2550 case SP::TRAPri:
2551 case SP::TXCCri: {
2552 switch (OpNum) {
2553 case 0:
2554 // op: rs1
2555 return 14;
2556 case 2:
2557 // op: cond
2558 return 25;
2559 case 1:
2560 // op: imm
2561 return 0;
2562 }
2563 break;
2564 }
2565 case SP::TICCrr:
2566 case SP::TRAPrr:
2567 case SP::TXCCrr: {
2568 switch (OpNum) {
2569 case 0:
2570 // op: rs1
2571 return 14;
2572 case 2:
2573 // op: cond
2574 return 25;
2575 case 1:
2576 // op: rs2
2577 return 0;
2578 }
2579 break;
2580 }
2581 case SP::CMASK8:
2582 case SP::CMASK16:
2583 case SP::CMASK32: {
2584 switch (OpNum) {
2585 case 0:
2586 // op: rs2
2587 return 0;
2588 }
2589 break;
2590 }
2591 case SP::MEMBARi:
2592 case SP::RET:
2593 case SP::RETL:
2594 case SP::SIR: {
2595 switch (OpNum) {
2596 case 0:
2597 // op: simm13
2598 return 0;
2599 }
2600 break;
2601 }
2602 case SP::BPICC:
2603 case SP::BPICCA:
2604 case SP::BPICCANT:
2605 case SP::BPICCNT:
2606 case SP::BPXCC:
2607 case SP::BPXCCA:
2608 case SP::BPXCCANT:
2609 case SP::BPXCCNT:
2610 case SP::FBCONDA_V9:
2611 case SP::FBCOND_V9: {
2612 switch (OpNum) {
2613 case 1:
2614 // op: cond
2615 return 25;
2616 case 0:
2617 // op: imm19
2618 return 0;
2619 }
2620 break;
2621 }
2622 case SP::SETHIi: {
2623 switch (OpNum) {
2624 case 1:
2625 // op: imm22
2626 return 0;
2627 case 0:
2628 // op: rd
2629 return 25;
2630 }
2631 break;
2632 }
2633 case SP::BPFCC:
2634 case SP::BPFCCA:
2635 case SP::BPFCCANT:
2636 case SP::BPFCCNT: {
2637 switch (OpNum) {
2638 case 2:
2639 // op: cc
2640 return 20;
2641 case 1:
2642 // op: cond
2643 return 25;
2644 case 0:
2645 // op: imm19
2646 return 0;
2647 }
2648 break;
2649 }
2650 case SP::PREFETCHr:
2651 case SP::STBrr:
2652 case SP::STCrr:
2653 case SP::STDCrr:
2654 case SP::STDFrr:
2655 case SP::STDrr:
2656 case SP::STFrr:
2657 case SP::STHrr:
2658 case SP::STQFrr:
2659 case SP::STXrr:
2660 case SP::STrr: {
2661 switch (OpNum) {
2662 case 2:
2663 // op: rd
2664 return 25;
2665 case 0:
2666 // op: rs1
2667 return 14;
2668 case 1:
2669 // op: rs2
2670 return 0;
2671 }
2672 break;
2673 }
2674 case SP::PREFETCHAi:
2675 case SP::PREFETCHi:
2676 case SP::STAri:
2677 case SP::STBAri:
2678 case SP::STBri:
2679 case SP::STCri:
2680 case SP::STDAri:
2681 case SP::STDCri:
2682 case SP::STDFAri:
2683 case SP::STDFri:
2684 case SP::STDri:
2685 case SP::STFAri:
2686 case SP::STFri:
2687 case SP::STHAri:
2688 case SP::STHri:
2689 case SP::STQFAri:
2690 case SP::STQFri:
2691 case SP::STXAri:
2692 case SP::STXri:
2693 case SP::STri: {
2694 switch (OpNum) {
2695 case 2:
2696 // op: rd
2697 return 25;
2698 case 0:
2699 // op: rs1
2700 return 14;
2701 case 1:
2702 // op: simm13
2703 return 0;
2704 }
2705 break;
2706 }
2707 case SP::STArr:
2708 case SP::STBArr:
2709 case SP::STDArr:
2710 case SP::STDFArr:
2711 case SP::STFArr:
2712 case SP::STHArr:
2713 case SP::STQFArr:
2714 case SP::STXArr: {
2715 switch (OpNum) {
2716 case 2:
2717 // op: rd
2718 return 25;
2719 case 0:
2720 // op: rs1
2721 return 14;
2722 case 3:
2723 // op: asi
2724 return 5;
2725 case 1:
2726 // op: rs2
2727 return 0;
2728 }
2729 break;
2730 }
2731 case SP::PREFETCHAr: {
2732 switch (OpNum) {
2733 case 3:
2734 // op: rd
2735 return 25;
2736 case 0:
2737 // op: rs1
2738 return 14;
2739 case 2:
2740 // op: asi
2741 return 5;
2742 case 1:
2743 // op: rs2
2744 return 0;
2745 }
2746 break;
2747 }
2748 }
2749 std::string msg;
2750 raw_string_ostream Msg(msg);
2751 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
2752 report_fatal_error(Msg.str().c_str());
2753}
2754
2755#endif // GET_OPERAND_BIT_OFFSET
2756
2757