1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass SystemZMCRegisterClasses[];
17
18namespace SystemZ {
19enum {
20 NoRegister,
21 CC = 1,
22 FPC = 2,
23 A0 = 3,
24 A1 = 4,
25 A2 = 5,
26 A3 = 6,
27 A4 = 7,
28 A5 = 8,
29 A6 = 9,
30 A7 = 10,
31 A8 = 11,
32 A9 = 12,
33 A10 = 13,
34 A11 = 14,
35 A12 = 15,
36 A13 = 16,
37 A14 = 17,
38 A15 = 18,
39 C0 = 19,
40 C1 = 20,
41 C2 = 21,
42 C3 = 22,
43 C4 = 23,
44 C5 = 24,
45 C6 = 25,
46 C7 = 26,
47 C8 = 27,
48 C9 = 28,
49 C10 = 29,
50 C11 = 30,
51 C12 = 31,
52 C13 = 32,
53 C14 = 33,
54 C15 = 34,
55 V0 = 35,
56 V1 = 36,
57 V2 = 37,
58 V3 = 38,
59 V4 = 39,
60 V5 = 40,
61 V6 = 41,
62 V7 = 42,
63 V8 = 43,
64 V9 = 44,
65 V10 = 45,
66 V11 = 46,
67 V12 = 47,
68 V13 = 48,
69 V14 = 49,
70 V15 = 50,
71 V16 = 51,
72 V17 = 52,
73 V18 = 53,
74 V19 = 54,
75 V20 = 55,
76 V21 = 56,
77 V22 = 57,
78 V23 = 58,
79 V24 = 59,
80 V25 = 60,
81 V26 = 61,
82 V27 = 62,
83 V28 = 63,
84 V29 = 64,
85 V30 = 65,
86 V31 = 66,
87 F0D = 67,
88 F1D = 68,
89 F2D = 69,
90 F3D = 70,
91 F4D = 71,
92 F5D = 72,
93 F6D = 73,
94 F7D = 74,
95 F8D = 75,
96 F9D = 76,
97 F10D = 77,
98 F11D = 78,
99 F12D = 79,
100 F13D = 80,
101 F14D = 81,
102 F15D = 82,
103 F16D = 83,
104 F17D = 84,
105 F18D = 85,
106 F19D = 86,
107 F20D = 87,
108 F21D = 88,
109 F22D = 89,
110 F23D = 90,
111 F24D = 91,
112 F25D = 92,
113 F26D = 93,
114 F27D = 94,
115 F28D = 95,
116 F29D = 96,
117 F30D = 97,
118 F31D = 98,
119 F0Q = 99,
120 F1Q = 100,
121 F4Q = 101,
122 F5Q = 102,
123 F8Q = 103,
124 F9Q = 104,
125 F12Q = 105,
126 F13Q = 106,
127 F0S = 107,
128 F1S = 108,
129 F2S = 109,
130 F3S = 110,
131 F4S = 111,
132 F5S = 112,
133 F6S = 113,
134 F7S = 114,
135 F8S = 115,
136 F9S = 116,
137 F10S = 117,
138 F11S = 118,
139 F12S = 119,
140 F13S = 120,
141 F14S = 121,
142 F15S = 122,
143 F16S = 123,
144 F17S = 124,
145 F18S = 125,
146 F19S = 126,
147 F20S = 127,
148 F21S = 128,
149 F22S = 129,
150 F23S = 130,
151 F24S = 131,
152 F25S = 132,
153 F26S = 133,
154 F27S = 134,
155 F28S = 135,
156 F29S = 136,
157 F30S = 137,
158 F31S = 138,
159 R0D = 139,
160 R1D = 140,
161 R2D = 141,
162 R3D = 142,
163 R4D = 143,
164 R5D = 144,
165 R6D = 145,
166 R7D = 146,
167 R8D = 147,
168 R9D = 148,
169 R10D = 149,
170 R11D = 150,
171 R12D = 151,
172 R13D = 152,
173 R14D = 153,
174 R15D = 154,
175 R0H = 155,
176 R1H = 156,
177 R2H = 157,
178 R3H = 158,
179 R4H = 159,
180 R5H = 160,
181 R6H = 161,
182 R7H = 162,
183 R8H = 163,
184 R9H = 164,
185 R10H = 165,
186 R11H = 166,
187 R12H = 167,
188 R13H = 168,
189 R14H = 169,
190 R15H = 170,
191 R0L = 171,
192 R1L = 172,
193 R2L = 173,
194 R3L = 174,
195 R4L = 175,
196 R5L = 176,
197 R6L = 177,
198 R7L = 178,
199 R8L = 179,
200 R9L = 180,
201 R10L = 181,
202 R11L = 182,
203 R12L = 183,
204 R13L = 184,
205 R14L = 185,
206 R15L = 186,
207 R0Q = 187,
208 R2Q = 188,
209 R4Q = 189,
210 R6Q = 190,
211 R8Q = 191,
212 R10Q = 192,
213 R12Q = 193,
214 R14Q = 194,
215 NUM_TARGET_REGS // 195
216};
217} // end namespace SystemZ
218
219// Register classes
220
221namespace SystemZ {
222enum {
223 GRX32BitRegClassID = 0,
224 VR32BitRegClassID = 1,
225 AR32BitRegClassID = 2,
226 FP32BitRegClassID = 3,
227 GR32BitRegClassID = 4,
228 GRH32BitRegClassID = 5,
229 ADDR32BitRegClassID = 6,
230 CCRRegClassID = 7,
231 FPCRegsRegClassID = 8,
232 AnyRegBitRegClassID = 9,
233 AnyRegBit_with_subreg_h32_in_FP32BitRegClassID = 10,
234 VR64BitRegClassID = 11,
235 AnyRegBit_with_subreg_h64RegClassID = 12,
236 CR64BitRegClassID = 13,
237 FP64BitRegClassID = 14,
238 GR64BitRegClassID = 15,
239 ADDR64BitRegClassID = 16,
240 VR128BitRegClassID = 17,
241 VF128BitRegClassID = 18,
242 FP128BitRegClassID = 19,
243 GR128BitRegClassID = 20,
244 ADDR128BitRegClassID = 21,
245
246};
247} // end namespace SystemZ
248
249
250// Subregister indices
251
252namespace SystemZ {
253enum : uint16_t {
254 NoSubRegister,
255 subreg_h32, // 1
256 subreg_h64, // 2
257 subreg_l32, // 3
258 subreg_l64, // 4
259 subreg_lh32, // 5
260 subreg_ll32, // 6
261 NUM_TARGET_SUBREGS
262};
263} // end namespace SystemZ
264
265// Register pressure sets enum.
266namespace SystemZ {
267enum RegisterPressureSets {
268 FP32Bit = 0,
269 GR32Bit = 1,
270 GRH32Bit = 2,
271 GRX32Bit = 3,
272 VR32Bit = 4,
273};
274} // end namespace SystemZ
275
276} // end namespace llvm
277
278#endif // GET_REGINFO_ENUM
279
280/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
281|* *|
282|* MC Register Information *|
283|* *|
284|* Automatically generated file, do not edit! *|
285|* *|
286\*===----------------------------------------------------------------------===*/
287
288
289#ifdef GET_REGINFO_MC_DESC
290#undef GET_REGINFO_MC_DESC
291
292namespace llvm {
293
294extern const int16_t SystemZRegDiffLists[] = {
295 /* 0 */ -40, -32, 0,
296 /* 3 */ -48, 32, -16, -15, 32, -16, 0,
297 /* 10 */ -47, 32, -16, -15, 32, -16, 0,
298 /* 17 */ -46, 32, -16, -15, 32, -16, 0,
299 /* 24 */ -45, 32, -16, -15, 32, -16, 0,
300 /* 31 */ -44, 32, -16, -15, 32, -16, 0,
301 /* 38 */ -43, 32, -16, -15, 32, -16, 0,
302 /* 45 */ -42, 32, -16, -15, 32, -16, 0,
303 /* 52 */ -41, 32, -16, -15, 32, -16, 0,
304 /* 59 */ 1, 1, 1, 0,
305 /* 63 */ 2, 0,
306 /* 65 */ -32, 40, -38, 40, 0,
307 /* 70 */ -30, 40, -38, 40, 0,
308 /* 75 */ -28, 40, -38, 40, 0,
309 /* 80 */ -26, 40, -38, 40, 0,
310 /* 85 */ -32, 40, 0,
311 /* 88 */ -16, 40, 0,
312 /* 91 */ 32, 40, 0,
313 /* 94 */ -32, 41, 0,
314 /* 97 */ -16, 41, 0,
315 /* 100 */ -32, 42, 0,
316 /* 103 */ -16, 42, 0,
317 /* 106 */ -32, 43, 0,
318 /* 109 */ -16, 43, 0,
319 /* 112 */ -32, 44, 0,
320 /* 115 */ -16, 44, 0,
321 /* 118 */ -32, 45, 0,
322 /* 121 */ -16, 45, 0,
323 /* 124 */ -32, 46, 0,
324 /* 127 */ -16, 46, 0,
325 /* 130 */ -32, 47, 0,
326 /* 133 */ -16, 47, 0,
327 /* 136 */ -32, 48, 0,
328 /* 139 */ -16, 48, 0,
329 /* 142 */ -40, -32, 56, 0,
330 /* 146 */ -40, -32, 58, 0,
331 /* 150 */ -40, -32, 60, 0,
332 /* 154 */ -40, -32, 62, 0,
333 /* 158 */ -40, -32, 64, 0,
334};
335
336extern const LaneBitmask SystemZLaneMaskLists[] = {
337 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
338 /* 3 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
339 /* 6 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
340 /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
341};
342
343extern const uint16_t SystemZSubRegIdxLists[] = {
344 /* 0 */ 2, 1, 0,
345 /* 3 */ 3, 1, 0,
346 /* 6 */ 2, 1, 4, 5, 0,
347 /* 11 */ 2, 3, 1, 4, 6, 5, 0,
348};
349
350
351#ifdef __GNUC__
352#pragma GCC diagnostic push
353#pragma GCC diagnostic ignored "-Woverlength-strings"
354#endif
355extern const char SystemZRegStrings[] = {
356 /* 0 */ "A10\0"
357 /* 4 */ "C10\0"
358 /* 8 */ "V10\0"
359 /* 12 */ "V20\0"
360 /* 16 */ "V30\0"
361 /* 20 */ "A0\0"
362 /* 23 */ "C0\0"
363 /* 26 */ "V0\0"
364 /* 29 */ "A11\0"
365 /* 33 */ "C11\0"
366 /* 37 */ "V11\0"
367 /* 41 */ "V21\0"
368 /* 45 */ "V31\0"
369 /* 49 */ "A1\0"
370 /* 52 */ "C1\0"
371 /* 55 */ "V1\0"
372 /* 58 */ "A12\0"
373 /* 62 */ "C12\0"
374 /* 66 */ "V12\0"
375 /* 70 */ "V22\0"
376 /* 74 */ "A2\0"
377 /* 77 */ "C2\0"
378 /* 80 */ "V2\0"
379 /* 83 */ "A13\0"
380 /* 87 */ "C13\0"
381 /* 91 */ "V13\0"
382 /* 95 */ "V23\0"
383 /* 99 */ "A3\0"
384 /* 102 */ "C3\0"
385 /* 105 */ "V3\0"
386 /* 108 */ "A14\0"
387 /* 112 */ "C14\0"
388 /* 116 */ "V14\0"
389 /* 120 */ "V24\0"
390 /* 124 */ "A4\0"
391 /* 127 */ "C4\0"
392 /* 130 */ "V4\0"
393 /* 133 */ "A15\0"
394 /* 137 */ "C15\0"
395 /* 141 */ "V15\0"
396 /* 145 */ "V25\0"
397 /* 149 */ "A5\0"
398 /* 152 */ "C5\0"
399 /* 155 */ "V5\0"
400 /* 158 */ "V16\0"
401 /* 162 */ "V26\0"
402 /* 166 */ "A6\0"
403 /* 169 */ "C6\0"
404 /* 172 */ "V6\0"
405 /* 175 */ "V17\0"
406 /* 179 */ "V27\0"
407 /* 183 */ "A7\0"
408 /* 186 */ "C7\0"
409 /* 189 */ "V7\0"
410 /* 192 */ "V18\0"
411 /* 196 */ "V28\0"
412 /* 200 */ "A8\0"
413 /* 203 */ "C8\0"
414 /* 206 */ "V8\0"
415 /* 209 */ "V19\0"
416 /* 213 */ "V29\0"
417 /* 217 */ "A9\0"
418 /* 220 */ "C9\0"
419 /* 223 */ "V9\0"
420 /* 226 */ "CC\0"
421 /* 229 */ "FPC\0"
422 /* 233 */ "F10D\0"
423 /* 238 */ "R10D\0"
424 /* 243 */ "F20D\0"
425 /* 248 */ "F30D\0"
426 /* 253 */ "F0D\0"
427 /* 257 */ "R0D\0"
428 /* 261 */ "F11D\0"
429 /* 266 */ "R11D\0"
430 /* 271 */ "F21D\0"
431 /* 276 */ "F31D\0"
432 /* 281 */ "F1D\0"
433 /* 285 */ "R1D\0"
434 /* 289 */ "F12D\0"
435 /* 294 */ "R12D\0"
436 /* 299 */ "F22D\0"
437 /* 304 */ "F2D\0"
438 /* 308 */ "R2D\0"
439 /* 312 */ "F13D\0"
440 /* 317 */ "R13D\0"
441 /* 322 */ "F23D\0"
442 /* 327 */ "F3D\0"
443 /* 331 */ "R3D\0"
444 /* 335 */ "F14D\0"
445 /* 340 */ "R14D\0"
446 /* 345 */ "F24D\0"
447 /* 350 */ "F4D\0"
448 /* 354 */ "R4D\0"
449 /* 358 */ "F15D\0"
450 /* 363 */ "R15D\0"
451 /* 368 */ "F25D\0"
452 /* 373 */ "F5D\0"
453 /* 377 */ "R5D\0"
454 /* 381 */ "F16D\0"
455 /* 386 */ "F26D\0"
456 /* 391 */ "F6D\0"
457 /* 395 */ "R6D\0"
458 /* 399 */ "F17D\0"
459 /* 404 */ "F27D\0"
460 /* 409 */ "F7D\0"
461 /* 413 */ "R7D\0"
462 /* 417 */ "F18D\0"
463 /* 422 */ "F28D\0"
464 /* 427 */ "F8D\0"
465 /* 431 */ "R8D\0"
466 /* 435 */ "F19D\0"
467 /* 440 */ "F29D\0"
468 /* 445 */ "F9D\0"
469 /* 449 */ "R9D\0"
470 /* 453 */ "R10H\0"
471 /* 458 */ "R0H\0"
472 /* 462 */ "R11H\0"
473 /* 467 */ "R1H\0"
474 /* 471 */ "R12H\0"
475 /* 476 */ "R2H\0"
476 /* 480 */ "R13H\0"
477 /* 485 */ "R3H\0"
478 /* 489 */ "R14H\0"
479 /* 494 */ "R4H\0"
480 /* 498 */ "R15H\0"
481 /* 503 */ "R5H\0"
482 /* 507 */ "R6H\0"
483 /* 511 */ "R7H\0"
484 /* 515 */ "R8H\0"
485 /* 519 */ "R9H\0"
486 /* 523 */ "R10L\0"
487 /* 528 */ "R0L\0"
488 /* 532 */ "R11L\0"
489 /* 537 */ "R1L\0"
490 /* 541 */ "R12L\0"
491 /* 546 */ "R2L\0"
492 /* 550 */ "R13L\0"
493 /* 555 */ "R3L\0"
494 /* 559 */ "R14L\0"
495 /* 564 */ "R4L\0"
496 /* 568 */ "R15L\0"
497 /* 573 */ "R5L\0"
498 /* 577 */ "R6L\0"
499 /* 581 */ "R7L\0"
500 /* 585 */ "R8L\0"
501 /* 589 */ "R9L\0"
502 /* 593 */ "R10Q\0"
503 /* 598 */ "F0Q\0"
504 /* 602 */ "R0Q\0"
505 /* 606 */ "F1Q\0"
506 /* 610 */ "F12Q\0"
507 /* 615 */ "R12Q\0"
508 /* 620 */ "R2Q\0"
509 /* 624 */ "F13Q\0"
510 /* 629 */ "R14Q\0"
511 /* 634 */ "F4Q\0"
512 /* 638 */ "R4Q\0"
513 /* 642 */ "F5Q\0"
514 /* 646 */ "R6Q\0"
515 /* 650 */ "F8Q\0"
516 /* 654 */ "R8Q\0"
517 /* 658 */ "F9Q\0"
518 /* 662 */ "F10S\0"
519 /* 667 */ "F20S\0"
520 /* 672 */ "F30S\0"
521 /* 677 */ "F0S\0"
522 /* 681 */ "F11S\0"
523 /* 686 */ "F21S\0"
524 /* 691 */ "F31S\0"
525 /* 696 */ "F1S\0"
526 /* 700 */ "F12S\0"
527 /* 705 */ "F22S\0"
528 /* 710 */ "F2S\0"
529 /* 714 */ "F13S\0"
530 /* 719 */ "F23S\0"
531 /* 724 */ "F3S\0"
532 /* 728 */ "F14S\0"
533 /* 733 */ "F24S\0"
534 /* 738 */ "F4S\0"
535 /* 742 */ "F15S\0"
536 /* 747 */ "F25S\0"
537 /* 752 */ "F5S\0"
538 /* 756 */ "F16S\0"
539 /* 761 */ "F26S\0"
540 /* 766 */ "F6S\0"
541 /* 770 */ "F17S\0"
542 /* 775 */ "F27S\0"
543 /* 780 */ "F7S\0"
544 /* 784 */ "F18S\0"
545 /* 789 */ "F28S\0"
546 /* 794 */ "F8S\0"
547 /* 798 */ "F19S\0"
548 /* 803 */ "F29S\0"
549 /* 808 */ "F9S\0"
550};
551#ifdef __GNUC__
552#pragma GCC diagnostic pop
553#endif
554
555extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
556 { 3, 0, 0, 0, 0, 0, 0 },
557 { 226, 2, 2, 2, 8192, 11, 0 },
558 { 229, 2, 2, 2, 8193, 11, 0 },
559 { 20, 2, 2, 2, 8194, 11, 0 },
560 { 49, 2, 2, 2, 8195, 11, 0 },
561 { 74, 2, 2, 2, 8196, 11, 0 },
562 { 99, 2, 2, 2, 8197, 11, 0 },
563 { 124, 2, 2, 2, 8198, 11, 0 },
564 { 149, 2, 2, 2, 8199, 11, 0 },
565 { 166, 2, 2, 2, 8200, 11, 0 },
566 { 183, 2, 2, 2, 8201, 11, 0 },
567 { 200, 2, 2, 2, 8202, 11, 0 },
568 { 217, 2, 2, 2, 8203, 11, 0 },
569 { 0, 2, 2, 2, 8204, 11, 0 },
570 { 29, 2, 2, 2, 8205, 11, 0 },
571 { 58, 2, 2, 2, 8206, 11, 0 },
572 { 83, 2, 2, 2, 8207, 11, 0 },
573 { 108, 2, 2, 2, 8208, 11, 0 },
574 { 133, 2, 2, 2, 8209, 11, 0 },
575 { 23, 2, 2, 2, 8210, 11, 0 },
576 { 52, 2, 2, 2, 8211, 11, 0 },
577 { 77, 2, 2, 2, 8212, 11, 0 },
578 { 102, 2, 2, 2, 8213, 11, 0 },
579 { 127, 2, 2, 2, 8214, 11, 0 },
580 { 152, 2, 2, 2, 8215, 11, 0 },
581 { 169, 2, 2, 2, 8216, 11, 0 },
582 { 186, 2, 2, 2, 8217, 11, 0 },
583 { 203, 2, 2, 2, 8218, 11, 0 },
584 { 220, 2, 2, 2, 8219, 11, 0 },
585 { 4, 2, 2, 2, 8220, 11, 0 },
586 { 33, 2, 2, 2, 8221, 11, 0 },
587 { 62, 2, 2, 2, 8222, 11, 0 },
588 { 87, 2, 2, 2, 8223, 11, 0 },
589 { 112, 2, 2, 2, 8224, 11, 0 },
590 { 137, 2, 2, 2, 8225, 11, 0 },
591 { 26, 91, 2, 0, 8226, 1, 0 },
592 { 55, 91, 2, 0, 8227, 1, 0 },
593 { 80, 91, 2, 0, 8228, 1, 0 },
594 { 105, 91, 2, 0, 8229, 1, 0 },
595 { 130, 91, 2, 0, 8230, 1, 0 },
596 { 155, 91, 2, 0, 8231, 1, 0 },
597 { 172, 91, 2, 0, 8232, 1, 0 },
598 { 189, 91, 2, 0, 8233, 1, 0 },
599 { 206, 91, 2, 0, 8234, 1, 0 },
600 { 223, 91, 2, 0, 8235, 1, 0 },
601 { 8, 91, 2, 0, 8236, 1, 0 },
602 { 37, 91, 2, 0, 8237, 1, 0 },
603 { 66, 91, 2, 0, 8238, 1, 0 },
604 { 91, 91, 2, 0, 8239, 1, 0 },
605 { 116, 91, 2, 0, 8240, 1, 0 },
606 { 141, 91, 2, 0, 8241, 1, 0 },
607 { 158, 91, 2, 0, 8242, 1, 0 },
608 { 175, 91, 2, 0, 8243, 1, 0 },
609 { 192, 91, 2, 0, 8244, 1, 0 },
610 { 209, 91, 2, 0, 8245, 1, 0 },
611 { 12, 91, 2, 0, 8246, 1, 0 },
612 { 41, 91, 2, 0, 8247, 1, 0 },
613 { 70, 91, 2, 0, 8248, 1, 0 },
614 { 95, 91, 2, 0, 8249, 1, 0 },
615 { 120, 91, 2, 0, 8250, 1, 0 },
616 { 145, 91, 2, 0, 8251, 1, 0 },
617 { 162, 91, 2, 0, 8252, 1, 0 },
618 { 179, 91, 2, 0, 8253, 1, 0 },
619 { 196, 91, 2, 0, 8254, 1, 0 },
620 { 213, 91, 2, 0, 8255, 1, 0 },
621 { 16, 91, 2, 0, 8256, 1, 0 },
622 { 45, 91, 2, 0, 8257, 1, 0 },
623 { 253, 68, 159, 1, 8226, 1, 0 },
624 { 281, 68, 159, 1, 8227, 1, 0 },
625 { 304, 68, 155, 1, 8228, 1, 0 },
626 { 327, 68, 155, 1, 8229, 1, 0 },
627 { 350, 68, 155, 1, 8230, 1, 0 },
628 { 373, 68, 155, 1, 8231, 1, 0 },
629 { 391, 68, 151, 1, 8232, 1, 0 },
630 { 409, 68, 151, 1, 8233, 1, 0 },
631 { 427, 68, 151, 1, 8234, 1, 0 },
632 { 445, 68, 151, 1, 8235, 1, 0 },
633 { 233, 68, 147, 1, 8236, 1, 0 },
634 { 261, 68, 147, 1, 8237, 1, 0 },
635 { 289, 68, 147, 1, 8238, 1, 0 },
636 { 312, 68, 147, 1, 8239, 1, 0 },
637 { 335, 68, 143, 1, 8240, 1, 0 },
638 { 358, 68, 143, 1, 8241, 1, 0 },
639 { 381, 68, 1, 1, 8242, 1, 0 },
640 { 399, 68, 1, 1, 8243, 1, 0 },
641 { 417, 68, 1, 1, 8244, 1, 0 },
642 { 435, 68, 1, 1, 8245, 1, 0 },
643 { 243, 68, 1, 1, 8246, 1, 0 },
644 { 271, 68, 1, 1, 8247, 1, 0 },
645 { 299, 68, 1, 1, 8248, 1, 0 },
646 { 322, 68, 1, 1, 8249, 1, 0 },
647 { 345, 68, 1, 1, 8250, 1, 0 },
648 { 368, 68, 1, 1, 8251, 1, 0 },
649 { 386, 68, 1, 1, 8252, 1, 0 },
650 { 404, 68, 1, 1, 8253, 1, 0 },
651 { 422, 68, 1, 1, 8254, 1, 0 },
652 { 440, 68, 1, 1, 8255, 1, 0 },
653 { 248, 68, 1, 1, 8256, 1, 0 },
654 { 276, 68, 1, 1, 8257, 1, 0 },
655 { 598, 65, 2, 6, 258082, 3, 0 },
656 { 606, 65, 2, 6, 258083, 3, 0 },
657 { 634, 70, 2, 6, 258086, 3, 0 },
658 { 642, 70, 2, 6, 258087, 3, 0 },
659 { 650, 75, 2, 6, 258090, 3, 0 },
660 { 658, 75, 2, 6, 258091, 3, 0 },
661 { 610, 80, 2, 6, 258094, 3, 0 },
662 { 624, 80, 2, 6, 258095, 3, 0 },
663 { 677, 2, 158, 2, 8226, 11, 0 },
664 { 696, 2, 158, 2, 8227, 11, 0 },
665 { 710, 2, 154, 2, 8228, 11, 0 },
666 { 724, 2, 154, 2, 8229, 11, 0 },
667 { 738, 2, 154, 2, 8230, 11, 0 },
668 { 752, 2, 154, 2, 8231, 11, 0 },
669 { 766, 2, 150, 2, 8232, 11, 0 },
670 { 780, 2, 150, 2, 8233, 11, 0 },
671 { 794, 2, 150, 2, 8234, 11, 0 },
672 { 808, 2, 150, 2, 8235, 11, 0 },
673 { 662, 2, 146, 2, 8236, 11, 0 },
674 { 681, 2, 146, 2, 8237, 11, 0 },
675 { 700, 2, 146, 2, 8238, 11, 0 },
676 { 714, 2, 146, 2, 8239, 11, 0 },
677 { 728, 2, 142, 2, 8240, 11, 0 },
678 { 742, 2, 142, 2, 8241, 11, 0 },
679 { 756, 2, 0, 2, 8242, 11, 0 },
680 { 770, 2, 0, 2, 8243, 11, 0 },
681 { 784, 2, 0, 2, 8244, 11, 0 },
682 { 798, 2, 0, 2, 8245, 11, 0 },
683 { 667, 2, 0, 2, 8246, 11, 0 },
684 { 686, 2, 0, 2, 8247, 11, 0 },
685 { 705, 2, 0, 2, 8248, 11, 0 },
686 { 719, 2, 0, 2, 8249, 11, 0 },
687 { 733, 2, 0, 2, 8250, 11, 0 },
688 { 747, 2, 0, 2, 8251, 11, 0 },
689 { 761, 2, 0, 2, 8252, 11, 0 },
690 { 775, 2, 0, 2, 8253, 11, 0 },
691 { 789, 2, 0, 2, 8254, 11, 0 },
692 { 803, 2, 0, 2, 8255, 11, 0 },
693 { 672, 2, 0, 2, 8256, 11, 0 },
694 { 691, 2, 0, 2, 8257, 11, 0 },
695 { 257, 7, 137, 3, 249922, 0, 0 },
696 { 285, 7, 131, 3, 249924, 0, 0 },
697 { 308, 7, 131, 3, 249926, 0, 0 },
698 { 331, 7, 125, 3, 249928, 0, 0 },
699 { 354, 7, 125, 3, 249930, 0, 0 },
700 { 377, 7, 119, 3, 249932, 0, 0 },
701 { 395, 7, 119, 3, 249934, 0, 0 },
702 { 413, 7, 113, 3, 249936, 0, 0 },
703 { 431, 7, 113, 3, 249938, 0, 0 },
704 { 449, 7, 107, 3, 249940, 0, 0 },
705 { 238, 7, 107, 3, 249942, 0, 0 },
706 { 266, 7, 101, 3, 249944, 0, 0 },
707 { 294, 7, 101, 3, 249946, 0, 0 },
708 { 317, 7, 95, 3, 249948, 0, 0 },
709 { 340, 7, 95, 3, 249950, 0, 0 },
710 { 363, 7, 68, 3, 249952, 0, 0 },
711 { 458, 2, 139, 2, 8259, 11, 0 },
712 { 467, 2, 133, 2, 8261, 11, 0 },
713 { 476, 2, 133, 2, 8263, 11, 0 },
714 { 485, 2, 127, 2, 8265, 11, 0 },
715 { 494, 2, 127, 2, 8267, 11, 0 },
716 { 503, 2, 121, 2, 8269, 11, 0 },
717 { 507, 2, 121, 2, 8271, 11, 0 },
718 { 511, 2, 115, 2, 8273, 11, 0 },
719 { 515, 2, 115, 2, 8275, 11, 0 },
720 { 519, 2, 109, 2, 8277, 11, 0 },
721 { 453, 2, 109, 2, 8279, 11, 0 },
722 { 462, 2, 103, 2, 8281, 11, 0 },
723 { 471, 2, 103, 2, 8283, 11, 0 },
724 { 480, 2, 97, 2, 8285, 11, 0 },
725 { 489, 2, 97, 2, 8287, 11, 0 },
726 { 498, 2, 88, 2, 8289, 11, 0 },
727 { 528, 2, 136, 2, 8258, 11, 0 },
728 { 537, 2, 130, 2, 8260, 11, 0 },
729 { 546, 2, 130, 2, 8262, 11, 0 },
730 { 555, 2, 124, 2, 8264, 11, 0 },
731 { 564, 2, 124, 2, 8266, 11, 0 },
732 { 573, 2, 118, 2, 8268, 11, 0 },
733 { 577, 2, 118, 2, 8270, 11, 0 },
734 { 581, 2, 112, 2, 8272, 11, 0 },
735 { 585, 2, 112, 2, 8274, 11, 0 },
736 { 589, 2, 106, 2, 8276, 11, 0 },
737 { 523, 2, 106, 2, 8278, 11, 0 },
738 { 532, 2, 100, 2, 8280, 11, 0 },
739 { 541, 2, 100, 2, 8282, 11, 0 },
740 { 550, 2, 94, 2, 8284, 11, 0 },
741 { 559, 2, 94, 2, 8286, 11, 0 },
742 { 568, 2, 85, 2, 8288, 11, 0 },
743 { 602, 3, 2, 11, 241730, 6, 0 },
744 { 620, 10, 2, 11, 241734, 6, 0 },
745 { 638, 17, 2, 11, 241738, 6, 0 },
746 { 646, 24, 2, 11, 241742, 6, 0 },
747 { 654, 31, 2, 11, 241746, 6, 0 },
748 { 593, 38, 2, 11, 241750, 6, 0 },
749 { 615, 45, 2, 11, 241754, 6, 0 },
750 { 629, 52, 2, 11, 241758, 6, 0 },
751};
752
753extern const MCPhysReg SystemZRegUnitRoots[][2] = {
754 { SystemZ::CC },
755 { SystemZ::FPC },
756 { SystemZ::A0 },
757 { SystemZ::A1 },
758 { SystemZ::A2 },
759 { SystemZ::A3 },
760 { SystemZ::A4 },
761 { SystemZ::A5 },
762 { SystemZ::A6 },
763 { SystemZ::A7 },
764 { SystemZ::A8 },
765 { SystemZ::A9 },
766 { SystemZ::A10 },
767 { SystemZ::A11 },
768 { SystemZ::A12 },
769 { SystemZ::A13 },
770 { SystemZ::A14 },
771 { SystemZ::A15 },
772 { SystemZ::C0 },
773 { SystemZ::C1 },
774 { SystemZ::C2 },
775 { SystemZ::C3 },
776 { SystemZ::C4 },
777 { SystemZ::C5 },
778 { SystemZ::C6 },
779 { SystemZ::C7 },
780 { SystemZ::C8 },
781 { SystemZ::C9 },
782 { SystemZ::C10 },
783 { SystemZ::C11 },
784 { SystemZ::C12 },
785 { SystemZ::C13 },
786 { SystemZ::C14 },
787 { SystemZ::C15 },
788 { SystemZ::F0S },
789 { SystemZ::F1S },
790 { SystemZ::F2S },
791 { SystemZ::F3S },
792 { SystemZ::F4S },
793 { SystemZ::F5S },
794 { SystemZ::F6S },
795 { SystemZ::F7S },
796 { SystemZ::F8S },
797 { SystemZ::F9S },
798 { SystemZ::F10S },
799 { SystemZ::F11S },
800 { SystemZ::F12S },
801 { SystemZ::F13S },
802 { SystemZ::F14S },
803 { SystemZ::F15S },
804 { SystemZ::F16S },
805 { SystemZ::F17S },
806 { SystemZ::F18S },
807 { SystemZ::F19S },
808 { SystemZ::F20S },
809 { SystemZ::F21S },
810 { SystemZ::F22S },
811 { SystemZ::F23S },
812 { SystemZ::F24S },
813 { SystemZ::F25S },
814 { SystemZ::F26S },
815 { SystemZ::F27S },
816 { SystemZ::F28S },
817 { SystemZ::F29S },
818 { SystemZ::F30S },
819 { SystemZ::F31S },
820 { SystemZ::R0L },
821 { SystemZ::R0H },
822 { SystemZ::R1L },
823 { SystemZ::R1H },
824 { SystemZ::R2L },
825 { SystemZ::R2H },
826 { SystemZ::R3L },
827 { SystemZ::R3H },
828 { SystemZ::R4L },
829 { SystemZ::R4H },
830 { SystemZ::R5L },
831 { SystemZ::R5H },
832 { SystemZ::R6L },
833 { SystemZ::R6H },
834 { SystemZ::R7L },
835 { SystemZ::R7H },
836 { SystemZ::R8L },
837 { SystemZ::R8H },
838 { SystemZ::R9L },
839 { SystemZ::R9H },
840 { SystemZ::R10L },
841 { SystemZ::R10H },
842 { SystemZ::R11L },
843 { SystemZ::R11H },
844 { SystemZ::R12L },
845 { SystemZ::R12H },
846 { SystemZ::R13L },
847 { SystemZ::R13H },
848 { SystemZ::R14L },
849 { SystemZ::R14H },
850 { SystemZ::R15L },
851 { SystemZ::R15H },
852};
853
854namespace { // Register classes...
855 // GRX32Bit Register Class...
856 const MCPhysReg GRX32Bit[] = {
857 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H,
858 };
859
860 // GRX32Bit Bit set.
861 const uint8_t GRX32BitBits[] = {
862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
863 };
864
865 // VR32Bit Register Class...
866 const MCPhysReg VR32Bit[] = {
867 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
868 };
869
870 // VR32Bit Bit set.
871 const uint8_t VR32BitBits[] = {
872 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
873 };
874
875 // AR32Bit Register Class...
876 const MCPhysReg AR32Bit[] = {
877 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15,
878 };
879
880 // AR32Bit Bit set.
881 const uint8_t AR32BitBits[] = {
882 0xf8, 0xff, 0x07,
883 };
884
885 // FP32Bit Register Class...
886 const MCPhysReg FP32Bit[] = {
887 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
888 };
889
890 // FP32Bit Bit set.
891 const uint8_t FP32BitBits[] = {
892 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
893 };
894
895 // GR32Bit Register Class...
896 const MCPhysReg GR32Bit[] = {
897 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
898 };
899
900 // GR32Bit Bit set.
901 const uint8_t GR32BitBits[] = {
902 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
903 };
904
905 // GRH32Bit Register Class...
906 const MCPhysReg GRH32Bit[] = {
907 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H,
908 };
909
910 // GRH32Bit Bit set.
911 const uint8_t GRH32BitBits[] = {
912 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
913 };
914
915 // ADDR32Bit Register Class...
916 const MCPhysReg ADDR32Bit[] = {
917 SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
918 };
919
920 // ADDR32Bit Bit set.
921 const uint8_t ADDR32BitBits[] = {
922 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
923 };
924
925 // CCR Register Class...
926 const MCPhysReg CCR[] = {
927 SystemZ::CC,
928 };
929
930 // CCR Bit set.
931 const uint8_t CCRBits[] = {
932 0x02,
933 };
934
935 // FPCRegs Register Class...
936 const MCPhysReg FPCRegs[] = {
937 SystemZ::FPC,
938 };
939
940 // FPCRegs Bit set.
941 const uint8_t FPCRegsBits[] = {
942 0x04,
943 };
944
945 // AnyRegBit Register Class...
946 const MCPhysReg AnyRegBit[] = {
947 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
948 };
949
950 // AnyRegBit Bit set.
951 const uint8_t AnyRegBitBits[] = {
952 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
953 };
954
955 // AnyRegBit_with_subreg_h32_in_FP32Bit Register Class...
956 const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = {
957 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
958 };
959
960 // AnyRegBit_with_subreg_h32_in_FP32Bit Bit set.
961 const uint8_t AnyRegBit_with_subreg_h32_in_FP32BitBits[] = {
962 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07,
963 };
964
965 // VR64Bit Register Class...
966 const MCPhysReg VR64Bit[] = {
967 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
968 };
969
970 // VR64Bit Bit set.
971 const uint8_t VR64BitBits[] = {
972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
973 };
974
975 // AnyRegBit_with_subreg_h64 Register Class...
976 const MCPhysReg AnyRegBit_with_subreg_h64[] = {
977 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
978 };
979
980 // AnyRegBit_with_subreg_h64 Bit set.
981 const uint8_t AnyRegBit_with_subreg_h64Bits[] = {
982 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
983 };
984
985 // CR64Bit Register Class...
986 const MCPhysReg CR64Bit[] = {
987 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15,
988 };
989
990 // CR64Bit Bit set.
991 const uint8_t CR64BitBits[] = {
992 0x00, 0x00, 0xf8, 0xff, 0x07,
993 };
994
995 // FP64Bit Register Class...
996 const MCPhysReg FP64Bit[] = {
997 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
998 };
999
1000 // FP64Bit Bit set.
1001 const uint8_t FP64BitBits[] = {
1002 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1003 };
1004
1005 // GR64Bit Register Class...
1006 const MCPhysReg GR64Bit[] = {
1007 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
1008 };
1009
1010 // GR64Bit Bit set.
1011 const uint8_t GR64BitBits[] = {
1012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1013 };
1014
1015 // ADDR64Bit Register Class...
1016 const MCPhysReg ADDR64Bit[] = {
1017 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
1018 };
1019
1020 // ADDR64Bit Bit set.
1021 const uint8_t ADDR64BitBits[] = {
1022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1023 };
1024
1025 // VR128Bit Register Class...
1026 const MCPhysReg VR128Bit[] = {
1027 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1028 };
1029
1030 // VR128Bit Bit set.
1031 const uint8_t VR128BitBits[] = {
1032 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1033 };
1034
1035 // VF128Bit Register Class...
1036 const MCPhysReg VF128Bit[] = {
1037 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1038 };
1039
1040 // VF128Bit Bit set.
1041 const uint8_t VF128BitBits[] = {
1042 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1043 };
1044
1045 // FP128Bit Register Class...
1046 const MCPhysReg FP128Bit[] = {
1047 SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q,
1048 };
1049
1050 // FP128Bit Bit set.
1051 const uint8_t FP128BitBits[] = {
1052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1053 };
1054
1055 // GR128Bit Register Class...
1056 const MCPhysReg GR128Bit[] = {
1057 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
1058 };
1059
1060 // GR128Bit Bit set.
1061 const uint8_t GR128BitBits[] = {
1062 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1063 };
1064
1065 // ADDR128Bit Register Class...
1066 const MCPhysReg ADDR128Bit[] = {
1067 SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
1068 };
1069
1070 // ADDR128Bit Bit set.
1071 const uint8_t ADDR128BitBits[] = {
1072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1073 };
1074
1075} // end anonymous namespace
1076
1077
1078#ifdef __GNUC__
1079#pragma GCC diagnostic push
1080#pragma GCC diagnostic ignored "-Woverlength-strings"
1081#endif
1082extern const char SystemZRegClassStrings[] = {
1083 /* 0 */ "AnyRegBit_with_subreg_h64\0"
1084 /* 26 */ "CCR\0"
1085 /* 30 */ "FPCRegs\0"
1086 /* 38 */ "GRH32Bit\0"
1087 /* 47 */ "AnyRegBit_with_subreg_h32_in_FP32Bit\0"
1088 /* 84 */ "AR32Bit\0"
1089 /* 92 */ "ADDR32Bit\0"
1090 /* 102 */ "GR32Bit\0"
1091 /* 110 */ "VR32Bit\0"
1092 /* 118 */ "GRX32Bit\0"
1093 /* 127 */ "FP64Bit\0"
1094 /* 135 */ "CR64Bit\0"
1095 /* 143 */ "ADDR64Bit\0"
1096 /* 153 */ "GR64Bit\0"
1097 /* 161 */ "VR64Bit\0"
1098 /* 169 */ "VF128Bit\0"
1099 /* 178 */ "FP128Bit\0"
1100 /* 187 */ "ADDR128Bit\0"
1101 /* 198 */ "GR128Bit\0"
1102 /* 207 */ "VR128Bit\0"
1103 /* 216 */ "AnyRegBit\0"
1104};
1105#ifdef __GNUC__
1106#pragma GCC diagnostic pop
1107#endif
1108
1109extern const MCRegisterClass SystemZMCRegisterClasses[] = {
1110 { GRX32Bit, GRX32BitBits, 118, 32, sizeof(GRX32BitBits), SystemZ::GRX32BitRegClassID, 32, 1, true, false },
1111 { VR32Bit, VR32BitBits, 110, 32, sizeof(VR32BitBits), SystemZ::VR32BitRegClassID, 32, 1, true, false },
1112 { AR32Bit, AR32BitBits, 84, 16, sizeof(AR32BitBits), SystemZ::AR32BitRegClassID, 32, 1, false, false },
1113 { FP32Bit, FP32BitBits, 76, 16, sizeof(FP32BitBits), SystemZ::FP32BitRegClassID, 32, 1, true, false },
1114 { GR32Bit, GR32BitBits, 102, 16, sizeof(GR32BitBits), SystemZ::GR32BitRegClassID, 32, 1, true, false },
1115 { GRH32Bit, GRH32BitBits, 38, 16, sizeof(GRH32BitBits), SystemZ::GRH32BitRegClassID, 32, 1, true, false },
1116 { ADDR32Bit, ADDR32BitBits, 92, 15, sizeof(ADDR32BitBits), SystemZ::ADDR32BitRegClassID, 32, 1, true, false },
1117 { CCR, CCRBits, 26, 1, sizeof(CCRBits), SystemZ::CCRRegClassID, 32, -1, false, false },
1118 { FPCRegs, FPCRegsBits, 30, 1, sizeof(FPCRegsBits), SystemZ::FPCRegsRegClassID, 32, 1, false, false },
1119 { AnyRegBit, AnyRegBitBits, 216, 48, sizeof(AnyRegBitBits), SystemZ::AnyRegBitRegClassID, 64, 1, false, false },
1120 { AnyRegBit_with_subreg_h32_in_FP32Bit, AnyRegBit_with_subreg_h32_in_FP32BitBits, 47, 32, sizeof(AnyRegBit_with_subreg_h32_in_FP32BitBits), SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClassID, 64, 1, false, false },
1121 { VR64Bit, VR64BitBits, 161, 32, sizeof(VR64BitBits), SystemZ::VR64BitRegClassID, 64, 1, true, false },
1122 { AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, 0, 16, sizeof(AnyRegBit_with_subreg_h64Bits), SystemZ::AnyRegBit_with_subreg_h64RegClassID, 64, 1, false, false },
1123 { CR64Bit, CR64BitBits, 135, 16, sizeof(CR64BitBits), SystemZ::CR64BitRegClassID, 64, 1, false, false },
1124 { FP64Bit, FP64BitBits, 127, 16, sizeof(FP64BitBits), SystemZ::FP64BitRegClassID, 64, 1, true, false },
1125 { GR64Bit, GR64BitBits, 153, 16, sizeof(GR64BitBits), SystemZ::GR64BitRegClassID, 64, 1, true, false },
1126 { ADDR64Bit, ADDR64BitBits, 143, 15, sizeof(ADDR64BitBits), SystemZ::ADDR64BitRegClassID, 64, 1, true, false },
1127 { VR128Bit, VR128BitBits, 207, 32, sizeof(VR128BitBits), SystemZ::VR128BitRegClassID, 128, 1, true, false },
1128 { VF128Bit, VF128BitBits, 169, 16, sizeof(VF128BitBits), SystemZ::VF128BitRegClassID, 128, 1, true, false },
1129 { FP128Bit, FP128BitBits, 178, 8, sizeof(FP128BitBits), SystemZ::FP128BitRegClassID, 128, 1, true, false },
1130 { GR128Bit, GR128BitBits, 198, 8, sizeof(GR128BitBits), SystemZ::GR128BitRegClassID, 128, 1, true, false },
1131 { ADDR128Bit, ADDR128BitBits, 187, 7, sizeof(ADDR128BitBits), SystemZ::ADDR128BitRegClassID, 128, 1, true, false },
1132};
1133
1134// SystemZ Dwarf<->LLVM register mappings.
1135extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
1136 { 0U, SystemZ::R0D },
1137 { 1U, SystemZ::R1D },
1138 { 2U, SystemZ::R2D },
1139 { 3U, SystemZ::R3D },
1140 { 4U, SystemZ::R4D },
1141 { 5U, SystemZ::R5D },
1142 { 6U, SystemZ::R6D },
1143 { 7U, SystemZ::R7D },
1144 { 8U, SystemZ::R8D },
1145 { 9U, SystemZ::R9D },
1146 { 10U, SystemZ::R10D },
1147 { 11U, SystemZ::R11D },
1148 { 12U, SystemZ::R12D },
1149 { 13U, SystemZ::R13D },
1150 { 14U, SystemZ::R14D },
1151 { 15U, SystemZ::R15D },
1152 { 16U, SystemZ::F0D },
1153 { 17U, SystemZ::F2D },
1154 { 18U, SystemZ::F4D },
1155 { 19U, SystemZ::F6D },
1156 { 20U, SystemZ::F1D },
1157 { 21U, SystemZ::F3D },
1158 { 22U, SystemZ::F5D },
1159 { 23U, SystemZ::F7D },
1160 { 24U, SystemZ::F8D },
1161 { 25U, SystemZ::F10D },
1162 { 26U, SystemZ::F12D },
1163 { 27U, SystemZ::F14D },
1164 { 28U, SystemZ::F9D },
1165 { 29U, SystemZ::F11D },
1166 { 30U, SystemZ::F13D },
1167 { 31U, SystemZ::F15D },
1168 { 32U, SystemZ::C0 },
1169 { 33U, SystemZ::C1 },
1170 { 34U, SystemZ::C2 },
1171 { 35U, SystemZ::C3 },
1172 { 36U, SystemZ::C4 },
1173 { 37U, SystemZ::C5 },
1174 { 38U, SystemZ::C6 },
1175 { 39U, SystemZ::C7 },
1176 { 40U, SystemZ::C8 },
1177 { 41U, SystemZ::C9 },
1178 { 42U, SystemZ::C10 },
1179 { 43U, SystemZ::C11 },
1180 { 44U, SystemZ::C12 },
1181 { 45U, SystemZ::C13 },
1182 { 46U, SystemZ::C14 },
1183 { 47U, SystemZ::C15 },
1184 { 48U, SystemZ::A0 },
1185 { 49U, SystemZ::A1 },
1186 { 50U, SystemZ::A2 },
1187 { 51U, SystemZ::A3 },
1188 { 52U, SystemZ::A4 },
1189 { 53U, SystemZ::A5 },
1190 { 54U, SystemZ::A6 },
1191 { 55U, SystemZ::A7 },
1192 { 56U, SystemZ::A8 },
1193 { 57U, SystemZ::A9 },
1194 { 58U, SystemZ::A10 },
1195 { 59U, SystemZ::A11 },
1196 { 60U, SystemZ::A12 },
1197 { 61U, SystemZ::A13 },
1198 { 62U, SystemZ::A14 },
1199 { 63U, SystemZ::A15 },
1200 { 68U, SystemZ::F16D },
1201 { 69U, SystemZ::F18D },
1202 { 70U, SystemZ::F20D },
1203 { 71U, SystemZ::F22D },
1204 { 72U, SystemZ::F17D },
1205 { 73U, SystemZ::F19D },
1206 { 74U, SystemZ::F21D },
1207 { 75U, SystemZ::F23D },
1208 { 76U, SystemZ::F24D },
1209 { 77U, SystemZ::F26D },
1210 { 78U, SystemZ::F28D },
1211 { 79U, SystemZ::F30D },
1212 { 80U, SystemZ::F25D },
1213 { 81U, SystemZ::F27D },
1214 { 82U, SystemZ::F29D },
1215 { 83U, SystemZ::F31D },
1216};
1217extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = std::size(SystemZDwarfFlavour0Dwarf2L);
1218
1219extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1220 { 0U, SystemZ::R0D },
1221 { 1U, SystemZ::R1D },
1222 { 2U, SystemZ::R2D },
1223 { 3U, SystemZ::R3D },
1224 { 4U, SystemZ::R4D },
1225 { 5U, SystemZ::R5D },
1226 { 6U, SystemZ::R6D },
1227 { 7U, SystemZ::R7D },
1228 { 8U, SystemZ::R8D },
1229 { 9U, SystemZ::R9D },
1230 { 10U, SystemZ::R10D },
1231 { 11U, SystemZ::R11D },
1232 { 12U, SystemZ::R12D },
1233 { 13U, SystemZ::R13D },
1234 { 14U, SystemZ::R14D },
1235 { 15U, SystemZ::R15D },
1236 { 16U, SystemZ::F0D },
1237 { 17U, SystemZ::F2D },
1238 { 18U, SystemZ::F4D },
1239 { 19U, SystemZ::F6D },
1240 { 20U, SystemZ::F1D },
1241 { 21U, SystemZ::F3D },
1242 { 22U, SystemZ::F5D },
1243 { 23U, SystemZ::F7D },
1244 { 24U, SystemZ::F8D },
1245 { 25U, SystemZ::F10D },
1246 { 26U, SystemZ::F12D },
1247 { 27U, SystemZ::F14D },
1248 { 28U, SystemZ::F9D },
1249 { 29U, SystemZ::F11D },
1250 { 30U, SystemZ::F13D },
1251 { 31U, SystemZ::F15D },
1252 { 32U, SystemZ::C0 },
1253 { 33U, SystemZ::C1 },
1254 { 34U, SystemZ::C2 },
1255 { 35U, SystemZ::C3 },
1256 { 36U, SystemZ::C4 },
1257 { 37U, SystemZ::C5 },
1258 { 38U, SystemZ::C6 },
1259 { 39U, SystemZ::C7 },
1260 { 40U, SystemZ::C8 },
1261 { 41U, SystemZ::C9 },
1262 { 42U, SystemZ::C10 },
1263 { 43U, SystemZ::C11 },
1264 { 44U, SystemZ::C12 },
1265 { 45U, SystemZ::C13 },
1266 { 46U, SystemZ::C14 },
1267 { 47U, SystemZ::C15 },
1268 { 48U, SystemZ::A0 },
1269 { 49U, SystemZ::A1 },
1270 { 50U, SystemZ::A2 },
1271 { 51U, SystemZ::A3 },
1272 { 52U, SystemZ::A4 },
1273 { 53U, SystemZ::A5 },
1274 { 54U, SystemZ::A6 },
1275 { 55U, SystemZ::A7 },
1276 { 56U, SystemZ::A8 },
1277 { 57U, SystemZ::A9 },
1278 { 58U, SystemZ::A10 },
1279 { 59U, SystemZ::A11 },
1280 { 60U, SystemZ::A12 },
1281 { 61U, SystemZ::A13 },
1282 { 62U, SystemZ::A14 },
1283 { 63U, SystemZ::A15 },
1284 { 68U, SystemZ::F16D },
1285 { 69U, SystemZ::F18D },
1286 { 70U, SystemZ::F20D },
1287 { 71U, SystemZ::F22D },
1288 { 72U, SystemZ::F17D },
1289 { 73U, SystemZ::F19D },
1290 { 74U, SystemZ::F21D },
1291 { 75U, SystemZ::F23D },
1292 { 76U, SystemZ::F24D },
1293 { 77U, SystemZ::F26D },
1294 { 78U, SystemZ::F28D },
1295 { 79U, SystemZ::F30D },
1296 { 80U, SystemZ::F25D },
1297 { 81U, SystemZ::F27D },
1298 { 82U, SystemZ::F29D },
1299 { 83U, SystemZ::F31D },
1300};
1301extern const unsigned SystemZEHFlavour0Dwarf2LSize = std::size(SystemZEHFlavour0Dwarf2L);
1302
1303extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1304 { SystemZ::A0, 48U },
1305 { SystemZ::A1, 49U },
1306 { SystemZ::A2, 50U },
1307 { SystemZ::A3, 51U },
1308 { SystemZ::A4, 52U },
1309 { SystemZ::A5, 53U },
1310 { SystemZ::A6, 54U },
1311 { SystemZ::A7, 55U },
1312 { SystemZ::A8, 56U },
1313 { SystemZ::A9, 57U },
1314 { SystemZ::A10, 58U },
1315 { SystemZ::A11, 59U },
1316 { SystemZ::A12, 60U },
1317 { SystemZ::A13, 61U },
1318 { SystemZ::A14, 62U },
1319 { SystemZ::A15, 63U },
1320 { SystemZ::C0, 32U },
1321 { SystemZ::C1, 33U },
1322 { SystemZ::C2, 34U },
1323 { SystemZ::C3, 35U },
1324 { SystemZ::C4, 36U },
1325 { SystemZ::C5, 37U },
1326 { SystemZ::C6, 38U },
1327 { SystemZ::C7, 39U },
1328 { SystemZ::C8, 40U },
1329 { SystemZ::C9, 41U },
1330 { SystemZ::C10, 42U },
1331 { SystemZ::C11, 43U },
1332 { SystemZ::C12, 44U },
1333 { SystemZ::C13, 45U },
1334 { SystemZ::C14, 46U },
1335 { SystemZ::C15, 47U },
1336 { SystemZ::V0, 16U },
1337 { SystemZ::V1, 20U },
1338 { SystemZ::V2, 17U },
1339 { SystemZ::V3, 21U },
1340 { SystemZ::V4, 18U },
1341 { SystemZ::V5, 22U },
1342 { SystemZ::V6, 19U },
1343 { SystemZ::V7, 23U },
1344 { SystemZ::V8, 24U },
1345 { SystemZ::V9, 28U },
1346 { SystemZ::V10, 25U },
1347 { SystemZ::V11, 29U },
1348 { SystemZ::V12, 26U },
1349 { SystemZ::V13, 30U },
1350 { SystemZ::V14, 27U },
1351 { SystemZ::V15, 31U },
1352 { SystemZ::V16, 68U },
1353 { SystemZ::V17, 72U },
1354 { SystemZ::V18, 69U },
1355 { SystemZ::V19, 73U },
1356 { SystemZ::V20, 70U },
1357 { SystemZ::V21, 74U },
1358 { SystemZ::V22, 71U },
1359 { SystemZ::V23, 75U },
1360 { SystemZ::V24, 76U },
1361 { SystemZ::V25, 80U },
1362 { SystemZ::V26, 77U },
1363 { SystemZ::V27, 81U },
1364 { SystemZ::V28, 78U },
1365 { SystemZ::V29, 82U },
1366 { SystemZ::V30, 79U },
1367 { SystemZ::V31, 83U },
1368 { SystemZ::F0D, 16U },
1369 { SystemZ::F1D, 20U },
1370 { SystemZ::F2D, 17U },
1371 { SystemZ::F3D, 21U },
1372 { SystemZ::F4D, 18U },
1373 { SystemZ::F5D, 22U },
1374 { SystemZ::F6D, 19U },
1375 { SystemZ::F7D, 23U },
1376 { SystemZ::F8D, 24U },
1377 { SystemZ::F9D, 28U },
1378 { SystemZ::F10D, 25U },
1379 { SystemZ::F11D, 29U },
1380 { SystemZ::F12D, 26U },
1381 { SystemZ::F13D, 30U },
1382 { SystemZ::F14D, 27U },
1383 { SystemZ::F15D, 31U },
1384 { SystemZ::F16D, 68U },
1385 { SystemZ::F17D, 72U },
1386 { SystemZ::F18D, 69U },
1387 { SystemZ::F19D, 73U },
1388 { SystemZ::F20D, 70U },
1389 { SystemZ::F21D, 74U },
1390 { SystemZ::F22D, 71U },
1391 { SystemZ::F23D, 75U },
1392 { SystemZ::F24D, 76U },
1393 { SystemZ::F25D, 80U },
1394 { SystemZ::F26D, 77U },
1395 { SystemZ::F27D, 81U },
1396 { SystemZ::F28D, 78U },
1397 { SystemZ::F29D, 82U },
1398 { SystemZ::F30D, 79U },
1399 { SystemZ::F31D, 83U },
1400 { SystemZ::R0D, 0U },
1401 { SystemZ::R1D, 1U },
1402 { SystemZ::R2D, 2U },
1403 { SystemZ::R3D, 3U },
1404 { SystemZ::R4D, 4U },
1405 { SystemZ::R5D, 5U },
1406 { SystemZ::R6D, 6U },
1407 { SystemZ::R7D, 7U },
1408 { SystemZ::R8D, 8U },
1409 { SystemZ::R9D, 9U },
1410 { SystemZ::R10D, 10U },
1411 { SystemZ::R11D, 11U },
1412 { SystemZ::R12D, 12U },
1413 { SystemZ::R13D, 13U },
1414 { SystemZ::R14D, 14U },
1415 { SystemZ::R15D, 15U },
1416};
1417extern const unsigned SystemZDwarfFlavour0L2DwarfSize = std::size(SystemZDwarfFlavour0L2Dwarf);
1418
1419extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1420 { SystemZ::A0, 48U },
1421 { SystemZ::A1, 49U },
1422 { SystemZ::A2, 50U },
1423 { SystemZ::A3, 51U },
1424 { SystemZ::A4, 52U },
1425 { SystemZ::A5, 53U },
1426 { SystemZ::A6, 54U },
1427 { SystemZ::A7, 55U },
1428 { SystemZ::A8, 56U },
1429 { SystemZ::A9, 57U },
1430 { SystemZ::A10, 58U },
1431 { SystemZ::A11, 59U },
1432 { SystemZ::A12, 60U },
1433 { SystemZ::A13, 61U },
1434 { SystemZ::A14, 62U },
1435 { SystemZ::A15, 63U },
1436 { SystemZ::C0, 32U },
1437 { SystemZ::C1, 33U },
1438 { SystemZ::C2, 34U },
1439 { SystemZ::C3, 35U },
1440 { SystemZ::C4, 36U },
1441 { SystemZ::C5, 37U },
1442 { SystemZ::C6, 38U },
1443 { SystemZ::C7, 39U },
1444 { SystemZ::C8, 40U },
1445 { SystemZ::C9, 41U },
1446 { SystemZ::C10, 42U },
1447 { SystemZ::C11, 43U },
1448 { SystemZ::C12, 44U },
1449 { SystemZ::C13, 45U },
1450 { SystemZ::C14, 46U },
1451 { SystemZ::C15, 47U },
1452 { SystemZ::V0, 16U },
1453 { SystemZ::V1, 20U },
1454 { SystemZ::V2, 17U },
1455 { SystemZ::V3, 21U },
1456 { SystemZ::V4, 18U },
1457 { SystemZ::V5, 22U },
1458 { SystemZ::V6, 19U },
1459 { SystemZ::V7, 23U },
1460 { SystemZ::V8, 24U },
1461 { SystemZ::V9, 28U },
1462 { SystemZ::V10, 25U },
1463 { SystemZ::V11, 29U },
1464 { SystemZ::V12, 26U },
1465 { SystemZ::V13, 30U },
1466 { SystemZ::V14, 27U },
1467 { SystemZ::V15, 31U },
1468 { SystemZ::V16, 68U },
1469 { SystemZ::V17, 72U },
1470 { SystemZ::V18, 69U },
1471 { SystemZ::V19, 73U },
1472 { SystemZ::V20, 70U },
1473 { SystemZ::V21, 74U },
1474 { SystemZ::V22, 71U },
1475 { SystemZ::V23, 75U },
1476 { SystemZ::V24, 76U },
1477 { SystemZ::V25, 80U },
1478 { SystemZ::V26, 77U },
1479 { SystemZ::V27, 81U },
1480 { SystemZ::V28, 78U },
1481 { SystemZ::V29, 82U },
1482 { SystemZ::V30, 79U },
1483 { SystemZ::V31, 83U },
1484 { SystemZ::F0D, 16U },
1485 { SystemZ::F1D, 20U },
1486 { SystemZ::F2D, 17U },
1487 { SystemZ::F3D, 21U },
1488 { SystemZ::F4D, 18U },
1489 { SystemZ::F5D, 22U },
1490 { SystemZ::F6D, 19U },
1491 { SystemZ::F7D, 23U },
1492 { SystemZ::F8D, 24U },
1493 { SystemZ::F9D, 28U },
1494 { SystemZ::F10D, 25U },
1495 { SystemZ::F11D, 29U },
1496 { SystemZ::F12D, 26U },
1497 { SystemZ::F13D, 30U },
1498 { SystemZ::F14D, 27U },
1499 { SystemZ::F15D, 31U },
1500 { SystemZ::F16D, 68U },
1501 { SystemZ::F17D, 72U },
1502 { SystemZ::F18D, 69U },
1503 { SystemZ::F19D, 73U },
1504 { SystemZ::F20D, 70U },
1505 { SystemZ::F21D, 74U },
1506 { SystemZ::F22D, 71U },
1507 { SystemZ::F23D, 75U },
1508 { SystemZ::F24D, 76U },
1509 { SystemZ::F25D, 80U },
1510 { SystemZ::F26D, 77U },
1511 { SystemZ::F27D, 81U },
1512 { SystemZ::F28D, 78U },
1513 { SystemZ::F29D, 82U },
1514 { SystemZ::F30D, 79U },
1515 { SystemZ::F31D, 83U },
1516 { SystemZ::R0D, 0U },
1517 { SystemZ::R1D, 1U },
1518 { SystemZ::R2D, 2U },
1519 { SystemZ::R3D, 3U },
1520 { SystemZ::R4D, 4U },
1521 { SystemZ::R5D, 5U },
1522 { SystemZ::R6D, 6U },
1523 { SystemZ::R7D, 7U },
1524 { SystemZ::R8D, 8U },
1525 { SystemZ::R9D, 9U },
1526 { SystemZ::R10D, 10U },
1527 { SystemZ::R11D, 11U },
1528 { SystemZ::R12D, 12U },
1529 { SystemZ::R13D, 13U },
1530 { SystemZ::R14D, 14U },
1531 { SystemZ::R15D, 15U },
1532};
1533extern const unsigned SystemZEHFlavour0L2DwarfSize = std::size(SystemZEHFlavour0L2Dwarf);
1534
1535extern const uint16_t SystemZRegEncodingTable[] = {
1536 0,
1537 0,
1538 0,
1539 0,
1540 1,
1541 2,
1542 3,
1543 4,
1544 5,
1545 6,
1546 7,
1547 8,
1548 9,
1549 10,
1550 11,
1551 12,
1552 13,
1553 14,
1554 15,
1555 0,
1556 1,
1557 2,
1558 3,
1559 4,
1560 5,
1561 6,
1562 7,
1563 8,
1564 9,
1565 10,
1566 11,
1567 12,
1568 13,
1569 14,
1570 15,
1571 0,
1572 1,
1573 2,
1574 3,
1575 4,
1576 5,
1577 6,
1578 7,
1579 8,
1580 9,
1581 10,
1582 11,
1583 12,
1584 13,
1585 14,
1586 15,
1587 16,
1588 17,
1589 18,
1590 19,
1591 20,
1592 21,
1593 22,
1594 23,
1595 24,
1596 25,
1597 26,
1598 27,
1599 28,
1600 29,
1601 30,
1602 31,
1603 0,
1604 1,
1605 2,
1606 3,
1607 4,
1608 5,
1609 6,
1610 7,
1611 8,
1612 9,
1613 10,
1614 11,
1615 12,
1616 13,
1617 14,
1618 15,
1619 16,
1620 17,
1621 18,
1622 19,
1623 20,
1624 21,
1625 22,
1626 23,
1627 24,
1628 25,
1629 26,
1630 27,
1631 28,
1632 29,
1633 30,
1634 31,
1635 0,
1636 1,
1637 4,
1638 5,
1639 8,
1640 9,
1641 12,
1642 13,
1643 0,
1644 1,
1645 2,
1646 3,
1647 4,
1648 5,
1649 6,
1650 7,
1651 8,
1652 9,
1653 10,
1654 11,
1655 12,
1656 13,
1657 14,
1658 15,
1659 16,
1660 17,
1661 18,
1662 19,
1663 20,
1664 21,
1665 22,
1666 23,
1667 24,
1668 25,
1669 26,
1670 27,
1671 28,
1672 29,
1673 30,
1674 31,
1675 0,
1676 1,
1677 2,
1678 3,
1679 4,
1680 5,
1681 6,
1682 7,
1683 8,
1684 9,
1685 10,
1686 11,
1687 12,
1688 13,
1689 14,
1690 15,
1691 0,
1692 1,
1693 2,
1694 3,
1695 4,
1696 5,
1697 6,
1698 7,
1699 8,
1700 9,
1701 10,
1702 11,
1703 12,
1704 13,
1705 14,
1706 15,
1707 0,
1708 1,
1709 2,
1710 3,
1711 4,
1712 5,
1713 6,
1714 7,
1715 8,
1716 9,
1717 10,
1718 11,
1719 12,
1720 13,
1721 14,
1722 15,
1723 0,
1724 2,
1725 4,
1726 6,
1727 8,
1728 10,
1729 12,
1730 14,
1731};
1732static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1733 RI->InitMCRegisterInfo(SystemZRegDesc, 195, RA, PC, SystemZMCRegisterClasses, 22, SystemZRegUnitRoots, 98, SystemZRegDiffLists, SystemZLaneMaskLists, SystemZRegStrings, SystemZRegClassStrings, SystemZSubRegIdxLists, 7,
1734SystemZRegEncodingTable);
1735
1736 switch (DwarfFlavour) {
1737 default:
1738 llvm_unreachable("Unknown DWARF flavour");
1739 case 0:
1740 RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
1741 break;
1742 }
1743 switch (EHFlavour) {
1744 default:
1745 llvm_unreachable("Unknown DWARF flavour");
1746 case 0:
1747 RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
1748 break;
1749 }
1750 switch (DwarfFlavour) {
1751 default:
1752 llvm_unreachable("Unknown DWARF flavour");
1753 case 0:
1754 RI->mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
1755 break;
1756 }
1757 switch (EHFlavour) {
1758 default:
1759 llvm_unreachable("Unknown DWARF flavour");
1760 case 0:
1761 RI->mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
1762 break;
1763 }
1764}
1765
1766} // end namespace llvm
1767
1768#endif // GET_REGINFO_MC_DESC
1769
1770/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1771|* *|
1772|* Register Information Header Fragment *|
1773|* *|
1774|* Automatically generated file, do not edit! *|
1775|* *|
1776\*===----------------------------------------------------------------------===*/
1777
1778
1779#ifdef GET_REGINFO_HEADER
1780#undef GET_REGINFO_HEADER
1781
1782#include "llvm/CodeGen/TargetRegisterInfo.h"
1783
1784namespace llvm {
1785
1786class SystemZFrameLowering;
1787
1788struct SystemZGenRegisterInfo : public TargetRegisterInfo {
1789 explicit SystemZGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1790 unsigned PC = 0, unsigned HwMode = 0);
1791 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1792 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1793 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1794 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
1795 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
1796 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1797 unsigned getRegUnitWeight(unsigned RegUnit) const override;
1798 unsigned getNumRegPressureSets() const override;
1799 const char *getRegPressureSetName(unsigned Idx) const override;
1800 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1801 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1802 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1803 ArrayRef<const char *> getRegMaskNames() const override;
1804 ArrayRef<const uint32_t *> getRegMasks() const override;
1805 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
1806 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
1807 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
1808 bool isConstantPhysReg(MCRegister PhysReg) const override final;
1809 /// Devirtualized TargetFrameLowering.
1810 static const SystemZFrameLowering *getFrameLowering(
1811 const MachineFunction &MF);
1812};
1813
1814namespace SystemZ { // Register classes
1815 extern const TargetRegisterClass GRX32BitRegClass;
1816 extern const TargetRegisterClass VR32BitRegClass;
1817 extern const TargetRegisterClass AR32BitRegClass;
1818 extern const TargetRegisterClass FP32BitRegClass;
1819 extern const TargetRegisterClass GR32BitRegClass;
1820 extern const TargetRegisterClass GRH32BitRegClass;
1821 extern const TargetRegisterClass ADDR32BitRegClass;
1822 extern const TargetRegisterClass CCRRegClass;
1823 extern const TargetRegisterClass FPCRegsRegClass;
1824 extern const TargetRegisterClass AnyRegBitRegClass;
1825 extern const TargetRegisterClass AnyRegBit_with_subreg_h32_in_FP32BitRegClass;
1826 extern const TargetRegisterClass VR64BitRegClass;
1827 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass;
1828 extern const TargetRegisterClass CR64BitRegClass;
1829 extern const TargetRegisterClass FP64BitRegClass;
1830 extern const TargetRegisterClass GR64BitRegClass;
1831 extern const TargetRegisterClass ADDR64BitRegClass;
1832 extern const TargetRegisterClass VR128BitRegClass;
1833 extern const TargetRegisterClass VF128BitRegClass;
1834 extern const TargetRegisterClass FP128BitRegClass;
1835 extern const TargetRegisterClass GR128BitRegClass;
1836 extern const TargetRegisterClass ADDR128BitRegClass;
1837} // end namespace SystemZ
1838
1839} // end namespace llvm
1840
1841#endif // GET_REGINFO_HEADER
1842
1843/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1844|* *|
1845|* Target Register and Register Classes Information *|
1846|* *|
1847|* Automatically generated file, do not edit! *|
1848|* *|
1849\*===----------------------------------------------------------------------===*/
1850
1851
1852#ifdef GET_REGINFO_TARGET_DESC
1853#undef GET_REGINFO_TARGET_DESC
1854
1855namespace llvm {
1856
1857extern const MCRegisterClass SystemZMCRegisterClasses[];
1858
1859static const MVT::SimpleValueType VTLists[] = {
1860 /* 0 */ MVT::i32, MVT::Other,
1861 /* 2 */ MVT::i64, MVT::Other,
1862 /* 4 */ MVT::f32, MVT::Other,
1863 /* 6 */ MVT::f64, MVT::Other,
1864 /* 8 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
1865 /* 17 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
1866 /* 21 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
1867 /* 28 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
1868 /* 35 */ MVT::Untyped, MVT::Other,
1869};
1870
1871static const char *SubRegIndexNameTable[] = { "subreg_h32", "subreg_h64", "subreg_l32", "subreg_l64", "subreg_lh32", "subreg_ll32", "" };
1872
1873static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
1874 { 65535, 65535 },
1875 { 32, 32 }, // subreg_h32
1876 { 64, 64 }, // subreg_h64
1877 { 0, 32 }, // subreg_l32
1878 { 0, 64 }, // subreg_l64
1879 { 32, 32 }, // subreg_lh32
1880 { 0, 32 }, // subreg_ll32
1881};
1882
1883
1884static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1885 LaneBitmask::getAll(),
1886 LaneBitmask(0x0000000000000001), // subreg_h32
1887 LaneBitmask(0x0000000000000003), // subreg_h64
1888 LaneBitmask(0x0000000000000002), // subreg_l32
1889 LaneBitmask(0x000000000000000C), // subreg_l64
1890 LaneBitmask(0x0000000000000004), // subreg_lh32
1891 LaneBitmask(0x0000000000000008), // subreg_ll32
1892 };
1893
1894
1895
1896static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1897 // Mode = 0 (Default)
1898 { 32, 32, 32, /*VTLists+*/0 }, // GRX32Bit
1899 { 32, 32, 32, /*VTLists+*/17 }, // VR32Bit
1900 { 32, 32, 32, /*VTLists+*/0 }, // AR32Bit
1901 { 32, 32, 32, /*VTLists+*/4 }, // FP32Bit
1902 { 32, 32, 32, /*VTLists+*/0 }, // GR32Bit
1903 { 32, 32, 32, /*VTLists+*/0 }, // GRH32Bit
1904 { 32, 32, 32, /*VTLists+*/0 }, // ADDR32Bit
1905 { 32, 32, 32, /*VTLists+*/0 }, // CCR
1906 { 32, 32, 32, /*VTLists+*/0 }, // FPCRegs
1907 { 64, 64, 64, /*VTLists+*/21 }, // AnyRegBit
1908 { 64, 64, 64, /*VTLists+*/21 }, // AnyRegBit_with_subreg_h32_in_FP32Bit
1909 { 64, 64, 64, /*VTLists+*/22 }, // VR64Bit
1910 { 64, 64, 64, /*VTLists+*/21 }, // AnyRegBit_with_subreg_h64
1911 { 64, 64, 64, /*VTLists+*/2 }, // CR64Bit
1912 { 64, 64, 64, /*VTLists+*/6 }, // FP64Bit
1913 { 64, 64, 64, /*VTLists+*/2 }, // GR64Bit
1914 { 64, 64, 64, /*VTLists+*/2 }, // ADDR64Bit
1915 { 128, 128, 128, /*VTLists+*/8 }, // VR128Bit
1916 { 128, 128, 128, /*VTLists+*/28 }, // VF128Bit
1917 { 128, 128, 128, /*VTLists+*/15 }, // FP128Bit
1918 { 128, 128, 128, /*VTLists+*/35 }, // GR128Bit
1919 { 128, 128, 128, /*VTLists+*/35 }, // ADDR128Bit
1920};
1921
1922static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1923
1924static const uint32_t GRX32BitSubClassMask[] = {
1925 0x00000071,
1926 0x00318000, // subreg_h32
1927 0x00318000, // subreg_l32
1928 0x00300000, // subreg_lh32
1929 0x00300000, // subreg_ll32
1930};
1931
1932static const uint32_t VR32BitSubClassMask[] = {
1933 0x0000000a,
1934 0x000e5c00, // subreg_h32
1935 0x00080000, // subreg_lh32
1936};
1937
1938static const uint32_t AR32BitSubClassMask[] = {
1939 0x00000004,
1940};
1941
1942static const uint32_t FP32BitSubClassMask[] = {
1943 0x00000008,
1944 0x000c5400, // subreg_h32
1945 0x00080000, // subreg_lh32
1946};
1947
1948static const uint32_t GR32BitSubClassMask[] = {
1949 0x00000050,
1950 0x00318000, // subreg_l32
1951 0x00300000, // subreg_ll32
1952};
1953
1954static const uint32_t GRH32BitSubClassMask[] = {
1955 0x00000020,
1956 0x00318000, // subreg_h32
1957 0x00300000, // subreg_lh32
1958};
1959
1960static const uint32_t ADDR32BitSubClassMask[] = {
1961 0x00000040,
1962 0x00210000, // subreg_l32
1963 0x00300000, // subreg_ll32
1964};
1965
1966static const uint32_t CCRSubClassMask[] = {
1967 0x00000080,
1968};
1969
1970static const uint32_t FPCRegsSubClassMask[] = {
1971 0x00000100,
1972};
1973
1974static const uint32_t AnyRegBitSubClassMask[] = {
1975 0x0005d600,
1976 0x003c1000, // subreg_h64
1977 0x00380000, // subreg_l64
1978};
1979
1980static const uint32_t AnyRegBit_with_subreg_h32_in_FP32BitSubClassMask[] = {
1981 0x00045400,
1982 0x000c1000, // subreg_h64
1983 0x00080000, // subreg_l64
1984};
1985
1986static const uint32_t VR64BitSubClassMask[] = {
1987 0x00004800,
1988 0x000e1000, // subreg_h64
1989 0x00080000, // subreg_l64
1990};
1991
1992static const uint32_t AnyRegBit_with_subreg_h64SubClassMask[] = {
1993 0x00041000,
1994};
1995
1996static const uint32_t CR64BitSubClassMask[] = {
1997 0x00002000,
1998};
1999
2000static const uint32_t FP64BitSubClassMask[] = {
2001 0x00004000,
2002 0x000c1000, // subreg_h64
2003 0x00080000, // subreg_l64
2004};
2005
2006static const uint32_t GR64BitSubClassMask[] = {
2007 0x00018000,
2008 0x00300000, // subreg_h64
2009 0x00300000, // subreg_l64
2010};
2011
2012static const uint32_t ADDR64BitSubClassMask[] = {
2013 0x00010000,
2014 0x00200000, // subreg_h64
2015 0x00300000, // subreg_l64
2016};
2017
2018static const uint32_t VR128BitSubClassMask[] = {
2019 0x00060000,
2020};
2021
2022static const uint32_t VF128BitSubClassMask[] = {
2023 0x00040000,
2024};
2025
2026static const uint32_t FP128BitSubClassMask[] = {
2027 0x00080000,
2028};
2029
2030static const uint32_t GR128BitSubClassMask[] = {
2031 0x00300000,
2032};
2033
2034static const uint32_t ADDR128BitSubClassMask[] = {
2035 0x00200000,
2036};
2037
2038static const uint16_t SuperRegIdxSeqs[] = {
2039 /* 0 */ 2, 4, 0,
2040 /* 3 */ 1, 5, 0,
2041 /* 6 */ 3, 6, 0,
2042 /* 9 */ 1, 3, 5, 6, 0,
2043};
2044
2045static const TargetRegisterClass *const FP32BitSuperclasses[] = {
2046 &SystemZ::VR32BitRegClass,
2047 nullptr
2048};
2049
2050static const TargetRegisterClass *const GR32BitSuperclasses[] = {
2051 &SystemZ::GRX32BitRegClass,
2052 nullptr
2053};
2054
2055static const TargetRegisterClass *const GRH32BitSuperclasses[] = {
2056 &SystemZ::GRX32BitRegClass,
2057 nullptr
2058};
2059
2060static const TargetRegisterClass *const ADDR32BitSuperclasses[] = {
2061 &SystemZ::GRX32BitRegClass,
2062 &SystemZ::GR32BitRegClass,
2063 nullptr
2064};
2065
2066static const TargetRegisterClass *const AnyRegBit_with_subreg_h32_in_FP32BitSuperclasses[] = {
2067 &SystemZ::AnyRegBitRegClass,
2068 nullptr
2069};
2070
2071static const TargetRegisterClass *const AnyRegBit_with_subreg_h64Superclasses[] = {
2072 &SystemZ::AnyRegBitRegClass,
2073 &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2074 nullptr
2075};
2076
2077static const TargetRegisterClass *const FP64BitSuperclasses[] = {
2078 &SystemZ::AnyRegBitRegClass,
2079 &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2080 &SystemZ::VR64BitRegClass,
2081 nullptr
2082};
2083
2084static const TargetRegisterClass *const GR64BitSuperclasses[] = {
2085 &SystemZ::AnyRegBitRegClass,
2086 nullptr
2087};
2088
2089static const TargetRegisterClass *const ADDR64BitSuperclasses[] = {
2090 &SystemZ::AnyRegBitRegClass,
2091 &SystemZ::GR64BitRegClass,
2092 nullptr
2093};
2094
2095static const TargetRegisterClass *const VF128BitSuperclasses[] = {
2096 &SystemZ::AnyRegBitRegClass,
2097 &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2098 &SystemZ::AnyRegBit_with_subreg_h64RegClass,
2099 &SystemZ::VR128BitRegClass,
2100 nullptr
2101};
2102
2103static const TargetRegisterClass *const ADDR128BitSuperclasses[] = {
2104 &SystemZ::GR128BitRegClass,
2105 nullptr
2106};
2107
2108
2109static inline unsigned GRX32BitAltOrderSelect(const MachineFunction &MF) {
2110 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2111 return S.isTargetXPLINK64();
2112 }
2113
2114static ArrayRef<MCPhysReg> GRX32BitGetRawAllocationOrder(const MachineFunction &MF) {
2115 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4L, SystemZ::R4H, SystemZ::R5L, SystemZ::R5H, SystemZ::R6L, SystemZ::R6H, SystemZ::R7L, SystemZ::R7H, SystemZ::R8L, SystemZ::R8H, SystemZ::R9L, SystemZ::R9H, SystemZ::R10L, SystemZ::R10H, SystemZ::R11L, SystemZ::R11H, SystemZ::R12L, SystemZ::R12H, SystemZ::R13L, SystemZ::R13H, SystemZ::R14L, SystemZ::R14H, SystemZ::R15L, SystemZ::R15H };
2116 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRX32BitRegClassID];
2117 const ArrayRef<MCPhysReg> Order[] = {
2118 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2119 ArrayRef(AltOrder1)
2120 };
2121 const unsigned Select = GRX32BitAltOrderSelect(MF);
2122 assert(Select < 2);
2123 return Order[Select];
2124}
2125
2126static inline unsigned VR32BitAltOrderSelect(const MachineFunction &MF) {
2127 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2128 return S.isTargetXPLINK64();
2129 }
2130
2131static ArrayRef<MCPhysReg> VR32BitGetRawAllocationOrder(const MachineFunction &MF) {
2132 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
2133 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR32BitRegClassID];
2134 const ArrayRef<MCPhysReg> Order[] = {
2135 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2136 ArrayRef(AltOrder1)
2137 };
2138 const unsigned Select = VR32BitAltOrderSelect(MF);
2139 assert(Select < 2);
2140 return Order[Select];
2141}
2142
2143static inline unsigned AR32BitAltOrderSelect(const MachineFunction &MF) {
2144 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2145 return S.isTargetXPLINK64();
2146 }
2147
2148static ArrayRef<MCPhysReg> AR32BitGetRawAllocationOrder(const MachineFunction &MF) {
2149 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AR32BitRegClassID];
2150 const ArrayRef<MCPhysReg> Order[] = {
2151 ArrayRef(MCR.begin(), MCR.getNumRegs())
2152 };
2153 const unsigned Select = AR32BitAltOrderSelect(MF);
2154 assert(Select < 1);
2155 return Order[Select];
2156}
2157
2158static inline unsigned FP32BitAltOrderSelect(const MachineFunction &MF) {
2159 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2160 return S.isTargetXPLINK64();
2161 }
2162
2163static ArrayRef<MCPhysReg> FP32BitGetRawAllocationOrder(const MachineFunction &MF) {
2164 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
2165 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP32BitRegClassID];
2166 const ArrayRef<MCPhysReg> Order[] = {
2167 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2168 ArrayRef(AltOrder1)
2169 };
2170 const unsigned Select = FP32BitAltOrderSelect(MF);
2171 assert(Select < 2);
2172 return Order[Select];
2173}
2174
2175static inline unsigned GR32BitAltOrderSelect(const MachineFunction &MF) {
2176 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2177 return S.isTargetXPLINK64();
2178 }
2179
2180static ArrayRef<MCPhysReg> GR32BitGetRawAllocationOrder(const MachineFunction &MF) {
2181 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
2182 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR32BitRegClassID];
2183 const ArrayRef<MCPhysReg> Order[] = {
2184 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2185 ArrayRef(AltOrder1)
2186 };
2187 const unsigned Select = GR32BitAltOrderSelect(MF);
2188 assert(Select < 2);
2189 return Order[Select];
2190}
2191
2192static inline unsigned GRH32BitAltOrderSelect(const MachineFunction &MF) {
2193 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2194 return S.isTargetXPLINK64();
2195 }
2196
2197static ArrayRef<MCPhysReg> GRH32BitGetRawAllocationOrder(const MachineFunction &MF) {
2198 static const MCPhysReg AltOrder1[] = { SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H };
2199 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRH32BitRegClassID];
2200 const ArrayRef<MCPhysReg> Order[] = {
2201 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2202 ArrayRef(AltOrder1)
2203 };
2204 const unsigned Select = GRH32BitAltOrderSelect(MF);
2205 assert(Select < 2);
2206 return Order[Select];
2207}
2208
2209static inline unsigned ADDR32BitAltOrderSelect(const MachineFunction &MF) {
2210 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2211 return S.isTargetXPLINK64();
2212 }
2213
2214static ArrayRef<MCPhysReg> ADDR32BitGetRawAllocationOrder(const MachineFunction &MF) {
2215 static const MCPhysReg AltOrder1[] = { SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
2216 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR32BitRegClassID];
2217 const ArrayRef<MCPhysReg> Order[] = {
2218 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2219 ArrayRef(AltOrder1)
2220 };
2221 const unsigned Select = ADDR32BitAltOrderSelect(MF);
2222 assert(Select < 2);
2223 return Order[Select];
2224}
2225
2226static inline unsigned AnyRegBitAltOrderSelect(const MachineFunction &MF) {
2227 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2228 return S.isTargetXPLINK64();
2229 }
2230
2231static ArrayRef<MCPhysReg> AnyRegBitGetRawAllocationOrder(const MachineFunction &MF) {
2232 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBitRegClassID];
2233 const ArrayRef<MCPhysReg> Order[] = {
2234 ArrayRef(MCR.begin(), MCR.getNumRegs())
2235 };
2236 const unsigned Select = AnyRegBitAltOrderSelect(MF);
2237 assert(Select < 1);
2238 return Order[Select];
2239}
2240
2241static inline unsigned AnyRegBit_with_subreg_h32_in_FP32BitAltOrderSelect(const MachineFunction &MF) {
2242 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2243 return S.isTargetXPLINK64();
2244 }
2245
2246static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h32_in_FP32BitGetRawAllocationOrder(const MachineFunction &MF) {
2247 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClassID];
2248 const ArrayRef<MCPhysReg> Order[] = {
2249 ArrayRef(MCR.begin(), MCR.getNumRegs())
2250 };
2251 const unsigned Select = AnyRegBit_with_subreg_h32_in_FP32BitAltOrderSelect(MF);
2252 assert(Select < 1);
2253 return Order[Select];
2254}
2255
2256static inline unsigned VR64BitAltOrderSelect(const MachineFunction &MF) {
2257 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2258 return S.isTargetXPLINK64();
2259 }
2260
2261static ArrayRef<MCPhysReg> VR64BitGetRawAllocationOrder(const MachineFunction &MF) {
2262 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
2263 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR64BitRegClassID];
2264 const ArrayRef<MCPhysReg> Order[] = {
2265 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2266 ArrayRef(AltOrder1)
2267 };
2268 const unsigned Select = VR64BitAltOrderSelect(MF);
2269 assert(Select < 2);
2270 return Order[Select];
2271}
2272
2273static inline unsigned AnyRegBit_with_subreg_h64AltOrderSelect(const MachineFunction &MF) {
2274 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2275 return S.isTargetXPLINK64();
2276 }
2277
2278static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h64GetRawAllocationOrder(const MachineFunction &MF) {
2279 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h64RegClassID];
2280 const ArrayRef<MCPhysReg> Order[] = {
2281 ArrayRef(MCR.begin(), MCR.getNumRegs())
2282 };
2283 const unsigned Select = AnyRegBit_with_subreg_h64AltOrderSelect(MF);
2284 assert(Select < 1);
2285 return Order[Select];
2286}
2287
2288static inline unsigned CR64BitAltOrderSelect(const MachineFunction &MF) {
2289 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2290 return S.isTargetXPLINK64();
2291 }
2292
2293static ArrayRef<MCPhysReg> CR64BitGetRawAllocationOrder(const MachineFunction &MF) {
2294 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::CR64BitRegClassID];
2295 const ArrayRef<MCPhysReg> Order[] = {
2296 ArrayRef(MCR.begin(), MCR.getNumRegs())
2297 };
2298 const unsigned Select = CR64BitAltOrderSelect(MF);
2299 assert(Select < 1);
2300 return Order[Select];
2301}
2302
2303static inline unsigned FP64BitAltOrderSelect(const MachineFunction &MF) {
2304 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2305 return S.isTargetXPLINK64();
2306 }
2307
2308static ArrayRef<MCPhysReg> FP64BitGetRawAllocationOrder(const MachineFunction &MF) {
2309 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
2310 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP64BitRegClassID];
2311 const ArrayRef<MCPhysReg> Order[] = {
2312 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2313 ArrayRef(AltOrder1)
2314 };
2315 const unsigned Select = FP64BitAltOrderSelect(MF);
2316 assert(Select < 2);
2317 return Order[Select];
2318}
2319
2320static inline unsigned GR64BitAltOrderSelect(const MachineFunction &MF) {
2321 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2322 return S.isTargetXPLINK64();
2323 }
2324
2325static ArrayRef<MCPhysReg> GR64BitGetRawAllocationOrder(const MachineFunction &MF) {
2326 static const MCPhysReg AltOrder1[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
2327 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR64BitRegClassID];
2328 const ArrayRef<MCPhysReg> Order[] = {
2329 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2330 ArrayRef(AltOrder1)
2331 };
2332 const unsigned Select = GR64BitAltOrderSelect(MF);
2333 assert(Select < 2);
2334 return Order[Select];
2335}
2336
2337static inline unsigned ADDR64BitAltOrderSelect(const MachineFunction &MF) {
2338 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2339 return S.isTargetXPLINK64();
2340 }
2341
2342static ArrayRef<MCPhysReg> ADDR64BitGetRawAllocationOrder(const MachineFunction &MF) {
2343 static const MCPhysReg AltOrder1[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
2344 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR64BitRegClassID];
2345 const ArrayRef<MCPhysReg> Order[] = {
2346 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2347 ArrayRef(AltOrder1)
2348 };
2349 const unsigned Select = ADDR64BitAltOrderSelect(MF);
2350 assert(Select < 2);
2351 return Order[Select];
2352}
2353
2354static inline unsigned VR128BitAltOrderSelect(const MachineFunction &MF) {
2355 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2356 return S.isTargetXPLINK64();
2357 }
2358
2359static ArrayRef<MCPhysReg> VR128BitGetRawAllocationOrder(const MachineFunction &MF) {
2360 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
2361 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR128BitRegClassID];
2362 const ArrayRef<MCPhysReg> Order[] = {
2363 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2364 ArrayRef(AltOrder1)
2365 };
2366 const unsigned Select = VR128BitAltOrderSelect(MF);
2367 assert(Select < 2);
2368 return Order[Select];
2369}
2370
2371static inline unsigned VF128BitAltOrderSelect(const MachineFunction &MF) {
2372 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2373 return S.isTargetXPLINK64();
2374 }
2375
2376static ArrayRef<MCPhysReg> VF128BitGetRawAllocationOrder(const MachineFunction &MF) {
2377 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
2378 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VF128BitRegClassID];
2379 const ArrayRef<MCPhysReg> Order[] = {
2380 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2381 ArrayRef(AltOrder1)
2382 };
2383 const unsigned Select = VF128BitAltOrderSelect(MF);
2384 assert(Select < 2);
2385 return Order[Select];
2386}
2387
2388static inline unsigned FP128BitAltOrderSelect(const MachineFunction &MF) {
2389 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2390 return S.isTargetXPLINK64();
2391 }
2392
2393static ArrayRef<MCPhysReg> FP128BitGetRawAllocationOrder(const MachineFunction &MF) {
2394 static const MCPhysReg AltOrder1[] = { SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q };
2395 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP128BitRegClassID];
2396 const ArrayRef<MCPhysReg> Order[] = {
2397 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2398 ArrayRef(AltOrder1)
2399 };
2400 const unsigned Select = FP128BitAltOrderSelect(MF);
2401 assert(Select < 2);
2402 return Order[Select];
2403}
2404
2405static inline unsigned GR128BitAltOrderSelect(const MachineFunction &MF) {
2406 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2407 return S.isTargetXPLINK64();
2408 }
2409
2410static ArrayRef<MCPhysReg> GR128BitGetRawAllocationOrder(const MachineFunction &MF) {
2411 static const MCPhysReg AltOrder1[] = { SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
2412 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR128BitRegClassID];
2413 const ArrayRef<MCPhysReg> Order[] = {
2414 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2415 ArrayRef(AltOrder1)
2416 };
2417 const unsigned Select = GR128BitAltOrderSelect(MF);
2418 assert(Select < 2);
2419 return Order[Select];
2420}
2421
2422static inline unsigned ADDR128BitAltOrderSelect(const MachineFunction &MF) {
2423 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2424 return S.isTargetXPLINK64();
2425 }
2426
2427static ArrayRef<MCPhysReg> ADDR128BitGetRawAllocationOrder(const MachineFunction &MF) {
2428 static const MCPhysReg AltOrder1[] = { SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
2429 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR128BitRegClassID];
2430 const ArrayRef<MCPhysReg> Order[] = {
2431 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2432 ArrayRef(AltOrder1)
2433 };
2434 const unsigned Select = ADDR128BitAltOrderSelect(MF);
2435 assert(Select < 2);
2436 return Order[Select];
2437}
2438
2439namespace SystemZ { // Register class instances
2440 extern const TargetRegisterClass GRX32BitRegClass = {
2441 &SystemZMCRegisterClasses[GRX32BitRegClassID],
2442 GRX32BitSubClassMask,
2443 SuperRegIdxSeqs + 9,
2444 LaneBitmask(0x0000000000000001),
2445 0,
2446 false,
2447 0x00, /* TSFlags */
2448 false, /* HasDisjunctSubRegs */
2449 false, /* CoveredBySubRegs */
2450 NullRegClasses,
2451 GRX32BitGetRawAllocationOrder
2452 };
2453
2454 extern const TargetRegisterClass VR32BitRegClass = {
2455 &SystemZMCRegisterClasses[VR32BitRegClassID],
2456 VR32BitSubClassMask,
2457 SuperRegIdxSeqs + 3,
2458 LaneBitmask(0x0000000000000001),
2459 0,
2460 false,
2461 0x00, /* TSFlags */
2462 false, /* HasDisjunctSubRegs */
2463 false, /* CoveredBySubRegs */
2464 NullRegClasses,
2465 VR32BitGetRawAllocationOrder
2466 };
2467
2468 extern const TargetRegisterClass AR32BitRegClass = {
2469 &SystemZMCRegisterClasses[AR32BitRegClassID],
2470 AR32BitSubClassMask,
2471 SuperRegIdxSeqs + 2,
2472 LaneBitmask(0x0000000000000001),
2473 0,
2474 false,
2475 0x00, /* TSFlags */
2476 false, /* HasDisjunctSubRegs */
2477 false, /* CoveredBySubRegs */
2478 NullRegClasses,
2479 AR32BitGetRawAllocationOrder
2480 };
2481
2482 extern const TargetRegisterClass FP32BitRegClass = {
2483 &SystemZMCRegisterClasses[FP32BitRegClassID],
2484 FP32BitSubClassMask,
2485 SuperRegIdxSeqs + 3,
2486 LaneBitmask(0x0000000000000001),
2487 0,
2488 false,
2489 0x00, /* TSFlags */
2490 false, /* HasDisjunctSubRegs */
2491 false, /* CoveredBySubRegs */
2492 FP32BitSuperclasses,
2493 FP32BitGetRawAllocationOrder
2494 };
2495
2496 extern const TargetRegisterClass GR32BitRegClass = {
2497 &SystemZMCRegisterClasses[GR32BitRegClassID],
2498 GR32BitSubClassMask,
2499 SuperRegIdxSeqs + 6,
2500 LaneBitmask(0x0000000000000001),
2501 0,
2502 false,
2503 0x00, /* TSFlags */
2504 false, /* HasDisjunctSubRegs */
2505 false, /* CoveredBySubRegs */
2506 GR32BitSuperclasses,
2507 GR32BitGetRawAllocationOrder
2508 };
2509
2510 extern const TargetRegisterClass GRH32BitRegClass = {
2511 &SystemZMCRegisterClasses[GRH32BitRegClassID],
2512 GRH32BitSubClassMask,
2513 SuperRegIdxSeqs + 3,
2514 LaneBitmask(0x0000000000000001),
2515 0,
2516 false,
2517 0x00, /* TSFlags */
2518 false, /* HasDisjunctSubRegs */
2519 false, /* CoveredBySubRegs */
2520 GRH32BitSuperclasses,
2521 GRH32BitGetRawAllocationOrder
2522 };
2523
2524 extern const TargetRegisterClass ADDR32BitRegClass = {
2525 &SystemZMCRegisterClasses[ADDR32BitRegClassID],
2526 ADDR32BitSubClassMask,
2527 SuperRegIdxSeqs + 6,
2528 LaneBitmask(0x0000000000000001),
2529 0,
2530 false,
2531 0x00, /* TSFlags */
2532 false, /* HasDisjunctSubRegs */
2533 false, /* CoveredBySubRegs */
2534 ADDR32BitSuperclasses,
2535 ADDR32BitGetRawAllocationOrder
2536 };
2537
2538 extern const TargetRegisterClass CCRRegClass = {
2539 &SystemZMCRegisterClasses[CCRRegClassID],
2540 CCRSubClassMask,
2541 SuperRegIdxSeqs + 2,
2542 LaneBitmask(0x0000000000000001),
2543 0,
2544 false,
2545 0x00, /* TSFlags */
2546 false, /* HasDisjunctSubRegs */
2547 false, /* CoveredBySubRegs */
2548 NullRegClasses,
2549 nullptr
2550 };
2551
2552 extern const TargetRegisterClass FPCRegsRegClass = {
2553 &SystemZMCRegisterClasses[FPCRegsRegClassID],
2554 FPCRegsSubClassMask,
2555 SuperRegIdxSeqs + 2,
2556 LaneBitmask(0x0000000000000001),
2557 0,
2558 false,
2559 0x00, /* TSFlags */
2560 false, /* HasDisjunctSubRegs */
2561 false, /* CoveredBySubRegs */
2562 NullRegClasses,
2563 nullptr
2564 };
2565
2566 extern const TargetRegisterClass AnyRegBitRegClass = {
2567 &SystemZMCRegisterClasses[AnyRegBitRegClassID],
2568 AnyRegBitSubClassMask,
2569 SuperRegIdxSeqs + 0,
2570 LaneBitmask(0x0000000000000003),
2571 0,
2572 false,
2573 0x00, /* TSFlags */
2574 true, /* HasDisjunctSubRegs */
2575 false, /* CoveredBySubRegs */
2576 NullRegClasses,
2577 AnyRegBitGetRawAllocationOrder
2578 };
2579
2580 extern const TargetRegisterClass AnyRegBit_with_subreg_h32_in_FP32BitRegClass = {
2581 &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h32_in_FP32BitRegClassID],
2582 AnyRegBit_with_subreg_h32_in_FP32BitSubClassMask,
2583 SuperRegIdxSeqs + 0,
2584 LaneBitmask(0x0000000000000003),
2585 0,
2586 false,
2587 0x00, /* TSFlags */
2588 false, /* HasDisjunctSubRegs */
2589 false, /* CoveredBySubRegs */
2590 AnyRegBit_with_subreg_h32_in_FP32BitSuperclasses,
2591 AnyRegBit_with_subreg_h32_in_FP32BitGetRawAllocationOrder
2592 };
2593
2594 extern const TargetRegisterClass VR64BitRegClass = {
2595 &SystemZMCRegisterClasses[VR64BitRegClassID],
2596 VR64BitSubClassMask,
2597 SuperRegIdxSeqs + 0,
2598 LaneBitmask(0x0000000000000001),
2599 0,
2600 false,
2601 0x00, /* TSFlags */
2602 false, /* HasDisjunctSubRegs */
2603 false, /* CoveredBySubRegs */
2604 NullRegClasses,
2605 VR64BitGetRawAllocationOrder
2606 };
2607
2608 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
2609 &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h64RegClassID],
2610 AnyRegBit_with_subreg_h64SubClassMask,
2611 SuperRegIdxSeqs + 2,
2612 LaneBitmask(0x0000000000000003),
2613 0,
2614 false,
2615 0x00, /* TSFlags */
2616 false, /* HasDisjunctSubRegs */
2617 false, /* CoveredBySubRegs */
2618 AnyRegBit_with_subreg_h64Superclasses,
2619 AnyRegBit_with_subreg_h64GetRawAllocationOrder
2620 };
2621
2622 extern const TargetRegisterClass CR64BitRegClass = {
2623 &SystemZMCRegisterClasses[CR64BitRegClassID],
2624 CR64BitSubClassMask,
2625 SuperRegIdxSeqs + 2,
2626 LaneBitmask(0x0000000000000001),
2627 0,
2628 false,
2629 0x00, /* TSFlags */
2630 false, /* HasDisjunctSubRegs */
2631 false, /* CoveredBySubRegs */
2632 NullRegClasses,
2633 CR64BitGetRawAllocationOrder
2634 };
2635
2636 extern const TargetRegisterClass FP64BitRegClass = {
2637 &SystemZMCRegisterClasses[FP64BitRegClassID],
2638 FP64BitSubClassMask,
2639 SuperRegIdxSeqs + 0,
2640 LaneBitmask(0x0000000000000001),
2641 0,
2642 false,
2643 0x00, /* TSFlags */
2644 false, /* HasDisjunctSubRegs */
2645 false, /* CoveredBySubRegs */
2646 FP64BitSuperclasses,
2647 FP64BitGetRawAllocationOrder
2648 };
2649
2650 extern const TargetRegisterClass GR64BitRegClass = {
2651 &SystemZMCRegisterClasses[GR64BitRegClassID],
2652 GR64BitSubClassMask,
2653 SuperRegIdxSeqs + 0,
2654 LaneBitmask(0x0000000000000003),
2655 0,
2656 false,
2657 0x00, /* TSFlags */
2658 true, /* HasDisjunctSubRegs */
2659 true, /* CoveredBySubRegs */
2660 GR64BitSuperclasses,
2661 GR64BitGetRawAllocationOrder
2662 };
2663
2664 extern const TargetRegisterClass ADDR64BitRegClass = {
2665 &SystemZMCRegisterClasses[ADDR64BitRegClassID],
2666 ADDR64BitSubClassMask,
2667 SuperRegIdxSeqs + 0,
2668 LaneBitmask(0x0000000000000003),
2669 0,
2670 false,
2671 0x00, /* TSFlags */
2672 true, /* HasDisjunctSubRegs */
2673 true, /* CoveredBySubRegs */
2674 ADDR64BitSuperclasses,
2675 ADDR64BitGetRawAllocationOrder
2676 };
2677
2678 extern const TargetRegisterClass VR128BitRegClass = {
2679 &SystemZMCRegisterClasses[VR128BitRegClassID],
2680 VR128BitSubClassMask,
2681 SuperRegIdxSeqs + 2,
2682 LaneBitmask(0x0000000000000003),
2683 0,
2684 false,
2685 0x00, /* TSFlags */
2686 false, /* HasDisjunctSubRegs */
2687 false, /* CoveredBySubRegs */
2688 NullRegClasses,
2689 VR128BitGetRawAllocationOrder
2690 };
2691
2692 extern const TargetRegisterClass VF128BitRegClass = {
2693 &SystemZMCRegisterClasses[VF128BitRegClassID],
2694 VF128BitSubClassMask,
2695 SuperRegIdxSeqs + 2,
2696 LaneBitmask(0x0000000000000003),
2697 0,
2698 false,
2699 0x00, /* TSFlags */
2700 false, /* HasDisjunctSubRegs */
2701 false, /* CoveredBySubRegs */
2702 VF128BitSuperclasses,
2703 VF128BitGetRawAllocationOrder
2704 };
2705
2706 extern const TargetRegisterClass FP128BitRegClass = {
2707 &SystemZMCRegisterClasses[FP128BitRegClassID],
2708 FP128BitSubClassMask,
2709 SuperRegIdxSeqs + 2,
2710 LaneBitmask(0x000000000000000F),
2711 0,
2712 false,
2713 0x00, /* TSFlags */
2714 true, /* HasDisjunctSubRegs */
2715 true, /* CoveredBySubRegs */
2716 NullRegClasses,
2717 FP128BitGetRawAllocationOrder
2718 };
2719
2720 extern const TargetRegisterClass GR128BitRegClass = {
2721 &SystemZMCRegisterClasses[GR128BitRegClassID],
2722 GR128BitSubClassMask,
2723 SuperRegIdxSeqs + 2,
2724 LaneBitmask(0x000000000000000F),
2725 0,
2726 false,
2727 0x00, /* TSFlags */
2728 true, /* HasDisjunctSubRegs */
2729 true, /* CoveredBySubRegs */
2730 NullRegClasses,
2731 GR128BitGetRawAllocationOrder
2732 };
2733
2734 extern const TargetRegisterClass ADDR128BitRegClass = {
2735 &SystemZMCRegisterClasses[ADDR128BitRegClassID],
2736 ADDR128BitSubClassMask,
2737 SuperRegIdxSeqs + 2,
2738 LaneBitmask(0x000000000000000F),
2739 0,
2740 false,
2741 0x00, /* TSFlags */
2742 true, /* HasDisjunctSubRegs */
2743 true, /* CoveredBySubRegs */
2744 ADDR128BitSuperclasses,
2745 ADDR128BitGetRawAllocationOrder
2746 };
2747
2748} // end namespace SystemZ
2749
2750namespace {
2751 const TargetRegisterClass *const RegisterClasses[] = {
2752 &SystemZ::GRX32BitRegClass,
2753 &SystemZ::VR32BitRegClass,
2754 &SystemZ::AR32BitRegClass,
2755 &SystemZ::FP32BitRegClass,
2756 &SystemZ::GR32BitRegClass,
2757 &SystemZ::GRH32BitRegClass,
2758 &SystemZ::ADDR32BitRegClass,
2759 &SystemZ::CCRRegClass,
2760 &SystemZ::FPCRegsRegClass,
2761 &SystemZ::AnyRegBitRegClass,
2762 &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2763 &SystemZ::VR64BitRegClass,
2764 &SystemZ::AnyRegBit_with_subreg_h64RegClass,
2765 &SystemZ::CR64BitRegClass,
2766 &SystemZ::FP64BitRegClass,
2767 &SystemZ::GR64BitRegClass,
2768 &SystemZ::ADDR64BitRegClass,
2769 &SystemZ::VR128BitRegClass,
2770 &SystemZ::VF128BitRegClass,
2771 &SystemZ::FP128BitRegClass,
2772 &SystemZ::GR128BitRegClass,
2773 &SystemZ::ADDR128BitRegClass,
2774 };
2775} // end anonymous namespace
2776
2777static const uint8_t CostPerUseTable[] = {
27780, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
2779
2780
2781static const bool InAllocatableClassTable[] = {
2782false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
2783
2784
2785static const TargetRegisterInfoDesc SystemZRegInfoDesc = { // Extra Descriptors
2786CostPerUseTable, 1, InAllocatableClassTable};
2787
2788unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2789 static const uint8_t RowMap[6] = {
2790 0, 0, 0, 1, 0, 0,
2791 };
2792 static const uint8_t Rows[2][6] = {
2793 { SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, },
2794 { SystemZ::subreg_lh32, 0, SystemZ::subreg_ll32, 0, 0, 0, },
2795 };
2796
2797 --IdxA; assert(IdxA < 6); (void) IdxA;
2798 --IdxB; assert(IdxB < 6);
2799 return Rows[RowMap[IdxA]][IdxB];
2800}
2801
2802 struct MaskRolOp {
2803 LaneBitmask Mask;
2804 uint8_t RotateLeft;
2805 };
2806 static const MaskRolOp LaneMaskComposeSequences[] = {
2807 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
2808 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
2809 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
2810 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 } // Sequence 6
2811 };
2812 static const uint8_t CompositeSequences[] = {
2813 0, // to subreg_h32
2814 0, // to subreg_h64
2815 2, // to subreg_l32
2816 4, // to subreg_l64
2817 4, // to subreg_lh32
2818 6 // to subreg_ll32
2819 };
2820
2821LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2822 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2823 LaneBitmask Result;
2824 for (const MaskRolOp *Ops =
2825 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2826 Ops->Mask.any(); ++Ops) {
2827 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2828 if (unsigned S = Ops->RotateLeft)
2829 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2830 else
2831 Result |= LaneBitmask(M);
2832 }
2833 return Result;
2834}
2835
2836LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2837 LaneMask &= getSubRegIndexLaneMask(IdxA);
2838 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2839 LaneBitmask Result;
2840 for (const MaskRolOp *Ops =
2841 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2842 Ops->Mask.any(); ++Ops) {
2843 LaneBitmask::Type M = LaneMask.getAsInteger();
2844 if (unsigned S = Ops->RotateLeft)
2845 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2846 else
2847 Result |= LaneBitmask(M);
2848 }
2849 return Result;
2850}
2851
2852const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2853 static const uint8_t Table[22][6] = {
2854 { // GRX32Bit
2855 0, // subreg_h32
2856 0, // subreg_h64
2857 0, // subreg_l32
2858 0, // subreg_l64
2859 0, // subreg_lh32
2860 0, // subreg_ll32
2861 },
2862 { // VR32Bit
2863 0, // subreg_h32
2864 0, // subreg_h64
2865 0, // subreg_l32
2866 0, // subreg_l64
2867 0, // subreg_lh32
2868 0, // subreg_ll32
2869 },
2870 { // AR32Bit
2871 0, // subreg_h32
2872 0, // subreg_h64
2873 0, // subreg_l32
2874 0, // subreg_l64
2875 0, // subreg_lh32
2876 0, // subreg_ll32
2877 },
2878 { // FP32Bit
2879 0, // subreg_h32
2880 0, // subreg_h64
2881 0, // subreg_l32
2882 0, // subreg_l64
2883 0, // subreg_lh32
2884 0, // subreg_ll32
2885 },
2886 { // GR32Bit
2887 0, // subreg_h32
2888 0, // subreg_h64
2889 0, // subreg_l32
2890 0, // subreg_l64
2891 0, // subreg_lh32
2892 0, // subreg_ll32
2893 },
2894 { // GRH32Bit
2895 0, // subreg_h32
2896 0, // subreg_h64
2897 0, // subreg_l32
2898 0, // subreg_l64
2899 0, // subreg_lh32
2900 0, // subreg_ll32
2901 },
2902 { // ADDR32Bit
2903 0, // subreg_h32
2904 0, // subreg_h64
2905 0, // subreg_l32
2906 0, // subreg_l64
2907 0, // subreg_lh32
2908 0, // subreg_ll32
2909 },
2910 { // CCR
2911 0, // subreg_h32
2912 0, // subreg_h64
2913 0, // subreg_l32
2914 0, // subreg_l64
2915 0, // subreg_lh32
2916 0, // subreg_ll32
2917 },
2918 { // FPCRegs
2919 0, // subreg_h32
2920 0, // subreg_h64
2921 0, // subreg_l32
2922 0, // subreg_l64
2923 0, // subreg_lh32
2924 0, // subreg_ll32
2925 },
2926 { // AnyRegBit
2927 10, // subreg_h32 -> AnyRegBit
2928 13, // subreg_h64 -> AnyRegBit_with_subreg_h64
2929 16, // subreg_l32 -> GR64Bit
2930 0, // subreg_l64
2931 0, // subreg_lh32
2932 0, // subreg_ll32
2933 },
2934 { // AnyRegBit_with_subreg_h32_in_FP32Bit
2935 11, // subreg_h32 -> AnyRegBit_with_subreg_h32_in_FP32Bit
2936 13, // subreg_h64 -> AnyRegBit_with_subreg_h64
2937 0, // subreg_l32
2938 0, // subreg_l64
2939 0, // subreg_lh32
2940 0, // subreg_ll32
2941 },
2942 { // VR64Bit
2943 12, // subreg_h32 -> VR64Bit
2944 0, // subreg_h64
2945 0, // subreg_l32
2946 0, // subreg_l64
2947 0, // subreg_lh32
2948 0, // subreg_ll32
2949 },
2950 { // AnyRegBit_with_subreg_h64
2951 13, // subreg_h32 -> AnyRegBit_with_subreg_h64
2952 13, // subreg_h64 -> AnyRegBit_with_subreg_h64
2953 0, // subreg_l32
2954 0, // subreg_l64
2955 0, // subreg_lh32
2956 0, // subreg_ll32
2957 },
2958 { // CR64Bit
2959 0, // subreg_h32
2960 0, // subreg_h64
2961 0, // subreg_l32
2962 0, // subreg_l64
2963 0, // subreg_lh32
2964 0, // subreg_ll32
2965 },
2966 { // FP64Bit
2967 15, // subreg_h32 -> FP64Bit
2968 0, // subreg_h64
2969 0, // subreg_l32
2970 0, // subreg_l64
2971 0, // subreg_lh32
2972 0, // subreg_ll32
2973 },
2974 { // GR64Bit
2975 16, // subreg_h32 -> GR64Bit
2976 0, // subreg_h64
2977 16, // subreg_l32 -> GR64Bit
2978 0, // subreg_l64
2979 0, // subreg_lh32
2980 0, // subreg_ll32
2981 },
2982 { // ADDR64Bit
2983 17, // subreg_h32 -> ADDR64Bit
2984 0, // subreg_h64
2985 17, // subreg_l32 -> ADDR64Bit
2986 0, // subreg_l64
2987 0, // subreg_lh32
2988 0, // subreg_ll32
2989 },
2990 { // VR128Bit
2991 18, // subreg_h32 -> VR128Bit
2992 18, // subreg_h64 -> VR128Bit
2993 0, // subreg_l32
2994 0, // subreg_l64
2995 0, // subreg_lh32
2996 0, // subreg_ll32
2997 },
2998 { // VF128Bit
2999 19, // subreg_h32 -> VF128Bit
3000 19, // subreg_h64 -> VF128Bit
3001 0, // subreg_l32
3002 0, // subreg_l64
3003 0, // subreg_lh32
3004 0, // subreg_ll32
3005 },
3006 { // FP128Bit
3007 20, // subreg_h32 -> FP128Bit
3008 20, // subreg_h64 -> FP128Bit
3009 0, // subreg_l32
3010 20, // subreg_l64 -> FP128Bit
3011 20, // subreg_lh32 -> FP128Bit
3012 0, // subreg_ll32
3013 },
3014 { // GR128Bit
3015 21, // subreg_h32 -> GR128Bit
3016 21, // subreg_h64 -> GR128Bit
3017 21, // subreg_l32 -> GR128Bit
3018 21, // subreg_l64 -> GR128Bit
3019 21, // subreg_lh32 -> GR128Bit
3020 21, // subreg_ll32 -> GR128Bit
3021 },
3022 { // ADDR128Bit
3023 22, // subreg_h32 -> ADDR128Bit
3024 22, // subreg_h64 -> ADDR128Bit
3025 22, // subreg_l32 -> ADDR128Bit
3026 22, // subreg_l64 -> ADDR128Bit
3027 22, // subreg_lh32 -> ADDR128Bit
3028 22, // subreg_ll32 -> ADDR128Bit
3029 },
3030 };
3031 assert(RC && "Missing regclass");
3032 if (!Idx) return RC;
3033 --Idx;
3034 assert(Idx < 6 && "Bad subreg");
3035 unsigned TV = Table[RC->getID()][Idx];
3036 return TV ? getRegClass(TV - 1) : nullptr;
3037}
3038
3039const TargetRegisterClass *SystemZGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
3040 static const uint8_t Table[22][6] = {
3041 { // GRX32Bit
3042 0, // GRX32Bit:subreg_h32
3043 0, // GRX32Bit:subreg_h64
3044 0, // GRX32Bit:subreg_l32
3045 0, // GRX32Bit:subreg_l64
3046 0, // GRX32Bit:subreg_lh32
3047 0, // GRX32Bit:subreg_ll32
3048 },
3049 { // VR32Bit
3050 0, // VR32Bit:subreg_h32
3051 0, // VR32Bit:subreg_h64
3052 0, // VR32Bit:subreg_l32
3053 0, // VR32Bit:subreg_l64
3054 0, // VR32Bit:subreg_lh32
3055 0, // VR32Bit:subreg_ll32
3056 },
3057 { // AR32Bit
3058 0, // AR32Bit:subreg_h32
3059 0, // AR32Bit:subreg_h64
3060 0, // AR32Bit:subreg_l32
3061 0, // AR32Bit:subreg_l64
3062 0, // AR32Bit:subreg_lh32
3063 0, // AR32Bit:subreg_ll32
3064 },
3065 { // FP32Bit
3066 0, // FP32Bit:subreg_h32
3067 0, // FP32Bit:subreg_h64
3068 0, // FP32Bit:subreg_l32
3069 0, // FP32Bit:subreg_l64
3070 0, // FP32Bit:subreg_lh32
3071 0, // FP32Bit:subreg_ll32
3072 },
3073 { // GR32Bit
3074 0, // GR32Bit:subreg_h32
3075 0, // GR32Bit:subreg_h64
3076 0, // GR32Bit:subreg_l32
3077 0, // GR32Bit:subreg_l64
3078 0, // GR32Bit:subreg_lh32
3079 0, // GR32Bit:subreg_ll32
3080 },
3081 { // GRH32Bit
3082 0, // GRH32Bit:subreg_h32
3083 0, // GRH32Bit:subreg_h64
3084 0, // GRH32Bit:subreg_l32
3085 0, // GRH32Bit:subreg_l64
3086 0, // GRH32Bit:subreg_lh32
3087 0, // GRH32Bit:subreg_ll32
3088 },
3089 { // ADDR32Bit
3090 0, // ADDR32Bit:subreg_h32
3091 0, // ADDR32Bit:subreg_h64
3092 0, // ADDR32Bit:subreg_l32
3093 0, // ADDR32Bit:subreg_l64
3094 0, // ADDR32Bit:subreg_lh32
3095 0, // ADDR32Bit:subreg_ll32
3096 },
3097 { // CCR
3098 0, // CCR:subreg_h32
3099 0, // CCR:subreg_h64
3100 0, // CCR:subreg_l32
3101 0, // CCR:subreg_l64
3102 0, // CCR:subreg_lh32
3103 0, // CCR:subreg_ll32
3104 },
3105 { // FPCRegs
3106 0, // FPCRegs:subreg_h32
3107 0, // FPCRegs:subreg_h64
3108 0, // FPCRegs:subreg_l32
3109 0, // FPCRegs:subreg_l64
3110 0, // FPCRegs:subreg_lh32
3111 0, // FPCRegs:subreg_ll32
3112 },
3113 { // AnyRegBit
3114 2, // AnyRegBit:subreg_h32 -> VR32Bit
3115 15, // AnyRegBit:subreg_h64 -> FP64Bit
3116 5, // AnyRegBit:subreg_l32 -> GR32Bit
3117 0, // AnyRegBit:subreg_l64
3118 0, // AnyRegBit:subreg_lh32
3119 0, // AnyRegBit:subreg_ll32
3120 },
3121 { // AnyRegBit_with_subreg_h32_in_FP32Bit
3122 2, // AnyRegBit_with_subreg_h32_in_FP32Bit:subreg_h32 -> VR32Bit
3123 15, // AnyRegBit_with_subreg_h32_in_FP32Bit:subreg_h64 -> FP64Bit
3124 0, // AnyRegBit_with_subreg_h32_in_FP32Bit:subreg_l32
3125 0, // AnyRegBit_with_subreg_h32_in_FP32Bit:subreg_l64
3126 0, // AnyRegBit_with_subreg_h32_in_FP32Bit:subreg_lh32
3127 0, // AnyRegBit_with_subreg_h32_in_FP32Bit:subreg_ll32
3128 },
3129 { // VR64Bit
3130 2, // VR64Bit:subreg_h32 -> VR32Bit
3131 0, // VR64Bit:subreg_h64
3132 0, // VR64Bit:subreg_l32
3133 0, // VR64Bit:subreg_l64
3134 0, // VR64Bit:subreg_lh32
3135 0, // VR64Bit:subreg_ll32
3136 },
3137 { // AnyRegBit_with_subreg_h64
3138 4, // AnyRegBit_with_subreg_h64:subreg_h32 -> FP32Bit
3139 15, // AnyRegBit_with_subreg_h64:subreg_h64 -> FP64Bit
3140 0, // AnyRegBit_with_subreg_h64:subreg_l32
3141 0, // AnyRegBit_with_subreg_h64:subreg_l64
3142 0, // AnyRegBit_with_subreg_h64:subreg_lh32
3143 0, // AnyRegBit_with_subreg_h64:subreg_ll32
3144 },
3145 { // CR64Bit
3146 0, // CR64Bit:subreg_h32
3147 0, // CR64Bit:subreg_h64
3148 0, // CR64Bit:subreg_l32
3149 0, // CR64Bit:subreg_l64
3150 0, // CR64Bit:subreg_lh32
3151 0, // CR64Bit:subreg_ll32
3152 },
3153 { // FP64Bit
3154 4, // FP64Bit:subreg_h32 -> FP32Bit
3155 0, // FP64Bit:subreg_h64
3156 0, // FP64Bit:subreg_l32
3157 0, // FP64Bit:subreg_l64
3158 0, // FP64Bit:subreg_lh32
3159 0, // FP64Bit:subreg_ll32
3160 },
3161 { // GR64Bit
3162 6, // GR64Bit:subreg_h32 -> GRH32Bit
3163 0, // GR64Bit:subreg_h64
3164 5, // GR64Bit:subreg_l32 -> GR32Bit
3165 0, // GR64Bit:subreg_l64
3166 0, // GR64Bit:subreg_lh32
3167 0, // GR64Bit:subreg_ll32
3168 },
3169 { // ADDR64Bit
3170 6, // ADDR64Bit:subreg_h32 -> GRH32Bit
3171 0, // ADDR64Bit:subreg_h64
3172 7, // ADDR64Bit:subreg_l32 -> ADDR32Bit
3173 0, // ADDR64Bit:subreg_l64
3174 0, // ADDR64Bit:subreg_lh32
3175 0, // ADDR64Bit:subreg_ll32
3176 },
3177 { // VR128Bit
3178 2, // VR128Bit:subreg_h32 -> VR32Bit
3179 12, // VR128Bit:subreg_h64 -> VR64Bit
3180 0, // VR128Bit:subreg_l32
3181 0, // VR128Bit:subreg_l64
3182 0, // VR128Bit:subreg_lh32
3183 0, // VR128Bit:subreg_ll32
3184 },
3185 { // VF128Bit
3186 4, // VF128Bit:subreg_h32 -> FP32Bit
3187 15, // VF128Bit:subreg_h64 -> FP64Bit
3188 0, // VF128Bit:subreg_l32
3189 0, // VF128Bit:subreg_l64
3190 0, // VF128Bit:subreg_lh32
3191 0, // VF128Bit:subreg_ll32
3192 },
3193 { // FP128Bit
3194 4, // FP128Bit:subreg_h32 -> FP32Bit
3195 15, // FP128Bit:subreg_h64 -> FP64Bit
3196 0, // FP128Bit:subreg_l32
3197 15, // FP128Bit:subreg_l64 -> FP64Bit
3198 4, // FP128Bit:subreg_lh32 -> FP32Bit
3199 0, // FP128Bit:subreg_ll32
3200 },
3201 { // GR128Bit
3202 6, // GR128Bit:subreg_h32 -> GRH32Bit
3203 16, // GR128Bit:subreg_h64 -> GR64Bit
3204 5, // GR128Bit:subreg_l32 -> GR32Bit
3205 17, // GR128Bit:subreg_l64 -> ADDR64Bit
3206 6, // GR128Bit:subreg_lh32 -> GRH32Bit
3207 7, // GR128Bit:subreg_ll32 -> ADDR32Bit
3208 },
3209 { // ADDR128Bit
3210 6, // ADDR128Bit:subreg_h32 -> GRH32Bit
3211 17, // ADDR128Bit:subreg_h64 -> ADDR64Bit
3212 7, // ADDR128Bit:subreg_l32 -> ADDR32Bit
3213 17, // ADDR128Bit:subreg_l64 -> ADDR64Bit
3214 6, // ADDR128Bit:subreg_lh32 -> GRH32Bit
3215 7, // ADDR128Bit:subreg_ll32 -> ADDR32Bit
3216 },
3217 };
3218 assert(RC && "Missing regclass");
3219 if (!Idx) return RC;
3220 --Idx;
3221 assert(Idx < 6 && "Bad subreg");
3222 unsigned TV = Table[RC->getID()][Idx];
3223 return TV ? getRegClass(TV - 1) : nullptr;
3224}
3225
3226/// Get the weight in units of pressure for this register class.
3227const RegClassWeight &SystemZGenRegisterInfo::
3228getRegClassWeight(const TargetRegisterClass *RC) const {
3229 static const RegClassWeight RCWeightTable[] = {
3230 {1, 32}, // GRX32Bit
3231 {1, 32}, // VR32Bit
3232 {0, 0}, // AR32Bit
3233 {1, 16}, // FP32Bit
3234 {1, 16}, // GR32Bit
3235 {1, 16}, // GRH32Bit
3236 {1, 15}, // ADDR32Bit
3237 {0, 0}, // CCR
3238 {0, 0}, // FPCRegs
3239 {1, 48}, // AnyRegBit
3240 {1, 16}, // AnyRegBit_with_subreg_h32_in_FP32Bit
3241 {1, 32}, // VR64Bit
3242 {1, 16}, // AnyRegBit_with_subreg_h64
3243 {0, 0}, // CR64Bit
3244 {1, 16}, // FP64Bit
3245 {2, 32}, // GR64Bit
3246 {2, 30}, // ADDR64Bit
3247 {1, 32}, // VR128Bit
3248 {1, 16}, // VF128Bit
3249 {2, 16}, // FP128Bit
3250 {4, 32}, // GR128Bit
3251 {4, 28}, // ADDR128Bit
3252 };
3253 return RCWeightTable[RC->getID()];
3254}
3255
3256/// Get the weight in units of pressure for this register unit.
3257unsigned SystemZGenRegisterInfo::
3258getRegUnitWeight(unsigned RegUnit) const {
3259 assert(RegUnit < 98 && "invalid register unit");
3260 // All register units have unit weight.
3261 return 1;
3262}
3263
3264
3265// Get the number of dimensions of register pressure.
3266unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
3267 return 5;
3268}
3269
3270// Get the name of this register unit pressure set.
3271const char *SystemZGenRegisterInfo::
3272getRegPressureSetName(unsigned Idx) const {
3273 static const char *PressureNameTable[] = {
3274 "FP32Bit",
3275 "GR32Bit",
3276 "GRH32Bit",
3277 "GRX32Bit",
3278 "VR32Bit",
3279 };
3280 return PressureNameTable[Idx];
3281}
3282
3283// Get the register unit pressure limit for this dimension.
3284// This limit must be adjusted dynamically for reserved registers.
3285unsigned SystemZGenRegisterInfo::
3286getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3287 static const uint8_t PressureLimitTable[] = {
3288 16, // 0: FP32Bit
3289 16, // 1: GR32Bit
3290 16, // 2: GRH32Bit
3291 32, // 3: GRX32Bit
3292 32, // 4: VR32Bit
3293 };
3294 return PressureLimitTable[Idx];
3295}
3296
3297/// Table of pressure sets per register class or unit.
3298static const int RCSetsTable[] = {
3299 /* 0 */ 1, 3, -1,
3300 /* 3 */ 2, 3, -1,
3301 /* 6 */ 0, 4, -1,
3302};
3303
3304/// Get the dimensions of register pressure impacted by this register class.
3305/// Returns a -1 terminated array of pressure set IDs
3306const int *SystemZGenRegisterInfo::
3307getRegClassPressureSets(const TargetRegisterClass *RC) const {
3308 static const uint8_t RCSetStartTable[] = {
3309 1,7,2,6,0,3,0,2,2,2,2,7,2,2,6,1,1,7,6,6,1,1,};
3310 return &RCSetsTable[RCSetStartTable[RC->getID()]];
3311}
3312
3313/// Get the dimensions of register pressure impacted by this register unit.
3314/// Returns a -1 terminated array of pressure set IDs
3315const int *SystemZGenRegisterInfo::
3316getRegUnitPressureSets(unsigned RegUnit) const {
3317 assert(RegUnit < 98 && "invalid register unit");
3318 static const uint8_t RUSetStartTable[] = {
3319 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,};
3320 return &RCSetsTable[RUSetStartTable[RegUnit]];
3321}
3322
3323extern const MCRegisterDesc SystemZRegDesc[];
3324extern const int16_t SystemZRegDiffLists[];
3325extern const LaneBitmask SystemZLaneMaskLists[];
3326extern const char SystemZRegStrings[];
3327extern const char SystemZRegClassStrings[];
3328extern const MCPhysReg SystemZRegUnitRoots[][2];
3329extern const uint16_t SystemZSubRegIdxLists[];
3330extern const uint16_t SystemZRegEncodingTable[];
3331// SystemZ Dwarf<->LLVM register mappings.
3332extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
3333extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
3334
3335extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
3336extern const unsigned SystemZEHFlavour0Dwarf2LSize;
3337
3338extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
3339extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
3340
3341extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
3342extern const unsigned SystemZEHFlavour0L2DwarfSize;
3343
3344SystemZGenRegisterInfo::
3345SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3346 unsigned PC, unsigned HwMode)
3347 : TargetRegisterInfo(&SystemZRegInfoDesc, RegisterClasses, RegisterClasses+22,
3348 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
3349 LaneBitmask(0xFFFFFFFFFFFFFFFC), RegClassInfos, VTLists, HwMode) {
3350 InitMCRegisterInfo(SystemZRegDesc, 195, RA, PC,
3351 SystemZMCRegisterClasses, 22,
3352 SystemZRegUnitRoots,
3353 98,
3354 SystemZRegDiffLists,
3355 SystemZLaneMaskLists,
3356 SystemZRegStrings,
3357 SystemZRegClassStrings,
3358 SystemZSubRegIdxLists,
3359 7,
3360 SystemZRegEncodingTable);
3361
3362 switch (DwarfFlavour) {
3363 default:
3364 llvm_unreachable("Unknown DWARF flavour");
3365 case 0:
3366 mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
3367 break;
3368 }
3369 switch (EHFlavour) {
3370 default:
3371 llvm_unreachable("Unknown DWARF flavour");
3372 case 0:
3373 mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
3374 break;
3375 }
3376 switch (DwarfFlavour) {
3377 default:
3378 llvm_unreachable("Unknown DWARF flavour");
3379 case 0:
3380 mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
3381 break;
3382 }
3383 switch (EHFlavour) {
3384 default:
3385 llvm_unreachable("Unknown DWARF flavour");
3386 case 0:
3387 mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
3388 break;
3389 }
3390}
3391
3392static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3393static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0007fff8, 0x07fffff8, 0xe7ffe000, 0xf7ffe7ff, 0x00000007, };
3394static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
3395static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xe7ffe7ff, 0xf7ffe7ff, 0x00000007, };
3396static const MCPhysReg CSR_SystemZ_ELF_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3397static const uint32_t CSR_SystemZ_ELF_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x07f80780, 0x07fe0000, 0xc7fe07fe, 0x00000007, };
3398static const MCPhysReg CSR_SystemZ_NoRegs_SaveList[] = { 0 };
3399static const uint32_t CSR_SystemZ_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
3400static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3401static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x07f80780, 0x07ee0000, 0x47ee07ee, 0x00000007, };
3402static const MCPhysReg CSR_SystemZ_XPLINK64_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, 0 };
3403static const uint32_t CSR_SystemZ_XPLINK64_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x07f80780, 0x07f80000, 0x87f807f8, 0x00000007, };
3404static const MCPhysReg CSR_SystemZ_XPLINK64_Vector_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, SystemZ::V23, SystemZ::V22, SystemZ::V21, SystemZ::V20, SystemZ::V19, SystemZ::V18, SystemZ::V17, SystemZ::V16, 0 };
3405static const uint32_t CSR_SystemZ_XPLINK64_Vector_RegMask[] = { 0x00000000, 0x07f80000, 0x07fff800, 0xfff80780, 0x07f80007, 0x87f807f8, 0x00000007, };
3406
3407
3408ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
3409 static const uint32_t *const Masks[] = {
3410 CSR_SystemZ_AllRegs_RegMask,
3411 CSR_SystemZ_AllRegs_Vector_RegMask,
3412 CSR_SystemZ_ELF_RegMask,
3413 CSR_SystemZ_NoRegs_RegMask,
3414 CSR_SystemZ_SwiftError_RegMask,
3415 CSR_SystemZ_XPLINK64_RegMask,
3416 CSR_SystemZ_XPLINK64_Vector_RegMask,
3417 };
3418 return ArrayRef(Masks);
3419}
3420
3421bool SystemZGenRegisterInfo::
3422isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3423 return
3424 false;
3425}
3426
3427bool SystemZGenRegisterInfo::
3428isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3429 return
3430 false;
3431}
3432
3433bool SystemZGenRegisterInfo::
3434isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3435 return
3436 false;
3437}
3438
3439bool SystemZGenRegisterInfo::
3440isConstantPhysReg(MCRegister PhysReg) const {
3441 return
3442 false;
3443}
3444
3445ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
3446 static const char *Names[] = {
3447 "CSR_SystemZ_AllRegs",
3448 "CSR_SystemZ_AllRegs_Vector",
3449 "CSR_SystemZ_ELF",
3450 "CSR_SystemZ_NoRegs",
3451 "CSR_SystemZ_SwiftError",
3452 "CSR_SystemZ_XPLINK64",
3453 "CSR_SystemZ_XPLINK64_Vector",
3454 };
3455 return ArrayRef(Names);
3456}
3457
3458const SystemZFrameLowering *
3459SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3460 return static_cast<const SystemZFrameLowering *>(
3461 MF.getSubtarget().getFrameLowering());
3462}
3463
3464} // end namespace llvm
3465
3466#endif // GET_REGINFO_TARGET_DESC
3467
3468