1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool CC_X86_32(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, CCState &State);
50static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, CCState &State);
53static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, CCState &State);
56static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
59static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
60 MVT LocVT, CCValAssign::LocInfo LocInfo,
61 ISD::ArgFlagsTy ArgFlags, CCState &State);
62static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
65static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, CCState &State);
68static bool CC_X86_64(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, CCState &State);
71static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
72 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 ISD::ArgFlagsTy ArgFlags, CCState &State);
74static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
75 MVT LocVT, CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State);
77static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
78 MVT LocVT, CCValAssign::LocInfo LocInfo,
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
80static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
82 ISD::ArgFlagsTy ArgFlags, CCState &State);
83static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
84 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 ISD::ArgFlagsTy ArgFlags, CCState &State);
86static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
87 MVT LocVT, CCValAssign::LocInfo LocInfo,
88 ISD::ArgFlagsTy ArgFlags, CCState &State);
89static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
90 MVT LocVT, CCValAssign::LocInfo LocInfo,
91 ISD::ArgFlagsTy ArgFlags, CCState &State);
92static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
93 MVT LocVT, CCValAssign::LocInfo LocInfo,
94 ISD::ArgFlagsTy ArgFlags, CCState &State);
95static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
96 MVT LocVT, CCValAssign::LocInfo LocInfo,
97 ISD::ArgFlagsTy ArgFlags, CCState &State);
98static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
99 MVT LocVT, CCValAssign::LocInfo LocInfo,
100 ISD::ArgFlagsTy ArgFlags, CCState &State);
101static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
102 MVT LocVT, CCValAssign::LocInfo LocInfo,
103 ISD::ArgFlagsTy ArgFlags, CCState &State);
104static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
105 MVT LocVT, CCValAssign::LocInfo LocInfo,
106 ISD::ArgFlagsTy ArgFlags, CCState &State);
107static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, CCState &State);
110static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
112 ISD::ArgFlagsTy ArgFlags, CCState &State);
113bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
114 MVT LocVT, CCValAssign::LocInfo LocInfo,
115 ISD::ArgFlagsTy ArgFlags, CCState &State);
116static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
117 MVT LocVT, CCValAssign::LocInfo LocInfo,
118 ISD::ArgFlagsTy ArgFlags, CCState &State);
119static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
120 MVT LocVT, CCValAssign::LocInfo LocInfo,
121 ISD::ArgFlagsTy ArgFlags, CCState &State);
122static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, CCState &State);
125static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
126 MVT LocVT, CCValAssign::LocInfo LocInfo,
127 ISD::ArgFlagsTy ArgFlags, CCState &State);
128static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
129 MVT LocVT, CCValAssign::LocInfo LocInfo,
130 ISD::ArgFlagsTy ArgFlags, CCState &State);
131static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
132 MVT LocVT, CCValAssign::LocInfo LocInfo,
133 ISD::ArgFlagsTy ArgFlags, CCState &State);
134static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
135 MVT LocVT, CCValAssign::LocInfo LocInfo,
136 ISD::ArgFlagsTy ArgFlags, CCState &State);
137static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
138 MVT LocVT, CCValAssign::LocInfo LocInfo,
139 ISD::ArgFlagsTy ArgFlags, CCState &State);
140static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
143static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
144 MVT LocVT, CCValAssign::LocInfo LocInfo,
145 ISD::ArgFlagsTy ArgFlags, CCState &State);
146static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
147 MVT LocVT, CCValAssign::LocInfo LocInfo,
148 ISD::ArgFlagsTy ArgFlags, CCState &State);
149static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
150 MVT LocVT, CCValAssign::LocInfo LocInfo,
151 ISD::ArgFlagsTy ArgFlags, CCState &State);
152static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
153 MVT LocVT, CCValAssign::LocInfo LocInfo,
154 ISD::ArgFlagsTy ArgFlags, CCState &State);
155static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, CCState &State);
158static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
159 MVT LocVT, CCValAssign::LocInfo LocInfo,
160 ISD::ArgFlagsTy ArgFlags, CCState &State);
161static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
162 MVT LocVT, CCValAssign::LocInfo LocInfo,
163 ISD::ArgFlagsTy ArgFlags, CCState &State);
164static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
165 MVT LocVT, CCValAssign::LocInfo LocInfo,
166 ISD::ArgFlagsTy ArgFlags, CCState &State);
167static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
168 MVT LocVT, CCValAssign::LocInfo LocInfo,
169 ISD::ArgFlagsTy ArgFlags, CCState &State);
170
171
172static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
173 MVT LocVT, CCValAssign::LocInfo LocInfo,
174 ISD::ArgFlagsTy ArgFlags, CCState &State) {
175
176 if (LocVT == MVT::i32) {
177 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
178 static const MCPhysReg RegList1[] = {
179 X86::ECX, X86::EDX, X86::R8D, X86::R9D
180 };
181 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
183 return false;
184 }
185 }
186 }
187
188 if (LocVT == MVT::i64) {
189 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
190 static const MCPhysReg RegList2[] = {
191 X86::RCX, X86::RDX, X86::R8, X86::R9
192 };
193 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
194 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
195 return false;
196 }
197 }
198 }
199
200 if (LocVT == MVT::i32) {
201 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
202 static const MCPhysReg RegList3[] = {
203 X86::EDI, X86::ESI, X86::EDX, X86::ECX
204 };
205 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
206 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
207 return false;
208 }
209 }
210 }
211
212 if (LocVT == MVT::i64) {
213 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
214 static const MCPhysReg RegList4[] = {
215 X86::RDI, X86::RSI, X86::RDX, X86::RCX
216 };
217 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
219 return false;
220 }
221 }
222 }
223
224 if (LocVT == MVT::i32) {
225 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
226 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
227 return false;
228 }
229
230 if (LocVT == MVT::f32 ||
231 LocVT == MVT::f64 ||
232 LocVT == MVT::v4i32 ||
233 LocVT == MVT::v2i64 ||
234 LocVT == MVT::v4f32 ||
235 LocVT == MVT::v2f64) {
236 static const MCPhysReg RegList6[] = {
237 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
238 };
239 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
240 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
241 return false;
242 }
243 }
244
245 if (LocVT == MVT::v8f32 ||
246 LocVT == MVT::v4f64 ||
247 LocVT == MVT::v8i32 ||
248 LocVT == MVT::v4i64) {
249 static const MCPhysReg RegList7[] = {
250 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
251 };
252 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
253 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
254 return false;
255 }
256 }
257
258 if (LocVT == MVT::v16f32 ||
259 LocVT == MVT::v8f64 ||
260 LocVT == MVT::v16i32 ||
261 LocVT == MVT::v8i64) {
262 static const MCPhysReg RegList8[] = {
263 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
264 };
265 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
266 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
267 return false;
268 }
269 }
270
271 if (LocVT == MVT::v16i1 ||
272 LocVT == MVT::v8i1) {
273 if (unsigned Reg = State.AllocateReg(Reg: X86::K1)) {
274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
275 return false;
276 }
277 }
278
279 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
280 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
281 return false;
282 }
283
284 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
285 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
286 return false;
287 }
288
289 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
290 return false;
291
292 return true; // CC didn't match.
293}
294
295
296bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
297 MVT LocVT, CCValAssign::LocInfo LocInfo,
298 ISD::ArgFlagsTy ArgFlags, CCState &State) {
299
300 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
301 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
302 return false;
303 }
304
305 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
306 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
307 return false;
308 }
309
310 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
311 return false;
312
313 return true; // CC didn't match.
314}
315
316
317static bool CC_X86_32(unsigned ValNo, MVT ValVT,
318 MVT LocVT, CCValAssign::LocInfo LocInfo,
319 ISD::ArgFlagsTy ArgFlags, CCState &State) {
320
321 if (State.getCallingConv() == CallingConv::X86_INTR) {
322 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
323 return false;
324 }
325
326 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
327 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
328 return false;
329 }
330
331 if (State.getCallingConv() == CallingConv::X86_FastCall) {
332 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
333 return false;
334 }
335
336 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
337 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
338 return false;
339 }
340
341 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
342 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
343 return false;
344 }
345
346 if (State.getCallingConv() == CallingConv::CFGuard_Check) {
347 if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
348 return false;
349 }
350
351 if (State.getCallingConv() == CallingConv::Fast) {
352 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
353 return false;
354 }
355
356 if (State.getCallingConv() == CallingConv::Tail) {
357 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
358 return false;
359 }
360
361 if (State.getCallingConv() == CallingConv::GHC) {
362 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
363 return false;
364 }
365
366 if (State.getCallingConv() == CallingConv::HiPE) {
367 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
368 return false;
369 }
370
371 if (State.getCallingConv() == CallingConv::X86_RegCall) {
372 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin32()) {
373 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
374 if (!CC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
375 return false;
376 }
377 }
378 }
379
380 if (State.getCallingConv() == CallingConv::X86_RegCall) {
381 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
382 return false;
383 }
384
385 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
386 return false;
387
388 return true; // CC didn't match.
389}
390
391
392static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
393 MVT LocVT, CCValAssign::LocInfo LocInfo,
394 ISD::ArgFlagsTy ArgFlags, CCState &State) {
395
396 if (LocVT == MVT::i1 ||
397 LocVT == MVT::i8 ||
398 LocVT == MVT::i16 ||
399 LocVT == MVT::v1i1) {
400 LocVT = MVT::i32;
401 if (ArgFlags.isSExt())
402 LocInfo = CCValAssign::SExt;
403 else if (ArgFlags.isZExt())
404 LocInfo = CCValAssign::ZExt;
405 else
406 LocInfo = CCValAssign::AExt;
407 }
408
409 if (ArgFlags.isNest()) {
410 if (unsigned Reg = State.AllocateReg(Reg: X86::ECX)) {
411 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
412 return false;
413 }
414 }
415
416 if (State.getCallingConv() == CallingConv::SwiftTail) {
417 if (ArgFlags.isSwiftSelf()) {
418 if (LocVT == MVT::i32) {
419 if (unsigned Reg = State.AllocateReg(Reg: X86::ECX)) {
420 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
421 return false;
422 }
423 }
424 }
425 }
426
427 if (!State.isVarArg()) {
428 if (ArgFlags.isInReg()) {
429 if (LocVT == MVT::i32) {
430 static const MCPhysReg RegList1[] = {
431 X86::EAX, X86::EDX, X86::ECX
432 };
433 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
434 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
435 return false;
436 }
437 }
438 }
439 }
440
441 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
442 return false;
443
444 return true; // CC didn't match.
445}
446
447
448static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
449 MVT LocVT, CCValAssign::LocInfo LocInfo,
450 ISD::ArgFlagsTy ArgFlags, CCState &State) {
451
452 if (ArgFlags.isByVal()) {
453 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
454 return false;
455 }
456
457 if (ArgFlags.isPreallocated()) {
458 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
459 return false;
460 }
461
462 if (!State.isVarArg()) {
463 if (ArgFlags.isInReg()) {
464 if (LocVT == MVT::f32 ||
465 LocVT == MVT::f64) {
466 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
467 static const MCPhysReg RegList1[] = {
468 X86::XMM0, X86::XMM1, X86::XMM2
469 };
470 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
471 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
472 return false;
473 }
474 }
475 }
476 }
477 }
478
479 if (!State.isVarArg()) {
480 if (ArgFlags.isInReg()) {
481 if (LocVT == MVT::f16) {
482 static const MCPhysReg RegList2[] = {
483 X86::XMM0, X86::XMM1, X86::XMM2
484 };
485 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
486 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
487 return false;
488 }
489 }
490 }
491 }
492
493 if (!State.isVarArg()) {
494 if (LocVT == MVT::x86mmx) {
495 static const MCPhysReg RegList3[] = {
496 X86::MM0, X86::MM1, X86::MM2
497 };
498 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
499 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
500 return false;
501 }
502 }
503 }
504
505 if (LocVT == MVT::f16) {
506 int64_t Offset4 = State.AllocateStack(Size: 4, Alignment: Align(4));
507 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
508 return false;
509 }
510
511 if (LocVT == MVT::i32 ||
512 LocVT == MVT::f32) {
513 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
514 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
515 return false;
516 }
517
518 if (LocVT == MVT::f64) {
519 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(4));
520 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
521 return false;
522 }
523
524 if (LocVT == MVT::f80) {
525 int64_t Offset7 = State.AllocateStack(
526 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
527 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
528 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
529 return false;
530 }
531
532 if (LocVT == MVT::v2i1) {
533 LocVT = MVT::v2i64;
534 if (ArgFlags.isSExt())
535 LocInfo = CCValAssign::SExt;
536 else if (ArgFlags.isZExt())
537 LocInfo = CCValAssign::ZExt;
538 else
539 LocInfo = CCValAssign::AExt;
540 }
541
542 if (LocVT == MVT::v4i1) {
543 LocVT = MVT::v4i32;
544 if (ArgFlags.isSExt())
545 LocInfo = CCValAssign::SExt;
546 else if (ArgFlags.isZExt())
547 LocInfo = CCValAssign::ZExt;
548 else
549 LocInfo = CCValAssign::AExt;
550 }
551
552 if (LocVT == MVT::v8i1) {
553 LocVT = MVT::v8i16;
554 if (ArgFlags.isSExt())
555 LocInfo = CCValAssign::SExt;
556 else if (ArgFlags.isZExt())
557 LocInfo = CCValAssign::ZExt;
558 else
559 LocInfo = CCValAssign::AExt;
560 }
561
562 if (LocVT == MVT::v16i1) {
563 LocVT = MVT::v16i8;
564 if (ArgFlags.isSExt())
565 LocInfo = CCValAssign::SExt;
566 else if (ArgFlags.isZExt())
567 LocInfo = CCValAssign::ZExt;
568 else
569 LocInfo = CCValAssign::AExt;
570 }
571
572 if (LocVT == MVT::v32i1) {
573 LocVT = MVT::v32i8;
574 if (ArgFlags.isSExt())
575 LocInfo = CCValAssign::SExt;
576 else if (ArgFlags.isZExt())
577 LocInfo = CCValAssign::ZExt;
578 else
579 LocInfo = CCValAssign::AExt;
580 }
581
582 if (LocVT == MVT::v64i1) {
583 LocVT = MVT::v64i8;
584 if (ArgFlags.isSExt())
585 LocInfo = CCValAssign::SExt;
586 else if (ArgFlags.isZExt())
587 LocInfo = CCValAssign::ZExt;
588 else
589 LocInfo = CCValAssign::AExt;
590 }
591
592 if (LocVT == MVT::x86mmx) {
593 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
594 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
595 return false;
596 }
597
598 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
599 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
600 return false;
601 }
602
603 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
604 return false;
605
606 return true; // CC didn't match.
607}
608
609
610static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
611 MVT LocVT, CCValAssign::LocInfo LocInfo,
612 ISD::ArgFlagsTy ArgFlags, CCState &State) {
613
614 if (ArgFlags.isByVal()) {
615 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
616 return false;
617 }
618
619 if (LocVT == MVT::i1 ||
620 LocVT == MVT::i8 ||
621 LocVT == MVT::i16 ||
622 LocVT == MVT::v1i1) {
623 LocVT = MVT::i32;
624 if (ArgFlags.isSExt())
625 LocInfo = CCValAssign::SExt;
626 else if (ArgFlags.isZExt())
627 LocInfo = CCValAssign::ZExt;
628 else
629 LocInfo = CCValAssign::AExt;
630 }
631
632 if (ArgFlags.isNest()) {
633 if (unsigned Reg = State.AllocateReg(Reg: X86::EAX)) {
634 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
635 return false;
636 }
637 }
638
639 if (LocVT == MVT::i32) {
640 static const MCPhysReg RegList1[] = {
641 X86::ECX, X86::EDX
642 };
643 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
644 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
645 return false;
646 }
647 }
648
649 if (!State.isVarArg()) {
650 if (LocVT == MVT::f32 ||
651 LocVT == MVT::f64) {
652 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
653 static const MCPhysReg RegList2[] = {
654 X86::XMM0, X86::XMM1, X86::XMM2
655 };
656 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
657 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
658 return false;
659 }
660 }
661 }
662 }
663
664 if (LocVT == MVT::f64) {
665 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
666 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
667 return false;
668 }
669
670 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
671 return false;
672
673 return true; // CC didn't match.
674}
675
676
677static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
678 MVT LocVT, CCValAssign::LocInfo LocInfo,
679 ISD::ArgFlagsTy ArgFlags, CCState &State) {
680
681 if (LocVT == MVT::i1) {
682 LocVT = MVT::i8;
683 if (ArgFlags.isSExt())
684 LocInfo = CCValAssign::SExt;
685 else if (ArgFlags.isZExt())
686 LocInfo = CCValAssign::ZExt;
687 else
688 LocInfo = CCValAssign::AExt;
689 }
690
691 if (ArgFlags.isNest()) {
692 if (unsigned Reg = State.AllocateReg(Reg: X86::EAX)) {
693 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
694 return false;
695 }
696 }
697
698 if (ArgFlags.isInReg()) {
699 if (LocVT == MVT::i8) {
700 static const MCPhysReg RegList1[] = {
701 X86::CL, X86::DL
702 };
703 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
704 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
705 return false;
706 }
707 }
708 }
709
710 if (ArgFlags.isInReg()) {
711 if (LocVT == MVT::i16) {
712 static const MCPhysReg RegList2[] = {
713 X86::CX, X86::DX
714 };
715 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
716 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
717 return false;
718 }
719 }
720 }
721
722 if (ArgFlags.isInReg()) {
723 if (LocVT == MVT::i32) {
724 static const MCPhysReg RegList3[] = {
725 X86::ECX, X86::EDX
726 };
727 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
728 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
729 return false;
730 }
731 }
732 }
733
734 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
735 return false;
736
737 return true; // CC didn't match.
738}
739
740
741static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
742 MVT LocVT, CCValAssign::LocInfo LocInfo,
743 ISD::ArgFlagsTy ArgFlags, CCState &State) {
744
745 if (LocVT == MVT::i8 ||
746 LocVT == MVT::i16) {
747 LocVT = MVT::i32;
748 if (ArgFlags.isSExt())
749 LocInfo = CCValAssign::SExt;
750 else if (ArgFlags.isZExt())
751 LocInfo = CCValAssign::ZExt;
752 else
753 LocInfo = CCValAssign::AExt;
754 }
755
756 if (LocVT == MVT::i32) {
757 static const MCPhysReg RegList1[] = {
758 X86::EBX, X86::EBP, X86::EDI, X86::ESI
759 };
760 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
761 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
762 return false;
763 }
764 }
765
766 return true; // CC didn't match.
767}
768
769
770static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
771 MVT LocVT, CCValAssign::LocInfo LocInfo,
772 ISD::ArgFlagsTy ArgFlags, CCState &State) {
773
774 if (LocVT == MVT::i8 ||
775 LocVT == MVT::i16) {
776 LocVT = MVT::i32;
777 if (ArgFlags.isSExt())
778 LocInfo = CCValAssign::SExt;
779 else if (ArgFlags.isZExt())
780 LocInfo = CCValAssign::ZExt;
781 else
782 LocInfo = CCValAssign::AExt;
783 }
784
785 if (LocVT == MVT::i32) {
786 static const MCPhysReg RegList1[] = {
787 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
788 };
789 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
790 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
791 return false;
792 }
793 }
794
795 if (LocVT == MVT::i32 ||
796 LocVT == MVT::f32) {
797 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
798 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
799 return false;
800 }
801
802 return true; // CC didn't match.
803}
804
805
806static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
807 MVT LocVT, CCValAssign::LocInfo LocInfo,
808 ISD::ArgFlagsTy ArgFlags, CCState &State) {
809
810 if (ArgFlags.isByVal()) {
811 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
812 return false;
813 }
814
815 if (LocVT == MVT::i1 ||
816 LocVT == MVT::i8 ||
817 LocVT == MVT::i16 ||
818 LocVT == MVT::v1i1) {
819 LocVT = MVT::i32;
820 if (ArgFlags.isSExt())
821 LocInfo = CCValAssign::SExt;
822 else if (ArgFlags.isZExt())
823 LocInfo = CCValAssign::ZExt;
824 else
825 LocInfo = CCValAssign::AExt;
826 }
827
828 if (!State.isVarArg()) {
829 if (LocVT == MVT::i32) {
830 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
831 return false;
832 }
833 }
834
835 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
836 return false;
837
838 return true; // CC didn't match.
839}
840
841
842static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
843 MVT LocVT, CCValAssign::LocInfo LocInfo,
844 ISD::ArgFlagsTy ArgFlags, CCState &State) {
845
846 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
847 if (ArgFlags.isByVal()) {
848 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
849 return false;
850 }
851 }
852
853 if (ArgFlags.isByVal()) {
854 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
855 return false;
856 }
857
858 if (LocVT == MVT::i1 ||
859 LocVT == MVT::i8 ||
860 LocVT == MVT::i16 ||
861 LocVT == MVT::v1i1) {
862 LocVT = MVT::i32;
863 if (ArgFlags.isSExt())
864 LocInfo = CCValAssign::SExt;
865 else if (ArgFlags.isZExt())
866 LocInfo = CCValAssign::ZExt;
867 else
868 LocInfo = CCValAssign::AExt;
869 }
870
871 if (LocVT == MVT::v8i1 ||
872 LocVT == MVT::v16i1 ||
873 LocVT == MVT::v32i1) {
874 LocVT = MVT::i32;
875 if (ArgFlags.isSExt())
876 LocInfo = CCValAssign::SExt;
877 else if (ArgFlags.isZExt())
878 LocInfo = CCValAssign::ZExt;
879 else
880 LocInfo = CCValAssign::AExt;
881 }
882
883 if (LocVT == MVT::i32) {
884 static const MCPhysReg RegList1[] = {
885 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
886 };
887 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
888 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
889 return false;
890 }
891 }
892
893 if (LocVT == MVT::i64) {
894 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
895 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
896 return false;
897 }
898 }
899
900 if (LocVT == MVT::v64i1) {
901 LocVT = MVT::i64;
902 if (ArgFlags.isSExt())
903 LocInfo = CCValAssign::SExt;
904 else if (ArgFlags.isZExt())
905 LocInfo = CCValAssign::ZExt;
906 else
907 LocInfo = CCValAssign::AExt;
908 }
909
910 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
911 if (LocVT == MVT::i64) {
912 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
913 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
914 return false;
915 }
916 }
917 }
918
919 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
920 if (LocVT == MVT::i64) {
921 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
922 return false;
923 }
924 }
925
926 if (LocVT == MVT::f32 ||
927 LocVT == MVT::f64 ||
928 LocVT == MVT::f128) {
929 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
930 static const MCPhysReg RegList2[] = {
931 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
932 };
933 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
934 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
935 return false;
936 }
937 }
938 }
939
940 if (LocVT == MVT::f80) {
941 if (unsigned Reg = State.AllocateReg(Reg: X86::FP0)) {
942 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
943 return false;
944 }
945 }
946
947 if (LocVT == MVT::v16i8 ||
948 LocVT == MVT::v8i16 ||
949 LocVT == MVT::v4i32 ||
950 LocVT == MVT::v2i64 ||
951 LocVT == MVT::v4f32 ||
952 LocVT == MVT::v2f64) {
953 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
954 static const MCPhysReg RegList3[] = {
955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
956 };
957 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
958 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
959 return false;
960 }
961 }
962 }
963
964 if (LocVT == MVT::v32i8 ||
965 LocVT == MVT::v16i16 ||
966 LocVT == MVT::v8i32 ||
967 LocVT == MVT::v4i64 ||
968 LocVT == MVT::v8f32 ||
969 LocVT == MVT::v4f64) {
970 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
971 static const MCPhysReg RegList4[] = {
972 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
973 };
974 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
975 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
976 return false;
977 }
978 }
979 }
980
981 if (LocVT == MVT::v64i8 ||
982 LocVT == MVT::v32i16 ||
983 LocVT == MVT::v16i32 ||
984 LocVT == MVT::v8i64 ||
985 LocVT == MVT::v16f32 ||
986 LocVT == MVT::v8f64) {
987 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
988 static const MCPhysReg RegList5[] = {
989 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
990 };
991 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
992 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
993 return false;
994 }
995 }
996 }
997
998 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
999 if (LocVT == MVT::i32 ||
1000 LocVT == MVT::i64 ||
1001 LocVT == MVT::f32 ||
1002 LocVT == MVT::f64) {
1003 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1004 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1005 return false;
1006 }
1007 }
1008
1009 if (LocVT == MVT::i32 ||
1010 LocVT == MVT::f32) {
1011 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1012 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1013 return false;
1014 }
1015
1016 if (LocVT == MVT::i64 ||
1017 LocVT == MVT::f64) {
1018 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1019 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1020 return false;
1021 }
1022
1023 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1024 if (LocVT == MVT::x86mmx) {
1025 int64_t Offset9 = State.AllocateStack(Size: 8, Alignment: Align(8));
1026 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1027 return false;
1028 }
1029 }
1030
1031 if (LocVT == MVT::x86mmx) {
1032 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
1033 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1034 return false;
1035 }
1036
1037 if (LocVT == MVT::f80 ||
1038 LocVT == MVT::f128) {
1039 int64_t Offset11 = State.AllocateStack(
1040 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1041 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1042 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1043 return false;
1044 }
1045
1046 if (LocVT == MVT::v16i8 ||
1047 LocVT == MVT::v8i16 ||
1048 LocVT == MVT::v4i32 ||
1049 LocVT == MVT::v2i64 ||
1050 LocVT == MVT::v4f32 ||
1051 LocVT == MVT::v2f64) {
1052 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
1053 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1054 return false;
1055 }
1056
1057 if (LocVT == MVT::v32i8 ||
1058 LocVT == MVT::v16i16 ||
1059 LocVT == MVT::v8i32 ||
1060 LocVT == MVT::v4i64 ||
1061 LocVT == MVT::v8f32 ||
1062 LocVT == MVT::v4f64) {
1063 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
1064 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
1065 return false;
1066 }
1067
1068 if (LocVT == MVT::v64i8 ||
1069 LocVT == MVT::v32i16 ||
1070 LocVT == MVT::v16i32 ||
1071 LocVT == MVT::v8i64 ||
1072 LocVT == MVT::v16f32 ||
1073 LocVT == MVT::v8f64) {
1074 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
1075 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1076 return false;
1077 }
1078
1079 return true; // CC didn't match.
1080}
1081
1082
1083static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
1084 MVT LocVT, CCValAssign::LocInfo LocInfo,
1085 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1086
1087 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1088 if (ArgFlags.isByVal()) {
1089 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1090 return false;
1091 }
1092 }
1093
1094 if (ArgFlags.isByVal()) {
1095 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
1096 return false;
1097 }
1098
1099 if (LocVT == MVT::i1 ||
1100 LocVT == MVT::i8 ||
1101 LocVT == MVT::i16 ||
1102 LocVT == MVT::v1i1) {
1103 LocVT = MVT::i32;
1104 if (ArgFlags.isSExt())
1105 LocInfo = CCValAssign::SExt;
1106 else if (ArgFlags.isZExt())
1107 LocInfo = CCValAssign::ZExt;
1108 else
1109 LocInfo = CCValAssign::AExt;
1110 }
1111
1112 if (LocVT == MVT::v8i1 ||
1113 LocVT == MVT::v16i1 ||
1114 LocVT == MVT::v32i1) {
1115 LocVT = MVT::i32;
1116 if (ArgFlags.isSExt())
1117 LocInfo = CCValAssign::SExt;
1118 else if (ArgFlags.isZExt())
1119 LocInfo = CCValAssign::ZExt;
1120 else
1121 LocInfo = CCValAssign::AExt;
1122 }
1123
1124 if (LocVT == MVT::i32) {
1125 static const MCPhysReg RegList1[] = {
1126 X86::ECX, X86::EDX, X86::EDI, X86::ESI
1127 };
1128 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1129 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1130 return false;
1131 }
1132 }
1133
1134 if (LocVT == MVT::i64) {
1135 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
1136 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1137 return false;
1138 }
1139 }
1140
1141 if (LocVT == MVT::v64i1) {
1142 LocVT = MVT::i64;
1143 if (ArgFlags.isSExt())
1144 LocInfo = CCValAssign::SExt;
1145 else if (ArgFlags.isZExt())
1146 LocInfo = CCValAssign::ZExt;
1147 else
1148 LocInfo = CCValAssign::AExt;
1149 }
1150
1151 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1152 if (LocVT == MVT::i64) {
1153 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
1154 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1155 return false;
1156 }
1157 }
1158 }
1159
1160 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
1161 if (LocVT == MVT::i64) {
1162 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1163 return false;
1164 }
1165 }
1166
1167 if (LocVT == MVT::f32 ||
1168 LocVT == MVT::f64 ||
1169 LocVT == MVT::f128) {
1170 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1171 static const MCPhysReg RegList2[] = {
1172 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1173 };
1174 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1175 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1176 return false;
1177 }
1178 }
1179 }
1180
1181 if (LocVT == MVT::f80) {
1182 if (unsigned Reg = State.AllocateReg(Reg: X86::FP0)) {
1183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1184 return false;
1185 }
1186 }
1187
1188 if (LocVT == MVT::v16i8 ||
1189 LocVT == MVT::v8i16 ||
1190 LocVT == MVT::v4i32 ||
1191 LocVT == MVT::v2i64 ||
1192 LocVT == MVT::v4f32 ||
1193 LocVT == MVT::v2f64) {
1194 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1195 static const MCPhysReg RegList3[] = {
1196 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1197 };
1198 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
1199 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1200 return false;
1201 }
1202 }
1203 }
1204
1205 if (LocVT == MVT::v32i8 ||
1206 LocVT == MVT::v16i16 ||
1207 LocVT == MVT::v8i32 ||
1208 LocVT == MVT::v4i64 ||
1209 LocVT == MVT::v8f32 ||
1210 LocVT == MVT::v4f64) {
1211 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1212 static const MCPhysReg RegList4[] = {
1213 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1214 };
1215 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
1216 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1217 return false;
1218 }
1219 }
1220 }
1221
1222 if (LocVT == MVT::v64i8 ||
1223 LocVT == MVT::v32i16 ||
1224 LocVT == MVT::v16i32 ||
1225 LocVT == MVT::v8i64 ||
1226 LocVT == MVT::v16f32 ||
1227 LocVT == MVT::v8f64) {
1228 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1229 static const MCPhysReg RegList5[] = {
1230 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1231 };
1232 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
1233 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1234 return false;
1235 }
1236 }
1237 }
1238
1239 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1240 if (LocVT == MVT::i32 ||
1241 LocVT == MVT::i64 ||
1242 LocVT == MVT::f32 ||
1243 LocVT == MVT::f64) {
1244 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1245 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1246 return false;
1247 }
1248 }
1249
1250 if (LocVT == MVT::i32 ||
1251 LocVT == MVT::f32) {
1252 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1253 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1254 return false;
1255 }
1256
1257 if (LocVT == MVT::i64 ||
1258 LocVT == MVT::f64) {
1259 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1260 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1261 return false;
1262 }
1263
1264 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1265 if (LocVT == MVT::x86mmx) {
1266 int64_t Offset9 = State.AllocateStack(Size: 8, Alignment: Align(8));
1267 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1268 return false;
1269 }
1270 }
1271
1272 if (LocVT == MVT::x86mmx) {
1273 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
1274 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1275 return false;
1276 }
1277
1278 if (LocVT == MVT::f80 ||
1279 LocVT == MVT::f128) {
1280 int64_t Offset11 = State.AllocateStack(
1281 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1282 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1283 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1284 return false;
1285 }
1286
1287 if (LocVT == MVT::v16i8 ||
1288 LocVT == MVT::v8i16 ||
1289 LocVT == MVT::v4i32 ||
1290 LocVT == MVT::v2i64 ||
1291 LocVT == MVT::v4f32 ||
1292 LocVT == MVT::v2f64) {
1293 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
1294 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1295 return false;
1296 }
1297
1298 if (LocVT == MVT::v32i8 ||
1299 LocVT == MVT::v16i16 ||
1300 LocVT == MVT::v8i32 ||
1301 LocVT == MVT::v4i64 ||
1302 LocVT == MVT::v8f32 ||
1303 LocVT == MVT::v4f64) {
1304 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
1305 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
1306 return false;
1307 }
1308
1309 if (LocVT == MVT::v64i8 ||
1310 LocVT == MVT::v32i16 ||
1311 LocVT == MVT::v16i32 ||
1312 LocVT == MVT::v8i64 ||
1313 LocVT == MVT::v16f32 ||
1314 LocVT == MVT::v8f64) {
1315 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
1316 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1317 return false;
1318 }
1319
1320 return true; // CC didn't match.
1321}
1322
1323
1324static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1325 MVT LocVT, CCValAssign::LocInfo LocInfo,
1326 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1327
1328 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1329 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1330 return false;
1331 }
1332
1333 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1334 return false;
1335
1336 return true; // CC didn't match.
1337}
1338
1339
1340static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1341 MVT LocVT, CCValAssign::LocInfo LocInfo,
1342 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1343
1344 if (LocVT == MVT::i32) {
1345 if (unsigned Reg = State.AllocateReg(Reg: X86::ECX)) {
1346 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1347 return false;
1348 }
1349 }
1350
1351 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1352 return false;
1353
1354 return true; // CC didn't match.
1355}
1356
1357
1358static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1359 MVT LocVT, CCValAssign::LocInfo LocInfo,
1360 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1361
1362 if (LocVT == MVT::i1 ||
1363 LocVT == MVT::i8 ||
1364 LocVT == MVT::i16 ||
1365 LocVT == MVT::v1i1) {
1366 LocVT = MVT::i32;
1367 if (ArgFlags.isSExt())
1368 LocInfo = CCValAssign::SExt;
1369 else if (ArgFlags.isZExt())
1370 LocInfo = CCValAssign::ZExt;
1371 else
1372 LocInfo = CCValAssign::AExt;
1373 }
1374
1375 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1376 return false;
1377
1378 return true; // CC didn't match.
1379}
1380
1381
1382static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1383 MVT LocVT, CCValAssign::LocInfo LocInfo,
1384 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1385
1386 if (LocVT == MVT::i1 ||
1387 LocVT == MVT::i8 ||
1388 LocVT == MVT::i16 ||
1389 LocVT == MVT::v1i1) {
1390 LocVT = MVT::i32;
1391 if (ArgFlags.isSExt())
1392 LocInfo = CCValAssign::SExt;
1393 else if (ArgFlags.isZExt())
1394 LocInfo = CCValAssign::ZExt;
1395 else
1396 LocInfo = CCValAssign::AExt;
1397 }
1398
1399 if (ArgFlags.isSRet()) {
1400 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1401 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1402 return false;
1403 }
1404
1405 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1406 return false;
1407
1408 return true; // CC didn't match.
1409}
1410
1411
1412static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1413 MVT LocVT, CCValAssign::LocInfo LocInfo,
1414 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1415
1416 if (LocVT == MVT::v16i8 ||
1417 LocVT == MVT::v8i16 ||
1418 LocVT == MVT::v4i32 ||
1419 LocVT == MVT::v2i64 ||
1420 LocVT == MVT::v8f16 ||
1421 LocVT == MVT::v4f32 ||
1422 LocVT == MVT::v2f64) {
1423 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
1424 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1425 return false;
1426 }
1427
1428 if (LocVT == MVT::v32i8 ||
1429 LocVT == MVT::v16i16 ||
1430 LocVT == MVT::v8i32 ||
1431 LocVT == MVT::v4i64 ||
1432 LocVT == MVT::v16f16 ||
1433 LocVT == MVT::v8f32 ||
1434 LocVT == MVT::v4f64) {
1435 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(32));
1436 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1437 return false;
1438 }
1439
1440 if (LocVT == MVT::v64i8 ||
1441 LocVT == MVT::v32i16 ||
1442 LocVT == MVT::v16i32 ||
1443 LocVT == MVT::v8i64 ||
1444 LocVT == MVT::v32f16 ||
1445 LocVT == MVT::v16f32 ||
1446 LocVT == MVT::v8f64) {
1447 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(64));
1448 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1449 return false;
1450 }
1451
1452 return true; // CC didn't match.
1453}
1454
1455
1456static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1457 MVT LocVT, CCValAssign::LocInfo LocInfo,
1458 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1459
1460 if (!State.isVarArg()) {
1461 if (LocVT == MVT::v16i8 ||
1462 LocVT == MVT::v8i16 ||
1463 LocVT == MVT::v4i32 ||
1464 LocVT == MVT::v2i64 ||
1465 LocVT == MVT::v8f16 ||
1466 LocVT == MVT::v4f32 ||
1467 LocVT == MVT::v2f64) {
1468 static const MCPhysReg RegList1[] = {
1469 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1470 };
1471 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1472 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1473 return false;
1474 }
1475 }
1476 }
1477
1478 if (!State.isVarArg()) {
1479 if (LocVT == MVT::v32i8 ||
1480 LocVT == MVT::v16i16 ||
1481 LocVT == MVT::v8i32 ||
1482 LocVT == MVT::v4i64 ||
1483 LocVT == MVT::v16f16 ||
1484 LocVT == MVT::v8f32 ||
1485 LocVT == MVT::v4f64) {
1486 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1487 static const MCPhysReg RegList2[] = {
1488 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1489 };
1490 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1491 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1492 return false;
1493 }
1494 }
1495 }
1496 }
1497
1498 if (!State.isVarArg()) {
1499 if (LocVT == MVT::v64i8 ||
1500 LocVT == MVT::v32i16 ||
1501 LocVT == MVT::v16i32 ||
1502 LocVT == MVT::v8i64 ||
1503 LocVT == MVT::v32f16 ||
1504 LocVT == MVT::v16f32 ||
1505 LocVT == MVT::v8f64) {
1506 static const MCPhysReg RegList3[] = {
1507 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1508 };
1509 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
1510 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1511 return false;
1512 }
1513 }
1514 }
1515
1516 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1517 return false;
1518
1519 return true; // CC didn't match.
1520}
1521
1522
1523static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1524 MVT LocVT, CCValAssign::LocInfo LocInfo,
1525 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1526
1527 if (!State.isVarArg()) {
1528 if (LocVT == MVT::v16i8 ||
1529 LocVT == MVT::v8i16 ||
1530 LocVT == MVT::v4i32 ||
1531 LocVT == MVT::v2i64 ||
1532 LocVT == MVT::v8f16 ||
1533 LocVT == MVT::v4f32 ||
1534 LocVT == MVT::v2f64) {
1535 static const MCPhysReg RegList1[] = {
1536 X86::XMM0, X86::XMM1, X86::XMM2
1537 };
1538 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1539 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1540 return false;
1541 }
1542 }
1543 }
1544
1545 if (!State.isVarArg()) {
1546 if (LocVT == MVT::v32i8 ||
1547 LocVT == MVT::v16i16 ||
1548 LocVT == MVT::v8i32 ||
1549 LocVT == MVT::v4i64 ||
1550 LocVT == MVT::v16f16 ||
1551 LocVT == MVT::v8f32 ||
1552 LocVT == MVT::v4f64) {
1553 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1554 static const MCPhysReg RegList2[] = {
1555 X86::YMM0, X86::YMM1, X86::YMM2
1556 };
1557 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1558 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1559 return false;
1560 }
1561 }
1562 }
1563 }
1564
1565 if (!State.isVarArg()) {
1566 if (LocVT == MVT::v64i8 ||
1567 LocVT == MVT::v32i16 ||
1568 LocVT == MVT::v16i32 ||
1569 LocVT == MVT::v8i64 ||
1570 LocVT == MVT::v32f16 ||
1571 LocVT == MVT::v16f32 ||
1572 LocVT == MVT::v8f64) {
1573 static const MCPhysReg RegList3[] = {
1574 X86::ZMM0, X86::ZMM1, X86::ZMM2
1575 };
1576 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
1577 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1578 return false;
1579 }
1580 }
1581 }
1582
1583 if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) {
1584 if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1585 return false;
1586 }
1587
1588 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1589 return false;
1590
1591 return true; // CC didn't match.
1592}
1593
1594
1595static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1596 MVT LocVT, CCValAssign::LocInfo LocInfo,
1597 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1598
1599 if (State.getCallingConv() == CallingConv::GHC) {
1600 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1601 return false;
1602 }
1603
1604 if (State.getCallingConv() == CallingConv::HiPE) {
1605 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1606 return false;
1607 }
1608
1609 if (State.getCallingConv() == CallingConv::AnyReg) {
1610 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1611 return false;
1612 }
1613
1614 if (State.getCallingConv() == CallingConv::Win64) {
1615 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1616 return false;
1617 }
1618
1619 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1620 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1621 return false;
1622 }
1623
1624 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1625 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1626 return false;
1627 }
1628
1629 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1630 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1631 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
1632 if (!CC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1633 return false;
1634 }
1635 }
1636 }
1637
1638 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1639 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1640 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1641 return false;
1642 }
1643 }
1644
1645 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1646 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1647 return false;
1648 }
1649
1650 if (State.getCallingConv() == CallingConv::PreserveNone) {
1651 if (!CC_X86_64_Preserve_None(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1652 return false;
1653 }
1654
1655 if (State.getCallingConv() == CallingConv::X86_INTR) {
1656 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1657 return false;
1658 }
1659
1660 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1661 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1662 return false;
1663 }
1664
1665 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1666 return false;
1667
1668 return true; // CC didn't match.
1669}
1670
1671
1672static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1673 MVT LocVT, CCValAssign::LocInfo LocInfo,
1674 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1675
1676 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1677 return false;
1678
1679 return true; // CC didn't match.
1680}
1681
1682
1683static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1684 MVT LocVT, CCValAssign::LocInfo LocInfo,
1685 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1686
1687 if (ArgFlags.isByVal()) {
1688 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1689 return false;
1690 }
1691
1692 if (LocVT == MVT::i1 ||
1693 LocVT == MVT::i8 ||
1694 LocVT == MVT::i16 ||
1695 LocVT == MVT::v1i1) {
1696 LocVT = MVT::i32;
1697 if (ArgFlags.isSExt())
1698 LocInfo = CCValAssign::SExt;
1699 else if (ArgFlags.isZExt())
1700 LocInfo = CCValAssign::ZExt;
1701 else
1702 LocInfo = CCValAssign::AExt;
1703 }
1704
1705 if (ArgFlags.isNest()) {
1706 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1707 if (unsigned Reg = State.AllocateReg(Reg: X86::R10D)) {
1708 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1709 return false;
1710 }
1711 }
1712 }
1713
1714 if (ArgFlags.isNest()) {
1715 if (unsigned Reg = State.AllocateReg(Reg: X86::R10)) {
1716 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1717 return false;
1718 }
1719 }
1720
1721 if (ArgFlags.isSwiftSelf()) {
1722 if (LocVT == MVT::i64) {
1723 if (unsigned Reg = State.AllocateReg(Reg: X86::R13)) {
1724 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1725 return false;
1726 }
1727 }
1728 }
1729
1730 if (ArgFlags.isSwiftError()) {
1731 if (LocVT == MVT::i64) {
1732 if (unsigned Reg = State.AllocateReg(Reg: X86::R12)) {
1733 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1734 return false;
1735 }
1736 }
1737 }
1738
1739 if (ArgFlags.isSwiftAsync()) {
1740 if (LocVT == MVT::i64) {
1741 if (unsigned Reg = State.AllocateReg(Reg: X86::R14)) {
1742 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1743 return false;
1744 }
1745 }
1746 }
1747
1748 if (State.getCallingConv() == CallingConv::Swift) {
1749 if (ArgFlags.isSRet()) {
1750 if (LocVT == MVT::i64) {
1751 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
1752 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1753 return false;
1754 }
1755 }
1756 }
1757 }
1758
1759 if (State.getCallingConv() == CallingConv::SwiftTail) {
1760 if (ArgFlags.isSRet()) {
1761 if (LocVT == MVT::i64) {
1762 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
1763 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1764 return false;
1765 }
1766 }
1767 }
1768 }
1769
1770 if (ArgFlags.isPointer()) {
1771 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1772 return false;
1773 }
1774
1775 if (LocVT == MVT::i32) {
1776 static const MCPhysReg RegList1[] = {
1777 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1778 };
1779 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1780 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1781 return false;
1782 }
1783 }
1784
1785 if (LocVT == MVT::i64) {
1786 if (ArgFlags.isSplit()) {
1787 static const MCPhysReg RegList2[] = {
1788 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8
1789 };
1790 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1791 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1792 return false;
1793 }
1794 }
1795 }
1796
1797 if (LocVT == MVT::i64) {
1798 if (ArgFlags.isSplit()) {
1799 static const MCPhysReg ShadowRegList3[] = {
1800 X86::R9
1801 };
1802 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList3);
1803 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
1804 return false;
1805 }
1806 }
1807
1808 if (LocVT == MVT::i64) {
1809 static const MCPhysReg RegList5[] = {
1810 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1811 };
1812 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
1813 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1814 return false;
1815 }
1816 }
1817
1818 if (LocVT == MVT::x86mmx) {
1819 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1820 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1821 LocVT = MVT::v2i64;
1822 if (ArgFlags.isSExt())
1823 LocInfo = CCValAssign::SExt;
1824 else if (ArgFlags.isZExt())
1825 LocInfo = CCValAssign::ZExt;
1826 else
1827 LocInfo = CCValAssign::AExt;
1828 }
1829 }
1830 }
1831
1832 if (LocVT == MVT::v2i1) {
1833 LocVT = MVT::v2i64;
1834 if (ArgFlags.isSExt())
1835 LocInfo = CCValAssign::SExt;
1836 else if (ArgFlags.isZExt())
1837 LocInfo = CCValAssign::ZExt;
1838 else
1839 LocInfo = CCValAssign::AExt;
1840 }
1841
1842 if (LocVT == MVT::v4i1) {
1843 LocVT = MVT::v4i32;
1844 if (ArgFlags.isSExt())
1845 LocInfo = CCValAssign::SExt;
1846 else if (ArgFlags.isZExt())
1847 LocInfo = CCValAssign::ZExt;
1848 else
1849 LocInfo = CCValAssign::AExt;
1850 }
1851
1852 if (LocVT == MVT::v8i1) {
1853 LocVT = MVT::v8i16;
1854 if (ArgFlags.isSExt())
1855 LocInfo = CCValAssign::SExt;
1856 else if (ArgFlags.isZExt())
1857 LocInfo = CCValAssign::ZExt;
1858 else
1859 LocInfo = CCValAssign::AExt;
1860 }
1861
1862 if (LocVT == MVT::v16i1) {
1863 LocVT = MVT::v16i8;
1864 if (ArgFlags.isSExt())
1865 LocInfo = CCValAssign::SExt;
1866 else if (ArgFlags.isZExt())
1867 LocInfo = CCValAssign::ZExt;
1868 else
1869 LocInfo = CCValAssign::AExt;
1870 }
1871
1872 if (LocVT == MVT::v32i1) {
1873 LocVT = MVT::v32i8;
1874 if (ArgFlags.isSExt())
1875 LocInfo = CCValAssign::SExt;
1876 else if (ArgFlags.isZExt())
1877 LocInfo = CCValAssign::ZExt;
1878 else
1879 LocInfo = CCValAssign::AExt;
1880 }
1881
1882 if (LocVT == MVT::v64i1) {
1883 LocVT = MVT::v64i8;
1884 if (ArgFlags.isSExt())
1885 LocInfo = CCValAssign::SExt;
1886 else if (ArgFlags.isZExt())
1887 LocInfo = CCValAssign::ZExt;
1888 else
1889 LocInfo = CCValAssign::AExt;
1890 }
1891
1892 if (LocVT == MVT::f16 ||
1893 LocVT == MVT::f32 ||
1894 LocVT == MVT::f64 ||
1895 LocVT == MVT::f128 ||
1896 LocVT == MVT::v16i8 ||
1897 LocVT == MVT::v8i16 ||
1898 LocVT == MVT::v4i32 ||
1899 LocVT == MVT::v2i64 ||
1900 LocVT == MVT::v8f16 ||
1901 LocVT == MVT::v4f32 ||
1902 LocVT == MVT::v2f64) {
1903 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1904 static const MCPhysReg RegList6[] = {
1905 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1906 };
1907 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
1908 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1909 return false;
1910 }
1911 }
1912 }
1913
1914 if (!State.isVarArg()) {
1915 if (LocVT == MVT::v32i8 ||
1916 LocVT == MVT::v16i16 ||
1917 LocVT == MVT::v8i32 ||
1918 LocVT == MVT::v4i64 ||
1919 LocVT == MVT::v16f16 ||
1920 LocVT == MVT::v8f32 ||
1921 LocVT == MVT::v4f64) {
1922 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1923 static const MCPhysReg RegList7[] = {
1924 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1925 };
1926 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
1927 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1928 return false;
1929 }
1930 }
1931 }
1932 }
1933
1934 if (!State.isVarArg()) {
1935 if (LocVT == MVT::v64i8 ||
1936 LocVT == MVT::v32i16 ||
1937 LocVT == MVT::v16i32 ||
1938 LocVT == MVT::v8i64 ||
1939 LocVT == MVT::v32f16 ||
1940 LocVT == MVT::v16f32 ||
1941 LocVT == MVT::v8f64) {
1942 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1943 static const MCPhysReg RegList8[] = {
1944 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1945 };
1946 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
1947 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1948 return false;
1949 }
1950 }
1951 }
1952 }
1953
1954 if (LocVT == MVT::i32 ||
1955 LocVT == MVT::i64 ||
1956 LocVT == MVT::f16 ||
1957 LocVT == MVT::f32 ||
1958 LocVT == MVT::f64) {
1959 int64_t Offset9 = State.AllocateStack(Size: 8, Alignment: Align(8));
1960 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1961 return false;
1962 }
1963
1964 if (LocVT == MVT::f80 ||
1965 LocVT == MVT::f128) {
1966 int64_t Offset10 = State.AllocateStack(
1967 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1968 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1969 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1970 return false;
1971 }
1972
1973 if (LocVT == MVT::v16i8 ||
1974 LocVT == MVT::v8i16 ||
1975 LocVT == MVT::v4i32 ||
1976 LocVT == MVT::v2i64 ||
1977 LocVT == MVT::v8f16 ||
1978 LocVT == MVT::v4f32 ||
1979 LocVT == MVT::v2f64) {
1980 int64_t Offset11 = State.AllocateStack(Size: 16, Alignment: Align(16));
1981 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1982 return false;
1983 }
1984
1985 if (LocVT == MVT::v32i8 ||
1986 LocVT == MVT::v16i16 ||
1987 LocVT == MVT::v8i32 ||
1988 LocVT == MVT::v4i64 ||
1989 LocVT == MVT::v16f16 ||
1990 LocVT == MVT::v8f32 ||
1991 LocVT == MVT::v4f64) {
1992 int64_t Offset12 = State.AllocateStack(Size: 32, Alignment: Align(32));
1993 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1994 return false;
1995 }
1996
1997 if (LocVT == MVT::v64i8 ||
1998 LocVT == MVT::v32i16 ||
1999 LocVT == MVT::v16i32 ||
2000 LocVT == MVT::v8i64 ||
2001 LocVT == MVT::v32f16 ||
2002 LocVT == MVT::v16f32 ||
2003 LocVT == MVT::v8f64) {
2004 int64_t Offset13 = State.AllocateStack(Size: 64, Alignment: Align(64));
2005 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2006 return false;
2007 }
2008
2009 return true; // CC didn't match.
2010}
2011
2012
2013static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
2014 MVT LocVT, CCValAssign::LocInfo LocInfo,
2015 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2016
2017 if (LocVT == MVT::i8 ||
2018 LocVT == MVT::i16 ||
2019 LocVT == MVT::i32) {
2020 LocVT = MVT::i64;
2021 if (ArgFlags.isSExt())
2022 LocInfo = CCValAssign::SExt;
2023 else if (ArgFlags.isZExt())
2024 LocInfo = CCValAssign::ZExt;
2025 else
2026 LocInfo = CCValAssign::AExt;
2027 }
2028
2029 if (LocVT == MVT::i64) {
2030 static const MCPhysReg RegList1[] = {
2031 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
2032 };
2033 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2034 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2035 return false;
2036 }
2037 }
2038
2039 if (LocVT == MVT::f32 ||
2040 LocVT == MVT::f64 ||
2041 LocVT == MVT::v16i8 ||
2042 LocVT == MVT::v8i16 ||
2043 LocVT == MVT::v4i32 ||
2044 LocVT == MVT::v2i64 ||
2045 LocVT == MVT::v4f32 ||
2046 LocVT == MVT::v2f64) {
2047 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2048 static const MCPhysReg RegList2[] = {
2049 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
2050 };
2051 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
2052 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2053 return false;
2054 }
2055 }
2056 }
2057
2058 if (LocVT == MVT::v32i8 ||
2059 LocVT == MVT::v16i16 ||
2060 LocVT == MVT::v8i32 ||
2061 LocVT == MVT::v4i64 ||
2062 LocVT == MVT::v8f32 ||
2063 LocVT == MVT::v4f64) {
2064 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2065 static const MCPhysReg RegList3[] = {
2066 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
2067 };
2068 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
2069 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2070 return false;
2071 }
2072 }
2073 }
2074
2075 if (LocVT == MVT::v64i8 ||
2076 LocVT == MVT::v32i16 ||
2077 LocVT == MVT::v16i32 ||
2078 LocVT == MVT::v8i64 ||
2079 LocVT == MVT::v16f32 ||
2080 LocVT == MVT::v8f64) {
2081 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2082 static const MCPhysReg RegList4[] = {
2083 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
2084 };
2085 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
2086 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2087 return false;
2088 }
2089 }
2090 }
2091
2092 return true; // CC didn't match.
2093}
2094
2095
2096static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
2097 MVT LocVT, CCValAssign::LocInfo LocInfo,
2098 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2099
2100 if (LocVT == MVT::i8 ||
2101 LocVT == MVT::i16 ||
2102 LocVT == MVT::i32) {
2103 LocVT = MVT::i64;
2104 if (ArgFlags.isSExt())
2105 LocInfo = CCValAssign::SExt;
2106 else if (ArgFlags.isZExt())
2107 LocInfo = CCValAssign::ZExt;
2108 else
2109 LocInfo = CCValAssign::AExt;
2110 }
2111
2112 if (LocVT == MVT::i64) {
2113 static const MCPhysReg RegList1[] = {
2114 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
2115 };
2116 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2117 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2118 return false;
2119 }
2120 }
2121
2122 if (LocVT == MVT::i32 ||
2123 LocVT == MVT::i64 ||
2124 LocVT == MVT::f32 ||
2125 LocVT == MVT::f64) {
2126 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
2127 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2128 return false;
2129 }
2130
2131 return true; // CC didn't match.
2132}
2133
2134
2135static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
2136 MVT LocVT, CCValAssign::LocInfo LocInfo,
2137 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2138
2139 if (LocVT == MVT::i32) {
2140 static const MCPhysReg RegList1[] = {
2141 X86::R12D, X86::R13D, X86::R14D, X86::R15D, X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D, X86::R11D, X86::EAX
2142 };
2143 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2144 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2145 return false;
2146 }
2147 }
2148
2149 if (LocVT == MVT::i64) {
2150 static const MCPhysReg RegList2[] = {
2151 X86::R12, X86::R13, X86::R14, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::R11, X86::RAX
2152 };
2153 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
2154 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2155 return false;
2156 }
2157 }
2158
2159 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2160 return false;
2161
2162 return true; // CC didn't match.
2163}
2164
2165
2166static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
2167 MVT LocVT, CCValAssign::LocInfo LocInfo,
2168 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2169
2170 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2171 if (ArgFlags.isByVal()) {
2172 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2173 return false;
2174 }
2175 }
2176
2177 if (ArgFlags.isByVal()) {
2178 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2179 return false;
2180 }
2181
2182 if (LocVT == MVT::i1 ||
2183 LocVT == MVT::i8 ||
2184 LocVT == MVT::i16 ||
2185 LocVT == MVT::v1i1) {
2186 LocVT = MVT::i32;
2187 if (ArgFlags.isSExt())
2188 LocInfo = CCValAssign::SExt;
2189 else if (ArgFlags.isZExt())
2190 LocInfo = CCValAssign::ZExt;
2191 else
2192 LocInfo = CCValAssign::AExt;
2193 }
2194
2195 if (LocVT == MVT::v8i1 ||
2196 LocVT == MVT::v16i1 ||
2197 LocVT == MVT::v32i1) {
2198 LocVT = MVT::i32;
2199 if (ArgFlags.isSExt())
2200 LocInfo = CCValAssign::SExt;
2201 else if (ArgFlags.isZExt())
2202 LocInfo = CCValAssign::ZExt;
2203 else
2204 LocInfo = CCValAssign::AExt;
2205 }
2206
2207 if (LocVT == MVT::i32) {
2208 static const MCPhysReg RegList1[] = {
2209 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
2210 };
2211 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2212 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2213 return false;
2214 }
2215 }
2216
2217 if (LocVT == MVT::i64) {
2218 static const MCPhysReg RegList2[] = {
2219 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2220 };
2221 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
2222 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2223 return false;
2224 }
2225 }
2226
2227 if (LocVT == MVT::v64i1) {
2228 LocVT = MVT::i64;
2229 if (ArgFlags.isSExt())
2230 LocInfo = CCValAssign::SExt;
2231 else if (ArgFlags.isZExt())
2232 LocInfo = CCValAssign::ZExt;
2233 else
2234 LocInfo = CCValAssign::AExt;
2235 }
2236
2237 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2238 if (LocVT == MVT::i64) {
2239 static const MCPhysReg RegList3[] = {
2240 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2241 };
2242 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
2243 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2244 return false;
2245 }
2246 }
2247 }
2248
2249 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2250 if (LocVT == MVT::i64) {
2251 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2252 return false;
2253 }
2254 }
2255
2256 if (LocVT == MVT::f32 ||
2257 LocVT == MVT::f64 ||
2258 LocVT == MVT::f128) {
2259 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2260 static const MCPhysReg RegList4[] = {
2261 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2262 };
2263 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
2264 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2265 return false;
2266 }
2267 }
2268 }
2269
2270 if (LocVT == MVT::f80) {
2271 if (unsigned Reg = State.AllocateReg(Reg: X86::FP0)) {
2272 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2273 return false;
2274 }
2275 }
2276
2277 if (LocVT == MVT::v16i8 ||
2278 LocVT == MVT::v8i16 ||
2279 LocVT == MVT::v4i32 ||
2280 LocVT == MVT::v2i64 ||
2281 LocVT == MVT::v4f32 ||
2282 LocVT == MVT::v2f64) {
2283 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2284 static const MCPhysReg RegList5[] = {
2285 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2286 };
2287 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
2288 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2289 return false;
2290 }
2291 }
2292 }
2293
2294 if (LocVT == MVT::v32i8 ||
2295 LocVT == MVT::v16i16 ||
2296 LocVT == MVT::v8i32 ||
2297 LocVT == MVT::v4i64 ||
2298 LocVT == MVT::v8f32 ||
2299 LocVT == MVT::v4f64) {
2300 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2301 static const MCPhysReg RegList6[] = {
2302 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2303 };
2304 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
2305 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2306 return false;
2307 }
2308 }
2309 }
2310
2311 if (LocVT == MVT::v64i8 ||
2312 LocVT == MVT::v32i16 ||
2313 LocVT == MVT::v16i32 ||
2314 LocVT == MVT::v8i64 ||
2315 LocVT == MVT::v16f32 ||
2316 LocVT == MVT::v8f64) {
2317 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2318 static const MCPhysReg RegList7[] = {
2319 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2320 };
2321 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
2322 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2323 return false;
2324 }
2325 }
2326 }
2327
2328 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2329 if (LocVT == MVT::i32 ||
2330 LocVT == MVT::i64 ||
2331 LocVT == MVT::f32 ||
2332 LocVT == MVT::f64) {
2333 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2334 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2335 return false;
2336 }
2337 }
2338
2339 if (LocVT == MVT::i32 ||
2340 LocVT == MVT::f32) {
2341 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2342 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2343 return false;
2344 }
2345
2346 if (LocVT == MVT::i64 ||
2347 LocVT == MVT::f64) {
2348 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2349 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2350 return false;
2351 }
2352
2353 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2354 if (LocVT == MVT::x86mmx) {
2355 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8));
2356 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2357 return false;
2358 }
2359 }
2360
2361 if (LocVT == MVT::x86mmx) {
2362 int64_t Offset12 = State.AllocateStack(Size: 8, Alignment: Align(4));
2363 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2364 return false;
2365 }
2366
2367 if (LocVT == MVT::f80 ||
2368 LocVT == MVT::f128) {
2369 int64_t Offset13 = State.AllocateStack(
2370 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2371 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2372 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2373 return false;
2374 }
2375
2376 if (LocVT == MVT::v16i8 ||
2377 LocVT == MVT::v8i16 ||
2378 LocVT == MVT::v4i32 ||
2379 LocVT == MVT::v2i64 ||
2380 LocVT == MVT::v4f32 ||
2381 LocVT == MVT::v2f64) {
2382 int64_t Offset14 = State.AllocateStack(Size: 16, Alignment: Align(16));
2383 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2384 return false;
2385 }
2386
2387 if (LocVT == MVT::v32i8 ||
2388 LocVT == MVT::v16i16 ||
2389 LocVT == MVT::v8i32 ||
2390 LocVT == MVT::v4i64 ||
2391 LocVT == MVT::v8f32 ||
2392 LocVT == MVT::v4f64) {
2393 int64_t Offset15 = State.AllocateStack(Size: 32, Alignment: Align(32));
2394 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
2395 return false;
2396 }
2397
2398 if (LocVT == MVT::v64i8 ||
2399 LocVT == MVT::v32i16 ||
2400 LocVT == MVT::v16i32 ||
2401 LocVT == MVT::v8i64 ||
2402 LocVT == MVT::v16f32 ||
2403 LocVT == MVT::v8f64) {
2404 int64_t Offset16 = State.AllocateStack(Size: 64, Alignment: Align(64));
2405 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
2406 return false;
2407 }
2408
2409 return true; // CC didn't match.
2410}
2411
2412
2413static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
2414 MVT LocVT, CCValAssign::LocInfo LocInfo,
2415 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2416
2417 if (LocVT == MVT::i32) {
2418 if (unsigned Reg = State.AllocateReg(Reg: X86::ECX)) {
2419 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2420 return false;
2421 }
2422 }
2423
2424 return true; // CC didn't match.
2425}
2426
2427
2428static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
2429 MVT LocVT, CCValAssign::LocInfo LocInfo,
2430 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2431
2432 if (LocVT == MVT::v16i8 ||
2433 LocVT == MVT::v8i16 ||
2434 LocVT == MVT::v4i32 ||
2435 LocVT == MVT::v2i64 ||
2436 LocVT == MVT::v8f16 ||
2437 LocVT == MVT::v4f32 ||
2438 LocVT == MVT::v2f64) {
2439 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(4));
2440 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
2441 return false;
2442 }
2443
2444 if (LocVT == MVT::v32i8 ||
2445 LocVT == MVT::v16i16 ||
2446 LocVT == MVT::v8i32 ||
2447 LocVT == MVT::v4i64 ||
2448 LocVT == MVT::v16f16 ||
2449 LocVT == MVT::v8f32 ||
2450 LocVT == MVT::v4f64) {
2451 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(4));
2452 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2453 return false;
2454 }
2455
2456 if (LocVT == MVT::v64i8 ||
2457 LocVT == MVT::v32i16 ||
2458 LocVT == MVT::v16i32 ||
2459 LocVT == MVT::v8i64 ||
2460 LocVT == MVT::v32f16 ||
2461 LocVT == MVT::v16f32 ||
2462 LocVT == MVT::v8f64) {
2463 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(4));
2464 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
2465 return false;
2466 }
2467
2468 return true; // CC didn't match.
2469}
2470
2471
2472static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2473 MVT LocVT, CCValAssign::LocInfo LocInfo,
2474 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2475
2476 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2477 return false;
2478
2479 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2480 return false;
2481
2482 return true; // CC didn't match.
2483}
2484
2485
2486static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2487 MVT LocVT, CCValAssign::LocInfo LocInfo,
2488 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2489
2490 if (ArgFlags.isByVal()) {
2491 LocVT = MVT::i64;
2492 LocInfo = CCValAssign::Indirect;
2493 }
2494
2495 if (LocVT == MVT::i1 ||
2496 LocVT == MVT::v1i1) {
2497 LocVT = MVT::i8;
2498 if (ArgFlags.isSExt())
2499 LocInfo = CCValAssign::SExt;
2500 else if (ArgFlags.isZExt())
2501 LocInfo = CCValAssign::ZExt;
2502 else
2503 LocInfo = CCValAssign::AExt;
2504 }
2505
2506 if (ArgFlags.isNest()) {
2507 if (unsigned Reg = State.AllocateReg(Reg: X86::R10)) {
2508 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2509 return false;
2510 }
2511 }
2512
2513 if (ArgFlags.isSwiftError()) {
2514 if (LocVT == MVT::i64) {
2515 if (unsigned Reg = State.AllocateReg(Reg: X86::R12)) {
2516 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2517 return false;
2518 }
2519 }
2520 }
2521
2522 if (ArgFlags.isSwiftSelf()) {
2523 if (LocVT == MVT::i64) {
2524 if (unsigned Reg = State.AllocateReg(Reg: X86::R13)) {
2525 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2526 return false;
2527 }
2528 }
2529 }
2530
2531 if (ArgFlags.isSwiftAsync()) {
2532 if (LocVT == MVT::i64) {
2533 if (unsigned Reg = State.AllocateReg(Reg: X86::R14)) {
2534 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2535 return false;
2536 }
2537 }
2538 }
2539
2540 if (ArgFlags.isCFGuardTarget()) {
2541 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
2542 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2543 return false;
2544 }
2545 }
2546
2547 if (LocVT == MVT::v16i8 ||
2548 LocVT == MVT::v8i16 ||
2549 LocVT == MVT::v4i32 ||
2550 LocVT == MVT::v2i64 ||
2551 LocVT == MVT::v8f16 ||
2552 LocVT == MVT::v4f32 ||
2553 LocVT == MVT::v2f64) {
2554 LocVT = MVT::i64;
2555 LocInfo = CCValAssign::Indirect;
2556 }
2557
2558 if (LocVT == MVT::v32i8 ||
2559 LocVT == MVT::v16i16 ||
2560 LocVT == MVT::v8i32 ||
2561 LocVT == MVT::v4i64 ||
2562 LocVT == MVT::v16f16 ||
2563 LocVT == MVT::v8f32 ||
2564 LocVT == MVT::v4f64) {
2565 LocVT = MVT::i64;
2566 LocInfo = CCValAssign::Indirect;
2567 }
2568
2569 if (LocVT == MVT::v64i8 ||
2570 LocVT == MVT::v32i16 ||
2571 LocVT == MVT::v16i32 ||
2572 LocVT == MVT::v32f16 ||
2573 LocVT == MVT::v16f32 ||
2574 LocVT == MVT::v8f64 ||
2575 LocVT == MVT::v8i64) {
2576 LocVT = MVT::i64;
2577 LocInfo = CCValAssign::Indirect;
2578 }
2579
2580 if (LocVT == MVT::f80) {
2581 LocVT = MVT::i64;
2582 LocInfo = CCValAssign::Indirect;
2583 }
2584
2585 if (LocVT == MVT::x86mmx) {
2586 LocVT = MVT::i64;
2587 LocInfo = CCValAssign::BCvt;
2588 }
2589
2590 if (LocVT == MVT::f32) {
2591 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2592 LocVT = MVT::i32;
2593 LocInfo = CCValAssign::BCvt;
2594 }
2595 }
2596
2597 if (LocVT == MVT::f64) {
2598 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2599 LocVT = MVT::i64;
2600 LocInfo = CCValAssign::BCvt;
2601 }
2602 }
2603
2604 if (LocVT == MVT::f16 ||
2605 LocVT == MVT::f32 ||
2606 LocVT == MVT::f64) {
2607 static const MCPhysReg RegList1[] = {
2608 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2609 };
2610 static const MCPhysReg RegList2[] = {
2611 X86::RCX, X86::RDX, X86::R8, X86::R9
2612 };
2613 if (unsigned Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
2614 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2615 return false;
2616 }
2617 }
2618
2619 if (LocVT == MVT::i8) {
2620 static const MCPhysReg RegList3[] = {
2621 X86::CL, X86::DL, X86::R8B, X86::R9B
2622 };
2623 static const MCPhysReg RegList4[] = {
2624 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2625 };
2626 if (unsigned Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
2627 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2628 return false;
2629 }
2630 }
2631
2632 if (LocVT == MVT::i16) {
2633 static const MCPhysReg RegList5[] = {
2634 X86::CX, X86::DX, X86::R8W, X86::R9W
2635 };
2636 static const MCPhysReg RegList6[] = {
2637 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2638 };
2639 if (unsigned Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
2640 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2641 return false;
2642 }
2643 }
2644
2645 if (LocVT == MVT::i32) {
2646 static const MCPhysReg RegList7[] = {
2647 X86::ECX, X86::EDX, X86::R8D, X86::R9D
2648 };
2649 static const MCPhysReg RegList8[] = {
2650 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2651 };
2652 if (unsigned Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
2653 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2654 return false;
2655 }
2656 }
2657
2658 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2659 if (ArgFlags.isSRet()) {
2660 if (LocVT == MVT::i64) {
2661 static const MCPhysReg RegList9[] = {
2662 X86::RDX, X86::R8, X86::R9
2663 };
2664 static const MCPhysReg RegList10[] = {
2665 X86::XMM1, X86::XMM2, X86::XMM3
2666 };
2667 if (unsigned Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
2668 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2669 return false;
2670 }
2671 }
2672 }
2673 }
2674
2675 if (LocVT == MVT::i64) {
2676 static const MCPhysReg RegList11[] = {
2677 X86::RCX, X86::RDX, X86::R8, X86::R9
2678 };
2679 static const MCPhysReg RegList12[] = {
2680 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2681 };
2682 if (unsigned Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
2683 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2684 return false;
2685 }
2686 }
2687
2688 if (LocVT == MVT::i8 ||
2689 LocVT == MVT::i16 ||
2690 LocVT == MVT::i32 ||
2691 LocVT == MVT::i64 ||
2692 LocVT == MVT::f16 ||
2693 LocVT == MVT::f32 ||
2694 LocVT == MVT::f64) {
2695 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
2696 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2697 return false;
2698 }
2699
2700 return true; // CC didn't match.
2701}
2702
2703
2704static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2705 MVT LocVT, CCValAssign::LocInfo LocInfo,
2706 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2707
2708 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2709 if (ArgFlags.isByVal()) {
2710 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2711 return false;
2712 }
2713 }
2714
2715 if (ArgFlags.isByVal()) {
2716 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2717 return false;
2718 }
2719
2720 if (LocVT == MVT::i1 ||
2721 LocVT == MVT::i8 ||
2722 LocVT == MVT::i16 ||
2723 LocVT == MVT::v1i1) {
2724 LocVT = MVT::i32;
2725 if (ArgFlags.isSExt())
2726 LocInfo = CCValAssign::SExt;
2727 else if (ArgFlags.isZExt())
2728 LocInfo = CCValAssign::ZExt;
2729 else
2730 LocInfo = CCValAssign::AExt;
2731 }
2732
2733 if (LocVT == MVT::v8i1 ||
2734 LocVT == MVT::v16i1 ||
2735 LocVT == MVT::v32i1) {
2736 LocVT = MVT::i32;
2737 if (ArgFlags.isSExt())
2738 LocInfo = CCValAssign::SExt;
2739 else if (ArgFlags.isZExt())
2740 LocInfo = CCValAssign::ZExt;
2741 else
2742 LocInfo = CCValAssign::AExt;
2743 }
2744
2745 if (LocVT == MVT::i32) {
2746 static const MCPhysReg RegList1[] = {
2747 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2748 };
2749 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2750 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2751 return false;
2752 }
2753 }
2754
2755 if (LocVT == MVT::i64) {
2756 static const MCPhysReg RegList2[] = {
2757 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2758 };
2759 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
2760 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2761 return false;
2762 }
2763 }
2764
2765 if (LocVT == MVT::v64i1) {
2766 LocVT = MVT::i64;
2767 if (ArgFlags.isSExt())
2768 LocInfo = CCValAssign::SExt;
2769 else if (ArgFlags.isZExt())
2770 LocInfo = CCValAssign::ZExt;
2771 else
2772 LocInfo = CCValAssign::AExt;
2773 }
2774
2775 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2776 if (LocVT == MVT::i64) {
2777 static const MCPhysReg RegList3[] = {
2778 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2779 };
2780 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
2781 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2782 return false;
2783 }
2784 }
2785 }
2786
2787 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2788 if (LocVT == MVT::i64) {
2789 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2790 return false;
2791 }
2792 }
2793
2794 if (LocVT == MVT::f32 ||
2795 LocVT == MVT::f64 ||
2796 LocVT == MVT::f128) {
2797 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2798 static const MCPhysReg RegList4[] = {
2799 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2800 };
2801 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
2802 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2803 return false;
2804 }
2805 }
2806 }
2807
2808 if (LocVT == MVT::f80) {
2809 if (unsigned Reg = State.AllocateReg(Reg: X86::FP0)) {
2810 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2811 return false;
2812 }
2813 }
2814
2815 if (LocVT == MVT::v16i8 ||
2816 LocVT == MVT::v8i16 ||
2817 LocVT == MVT::v4i32 ||
2818 LocVT == MVT::v2i64 ||
2819 LocVT == MVT::v4f32 ||
2820 LocVT == MVT::v2f64) {
2821 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2822 static const MCPhysReg RegList5[] = {
2823 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2824 };
2825 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
2826 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2827 return false;
2828 }
2829 }
2830 }
2831
2832 if (LocVT == MVT::v32i8 ||
2833 LocVT == MVT::v16i16 ||
2834 LocVT == MVT::v8i32 ||
2835 LocVT == MVT::v4i64 ||
2836 LocVT == MVT::v8f32 ||
2837 LocVT == MVT::v4f64) {
2838 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2839 static const MCPhysReg RegList6[] = {
2840 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2841 };
2842 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
2843 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2844 return false;
2845 }
2846 }
2847 }
2848
2849 if (LocVT == MVT::v64i8 ||
2850 LocVT == MVT::v32i16 ||
2851 LocVT == MVT::v16i32 ||
2852 LocVT == MVT::v8i64 ||
2853 LocVT == MVT::v16f32 ||
2854 LocVT == MVT::v8f64) {
2855 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2856 static const MCPhysReg RegList7[] = {
2857 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2858 };
2859 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
2860 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2861 return false;
2862 }
2863 }
2864 }
2865
2866 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2867 if (LocVT == MVT::i32 ||
2868 LocVT == MVT::i64 ||
2869 LocVT == MVT::f32 ||
2870 LocVT == MVT::f64) {
2871 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2872 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2873 return false;
2874 }
2875 }
2876
2877 if (LocVT == MVT::i32 ||
2878 LocVT == MVT::f32) {
2879 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2880 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2881 return false;
2882 }
2883
2884 if (LocVT == MVT::i64 ||
2885 LocVT == MVT::f64) {
2886 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2887 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2888 return false;
2889 }
2890
2891 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2892 if (LocVT == MVT::x86mmx) {
2893 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8));
2894 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2895 return false;
2896 }
2897 }
2898
2899 if (LocVT == MVT::x86mmx) {
2900 int64_t Offset12 = State.AllocateStack(Size: 8, Alignment: Align(4));
2901 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2902 return false;
2903 }
2904
2905 if (LocVT == MVT::f80 ||
2906 LocVT == MVT::f128) {
2907 int64_t Offset13 = State.AllocateStack(
2908 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2909 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2910 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2911 return false;
2912 }
2913
2914 if (LocVT == MVT::v16i8 ||
2915 LocVT == MVT::v8i16 ||
2916 LocVT == MVT::v4i32 ||
2917 LocVT == MVT::v2i64 ||
2918 LocVT == MVT::v4f32 ||
2919 LocVT == MVT::v2f64) {
2920 int64_t Offset14 = State.AllocateStack(Size: 16, Alignment: Align(16));
2921 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2922 return false;
2923 }
2924
2925 if (LocVT == MVT::v32i8 ||
2926 LocVT == MVT::v16i16 ||
2927 LocVT == MVT::v8i32 ||
2928 LocVT == MVT::v4i64 ||
2929 LocVT == MVT::v8f32 ||
2930 LocVT == MVT::v4f64) {
2931 int64_t Offset15 = State.AllocateStack(Size: 32, Alignment: Align(32));
2932 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
2933 return false;
2934 }
2935
2936 if (LocVT == MVT::v64i8 ||
2937 LocVT == MVT::v32i16 ||
2938 LocVT == MVT::v16i32 ||
2939 LocVT == MVT::v8i64 ||
2940 LocVT == MVT::v16f32 ||
2941 LocVT == MVT::v8f64) {
2942 int64_t Offset16 = State.AllocateStack(Size: 64, Alignment: Align(64));
2943 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
2944 return false;
2945 }
2946
2947 return true; // CC didn't match.
2948}
2949
2950
2951static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
2952 MVT LocVT, CCValAssign::LocInfo LocInfo,
2953 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2954
2955 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2956 if (ArgFlags.isByVal()) {
2957 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2958 return false;
2959 }
2960 }
2961
2962 if (ArgFlags.isByVal()) {
2963 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2964 return false;
2965 }
2966
2967 if (LocVT == MVT::i1 ||
2968 LocVT == MVT::i8 ||
2969 LocVT == MVT::i16 ||
2970 LocVT == MVT::v1i1) {
2971 LocVT = MVT::i32;
2972 if (ArgFlags.isSExt())
2973 LocInfo = CCValAssign::SExt;
2974 else if (ArgFlags.isZExt())
2975 LocInfo = CCValAssign::ZExt;
2976 else
2977 LocInfo = CCValAssign::AExt;
2978 }
2979
2980 if (LocVT == MVT::v8i1 ||
2981 LocVT == MVT::v16i1 ||
2982 LocVT == MVT::v32i1) {
2983 LocVT = MVT::i32;
2984 if (ArgFlags.isSExt())
2985 LocInfo = CCValAssign::SExt;
2986 else if (ArgFlags.isZExt())
2987 LocInfo = CCValAssign::ZExt;
2988 else
2989 LocInfo = CCValAssign::AExt;
2990 }
2991
2992 if (LocVT == MVT::i32) {
2993 static const MCPhysReg RegList1[] = {
2994 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2995 };
2996 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2997 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2998 return false;
2999 }
3000 }
3001
3002 if (LocVT == MVT::i64) {
3003 static const MCPhysReg RegList2[] = {
3004 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
3005 };
3006 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3007 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3008 return false;
3009 }
3010 }
3011
3012 if (LocVT == MVT::v64i1) {
3013 LocVT = MVT::i64;
3014 if (ArgFlags.isSExt())
3015 LocInfo = CCValAssign::SExt;
3016 else if (ArgFlags.isZExt())
3017 LocInfo = CCValAssign::ZExt;
3018 else
3019 LocInfo = CCValAssign::AExt;
3020 }
3021
3022 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3023 if (LocVT == MVT::i64) {
3024 static const MCPhysReg RegList3[] = {
3025 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
3026 };
3027 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3028 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3029 return false;
3030 }
3031 }
3032 }
3033
3034 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3035 if (LocVT == MVT::i64) {
3036 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3037 return false;
3038 }
3039 }
3040
3041 if (LocVT == MVT::f32 ||
3042 LocVT == MVT::f64 ||
3043 LocVT == MVT::f128) {
3044 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3045 static const MCPhysReg RegList4[] = {
3046 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3047 };
3048 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
3049 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3050 return false;
3051 }
3052 }
3053 }
3054
3055 if (LocVT == MVT::f80) {
3056 if (unsigned Reg = State.AllocateReg(Reg: X86::FP0)) {
3057 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3058 return false;
3059 }
3060 }
3061
3062 if (LocVT == MVT::v16i8 ||
3063 LocVT == MVT::v8i16 ||
3064 LocVT == MVT::v4i32 ||
3065 LocVT == MVT::v2i64 ||
3066 LocVT == MVT::v4f32 ||
3067 LocVT == MVT::v2f64) {
3068 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3069 static const MCPhysReg RegList5[] = {
3070 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3071 };
3072 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
3073 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3074 return false;
3075 }
3076 }
3077 }
3078
3079 if (LocVT == MVT::v32i8 ||
3080 LocVT == MVT::v16i16 ||
3081 LocVT == MVT::v8i32 ||
3082 LocVT == MVT::v4i64 ||
3083 LocVT == MVT::v8f32 ||
3084 LocVT == MVT::v4f64) {
3085 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3086 static const MCPhysReg RegList6[] = {
3087 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3088 };
3089 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
3090 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3091 return false;
3092 }
3093 }
3094 }
3095
3096 if (LocVT == MVT::v64i8 ||
3097 LocVT == MVT::v32i16 ||
3098 LocVT == MVT::v16i32 ||
3099 LocVT == MVT::v8i64 ||
3100 LocVT == MVT::v16f32 ||
3101 LocVT == MVT::v8f64) {
3102 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3103 static const MCPhysReg RegList7[] = {
3104 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3105 };
3106 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
3107 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3108 return false;
3109 }
3110 }
3111 }
3112
3113 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3114 if (LocVT == MVT::i32 ||
3115 LocVT == MVT::i64 ||
3116 LocVT == MVT::f32 ||
3117 LocVT == MVT::f64) {
3118 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
3119 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
3120 return false;
3121 }
3122 }
3123
3124 if (LocVT == MVT::i32 ||
3125 LocVT == MVT::f32) {
3126 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
3127 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
3128 return false;
3129 }
3130
3131 if (LocVT == MVT::i64 ||
3132 LocVT == MVT::f64) {
3133 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
3134 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
3135 return false;
3136 }
3137
3138 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3139 if (LocVT == MVT::x86mmx) {
3140 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8));
3141 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
3142 return false;
3143 }
3144 }
3145
3146 if (LocVT == MVT::x86mmx) {
3147 int64_t Offset12 = State.AllocateStack(Size: 8, Alignment: Align(4));
3148 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
3149 return false;
3150 }
3151
3152 if (LocVT == MVT::f80 ||
3153 LocVT == MVT::f128) {
3154 int64_t Offset13 = State.AllocateStack(
3155 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
3156 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
3157 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
3158 return false;
3159 }
3160
3161 if (LocVT == MVT::v16i8 ||
3162 LocVT == MVT::v8i16 ||
3163 LocVT == MVT::v4i32 ||
3164 LocVT == MVT::v2i64 ||
3165 LocVT == MVT::v4f32 ||
3166 LocVT == MVT::v2f64) {
3167 int64_t Offset14 = State.AllocateStack(Size: 16, Alignment: Align(16));
3168 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
3169 return false;
3170 }
3171
3172 if (LocVT == MVT::v32i8 ||
3173 LocVT == MVT::v16i16 ||
3174 LocVT == MVT::v8i32 ||
3175 LocVT == MVT::v4i64 ||
3176 LocVT == MVT::v8f32 ||
3177 LocVT == MVT::v4f64) {
3178 int64_t Offset15 = State.AllocateStack(Size: 32, Alignment: Align(32));
3179 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
3180 return false;
3181 }
3182
3183 if (LocVT == MVT::v64i8 ||
3184 LocVT == MVT::v32i16 ||
3185 LocVT == MVT::v16i32 ||
3186 LocVT == MVT::v8i64 ||
3187 LocVT == MVT::v16f32 ||
3188 LocVT == MVT::v8f64) {
3189 int64_t Offset16 = State.AllocateStack(Size: 64, Alignment: Align(64));
3190 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
3191 return false;
3192 }
3193
3194 return true; // CC didn't match.
3195}
3196
3197
3198static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
3199 MVT LocVT, CCValAssign::LocInfo LocInfo,
3200 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3201
3202 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3203 return false;
3204
3205 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3206 return false;
3207
3208 return true; // CC didn't match.
3209}
3210
3211
3212static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
3213 MVT LocVT, CCValAssign::LocInfo LocInfo,
3214 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3215
3216 if (LocVT == MVT::f32 ||
3217 LocVT == MVT::f64 ||
3218 LocVT == MVT::v4i32 ||
3219 LocVT == MVT::v2i64 ||
3220 LocVT == MVT::v4f32 ||
3221 LocVT == MVT::v2f64) {
3222 static const MCPhysReg RegList1[] = {
3223 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3224 };
3225 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3226 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3227 return false;
3228 }
3229 }
3230
3231 if (LocVT == MVT::v8f32 ||
3232 LocVT == MVT::v4f64 ||
3233 LocVT == MVT::v8i32 ||
3234 LocVT == MVT::v4i64) {
3235 static const MCPhysReg RegList2[] = {
3236 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3237 };
3238 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3239 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3240 return false;
3241 }
3242 }
3243
3244 if (LocVT == MVT::v16f32 ||
3245 LocVT == MVT::v8f64 ||
3246 LocVT == MVT::v16i32 ||
3247 LocVT == MVT::v8i64) {
3248 static const MCPhysReg RegList3[] = {
3249 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3250 };
3251 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3252 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3253 return false;
3254 }
3255 }
3256
3257 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3258 return false;
3259
3260 return true; // CC didn't match.
3261}
3262
3263
3264bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
3265 MVT LocVT, CCValAssign::LocInfo LocInfo,
3266 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3267
3268 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
3269 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3270 return false;
3271 }
3272
3273 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3274 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3275 return false;
3276 }
3277
3278 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3279 return false;
3280
3281 return true; // CC didn't match.
3282}
3283
3284
3285static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
3286 MVT LocVT, CCValAssign::LocInfo LocInfo,
3287 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3288
3289 if (LocVT == MVT::v1i1) {
3290 LocVT = MVT::i8;
3291 if (ArgFlags.isSExt())
3292 LocInfo = CCValAssign::SExt;
3293 else if (ArgFlags.isZExt())
3294 LocInfo = CCValAssign::ZExt;
3295 else
3296 LocInfo = CCValAssign::AExt;
3297 }
3298
3299 if (LocVT == MVT::i1) {
3300 LocVT = MVT::i8;
3301 if (ArgFlags.isSExt())
3302 LocInfo = CCValAssign::SExt;
3303 else if (ArgFlags.isZExt())
3304 LocInfo = CCValAssign::ZExt;
3305 else
3306 LocInfo = CCValAssign::AExt;
3307 }
3308
3309 if (LocVT == MVT::i8) {
3310 static const MCPhysReg RegList1[] = {
3311 X86::AL, X86::DL, X86::CL
3312 };
3313 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3314 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3315 return false;
3316 }
3317 }
3318
3319 if (LocVT == MVT::i16) {
3320 static const MCPhysReg RegList2[] = {
3321 X86::AX, X86::DX, X86::CX
3322 };
3323 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3324 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3325 return false;
3326 }
3327 }
3328
3329 if (LocVT == MVT::i32) {
3330 static const MCPhysReg RegList3[] = {
3331 X86::EAX, X86::EDX, X86::ECX
3332 };
3333 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3334 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3335 return false;
3336 }
3337 }
3338
3339 if (LocVT == MVT::i64) {
3340 static const MCPhysReg RegList4[] = {
3341 X86::RAX, X86::RDX, X86::RCX
3342 };
3343 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
3344 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3345 return false;
3346 }
3347 }
3348
3349 if (LocVT == MVT::v2i1) {
3350 LocVT = MVT::v2i64;
3351 if (ArgFlags.isSExt())
3352 LocInfo = CCValAssign::SExt;
3353 else if (ArgFlags.isZExt())
3354 LocInfo = CCValAssign::ZExt;
3355 else
3356 LocInfo = CCValAssign::AExt;
3357 }
3358
3359 if (LocVT == MVT::v4i1) {
3360 LocVT = MVT::v4i32;
3361 if (ArgFlags.isSExt())
3362 LocInfo = CCValAssign::SExt;
3363 else if (ArgFlags.isZExt())
3364 LocInfo = CCValAssign::ZExt;
3365 else
3366 LocInfo = CCValAssign::AExt;
3367 }
3368
3369 if (LocVT == MVT::v8i1) {
3370 LocVT = MVT::v8i16;
3371 if (ArgFlags.isSExt())
3372 LocInfo = CCValAssign::SExt;
3373 else if (ArgFlags.isZExt())
3374 LocInfo = CCValAssign::ZExt;
3375 else
3376 LocInfo = CCValAssign::AExt;
3377 }
3378
3379 if (LocVT == MVT::v16i1) {
3380 LocVT = MVT::v16i8;
3381 if (ArgFlags.isSExt())
3382 LocInfo = CCValAssign::SExt;
3383 else if (ArgFlags.isZExt())
3384 LocInfo = CCValAssign::ZExt;
3385 else
3386 LocInfo = CCValAssign::AExt;
3387 }
3388
3389 if (LocVT == MVT::v32i1) {
3390 LocVT = MVT::v32i8;
3391 if (ArgFlags.isSExt())
3392 LocInfo = CCValAssign::SExt;
3393 else if (ArgFlags.isZExt())
3394 LocInfo = CCValAssign::ZExt;
3395 else
3396 LocInfo = CCValAssign::AExt;
3397 }
3398
3399 if (LocVT == MVT::v64i1) {
3400 LocVT = MVT::v64i8;
3401 if (ArgFlags.isSExt())
3402 LocInfo = CCValAssign::SExt;
3403 else if (ArgFlags.isZExt())
3404 LocInfo = CCValAssign::ZExt;
3405 else
3406 LocInfo = CCValAssign::AExt;
3407 }
3408
3409 if (LocVT == MVT::v16i8 ||
3410 LocVT == MVT::v8i16 ||
3411 LocVT == MVT::v4i32 ||
3412 LocVT == MVT::v2i64 ||
3413 LocVT == MVT::v8f16 ||
3414 LocVT == MVT::v4f32 ||
3415 LocVT == MVT::v2f64) {
3416 static const MCPhysReg RegList5[] = {
3417 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3418 };
3419 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
3420 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3421 return false;
3422 }
3423 }
3424
3425 if (LocVT == MVT::v32i8 ||
3426 LocVT == MVT::v16i16 ||
3427 LocVT == MVT::v8i32 ||
3428 LocVT == MVT::v4i64 ||
3429 LocVT == MVT::v16f16 ||
3430 LocVT == MVT::v8f32 ||
3431 LocVT == MVT::v4f64) {
3432 static const MCPhysReg RegList6[] = {
3433 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3434 };
3435 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
3436 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3437 return false;
3438 }
3439 }
3440
3441 if (LocVT == MVT::v64i8 ||
3442 LocVT == MVT::v32i16 ||
3443 LocVT == MVT::v16i32 ||
3444 LocVT == MVT::v8i64 ||
3445 LocVT == MVT::v32f16 ||
3446 LocVT == MVT::v16f32 ||
3447 LocVT == MVT::v8f64) {
3448 static const MCPhysReg RegList7[] = {
3449 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3450 };
3451 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
3452 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3453 return false;
3454 }
3455 }
3456
3457 if (LocVT == MVT::x86mmx) {
3458 if (unsigned Reg = State.AllocateReg(Reg: X86::MM0)) {
3459 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3460 return false;
3461 }
3462 }
3463
3464 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3465 if (LocVT == MVT::f80) {
3466 static const MCPhysReg RegList8[] = {
3467 X86::FP0, X86::FP1
3468 };
3469 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
3470 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3471 return false;
3472 }
3473 }
3474 }
3475
3476 return true; // CC didn't match.
3477}
3478
3479
3480static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
3481 MVT LocVT, CCValAssign::LocInfo LocInfo,
3482 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3483
3484 if (State.getCallingConv() == CallingConv::Fast) {
3485 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3486 return false;
3487 }
3488
3489 if (State.getCallingConv() == CallingConv::Tail) {
3490 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3491 return false;
3492 }
3493
3494 if (State.getCallingConv() == CallingConv::HiPE) {
3495 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3496 return false;
3497 }
3498
3499 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3500 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3501 return false;
3502 }
3503
3504 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3505 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin32()) {
3506 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
3507 if (!RetCC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3508 return false;
3509 }
3510 }
3511 }
3512
3513 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3514 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3515 return false;
3516 }
3517
3518 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3519 return false;
3520
3521 return true; // CC didn't match.
3522}
3523
3524
3525static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
3526 MVT LocVT, CCValAssign::LocInfo LocInfo,
3527 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3528
3529 if (ArgFlags.isInReg()) {
3530 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3531 if (LocVT == MVT::f32 ||
3532 LocVT == MVT::f64) {
3533 static const MCPhysReg RegList1[] = {
3534 X86::XMM0, X86::XMM1, X86::XMM2
3535 };
3536 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3537 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3538 return false;
3539 }
3540 }
3541 }
3542 }
3543
3544 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasX87()) {
3545 if (LocVT == MVT::f32 ||
3546 LocVT == MVT::f64) {
3547 static const MCPhysReg RegList2[] = {
3548 X86::FP0, X86::FP1
3549 };
3550 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3551 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3552 return false;
3553 }
3554 }
3555 }
3556
3557 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasX87()) {
3558 if (LocVT == MVT::f32) {
3559 static const MCPhysReg RegList3[] = {
3560 X86::EAX, X86::EDX, X86::ECX
3561 };
3562 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3563 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3564 return false;
3565 }
3566 }
3567 }
3568
3569 if (LocVT == MVT::f16) {
3570 static const MCPhysReg RegList4[] = {
3571 X86::XMM0, X86::XMM1, X86::XMM2
3572 };
3573 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
3574 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3575 return false;
3576 }
3577 }
3578
3579 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3580 return false;
3581
3582 return true; // CC didn't match.
3583}
3584
3585
3586static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
3587 MVT LocVT, CCValAssign::LocInfo LocInfo,
3588 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3589
3590 if (LocVT == MVT::f32) {
3591 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3592 static const MCPhysReg RegList1[] = {
3593 X86::XMM0, X86::XMM1, X86::XMM2
3594 };
3595 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3596 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3597 return false;
3598 }
3599 }
3600 }
3601
3602 if (LocVT == MVT::f64) {
3603 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3604 static const MCPhysReg RegList2[] = {
3605 X86::XMM0, X86::XMM1, X86::XMM2
3606 };
3607 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3608 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3609 return false;
3610 }
3611 }
3612 }
3613
3614 if (LocVT == MVT::i8) {
3615 static const MCPhysReg RegList3[] = {
3616 X86::AL, X86::DL, X86::CL
3617 };
3618 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3619 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3620 return false;
3621 }
3622 }
3623
3624 if (LocVT == MVT::i16) {
3625 static const MCPhysReg RegList4[] = {
3626 X86::AX, X86::DX, X86::CX
3627 };
3628 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
3629 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3630 return false;
3631 }
3632 }
3633
3634 if (LocVT == MVT::i32) {
3635 static const MCPhysReg RegList5[] = {
3636 X86::EAX, X86::EDX, X86::ECX
3637 };
3638 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
3639 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3640 return false;
3641 }
3642 }
3643
3644 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3645 return false;
3646
3647 return true; // CC didn't match.
3648}
3649
3650
3651static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
3652 MVT LocVT, CCValAssign::LocInfo LocInfo,
3653 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3654
3655 if (LocVT == MVT::i8 ||
3656 LocVT == MVT::i16) {
3657 LocVT = MVT::i32;
3658 if (ArgFlags.isSExt())
3659 LocInfo = CCValAssign::SExt;
3660 else if (ArgFlags.isZExt())
3661 LocInfo = CCValAssign::ZExt;
3662 else
3663 LocInfo = CCValAssign::AExt;
3664 }
3665
3666 if (LocVT == MVT::i32) {
3667 static const MCPhysReg RegList1[] = {
3668 X86::ESI, X86::EBP, X86::EAX, X86::EDX
3669 };
3670 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3671 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3672 return false;
3673 }
3674 }
3675
3676 return true; // CC didn't match.
3677}
3678
3679
3680static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
3681 MVT LocVT, CCValAssign::LocInfo LocInfo,
3682 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3683
3684 if (LocVT == MVT::i1 ||
3685 LocVT == MVT::v1i1 ||
3686 LocVT == MVT::v8i1) {
3687 LocVT = MVT::i8;
3688 if (ArgFlags.isSExt())
3689 LocInfo = CCValAssign::SExt;
3690 else if (ArgFlags.isZExt())
3691 LocInfo = CCValAssign::ZExt;
3692 else
3693 LocInfo = CCValAssign::AExt;
3694 }
3695
3696 if (LocVT == MVT::v16i1) {
3697 LocVT = MVT::i16;
3698 if (ArgFlags.isSExt())
3699 LocInfo = CCValAssign::SExt;
3700 else if (ArgFlags.isZExt())
3701 LocInfo = CCValAssign::ZExt;
3702 else
3703 LocInfo = CCValAssign::AExt;
3704 }
3705
3706 if (LocVT == MVT::v32i1) {
3707 LocVT = MVT::i32;
3708 if (ArgFlags.isSExt())
3709 LocInfo = CCValAssign::SExt;
3710 else if (ArgFlags.isZExt())
3711 LocInfo = CCValAssign::ZExt;
3712 else
3713 LocInfo = CCValAssign::AExt;
3714 }
3715
3716 if (LocVT == MVT::i8) {
3717 static const MCPhysReg RegList1[] = {
3718 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3719 };
3720 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3721 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3722 return false;
3723 }
3724 }
3725
3726 if (LocVT == MVT::i16) {
3727 static const MCPhysReg RegList2[] = {
3728 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3729 };
3730 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3731 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3732 return false;
3733 }
3734 }
3735
3736 if (LocVT == MVT::i32) {
3737 static const MCPhysReg RegList3[] = {
3738 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3739 };
3740 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3741 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3742 return false;
3743 }
3744 }
3745
3746 if (LocVT == MVT::i64) {
3747 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
3748 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3749 return false;
3750 }
3751 }
3752
3753 if (LocVT == MVT::v64i1) {
3754 LocVT = MVT::i64;
3755 if (ArgFlags.isSExt())
3756 LocInfo = CCValAssign::SExt;
3757 else if (ArgFlags.isZExt())
3758 LocInfo = CCValAssign::ZExt;
3759 else
3760 LocInfo = CCValAssign::AExt;
3761 }
3762
3763 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3764 if (LocVT == MVT::i64) {
3765 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
3766 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3767 return false;
3768 }
3769 }
3770 }
3771
3772 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3773 if (LocVT == MVT::i64) {
3774 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3775 return false;
3776 }
3777 }
3778
3779 if (LocVT == MVT::f80) {
3780 static const MCPhysReg RegList4[] = {
3781 X86::FP0, X86::FP1
3782 };
3783 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
3784 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3785 return false;
3786 }
3787 }
3788
3789 if (LocVT == MVT::f32 ||
3790 LocVT == MVT::f64 ||
3791 LocVT == MVT::f128) {
3792 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3793 static const MCPhysReg RegList5[] = {
3794 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3795 };
3796 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
3797 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3798 return false;
3799 }
3800 }
3801 }
3802
3803 if (LocVT == MVT::v16i8 ||
3804 LocVT == MVT::v8i16 ||
3805 LocVT == MVT::v4i32 ||
3806 LocVT == MVT::v2i64 ||
3807 LocVT == MVT::v4f32 ||
3808 LocVT == MVT::v2f64) {
3809 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3810 static const MCPhysReg RegList6[] = {
3811 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3812 };
3813 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
3814 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3815 return false;
3816 }
3817 }
3818 }
3819
3820 if (LocVT == MVT::v32i8 ||
3821 LocVT == MVT::v16i16 ||
3822 LocVT == MVT::v8i32 ||
3823 LocVT == MVT::v4i64 ||
3824 LocVT == MVT::v8f32 ||
3825 LocVT == MVT::v4f64) {
3826 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3827 static const MCPhysReg RegList7[] = {
3828 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3829 };
3830 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
3831 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3832 return false;
3833 }
3834 }
3835 }
3836
3837 if (LocVT == MVT::v64i8 ||
3838 LocVT == MVT::v32i16 ||
3839 LocVT == MVT::v16i32 ||
3840 LocVT == MVT::v8i64 ||
3841 LocVT == MVT::v16f32 ||
3842 LocVT == MVT::v8f64) {
3843 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3844 static const MCPhysReg RegList8[] = {
3845 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3846 };
3847 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
3848 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3849 return false;
3850 }
3851 }
3852 }
3853
3854 return true; // CC didn't match.
3855}
3856
3857
3858static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
3859 MVT LocVT, CCValAssign::LocInfo LocInfo,
3860 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3861
3862 if (LocVT == MVT::i1 ||
3863 LocVT == MVT::v1i1 ||
3864 LocVT == MVT::v8i1) {
3865 LocVT = MVT::i8;
3866 if (ArgFlags.isSExt())
3867 LocInfo = CCValAssign::SExt;
3868 else if (ArgFlags.isZExt())
3869 LocInfo = CCValAssign::ZExt;
3870 else
3871 LocInfo = CCValAssign::AExt;
3872 }
3873
3874 if (LocVT == MVT::v16i1) {
3875 LocVT = MVT::i16;
3876 if (ArgFlags.isSExt())
3877 LocInfo = CCValAssign::SExt;
3878 else if (ArgFlags.isZExt())
3879 LocInfo = CCValAssign::ZExt;
3880 else
3881 LocInfo = CCValAssign::AExt;
3882 }
3883
3884 if (LocVT == MVT::v32i1) {
3885 LocVT = MVT::i32;
3886 if (ArgFlags.isSExt())
3887 LocInfo = CCValAssign::SExt;
3888 else if (ArgFlags.isZExt())
3889 LocInfo = CCValAssign::ZExt;
3890 else
3891 LocInfo = CCValAssign::AExt;
3892 }
3893
3894 if (LocVT == MVT::i8) {
3895 static const MCPhysReg RegList1[] = {
3896 X86::CL, X86::DL, X86::DIL, X86::SIL
3897 };
3898 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
3899 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3900 return false;
3901 }
3902 }
3903
3904 if (LocVT == MVT::i16) {
3905 static const MCPhysReg RegList2[] = {
3906 X86::CX, X86::DX, X86::DI, X86::SI
3907 };
3908 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
3909 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3910 return false;
3911 }
3912 }
3913
3914 if (LocVT == MVT::i32) {
3915 static const MCPhysReg RegList3[] = {
3916 X86::ECX, X86::EDX, X86::EDI, X86::ESI
3917 };
3918 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
3919 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3920 return false;
3921 }
3922 }
3923
3924 if (LocVT == MVT::i64) {
3925 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
3926 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3927 return false;
3928 }
3929 }
3930
3931 if (LocVT == MVT::v64i1) {
3932 LocVT = MVT::i64;
3933 if (ArgFlags.isSExt())
3934 LocInfo = CCValAssign::SExt;
3935 else if (ArgFlags.isZExt())
3936 LocInfo = CCValAssign::ZExt;
3937 else
3938 LocInfo = CCValAssign::AExt;
3939 }
3940
3941 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3942 if (LocVT == MVT::i64) {
3943 if (unsigned Reg = State.AllocateReg(Reg: X86::RAX)) {
3944 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3945 return false;
3946 }
3947 }
3948 }
3949
3950 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3951 if (LocVT == MVT::i64) {
3952 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3953 return false;
3954 }
3955 }
3956
3957 if (LocVT == MVT::f80) {
3958 static const MCPhysReg RegList4[] = {
3959 X86::FP0, X86::FP1
3960 };
3961 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
3962 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3963 return false;
3964 }
3965 }
3966
3967 if (LocVT == MVT::f32 ||
3968 LocVT == MVT::f64 ||
3969 LocVT == MVT::f128) {
3970 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3971 static const MCPhysReg RegList5[] = {
3972 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3973 };
3974 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
3975 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3976 return false;
3977 }
3978 }
3979 }
3980
3981 if (LocVT == MVT::v16i8 ||
3982 LocVT == MVT::v8i16 ||
3983 LocVT == MVT::v4i32 ||
3984 LocVT == MVT::v2i64 ||
3985 LocVT == MVT::v4f32 ||
3986 LocVT == MVT::v2f64) {
3987 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3988 static const MCPhysReg RegList6[] = {
3989 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3990 };
3991 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
3992 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
3993 return false;
3994 }
3995 }
3996 }
3997
3998 if (LocVT == MVT::v32i8 ||
3999 LocVT == MVT::v16i16 ||
4000 LocVT == MVT::v8i32 ||
4001 LocVT == MVT::v4i64 ||
4002 LocVT == MVT::v8f32 ||
4003 LocVT == MVT::v4f64) {
4004 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
4005 static const MCPhysReg RegList7[] = {
4006 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
4007 };
4008 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
4009 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4010 return false;
4011 }
4012 }
4013 }
4014
4015 if (LocVT == MVT::v64i8 ||
4016 LocVT == MVT::v32i16 ||
4017 LocVT == MVT::v16i32 ||
4018 LocVT == MVT::v8i64 ||
4019 LocVT == MVT::v16f32 ||
4020 LocVT == MVT::v8f64) {
4021 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
4022 static const MCPhysReg RegList8[] = {
4023 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
4024 };
4025 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
4026 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4027 return false;
4028 }
4029 }
4030 }
4031
4032 return true; // CC didn't match.
4033}
4034
4035
4036static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
4037 MVT LocVT, CCValAssign::LocInfo LocInfo,
4038 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4039
4040 if (LocVT == MVT::f32 ||
4041 LocVT == MVT::f64 ||
4042 LocVT == MVT::f128) {
4043 static const MCPhysReg RegList1[] = {
4044 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4045 };
4046 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4047 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4048 return false;
4049 }
4050 }
4051
4052 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4053 return false;
4054
4055 return true; // CC didn't match.
4056}
4057
4058
4059static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
4060 MVT LocVT, CCValAssign::LocInfo LocInfo,
4061 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4062
4063 if (State.getCallingConv() == CallingConv::HiPE) {
4064 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4065 return false;
4066 }
4067
4068 if (State.getCallingConv() == CallingConv::AnyReg) {
4069 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4070 return false;
4071 }
4072
4073 if (State.getCallingConv() == CallingConv::Swift) {
4074 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4075 return false;
4076 }
4077
4078 if (State.getCallingConv() == CallingConv::SwiftTail) {
4079 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4080 return false;
4081 }
4082
4083 if (State.getCallingConv() == CallingConv::Win64) {
4084 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4085 return false;
4086 }
4087
4088 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
4089 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4090 return false;
4091 }
4092
4093 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
4094 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4095 return false;
4096 }
4097
4098 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4099 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
4100 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
4101 if (!RetCC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4102 return false;
4103 }
4104 }
4105 }
4106
4107 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4108 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
4109 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4110 return false;
4111 }
4112 }
4113
4114 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4115 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4116 return false;
4117 }
4118
4119 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
4120 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4121 return false;
4122 }
4123
4124 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4125 return false;
4126
4127 return true; // CC didn't match.
4128}
4129
4130
4131static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
4132 MVT LocVT, CCValAssign::LocInfo LocInfo,
4133 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4134
4135 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4136 return false;
4137
4138 return true; // CC didn't match.
4139}
4140
4141
4142static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
4143 MVT LocVT, CCValAssign::LocInfo LocInfo,
4144 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4145
4146 if (LocVT == MVT::f16) {
4147 static const MCPhysReg RegList1[] = {
4148 X86::XMM0, X86::XMM1
4149 };
4150 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4151 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4152 return false;
4153 }
4154 }
4155
4156 if (LocVT == MVT::f32) {
4157 static const MCPhysReg RegList2[] = {
4158 X86::XMM0, X86::XMM1
4159 };
4160 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
4161 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4162 return false;
4163 }
4164 }
4165
4166 if (LocVT == MVT::f64) {
4167 static const MCPhysReg RegList3[] = {
4168 X86::XMM0, X86::XMM1
4169 };
4170 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
4171 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4172 return false;
4173 }
4174 }
4175
4176 if (LocVT == MVT::f128) {
4177 static const MCPhysReg RegList4[] = {
4178 X86::XMM0, X86::XMM1
4179 };
4180 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
4181 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4182 return false;
4183 }
4184 }
4185
4186 if (LocVT == MVT::x86mmx) {
4187 static const MCPhysReg RegList5[] = {
4188 X86::XMM0, X86::XMM1
4189 };
4190 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
4191 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4192 return false;
4193 }
4194 }
4195
4196 if (ArgFlags.isPointer()) {
4197 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4198 return false;
4199 }
4200
4201 if (ArgFlags.isSwiftError()) {
4202 if (LocVT == MVT::i64) {
4203 if (unsigned Reg = State.AllocateReg(Reg: X86::R12)) {
4204 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4205 return false;
4206 }
4207 }
4208 }
4209
4210 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4211 return false;
4212
4213 return true; // CC didn't match.
4214}
4215
4216
4217static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
4218 MVT LocVT, CCValAssign::LocInfo LocInfo,
4219 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4220
4221 if (LocVT == MVT::i8 ||
4222 LocVT == MVT::i16 ||
4223 LocVT == MVT::i32) {
4224 LocVT = MVT::i64;
4225 if (ArgFlags.isSExt())
4226 LocInfo = CCValAssign::SExt;
4227 else if (ArgFlags.isZExt())
4228 LocInfo = CCValAssign::ZExt;
4229 else
4230 LocInfo = CCValAssign::AExt;
4231 }
4232
4233 if (LocVT == MVT::i64) {
4234 static const MCPhysReg RegList1[] = {
4235 X86::R15, X86::RBP, X86::RAX, X86::RDX
4236 };
4237 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4238 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4239 return false;
4240 }
4241 }
4242
4243 return true; // CC didn't match.
4244}
4245
4246
4247static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
4248 MVT LocVT, CCValAssign::LocInfo LocInfo,
4249 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4250
4251 if (ArgFlags.isSwiftError()) {
4252 if (LocVT == MVT::i64) {
4253 if (unsigned Reg = State.AllocateReg(Reg: X86::R12)) {
4254 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4255 return false;
4256 }
4257 }
4258 }
4259
4260 if (LocVT == MVT::v1i1) {
4261 LocVT = MVT::i8;
4262 if (ArgFlags.isSExt())
4263 LocInfo = CCValAssign::SExt;
4264 else if (ArgFlags.isZExt())
4265 LocInfo = CCValAssign::ZExt;
4266 else
4267 LocInfo = CCValAssign::AExt;
4268 }
4269
4270 if (LocVT == MVT::i1) {
4271 LocVT = MVT::i8;
4272 if (ArgFlags.isSExt())
4273 LocInfo = CCValAssign::SExt;
4274 else if (ArgFlags.isZExt())
4275 LocInfo = CCValAssign::ZExt;
4276 else
4277 LocInfo = CCValAssign::AExt;
4278 }
4279
4280 if (LocVT == MVT::i8) {
4281 static const MCPhysReg RegList1[] = {
4282 X86::AL, X86::DL, X86::CL, X86::R8B
4283 };
4284 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4285 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4286 return false;
4287 }
4288 }
4289
4290 if (LocVT == MVT::i16) {
4291 static const MCPhysReg RegList2[] = {
4292 X86::AX, X86::DX, X86::CX, X86::R8W
4293 };
4294 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
4295 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4296 return false;
4297 }
4298 }
4299
4300 if (LocVT == MVT::i32) {
4301 static const MCPhysReg RegList3[] = {
4302 X86::EAX, X86::EDX, X86::ECX, X86::R8D
4303 };
4304 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
4305 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4306 return false;
4307 }
4308 }
4309
4310 if (LocVT == MVT::i64) {
4311 static const MCPhysReg RegList4[] = {
4312 X86::RAX, X86::RDX, X86::RCX, X86::R8
4313 };
4314 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
4315 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4316 return false;
4317 }
4318 }
4319
4320 if (LocVT == MVT::f32) {
4321 static const MCPhysReg RegList5[] = {
4322 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4323 };
4324 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
4325 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4326 return false;
4327 }
4328 }
4329
4330 if (LocVT == MVT::f64) {
4331 static const MCPhysReg RegList6[] = {
4332 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4333 };
4334 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
4335 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4336 return false;
4337 }
4338 }
4339
4340 if (LocVT == MVT::f128) {
4341 static const MCPhysReg RegList7[] = {
4342 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4343 };
4344 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
4345 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4346 return false;
4347 }
4348 }
4349
4350 if (LocVT == MVT::x86mmx) {
4351 static const MCPhysReg RegList8[] = {
4352 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4353 };
4354 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
4355 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4356 return false;
4357 }
4358 }
4359
4360 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4361 return false;
4362
4363 return true; // CC didn't match.
4364}
4365
4366
4367static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
4368 MVT LocVT, CCValAssign::LocInfo LocInfo,
4369 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4370
4371 if (LocVT == MVT::f32 ||
4372 LocVT == MVT::f64 ||
4373 LocVT == MVT::f128) {
4374 static const MCPhysReg RegList1[] = {
4375 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4376 };
4377 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4378 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4379 return false;
4380 }
4381 }
4382
4383 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4384 return false;
4385
4386 return true; // CC didn't match.
4387}
4388
4389
4390static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
4391 MVT LocVT, CCValAssign::LocInfo LocInfo,
4392 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4393
4394 if (LocVT == MVT::i1 ||
4395 LocVT == MVT::v1i1 ||
4396 LocVT == MVT::v8i1) {
4397 LocVT = MVT::i8;
4398 if (ArgFlags.isSExt())
4399 LocInfo = CCValAssign::SExt;
4400 else if (ArgFlags.isZExt())
4401 LocInfo = CCValAssign::ZExt;
4402 else
4403 LocInfo = CCValAssign::AExt;
4404 }
4405
4406 if (LocVT == MVT::v16i1) {
4407 LocVT = MVT::i16;
4408 if (ArgFlags.isSExt())
4409 LocInfo = CCValAssign::SExt;
4410 else if (ArgFlags.isZExt())
4411 LocInfo = CCValAssign::ZExt;
4412 else
4413 LocInfo = CCValAssign::AExt;
4414 }
4415
4416 if (LocVT == MVT::v32i1) {
4417 LocVT = MVT::i32;
4418 if (ArgFlags.isSExt())
4419 LocInfo = CCValAssign::SExt;
4420 else if (ArgFlags.isZExt())
4421 LocInfo = CCValAssign::ZExt;
4422 else
4423 LocInfo = CCValAssign::AExt;
4424 }
4425
4426 if (LocVT == MVT::i8) {
4427 static const MCPhysReg RegList1[] = {
4428 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
4429 };
4430 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4431 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4432 return false;
4433 }
4434 }
4435
4436 if (LocVT == MVT::i16) {
4437 static const MCPhysReg RegList2[] = {
4438 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
4439 };
4440 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
4441 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4442 return false;
4443 }
4444 }
4445
4446 if (LocVT == MVT::i32) {
4447 static const MCPhysReg RegList3[] = {
4448 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
4449 };
4450 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
4451 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4452 return false;
4453 }
4454 }
4455
4456 if (LocVT == MVT::i64) {
4457 static const MCPhysReg RegList4[] = {
4458 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4459 };
4460 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
4461 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4462 return false;
4463 }
4464 }
4465
4466 if (LocVT == MVT::v64i1) {
4467 LocVT = MVT::i64;
4468 if (ArgFlags.isSExt())
4469 LocInfo = CCValAssign::SExt;
4470 else if (ArgFlags.isZExt())
4471 LocInfo = CCValAssign::ZExt;
4472 else
4473 LocInfo = CCValAssign::AExt;
4474 }
4475
4476 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
4477 if (LocVT == MVT::i64) {
4478 static const MCPhysReg RegList5[] = {
4479 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4480 };
4481 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
4482 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4483 return false;
4484 }
4485 }
4486 }
4487
4488 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
4489 if (LocVT == MVT::i64) {
4490 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4491 return false;
4492 }
4493 }
4494
4495 if (LocVT == MVT::f80) {
4496 static const MCPhysReg RegList6[] = {
4497 X86::FP0, X86::FP1
4498 };
4499 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
4500 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4501 return false;
4502 }
4503 }
4504
4505 if (LocVT == MVT::f32 ||
4506 LocVT == MVT::f64 ||
4507 LocVT == MVT::f128) {
4508 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4509 static const MCPhysReg RegList7[] = {
4510 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4511 };
4512 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
4513 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4514 return false;
4515 }
4516 }
4517 }
4518
4519 if (LocVT == MVT::v16i8 ||
4520 LocVT == MVT::v8i16 ||
4521 LocVT == MVT::v4i32 ||
4522 LocVT == MVT::v2i64 ||
4523 LocVT == MVT::v4f32 ||
4524 LocVT == MVT::v2f64) {
4525 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4526 static const MCPhysReg RegList8[] = {
4527 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4528 };
4529 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
4530 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4531 return false;
4532 }
4533 }
4534 }
4535
4536 if (LocVT == MVT::v32i8 ||
4537 LocVT == MVT::v16i16 ||
4538 LocVT == MVT::v8i32 ||
4539 LocVT == MVT::v4i64 ||
4540 LocVT == MVT::v8f32 ||
4541 LocVT == MVT::v4f64) {
4542 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
4543 static const MCPhysReg RegList9[] = {
4544 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4545 };
4546 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
4547 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4548 return false;
4549 }
4550 }
4551 }
4552
4553 if (LocVT == MVT::v64i8 ||
4554 LocVT == MVT::v32i16 ||
4555 LocVT == MVT::v16i32 ||
4556 LocVT == MVT::v8i64 ||
4557 LocVT == MVT::v16f32 ||
4558 LocVT == MVT::v8f64) {
4559 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
4560 static const MCPhysReg RegList10[] = {
4561 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4562 };
4563 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
4564 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4565 return false;
4566 }
4567 }
4568 }
4569
4570 return true; // CC didn't match.
4571}
4572
4573
4574static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
4575 MVT LocVT, CCValAssign::LocInfo LocInfo,
4576 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4577
4578 if (LocVT == MVT::x86mmx) {
4579 LocVT = MVT::i64;
4580 LocInfo = CCValAssign::BCvt;
4581 }
4582
4583 if (LocVT == MVT::f32) {
4584 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4585 LocVT = MVT::i32;
4586 LocInfo = CCValAssign::BCvt;
4587 }
4588 }
4589
4590 if (LocVT == MVT::f64) {
4591 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4592 LocVT = MVT::i64;
4593 LocInfo = CCValAssign::BCvt;
4594 }
4595 }
4596
4597 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4598 return false;
4599
4600 return true; // CC didn't match.
4601}
4602
4603
4604static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
4605 MVT LocVT, CCValAssign::LocInfo LocInfo,
4606 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4607
4608 if (LocVT == MVT::i1 ||
4609 LocVT == MVT::v1i1 ||
4610 LocVT == MVT::v8i1) {
4611 LocVT = MVT::i8;
4612 if (ArgFlags.isSExt())
4613 LocInfo = CCValAssign::SExt;
4614 else if (ArgFlags.isZExt())
4615 LocInfo = CCValAssign::ZExt;
4616 else
4617 LocInfo = CCValAssign::AExt;
4618 }
4619
4620 if (LocVT == MVT::v16i1) {
4621 LocVT = MVT::i16;
4622 if (ArgFlags.isSExt())
4623 LocInfo = CCValAssign::SExt;
4624 else if (ArgFlags.isZExt())
4625 LocInfo = CCValAssign::ZExt;
4626 else
4627 LocInfo = CCValAssign::AExt;
4628 }
4629
4630 if (LocVT == MVT::v32i1) {
4631 LocVT = MVT::i32;
4632 if (ArgFlags.isSExt())
4633 LocInfo = CCValAssign::SExt;
4634 else if (ArgFlags.isZExt())
4635 LocInfo = CCValAssign::ZExt;
4636 else
4637 LocInfo = CCValAssign::AExt;
4638 }
4639
4640 if (LocVT == MVT::i8) {
4641 static const MCPhysReg RegList1[] = {
4642 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4643 };
4644 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4645 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4646 return false;
4647 }
4648 }
4649
4650 if (LocVT == MVT::i16) {
4651 static const MCPhysReg RegList2[] = {
4652 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4653 };
4654 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
4655 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4656 return false;
4657 }
4658 }
4659
4660 if (LocVT == MVT::i32) {
4661 static const MCPhysReg RegList3[] = {
4662 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4663 };
4664 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
4665 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4666 return false;
4667 }
4668 }
4669
4670 if (LocVT == MVT::i64) {
4671 static const MCPhysReg RegList4[] = {
4672 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4673 };
4674 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
4675 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4676 return false;
4677 }
4678 }
4679
4680 if (LocVT == MVT::v64i1) {
4681 LocVT = MVT::i64;
4682 if (ArgFlags.isSExt())
4683 LocInfo = CCValAssign::SExt;
4684 else if (ArgFlags.isZExt())
4685 LocInfo = CCValAssign::ZExt;
4686 else
4687 LocInfo = CCValAssign::AExt;
4688 }
4689
4690 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
4691 if (LocVT == MVT::i64) {
4692 static const MCPhysReg RegList5[] = {
4693 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4694 };
4695 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
4696 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4697 return false;
4698 }
4699 }
4700 }
4701
4702 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
4703 if (LocVT == MVT::i64) {
4704 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4705 return false;
4706 }
4707 }
4708
4709 if (LocVT == MVT::f80) {
4710 static const MCPhysReg RegList6[] = {
4711 X86::FP0, X86::FP1
4712 };
4713 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
4714 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4715 return false;
4716 }
4717 }
4718
4719 if (LocVT == MVT::f32 ||
4720 LocVT == MVT::f64 ||
4721 LocVT == MVT::f128) {
4722 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4723 static const MCPhysReg RegList7[] = {
4724 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4725 };
4726 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
4727 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4728 return false;
4729 }
4730 }
4731 }
4732
4733 if (LocVT == MVT::v16i8 ||
4734 LocVT == MVT::v8i16 ||
4735 LocVT == MVT::v4i32 ||
4736 LocVT == MVT::v2i64 ||
4737 LocVT == MVT::v4f32 ||
4738 LocVT == MVT::v2f64) {
4739 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4740 static const MCPhysReg RegList8[] = {
4741 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4742 };
4743 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
4744 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4745 return false;
4746 }
4747 }
4748 }
4749
4750 if (LocVT == MVT::v32i8 ||
4751 LocVT == MVT::v16i16 ||
4752 LocVT == MVT::v8i32 ||
4753 LocVT == MVT::v4i64 ||
4754 LocVT == MVT::v8f32 ||
4755 LocVT == MVT::v4f64) {
4756 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
4757 static const MCPhysReg RegList9[] = {
4758 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4759 };
4760 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
4761 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4762 return false;
4763 }
4764 }
4765 }
4766
4767 if (LocVT == MVT::v64i8 ||
4768 LocVT == MVT::v32i16 ||
4769 LocVT == MVT::v16i32 ||
4770 LocVT == MVT::v8i64 ||
4771 LocVT == MVT::v16f32 ||
4772 LocVT == MVT::v8f64) {
4773 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
4774 static const MCPhysReg RegList10[] = {
4775 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4776 };
4777 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
4778 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4779 return false;
4780 }
4781 }
4782 }
4783
4784 return true; // CC didn't match.
4785}
4786
4787
4788static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
4789 MVT LocVT, CCValAssign::LocInfo LocInfo,
4790 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4791
4792 if (LocVT == MVT::i1 ||
4793 LocVT == MVT::v1i1 ||
4794 LocVT == MVT::v8i1) {
4795 LocVT = MVT::i8;
4796 if (ArgFlags.isSExt())
4797 LocInfo = CCValAssign::SExt;
4798 else if (ArgFlags.isZExt())
4799 LocInfo = CCValAssign::ZExt;
4800 else
4801 LocInfo = CCValAssign::AExt;
4802 }
4803
4804 if (LocVT == MVT::v16i1) {
4805 LocVT = MVT::i16;
4806 if (ArgFlags.isSExt())
4807 LocInfo = CCValAssign::SExt;
4808 else if (ArgFlags.isZExt())
4809 LocInfo = CCValAssign::ZExt;
4810 else
4811 LocInfo = CCValAssign::AExt;
4812 }
4813
4814 if (LocVT == MVT::v32i1) {
4815 LocVT = MVT::i32;
4816 if (ArgFlags.isSExt())
4817 LocInfo = CCValAssign::SExt;
4818 else if (ArgFlags.isZExt())
4819 LocInfo = CCValAssign::ZExt;
4820 else
4821 LocInfo = CCValAssign::AExt;
4822 }
4823
4824 if (LocVT == MVT::i8) {
4825 static const MCPhysReg RegList1[] = {
4826 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4827 };
4828 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
4829 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4830 return false;
4831 }
4832 }
4833
4834 if (LocVT == MVT::i16) {
4835 static const MCPhysReg RegList2[] = {
4836 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4837 };
4838 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
4839 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4840 return false;
4841 }
4842 }
4843
4844 if (LocVT == MVT::i32) {
4845 static const MCPhysReg RegList3[] = {
4846 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4847 };
4848 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
4849 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4850 return false;
4851 }
4852 }
4853
4854 if (LocVT == MVT::i64) {
4855 static const MCPhysReg RegList4[] = {
4856 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4857 };
4858 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
4859 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4860 return false;
4861 }
4862 }
4863
4864 if (LocVT == MVT::v64i1) {
4865 LocVT = MVT::i64;
4866 if (ArgFlags.isSExt())
4867 LocInfo = CCValAssign::SExt;
4868 else if (ArgFlags.isZExt())
4869 LocInfo = CCValAssign::ZExt;
4870 else
4871 LocInfo = CCValAssign::AExt;
4872 }
4873
4874 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
4875 if (LocVT == MVT::i64) {
4876 static const MCPhysReg RegList5[] = {
4877 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4878 };
4879 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
4880 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4881 return false;
4882 }
4883 }
4884 }
4885
4886 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
4887 if (LocVT == MVT::i64) {
4888 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4889 return false;
4890 }
4891 }
4892
4893 if (LocVT == MVT::f80) {
4894 static const MCPhysReg RegList6[] = {
4895 X86::FP0, X86::FP1
4896 };
4897 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
4898 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4899 return false;
4900 }
4901 }
4902
4903 if (LocVT == MVT::f32 ||
4904 LocVT == MVT::f64 ||
4905 LocVT == MVT::f128) {
4906 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4907 static const MCPhysReg RegList7[] = {
4908 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4909 };
4910 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
4911 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4912 return false;
4913 }
4914 }
4915 }
4916
4917 if (LocVT == MVT::v16i8 ||
4918 LocVT == MVT::v8i16 ||
4919 LocVT == MVT::v4i32 ||
4920 LocVT == MVT::v2i64 ||
4921 LocVT == MVT::v4f32 ||
4922 LocVT == MVT::v2f64) {
4923 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4924 static const MCPhysReg RegList8[] = {
4925 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4926 };
4927 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
4928 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4929 return false;
4930 }
4931 }
4932 }
4933
4934 if (LocVT == MVT::v32i8 ||
4935 LocVT == MVT::v16i16 ||
4936 LocVT == MVT::v8i32 ||
4937 LocVT == MVT::v4i64 ||
4938 LocVT == MVT::v8f32 ||
4939 LocVT == MVT::v4f64) {
4940 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
4941 static const MCPhysReg RegList9[] = {
4942 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4943 };
4944 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
4945 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4946 return false;
4947 }
4948 }
4949 }
4950
4951 if (LocVT == MVT::v64i8 ||
4952 LocVT == MVT::v32i16 ||
4953 LocVT == MVT::v16i32 ||
4954 LocVT == MVT::v8i64 ||
4955 LocVT == MVT::v16f32 ||
4956 LocVT == MVT::v8f64) {
4957 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
4958 static const MCPhysReg RegList10[] = {
4959 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4960 };
4961 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
4962 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
4963 return false;
4964 }
4965 }
4966 }
4967
4968 return true; // CC didn't match.
4969}
4970
4971#else
4972
4973const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4974const MCRegister CC_X86_ArgRegs[] = { 0 };
4975const MCRegister CC_X86_32_ArgRegs[] = { 0 };
4976const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX };
4977const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::MM0, X86::MM1, X86::MM2, X86::XMM0, X86::XMM1, X86::XMM2 };
4978const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4979const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX };
4980const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI };
4981const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI };
4982const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 };
4983const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4984const MCRegister CC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4985const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 };
4986const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX };
4987const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 };
4988const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 };
4989const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 };
4990const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4991const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 };
4992const MCRegister CC_X86_64_ArgRegs[] = { 0 };
4993const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 };
4994const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4995const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 };
4996const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI };
4997const MCRegister CC_X86_64_Preserve_None_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4998const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4999const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX };
5000const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 };
5001const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 };
5002const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX };
5003const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
5004const MCRegister CC_X86_Win64_RegCallv4_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
5005const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 };
5006const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
5007const MCRegister RetCC_X86_ArgRegs[] = { 0 };
5008const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::MM0, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
5009const MCRegister RetCC_X86_32_ArgRegs[] = { 0 };
5010const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 };
5011const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
5012const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI };
5013const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
5014const MCRegister RetCC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
5015const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
5016const MCRegister RetCC_X86_64_ArgRegs[] = { 0 };
5017const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 };
5018const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 };
5019const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX };
5020const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
5021const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
5022const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
5023const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 };
5024const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
5025const MCRegister RetCC_X86_Win64_RegCallv4_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
5026
5027// Registers used by Swift.
5028const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
5029const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
5030const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 };
5031const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 };
5032
5033#endif // CC_REGISTER_LIST
5034