1//===- RegAllocBase.cpp - Register Allocator Base Class -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegAllocBase class which provides common functionality
10// for LiveIntervalUnion-based register allocators.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RegAllocBase.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/LiveInterval.h"
18#include "llvm/CodeGen/LiveIntervals.h"
19#include "llvm/CodeGen/LiveRegMatrix.h"
20#include "llvm/CodeGen/MachineInstr.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/Spiller.h"
24#include "llvm/CodeGen/TargetRegisterInfo.h"
25#include "llvm/CodeGen/VirtRegMap.h"
26#include "llvm/IR/Module.h"
27#include "llvm/Pass.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/Timer.h"
32#include "llvm/Support/raw_ostream.h"
33#include <cassert>
34
35using namespace llvm;
36
37#define DEBUG_TYPE "regalloc"
38
39STATISTIC(NumNewQueued, "Number of new live ranges queued");
40
41// Temporary verification option until we can put verification inside
42// MachineVerifier.
43static cl::opt<bool, true>
44 VerifyRegAlloc("verify-regalloc", cl::location(L&: RegAllocBase::VerifyEnabled),
45 cl::Hidden, cl::desc("Verify during register allocation"));
46
47const char RegAllocBase::TimerGroupName[] = "regalloc";
48const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
49bool RegAllocBase::VerifyEnabled = false;
50
51//===----------------------------------------------------------------------===//
52// RegAllocBase Implementation
53//===----------------------------------------------------------------------===//
54
55// Pin the vtable to this file.
56void RegAllocBase::anchor() {}
57
58void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
59 LiveRegMatrix &mat) {
60 TRI = &vrm.getTargetRegInfo();
61 MRI = &vrm.getRegInfo();
62 VRM = &vrm;
63 LIS = &lis;
64 Matrix = &mat;
65 MRI->freezeReservedRegs();
66 RegClassInfo.runOnMachineFunction(MF: vrm.getMachineFunction());
67}
68
69// Visit all the live registers. If they are already assigned to a physical
70// register, unify them with the corresponding LiveIntervalUnion, otherwise push
71// them on the priority queue for later assignment.
72void RegAllocBase::seedLiveRegs() {
73 NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,
74 TimerGroupDescription, TimePassesIsEnabled);
75 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
76 Register Reg = Register::index2VirtReg(Index: i);
77 if (MRI->reg_nodbg_empty(RegNo: Reg))
78 continue;
79 enqueue(LI: &LIS->getInterval(Reg));
80 }
81}
82
83// Top-level driver to manage the queue of unassigned VirtRegs and call the
84// selectOrSplit implementation.
85void RegAllocBase::allocatePhysRegs() {
86 seedLiveRegs();
87
88 // Continue assigning vregs one at a time to available physical registers.
89 while (const LiveInterval *VirtReg = dequeue()) {
90 assert(!VRM->hasPhys(VirtReg->reg()) && "Register already assigned");
91
92 // Unused registers can appear when the spiller coalesces snippets.
93 if (MRI->reg_nodbg_empty(RegNo: VirtReg->reg())) {
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
95 aboutToRemoveInterval(LI: *VirtReg);
96 LIS->removeInterval(Reg: VirtReg->reg());
97 continue;
98 }
99
100 // Invalidate all interference queries, live ranges could have changed.
101 Matrix->invalidateVirtRegs();
102
103 // selectOrSplit requests the allocator to return an available physical
104 // register if possible and populate a list of new live intervals that
105 // result from splitting.
106 LLVM_DEBUG(dbgs() << "\nselectOrSplit "
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg()))
108 << ':' << *VirtReg << " w=" << VirtReg->weight() << '\n');
109
110 using VirtRegVec = SmallVector<Register, 4>;
111
112 VirtRegVec SplitVRegs;
113 MCRegister AvailablePhysReg = selectOrSplit(VirtReg: *VirtReg, splitLVRs&: SplitVRegs);
114
115 if (AvailablePhysReg == ~0u) {
116 // selectOrSplit failed to find a register!
117 // Probably caused by an inline asm.
118 MachineInstr *MI = nullptr;
119 for (MachineInstr &MIR : MRI->reg_instructions(Reg: VirtReg->reg())) {
120 MI = &MIR;
121 if (MI->isInlineAsm())
122 break;
123 }
124
125 const TargetRegisterClass *RC = MRI->getRegClass(Reg: VirtReg->reg());
126 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
127 if (AllocOrder.empty())
128 report_fatal_error(reason: "no registers from class available to allocate");
129 else if (MI && MI->isInlineAsm()) {
130 MI->emitError(Msg: "inline assembly requires more registers than available");
131 } else if (MI) {
132 LLVMContext &Context =
133 MI->getParent()->getParent()->getFunction().getContext();
134 Context.emitError(ErrorStr: "ran out of registers during register allocation");
135 } else {
136 report_fatal_error(reason: "ran out of registers during register allocation");
137 }
138
139 // Keep going after reporting the error.
140 VRM->assignVirt2Phys(virtReg: VirtReg->reg(), physReg: AllocOrder.front());
141 } else if (AvailablePhysReg)
142 Matrix->assign(VirtReg: *VirtReg, PhysReg: AvailablePhysReg);
143
144 for (Register Reg : SplitVRegs) {
145 assert(LIS->hasInterval(Reg));
146
147 LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
148 assert(!VRM->hasPhys(SplitVirtReg->reg()) && "Register already assigned");
149 if (MRI->reg_nodbg_empty(RegNo: SplitVirtReg->reg())) {
150 assert(SplitVirtReg->empty() && "Non-empty but used interval");
151 LLVM_DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
152 aboutToRemoveInterval(LI: *SplitVirtReg);
153 LIS->removeInterval(Reg: SplitVirtReg->reg());
154 continue;
155 }
156 LLVM_DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
157 assert(SplitVirtReg->reg().isVirtual() &&
158 "expect split value in virtual register");
159 enqueue(LI: SplitVirtReg);
160 ++NumNewQueued;
161 }
162 }
163}
164
165void RegAllocBase::postOptimization() {
166 spiller().postOptimization();
167 for (auto *DeadInst : DeadRemats) {
168 LIS->RemoveMachineInstrFromMaps(MI&: *DeadInst);
169 DeadInst->eraseFromParent();
170 }
171 DeadRemats.clear();
172}
173
174void RegAllocBase::enqueue(const LiveInterval *LI) {
175 const Register Reg = LI->reg();
176
177 assert(Reg.isVirtual() && "Can only enqueue virtual registers");
178
179 if (VRM->hasPhys(virtReg: Reg))
180 return;
181
182 if (shouldAllocateRegister(Reg)) {
183 LLVM_DEBUG(dbgs() << "Enqueuing " << printReg(Reg, TRI) << '\n');
184 enqueueImpl(LI);
185 } else {
186 LLVM_DEBUG(dbgs() << "Not enqueueing " << printReg(Reg, TRI)
187 << " in skipped register class\n");
188 }
189}
190