1//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides basic encoding and assembly information for AArch64.
10//
11//===----------------------------------------------------------------------===//
12#include "AArch64BaseInfo.h"
13#include "llvm/ADT/ArrayRef.h"
14#include "llvm/ADT/SmallVector.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Support/Regex.h"
17
18using namespace llvm;
19
20namespace llvm {
21 namespace AArch64AT {
22#define GET_AT_IMPL
23#include "AArch64GenSystemOperands.inc"
24 }
25}
26
27
28namespace llvm {
29 namespace AArch64DBnXS {
30#define GET_DBNXS_IMPL
31#include "AArch64GenSystemOperands.inc"
32 }
33}
34
35namespace llvm {
36 namespace AArch64DB {
37#define GET_DB_IMPL
38#include "AArch64GenSystemOperands.inc"
39 }
40}
41
42namespace llvm {
43 namespace AArch64DC {
44#define GET_DC_IMPL
45#include "AArch64GenSystemOperands.inc"
46 }
47}
48
49namespace llvm {
50 namespace AArch64IC {
51#define GET_IC_IMPL
52#include "AArch64GenSystemOperands.inc"
53 }
54}
55
56namespace llvm {
57 namespace AArch64ISB {
58#define GET_ISB_IMPL
59#include "AArch64GenSystemOperands.inc"
60 }
61}
62
63namespace llvm {
64 namespace AArch64TSB {
65#define GET_TSB_IMPL
66#include "AArch64GenSystemOperands.inc"
67 }
68}
69
70namespace llvm {
71 namespace AArch64PRCTX {
72#define GET_PRCTX_IMPL
73#include "AArch64GenSystemOperands.inc"
74 }
75}
76
77namespace llvm {
78 namespace AArch64PRFM {
79#define GET_PRFM_IMPL
80#include "AArch64GenSystemOperands.inc"
81 }
82}
83
84namespace llvm {
85 namespace AArch64SVEPRFM {
86#define GET_SVEPRFM_IMPL
87#include "AArch64GenSystemOperands.inc"
88 }
89}
90
91namespace llvm {
92 namespace AArch64RPRFM {
93#define GET_RPRFM_IMPL
94#include "AArch64GenSystemOperands.inc"
95 } // namespace AArch64RPRFM
96} // namespace llvm
97
98namespace llvm {
99 namespace AArch64SVEPredPattern {
100#define GET_SVEPREDPAT_IMPL
101#include "AArch64GenSystemOperands.inc"
102 }
103}
104
105namespace llvm {
106namespace AArch64SVEVecLenSpecifier {
107#define GET_SVEVECLENSPECIFIER_IMPL
108#include "AArch64GenSystemOperands.inc"
109} // namespace AArch64SVEVecLenSpecifier
110} // namespace llvm
111
112namespace llvm {
113 namespace AArch64ExactFPImm {
114#define GET_EXACTFPIMM_IMPL
115#include "AArch64GenSystemOperands.inc"
116 }
117}
118
119namespace llvm {
120 namespace AArch64PState {
121#define GET_PSTATEIMM0_15_IMPL
122#include "AArch64GenSystemOperands.inc"
123#define GET_PSTATEIMM0_1_IMPL
124#include "AArch64GenSystemOperands.inc"
125 }
126}
127
128namespace llvm {
129 namespace AArch64PSBHint {
130#define GET_PSB_IMPL
131#include "AArch64GenSystemOperands.inc"
132 }
133}
134
135namespace llvm {
136 namespace AArch64BTIHint {
137#define GET_BTI_IMPL
138#include "AArch64GenSystemOperands.inc"
139 }
140}
141
142namespace llvm {
143 namespace AArch64SysReg {
144#define GET_SYSREG_IMPL
145#include "AArch64GenSystemOperands.inc"
146 }
147}
148
149uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
150 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
151 static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
152
153 std::string UpperName = Name.upper();
154 SmallVector<StringRef, 5> Ops;
155 if (!GenericRegPattern.match(String: UpperName, Matches: &Ops))
156 return -1;
157
158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
159 uint32_t Bits;
160 Ops[1].getAsInteger(Radix: 10, Result&: Op0);
161 Ops[2].getAsInteger(Radix: 10, Result&: Op1);
162 Ops[3].getAsInteger(Radix: 10, Result&: CRn);
163 Ops[4].getAsInteger(Radix: 10, Result&: CRm);
164 Ops[5].getAsInteger(Radix: 10, Result&: Op2);
165 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
166
167 return Bits;
168}
169
170std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
171 assert(Bits < 0x10000);
172 uint32_t Op0 = (Bits >> 14) & 0x3;
173 uint32_t Op1 = (Bits >> 11) & 0x7;
174 uint32_t CRn = (Bits >> 7) & 0xf;
175 uint32_t CRm = (Bits >> 3) & 0xf;
176 uint32_t Op2 = Bits & 0x7;
177
178 return "S" + utostr(X: Op0) + "_" + utostr(X: Op1) + "_C" + utostr(X: CRn) + "_C" +
179 utostr(X: CRm) + "_" + utostr(X: Op2);
180}
181
182namespace llvm {
183 namespace AArch64TLBI {
184#define GET_TLBITable_IMPL
185#include "AArch64GenSystemOperands.inc"
186 }
187}
188
189namespace llvm {
190 namespace AArch64SVCR {
191#define GET_SVCR_IMPL
192#include "AArch64GenSystemOperands.inc"
193 }
194}
195