1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
14#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15
16#include "ARMSubtarget.h"
17#include "llvm/ADT/StringMap.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/Support/CodeGen.h"
21#include "llvm/Target/TargetMachine.h"
22#include <memory>
23#include <optional>
24
25namespace llvm {
26
27class ARMBaseTargetMachine : public LLVMTargetMachine {
28public:
29 enum ARMABI {
30 ARM_ABI_UNKNOWN,
31 ARM_ABI_APCS,
32 ARM_ABI_AAPCS, // ARM EABI
33 ARM_ABI_AAPCS16
34 } TargetABI;
35
36protected:
37 std::unique_ptr<TargetLoweringObjectFile> TLOF;
38 bool isLittle;
39 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
40
41public:
42 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
43 StringRef FS, const TargetOptions &Options,
44 std::optional<Reloc::Model> RM,
45 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
46 bool isLittle);
47 ~ARMBaseTargetMachine() override;
48
49 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
50 // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
51 // subtargets are per-function entities based on the target-specific
52 // attributes of each function.
53 const ARMSubtarget *getSubtargetImpl() const = delete;
54 bool isLittleEndian() const { return isLittle; }
55
56 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
57
58 // Pass Pipeline Configuration
59 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
60
61 TargetLoweringObjectFile *getObjFileLowering() const override {
62 return TLOF.get();
63 }
64
65 bool isTargetHardFloat() const {
66 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
67 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
68 TargetTriple.getEnvironment() == Triple::EABIHF ||
69 (TargetTriple.isOSBinFormatMachO() &&
70 TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
71 TargetTriple.isOSWindows() ||
72 TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
73 }
74
75 bool targetSchedulesPostRAScheduling() const override { return true; };
76
77 MachineFunctionInfo *
78 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
79 const TargetSubtargetInfo *STI) const override;
80
81 /// Returns true if a cast between SrcAS and DestAS is a noop.
82 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
83 // Addrspacecasts are always noops.
84 return true;
85 }
86
87 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
88 yaml::MachineFunctionInfo *
89 convertFuncInfoToYAML(const MachineFunction &MF) const override;
90 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
91 PerFunctionMIParsingState &PFS,
92 SMDiagnostic &Error,
93 SMRange &SourceRange) const override;
94};
95
96/// ARM/Thumb little endian target machine.
97///
98class ARMLETargetMachine : public ARMBaseTargetMachine {
99public:
100 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
101 StringRef FS, const TargetOptions &Options,
102 std::optional<Reloc::Model> RM,
103 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
104 bool JIT);
105};
106
107/// ARM/Thumb big endian target machine.
108///
109class ARMBETargetMachine : public ARMBaseTargetMachine {
110public:
111 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
112 StringRef FS, const TargetOptions &Options,
113 std::optional<Reloc::Model> RM,
114 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
115 bool JIT);
116};
117
118} // end namespace llvm
119
120#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
121