1 | //===-- NVPTXTargetMachine.h - Define TargetMachine for NVPTX ---*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file declares the NVPTX specific subclass of TargetMachine. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H |
14 | #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H |
15 | |
16 | #include "NVPTXSubtarget.h" |
17 | #include "llvm/Target/TargetMachine.h" |
18 | #include <optional> |
19 | #include <utility> |
20 | |
21 | namespace llvm { |
22 | |
23 | /// NVPTXTargetMachine |
24 | /// |
25 | class NVPTXTargetMachine : public LLVMTargetMachine { |
26 | bool is64bit; |
27 | std::unique_ptr<TargetLoweringObjectFile> TLOF; |
28 | NVPTX::DrvInterface drvInterface; |
29 | NVPTXSubtarget Subtarget; |
30 | |
31 | // Hold Strings that can be free'd all together with NVPTXTargetMachine |
32 | BumpPtrAllocator StrAlloc; |
33 | UniqueStringSaver StrPool; |
34 | |
35 | public: |
36 | NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, |
37 | StringRef FS, const TargetOptions &Options, |
38 | std::optional<Reloc::Model> RM, |
39 | std::optional<CodeModel::Model> CM, CodeGenOptLevel OP, |
40 | bool is64bit); |
41 | ~NVPTXTargetMachine() override; |
42 | const NVPTXSubtarget *getSubtargetImpl(const Function &) const override { |
43 | return &Subtarget; |
44 | } |
45 | const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; } |
46 | bool is64Bit() const { return is64bit; } |
47 | NVPTX::DrvInterface getDrvInterface() const { return drvInterface; } |
48 | UniqueStringSaver &getStrPool() const { |
49 | return const_cast<UniqueStringSaver &>(StrPool); |
50 | } |
51 | |
52 | TargetPassConfig *createPassConfig(PassManagerBase &PM) override; |
53 | |
54 | // Emission of machine code through MCJIT is not supported. |
55 | bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_pwrite_stream &, |
56 | bool = true) override { |
57 | return true; |
58 | } |
59 | TargetLoweringObjectFile *getObjFileLowering() const override { |
60 | return TLOF.get(); |
61 | } |
62 | |
63 | MachineFunctionInfo * |
64 | createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, |
65 | const TargetSubtargetInfo *STI) const override; |
66 | |
67 | void registerDefaultAliasAnalyses(AAManager &AAM) override; |
68 | |
69 | void registerPassBuilderCallbacks(PassBuilder &PB) override; |
70 | |
71 | TargetTransformInfo getTargetTransformInfo(const Function &F) const override; |
72 | |
73 | bool isMachineVerifierClean() const override { |
74 | return false; |
75 | } |
76 | |
77 | std::pair<const Value *, unsigned> |
78 | getPredicatedAddrSpace(const Value *V) const override; |
79 | }; // NVPTXTargetMachine. |
80 | |
81 | class NVPTXTargetMachine32 : public NVPTXTargetMachine { |
82 | virtual void anchor(); |
83 | |
84 | public: |
85 | NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, |
86 | StringRef FS, const TargetOptions &Options, |
87 | std::optional<Reloc::Model> RM, |
88 | std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, |
89 | bool JIT); |
90 | }; |
91 | |
92 | class NVPTXTargetMachine64 : public NVPTXTargetMachine { |
93 | virtual void anchor(); |
94 | |
95 | public: |
96 | NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, |
97 | StringRef FS, const TargetOptions &Options, |
98 | std::optional<Reloc::Model> RM, |
99 | std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, |
100 | bool JIT); |
101 | }; |
102 | |
103 | } // end namespace llvm |
104 | |
105 | #endif |
106 | |