1//===-- RISCVAsmBackend.cpp - RISC-V Assembler Backend --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVAsmBackend.h"
10#include "RISCVMCExpr.h"
11#include "llvm/ADT/APInt.h"
12#include "llvm/MC/MCAsmInfo.h"
13#include "llvm/MC/MCAssembler.h"
14#include "llvm/MC/MCContext.h"
15#include "llvm/MC/MCDirectives.h"
16#include "llvm/MC/MCELFObjectWriter.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCObjectWriter.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/MC/MCValue.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/Endian.h"
23#include "llvm/Support/EndianStream.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/LEB128.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30static cl::opt<bool> RelaxBranches("riscv-asm-relax-branches", cl::init(Val: true),
31 cl::Hidden);
32// Temporary workaround for old linkers that do not support ULEB128 relocations,
33// which are abused by DWARF v5 DW_LLE_offset_pair/DW_RLE_offset_pair
34// implemented in Clang/LLVM.
35static cl::opt<bool> ULEB128Reloc(
36 "riscv-uleb128-reloc", cl::init(Val: true), cl::Hidden,
37 cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"));
38
39std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
40 if (STI.getTargetTriple().isOSBinFormatELF()) {
41 unsigned Type;
42 Type = llvm::StringSwitch<unsigned>(Name)
43#define ELF_RELOC(X, Y) .Case(#X, Y)
44#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
45#undef ELF_RELOC
46 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_RISCV_NONE)
47 .Case(S: "BFD_RELOC_32", Value: ELF::R_RISCV_32)
48 .Case(S: "BFD_RELOC_64", Value: ELF::R_RISCV_64)
49 .Default(Value: -1u);
50 if (Type != -1u)
51 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
52 }
53 return std::nullopt;
54}
55
56const MCFixupKindInfo &
57RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
58 const static MCFixupKindInfo Infos[] = {
59 // This table *must* be in the order that the fixup_* kinds are defined in
60 // RISCVFixupKinds.h.
61 //
62 // name offset bits flags
63 {.Name: "fixup_riscv_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
64 {.Name: "fixup_riscv_lo12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
65 {.Name: "fixup_riscv_12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
66 {.Name: "fixup_riscv_lo12_s", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
67 {.Name: "fixup_riscv_pcrel_hi20", .TargetOffset: 12, .TargetSize: 20,
68 .Flags: MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
69 {.Name: "fixup_riscv_pcrel_lo12_i", .TargetOffset: 20, .TargetSize: 12,
70 .Flags: MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
71 {.Name: "fixup_riscv_pcrel_lo12_s", .TargetOffset: 0, .TargetSize: 32,
72 .Flags: MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
73 {.Name: "fixup_riscv_got_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: MCFixupKindInfo::FKF_IsPCRel},
74 {.Name: "fixup_riscv_tprel_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
75 {.Name: "fixup_riscv_tprel_lo12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
76 {.Name: "fixup_riscv_tprel_lo12_s", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
77 {.Name: "fixup_riscv_tprel_add", .TargetOffset: 0, .TargetSize: 0, .Flags: 0},
78 {.Name: "fixup_riscv_tls_got_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: MCFixupKindInfo::FKF_IsPCRel},
79 {.Name: "fixup_riscv_tls_gd_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: MCFixupKindInfo::FKF_IsPCRel},
80 {.Name: "fixup_riscv_jal", .TargetOffset: 12, .TargetSize: 20, .Flags: MCFixupKindInfo::FKF_IsPCRel},
81 {.Name: "fixup_riscv_branch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
82 {.Name: "fixup_riscv_rvc_jump", .TargetOffset: 2, .TargetSize: 11, .Flags: MCFixupKindInfo::FKF_IsPCRel},
83 {.Name: "fixup_riscv_rvc_branch", .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel},
84 {.Name: "fixup_riscv_call", .TargetOffset: 0, .TargetSize: 64, .Flags: MCFixupKindInfo::FKF_IsPCRel},
85 {.Name: "fixup_riscv_call_plt", .TargetOffset: 0, .TargetSize: 64, .Flags: MCFixupKindInfo::FKF_IsPCRel},
86 {.Name: "fixup_riscv_relax", .TargetOffset: 0, .TargetSize: 0, .Flags: 0},
87 {.Name: "fixup_riscv_align", .TargetOffset: 0, .TargetSize: 0, .Flags: 0},
88
89 {.Name: "fixup_riscv_tlsdesc_hi20", .TargetOffset: 12, .TargetSize: 20,
90 .Flags: MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
91 {.Name: "fixup_riscv_tlsdesc_load_lo12", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
92 {.Name: "fixup_riscv_tlsdesc_add_lo12", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
93 {.Name: "fixup_riscv_tlsdesc_call", .TargetOffset: 0, .TargetSize: 0, .Flags: 0},
94 };
95 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
96 "Not all fixup kinds added to Infos array");
97
98 // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
99 // do not require any extra processing.
100 if (Kind >= FirstLiteralRelocationKind)
101 return MCAsmBackend::getFixupKindInfo(Kind: FK_NONE);
102
103 if (Kind < FirstTargetFixupKind)
104 return MCAsmBackend::getFixupKindInfo(Kind);
105
106 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
107 "Invalid kind!");
108 return Infos[Kind - FirstTargetFixupKind];
109}
110
111// If linker relaxation is enabled, or the relax option had previously been
112// enabled, always emit relocations even if the fixup can be resolved. This is
113// necessary for correctness as offsets may change during relaxation.
114bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
115 const MCFixup &Fixup,
116 const MCValue &Target,
117 const MCSubtargetInfo *STI) {
118 if (Fixup.getKind() >= FirstLiteralRelocationKind)
119 return true;
120 switch (Fixup.getTargetKind()) {
121 default:
122 break;
123 case FK_Data_1:
124 case FK_Data_2:
125 case FK_Data_4:
126 case FK_Data_8:
127 case FK_Data_leb128:
128 if (Target.isAbsolute())
129 return false;
130 break;
131 case RISCV::fixup_riscv_got_hi20:
132 case RISCV::fixup_riscv_tls_got_hi20:
133 case RISCV::fixup_riscv_tls_gd_hi20:
134 case RISCV::fixup_riscv_tlsdesc_hi20:
135 return true;
136 }
137
138 return STI->hasFeature(Feature: RISCV::FeatureRelax) || ForceRelocs;
139}
140
141bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(
142 const MCAssembler &Asm, const MCFixup &Fixup, bool Resolved, uint64_t Value,
143 const MCRelaxableFragment *DF, const bool WasForced) const {
144 if (!RelaxBranches)
145 return false;
146
147 int64_t Offset = int64_t(Value);
148 unsigned Kind = Fixup.getTargetKind();
149
150 // Return true if the symbol is actually unresolved.
151 // Resolved could be always false when shouldForceRelocation return true.
152 // We use !WasForced to indicate that the symbol is unresolved and not forced
153 // by shouldForceRelocation.
154 if (!Resolved && !WasForced)
155 return true;
156
157 switch (Kind) {
158 default:
159 return false;
160 case RISCV::fixup_riscv_rvc_branch:
161 // For compressed branch instructions the immediate must be
162 // in the range [-256, 254].
163 return Offset > 254 || Offset < -256;
164 case RISCV::fixup_riscv_rvc_jump:
165 // For compressed jump instructions the immediate must be
166 // in the range [-2048, 2046].
167 return Offset > 2046 || Offset < -2048;
168 case RISCV::fixup_riscv_branch:
169 // For conditional branch instructions the immediate must be
170 // in the range [-4096, 4095].
171 return !isInt<13>(x: Offset);
172 }
173}
174
175void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
176 const MCSubtargetInfo &STI) const {
177 MCInst Res;
178 switch (Inst.getOpcode()) {
179 default:
180 llvm_unreachable("Opcode not expected!");
181 case RISCV::C_BEQZ:
182 case RISCV::C_BNEZ:
183 case RISCV::C_J:
184 case RISCV::C_JAL: {
185 [[maybe_unused]] bool Success = RISCVRVC::uncompress(OutInst&: Res, MI: Inst, STI);
186 assert(Success && "Can't uncompress instruction");
187 break;
188 }
189 case RISCV::BEQ:
190 case RISCV::BNE:
191 case RISCV::BLT:
192 case RISCV::BGE:
193 case RISCV::BLTU:
194 case RISCV::BGEU:
195 Res.setOpcode(getRelaxedOpcode(Op: Inst.getOpcode()));
196 Res.addOperand(Op: Inst.getOperand(i: 0));
197 Res.addOperand(Op: Inst.getOperand(i: 1));
198 Res.addOperand(Op: Inst.getOperand(i: 2));
199 break;
200 }
201 Inst = std::move(Res);
202}
203
204bool RISCVAsmBackend::relaxDwarfLineAddr(const MCAssembler &Asm,
205 MCDwarfLineAddrFragment &DF,
206 bool &WasRelaxed) const {
207 MCContext &C = Asm.getContext();
208
209 int64_t LineDelta = DF.getLineDelta();
210 const MCExpr &AddrDelta = DF.getAddrDelta();
211 SmallVectorImpl<char> &Data = DF.getContents();
212 SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
213 size_t OldSize = Data.size();
214
215 int64_t Value;
216 [[maybe_unused]] bool IsAbsolute =
217 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm);
218 assert(IsAbsolute && "CFA with invalid expression");
219
220 Data.clear();
221 Fixups.clear();
222 raw_svector_ostream OS(Data);
223
224 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
225 if (LineDelta != INT64_MAX) {
226 OS << uint8_t(dwarf::DW_LNS_advance_line);
227 encodeSLEB128(Value: LineDelta, OS);
228 }
229
230 unsigned Offset;
231 std::pair<MCFixupKind, MCFixupKind> Fixup;
232
233 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
234 // takes a single unsigned half (unencoded) operand. The maximum encodable
235 // value is therefore 65535. Set a conservative upper bound for relaxation.
236 if (Value > 60000) {
237 unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
238
239 OS << uint8_t(dwarf::DW_LNS_extended_op);
240 encodeULEB128(Value: PtrSize + 1, OS);
241
242 OS << uint8_t(dwarf::DW_LNE_set_address);
243 Offset = OS.tell();
244 assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
245 Fixup = RISCV::getRelocPairForSize(Size: PtrSize);
246 OS.write_zeros(NumZeros: PtrSize);
247 } else {
248 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
249 Offset = OS.tell();
250 Fixup = RISCV::getRelocPairForSize(Size: 2);
251 support::endian::write<uint16_t>(os&: OS, value: 0, endian: llvm::endianness::little);
252 }
253
254 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(Val: AddrDelta);
255 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getLHS(), Kind: std::get<0>(in&: Fixup)));
256 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getRHS(), Kind: std::get<1>(in&: Fixup)));
257
258 if (LineDelta == INT64_MAX) {
259 OS << uint8_t(dwarf::DW_LNS_extended_op);
260 OS << uint8_t(1);
261 OS << uint8_t(dwarf::DW_LNE_end_sequence);
262 } else {
263 OS << uint8_t(dwarf::DW_LNS_copy);
264 }
265
266 WasRelaxed = OldSize != Data.size();
267 return true;
268}
269
270bool RISCVAsmBackend::relaxDwarfCFA(const MCAssembler &Asm,
271 MCDwarfCallFrameFragment &DF,
272 bool &WasRelaxed) const {
273 const MCExpr &AddrDelta = DF.getAddrDelta();
274 SmallVectorImpl<char> &Data = DF.getContents();
275 SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
276 size_t OldSize = Data.size();
277
278 int64_t Value;
279 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm))
280 return false;
281 [[maybe_unused]] bool IsAbsolute =
282 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm);
283 assert(IsAbsolute && "CFA with invalid expression");
284
285 Data.clear();
286 Fixups.clear();
287 raw_svector_ostream OS(Data);
288
289 assert(Asm.getContext().getAsmInfo()->getMinInstAlignment() == 1 &&
290 "expected 1-byte alignment");
291 if (Value == 0) {
292 WasRelaxed = OldSize != Data.size();
293 return true;
294 }
295
296 auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,
297 std::pair<unsigned, unsigned> Fixup) {
298 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(Val: AddrDelta);
299 Fixups.push_back(
300 Elt: MCFixup::create(Offset, Value: MBE.getLHS(),
301 Kind: static_cast<MCFixupKind>(FirstLiteralRelocationKind +
302 std::get<0>(in&: Fixup))));
303 Fixups.push_back(
304 Elt: MCFixup::create(Offset, Value: MBE.getRHS(),
305 Kind: static_cast<MCFixupKind>(FirstLiteralRelocationKind +
306 std::get<1>(in&: Fixup))));
307 };
308
309 if (isUIntN(N: 6, x: Value)) {
310 OS << uint8_t(dwarf::DW_CFA_advance_loc);
311 AddFixups(0, {ELF::R_RISCV_SET6, ELF::R_RISCV_SUB6});
312 } else if (isUInt<8>(x: Value)) {
313 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
314 support::endian::write<uint8_t>(os&: OS, value: 0, endian: llvm::endianness::little);
315 AddFixups(1, {ELF::R_RISCV_SET8, ELF::R_RISCV_SUB8});
316 } else if (isUInt<16>(x: Value)) {
317 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
318 support::endian::write<uint16_t>(os&: OS, value: 0, endian: llvm::endianness::little);
319 AddFixups(1, {ELF::R_RISCV_SET16, ELF::R_RISCV_SUB16});
320 } else if (isUInt<32>(x: Value)) {
321 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
322 support::endian::write<uint32_t>(os&: OS, value: 0, endian: llvm::endianness::little);
323 AddFixups(1, {ELF::R_RISCV_SET32, ELF::R_RISCV_SUB32});
324 } else {
325 llvm_unreachable("unsupported CFA encoding");
326 }
327
328 WasRelaxed = OldSize != Data.size();
329 return true;
330}
331
332std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
333 MCLEBFragment &LF,
334 int64_t &Value) const {
335 if (LF.isSigned())
336 return std::make_pair(x: false, y: false);
337 const MCExpr &Expr = LF.getValue();
338 if (ULEB128Reloc) {
339 LF.getFixups().push_back(
340 Elt: MCFixup::create(Offset: 0, Value: &Expr, Kind: FK_Data_leb128, Loc: Expr.getLoc()));
341 }
342 return std::make_pair(x: Expr.evaluateKnownAbsolute(Res&: Value, Asm), y: false);
343}
344
345// Given a compressed control flow instruction this function returns
346// the expanded instruction.
347unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
348 switch (Op) {
349 default:
350 return Op;
351 case RISCV::C_BEQZ:
352 return RISCV::BEQ;
353 case RISCV::C_BNEZ:
354 return RISCV::BNE;
355 case RISCV::C_J:
356 case RISCV::C_JAL: // fall through.
357 return RISCV::JAL;
358 case RISCV::BEQ:
359 return RISCV::PseudoLongBEQ;
360 case RISCV::BNE:
361 return RISCV::PseudoLongBNE;
362 case RISCV::BLT:
363 return RISCV::PseudoLongBLT;
364 case RISCV::BGE:
365 return RISCV::PseudoLongBGE;
366 case RISCV::BLTU:
367 return RISCV::PseudoLongBLTU;
368 case RISCV::BGEU:
369 return RISCV::PseudoLongBGEU;
370 }
371}
372
373bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
374 const MCSubtargetInfo &STI) const {
375 return getRelaxedOpcode(Op: Inst.getOpcode()) != Inst.getOpcode();
376}
377
378bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
379 const MCSubtargetInfo *STI) const {
380 // We mostly follow binutils' convention here: align to even boundary with a
381 // 0-fill padding. We emit up to 1 2-byte nop, though we use c.nop if RVC is
382 // enabled or 0-fill otherwise. The remainder is now padded with 4-byte nops.
383
384 // Instructions always are at even addresses. We must be in a data area or
385 // be unaligned due to some other reason.
386 if (Count % 2) {
387 OS.write(Ptr: "\0", Size: 1);
388 Count -= 1;
389 }
390
391 bool UseCompressedNop = STI->hasFeature(Feature: RISCV::FeatureStdExtC) ||
392 STI->hasFeature(Feature: RISCV::FeatureStdExtZca);
393 // The canonical nop on RVC is c.nop.
394 if (Count % 4 == 2) {
395 OS.write(Ptr: UseCompressedNop ? "\x01\0" : "\0\0", Size: 2);
396 Count -= 2;
397 }
398
399 // The canonical nop on RISC-V is addi x0, x0, 0.
400 for (; Count >= 4; Count -= 4)
401 OS.write(Ptr: "\x13\0\0\0", Size: 4);
402
403 return true;
404}
405
406static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
407 MCContext &Ctx) {
408 switch (Fixup.getTargetKind()) {
409 default:
410 llvm_unreachable("Unknown fixup kind!");
411 case RISCV::fixup_riscv_got_hi20:
412 case RISCV::fixup_riscv_tls_got_hi20:
413 case RISCV::fixup_riscv_tls_gd_hi20:
414 case RISCV::fixup_riscv_tlsdesc_hi20:
415 llvm_unreachable("Relocation should be unconditionally forced\n");
416 case FK_Data_1:
417 case FK_Data_2:
418 case FK_Data_4:
419 case FK_Data_8:
420 case FK_Data_leb128:
421 return Value;
422 case RISCV::fixup_riscv_lo12_i:
423 case RISCV::fixup_riscv_pcrel_lo12_i:
424 case RISCV::fixup_riscv_tprel_lo12_i:
425 case RISCV::fixup_riscv_tlsdesc_load_lo12:
426 return Value & 0xfff;
427 case RISCV::fixup_riscv_12_i:
428 if (!isInt<12>(x: Value)) {
429 Ctx.reportError(L: Fixup.getLoc(),
430 Msg: "operand must be a constant 12-bit integer");
431 }
432 return Value & 0xfff;
433 case RISCV::fixup_riscv_lo12_s:
434 case RISCV::fixup_riscv_pcrel_lo12_s:
435 case RISCV::fixup_riscv_tprel_lo12_s:
436 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
437 case RISCV::fixup_riscv_hi20:
438 case RISCV::fixup_riscv_pcrel_hi20:
439 case RISCV::fixup_riscv_tprel_hi20:
440 // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
441 return ((Value + 0x800) >> 12) & 0xfffff;
442 case RISCV::fixup_riscv_jal: {
443 if (!isInt<21>(x: Value))
444 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
445 if (Value & 0x1)
446 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
447 // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
448 unsigned Sbit = (Value >> 20) & 0x1;
449 unsigned Hi8 = (Value >> 12) & 0xff;
450 unsigned Mid1 = (Value >> 11) & 0x1;
451 unsigned Lo10 = (Value >> 1) & 0x3ff;
452 // Inst{31} = Sbit;
453 // Inst{30-21} = Lo10;
454 // Inst{20} = Mid1;
455 // Inst{19-12} = Hi8;
456 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
457 return Value;
458 }
459 case RISCV::fixup_riscv_branch: {
460 if (!isInt<13>(x: Value))
461 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
462 if (Value & 0x1)
463 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
464 // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
465 // Value.
466 unsigned Sbit = (Value >> 12) & 0x1;
467 unsigned Hi1 = (Value >> 11) & 0x1;
468 unsigned Mid6 = (Value >> 5) & 0x3f;
469 unsigned Lo4 = (Value >> 1) & 0xf;
470 // Inst{31} = Sbit;
471 // Inst{30-25} = Mid6;
472 // Inst{11-8} = Lo4;
473 // Inst{7} = Hi1;
474 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
475 return Value;
476 }
477 case RISCV::fixup_riscv_call:
478 case RISCV::fixup_riscv_call_plt: {
479 // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
480 // we need to add 0x800ULL before extract upper bits to reflect the
481 // effect of the sign extension.
482 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
483 uint64_t LowerImm = Value & 0xfffULL;
484 return UpperImm | ((LowerImm << 20) << 32);
485 }
486 case RISCV::fixup_riscv_rvc_jump: {
487 if (!isInt<12>(x: Value))
488 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
489 // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
490 unsigned Bit11 = (Value >> 11) & 0x1;
491 unsigned Bit4 = (Value >> 4) & 0x1;
492 unsigned Bit9_8 = (Value >> 8) & 0x3;
493 unsigned Bit10 = (Value >> 10) & 0x1;
494 unsigned Bit6 = (Value >> 6) & 0x1;
495 unsigned Bit7 = (Value >> 7) & 0x1;
496 unsigned Bit3_1 = (Value >> 1) & 0x7;
497 unsigned Bit5 = (Value >> 5) & 0x1;
498 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
499 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
500 return Value;
501 }
502 case RISCV::fixup_riscv_rvc_branch: {
503 if (!isInt<9>(x: Value))
504 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
505 // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
506 unsigned Bit8 = (Value >> 8) & 0x1;
507 unsigned Bit7_6 = (Value >> 6) & 0x3;
508 unsigned Bit5 = (Value >> 5) & 0x1;
509 unsigned Bit4_3 = (Value >> 3) & 0x3;
510 unsigned Bit2_1 = (Value >> 1) & 0x3;
511 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
512 (Bit5 << 2);
513 return Value;
514 }
515
516 }
517}
518
519bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm,
520 const MCFixup &Fixup,
521 const MCFragment *DF,
522 const MCValue &Target,
523 const MCSubtargetInfo *STI,
524 uint64_t &Value, bool &WasForced) {
525 const MCFixup *AUIPCFixup;
526 const MCFragment *AUIPCDF;
527 MCValue AUIPCTarget;
528 switch (Fixup.getTargetKind()) {
529 default:
530 llvm_unreachable("Unexpected fixup kind!");
531 case RISCV::fixup_riscv_tlsdesc_hi20:
532 case RISCV::fixup_riscv_pcrel_hi20:
533 AUIPCFixup = &Fixup;
534 AUIPCDF = DF;
535 AUIPCTarget = Target;
536 break;
537 case RISCV::fixup_riscv_pcrel_lo12_i:
538 case RISCV::fixup_riscv_pcrel_lo12_s: {
539 AUIPCFixup = cast<RISCVMCExpr>(Val: Fixup.getValue())->getPCRelHiFixup(DFOut: &AUIPCDF);
540 if (!AUIPCFixup) {
541 Asm.getContext().reportError(L: Fixup.getLoc(),
542 Msg: "could not find corresponding %pcrel_hi");
543 return true;
544 }
545
546 // MCAssembler::evaluateFixup will emit an error for this case when it sees
547 // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
548 const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
549 if (!AUIPCExpr->evaluateAsRelocatable(Res&: AUIPCTarget, Asm: &Asm, Fixup: AUIPCFixup))
550 return true;
551 break;
552 }
553 }
554
555 if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB())
556 return false;
557
558 const MCSymbolRefExpr *A = AUIPCTarget.getSymA();
559 const MCSymbol &SA = A->getSymbol();
560 if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined())
561 return false;
562
563 bool IsResolved = Asm.getWriter().isSymbolRefDifferenceFullyResolvedImpl(
564 Asm, SymA: SA, FB: *AUIPCDF, InSet: false, IsPCRel: true);
565 if (!IsResolved)
566 return false;
567
568 Value = Asm.getSymbolOffset(S: SA) + AUIPCTarget.getConstant();
569 Value -= Asm.getFragmentOffset(F: *AUIPCDF) + AUIPCFixup->getOffset();
570
571 if (shouldForceRelocation(Asm, Fixup: *AUIPCFixup, Target: AUIPCTarget, STI)) {
572 WasForced = true;
573 return false;
574 }
575
576 return true;
577}
578
579bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,
580 const MCFragment &F,
581 const MCFixup &Fixup,
582 const MCValue &Target,
583 uint64_t &FixedValue) const {
584 uint64_t FixedValueA, FixedValueB;
585 unsigned TA = 0, TB = 0;
586 switch (Fixup.getKind()) {
587 case llvm::FK_Data_1:
588 TA = ELF::R_RISCV_ADD8;
589 TB = ELF::R_RISCV_SUB8;
590 break;
591 case llvm::FK_Data_2:
592 TA = ELF::R_RISCV_ADD16;
593 TB = ELF::R_RISCV_SUB16;
594 break;
595 case llvm::FK_Data_4:
596 TA = ELF::R_RISCV_ADD32;
597 TB = ELF::R_RISCV_SUB32;
598 break;
599 case llvm::FK_Data_8:
600 TA = ELF::R_RISCV_ADD64;
601 TB = ELF::R_RISCV_SUB64;
602 break;
603 case llvm::FK_Data_leb128:
604 TA = ELF::R_RISCV_SET_ULEB128;
605 TB = ELF::R_RISCV_SUB_ULEB128;
606 break;
607 default:
608 llvm_unreachable("unsupported fixup size");
609 }
610 MCValue A = MCValue::get(SymA: Target.getSymA(), SymB: nullptr, Val: Target.getConstant());
611 MCValue B = MCValue::get(SymA: Target.getSymB());
612 auto FA = MCFixup::create(
613 Offset: Fixup.getOffset(), Value: nullptr,
614 Kind: static_cast<MCFixupKind>(FirstLiteralRelocationKind + TA));
615 auto FB = MCFixup::create(
616 Offset: Fixup.getOffset(), Value: nullptr,
617 Kind: static_cast<MCFixupKind>(FirstLiteralRelocationKind + TB));
618 auto &Assembler = const_cast<MCAssembler &>(Asm);
619 Asm.getWriter().recordRelocation(Asm&: Assembler, Fragment: &F, Fixup: FA, Target: A, FixedValue&: FixedValueA);
620 Asm.getWriter().recordRelocation(Asm&: Assembler, Fragment: &F, Fixup: FB, Target: B, FixedValue&: FixedValueB);
621 FixedValue = FixedValueA - FixedValueB;
622 return true;
623}
624
625void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
626 const MCValue &Target,
627 MutableArrayRef<char> Data, uint64_t Value,
628 bool IsResolved,
629 const MCSubtargetInfo *STI) const {
630 MCFixupKind Kind = Fixup.getKind();
631 if (Kind >= FirstLiteralRelocationKind)
632 return;
633 MCContext &Ctx = Asm.getContext();
634 MCFixupKindInfo Info = getFixupKindInfo(Kind);
635 if (!Value)
636 return; // Doesn't change encoding.
637 // Apply any target-specific value adjustments.
638 Value = adjustFixupValue(Fixup, Value, Ctx);
639
640 // Shift the value into position.
641 Value <<= Info.TargetOffset;
642
643 unsigned Offset = Fixup.getOffset();
644 unsigned NumBytes = alignTo(Value: Info.TargetSize + Info.TargetOffset, Align: 8) / 8;
645
646 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
647
648 // For each byte of the fragment that the fixup touches, mask in the
649 // bits from the fixup value.
650 for (unsigned i = 0; i != NumBytes; ++i) {
651 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
652 }
653}
654
655// Linker relaxation may change code size. We have to insert Nops
656// for .align directive when linker relaxation enabled. So then Linker
657// could satisfy alignment by removing Nops.
658// The function return the total Nops Size we need to insert.
659bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
660 const MCAlignFragment &AF, unsigned &Size) {
661 // Calculate Nops Size only when linker relaxation enabled.
662 const MCSubtargetInfo *STI = AF.getSubtargetInfo();
663 if (!STI->hasFeature(Feature: RISCV::FeatureRelax))
664 return false;
665
666 bool UseCompressedNop = STI->hasFeature(Feature: RISCV::FeatureStdExtC) ||
667 STI->hasFeature(Feature: RISCV::FeatureStdExtZca);
668 unsigned MinNopLen = UseCompressedNop ? 2 : 4;
669
670 if (AF.getAlignment() <= MinNopLen) {
671 return false;
672 } else {
673 Size = AF.getAlignment().value() - MinNopLen;
674 return true;
675 }
676}
677
678// We need to insert R_RISCV_ALIGN relocation type to indicate the
679// position of Nops and the total bytes of the Nops have been inserted
680// when linker relaxation enabled.
681// The function insert fixup_riscv_align fixup which eventually will
682// transfer to R_RISCV_ALIGN relocation type.
683bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
684 MCAlignFragment &AF) {
685 // Insert the fixup only when linker relaxation enabled.
686 const MCSubtargetInfo *STI = AF.getSubtargetInfo();
687 if (!STI->hasFeature(Feature: RISCV::FeatureRelax))
688 return false;
689
690 // Calculate total Nops we need to insert. If there are none to insert
691 // then simply return.
692 unsigned Count;
693 if (!shouldInsertExtraNopBytesForCodeAlign(AF, Size&: Count) || (Count == 0))
694 return false;
695
696 MCContext &Ctx = Asm.getContext();
697 const MCExpr *Dummy = MCConstantExpr::create(Value: 0, Ctx);
698 // Create fixup_riscv_align fixup.
699 MCFixup Fixup =
700 MCFixup::create(Offset: 0, Value: Dummy, Kind: MCFixupKind(RISCV::fixup_riscv_align), Loc: SMLoc());
701
702 uint64_t FixedValue = 0;
703 MCValue NopBytes = MCValue::get(Val: Count);
704
705 Asm.getWriter().recordRelocation(Asm, Fragment: &AF, Fixup, Target: NopBytes, FixedValue);
706
707 return true;
708}
709
710std::unique_ptr<MCObjectTargetWriter>
711RISCVAsmBackend::createObjectTargetWriter() const {
712 return createRISCVELFObjectWriter(OSABI, Is64Bit);
713}
714
715MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
716 const MCSubtargetInfo &STI,
717 const MCRegisterInfo &MRI,
718 const MCTargetOptions &Options) {
719 const Triple &TT = STI.getTargetTriple();
720 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TT.getOS());
721 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
722}
723