1//===-- VEFrameLowering.cpp - VE Frame Information ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the VE implementation of TargetFrameLowering class.
10//
11// On VE, stack frames are structured as follows:
12//
13// The stack grows downward.
14//
15// All of the individual frame areas on the frame below are optional, i.e. it's
16// possible to create a function so that the particular area isn't present
17// in the frame.
18//
19// At function entry, the "frame" looks as follows:
20//
21// | | Higher address
22// |----------------------------------------------|
23// | Parameter area for this function |
24// |----------------------------------------------|
25// | Register save area (RSA) for this function |
26// |----------------------------------------------|
27// | Return address for this function |
28// |----------------------------------------------|
29// | Frame pointer for this function |
30// |----------------------------------------------| <- sp
31// | | Lower address
32//
33// VE doesn't use on demand stack allocation, so user code generated by LLVM
34// needs to call VEOS to allocate stack frame. VE's ABI want to reduce the
35// number of VEOS calls, so ABI requires to allocate not only RSA (in general
36// CSR, callee saved register) area but also call frame at the prologue of
37// caller function.
38//
39// After the prologue has run, the frame has the following general structure.
40// Note that technically the last frame area (VLAs) doesn't get created until
41// in the main function body, after the prologue is run. However, it's depicted
42// here for completeness.
43//
44// | | Higher address
45// |----------------------------------------------|
46// | Parameter area for this function |
47// |----------------------------------------------|
48// | Register save area (RSA) for this function |
49// |----------------------------------------------|
50// | Return address for this function |
51// |----------------------------------------------|
52// | Frame pointer for this function |
53// |----------------------------------------------| <- fp(=old sp)
54// |.empty.space.to.make.part.below.aligned.in....|
55// |.case.it.needs.more.than.the.standard.16-byte.| (size of this area is
56// |.alignment....................................| unknown at compile time)
57// |----------------------------------------------|
58// | Local variables of fixed size including spill|
59// | slots |
60// |----------------------------------------------| <- bp(not defined by ABI,
61// |.variable-sized.local.variables.(VLAs)........| LLVM chooses SX17)
62// |..............................................| (size of this area is
63// |..............................................| unknown at compile time)
64// |----------------------------------------------| <- stack top (returned by
65// | Parameter area for callee | alloca)
66// |----------------------------------------------|
67// | Register save area (RSA) for callee |
68// |----------------------------------------------|
69// | Return address for callee |
70// |----------------------------------------------|
71// | Frame pointer for callee |
72// |----------------------------------------------| <- sp
73// | | Lower address
74//
75// To access the data in a frame, at-compile time, a constant offset must be
76// computable from one of the pointers (fp, bp, sp) to access it. The size
77// of the areas with a dotted background cannot be computed at compile-time
78// if they are present, making it required to have all three of fp, bp and
79// sp to be set up to be able to access all contents in the frame areas,
80// assuming all of the frame areas are non-empty.
81//
82// For most functions, some of the frame areas are empty. For those functions,
83// it may not be necessary to set up fp or bp:
84// * A base pointer is definitely needed when there are both VLAs and local
85// variables with more-than-default alignment requirements.
86// * A frame pointer is definitely needed when there are local variables with
87// more-than-default alignment requirements.
88//
89// In addition, VE ABI defines RSA frame, return address, and frame pointer
90// as follows:
91//
92// |----------------------------------------------| <- sp+176
93// | %s18...%s33 |
94// |----------------------------------------------| <- sp+48
95// | Linkage area register (%s17) |
96// |----------------------------------------------| <- sp+40
97// | Procedure linkage table register (%plt=%s16) |
98// |----------------------------------------------| <- sp+32
99// | Global offset table register (%got=%s15) |
100// |----------------------------------------------| <- sp+24
101// | Thread pointer register (%tp=%s14) |
102// |----------------------------------------------| <- sp+16
103// | Return address |
104// |----------------------------------------------| <- sp+8
105// | Frame pointer |
106// |----------------------------------------------| <- sp+0
107//
108// NOTE: This description is based on VE ABI and description in
109// AArch64FrameLowering.cpp. Thanks a lot.
110//===----------------------------------------------------------------------===//
111
112#include "VEFrameLowering.h"
113#include "VEInstrInfo.h"
114#include "VEMachineFunctionInfo.h"
115#include "VESubtarget.h"
116#include "llvm/CodeGen/MachineFrameInfo.h"
117#include "llvm/CodeGen/MachineFunction.h"
118#include "llvm/CodeGen/MachineInstrBuilder.h"
119#include "llvm/CodeGen/MachineModuleInfo.h"
120#include "llvm/CodeGen/MachineRegisterInfo.h"
121#include "llvm/CodeGen/RegisterScavenging.h"
122#include "llvm/IR/DataLayout.h"
123#include "llvm/IR/Function.h"
124#include "llvm/Support/CommandLine.h"
125#include "llvm/Target/TargetOptions.h"
126#include "llvm/Support/MathExtras.h"
127
128using namespace llvm;
129
130VEFrameLowering::VEFrameLowering(const VESubtarget &ST)
131 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(16), 0,
132 Align(16)),
133 STI(ST) {}
134
135void VEFrameLowering::emitPrologueInsns(MachineFunction &MF,
136 MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MBBI,
138 uint64_t NumBytes,
139 bool RequireFPUpdate) const {
140 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
141 DebugLoc DL;
142 const VEInstrInfo &TII = *STI.getInstrInfo();
143
144 // Insert following codes here as prologue
145 //
146 // st %fp, 0(, %sp) iff !isLeafProc
147 // st %lr, 8(, %sp) iff !isLeafProc
148 // st %got, 24(, %sp) iff hasGOT
149 // st %plt, 32(, %sp) iff hasGOT
150 // st %s17, 40(, %sp) iff hasBP
151 if (!FuncInfo->isLeafProc()) {
152 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::STrii))
153 .addReg(RegNo: VE::SX11)
154 .addImm(Val: 0)
155 .addImm(Val: 0)
156 .addReg(RegNo: VE::SX9);
157 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::STrii))
158 .addReg(RegNo: VE::SX11)
159 .addImm(Val: 0)
160 .addImm(Val: 8)
161 .addReg(RegNo: VE::SX10);
162 }
163 if (hasGOT(MF)) {
164 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::STrii))
165 .addReg(RegNo: VE::SX11)
166 .addImm(Val: 0)
167 .addImm(Val: 24)
168 .addReg(RegNo: VE::SX15);
169 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::STrii))
170 .addReg(RegNo: VE::SX11)
171 .addImm(Val: 0)
172 .addImm(Val: 32)
173 .addReg(RegNo: VE::SX16);
174 }
175 if (hasBP(MF))
176 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::STrii))
177 .addReg(RegNo: VE::SX11)
178 .addImm(Val: 0)
179 .addImm(Val: 40)
180 .addReg(RegNo: VE::SX17);
181}
182
183void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF,
184 MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MBBI,
186 uint64_t NumBytes,
187 bool RequireFPUpdate) const {
188 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
189 DebugLoc DL;
190 const VEInstrInfo &TII = *STI.getInstrInfo();
191
192 // Insert following codes here as epilogue
193 //
194 // ld %s17, 40(, %sp) iff hasBP
195 // ld %plt, 32(, %sp) iff hasGOT
196 // ld %got, 24(, %sp) iff hasGOT
197 // ld %lr, 8(, %sp) iff !isLeafProc
198 // ld %fp, 0(, %sp) iff !isLeafProc
199 if (hasBP(MF))
200 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LDrii), DestReg: VE::SX17)
201 .addReg(RegNo: VE::SX11)
202 .addImm(Val: 0)
203 .addImm(Val: 40);
204 if (hasGOT(MF)) {
205 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LDrii), DestReg: VE::SX16)
206 .addReg(RegNo: VE::SX11)
207 .addImm(Val: 0)
208 .addImm(Val: 32);
209 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LDrii), DestReg: VE::SX15)
210 .addReg(RegNo: VE::SX11)
211 .addImm(Val: 0)
212 .addImm(Val: 24);
213 }
214 if (!FuncInfo->isLeafProc()) {
215 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LDrii), DestReg: VE::SX10)
216 .addReg(RegNo: VE::SX11)
217 .addImm(Val: 0)
218 .addImm(Val: 8);
219 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LDrii), DestReg: VE::SX9)
220 .addReg(RegNo: VE::SX11)
221 .addImm(Val: 0)
222 .addImm(Val: 0);
223 }
224}
225
226void VEFrameLowering::emitSPAdjustment(MachineFunction &MF,
227 MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator MBBI,
229 int64_t NumBytes,
230 MaybeAlign MaybeAlign) const {
231 DebugLoc DL;
232 const VEInstrInfo &TII = *STI.getInstrInfo();
233
234 if (NumBytes == 0) {
235 // Nothing to do here.
236 } else if (isInt<7>(x: NumBytes)) {
237 // adds.l %s11, NumBytes@lo, %s11
238 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::ADDSLri), DestReg: VE::SX11)
239 .addReg(RegNo: VE::SX11)
240 .addImm(Val: NumBytes);
241 } else if (isInt<32>(x: NumBytes)) {
242 // lea %s11, NumBytes@lo(, %s11)
243 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LEArii), DestReg: VE::SX11)
244 .addReg(RegNo: VE::SX11)
245 .addImm(Val: 0)
246 .addImm(Val: Lo_32(Value: NumBytes));
247 } else {
248 // Emit following codes. This clobbers SX13 which we always know is
249 // available here.
250 // lea %s13, NumBytes@lo
251 // and %s13, %s13, (32)0
252 // lea.sl %sp, NumBytes@hi(%s13, %sp)
253 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LEAzii), DestReg: VE::SX13)
254 .addImm(Val: 0)
255 .addImm(Val: 0)
256 .addImm(Val: Lo_32(Value: NumBytes));
257 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::ANDrm), DestReg: VE::SX13)
258 .addReg(RegNo: VE::SX13)
259 .addImm(Val: M0(Val: 32));
260 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::LEASLrri), DestReg: VE::SX11)
261 .addReg(RegNo: VE::SX11)
262 .addReg(RegNo: VE::SX13)
263 .addImm(Val: Hi_32(Value: NumBytes));
264 }
265
266 if (MaybeAlign) {
267 // and %sp, %sp, Align-1
268 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::ANDrm), DestReg: VE::SX11)
269 .addReg(RegNo: VE::SX11)
270 .addImm(Val: M1(Val: 64 - Log2_64(Value: MaybeAlign.valueOrOne().value())));
271 }
272}
273
274void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,
275 MachineBasicBlock::iterator MBBI) const {
276 DebugLoc DL;
277 const VEInstrInfo &TII = *STI.getInstrInfo();
278
279 // Emit following codes. It is not possible to insert multiple
280 // BasicBlocks in PEI pass, so we emit two pseudo instructions here.
281 //
282 // EXTEND_STACK // pseudo instrcution
283 // EXTEND_STACK_GUARD // pseudo instrcution
284 //
285 // EXTEND_STACK pseudo will be converted by ExpandPostRA pass into
286 // following instructions with multiple basic blocks later.
287 //
288 // thisBB:
289 // brge.l.t %sp, %sl, sinkBB
290 // syscallBB:
291 // ld %s61, 0x18(, %tp) // load param area
292 // or %s62, 0, %s0 // spill the value of %s0
293 // lea %s63, 0x13b // syscall # of grow
294 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0
295 // shm.l %sl, 0x8(%s61) // store old limit at addr:8
296 // shm.l %sp, 0x10(%s61) // store new limit at addr:16
297 // monc // call monitor
298 // or %s0, 0, %s62 // restore the value of %s0
299 // sinkBB:
300 //
301 // EXTEND_STACK_GUARD pseudo will be simply eliminated by ExpandPostRA
302 // pass. This pseudo is required to be at the next of EXTEND_STACK
303 // pseudo in order to protect iteration loop in ExpandPostRA.
304 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::EXTEND_STACK));
305 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::EXTEND_STACK_GUARD));
306}
307
308void VEFrameLowering::emitPrologue(MachineFunction &MF,
309 MachineBasicBlock &MBB) const {
310 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
311 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
312 MachineFrameInfo &MFI = MF.getFrameInfo();
313 const VEInstrInfo &TII = *STI.getInstrInfo();
314 const VERegisterInfo &RegInfo = *STI.getRegisterInfo();
315 MachineBasicBlock::iterator MBBI = MBB.begin();
316 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF);
317
318 // Debug location must be unknown since the first debug location is used
319 // to determine the end of the prologue.
320 DebugLoc DL;
321
322 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF))
323 report_fatal_error(reason: "Function \"" + Twine(MF.getName()) +
324 "\" required "
325 "stack re-alignment, but LLVM couldn't handle it "
326 "(probably because it has a dynamic alloca).");
327
328 // Get the number of bytes to allocate from the FrameInfo.
329 // This number of bytes is already aligned to ABI stack alignment.
330 uint64_t NumBytes = MFI.getStackSize();
331
332 // Adjust stack size if this function is not a leaf function since the
333 // VE ABI requires a reserved area at the top of stack as described in
334 // VEFrameLowering.cpp.
335 if (!FuncInfo->isLeafProc()) {
336 // NOTE: The number is aligned to ABI stack alignment after adjustment.
337 NumBytes = STI.getAdjustedFrameSize(FrameSize: NumBytes);
338 }
339
340 // Finally, ensure that the size is sufficiently aligned for the
341 // data on the stack.
342 NumBytes = alignTo(Size: NumBytes, A: MFI.getMaxAlign());
343
344 // Update stack size with corrected value.
345 MFI.setStackSize(NumBytes);
346
347 // Emit Prologue instructions to save multiple registers.
348 emitPrologueInsns(MF, MBB, MBBI, NumBytes, RequireFPUpdate: true);
349
350 // Emit instructions to save SP in FP as follows if this is not a leaf
351 // function:
352 // or %fp, 0, %sp
353 if (!FuncInfo->isLeafProc())
354 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::ORri), DestReg: VE::SX9)
355 .addReg(RegNo: VE::SX11)
356 .addImm(Val: 0);
357
358 // Emit stack adjust instructions
359 MaybeAlign RuntimeAlign =
360 NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : std::nullopt;
361 assert((RuntimeAlign == std::nullopt || !FuncInfo->isLeafProc()) &&
362 "SP has to be saved in order to align variable sized stack object!");
363 emitSPAdjustment(MF, MBB, MBBI, NumBytes: -(int64_t)NumBytes, MaybeAlign: RuntimeAlign);
364
365 if (hasBP(MF)) {
366 // Copy SP to BP.
367 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::ORri), DestReg: VE::SX17)
368 .addReg(RegNo: VE::SX11)
369 .addImm(Val: 0);
370 }
371
372 // Emit stack extend instructions
373 if (NumBytes != 0)
374 emitSPExtend(MF, MBB, MBBI);
375}
376
377MachineBasicBlock::iterator VEFrameLowering::eliminateCallFramePseudoInstr(
378 MachineFunction &MF, MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator I) const {
380 if (!hasReservedCallFrame(MF)) {
381 MachineInstr &MI = *I;
382 int64_t Size = MI.getOperand(i: 0).getImm();
383 if (MI.getOpcode() == VE::ADJCALLSTACKDOWN)
384 Size = -Size;
385
386 if (Size)
387 emitSPAdjustment(MF, MBB, MBBI: I, NumBytes: Size);
388 }
389 return MBB.erase(I);
390}
391
392void VEFrameLowering::emitEpilogue(MachineFunction &MF,
393 MachineBasicBlock &MBB) const {
394 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
395 DebugLoc DL;
396 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
397 MachineFrameInfo &MFI = MF.getFrameInfo();
398 const VEInstrInfo &TII = *STI.getInstrInfo();
399
400 uint64_t NumBytes = MFI.getStackSize();
401
402 // Emit instructions to retrieve original SP.
403 if (!FuncInfo->isLeafProc()) {
404 // If SP is saved in FP, retrieve it as follows:
405 // or %sp, 0, %fp iff !isLeafProc
406 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: VE::ORri), DestReg: VE::SX11)
407 .addReg(RegNo: VE::SX9)
408 .addImm(Val: 0);
409 } else {
410 // Emit stack adjust instructions.
411 emitSPAdjustment(MF, MBB, MBBI, NumBytes, MaybeAlign: std::nullopt);
412 }
413
414 // Emit Epilogue instructions to restore multiple registers.
415 emitEpilogueInsns(MF, MBB, MBBI, NumBytes, RequireFPUpdate: true);
416}
417
418// hasFP - Return true if the specified function should have a dedicated frame
419// pointer register. This is true if the function has variable sized allocas
420// or if frame pointer elimination is disabled.
421bool VEFrameLowering::hasFP(const MachineFunction &MF) const {
422 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
423
424 const MachineFrameInfo &MFI = MF.getFrameInfo();
425 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
426 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
427 MFI.isFrameAddressTaken();
428}
429
430bool VEFrameLowering::hasBP(const MachineFunction &MF) const {
431 const MachineFrameInfo &MFI = MF.getFrameInfo();
432 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
433
434 return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);
435}
436
437bool VEFrameLowering::hasGOT(const MachineFunction &MF) const {
438 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
439
440 // If a global base register is assigned (!= 0), GOT is used.
441 return FuncInfo->getGlobalBaseReg() != 0;
442}
443
444StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
445 int FI,
446 Register &FrameReg) const {
447 const MachineFrameInfo &MFI = MF.getFrameInfo();
448 const VERegisterInfo *RegInfo = STI.getRegisterInfo();
449 bool isFixed = MFI.isFixedObjectIndex(ObjectIdx: FI);
450
451 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(ObjectIdx: FI);
452
453 if (!hasFP(MF)) {
454 // If FP is not used, frame indexies are based on a %sp regiter.
455 FrameReg = VE::SX11; // %sp
456 return StackOffset::getFixed(Fixed: FrameOffset +
457 MF.getFrameInfo().getStackSize());
458 }
459 if (RegInfo->hasStackRealignment(MF) && !isFixed) {
460 // If data on stack require realignemnt, frame indexies are based on a %sp
461 // or %s17 (bp) register. If there is a variable sized object, bp is used.
462 if (hasBP(MF))
463 FrameReg = VE::SX17; // %bp
464 else
465 FrameReg = VE::SX11; // %sp
466 return StackOffset::getFixed(Fixed: FrameOffset +
467 MF.getFrameInfo().getStackSize());
468 }
469 // Use %fp by default.
470 FrameReg = RegInfo->getFrameRegister(MF);
471 return StackOffset::getFixed(Fixed: FrameOffset);
472}
473
474bool VEFrameLowering::isLeafProc(MachineFunction &MF) const {
475
476 MachineRegisterInfo &MRI = MF.getRegInfo();
477 MachineFrameInfo &MFI = MF.getFrameInfo();
478
479 return !MFI.hasCalls() // No calls
480 && !MRI.isPhysRegUsed(PhysReg: VE::SX18) // Registers within limits
481 // (s18 is first CSR)
482 && !MRI.isPhysRegUsed(PhysReg: VE::SX11) // %sp un-used
483 && !hasFP(MF); // Don't need %fp
484}
485
486void VEFrameLowering::determineCalleeSaves(MachineFunction &MF,
487 BitVector &SavedRegs,
488 RegScavenger *RS) const {
489 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
490
491 // Functions having BP need to emit prologue and epilogue to allocate local
492 // buffer on the stack even if the function is a leaf function.
493 if (isLeafProc(MF) && !hasBP(MF)) {
494 VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
495 FuncInfo->setLeafProc(true);
496 }
497}
498