1//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
14#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
15
16#include "llvm/CodeGen/TargetRegisterInfo.h"
17
18#define GET_REGINFO_HEADER
19#include "X86GenRegisterInfo.inc"
20
21namespace llvm {
22 class Triple;
23
24class X86RegisterInfo final : public X86GenRegisterInfo {
25private:
26 /// Is64Bit - Is the target 64-bits.
27 ///
28 bool Is64Bit;
29
30 /// IsWin64 - Is the target on of win64 flavours
31 ///
32 bool IsWin64;
33
34 /// SlotSize - Stack slot size in bytes.
35 ///
36 unsigned SlotSize;
37
38 /// StackPtr - X86 physical register used as stack ptr.
39 ///
40 unsigned StackPtr;
41
42 /// FramePtr - X86 physical register used as frame ptr.
43 ///
44 unsigned FramePtr;
45
46 /// BasePtr - X86 physical register used as a base ptr in complex stack
47 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
48 /// variable size stack objects.
49 unsigned BasePtr;
50
51public:
52 explicit X86RegisterInfo(const Triple &TT);
53
54 /// Return the number of registers for the function.
55 unsigned getNumSupportedRegs(const MachineFunction &MF) const override;
56
57 // FIXME: This should be tablegen'd like getDwarfRegNum is
58 int getSEHRegNum(unsigned i) const;
59
60 /// getMatchingSuperRegClass - Return a subclass of the specified register
61 /// class A so that each register in it has a sub-register of the
62 /// specified sub-register index which is in the specified register class B.
63 const TargetRegisterClass *
64 getMatchingSuperRegClass(const TargetRegisterClass *A,
65 const TargetRegisterClass *B,
66 unsigned Idx) const override;
67
68 const TargetRegisterClass *
69 getSubClassWithSubReg(const TargetRegisterClass *RC,
70 unsigned Idx) const override;
71
72 const TargetRegisterClass *
73 getLargestLegalSuperClass(const TargetRegisterClass *RC,
74 const MachineFunction &MF) const override;
75
76 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
77 unsigned DefSubReg,
78 const TargetRegisterClass *SrcRC,
79 unsigned SrcSubReg) const override;
80
81 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
82 /// values.
83 const TargetRegisterClass *
84 getPointerRegClass(const MachineFunction &MF,
85 unsigned Kind = 0) const override;
86
87 /// getCrossCopyRegClass - Returns a legal register class to copy a register
88 /// in the specified class to or from. Returns NULL if it is possible to copy
89 /// between a two registers of the specified class.
90 const TargetRegisterClass *
91 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
92
93 /// getGPRsForTailCall - Returns a register class with registers that can be
94 /// used in forming tail calls.
95 const TargetRegisterClass *
96 getGPRsForTailCall(const MachineFunction &MF) const;
97
98 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
99 MachineFunction &MF) const override;
100
101 /// getCalleeSavedRegs - Return a null-terminated list of all of the
102 /// callee-save registers on this target.
103 const MCPhysReg *
104 getCalleeSavedRegs(const MachineFunction* MF) const override;
105 const MCPhysReg *
106 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
107 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
108 CallingConv::ID) const override;
109 const uint32_t *getNoPreservedMask() const override;
110
111 // Calls involved in thread-local variable lookup save more registers than
112 // normal calls, so they need a different mask to represent this.
113 const uint32_t *getDarwinTLSCallPreservedMask() const;
114
115 /// getReservedRegs - Returns a bitset indexed by physical register number
116 /// indicating if a register is a special register that has particular uses and
117 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
118 /// register scavenger to determine what registers are free.
119 BitVector getReservedRegs(const MachineFunction &MF) const override;
120
121 /// isArgumentReg - Returns true if Reg can be used as an argument to a
122 /// function.
123 bool isArgumentRegister(const MachineFunction &MF,
124 MCRegister Reg) const override;
125
126 /// Return true if it is tile register class.
127 bool isTileRegisterClass(const TargetRegisterClass *RC) const;
128
129 /// Returns true if PhysReg is a fixed register.
130 bool isFixedRegister(const MachineFunction &MF,
131 MCRegister PhysReg) const override;
132
133 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
134
135 bool hasBasePointer(const MachineFunction &MF) const;
136
137 bool canRealignStack(const MachineFunction &MF) const override;
138
139 bool shouldRealignStack(const MachineFunction &MF) const override;
140
141 void eliminateFrameIndex(MachineBasicBlock::iterator II,
142 unsigned FIOperandNum, Register BaseReg,
143 int FIOffset) const;
144
145 bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
146 int SPAdj, unsigned FIOperandNum,
147 RegScavenger *RS = nullptr) const override;
148
149 /// Process frame indices in forwards block order because
150 /// X86InstrInfo::getSPAdjust relies on it when searching for the
151 /// ADJCALLSTACKUP pseudo following a call.
152 /// TODO: Fix this and return true like all other targets.
153 bool eliminateFrameIndicesBackwards() const override { return false; }
154
155 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
156 /// when it reaches the "return" instruction. We can then pop a stack object
157 /// to this register without worry about clobbering it.
158 unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator &MBBI) const;
160
161 // Debug information queries.
162 Register getFrameRegister(const MachineFunction &MF) const override;
163 unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
164 unsigned getPtrSizedStackRegister(const MachineFunction &MF) const;
165 Register getStackRegister() const { return StackPtr; }
166 Register getBaseRegister() const { return BasePtr; }
167 /// Returns physical register used as frame pointer.
168 /// This will always returns the frame pointer register, contrary to
169 /// getFrameRegister() which returns the "base pointer" in situations
170 /// involving a stack, frame and base pointer.
171 Register getFramePtr() const { return FramePtr; }
172 // FIXME: Move to FrameInfok
173 unsigned getSlotSize() const { return SlotSize; }
174
175 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
176 SmallVectorImpl<MCPhysReg> &Hints,
177 const MachineFunction &MF, const VirtRegMap *VRM,
178 const LiveRegMatrix *Matrix) const override;
179};
180
181} // End llvm namespace
182
183#endif
184