1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
23 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
24bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
25 MVT LocVT, CCValAssign::LocInfo LocInfo,
26 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
27bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
28 MVT LocVT, CCValAssign::LocInfo LocInfo,
29 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
30bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
31 MVT LocVT, CCValAssign::LocInfo LocInfo,
32 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
33bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
34 MVT LocVT, CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
36bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
37 MVT LocVT, CCValAssign::LocInfo LocInfo,
38 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
39bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
40 MVT LocVT, CCValAssign::LocInfo LocInfo,
41 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
42bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
43 MVT LocVT, CCValAssign::LocInfo LocInfo,
44 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
45bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
46 MVT LocVT, CCValAssign::LocInfo LocInfo,
47 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
48bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
49 MVT LocVT, CCValAssign::LocInfo LocInfo,
50 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
51bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
52 MVT LocVT, CCValAssign::LocInfo LocInfo,
53 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
54bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
55 MVT LocVT, CCValAssign::LocInfo LocInfo,
56 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
57bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
58 MVT LocVT, CCValAssign::LocInfo LocInfo,
59 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
60
61
62bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
65
66 if (ArgFlags.isNest()) {
67 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
68 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
69 return false;
70 }
71 }
72
73 if (LocVT == MVT::iPTR) {
74 LocVT = MVT::i64;
75 LocInfo = CCValAssign::BCvt;
76 }
77
78 if (LocVT == MVT::v2f32) {
79 LocVT = MVT::v2i32;
80 LocInfo = CCValAssign::BCvt;
81 }
82
83 if (LocVT == MVT::v2f64 ||
84 LocVT == MVT::v4f32) {
85 LocVT = MVT::v2i64;
86 LocInfo = CCValAssign::BCvt;
87 }
88
89 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
90 if (LocVT == MVT::v2i32 ||
91 LocVT == MVT::v2f32 ||
92 LocVT == MVT::v4i16 ||
93 LocVT == MVT::v4f16 ||
94 LocVT == MVT::v4bf16 ||
95 LocVT == MVT::v8i8) {
96 LocVT = MVT::f64;
97 LocInfo = CCValAssign::BCvt;
98 }
99 }
100
101 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
102 if (LocVT == MVT::v2i64 ||
103 LocVT == MVT::v2f64 ||
104 LocVT == MVT::v4i32 ||
105 LocVT == MVT::v4f32 ||
106 LocVT == MVT::v8i16 ||
107 LocVT == MVT::v8f16 ||
108 LocVT == MVT::v8bf16 ||
109 LocVT == MVT::v16i8) {
110 LocVT = MVT::f128;
111 LocInfo = CCValAssign::BCvt;
112 }
113 }
114
115 if (ArgFlags.isInReg()) {
116 if (LocVT == MVT::i64) {
117 if (ArgFlags.isSRet()) {
118 if (LocVT == MVT::i64) {
119 static const MCPhysReg RegList1[] = {
120 AArch64::X0, AArch64::X1
121 };
122 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
123 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
124 return false;
125 }
126 }
127 }
128 }
129 }
130
131 if (ArgFlags.isSRet()) {
132 if (LocVT == MVT::i64) {
133 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
134 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
135 return false;
136 }
137 }
138 }
139
140 if (ArgFlags.isByVal()) {
141 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
142 return false;
143 }
144
145 if (ArgFlags.isSwiftSelf()) {
146 if (LocVT == MVT::i64) {
147 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
148 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
149 return false;
150 }
151 }
152 }
153
154 if (ArgFlags.isSwiftError()) {
155 if (LocVT == MVT::i64) {
156 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
157 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
158 return false;
159 }
160 }
161 }
162
163 if (ArgFlags.isSwiftAsync()) {
164 if (LocVT == MVT::i64) {
165 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
166 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
167 return false;
168 }
169 }
170 }
171
172 if (ArgFlags.isInConsecutiveRegs()) {
173 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
174 return false;
175 }
176
177 if (LocVT == MVT::nxv16i8 ||
178 LocVT == MVT::nxv8i16 ||
179 LocVT == MVT::nxv4i32 ||
180 LocVT == MVT::nxv2i64 ||
181 LocVT == MVT::nxv2f16 ||
182 LocVT == MVT::nxv4f16 ||
183 LocVT == MVT::nxv8f16 ||
184 LocVT == MVT::nxv2bf16 ||
185 LocVT == MVT::nxv4bf16 ||
186 LocVT == MVT::nxv8bf16 ||
187 LocVT == MVT::nxv2f32 ||
188 LocVT == MVT::nxv4f32 ||
189 LocVT == MVT::nxv2f64) {
190 static const MCPhysReg RegList2[] = {
191 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
192 };
193 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
194 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
195 return false;
196 }
197 }
198
199 if (LocVT == MVT::nxv16i8 ||
200 LocVT == MVT::nxv8i16 ||
201 LocVT == MVT::nxv4i32 ||
202 LocVT == MVT::nxv2i64 ||
203 LocVT == MVT::nxv2f16 ||
204 LocVT == MVT::nxv4f16 ||
205 LocVT == MVT::nxv8f16 ||
206 LocVT == MVT::nxv2bf16 ||
207 LocVT == MVT::nxv4bf16 ||
208 LocVT == MVT::nxv8bf16 ||
209 LocVT == MVT::nxv2f32 ||
210 LocVT == MVT::nxv4f32 ||
211 LocVT == MVT::nxv2f64) {
212 LocVT = MVT::i64;
213 LocInfo = CCValAssign::Indirect;
214 }
215
216 if (LocVT == MVT::nxv1i1 ||
217 LocVT == MVT::nxv2i1 ||
218 LocVT == MVT::nxv4i1 ||
219 LocVT == MVT::nxv8i1 ||
220 LocVT == MVT::nxv16i1 ||
221 LocVT == MVT::aarch64svcount) {
222 static const MCPhysReg RegList3[] = {
223 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
224 };
225 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
226 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
227 return false;
228 }
229 }
230
231 if (LocVT == MVT::nxv1i1 ||
232 LocVT == MVT::nxv2i1 ||
233 LocVT == MVT::nxv4i1 ||
234 LocVT == MVT::nxv8i1 ||
235 LocVT == MVT::nxv16i1 ||
236 LocVT == MVT::aarch64svcount) {
237 LocVT = MVT::i64;
238 LocInfo = CCValAssign::Indirect;
239 }
240
241 if (LocVT == MVT::i1 ||
242 LocVT == MVT::i8 ||
243 LocVT == MVT::i16) {
244 LocVT = MVT::i32;
245 if (ArgFlags.isSExt())
246 LocInfo = CCValAssign::SExt;
247 else if (ArgFlags.isZExt())
248 LocInfo = CCValAssign::ZExt;
249 else
250 LocInfo = CCValAssign::AExt;
251 }
252
253 if (LocVT == MVT::i32) {
254 static const MCPhysReg RegList4[] = {
255 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
256 };
257 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
258 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
259 return false;
260 }
261 }
262
263 if (LocVT == MVT::i64) {
264 if (ArgFlags.isSplit()) {
265 static const MCPhysReg RegList5[] = {
266 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
267 };
268 static const MCPhysReg RegList6[] = {
269 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
270 };
271 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
272 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
273 return false;
274 }
275 }
276 }
277
278 if (LocVT == MVT::i64) {
279 if (ArgFlags.isSplit()) {
280 static const MCPhysReg ShadowRegList7[] = {
281 AArch64::X7
282 };
283 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
284 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
285 return false;
286 }
287 }
288
289 if (LocVT == MVT::i64) {
290 static const MCPhysReg RegList9[] = {
291 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
292 };
293 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
294 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
295 return false;
296 }
297 }
298
299 if (LocVT == MVT::f16) {
300 static const MCPhysReg RegList10[] = {
301 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
302 };
303 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
304 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
305 return false;
306 }
307 }
308
309 if (LocVT == MVT::bf16) {
310 static const MCPhysReg RegList11[] = {
311 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
312 };
313 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
314 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
315 return false;
316 }
317 }
318
319 if (LocVT == MVT::f32) {
320 static const MCPhysReg RegList12[] = {
321 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
322 };
323 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
324 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
325 return false;
326 }
327 }
328
329 if (LocVT == MVT::f64) {
330 static const MCPhysReg RegList13[] = {
331 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
332 };
333 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
334 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
335 return false;
336 }
337 }
338
339 if (LocVT == MVT::v1i64 ||
340 LocVT == MVT::v2i32 ||
341 LocVT == MVT::v4i16 ||
342 LocVT == MVT::v8i8 ||
343 LocVT == MVT::v1f64 ||
344 LocVT == MVT::v2f32 ||
345 LocVT == MVT::v4f16 ||
346 LocVT == MVT::v4bf16) {
347 static const MCPhysReg RegList14[] = {
348 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
349 };
350 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
351 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
352 return false;
353 }
354 }
355
356 if (LocVT == MVT::f128 ||
357 LocVT == MVT::v2i64 ||
358 LocVT == MVT::v4i32 ||
359 LocVT == MVT::v8i16 ||
360 LocVT == MVT::v16i8 ||
361 LocVT == MVT::v4f32 ||
362 LocVT == MVT::v2f64 ||
363 LocVT == MVT::v8f16 ||
364 LocVT == MVT::v8bf16) {
365 static const MCPhysReg RegList15[] = {
366 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
367 };
368 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
369 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
370 return false;
371 }
372 }
373
374 if (LocVT == MVT::i1 ||
375 LocVT == MVT::i8 ||
376 LocVT == MVT::i16 ||
377 LocVT == MVT::f16 ||
378 LocVT == MVT::bf16) {
379 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
380 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
381 return false;
382 }
383
384 if (LocVT == MVT::i32 ||
385 LocVT == MVT::f32) {
386 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
387 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
388 return false;
389 }
390
391 if (LocVT == MVT::i64 ||
392 LocVT == MVT::f64 ||
393 LocVT == MVT::v1f64 ||
394 LocVT == MVT::v2f32 ||
395 LocVT == MVT::v1i64 ||
396 LocVT == MVT::v2i32 ||
397 LocVT == MVT::v4i16 ||
398 LocVT == MVT::v8i8 ||
399 LocVT == MVT::v4f16 ||
400 LocVT == MVT::v4bf16) {
401 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
402 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
403 return false;
404 }
405
406 if (LocVT == MVT::f128 ||
407 LocVT == MVT::v2i64 ||
408 LocVT == MVT::v4i32 ||
409 LocVT == MVT::v8i16 ||
410 LocVT == MVT::v16i8 ||
411 LocVT == MVT::v4f32 ||
412 LocVT == MVT::v2f64 ||
413 LocVT == MVT::v8f16 ||
414 LocVT == MVT::v8bf16) {
415 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
416 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
417 return false;
418 }
419
420 return true; // CC didn't match.
421}
422
423
424bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
425 MVT LocVT, CCValAssign::LocInfo LocInfo,
426 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
427
428 if (LocVT == MVT::i64) {
429 static const MCPhysReg RegList1[] = {
430 AArch64::X11, AArch64::X10, AArch64::X9
431 };
432 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
433 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
434 return false;
435 }
436 }
437
438 return true; // CC didn't match.
439}
440
441
442bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
443 MVT LocVT, CCValAssign::LocInfo LocInfo,
444 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
445
446 if (ArgFlags.isInReg()) {
447 if (LocVT == MVT::i64) {
448 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
449 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
450 return false;
451 }
452 }
453 }
454
455 if (ArgFlags.isByVal()) {
456 LocVT = MVT::i64;
457 LocInfo = CCValAssign::Indirect;
458 }
459
460 if (LocVT == MVT::i1 ||
461 LocVT == MVT::i8 ||
462 LocVT == MVT::i16) {
463 LocVT = MVT::i32;
464 if (ArgFlags.isSExt())
465 LocInfo = CCValAssign::SExt;
466 else if (ArgFlags.isZExt())
467 LocInfo = CCValAssign::ZExt;
468 else
469 LocInfo = CCValAssign::AExt;
470 }
471
472 if (ArgFlags.isNest()) {
473 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
474 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
475 return false;
476 }
477 }
478
479 if (ArgFlags.isSwiftError()) {
480 if (LocVT == MVT::i64) {
481 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
482 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
483 return false;
484 }
485 }
486 }
487
488 if (ArgFlags.isSwiftSelf()) {
489 if (LocVT == MVT::i64) {
490 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
491 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
492 return false;
493 }
494 }
495 }
496
497 if (ArgFlags.isSwiftAsync()) {
498 if (LocVT == MVT::i64) {
499 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
500 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
501 return false;
502 }
503 }
504 }
505
506 if (ArgFlags.isCFGuardTarget()) {
507 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
508 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
509 return false;
510 }
511 }
512
513 if (LocVT == MVT::v16i8 ||
514 LocVT == MVT::v8i16 ||
515 LocVT == MVT::v4i32 ||
516 LocVT == MVT::v2i64 ||
517 LocVT == MVT::v8f16 ||
518 LocVT == MVT::v4f32 ||
519 LocVT == MVT::v2f64) {
520 LocVT = MVT::i64;
521 LocInfo = CCValAssign::Indirect;
522 }
523
524 if (LocVT == MVT::v32i8 ||
525 LocVT == MVT::v16i16 ||
526 LocVT == MVT::v8i32 ||
527 LocVT == MVT::v4i64 ||
528 LocVT == MVT::v16f16 ||
529 LocVT == MVT::v8f32 ||
530 LocVT == MVT::v4f64) {
531 LocVT = MVT::i64;
532 LocInfo = CCValAssign::Indirect;
533 }
534
535 if (LocVT == MVT::v64i8 ||
536 LocVT == MVT::v32i16 ||
537 LocVT == MVT::v16i32 ||
538 LocVT == MVT::v32f16 ||
539 LocVT == MVT::v16f32 ||
540 LocVT == MVT::v8f64 ||
541 LocVT == MVT::v8i64) {
542 LocVT = MVT::i64;
543 LocInfo = CCValAssign::Indirect;
544 }
545
546 if (LocVT == MVT::f80) {
547 LocVT = MVT::i64;
548 LocInfo = CCValAssign::Indirect;
549 }
550
551 if (LocVT == MVT::x86mmx) {
552 LocVT = MVT::i64;
553 LocInfo = CCValAssign::BCvt;
554 }
555
556 if (LocVT == MVT::f16) {
557 static const MCPhysReg RegList1[] = {
558 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
559 };
560 static const MCPhysReg RegList2[] = {
561 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
562 };
563 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
564 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
565 return false;
566 }
567 }
568
569 if (LocVT == MVT::bf16) {
570 static const MCPhysReg RegList3[] = {
571 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
572 };
573 static const MCPhysReg RegList4[] = {
574 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
575 };
576 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
577 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
578 return false;
579 }
580 }
581
582 if (LocVT == MVT::f32) {
583 static const MCPhysReg RegList5[] = {
584 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3
585 };
586 static const MCPhysReg RegList6[] = {
587 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
588 };
589 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
590 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
591 return false;
592 }
593 }
594
595 if (LocVT == MVT::f64) {
596 static const MCPhysReg RegList7[] = {
597 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3
598 };
599 static const MCPhysReg RegList8[] = {
600 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
601 };
602 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
603 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
604 return false;
605 }
606 }
607
608 if (LocVT == MVT::i32) {
609 static const MCPhysReg RegList9[] = {
610 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
611 };
612 static const MCPhysReg RegList10[] = {
613 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
614 };
615 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
616 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
617 return false;
618 }
619 }
620
621 if (LocVT == MVT::i64) {
622 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
623 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
624 return false;
625 }
626 }
627
628 if (LocVT == MVT::i64) {
629 static const MCPhysReg RegList11[] = {
630 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
631 };
632 static const MCPhysReg RegList12[] = {
633 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
634 };
635 if (MCRegister Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
636 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
637 return false;
638 }
639 }
640
641 if (LocVT == MVT::i8 ||
642 LocVT == MVT::i16 ||
643 LocVT == MVT::i32 ||
644 LocVT == MVT::i64 ||
645 LocVT == MVT::f16 ||
646 LocVT == MVT::bf16 ||
647 LocVT == MVT::f32 ||
648 LocVT == MVT::f64) {
649 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
650 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
651 return false;
652 }
653
654 return true; // CC didn't match.
655}
656
657
658bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
659 MVT LocVT, CCValAssign::LocInfo LocInfo,
660 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
661
662 if (LocVT == MVT::i64) {
663 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
664 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
665 return false;
666 }
667 }
668
669 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
670 return false;
671
672 return true; // CC didn't match.
673}
674
675
676bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
677 MVT LocVT, CCValAssign::LocInfo LocInfo,
678 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
679
680 if (ArgFlags.isCFGuardTarget()) {
681 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
682 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
683 return false;
684 }
685 }
686
687 if (ArgFlags.isNest()) {
688 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
689 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
690 return false;
691 }
692 }
693
694 if (LocVT == MVT::f16 ||
695 LocVT == MVT::bf16) {
696 LocVT = MVT::i16;
697 LocInfo = CCValAssign::BCvt;
698 }
699
700 if (LocVT == MVT::f32) {
701 LocVT = MVT::i32;
702 LocInfo = CCValAssign::BCvt;
703 }
704
705 if (LocVT == MVT::f64 ||
706 LocVT == MVT::v1f64 ||
707 LocVT == MVT::v1i64 ||
708 LocVT == MVT::v2f32 ||
709 LocVT == MVT::v2i32 ||
710 LocVT == MVT::v4i16 ||
711 LocVT == MVT::v4f16 ||
712 LocVT == MVT::v4bf16 ||
713 LocVT == MVT::v8i8 ||
714 LocVT == MVT::iPTR) {
715 LocVT = MVT::i64;
716 LocInfo = CCValAssign::BCvt;
717 }
718
719 if (LocVT == MVT::f128 ||
720 LocVT == MVT::v2f64 ||
721 LocVT == MVT::v2i64 ||
722 LocVT == MVT::v4i32 ||
723 LocVT == MVT::v4f32 ||
724 LocVT == MVT::v8i16 ||
725 LocVT == MVT::v8f16 ||
726 LocVT == MVT::v8bf16 ||
727 LocVT == MVT::v16i8) {
728 LocVT = MVT::i64;
729 LocInfo = CCValAssign::Indirect;
730 }
731
732 if (LocVT == MVT::nxv16i8 ||
733 LocVT == MVT::nxv8i16 ||
734 LocVT == MVT::nxv4i32 ||
735 LocVT == MVT::nxv2i64 ||
736 LocVT == MVT::nxv2f16 ||
737 LocVT == MVT::nxv4f16 ||
738 LocVT == MVT::nxv8f16 ||
739 LocVT == MVT::nxv2bf16 ||
740 LocVT == MVT::nxv4bf16 ||
741 LocVT == MVT::nxv8bf16 ||
742 LocVT == MVT::nxv2f32 ||
743 LocVT == MVT::nxv4f32 ||
744 LocVT == MVT::nxv2f64) {
745 LocVT = MVT::i64;
746 LocInfo = CCValAssign::Indirect;
747 }
748
749 if (LocVT == MVT::nxv2i1 ||
750 LocVT == MVT::nxv4i1 ||
751 LocVT == MVT::nxv8i1 ||
752 LocVT == MVT::nxv16i1) {
753 LocVT = MVT::i64;
754 LocInfo = CCValAssign::Indirect;
755 }
756
757 if (ArgFlags.isInReg()) {
758 if (LocVT == MVT::i64) {
759 if (ArgFlags.isSRet()) {
760 if (LocVT == MVT::i64) {
761 static const MCPhysReg RegList1[] = {
762 AArch64::X0, AArch64::X1
763 };
764 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
765 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
766 return false;
767 }
768 }
769 }
770 }
771 }
772
773 if (ArgFlags.isSRet()) {
774 if (LocVT == MVT::i64) {
775 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
776 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
777 return false;
778 }
779 }
780 }
781
782 if (ArgFlags.isByVal()) {
783 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
784 return false;
785 }
786
787 if (LocVT == MVT::i1 ||
788 LocVT == MVT::i8 ||
789 LocVT == MVT::i16) {
790 LocVT = MVT::i32;
791 if (ArgFlags.isSExt())
792 LocInfo = CCValAssign::SExt;
793 else if (ArgFlags.isZExt())
794 LocInfo = CCValAssign::ZExt;
795 else
796 LocInfo = CCValAssign::AExt;
797 }
798
799 if (LocVT == MVT::i32) {
800 static const MCPhysReg RegList2[] = {
801 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
802 };
803 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
804 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
805 return false;
806 }
807 }
808
809 if (LocVT == MVT::i64) {
810 static const MCPhysReg RegList3[] = {
811 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
812 };
813 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
814 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
815 return false;
816 }
817 }
818
819 if (LocVT == MVT::i32 ||
820 LocVT == MVT::i64) {
821 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
822 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
823 return false;
824 }
825
826 return true; // CC didn't match.
827}
828
829
830bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
831 MVT LocVT, CCValAssign::LocInfo LocInfo,
832 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
833
834 if (ArgFlags.isNest()) {
835 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
836 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
837 return false;
838 }
839 }
840
841 if (LocVT == MVT::iPTR) {
842 LocVT = MVT::i64;
843 LocInfo = CCValAssign::BCvt;
844 }
845
846 if (LocVT == MVT::v2f32) {
847 LocVT = MVT::v2i32;
848 LocInfo = CCValAssign::BCvt;
849 }
850
851 if (LocVT == MVT::v2f64 ||
852 LocVT == MVT::v4f32 ||
853 LocVT == MVT::f128) {
854 LocVT = MVT::v2i64;
855 LocInfo = CCValAssign::BCvt;
856 }
857
858 if (ArgFlags.isSRet()) {
859 if (LocVT == MVT::i64) {
860 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
861 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
862 return false;
863 }
864 }
865 }
866
867 if (ArgFlags.isByVal()) {
868 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
869 return false;
870 }
871
872 if (ArgFlags.isSwiftSelf()) {
873 if (LocVT == MVT::i64) {
874 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
875 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
876 return false;
877 }
878 }
879 }
880
881 if (ArgFlags.isSwiftError()) {
882 if (LocVT == MVT::i64) {
883 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
884 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
885 return false;
886 }
887 }
888 }
889
890 if (ArgFlags.isSwiftAsync()) {
891 if (LocVT == MVT::i64) {
892 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
893 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
894 return false;
895 }
896 }
897 }
898
899 if (ArgFlags.isInConsecutiveRegs()) {
900 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
901 return false;
902 }
903
904 if (LocVT == MVT::nxv16i8 ||
905 LocVT == MVT::nxv8i16 ||
906 LocVT == MVT::nxv4i32 ||
907 LocVT == MVT::nxv2i64 ||
908 LocVT == MVT::nxv2f16 ||
909 LocVT == MVT::nxv4f16 ||
910 LocVT == MVT::nxv8f16 ||
911 LocVT == MVT::nxv2bf16 ||
912 LocVT == MVT::nxv4bf16 ||
913 LocVT == MVT::nxv8bf16 ||
914 LocVT == MVT::nxv2f32 ||
915 LocVT == MVT::nxv4f32 ||
916 LocVT == MVT::nxv2f64) {
917 static const MCPhysReg RegList1[] = {
918 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
919 };
920 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
921 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
922 return false;
923 }
924 }
925
926 if (LocVT == MVT::nxv16i8 ||
927 LocVT == MVT::nxv8i16 ||
928 LocVT == MVT::nxv4i32 ||
929 LocVT == MVT::nxv2i64 ||
930 LocVT == MVT::nxv2f16 ||
931 LocVT == MVT::nxv4f16 ||
932 LocVT == MVT::nxv8f16 ||
933 LocVT == MVT::nxv2bf16 ||
934 LocVT == MVT::nxv4bf16 ||
935 LocVT == MVT::nxv8bf16 ||
936 LocVT == MVT::nxv2f32 ||
937 LocVT == MVT::nxv4f32 ||
938 LocVT == MVT::nxv2f64) {
939 LocVT = MVT::i64;
940 LocInfo = CCValAssign::Indirect;
941 }
942
943 if (LocVT == MVT::nxv1i1 ||
944 LocVT == MVT::nxv2i1 ||
945 LocVT == MVT::nxv4i1 ||
946 LocVT == MVT::nxv8i1 ||
947 LocVT == MVT::nxv16i1 ||
948 LocVT == MVT::aarch64svcount) {
949 static const MCPhysReg RegList2[] = {
950 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
951 };
952 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
953 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
954 return false;
955 }
956 }
957
958 if (LocVT == MVT::nxv1i1 ||
959 LocVT == MVT::nxv2i1 ||
960 LocVT == MVT::nxv4i1 ||
961 LocVT == MVT::nxv8i1 ||
962 LocVT == MVT::nxv16i1 ||
963 LocVT == MVT::aarch64svcount) {
964 LocVT = MVT::i64;
965 LocInfo = CCValAssign::Indirect;
966 }
967
968 if (LocVT == MVT::i1 ||
969 LocVT == MVT::i8 ||
970 LocVT == MVT::i16) {
971 LocVT = MVT::i32;
972 if (ArgFlags.isSExt())
973 LocInfo = CCValAssign::SExt;
974 else if (ArgFlags.isZExt())
975 LocInfo = CCValAssign::ZExt;
976 else
977 LocInfo = CCValAssign::AExt;
978 }
979
980 if (LocVT == MVT::i32) {
981 static const MCPhysReg RegList3[] = {
982 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
983 };
984 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
985 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
986 return false;
987 }
988 }
989
990 if (LocVT == MVT::i64) {
991 if (ArgFlags.isSplit()) {
992 static const MCPhysReg RegList4[] = {
993 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
994 };
995 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
996 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
997 return false;
998 }
999 }
1000 }
1001
1002 if (LocVT == MVT::i64) {
1003 if (ArgFlags.isSplit()) {
1004 static const MCPhysReg ShadowRegList5[] = {
1005 AArch64::X7
1006 };
1007 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList5);
1008 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1009 return false;
1010 }
1011 }
1012
1013 if (LocVT == MVT::i64) {
1014 static const MCPhysReg RegList7[] = {
1015 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1016 };
1017 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
1018 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1019 return false;
1020 }
1021 }
1022
1023 if (LocVT == MVT::f16) {
1024 static const MCPhysReg RegList8[] = {
1025 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1026 };
1027 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
1028 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1029 return false;
1030 }
1031 }
1032
1033 if (LocVT == MVT::bf16) {
1034 static const MCPhysReg RegList9[] = {
1035 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1036 };
1037 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1038 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1039 return false;
1040 }
1041 }
1042
1043 if (LocVT == MVT::f32) {
1044 static const MCPhysReg RegList10[] = {
1045 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1046 };
1047 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1048 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1049 return false;
1050 }
1051 }
1052
1053 if (LocVT == MVT::f64) {
1054 static const MCPhysReg RegList11[] = {
1055 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1056 };
1057 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1058 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1059 return false;
1060 }
1061 }
1062
1063 if (LocVT == MVT::v1i64 ||
1064 LocVT == MVT::v2i32 ||
1065 LocVT == MVT::v4i16 ||
1066 LocVT == MVT::v8i8 ||
1067 LocVT == MVT::v1f64 ||
1068 LocVT == MVT::v2f32 ||
1069 LocVT == MVT::v4f16 ||
1070 LocVT == MVT::v4bf16) {
1071 static const MCPhysReg RegList12[] = {
1072 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1073 };
1074 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1075 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1076 return false;
1077 }
1078 }
1079
1080 if (LocVT == MVT::v2i64 ||
1081 LocVT == MVT::v4i32 ||
1082 LocVT == MVT::v8i16 ||
1083 LocVT == MVT::v16i8 ||
1084 LocVT == MVT::v4f32 ||
1085 LocVT == MVT::v2f64 ||
1086 LocVT == MVT::v8f16 ||
1087 LocVT == MVT::v8bf16) {
1088 static const MCPhysReg RegList13[] = {
1089 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1090 };
1091 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1092 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1093 return false;
1094 }
1095 }
1096
1097 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
1098 int64_t Offset14 = State.AllocateStack(Size: 1, Alignment: Align(1));
1099 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1100 return false;
1101 }
1102
1103 if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) {
1104 int64_t Offset15 = State.AllocateStack(Size: 2, Alignment: Align(2));
1105 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
1106 return false;
1107 }
1108
1109 if (LocVT == MVT::i32 ||
1110 LocVT == MVT::f32) {
1111 int64_t Offset16 = State.AllocateStack(Size: 4, Alignment: Align(4));
1112 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1113 return false;
1114 }
1115
1116 if (ArgFlags.isPointer()) {
1117 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1118 LocVT = MVT::i32;
1119 LocInfo = CCValAssign::Trunc;
1120 }
1121 }
1122
1123 if (ArgFlags.isPointer()) {
1124 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1125 int64_t Offset17 = State.AllocateStack(Size: 4, Alignment: Align(4));
1126 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1127 return false;
1128 }
1129 }
1130
1131 if (LocVT == MVT::i64 ||
1132 LocVT == MVT::f64 ||
1133 LocVT == MVT::v1f64 ||
1134 LocVT == MVT::v2f32 ||
1135 LocVT == MVT::v1i64 ||
1136 LocVT == MVT::v2i32 ||
1137 LocVT == MVT::v4i16 ||
1138 LocVT == MVT::v8i8 ||
1139 LocVT == MVT::v4f16 ||
1140 LocVT == MVT::v4bf16) {
1141 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1142 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1143 return false;
1144 }
1145
1146 if (LocVT == MVT::v2i64 ||
1147 LocVT == MVT::v4i32 ||
1148 LocVT == MVT::v8i16 ||
1149 LocVT == MVT::v16i8 ||
1150 LocVT == MVT::v4f32 ||
1151 LocVT == MVT::v2f64 ||
1152 LocVT == MVT::v8f16 ||
1153 LocVT == MVT::v8bf16) {
1154 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1155 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1156 return false;
1157 }
1158
1159 return true; // CC didn't match.
1160}
1161
1162
1163bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
1164 MVT LocVT, CCValAssign::LocInfo LocInfo,
1165 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1166
1167 if (ArgFlags.isNest()) {
1168 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1170 return false;
1171 }
1172 }
1173
1174 if (LocVT == MVT::v2f32) {
1175 LocVT = MVT::v2i32;
1176 LocInfo = CCValAssign::BCvt;
1177 }
1178
1179 if (LocVT == MVT::v2f64 ||
1180 LocVT == MVT::v4f32 ||
1181 LocVT == MVT::f128) {
1182 LocVT = MVT::v2i64;
1183 LocInfo = CCValAssign::BCvt;
1184 }
1185
1186 if (LocVT == MVT::i8 ||
1187 LocVT == MVT::i16) {
1188 LocVT = MVT::i32;
1189 if (ArgFlags.isSExt())
1190 LocInfo = CCValAssign::SExt;
1191 else if (ArgFlags.isZExt())
1192 LocInfo = CCValAssign::ZExt;
1193 else
1194 LocInfo = CCValAssign::AExt;
1195 }
1196
1197 if (LocVT == MVT::f16 ||
1198 LocVT == MVT::bf16) {
1199 LocVT = MVT::f32;
1200 LocInfo = CCValAssign::FPExt;
1201 }
1202
1203 if (ArgFlags.isPointer()) {
1204 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1205 LocVT = MVT::i32;
1206 LocInfo = CCValAssign::Trunc;
1207 }
1208 }
1209
1210 if (LocVT == MVT::i32 ||
1211 LocVT == MVT::f32) {
1212 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1213 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1214 return false;
1215 }
1216
1217 if (LocVT == MVT::i64) {
1218 if (ArgFlags.isSplit()) {
1219 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(16));
1220 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1221 return false;
1222 }
1223 }
1224
1225 if (LocVT == MVT::i64 ||
1226 LocVT == MVT::f64 ||
1227 LocVT == MVT::v1i64 ||
1228 LocVT == MVT::v2i32 ||
1229 LocVT == MVT::v4i16 ||
1230 LocVT == MVT::v8i8 ||
1231 LocVT == MVT::v1f64 ||
1232 LocVT == MVT::v2f32 ||
1233 LocVT == MVT::v4f16 ||
1234 LocVT == MVT::v4bf16) {
1235 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
1236 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1237 return false;
1238 }
1239
1240 if (LocVT == MVT::v2i64 ||
1241 LocVT == MVT::v4i32 ||
1242 LocVT == MVT::v8i16 ||
1243 LocVT == MVT::v16i8 ||
1244 LocVT == MVT::v4f32 ||
1245 LocVT == MVT::v2f64 ||
1246 LocVT == MVT::v8f16 ||
1247 LocVT == MVT::v8bf16) {
1248 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(16));
1249 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
1250 return false;
1251 }
1252
1253 return true; // CC didn't match.
1254}
1255
1256
1257bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
1258 MVT LocVT, CCValAssign::LocInfo LocInfo,
1259 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1260
1261 if (ArgFlags.isNest()) {
1262 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1263 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1264 return false;
1265 }
1266 }
1267
1268 if (LocVT == MVT::iPTR) {
1269 LocVT = MVT::i64;
1270 LocInfo = CCValAssign::BCvt;
1271 }
1272
1273 if (LocVT == MVT::v2f32) {
1274 LocVT = MVT::v2i32;
1275 LocInfo = CCValAssign::BCvt;
1276 }
1277
1278 if (LocVT == MVT::v2f64 ||
1279 LocVT == MVT::v4f32 ||
1280 LocVT == MVT::f128) {
1281 LocVT = MVT::v2i64;
1282 LocInfo = CCValAssign::BCvt;
1283 }
1284
1285 if (ArgFlags.isInConsecutiveRegs()) {
1286 if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1287 return false;
1288 }
1289
1290 if (LocVT == MVT::i8 ||
1291 LocVT == MVT::i16 ||
1292 LocVT == MVT::i32) {
1293 LocVT = MVT::i64;
1294 if (ArgFlags.isSExt())
1295 LocInfo = CCValAssign::SExt;
1296 else if (ArgFlags.isZExt())
1297 LocInfo = CCValAssign::ZExt;
1298 else
1299 LocInfo = CCValAssign::AExt;
1300 }
1301
1302 if (LocVT == MVT::f16 ||
1303 LocVT == MVT::bf16 ||
1304 LocVT == MVT::f32) {
1305 LocVT = MVT::f64;
1306 LocInfo = CCValAssign::FPExt;
1307 }
1308
1309 if (LocVT == MVT::i64) {
1310 if (ArgFlags.isSplit()) {
1311 int64_t Offset1 = State.AllocateStack(Size: 8, Alignment: Align(16));
1312 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1313 return false;
1314 }
1315 }
1316
1317 if (LocVT == MVT::i64 ||
1318 LocVT == MVT::f64 ||
1319 LocVT == MVT::v1i64 ||
1320 LocVT == MVT::v2i32 ||
1321 LocVT == MVT::v4i16 ||
1322 LocVT == MVT::v8i8 ||
1323 LocVT == MVT::v1f64 ||
1324 LocVT == MVT::v2f32 ||
1325 LocVT == MVT::v4f16 ||
1326 LocVT == MVT::v4bf16) {
1327 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
1328 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1329 return false;
1330 }
1331
1332 if (LocVT == MVT::v2i64 ||
1333 LocVT == MVT::v4i32 ||
1334 LocVT == MVT::v8i16 ||
1335 LocVT == MVT::v16i8 ||
1336 LocVT == MVT::v4f32 ||
1337 LocVT == MVT::v2f64 ||
1338 LocVT == MVT::v8f16 ||
1339 LocVT == MVT::v8bf16) {
1340 int64_t Offset3 = State.AllocateStack(Size: 16, Alignment: Align(16));
1341 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1342 return false;
1343 }
1344
1345 return true; // CC didn't match.
1346}
1347
1348
1349bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
1350 MVT LocVT, CCValAssign::LocInfo LocInfo,
1351 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1352
1353 if (ArgFlags.isNest()) {
1354 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1355 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1356 return false;
1357 }
1358 }
1359
1360 if (LocVT == MVT::iPTR) {
1361 LocVT = MVT::i64;
1362 LocInfo = CCValAssign::BCvt;
1363 }
1364
1365 if (LocVT == MVT::v1i64 ||
1366 LocVT == MVT::v2i32 ||
1367 LocVT == MVT::v4i16 ||
1368 LocVT == MVT::v8i8 ||
1369 LocVT == MVT::v2f32) {
1370 LocVT = MVT::f64;
1371 LocInfo = CCValAssign::BCvt;
1372 }
1373
1374 if (LocVT == MVT::v2i64 ||
1375 LocVT == MVT::v4i32 ||
1376 LocVT == MVT::v8i16 ||
1377 LocVT == MVT::v16i8 ||
1378 LocVT == MVT::v4f32 ||
1379 LocVT == MVT::f128) {
1380 LocVT = MVT::v2f64;
1381 LocInfo = CCValAssign::BCvt;
1382 }
1383
1384 if (LocVT == MVT::v2f64) {
1385 static const MCPhysReg RegList1[] = {
1386 AArch64::Q4, AArch64::Q5
1387 };
1388 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1389 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1390 return false;
1391 }
1392 }
1393
1394 if (LocVT == MVT::f32) {
1395 static const MCPhysReg RegList2[] = {
1396 AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
1397 };
1398 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1399 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1400 return false;
1401 }
1402 }
1403
1404 if (LocVT == MVT::f64) {
1405 static const MCPhysReg RegList3[] = {
1406 AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
1407 };
1408 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1409 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1410 return false;
1411 }
1412 }
1413
1414 if (LocVT == MVT::i8 ||
1415 LocVT == MVT::i16 ||
1416 LocVT == MVT::i32) {
1417 LocVT = MVT::i64;
1418 if (ArgFlags.isSExt())
1419 LocInfo = CCValAssign::SExt;
1420 else if (ArgFlags.isZExt())
1421 LocInfo = CCValAssign::ZExt;
1422 else
1423 LocInfo = CCValAssign::AExt;
1424 }
1425
1426 if (LocVT == MVT::i64) {
1427 static const MCPhysReg RegList4[] = {
1428 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
1429 };
1430 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1431 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1432 return false;
1433 }
1434 }
1435
1436 return true; // CC didn't match.
1437}
1438
1439
1440bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
1441 MVT LocVT, CCValAssign::LocInfo LocInfo,
1442 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1443
1444 if (State.isVarArg()) {
1445 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
1446 if (!CC_AArch64_DarwinPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1447 return false;
1448 }
1449 }
1450
1451 if (State.isVarArg()) {
1452 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1453 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1454 return false;
1455 }
1456 }
1457
1458 if (State.isVarArg()) {
1459 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1460 return false;
1461 }
1462
1463 if (LocVT == MVT::i32) {
1464 static const MCPhysReg RegList1[] = {
1465 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W9
1466 };
1467 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1468 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1469 return false;
1470 }
1471 }
1472
1473 if (LocVT == MVT::i64) {
1474 static const MCPhysReg RegList2[] = {
1475 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X9
1476 };
1477 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1478 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1479 return false;
1480 }
1481 }
1482
1483 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1484 if (LocVT == MVT::i32) {
1485 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::W15)) {
1486 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1487 return false;
1488 }
1489 }
1490 }
1491
1492 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1493 if (LocVT == MVT::i64) {
1494 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1495 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1496 return false;
1497 }
1498 }
1499 }
1500
1501 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1502 return false;
1503
1504 return true; // CC didn't match.
1505}
1506
1507
1508bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
1509 MVT LocVT, CCValAssign::LocInfo LocInfo,
1510 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1511
1512 if (ArgFlags.isCFGuardTarget()) {
1513 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
1514 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1515 return false;
1516 }
1517 }
1518
1519 if (ArgFlags.isNest()) {
1520 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1521 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1522 return false;
1523 }
1524 }
1525
1526 if (LocVT == MVT::iPTR) {
1527 LocVT = MVT::i64;
1528 LocInfo = CCValAssign::BCvt;
1529 }
1530
1531 if (LocVT == MVT::v2f32) {
1532 LocVT = MVT::v2i32;
1533 LocInfo = CCValAssign::BCvt;
1534 }
1535
1536 if (LocVT == MVT::v2f64 ||
1537 LocVT == MVT::v4f32) {
1538 LocVT = MVT::v2i64;
1539 LocInfo = CCValAssign::BCvt;
1540 }
1541
1542 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1543 if (LocVT == MVT::v2i32 ||
1544 LocVT == MVT::v2f32 ||
1545 LocVT == MVT::v4i16 ||
1546 LocVT == MVT::v4f16 ||
1547 LocVT == MVT::v4bf16 ||
1548 LocVT == MVT::v8i8) {
1549 LocVT = MVT::f64;
1550 LocInfo = CCValAssign::BCvt;
1551 }
1552 }
1553
1554 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1555 if (LocVT == MVT::v2i64 ||
1556 LocVT == MVT::v2f64 ||
1557 LocVT == MVT::v4i32 ||
1558 LocVT == MVT::v4f32 ||
1559 LocVT == MVT::v8i16 ||
1560 LocVT == MVT::v8f16 ||
1561 LocVT == MVT::v8bf16 ||
1562 LocVT == MVT::v16i8) {
1563 LocVT = MVT::f128;
1564 LocInfo = CCValAssign::BCvt;
1565 }
1566 }
1567
1568 if (ArgFlags.isInReg()) {
1569 if (LocVT == MVT::i64) {
1570 if (ArgFlags.isSRet()) {
1571 if (LocVT == MVT::i64) {
1572 static const MCPhysReg RegList1[] = {
1573 AArch64::X0, AArch64::X1
1574 };
1575 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1576 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1577 return false;
1578 }
1579 }
1580 }
1581 }
1582 }
1583
1584 if (ArgFlags.isSRet()) {
1585 if (LocVT == MVT::i64) {
1586 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
1587 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1588 return false;
1589 }
1590 }
1591 }
1592
1593 if (ArgFlags.isByVal()) {
1594 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1595 return false;
1596 }
1597
1598 if (ArgFlags.isSwiftSelf()) {
1599 if (LocVT == MVT::i64) {
1600 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
1601 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1602 return false;
1603 }
1604 }
1605 }
1606
1607 if (ArgFlags.isSwiftError()) {
1608 if (LocVT == MVT::i64) {
1609 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1610 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1611 return false;
1612 }
1613 }
1614 }
1615
1616 if (ArgFlags.isSwiftAsync()) {
1617 if (LocVT == MVT::i64) {
1618 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
1619 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1620 return false;
1621 }
1622 }
1623 }
1624
1625 if (ArgFlags.isInConsecutiveRegs()) {
1626 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1627 return false;
1628 }
1629
1630 if (LocVT == MVT::nxv16i8 ||
1631 LocVT == MVT::nxv8i16 ||
1632 LocVT == MVT::nxv4i32 ||
1633 LocVT == MVT::nxv2i64 ||
1634 LocVT == MVT::nxv2f16 ||
1635 LocVT == MVT::nxv4f16 ||
1636 LocVT == MVT::nxv8f16 ||
1637 LocVT == MVT::nxv2bf16 ||
1638 LocVT == MVT::nxv4bf16 ||
1639 LocVT == MVT::nxv8bf16 ||
1640 LocVT == MVT::nxv2f32 ||
1641 LocVT == MVT::nxv4f32 ||
1642 LocVT == MVT::nxv2f64) {
1643 static const MCPhysReg RegList2[] = {
1644 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1645 };
1646 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1647 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1648 return false;
1649 }
1650 }
1651
1652 if (LocVT == MVT::nxv16i8 ||
1653 LocVT == MVT::nxv8i16 ||
1654 LocVT == MVT::nxv4i32 ||
1655 LocVT == MVT::nxv2i64 ||
1656 LocVT == MVT::nxv2f16 ||
1657 LocVT == MVT::nxv4f16 ||
1658 LocVT == MVT::nxv8f16 ||
1659 LocVT == MVT::nxv2bf16 ||
1660 LocVT == MVT::nxv4bf16 ||
1661 LocVT == MVT::nxv8bf16 ||
1662 LocVT == MVT::nxv2f32 ||
1663 LocVT == MVT::nxv4f32 ||
1664 LocVT == MVT::nxv2f64) {
1665 LocVT = MVT::i64;
1666 LocInfo = CCValAssign::Indirect;
1667 }
1668
1669 if (LocVT == MVT::nxv1i1 ||
1670 LocVT == MVT::nxv2i1 ||
1671 LocVT == MVT::nxv4i1 ||
1672 LocVT == MVT::nxv8i1 ||
1673 LocVT == MVT::nxv16i1 ||
1674 LocVT == MVT::aarch64svcount) {
1675 static const MCPhysReg RegList3[] = {
1676 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
1677 };
1678 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1679 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1680 return false;
1681 }
1682 }
1683
1684 if (LocVT == MVT::nxv1i1 ||
1685 LocVT == MVT::nxv2i1 ||
1686 LocVT == MVT::nxv4i1 ||
1687 LocVT == MVT::nxv8i1 ||
1688 LocVT == MVT::nxv16i1 ||
1689 LocVT == MVT::aarch64svcount) {
1690 LocVT = MVT::i64;
1691 LocInfo = CCValAssign::Indirect;
1692 }
1693
1694 if (LocVT == MVT::i1 ||
1695 LocVT == MVT::i8 ||
1696 LocVT == MVT::i16) {
1697 LocVT = MVT::i32;
1698 if (ArgFlags.isSExt())
1699 LocInfo = CCValAssign::SExt;
1700 else if (ArgFlags.isZExt())
1701 LocInfo = CCValAssign::ZExt;
1702 else
1703 LocInfo = CCValAssign::AExt;
1704 }
1705
1706 if (LocVT == MVT::i32) {
1707 static const MCPhysReg RegList4[] = {
1708 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1709 };
1710 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1711 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1712 return false;
1713 }
1714 }
1715
1716 if (LocVT == MVT::i64) {
1717 if (ArgFlags.isSplit()) {
1718 static const MCPhysReg RegList5[] = {
1719 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
1720 };
1721 static const MCPhysReg RegList6[] = {
1722 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
1723 };
1724 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
1725 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1726 return false;
1727 }
1728 }
1729 }
1730
1731 if (LocVT == MVT::i64) {
1732 if (ArgFlags.isSplit()) {
1733 static const MCPhysReg ShadowRegList7[] = {
1734 AArch64::X7
1735 };
1736 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
1737 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1738 return false;
1739 }
1740 }
1741
1742 if (LocVT == MVT::i64) {
1743 static const MCPhysReg RegList9[] = {
1744 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1745 };
1746 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1747 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1748 return false;
1749 }
1750 }
1751
1752 if (LocVT == MVT::f16) {
1753 static const MCPhysReg RegList10[] = {
1754 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1755 };
1756 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1757 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1758 return false;
1759 }
1760 }
1761
1762 if (LocVT == MVT::bf16) {
1763 static const MCPhysReg RegList11[] = {
1764 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1765 };
1766 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1767 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1768 return false;
1769 }
1770 }
1771
1772 if (LocVT == MVT::f32) {
1773 static const MCPhysReg RegList12[] = {
1774 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1775 };
1776 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1777 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1778 return false;
1779 }
1780 }
1781
1782 if (LocVT == MVT::f64) {
1783 static const MCPhysReg RegList13[] = {
1784 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1785 };
1786 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1787 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1788 return false;
1789 }
1790 }
1791
1792 if (LocVT == MVT::v1i64 ||
1793 LocVT == MVT::v2i32 ||
1794 LocVT == MVT::v4i16 ||
1795 LocVT == MVT::v8i8 ||
1796 LocVT == MVT::v1f64 ||
1797 LocVT == MVT::v2f32 ||
1798 LocVT == MVT::v4f16 ||
1799 LocVT == MVT::v4bf16) {
1800 static const MCPhysReg RegList14[] = {
1801 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1802 };
1803 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
1804 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1805 return false;
1806 }
1807 }
1808
1809 if (LocVT == MVT::f128 ||
1810 LocVT == MVT::v2i64 ||
1811 LocVT == MVT::v4i32 ||
1812 LocVT == MVT::v8i16 ||
1813 LocVT == MVT::v16i8 ||
1814 LocVT == MVT::v4f32 ||
1815 LocVT == MVT::v2f64 ||
1816 LocVT == MVT::v8f16 ||
1817 LocVT == MVT::v8bf16) {
1818 static const MCPhysReg RegList15[] = {
1819 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1820 };
1821 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
1822 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1823 return false;
1824 }
1825 }
1826
1827 if (LocVT == MVT::i1 ||
1828 LocVT == MVT::i8 ||
1829 LocVT == MVT::i16 ||
1830 LocVT == MVT::f16 ||
1831 LocVT == MVT::bf16) {
1832 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
1833 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1834 return false;
1835 }
1836
1837 if (LocVT == MVT::i32 ||
1838 LocVT == MVT::f32) {
1839 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
1840 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1841 return false;
1842 }
1843
1844 if (LocVT == MVT::i64 ||
1845 LocVT == MVT::f64 ||
1846 LocVT == MVT::v1f64 ||
1847 LocVT == MVT::v2f32 ||
1848 LocVT == MVT::v1i64 ||
1849 LocVT == MVT::v2i32 ||
1850 LocVT == MVT::v4i16 ||
1851 LocVT == MVT::v8i8 ||
1852 LocVT == MVT::v4f16 ||
1853 LocVT == MVT::v4bf16) {
1854 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1855 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1856 return false;
1857 }
1858
1859 if (LocVT == MVT::f128 ||
1860 LocVT == MVT::v2i64 ||
1861 LocVT == MVT::v4i32 ||
1862 LocVT == MVT::v8i16 ||
1863 LocVT == MVT::v16i8 ||
1864 LocVT == MVT::v4f32 ||
1865 LocVT == MVT::v2f64 ||
1866 LocVT == MVT::v8f16 ||
1867 LocVT == MVT::v8bf16) {
1868 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1869 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1870 return false;
1871 }
1872
1873 return true; // CC didn't match.
1874}
1875
1876
1877bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
1878 MVT LocVT, CCValAssign::LocInfo LocInfo,
1879 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1880
1881 if (LocVT == MVT::i64) {
1882 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1883 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1884 return false;
1885 }
1886 }
1887
1888 return true; // CC didn't match.
1889}
1890
1891
1892bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
1893 MVT LocVT, CCValAssign::LocInfo LocInfo,
1894 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1895
1896 if (LocVT == MVT::f16 ||
1897 LocVT == MVT::bf16) {
1898 LocVT = MVT::i16;
1899 LocInfo = CCValAssign::BCvt;
1900 }
1901
1902 if (LocVT == MVT::f32) {
1903 LocVT = MVT::i32;
1904 LocInfo = CCValAssign::BCvt;
1905 }
1906
1907 if (LocVT == MVT::f64) {
1908 LocVT = MVT::i64;
1909 LocInfo = CCValAssign::BCvt;
1910 }
1911
1912 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1913 return false;
1914
1915 return true; // CC didn't match.
1916}
1917
1918
1919bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
1920 MVT LocVT, CCValAssign::LocInfo LocInfo,
1921 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1922
1923 if (LocVT == MVT::iPTR) {
1924 LocVT = MVT::i64;
1925 LocInfo = CCValAssign::BCvt;
1926 }
1927
1928 if (LocVT == MVT::v2f32) {
1929 LocVT = MVT::v2i32;
1930 LocInfo = CCValAssign::BCvt;
1931 }
1932
1933 if (LocVT == MVT::v2f64 ||
1934 LocVT == MVT::v4f32) {
1935 LocVT = MVT::v2i64;
1936 LocInfo = CCValAssign::BCvt;
1937 }
1938
1939 if (ArgFlags.isInConsecutiveRegs()) {
1940 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1941 return false;
1942 }
1943
1944 if (ArgFlags.isSwiftError()) {
1945 if (LocVT == MVT::i64) {
1946 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1947 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1948 return false;
1949 }
1950 }
1951 }
1952
1953 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1954 if (LocVT == MVT::v2i32 ||
1955 LocVT == MVT::v2f32 ||
1956 LocVT == MVT::v4i16 ||
1957 LocVT == MVT::v4f16 ||
1958 LocVT == MVT::v4bf16 ||
1959 LocVT == MVT::v8i8) {
1960 LocVT = MVT::f64;
1961 LocInfo = CCValAssign::BCvt;
1962 }
1963 }
1964
1965 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1966 if (LocVT == MVT::v2i64 ||
1967 LocVT == MVT::v2f64 ||
1968 LocVT == MVT::v4i32 ||
1969 LocVT == MVT::v4f32 ||
1970 LocVT == MVT::v8i16 ||
1971 LocVT == MVT::v8f16 ||
1972 LocVT == MVT::v8bf16 ||
1973 LocVT == MVT::v16i8) {
1974 LocVT = MVT::f128;
1975 LocInfo = CCValAssign::BCvt;
1976 }
1977 }
1978
1979 if (LocVT == MVT::i1 ||
1980 LocVT == MVT::i8 ||
1981 LocVT == MVT::i16) {
1982 LocVT = MVT::i32;
1983 if (ArgFlags.isSExt())
1984 LocInfo = CCValAssign::SExt;
1985 else if (ArgFlags.isZExt())
1986 LocInfo = CCValAssign::ZExt;
1987 else
1988 LocInfo = CCValAssign::AExt;
1989 }
1990
1991 if (LocVT == MVT::i32) {
1992 static const MCPhysReg RegList1[] = {
1993 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1994 };
1995 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1996 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1997 return false;
1998 }
1999 }
2000
2001 if (LocVT == MVT::i64) {
2002 static const MCPhysReg RegList2[] = {
2003 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
2004 };
2005 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2006 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2007 return false;
2008 }
2009 }
2010
2011 if (LocVT == MVT::f16) {
2012 static const MCPhysReg RegList3[] = {
2013 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
2014 };
2015 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2016 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2017 return false;
2018 }
2019 }
2020
2021 if (LocVT == MVT::bf16) {
2022 static const MCPhysReg RegList4[] = {
2023 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
2024 };
2025 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2026 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2027 return false;
2028 }
2029 }
2030
2031 if (LocVT == MVT::f32) {
2032 static const MCPhysReg RegList5[] = {
2033 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
2034 };
2035 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2036 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2037 return false;
2038 }
2039 }
2040
2041 if (LocVT == MVT::f64) {
2042 static const MCPhysReg RegList6[] = {
2043 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2044 };
2045 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2046 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2047 return false;
2048 }
2049 }
2050
2051 if (LocVT == MVT::v1i64 ||
2052 LocVT == MVT::v2i32 ||
2053 LocVT == MVT::v4i16 ||
2054 LocVT == MVT::v8i8 ||
2055 LocVT == MVT::v1f64 ||
2056 LocVT == MVT::v2f32 ||
2057 LocVT == MVT::v4f16 ||
2058 LocVT == MVT::v4bf16) {
2059 static const MCPhysReg RegList7[] = {
2060 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2061 };
2062 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2063 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2064 return false;
2065 }
2066 }
2067
2068 if (LocVT == MVT::f128 ||
2069 LocVT == MVT::v2i64 ||
2070 LocVT == MVT::v4i32 ||
2071 LocVT == MVT::v8i16 ||
2072 LocVT == MVT::v16i8 ||
2073 LocVT == MVT::v4f32 ||
2074 LocVT == MVT::v2f64 ||
2075 LocVT == MVT::v8f16 ||
2076 LocVT == MVT::v8bf16) {
2077 static const MCPhysReg RegList8[] = {
2078 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
2079 };
2080 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
2081 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2082 return false;
2083 }
2084 }
2085
2086 if (LocVT == MVT::nxv16i8 ||
2087 LocVT == MVT::nxv8i16 ||
2088 LocVT == MVT::nxv4i32 ||
2089 LocVT == MVT::nxv2i64 ||
2090 LocVT == MVT::nxv2f16 ||
2091 LocVT == MVT::nxv4f16 ||
2092 LocVT == MVT::nxv8f16 ||
2093 LocVT == MVT::nxv2bf16 ||
2094 LocVT == MVT::nxv4bf16 ||
2095 LocVT == MVT::nxv8bf16 ||
2096 LocVT == MVT::nxv2f32 ||
2097 LocVT == MVT::nxv4f32 ||
2098 LocVT == MVT::nxv2f64) {
2099 static const MCPhysReg RegList9[] = {
2100 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
2101 };
2102 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
2103 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2104 return false;
2105 }
2106 }
2107
2108 if (LocVT == MVT::nxv1i1 ||
2109 LocVT == MVT::nxv2i1 ||
2110 LocVT == MVT::nxv4i1 ||
2111 LocVT == MVT::nxv8i1 ||
2112 LocVT == MVT::nxv16i1 ||
2113 LocVT == MVT::aarch64svcount) {
2114 static const MCPhysReg RegList10[] = {
2115 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
2116 };
2117 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
2118 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2119 return false;
2120 }
2121 }
2122
2123 return true; // CC didn't match.
2124}
2125
2126
2127bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
2128 MVT LocVT, CCValAssign::LocInfo LocInfo,
2129 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2130
2131 if (LocVT == MVT::i64) {
2132 static const MCPhysReg RegList1[] = {
2133 AArch64::X11, AArch64::X9
2134 };
2135 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2136 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2137 return false;
2138 }
2139 }
2140
2141 return true; // CC didn't match.
2142}
2143
2144
2145bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
2146 MVT LocVT, CCValAssign::LocInfo LocInfo,
2147 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2148
2149 if (LocVT == MVT::x86mmx) {
2150 LocVT = MVT::i64;
2151 LocInfo = CCValAssign::BCvt;
2152 }
2153
2154 if (LocVT == MVT::f16) {
2155 static const MCPhysReg RegList1[] = {
2156 AArch64::H0, AArch64::H1
2157 };
2158 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2159 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2160 return false;
2161 }
2162 }
2163
2164 if (LocVT == MVT::bf16) {
2165 static const MCPhysReg RegList2[] = {
2166 AArch64::H0, AArch64::H1
2167 };
2168 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2170 return false;
2171 }
2172 }
2173
2174 if (LocVT == MVT::f32) {
2175 static const MCPhysReg RegList3[] = {
2176 AArch64::S0, AArch64::S1
2177 };
2178 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2179 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2180 return false;
2181 }
2182 }
2183
2184 if (LocVT == MVT::f64) {
2185 static const MCPhysReg RegList4[] = {
2186 AArch64::D0, AArch64::D1
2187 };
2188 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2189 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2190 return false;
2191 }
2192 }
2193
2194 if (LocVT == MVT::f128) {
2195 static const MCPhysReg RegList5[] = {
2196 AArch64::Q0, AArch64::Q1
2197 };
2198 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2199 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2200 return false;
2201 }
2202 }
2203
2204 if (ArgFlags.isSwiftError()) {
2205 if (LocVT == MVT::i64) {
2206 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
2207 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2208 return false;
2209 }
2210 }
2211 }
2212
2213 if (LocVT == MVT::i1 ||
2214 LocVT == MVT::i8 ||
2215 LocVT == MVT::i16) {
2216 LocVT = MVT::i32;
2217 if (ArgFlags.isSExt())
2218 LocInfo = CCValAssign::SExt;
2219 else if (ArgFlags.isZExt())
2220 LocInfo = CCValAssign::ZExt;
2221 else
2222 LocInfo = CCValAssign::AExt;
2223 }
2224
2225 if (LocVT == MVT::i32) {
2226 static const MCPhysReg RegList6[] = {
2227 AArch64::W8, AArch64::W1, AArch64::W0
2228 };
2229 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2230 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2231 return false;
2232 }
2233 }
2234
2235 if (LocVT == MVT::i64) {
2236 static const MCPhysReg RegList7[] = {
2237 AArch64::X8, AArch64::X1, AArch64::X0
2238 };
2239 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2240 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2241 return false;
2242 }
2243 }
2244
2245 if (LocVT == MVT::v16i8 ||
2246 LocVT == MVT::v8i16 ||
2247 LocVT == MVT::v4i32 ||
2248 LocVT == MVT::v2i64 ||
2249 LocVT == MVT::v8f16 ||
2250 LocVT == MVT::v4f32 ||
2251 LocVT == MVT::v2f64) {
2252 static const MCPhysReg RegList8[] = {
2253 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
2254 };
2255 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
2256 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2257 return false;
2258 }
2259 }
2260
2261 return true; // CC didn't match.
2262}
2263
2264#endif // GET_CALLING_CONV_IMPL
2265
2266#ifdef GET_CC_REGISTER_LISTS
2267#undef GET_CC_REGISTER_LISTS
2268
2269const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2270const MCRegister CC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X10, AArch64::X11, AArch64::X9 };
2271const MCRegister CC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::X4, AArch64::X8, AArch64::X9 };
2272const MCRegister CC_AArch64_Arm64EC_Thunk_Native_ArgRegs[] = { AArch64::X9 };
2273const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X8, AArch64::X9 };
2274const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2275const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { AArch64::X15 };
2276const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { AArch64::X15 };
2277const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 };
2278const MCRegister CC_AArch64_Preserve_None_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W2, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W9, AArch64::X0, AArch64::X1, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X2, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X9 };
2279const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2280const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 };
2281const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 };
2282const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2283const MCRegister RetCC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X11, AArch64::X9 };
2284const MCRegister RetCC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::H0, AArch64::H1, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::S0, AArch64::S1, AArch64::W0, AArch64::W1, AArch64::W8, AArch64::X0, AArch64::X1, AArch64::X8 };
2285
2286// Registers used by Swift.
2287const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2288const MCRegister CC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19, AArch64::X20, AArch64::X21 };
2289const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2290const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2291const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 };
2292const MCRegister RetCC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19 };
2293
2294#endif // GET_CC_REGISTER_LISTS
2295
2296