1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#if !defined(GET_CC_REGISTER_LISTS)
10
11bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
14bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
17bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
20bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
23bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
26bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
29bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
32bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
35bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
38bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
41bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
44bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
47bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
50bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
53bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
56bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
59
60
61bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
62 MVT LocVT, CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
64
65 if (ArgFlags.isNest()) {
66 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
67 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
68 return false;
69 }
70 }
71
72 if (LocVT == MVT::iPTR) {
73 LocVT = MVT::i64;
74 LocInfo = CCValAssign::BCvt;
75 }
76
77 if (LocVT == MVT::v2f32) {
78 LocVT = MVT::v2i32;
79 LocInfo = CCValAssign::BCvt;
80 }
81
82 if (LocVT == MVT::v2f64 ||
83 LocVT == MVT::v4f32) {
84 LocVT = MVT::v2i64;
85 LocInfo = CCValAssign::BCvt;
86 }
87
88 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
89 if (LocVT == MVT::v2i32 ||
90 LocVT == MVT::v2f32 ||
91 LocVT == MVT::v4i16 ||
92 LocVT == MVT::v4f16 ||
93 LocVT == MVT::v4bf16 ||
94 LocVT == MVT::v8i8) {
95 LocVT = MVT::f64;
96 LocInfo = CCValAssign::BCvt;
97 }
98 }
99
100 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
101 if (LocVT == MVT::v2i64 ||
102 LocVT == MVT::v2f64 ||
103 LocVT == MVT::v4i32 ||
104 LocVT == MVT::v4f32 ||
105 LocVT == MVT::v8i16 ||
106 LocVT == MVT::v8f16 ||
107 LocVT == MVT::v8bf16 ||
108 LocVT == MVT::v16i8) {
109 LocVT = MVT::f128;
110 LocInfo = CCValAssign::BCvt;
111 }
112 }
113
114 if (ArgFlags.isInReg()) {
115 if (LocVT == MVT::i64) {
116 if (ArgFlags.isSRet()) {
117 if (LocVT == MVT::i64) {
118 static const MCPhysReg RegList1[] = {
119 AArch64::X0, AArch64::X1
120 };
121 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
122 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
123 return false;
124 }
125 }
126 }
127 }
128 }
129
130 if (ArgFlags.isSRet()) {
131 if (LocVT == MVT::i64) {
132 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
133 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
134 return false;
135 }
136 }
137 }
138
139 if (ArgFlags.isByVal()) {
140 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
141 return false;
142 }
143
144 if (ArgFlags.isSwiftSelf()) {
145 if (LocVT == MVT::i64) {
146 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
147 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
148 return false;
149 }
150 }
151 }
152
153 if (ArgFlags.isSwiftError()) {
154 if (LocVT == MVT::i64) {
155 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
157 return false;
158 }
159 }
160 }
161
162 if (ArgFlags.isSwiftAsync()) {
163 if (LocVT == MVT::i64) {
164 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
165 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
166 return false;
167 }
168 }
169 }
170
171 if (ArgFlags.isInConsecutiveRegs()) {
172 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
173 return false;
174 }
175
176 if (LocVT == MVT::nxv16i8 ||
177 LocVT == MVT::nxv8i16 ||
178 LocVT == MVT::nxv4i32 ||
179 LocVT == MVT::nxv2i64 ||
180 LocVT == MVT::nxv2f16 ||
181 LocVT == MVT::nxv4f16 ||
182 LocVT == MVT::nxv8f16 ||
183 LocVT == MVT::nxv2bf16 ||
184 LocVT == MVT::nxv4bf16 ||
185 LocVT == MVT::nxv8bf16 ||
186 LocVT == MVT::nxv2f32 ||
187 LocVT == MVT::nxv4f32 ||
188 LocVT == MVT::nxv2f64) {
189 static const MCPhysReg RegList2[] = {
190 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
191 };
192 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
193 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
194 return false;
195 }
196 }
197
198 if (LocVT == MVT::nxv16i8 ||
199 LocVT == MVT::nxv8i16 ||
200 LocVT == MVT::nxv4i32 ||
201 LocVT == MVT::nxv2i64 ||
202 LocVT == MVT::nxv2f16 ||
203 LocVT == MVT::nxv4f16 ||
204 LocVT == MVT::nxv8f16 ||
205 LocVT == MVT::nxv2bf16 ||
206 LocVT == MVT::nxv4bf16 ||
207 LocVT == MVT::nxv8bf16 ||
208 LocVT == MVT::nxv2f32 ||
209 LocVT == MVT::nxv4f32 ||
210 LocVT == MVT::nxv2f64) {
211 LocVT = MVT::i64;
212 LocInfo = CCValAssign::Indirect;
213 }
214
215 if (LocVT == MVT::nxv1i1 ||
216 LocVT == MVT::nxv2i1 ||
217 LocVT == MVT::nxv4i1 ||
218 LocVT == MVT::nxv8i1 ||
219 LocVT == MVT::nxv16i1 ||
220 LocVT == MVT::aarch64svcount) {
221 static const MCPhysReg RegList3[] = {
222 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
223 };
224 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
225 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
226 return false;
227 }
228 }
229
230 if (LocVT == MVT::nxv1i1 ||
231 LocVT == MVT::nxv2i1 ||
232 LocVT == MVT::nxv4i1 ||
233 LocVT == MVT::nxv8i1 ||
234 LocVT == MVT::nxv16i1 ||
235 LocVT == MVT::aarch64svcount) {
236 LocVT = MVT::i64;
237 LocInfo = CCValAssign::Indirect;
238 }
239
240 if (LocVT == MVT::i1 ||
241 LocVT == MVT::i8 ||
242 LocVT == MVT::i16) {
243 LocVT = MVT::i32;
244 if (ArgFlags.isSExt())
245 LocInfo = CCValAssign::SExt;
246 else if (ArgFlags.isZExt())
247 LocInfo = CCValAssign::ZExt;
248 else
249 LocInfo = CCValAssign::AExt;
250 }
251
252 if (LocVT == MVT::i32) {
253 static const MCPhysReg RegList4[] = {
254 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
255 };
256 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
257 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
258 return false;
259 }
260 }
261
262 if (LocVT == MVT::i64) {
263 if (ArgFlags.isSplit()) {
264 static const MCPhysReg RegList5[] = {
265 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
266 };
267 static const MCPhysReg RegList6[] = {
268 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
269 };
270 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
271 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
272 return false;
273 }
274 }
275 }
276
277 if (LocVT == MVT::i64) {
278 if (ArgFlags.isSplit()) {
279 static const MCPhysReg ShadowRegList7[] = {
280 AArch64::X7
281 };
282 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
283 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
284 return false;
285 }
286 }
287
288 if (LocVT == MVT::i64) {
289 static const MCPhysReg RegList9[] = {
290 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
291 };
292 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
293 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
294 return false;
295 }
296 }
297
298 if (LocVT == MVT::f16) {
299 static const MCPhysReg RegList10[] = {
300 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
301 };
302 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
303 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
304 return false;
305 }
306 }
307
308 if (LocVT == MVT::bf16) {
309 static const MCPhysReg RegList11[] = {
310 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
311 };
312 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
313 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
314 return false;
315 }
316 }
317
318 if (LocVT == MVT::f32) {
319 static const MCPhysReg RegList12[] = {
320 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
321 };
322 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
323 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
324 return false;
325 }
326 }
327
328 if (LocVT == MVT::f64) {
329 static const MCPhysReg RegList13[] = {
330 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
331 };
332 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
333 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
334 return false;
335 }
336 }
337
338 if (LocVT == MVT::v1i64 ||
339 LocVT == MVT::v2i32 ||
340 LocVT == MVT::v4i16 ||
341 LocVT == MVT::v8i8 ||
342 LocVT == MVT::v1f64 ||
343 LocVT == MVT::v2f32 ||
344 LocVT == MVT::v4f16 ||
345 LocVT == MVT::v4bf16) {
346 static const MCPhysReg RegList14[] = {
347 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
348 };
349 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
350 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
351 return false;
352 }
353 }
354
355 if (LocVT == MVT::f128 ||
356 LocVT == MVT::v2i64 ||
357 LocVT == MVT::v4i32 ||
358 LocVT == MVT::v8i16 ||
359 LocVT == MVT::v16i8 ||
360 LocVT == MVT::v4f32 ||
361 LocVT == MVT::v2f64 ||
362 LocVT == MVT::v8f16 ||
363 LocVT == MVT::v8bf16) {
364 static const MCPhysReg RegList15[] = {
365 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
366 };
367 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
368 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
369 return false;
370 }
371 }
372
373 if (LocVT == MVT::i1 ||
374 LocVT == MVT::i8 ||
375 LocVT == MVT::i16 ||
376 LocVT == MVT::f16 ||
377 LocVT == MVT::bf16) {
378 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
379 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
380 return false;
381 }
382
383 if (LocVT == MVT::i32 ||
384 LocVT == MVT::f32) {
385 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
386 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
387 return false;
388 }
389
390 if (LocVT == MVT::i64 ||
391 LocVT == MVT::f64 ||
392 LocVT == MVT::v1f64 ||
393 LocVT == MVT::v2f32 ||
394 LocVT == MVT::v1i64 ||
395 LocVT == MVT::v2i32 ||
396 LocVT == MVT::v4i16 ||
397 LocVT == MVT::v8i8 ||
398 LocVT == MVT::v4f16 ||
399 LocVT == MVT::v4bf16) {
400 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
401 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
402 return false;
403 }
404
405 if (LocVT == MVT::f128 ||
406 LocVT == MVT::v2i64 ||
407 LocVT == MVT::v4i32 ||
408 LocVT == MVT::v8i16 ||
409 LocVT == MVT::v16i8 ||
410 LocVT == MVT::v4f32 ||
411 LocVT == MVT::v2f64 ||
412 LocVT == MVT::v8f16 ||
413 LocVT == MVT::v8bf16) {
414 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
415 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
416 return false;
417 }
418
419 return true; // CC didn't match.
420}
421
422
423bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
424 MVT LocVT, CCValAssign::LocInfo LocInfo,
425 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
426
427 if (LocVT == MVT::i64) {
428 static const MCPhysReg RegList1[] = {
429 AArch64::X11, AArch64::X10, AArch64::X9
430 };
431 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
432 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
433 return false;
434 }
435 }
436
437 return true; // CC didn't match.
438}
439
440
441bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
442 MVT LocVT, CCValAssign::LocInfo LocInfo,
443 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
444
445 if (ArgFlags.isInReg()) {
446 if (LocVT == MVT::i64) {
447 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
448 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
449 return false;
450 }
451 }
452 }
453
454 if (ArgFlags.isByVal()) {
455 LocVT = MVT::i64;
456 LocInfo = CCValAssign::Indirect;
457 }
458
459 if (LocVT == MVT::i1 ||
460 LocVT == MVT::i8 ||
461 LocVT == MVT::i16) {
462 LocVT = MVT::i32;
463 if (ArgFlags.isSExt())
464 LocInfo = CCValAssign::SExt;
465 else if (ArgFlags.isZExt())
466 LocInfo = CCValAssign::ZExt;
467 else
468 LocInfo = CCValAssign::AExt;
469 }
470
471 if (ArgFlags.isNest()) {
472 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
473 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
474 return false;
475 }
476 }
477
478 if (ArgFlags.isSwiftError()) {
479 if (LocVT == MVT::i64) {
480 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
481 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
482 return false;
483 }
484 }
485 }
486
487 if (ArgFlags.isSwiftSelf()) {
488 if (LocVT == MVT::i64) {
489 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
490 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
491 return false;
492 }
493 }
494 }
495
496 if (ArgFlags.isSwiftAsync()) {
497 if (LocVT == MVT::i64) {
498 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
499 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
500 return false;
501 }
502 }
503 }
504
505 if (ArgFlags.isCFGuardTarget()) {
506 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
507 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
508 return false;
509 }
510 }
511
512 if (LocVT == MVT::v16i8 ||
513 LocVT == MVT::v8i16 ||
514 LocVT == MVT::v4i32 ||
515 LocVT == MVT::v2i64 ||
516 LocVT == MVT::v8f16 ||
517 LocVT == MVT::v4f32 ||
518 LocVT == MVT::v2f64) {
519 LocVT = MVT::i64;
520 LocInfo = CCValAssign::Indirect;
521 }
522
523 if (LocVT == MVT::v32i8 ||
524 LocVT == MVT::v16i16 ||
525 LocVT == MVT::v8i32 ||
526 LocVT == MVT::v4i64 ||
527 LocVT == MVT::v16f16 ||
528 LocVT == MVT::v8f32 ||
529 LocVT == MVT::v4f64) {
530 LocVT = MVT::i64;
531 LocInfo = CCValAssign::Indirect;
532 }
533
534 if (LocVT == MVT::v64i8 ||
535 LocVT == MVT::v32i16 ||
536 LocVT == MVT::v16i32 ||
537 LocVT == MVT::v32f16 ||
538 LocVT == MVT::v16f32 ||
539 LocVT == MVT::v8f64 ||
540 LocVT == MVT::v8i64) {
541 LocVT = MVT::i64;
542 LocInfo = CCValAssign::Indirect;
543 }
544
545 if (LocVT == MVT::f80) {
546 LocVT = MVT::i64;
547 LocInfo = CCValAssign::Indirect;
548 }
549
550 if (LocVT == MVT::x86mmx) {
551 LocVT = MVT::i64;
552 LocInfo = CCValAssign::BCvt;
553 }
554
555 if (LocVT == MVT::f16) {
556 static const MCPhysReg RegList1[] = {
557 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
558 };
559 static const MCPhysReg RegList2[] = {
560 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
561 };
562 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
563 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
564 return false;
565 }
566 }
567
568 if (LocVT == MVT::f32) {
569 static const MCPhysReg RegList3[] = {
570 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3
571 };
572 static const MCPhysReg RegList4[] = {
573 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
574 };
575 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
576 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
577 return false;
578 }
579 }
580
581 if (LocVT == MVT::f64) {
582 static const MCPhysReg RegList5[] = {
583 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3
584 };
585 static const MCPhysReg RegList6[] = {
586 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
587 };
588 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
589 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
590 return false;
591 }
592 }
593
594 if (LocVT == MVT::i32) {
595 static const MCPhysReg RegList7[] = {
596 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
597 };
598 static const MCPhysReg RegList8[] = {
599 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
600 };
601 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
602 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
603 return false;
604 }
605 }
606
607 if (LocVT == MVT::i64) {
608 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
609 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
610 return false;
611 }
612 }
613
614 if (LocVT == MVT::i64) {
615 static const MCPhysReg RegList9[] = {
616 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
617 };
618 static const MCPhysReg RegList10[] = {
619 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
620 };
621 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
622 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
623 return false;
624 }
625 }
626
627 if (LocVT == MVT::i8 ||
628 LocVT == MVT::i16 ||
629 LocVT == MVT::i32 ||
630 LocVT == MVT::i64 ||
631 LocVT == MVT::f16 ||
632 LocVT == MVT::f32 ||
633 LocVT == MVT::f64) {
634 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8));
635 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
636 return false;
637 }
638
639 return true; // CC didn't match.
640}
641
642
643bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
644 MVT LocVT, CCValAssign::LocInfo LocInfo,
645 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
646
647 if (LocVT == MVT::i64) {
648 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
649 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
650 return false;
651 }
652 }
653
654 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
655 return false;
656
657 return true; // CC didn't match.
658}
659
660
661bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
662 MVT LocVT, CCValAssign::LocInfo LocInfo,
663 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
664
665 if (ArgFlags.isCFGuardTarget()) {
666 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
667 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
668 return false;
669 }
670 }
671
672 if (ArgFlags.isNest()) {
673 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
674 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
675 return false;
676 }
677 }
678
679 if (LocVT == MVT::f16 ||
680 LocVT == MVT::bf16) {
681 LocVT = MVT::i16;
682 LocInfo = CCValAssign::BCvt;
683 }
684
685 if (LocVT == MVT::f32) {
686 LocVT = MVT::i32;
687 LocInfo = CCValAssign::BCvt;
688 }
689
690 if (LocVT == MVT::f64 ||
691 LocVT == MVT::v1f64 ||
692 LocVT == MVT::v1i64 ||
693 LocVT == MVT::v2f32 ||
694 LocVT == MVT::v2i32 ||
695 LocVT == MVT::v4i16 ||
696 LocVT == MVT::v4f16 ||
697 LocVT == MVT::v4bf16 ||
698 LocVT == MVT::v8i8 ||
699 LocVT == MVT::iPTR) {
700 LocVT = MVT::i64;
701 LocInfo = CCValAssign::BCvt;
702 }
703
704 if (LocVT == MVT::f128 ||
705 LocVT == MVT::v2f64 ||
706 LocVT == MVT::v2i64 ||
707 LocVT == MVT::v4i32 ||
708 LocVT == MVT::v4f32 ||
709 LocVT == MVT::v8i16 ||
710 LocVT == MVT::v8f16 ||
711 LocVT == MVT::v8bf16 ||
712 LocVT == MVT::v16i8) {
713 LocVT = MVT::i64;
714 LocInfo = CCValAssign::Indirect;
715 }
716
717 if (LocVT == MVT::nxv16i8 ||
718 LocVT == MVT::nxv8i16 ||
719 LocVT == MVT::nxv4i32 ||
720 LocVT == MVT::nxv2i64 ||
721 LocVT == MVT::nxv2f16 ||
722 LocVT == MVT::nxv4f16 ||
723 LocVT == MVT::nxv8f16 ||
724 LocVT == MVT::nxv2bf16 ||
725 LocVT == MVT::nxv4bf16 ||
726 LocVT == MVT::nxv8bf16 ||
727 LocVT == MVT::nxv2f32 ||
728 LocVT == MVT::nxv4f32 ||
729 LocVT == MVT::nxv2f64) {
730 LocVT = MVT::i64;
731 LocInfo = CCValAssign::Indirect;
732 }
733
734 if (LocVT == MVT::nxv2i1 ||
735 LocVT == MVT::nxv4i1 ||
736 LocVT == MVT::nxv8i1 ||
737 LocVT == MVT::nxv16i1) {
738 LocVT = MVT::i64;
739 LocInfo = CCValAssign::Indirect;
740 }
741
742 if (ArgFlags.isInReg()) {
743 if (LocVT == MVT::i64) {
744 if (ArgFlags.isSRet()) {
745 if (LocVT == MVT::i64) {
746 static const MCPhysReg RegList1[] = {
747 AArch64::X0, AArch64::X1
748 };
749 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
750 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
751 return false;
752 }
753 }
754 }
755 }
756 }
757
758 if (ArgFlags.isSRet()) {
759 if (LocVT == MVT::i64) {
760 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
761 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
762 return false;
763 }
764 }
765 }
766
767 if (ArgFlags.isByVal()) {
768 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
769 return false;
770 }
771
772 if (LocVT == MVT::i1 ||
773 LocVT == MVT::i8 ||
774 LocVT == MVT::i16) {
775 LocVT = MVT::i32;
776 if (ArgFlags.isSExt())
777 LocInfo = CCValAssign::SExt;
778 else if (ArgFlags.isZExt())
779 LocInfo = CCValAssign::ZExt;
780 else
781 LocInfo = CCValAssign::AExt;
782 }
783
784 if (LocVT == MVT::i32) {
785 static const MCPhysReg RegList2[] = {
786 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
787 };
788 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
789 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
790 return false;
791 }
792 }
793
794 if (LocVT == MVT::i64) {
795 static const MCPhysReg RegList3[] = {
796 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
797 };
798 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
799 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
800 return false;
801 }
802 }
803
804 if (LocVT == MVT::i32 ||
805 LocVT == MVT::i64) {
806 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
807 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
808 return false;
809 }
810
811 return true; // CC didn't match.
812}
813
814
815bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
816 MVT LocVT, CCValAssign::LocInfo LocInfo,
817 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
818
819 if (ArgFlags.isNest()) {
820 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
821 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
822 return false;
823 }
824 }
825
826 if (LocVT == MVT::iPTR) {
827 LocVT = MVT::i64;
828 LocInfo = CCValAssign::BCvt;
829 }
830
831 if (LocVT == MVT::v2f32) {
832 LocVT = MVT::v2i32;
833 LocInfo = CCValAssign::BCvt;
834 }
835
836 if (LocVT == MVT::v2f64 ||
837 LocVT == MVT::v4f32 ||
838 LocVT == MVT::f128) {
839 LocVT = MVT::v2i64;
840 LocInfo = CCValAssign::BCvt;
841 }
842
843 if (ArgFlags.isSRet()) {
844 if (LocVT == MVT::i64) {
845 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
846 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
847 return false;
848 }
849 }
850 }
851
852 if (ArgFlags.isByVal()) {
853 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
854 return false;
855 }
856
857 if (ArgFlags.isSwiftSelf()) {
858 if (LocVT == MVT::i64) {
859 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
860 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
861 return false;
862 }
863 }
864 }
865
866 if (ArgFlags.isSwiftError()) {
867 if (LocVT == MVT::i64) {
868 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
869 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
870 return false;
871 }
872 }
873 }
874
875 if (ArgFlags.isSwiftAsync()) {
876 if (LocVT == MVT::i64) {
877 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
878 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
879 return false;
880 }
881 }
882 }
883
884 if (ArgFlags.isInConsecutiveRegs()) {
885 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
886 return false;
887 }
888
889 if (LocVT == MVT::nxv16i8 ||
890 LocVT == MVT::nxv8i16 ||
891 LocVT == MVT::nxv4i32 ||
892 LocVT == MVT::nxv2i64 ||
893 LocVT == MVT::nxv2f16 ||
894 LocVT == MVT::nxv4f16 ||
895 LocVT == MVT::nxv8f16 ||
896 LocVT == MVT::nxv2bf16 ||
897 LocVT == MVT::nxv4bf16 ||
898 LocVT == MVT::nxv8bf16 ||
899 LocVT == MVT::nxv2f32 ||
900 LocVT == MVT::nxv4f32 ||
901 LocVT == MVT::nxv2f64) {
902 static const MCPhysReg RegList1[] = {
903 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
904 };
905 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
906 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
907 return false;
908 }
909 }
910
911 if (LocVT == MVT::nxv16i8 ||
912 LocVT == MVT::nxv8i16 ||
913 LocVT == MVT::nxv4i32 ||
914 LocVT == MVT::nxv2i64 ||
915 LocVT == MVT::nxv2f16 ||
916 LocVT == MVT::nxv4f16 ||
917 LocVT == MVT::nxv8f16 ||
918 LocVT == MVT::nxv2bf16 ||
919 LocVT == MVT::nxv4bf16 ||
920 LocVT == MVT::nxv8bf16 ||
921 LocVT == MVT::nxv2f32 ||
922 LocVT == MVT::nxv4f32 ||
923 LocVT == MVT::nxv2f64) {
924 LocVT = MVT::i64;
925 LocInfo = CCValAssign::Indirect;
926 }
927
928 if (LocVT == MVT::nxv1i1 ||
929 LocVT == MVT::nxv2i1 ||
930 LocVT == MVT::nxv4i1 ||
931 LocVT == MVT::nxv8i1 ||
932 LocVT == MVT::nxv16i1 ||
933 LocVT == MVT::aarch64svcount) {
934 static const MCPhysReg RegList2[] = {
935 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
936 };
937 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
938 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
939 return false;
940 }
941 }
942
943 if (LocVT == MVT::nxv1i1 ||
944 LocVT == MVT::nxv2i1 ||
945 LocVT == MVT::nxv4i1 ||
946 LocVT == MVT::nxv8i1 ||
947 LocVT == MVT::nxv16i1 ||
948 LocVT == MVT::aarch64svcount) {
949 LocVT = MVT::i64;
950 LocInfo = CCValAssign::Indirect;
951 }
952
953 if (LocVT == MVT::i1 ||
954 LocVT == MVT::i8 ||
955 LocVT == MVT::i16) {
956 LocVT = MVT::i32;
957 if (ArgFlags.isSExt())
958 LocInfo = CCValAssign::SExt;
959 else if (ArgFlags.isZExt())
960 LocInfo = CCValAssign::ZExt;
961 else
962 LocInfo = CCValAssign::AExt;
963 }
964
965 if (LocVT == MVT::i32) {
966 static const MCPhysReg RegList3[] = {
967 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
968 };
969 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
970 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
971 return false;
972 }
973 }
974
975 if (LocVT == MVT::i64) {
976 if (ArgFlags.isSplit()) {
977 static const MCPhysReg RegList4[] = {
978 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
979 };
980 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
981 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
982 return false;
983 }
984 }
985 }
986
987 if (LocVT == MVT::i64) {
988 if (ArgFlags.isSplit()) {
989 static const MCPhysReg ShadowRegList5[] = {
990 AArch64::X7
991 };
992 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList5);
993 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
994 return false;
995 }
996 }
997
998 if (LocVT == MVT::i64) {
999 static const MCPhysReg RegList7[] = {
1000 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1001 };
1002 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
1003 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1004 return false;
1005 }
1006 }
1007
1008 if (LocVT == MVT::f16) {
1009 static const MCPhysReg RegList8[] = {
1010 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1011 };
1012 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
1013 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1014 return false;
1015 }
1016 }
1017
1018 if (LocVT == MVT::bf16) {
1019 static const MCPhysReg RegList9[] = {
1020 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1021 };
1022 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1023 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1024 return false;
1025 }
1026 }
1027
1028 if (LocVT == MVT::f32) {
1029 static const MCPhysReg RegList10[] = {
1030 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1031 };
1032 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1033 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1034 return false;
1035 }
1036 }
1037
1038 if (LocVT == MVT::f64) {
1039 static const MCPhysReg RegList11[] = {
1040 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1041 };
1042 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1043 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1044 return false;
1045 }
1046 }
1047
1048 if (LocVT == MVT::v1i64 ||
1049 LocVT == MVT::v2i32 ||
1050 LocVT == MVT::v4i16 ||
1051 LocVT == MVT::v8i8 ||
1052 LocVT == MVT::v1f64 ||
1053 LocVT == MVT::v2f32 ||
1054 LocVT == MVT::v4f16 ||
1055 LocVT == MVT::v4bf16) {
1056 static const MCPhysReg RegList12[] = {
1057 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1058 };
1059 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1060 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1061 return false;
1062 }
1063 }
1064
1065 if (LocVT == MVT::v2i64 ||
1066 LocVT == MVT::v4i32 ||
1067 LocVT == MVT::v8i16 ||
1068 LocVT == MVT::v16i8 ||
1069 LocVT == MVT::v4f32 ||
1070 LocVT == MVT::v2f64 ||
1071 LocVT == MVT::v8f16 ||
1072 LocVT == MVT::v8bf16) {
1073 static const MCPhysReg RegList13[] = {
1074 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1075 };
1076 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1077 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1078 return false;
1079 }
1080 }
1081
1082 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
1083 int64_t Offset14 = State.AllocateStack(Size: 1, Alignment: Align(1));
1084 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1085 return false;
1086 }
1087
1088 if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) {
1089 int64_t Offset15 = State.AllocateStack(Size: 2, Alignment: Align(2));
1090 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
1091 return false;
1092 }
1093
1094 if (LocVT == MVT::i32 ||
1095 LocVT == MVT::f32) {
1096 int64_t Offset16 = State.AllocateStack(Size: 4, Alignment: Align(4));
1097 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1098 return false;
1099 }
1100
1101 if (ArgFlags.isPointer()) {
1102 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1103 LocVT = MVT::i32;
1104 LocInfo = CCValAssign::Trunc;
1105 }
1106 }
1107
1108 if (ArgFlags.isPointer()) {
1109 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1110 int64_t Offset17 = State.AllocateStack(Size: 4, Alignment: Align(4));
1111 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1112 return false;
1113 }
1114 }
1115
1116 if (LocVT == MVT::i64 ||
1117 LocVT == MVT::f64 ||
1118 LocVT == MVT::v1f64 ||
1119 LocVT == MVT::v2f32 ||
1120 LocVT == MVT::v1i64 ||
1121 LocVT == MVT::v2i32 ||
1122 LocVT == MVT::v4i16 ||
1123 LocVT == MVT::v8i8 ||
1124 LocVT == MVT::v4f16 ||
1125 LocVT == MVT::v4bf16) {
1126 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1127 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1128 return false;
1129 }
1130
1131 if (LocVT == MVT::v2i64 ||
1132 LocVT == MVT::v4i32 ||
1133 LocVT == MVT::v8i16 ||
1134 LocVT == MVT::v16i8 ||
1135 LocVT == MVT::v4f32 ||
1136 LocVT == MVT::v2f64 ||
1137 LocVT == MVT::v8f16 ||
1138 LocVT == MVT::v8bf16) {
1139 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1140 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1141 return false;
1142 }
1143
1144 return true; // CC didn't match.
1145}
1146
1147
1148bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
1149 MVT LocVT, CCValAssign::LocInfo LocInfo,
1150 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1151
1152 if (ArgFlags.isNest()) {
1153 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1154 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1155 return false;
1156 }
1157 }
1158
1159 if (LocVT == MVT::v2f32) {
1160 LocVT = MVT::v2i32;
1161 LocInfo = CCValAssign::BCvt;
1162 }
1163
1164 if (LocVT == MVT::v2f64 ||
1165 LocVT == MVT::v4f32 ||
1166 LocVT == MVT::f128) {
1167 LocVT = MVT::v2i64;
1168 LocInfo = CCValAssign::BCvt;
1169 }
1170
1171 if (LocVT == MVT::i8 ||
1172 LocVT == MVT::i16) {
1173 LocVT = MVT::i32;
1174 if (ArgFlags.isSExt())
1175 LocInfo = CCValAssign::SExt;
1176 else if (ArgFlags.isZExt())
1177 LocInfo = CCValAssign::ZExt;
1178 else
1179 LocInfo = CCValAssign::AExt;
1180 }
1181
1182 if (LocVT == MVT::f16 ||
1183 LocVT == MVT::bf16) {
1184 LocVT = MVT::f32;
1185 LocInfo = CCValAssign::FPExt;
1186 }
1187
1188 if (ArgFlags.isPointer()) {
1189 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1190 LocVT = MVT::i32;
1191 LocInfo = CCValAssign::Trunc;
1192 }
1193 }
1194
1195 if (LocVT == MVT::i32 ||
1196 LocVT == MVT::f32) {
1197 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1198 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1199 return false;
1200 }
1201
1202 if (LocVT == MVT::i64) {
1203 if (ArgFlags.isSplit()) {
1204 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(16));
1205 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1206 return false;
1207 }
1208 }
1209
1210 if (LocVT == MVT::i64 ||
1211 LocVT == MVT::f64 ||
1212 LocVT == MVT::v1i64 ||
1213 LocVT == MVT::v2i32 ||
1214 LocVT == MVT::v4i16 ||
1215 LocVT == MVT::v8i8 ||
1216 LocVT == MVT::v1f64 ||
1217 LocVT == MVT::v2f32 ||
1218 LocVT == MVT::v4f16 ||
1219 LocVT == MVT::v4bf16) {
1220 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
1221 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1222 return false;
1223 }
1224
1225 if (LocVT == MVT::v2i64 ||
1226 LocVT == MVT::v4i32 ||
1227 LocVT == MVT::v8i16 ||
1228 LocVT == MVT::v16i8 ||
1229 LocVT == MVT::v4f32 ||
1230 LocVT == MVT::v2f64 ||
1231 LocVT == MVT::v8f16 ||
1232 LocVT == MVT::v8bf16) {
1233 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(16));
1234 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
1235 return false;
1236 }
1237
1238 return true; // CC didn't match.
1239}
1240
1241
1242bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
1243 MVT LocVT, CCValAssign::LocInfo LocInfo,
1244 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1245
1246 if (ArgFlags.isNest()) {
1247 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1248 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1249 return false;
1250 }
1251 }
1252
1253 if (LocVT == MVT::iPTR) {
1254 LocVT = MVT::i64;
1255 LocInfo = CCValAssign::BCvt;
1256 }
1257
1258 if (LocVT == MVT::v2f32) {
1259 LocVT = MVT::v2i32;
1260 LocInfo = CCValAssign::BCvt;
1261 }
1262
1263 if (LocVT == MVT::v2f64 ||
1264 LocVT == MVT::v4f32 ||
1265 LocVT == MVT::f128) {
1266 LocVT = MVT::v2i64;
1267 LocInfo = CCValAssign::BCvt;
1268 }
1269
1270 if (ArgFlags.isInConsecutiveRegs()) {
1271 if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1272 return false;
1273 }
1274
1275 if (LocVT == MVT::i8 ||
1276 LocVT == MVT::i16 ||
1277 LocVT == MVT::i32) {
1278 LocVT = MVT::i64;
1279 if (ArgFlags.isSExt())
1280 LocInfo = CCValAssign::SExt;
1281 else if (ArgFlags.isZExt())
1282 LocInfo = CCValAssign::ZExt;
1283 else
1284 LocInfo = CCValAssign::AExt;
1285 }
1286
1287 if (LocVT == MVT::f16 ||
1288 LocVT == MVT::bf16 ||
1289 LocVT == MVT::f32) {
1290 LocVT = MVT::f64;
1291 LocInfo = CCValAssign::FPExt;
1292 }
1293
1294 if (LocVT == MVT::i64) {
1295 if (ArgFlags.isSplit()) {
1296 int64_t Offset1 = State.AllocateStack(Size: 8, Alignment: Align(16));
1297 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1298 return false;
1299 }
1300 }
1301
1302 if (LocVT == MVT::i64 ||
1303 LocVT == MVT::f64 ||
1304 LocVT == MVT::v1i64 ||
1305 LocVT == MVT::v2i32 ||
1306 LocVT == MVT::v4i16 ||
1307 LocVT == MVT::v8i8 ||
1308 LocVT == MVT::v1f64 ||
1309 LocVT == MVT::v2f32 ||
1310 LocVT == MVT::v4f16 ||
1311 LocVT == MVT::v4bf16) {
1312 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
1313 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1314 return false;
1315 }
1316
1317 if (LocVT == MVT::v2i64 ||
1318 LocVT == MVT::v4i32 ||
1319 LocVT == MVT::v8i16 ||
1320 LocVT == MVT::v16i8 ||
1321 LocVT == MVT::v4f32 ||
1322 LocVT == MVT::v2f64 ||
1323 LocVT == MVT::v8f16 ||
1324 LocVT == MVT::v8bf16) {
1325 int64_t Offset3 = State.AllocateStack(Size: 16, Alignment: Align(16));
1326 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1327 return false;
1328 }
1329
1330 return true; // CC didn't match.
1331}
1332
1333
1334bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
1335 MVT LocVT, CCValAssign::LocInfo LocInfo,
1336 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1337
1338 if (ArgFlags.isNest()) {
1339 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1340 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1341 return false;
1342 }
1343 }
1344
1345 if (LocVT == MVT::iPTR) {
1346 LocVT = MVT::i64;
1347 LocInfo = CCValAssign::BCvt;
1348 }
1349
1350 if (LocVT == MVT::v1i64 ||
1351 LocVT == MVT::v2i32 ||
1352 LocVT == MVT::v4i16 ||
1353 LocVT == MVT::v8i8 ||
1354 LocVT == MVT::v2f32) {
1355 LocVT = MVT::f64;
1356 LocInfo = CCValAssign::BCvt;
1357 }
1358
1359 if (LocVT == MVT::v2i64 ||
1360 LocVT == MVT::v4i32 ||
1361 LocVT == MVT::v8i16 ||
1362 LocVT == MVT::v16i8 ||
1363 LocVT == MVT::v4f32 ||
1364 LocVT == MVT::f128) {
1365 LocVT = MVT::v2f64;
1366 LocInfo = CCValAssign::BCvt;
1367 }
1368
1369 if (LocVT == MVT::v2f64) {
1370 static const MCPhysReg RegList1[] = {
1371 AArch64::Q4, AArch64::Q5
1372 };
1373 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1374 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1375 return false;
1376 }
1377 }
1378
1379 if (LocVT == MVT::f32) {
1380 static const MCPhysReg RegList2[] = {
1381 AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
1382 };
1383 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1384 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1385 return false;
1386 }
1387 }
1388
1389 if (LocVT == MVT::f64) {
1390 static const MCPhysReg RegList3[] = {
1391 AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
1392 };
1393 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1394 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1395 return false;
1396 }
1397 }
1398
1399 if (LocVT == MVT::i8 ||
1400 LocVT == MVT::i16 ||
1401 LocVT == MVT::i32) {
1402 LocVT = MVT::i64;
1403 if (ArgFlags.isSExt())
1404 LocInfo = CCValAssign::SExt;
1405 else if (ArgFlags.isZExt())
1406 LocInfo = CCValAssign::ZExt;
1407 else
1408 LocInfo = CCValAssign::AExt;
1409 }
1410
1411 if (LocVT == MVT::i64) {
1412 static const MCPhysReg RegList4[] = {
1413 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
1414 };
1415 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1416 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1417 return false;
1418 }
1419 }
1420
1421 return true; // CC didn't match.
1422}
1423
1424
1425bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
1426 MVT LocVT, CCValAssign::LocInfo LocInfo,
1427 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1428
1429 if (State.isVarArg()) {
1430 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
1431 if (!CC_AArch64_DarwinPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1432 return false;
1433 }
1434 }
1435
1436 if (State.isVarArg()) {
1437 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1438 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1439 return false;
1440 }
1441 }
1442
1443 if (State.isVarArg()) {
1444 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1445 return false;
1446 }
1447
1448 if (LocVT == MVT::i32) {
1449 static const MCPhysReg RegList1[] = {
1450 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W9
1451 };
1452 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1453 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1454 return false;
1455 }
1456 }
1457
1458 if (LocVT == MVT::i64) {
1459 static const MCPhysReg RegList2[] = {
1460 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X9
1461 };
1462 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1463 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1464 return false;
1465 }
1466 }
1467
1468 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1469 if (LocVT == MVT::i32) {
1470 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::W15)) {
1471 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1472 return false;
1473 }
1474 }
1475 }
1476
1477 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1478 if (LocVT == MVT::i64) {
1479 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1480 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1481 return false;
1482 }
1483 }
1484 }
1485
1486 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1487 return false;
1488
1489 return true; // CC didn't match.
1490}
1491
1492
1493bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
1494 MVT LocVT, CCValAssign::LocInfo LocInfo,
1495 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1496
1497 if (ArgFlags.isCFGuardTarget()) {
1498 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
1499 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1500 return false;
1501 }
1502 }
1503
1504 if (ArgFlags.isNest()) {
1505 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1506 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1507 return false;
1508 }
1509 }
1510
1511 if (LocVT == MVT::iPTR) {
1512 LocVT = MVT::i64;
1513 LocInfo = CCValAssign::BCvt;
1514 }
1515
1516 if (LocVT == MVT::v2f32) {
1517 LocVT = MVT::v2i32;
1518 LocInfo = CCValAssign::BCvt;
1519 }
1520
1521 if (LocVT == MVT::v2f64 ||
1522 LocVT == MVT::v4f32) {
1523 LocVT = MVT::v2i64;
1524 LocInfo = CCValAssign::BCvt;
1525 }
1526
1527 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1528 if (LocVT == MVT::v2i32 ||
1529 LocVT == MVT::v2f32 ||
1530 LocVT == MVT::v4i16 ||
1531 LocVT == MVT::v4f16 ||
1532 LocVT == MVT::v4bf16 ||
1533 LocVT == MVT::v8i8) {
1534 LocVT = MVT::f64;
1535 LocInfo = CCValAssign::BCvt;
1536 }
1537 }
1538
1539 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1540 if (LocVT == MVT::v2i64 ||
1541 LocVT == MVT::v2f64 ||
1542 LocVT == MVT::v4i32 ||
1543 LocVT == MVT::v4f32 ||
1544 LocVT == MVT::v8i16 ||
1545 LocVT == MVT::v8f16 ||
1546 LocVT == MVT::v8bf16 ||
1547 LocVT == MVT::v16i8) {
1548 LocVT = MVT::f128;
1549 LocInfo = CCValAssign::BCvt;
1550 }
1551 }
1552
1553 if (ArgFlags.isInReg()) {
1554 if (LocVT == MVT::i64) {
1555 if (ArgFlags.isSRet()) {
1556 if (LocVT == MVT::i64) {
1557 static const MCPhysReg RegList1[] = {
1558 AArch64::X0, AArch64::X1
1559 };
1560 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1561 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1562 return false;
1563 }
1564 }
1565 }
1566 }
1567 }
1568
1569 if (ArgFlags.isSRet()) {
1570 if (LocVT == MVT::i64) {
1571 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
1572 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1573 return false;
1574 }
1575 }
1576 }
1577
1578 if (ArgFlags.isByVal()) {
1579 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1580 return false;
1581 }
1582
1583 if (ArgFlags.isSwiftSelf()) {
1584 if (LocVT == MVT::i64) {
1585 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
1586 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1587 return false;
1588 }
1589 }
1590 }
1591
1592 if (ArgFlags.isSwiftError()) {
1593 if (LocVT == MVT::i64) {
1594 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1595 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1596 return false;
1597 }
1598 }
1599 }
1600
1601 if (ArgFlags.isSwiftAsync()) {
1602 if (LocVT == MVT::i64) {
1603 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
1604 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1605 return false;
1606 }
1607 }
1608 }
1609
1610 if (ArgFlags.isInConsecutiveRegs()) {
1611 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1612 return false;
1613 }
1614
1615 if (LocVT == MVT::nxv16i8 ||
1616 LocVT == MVT::nxv8i16 ||
1617 LocVT == MVT::nxv4i32 ||
1618 LocVT == MVT::nxv2i64 ||
1619 LocVT == MVT::nxv2f16 ||
1620 LocVT == MVT::nxv4f16 ||
1621 LocVT == MVT::nxv8f16 ||
1622 LocVT == MVT::nxv2bf16 ||
1623 LocVT == MVT::nxv4bf16 ||
1624 LocVT == MVT::nxv8bf16 ||
1625 LocVT == MVT::nxv2f32 ||
1626 LocVT == MVT::nxv4f32 ||
1627 LocVT == MVT::nxv2f64) {
1628 static const MCPhysReg RegList2[] = {
1629 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1630 };
1631 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1632 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1633 return false;
1634 }
1635 }
1636
1637 if (LocVT == MVT::nxv16i8 ||
1638 LocVT == MVT::nxv8i16 ||
1639 LocVT == MVT::nxv4i32 ||
1640 LocVT == MVT::nxv2i64 ||
1641 LocVT == MVT::nxv2f16 ||
1642 LocVT == MVT::nxv4f16 ||
1643 LocVT == MVT::nxv8f16 ||
1644 LocVT == MVT::nxv2bf16 ||
1645 LocVT == MVT::nxv4bf16 ||
1646 LocVT == MVT::nxv8bf16 ||
1647 LocVT == MVT::nxv2f32 ||
1648 LocVT == MVT::nxv4f32 ||
1649 LocVT == MVT::nxv2f64) {
1650 LocVT = MVT::i64;
1651 LocInfo = CCValAssign::Indirect;
1652 }
1653
1654 if (LocVT == MVT::nxv1i1 ||
1655 LocVT == MVT::nxv2i1 ||
1656 LocVT == MVT::nxv4i1 ||
1657 LocVT == MVT::nxv8i1 ||
1658 LocVT == MVT::nxv16i1 ||
1659 LocVT == MVT::aarch64svcount) {
1660 static const MCPhysReg RegList3[] = {
1661 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
1662 };
1663 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1664 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1665 return false;
1666 }
1667 }
1668
1669 if (LocVT == MVT::nxv1i1 ||
1670 LocVT == MVT::nxv2i1 ||
1671 LocVT == MVT::nxv4i1 ||
1672 LocVT == MVT::nxv8i1 ||
1673 LocVT == MVT::nxv16i1 ||
1674 LocVT == MVT::aarch64svcount) {
1675 LocVT = MVT::i64;
1676 LocInfo = CCValAssign::Indirect;
1677 }
1678
1679 if (LocVT == MVT::i1 ||
1680 LocVT == MVT::i8 ||
1681 LocVT == MVT::i16) {
1682 LocVT = MVT::i32;
1683 if (ArgFlags.isSExt())
1684 LocInfo = CCValAssign::SExt;
1685 else if (ArgFlags.isZExt())
1686 LocInfo = CCValAssign::ZExt;
1687 else
1688 LocInfo = CCValAssign::AExt;
1689 }
1690
1691 if (LocVT == MVT::i32) {
1692 static const MCPhysReg RegList4[] = {
1693 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1694 };
1695 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1696 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1697 return false;
1698 }
1699 }
1700
1701 if (LocVT == MVT::i64) {
1702 if (ArgFlags.isSplit()) {
1703 static const MCPhysReg RegList5[] = {
1704 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
1705 };
1706 static const MCPhysReg RegList6[] = {
1707 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
1708 };
1709 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
1710 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1711 return false;
1712 }
1713 }
1714 }
1715
1716 if (LocVT == MVT::i64) {
1717 if (ArgFlags.isSplit()) {
1718 static const MCPhysReg ShadowRegList7[] = {
1719 AArch64::X7
1720 };
1721 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
1722 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1723 return false;
1724 }
1725 }
1726
1727 if (LocVT == MVT::i64) {
1728 static const MCPhysReg RegList9[] = {
1729 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1730 };
1731 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1732 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1733 return false;
1734 }
1735 }
1736
1737 if (LocVT == MVT::f16) {
1738 static const MCPhysReg RegList10[] = {
1739 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1740 };
1741 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1742 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1743 return false;
1744 }
1745 }
1746
1747 if (LocVT == MVT::bf16) {
1748 static const MCPhysReg RegList11[] = {
1749 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1750 };
1751 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1752 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1753 return false;
1754 }
1755 }
1756
1757 if (LocVT == MVT::f32) {
1758 static const MCPhysReg RegList12[] = {
1759 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1760 };
1761 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1762 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1763 return false;
1764 }
1765 }
1766
1767 if (LocVT == MVT::f64) {
1768 static const MCPhysReg RegList13[] = {
1769 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1770 };
1771 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1772 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1773 return false;
1774 }
1775 }
1776
1777 if (LocVT == MVT::v1i64 ||
1778 LocVT == MVT::v2i32 ||
1779 LocVT == MVT::v4i16 ||
1780 LocVT == MVT::v8i8 ||
1781 LocVT == MVT::v1f64 ||
1782 LocVT == MVT::v2f32 ||
1783 LocVT == MVT::v4f16 ||
1784 LocVT == MVT::v4bf16) {
1785 static const MCPhysReg RegList14[] = {
1786 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1787 };
1788 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
1789 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1790 return false;
1791 }
1792 }
1793
1794 if (LocVT == MVT::f128 ||
1795 LocVT == MVT::v2i64 ||
1796 LocVT == MVT::v4i32 ||
1797 LocVT == MVT::v8i16 ||
1798 LocVT == MVT::v16i8 ||
1799 LocVT == MVT::v4f32 ||
1800 LocVT == MVT::v2f64 ||
1801 LocVT == MVT::v8f16 ||
1802 LocVT == MVT::v8bf16) {
1803 static const MCPhysReg RegList15[] = {
1804 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1805 };
1806 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
1807 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1808 return false;
1809 }
1810 }
1811
1812 if (LocVT == MVT::i1 ||
1813 LocVT == MVT::i8 ||
1814 LocVT == MVT::i16 ||
1815 LocVT == MVT::f16 ||
1816 LocVT == MVT::bf16) {
1817 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
1818 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1819 return false;
1820 }
1821
1822 if (LocVT == MVT::i32 ||
1823 LocVT == MVT::f32) {
1824 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
1825 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1826 return false;
1827 }
1828
1829 if (LocVT == MVT::i64 ||
1830 LocVT == MVT::f64 ||
1831 LocVT == MVT::v1f64 ||
1832 LocVT == MVT::v2f32 ||
1833 LocVT == MVT::v1i64 ||
1834 LocVT == MVT::v2i32 ||
1835 LocVT == MVT::v4i16 ||
1836 LocVT == MVT::v8i8 ||
1837 LocVT == MVT::v4f16 ||
1838 LocVT == MVT::v4bf16) {
1839 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1840 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1841 return false;
1842 }
1843
1844 if (LocVT == MVT::f128 ||
1845 LocVT == MVT::v2i64 ||
1846 LocVT == MVT::v4i32 ||
1847 LocVT == MVT::v8i16 ||
1848 LocVT == MVT::v16i8 ||
1849 LocVT == MVT::v4f32 ||
1850 LocVT == MVT::v2f64 ||
1851 LocVT == MVT::v8f16 ||
1852 LocVT == MVT::v8bf16) {
1853 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1854 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1855 return false;
1856 }
1857
1858 return true; // CC didn't match.
1859}
1860
1861
1862bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
1863 MVT LocVT, CCValAssign::LocInfo LocInfo,
1864 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1865
1866 if (LocVT == MVT::i64) {
1867 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1868 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1869 return false;
1870 }
1871 }
1872
1873 return true; // CC didn't match.
1874}
1875
1876
1877bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
1878 MVT LocVT, CCValAssign::LocInfo LocInfo,
1879 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1880
1881 if (LocVT == MVT::f16 ||
1882 LocVT == MVT::bf16) {
1883 LocVT = MVT::i16;
1884 LocInfo = CCValAssign::BCvt;
1885 }
1886
1887 if (LocVT == MVT::f32) {
1888 LocVT = MVT::i32;
1889 LocInfo = CCValAssign::BCvt;
1890 }
1891
1892 if (LocVT == MVT::f64) {
1893 LocVT = MVT::i64;
1894 LocInfo = CCValAssign::BCvt;
1895 }
1896
1897 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1898 return false;
1899
1900 return true; // CC didn't match.
1901}
1902
1903
1904bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
1905 MVT LocVT, CCValAssign::LocInfo LocInfo,
1906 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1907
1908 if (LocVT == MVT::iPTR) {
1909 LocVT = MVT::i64;
1910 LocInfo = CCValAssign::BCvt;
1911 }
1912
1913 if (LocVT == MVT::v2f32) {
1914 LocVT = MVT::v2i32;
1915 LocInfo = CCValAssign::BCvt;
1916 }
1917
1918 if (LocVT == MVT::v2f64 ||
1919 LocVT == MVT::v4f32) {
1920 LocVT = MVT::v2i64;
1921 LocInfo = CCValAssign::BCvt;
1922 }
1923
1924 if (ArgFlags.isInConsecutiveRegs()) {
1925 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1926 return false;
1927 }
1928
1929 if (ArgFlags.isSwiftError()) {
1930 if (LocVT == MVT::i64) {
1931 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1932 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1933 return false;
1934 }
1935 }
1936 }
1937
1938 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1939 if (LocVT == MVT::v2i32 ||
1940 LocVT == MVT::v2f32 ||
1941 LocVT == MVT::v4i16 ||
1942 LocVT == MVT::v4f16 ||
1943 LocVT == MVT::v4bf16 ||
1944 LocVT == MVT::v8i8) {
1945 LocVT = MVT::f64;
1946 LocInfo = CCValAssign::BCvt;
1947 }
1948 }
1949
1950 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1951 if (LocVT == MVT::v2i64 ||
1952 LocVT == MVT::v2f64 ||
1953 LocVT == MVT::v4i32 ||
1954 LocVT == MVT::v4f32 ||
1955 LocVT == MVT::v8i16 ||
1956 LocVT == MVT::v8f16 ||
1957 LocVT == MVT::v8bf16 ||
1958 LocVT == MVT::v16i8) {
1959 LocVT = MVT::f128;
1960 LocInfo = CCValAssign::BCvt;
1961 }
1962 }
1963
1964 if (LocVT == MVT::i1 ||
1965 LocVT == MVT::i8 ||
1966 LocVT == MVT::i16) {
1967 LocVT = MVT::i32;
1968 if (ArgFlags.isSExt())
1969 LocInfo = CCValAssign::SExt;
1970 else if (ArgFlags.isZExt())
1971 LocInfo = CCValAssign::ZExt;
1972 else
1973 LocInfo = CCValAssign::AExt;
1974 }
1975
1976 if (LocVT == MVT::i32) {
1977 static const MCPhysReg RegList1[] = {
1978 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1979 };
1980 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1981 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1982 return false;
1983 }
1984 }
1985
1986 if (LocVT == MVT::i64) {
1987 static const MCPhysReg RegList2[] = {
1988 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1989 };
1990 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1991 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1992 return false;
1993 }
1994 }
1995
1996 if (LocVT == MVT::f16) {
1997 static const MCPhysReg RegList3[] = {
1998 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1999 };
2000 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2001 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2002 return false;
2003 }
2004 }
2005
2006 if (LocVT == MVT::bf16) {
2007 static const MCPhysReg RegList4[] = {
2008 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
2009 };
2010 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2011 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2012 return false;
2013 }
2014 }
2015
2016 if (LocVT == MVT::f32) {
2017 static const MCPhysReg RegList5[] = {
2018 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
2019 };
2020 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2021 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2022 return false;
2023 }
2024 }
2025
2026 if (LocVT == MVT::f64) {
2027 static const MCPhysReg RegList6[] = {
2028 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2029 };
2030 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2031 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2032 return false;
2033 }
2034 }
2035
2036 if (LocVT == MVT::v1i64 ||
2037 LocVT == MVT::v2i32 ||
2038 LocVT == MVT::v4i16 ||
2039 LocVT == MVT::v8i8 ||
2040 LocVT == MVT::v1f64 ||
2041 LocVT == MVT::v2f32 ||
2042 LocVT == MVT::v4f16 ||
2043 LocVT == MVT::v4bf16) {
2044 static const MCPhysReg RegList7[] = {
2045 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2046 };
2047 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2048 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2049 return false;
2050 }
2051 }
2052
2053 if (LocVT == MVT::f128 ||
2054 LocVT == MVT::v2i64 ||
2055 LocVT == MVT::v4i32 ||
2056 LocVT == MVT::v8i16 ||
2057 LocVT == MVT::v16i8 ||
2058 LocVT == MVT::v4f32 ||
2059 LocVT == MVT::v2f64 ||
2060 LocVT == MVT::v8f16 ||
2061 LocVT == MVT::v8bf16) {
2062 static const MCPhysReg RegList8[] = {
2063 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
2064 };
2065 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
2066 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2067 return false;
2068 }
2069 }
2070
2071 if (LocVT == MVT::nxv16i8 ||
2072 LocVT == MVT::nxv8i16 ||
2073 LocVT == MVT::nxv4i32 ||
2074 LocVT == MVT::nxv2i64 ||
2075 LocVT == MVT::nxv2f16 ||
2076 LocVT == MVT::nxv4f16 ||
2077 LocVT == MVT::nxv8f16 ||
2078 LocVT == MVT::nxv2bf16 ||
2079 LocVT == MVT::nxv4bf16 ||
2080 LocVT == MVT::nxv8bf16 ||
2081 LocVT == MVT::nxv2f32 ||
2082 LocVT == MVT::nxv4f32 ||
2083 LocVT == MVT::nxv2f64) {
2084 static const MCPhysReg RegList9[] = {
2085 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
2086 };
2087 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
2088 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2089 return false;
2090 }
2091 }
2092
2093 if (LocVT == MVT::nxv1i1 ||
2094 LocVT == MVT::nxv2i1 ||
2095 LocVT == MVT::nxv4i1 ||
2096 LocVT == MVT::nxv8i1 ||
2097 LocVT == MVT::nxv16i1 ||
2098 LocVT == MVT::aarch64svcount) {
2099 static const MCPhysReg RegList10[] = {
2100 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
2101 };
2102 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
2103 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2104 return false;
2105 }
2106 }
2107
2108 return true; // CC didn't match.
2109}
2110
2111
2112bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
2113 MVT LocVT, CCValAssign::LocInfo LocInfo,
2114 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2115
2116 if (LocVT == MVT::i64) {
2117 static const MCPhysReg RegList1[] = {
2118 AArch64::X11, AArch64::X9
2119 };
2120 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2121 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2122 return false;
2123 }
2124 }
2125
2126 return true; // CC didn't match.
2127}
2128
2129
2130bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
2131 MVT LocVT, CCValAssign::LocInfo LocInfo,
2132 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2133
2134 if (LocVT == MVT::x86mmx) {
2135 LocVT = MVT::i64;
2136 LocInfo = CCValAssign::BCvt;
2137 }
2138
2139 if (LocVT == MVT::f16) {
2140 static const MCPhysReg RegList1[] = {
2141 AArch64::H0, AArch64::H1
2142 };
2143 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2144 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2145 return false;
2146 }
2147 }
2148
2149 if (LocVT == MVT::f32) {
2150 static const MCPhysReg RegList2[] = {
2151 AArch64::S0, AArch64::S1
2152 };
2153 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2154 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2155 return false;
2156 }
2157 }
2158
2159 if (LocVT == MVT::f64) {
2160 static const MCPhysReg RegList3[] = {
2161 AArch64::D0, AArch64::D1
2162 };
2163 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2164 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2165 return false;
2166 }
2167 }
2168
2169 if (LocVT == MVT::f128) {
2170 static const MCPhysReg RegList4[] = {
2171 AArch64::Q0, AArch64::Q1
2172 };
2173 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2174 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2175 return false;
2176 }
2177 }
2178
2179 if (ArgFlags.isSwiftError()) {
2180 if (LocVT == MVT::i64) {
2181 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
2182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2183 return false;
2184 }
2185 }
2186 }
2187
2188 if (LocVT == MVT::i1 ||
2189 LocVT == MVT::i8 ||
2190 LocVT == MVT::i16) {
2191 LocVT = MVT::i32;
2192 if (ArgFlags.isSExt())
2193 LocInfo = CCValAssign::SExt;
2194 else if (ArgFlags.isZExt())
2195 LocInfo = CCValAssign::ZExt;
2196 else
2197 LocInfo = CCValAssign::AExt;
2198 }
2199
2200 if (LocVT == MVT::i32) {
2201 static const MCPhysReg RegList5[] = {
2202 AArch64::W8, AArch64::W1, AArch64::W0
2203 };
2204 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2205 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2206 return false;
2207 }
2208 }
2209
2210 if (LocVT == MVT::i64) {
2211 static const MCPhysReg RegList6[] = {
2212 AArch64::X8, AArch64::X1, AArch64::X0
2213 };
2214 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2215 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2216 return false;
2217 }
2218 }
2219
2220 if (LocVT == MVT::v16i8 ||
2221 LocVT == MVT::v8i16 ||
2222 LocVT == MVT::v4i32 ||
2223 LocVT == MVT::v2i64 ||
2224 LocVT == MVT::v8f16 ||
2225 LocVT == MVT::v4f32 ||
2226 LocVT == MVT::v2f64) {
2227 static const MCPhysReg RegList7[] = {
2228 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
2229 };
2230 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2231 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2232 return false;
2233 }
2234 }
2235
2236 return true; // CC didn't match.
2237}
2238
2239#else
2240
2241const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2242const MCRegister CC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X10, AArch64::X11, AArch64::X9 };
2243const MCRegister CC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::X4, AArch64::X8, AArch64::X9 };
2244const MCRegister CC_AArch64_Arm64EC_Thunk_Native_ArgRegs[] = { AArch64::X9 };
2245const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X8, AArch64::X9 };
2246const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2247const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { AArch64::X15 };
2248const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { AArch64::X15 };
2249const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 };
2250const MCRegister CC_AArch64_Preserve_None_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W2, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W9, AArch64::X0, AArch64::X1, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X2, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X9 };
2251const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2252const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 };
2253const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 };
2254const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2255const MCRegister RetCC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X11, AArch64::X9 };
2256const MCRegister RetCC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::H0, AArch64::H1, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::S0, AArch64::S1, AArch64::W0, AArch64::W1, AArch64::W8, AArch64::X0, AArch64::X1, AArch64::X8 };
2257
2258// Registers used by Swift.
2259const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2260const MCRegister CC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19, AArch64::X20, AArch64::X21 };
2261const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2262const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2263const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 };
2264const MCRegister RetCC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19 };
2265
2266#endif // !defined(GET_CC_REGISTER_LISTS)
2267
2268