1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15bool llvm::CC_AArch64_AnyReg(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
23 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
24bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
25 MVT LocVT, CCValAssign::LocInfo LocInfo,
26 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
27bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
28 MVT LocVT, CCValAssign::LocInfo LocInfo,
29 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
30bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
31 MVT LocVT, CCValAssign::LocInfo LocInfo,
32 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
33bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
34 MVT LocVT, CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
36bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
37 MVT LocVT, CCValAssign::LocInfo LocInfo,
38 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
39bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
40 MVT LocVT, CCValAssign::LocInfo LocInfo,
41 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
42bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
43 MVT LocVT, CCValAssign::LocInfo LocInfo,
44 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
45bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
46 MVT LocVT, CCValAssign::LocInfo LocInfo,
47 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
48bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
49 MVT LocVT, CCValAssign::LocInfo LocInfo,
50 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
51bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
52 MVT LocVT, CCValAssign::LocInfo LocInfo,
53 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
54bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
55 MVT LocVT, CCValAssign::LocInfo LocInfo,
56 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
57bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
58 MVT LocVT, CCValAssign::LocInfo LocInfo,
59 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
60bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
61 MVT LocVT, CCValAssign::LocInfo LocInfo,
62 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
63
64
65bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
68
69 if (ArgFlags.isNest()) {
70 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
71 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
72 return false;
73 }
74 }
75
76 if (LocVT == MVT::iPTR) {
77 LocVT = MVT::i64;
78 LocInfo = CCValAssign::BCvt;
79 }
80
81 if (LocVT == MVT::v2f32) {
82 LocVT = MVT::v2i32;
83 LocInfo = CCValAssign::BCvt;
84 }
85
86 if (LocVT == MVT::v2f64 ||
87 LocVT == MVT::v4f32) {
88 LocVT = MVT::v2i64;
89 LocInfo = CCValAssign::BCvt;
90 }
91
92 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
93 if (LocVT == MVT::v2i32 ||
94 LocVT == MVT::v2f32 ||
95 LocVT == MVT::v4i16 ||
96 LocVT == MVT::v4f16 ||
97 LocVT == MVT::v4bf16 ||
98 LocVT == MVT::v8i8) {
99 LocVT = MVT::f64;
100 LocInfo = CCValAssign::BCvt;
101 }
102 }
103
104 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
105 if (LocVT == MVT::v2i64 ||
106 LocVT == MVT::v2f64 ||
107 LocVT == MVT::v4i32 ||
108 LocVT == MVT::v4f32 ||
109 LocVT == MVT::v8i16 ||
110 LocVT == MVT::v8f16 ||
111 LocVT == MVT::v8bf16 ||
112 LocVT == MVT::v16i8) {
113 LocVT = MVT::f128;
114 LocInfo = CCValAssign::BCvt;
115 }
116 }
117
118 if (ArgFlags.isInReg()) {
119 if (LocVT == MVT::i64) {
120 if (ArgFlags.isSRet()) {
121 if (LocVT == MVT::i64) {
122 static const MCPhysReg RegList1[] = {
123 AArch64::X0, AArch64::X1
124 };
125 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
126 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
127 return false;
128 }
129 }
130 }
131 }
132 }
133
134 if (ArgFlags.isSRet()) {
135 if (LocVT == MVT::i64) {
136 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
137 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
138 return false;
139 }
140 }
141 }
142
143 if (ArgFlags.isByVal()) {
144 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
145 return false;
146 }
147
148 if (ArgFlags.isSwiftSelf()) {
149 if (LocVT == MVT::i64) {
150 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
151 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
152 return false;
153 }
154 }
155 }
156
157 if (ArgFlags.isSwiftError()) {
158 if (LocVT == MVT::i64) {
159 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
160 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
161 return false;
162 }
163 }
164 }
165
166 if (ArgFlags.isSwiftAsync()) {
167 if (LocVT == MVT::i64) {
168 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
169 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
170 return false;
171 }
172 }
173 }
174
175 if (ArgFlags.isInConsecutiveRegs()) {
176 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
177 return false;
178 }
179
180 if (LocVT == MVT::nxv16i8 ||
181 LocVT == MVT::nxv8i16 ||
182 LocVT == MVT::nxv4i32 ||
183 LocVT == MVT::nxv2i64 ||
184 LocVT == MVT::nxv2f16 ||
185 LocVT == MVT::nxv4f16 ||
186 LocVT == MVT::nxv8f16 ||
187 LocVT == MVT::nxv2bf16 ||
188 LocVT == MVT::nxv4bf16 ||
189 LocVT == MVT::nxv8bf16 ||
190 LocVT == MVT::nxv2f32 ||
191 LocVT == MVT::nxv4f32 ||
192 LocVT == MVT::nxv2f64) {
193 static const MCPhysReg RegList2[] = {
194 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
195 };
196 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
197 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
198 return false;
199 }
200 }
201
202 if (LocVT == MVT::nxv16i8 ||
203 LocVT == MVT::nxv8i16 ||
204 LocVT == MVT::nxv4i32 ||
205 LocVT == MVT::nxv2i64 ||
206 LocVT == MVT::nxv2f16 ||
207 LocVT == MVT::nxv4f16 ||
208 LocVT == MVT::nxv8f16 ||
209 LocVT == MVT::nxv2bf16 ||
210 LocVT == MVT::nxv4bf16 ||
211 LocVT == MVT::nxv8bf16 ||
212 LocVT == MVT::nxv2f32 ||
213 LocVT == MVT::nxv4f32 ||
214 LocVT == MVT::nxv2f64) {
215 LocVT = MVT::i64;
216 LocInfo = CCValAssign::Indirect;
217 }
218
219 if (LocVT == MVT::nxv1i1 ||
220 LocVT == MVT::nxv2i1 ||
221 LocVT == MVT::nxv4i1 ||
222 LocVT == MVT::nxv8i1 ||
223 LocVT == MVT::nxv16i1 ||
224 LocVT == MVT::aarch64svcount) {
225 static const MCPhysReg RegList3[] = {
226 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
227 };
228 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
229 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
230 return false;
231 }
232 }
233
234 if (LocVT == MVT::nxv1i1 ||
235 LocVT == MVT::nxv2i1 ||
236 LocVT == MVT::nxv4i1 ||
237 LocVT == MVT::nxv8i1 ||
238 LocVT == MVT::nxv16i1 ||
239 LocVT == MVT::aarch64svcount) {
240 LocVT = MVT::i64;
241 LocInfo = CCValAssign::Indirect;
242 }
243
244 if (LocVT == MVT::i1 ||
245 LocVT == MVT::i8 ||
246 LocVT == MVT::i16) {
247 LocVT = MVT::i32;
248 if (ArgFlags.isSExt())
249 LocInfo = CCValAssign::SExt;
250 else if (ArgFlags.isZExt())
251 LocInfo = CCValAssign::ZExt;
252 else
253 LocInfo = CCValAssign::AExt;
254 }
255
256 if (LocVT == MVT::i32) {
257 static const MCPhysReg RegList4[] = {
258 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
259 };
260 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
261 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
262 return false;
263 }
264 }
265
266 if (LocVT == MVT::i64) {
267 if (ArgFlags.isSplit()) {
268 static const MCPhysReg RegList5[] = {
269 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
270 };
271 static const MCPhysReg RegList6[] = {
272 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
273 };
274 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
275 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
276 return false;
277 }
278 }
279 }
280
281 if (LocVT == MVT::i64) {
282 if (ArgFlags.isSplit()) {
283 static const MCPhysReg ShadowRegList7[] = {
284 AArch64::X7
285 };
286 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
287 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
288 return false;
289 }
290 }
291
292 if (LocVT == MVT::i64) {
293 static const MCPhysReg RegList9[] = {
294 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
295 };
296 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
297 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
298 return false;
299 }
300 }
301
302 if (LocVT == MVT::f16) {
303 static const MCPhysReg RegList10[] = {
304 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
305 };
306 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
307 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
308 return false;
309 }
310 }
311
312 if (LocVT == MVT::bf16) {
313 static const MCPhysReg RegList11[] = {
314 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
315 };
316 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
317 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
318 return false;
319 }
320 }
321
322 if (LocVT == MVT::f32) {
323 static const MCPhysReg RegList12[] = {
324 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
325 };
326 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
327 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
328 return false;
329 }
330 }
331
332 if (LocVT == MVT::f64) {
333 static const MCPhysReg RegList13[] = {
334 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
335 };
336 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
337 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
338 return false;
339 }
340 }
341
342 if (LocVT == MVT::v1i64 ||
343 LocVT == MVT::v2i32 ||
344 LocVT == MVT::v4i16 ||
345 LocVT == MVT::v8i8 ||
346 LocVT == MVT::v1f64 ||
347 LocVT == MVT::v2f32 ||
348 LocVT == MVT::v4f16 ||
349 LocVT == MVT::v4bf16) {
350 static const MCPhysReg RegList14[] = {
351 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
352 };
353 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
354 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
355 return false;
356 }
357 }
358
359 if (LocVT == MVT::f128 ||
360 LocVT == MVT::v2i64 ||
361 LocVT == MVT::v4i32 ||
362 LocVT == MVT::v8i16 ||
363 LocVT == MVT::v16i8 ||
364 LocVT == MVT::v4f32 ||
365 LocVT == MVT::v2f64 ||
366 LocVT == MVT::v8f16 ||
367 LocVT == MVT::v8bf16) {
368 static const MCPhysReg RegList15[] = {
369 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
370 };
371 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
372 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
373 return false;
374 }
375 }
376
377 if (LocVT == MVT::i1 ||
378 LocVT == MVT::i8 ||
379 LocVT == MVT::i16 ||
380 LocVT == MVT::f16 ||
381 LocVT == MVT::bf16) {
382 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
383 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
384 return false;
385 }
386
387 if (LocVT == MVT::i32 ||
388 LocVT == MVT::f32) {
389 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
390 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
391 return false;
392 }
393
394 if (LocVT == MVT::i64 ||
395 LocVT == MVT::f64 ||
396 LocVT == MVT::v1f64 ||
397 LocVT == MVT::v2f32 ||
398 LocVT == MVT::v1i64 ||
399 LocVT == MVT::v2i32 ||
400 LocVT == MVT::v4i16 ||
401 LocVT == MVT::v8i8 ||
402 LocVT == MVT::v4f16 ||
403 LocVT == MVT::v4bf16) {
404 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
405 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
406 return false;
407 }
408
409 if (LocVT == MVT::f128 ||
410 LocVT == MVT::v2i64 ||
411 LocVT == MVT::v4i32 ||
412 LocVT == MVT::v8i16 ||
413 LocVT == MVT::v16i8 ||
414 LocVT == MVT::v4f32 ||
415 LocVT == MVT::v2f64 ||
416 LocVT == MVT::v8f16 ||
417 LocVT == MVT::v8bf16) {
418 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
419 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
420 return false;
421 }
422
423 return true; // CC didn't match.
424}
425
426
427bool llvm::CC_AArch64_AnyReg(unsigned ValNo, MVT ValVT,
428 MVT LocVT, CCValAssign::LocInfo LocInfo,
429 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
430
431 if (CC_AArch64_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
432 return false;
433
434 return true; // CC didn't match.
435}
436
437
438bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
439 MVT LocVT, CCValAssign::LocInfo LocInfo,
440 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
441
442 if (LocVT == MVT::i64) {
443 static const MCPhysReg RegList1[] = {
444 AArch64::X11, AArch64::X10, AArch64::X9
445 };
446 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
447 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
448 return false;
449 }
450 }
451
452 return true; // CC didn't match.
453}
454
455
456bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
457 MVT LocVT, CCValAssign::LocInfo LocInfo,
458 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
459
460 if (ArgFlags.isInReg()) {
461 if (LocVT == MVT::i64) {
462 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
463 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
464 return false;
465 }
466 }
467 }
468
469 if (ArgFlags.isByVal()) {
470 LocVT = MVT::i64;
471 LocInfo = CCValAssign::Indirect;
472 }
473
474 if (LocVT == MVT::i1 ||
475 LocVT == MVT::i8 ||
476 LocVT == MVT::i16) {
477 LocVT = MVT::i32;
478 if (ArgFlags.isSExt())
479 LocInfo = CCValAssign::SExt;
480 else if (ArgFlags.isZExt())
481 LocInfo = CCValAssign::ZExt;
482 else
483 LocInfo = CCValAssign::AExt;
484 }
485
486 if (ArgFlags.isNest()) {
487 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
488 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
489 return false;
490 }
491 }
492
493 if (ArgFlags.isSwiftError()) {
494 if (LocVT == MVT::i64) {
495 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
496 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
497 return false;
498 }
499 }
500 }
501
502 if (ArgFlags.isSwiftSelf()) {
503 if (LocVT == MVT::i64) {
504 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
505 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
506 return false;
507 }
508 }
509 }
510
511 if (ArgFlags.isSwiftAsync()) {
512 if (LocVT == MVT::i64) {
513 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
514 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
515 return false;
516 }
517 }
518 }
519
520 if (ArgFlags.isCFGuardTarget()) {
521 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
522 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
523 return false;
524 }
525 }
526
527 if (LocVT == MVT::v16i8 ||
528 LocVT == MVT::v8i16 ||
529 LocVT == MVT::v4i32 ||
530 LocVT == MVT::v2i64 ||
531 LocVT == MVT::v8f16 ||
532 LocVT == MVT::v4f32 ||
533 LocVT == MVT::v2f64) {
534 LocVT = MVT::i64;
535 LocInfo = CCValAssign::Indirect;
536 }
537
538 if (LocVT == MVT::v32i8 ||
539 LocVT == MVT::v16i16 ||
540 LocVT == MVT::v8i32 ||
541 LocVT == MVT::v4i64 ||
542 LocVT == MVT::v16f16 ||
543 LocVT == MVT::v8f32 ||
544 LocVT == MVT::v4f64) {
545 LocVT = MVT::i64;
546 LocInfo = CCValAssign::Indirect;
547 }
548
549 if (LocVT == MVT::v64i8 ||
550 LocVT == MVT::v32i16 ||
551 LocVT == MVT::v16i32 ||
552 LocVT == MVT::v32f16 ||
553 LocVT == MVT::v16f32 ||
554 LocVT == MVT::v8f64 ||
555 LocVT == MVT::v8i64) {
556 LocVT = MVT::i64;
557 LocInfo = CCValAssign::Indirect;
558 }
559
560 if (LocVT == MVT::f80) {
561 LocVT = MVT::i64;
562 LocInfo = CCValAssign::Indirect;
563 }
564
565 if (LocVT == MVT::x86mmx) {
566 LocVT = MVT::i64;
567 LocInfo = CCValAssign::BCvt;
568 }
569
570 if (LocVT == MVT::f16) {
571 static const MCPhysReg RegList1[] = {
572 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
573 };
574 static const MCPhysReg RegList2[] = {
575 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
576 };
577 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
578 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
579 return false;
580 }
581 }
582
583 if (LocVT == MVT::bf16) {
584 static const MCPhysReg RegList3[] = {
585 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
586 };
587 static const MCPhysReg RegList4[] = {
588 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
589 };
590 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
591 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
592 return false;
593 }
594 }
595
596 if (LocVT == MVT::f32) {
597 static const MCPhysReg RegList5[] = {
598 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3
599 };
600 static const MCPhysReg RegList6[] = {
601 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
602 };
603 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
604 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
605 return false;
606 }
607 }
608
609 if (LocVT == MVT::f64) {
610 static const MCPhysReg RegList7[] = {
611 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3
612 };
613 static const MCPhysReg RegList8[] = {
614 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
615 };
616 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
617 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
618 return false;
619 }
620 }
621
622 if (LocVT == MVT::i32) {
623 static const MCPhysReg RegList9[] = {
624 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
625 };
626 static const MCPhysReg RegList10[] = {
627 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
628 };
629 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
630 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
631 return false;
632 }
633 }
634
635 if (LocVT == MVT::i64) {
636 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
637 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
638 return false;
639 }
640 }
641
642 if (LocVT == MVT::i64) {
643 static const MCPhysReg RegList11[] = {
644 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
645 };
646 static const MCPhysReg RegList12[] = {
647 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
648 };
649 if (MCRegister Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
650 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
651 return false;
652 }
653 }
654
655 if (LocVT == MVT::i8 ||
656 LocVT == MVT::i16 ||
657 LocVT == MVT::i32 ||
658 LocVT == MVT::i64 ||
659 LocVT == MVT::f16 ||
660 LocVT == MVT::bf16 ||
661 LocVT == MVT::f32 ||
662 LocVT == MVT::f64) {
663 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
664 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
665 return false;
666 }
667
668 return true; // CC didn't match.
669}
670
671
672bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
673 MVT LocVT, CCValAssign::LocInfo LocInfo,
674 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
675
676 if (LocVT == MVT::i64) {
677 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
678 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
679 return false;
680 }
681 }
682
683 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
684 return false;
685
686 return true; // CC didn't match.
687}
688
689
690bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
691 MVT LocVT, CCValAssign::LocInfo LocInfo,
692 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
693
694 if (ArgFlags.isCFGuardTarget()) {
695 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
696 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
697 return false;
698 }
699 }
700
701 if (ArgFlags.isNest()) {
702 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
703 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
704 return false;
705 }
706 }
707
708 if (LocVT == MVT::f16 ||
709 LocVT == MVT::bf16) {
710 LocVT = MVT::i16;
711 LocInfo = CCValAssign::BCvt;
712 }
713
714 if (LocVT == MVT::f32) {
715 LocVT = MVT::i32;
716 LocInfo = CCValAssign::BCvt;
717 }
718
719 if (LocVT == MVT::f64 ||
720 LocVT == MVT::v1f64 ||
721 LocVT == MVT::v1i64 ||
722 LocVT == MVT::v2f32 ||
723 LocVT == MVT::v2i32 ||
724 LocVT == MVT::v4i16 ||
725 LocVT == MVT::v4f16 ||
726 LocVT == MVT::v4bf16 ||
727 LocVT == MVT::v8i8 ||
728 LocVT == MVT::iPTR) {
729 LocVT = MVT::i64;
730 LocInfo = CCValAssign::BCvt;
731 }
732
733 if (LocVT == MVT::f128 ||
734 LocVT == MVT::v2f64 ||
735 LocVT == MVT::v2i64 ||
736 LocVT == MVT::v4i32 ||
737 LocVT == MVT::v4f32 ||
738 LocVT == MVT::v8i16 ||
739 LocVT == MVT::v8f16 ||
740 LocVT == MVT::v8bf16 ||
741 LocVT == MVT::v16i8) {
742 LocVT = MVT::i64;
743 LocInfo = CCValAssign::Indirect;
744 }
745
746 if (LocVT == MVT::nxv16i8 ||
747 LocVT == MVT::nxv8i16 ||
748 LocVT == MVT::nxv4i32 ||
749 LocVT == MVT::nxv2i64 ||
750 LocVT == MVT::nxv2f16 ||
751 LocVT == MVT::nxv4f16 ||
752 LocVT == MVT::nxv8f16 ||
753 LocVT == MVT::nxv2bf16 ||
754 LocVT == MVT::nxv4bf16 ||
755 LocVT == MVT::nxv8bf16 ||
756 LocVT == MVT::nxv2f32 ||
757 LocVT == MVT::nxv4f32 ||
758 LocVT == MVT::nxv2f64) {
759 LocVT = MVT::i64;
760 LocInfo = CCValAssign::Indirect;
761 }
762
763 if (LocVT == MVT::nxv2i1 ||
764 LocVT == MVT::nxv4i1 ||
765 LocVT == MVT::nxv8i1 ||
766 LocVT == MVT::nxv16i1) {
767 LocVT = MVT::i64;
768 LocInfo = CCValAssign::Indirect;
769 }
770
771 if (ArgFlags.isInReg()) {
772 if (LocVT == MVT::i64) {
773 if (ArgFlags.isSRet()) {
774 if (LocVT == MVT::i64) {
775 static const MCPhysReg RegList1[] = {
776 AArch64::X0, AArch64::X1
777 };
778 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
779 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
780 return false;
781 }
782 }
783 }
784 }
785 }
786
787 if (ArgFlags.isSRet()) {
788 if (LocVT == MVT::i64) {
789 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
790 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
791 return false;
792 }
793 }
794 }
795
796 if (ArgFlags.isByVal()) {
797 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
798 return false;
799 }
800
801 if (LocVT == MVT::i1 ||
802 LocVT == MVT::i8 ||
803 LocVT == MVT::i16) {
804 LocVT = MVT::i32;
805 if (ArgFlags.isSExt())
806 LocInfo = CCValAssign::SExt;
807 else if (ArgFlags.isZExt())
808 LocInfo = CCValAssign::ZExt;
809 else
810 LocInfo = CCValAssign::AExt;
811 }
812
813 if (LocVT == MVT::i32) {
814 static const MCPhysReg RegList2[] = {
815 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
816 };
817 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
818 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
819 return false;
820 }
821 }
822
823 if (LocVT == MVT::i64) {
824 static const MCPhysReg RegList3[] = {
825 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
826 };
827 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
828 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
829 return false;
830 }
831 }
832
833 if (LocVT == MVT::i32 ||
834 LocVT == MVT::i64) {
835 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
836 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
837 return false;
838 }
839
840 return true; // CC didn't match.
841}
842
843
844bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
845 MVT LocVT, CCValAssign::LocInfo LocInfo,
846 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
847
848 if (ArgFlags.isNest()) {
849 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
850 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
851 return false;
852 }
853 }
854
855 if (LocVT == MVT::iPTR) {
856 LocVT = MVT::i64;
857 LocInfo = CCValAssign::BCvt;
858 }
859
860 if (LocVT == MVT::v2f32) {
861 LocVT = MVT::v2i32;
862 LocInfo = CCValAssign::BCvt;
863 }
864
865 if (LocVT == MVT::v2f64 ||
866 LocVT == MVT::v4f32 ||
867 LocVT == MVT::f128) {
868 LocVT = MVT::v2i64;
869 LocInfo = CCValAssign::BCvt;
870 }
871
872 if (ArgFlags.isSRet()) {
873 if (LocVT == MVT::i64) {
874 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
875 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
876 return false;
877 }
878 }
879 }
880
881 if (ArgFlags.isByVal()) {
882 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
883 return false;
884 }
885
886 if (ArgFlags.isSwiftSelf()) {
887 if (LocVT == MVT::i64) {
888 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
889 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
890 return false;
891 }
892 }
893 }
894
895 if (ArgFlags.isSwiftError()) {
896 if (LocVT == MVT::i64) {
897 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
898 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
899 return false;
900 }
901 }
902 }
903
904 if (ArgFlags.isSwiftAsync()) {
905 if (LocVT == MVT::i64) {
906 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
907 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
908 return false;
909 }
910 }
911 }
912
913 if (ArgFlags.isInConsecutiveRegs()) {
914 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
915 return false;
916 }
917
918 if (LocVT == MVT::nxv16i8 ||
919 LocVT == MVT::nxv8i16 ||
920 LocVT == MVT::nxv4i32 ||
921 LocVT == MVT::nxv2i64 ||
922 LocVT == MVT::nxv2f16 ||
923 LocVT == MVT::nxv4f16 ||
924 LocVT == MVT::nxv8f16 ||
925 LocVT == MVT::nxv2bf16 ||
926 LocVT == MVT::nxv4bf16 ||
927 LocVT == MVT::nxv8bf16 ||
928 LocVT == MVT::nxv2f32 ||
929 LocVT == MVT::nxv4f32 ||
930 LocVT == MVT::nxv2f64) {
931 static const MCPhysReg RegList1[] = {
932 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
933 };
934 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
935 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
936 return false;
937 }
938 }
939
940 if (LocVT == MVT::nxv16i8 ||
941 LocVT == MVT::nxv8i16 ||
942 LocVT == MVT::nxv4i32 ||
943 LocVT == MVT::nxv2i64 ||
944 LocVT == MVT::nxv2f16 ||
945 LocVT == MVT::nxv4f16 ||
946 LocVT == MVT::nxv8f16 ||
947 LocVT == MVT::nxv2bf16 ||
948 LocVT == MVT::nxv4bf16 ||
949 LocVT == MVT::nxv8bf16 ||
950 LocVT == MVT::nxv2f32 ||
951 LocVT == MVT::nxv4f32 ||
952 LocVT == MVT::nxv2f64) {
953 LocVT = MVT::i64;
954 LocInfo = CCValAssign::Indirect;
955 }
956
957 if (LocVT == MVT::nxv1i1 ||
958 LocVT == MVT::nxv2i1 ||
959 LocVT == MVT::nxv4i1 ||
960 LocVT == MVT::nxv8i1 ||
961 LocVT == MVT::nxv16i1 ||
962 LocVT == MVT::aarch64svcount) {
963 static const MCPhysReg RegList2[] = {
964 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
965 };
966 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
967 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
968 return false;
969 }
970 }
971
972 if (LocVT == MVT::nxv1i1 ||
973 LocVT == MVT::nxv2i1 ||
974 LocVT == MVT::nxv4i1 ||
975 LocVT == MVT::nxv8i1 ||
976 LocVT == MVT::nxv16i1 ||
977 LocVT == MVT::aarch64svcount) {
978 LocVT = MVT::i64;
979 LocInfo = CCValAssign::Indirect;
980 }
981
982 if (LocVT == MVT::i1 ||
983 LocVT == MVT::i8 ||
984 LocVT == MVT::i16) {
985 LocVT = MVT::i32;
986 if (ArgFlags.isSExt())
987 LocInfo = CCValAssign::SExt;
988 else if (ArgFlags.isZExt())
989 LocInfo = CCValAssign::ZExt;
990 else
991 LocInfo = CCValAssign::AExt;
992 }
993
994 if (LocVT == MVT::i32) {
995 static const MCPhysReg RegList3[] = {
996 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
997 };
998 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
999 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1000 return false;
1001 }
1002 }
1003
1004 if (LocVT == MVT::i64) {
1005 if (ArgFlags.isSplit()) {
1006 static const MCPhysReg RegList4[] = {
1007 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
1008 };
1009 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1010 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1011 return false;
1012 }
1013 }
1014 }
1015
1016 if (LocVT == MVT::i64) {
1017 if (ArgFlags.isSplit()) {
1018 static const MCPhysReg ShadowRegList5[] = {
1019 AArch64::X7
1020 };
1021 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList5);
1022 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1023 return false;
1024 }
1025 }
1026
1027 if (LocVT == MVT::i64) {
1028 static const MCPhysReg RegList7[] = {
1029 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1030 };
1031 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
1032 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1033 return false;
1034 }
1035 }
1036
1037 if (LocVT == MVT::f16) {
1038 static const MCPhysReg RegList8[] = {
1039 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1040 };
1041 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
1042 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1043 return false;
1044 }
1045 }
1046
1047 if (LocVT == MVT::bf16) {
1048 static const MCPhysReg RegList9[] = {
1049 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1050 };
1051 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1052 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1053 return false;
1054 }
1055 }
1056
1057 if (LocVT == MVT::f32) {
1058 static const MCPhysReg RegList10[] = {
1059 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1060 };
1061 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1062 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1063 return false;
1064 }
1065 }
1066
1067 if (LocVT == MVT::f64) {
1068 static const MCPhysReg RegList11[] = {
1069 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1070 };
1071 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1072 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1073 return false;
1074 }
1075 }
1076
1077 if (LocVT == MVT::v1i64 ||
1078 LocVT == MVT::v2i32 ||
1079 LocVT == MVT::v4i16 ||
1080 LocVT == MVT::v8i8 ||
1081 LocVT == MVT::v1f64 ||
1082 LocVT == MVT::v2f32 ||
1083 LocVT == MVT::v4f16 ||
1084 LocVT == MVT::v4bf16) {
1085 static const MCPhysReg RegList12[] = {
1086 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1087 };
1088 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1089 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1090 return false;
1091 }
1092 }
1093
1094 if (LocVT == MVT::v2i64 ||
1095 LocVT == MVT::v4i32 ||
1096 LocVT == MVT::v8i16 ||
1097 LocVT == MVT::v16i8 ||
1098 LocVT == MVT::v4f32 ||
1099 LocVT == MVT::v2f64 ||
1100 LocVT == MVT::v8f16 ||
1101 LocVT == MVT::v8bf16) {
1102 static const MCPhysReg RegList13[] = {
1103 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1104 };
1105 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1106 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1107 return false;
1108 }
1109 }
1110
1111 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
1112 int64_t Offset14 = State.AllocateStack(Size: 1, Alignment: Align(1));
1113 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1114 return false;
1115 }
1116
1117 if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) {
1118 int64_t Offset15 = State.AllocateStack(Size: 2, Alignment: Align(2));
1119 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
1120 return false;
1121 }
1122
1123 if (LocVT == MVT::i32 ||
1124 LocVT == MVT::f32) {
1125 int64_t Offset16 = State.AllocateStack(Size: 4, Alignment: Align(4));
1126 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1127 return false;
1128 }
1129
1130 if (ArgFlags.isPointer()) {
1131 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1132 LocVT = MVT::i32;
1133 LocInfo = CCValAssign::Trunc;
1134 }
1135 }
1136
1137 if (ArgFlags.isPointer()) {
1138 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1139 int64_t Offset17 = State.AllocateStack(Size: 4, Alignment: Align(4));
1140 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1141 return false;
1142 }
1143 }
1144
1145 if (LocVT == MVT::i64 ||
1146 LocVT == MVT::f64 ||
1147 LocVT == MVT::v1f64 ||
1148 LocVT == MVT::v2f32 ||
1149 LocVT == MVT::v1i64 ||
1150 LocVT == MVT::v2i32 ||
1151 LocVT == MVT::v4i16 ||
1152 LocVT == MVT::v8i8 ||
1153 LocVT == MVT::v4f16 ||
1154 LocVT == MVT::v4bf16) {
1155 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1156 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1157 return false;
1158 }
1159
1160 if (LocVT == MVT::v2i64 ||
1161 LocVT == MVT::v4i32 ||
1162 LocVT == MVT::v8i16 ||
1163 LocVT == MVT::v16i8 ||
1164 LocVT == MVT::v4f32 ||
1165 LocVT == MVT::v2f64 ||
1166 LocVT == MVT::v8f16 ||
1167 LocVT == MVT::v8bf16) {
1168 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1169 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1170 return false;
1171 }
1172
1173 return true; // CC didn't match.
1174}
1175
1176
1177bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
1178 MVT LocVT, CCValAssign::LocInfo LocInfo,
1179 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1180
1181 if (ArgFlags.isNest()) {
1182 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1184 return false;
1185 }
1186 }
1187
1188 if (LocVT == MVT::v2f32) {
1189 LocVT = MVT::v2i32;
1190 LocInfo = CCValAssign::BCvt;
1191 }
1192
1193 if (LocVT == MVT::v2f64 ||
1194 LocVT == MVT::v4f32 ||
1195 LocVT == MVT::f128) {
1196 LocVT = MVT::v2i64;
1197 LocInfo = CCValAssign::BCvt;
1198 }
1199
1200 if (LocVT == MVT::i8 ||
1201 LocVT == MVT::i16) {
1202 LocVT = MVT::i32;
1203 if (ArgFlags.isSExt())
1204 LocInfo = CCValAssign::SExt;
1205 else if (ArgFlags.isZExt())
1206 LocInfo = CCValAssign::ZExt;
1207 else
1208 LocInfo = CCValAssign::AExt;
1209 }
1210
1211 if (LocVT == MVT::f16 ||
1212 LocVT == MVT::bf16) {
1213 LocVT = MVT::f32;
1214 LocInfo = CCValAssign::FPExt;
1215 }
1216
1217 if (ArgFlags.isPointer()) {
1218 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1219 LocVT = MVT::i32;
1220 LocInfo = CCValAssign::Trunc;
1221 }
1222 }
1223
1224 if (LocVT == MVT::i32 ||
1225 LocVT == MVT::f32) {
1226 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1227 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1228 return false;
1229 }
1230
1231 if (LocVT == MVT::i64) {
1232 if (ArgFlags.isSplit()) {
1233 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(16));
1234 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1235 return false;
1236 }
1237 }
1238
1239 if (LocVT == MVT::i64 ||
1240 LocVT == MVT::f64 ||
1241 LocVT == MVT::v1i64 ||
1242 LocVT == MVT::v2i32 ||
1243 LocVT == MVT::v4i16 ||
1244 LocVT == MVT::v8i8 ||
1245 LocVT == MVT::v1f64 ||
1246 LocVT == MVT::v2f32 ||
1247 LocVT == MVT::v4f16 ||
1248 LocVT == MVT::v4bf16) {
1249 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
1250 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1251 return false;
1252 }
1253
1254 if (LocVT == MVT::v2i64 ||
1255 LocVT == MVT::v4i32 ||
1256 LocVT == MVT::v8i16 ||
1257 LocVT == MVT::v16i8 ||
1258 LocVT == MVT::v4f32 ||
1259 LocVT == MVT::v2f64 ||
1260 LocVT == MVT::v8f16 ||
1261 LocVT == MVT::v8bf16) {
1262 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(16));
1263 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
1264 return false;
1265 }
1266
1267 return true; // CC didn't match.
1268}
1269
1270
1271bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
1272 MVT LocVT, CCValAssign::LocInfo LocInfo,
1273 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1274
1275 if (ArgFlags.isNest()) {
1276 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1277 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1278 return false;
1279 }
1280 }
1281
1282 if (LocVT == MVT::iPTR) {
1283 LocVT = MVT::i64;
1284 LocInfo = CCValAssign::BCvt;
1285 }
1286
1287 if (LocVT == MVT::v2f32) {
1288 LocVT = MVT::v2i32;
1289 LocInfo = CCValAssign::BCvt;
1290 }
1291
1292 if (LocVT == MVT::v2f64 ||
1293 LocVT == MVT::v4f32 ||
1294 LocVT == MVT::f128) {
1295 LocVT = MVT::v2i64;
1296 LocInfo = CCValAssign::BCvt;
1297 }
1298
1299 if (ArgFlags.isInConsecutiveRegs()) {
1300 if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1301 return false;
1302 }
1303
1304 if (LocVT == MVT::i8 ||
1305 LocVT == MVT::i16 ||
1306 LocVT == MVT::i32) {
1307 LocVT = MVT::i64;
1308 if (ArgFlags.isSExt())
1309 LocInfo = CCValAssign::SExt;
1310 else if (ArgFlags.isZExt())
1311 LocInfo = CCValAssign::ZExt;
1312 else
1313 LocInfo = CCValAssign::AExt;
1314 }
1315
1316 if (LocVT == MVT::f16 ||
1317 LocVT == MVT::bf16 ||
1318 LocVT == MVT::f32) {
1319 LocVT = MVT::f64;
1320 LocInfo = CCValAssign::FPExt;
1321 }
1322
1323 if (LocVT == MVT::i64) {
1324 if (ArgFlags.isSplit()) {
1325 int64_t Offset1 = State.AllocateStack(Size: 8, Alignment: Align(16));
1326 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1327 return false;
1328 }
1329 }
1330
1331 if (LocVT == MVT::i64 ||
1332 LocVT == MVT::f64 ||
1333 LocVT == MVT::v1i64 ||
1334 LocVT == MVT::v2i32 ||
1335 LocVT == MVT::v4i16 ||
1336 LocVT == MVT::v8i8 ||
1337 LocVT == MVT::v1f64 ||
1338 LocVT == MVT::v2f32 ||
1339 LocVT == MVT::v4f16 ||
1340 LocVT == MVT::v4bf16) {
1341 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
1342 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1343 return false;
1344 }
1345
1346 if (LocVT == MVT::v2i64 ||
1347 LocVT == MVT::v4i32 ||
1348 LocVT == MVT::v8i16 ||
1349 LocVT == MVT::v16i8 ||
1350 LocVT == MVT::v4f32 ||
1351 LocVT == MVT::v2f64 ||
1352 LocVT == MVT::v8f16 ||
1353 LocVT == MVT::v8bf16) {
1354 int64_t Offset3 = State.AllocateStack(Size: 16, Alignment: Align(16));
1355 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1356 return false;
1357 }
1358
1359 return true; // CC didn't match.
1360}
1361
1362
1363bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
1364 MVT LocVT, CCValAssign::LocInfo LocInfo,
1365 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1366
1367 if (ArgFlags.isNest()) {
1368 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1369 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1370 return false;
1371 }
1372 }
1373
1374 if (LocVT == MVT::iPTR) {
1375 LocVT = MVT::i64;
1376 LocInfo = CCValAssign::BCvt;
1377 }
1378
1379 if (LocVT == MVT::v1i64 ||
1380 LocVT == MVT::v2i32 ||
1381 LocVT == MVT::v4i16 ||
1382 LocVT == MVT::v8i8 ||
1383 LocVT == MVT::v2f32) {
1384 LocVT = MVT::f64;
1385 LocInfo = CCValAssign::BCvt;
1386 }
1387
1388 if (LocVT == MVT::v2i64 ||
1389 LocVT == MVT::v4i32 ||
1390 LocVT == MVT::v8i16 ||
1391 LocVT == MVT::v16i8 ||
1392 LocVT == MVT::v4f32 ||
1393 LocVT == MVT::f128) {
1394 LocVT = MVT::v2f64;
1395 LocInfo = CCValAssign::BCvt;
1396 }
1397
1398 if (LocVT == MVT::v2f64) {
1399 static const MCPhysReg RegList1[] = {
1400 AArch64::Q4, AArch64::Q5
1401 };
1402 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1403 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1404 return false;
1405 }
1406 }
1407
1408 if (LocVT == MVT::f32) {
1409 static const MCPhysReg RegList2[] = {
1410 AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
1411 };
1412 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1413 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1414 return false;
1415 }
1416 }
1417
1418 if (LocVT == MVT::f64) {
1419 static const MCPhysReg RegList3[] = {
1420 AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
1421 };
1422 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1423 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1424 return false;
1425 }
1426 }
1427
1428 if (LocVT == MVT::i8 ||
1429 LocVT == MVT::i16 ||
1430 LocVT == MVT::i32) {
1431 LocVT = MVT::i64;
1432 if (ArgFlags.isSExt())
1433 LocInfo = CCValAssign::SExt;
1434 else if (ArgFlags.isZExt())
1435 LocInfo = CCValAssign::ZExt;
1436 else
1437 LocInfo = CCValAssign::AExt;
1438 }
1439
1440 if (LocVT == MVT::i64) {
1441 static const MCPhysReg RegList4[] = {
1442 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
1443 };
1444 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1445 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1446 return false;
1447 }
1448 }
1449
1450 return true; // CC didn't match.
1451}
1452
1453
1454bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
1455 MVT LocVT, CCValAssign::LocInfo LocInfo,
1456 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1457
1458 if (State.isVarArg()) {
1459 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
1460 if (!CC_AArch64_DarwinPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1461 return false;
1462 }
1463 }
1464
1465 if (State.isVarArg()) {
1466 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1467 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1468 return false;
1469 }
1470 }
1471
1472 if (State.isVarArg()) {
1473 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1474 return false;
1475 }
1476
1477 if (LocVT == MVT::i32) {
1478 static const MCPhysReg RegList1[] = {
1479 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W9
1480 };
1481 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1482 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1483 return false;
1484 }
1485 }
1486
1487 if (LocVT == MVT::i64) {
1488 static const MCPhysReg RegList2[] = {
1489 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X9
1490 };
1491 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1492 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1493 return false;
1494 }
1495 }
1496
1497 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1498 if (LocVT == MVT::i32) {
1499 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::W15)) {
1500 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1501 return false;
1502 }
1503 }
1504 }
1505
1506 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1507 if (LocVT == MVT::i64) {
1508 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1509 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1510 return false;
1511 }
1512 }
1513 }
1514
1515 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1516 return false;
1517
1518 return true; // CC didn't match.
1519}
1520
1521
1522bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
1523 MVT LocVT, CCValAssign::LocInfo LocInfo,
1524 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1525
1526 if (ArgFlags.isCFGuardTarget()) {
1527 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
1528 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1529 return false;
1530 }
1531 }
1532
1533 if (ArgFlags.isNest()) {
1534 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1535 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1536 return false;
1537 }
1538 }
1539
1540 if (LocVT == MVT::iPTR) {
1541 LocVT = MVT::i64;
1542 LocInfo = CCValAssign::BCvt;
1543 }
1544
1545 if (LocVT == MVT::v2f32) {
1546 LocVT = MVT::v2i32;
1547 LocInfo = CCValAssign::BCvt;
1548 }
1549
1550 if (LocVT == MVT::v2f64 ||
1551 LocVT == MVT::v4f32) {
1552 LocVT = MVT::v2i64;
1553 LocInfo = CCValAssign::BCvt;
1554 }
1555
1556 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1557 if (LocVT == MVT::v2i32 ||
1558 LocVT == MVT::v2f32 ||
1559 LocVT == MVT::v4i16 ||
1560 LocVT == MVT::v4f16 ||
1561 LocVT == MVT::v4bf16 ||
1562 LocVT == MVT::v8i8) {
1563 LocVT = MVT::f64;
1564 LocInfo = CCValAssign::BCvt;
1565 }
1566 }
1567
1568 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1569 if (LocVT == MVT::v2i64 ||
1570 LocVT == MVT::v2f64 ||
1571 LocVT == MVT::v4i32 ||
1572 LocVT == MVT::v4f32 ||
1573 LocVT == MVT::v8i16 ||
1574 LocVT == MVT::v8f16 ||
1575 LocVT == MVT::v8bf16 ||
1576 LocVT == MVT::v16i8) {
1577 LocVT = MVT::f128;
1578 LocInfo = CCValAssign::BCvt;
1579 }
1580 }
1581
1582 if (ArgFlags.isInReg()) {
1583 if (LocVT == MVT::i64) {
1584 if (ArgFlags.isSRet()) {
1585 if (LocVT == MVT::i64) {
1586 static const MCPhysReg RegList1[] = {
1587 AArch64::X0, AArch64::X1
1588 };
1589 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1590 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1591 return false;
1592 }
1593 }
1594 }
1595 }
1596 }
1597
1598 if (ArgFlags.isSRet()) {
1599 if (LocVT == MVT::i64) {
1600 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
1601 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1602 return false;
1603 }
1604 }
1605 }
1606
1607 if (ArgFlags.isByVal()) {
1608 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1609 return false;
1610 }
1611
1612 if (ArgFlags.isSwiftSelf()) {
1613 if (LocVT == MVT::i64) {
1614 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
1615 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1616 return false;
1617 }
1618 }
1619 }
1620
1621 if (ArgFlags.isSwiftError()) {
1622 if (LocVT == MVT::i64) {
1623 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1624 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1625 return false;
1626 }
1627 }
1628 }
1629
1630 if (ArgFlags.isSwiftAsync()) {
1631 if (LocVT == MVT::i64) {
1632 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
1633 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1634 return false;
1635 }
1636 }
1637 }
1638
1639 if (ArgFlags.isInConsecutiveRegs()) {
1640 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1641 return false;
1642 }
1643
1644 if (LocVT == MVT::nxv16i8 ||
1645 LocVT == MVT::nxv8i16 ||
1646 LocVT == MVT::nxv4i32 ||
1647 LocVT == MVT::nxv2i64 ||
1648 LocVT == MVT::nxv2f16 ||
1649 LocVT == MVT::nxv4f16 ||
1650 LocVT == MVT::nxv8f16 ||
1651 LocVT == MVT::nxv2bf16 ||
1652 LocVT == MVT::nxv4bf16 ||
1653 LocVT == MVT::nxv8bf16 ||
1654 LocVT == MVT::nxv2f32 ||
1655 LocVT == MVT::nxv4f32 ||
1656 LocVT == MVT::nxv2f64) {
1657 static const MCPhysReg RegList2[] = {
1658 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1659 };
1660 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1661 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1662 return false;
1663 }
1664 }
1665
1666 if (LocVT == MVT::nxv16i8 ||
1667 LocVT == MVT::nxv8i16 ||
1668 LocVT == MVT::nxv4i32 ||
1669 LocVT == MVT::nxv2i64 ||
1670 LocVT == MVT::nxv2f16 ||
1671 LocVT == MVT::nxv4f16 ||
1672 LocVT == MVT::nxv8f16 ||
1673 LocVT == MVT::nxv2bf16 ||
1674 LocVT == MVT::nxv4bf16 ||
1675 LocVT == MVT::nxv8bf16 ||
1676 LocVT == MVT::nxv2f32 ||
1677 LocVT == MVT::nxv4f32 ||
1678 LocVT == MVT::nxv2f64) {
1679 LocVT = MVT::i64;
1680 LocInfo = CCValAssign::Indirect;
1681 }
1682
1683 if (LocVT == MVT::nxv1i1 ||
1684 LocVT == MVT::nxv2i1 ||
1685 LocVT == MVT::nxv4i1 ||
1686 LocVT == MVT::nxv8i1 ||
1687 LocVT == MVT::nxv16i1 ||
1688 LocVT == MVT::aarch64svcount) {
1689 static const MCPhysReg RegList3[] = {
1690 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
1691 };
1692 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1693 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1694 return false;
1695 }
1696 }
1697
1698 if (LocVT == MVT::nxv1i1 ||
1699 LocVT == MVT::nxv2i1 ||
1700 LocVT == MVT::nxv4i1 ||
1701 LocVT == MVT::nxv8i1 ||
1702 LocVT == MVT::nxv16i1 ||
1703 LocVT == MVT::aarch64svcount) {
1704 LocVT = MVT::i64;
1705 LocInfo = CCValAssign::Indirect;
1706 }
1707
1708 if (LocVT == MVT::i1 ||
1709 LocVT == MVT::i8 ||
1710 LocVT == MVT::i16) {
1711 LocVT = MVT::i32;
1712 if (ArgFlags.isSExt())
1713 LocInfo = CCValAssign::SExt;
1714 else if (ArgFlags.isZExt())
1715 LocInfo = CCValAssign::ZExt;
1716 else
1717 LocInfo = CCValAssign::AExt;
1718 }
1719
1720 if (LocVT == MVT::i32) {
1721 static const MCPhysReg RegList4[] = {
1722 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1723 };
1724 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1725 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1726 return false;
1727 }
1728 }
1729
1730 if (LocVT == MVT::i64) {
1731 if (ArgFlags.isSplit()) {
1732 static const MCPhysReg RegList5[] = {
1733 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
1734 };
1735 static const MCPhysReg RegList6[] = {
1736 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
1737 };
1738 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
1739 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1740 return false;
1741 }
1742 }
1743 }
1744
1745 if (LocVT == MVT::i64) {
1746 if (ArgFlags.isSplit()) {
1747 static const MCPhysReg ShadowRegList7[] = {
1748 AArch64::X7
1749 };
1750 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
1751 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1752 return false;
1753 }
1754 }
1755
1756 if (LocVT == MVT::i64) {
1757 static const MCPhysReg RegList9[] = {
1758 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1759 };
1760 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1761 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1762 return false;
1763 }
1764 }
1765
1766 if (LocVT == MVT::f16) {
1767 static const MCPhysReg RegList10[] = {
1768 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1769 };
1770 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1771 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1772 return false;
1773 }
1774 }
1775
1776 if (LocVT == MVT::bf16) {
1777 static const MCPhysReg RegList11[] = {
1778 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1779 };
1780 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1781 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1782 return false;
1783 }
1784 }
1785
1786 if (LocVT == MVT::f32) {
1787 static const MCPhysReg RegList12[] = {
1788 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1789 };
1790 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1791 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1792 return false;
1793 }
1794 }
1795
1796 if (LocVT == MVT::f64) {
1797 static const MCPhysReg RegList13[] = {
1798 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1799 };
1800 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1801 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1802 return false;
1803 }
1804 }
1805
1806 if (LocVT == MVT::v1i64 ||
1807 LocVT == MVT::v2i32 ||
1808 LocVT == MVT::v4i16 ||
1809 LocVT == MVT::v8i8 ||
1810 LocVT == MVT::v1f64 ||
1811 LocVT == MVT::v2f32 ||
1812 LocVT == MVT::v4f16 ||
1813 LocVT == MVT::v4bf16) {
1814 static const MCPhysReg RegList14[] = {
1815 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1816 };
1817 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
1818 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1819 return false;
1820 }
1821 }
1822
1823 if (LocVT == MVT::f128 ||
1824 LocVT == MVT::v2i64 ||
1825 LocVT == MVT::v4i32 ||
1826 LocVT == MVT::v8i16 ||
1827 LocVT == MVT::v16i8 ||
1828 LocVT == MVT::v4f32 ||
1829 LocVT == MVT::v2f64 ||
1830 LocVT == MVT::v8f16 ||
1831 LocVT == MVT::v8bf16) {
1832 static const MCPhysReg RegList15[] = {
1833 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1834 };
1835 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
1836 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1837 return false;
1838 }
1839 }
1840
1841 if (LocVT == MVT::i1 ||
1842 LocVT == MVT::i8 ||
1843 LocVT == MVT::i16 ||
1844 LocVT == MVT::f16 ||
1845 LocVT == MVT::bf16) {
1846 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
1847 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1848 return false;
1849 }
1850
1851 if (LocVT == MVT::i32 ||
1852 LocVT == MVT::f32) {
1853 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
1854 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1855 return false;
1856 }
1857
1858 if (LocVT == MVT::i64 ||
1859 LocVT == MVT::f64 ||
1860 LocVT == MVT::v1f64 ||
1861 LocVT == MVT::v2f32 ||
1862 LocVT == MVT::v1i64 ||
1863 LocVT == MVT::v2i32 ||
1864 LocVT == MVT::v4i16 ||
1865 LocVT == MVT::v8i8 ||
1866 LocVT == MVT::v4f16 ||
1867 LocVT == MVT::v4bf16) {
1868 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1869 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1870 return false;
1871 }
1872
1873 if (LocVT == MVT::f128 ||
1874 LocVT == MVT::v2i64 ||
1875 LocVT == MVT::v4i32 ||
1876 LocVT == MVT::v8i16 ||
1877 LocVT == MVT::v16i8 ||
1878 LocVT == MVT::v4f32 ||
1879 LocVT == MVT::v2f64 ||
1880 LocVT == MVT::v8f16 ||
1881 LocVT == MVT::v8bf16) {
1882 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1883 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1884 return false;
1885 }
1886
1887 return true; // CC didn't match.
1888}
1889
1890
1891bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
1892 MVT LocVT, CCValAssign::LocInfo LocInfo,
1893 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1894
1895 if (LocVT == MVT::i64) {
1896 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1897 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1898 return false;
1899 }
1900 }
1901
1902 return true; // CC didn't match.
1903}
1904
1905
1906bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
1907 MVT LocVT, CCValAssign::LocInfo LocInfo,
1908 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1909
1910 if (LocVT == MVT::f16 ||
1911 LocVT == MVT::bf16) {
1912 LocVT = MVT::i16;
1913 LocInfo = CCValAssign::BCvt;
1914 }
1915
1916 if (LocVT == MVT::f32) {
1917 LocVT = MVT::i32;
1918 LocInfo = CCValAssign::BCvt;
1919 }
1920
1921 if (LocVT == MVT::f64) {
1922 LocVT = MVT::i64;
1923 LocInfo = CCValAssign::BCvt;
1924 }
1925
1926 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
1927 return false;
1928
1929 return true; // CC didn't match.
1930}
1931
1932
1933bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
1934 MVT LocVT, CCValAssign::LocInfo LocInfo,
1935 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
1936
1937 if (LocVT == MVT::iPTR) {
1938 LocVT = MVT::i64;
1939 LocInfo = CCValAssign::BCvt;
1940 }
1941
1942 if (LocVT == MVT::v2f32) {
1943 LocVT = MVT::v2i32;
1944 LocInfo = CCValAssign::BCvt;
1945 }
1946
1947 if (LocVT == MVT::v2f64 ||
1948 LocVT == MVT::v4f32) {
1949 LocVT = MVT::v2i64;
1950 LocInfo = CCValAssign::BCvt;
1951 }
1952
1953 if (ArgFlags.isInConsecutiveRegs()) {
1954 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1955 return false;
1956 }
1957
1958 if (ArgFlags.isSwiftError()) {
1959 if (LocVT == MVT::i64) {
1960 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1961 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1962 return false;
1963 }
1964 }
1965 }
1966
1967 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1968 if (LocVT == MVT::v2i32 ||
1969 LocVT == MVT::v2f32 ||
1970 LocVT == MVT::v4i16 ||
1971 LocVT == MVT::v4f16 ||
1972 LocVT == MVT::v4bf16 ||
1973 LocVT == MVT::v8i8) {
1974 LocVT = MVT::f64;
1975 LocInfo = CCValAssign::BCvt;
1976 }
1977 }
1978
1979 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1980 if (LocVT == MVT::v2i64 ||
1981 LocVT == MVT::v2f64 ||
1982 LocVT == MVT::v4i32 ||
1983 LocVT == MVT::v4f32 ||
1984 LocVT == MVT::v8i16 ||
1985 LocVT == MVT::v8f16 ||
1986 LocVT == MVT::v8bf16 ||
1987 LocVT == MVT::v16i8) {
1988 LocVT = MVT::f128;
1989 LocInfo = CCValAssign::BCvt;
1990 }
1991 }
1992
1993 if (LocVT == MVT::i1 ||
1994 LocVT == MVT::i8 ||
1995 LocVT == MVT::i16) {
1996 LocVT = MVT::i32;
1997 if (ArgFlags.isSExt())
1998 LocInfo = CCValAssign::SExt;
1999 else if (ArgFlags.isZExt())
2000 LocInfo = CCValAssign::ZExt;
2001 else
2002 LocInfo = CCValAssign::AExt;
2003 }
2004
2005 if (LocVT == MVT::i32) {
2006 static const MCPhysReg RegList1[] = {
2007 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
2008 };
2009 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2010 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2011 return false;
2012 }
2013 }
2014
2015 if (LocVT == MVT::i64) {
2016 static const MCPhysReg RegList2[] = {
2017 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
2018 };
2019 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2020 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2021 return false;
2022 }
2023 }
2024
2025 if (LocVT == MVT::f16) {
2026 static const MCPhysReg RegList3[] = {
2027 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
2028 };
2029 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2030 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2031 return false;
2032 }
2033 }
2034
2035 if (LocVT == MVT::bf16) {
2036 static const MCPhysReg RegList4[] = {
2037 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
2038 };
2039 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2040 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2041 return false;
2042 }
2043 }
2044
2045 if (LocVT == MVT::f32) {
2046 static const MCPhysReg RegList5[] = {
2047 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
2048 };
2049 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2050 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2051 return false;
2052 }
2053 }
2054
2055 if (LocVT == MVT::f64) {
2056 static const MCPhysReg RegList6[] = {
2057 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2058 };
2059 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2060 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2061 return false;
2062 }
2063 }
2064
2065 if (LocVT == MVT::v1i64 ||
2066 LocVT == MVT::v2i32 ||
2067 LocVT == MVT::v4i16 ||
2068 LocVT == MVT::v8i8 ||
2069 LocVT == MVT::v1f64 ||
2070 LocVT == MVT::v2f32 ||
2071 LocVT == MVT::v4f16 ||
2072 LocVT == MVT::v4bf16) {
2073 static const MCPhysReg RegList7[] = {
2074 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2075 };
2076 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2077 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2078 return false;
2079 }
2080 }
2081
2082 if (LocVT == MVT::f128 ||
2083 LocVT == MVT::v2i64 ||
2084 LocVT == MVT::v4i32 ||
2085 LocVT == MVT::v8i16 ||
2086 LocVT == MVT::v16i8 ||
2087 LocVT == MVT::v4f32 ||
2088 LocVT == MVT::v2f64 ||
2089 LocVT == MVT::v8f16 ||
2090 LocVT == MVT::v8bf16) {
2091 static const MCPhysReg RegList8[] = {
2092 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
2093 };
2094 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
2095 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2096 return false;
2097 }
2098 }
2099
2100 if (LocVT == MVT::nxv16i8 ||
2101 LocVT == MVT::nxv8i16 ||
2102 LocVT == MVT::nxv4i32 ||
2103 LocVT == MVT::nxv2i64 ||
2104 LocVT == MVT::nxv2f16 ||
2105 LocVT == MVT::nxv4f16 ||
2106 LocVT == MVT::nxv8f16 ||
2107 LocVT == MVT::nxv2bf16 ||
2108 LocVT == MVT::nxv4bf16 ||
2109 LocVT == MVT::nxv8bf16 ||
2110 LocVT == MVT::nxv2f32 ||
2111 LocVT == MVT::nxv4f32 ||
2112 LocVT == MVT::nxv2f64) {
2113 static const MCPhysReg RegList9[] = {
2114 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
2115 };
2116 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
2117 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2118 return false;
2119 }
2120 }
2121
2122 if (LocVT == MVT::nxv1i1 ||
2123 LocVT == MVT::nxv2i1 ||
2124 LocVT == MVT::nxv4i1 ||
2125 LocVT == MVT::nxv8i1 ||
2126 LocVT == MVT::nxv16i1 ||
2127 LocVT == MVT::aarch64svcount) {
2128 static const MCPhysReg RegList10[] = {
2129 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
2130 };
2131 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
2132 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2133 return false;
2134 }
2135 }
2136
2137 return true; // CC didn't match.
2138}
2139
2140
2141bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
2142 MVT LocVT, CCValAssign::LocInfo LocInfo,
2143 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2144
2145 if (LocVT == MVT::i64) {
2146 static const MCPhysReg RegList1[] = {
2147 AArch64::X11, AArch64::X9
2148 };
2149 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2150 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2151 return false;
2152 }
2153 }
2154
2155 return true; // CC didn't match.
2156}
2157
2158
2159bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
2160 MVT LocVT, CCValAssign::LocInfo LocInfo,
2161 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
2162
2163 if (LocVT == MVT::x86mmx) {
2164 LocVT = MVT::i64;
2165 LocInfo = CCValAssign::BCvt;
2166 }
2167
2168 if (LocVT == MVT::f16) {
2169 static const MCPhysReg RegList1[] = {
2170 AArch64::H0, AArch64::H1
2171 };
2172 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2173 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2174 return false;
2175 }
2176 }
2177
2178 if (LocVT == MVT::bf16) {
2179 static const MCPhysReg RegList2[] = {
2180 AArch64::H0, AArch64::H1
2181 };
2182 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2184 return false;
2185 }
2186 }
2187
2188 if (LocVT == MVT::f32) {
2189 static const MCPhysReg RegList3[] = {
2190 AArch64::S0, AArch64::S1
2191 };
2192 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2193 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2194 return false;
2195 }
2196 }
2197
2198 if (LocVT == MVT::f64) {
2199 static const MCPhysReg RegList4[] = {
2200 AArch64::D0, AArch64::D1
2201 };
2202 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2203 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2204 return false;
2205 }
2206 }
2207
2208 if (LocVT == MVT::f128) {
2209 static const MCPhysReg RegList5[] = {
2210 AArch64::Q0, AArch64::Q1
2211 };
2212 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2213 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2214 return false;
2215 }
2216 }
2217
2218 if (ArgFlags.isSwiftError()) {
2219 if (LocVT == MVT::i64) {
2220 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
2221 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2222 return false;
2223 }
2224 }
2225 }
2226
2227 if (LocVT == MVT::i1 ||
2228 LocVT == MVT::i8 ||
2229 LocVT == MVT::i16) {
2230 LocVT = MVT::i32;
2231 if (ArgFlags.isSExt())
2232 LocInfo = CCValAssign::SExt;
2233 else if (ArgFlags.isZExt())
2234 LocInfo = CCValAssign::ZExt;
2235 else
2236 LocInfo = CCValAssign::AExt;
2237 }
2238
2239 if (LocVT == MVT::i32) {
2240 static const MCPhysReg RegList6[] = {
2241 AArch64::W8, AArch64::W1, AArch64::W0
2242 };
2243 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2244 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2245 return false;
2246 }
2247 }
2248
2249 if (LocVT == MVT::i64) {
2250 static const MCPhysReg RegList7[] = {
2251 AArch64::X8, AArch64::X1, AArch64::X0
2252 };
2253 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2254 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2255 return false;
2256 }
2257 }
2258
2259 if (LocVT == MVT::v16i8 ||
2260 LocVT == MVT::v8i16 ||
2261 LocVT == MVT::v4i32 ||
2262 LocVT == MVT::v2i64 ||
2263 LocVT == MVT::v8f16 ||
2264 LocVT == MVT::v4f32 ||
2265 LocVT == MVT::v2f64) {
2266 static const MCPhysReg RegList8[] = {
2267 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
2268 };
2269 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
2270 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2271 return false;
2272 }
2273 }
2274
2275 return true; // CC didn't match.
2276}
2277
2278#endif // GET_CALLING_CONV_IMPL
2279
2280#ifdef GET_CC_REGISTER_LISTS
2281#undef GET_CC_REGISTER_LISTS
2282
2283const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2284const MCRegister CC_AArch64_AnyReg_ArgRegs[] = { 0 };
2285const MCRegister CC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X10, AArch64::X11, AArch64::X9 };
2286const MCRegister CC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::X4, AArch64::X8, AArch64::X9 };
2287const MCRegister CC_AArch64_Arm64EC_Thunk_Native_ArgRegs[] = { AArch64::X9 };
2288const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X8, AArch64::X9 };
2289const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2290const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { AArch64::X15 };
2291const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { AArch64::X15 };
2292const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 };
2293const MCRegister CC_AArch64_Preserve_None_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W2, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W9, AArch64::X0, AArch64::X1, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X2, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X9 };
2294const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2295const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 };
2296const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 };
2297const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2298const MCRegister RetCC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X11, AArch64::X9 };
2299const MCRegister RetCC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::H0, AArch64::H1, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::S0, AArch64::S1, AArch64::W0, AArch64::W1, AArch64::W8, AArch64::X0, AArch64::X1, AArch64::X8 };
2300
2301// Registers used by Swift.
2302const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2303const MCRegister CC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19, AArch64::X20, AArch64::X21 };
2304const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2305const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2306const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 };
2307const MCRegister RetCC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19 };
2308
2309#endif // GET_CC_REGISTER_LISTS
2310
2311