1//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15
16#include "AArch64FrameLowering.h"
17#include "AArch64ISelLowering.h"
18#include "AArch64InstrInfo.h"
19#include "AArch64PointerAuth.h"
20#include "AArch64RegisterInfo.h"
21#include "AArch64SelectionDAGInfo.h"
22#include "llvm/CodeGen/GlobalISel/CallLowering.h"
23#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
24#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
25#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
26#include "llvm/CodeGen/RegisterBankInfo.h"
27#include "llvm/CodeGen/TargetSubtargetInfo.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/TargetParser/Triple.h"
30
31#define GET_SUBTARGETINFO_HEADER
32#include "AArch64GenSubtargetInfo.inc"
33
34namespace llvm {
35class GlobalValue;
36class StringRef;
37
38class AArch64Subtarget final : public AArch64GenSubtargetInfo {
39public:
40 enum ARMProcFamilyEnum : uint8_t {
41 Generic,
42#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
43#include "llvm/TargetParser/AArch64TargetParserDef.inc"
44#undef ARM_PROCESSOR_FAMILY
45 };
46
47protected:
48 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
49 ARMProcFamilyEnum ARMProcFamily = Generic;
50
51 // Enable 64-bit vectorization in SLP.
52 unsigned MinVectorRegisterBitWidth = 64;
53
54// Bool members corresponding to the SubtargetFeatures defined in tablegen
55#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
56 bool ATTRIBUTE = DEFAULT;
57#include "AArch64GenSubtargetInfo.inc"
58
59 unsigned EpilogueVectorizationMinVF = 16;
60 uint8_t MaxInterleaveFactor = 2;
61 uint8_t VectorInsertExtractBaseCost = 2;
62 uint16_t CacheLineSize = 64;
63 // Default scatter/gather overhead.
64 unsigned ScatterOverhead = 10;
65 unsigned GatherOverhead = 10;
66 uint16_t PrefetchDistance = 0;
67 uint16_t MinPrefetchStride = 1;
68 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
69 Align PrefFunctionAlignment;
70 Align PrefLoopAlignment;
71 unsigned MaxBytesForLoopAlignment = 0;
72 unsigned MinimumJumpTableEntries = 4;
73 unsigned MaxJumpTableSize = 0;
74 unsigned FixedLoadLatency = 0;
75
76 // ReserveXRegister[i] - X#i is not available as a general purpose register.
77 BitVector ReserveXRegister;
78
79 // ReserveXRegisterForRA[i] - X#i is not available for register allocator.
80 BitVector ReserveXRegisterForRA;
81
82 // CustomCallUsedXRegister[i] - X#i call saved.
83 BitVector CustomCallSavedXRegs;
84
85 bool IsLittle;
86
87 bool IsStreaming;
88 bool IsStreamingCompatible;
89 std::optional<unsigned> StreamingHazardSize;
90 unsigned MinSVEVectorSizeInBits;
91 unsigned MaxSVEVectorSizeInBits;
92 bool EnableSRLTSubregToRegMitigation;
93 unsigned VScaleForTuning = 1;
94 TailFoldingOpts DefaultSVETFOpts = TailFoldingOpts::Disabled;
95
96 bool EnableSubregLiveness;
97
98 /// TargetTriple - What processor and OS we're targeting.
99 Triple TargetTriple;
100
101 AArch64FrameLowering FrameLowering;
102 AArch64InstrInfo InstrInfo;
103 AArch64SelectionDAGInfo TSInfo;
104 AArch64TargetLowering TLInfo;
105
106 /// GlobalISel related APIs.
107 std::unique_ptr<CallLowering> CallLoweringInfo;
108 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
109 std::unique_ptr<InstructionSelector> InstSelector;
110 std::unique_ptr<LegalizerInfo> Legalizer;
111 std::unique_ptr<RegisterBankInfo> RegBankInfo;
112
113private:
114 /// initializeSubtargetDependencies - Initializes using CPUString and the
115 /// passed in feature string so that we can use initializer lists for
116 /// subtarget initialization.
117 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
118 StringRef CPUString,
119 StringRef TuneCPUString,
120 bool HasMinSize);
121
122 /// Initialize properties based on the selected processor family.
123 void initializeProperties(bool HasMinSize);
124
125public:
126 /// This constructor initializes the data members to match that
127 /// of the specified triple.
128 AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
129 StringRef FS, const TargetMachine &TM, bool LittleEndian,
130 unsigned MinSVEVectorSizeInBitsOverride = 0,
131 unsigned MaxSVEVectorSizeInBitsOverride = 0,
132 bool IsStreaming = false, bool IsStreamingCompatible = false,
133 bool HasMinSize = false,
134 bool EnableSRLTSubregToRegMitigation = false);
135
136// Getters for SubtargetFeatures defined in tablegen
137#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
138 bool GETTER() const { return ATTRIBUTE; }
139#include "AArch64GenSubtargetInfo.inc"
140
141 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
142 return &TSInfo;
143 }
144 const AArch64FrameLowering *getFrameLowering() const override {
145 return &FrameLowering;
146 }
147 const AArch64TargetLowering *getTargetLowering() const override {
148 return &TLInfo;
149 }
150 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
151 const AArch64RegisterInfo *getRegisterInfo() const override {
152 return &getInstrInfo()->getRegisterInfo();
153 }
154 const CallLowering *getCallLowering() const override;
155 const InlineAsmLowering *getInlineAsmLowering() const override;
156 InstructionSelector *getInstructionSelector() const override;
157 const LegalizerInfo *getLegalizerInfo() const override;
158 const RegisterBankInfo *getRegBankInfo() const override;
159 const Triple &getTargetTriple() const { return TargetTriple; }
160 bool enableMachineScheduler() const override { return true; }
161 bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
162 bool enableSubRegLiveness() const override { return EnableSubregLiveness; }
163
164 bool enableMachinePipeliner() const override;
165 bool useDFAforSMS() const override { return false; }
166
167 /// Returns ARM processor family.
168 /// Avoid this function! CPU specifics should be kept local to this class
169 /// and preferably modeled with SubtargetFeatures or properties in
170 /// initializeProperties().
171 ARMProcFamilyEnum getProcFamily() const {
172 return ARMProcFamily;
173 }
174
175 /// Returns true if the processor is an Apple M-series or aligned A-series
176 /// (A14 or newer).
177 bool isAppleMLike() const {
178 switch (ARMProcFamily) {
179 case AppleA14:
180 case AppleA15:
181 case AppleA16:
182 case AppleA17:
183 case AppleM4:
184 case AppleM5:
185 return true;
186 default:
187 return false;
188 }
189 }
190
191 bool isXRaySupported() const override { return true; }
192
193 /// Returns true if the function has a streaming body.
194 bool isStreaming() const { return IsStreaming; }
195
196 /// Returns true if the function has a streaming-compatible body.
197 bool isStreamingCompatible() const { return IsStreamingCompatible; }
198
199 /// Returns the size of memory region that if accessed by both the CPU and
200 /// the SME unit could result in a hazard. 0 = disabled.
201 unsigned getStreamingHazardSize() const {
202 return StreamingHazardSize.value_or(
203 u: !hasSMEFA64() && hasSME() && hasSVE() ? 1024 : 0);
204 }
205
206 /// Returns true if the target has NEON and the function at runtime is known
207 /// to have NEON enabled (e.g. the function is known not to be in streaming-SVE
208 /// mode, which disables NEON instructions).
209 bool isNeonAvailable() const {
210 return hasNEON() &&
211 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
212 }
213
214 /// Returns true if the target has SVE and can use the full range of SVE
215 /// instructions, for example because it knows the function is known not to be
216 /// in streaming-SVE mode or when the target has FEAT_FA64 enabled.
217 bool isSVEAvailable() const {
218 return hasSVE() &&
219 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
220 }
221
222 /// Returns true if the target has access to the streaming-compatible subset
223 /// of SVE instructions.
224 bool isStreamingSVEAvailable() const { return hasSME() && isStreaming(); }
225
226 /// Returns true if the target has access to either the full range of SVE
227 /// instructions, or the streaming-compatible subset of SVE instructions.
228 bool isSVEorStreamingSVEAvailable() const {
229 return hasSVE() || isStreamingSVEAvailable();
230 }
231
232 /// Returns true if the target has access to either the full range of SVE
233 /// instructions, or the streaming-compatible subset of SVE instructions
234 /// available to SME2.
235 bool isNonStreamingSVEorSME2Available() const {
236 return isSVEAvailable() || (isSVEorStreamingSVEAvailable() && hasSME2());
237 }
238
239 unsigned getMinVectorRegisterBitWidth() const {
240 // Don't assume any minimum vector size when PSTATE.SM may not be 0, because
241 // we don't yet support streaming-compatible codegen support that we trust
242 // is safe for functions that may be executed in streaming-SVE mode.
243 // By returning '0' here, we disable vectorization.
244 if (!isSVEAvailable() && !isNeonAvailable())
245 return 0;
246 return MinVectorRegisterBitWidth;
247 }
248
249 bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
250 bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
251 unsigned getNumXRegisterReserved() const {
252 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
253 AllReservedX |= ReserveXRegister;
254 AllReservedX |= ReserveXRegisterForRA;
255 return AllReservedX.count();
256 }
257 bool isLRReservedForRA() const { return ReserveLRForRA; }
258 bool isXRegCustomCalleeSaved(size_t i) const {
259 return CustomCallSavedXRegs[i];
260 }
261 bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
262
263 /// Return true if the CPU supports any kind of instruction fusion.
264 bool hasFusion() const {
265 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
266 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCmpCSel() ||
267 hasFuseFCmpFCSel() || hasFuseCmpCSet() || hasFuseAdrpAdd() ||
268 hasFuseLiterals() || hasFuseAppleSMECompute() || hasFuseFMinFMax();
269 }
270
271 /// Return true if the subtarget fuses this pair of move immediate
272 /// instructions.
273 bool fusesMOVImmPair(unsigned FirstOpc, unsigned FirstShift,
274 unsigned SecondOpc, unsigned SecondShift) const;
275
276 /// Return true if the subtarget fuses this pair of move immediate
277 /// instructions. The 1st instruction is a wildcard when it is nullptr, which
278 /// tells whether the 2nd one can be fused at all.
279 bool fusesMOVImmPair(const MachineInstr *FirstMI,
280 const MachineInstr &SecondMI) const;
281
282 unsigned getEpilogueVectorizationMinVF() const {
283 return EpilogueVectorizationMinVF;
284 }
285 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
286 unsigned getVectorInsertExtractBaseCost() const;
287 unsigned getCacheLineSize() const override { return CacheLineSize; }
288 unsigned getScatterOverhead() const { return ScatterOverhead; }
289 unsigned getGatherOverhead() const { return GatherOverhead; }
290 unsigned getPrefetchDistance() const override { return PrefetchDistance; }
291 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
292 unsigned NumStridedMemAccesses,
293 unsigned NumPrefetches,
294 bool HasCall) const override {
295 return MinPrefetchStride;
296 }
297 unsigned getMaxPrefetchIterationsAhead() const override {
298 return MaxPrefetchIterationsAhead;
299 }
300 Align getPrefFunctionAlignment() const {
301 return PrefFunctionAlignment;
302 }
303 Align getPrefLoopAlignment() const { return PrefLoopAlignment; }
304
305 unsigned getMaxBytesForLoopAlignment() const {
306 return MaxBytesForLoopAlignment;
307 }
308
309 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
310 unsigned getMinimumJumpTableEntries() const {
311 return MinimumJumpTableEntries;
312 }
313
314 unsigned getFixedLoadLatency() const { return FixedLoadLatency; }
315
316 /// CPU has TBI (top byte of addresses is ignored during HW address
317 /// translation) and OS enables it.
318 bool supportsAddressTopByteIgnored() const;
319
320 bool isLittleEndian() const { return IsLittle; }
321
322 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
323 bool isTargetIOS() const { return TargetTriple.isiOS(); }
324 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
325 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
326 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
327 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
328 bool isWindowsArm64EC() const { return TargetTriple.isWindowsArm64EC(); }
329 bool isLFI() const { return TargetTriple.isLFI(); }
330
331 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
332 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
333 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
334
335 bool isTargetILP32() const {
336 return TargetTriple.isArch32Bit() ||
337 TargetTriple.getEnvironment() == Triple::GNUILP32;
338 }
339
340 bool useAA() const override;
341
342 bool addrSinkUsingGEPs() const override {
343 // Keeping GEPs inbounds is important for exploiting AArch64
344 // addressing-modes in ILP32 mode.
345 return useAA() || isTargetILP32();
346 }
347
348 bool useSmallAddressing() const {
349 switch (TLInfo.getTargetMachine().getCodeModel()) {
350 case CodeModel::Kernel:
351 // Kernel is currently allowed only for Fuchsia targets,
352 // where it is the same as Small for almost all purposes.
353 case CodeModel::Small:
354 return true;
355 default:
356 return false;
357 }
358 }
359
360 /// Returns whether the operating system makes it safer to store sensitive
361 /// values in x16 and x17 as opposed to other registers.
362 bool isX16X17Safer() const;
363
364 /// ParseSubtargetFeatures - Parses features string setting specified
365 /// subtarget options. Definition of function is auto generated by tblgen.
366 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
367
368 /// ClassifyGlobalReference - Find the target operand flags that describe
369 /// how a global value should be referenced for the current subtarget.
370 unsigned ClassifyGlobalReference(const GlobalValue *GV,
371 const TargetMachine &TM) const;
372
373 unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
374 const TargetMachine &TM) const;
375
376 /// This function is design to compatible with the function def in other
377 /// targets and escape build error about the virtual function def in base
378 /// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
379 unsigned char
380 classifyGlobalFunctionReference(const GlobalValue *GV) const override {
381 return 0;
382 }
383
384 void overrideSchedPolicy(MachineSchedPolicy &Policy,
385 const SchedRegion &Region) const override;
386
387 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
388 SDep &Dep,
389 const TargetSchedModel *SchedModel) const override;
390
391 bool enableEarlyIfConversion() const override;
392
393 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
394
395 bool isCallingConvWin64(CallingConv::ID CC, bool IsVarArg) const {
396 switch (CC) {
397 case CallingConv::C:
398 case CallingConv::Fast:
399 case CallingConv::Swift:
400 case CallingConv::SwiftTail:
401 return isTargetWindows();
402 case CallingConv::PreserveNone:
403 return IsVarArg && isTargetWindows();
404 case CallingConv::Win64:
405 return true;
406 default:
407 return false;
408 }
409 }
410
411 /// Return whether FrameLowering should always set the "extended frame
412 /// present" bit in FP, or set it based on a symbol in the runtime.
413 bool swiftAsyncContextIsDynamicallySet() const {
414 // Older OS versions (particularly system unwinders) are confused by the
415 // Swift extended frame, so when building code that might be run on them we
416 // must dynamically query the concurrency library to determine whether
417 // extended frames should be flagged as present.
418 const Triple &TT = getTargetTriple();
419
420 unsigned Major = TT.getOSVersion().getMajor();
421 switch(TT.getOS()) {
422 default:
423 return false;
424 case Triple::IOS:
425 case Triple::TvOS:
426 return Major < 15;
427 case Triple::WatchOS:
428 return Major < 8;
429 case Triple::MacOSX:
430 case Triple::Darwin:
431 return Major < 12;
432 }
433 }
434
435 void mirFileLoaded(MachineFunction &MF) const override;
436
437 // Return the known range for the bit length of SVE data registers. A value
438 // of 0 means nothing is known about that particular limit beyond what's
439 // implied by the architecture.
440 unsigned getMaxSVEVectorSizeInBits() const {
441 assert(isSVEorStreamingSVEAvailable() &&
442 "Tried to get SVE vector length without SVE support!");
443 return MaxSVEVectorSizeInBits;
444 }
445
446 unsigned getMinSVEVectorSizeInBits() const {
447 assert(isSVEorStreamingSVEAvailable() &&
448 "Tried to get SVE vector length without SVE support!");
449 return MinSVEVectorSizeInBits;
450 }
451
452 // Return the known bit length of SVE data registers. A value of 0 means the
453 // length is unknown beyond what's implied by the architecture.
454 unsigned getSVEVectorSizeInBits() const {
455 assert(isSVEorStreamingSVEAvailable() &&
456 "Tried to get SVE vector length without SVE support!");
457 if (MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
458 return MaxSVEVectorSizeInBits;
459 return 0;
460 }
461
462 // Return the known bit length of SVE predicate registers. A value of 0 means
463 // the length is unknown beyond what's implied by the architecture.
464 unsigned getSVEPredicateSizeInBits() const {
465 return getSVEVectorSizeInBits() / 8;
466 }
467
468 bool useSVEForFixedLengthVectors() const {
469 if (!isSVEorStreamingSVEAvailable())
470 return false;
471
472 // Prefer NEON unless larger SVE registers are available.
473 return !isNeonAvailable() || getMinSVEVectorSizeInBits() >= 256;
474 }
475
476 bool useSVEForFixedLengthVectors(EVT VT) const {
477 if (!useSVEForFixedLengthVectors() || !VT.isFixedLengthVector())
478 return false;
479 return VT.getFixedSizeInBits() > AArch64::SVEBitsPerBlock ||
480 !isNeonAvailable();
481 }
482
483 unsigned getVScaleForTuning() const { return VScaleForTuning; }
484
485 TailFoldingOpts getSVETailFoldingDefaultOpts() const {
486 return DefaultSVETFOpts;
487 }
488
489 /// Returns true to use the addvl/inc/dec instructions, as opposed to separate
490 /// add + cnt instructions.
491 bool useScalarIncVL() const;
492
493 bool enableSRLTSubregToRegMitigation() const {
494 return EnableSRLTSubregToRegMitigation;
495 }
496
497 /// Choose a method of checking LR before performing a tail call.
498 AArch64PAuth::AuthCheckMethod
499 getAuthenticatedLRCheckMethod(const MachineFunction &MF) const;
500
501 /// Compute the integer discriminator for a given BlockAddress constant, if
502 /// blockaddress signing is enabled, or std::nullopt otherwise.
503 /// Blockaddress signing is controlled by the function attribute
504 /// "ptrauth-indirect-gotos" on the parent function.
505 /// Note that this assumes the discriminator is independent of the indirect
506 /// goto branch site itself, i.e., it's the same for all BlockAddresses in
507 /// a function.
508 std::optional<uint16_t>
509 getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const;
510
511 bool enableAggressiveInterleaving() const { return AggressiveInterleaving; }
512};
513} // End llvm namespace
514
515#endif
516