1//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15
16#include "AArch64FrameLowering.h"
17#include "AArch64ISelLowering.h"
18#include "AArch64InstrInfo.h"
19#include "AArch64PointerAuth.h"
20#include "AArch64RegisterInfo.h"
21#include "AArch64SelectionDAGInfo.h"
22#include "llvm/CodeGen/GlobalISel/CallLowering.h"
23#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
24#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
25#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
26#include "llvm/CodeGen/RegisterBankInfo.h"
27#include "llvm/CodeGen/TargetSubtargetInfo.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/TargetParser/Triple.h"
30
31#define GET_SUBTARGETINFO_HEADER
32#include "AArch64GenSubtargetInfo.inc"
33
34namespace llvm {
35class GlobalValue;
36class StringRef;
37
38class AArch64Subtarget final : public AArch64GenSubtargetInfo {
39public:
40 enum ARMProcFamilyEnum : uint8_t {
41 Generic,
42#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
43#include "llvm/TargetParser/AArch64TargetParserDef.inc"
44#undef ARM_PROCESSOR_FAMILY
45 };
46
47protected:
48 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
49 ARMProcFamilyEnum ARMProcFamily = Generic;
50
51 // Enable 64-bit vectorization in SLP.
52 unsigned MinVectorRegisterBitWidth = 64;
53
54// Bool members corresponding to the SubtargetFeatures defined in tablegen
55#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
56 bool ATTRIBUTE = DEFAULT;
57#include "AArch64GenSubtargetInfo.inc"
58
59 unsigned EpilogueVectorizationMinVF = 16;
60 uint8_t MaxInterleaveFactor = 2;
61 uint8_t VectorInsertExtractBaseCost = 2;
62 uint16_t CacheLineSize = 64;
63 // Default scatter/gather overhead.
64 unsigned ScatterOverhead = 10;
65 unsigned GatherOverhead = 10;
66 uint16_t PrefetchDistance = 0;
67 uint16_t MinPrefetchStride = 1;
68 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
69 Align PrefFunctionAlignment;
70 Align PrefLoopAlignment;
71 unsigned MaxBytesForLoopAlignment = 0;
72 unsigned MinimumJumpTableEntries = 4;
73 unsigned MaxJumpTableSize = 0;
74 unsigned FixedLoadLatency = 0;
75
76 // ReserveXRegister[i] - X#i is not available as a general purpose register.
77 BitVector ReserveXRegister;
78
79 // ReserveXRegisterForRA[i] - X#i is not available for register allocator.
80 BitVector ReserveXRegisterForRA;
81
82 // CustomCallUsedXRegister[i] - X#i call saved.
83 BitVector CustomCallSavedXRegs;
84
85 bool IsLittle;
86
87 bool IsStreaming;
88 bool IsStreamingCompatible;
89 std::optional<unsigned> StreamingHazardSize;
90 unsigned MinSVEVectorSizeInBits;
91 unsigned MaxSVEVectorSizeInBits;
92 bool EnableSRLTSubregToRegMitigation;
93 unsigned VScaleForTuning = 1;
94 TailFoldingOpts DefaultSVETFOpts = TailFoldingOpts::Disabled;
95
96 bool EnableSubregLiveness;
97
98 /// TargetTriple - What processor and OS we're targeting.
99 Triple TargetTriple;
100
101 AArch64FrameLowering FrameLowering;
102 AArch64InstrInfo InstrInfo;
103 AArch64SelectionDAGInfo TSInfo;
104 AArch64TargetLowering TLInfo;
105
106 /// GlobalISel related APIs.
107 std::unique_ptr<CallLowering> CallLoweringInfo;
108 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
109 std::unique_ptr<InstructionSelector> InstSelector;
110 std::unique_ptr<LegalizerInfo> Legalizer;
111 std::unique_ptr<RegisterBankInfo> RegBankInfo;
112
113private:
114 /// initializeSubtargetDependencies - Initializes using CPUString and the
115 /// passed in feature string so that we can use initializer lists for
116 /// subtarget initialization.
117 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
118 StringRef CPUString,
119 StringRef TuneCPUString,
120 bool HasMinSize);
121
122 /// Initialize properties based on the selected processor family.
123 void initializeProperties(bool HasMinSize);
124
125public:
126 /// This constructor initializes the data members to match that
127 /// of the specified triple.
128 AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
129 StringRef FS, const TargetMachine &TM, bool LittleEndian,
130 unsigned MinSVEVectorSizeInBitsOverride = 0,
131 unsigned MaxSVEVectorSizeInBitsOverride = 0,
132 bool IsStreaming = false, bool IsStreamingCompatible = false,
133 bool HasMinSize = false,
134 bool EnableSRLTSubregToRegMitigation = false);
135
136// Getters for SubtargetFeatures defined in tablegen
137#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
138 bool GETTER() const { return ATTRIBUTE; }
139#include "AArch64GenSubtargetInfo.inc"
140
141 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
142 return &TSInfo;
143 }
144 const AArch64FrameLowering *getFrameLowering() const override {
145 return &FrameLowering;
146 }
147 const AArch64TargetLowering *getTargetLowering() const override {
148 return &TLInfo;
149 }
150 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
151 const AArch64RegisterInfo *getRegisterInfo() const override {
152 return &getInstrInfo()->getRegisterInfo();
153 }
154 const CallLowering *getCallLowering() const override;
155 const InlineAsmLowering *getInlineAsmLowering() const override;
156 InstructionSelector *getInstructionSelector() const override;
157 const LegalizerInfo *getLegalizerInfo() const override;
158 const RegisterBankInfo *getRegBankInfo() const override;
159 const Triple &getTargetTriple() const { return TargetTriple; }
160 bool enableMachineScheduler() const override { return true; }
161 bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
162 bool enableSubRegLiveness() const override { return EnableSubregLiveness; }
163 bool enableSpillageCopyElimination() const override { return true; }
164
165 bool enableMachinePipeliner() const override;
166 bool useDFAforSMS() const override { return false; }
167
168 /// Returns ARM processor family.
169 /// Avoid this function! CPU specifics should be kept local to this class
170 /// and preferably modeled with SubtargetFeatures or properties in
171 /// initializeProperties().
172 ARMProcFamilyEnum getProcFamily() const {
173 return ARMProcFamily;
174 }
175
176 /// Returns true if the processor is an Apple M-series or aligned A-series
177 /// (A14 or newer).
178 bool isAppleMLike() const {
179 switch (ARMProcFamily) {
180 case AppleA14:
181 case AppleA15:
182 case AppleA16:
183 case AppleA17:
184 case AppleM4:
185 case AppleM5:
186 return true;
187 default:
188 return false;
189 }
190 }
191
192 bool isXRaySupported() const override { return true; }
193
194 /// Returns true if the function has a streaming body.
195 bool isStreaming() const { return IsStreaming; }
196
197 /// Returns true if the function has a streaming-compatible body.
198 bool isStreamingCompatible() const { return IsStreamingCompatible; }
199
200 /// Returns the size of memory region that if accessed by both the CPU and
201 /// the SME unit could result in a hazard. 0 = disabled.
202 unsigned getStreamingHazardSize() const {
203 return StreamingHazardSize.value_or(
204 u: !hasSMEFA64() && hasSME() && hasSVE() ? 1024 : 0);
205 }
206
207 /// Returns true if the target has NEON and the function at runtime is known
208 /// to have NEON enabled (e.g. the function is known not to be in streaming-SVE
209 /// mode, which disables NEON instructions).
210 bool isNeonAvailable() const {
211 return hasNEON() &&
212 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
213 }
214
215 /// Returns true if the target has SVE and can use the full range of SVE
216 /// instructions, for example because it knows the function is known not to be
217 /// in streaming-SVE mode or when the target has FEAT_FA64 enabled.
218 bool isSVEAvailable() const {
219 return hasSVE() &&
220 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
221 }
222
223 /// Returns true if the target has access to the streaming-compatible subset
224 /// of SVE instructions.
225 bool isStreamingSVEAvailable() const { return hasSME() && isStreaming(); }
226
227 /// Returns true if the target has access to either the full range of SVE
228 /// instructions, or the streaming-compatible subset of SVE instructions.
229 bool isSVEorStreamingSVEAvailable() const {
230 return hasSVE() || isStreamingSVEAvailable();
231 }
232
233 /// Returns true if the target has access to either the full range of SVE
234 /// instructions, or the streaming-compatible subset of SVE instructions
235 /// available to SME2.
236 bool isNonStreamingSVEorSME2Available() const {
237 return isSVEAvailable() || (isSVEorStreamingSVEAvailable() && hasSME2());
238 }
239
240 unsigned getMinVectorRegisterBitWidth() const {
241 // Don't assume any minimum vector size when PSTATE.SM may not be 0, because
242 // we don't yet support streaming-compatible codegen support that we trust
243 // is safe for functions that may be executed in streaming-SVE mode.
244 // By returning '0' here, we disable vectorization.
245 if (!isSVEAvailable() && !isNeonAvailable())
246 return 0;
247 return MinVectorRegisterBitWidth;
248 }
249
250 bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
251 bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
252 unsigned getNumXRegisterReserved() const {
253 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
254 AllReservedX |= ReserveXRegister;
255 AllReservedX |= ReserveXRegisterForRA;
256 return AllReservedX.count();
257 }
258 bool isLRReservedForRA() const { return ReserveLRForRA; }
259 bool isXRegCustomCalleeSaved(size_t i) const {
260 return CustomCallSavedXRegs[i];
261 }
262 bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
263
264 /// Return true if the CPU supports any kind of instruction fusion.
265 bool hasFusion() const {
266 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
267 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCmpCSel() ||
268 hasFuseFCmpFCSel() || hasFuseCmpCSet() || hasFuseAdrpAdd() ||
269 hasFuseLiterals();
270 }
271
272 unsigned getEpilogueVectorizationMinVF() const {
273 return EpilogueVectorizationMinVF;
274 }
275 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
276 unsigned getVectorInsertExtractBaseCost() const;
277 unsigned getCacheLineSize() const override { return CacheLineSize; }
278 unsigned getScatterOverhead() const { return ScatterOverhead; }
279 unsigned getGatherOverhead() const { return GatherOverhead; }
280 unsigned getPrefetchDistance() const override { return PrefetchDistance; }
281 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
282 unsigned NumStridedMemAccesses,
283 unsigned NumPrefetches,
284 bool HasCall) const override {
285 return MinPrefetchStride;
286 }
287 unsigned getMaxPrefetchIterationsAhead() const override {
288 return MaxPrefetchIterationsAhead;
289 }
290 Align getPrefFunctionAlignment() const {
291 return PrefFunctionAlignment;
292 }
293 Align getPrefLoopAlignment() const { return PrefLoopAlignment; }
294
295 unsigned getMaxBytesForLoopAlignment() const {
296 return MaxBytesForLoopAlignment;
297 }
298
299 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
300 unsigned getMinimumJumpTableEntries() const {
301 return MinimumJumpTableEntries;
302 }
303
304 unsigned getFixedLoadLatency() const { return FixedLoadLatency; }
305
306 /// CPU has TBI (top byte of addresses is ignored during HW address
307 /// translation) and OS enables it.
308 bool supportsAddressTopByteIgnored() const;
309
310 bool isLittleEndian() const { return IsLittle; }
311
312 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
313 bool isTargetIOS() const { return TargetTriple.isiOS(); }
314 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
315 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
316 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
317 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
318 bool isWindowsArm64EC() const { return TargetTriple.isWindowsArm64EC(); }
319 bool isLFI() const { return TargetTriple.isLFI(); }
320
321 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
322 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
323 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
324
325 bool isTargetILP32() const {
326 return TargetTriple.isArch32Bit() ||
327 TargetTriple.getEnvironment() == Triple::GNUILP32;
328 }
329
330 bool useAA() const override;
331
332 bool addrSinkUsingGEPs() const override {
333 // Keeping GEPs inbounds is important for exploiting AArch64
334 // addressing-modes in ILP32 mode.
335 return useAA() || isTargetILP32();
336 }
337
338 bool useSmallAddressing() const {
339 switch (TLInfo.getTargetMachine().getCodeModel()) {
340 case CodeModel::Kernel:
341 // Kernel is currently allowed only for Fuchsia targets,
342 // where it is the same as Small for almost all purposes.
343 case CodeModel::Small:
344 return true;
345 default:
346 return false;
347 }
348 }
349
350 /// Returns whether the operating system makes it safer to store sensitive
351 /// values in x16 and x17 as opposed to other registers.
352 bool isX16X17Safer() const;
353
354 /// ParseSubtargetFeatures - Parses features string setting specified
355 /// subtarget options. Definition of function is auto generated by tblgen.
356 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
357
358 /// ClassifyGlobalReference - Find the target operand flags that describe
359 /// how a global value should be referenced for the current subtarget.
360 unsigned ClassifyGlobalReference(const GlobalValue *GV,
361 const TargetMachine &TM) const;
362
363 unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
364 const TargetMachine &TM) const;
365
366 /// This function is design to compatible with the function def in other
367 /// targets and escape build error about the virtual function def in base
368 /// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
369 unsigned char
370 classifyGlobalFunctionReference(const GlobalValue *GV) const override {
371 return 0;
372 }
373
374 void overrideSchedPolicy(MachineSchedPolicy &Policy,
375 const SchedRegion &Region) const override;
376
377 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
378 SDep &Dep,
379 const TargetSchedModel *SchedModel) const override;
380
381 bool enableEarlyIfConversion() const override;
382
383 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
384
385 bool isCallingConvWin64(CallingConv::ID CC, bool IsVarArg) const {
386 switch (CC) {
387 case CallingConv::C:
388 case CallingConv::Fast:
389 case CallingConv::Swift:
390 case CallingConv::SwiftTail:
391 return isTargetWindows();
392 case CallingConv::PreserveNone:
393 return IsVarArg && isTargetWindows();
394 case CallingConv::Win64:
395 return true;
396 default:
397 return false;
398 }
399 }
400
401 /// Return whether FrameLowering should always set the "extended frame
402 /// present" bit in FP, or set it based on a symbol in the runtime.
403 bool swiftAsyncContextIsDynamicallySet() const {
404 // Older OS versions (particularly system unwinders) are confused by the
405 // Swift extended frame, so when building code that might be run on them we
406 // must dynamically query the concurrency library to determine whether
407 // extended frames should be flagged as present.
408 const Triple &TT = getTargetTriple();
409
410 unsigned Major = TT.getOSVersion().getMajor();
411 switch(TT.getOS()) {
412 default:
413 return false;
414 case Triple::IOS:
415 case Triple::TvOS:
416 return Major < 15;
417 case Triple::WatchOS:
418 return Major < 8;
419 case Triple::MacOSX:
420 case Triple::Darwin:
421 return Major < 12;
422 }
423 }
424
425 void mirFileLoaded(MachineFunction &MF) const override;
426
427 // Return the known range for the bit length of SVE data registers. A value
428 // of 0 means nothing is known about that particular limit beyond what's
429 // implied by the architecture.
430 unsigned getMaxSVEVectorSizeInBits() const {
431 assert(isSVEorStreamingSVEAvailable() &&
432 "Tried to get SVE vector length without SVE support!");
433 return MaxSVEVectorSizeInBits;
434 }
435
436 unsigned getMinSVEVectorSizeInBits() const {
437 assert(isSVEorStreamingSVEAvailable() &&
438 "Tried to get SVE vector length without SVE support!");
439 return MinSVEVectorSizeInBits;
440 }
441
442 // Return the known bit length of SVE data registers. A value of 0 means the
443 // length is unknown beyond what's implied by the architecture.
444 unsigned getSVEVectorSizeInBits() const {
445 assert(isSVEorStreamingSVEAvailable() &&
446 "Tried to get SVE vector length without SVE support!");
447 if (MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
448 return MaxSVEVectorSizeInBits;
449 return 0;
450 }
451
452 // Return the known bit length of SVE predicate registers. A value of 0 means
453 // the length is unknown beyond what's implied by the architecture.
454 unsigned getSVEPredicateSizeInBits() const {
455 return getSVEVectorSizeInBits() / 8;
456 }
457
458 bool useSVEForFixedLengthVectors() const {
459 if (!isSVEorStreamingSVEAvailable())
460 return false;
461
462 // Prefer NEON unless larger SVE registers are available.
463 return !isNeonAvailable() || getMinSVEVectorSizeInBits() >= 256;
464 }
465
466 bool useSVEForFixedLengthVectors(EVT VT) const {
467 if (!useSVEForFixedLengthVectors() || !VT.isFixedLengthVector())
468 return false;
469 return VT.getFixedSizeInBits() > AArch64::SVEBitsPerBlock ||
470 !isNeonAvailable();
471 }
472
473 unsigned getVScaleForTuning() const { return VScaleForTuning; }
474
475 TailFoldingOpts getSVETailFoldingDefaultOpts() const {
476 return DefaultSVETFOpts;
477 }
478
479 /// Returns true to use the addvl/inc/dec instructions, as opposed to separate
480 /// add + cnt instructions.
481 bool useScalarIncVL() const;
482
483 bool enableSRLTSubregToRegMitigation() const {
484 return EnableSRLTSubregToRegMitigation;
485 }
486
487 /// Choose a method of checking LR before performing a tail call.
488 AArch64PAuth::AuthCheckMethod
489 getAuthenticatedLRCheckMethod(const MachineFunction &MF) const;
490
491 /// Compute the integer discriminator for a given BlockAddress constant, if
492 /// blockaddress signing is enabled, or std::nullopt otherwise.
493 /// Blockaddress signing is controlled by the function attribute
494 /// "ptrauth-indirect-gotos" on the parent function.
495 /// Note that this assumes the discriminator is independent of the indirect
496 /// goto branch site itself, i.e., it's the same for all BlockAddresses in
497 /// a function.
498 std::optional<uint16_t>
499 getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const;
500
501 bool enableAggressiveInterleaving() const { return AggressiveInterleaving; }
502};
503} // End llvm namespace
504
505#endif
506