1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AArch64 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16
17#include "llvm/CodeGen/CallingConvLower.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/CodeGen/TargetLowering.h"
21#include "llvm/IR/CallingConv.h"
22#include "llvm/IR/Instruction.h"
23
24namespace llvm {
25
26class AArch64TargetMachine;
27
28namespace AArch64 {
29/// Possible values of current rounding mode, which is specified in bits
30/// 23:22 of FPCR.
31enum Rounding {
32 RN = 0, // Round to Nearest
33 RP = 1, // Round towards Plus infinity
34 RM = 2, // Round towards Minus infinity
35 RZ = 3, // Round towards Zero
36 rmMask = 3 // Bit mask selecting rounding mode
37};
38
39// Bit position of rounding mode bits in FPCR.
40const unsigned RoundingBitsPos = 22;
41
42// Reserved bits should be preserved when modifying FPCR.
43const uint64_t ReservedFPControlBits = 0xfffffffff80040f8;
44
45// Registers used to pass function arguments.
46ArrayRef<MCPhysReg> getGPRArgRegs();
47ArrayRef<MCPhysReg> getFPRArgRegs();
48
49/// Maximum allowed number of unprobed bytes above SP at an ABI
50/// boundary.
51const unsigned StackProbeMaxUnprobedStack = 1024;
52
53/// Maximum number of iterations to unroll for a constant size probing loop.
54const unsigned StackProbeMaxLoopUnroll = 4;
55
56} // namespace AArch64
57
58namespace ARM64AS {
59enum : unsigned { PTR32_SPTR = 270, PTR32_UPTR = 271, PTR64 = 272 };
60}
61
62class AArch64Subtarget;
63
64class AArch64TargetLowering : public TargetLowering {
65public:
66 explicit AArch64TargetLowering(const TargetMachine &TM,
67 const AArch64Subtarget &STI);
68
69 const AArch64TargetMachine &getTM() const;
70
71 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
72 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
73 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
74 SDValue N1) const override;
75
76 /// Selects the correct CCAssignFn for a given CallingConvention value.
77 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
78
79 /// Selects the correct CCAssignFn for a given CallingConvention value.
80 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
81
82 /// Determine which of the bits specified in Mask are known to be either zero
83 /// or one and return them in the KnownZero/KnownOne bitsets.
84 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
85 const APInt &DemandedElts,
86 const SelectionDAG &DAG,
87 unsigned Depth = 0) const override;
88
89 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
90 const APInt &DemandedElts,
91 const SelectionDAG &DAG,
92 unsigned Depth) const override;
93
94 unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
95 Register R,
96 const APInt &DemandedElts,
97 const MachineRegisterInfo &MRI,
98 unsigned Depth = 0) const override;
99
100 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
101 if ((AS == ARM64AS::PTR32_SPTR) || (AS == ARM64AS::PTR32_UPTR)) {
102 // These are 32-bit pointers created using the `__ptr32` extension or
103 // similar. They are handled by marking them as being in a different
104 // address space, and will be extended to 64-bits when used as the target
105 // of a load or store operation, or cast to a 64-bit pointer type.
106 return MVT::i32;
107 } else {
108 // Returning i64 unconditionally here (i.e. even for ILP32) means that the
109 // *DAG* representation of pointers will always be 64-bits. They will be
110 // truncated and extended when transferred to memory, but the 64-bit DAG
111 // allows us to use AArch64's addressing modes much more easily.
112 return MVT::i64;
113 }
114 }
115
116 unsigned getVectorIdxWidth(const DataLayout &DL) const override {
117 // The VectorIdx type is i64, with both normal and ilp32.
118 return 64;
119 }
120
121 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
122 const APInt &DemandedElts,
123 TargetLoweringOpt &TLO) const override;
124
125 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
126
127 /// Returns true if the target allows unaligned memory accesses of the
128 /// specified type.
129 bool allowsMisalignedMemoryAccesses(
130 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
131 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
132 unsigned *Fast = nullptr) const override;
133 /// LLT variant.
134 bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
135 Align Alignment,
136 MachineMemOperand::Flags Flags,
137 unsigned *Fast = nullptr) const override;
138
139 /// Provide custom lowering hooks for some operations.
140 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
141
142 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
143
144 /// This method returns a target specific FastISel object, or null if the
145 /// target does not support "fast" ISel.
146 FastISel *
147 createFastISel(FunctionLoweringInfo &funcInfo,
148 const TargetLibraryInfo *libInfo,
149 const LibcallLoweringInfo *libcallLowering) const override;
150
151 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
152
153 bool isFPImmLegalAsFMov(const APFloat &Imm, EVT VT) const;
154
155 bool isFPImmLegal(const APFloat &Imm, EVT VT,
156 bool ForCodeSize) const override;
157
158 /// Return true if the given shuffle mask can be codegen'd directly, or if it
159 /// should be stack expanded.
160 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
161
162 /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
163 /// shuffle mask can be codegen'd directly.
164 bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
165
166 /// Return the ISD::SETCC ValueType.
167 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
168 EVT VT) const override;
169
170 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
171
172 MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
173 MachineBasicBlock *BB) const;
174
175 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
176 MachineBasicBlock *BB) const;
177
178 MachineBasicBlock *EmitLoweredSetFpmr(MachineInstr &MI,
179 MachineBasicBlock *MBB) const;
180
181 MachineBasicBlock *EmitDynamicProbedAlloc(MachineInstr &MI,
182 MachineBasicBlock *MBB) const;
183
184 MachineBasicBlock *EmitCheckMatchingVL(MachineInstr &MI,
185 MachineBasicBlock *MBB) const;
186
187 MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
188 MachineInstr &MI,
189 MachineBasicBlock *BB) const;
190 MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const;
191 MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
192 MachineInstr &MI, MachineBasicBlock *BB) const;
193 MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB,
194 unsigned Opcode, bool Op0IsDef) const;
195 MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const;
196 MachineBasicBlock *EmitEntryPStateSM(MachineInstr &MI,
197 MachineBasicBlock *BB) const;
198
199 /// Replace (0, vreg) discriminator components with the operands of blend
200 /// or with (immediate, NoRegister) when possible.
201 void fixupPtrauthDiscriminator(MachineInstr &MI, MachineBasicBlock *BB,
202 MachineOperand &IntDiscOp,
203 MachineOperand &AddrDiscOp,
204 const TargetRegisterClass *AddrDiscRC) const;
205
206 MachineBasicBlock *
207 EmitInstrWithCustomInserter(MachineInstr &MI,
208 MachineBasicBlock *MBB) const override;
209
210 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
211 const CallBase &I, MachineFunction &MF,
212 unsigned Intrinsic) const override;
213
214 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
215 std::optional<unsigned> ByteOffset) const override;
216
217 bool shouldRemoveRedundantExtend(SDValue Op) const override;
218
219 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
220 bool isTruncateFree(EVT VT1, EVT VT2) const override;
221
222 bool isProfitableToHoist(Instruction *I) const override;
223
224 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
225 bool isZExtFree(EVT VT1, EVT VT2) const override;
226 bool isZExtFree(SDValue Val, EVT VT2) const override;
227
228 bool optimizeExtendOrTruncateConversion(
229 Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override;
230
231 bool hasPairedLoad(EVT LoadedType, Align &RequiredAlignment) const override;
232
233 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
234
235 bool lowerInterleavedLoad(Instruction *Load, Value *Mask,
236 ArrayRef<ShuffleVectorInst *> Shuffles,
237 ArrayRef<unsigned> Indices, unsigned Factor,
238 const APInt &GapMask) const override;
239 bool lowerInterleavedStore(Instruction *Store, Value *Mask,
240 ShuffleVectorInst *SVI, unsigned Factor,
241 const APInt &GapMask) const override;
242
243 bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask,
244 IntrinsicInst *DI,
245 const APInt &GapMask) const override;
246
247 bool lowerInterleaveIntrinsicToStore(
248 Instruction *Store, Value *Mask,
249 ArrayRef<Value *> InterleaveValues) const override;
250
251 bool isLegalAddImmediate(int64_t) const override;
252 bool isLegalAddScalableImmediate(int64_t) const override;
253 bool isLegalICmpImmediate(int64_t) const override;
254
255 bool isMulAddWithConstProfitable(SDValue AddNode,
256 SDValue ConstNode) const override;
257
258 bool shouldConsiderGEPOffsetSplit() const override;
259
260 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
261 const AttributeList &FuncAttributes) const override;
262
263 LLT getOptimalMemOpLLT(const MemOp &Op,
264 const AttributeList &FuncAttributes) const override;
265
266 bool findOptimalMemOpLowering(LLVMContext &Context, std::vector<EVT> &MemOps,
267 unsigned Limit, const MemOp &Op, unsigned DstAS,
268 unsigned SrcAS,
269 const AttributeList &FuncAttributes,
270 EVT *LargestVT = nullptr) const override;
271
272 /// Return true if the addressing mode represented by AM is legal for this
273 /// target, for a load/store of the specified type.
274 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
275 unsigned AS,
276 Instruction *I = nullptr) const override;
277
278 int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset,
279 int64_t MaxOffset) const override;
280
281 /// Return true if an FMA operation is faster than a pair of fmul and fadd
282 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
283 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
284 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
285 EVT VT) const override;
286 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
287
288 bool generateFMAsInMachineCombiner(EVT VT,
289 CodeGenOptLevel OptLevel) const override;
290
291 /// Return true if the target has native support for
292 /// the specified value type and it is 'desirable' to use the type for the
293 /// given node type.
294 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
295
296 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
297 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
298
299 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
300 bool isDesirableToCommuteWithShift(const SDNode *N,
301 CombineLevel Level) const override;
302
303 bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override {
304 return false;
305 }
306
307 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
308 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
309
310 /// Return true if it is profitable to fold a pair of shifts into a mask.
311 bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override;
312
313 /// Return true if it is profitable to fold a pair of shifts into a mask.
314 bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override {
315 EVT VT = Y.getValueType();
316
317 if (VT.isVector())
318 return false;
319
320 return VT.getScalarSizeInBits() <= 64;
321 }
322
323 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
324 unsigned SelectOpcode, SDValue X,
325 SDValue Y) const override;
326
327 /// Returns true if it is beneficial to convert a load of a constant
328 /// to just the constant itself.
329 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
330 Type *Ty) const override;
331
332 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
333 /// with this index.
334 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
335 unsigned Index) const override;
336
337 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
338 bool MathUsed) const override {
339 // Using overflow ops for overflow checks only should beneficial on
340 // AArch64.
341 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed: true);
342 }
343
344 // Return true if the target wants to optimize the mul overflow intrinsic
345 // for the given \p VT.
346 bool shouldOptimizeMulOverflowWithZeroHighBits(LLVMContext &Context,
347 EVT VT) const override;
348
349 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
350 AtomicOrdering Ord) const override;
351 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
352 AtomicOrdering Ord) const override;
353
354 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
355
356 bool isOpSuitableForLDPSTP(const Instruction *I) const;
357 bool isOpSuitableForLSE128(const Instruction *I) const;
358 bool isOpSuitableForRCPC3(const Instruction *I) const;
359 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
360 bool shouldInsertTrailingSeqCstFenceForAtomicStore(
361 const Instruction *I) const override;
362
363 TargetLoweringBase::AtomicExpansionKind
364 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
365
366 TargetLoweringBase::AtomicExpansionKind
367 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
368 TargetLoweringBase::AtomicExpansionKind
369 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override;
370
371 TargetLoweringBase::AtomicExpansionKind
372 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
373
374 bool shouldIssueAtomicLoadForAtomicEmulationLoop() const override {
375 return false;
376 }
377
378 bool useLoadStackGuardNode(const Module &M) const override;
379 TargetLoweringBase::LegalizeTypeAction
380 getPreferredVectorAction(MVT VT) const override;
381
382 /// If the target has a standard location for the stack protector cookie,
383 /// returns the address of that location. Otherwise, returns nullptr.
384 Value *getIRStackGuard(IRBuilderBase &IRB,
385 const LibcallLoweringInfo &Libcalls) const override;
386
387 void
388 insertSSPDeclarations(Module &M,
389 const LibcallLoweringInfo &Libcalls) const override;
390
391 /// If the target has a standard location for the unsafe stack pointer,
392 /// returns the address of that location. Otherwise, returns nullptr.
393 Value *getSafeStackPointerLocation(
394 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const override;
395
396 /// If a physical register, this returns the register that receives the
397 /// exception address on entry to an EH pad.
398 Register
399 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
400
401 /// If a physical register, this returns the register that receives the
402 /// exception typeid on entry to a landing pad.
403 Register
404 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
405
406 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
407
408 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
409 const MachineFunction &MF) const override;
410
411 bool isCheapToSpeculateCttz(Type *) const override {
412 return true;
413 }
414
415 bool isCheapToSpeculateCtlz(Type *) const override {
416 return true;
417 }
418
419 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
420
421 bool hasAndNotCompare(SDValue V) const override {
422 // We can use bics for any scalar.
423 return V.getValueType().isScalarInteger();
424 }
425
426 bool hasAndNot(SDValue Y) const override {
427 EVT VT = Y.getValueType();
428
429 if (!VT.isVector())
430 return hasAndNotCompare(V: Y);
431
432 if (VT.isScalableVector())
433 return true;
434
435 return VT.getFixedSizeInBits() >= 64; // vector 'bic'
436 }
437
438 bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
439 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
440 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
441 SelectionDAG &DAG) const override;
442
443 ShiftLegalizationStrategy
444 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
445 unsigned ExpansionFactor) const override;
446
447 CondMergingParams
448 getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
449 const Value *Rhs) const override;
450
451 bool shouldTransformSignedTruncationCheck(EVT XVT,
452 unsigned KeptBits) const override {
453 // For vectors, we don't have a preference..
454 if (XVT.isVector())
455 return false;
456
457 auto VTIsOk = [](EVT VT) -> bool {
458 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
459 VT == MVT::i64;
460 };
461
462 // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
463 // XVT will be larger than KeptBitsVT.
464 MVT KeptBitsVT = MVT::getIntegerVT(BitWidth: KeptBits);
465 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
466 }
467
468 bool preferIncOfAddToSubOfNot(EVT VT) const override;
469
470 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
471
472 bool preferSelectsOverBooleanArithmetic(EVT VT) const override;
473
474 bool isComplexDeinterleavingSupported() const override;
475 bool isComplexDeinterleavingOperationSupported(
476 ComplexDeinterleavingOperation Operation, Type *Ty) const override;
477
478 Value *createComplexDeinterleavingIR(
479 IRBuilderBase &B, ComplexDeinterleavingOperation OperationType,
480 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
481 Value *Accumulator = nullptr) const override;
482
483 bool supportSplitCSR(MachineFunction *MF) const override {
484 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
485 MF->getFunction().hasFnAttribute(Kind: Attribute::NoUnwind);
486 }
487 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
488 void insertCopiesSplitCSR(
489 MachineBasicBlock *Entry,
490 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
491
492 bool supportSwiftError() const override {
493 return true;
494 }
495
496 bool supportPtrAuthBundles() const override { return true; }
497
498 bool supportKCFIBundles() const override { return true; }
499
500 MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
501 MachineBasicBlock::instr_iterator &MBBI,
502 const TargetInstrInfo *TII) const override;
503
504 bool shallExtractConstSplatVectorElementToStore(
505 Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const override;
506
507 /// Enable aggressive FMA fusion on targets that want it.
508 bool enableAggressiveFMAFusion(EVT VT) const override;
509
510 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override {
511 return true;
512 }
513
514 /// Returns the size of the platform's va_list object.
515 unsigned getVaListSizeInBits(const DataLayout &DL) const override;
516
517 /// Returns true if \p VecTy is a legal interleaved access type. This
518 /// function checks the vector element type and the overall width of the
519 /// vector.
520 bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL,
521 bool &UseScalable) const;
522
523 /// Returns the number of interleaved accesses that will be generated when
524 /// lowering accesses of the given type.
525 unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
526 bool UseScalable) const;
527
528 MachineMemOperand::Flags getTargetMMOFlags(
529 const Instruction &I) const override;
530
531 bool functionArgumentNeedsConsecutiveRegisters(
532 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
533 const DataLayout &DL) const override;
534
535 /// Used for exception handling on Win64.
536 bool needsFixedCatchObjects() const override;
537
538 bool fallBackToDAGISel(const Instruction &Inst) const override;
539
540 /// SVE code generation for fixed length vectors does not custom lower
541 /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
542 /// merge. However, merging them creates a BUILD_VECTOR that is just as
543 /// illegal as the original, thus leading to an infinite legalisation loop.
544 /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
545 /// vector types this override can be removed.
546 bool mergeStoresAfterLegalization(EVT VT) const override;
547
548 // If the platform/function should have a redzone, return the size in bytes.
549 unsigned getRedZoneSize(const Function &F) const {
550 if (F.hasFnAttribute(Kind: Attribute::NoRedZone))
551 return 0;
552 return 128;
553 }
554
555 bool isAllActivePredicate(const SelectionDAG &DAG, SDValue N) const;
556 EVT getPromotedVTForPredicate(EVT VT) const;
557
558 EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty,
559 bool AllowUnknown = false) const override;
560
561 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
562
563 bool shouldExpandCttzElements(EVT VT) const override;
564
565 bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const override;
566
567 /// If a change in streaming mode is required on entry to/return from a
568 /// function call it emits and returns the corresponding SMSTART or SMSTOP
569 /// node. \p Condition should be one of the enum values from
570 /// AArch64SME::ToggleCondition.
571 SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable,
572 SDValue Chain, SDValue InGlue, unsigned Condition,
573 bool InsertVectorLengthCheck = false) const;
574
575 /// Returns true if \p RdxOp should be lowered to a SVE reduction. If a SVE2
576 /// pairwise operation can be used for the reduction \p PairwiseOpIID is set
577 /// to its intrinsic ID.
578 bool
579 shouldLowerReductionToSVE(SDValue RdxOp,
580 std::optional<Intrinsic::ID> &PairwiseOpIID) const;
581
582 // Normally SVE is only used for byte size vectors that do not fit within a
583 // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
584 // used for 64bit and 128bit vectors as well.
585 bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
586
587 // Follow NEON ABI rules even when using SVE for fixed length vectors.
588 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
589 EVT VT) const override;
590 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
591 CallingConv::ID CC,
592 EVT VT) const override;
593 unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
594 CallingConv::ID CC, EVT VT,
595 EVT &IntermediateVT,
596 unsigned &NumIntermediates,
597 MVT &RegisterVT) const override;
598
599 /// True if stack clash protection is enabled for this functions.
600 bool hasInlineStackProbe(const MachineFunction &MF) const override;
601
602 /// In AArch64, true if FEAT_CPA is present. Allows pointer arithmetic
603 /// semantics to be preserved for instruction selection.
604 bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override;
605
606 // Match a register name (e.g. "x5", "d5", "sp") to its register number, with
607 // no validity filtering. This is the single entry point for the generated
608 // register-name matcher, shared with getRegisterByName.
609 Register matchRegisterName(StringRef RegName) const;
610
611private:
612 /// Keep a pointer to the AArch64Subtarget around so that we can
613 /// make the right decision when generating code for different targets.
614 const AArch64Subtarget *Subtarget;
615
616 bool isExtFreeImpl(const Instruction *Ext) const override;
617
618 void addTypeForNEON(MVT VT);
619 void addTypeForFixedLengthSVE(MVT VT);
620 void addDRType(MVT VT);
621 void addQRType(MVT VT);
622
623 bool shouldExpandBuildVectorWithShuffles(EVT, unsigned) const override;
624
625 SDValue lowerEHPadEntry(SDValue Chain, SDLoc const &DL,
626 SelectionDAG &DAG) const override;
627
628 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
629 bool isVarArg,
630 const SmallVectorImpl<ISD::InputArg> &Ins,
631 const SDLoc &DL, SelectionDAG &DAG,
632 SmallVectorImpl<SDValue> &InVals) const override;
633
634 void AdjustInstrPostInstrSelection(MachineInstr &MI,
635 SDNode *Node) const override;
636
637 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
638 SmallVectorImpl<SDValue> &InVals) const override;
639
640 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
641 CallingConv::ID CallConv, bool isVarArg,
642 const SmallVectorImpl<CCValAssign> &RVLocs,
643 const SDLoc &DL, SelectionDAG &DAG,
644 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
645 SDValue ThisVal, bool RequiresSMChange) const;
646
647 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
648 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
649 SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
650 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
651 SDValue LowerFMUL(SDValue Op, SelectionDAG &DAG) const;
652 SDValue LowerFMA(SDValue Op, SelectionDAG &DAG) const;
653 SDValue LowerCLMUL(SDValue Op, SelectionDAG &DAG) const;
654
655 SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
656 SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
657
658 SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
659
660 SDValue LowerVECTOR_COMPRESS(SDValue Op, SelectionDAG &DAG) const;
661
662 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
663 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
664 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
665
666 bool
667 isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
668
669 /// Finds the incoming stack arguments which overlap the given fixed stack
670 /// object and incorporates their load into the current chain. This prevents
671 /// an upcoming store from clobbering the stack argument before it's used.
672 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
673 MachineFrameInfo &MFI, int ClobberedFI) const;
674
675 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
676
677 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
678 SDValue &Chain) const;
679
680 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
681 bool isVarArg,
682 const SmallVectorImpl<ISD::OutputArg> &Outs,
683 LLVMContext &Context, const Type *RetTy) const override;
684
685 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
686 const SmallVectorImpl<ISD::OutputArg> &Outs,
687 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
688 SelectionDAG &DAG) const override;
689
690 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
691 unsigned Flag) const;
692 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
693 unsigned Flag) const;
694 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
695 unsigned Flag) const;
696 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
697 unsigned Flag) const;
698 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
699 unsigned Flag) const;
700 template <class NodeTy>
701 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
702 template <class NodeTy>
703 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
704 template <class NodeTy>
705 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
706 template <class NodeTy>
707 SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
708 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
709 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
710 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
711 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
712 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
713 SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
714 const SDLoc &DL, SelectionDAG &DAG) const;
715 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
716 SelectionDAG &DAG) const;
717 SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
718 SDValue LowerPtrAuthGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
719 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
720 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
721 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
722 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
723 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
724 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
725 SDValue TVal, SDValue FVal,
726 iterator_range<SDNode::user_iterator> Users,
727 SDNodeFlags Flags, const SDLoc &dl,
728 SelectionDAG &DAG) const;
729 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
730 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
731 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
732 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
733 SDValue LowerBRIND(SDValue Op, SelectionDAG &DAG) const;
734 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
735 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
736 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
741 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
743 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
744 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
745 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
746 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
747 SDValue LowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
748 SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
749 SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
750 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
751 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
752 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
753 SDValue LowerEXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
754 SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
755 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
757 SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
759 unsigned NewOp) const;
760 SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
762 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
763 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
765 SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerVECTOR_HISTOGRAM(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerPARTIAL_REDUCE_MLA(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerGET_ACTIVE_LANE_MASK(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
774 SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const;
775 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
776 SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerVectorXRINT(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerLOOP_DEPENDENCE_MASK(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerVECREDUCE_MUL(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerMSTORE(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerFCANONICALIZE(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const;
804
805 SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
806 SelectionDAG &DAG) const;
807 SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
808 SelectionDAG &DAG) const;
809 SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
812 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
813 SDValue LowerReductionToSVE(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
818 SelectionDAG &DAG) const;
819 SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
820 SelectionDAG &DAG) const;
821 SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
825 SelectionDAG &DAG) const;
826 SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
831 SelectionDAG &DAG) const;
832 SDValue LowerFixedLengthBuildVectorToSVE(SDValue Op, SelectionDAG &DAG) const;
833 SDValue LowerFixedLengthVectorCompressToSVE(SDValue Op,
834 SelectionDAG &DAG) const;
835
836 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
837 SmallVectorImpl<SDNode *> &Created) const override;
838 SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
839 SmallVectorImpl<SDNode *> &Created) const override;
840 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
841 int &ExtraSteps, bool &UseOneConst,
842 bool Reciprocal) const override;
843 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
844 int &ExtraSteps) const override;
845 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
846 const DenormalMode &Mode,
847 SDNodeFlags Flags = {}) const override;
848 SDValue getSqrtResultForDenormInput(SDValue Operand,
849 SelectionDAG &DAG) const override;
850 unsigned combineRepeatedFPDivisors() const override;
851
852 ConstraintType getConstraintType(StringRef Constraint) const override;
853 Register getRegisterByName(const char* RegName, LLT VT,
854 const MachineFunction &MF) const override;
855
856private:
857 /// Examine constraint string and operand type and determine a weight value.
858 /// The operand object must already have been set up with the operand type.
859 ConstraintWeight
860 getSingleConstraintMatchWeight(AsmOperandInfo &info,
861 const char *constraint) const override;
862
863 std::pair<unsigned, const TargetRegisterClass *>
864 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
865 StringRef Constraint, MVT VT) const override;
866
867 const char *LowerXConstraint(EVT ConstraintVT) const override;
868
869 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
870 std::vector<SDValue> &Ops,
871 SelectionDAG &DAG) const override;
872
873 InlineAsm::ConstraintCode
874 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
875 if (ConstraintCode == "Q")
876 return InlineAsm::ConstraintCode::Q;
877 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
878 // followed by llvm_unreachable so we'll leave them unimplemented in
879 // the backend for now.
880 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
881 }
882
883 /// Handle Lowering flag assembly outputs.
884 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
885 const SDLoc &DL,
886 const AsmOperandInfo &Constraint,
887 SelectionDAG &DAG) const override;
888
889 bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
890 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
891 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
892 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
893 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
894 bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
895 SDValue &Offset, SelectionDAG &DAG) const;
896 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
897 ISD::MemIndexedMode &AM,
898 SelectionDAG &DAG) const override;
899 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
900 SDValue &Offset, ISD::MemIndexedMode &AM,
901 SelectionDAG &DAG) const override;
902 bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
903 bool IsPre, MachineRegisterInfo &MRI) const override;
904
905 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
906 SelectionDAG &DAG) const override;
907 void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
908 SelectionDAG &DAG) const;
909 void ReplaceExtractSubVectorResults(SDNode *N,
910 SmallVectorImpl<SDValue> &Results,
911 SelectionDAG &DAG) const;
912 void ReplaceGetActiveLaneMaskResults(SDNode *N,
913 SmallVectorImpl<SDValue> &Results,
914 SelectionDAG &DAG) const;
915
916 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT, EVT) const override;
917
918 void finalizeLowering(MachineFunction &MF) const override;
919
920 bool shouldLocalize(const MachineInstr &MI,
921 const TargetTransformInfo *TTI) const override;
922
923 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
924 const APInt &OriginalDemandedBits,
925 const APInt &OriginalDemandedElts,
926 KnownBits &Known,
927 TargetLoweringOpt &TLO,
928 unsigned Depth) const override;
929
930 bool canCreateUndefOrPoisonForTargetNode(
931 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
932 UndefPoisonKind Kind, bool ConsiderFlags, unsigned Depth) const override;
933
934 bool isTargetCanonicalConstantNode(SDValue Op) const override;
935
936 // With the exception of data-predicate transitions, no instructions are
937 // required to cast between legal scalable vector types. However:
938 // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
939 // is not universally useable.
940 // 2. Most unpacked integer types are not legal and thus integer extends
941 // cannot be used to convert between unpacked and packed types.
942 // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
943 // to transition between unpacked and packed types of the same element type,
944 // with BITCAST used otherwise.
945 // This function does not handle predicate bitcasts.
946 SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
947
948 // Returns the runtime value for PSTATE.SM by generating a call to
949 // __arm_sme_state.
950 SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
951 EVT VT) const;
952
953 bool preferScalarizeSplat(SDNode *N) const override;
954
955 unsigned getMinimumJumpTableEntries() const override;
956
957 bool shouldScalarizeBinop(SDValue VecOp) const override {
958 return VecOp.getOpcode() == ISD::SETCC;
959 }
960
961 bool hasMultipleConditionRegisters(EVT VT) const override {
962 return VT.isScalableVector();
963 }
964};
965
966namespace AArch64 {
967FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
968 const TargetLibraryInfo *libInfo,
969 const LibcallLoweringInfo *libcallLowering);
970} // end namespace AArch64
971
972} // end namespace llvm
973
974#endif
975