1//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the MRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15
16#define GET_REGINFO_HEADER
17#include "AArch64GenRegisterInfo.inc"
18
19namespace llvm {
20
21class MachineFunction;
22class RegScavenger;
23class MCRegisterClass;
24using TargetRegisterClass = MCRegisterClass;
25class Triple;
26
27class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
28 const Triple &TT;
29
30public:
31 AArch64RegisterInfo(const Triple &TT, unsigned HwMode);
32
33 // FIXME: This should be tablegen'd like getDwarfRegNum is
34 int getSEHRegNum(unsigned i) const {
35 return getEncodingValue(Reg: i);
36 }
37
38 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
39 bool isUserReservedReg(const MachineFunction &MF, MCRegister Reg) const;
40 bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const;
41 bool isAnyArgRegReserved(const MachineFunction &MF) const;
42 void emitReservedArgRegCallError(const MachineFunction &MF) const;
43
44 void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
45 void UpdateCustomCallPreservedMask(MachineFunction &MF,
46 const uint32_t **Mask) const;
47
48 /// Code Generation virtual methods...
49 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
50 const MCPhysReg *
51 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
52 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
53 CallingConv::ID) const override;
54 const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF,
55 CallingConv::ID) const;
56
57 unsigned getCSRCost() const override {
58 // The cost will be compared against BlockFrequency where entry has the
59 // value of 1 << 14. A value of 5 will choose to spill or split really
60 // cold path instead of using a callee-saved register.
61 return 5;
62 }
63 unsigned getCSRFirstUseCost() const override {
64 // The cost of 2 means push and pop for each CSR.
65 return 2;
66 }
67
68 const TargetRegisterClass *
69 getSubClassWithSubReg(const TargetRegisterClass *RC,
70 unsigned Idx) const override;
71
72 // Calls involved in thread-local variable lookup save more registers than
73 // normal calls, so they need a different mask to represent this.
74 const uint32_t *getTLSCallPreservedMask() const;
75
76 const uint32_t *getSMStartStopCallPreservedMask() const;
77 const uint32_t *SMEABISupportRoutinesCallPreservedMaskFromX0() const;
78
79 // Funclets on ARM64 Windows don't preserve any registers.
80 const uint32_t *getNoPreservedMask() const override;
81
82 // Unwinders may not preserve all Neon and SVE registers.
83 const uint32_t *
84 getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
85
86 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
87 /// case that 'returned' is on an i64 first argument if the calling convention
88 /// is one that can (partially) model this attribute with a preserved mask
89 /// (i.e. it is a calling convention that uses the same register for the first
90 /// i64 argument and an i64 return value)
91 ///
92 /// Should return NULL in the case that the calling convention does not have
93 /// this property
94 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
95 CallingConv::ID) const;
96
97 /// Stack probing calls preserve different CSRs to the normal CC.
98 const uint32_t *getWindowsStackProbePreservedMask() const;
99
100 BitVector getStrictlyReservedRegs(const MachineFunction &MF) const;
101 BitVector getUserReservedRegs(const MachineFunction &MF) const;
102 BitVector getReservedRegs(const MachineFunction &MF) const override;
103 std::optional<std::string>
104 explainReservedReg(const MachineFunction &MF,
105 MCRegister PhysReg) const override;
106 bool isAsmClobberable(const MachineFunction &MF,
107 MCRegister PhysReg) const override;
108 const TargetRegisterClass *
109 getPointerRegClass(unsigned Kind = 0) const override;
110 const TargetRegisterClass *
111 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
112
113 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
114 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
115 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
116
117 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
118 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
119 int64_t Offset) const override;
120 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
121 int64_t Offset) const override;
122 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
123 int64_t Offset) const override;
124 bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
125 unsigned FIOperandNum,
126 RegScavenger *RS = nullptr) const override;
127 bool cannotEliminateFrame(const MachineFunction &MF) const;
128
129 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
130 bool hasBasePointer(const MachineFunction &MF) const;
131 MCRegister getBaseRegister() const;
132
133 bool isArgumentRegister(const MachineFunction &MF,
134 MCRegister Reg) const override;
135
136 // Debug information queries.
137 Register getFrameRegister(const MachineFunction &MF) const override;
138
139 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
140 MachineFunction &MF) const override;
141
142 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
143 SmallVectorImpl<MCPhysReg> &Hints,
144 const MachineFunction &MF, const VirtRegMap *VRM,
145 const LiveRegMatrix *Matrix) const override;
146
147 unsigned getLocalAddressRegister(const MachineFunction &MF) const;
148 bool regNeedsCFI(MCRegister Reg, MCRegister &RegToUseForCFI) const;
149
150 /// SrcRC and DstRC will be morphed into NewRC if this returns true
151 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
152 unsigned SubReg, const TargetRegisterClass *DstRC,
153 unsigned DstSubReg, const TargetRegisterClass *NewRC,
154 LiveIntervals &LIS) const override;
155
156 void getOffsetOpcodes(const StackOffset &Offset,
157 SmallVectorImpl<uint64_t> &Ops) const override;
158
159 bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override;
160
161 bool isIgnoredCVReg(MCRegister LLVMReg) const override;
162};
163
164} // end namespace llvm
165
166#endif
167