1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the AArch64 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19// FIXME: Is it easiest to fix this layering violation by moving the .inc
20// #includes from AArch64MCTargetDesc.h to here?
21#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/APSInt.h"
24#include "llvm/ADT/BitmaskEnum.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/TargetParser/SubtargetFeature.h"
29
30namespace llvm {
31
32inline static MCRegister getWRegFromXReg(MCRegister Reg) {
33 switch (Reg.id()) {
34 case AArch64::X0: return AArch64::W0;
35 case AArch64::X1: return AArch64::W1;
36 case AArch64::X2: return AArch64::W2;
37 case AArch64::X3: return AArch64::W3;
38 case AArch64::X4: return AArch64::W4;
39 case AArch64::X5: return AArch64::W5;
40 case AArch64::X6: return AArch64::W6;
41 case AArch64::X7: return AArch64::W7;
42 case AArch64::X8: return AArch64::W8;
43 case AArch64::X9: return AArch64::W9;
44 case AArch64::X10: return AArch64::W10;
45 case AArch64::X11: return AArch64::W11;
46 case AArch64::X12: return AArch64::W12;
47 case AArch64::X13: return AArch64::W13;
48 case AArch64::X14: return AArch64::W14;
49 case AArch64::X15: return AArch64::W15;
50 case AArch64::X16: return AArch64::W16;
51 case AArch64::X17: return AArch64::W17;
52 case AArch64::X18: return AArch64::W18;
53 case AArch64::X19: return AArch64::W19;
54 case AArch64::X20: return AArch64::W20;
55 case AArch64::X21: return AArch64::W21;
56 case AArch64::X22: return AArch64::W22;
57 case AArch64::X23: return AArch64::W23;
58 case AArch64::X24: return AArch64::W24;
59 case AArch64::X25: return AArch64::W25;
60 case AArch64::X26: return AArch64::W26;
61 case AArch64::X27: return AArch64::W27;
62 case AArch64::X28: return AArch64::W28;
63 case AArch64::FP: return AArch64::W29;
64 case AArch64::LR: return AArch64::W30;
65 case AArch64::SP: return AArch64::WSP;
66 case AArch64::XZR: return AArch64::WZR;
67 }
68 // For anything else, return it unchanged.
69 return Reg;
70}
71
72inline static MCRegister getXRegFromWReg(MCRegister Reg) {
73 switch (Reg.id()) {
74 case AArch64::W0: return AArch64::X0;
75 case AArch64::W1: return AArch64::X1;
76 case AArch64::W2: return AArch64::X2;
77 case AArch64::W3: return AArch64::X3;
78 case AArch64::W4: return AArch64::X4;
79 case AArch64::W5: return AArch64::X5;
80 case AArch64::W6: return AArch64::X6;
81 case AArch64::W7: return AArch64::X7;
82 case AArch64::W8: return AArch64::X8;
83 case AArch64::W9: return AArch64::X9;
84 case AArch64::W10: return AArch64::X10;
85 case AArch64::W11: return AArch64::X11;
86 case AArch64::W12: return AArch64::X12;
87 case AArch64::W13: return AArch64::X13;
88 case AArch64::W14: return AArch64::X14;
89 case AArch64::W15: return AArch64::X15;
90 case AArch64::W16: return AArch64::X16;
91 case AArch64::W17: return AArch64::X17;
92 case AArch64::W18: return AArch64::X18;
93 case AArch64::W19: return AArch64::X19;
94 case AArch64::W20: return AArch64::X20;
95 case AArch64::W21: return AArch64::X21;
96 case AArch64::W22: return AArch64::X22;
97 case AArch64::W23: return AArch64::X23;
98 case AArch64::W24: return AArch64::X24;
99 case AArch64::W25: return AArch64::X25;
100 case AArch64::W26: return AArch64::X26;
101 case AArch64::W27: return AArch64::X27;
102 case AArch64::W28: return AArch64::X28;
103 case AArch64::W29: return AArch64::FP;
104 case AArch64::W30: return AArch64::LR;
105 case AArch64::WSP: return AArch64::SP;
106 case AArch64::WZR: return AArch64::XZR;
107 }
108 // For anything else, return it unchanged.
109 return Reg;
110}
111
112inline static MCRegister getXRegFromXRegTuple(MCRegister RegTuple) {
113 switch (RegTuple.id()) {
114 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
115 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
116 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
117 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
118 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
119 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
120 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
121 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
122 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
123 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
124 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
125 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
126 }
127 // For anything else, return it unchanged.
128 return RegTuple;
129}
130
131static inline MCRegister getBRegFromDReg(MCRegister Reg) {
132 switch (Reg.id()) {
133 case AArch64::D0: return AArch64::B0;
134 case AArch64::D1: return AArch64::B1;
135 case AArch64::D2: return AArch64::B2;
136 case AArch64::D3: return AArch64::B3;
137 case AArch64::D4: return AArch64::B4;
138 case AArch64::D5: return AArch64::B5;
139 case AArch64::D6: return AArch64::B6;
140 case AArch64::D7: return AArch64::B7;
141 case AArch64::D8: return AArch64::B8;
142 case AArch64::D9: return AArch64::B9;
143 case AArch64::D10: return AArch64::B10;
144 case AArch64::D11: return AArch64::B11;
145 case AArch64::D12: return AArch64::B12;
146 case AArch64::D13: return AArch64::B13;
147 case AArch64::D14: return AArch64::B14;
148 case AArch64::D15: return AArch64::B15;
149 case AArch64::D16: return AArch64::B16;
150 case AArch64::D17: return AArch64::B17;
151 case AArch64::D18: return AArch64::B18;
152 case AArch64::D19: return AArch64::B19;
153 case AArch64::D20: return AArch64::B20;
154 case AArch64::D21: return AArch64::B21;
155 case AArch64::D22: return AArch64::B22;
156 case AArch64::D23: return AArch64::B23;
157 case AArch64::D24: return AArch64::B24;
158 case AArch64::D25: return AArch64::B25;
159 case AArch64::D26: return AArch64::B26;
160 case AArch64::D27: return AArch64::B27;
161 case AArch64::D28: return AArch64::B28;
162 case AArch64::D29: return AArch64::B29;
163 case AArch64::D30: return AArch64::B30;
164 case AArch64::D31: return AArch64::B31;
165 }
166 // For anything else, return it unchanged.
167 return Reg;
168}
169
170static inline MCRegister getDRegFromBReg(MCRegister Reg) {
171 switch (Reg.id()) {
172 case AArch64::B0: return AArch64::D0;
173 case AArch64::B1: return AArch64::D1;
174 case AArch64::B2: return AArch64::D2;
175 case AArch64::B3: return AArch64::D3;
176 case AArch64::B4: return AArch64::D4;
177 case AArch64::B5: return AArch64::D5;
178 case AArch64::B6: return AArch64::D6;
179 case AArch64::B7: return AArch64::D7;
180 case AArch64::B8: return AArch64::D8;
181 case AArch64::B9: return AArch64::D9;
182 case AArch64::B10: return AArch64::D10;
183 case AArch64::B11: return AArch64::D11;
184 case AArch64::B12: return AArch64::D12;
185 case AArch64::B13: return AArch64::D13;
186 case AArch64::B14: return AArch64::D14;
187 case AArch64::B15: return AArch64::D15;
188 case AArch64::B16: return AArch64::D16;
189 case AArch64::B17: return AArch64::D17;
190 case AArch64::B18: return AArch64::D18;
191 case AArch64::B19: return AArch64::D19;
192 case AArch64::B20: return AArch64::D20;
193 case AArch64::B21: return AArch64::D21;
194 case AArch64::B22: return AArch64::D22;
195 case AArch64::B23: return AArch64::D23;
196 case AArch64::B24: return AArch64::D24;
197 case AArch64::B25: return AArch64::D25;
198 case AArch64::B26: return AArch64::D26;
199 case AArch64::B27: return AArch64::D27;
200 case AArch64::B28: return AArch64::D28;
201 case AArch64::B29: return AArch64::D29;
202 case AArch64::B30: return AArch64::D30;
203 case AArch64::B31: return AArch64::D31;
204 }
205 // For anything else, return it unchanged.
206 return Reg;
207}
208
209static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
210 switch (Opcode) {
211 case AArch64::LDADDAB: case AArch64::LDADDAH:
212 case AArch64::LDADDAW: case AArch64::LDADDAX:
213 case AArch64::LDADDALB: case AArch64::LDADDALH:
214 case AArch64::LDADDALW: case AArch64::LDADDALX:
215 case AArch64::LDCLRAB: case AArch64::LDCLRAH:
216 case AArch64::LDCLRAW: case AArch64::LDCLRAX:
217 case AArch64::LDCLRALB: case AArch64::LDCLRALH:
218 case AArch64::LDCLRALW: case AArch64::LDCLRALX:
219 case AArch64::LDEORAB: case AArch64::LDEORAH:
220 case AArch64::LDEORAW: case AArch64::LDEORAX:
221 case AArch64::LDEORALB: case AArch64::LDEORALH:
222 case AArch64::LDEORALW: case AArch64::LDEORALX:
223 case AArch64::LDSETAB: case AArch64::LDSETAH:
224 case AArch64::LDSETAW: case AArch64::LDSETAX:
225 case AArch64::LDSETALB: case AArch64::LDSETALH:
226 case AArch64::LDSETALW: case AArch64::LDSETALX:
227 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
228 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
229 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
230 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
231 case AArch64::LDSMINAB: case AArch64::LDSMINAH:
232 case AArch64::LDSMINAW: case AArch64::LDSMINAX:
233 case AArch64::LDSMINALB: case AArch64::LDSMINALH:
234 case AArch64::LDSMINALW: case AArch64::LDSMINALX:
235 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
236 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
237 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
238 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
239 case AArch64::LDUMINAB: case AArch64::LDUMINAH:
240 case AArch64::LDUMINAW: case AArch64::LDUMINAX:
241 case AArch64::LDUMINALB: case AArch64::LDUMINALH:
242 case AArch64::LDUMINALW: case AArch64::LDUMINALX:
243 case AArch64::SWPAB: case AArch64::SWPAH:
244 case AArch64::SWPAW: case AArch64::SWPAX:
245 case AArch64::SWPALB: case AArch64::SWPALH:
246 case AArch64::SWPALW: case AArch64::SWPALX:
247 return true;
248 }
249 return false;
250}
251
252inline unsigned CheckFixedPointOperandConstant(APFloat &FVal, unsigned RegWidth,
253 bool isReciprocal) {
254 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
255 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
256 // x-register.
257 //
258 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
259 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
260 // integers.
261 bool IsExact;
262
263 if (isReciprocal)
264 if (!FVal.getExactInverse(Inv: &FVal))
265 return 0;
266
267 // fbits is between 1 and 64 in the worst-case, which means the fmul
268 // could have 2^64 as an actual operand. Need 65 bits of precision.
269 APSInt IntVal(65, true);
270 FVal.convertToInteger(Result&: IntVal, RM: APFloat::rmTowardZero, IsExact: &IsExact);
271
272 // N.b. isPowerOf2 also checks for > 0.
273 if (!IsExact || !IntVal.isPowerOf2())
274 return 0;
275 unsigned FBits = IntVal.logBase2();
276
277 // Checks above should have guaranteed that we haven't lost information in
278 // finding FBits, but it must still be in range.
279 if (FBits == 0 || FBits > RegWidth)
280 return 0;
281 return FBits;
282}
283
284namespace AArch64CC {
285
286// The CondCodes constants map directly to the 4-bit encoding of the condition
287// field for predicated instructions.
288enum CondCode { // Meaning (integer) Meaning (floating-point)
289 EQ = 0x0, // Equal Equal
290 NE = 0x1, // Not equal Not equal, or unordered
291 HS = 0x2, // Unsigned higher or same >, ==, or unordered
292 LO = 0x3, // Unsigned lower Less than
293 MI = 0x4, // Minus, negative Less than
294 PL = 0x5, // Plus, positive or zero >, ==, or unordered
295 VS = 0x6, // Overflow Unordered
296 VC = 0x7, // No overflow Not unordered
297 HI = 0x8, // Unsigned higher Greater than, or unordered
298 LS = 0x9, // Unsigned lower or same Less than or equal
299 GE = 0xa, // Greater than or equal Greater than or equal
300 LT = 0xb, // Less than Less than, or unordered
301 GT = 0xc, // Greater than Greater than
302 LE = 0xd, // Less than or equal <, ==, or unordered
303 AL = 0xe, // Always (unconditional) Always (unconditional)
304 NV = 0xf, // Always (unconditional) Always (unconditional)
305 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
306 Invalid,
307
308 // Common aliases used for SVE.
309 ANY_ACTIVE = NE, // (!Z)
310 FIRST_ACTIVE = MI, // ( N)
311 LAST_ACTIVE = LO, // (!C)
312 NONE_ACTIVE = EQ // ( Z)
313};
314
315inline static const char *getCondCodeName(CondCode Code) {
316 switch (Code) {
317 default: llvm_unreachable("Unknown condition code");
318 case EQ: return "eq";
319 case NE: return "ne";
320 case HS: return "hs";
321 case LO: return "lo";
322 case MI: return "mi";
323 case PL: return "pl";
324 case VS: return "vs";
325 case VC: return "vc";
326 case HI: return "hi";
327 case LS: return "ls";
328 case GE: return "ge";
329 case LT: return "lt";
330 case GT: return "gt";
331 case LE: return "le";
332 case AL: return "al";
333 case NV: return "nv";
334 }
335}
336
337inline static CondCode getInvertedCondCode(CondCode Code) {
338 // To reverse a condition it's necessary to only invert the low bit:
339
340 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
341}
342
343/// getSwappedCondition - assume the flags are set by MI(a,b), return
344/// the condition code if we modify the instructions such that flags are
345/// set by MI(b,a).
346inline static CondCode getSwappedCondition(CondCode CC) {
347 switch (CC) {
348 default:
349 return AL;
350 case EQ:
351 return EQ;
352 case NE:
353 return NE;
354 case HS:
355 return LS;
356 case LO:
357 return HI;
358 case HI:
359 return LO;
360 case LS:
361 return HS;
362 case GE:
363 return LE;
364 case LT:
365 return GT;
366 case GT:
367 return LT;
368 case LE:
369 return GE;
370 }
371}
372
373/// Given a condition code, return NZCV flags that would satisfy that condition.
374/// The flag bits are in the format expected by the ccmp instructions.
375/// Note that many different flag settings can satisfy a given condition code,
376/// this function just returns one of them.
377inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
378 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
379 enum { N = 8, Z = 4, C = 2, V = 1 };
380 switch (Code) {
381 default: llvm_unreachable("Unknown condition code");
382 case EQ: return Z; // Z == 1
383 case NE: return 0; // Z == 0
384 case HS: return C; // C == 1
385 case LO: return 0; // C == 0
386 case MI: return N; // N == 1
387 case PL: return 0; // N == 0
388 case VS: return V; // V == 1
389 case VC: return 0; // V == 0
390 case HI: return C; // C == 1 && Z == 0
391 case LS: return 0; // C == 0 || Z == 1
392 case GE: return 0; // N == V
393 case LT: return N; // N != V
394 case GT: return 0; // Z == 0 && N == V
395 case LE: return Z; // Z == 1 || N != V
396 }
397}
398
399/// True, if a given condition code can be used in a fused compare-and-branch
400/// instructions, false otherwise.
401inline static bool isValidCBCond(AArch64CC::CondCode Code) {
402 switch (Code) {
403 default:
404 return false;
405 case AArch64CC::EQ:
406 case AArch64CC::NE:
407 case AArch64CC::HS:
408 case AArch64CC::LO:
409 case AArch64CC::HI:
410 case AArch64CC::LS:
411 case AArch64CC::GE:
412 case AArch64CC::LT:
413 case AArch64CC::GT:
414 case AArch64CC::LE:
415 return true;
416 }
417}
418
419} // end namespace AArch64CC
420
421struct SysAlias {
422 const char *Name;
423 uint16_t Encoding;
424 FeatureBitset FeaturesRequired;
425
426 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
427 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
428 : Name(N), Encoding(E), FeaturesRequired(F) {}
429
430 bool haveFeatures(FeatureBitset ActiveFeatures) const {
431 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
432 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
433 }
434
435 FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
436};
437
438struct SysAliasReg : SysAlias {
439 bool NeedsReg;
440 constexpr SysAliasReg(const char *N, uint16_t E, bool R)
441 : SysAlias(N, E), NeedsReg(R) {}
442 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
443 : SysAlias(N, E, F), NeedsReg(R) {}
444};
445
446struct SysAliasOptionalReg : SysAlias {
447 bool NeedsReg;
448 bool OptionalReg;
449 constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
450 : SysAlias(N, E), NeedsReg(R), OptionalReg(O) {}
451 constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O,
452 FeatureBitset F)
453 : SysAlias(N, E, F), NeedsReg(R), OptionalReg(O) {}
454};
455
456struct SysAliasImm : SysAlias {
457 uint16_t ImmValue;
458 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
459 : SysAlias(N, E), ImmValue(I) {}
460 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
461 : SysAlias(N, E, F), ImmValue(I) {}
462};
463
464namespace AArch64SVCR {
465 struct SVCR : SysAlias{
466 using SysAlias::SysAlias;
467 };
468#define GET_SVCRValues_DECL
469#define GET_SVCRsList_DECL
470#include "AArch64GenSystemOperands.inc"
471}
472
473namespace AArch64AT{
474 struct AT : SysAlias {
475 using SysAlias::SysAlias;
476 };
477#define GET_ATValues_DECL
478#define GET_ATsList_DECL
479#include "AArch64GenSystemOperands.inc"
480}
481
482namespace AArch64DB {
483 struct DB : SysAlias {
484 using SysAlias::SysAlias;
485 };
486#define GET_DBValues_DECL
487#define GET_DBsList_DECL
488#include "AArch64GenSystemOperands.inc"
489}
490
491namespace AArch64DBnXS {
492 struct DBnXS : SysAliasImm {
493 using SysAliasImm::SysAliasImm;
494 };
495#define GET_DBnXSValues_DECL
496#define GET_DBnXSsList_DECL
497#include "AArch64GenSystemOperands.inc"
498}
499
500namespace AArch64DC {
501 struct DC : SysAlias {
502 using SysAlias::SysAlias;
503 };
504#define GET_DCValues_DECL
505#define GET_DCsList_DECL
506#include "AArch64GenSystemOperands.inc"
507}
508
509namespace AArch64IC {
510 struct IC : SysAliasReg {
511 using SysAliasReg::SysAliasReg;
512 };
513#define GET_ICValues_DECL
514#define GET_ICsList_DECL
515#include "AArch64GenSystemOperands.inc"
516}
517
518namespace AArch64ISB {
519 struct ISB : SysAlias {
520 using SysAlias::SysAlias;
521 };
522#define GET_ISBValues_DECL
523#define GET_ISBsList_DECL
524#include "AArch64GenSystemOperands.inc"
525}
526
527namespace AArch64TSB {
528 struct TSB : SysAlias {
529 using SysAlias::SysAlias;
530 };
531#define GET_TSBValues_DECL
532#define GET_TSBsList_DECL
533#include "AArch64GenSystemOperands.inc"
534}
535
536namespace AArch64PRFM {
537 struct PRFM : SysAlias {
538 using SysAlias::SysAlias;
539 };
540#define GET_PRFMValues_DECL
541#define GET_PRFMsList_DECL
542#include "AArch64GenSystemOperands.inc"
543}
544
545namespace AArch64SVEPRFM {
546 struct SVEPRFM : SysAlias {
547 using SysAlias::SysAlias;
548 };
549#define GET_SVEPRFMValues_DECL
550#define GET_SVEPRFMsList_DECL
551#include "AArch64GenSystemOperands.inc"
552}
553
554namespace AArch64RPRFM {
555struct RPRFM : SysAlias {
556 using SysAlias::SysAlias;
557};
558#define GET_RPRFMValues_DECL
559#define GET_RPRFMsList_DECL
560#include "AArch64GenSystemOperands.inc"
561} // namespace AArch64RPRFM
562
563namespace AArch64SVEPredPattern {
564 struct SVEPREDPAT {
565 const char *Name;
566 uint16_t Encoding;
567 };
568#define GET_SVEPREDPATValues_DECL
569#define GET_SVEPREDPATsList_DECL
570#include "AArch64GenSystemOperands.inc"
571}
572
573namespace AArch64SVEVecLenSpecifier {
574 struct SVEVECLENSPECIFIER {
575 const char *Name;
576 uint16_t Encoding;
577 };
578#define GET_SVEVECLENSPECIFIERValues_DECL
579#define GET_SVEVECLENSPECIFIERsList_DECL
580#include "AArch64GenSystemOperands.inc"
581} // namespace AArch64SVEVecLenSpecifier
582
583/// Return the number of active elements for VL1 to VL256 predicate pattern,
584/// zero for all other patterns.
585inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
586 switch (Pattern) {
587 default:
588 return 0;
589 case AArch64SVEPredPattern::vl1:
590 case AArch64SVEPredPattern::vl2:
591 case AArch64SVEPredPattern::vl3:
592 case AArch64SVEPredPattern::vl4:
593 case AArch64SVEPredPattern::vl5:
594 case AArch64SVEPredPattern::vl6:
595 case AArch64SVEPredPattern::vl7:
596 case AArch64SVEPredPattern::vl8:
597 return Pattern;
598 case AArch64SVEPredPattern::vl16:
599 return 16;
600 case AArch64SVEPredPattern::vl32:
601 return 32;
602 case AArch64SVEPredPattern::vl64:
603 return 64;
604 case AArch64SVEPredPattern::vl128:
605 return 128;
606 case AArch64SVEPredPattern::vl256:
607 return 256;
608 }
609}
610
611/// Return specific VL predicate pattern based on the number of elements.
612inline std::optional<unsigned>
613getSVEPredPatternFromNumElements(unsigned MinNumElts) {
614 switch (MinNumElts) {
615 default:
616 return std::nullopt;
617 case 1:
618 case 2:
619 case 3:
620 case 4:
621 case 5:
622 case 6:
623 case 7:
624 case 8:
625 return MinNumElts;
626 case 16:
627 return AArch64SVEPredPattern::vl16;
628 case 32:
629 return AArch64SVEPredPattern::vl32;
630 case 64:
631 return AArch64SVEPredPattern::vl64;
632 case 128:
633 return AArch64SVEPredPattern::vl128;
634 case 256:
635 return AArch64SVEPredPattern::vl256;
636 }
637}
638
639/// An enum to describe what types of loops we should attempt to tail-fold:
640/// Disabled: None
641/// Reductions: Loops containing reductions
642/// Recurrences: Loops with first-order recurrences, i.e. that would
643/// require a SVE splice instruction
644/// Reverse: Reverse loops
645/// Simple: Loops that are not reversed and don't contain reductions
646/// or first-order recurrences.
647/// All: All
648enum class TailFoldingOpts : uint8_t {
649 Disabled = 0x00,
650 Simple = 0x01,
651 Reductions = 0x02,
652 Recurrences = 0x04,
653 Reverse = 0x08,
654 All = Reductions | Recurrences | Simple | Reverse
655};
656
657LLVM_DECLARE_ENUM_AS_BITMASK(TailFoldingOpts,
658 /* LargestValue */ (long)TailFoldingOpts::Reverse);
659
660namespace AArch64ExactFPImm {
661struct ExactFPImm {
662 int Enum;
663 const char *Repr;
664};
665#define GET_ExactFPImmValues_DECL
666#define GET_ExactFPImmsList_DECL
667#include "AArch64GenSystemOperands.inc"
668}
669
670namespace AArch64PState {
671 struct PStateImm0_15 : SysAlias{
672 using SysAlias::SysAlias;
673 };
674#define GET_PStateImm0_15Values_DECL
675#define GET_PStateImm0_15sList_DECL
676#include "AArch64GenSystemOperands.inc"
677
678 struct PStateImm0_1 : SysAlias{
679 using SysAlias::SysAlias;
680 };
681#define GET_PStateImm0_1Values_DECL
682#define GET_PStateImm0_1sList_DECL
683#include "AArch64GenSystemOperands.inc"
684}
685
686namespace AArch64PSBHint {
687 struct PSB : SysAlias {
688 using SysAlias::SysAlias;
689 };
690#define GET_PSBValues_DECL
691#define GET_PSBsList_DECL
692#include "AArch64GenSystemOperands.inc"
693}
694
695namespace AArch64PHint {
696struct PHint {
697 const char *Name;
698 unsigned Encoding;
699 FeatureBitset FeaturesRequired;
700
701 bool haveFeatures(FeatureBitset ActiveFeatures) const {
702 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
703 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
704 }
705};
706
707#define GET_PHintValues_DECL
708#define GET_PHintsList_DECL
709#include "AArch64GenSystemOperands.inc"
710
711const PHint *lookupPHintByName(StringRef);
712const PHint *lookupPHintByEncoding(uint16_t);
713} // namespace AArch64PHint
714
715namespace AArch64BTIHint {
716 struct BTI : SysAlias {
717 using SysAlias::SysAlias;
718 };
719#define GET_BTIValues_DECL
720#define GET_BTIsList_DECL
721#include "AArch64GenSystemOperands.inc"
722}
723
724namespace AArch64CMHPriorityHint {
725struct CMHPriorityHint : SysAlias {
726 using SysAlias::SysAlias;
727};
728#define GET_CMHPRIORITYHINT_DECL
729#include "AArch64GenSystemOperands.inc"
730} // namespace AArch64CMHPriorityHint
731
732namespace AArch64TIndexHint {
733struct TIndex : SysAlias {
734 using SysAlias::SysAlias;
735};
736#define GET_TINDEX_DECL
737#include "AArch64GenSystemOperands.inc"
738} // namespace AArch64TIndexHint
739
740namespace AArch64SME {
741enum ToggleCondition : unsigned {
742 Always,
743 IfCallerIsStreaming,
744 IfCallerIsNonStreaming
745};
746}
747
748namespace AArch64SE {
749 enum ShiftExtSpecifiers {
750 Invalid = -1,
751 LSL,
752 MSL,
753 LSR,
754 ASR,
755 ROR,
756
757 UXTB,
758 UXTH,
759 UXTW,
760 UXTX,
761
762 SXTB,
763 SXTH,
764 SXTW,
765 SXTX
766 };
767}
768
769namespace AArch64Layout {
770 enum VectorLayout {
771 Invalid = -1,
772 VL_8B,
773 VL_4H,
774 VL_2S,
775 VL_1D,
776
777 VL_16B,
778 VL_8H,
779 VL_4S,
780 VL_2D,
781
782 // Bare layout for the 128-bit vector
783 // (only show ".b", ".h", ".s", ".d" without vector number)
784 VL_B,
785 VL_H,
786 VL_S,
787 VL_D
788 };
789}
790
791inline static const char *
792AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
793 switch (Layout) {
794 case AArch64Layout::VL_8B: return ".8b";
795 case AArch64Layout::VL_4H: return ".4h";
796 case AArch64Layout::VL_2S: return ".2s";
797 case AArch64Layout::VL_1D: return ".1d";
798 case AArch64Layout::VL_16B: return ".16b";
799 case AArch64Layout::VL_8H: return ".8h";
800 case AArch64Layout::VL_4S: return ".4s";
801 case AArch64Layout::VL_2D: return ".2d";
802 case AArch64Layout::VL_B: return ".b";
803 case AArch64Layout::VL_H: return ".h";
804 case AArch64Layout::VL_S: return ".s";
805 case AArch64Layout::VL_D: return ".d";
806 default: llvm_unreachable("Unknown Vector Layout");
807 }
808}
809
810inline static AArch64Layout::VectorLayout
811AArch64StringToVectorLayout(StringRef LayoutStr) {
812 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
813 .Case(S: ".8b", Value: AArch64Layout::VL_8B)
814 .Case(S: ".4h", Value: AArch64Layout::VL_4H)
815 .Case(S: ".2s", Value: AArch64Layout::VL_2S)
816 .Case(S: ".1d", Value: AArch64Layout::VL_1D)
817 .Case(S: ".16b", Value: AArch64Layout::VL_16B)
818 .Case(S: ".8h", Value: AArch64Layout::VL_8H)
819 .Case(S: ".4s", Value: AArch64Layout::VL_4S)
820 .Case(S: ".2d", Value: AArch64Layout::VL_2D)
821 .Case(S: ".b", Value: AArch64Layout::VL_B)
822 .Case(S: ".h", Value: AArch64Layout::VL_H)
823 .Case(S: ".s", Value: AArch64Layout::VL_S)
824 .Case(S: ".d", Value: AArch64Layout::VL_D)
825 .Default(Value: AArch64Layout::Invalid);
826}
827
828namespace AArch64SysReg {
829 struct SysReg {
830 const char Name[32];
831 unsigned Encoding;
832 bool Readable;
833 bool Writeable;
834 FeatureBitset FeaturesRequired;
835
836 bool haveFeatures(FeatureBitset ActiveFeatures) const {
837 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
838 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
839 }
840 };
841
842#define GET_SysRegsList_DECL
843#define GET_SysRegValues_DECL
844#include "AArch64GenSystemOperands.inc"
845
846 uint32_t parseGenericRegister(StringRef Name);
847 std::string genericRegisterString(uint32_t Bits);
848}
849
850namespace AArch64TLBI {
851struct TLBI : SysAliasOptionalReg {
852 using SysAliasOptionalReg::SysAliasOptionalReg;
853};
854#define GET_TLBITable_DECL
855#include "AArch64GenSystemOperands.inc"
856}
857
858namespace AArch64TLBIP {
859struct TLBIP : SysAliasOptionalReg {
860 using SysAliasOptionalReg::SysAliasOptionalReg;
861};
862#define GET_TLBIPTable_DECL
863#include "AArch64GenSystemOperands.inc"
864} // namespace AArch64TLBIP
865
866namespace AArch64MLBI {
867struct MLBI : SysAliasReg {
868 using SysAliasReg::SysAliasReg;
869};
870#define GET_MLBITable_DECL
871#include "AArch64GenSystemOperands.inc"
872} // namespace AArch64MLBI
873
874namespace AArch64GIC {
875struct GIC : SysAliasReg {
876 using SysAliasReg::SysAliasReg;
877};
878#define GET_GICTable_DECL
879#include "AArch64GenSystemOperands.inc"
880} // namespace AArch64GIC
881
882namespace AArch64GICR {
883struct GICR : SysAliasReg {
884 using SysAliasReg::SysAliasReg;
885};
886#define GET_GICRTable_DECL
887#include "AArch64GenSystemOperands.inc"
888} // namespace AArch64GICR
889
890namespace AArch64GSB {
891struct GSB : SysAlias {
892 using SysAlias::SysAlias;
893};
894#define GET_GSBTable_DECL
895#include "AArch64GenSystemOperands.inc"
896} // namespace AArch64GSB
897
898namespace AArch64PLBI {
899struct PLBI : SysAliasOptionalReg {
900 using SysAliasOptionalReg::SysAliasOptionalReg;
901};
902#define GET_PLBITable_DECL
903#include "AArch64GenSystemOperands.inc"
904} // namespace AArch64PLBI
905
906namespace AArch64II {
907/// Target Operand Flag enum.
908enum TOF {
909 //===------------------------------------------------------------------===//
910 // AArch64 Specific MachineOperand flags.
911
912 MO_NO_FLAG,
913
914 MO_FRAGMENT = 0x7,
915
916 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
917 /// offset of the 4K page containing the symbol. This is used with the
918 /// ADRP instruction.
919 MO_PAGE = 1,
920
921 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
922 /// that symbol within a 4K page. This offset is added to the page address
923 /// to produce the complete address.
924 MO_PAGEOFF = 2,
925
926 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
927 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
928 MO_G3 = 3,
929
930 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
931 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
932 MO_G2 = 4,
933
934 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
935 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
936 MO_G1 = 5,
937
938 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
939 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
940 MO_G0 = 6,
941
942 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
943 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
944 /// by-12-bits instruction.
945 MO_HI12 = 7,
946
947 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
948 /// reference is actually to the ".refptr.FOO" symbol. This is used for
949 /// stub symbols on windows.
950 MO_COFFSTUB = 0x8,
951
952 /// MO_GOT - This flag indicates that a symbol operand represents the
953 /// address of the GOT entry for the symbol, rather than the address of
954 /// the symbol itself.
955 MO_GOT = 0x10,
956
957 /// MO_NC - Indicates whether the linker is expected to check the symbol
958 /// reference for overflow. For example in an ADRP/ADD pair of relocations
959 /// the ADRP usually does check, but not the ADD.
960 MO_NC = 0x20,
961
962 /// MO_TLS - Indicates that the operand being accessed is some kind of
963 /// thread-local symbol. On Darwin, only one type of thread-local access
964 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
965 /// referee will affect interpretation.
966 MO_TLS = 0x40,
967
968 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
969 /// to the symbol is for an import stub. This is used for DLL import
970 /// storage class indication on Windows.
971 MO_DLLIMPORT = 0x80,
972
973 /// MO_S - Indicates that the bits of the symbol operand represented by
974 /// MO_G0 etc are signed.
975 MO_S = 0x100,
976
977 /// MO_PREL - Indicates that the bits of the symbol operand represented by
978 /// MO_G0 etc are PC relative.
979 MO_PREL = 0x200,
980
981 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
982 /// in bits 56-63.
983 /// On a FrameIndex operand, indicates that the underlying memory is tagged
984 /// with an unknown tag value (MTE); this needs to be lowered either to an
985 /// SP-relative load or store instruction (which do not check tags), or to
986 /// an LDG instruction to obtain the tag value.
987 MO_TAGGED = 0x400,
988
989 /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
990 /// of a symbol, not the original. For dllimport symbols, this means it
991 /// uses "__imp_aux". For other symbols, this means it uses the mangled
992 /// ("#" prefix for C) name.
993 MO_ARM64EC_CALLMANGLE = 0x800,
994};
995} // end namespace AArch64II
996
997//===----------------------------------------------------------------------===//
998// v8.3a Pointer Authentication
999//
1000
1001namespace AArch64PACKey {
1002enum ID : uint8_t {
1003 IA = 0,
1004 IB = 1,
1005 DA = 2,
1006 DB = 3,
1007 LAST = DB
1008};
1009} // namespace AArch64PACKey
1010
1011/// Return 2-letter identifier string for numeric key ID.
1012inline static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID) {
1013 switch (KeyID) {
1014 case AArch64PACKey::IA:
1015 return StringRef("ia");
1016 case AArch64PACKey::IB:
1017 return StringRef("ib");
1018 case AArch64PACKey::DA:
1019 return StringRef("da");
1020 case AArch64PACKey::DB:
1021 return StringRef("db");
1022 }
1023 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
1024}
1025
1026/// Return numeric key ID for 2-letter identifier string.
1027inline static std::optional<AArch64PACKey::ID>
1028AArch64StringToPACKeyID(StringRef Name) {
1029 if (Name == "ia")
1030 return AArch64PACKey::IA;
1031 if (Name == "ib")
1032 return AArch64PACKey::IB;
1033 if (Name == "da")
1034 return AArch64PACKey::DA;
1035 if (Name == "db")
1036 return AArch64PACKey::DB;
1037 return std::nullopt;
1038}
1039
1040inline static unsigned getBTIHintNum(bool CallTarget, bool JumpTarget) {
1041 unsigned HintNum = 32;
1042 if (CallTarget)
1043 HintNum |= 2;
1044 if (JumpTarget)
1045 HintNum |= 4;
1046 assert(HintNum != 32 && "No target kinds!");
1047 return HintNum;
1048}
1049
1050namespace AArch64 {
1051// The number of bits in a SVE register is architecturally defined
1052// to be a multiple of this value. If <M x t> has this number of bits,
1053// a <n x M x t> vector can be stored in a SVE register without any
1054// redundant bits. If <M x t> has this number of bits divided by P,
1055// a <n x M x t> vector is stored in a SVE register by placing index i
1056// in index i*P of a <n x (M*P) x t> vector. The other elements of the
1057// <n x (M*P) x t> vector (such as index 1) are undefined.
1058static constexpr unsigned SVEBitsPerBlock = 128;
1059static constexpr unsigned SVEMaxBitsPerVector = 2048;
1060} // end namespace AArch64
1061} // end namespace llvm
1062
1063#endif
1064